Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 40
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
1 22:19:29.846213 lava-dispatcher, installed at version: 2023.05.1
2 22:19:29.846457 start: 0 validate
3 22:19:29.846623 Start time: 2023-06-05 22:19:29.846612+00:00 (UTC)
4 22:19:29.846794 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:19:29.846981 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:19:30.153125 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:19:30.153338 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:19:30.448770 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:19:30.449002 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:19:30.753326 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:19:30.753512 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:19:31.072025 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:19:31.072210 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:19:31.365451 validate duration: 1.52
16 22:19:31.365721 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:19:31.365828 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:19:31.365922 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:19:31.366047 Not decompressing ramdisk as can be used compressed.
20 22:19:31.366137 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 22:19:31.366202 saving as /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/ramdisk/initrd.cpio.gz
22 22:19:31.366280 total size: 4665273 (4MB)
23 22:19:31.367824 progress 0% (0MB)
24 22:19:31.369293 progress 5% (0MB)
25 22:19:31.370566 progress 10% (0MB)
26 22:19:31.371850 progress 15% (0MB)
27 22:19:31.373140 progress 20% (0MB)
28 22:19:31.374375 progress 25% (1MB)
29 22:19:31.375645 progress 30% (1MB)
30 22:19:31.376939 progress 35% (1MB)
31 22:19:31.378179 progress 40% (1MB)
32 22:19:31.379594 progress 45% (2MB)
33 22:19:31.380909 progress 50% (2MB)
34 22:19:31.382176 progress 55% (2MB)
35 22:19:31.383509 progress 60% (2MB)
36 22:19:31.384742 progress 65% (2MB)
37 22:19:31.385991 progress 70% (3MB)
38 22:19:31.387202 progress 75% (3MB)
39 22:19:31.388489 progress 80% (3MB)
40 22:19:31.390015 progress 85% (3MB)
41 22:19:31.391386 progress 90% (4MB)
42 22:19:31.392715 progress 95% (4MB)
43 22:19:31.394067 progress 100% (4MB)
44 22:19:31.394248 4MB downloaded in 0.03s (159.10MB/s)
45 22:19:31.394444 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:19:31.394840 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:19:31.394962 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:19:31.395086 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:19:31.395251 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:19:31.395351 saving as /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/kernel/Image
52 22:19:31.395445 total size: 45746688 (43MB)
53 22:19:31.395534 No compression specified
54 22:19:31.396829 progress 0% (0MB)
55 22:19:31.408667 progress 5% (2MB)
56 22:19:31.420376 progress 10% (4MB)
57 22:19:31.431992 progress 15% (6MB)
58 22:19:31.443820 progress 20% (8MB)
59 22:19:31.456139 progress 25% (10MB)
60 22:19:31.468161 progress 30% (13MB)
61 22:19:31.480323 progress 35% (15MB)
62 22:19:31.492473 progress 40% (17MB)
63 22:19:31.504594 progress 45% (19MB)
64 22:19:31.516612 progress 50% (21MB)
65 22:19:31.528418 progress 55% (24MB)
66 22:19:31.540368 progress 60% (26MB)
67 22:19:31.552517 progress 65% (28MB)
68 22:19:31.564528 progress 70% (30MB)
69 22:19:31.576481 progress 75% (32MB)
70 22:19:31.588225 progress 80% (34MB)
71 22:19:31.600325 progress 85% (37MB)
72 22:19:31.612535 progress 90% (39MB)
73 22:19:31.624507 progress 95% (41MB)
74 22:19:31.636477 progress 100% (43MB)
75 22:19:31.636627 43MB downloaded in 0.24s (180.89MB/s)
76 22:19:31.636859 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:19:31.637101 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:19:31.637188 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:19:31.637284 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:19:31.637415 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:19:31.637489 saving as /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/dtb/mt8192-asurada-spherion-r0.dtb
83 22:19:31.637550 total size: 46924 (0MB)
84 22:19:31.637607 No compression specified
85 22:19:31.638888 progress 69% (0MB)
86 22:19:31.639191 progress 100% (0MB)
87 22:19:31.639367 0MB downloaded in 0.00s (24.67MB/s)
88 22:19:31.639531 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:19:31.639891 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:19:31.640004 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:19:31.640117 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:19:31.640259 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 22:19:31.640350 saving as /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/nfsrootfs/full.rootfs.tar
95 22:19:31.640437 total size: 89386020 (85MB)
96 22:19:31.640522 Using unxz to decompress xz
97 22:19:31.644556 progress 0% (0MB)
98 22:19:31.853177 progress 5% (4MB)
99 22:19:32.075240 progress 10% (8MB)
100 22:19:32.339234 progress 15% (12MB)
101 22:19:32.535727 progress 20% (17MB)
102 22:19:32.631386 progress 25% (21MB)
103 22:19:32.891487 progress 30% (25MB)
104 22:19:33.195531 progress 35% (29MB)
105 22:19:33.479344 progress 40% (34MB)
106 22:19:33.753525 progress 45% (38MB)
107 22:19:33.998646 progress 50% (42MB)
108 22:19:34.259399 progress 55% (46MB)
109 22:19:34.511950 progress 60% (51MB)
110 22:19:34.787832 progress 65% (55MB)
111 22:19:35.083285 progress 70% (59MB)
112 22:19:35.386997 progress 75% (63MB)
113 22:19:35.689713 progress 80% (68MB)
114 22:19:35.958458 progress 85% (72MB)
115 22:19:36.201490 progress 90% (76MB)
116 22:19:36.478091 progress 95% (81MB)
117 22:19:36.762009 progress 100% (85MB)
118 22:19:36.768687 85MB downloaded in 5.13s (16.62MB/s)
119 22:19:36.769003 end: 1.4.1 http-download (duration 00:00:05) [common]
121 22:19:36.769304 end: 1.4 download-retry (duration 00:00:05) [common]
122 22:19:36.769415 start: 1.5 download-retry (timeout 00:09:55) [common]
123 22:19:36.769526 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 22:19:36.769699 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:19:36.769781 saving as /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/modules/modules.tar
126 22:19:36.769861 total size: 8543056 (8MB)
127 22:19:36.769970 Using unxz to decompress xz
128 22:19:36.774235 progress 0% (0MB)
129 22:19:36.797640 progress 5% (0MB)
130 22:19:36.825097 progress 10% (0MB)
131 22:19:36.851770 progress 15% (1MB)
132 22:19:36.878324 progress 20% (1MB)
133 22:19:36.902534 progress 25% (2MB)
134 22:19:36.929246 progress 30% (2MB)
135 22:19:36.954285 progress 35% (2MB)
136 22:19:36.978663 progress 40% (3MB)
137 22:19:37.002508 progress 45% (3MB)
138 22:19:37.026951 progress 50% (4MB)
139 22:19:37.050758 progress 55% (4MB)
140 22:19:37.076245 progress 60% (4MB)
141 22:19:37.102439 progress 65% (5MB)
142 22:19:37.127185 progress 70% (5MB)
143 22:19:37.150650 progress 75% (6MB)
144 22:19:37.174816 progress 80% (6MB)
145 22:19:37.199753 progress 85% (6MB)
146 22:19:37.228889 progress 90% (7MB)
147 22:19:37.254324 progress 95% (7MB)
148 22:19:37.278688 progress 100% (8MB)
149 22:19:37.284586 8MB downloaded in 0.51s (15.83MB/s)
150 22:19:37.284858 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:19:37.285129 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:19:37.285227 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 22:19:37.285329 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 22:19:38.907318 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5
156 22:19:38.907519 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 22:19:38.907623 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 22:19:38.907796 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e
159 22:19:38.907929 makedir: /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin
160 22:19:38.908036 makedir: /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/tests
161 22:19:38.908139 makedir: /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/results
162 22:19:38.908243 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-add-keys
163 22:19:38.908390 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-add-sources
164 22:19:38.908520 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-background-process-start
165 22:19:38.908651 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-background-process-stop
166 22:19:38.909079 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-common-functions
167 22:19:38.909210 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-echo-ipv4
168 22:19:38.909340 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-install-packages
169 22:19:38.909469 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-installed-packages
170 22:19:38.909671 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-os-build
171 22:19:38.909798 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-probe-channel
172 22:19:38.909926 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-probe-ip
173 22:19:38.910050 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-target-ip
174 22:19:38.910174 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-target-mac
175 22:19:38.910298 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-target-storage
176 22:19:38.910427 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-case
177 22:19:38.910554 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-event
178 22:19:38.910676 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-feedback
179 22:19:38.910806 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-raise
180 22:19:38.910928 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-reference
181 22:19:38.911050 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-runner
182 22:19:38.911177 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-set
183 22:19:38.911299 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-test-shell
184 22:19:38.911422 Updating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-install-packages (oe)
185 22:19:38.911579 Updating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/bin/lava-installed-packages (oe)
186 22:19:38.911711 Creating /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/environment
187 22:19:38.911812 LAVA metadata
188 22:19:38.911885 - LAVA_JOB_ID=10597287
189 22:19:38.911950 - LAVA_DISPATCHER_IP=192.168.201.1
190 22:19:38.912054 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 22:19:38.912124 skipped lava-vland-overlay
192 22:19:38.912200 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 22:19:38.912280 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 22:19:38.912343 skipped lava-multinode-overlay
195 22:19:38.912418 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 22:19:38.912497 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 22:19:38.912571 Loading test definitions
198 22:19:38.912669 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 22:19:38.912743 Using /lava-10597287 at stage 0
200 22:19:38.913078 uuid=10597287_1.6.2.3.1 testdef=None
201 22:19:38.913170 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 22:19:38.913258 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 22:19:38.913741 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 22:19:38.913971 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 22:19:38.914585 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 22:19:38.914822 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 22:19:38.915416 runner path: /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/0/tests/0_lc-compliance test_uuid 10597287_1.6.2.3.1
210 22:19:38.915574 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 22:19:38.915783 Creating lava-test-runner.conf files
213 22:19:38.915847 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597287/lava-overlay-jjj3ie5e/lava-10597287/0 for stage 0
214 22:19:38.915941 - 0_lc-compliance
215 22:19:38.916042 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 22:19:38.916133 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 22:19:38.922223 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 22:19:38.922335 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 22:19:38.922423 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 22:19:38.922509 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 22:19:38.922598 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 22:19:39.038747 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 22:19:39.039106 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 22:19:39.039231 extracting modules file /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5
225 22:19:39.255538 extracting modules file /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597287/extract-overlay-ramdisk-jehuw1e0/ramdisk
226 22:19:39.478267 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 22:19:39.478440 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 22:19:39.478552 [common] Applying overlay to NFS
229 22:19:39.478649 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597287/compress-overlay-s6tz6qyt/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5
230 22:19:39.485812 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 22:19:39.485926 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 22:19:39.486021 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 22:19:39.486109 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 22:19:39.486189 Building ramdisk /var/lib/lava/dispatcher/tmp/10597287/extract-overlay-ramdisk-jehuw1e0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597287/extract-overlay-ramdisk-jehuw1e0/ramdisk
235 22:19:39.751782 >> 117807 blocks
236 22:19:41.700704 rename /var/lib/lava/dispatcher/tmp/10597287/extract-overlay-ramdisk-jehuw1e0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/ramdisk/ramdisk.cpio.gz
237 22:19:41.701170 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 22:19:41.701295 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 22:19:41.701398 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 22:19:41.701506 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/kernel/Image'
241 22:19:53.250103 Returned 0 in 11 seconds
242 22:19:53.350693 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/kernel/image.itb
243 22:19:53.671541 output: FIT description: Kernel Image image with one or more FDT blobs
244 22:19:53.671895 output: Created: Mon Jun 5 23:19:53 2023
245 22:19:53.671979 output: Image 0 (kernel-1)
246 22:19:53.672046 output: Description:
247 22:19:53.672111 output: Created: Mon Jun 5 23:19:53 2023
248 22:19:53.672175 output: Type: Kernel Image
249 22:19:53.672236 output: Compression: lzma compressed
250 22:19:53.672296 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
251 22:19:53.672358 output: Architecture: AArch64
252 22:19:53.672418 output: OS: Linux
253 22:19:53.672475 output: Load Address: 0x00000000
254 22:19:53.672537 output: Entry Point: 0x00000000
255 22:19:53.672597 output: Hash algo: crc32
256 22:19:53.672651 output: Hash value: c242daf7
257 22:19:53.672706 output: Image 1 (fdt-1)
258 22:19:53.672831 output: Description: mt8192-asurada-spherion-r0
259 22:19:53.672916 output: Created: Mon Jun 5 23:19:53 2023
260 22:19:53.673001 output: Type: Flat Device Tree
261 22:19:53.673085 output: Compression: uncompressed
262 22:19:53.673168 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 22:19:53.673252 output: Architecture: AArch64
264 22:19:53.673336 output: Hash algo: crc32
265 22:19:53.673418 output: Hash value: 1df858fa
266 22:19:53.673502 output: Image 2 (ramdisk-1)
267 22:19:53.673585 output: Description: unavailable
268 22:19:53.673668 output: Created: Mon Jun 5 23:19:53 2023
269 22:19:53.673751 output: Type: RAMDisk Image
270 22:19:53.673836 output: Compression: Unknown Compression
271 22:19:53.673919 output: Data Size: 17644812 Bytes = 17231.26 KiB = 16.83 MiB
272 22:19:53.674007 output: Architecture: AArch64
273 22:19:53.674092 output: OS: Linux
274 22:19:53.674175 output: Load Address: unavailable
275 22:19:53.674258 output: Entry Point: unavailable
276 22:19:53.674341 output: Hash algo: crc32
277 22:19:53.674429 output: Hash value: dca97bcb
278 22:19:53.674512 output: Default Configuration: 'conf-1'
279 22:19:53.674595 output: Configuration 0 (conf-1)
280 22:19:53.674680 output: Description: mt8192-asurada-spherion-r0
281 22:19:53.674763 output: Kernel: kernel-1
282 22:19:53.674847 output: Init Ramdisk: ramdisk-1
283 22:19:53.674930 output: FDT: fdt-1
284 22:19:53.675012 output: Loadables: kernel-1
285 22:19:53.675094 output:
286 22:19:53.675304 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
287 22:19:53.675408 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
288 22:19:53.675517 end: 1.6 prepare-tftp-overlay (duration 00:00:16) [common]
289 22:19:53.675613 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:38) [common]
290 22:19:53.675695 No LXC device requested
291 22:19:53.675785 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 22:19:53.675904 start: 1.8 deploy-device-env (timeout 00:09:38) [common]
293 22:19:53.676015 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 22:19:53.676093 Checking files for TFTP limit of 4294967296 bytes.
295 22:19:53.676589 end: 1 tftp-deploy (duration 00:00:22) [common]
296 22:19:53.676694 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 22:19:53.676814 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 22:19:53.676960 substitutions:
299 22:19:53.677029 - {DTB}: 10597287/tftp-deploy-i8g293z_/dtb/mt8192-asurada-spherion-r0.dtb
300 22:19:53.677095 - {INITRD}: 10597287/tftp-deploy-i8g293z_/ramdisk/ramdisk.cpio.gz
301 22:19:53.677154 - {KERNEL}: 10597287/tftp-deploy-i8g293z_/kernel/Image
302 22:19:53.677212 - {LAVA_MAC}: None
303 22:19:53.677268 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5
304 22:19:53.677325 - {NFS_SERVER_IP}: 192.168.201.1
305 22:19:53.677383 - {PRESEED_CONFIG}: None
306 22:19:53.677440 - {PRESEED_LOCAL}: None
307 22:19:53.677494 - {RAMDISK}: 10597287/tftp-deploy-i8g293z_/ramdisk/ramdisk.cpio.gz
308 22:19:53.677549 - {ROOT_PART}: None
309 22:19:53.677607 - {ROOT}: None
310 22:19:53.677662 - {SERVER_IP}: 192.168.201.1
311 22:19:53.677716 - {TEE}: None
312 22:19:53.677770 Parsed boot commands:
313 22:19:53.677824 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 22:19:53.678012 Parsed boot commands: tftpboot 192.168.201.1 10597287/tftp-deploy-i8g293z_/kernel/image.itb 10597287/tftp-deploy-i8g293z_/kernel/cmdline
315 22:19:53.678108 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 22:19:53.678196 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 22:19:53.678291 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 22:19:53.678379 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 22:19:53.678452 Not connected, no need to disconnect.
320 22:19:53.678528 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 22:19:53.678609 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 22:19:53.678682 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
323 22:19:53.682191 Setting prompt string to ['lava-test: # ']
324 22:19:53.682560 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 22:19:53.682669 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 22:19:53.682770 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 22:19:53.682865 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 22:19:53.683064 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 22:19:58.815897 >> Command sent successfully.
330 22:19:58.818339 Returned 0 in 5 seconds
331 22:19:58.918737 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 22:19:58.919194 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 22:19:58.919328 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 22:19:58.919451 Setting prompt string to 'Starting depthcharge on Spherion...'
336 22:19:58.919551 Changing prompt to 'Starting depthcharge on Spherion...'
337 22:19:58.919658 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 22:19:58.920022 [Enter `^Ec?' for help]
339 22:19:59.091779
340 22:19:59.091951
341 22:19:59.092025 F0: 102B 0000
342 22:19:59.092098
343 22:19:59.092161 F3: 1001 0000 [0200]
344 22:19:59.092223
345 22:19:59.095711 F3: 1001 0000
346 22:19:59.095804
347 22:19:59.095902 F7: 102D 0000
348 22:19:59.095965
349 22:19:59.096025 F1: 0000 0000
350 22:19:59.098987
351 22:19:59.099087 V0: 0000 0000 [0001]
352 22:19:59.099180
353 22:19:59.099269 00: 0007 8000
354 22:19:59.099360
355 22:19:59.102729 01: 0000 0000
356 22:19:59.102814
357 22:19:59.102881 BP: 0C00 0209 [0000]
358 22:19:59.102943
359 22:19:59.106432 G0: 1182 0000
360 22:19:59.106516
361 22:19:59.106583 EC: 0000 0021 [4000]
362 22:19:59.106645
363 22:19:59.110114 S7: 0000 0000 [0000]
364 22:19:59.110197
365 22:19:59.110263 CC: 0000 0000 [0001]
366 22:19:59.110325
367 22:19:59.113436 T0: 0000 0040 [010F]
368 22:19:59.113522
369 22:19:59.113589 Jump to BL
370 22:19:59.113652
371 22:19:59.139031
372 22:19:59.139147
373 22:19:59.139243
374 22:19:59.146787 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 22:19:59.150782 ARM64: Exception handlers installed.
376 22:19:59.153945 ARM64: Testing exception
377 22:19:59.154052 ARM64: Done test exception
378 22:19:59.161355 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 22:19:59.172505 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 22:19:59.179603 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 22:19:59.189391 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 22:19:59.196283 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 22:19:59.206381 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 22:19:59.216407 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 22:19:59.222783 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 22:19:59.241116 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 22:19:59.244879 WDT: Last reset was cold boot
388 22:19:59.248056 SPI1(PAD0) initialized at 2873684 Hz
389 22:19:59.251188 SPI5(PAD0) initialized at 992727 Hz
390 22:19:59.254739 VBOOT: Loading verstage.
391 22:19:59.261466 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 22:19:59.264742 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 22:19:59.268098 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 22:19:59.271263 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 22:19:59.278858 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 22:19:59.285585 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 22:19:59.296458 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 22:19:59.296573
399 22:19:59.296671
400 22:19:59.306406 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 22:19:59.309623 ARM64: Exception handlers installed.
402 22:19:59.313287 ARM64: Testing exception
403 22:19:59.313364 ARM64: Done test exception
404 22:19:59.319621 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 22:19:59.322814 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 22:19:59.337430 Probing TPM: . done!
407 22:19:59.337513 TPM ready after 0 ms
408 22:19:59.344226 Connected to device vid:did:rid of 1ae0:0028:00
409 22:19:59.351686 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 22:19:59.408770 Initialized TPM device CR50 revision 0
411 22:19:59.420644 tlcl_send_startup: Startup return code is 0
412 22:19:59.420741 TPM: setup succeeded
413 22:19:59.431832 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 22:19:59.440361 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 22:19:59.450906 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 22:19:59.460336 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 22:19:59.463172 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 22:19:59.471835 in-header: 03 07 00 00 08 00 00 00
419 22:19:59.475400 in-data: aa e4 47 04 13 02 00 00
420 22:19:59.479004 Chrome EC: UHEPI supported
421 22:19:59.486174 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 22:19:59.489702 in-header: 03 ad 00 00 08 00 00 00
423 22:19:59.493414 in-data: 00 20 20 08 00 00 00 00
424 22:19:59.493498 Phase 1
425 22:19:59.496992 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 22:19:59.504500 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 22:19:59.508024 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 22:19:59.511959 Recovery requested (1009000e)
429 22:19:59.521824 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 22:19:59.528192 tlcl_extend: response is 0
431 22:19:59.537599 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 22:19:59.543584 tlcl_extend: response is 0
433 22:19:59.550562 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 22:19:59.571071 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 22:19:59.578159 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 22:19:59.578247
437 22:19:59.578315
438 22:19:59.587947 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 22:19:59.591561 ARM64: Exception handlers installed.
440 22:19:59.591647 ARM64: Testing exception
441 22:19:59.595009 ARM64: Done test exception
442 22:19:59.616623 pmic_efuse_setting: Set efuses in 11 msecs
443 22:19:59.619956 pmwrap_interface_init: Select PMIF_VLD_RDY
444 22:19:59.627589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 22:19:59.630645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 22:19:59.633751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 22:19:59.640420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 22:19:59.644180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 22:19:59.651412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 22:19:59.655081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 22:19:59.659169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 22:19:59.662677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 22:19:59.670633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 22:19:59.674011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 22:19:59.677276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 22:19:59.680526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 22:19:59.688139 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 22:19:59.694486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 22:19:59.701485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 22:19:59.705546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 22:19:59.712654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 22:19:59.716226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 22:19:59.722927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 22:19:59.726509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 22:19:59.733019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 22:19:59.740164 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 22:19:59.743320 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 22:19:59.749830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 22:19:59.756328 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 22:19:59.759560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 22:19:59.766172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 22:19:59.769432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 22:19:59.776119 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 22:19:59.779393 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 22:19:59.786124 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 22:19:59.789337 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 22:19:59.795764 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 22:19:59.799641 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 22:19:59.805842 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 22:19:59.809056 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 22:19:59.815671 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 22:19:59.819230 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 22:19:59.825906 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 22:19:59.829186 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 22:19:59.832602 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 22:19:59.835653 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 22:19:59.842739 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 22:19:59.846324 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 22:19:59.849982 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 22:19:59.853067 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 22:19:59.859559 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 22:19:59.863038 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 22:19:59.866334 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 22:19:59.869792 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 22:19:59.880169 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 22:19:59.887407 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 22:19:59.891531 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 22:19:59.902362 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 22:19:59.909399 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 22:19:59.912669 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 22:19:59.916493 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 22:19:59.923990 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 22:19:59.931446 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
504 22:19:59.934448 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 22:19:59.941010 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 22:19:59.944480 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 22:19:59.954268 [RTC]rtc_get_frequency_meter,154: input=15, output=772
508 22:19:59.963260 [RTC]rtc_get_frequency_meter,154: input=23, output=959
509 22:19:59.972325 [RTC]rtc_get_frequency_meter,154: input=19, output=863
510 22:19:59.981920 [RTC]rtc_get_frequency_meter,154: input=17, output=817
511 22:19:59.991819 [RTC]rtc_get_frequency_meter,154: input=16, output=797
512 22:20:00.001031 [RTC]rtc_get_frequency_meter,154: input=15, output=772
513 22:20:00.011118 [RTC]rtc_get_frequency_meter,154: input=16, output=795
514 22:20:00.014472 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
515 22:20:00.021076 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 22:20:00.024322 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 22:20:00.027598 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 22:20:00.033974 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 22:20:00.037814 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 22:20:00.040563 ADC[4]: Raw value=903245 ID=7
521 22:20:00.040710 ADC[3]: Raw value=213179 ID=1
522 22:20:00.043889 RAM Code: 0x71
523 22:20:00.047283 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 22:20:00.053940 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 22:20:00.060999 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 22:20:00.067572 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 22:20:00.070707 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 22:20:00.074152 in-header: 03 07 00 00 08 00 00 00
529 22:20:00.077356 in-data: aa e4 47 04 13 02 00 00
530 22:20:00.081040 Chrome EC: UHEPI supported
531 22:20:00.087462 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 22:20:00.090800 in-header: 03 ed 00 00 08 00 00 00
533 22:20:00.094113 in-data: 80 20 60 08 00 00 00 00
534 22:20:00.097323 MRC: failed to locate region type 0.
535 22:20:00.104205 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 22:20:00.107418 DRAM-K: Running full calibration
537 22:20:00.113839 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 22:20:00.117376 header.status = 0x0
539 22:20:00.120632 header.version = 0x6 (expected: 0x6)
540 22:20:00.123882 header.size = 0xd00 (expected: 0xd00)
541 22:20:00.123968 header.flags = 0x0
542 22:20:00.130450 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 22:20:00.147977 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
544 22:20:00.154825 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 22:20:00.158074 dram_init: ddr_geometry: 2
546 22:20:00.161546 [EMI] MDL number = 2
547 22:20:00.161632 [EMI] Get MDL freq = 0
548 22:20:00.164562 dram_init: ddr_type: 0
549 22:20:00.164647 is_discrete_lpddr4: 1
550 22:20:00.168268 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 22:20:00.168354
552 22:20:00.168421
553 22:20:00.171444 [Bian_co] ETT version 0.0.0.1
554 22:20:00.178156 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 22:20:00.178241
556 22:20:00.181499 dramc_set_vcore_voltage set vcore to 650000
557 22:20:00.184545 Read voltage for 800, 4
558 22:20:00.184630 Vio18 = 0
559 22:20:00.184698 Vcore = 650000
560 22:20:00.188035 Vdram = 0
561 22:20:00.188120 Vddq = 0
562 22:20:00.188187 Vmddr = 0
563 22:20:00.191247 dram_init: config_dvfs: 1
564 22:20:00.194380 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 22:20:00.201224 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 22:20:00.204373 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
567 22:20:00.207601 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
568 22:20:00.211291 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 22:20:00.217989 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 22:20:00.218077 MEM_TYPE=3, freq_sel=18
571 22:20:00.221256 sv_algorithm_assistance_LP4_1600
572 22:20:00.224346 ============ PULL DRAM RESETB DOWN ============
573 22:20:00.230988 ========== PULL DRAM RESETB DOWN end =========
574 22:20:00.234644 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 22:20:00.237976 ===================================
576 22:20:00.241301 LPDDR4 DRAM CONFIGURATION
577 22:20:00.244653 ===================================
578 22:20:00.244739 EX_ROW_EN[0] = 0x0
579 22:20:00.247592 EX_ROW_EN[1] = 0x0
580 22:20:00.247677 LP4Y_EN = 0x0
581 22:20:00.250728 WORK_FSP = 0x0
582 22:20:00.254342 WL = 0x2
583 22:20:00.254427 RL = 0x2
584 22:20:00.257674 BL = 0x2
585 22:20:00.257758 RPST = 0x0
586 22:20:00.260971 RD_PRE = 0x0
587 22:20:00.261055 WR_PRE = 0x1
588 22:20:00.264239 WR_PST = 0x0
589 22:20:00.264324 DBI_WR = 0x0
590 22:20:00.267707 DBI_RD = 0x0
591 22:20:00.267792 OTF = 0x1
592 22:20:00.271070 ===================================
593 22:20:00.274300 ===================================
594 22:20:00.277303 ANA top config
595 22:20:00.280544 ===================================
596 22:20:00.280630 DLL_ASYNC_EN = 0
597 22:20:00.284273 ALL_SLAVE_EN = 1
598 22:20:00.287540 NEW_RANK_MODE = 1
599 22:20:00.290814 DLL_IDLE_MODE = 1
600 22:20:00.290899 LP45_APHY_COMB_EN = 1
601 22:20:00.293995 TX_ODT_DIS = 1
602 22:20:00.297150 NEW_8X_MODE = 1
603 22:20:00.300789 ===================================
604 22:20:00.304180 ===================================
605 22:20:00.307497 data_rate = 1600
606 22:20:00.310767 CKR = 1
607 22:20:00.314012 DQ_P2S_RATIO = 8
608 22:20:00.317139 ===================================
609 22:20:00.317225 CA_P2S_RATIO = 8
610 22:20:00.320472 DQ_CA_OPEN = 0
611 22:20:00.324014 DQ_SEMI_OPEN = 0
612 22:20:00.327292 CA_SEMI_OPEN = 0
613 22:20:00.330464 CA_FULL_RATE = 0
614 22:20:00.334176 DQ_CKDIV4_EN = 1
615 22:20:00.334261 CA_CKDIV4_EN = 1
616 22:20:00.337196 CA_PREDIV_EN = 0
617 22:20:00.340694 PH8_DLY = 0
618 22:20:00.343929 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 22:20:00.347477 DQ_AAMCK_DIV = 4
620 22:20:00.350374 CA_AAMCK_DIV = 4
621 22:20:00.350460 CA_ADMCK_DIV = 4
622 22:20:00.353735 DQ_TRACK_CA_EN = 0
623 22:20:00.357265 CA_PICK = 800
624 22:20:00.360702 CA_MCKIO = 800
625 22:20:00.364070 MCKIO_SEMI = 0
626 22:20:00.367872 PLL_FREQ = 3068
627 22:20:00.367981 DQ_UI_PI_RATIO = 32
628 22:20:00.370889 CA_UI_PI_RATIO = 0
629 22:20:00.374714 ===================================
630 22:20:00.378218 ===================================
631 22:20:00.382074 memory_type:LPDDR4
632 22:20:00.382159 GP_NUM : 10
633 22:20:00.385344 SRAM_EN : 1
634 22:20:00.385429 MD32_EN : 0
635 22:20:00.388908 ===================================
636 22:20:00.392541 [ANA_INIT] >>>>>>>>>>>>>>
637 22:20:00.396193 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 22:20:00.399783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 22:20:00.403003 ===================================
640 22:20:00.403088 data_rate = 1600,PCW = 0X7600
641 22:20:00.406597 ===================================
642 22:20:00.409749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 22:20:00.416214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 22:20:00.423501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 22:20:00.426753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 22:20:00.430613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 22:20:00.434264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 22:20:00.437418 [ANA_INIT] flow start
649 22:20:00.437503 [ANA_INIT] PLL >>>>>>>>
650 22:20:00.441064 [ANA_INIT] PLL <<<<<<<<
651 22:20:00.444545 [ANA_INIT] MIDPI >>>>>>>>
652 22:20:00.444630 [ANA_INIT] MIDPI <<<<<<<<
653 22:20:00.448085 [ANA_INIT] DLL >>>>>>>>
654 22:20:00.448170 [ANA_INIT] flow end
655 22:20:00.452022 ============ LP4 DIFF to SE enter ============
656 22:20:00.459748 ============ LP4 DIFF to SE exit ============
657 22:20:00.459834 [ANA_INIT] <<<<<<<<<<<<<
658 22:20:00.462758 [Flow] Enable top DCM control >>>>>
659 22:20:00.466884 [Flow] Enable top DCM control <<<<<
660 22:20:00.470532 Enable DLL master slave shuffle
661 22:20:00.473887 ==============================================================
662 22:20:00.477504 Gating Mode config
663 22:20:00.481537 ==============================================================
664 22:20:00.484943 Config description:
665 22:20:00.492485 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 22:20:00.499826 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 22:20:00.503548 SELPH_MODE 0: By rank 1: By Phase
668 22:20:00.511262 ==============================================================
669 22:20:00.514990 GAT_TRACK_EN = 1
670 22:20:00.518665 RX_GATING_MODE = 2
671 22:20:00.518750 RX_GATING_TRACK_MODE = 2
672 22:20:00.521826 SELPH_MODE = 1
673 22:20:00.525604 PICG_EARLY_EN = 1
674 22:20:00.529130 VALID_LAT_VALUE = 1
675 22:20:00.532799 ==============================================================
676 22:20:00.536586 Enter into Gating configuration >>>>
677 22:20:00.540156 Exit from Gating configuration <<<<
678 22:20:00.544321 Enter into DVFS_PRE_config >>>>>
679 22:20:00.555473 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 22:20:00.559160 Exit from DVFS_PRE_config <<<<<
681 22:20:00.562607 Enter into PICG configuration >>>>
682 22:20:00.566329 Exit from PICG configuration <<<<
683 22:20:00.566442 [RX_INPUT] configuration >>>>>
684 22:20:00.570135 [RX_INPUT] configuration <<<<<
685 22:20:00.577671 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 22:20:00.581202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 22:20:00.588527 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 22:20:00.592398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 22:20:00.599514 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 22:20:00.607174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 22:20:00.610925 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 22:20:00.614610 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 22:20:00.618265 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 22:20:00.621578 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 22:20:00.625562 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 22:20:00.629147 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 22:20:00.632790 ===================================
698 22:20:00.636737 LPDDR4 DRAM CONFIGURATION
699 22:20:00.640539 ===================================
700 22:20:00.640625 EX_ROW_EN[0] = 0x0
701 22:20:00.644210 EX_ROW_EN[1] = 0x0
702 22:20:00.644296 LP4Y_EN = 0x0
703 22:20:00.647767 WORK_FSP = 0x0
704 22:20:00.647851 WL = 0x2
705 22:20:00.651778 RL = 0x2
706 22:20:00.651864 BL = 0x2
707 22:20:00.655399 RPST = 0x0
708 22:20:00.655484 RD_PRE = 0x0
709 22:20:00.658638 WR_PRE = 0x1
710 22:20:00.658724 WR_PST = 0x0
711 22:20:00.662398 DBI_WR = 0x0
712 22:20:00.662484 DBI_RD = 0x0
713 22:20:00.662552 OTF = 0x1
714 22:20:00.665996 ===================================
715 22:20:00.669965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 22:20:00.673750 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 22:20:00.680934 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 22:20:00.684615 ===================================
719 22:20:00.684700 LPDDR4 DRAM CONFIGURATION
720 22:20:00.688725 ===================================
721 22:20:00.692184 EX_ROW_EN[0] = 0x10
722 22:20:00.692270 EX_ROW_EN[1] = 0x0
723 22:20:00.695842 LP4Y_EN = 0x0
724 22:20:00.695927 WORK_FSP = 0x0
725 22:20:00.699765 WL = 0x2
726 22:20:00.699850 RL = 0x2
727 22:20:00.703276 BL = 0x2
728 22:20:00.703361 RPST = 0x0
729 22:20:00.703430 RD_PRE = 0x0
730 22:20:00.707285 WR_PRE = 0x1
731 22:20:00.707371 WR_PST = 0x0
732 22:20:00.710784 DBI_WR = 0x0
733 22:20:00.710869 DBI_RD = 0x0
734 22:20:00.714916 OTF = 0x1
735 22:20:00.718456 ===================================
736 22:20:00.722090 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 22:20:00.727110 nWR fixed to 40
738 22:20:00.730259 [ModeRegInit_LP4] CH0 RK0
739 22:20:00.730345 [ModeRegInit_LP4] CH0 RK1
740 22:20:00.733825 [ModeRegInit_LP4] CH1 RK0
741 22:20:00.737033 [ModeRegInit_LP4] CH1 RK1
742 22:20:00.737118 match AC timing 13
743 22:20:00.743530 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 22:20:00.747229 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 22:20:00.750277 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 22:20:00.757089 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 22:20:00.760709 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 22:20:00.760847 [EMI DOE] emi_dcm 0
749 22:20:00.766943 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 22:20:00.767029 ==
751 22:20:00.770086 Dram Type= 6, Freq= 0, CH_0, rank 0
752 22:20:00.773454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 22:20:00.773540 ==
754 22:20:00.780087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 22:20:00.786664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 22:20:00.794849 [CA 0] Center 38 (7~69) winsize 63
757 22:20:00.797837 [CA 1] Center 38 (7~69) winsize 63
758 22:20:00.801206 [CA 2] Center 35 (5~66) winsize 62
759 22:20:00.804411 [CA 3] Center 35 (4~66) winsize 63
760 22:20:00.807765 [CA 4] Center 34 (4~65) winsize 62
761 22:20:00.811186 [CA 5] Center 33 (3~64) winsize 62
762 22:20:00.811272
763 22:20:00.814192 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 22:20:00.814278
765 22:20:00.817496 [CATrainingPosCal] consider 1 rank data
766 22:20:00.821123 u2DelayCellTimex100 = 270/100 ps
767 22:20:00.824304 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
768 22:20:00.828057 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
769 22:20:00.834349 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
770 22:20:00.837863 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
771 22:20:00.841160 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
772 22:20:00.844260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 22:20:00.844345
774 22:20:00.847495 CA PerBit enable=1, Macro0, CA PI delay=33
775 22:20:00.847581
776 22:20:00.851197 [CBTSetCACLKResult] CA Dly = 33
777 22:20:00.851281 CS Dly: 5 (0~36)
778 22:20:00.854267 ==
779 22:20:00.857551 Dram Type= 6, Freq= 0, CH_0, rank 1
780 22:20:00.861052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 22:20:00.861140 ==
782 22:20:00.864092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 22:20:00.870666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 22:20:00.880898 [CA 0] Center 38 (7~69) winsize 63
785 22:20:00.884410 [CA 1] Center 38 (7~69) winsize 63
786 22:20:00.887323 [CA 2] Center 36 (6~67) winsize 62
787 22:20:00.890948 [CA 3] Center 35 (5~66) winsize 62
788 22:20:00.894195 [CA 4] Center 35 (4~66) winsize 63
789 22:20:00.897494 [CA 5] Center 34 (4~65) winsize 62
790 22:20:00.897579
791 22:20:00.900743 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 22:20:00.900852
793 22:20:00.904134 [CATrainingPosCal] consider 2 rank data
794 22:20:00.907254 u2DelayCellTimex100 = 270/100 ps
795 22:20:00.910548 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
796 22:20:00.917543 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
797 22:20:00.920706 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
798 22:20:00.924209 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
799 22:20:00.927482 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
800 22:20:00.930594 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
801 22:20:00.930679
802 22:20:00.934330 CA PerBit enable=1, Macro0, CA PI delay=34
803 22:20:00.934416
804 22:20:00.937658 [CBTSetCACLKResult] CA Dly = 34
805 22:20:00.937743 CS Dly: 6 (0~38)
806 22:20:00.937811
807 22:20:00.944121 ----->DramcWriteLeveling(PI) begin...
808 22:20:00.944208 ==
809 22:20:00.947376 Dram Type= 6, Freq= 0, CH_0, rank 0
810 22:20:00.950967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:20:00.951070 ==
812 22:20:00.954720 Write leveling (Byte 0): 30 => 30
813 22:20:00.954856 Write leveling (Byte 1): 33 => 33
814 22:20:00.958716 DramcWriteLeveling(PI) end<-----
815 22:20:00.958803
816 22:20:00.958910 ==
817 22:20:00.962420 Dram Type= 6, Freq= 0, CH_0, rank 0
818 22:20:00.965506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 22:20:00.969023 ==
820 22:20:00.969110 [Gating] SW mode calibration
821 22:20:00.975601 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 22:20:00.982812 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 22:20:00.985835 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 22:20:00.992570 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 22:20:00.995868 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
826 22:20:00.999459 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:20:01.005834 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:20:01.009240 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 22:20:01.012407 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 22:20:01.016013 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 22:20:01.023004 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 22:20:01.026101 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 22:20:01.029530 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 22:20:01.036385 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 22:20:01.039505 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 22:20:01.042626 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 22:20:01.049145 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 22:20:01.052703 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 22:20:01.056129 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:20:01.062691 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
841 22:20:01.066060 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 22:20:01.069527 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:20:01.075738 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 22:20:01.079395 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 22:20:01.082324 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 22:20:01.089314 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 22:20:01.092729 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 22:20:01.095980 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
849 22:20:01.102774 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
850 22:20:01.106050 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
851 22:20:01.109242 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 22:20:01.115693 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 22:20:01.119247 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 22:20:01.122422 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 22:20:01.125727 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 22:20:01.132291 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
857 22:20:01.135868 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
858 22:20:01.139142 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
859 22:20:01.145462 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:20:01.149080 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:20:01.152221 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:20:01.159031 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:20:01.162042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:20:01.165424 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
865 22:20:01.172313 0 11 8 | B1->B0 | 2e2e 4646 | 1 0 | (1 1) (0 0)
866 22:20:01.175266 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
867 22:20:01.178831 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 22:20:01.185455 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 22:20:01.188710 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 22:20:01.192385 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 22:20:01.198536 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 22:20:01.202074 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
873 22:20:01.205218 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 22:20:01.212048 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 22:20:01.215544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 22:20:01.218795 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 22:20:01.224994 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 22:20:01.228403 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 22:20:01.231737 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 22:20:01.238503 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 22:20:01.241653 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 22:20:01.245298 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 22:20:01.252086 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 22:20:01.255164 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 22:20:01.258383 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 22:20:01.265228 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 22:20:01.268410 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 22:20:01.271760 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 22:20:01.274906 Total UI for P1: 0, mck2ui 16
890 22:20:01.278442 best dqsien dly found for B0: ( 0, 14, 2)
891 22:20:01.281362 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
892 22:20:01.288173 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 22:20:01.291437 Total UI for P1: 0, mck2ui 16
894 22:20:01.294827 best dqsien dly found for B1: ( 0, 14, 6)
895 22:20:01.298084 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
896 22:20:01.301748 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
897 22:20:01.301833
898 22:20:01.305214 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
899 22:20:01.308052 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
900 22:20:01.311616 [Gating] SW calibration Done
901 22:20:01.311702 ==
902 22:20:01.314722 Dram Type= 6, Freq= 0, CH_0, rank 0
903 22:20:01.318289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 22:20:01.318376 ==
905 22:20:01.321485 RX Vref Scan: 0
906 22:20:01.321569
907 22:20:01.321636 RX Vref 0 -> 0, step: 1
908 22:20:01.324717
909 22:20:01.324855 RX Delay -130 -> 252, step: 16
910 22:20:01.331362 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 22:20:01.334819 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
912 22:20:01.338130 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 22:20:01.341633 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 22:20:01.344874 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 22:20:01.351429 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 22:20:01.354580 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 22:20:01.358143 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
918 22:20:01.361384 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
919 22:20:01.364620 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
920 22:20:01.371395 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
921 22:20:01.374444 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
922 22:20:01.378130 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
923 22:20:01.381117 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
924 22:20:01.384962 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
925 22:20:01.391280 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
926 22:20:01.391362 ==
927 22:20:01.394547 Dram Type= 6, Freq= 0, CH_0, rank 0
928 22:20:01.398148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 22:20:01.398223 ==
930 22:20:01.398288 DQS Delay:
931 22:20:01.400978 DQS0 = 0, DQS1 = 0
932 22:20:01.401050 DQM Delay:
933 22:20:01.404517 DQM0 = 89, DQM1 = 80
934 22:20:01.404590 DQ Delay:
935 22:20:01.407541 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
936 22:20:01.411089 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
937 22:20:01.414474 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
938 22:20:01.417715 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
939 22:20:01.417793
940 22:20:01.417858
941 22:20:01.417916 ==
942 22:20:01.421181 Dram Type= 6, Freq= 0, CH_0, rank 0
943 22:20:01.424302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 22:20:01.427859 ==
945 22:20:01.427932
946 22:20:01.427995
947 22:20:01.428054 TX Vref Scan disable
948 22:20:01.431033 == TX Byte 0 ==
949 22:20:01.434185 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 22:20:01.437775 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 22:20:01.441103 == TX Byte 1 ==
952 22:20:01.444044 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
953 22:20:01.447543 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
954 22:20:01.451008 ==
955 22:20:01.454327 Dram Type= 6, Freq= 0, CH_0, rank 0
956 22:20:01.457305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 22:20:01.457379 ==
958 22:20:01.469869 TX Vref=22, minBit 6, minWin=27, winSum=440
959 22:20:01.473266 TX Vref=24, minBit 6, minWin=27, winSum=443
960 22:20:01.476352 TX Vref=26, minBit 6, minWin=27, winSum=447
961 22:20:01.479952 TX Vref=28, minBit 8, minWin=27, winSum=453
962 22:20:01.483133 TX Vref=30, minBit 8, minWin=28, winSum=459
963 22:20:01.486644 TX Vref=32, minBit 5, minWin=28, winSum=457
964 22:20:01.493062 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
965 22:20:01.493140
966 22:20:01.496580 Final TX Range 1 Vref 30
967 22:20:01.496682
968 22:20:01.496781 ==
969 22:20:01.499756 Dram Type= 6, Freq= 0, CH_0, rank 0
970 22:20:01.503066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 22:20:01.503141 ==
972 22:20:01.503203
973 22:20:01.506245
974 22:20:01.506316 TX Vref Scan disable
975 22:20:01.509617 == TX Byte 0 ==
976 22:20:01.512886 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 22:20:01.519629 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 22:20:01.519705 == TX Byte 1 ==
979 22:20:01.523116 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 22:20:01.529371 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 22:20:01.529447
982 22:20:01.529510 [DATLAT]
983 22:20:01.529570 Freq=800, CH0 RK0
984 22:20:01.529632
985 22:20:01.533198 DATLAT Default: 0xa
986 22:20:01.533272 0, 0xFFFF, sum = 0
987 22:20:01.536445 1, 0xFFFF, sum = 0
988 22:20:01.536525 2, 0xFFFF, sum = 0
989 22:20:01.539463 3, 0xFFFF, sum = 0
990 22:20:01.543069 4, 0xFFFF, sum = 0
991 22:20:01.543145 5, 0xFFFF, sum = 0
992 22:20:01.546133 6, 0xFFFF, sum = 0
993 22:20:01.546207 7, 0xFFFF, sum = 0
994 22:20:01.549573 8, 0xFFFF, sum = 0
995 22:20:01.549675 9, 0x0, sum = 1
996 22:20:01.549770 10, 0x0, sum = 2
997 22:20:01.552676 11, 0x0, sum = 3
998 22:20:01.552799 12, 0x0, sum = 4
999 22:20:01.556321 best_step = 10
1000 22:20:01.556394
1001 22:20:01.556455 ==
1002 22:20:01.559843 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 22:20:01.562918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 22:20:01.563020 ==
1005 22:20:01.566152 RX Vref Scan: 1
1006 22:20:01.566254
1007 22:20:01.566345 Set Vref Range= 32 -> 127
1008 22:20:01.569444
1009 22:20:01.569517 RX Vref 32 -> 127, step: 1
1010 22:20:01.569579
1011 22:20:01.572703 RX Delay -95 -> 252, step: 8
1012 22:20:01.572826
1013 22:20:01.575925 Set Vref, RX VrefLevel [Byte0]: 32
1014 22:20:01.579562 [Byte1]: 32
1015 22:20:01.579645
1016 22:20:01.582612 Set Vref, RX VrefLevel [Byte0]: 33
1017 22:20:01.585849 [Byte1]: 33
1018 22:20:01.590135
1019 22:20:01.590218 Set Vref, RX VrefLevel [Byte0]: 34
1020 22:20:01.593504 [Byte1]: 34
1021 22:20:01.597815
1022 22:20:01.597897 Set Vref, RX VrefLevel [Byte0]: 35
1023 22:20:01.601264 [Byte1]: 35
1024 22:20:01.605025
1025 22:20:01.605117 Set Vref, RX VrefLevel [Byte0]: 36
1026 22:20:01.608682 [Byte1]: 36
1027 22:20:01.612934
1028 22:20:01.613016 Set Vref, RX VrefLevel [Byte0]: 37
1029 22:20:01.616619 [Byte1]: 37
1030 22:20:01.620981
1031 22:20:01.621063 Set Vref, RX VrefLevel [Byte0]: 38
1032 22:20:01.624041 [Byte1]: 38
1033 22:20:01.628573
1034 22:20:01.628655 Set Vref, RX VrefLevel [Byte0]: 39
1035 22:20:01.631561 [Byte1]: 39
1036 22:20:01.635692
1037 22:20:01.635774 Set Vref, RX VrefLevel [Byte0]: 40
1038 22:20:01.638978 [Byte1]: 40
1039 22:20:01.643375
1040 22:20:01.643457 Set Vref, RX VrefLevel [Byte0]: 41
1041 22:20:01.646649 [Byte1]: 41
1042 22:20:01.651162
1043 22:20:01.651239 Set Vref, RX VrefLevel [Byte0]: 42
1044 22:20:01.654167 [Byte1]: 42
1045 22:20:01.658303
1046 22:20:01.658385 Set Vref, RX VrefLevel [Byte0]: 43
1047 22:20:01.661445 [Byte1]: 43
1048 22:20:01.665855
1049 22:20:01.665928 Set Vref, RX VrefLevel [Byte0]: 44
1050 22:20:01.669131 [Byte1]: 44
1051 22:20:01.673532
1052 22:20:01.673608 Set Vref, RX VrefLevel [Byte0]: 45
1053 22:20:01.676675 [Byte1]: 45
1054 22:20:01.681003
1055 22:20:01.681076 Set Vref, RX VrefLevel [Byte0]: 46
1056 22:20:01.684301 [Byte1]: 46
1057 22:20:01.688916
1058 22:20:01.688998 Set Vref, RX VrefLevel [Byte0]: 47
1059 22:20:01.692308 [Byte1]: 47
1060 22:20:01.696306
1061 22:20:01.696387 Set Vref, RX VrefLevel [Byte0]: 48
1062 22:20:01.699823 [Byte1]: 48
1063 22:20:01.703967
1064 22:20:01.704076 Set Vref, RX VrefLevel [Byte0]: 49
1065 22:20:01.707191 [Byte1]: 49
1066 22:20:01.711356
1067 22:20:01.711438 Set Vref, RX VrefLevel [Byte0]: 50
1068 22:20:01.714944 [Byte1]: 50
1069 22:20:01.719250
1070 22:20:01.719332 Set Vref, RX VrefLevel [Byte0]: 51
1071 22:20:01.722732 [Byte1]: 51
1072 22:20:01.726808
1073 22:20:01.726916 Set Vref, RX VrefLevel [Byte0]: 52
1074 22:20:01.730018 [Byte1]: 52
1075 22:20:01.734192
1076 22:20:01.734303 Set Vref, RX VrefLevel [Byte0]: 53
1077 22:20:01.737716 [Byte1]: 53
1078 22:20:01.741946
1079 22:20:01.742022 Set Vref, RX VrefLevel [Byte0]: 54
1080 22:20:01.745243 [Byte1]: 54
1081 22:20:01.749349
1082 22:20:01.749454 Set Vref, RX VrefLevel [Byte0]: 55
1083 22:20:01.753048 [Byte1]: 55
1084 22:20:01.756907
1085 22:20:01.756984 Set Vref, RX VrefLevel [Byte0]: 56
1086 22:20:01.760410 [Byte1]: 56
1087 22:20:01.764511
1088 22:20:01.764610 Set Vref, RX VrefLevel [Byte0]: 57
1089 22:20:01.768060 [Byte1]: 57
1090 22:20:01.772485
1091 22:20:01.772606 Set Vref, RX VrefLevel [Byte0]: 58
1092 22:20:01.775560 [Byte1]: 58
1093 22:20:01.779698
1094 22:20:01.779799 Set Vref, RX VrefLevel [Byte0]: 59
1095 22:20:01.783331 [Byte1]: 59
1096 22:20:01.787578
1097 22:20:01.787682 Set Vref, RX VrefLevel [Byte0]: 60
1098 22:20:01.790597 [Byte1]: 60
1099 22:20:01.795331
1100 22:20:01.795481 Set Vref, RX VrefLevel [Byte0]: 61
1101 22:20:01.798563 [Byte1]: 61
1102 22:20:01.802494
1103 22:20:01.806166 Set Vref, RX VrefLevel [Byte0]: 62
1104 22:20:01.806272 [Byte1]: 62
1105 22:20:01.810330
1106 22:20:01.810432 Set Vref, RX VrefLevel [Byte0]: 63
1107 22:20:01.813614 [Byte1]: 63
1108 22:20:01.817707
1109 22:20:01.817848 Set Vref, RX VrefLevel [Byte0]: 64
1110 22:20:01.821056 [Byte1]: 64
1111 22:20:01.825354
1112 22:20:01.825458 Set Vref, RX VrefLevel [Byte0]: 65
1113 22:20:01.828613 [Byte1]: 65
1114 22:20:01.833080
1115 22:20:01.833153 Set Vref, RX VrefLevel [Byte0]: 66
1116 22:20:01.836262 [Byte1]: 66
1117 22:20:01.840490
1118 22:20:01.840592 Set Vref, RX VrefLevel [Byte0]: 67
1119 22:20:01.843885 [Byte1]: 67
1120 22:20:01.848317
1121 22:20:01.848422 Set Vref, RX VrefLevel [Byte0]: 68
1122 22:20:01.851529 [Byte1]: 68
1123 22:20:01.856004
1124 22:20:01.856110 Set Vref, RX VrefLevel [Byte0]: 69
1125 22:20:01.859013 [Byte1]: 69
1126 22:20:01.863578
1127 22:20:01.863682 Set Vref, RX VrefLevel [Byte0]: 70
1128 22:20:01.866837 [Byte1]: 70
1129 22:20:01.871022
1130 22:20:01.871129 Set Vref, RX VrefLevel [Byte0]: 71
1131 22:20:01.874411 [Byte1]: 71
1132 22:20:01.878594
1133 22:20:01.878697 Set Vref, RX VrefLevel [Byte0]: 72
1134 22:20:01.882236 [Byte1]: 72
1135 22:20:01.886107
1136 22:20:01.886209 Set Vref, RX VrefLevel [Byte0]: 73
1137 22:20:01.889430 [Byte1]: 73
1138 22:20:01.894015
1139 22:20:01.894124 Set Vref, RX VrefLevel [Byte0]: 74
1140 22:20:01.897072 [Byte1]: 74
1141 22:20:01.901205
1142 22:20:01.904550 Set Vref, RX VrefLevel [Byte0]: 75
1143 22:20:01.907742 [Byte1]: 75
1144 22:20:01.907838
1145 22:20:01.911157 Set Vref, RX VrefLevel [Byte0]: 76
1146 22:20:01.914253 [Byte1]: 76
1147 22:20:01.914361
1148 22:20:01.918017 Set Vref, RX VrefLevel [Byte0]: 77
1149 22:20:01.921242 [Byte1]: 77
1150 22:20:01.921354
1151 22:20:01.924391 Final RX Vref Byte 0 = 61 to rank0
1152 22:20:01.927601 Final RX Vref Byte 1 = 61 to rank0
1153 22:20:01.931143 Final RX Vref Byte 0 = 61 to rank1
1154 22:20:01.934363 Final RX Vref Byte 1 = 61 to rank1==
1155 22:20:01.937477 Dram Type= 6, Freq= 0, CH_0, rank 0
1156 22:20:01.941228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 22:20:01.944245 ==
1158 22:20:01.944349 DQS Delay:
1159 22:20:01.944442 DQS0 = 0, DQS1 = 0
1160 22:20:01.947912 DQM Delay:
1161 22:20:01.948010 DQM0 = 93, DQM1 = 82
1162 22:20:01.951188 DQ Delay:
1163 22:20:01.954387 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1164 22:20:01.957460 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1165 22:20:01.960704 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1166 22:20:01.964278 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1167 22:20:01.964381
1168 22:20:01.964475
1169 22:20:01.970683 [DQSOSCAuto] RK0, (LSB)MR18= 0x3934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1170 22:20:01.974014 CH0 RK0: MR19=606, MR18=3934
1171 22:20:01.980523 CH0_RK0: MR19=0x606, MR18=0x3934, DQSOSC=395, MR23=63, INC=94, DEC=63
1172 22:20:01.980624
1173 22:20:01.984008 ----->DramcWriteLeveling(PI) begin...
1174 22:20:01.984117 ==
1175 22:20:01.987359 Dram Type= 6, Freq= 0, CH_0, rank 1
1176 22:20:01.990849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1177 22:20:01.990931 ==
1178 22:20:01.994005 Write leveling (Byte 0): 31 => 31
1179 22:20:01.997441 Write leveling (Byte 1): 27 => 27
1180 22:20:02.000654 DramcWriteLeveling(PI) end<-----
1181 22:20:02.000760
1182 22:20:02.000868 ==
1183 22:20:02.003834 Dram Type= 6, Freq= 0, CH_0, rank 1
1184 22:20:02.007282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 22:20:02.007366 ==
1186 22:20:02.010978 [Gating] SW mode calibration
1187 22:20:02.058372 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1188 22:20:02.058674 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1189 22:20:02.059179 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1190 22:20:02.059273 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1191 22:20:02.059564 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1192 22:20:02.059653 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:20:02.059962 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:20:02.060314 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:20:02.060468 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:20:02.060979 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:20:02.102188 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:20:02.102541 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:20:02.102958 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:20:02.103045 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:20:02.103291 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:20:02.103369 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:20:02.103609 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:20:02.104029 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:20:02.104125 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:20:02.104748 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1207 22:20:02.119736 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1208 22:20:02.120180 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 22:20:02.120443 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 22:20:02.120513 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 22:20:02.123436 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 22:20:02.130188 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 22:20:02.133148 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:20:02.136570 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1215 22:20:02.143222 0 9 8 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
1216 22:20:02.146606 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1217 22:20:02.150107 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 22:20:02.156477 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 22:20:02.160095 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 22:20:02.163086 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 22:20:02.169836 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 22:20:02.173322 0 10 4 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
1223 22:20:02.176466 0 10 8 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
1224 22:20:02.183290 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:20:02.186455 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:20:02.189545 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:20:02.196329 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:20:02.199966 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:20:02.203470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:20:02.207592 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1231 22:20:02.211182 0 11 8 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
1232 22:20:02.217902 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 22:20:02.220725 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 22:20:02.224037 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 22:20:02.230986 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 22:20:02.234281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 22:20:02.237587 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 22:20:02.244411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1239 22:20:02.247557 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1240 22:20:02.251210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 22:20:02.257810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 22:20:02.261100 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 22:20:02.264183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 22:20:02.270869 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 22:20:02.274636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 22:20:02.277649 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 22:20:02.283970 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 22:20:02.287569 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 22:20:02.290736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 22:20:02.294383 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 22:20:02.300573 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 22:20:02.303983 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 22:20:02.307263 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1254 22:20:02.314327 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1255 22:20:02.317252 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 22:20:02.320963 Total UI for P1: 0, mck2ui 16
1257 22:20:02.323987 best dqsien dly found for B0: ( 0, 14, 2)
1258 22:20:02.327558 Total UI for P1: 0, mck2ui 16
1259 22:20:02.331044 best dqsien dly found for B1: ( 0, 14, 6)
1260 22:20:02.334278 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1261 22:20:02.337509 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1262 22:20:02.337592
1263 22:20:02.340786 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1264 22:20:02.343978 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1265 22:20:02.347520 [Gating] SW calibration Done
1266 22:20:02.347603 ==
1267 22:20:02.350605 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 22:20:02.353922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 22:20:02.357357 ==
1270 22:20:02.357440 RX Vref Scan: 0
1271 22:20:02.357505
1272 22:20:02.360942 RX Vref 0 -> 0, step: 1
1273 22:20:02.361024
1274 22:20:02.363989 RX Delay -130 -> 252, step: 16
1275 22:20:02.367245 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1276 22:20:02.370390 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1277 22:20:02.373987 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1278 22:20:02.377145 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1279 22:20:02.384004 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1280 22:20:02.386986 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1281 22:20:02.390549 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1282 22:20:02.393819 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1283 22:20:02.396959 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1284 22:20:02.403812 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1285 22:20:02.406986 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1286 22:20:02.410532 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1287 22:20:02.413603 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1288 22:20:02.420362 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1289 22:20:02.423844 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1290 22:20:02.426657 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1291 22:20:02.426766 ==
1292 22:20:02.430019 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 22:20:02.433501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 22:20:02.433584 ==
1295 22:20:02.437032 DQS Delay:
1296 22:20:02.437114 DQS0 = 0, DQS1 = 0
1297 22:20:02.439976 DQM Delay:
1298 22:20:02.440059 DQM0 = 89, DQM1 = 80
1299 22:20:02.440124 DQ Delay:
1300 22:20:02.443729 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1301 22:20:02.446763 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1302 22:20:02.450153 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1303 22:20:02.453327 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1304 22:20:02.453409
1305 22:20:02.453474
1306 22:20:02.456901 ==
1307 22:20:02.460089 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 22:20:02.463120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 22:20:02.463205 ==
1310 22:20:02.463288
1311 22:20:02.463381
1312 22:20:02.466706 TX Vref Scan disable
1313 22:20:02.466863 == TX Byte 0 ==
1314 22:20:02.472976 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1315 22:20:02.476594 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1316 22:20:02.476711 == TX Byte 1 ==
1317 22:20:02.482903 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1318 22:20:02.486552 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1319 22:20:02.486657 ==
1320 22:20:02.489673 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 22:20:02.492909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 22:20:02.492984 ==
1323 22:20:02.506988 TX Vref=22, minBit 3, minWin=27, winSum=441
1324 22:20:02.510098 TX Vref=24, minBit 8, minWin=27, winSum=451
1325 22:20:02.513518 TX Vref=26, minBit 8, minWin=27, winSum=450
1326 22:20:02.517407 TX Vref=28, minBit 4, minWin=28, winSum=456
1327 22:20:02.520078 TX Vref=30, minBit 8, minWin=28, winSum=457
1328 22:20:02.526951 TX Vref=32, minBit 8, minWin=28, winSum=457
1329 22:20:02.530123 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 30
1330 22:20:02.530198
1331 22:20:02.533849 Final TX Range 1 Vref 30
1332 22:20:02.533925
1333 22:20:02.533991 ==
1334 22:20:02.536925 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 22:20:02.540156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 22:20:02.543188 ==
1337 22:20:02.543292
1338 22:20:02.543382
1339 22:20:02.543479 TX Vref Scan disable
1340 22:20:02.546848 == TX Byte 0 ==
1341 22:20:02.550376 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1342 22:20:02.557110 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1343 22:20:02.557219 == TX Byte 1 ==
1344 22:20:02.560350 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1345 22:20:02.566999 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1346 22:20:02.567104
1347 22:20:02.567198 [DATLAT]
1348 22:20:02.567293 Freq=800, CH0 RK1
1349 22:20:02.567385
1350 22:20:02.570146 DATLAT Default: 0xa
1351 22:20:02.570242 0, 0xFFFF, sum = 0
1352 22:20:02.573382 1, 0xFFFF, sum = 0
1353 22:20:02.577113 2, 0xFFFF, sum = 0
1354 22:20:02.577193 3, 0xFFFF, sum = 0
1355 22:20:02.580079 4, 0xFFFF, sum = 0
1356 22:20:02.580150 5, 0xFFFF, sum = 0
1357 22:20:02.583591 6, 0xFFFF, sum = 0
1358 22:20:02.583687 7, 0xFFFF, sum = 0
1359 22:20:02.586801 8, 0xFFFF, sum = 0
1360 22:20:02.586901 9, 0x0, sum = 1
1361 22:20:02.589908 10, 0x0, sum = 2
1362 22:20:02.590013 11, 0x0, sum = 3
1363 22:20:02.590104 12, 0x0, sum = 4
1364 22:20:02.593491 best_step = 10
1365 22:20:02.593565
1366 22:20:02.593625 ==
1367 22:20:02.596671 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 22:20:02.599953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 22:20:02.600023 ==
1370 22:20:02.603498 RX Vref Scan: 0
1371 22:20:02.603598
1372 22:20:02.606360 RX Vref 0 -> 0, step: 1
1373 22:20:02.606455
1374 22:20:02.606542 RX Delay -79 -> 252, step: 8
1375 22:20:02.613657 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1376 22:20:02.617030 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1377 22:20:02.620435 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1378 22:20:02.624001 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1379 22:20:02.626838 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1380 22:20:02.633797 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1381 22:20:02.636863 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1382 22:20:02.640012 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1383 22:20:02.643298 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1384 22:20:02.646969 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1385 22:20:02.653398 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1386 22:20:02.656721 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1387 22:20:02.659945 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1388 22:20:02.663373 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1389 22:20:02.670215 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1390 22:20:02.673401 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1391 22:20:02.673512 ==
1392 22:20:02.677009 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 22:20:02.680052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 22:20:02.680121 ==
1395 22:20:02.680181 DQS Delay:
1396 22:20:02.683225 DQS0 = 0, DQS1 = 0
1397 22:20:02.683318 DQM Delay:
1398 22:20:02.686632 DQM0 = 91, DQM1 = 81
1399 22:20:02.686727 DQ Delay:
1400 22:20:02.689969 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1401 22:20:02.693071 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1402 22:20:02.696442 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1403 22:20:02.699948 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1404 22:20:02.700016
1405 22:20:02.700074
1406 22:20:02.709764 [DQSOSCAuto] RK1, (LSB)MR18= 0x401a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1407 22:20:02.709842 CH0 RK1: MR19=606, MR18=401A
1408 22:20:02.716523 CH0_RK1: MR19=0x606, MR18=0x401A, DQSOSC=393, MR23=63, INC=95, DEC=63
1409 22:20:02.719576 [RxdqsGatingPostProcess] freq 800
1410 22:20:02.726351 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1411 22:20:02.729748 Pre-setting of DQS Precalculation
1412 22:20:02.732971 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1413 22:20:02.733070 ==
1414 22:20:02.736247 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 22:20:02.742976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 22:20:02.743047 ==
1417 22:20:02.746399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 22:20:02.752966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 22:20:02.762143 [CA 0] Center 36 (6~67) winsize 62
1420 22:20:02.765520 [CA 1] Center 36 (6~67) winsize 62
1421 22:20:02.768878 [CA 2] Center 35 (5~65) winsize 61
1422 22:20:02.771924 [CA 3] Center 34 (4~65) winsize 62
1423 22:20:02.775590 [CA 4] Center 34 (4~65) winsize 62
1424 22:20:02.778939 [CA 5] Center 34 (3~65) winsize 63
1425 22:20:02.779041
1426 22:20:02.782058 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1427 22:20:02.782133
1428 22:20:02.785389 [CATrainingPosCal] consider 1 rank data
1429 22:20:02.788746 u2DelayCellTimex100 = 270/100 ps
1430 22:20:02.791922 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1431 22:20:02.795462 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1432 22:20:02.802271 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1433 22:20:02.805415 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1434 22:20:02.808549 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 22:20:02.812251 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1436 22:20:02.812322
1437 22:20:02.815387 CA PerBit enable=1, Macro0, CA PI delay=34
1438 22:20:02.815456
1439 22:20:02.818589 [CBTSetCACLKResult] CA Dly = 34
1440 22:20:02.818656 CS Dly: 5 (0~36)
1441 22:20:02.821996 ==
1442 22:20:02.822062 Dram Type= 6, Freq= 0, CH_1, rank 1
1443 22:20:02.828664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 22:20:02.828760 ==
1445 22:20:02.831737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 22:20:02.838649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 22:20:02.848321 [CA 0] Center 37 (7~68) winsize 62
1448 22:20:02.851644 [CA 1] Center 37 (6~68) winsize 63
1449 22:20:02.854875 [CA 2] Center 35 (5~66) winsize 62
1450 22:20:02.858546 [CA 3] Center 34 (4~65) winsize 62
1451 22:20:02.861749 [CA 4] Center 35 (5~65) winsize 61
1452 22:20:02.865210 [CA 5] Center 34 (4~65) winsize 62
1453 22:20:02.865295
1454 22:20:02.868697 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 22:20:02.868823
1456 22:20:02.872941 [CATrainingPosCal] consider 2 rank data
1457 22:20:02.876206 u2DelayCellTimex100 = 270/100 ps
1458 22:20:02.879960 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1459 22:20:02.883393 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 22:20:02.887056 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1461 22:20:02.890691 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 22:20:02.894199 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1463 22:20:02.897938 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 22:20:02.898043
1465 22:20:02.901352 CA PerBit enable=1, Macro0, CA PI delay=34
1466 22:20:02.901448
1467 22:20:02.904740 [CBTSetCACLKResult] CA Dly = 34
1468 22:20:02.904865 CS Dly: 5 (0~37)
1469 22:20:02.904931
1470 22:20:02.911304 ----->DramcWriteLeveling(PI) begin...
1471 22:20:02.911407 ==
1472 22:20:02.914912 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 22:20:02.918147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 22:20:02.918224 ==
1475 22:20:02.921327 Write leveling (Byte 0): 28 => 28
1476 22:20:02.924465 Write leveling (Byte 1): 31 => 31
1477 22:20:02.927836 DramcWriteLeveling(PI) end<-----
1478 22:20:02.927933
1479 22:20:02.928020 ==
1480 22:20:02.931036 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 22:20:02.934581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 22:20:02.934681 ==
1483 22:20:02.938120 [Gating] SW mode calibration
1484 22:20:02.944412 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1485 22:20:02.951136 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1486 22:20:02.954446 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1487 22:20:02.957673 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1488 22:20:02.964583 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:20:02.967554 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:20:02.970829 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:20:02.977591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:20:02.980990 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:20:02.983992 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:20:02.990951 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:20:02.994525 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:20:02.997601 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:20:03.001196 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:20:03.007343 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:20:03.011134 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:20:03.014186 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:20:03.020588 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:20:03.024230 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1503 22:20:03.027490 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1504 22:20:03.033991 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 22:20:03.037540 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 22:20:03.040708 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 22:20:03.047475 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 22:20:03.050689 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 22:20:03.053957 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 22:20:03.060879 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:20:03.063907 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:20:03.067170 0 9 8 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
1513 22:20:03.074161 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 22:20:03.077552 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1515 22:20:03.080676 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 22:20:03.087408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 22:20:03.090609 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 22:20:03.094008 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 22:20:03.100546 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
1520 22:20:03.103813 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:20:03.107132 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:20:03.113835 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:20:03.116913 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:20:03.120292 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:20:03.126928 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:20:03.130513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:20:03.133634 0 11 4 | B1->B0 | 3130 3030 | 1 0 | (0 0) (0 0)
1528 22:20:03.137222 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1529 22:20:03.143991 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 22:20:03.146920 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 22:20:03.153214 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 22:20:03.156751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 22:20:03.160068 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 22:20:03.163217 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 22:20:03.169907 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1536 22:20:03.173231 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 22:20:03.176498 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 22:20:03.183106 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 22:20:03.186708 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 22:20:03.190027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 22:20:03.196584 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 22:20:03.199784 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 22:20:03.203277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 22:20:03.209927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 22:20:03.213204 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 22:20:03.216432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 22:20:03.222941 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 22:20:03.226036 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 22:20:03.229800 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 22:20:03.236135 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1551 22:20:03.239522 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1552 22:20:03.242786 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 22:20:03.246463 Total UI for P1: 0, mck2ui 16
1554 22:20:03.249877 best dqsien dly found for B0: ( 0, 14, 2)
1555 22:20:03.252958 Total UI for P1: 0, mck2ui 16
1556 22:20:03.256091 best dqsien dly found for B1: ( 0, 14, 2)
1557 22:20:03.259435 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1558 22:20:03.263065 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1559 22:20:03.263172
1560 22:20:03.269556 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1561 22:20:03.272921 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1562 22:20:03.273030 [Gating] SW calibration Done
1563 22:20:03.276147 ==
1564 22:20:03.276224 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 22:20:03.282983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 22:20:03.283092 ==
1567 22:20:03.283205 RX Vref Scan: 0
1568 22:20:03.283302
1569 22:20:03.286384 RX Vref 0 -> 0, step: 1
1570 22:20:03.286503
1571 22:20:03.289638 RX Delay -130 -> 252, step: 16
1572 22:20:03.292913 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1573 22:20:03.296131 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1574 22:20:03.299419 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1575 22:20:03.306098 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1576 22:20:03.309388 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1577 22:20:03.312730 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1578 22:20:03.316097 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1579 22:20:03.319364 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1580 22:20:03.325993 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1581 22:20:03.329538 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1582 22:20:03.332629 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1583 22:20:03.336315 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1584 22:20:03.339529 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1585 22:20:03.345989 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1586 22:20:03.349572 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1587 22:20:03.352305 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1588 22:20:03.352380 ==
1589 22:20:03.355911 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 22:20:03.359196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 22:20:03.362554 ==
1592 22:20:03.362625 DQS Delay:
1593 22:20:03.362687 DQS0 = 0, DQS1 = 0
1594 22:20:03.365743 DQM Delay:
1595 22:20:03.365817 DQM0 = 90, DQM1 = 83
1596 22:20:03.369256 DQ Delay:
1597 22:20:03.369330 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1598 22:20:03.372411 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =93
1599 22:20:03.376023 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1600 22:20:03.379156 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1601 22:20:03.382203
1602 22:20:03.382276
1603 22:20:03.382337 ==
1604 22:20:03.385815 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 22:20:03.388927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 22:20:03.388995 ==
1607 22:20:03.389055
1608 22:20:03.389112
1609 22:20:03.392039 TX Vref Scan disable
1610 22:20:03.392122 == TX Byte 0 ==
1611 22:20:03.398910 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1612 22:20:03.402185 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1613 22:20:03.402265 == TX Byte 1 ==
1614 22:20:03.408996 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1615 22:20:03.412090 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1616 22:20:03.412169 ==
1617 22:20:03.415468 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 22:20:03.418748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 22:20:03.418821 ==
1620 22:20:03.432541 TX Vref=22, minBit 11, minWin=26, winSum=447
1621 22:20:03.436001 TX Vref=24, minBit 8, minWin=27, winSum=451
1622 22:20:03.439506 TX Vref=26, minBit 8, minWin=27, winSum=454
1623 22:20:03.442737 TX Vref=28, minBit 8, minWin=27, winSum=456
1624 22:20:03.446438 TX Vref=30, minBit 15, minWin=27, winSum=459
1625 22:20:03.449686 TX Vref=32, minBit 12, minWin=27, winSum=458
1626 22:20:03.456226 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1627 22:20:03.456311
1628 22:20:03.459706 Final TX Range 1 Vref 30
1629 22:20:03.459780
1630 22:20:03.459843 ==
1631 22:20:03.463010 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:20:03.466453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:20:03.466527 ==
1634 22:20:03.466589
1635 22:20:03.469867
1636 22:20:03.469937 TX Vref Scan disable
1637 22:20:03.472981 == TX Byte 0 ==
1638 22:20:03.476502 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1639 22:20:03.479933 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1640 22:20:03.482891 == TX Byte 1 ==
1641 22:20:03.486509 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1642 22:20:03.489703 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1643 22:20:03.493189
1644 22:20:03.493263 [DATLAT]
1645 22:20:03.493326 Freq=800, CH1 RK0
1646 22:20:03.493386
1647 22:20:03.496211 DATLAT Default: 0xa
1648 22:20:03.496281 0, 0xFFFF, sum = 0
1649 22:20:03.499742 1, 0xFFFF, sum = 0
1650 22:20:03.499814 2, 0xFFFF, sum = 0
1651 22:20:03.503142 3, 0xFFFF, sum = 0
1652 22:20:03.503214 4, 0xFFFF, sum = 0
1653 22:20:03.506312 5, 0xFFFF, sum = 0
1654 22:20:03.506392 6, 0xFFFF, sum = 0
1655 22:20:03.510045 7, 0xFFFF, sum = 0
1656 22:20:03.513077 8, 0xFFFF, sum = 0
1657 22:20:03.513150 9, 0x0, sum = 1
1658 22:20:03.513223 10, 0x0, sum = 2
1659 22:20:03.516431 11, 0x0, sum = 3
1660 22:20:03.516503 12, 0x0, sum = 4
1661 22:20:03.519569 best_step = 10
1662 22:20:03.519654
1663 22:20:03.519718 ==
1664 22:20:03.522947 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 22:20:03.526242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 22:20:03.526405 ==
1667 22:20:03.529760 RX Vref Scan: 1
1668 22:20:03.529836
1669 22:20:03.529900 Set Vref Range= 32 -> 127
1670 22:20:03.529960
1671 22:20:03.532651 RX Vref 32 -> 127, step: 1
1672 22:20:03.532722
1673 22:20:03.536089 RX Delay -95 -> 252, step: 8
1674 22:20:03.536160
1675 22:20:03.539311 Set Vref, RX VrefLevel [Byte0]: 32
1676 22:20:03.542750 [Byte1]: 32
1677 22:20:03.542821
1678 22:20:03.546016 Set Vref, RX VrefLevel [Byte0]: 33
1679 22:20:03.549680 [Byte1]: 33
1680 22:20:03.553319
1681 22:20:03.553389 Set Vref, RX VrefLevel [Byte0]: 34
1682 22:20:03.556728 [Byte1]: 34
1683 22:20:03.560965
1684 22:20:03.561051 Set Vref, RX VrefLevel [Byte0]: 35
1685 22:20:03.564174 [Byte1]: 35
1686 22:20:03.568366
1687 22:20:03.568440 Set Vref, RX VrefLevel [Byte0]: 36
1688 22:20:03.571946 [Byte1]: 36
1689 22:20:03.576132
1690 22:20:03.576208 Set Vref, RX VrefLevel [Byte0]: 37
1691 22:20:03.579401 [Byte1]: 37
1692 22:20:03.583653
1693 22:20:03.583730 Set Vref, RX VrefLevel [Byte0]: 38
1694 22:20:03.587118 [Byte1]: 38
1695 22:20:03.591107
1696 22:20:03.591183 Set Vref, RX VrefLevel [Byte0]: 39
1697 22:20:03.594815 [Byte1]: 39
1698 22:20:03.598583
1699 22:20:03.598657 Set Vref, RX VrefLevel [Byte0]: 40
1700 22:20:03.602271 [Byte1]: 40
1701 22:20:03.606292
1702 22:20:03.606366 Set Vref, RX VrefLevel [Byte0]: 41
1703 22:20:03.609514 [Byte1]: 41
1704 22:20:03.614015
1705 22:20:03.614091 Set Vref, RX VrefLevel [Byte0]: 42
1706 22:20:03.617532 [Byte1]: 42
1707 22:20:03.621536
1708 22:20:03.621610 Set Vref, RX VrefLevel [Byte0]: 43
1709 22:20:03.624710 [Byte1]: 43
1710 22:20:03.628986
1711 22:20:03.629062 Set Vref, RX VrefLevel [Byte0]: 44
1712 22:20:03.632629 [Byte1]: 44
1713 22:20:03.636771
1714 22:20:03.636869 Set Vref, RX VrefLevel [Byte0]: 45
1715 22:20:03.640356 [Byte1]: 45
1716 22:20:03.644751
1717 22:20:03.647477 Set Vref, RX VrefLevel [Byte0]: 46
1718 22:20:03.650973 [Byte1]: 46
1719 22:20:03.651052
1720 22:20:03.654159 Set Vref, RX VrefLevel [Byte0]: 47
1721 22:20:03.657429 [Byte1]: 47
1722 22:20:03.657506
1723 22:20:03.660937 Set Vref, RX VrefLevel [Byte0]: 48
1724 22:20:03.664113 [Byte1]: 48
1725 22:20:03.664188
1726 22:20:03.667489 Set Vref, RX VrefLevel [Byte0]: 49
1727 22:20:03.670831 [Byte1]: 49
1728 22:20:03.674817
1729 22:20:03.674896 Set Vref, RX VrefLevel [Byte0]: 50
1730 22:20:03.678015 [Byte1]: 50
1731 22:20:03.682523
1732 22:20:03.682600 Set Vref, RX VrefLevel [Byte0]: 51
1733 22:20:03.685598 [Byte1]: 51
1734 22:20:03.690148
1735 22:20:03.690234 Set Vref, RX VrefLevel [Byte0]: 52
1736 22:20:03.693409 [Byte1]: 52
1737 22:20:03.697794
1738 22:20:03.697897 Set Vref, RX VrefLevel [Byte0]: 53
1739 22:20:03.700875 [Byte1]: 53
1740 22:20:03.705267
1741 22:20:03.705394 Set Vref, RX VrefLevel [Byte0]: 54
1742 22:20:03.708454 [Byte1]: 54
1743 22:20:03.712982
1744 22:20:03.713078 Set Vref, RX VrefLevel [Byte0]: 55
1745 22:20:03.715913 [Byte1]: 55
1746 22:20:03.720579
1747 22:20:03.720681 Set Vref, RX VrefLevel [Byte0]: 56
1748 22:20:03.723957 [Byte1]: 56
1749 22:20:03.728236
1750 22:20:03.728363 Set Vref, RX VrefLevel [Byte0]: 57
1751 22:20:03.731066 [Byte1]: 57
1752 22:20:03.735678
1753 22:20:03.735778 Set Vref, RX VrefLevel [Byte0]: 58
1754 22:20:03.738876 [Byte1]: 58
1755 22:20:03.743404
1756 22:20:03.743488 Set Vref, RX VrefLevel [Byte0]: 59
1757 22:20:03.746665 [Byte1]: 59
1758 22:20:03.750844
1759 22:20:03.750916 Set Vref, RX VrefLevel [Byte0]: 60
1760 22:20:03.754281 [Byte1]: 60
1761 22:20:03.758276
1762 22:20:03.758351 Set Vref, RX VrefLevel [Byte0]: 61
1763 22:20:03.761760 [Byte1]: 61
1764 22:20:03.766163
1765 22:20:03.766269 Set Vref, RX VrefLevel [Byte0]: 62
1766 22:20:03.769501 [Byte1]: 62
1767 22:20:03.773515
1768 22:20:03.773626 Set Vref, RX VrefLevel [Byte0]: 63
1769 22:20:03.779942 [Byte1]: 63
1770 22:20:03.780016
1771 22:20:03.783191 Set Vref, RX VrefLevel [Byte0]: 64
1772 22:20:03.786802 [Byte1]: 64
1773 22:20:03.786874
1774 22:20:03.790093 Set Vref, RX VrefLevel [Byte0]: 65
1775 22:20:03.793088 [Byte1]: 65
1776 22:20:03.796680
1777 22:20:03.796820 Set Vref, RX VrefLevel [Byte0]: 66
1778 22:20:03.799961 [Byte1]: 66
1779 22:20:03.803933
1780 22:20:03.804003 Set Vref, RX VrefLevel [Byte0]: 67
1781 22:20:03.807493 [Byte1]: 67
1782 22:20:03.811883
1783 22:20:03.811968 Set Vref, RX VrefLevel [Byte0]: 68
1784 22:20:03.814798 [Byte1]: 68
1785 22:20:03.819300
1786 22:20:03.819372 Set Vref, RX VrefLevel [Byte0]: 69
1787 22:20:03.822489 [Byte1]: 69
1788 22:20:03.826998
1789 22:20:03.827078 Set Vref, RX VrefLevel [Byte0]: 70
1790 22:20:03.830053 [Byte1]: 70
1791 22:20:03.834508
1792 22:20:03.834589 Set Vref, RX VrefLevel [Byte0]: 71
1793 22:20:03.837635 [Byte1]: 71
1794 22:20:03.842097
1795 22:20:03.842169 Set Vref, RX VrefLevel [Byte0]: 72
1796 22:20:03.845151 [Byte1]: 72
1797 22:20:03.849762
1798 22:20:03.849836 Set Vref, RX VrefLevel [Byte0]: 73
1799 22:20:03.852959 [Byte1]: 73
1800 22:20:03.857325
1801 22:20:03.857403 Set Vref, RX VrefLevel [Byte0]: 74
1802 22:20:03.860226 [Byte1]: 74
1803 22:20:03.864628
1804 22:20:03.864713 Set Vref, RX VrefLevel [Byte0]: 75
1805 22:20:03.868240 [Byte1]: 75
1806 22:20:03.872271
1807 22:20:03.872348 Final RX Vref Byte 0 = 50 to rank0
1808 22:20:03.875694 Final RX Vref Byte 1 = 63 to rank0
1809 22:20:03.878917 Final RX Vref Byte 0 = 50 to rank1
1810 22:20:03.882121 Final RX Vref Byte 1 = 63 to rank1==
1811 22:20:03.885506 Dram Type= 6, Freq= 0, CH_1, rank 0
1812 22:20:03.891978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 22:20:03.892055 ==
1814 22:20:03.892119 DQS Delay:
1815 22:20:03.895611 DQS0 = 0, DQS1 = 0
1816 22:20:03.895683 DQM Delay:
1817 22:20:03.895743 DQM0 = 92, DQM1 = 83
1818 22:20:03.898507 DQ Delay:
1819 22:20:03.902071 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1820 22:20:03.905184 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1821 22:20:03.908810 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1822 22:20:03.911837 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1823 22:20:03.911913
1824 22:20:03.911983
1825 22:20:03.918453 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1826 22:20:03.921722 CH1 RK0: MR19=606, MR18=2C49
1827 22:20:03.928440 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1828 22:20:03.928514
1829 22:20:03.931490 ----->DramcWriteLeveling(PI) begin...
1830 22:20:03.931567 ==
1831 22:20:03.934949 Dram Type= 6, Freq= 0, CH_1, rank 1
1832 22:20:03.938392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 22:20:03.938470 ==
1834 22:20:03.941556 Write leveling (Byte 0): 27 => 27
1835 22:20:03.944949 Write leveling (Byte 1): 30 => 30
1836 22:20:03.948103 DramcWriteLeveling(PI) end<-----
1837 22:20:03.948173
1838 22:20:03.948242 ==
1839 22:20:03.951501 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 22:20:03.954660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 22:20:03.958202 ==
1842 22:20:03.958276 [Gating] SW mode calibration
1843 22:20:03.964740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1844 22:20:03.971541 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1845 22:20:03.974850 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1846 22:20:03.981595 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1847 22:20:03.984832 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:20:03.988369 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:20:03.994899 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:20:03.998036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:20:04.001669 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:20:04.007962 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:20:04.011208 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:20:04.014546 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:20:04.021512 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:20:04.024702 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:20:04.027777 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 22:20:04.034776 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:20:04.038009 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:20:04.041391 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:20:04.048055 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1862 22:20:04.051048 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1863 22:20:04.054349 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1864 22:20:04.057728 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:20:04.064384 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:20:04.067666 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:20:04.071058 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:20:04.077638 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:20:04.081112 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:20:04.084453 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:20:04.091115 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1872 22:20:04.094271 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 22:20:04.097580 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 22:20:04.104108 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 22:20:04.107317 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 22:20:04.110965 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 22:20:04.117600 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 22:20:04.121008 0 10 4 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
1879 22:20:04.124150 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:20:04.131125 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:20:04.134217 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:20:04.137473 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:20:04.144180 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:20:04.147691 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:20:04.150836 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:20:04.157538 0 11 4 | B1->B0 | 3232 2f2f | 0 1 | (1 1) (0 0)
1887 22:20:04.160701 0 11 8 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1888 22:20:04.164154 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 22:20:04.170634 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 22:20:04.174085 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 22:20:04.177416 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 22:20:04.184053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 22:20:04.187385 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 22:20:04.190381 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1895 22:20:04.197178 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 22:20:04.200643 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 22:20:04.203703 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 22:20:04.206894 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 22:20:04.213797 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 22:20:04.217044 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 22:20:04.220462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 22:20:04.227078 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 22:20:04.230358 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 22:20:04.233426 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 22:20:04.240113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 22:20:04.243641 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 22:20:04.247300 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 22:20:04.253768 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 22:20:04.256933 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 22:20:04.260304 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1911 22:20:04.267030 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 22:20:04.267113 Total UI for P1: 0, mck2ui 16
1913 22:20:04.273771 best dqsien dly found for B0: ( 0, 14, 4)
1914 22:20:04.273895 Total UI for P1: 0, mck2ui 16
1915 22:20:04.280054 best dqsien dly found for B1: ( 0, 14, 4)
1916 22:20:04.283497 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1917 22:20:04.286808 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1918 22:20:04.286912
1919 22:20:04.290228 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1920 22:20:04.293545 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1921 22:20:04.297006 [Gating] SW calibration Done
1922 22:20:04.297097 ==
1923 22:20:04.299848 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 22:20:04.303577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 22:20:04.303668 ==
1926 22:20:04.306675 RX Vref Scan: 0
1927 22:20:04.306759
1928 22:20:04.306824 RX Vref 0 -> 0, step: 1
1929 22:20:04.306886
1930 22:20:04.309850 RX Delay -130 -> 252, step: 16
1931 22:20:04.313105 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1932 22:20:04.319907 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1933 22:20:04.323513 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1934 22:20:04.326568 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1935 22:20:04.330184 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1936 22:20:04.333210 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1937 22:20:04.339918 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1938 22:20:04.343111 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1939 22:20:04.346400 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1940 22:20:04.350084 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1941 22:20:04.353581 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1942 22:20:04.360181 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1943 22:20:04.362973 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1944 22:20:04.366680 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1945 22:20:04.369800 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1946 22:20:04.373333 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1947 22:20:04.376562 ==
1948 22:20:04.379900 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 22:20:04.382903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 22:20:04.383008 ==
1951 22:20:04.383110 DQS Delay:
1952 22:20:04.386425 DQS0 = 0, DQS1 = 0
1953 22:20:04.386523 DQM Delay:
1954 22:20:04.389790 DQM0 = 92, DQM1 = 86
1955 22:20:04.389866 DQ Delay:
1956 22:20:04.392773 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1957 22:20:04.396456 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1958 22:20:04.399530 DQ8 =69, DQ9 =77, DQ10 =93, DQ11 =77
1959 22:20:04.402978 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1960 22:20:04.403064
1961 22:20:04.403129
1962 22:20:04.403190 ==
1963 22:20:04.406133 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 22:20:04.409515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 22:20:04.409603 ==
1966 22:20:04.409669
1967 22:20:04.412636
1968 22:20:04.412721 TX Vref Scan disable
1969 22:20:04.415933 == TX Byte 0 ==
1970 22:20:04.419575 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1971 22:20:04.422690 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1972 22:20:04.426142 == TX Byte 1 ==
1973 22:20:04.429308 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1974 22:20:04.432647 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1975 22:20:04.432730 ==
1976 22:20:04.435929 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 22:20:04.442738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 22:20:04.442822 ==
1979 22:20:04.454426 TX Vref=22, minBit 8, minWin=27, winSum=450
1980 22:20:04.457906 TX Vref=24, minBit 13, minWin=27, winSum=456
1981 22:20:04.461037 TX Vref=26, minBit 13, minWin=27, winSum=455
1982 22:20:04.464387 TX Vref=28, minBit 8, minWin=27, winSum=459
1983 22:20:04.467927 TX Vref=30, minBit 8, minWin=28, winSum=461
1984 22:20:04.474685 TX Vref=32, minBit 14, minWin=27, winSum=459
1985 22:20:04.477854 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1986 22:20:04.477937
1987 22:20:04.481012 Final TX Range 1 Vref 30
1988 22:20:04.481094
1989 22:20:04.481159 ==
1990 22:20:04.484465 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 22:20:04.487755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 22:20:04.490942 ==
1993 22:20:04.491023
1994 22:20:04.491088
1995 22:20:04.491148 TX Vref Scan disable
1996 22:20:04.494612 == TX Byte 0 ==
1997 22:20:04.498237 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1998 22:20:04.504719 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1999 22:20:04.504821 == TX Byte 1 ==
2000 22:20:04.508132 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2001 22:20:04.514818 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2002 22:20:04.514901
2003 22:20:04.514966 [DATLAT]
2004 22:20:04.515028 Freq=800, CH1 RK1
2005 22:20:04.515087
2006 22:20:04.518020 DATLAT Default: 0xa
2007 22:20:04.518102 0, 0xFFFF, sum = 0
2008 22:20:04.521266 1, 0xFFFF, sum = 0
2009 22:20:04.521349 2, 0xFFFF, sum = 0
2010 22:20:04.524983 3, 0xFFFF, sum = 0
2011 22:20:04.525067 4, 0xFFFF, sum = 0
2012 22:20:04.528072 5, 0xFFFF, sum = 0
2013 22:20:04.531269 6, 0xFFFF, sum = 0
2014 22:20:04.531352 7, 0xFFFF, sum = 0
2015 22:20:04.534781 8, 0xFFFF, sum = 0
2016 22:20:04.534864 9, 0x0, sum = 1
2017 22:20:04.534931 10, 0x0, sum = 2
2018 22:20:04.537842 11, 0x0, sum = 3
2019 22:20:04.537925 12, 0x0, sum = 4
2020 22:20:04.541555 best_step = 10
2021 22:20:04.541636
2022 22:20:04.541701 ==
2023 22:20:04.544674 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 22:20:04.547924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 22:20:04.548007 ==
2026 22:20:04.551153 RX Vref Scan: 0
2027 22:20:04.551234
2028 22:20:04.551299 RX Vref 0 -> 0, step: 1
2029 22:20:04.551360
2030 22:20:04.554372 RX Delay -79 -> 252, step: 8
2031 22:20:04.561327 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2032 22:20:04.564974 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2033 22:20:04.568069 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2034 22:20:04.571359 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2035 22:20:04.574515 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2036 22:20:04.581393 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2037 22:20:04.584451 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2038 22:20:04.588089 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2039 22:20:04.591338 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2040 22:20:04.594517 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2041 22:20:04.601237 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2042 22:20:04.604277 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2043 22:20:04.607755 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2044 22:20:04.611031 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2045 22:20:04.614215 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2046 22:20:04.621247 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2047 22:20:04.621333 ==
2048 22:20:04.624237 Dram Type= 6, Freq= 0, CH_1, rank 1
2049 22:20:04.627336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2050 22:20:04.627409 ==
2051 22:20:04.627477 DQS Delay:
2052 22:20:04.631059 DQS0 = 0, DQS1 = 0
2053 22:20:04.631136 DQM Delay:
2054 22:20:04.634296 DQM0 = 92, DQM1 = 85
2055 22:20:04.634364 DQ Delay:
2056 22:20:04.637497 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =92
2057 22:20:04.640999 DQ4 =96, DQ5 =108, DQ6 =96, DQ7 =88
2058 22:20:04.644223 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2059 22:20:04.647274 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2060 22:20:04.647343
2061 22:20:04.647403
2062 22:20:04.657362 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2063 22:20:04.657440 CH1 RK1: MR19=606, MR18=3C10
2064 22:20:04.664011 CH1_RK1: MR19=0x606, MR18=0x3C10, DQSOSC=394, MR23=63, INC=95, DEC=63
2065 22:20:04.667091 [RxdqsGatingPostProcess] freq 800
2066 22:20:04.674103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2067 22:20:04.677217 Pre-setting of DQS Precalculation
2068 22:20:04.680416 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2069 22:20:04.687572 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2070 22:20:04.694021 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2071 22:20:04.697456
2072 22:20:04.697528
2073 22:20:04.697597 [Calibration Summary] 1600 Mbps
2074 22:20:04.700777 CH 0, Rank 0
2075 22:20:04.700885 SW Impedance : PASS
2076 22:20:04.703986 DUTY Scan : NO K
2077 22:20:04.707162 ZQ Calibration : PASS
2078 22:20:04.707233 Jitter Meter : NO K
2079 22:20:04.710788 CBT Training : PASS
2080 22:20:04.713713 Write leveling : PASS
2081 22:20:04.713787 RX DQS gating : PASS
2082 22:20:04.717063 RX DQ/DQS(RDDQC) : PASS
2083 22:20:04.720419 TX DQ/DQS : PASS
2084 22:20:04.720488 RX DATLAT : PASS
2085 22:20:04.723689 RX DQ/DQS(Engine): PASS
2086 22:20:04.726922 TX OE : NO K
2087 22:20:04.727018 All Pass.
2088 22:20:04.727079
2089 22:20:04.727146 CH 0, Rank 1
2090 22:20:04.730612 SW Impedance : PASS
2091 22:20:04.733724 DUTY Scan : NO K
2092 22:20:04.733796 ZQ Calibration : PASS
2093 22:20:04.736931 Jitter Meter : NO K
2094 22:20:04.740082 CBT Training : PASS
2095 22:20:04.740153 Write leveling : PASS
2096 22:20:04.743531 RX DQS gating : PASS
2097 22:20:04.746710 RX DQ/DQS(RDDQC) : PASS
2098 22:20:04.746781 TX DQ/DQS : PASS
2099 22:20:04.750418 RX DATLAT : PASS
2100 22:20:04.750487 RX DQ/DQS(Engine): PASS
2101 22:20:04.753643 TX OE : NO K
2102 22:20:04.753713 All Pass.
2103 22:20:04.753773
2104 22:20:04.756787 CH 1, Rank 0
2105 22:20:04.756854 SW Impedance : PASS
2106 22:20:04.759845 DUTY Scan : NO K
2107 22:20:04.763551 ZQ Calibration : PASS
2108 22:20:04.763633 Jitter Meter : NO K
2109 22:20:04.766639 CBT Training : PASS
2110 22:20:04.770047 Write leveling : PASS
2111 22:20:04.770121 RX DQS gating : PASS
2112 22:20:04.773456 RX DQ/DQS(RDDQC) : PASS
2113 22:20:04.776359 TX DQ/DQS : PASS
2114 22:20:04.776434 RX DATLAT : PASS
2115 22:20:04.780004 RX DQ/DQS(Engine): PASS
2116 22:20:04.783112 TX OE : NO K
2117 22:20:04.783189 All Pass.
2118 22:20:04.783251
2119 22:20:04.783307 CH 1, Rank 1
2120 22:20:04.786427 SW Impedance : PASS
2121 22:20:04.790077 DUTY Scan : NO K
2122 22:20:04.790156 ZQ Calibration : PASS
2123 22:20:04.793137 Jitter Meter : NO K
2124 22:20:04.796435 CBT Training : PASS
2125 22:20:04.796507 Write leveling : PASS
2126 22:20:04.799764 RX DQS gating : PASS
2127 22:20:04.803409 RX DQ/DQS(RDDQC) : PASS
2128 22:20:04.803480 TX DQ/DQS : PASS
2129 22:20:04.806514 RX DATLAT : PASS
2130 22:20:04.806584 RX DQ/DQS(Engine): PASS
2131 22:20:04.809654 TX OE : NO K
2132 22:20:04.809731 All Pass.
2133 22:20:04.809791
2134 22:20:04.813068 DramC Write-DBI off
2135 22:20:04.816279 PER_BANK_REFRESH: Hybrid Mode
2136 22:20:04.816378 TX_TRACKING: ON
2137 22:20:04.819537 [GetDramInforAfterCalByMRR] Vendor 6.
2138 22:20:04.823203 [GetDramInforAfterCalByMRR] Revision 606.
2139 22:20:04.829580 [GetDramInforAfterCalByMRR] Revision 2 0.
2140 22:20:04.829665 MR0 0x3b3b
2141 22:20:04.829730 MR8 0x5151
2142 22:20:04.842085 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2143 22:20:04.842206
2144 22:20:04.842298 MR0 0x3b3b
2145 22:20:04.842393 MR8 0x5151
2146 22:20:04.842480 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2147 22:20:04.842572
2148 22:20:04.849728 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2149 22:20:04.853199 [FAST_K] Save calibration result to emmc
2150 22:20:04.856541 [FAST_K] Save calibration result to emmc
2151 22:20:04.859533 dram_init: config_dvfs: 1
2152 22:20:04.862775 dramc_set_vcore_voltage set vcore to 662500
2153 22:20:04.862845 Read voltage for 1200, 2
2154 22:20:04.866371 Vio18 = 0
2155 22:20:04.866469 Vcore = 662500
2156 22:20:04.866544 Vdram = 0
2157 22:20:04.869439 Vddq = 0
2158 22:20:04.869508 Vmddr = 0
2159 22:20:04.876143 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2160 22:20:04.879385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2161 22:20:04.882821 MEM_TYPE=3, freq_sel=15
2162 22:20:04.885965 sv_algorithm_assistance_LP4_1600
2163 22:20:04.889702 ============ PULL DRAM RESETB DOWN ============
2164 22:20:04.892757 ========== PULL DRAM RESETB DOWN end =========
2165 22:20:04.899431 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2166 22:20:04.902462 ===================================
2167 22:20:04.902542 LPDDR4 DRAM CONFIGURATION
2168 22:20:04.905946 ===================================
2169 22:20:04.909536 EX_ROW_EN[0] = 0x0
2170 22:20:04.912544 EX_ROW_EN[1] = 0x0
2171 22:20:04.912641 LP4Y_EN = 0x0
2172 22:20:04.915680 WORK_FSP = 0x0
2173 22:20:04.915754 WL = 0x4
2174 22:20:04.919364 RL = 0x4
2175 22:20:04.919447 BL = 0x2
2176 22:20:04.922654 RPST = 0x0
2177 22:20:04.922734 RD_PRE = 0x0
2178 22:20:04.925705 WR_PRE = 0x1
2179 22:20:04.925782 WR_PST = 0x0
2180 22:20:04.929143 DBI_WR = 0x0
2181 22:20:04.929221 DBI_RD = 0x0
2182 22:20:04.932619 OTF = 0x1
2183 22:20:04.935572 ===================================
2184 22:20:04.938983 ===================================
2185 22:20:04.939068 ANA top config
2186 22:20:04.942427 ===================================
2187 22:20:04.945737 DLL_ASYNC_EN = 0
2188 22:20:04.949125 ALL_SLAVE_EN = 0
2189 22:20:04.952405 NEW_RANK_MODE = 1
2190 22:20:04.952491 DLL_IDLE_MODE = 1
2191 22:20:04.955709 LP45_APHY_COMB_EN = 1
2192 22:20:04.959391 TX_ODT_DIS = 1
2193 22:20:04.962302 NEW_8X_MODE = 1
2194 22:20:04.965937 ===================================
2195 22:20:04.968995 ===================================
2196 22:20:04.969080 data_rate = 2400
2197 22:20:04.972348 CKR = 1
2198 22:20:04.975591 DQ_P2S_RATIO = 8
2199 22:20:04.979034 ===================================
2200 22:20:04.982537 CA_P2S_RATIO = 8
2201 22:20:04.985636 DQ_CA_OPEN = 0
2202 22:20:04.989060 DQ_SEMI_OPEN = 0
2203 22:20:04.989142 CA_SEMI_OPEN = 0
2204 22:20:04.992532 CA_FULL_RATE = 0
2205 22:20:04.995723 DQ_CKDIV4_EN = 0
2206 22:20:04.999238 CA_CKDIV4_EN = 0
2207 22:20:05.002216 CA_PREDIV_EN = 0
2208 22:20:05.005400 PH8_DLY = 17
2209 22:20:05.005483 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2210 22:20:05.008824 DQ_AAMCK_DIV = 4
2211 22:20:05.012000 CA_AAMCK_DIV = 4
2212 22:20:05.015640 CA_ADMCK_DIV = 4
2213 22:20:05.019020 DQ_TRACK_CA_EN = 0
2214 22:20:05.022493 CA_PICK = 1200
2215 22:20:05.025438 CA_MCKIO = 1200
2216 22:20:05.025522 MCKIO_SEMI = 0
2217 22:20:05.028897 PLL_FREQ = 2366
2218 22:20:05.032049 DQ_UI_PI_RATIO = 32
2219 22:20:05.035396 CA_UI_PI_RATIO = 0
2220 22:20:05.038912 ===================================
2221 22:20:05.042231 ===================================
2222 22:20:05.045221 memory_type:LPDDR4
2223 22:20:05.045303 GP_NUM : 10
2224 22:20:05.048585 SRAM_EN : 1
2225 22:20:05.052053 MD32_EN : 0
2226 22:20:05.055466 ===================================
2227 22:20:05.055549 [ANA_INIT] >>>>>>>>>>>>>>
2228 22:20:05.058580 <<<<<< [CONFIGURE PHASE]: ANA_TX
2229 22:20:05.062148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2230 22:20:05.065620 ===================================
2231 22:20:05.068638 data_rate = 2400,PCW = 0X5b00
2232 22:20:05.071879 ===================================
2233 22:20:05.075075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2234 22:20:05.082106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2235 22:20:05.085162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 22:20:05.092207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2237 22:20:05.095378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2238 22:20:05.098529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2239 22:20:05.098612 [ANA_INIT] flow start
2240 22:20:05.101734 [ANA_INIT] PLL >>>>>>>>
2241 22:20:05.105068 [ANA_INIT] PLL <<<<<<<<
2242 22:20:05.105149 [ANA_INIT] MIDPI >>>>>>>>
2243 22:20:05.108509 [ANA_INIT] MIDPI <<<<<<<<
2244 22:20:05.111929 [ANA_INIT] DLL >>>>>>>>
2245 22:20:05.115066 [ANA_INIT] DLL <<<<<<<<
2246 22:20:05.115147 [ANA_INIT] flow end
2247 22:20:05.118551 ============ LP4 DIFF to SE enter ============
2248 22:20:05.125128 ============ LP4 DIFF to SE exit ============
2249 22:20:05.125212 [ANA_INIT] <<<<<<<<<<<<<
2250 22:20:05.128437 [Flow] Enable top DCM control >>>>>
2251 22:20:05.132032 [Flow] Enable top DCM control <<<<<
2252 22:20:05.135221 Enable DLL master slave shuffle
2253 22:20:05.141659 ==============================================================
2254 22:20:05.141743 Gating Mode config
2255 22:20:05.148130 ==============================================================
2256 22:20:05.151585 Config description:
2257 22:20:05.161548 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2258 22:20:05.168195 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2259 22:20:05.171471 SELPH_MODE 0: By rank 1: By Phase
2260 22:20:05.178072 ==============================================================
2261 22:20:05.181676 GAT_TRACK_EN = 1
2262 22:20:05.181759 RX_GATING_MODE = 2
2263 22:20:05.184938 RX_GATING_TRACK_MODE = 2
2264 22:20:05.188384 SELPH_MODE = 1
2265 22:20:05.191642 PICG_EARLY_EN = 1
2266 22:20:05.195044 VALID_LAT_VALUE = 1
2267 22:20:05.201241 ==============================================================
2268 22:20:05.205020 Enter into Gating configuration >>>>
2269 22:20:05.207961 Exit from Gating configuration <<<<
2270 22:20:05.211464 Enter into DVFS_PRE_config >>>>>
2271 22:20:05.221224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2272 22:20:05.224492 Exit from DVFS_PRE_config <<<<<
2273 22:20:05.227849 Enter into PICG configuration >>>>
2274 22:20:05.231230 Exit from PICG configuration <<<<
2275 22:20:05.234525 [RX_INPUT] configuration >>>>>
2276 22:20:05.237948 [RX_INPUT] configuration <<<<<
2277 22:20:05.241076 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2278 22:20:05.247693 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2279 22:20:05.254515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 22:20:05.257646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 22:20:05.264629 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2282 22:20:05.271246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2283 22:20:05.274552 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2284 22:20:05.281174 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2285 22:20:05.284471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2286 22:20:05.287785 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2287 22:20:05.291121 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2288 22:20:05.297947 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 22:20:05.301065 ===================================
2290 22:20:05.301150 LPDDR4 DRAM CONFIGURATION
2291 22:20:05.304502 ===================================
2292 22:20:05.307743 EX_ROW_EN[0] = 0x0
2293 22:20:05.311165 EX_ROW_EN[1] = 0x0
2294 22:20:05.311248 LP4Y_EN = 0x0
2295 22:20:05.314600 WORK_FSP = 0x0
2296 22:20:05.314683 WL = 0x4
2297 22:20:05.317630 RL = 0x4
2298 22:20:05.317713 BL = 0x2
2299 22:20:05.320946 RPST = 0x0
2300 22:20:05.321028 RD_PRE = 0x0
2301 22:20:05.324667 WR_PRE = 0x1
2302 22:20:05.324751 WR_PST = 0x0
2303 22:20:05.327620 DBI_WR = 0x0
2304 22:20:05.327704 DBI_RD = 0x0
2305 22:20:05.330958 OTF = 0x1
2306 22:20:05.334266 ===================================
2307 22:20:05.337808 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2308 22:20:05.341036 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2309 22:20:05.347628 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 22:20:05.351176 ===================================
2311 22:20:05.351262 LPDDR4 DRAM CONFIGURATION
2312 22:20:05.354285 ===================================
2313 22:20:05.357683 EX_ROW_EN[0] = 0x10
2314 22:20:05.357769 EX_ROW_EN[1] = 0x0
2315 22:20:05.361310 LP4Y_EN = 0x0
2316 22:20:05.361395 WORK_FSP = 0x0
2317 22:20:05.364249 WL = 0x4
2318 22:20:05.364332 RL = 0x4
2319 22:20:05.367744 BL = 0x2
2320 22:20:05.367827 RPST = 0x0
2321 22:20:05.370924 RD_PRE = 0x0
2322 22:20:05.374185 WR_PRE = 0x1
2323 22:20:05.374270 WR_PST = 0x0
2324 22:20:05.377549 DBI_WR = 0x0
2325 22:20:05.377632 DBI_RD = 0x0
2326 22:20:05.380773 OTF = 0x1
2327 22:20:05.384281 ===================================
2328 22:20:05.387633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2329 22:20:05.391021 ==
2330 22:20:05.394469 Dram Type= 6, Freq= 0, CH_0, rank 0
2331 22:20:05.397845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2332 22:20:05.397928 ==
2333 22:20:05.400951 [Duty_Offset_Calibration]
2334 22:20:05.401033 B0:2 B1:0 CA:1
2335 22:20:05.401098
2336 22:20:05.404024 [DutyScan_Calibration_Flow] k_type=0
2337 22:20:05.413184
2338 22:20:05.413265 ==CLK 0==
2339 22:20:05.416500 Final CLK duty delay cell = -4
2340 22:20:05.420364 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2341 22:20:05.423315 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2342 22:20:05.426444 [-4] AVG Duty = 4953%(X100)
2343 22:20:05.426525
2344 22:20:05.429824 CH0 CLK Duty spec in!! Max-Min= 156%
2345 22:20:05.432965 [DutyScan_Calibration_Flow] ====Done====
2346 22:20:05.433047
2347 22:20:05.436233 [DutyScan_Calibration_Flow] k_type=1
2348 22:20:05.451614
2349 22:20:05.451705 ==DQS 0 ==
2350 22:20:05.454966 Final DQS duty delay cell = 0
2351 22:20:05.458194 [0] MAX Duty = 5187%(X100), DQS PI = 30
2352 22:20:05.461451 [0] MIN Duty = 4938%(X100), DQS PI = 2
2353 22:20:05.465169 [0] AVG Duty = 5062%(X100)
2354 22:20:05.465277
2355 22:20:05.465342 ==DQS 1 ==
2356 22:20:05.468359 Final DQS duty delay cell = -4
2357 22:20:05.471852 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2358 22:20:05.475304 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2359 22:20:05.478355 [-4] AVG Duty = 5031%(X100)
2360 22:20:05.478436
2361 22:20:05.481616 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2362 22:20:05.481696
2363 22:20:05.484699 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2364 22:20:05.488377 [DutyScan_Calibration_Flow] ====Done====
2365 22:20:05.488449
2366 22:20:05.491601 [DutyScan_Calibration_Flow] k_type=3
2367 22:20:05.508575
2368 22:20:05.508692 ==DQM 0 ==
2369 22:20:05.511781 Final DQM duty delay cell = 0
2370 22:20:05.515011 [0] MAX Duty = 5062%(X100), DQS PI = 24
2371 22:20:05.518155 [0] MIN Duty = 4844%(X100), DQS PI = 0
2372 22:20:05.521615 [0] AVG Duty = 4953%(X100)
2373 22:20:05.521695
2374 22:20:05.521758 ==DQM 1 ==
2375 22:20:05.524980 Final DQM duty delay cell = 0
2376 22:20:05.528590 [0] MAX Duty = 5187%(X100), DQS PI = 48
2377 22:20:05.531570 [0] MIN Duty = 5000%(X100), DQS PI = 22
2378 22:20:05.535048 [0] AVG Duty = 5093%(X100)
2379 22:20:05.535121
2380 22:20:05.538196 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2381 22:20:05.538281
2382 22:20:05.541625 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2383 22:20:05.545000 [DutyScan_Calibration_Flow] ====Done====
2384 22:20:05.545073
2385 22:20:05.548134 [DutyScan_Calibration_Flow] k_type=2
2386 22:20:05.564994
2387 22:20:05.565168 ==DQ 0 ==
2388 22:20:05.568553 Final DQ duty delay cell = -4
2389 22:20:05.571433 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2390 22:20:05.575308 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2391 22:20:05.578679 [-4] AVG Duty = 4953%(X100)
2392 22:20:05.578789
2393 22:20:05.578879 ==DQ 1 ==
2394 22:20:05.581698 Final DQ duty delay cell = 4
2395 22:20:05.584974 [4] MAX Duty = 5093%(X100), DQS PI = 4
2396 22:20:05.588413 [4] MIN Duty = 5031%(X100), DQS PI = 2
2397 22:20:05.591589 [4] AVG Duty = 5062%(X100)
2398 22:20:05.591662
2399 22:20:05.594766 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2400 22:20:05.594837
2401 22:20:05.597929 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2402 22:20:05.601536 [DutyScan_Calibration_Flow] ====Done====
2403 22:20:05.601618 ==
2404 22:20:05.605127 Dram Type= 6, Freq= 0, CH_1, rank 0
2405 22:20:05.608227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2406 22:20:05.608305 ==
2407 22:20:05.611444 [Duty_Offset_Calibration]
2408 22:20:05.611514 B0:0 B1:-1 CA:2
2409 22:20:05.611582
2410 22:20:05.614448 [DutyScan_Calibration_Flow] k_type=0
2411 22:20:05.625211
2412 22:20:05.625284 ==CLK 0==
2413 22:20:05.628668 Final CLK duty delay cell = 0
2414 22:20:05.631996 [0] MAX Duty = 5156%(X100), DQS PI = 16
2415 22:20:05.635096 [0] MIN Duty = 4938%(X100), DQS PI = 44
2416 22:20:05.638382 [0] AVG Duty = 5047%(X100)
2417 22:20:05.638455
2418 22:20:05.641575 CH1 CLK Duty spec in!! Max-Min= 218%
2419 22:20:05.645043 [DutyScan_Calibration_Flow] ====Done====
2420 22:20:05.645117
2421 22:20:05.648279 [DutyScan_Calibration_Flow] k_type=1
2422 22:20:05.664574
2423 22:20:05.664681 ==DQS 0 ==
2424 22:20:05.667693 Final DQS duty delay cell = 0
2425 22:20:05.671270 [0] MAX Duty = 5093%(X100), DQS PI = 24
2426 22:20:05.674341 [0] MIN Duty = 4969%(X100), DQS PI = 0
2427 22:20:05.674423 [0] AVG Duty = 5031%(X100)
2428 22:20:05.677767
2429 22:20:05.677852 ==DQS 1 ==
2430 22:20:05.681027 Final DQS duty delay cell = 0
2431 22:20:05.684445 [0] MAX Duty = 5156%(X100), DQS PI = 0
2432 22:20:05.687557 [0] MIN Duty = 4844%(X100), DQS PI = 36
2433 22:20:05.690858 [0] AVG Duty = 5000%(X100)
2434 22:20:05.690939
2435 22:20:05.694498 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2436 22:20:05.694581
2437 22:20:05.697970 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2438 22:20:05.700693 [DutyScan_Calibration_Flow] ====Done====
2439 22:20:05.700827
2440 22:20:05.704156 [DutyScan_Calibration_Flow] k_type=3
2441 22:20:05.720965
2442 22:20:05.721078 ==DQM 0 ==
2443 22:20:05.724669 Final DQM duty delay cell = 4
2444 22:20:05.728071 [4] MAX Duty = 5093%(X100), DQS PI = 20
2445 22:20:05.730975 [4] MIN Duty = 4969%(X100), DQS PI = 28
2446 22:20:05.734056 [4] AVG Duty = 5031%(X100)
2447 22:20:05.734167
2448 22:20:05.734230 ==DQM 1 ==
2449 22:20:05.737911 Final DQM duty delay cell = -4
2450 22:20:05.741032 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2451 22:20:05.744285 [-4] MIN Duty = 4751%(X100), DQS PI = 38
2452 22:20:05.747488 [-4] AVG Duty = 4875%(X100)
2453 22:20:05.747579
2454 22:20:05.750729 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2455 22:20:05.750809
2456 22:20:05.754285 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2457 22:20:05.757773 [DutyScan_Calibration_Flow] ====Done====
2458 22:20:05.757845
2459 22:20:05.760603 [DutyScan_Calibration_Flow] k_type=2
2460 22:20:05.777703
2461 22:20:05.777783 ==DQ 0 ==
2462 22:20:05.780924 Final DQ duty delay cell = 0
2463 22:20:05.784555 [0] MAX Duty = 5062%(X100), DQS PI = 20
2464 22:20:05.788066 [0] MIN Duty = 4938%(X100), DQS PI = 46
2465 22:20:05.790942 [0] AVG Duty = 5000%(X100)
2466 22:20:05.791017
2467 22:20:05.791079 ==DQ 1 ==
2468 22:20:05.794744 Final DQ duty delay cell = 0
2469 22:20:05.797899 [0] MAX Duty = 5062%(X100), DQS PI = 4
2470 22:20:05.801104 [0] MIN Duty = 4813%(X100), DQS PI = 34
2471 22:20:05.801186 [0] AVG Duty = 4937%(X100)
2472 22:20:05.804532
2473 22:20:05.807788 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2474 22:20:05.807871
2475 22:20:05.810951 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2476 22:20:05.814223 [DutyScan_Calibration_Flow] ====Done====
2477 22:20:05.817589 nWR fixed to 30
2478 22:20:05.817672 [ModeRegInit_LP4] CH0 RK0
2479 22:20:05.821104 [ModeRegInit_LP4] CH0 RK1
2480 22:20:05.824219 [ModeRegInit_LP4] CH1 RK0
2481 22:20:05.827520 [ModeRegInit_LP4] CH1 RK1
2482 22:20:05.827601 match AC timing 7
2483 22:20:05.831346 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2484 22:20:05.837569 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2485 22:20:05.840913 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2486 22:20:05.847495 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2487 22:20:05.850855 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2488 22:20:05.850937 ==
2489 22:20:05.854284 Dram Type= 6, Freq= 0, CH_0, rank 0
2490 22:20:05.857648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 22:20:05.857730 ==
2492 22:20:05.864265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 22:20:05.870523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 22:20:05.877599 [CA 0] Center 38 (7~69) winsize 63
2495 22:20:05.881054 [CA 1] Center 38 (7~69) winsize 63
2496 22:20:05.884290 [CA 2] Center 35 (4~66) winsize 63
2497 22:20:05.887986 [CA 3] Center 35 (4~66) winsize 63
2498 22:20:05.890964 [CA 4] Center 34 (4~65) winsize 62
2499 22:20:05.894393 [CA 5] Center 33 (3~63) winsize 61
2500 22:20:05.894474
2501 22:20:05.897690 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 22:20:05.897772
2503 22:20:05.901140 [CATrainingPosCal] consider 1 rank data
2504 22:20:05.904390 u2DelayCellTimex100 = 270/100 ps
2505 22:20:05.907696 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2506 22:20:05.911142 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2507 22:20:05.917752 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2508 22:20:05.921038 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2509 22:20:05.924190 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2510 22:20:05.927913 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2511 22:20:05.927982
2512 22:20:05.931060 CA PerBit enable=1, Macro0, CA PI delay=33
2513 22:20:05.931128
2514 22:20:05.934377 [CBTSetCACLKResult] CA Dly = 33
2515 22:20:05.934443 CS Dly: 6 (0~37)
2516 22:20:05.937463 ==
2517 22:20:05.937530 Dram Type= 6, Freq= 0, CH_0, rank 1
2518 22:20:05.944620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 22:20:05.944689 ==
2520 22:20:05.947544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2521 22:20:05.954022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2522 22:20:05.963265 [CA 0] Center 39 (8~70) winsize 63
2523 22:20:05.966708 [CA 1] Center 38 (8~69) winsize 62
2524 22:20:05.970224 [CA 2] Center 35 (5~66) winsize 62
2525 22:20:05.973568 [CA 3] Center 35 (5~66) winsize 62
2526 22:20:05.976712 [CA 4] Center 34 (4~65) winsize 62
2527 22:20:05.980090 [CA 5] Center 34 (4~64) winsize 61
2528 22:20:05.980158
2529 22:20:05.983397 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2530 22:20:05.983463
2531 22:20:05.986556 [CATrainingPosCal] consider 2 rank data
2532 22:20:05.989797 u2DelayCellTimex100 = 270/100 ps
2533 22:20:05.993502 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2534 22:20:05.999937 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2535 22:20:06.003510 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 22:20:06.006521 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2537 22:20:06.010022 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2538 22:20:06.013159 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2539 22:20:06.013225
2540 22:20:06.016422 CA PerBit enable=1, Macro0, CA PI delay=33
2541 22:20:06.016489
2542 22:20:06.020175 [CBTSetCACLKResult] CA Dly = 33
2543 22:20:06.020239 CS Dly: 7 (0~39)
2544 22:20:06.020301
2545 22:20:06.023240 ----->DramcWriteLeveling(PI) begin...
2546 22:20:06.026502 ==
2547 22:20:06.029953 Dram Type= 6, Freq= 0, CH_0, rank 0
2548 22:20:06.033333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 22:20:06.033403 ==
2550 22:20:06.036649 Write leveling (Byte 0): 33 => 33
2551 22:20:06.039974 Write leveling (Byte 1): 31 => 31
2552 22:20:06.043320 DramcWriteLeveling(PI) end<-----
2553 22:20:06.043389
2554 22:20:06.043448 ==
2555 22:20:06.046772 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 22:20:06.050105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 22:20:06.050171 ==
2558 22:20:06.053092 [Gating] SW mode calibration
2559 22:20:06.059856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2560 22:20:06.066499 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2561 22:20:06.070124 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2562 22:20:06.073056 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2563 22:20:06.079961 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 22:20:06.082938 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 22:20:06.086157 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 22:20:06.092943 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 22:20:06.096408 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2568 22:20:06.099651 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2569 22:20:06.102761 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
2570 22:20:06.109688 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 22:20:06.112994 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 22:20:06.116254 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 22:20:06.122880 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 22:20:06.126229 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 22:20:06.129839 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2576 22:20:06.136424 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2577 22:20:06.139540 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2578 22:20:06.142965 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2579 22:20:06.149503 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 22:20:06.152792 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 22:20:06.156148 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 22:20:06.162959 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 22:20:06.166322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 22:20:06.169425 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2585 22:20:06.176454 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2586 22:20:06.179249 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2587 22:20:06.182709 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 22:20:06.189535 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 22:20:06.192675 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 22:20:06.195994 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 22:20:06.202795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 22:20:06.205997 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 22:20:06.209377 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 22:20:06.212535 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 22:20:06.219412 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 22:20:06.222655 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 22:20:06.226172 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 22:20:06.232532 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 22:20:06.236088 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2600 22:20:06.239518 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2601 22:20:06.242711 Total UI for P1: 0, mck2ui 16
2602 22:20:06.246117 best dqsien dly found for B0: ( 1, 3, 24)
2603 22:20:06.252590 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2604 22:20:06.256037 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 22:20:06.259243 Total UI for P1: 0, mck2ui 16
2606 22:20:06.262664 best dqsien dly found for B1: ( 1, 3, 30)
2607 22:20:06.265969 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2608 22:20:06.269102 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2609 22:20:06.269211
2610 22:20:06.272560 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2611 22:20:06.275902 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2612 22:20:06.279431 [Gating] SW calibration Done
2613 22:20:06.279516 ==
2614 22:20:06.282404 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 22:20:06.285998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 22:20:06.289035 ==
2617 22:20:06.289119 RX Vref Scan: 0
2618 22:20:06.289204
2619 22:20:06.292934 RX Vref 0 -> 0, step: 1
2620 22:20:06.293044
2621 22:20:06.295676 RX Delay -40 -> 252, step: 8
2622 22:20:06.299112 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2623 22:20:06.302468 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2624 22:20:06.305940 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2625 22:20:06.308969 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2626 22:20:06.315536 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2627 22:20:06.319142 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2628 22:20:06.322140 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2629 22:20:06.325423 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2630 22:20:06.328979 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2631 22:20:06.335484 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2632 22:20:06.338977 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2633 22:20:06.342058 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2634 22:20:06.345439 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2635 22:20:06.348848 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2636 22:20:06.355346 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2637 22:20:06.358666 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2638 22:20:06.358776 ==
2639 22:20:06.362096 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 22:20:06.365479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 22:20:06.365564 ==
2642 22:20:06.368460 DQS Delay:
2643 22:20:06.368544 DQS0 = 0, DQS1 = 0
2644 22:20:06.368646 DQM Delay:
2645 22:20:06.372015 DQM0 = 123, DQM1 = 110
2646 22:20:06.372099 DQ Delay:
2647 22:20:06.375198 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2648 22:20:06.378580 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2649 22:20:06.381911 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2650 22:20:06.388483 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2651 22:20:06.388568
2652 22:20:06.388653
2653 22:20:06.388734 ==
2654 22:20:06.392139 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 22:20:06.395356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 22:20:06.395467 ==
2657 22:20:06.395552
2658 22:20:06.395632
2659 22:20:06.398538 TX Vref Scan disable
2660 22:20:06.398623 == TX Byte 0 ==
2661 22:20:06.404942 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2662 22:20:06.408257 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2663 22:20:06.408342 == TX Byte 1 ==
2664 22:20:06.414973 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2665 22:20:06.418160 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2666 22:20:06.418245 ==
2667 22:20:06.421694 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 22:20:06.424714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 22:20:06.424854 ==
2670 22:20:06.437896 TX Vref=22, minBit 0, minWin=24, winSum=414
2671 22:20:06.441307 TX Vref=24, minBit 1, minWin=24, winSum=416
2672 22:20:06.444472 TX Vref=26, minBit 0, minWin=25, winSum=414
2673 22:20:06.447875 TX Vref=28, minBit 0, minWin=25, winSum=423
2674 22:20:06.451045 TX Vref=30, minBit 3, minWin=25, winSum=422
2675 22:20:06.457671 TX Vref=32, minBit 1, minWin=25, winSum=419
2676 22:20:06.461449 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
2677 22:20:06.461535
2678 22:20:06.464708 Final TX Range 1 Vref 28
2679 22:20:06.464846
2680 22:20:06.464931 ==
2681 22:20:06.467637 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 22:20:06.471062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 22:20:06.471148 ==
2684 22:20:06.474667
2685 22:20:06.474751
2686 22:20:06.474835 TX Vref Scan disable
2687 22:20:06.477562 == TX Byte 0 ==
2688 22:20:06.480901 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2689 22:20:06.484604 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2690 22:20:06.487883 == TX Byte 1 ==
2691 22:20:06.490907 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2692 22:20:06.494285 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2693 22:20:06.497756
2694 22:20:06.497841 [DATLAT]
2695 22:20:06.497927 Freq=1200, CH0 RK0
2696 22:20:06.498009
2697 22:20:06.501099 DATLAT Default: 0xd
2698 22:20:06.501183 0, 0xFFFF, sum = 0
2699 22:20:06.504449 1, 0xFFFF, sum = 0
2700 22:20:06.504535 2, 0xFFFF, sum = 0
2701 22:20:06.507402 3, 0xFFFF, sum = 0
2702 22:20:06.511066 4, 0xFFFF, sum = 0
2703 22:20:06.511152 5, 0xFFFF, sum = 0
2704 22:20:06.514256 6, 0xFFFF, sum = 0
2705 22:20:06.514342 7, 0xFFFF, sum = 0
2706 22:20:06.517526 8, 0xFFFF, sum = 0
2707 22:20:06.517612 9, 0xFFFF, sum = 0
2708 22:20:06.520925 10, 0xFFFF, sum = 0
2709 22:20:06.521011 11, 0xFFFF, sum = 0
2710 22:20:06.524077 12, 0x0, sum = 1
2711 22:20:06.524163 13, 0x0, sum = 2
2712 22:20:06.527296 14, 0x0, sum = 3
2713 22:20:06.527381 15, 0x0, sum = 4
2714 22:20:06.527468 best_step = 13
2715 22:20:06.530679
2716 22:20:06.530763 ==
2717 22:20:06.534329 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 22:20:06.537343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 22:20:06.537429 ==
2720 22:20:06.537514 RX Vref Scan: 1
2721 22:20:06.537593
2722 22:20:06.541210 Set Vref Range= 32 -> 127
2723 22:20:06.541295
2724 22:20:06.543935 RX Vref 32 -> 127, step: 1
2725 22:20:06.544059
2726 22:20:06.547247 RX Delay -13 -> 252, step: 4
2727 22:20:06.547332
2728 22:20:06.550820 Set Vref, RX VrefLevel [Byte0]: 32
2729 22:20:06.554105 [Byte1]: 32
2730 22:20:06.554189
2731 22:20:06.557355 Set Vref, RX VrefLevel [Byte0]: 33
2732 22:20:06.560621 [Byte1]: 33
2733 22:20:06.564210
2734 22:20:06.564295 Set Vref, RX VrefLevel [Byte0]: 34
2735 22:20:06.567499 [Byte1]: 34
2736 22:20:06.571666
2737 22:20:06.571751 Set Vref, RX VrefLevel [Byte0]: 35
2738 22:20:06.575094 [Byte1]: 35
2739 22:20:06.580210
2740 22:20:06.580295 Set Vref, RX VrefLevel [Byte0]: 36
2741 22:20:06.583217 [Byte1]: 36
2742 22:20:06.587551
2743 22:20:06.587636 Set Vref, RX VrefLevel [Byte0]: 37
2744 22:20:06.594073 [Byte1]: 37
2745 22:20:06.594157
2746 22:20:06.597629 Set Vref, RX VrefLevel [Byte0]: 38
2747 22:20:06.600718 [Byte1]: 38
2748 22:20:06.600857
2749 22:20:06.604104 Set Vref, RX VrefLevel [Byte0]: 39
2750 22:20:06.607246 [Byte1]: 39
2751 22:20:06.611180
2752 22:20:06.611265 Set Vref, RX VrefLevel [Byte0]: 40
2753 22:20:06.614819 [Byte1]: 40
2754 22:20:06.619230
2755 22:20:06.619315 Set Vref, RX VrefLevel [Byte0]: 41
2756 22:20:06.622598 [Byte1]: 41
2757 22:20:06.627317
2758 22:20:06.627402 Set Vref, RX VrefLevel [Byte0]: 42
2759 22:20:06.630696 [Byte1]: 42
2760 22:20:06.634952
2761 22:20:06.635037 Set Vref, RX VrefLevel [Byte0]: 43
2762 22:20:06.638258 [Byte1]: 43
2763 22:20:06.642718
2764 22:20:06.642803 Set Vref, RX VrefLevel [Byte0]: 44
2765 22:20:06.646224 [Byte1]: 44
2766 22:20:06.650881
2767 22:20:06.650956 Set Vref, RX VrefLevel [Byte0]: 45
2768 22:20:06.654135 [Byte1]: 45
2769 22:20:06.658756
2770 22:20:06.658835 Set Vref, RX VrefLevel [Byte0]: 46
2771 22:20:06.661800 [Byte1]: 46
2772 22:20:06.666497
2773 22:20:06.666568 Set Vref, RX VrefLevel [Byte0]: 47
2774 22:20:06.669929 [Byte1]: 47
2775 22:20:06.674435
2776 22:20:06.674504 Set Vref, RX VrefLevel [Byte0]: 48
2777 22:20:06.678066 [Byte1]: 48
2778 22:20:06.682227
2779 22:20:06.682294 Set Vref, RX VrefLevel [Byte0]: 49
2780 22:20:06.685476 [Byte1]: 49
2781 22:20:06.690162
2782 22:20:06.690230 Set Vref, RX VrefLevel [Byte0]: 50
2783 22:20:06.693485 [Byte1]: 50
2784 22:20:06.698388
2785 22:20:06.698456 Set Vref, RX VrefLevel [Byte0]: 51
2786 22:20:06.701515 [Byte1]: 51
2787 22:20:06.706324
2788 22:20:06.706391 Set Vref, RX VrefLevel [Byte0]: 52
2789 22:20:06.709188 [Byte1]: 52
2790 22:20:06.713800
2791 22:20:06.713867 Set Vref, RX VrefLevel [Byte0]: 53
2792 22:20:06.717124 [Byte1]: 53
2793 22:20:06.722000
2794 22:20:06.722067 Set Vref, RX VrefLevel [Byte0]: 54
2795 22:20:06.724976 [Byte1]: 54
2796 22:20:06.729558
2797 22:20:06.729639 Set Vref, RX VrefLevel [Byte0]: 55
2798 22:20:06.732998 [Byte1]: 55
2799 22:20:06.737579
2800 22:20:06.737660 Set Vref, RX VrefLevel [Byte0]: 56
2801 22:20:06.740762 [Byte1]: 56
2802 22:20:06.745563
2803 22:20:06.745644 Set Vref, RX VrefLevel [Byte0]: 57
2804 22:20:06.748767 [Byte1]: 57
2805 22:20:06.753205
2806 22:20:06.753286 Set Vref, RX VrefLevel [Byte0]: 58
2807 22:20:06.756790 [Byte1]: 58
2808 22:20:06.761244
2809 22:20:06.761325 Set Vref, RX VrefLevel [Byte0]: 59
2810 22:20:06.764641 [Byte1]: 59
2811 22:20:06.769019
2812 22:20:06.769100 Set Vref, RX VrefLevel [Byte0]: 60
2813 22:20:06.772263 [Byte1]: 60
2814 22:20:06.776960
2815 22:20:06.777041 Set Vref, RX VrefLevel [Byte0]: 61
2816 22:20:06.780362 [Byte1]: 61
2817 22:20:06.784962
2818 22:20:06.785044 Set Vref, RX VrefLevel [Byte0]: 62
2819 22:20:06.787953 [Byte1]: 62
2820 22:20:06.792561
2821 22:20:06.792642 Set Vref, RX VrefLevel [Byte0]: 63
2822 22:20:06.795886 [Byte1]: 63
2823 22:20:06.800694
2824 22:20:06.800782 Set Vref, RX VrefLevel [Byte0]: 64
2825 22:20:06.803840 [Byte1]: 64
2826 22:20:06.808425
2827 22:20:06.808506 Set Vref, RX VrefLevel [Byte0]: 65
2828 22:20:06.811922 [Byte1]: 65
2829 22:20:06.816395
2830 22:20:06.816476 Set Vref, RX VrefLevel [Byte0]: 66
2831 22:20:06.819921 [Byte1]: 66
2832 22:20:06.824323
2833 22:20:06.824404 Set Vref, RX VrefLevel [Byte0]: 67
2834 22:20:06.827513 [Byte1]: 67
2835 22:20:06.832174
2836 22:20:06.832256 Set Vref, RX VrefLevel [Byte0]: 68
2837 22:20:06.835787 [Byte1]: 68
2838 22:20:06.840163
2839 22:20:06.840244 Set Vref, RX VrefLevel [Byte0]: 69
2840 22:20:06.843413 [Byte1]: 69
2841 22:20:06.847991
2842 22:20:06.848073 Final RX Vref Byte 0 = 59 to rank0
2843 22:20:06.851150 Final RX Vref Byte 1 = 49 to rank0
2844 22:20:06.854661 Final RX Vref Byte 0 = 59 to rank1
2845 22:20:06.858326 Final RX Vref Byte 1 = 49 to rank1==
2846 22:20:06.861579 Dram Type= 6, Freq= 0, CH_0, rank 0
2847 22:20:06.867843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 22:20:06.867926 ==
2849 22:20:06.867991 DQS Delay:
2850 22:20:06.868050 DQS0 = 0, DQS1 = 0
2851 22:20:06.871517 DQM Delay:
2852 22:20:06.871599 DQM0 = 122, DQM1 = 109
2853 22:20:06.874559 DQ Delay:
2854 22:20:06.878206 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2855 22:20:06.881040 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2856 22:20:06.884438 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2857 22:20:06.887669 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2858 22:20:06.887751
2859 22:20:06.887815
2860 22:20:06.897575 [DQSOSCAuto] RK0, (LSB)MR18= 0xc09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2861 22:20:06.897658 CH0 RK0: MR19=404, MR18=C09
2862 22:20:06.904434 CH0_RK0: MR19=0x404, MR18=0xC09, DQSOSC=405, MR23=63, INC=39, DEC=26
2863 22:20:06.904517
2864 22:20:06.907728 ----->DramcWriteLeveling(PI) begin...
2865 22:20:06.907812 ==
2866 22:20:06.911257 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 22:20:06.914396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 22:20:06.917935 ==
2869 22:20:06.918017 Write leveling (Byte 0): 34 => 34
2870 22:20:06.921080 Write leveling (Byte 1): 30 => 30
2871 22:20:06.924447 DramcWriteLeveling(PI) end<-----
2872 22:20:06.924529
2873 22:20:06.924593 ==
2874 22:20:06.928023 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 22:20:06.934316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 22:20:06.934398 ==
2877 22:20:06.934463 [Gating] SW mode calibration
2878 22:20:06.944327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2879 22:20:06.947808 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2880 22:20:06.954399 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2881 22:20:06.957405 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 22:20:06.960695 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 22:20:06.967812 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 22:20:06.970726 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 22:20:06.974498 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 22:20:06.977524 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 22:20:06.983999 0 15 28 | B1->B0 | 2d2d 2d2d | 0 0 | (0 1) (0 1)
2888 22:20:06.987332 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 22:20:06.990893 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 22:20:06.997450 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 22:20:07.000986 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 22:20:07.004224 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 22:20:07.010691 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 22:20:07.014164 1 0 24 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
2895 22:20:07.017629 1 0 28 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
2896 22:20:07.024119 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 22:20:07.027048 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 22:20:07.030555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 22:20:07.037231 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 22:20:07.040470 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 22:20:07.043847 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 22:20:07.050340 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 22:20:07.053944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2904 22:20:07.057499 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 22:20:07.063677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 22:20:07.066944 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 22:20:07.070452 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 22:20:07.077353 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 22:20:07.080664 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 22:20:07.083670 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 22:20:07.090294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 22:20:07.093380 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 22:20:07.096797 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 22:20:07.103719 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 22:20:07.106959 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 22:20:07.110100 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 22:20:07.116995 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 22:20:07.120103 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 22:20:07.123549 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2920 22:20:07.126667 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 22:20:07.130078 Total UI for P1: 0, mck2ui 16
2922 22:20:07.133315 best dqsien dly found for B0: ( 1, 3, 28)
2923 22:20:07.136886 Total UI for P1: 0, mck2ui 16
2924 22:20:07.139899 best dqsien dly found for B1: ( 1, 3, 30)
2925 22:20:07.143379 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2926 22:20:07.150038 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2927 22:20:07.150120
2928 22:20:07.153401 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2929 22:20:07.156588 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2930 22:20:07.160097 [Gating] SW calibration Done
2931 22:20:07.160178 ==
2932 22:20:07.163422 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 22:20:07.166647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 22:20:07.166730 ==
2935 22:20:07.166835 RX Vref Scan: 0
2936 22:20:07.170061
2937 22:20:07.170143 RX Vref 0 -> 0, step: 1
2938 22:20:07.170208
2939 22:20:07.174006 RX Delay -40 -> 252, step: 8
2940 22:20:07.176541 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2941 22:20:07.179847 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2942 22:20:07.186708 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2943 22:20:07.189765 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2944 22:20:07.193103 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2945 22:20:07.196670 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2946 22:20:07.199870 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2947 22:20:07.206528 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2948 22:20:07.209903 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2949 22:20:07.213025 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2950 22:20:07.216573 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2951 22:20:07.219925 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2952 22:20:07.226677 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2953 22:20:07.229735 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2954 22:20:07.233231 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2955 22:20:07.236601 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2956 22:20:07.236709 ==
2957 22:20:07.239753 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 22:20:07.246520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 22:20:07.246602 ==
2960 22:20:07.246668 DQS Delay:
2961 22:20:07.246727 DQS0 = 0, DQS1 = 0
2962 22:20:07.249593 DQM Delay:
2963 22:20:07.249675 DQM0 = 120, DQM1 = 108
2964 22:20:07.253136 DQ Delay:
2965 22:20:07.256529 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2966 22:20:07.259570 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2967 22:20:07.263155 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2968 22:20:07.266436 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2969 22:20:07.266518
2970 22:20:07.266583
2971 22:20:07.266642 ==
2972 22:20:07.269569 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 22:20:07.272939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 22:20:07.273022 ==
2975 22:20:07.276357
2976 22:20:07.276438
2977 22:20:07.276502 TX Vref Scan disable
2978 22:20:07.279364 == TX Byte 0 ==
2979 22:20:07.283053 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2980 22:20:07.287286 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2981 22:20:07.289774 == TX Byte 1 ==
2982 22:20:07.293220 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2983 22:20:07.296345 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2984 22:20:07.296427 ==
2985 22:20:07.299444 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 22:20:07.305996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 22:20:07.306078 ==
2988 22:20:07.317152 TX Vref=22, minBit 1, minWin=24, winSum=412
2989 22:20:07.320570 TX Vref=24, minBit 3, minWin=24, winSum=415
2990 22:20:07.323756 TX Vref=26, minBit 1, minWin=24, winSum=418
2991 22:20:07.327365 TX Vref=28, minBit 1, minWin=25, winSum=425
2992 22:20:07.330549 TX Vref=30, minBit 2, minWin=25, winSum=424
2993 22:20:07.333993 TX Vref=32, minBit 1, minWin=25, winSum=421
2994 22:20:07.340693 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
2995 22:20:07.340802
2996 22:20:07.343721 Final TX Range 1 Vref 28
2997 22:20:07.343803
2998 22:20:07.343867 ==
2999 22:20:07.347251 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 22:20:07.350267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 22:20:07.350349 ==
3002 22:20:07.350414
3003 22:20:07.353780
3004 22:20:07.353862 TX Vref Scan disable
3005 22:20:07.356952 == TX Byte 0 ==
3006 22:20:07.360312 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3007 22:20:07.363593 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3008 22:20:07.367219 == TX Byte 1 ==
3009 22:20:07.370398 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3010 22:20:07.373699 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3011 22:20:07.376984
3012 22:20:07.377065 [DATLAT]
3013 22:20:07.377130 Freq=1200, CH0 RK1
3014 22:20:07.377191
3015 22:20:07.380254 DATLAT Default: 0xd
3016 22:20:07.380340 0, 0xFFFF, sum = 0
3017 22:20:07.383423 1, 0xFFFF, sum = 0
3018 22:20:07.383507 2, 0xFFFF, sum = 0
3019 22:20:07.387473 3, 0xFFFF, sum = 0
3020 22:20:07.387556 4, 0xFFFF, sum = 0
3021 22:20:07.390283 5, 0xFFFF, sum = 0
3022 22:20:07.393680 6, 0xFFFF, sum = 0
3023 22:20:07.393762 7, 0xFFFF, sum = 0
3024 22:20:07.397162 8, 0xFFFF, sum = 0
3025 22:20:07.397246 9, 0xFFFF, sum = 0
3026 22:20:07.400432 10, 0xFFFF, sum = 0
3027 22:20:07.400516 11, 0xFFFF, sum = 0
3028 22:20:07.404014 12, 0x0, sum = 1
3029 22:20:07.404098 13, 0x0, sum = 2
3030 22:20:07.406928 14, 0x0, sum = 3
3031 22:20:07.407011 15, 0x0, sum = 4
3032 22:20:07.407079 best_step = 13
3033 22:20:07.407139
3034 22:20:07.410336 ==
3035 22:20:07.413800 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 22:20:07.416969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 22:20:07.417084 ==
3038 22:20:07.417224 RX Vref Scan: 0
3039 22:20:07.417352
3040 22:20:07.420409 RX Vref 0 -> 0, step: 1
3041 22:20:07.420505
3042 22:20:07.424014 RX Delay -21 -> 252, step: 4
3043 22:20:07.427221 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3044 22:20:07.433652 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3045 22:20:07.437124 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3046 22:20:07.440313 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3047 22:20:07.443626 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3048 22:20:07.447220 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3049 22:20:07.453414 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3050 22:20:07.456946 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3051 22:20:07.460099 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3052 22:20:07.463622 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3053 22:20:07.467392 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3054 22:20:07.470154 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3055 22:20:07.476877 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3056 22:20:07.480301 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3057 22:20:07.483427 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3058 22:20:07.487053 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3059 22:20:07.487136 ==
3060 22:20:07.490493 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 22:20:07.496640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 22:20:07.496749 ==
3063 22:20:07.496857 DQS Delay:
3064 22:20:07.499959 DQS0 = 0, DQS1 = 0
3065 22:20:07.500042 DQM Delay:
3066 22:20:07.503426 DQM0 = 119, DQM1 = 107
3067 22:20:07.503509 DQ Delay:
3068 22:20:07.506913 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3069 22:20:07.509941 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3070 22:20:07.513344 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3071 22:20:07.516718 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3072 22:20:07.516820
3073 22:20:07.516884
3074 22:20:07.526827 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3075 22:20:07.526903 CH0 RK1: MR19=403, MR18=CF4
3076 22:20:07.533294 CH0_RK1: MR19=0x403, MR18=0xCF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3077 22:20:07.536536 [RxdqsGatingPostProcess] freq 1200
3078 22:20:07.543274 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3079 22:20:07.546702 best DQS0 dly(2T, 0.5T) = (0, 11)
3080 22:20:07.549731 best DQS1 dly(2T, 0.5T) = (0, 11)
3081 22:20:07.553033 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3082 22:20:07.556486 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3083 22:20:07.556561 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 22:20:07.559929 best DQS1 dly(2T, 0.5T) = (0, 11)
3085 22:20:07.563189 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 22:20:07.566708 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3087 22:20:07.569681 Pre-setting of DQS Precalculation
3088 22:20:07.576575 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3089 22:20:07.576650 ==
3090 22:20:07.579611 Dram Type= 6, Freq= 0, CH_1, rank 0
3091 22:20:07.583321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 22:20:07.583398 ==
3093 22:20:07.589535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 22:20:07.595944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3095 22:20:07.603311 [CA 0] Center 37 (7~68) winsize 62
3096 22:20:07.606270 [CA 1] Center 37 (7~68) winsize 62
3097 22:20:07.609921 [CA 2] Center 35 (5~65) winsize 61
3098 22:20:07.613144 [CA 3] Center 34 (4~65) winsize 62
3099 22:20:07.616884 [CA 4] Center 34 (3~65) winsize 63
3100 22:20:07.619615 [CA 5] Center 33 (3~64) winsize 62
3101 22:20:07.619722
3102 22:20:07.623183 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3103 22:20:07.623255
3104 22:20:07.626472 [CATrainingPosCal] consider 1 rank data
3105 22:20:07.629676 u2DelayCellTimex100 = 270/100 ps
3106 22:20:07.633100 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3107 22:20:07.636535 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3108 22:20:07.642992 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3109 22:20:07.646308 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3110 22:20:07.649677 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3111 22:20:07.652936 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3112 22:20:07.653007
3113 22:20:07.656672 CA PerBit enable=1, Macro0, CA PI delay=33
3114 22:20:07.656795
3115 22:20:07.659935 [CBTSetCACLKResult] CA Dly = 33
3116 22:20:07.660003 CS Dly: 5 (0~36)
3117 22:20:07.660071 ==
3118 22:20:07.662979 Dram Type= 6, Freq= 0, CH_1, rank 1
3119 22:20:07.669660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 22:20:07.669735 ==
3121 22:20:07.672876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3122 22:20:07.679375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3123 22:20:07.688728 [CA 0] Center 38 (8~68) winsize 61
3124 22:20:07.692084 [CA 1] Center 37 (7~68) winsize 62
3125 22:20:07.695569 [CA 2] Center 35 (5~66) winsize 62
3126 22:20:07.698680 [CA 3] Center 35 (5~65) winsize 61
3127 22:20:07.702263 [CA 4] Center 35 (5~65) winsize 61
3128 22:20:07.705589 [CA 5] Center 34 (4~64) winsize 61
3129 22:20:07.705662
3130 22:20:07.708827 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3131 22:20:07.708898
3132 22:20:07.712236 [CATrainingPosCal] consider 2 rank data
3133 22:20:07.715223 u2DelayCellTimex100 = 270/100 ps
3134 22:20:07.718984 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3135 22:20:07.722292 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3136 22:20:07.728900 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3137 22:20:07.732243 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3138 22:20:07.735262 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3139 22:20:07.738841 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3140 22:20:07.738913
3141 22:20:07.741788 CA PerBit enable=1, Macro0, CA PI delay=34
3142 22:20:07.741868
3143 22:20:07.745636 [CBTSetCACLKResult] CA Dly = 34
3144 22:20:07.745724 CS Dly: 6 (0~39)
3145 22:20:07.745789
3146 22:20:07.748652 ----->DramcWriteLeveling(PI) begin...
3147 22:20:07.752343 ==
3148 22:20:07.755238 Dram Type= 6, Freq= 0, CH_1, rank 0
3149 22:20:07.758764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3150 22:20:07.758846 ==
3151 22:20:07.761896 Write leveling (Byte 0): 24 => 24
3152 22:20:07.765415 Write leveling (Byte 1): 27 => 27
3153 22:20:07.768443 DramcWriteLeveling(PI) end<-----
3154 22:20:07.768524
3155 22:20:07.768625 ==
3156 22:20:07.772025 Dram Type= 6, Freq= 0, CH_1, rank 0
3157 22:20:07.775388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 22:20:07.775471 ==
3159 22:20:07.778403 [Gating] SW mode calibration
3160 22:20:07.785094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3161 22:20:07.791623 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3162 22:20:07.795412 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 22:20:07.798676 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 22:20:07.802019 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 22:20:07.808318 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 22:20:07.812095 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 22:20:07.815414 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 22:20:07.821778 0 15 24 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (1 0)
3169 22:20:07.825160 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3170 22:20:07.828221 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 22:20:07.835201 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 22:20:07.838139 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 22:20:07.841852 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 22:20:07.848266 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 22:20:07.851587 1 0 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3176 22:20:07.855073 1 0 24 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
3177 22:20:07.861916 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 22:20:07.864720 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 22:20:07.867950 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 22:20:07.874720 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 22:20:07.878281 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 22:20:07.881512 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 22:20:07.888258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 22:20:07.891474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3185 22:20:07.894764 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3186 22:20:07.901237 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 22:20:07.904649 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 22:20:07.908140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 22:20:07.914834 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 22:20:07.918236 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 22:20:07.921559 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 22:20:07.927888 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 22:20:07.931254 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 22:20:07.934730 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 22:20:07.941041 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 22:20:07.944697 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 22:20:07.948045 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 22:20:07.954563 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:20:07.957953 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3200 22:20:07.960951 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3201 22:20:07.967507 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3202 22:20:07.967590 Total UI for P1: 0, mck2ui 16
3203 22:20:07.970802 best dqsien dly found for B0: ( 1, 3, 22)
3204 22:20:07.977746 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 22:20:07.981227 Total UI for P1: 0, mck2ui 16
3206 22:20:07.984630 best dqsien dly found for B1: ( 1, 3, 26)
3207 22:20:07.987697 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3208 22:20:07.991223 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3209 22:20:07.991305
3210 22:20:07.994486 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3211 22:20:07.997806 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3212 22:20:08.000742 [Gating] SW calibration Done
3213 22:20:08.000861 ==
3214 22:20:08.004523 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 22:20:08.008038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 22:20:08.008121 ==
3217 22:20:08.010753 RX Vref Scan: 0
3218 22:20:08.010836
3219 22:20:08.014208 RX Vref 0 -> 0, step: 1
3220 22:20:08.014290
3221 22:20:08.014356 RX Delay -40 -> 252, step: 8
3222 22:20:08.020532 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3223 22:20:08.024205 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3224 22:20:08.027523 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3225 22:20:08.030552 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3226 22:20:08.034225 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3227 22:20:08.040715 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3228 22:20:08.043957 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3229 22:20:08.047275 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3230 22:20:08.050529 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3231 22:20:08.054130 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3232 22:20:08.060282 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3233 22:20:08.063762 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3234 22:20:08.067056 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3235 22:20:08.070284 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3236 22:20:08.073517 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3237 22:20:08.080134 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3238 22:20:08.080217 ==
3239 22:20:08.083551 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 22:20:08.087215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 22:20:08.087298 ==
3242 22:20:08.087364 DQS Delay:
3243 22:20:08.090154 DQS0 = 0, DQS1 = 0
3244 22:20:08.090242 DQM Delay:
3245 22:20:08.093566 DQM0 = 120, DQM1 = 112
3246 22:20:08.093661 DQ Delay:
3247 22:20:08.096687 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3248 22:20:08.100029 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =123
3249 22:20:08.103708 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3250 22:20:08.106680 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3251 22:20:08.106764
3252 22:20:08.110007
3253 22:20:08.110089 ==
3254 22:20:08.113472 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 22:20:08.116631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 22:20:08.116714 ==
3257 22:20:08.116805
3258 22:20:08.116881
3259 22:20:08.120181 TX Vref Scan disable
3260 22:20:08.120264 == TX Byte 0 ==
3261 22:20:08.126604 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3262 22:20:08.130101 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3263 22:20:08.130184 == TX Byte 1 ==
3264 22:20:08.136890 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3265 22:20:08.140012 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3266 22:20:08.140096 ==
3267 22:20:08.143383 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 22:20:08.146731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 22:20:08.146815 ==
3270 22:20:08.158951 TX Vref=22, minBit 10, minWin=23, winSum=404
3271 22:20:08.162432 TX Vref=24, minBit 1, minWin=25, winSum=409
3272 22:20:08.165537 TX Vref=26, minBit 9, minWin=25, winSum=417
3273 22:20:08.168912 TX Vref=28, minBit 9, minWin=25, winSum=419
3274 22:20:08.172083 TX Vref=30, minBit 11, minWin=25, winSum=422
3275 22:20:08.178638 TX Vref=32, minBit 1, minWin=26, winSum=424
3276 22:20:08.182339 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3277 22:20:08.182423
3278 22:20:08.185266 Final TX Range 1 Vref 32
3279 22:20:08.185348
3280 22:20:08.185413 ==
3281 22:20:08.189060 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 22:20:08.192412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 22:20:08.192495 ==
3284 22:20:08.195660
3285 22:20:08.195742
3286 22:20:08.195807 TX Vref Scan disable
3287 22:20:08.198832 == TX Byte 0 ==
3288 22:20:08.201964 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3289 22:20:08.205375 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3290 22:20:08.208563 == TX Byte 1 ==
3291 22:20:08.212051 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3292 22:20:08.215520 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3293 22:20:08.218694
3294 22:20:08.218776 [DATLAT]
3295 22:20:08.218841 Freq=1200, CH1 RK0
3296 22:20:08.218903
3297 22:20:08.222365 DATLAT Default: 0xd
3298 22:20:08.222448 0, 0xFFFF, sum = 0
3299 22:20:08.225353 1, 0xFFFF, sum = 0
3300 22:20:08.225437 2, 0xFFFF, sum = 0
3301 22:20:08.228568 3, 0xFFFF, sum = 0
3302 22:20:08.232019 4, 0xFFFF, sum = 0
3303 22:20:08.232104 5, 0xFFFF, sum = 0
3304 22:20:08.235235 6, 0xFFFF, sum = 0
3305 22:20:08.235319 7, 0xFFFF, sum = 0
3306 22:20:08.238477 8, 0xFFFF, sum = 0
3307 22:20:08.238561 9, 0xFFFF, sum = 0
3308 22:20:08.242280 10, 0xFFFF, sum = 0
3309 22:20:08.242364 11, 0xFFFF, sum = 0
3310 22:20:08.245333 12, 0x0, sum = 1
3311 22:20:08.245436 13, 0x0, sum = 2
3312 22:20:08.248701 14, 0x0, sum = 3
3313 22:20:08.248823 15, 0x0, sum = 4
3314 22:20:08.251811 best_step = 13
3315 22:20:08.251893
3316 22:20:08.251958 ==
3317 22:20:08.254974 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 22:20:08.258229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 22:20:08.258313 ==
3320 22:20:08.258379 RX Vref Scan: 1
3321 22:20:08.258440
3322 22:20:08.261916 Set Vref Range= 32 -> 127
3323 22:20:08.261998
3324 22:20:08.265143 RX Vref 32 -> 127, step: 1
3325 22:20:08.265225
3326 22:20:08.268642 RX Delay -13 -> 252, step: 4
3327 22:20:08.268725
3328 22:20:08.272019 Set Vref, RX VrefLevel [Byte0]: 32
3329 22:20:08.275284 [Byte1]: 32
3330 22:20:08.275364
3331 22:20:08.278410 Set Vref, RX VrefLevel [Byte0]: 33
3332 22:20:08.281646 [Byte1]: 33
3333 22:20:08.284931
3334 22:20:08.285047 Set Vref, RX VrefLevel [Byte0]: 34
3335 22:20:08.288280 [Byte1]: 34
3336 22:20:08.292992
3337 22:20:08.293078 Set Vref, RX VrefLevel [Byte0]: 35
3338 22:20:08.296557 [Byte1]: 35
3339 22:20:08.300812
3340 22:20:08.300905 Set Vref, RX VrefLevel [Byte0]: 36
3341 22:20:08.304540 [Byte1]: 36
3342 22:20:08.308984
3343 22:20:08.309092 Set Vref, RX VrefLevel [Byte0]: 37
3344 22:20:08.315172 [Byte1]: 37
3345 22:20:08.315293
3346 22:20:08.318777 Set Vref, RX VrefLevel [Byte0]: 38
3347 22:20:08.321773 [Byte1]: 38
3348 22:20:08.321859
3349 22:20:08.325815 Set Vref, RX VrefLevel [Byte0]: 39
3350 22:20:08.328552 [Byte1]: 39
3351 22:20:08.332535
3352 22:20:08.332615 Set Vref, RX VrefLevel [Byte0]: 40
3353 22:20:08.335641 [Byte1]: 40
3354 22:20:08.340049
3355 22:20:08.340143 Set Vref, RX VrefLevel [Byte0]: 41
3356 22:20:08.344328 [Byte1]: 41
3357 22:20:08.348309
3358 22:20:08.348391 Set Vref, RX VrefLevel [Byte0]: 42
3359 22:20:08.351742 [Byte1]: 42
3360 22:20:08.356098
3361 22:20:08.356178 Set Vref, RX VrefLevel [Byte0]: 43
3362 22:20:08.359210 [Byte1]: 43
3363 22:20:08.363955
3364 22:20:08.364037 Set Vref, RX VrefLevel [Byte0]: 44
3365 22:20:08.367105 [Byte1]: 44
3366 22:20:08.372183
3367 22:20:08.372265 Set Vref, RX VrefLevel [Byte0]: 45
3368 22:20:08.375235 [Byte1]: 45
3369 22:20:08.379646
3370 22:20:08.379727 Set Vref, RX VrefLevel [Byte0]: 46
3371 22:20:08.383230 [Byte1]: 46
3372 22:20:08.387633
3373 22:20:08.387713 Set Vref, RX VrefLevel [Byte0]: 47
3374 22:20:08.390806 [Byte1]: 47
3375 22:20:08.395368
3376 22:20:08.395449 Set Vref, RX VrefLevel [Byte0]: 48
3377 22:20:08.399201 [Byte1]: 48
3378 22:20:08.403384
3379 22:20:08.403464 Set Vref, RX VrefLevel [Byte0]: 49
3380 22:20:08.406455 [Byte1]: 49
3381 22:20:08.411324
3382 22:20:08.414666 Set Vref, RX VrefLevel [Byte0]: 50
3383 22:20:08.415121 [Byte1]: 50
3384 22:20:08.419359
3385 22:20:08.419812 Set Vref, RX VrefLevel [Byte0]: 51
3386 22:20:08.423071 [Byte1]: 51
3387 22:20:08.427323
3388 22:20:08.427736 Set Vref, RX VrefLevel [Byte0]: 52
3389 22:20:08.430488 [Byte1]: 52
3390 22:20:08.435429
3391 22:20:08.435837 Set Vref, RX VrefLevel [Byte0]: 53
3392 22:20:08.438487 [Byte1]: 53
3393 22:20:08.442875
3394 22:20:08.443328 Set Vref, RX VrefLevel [Byte0]: 54
3395 22:20:08.446489 [Byte1]: 54
3396 22:20:08.451184
3397 22:20:08.451640 Set Vref, RX VrefLevel [Byte0]: 55
3398 22:20:08.453947 [Byte1]: 55
3399 22:20:08.458527
3400 22:20:08.458611 Set Vref, RX VrefLevel [Byte0]: 56
3401 22:20:08.462057 [Byte1]: 56
3402 22:20:08.466445
3403 22:20:08.466533 Set Vref, RX VrefLevel [Byte0]: 57
3404 22:20:08.469538 [Byte1]: 57
3405 22:20:08.474191
3406 22:20:08.474294 Set Vref, RX VrefLevel [Byte0]: 58
3407 22:20:08.480802 [Byte1]: 58
3408 22:20:08.480914
3409 22:20:08.484021 Set Vref, RX VrefLevel [Byte0]: 59
3410 22:20:08.487417 [Byte1]: 59
3411 22:20:08.487541
3412 22:20:08.490637 Set Vref, RX VrefLevel [Byte0]: 60
3413 22:20:08.493958 [Byte1]: 60
3414 22:20:08.498163
3415 22:20:08.498338 Set Vref, RX VrefLevel [Byte0]: 61
3416 22:20:08.501541 [Byte1]: 61
3417 22:20:08.505941
3418 22:20:08.506115 Set Vref, RX VrefLevel [Byte0]: 62
3419 22:20:08.509136 [Byte1]: 62
3420 22:20:08.514070
3421 22:20:08.514272 Set Vref, RX VrefLevel [Byte0]: 63
3422 22:20:08.517194 [Byte1]: 63
3423 22:20:08.522161
3424 22:20:08.522402 Set Vref, RX VrefLevel [Byte0]: 64
3425 22:20:08.525380 [Byte1]: 64
3426 22:20:08.529962
3427 22:20:08.530349 Set Vref, RX VrefLevel [Byte0]: 65
3428 22:20:08.533313 [Byte1]: 65
3429 22:20:08.537655
3430 22:20:08.538078 Set Vref, RX VrefLevel [Byte0]: 66
3431 22:20:08.541011 [Byte1]: 66
3432 22:20:08.545771
3433 22:20:08.546234 Set Vref, RX VrefLevel [Byte0]: 67
3434 22:20:08.548840 [Byte1]: 67
3435 22:20:08.553586
3436 22:20:08.554007 Final RX Vref Byte 0 = 53 to rank0
3437 22:20:08.556724 Final RX Vref Byte 1 = 53 to rank0
3438 22:20:08.559985 Final RX Vref Byte 0 = 53 to rank1
3439 22:20:08.563560 Final RX Vref Byte 1 = 53 to rank1==
3440 22:20:08.566971 Dram Type= 6, Freq= 0, CH_1, rank 0
3441 22:20:08.573682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 22:20:08.574124 ==
3443 22:20:08.574481 DQS Delay:
3444 22:20:08.574818 DQS0 = 0, DQS1 = 0
3445 22:20:08.576815 DQM Delay:
3446 22:20:08.577189 DQM0 = 119, DQM1 = 112
3447 22:20:08.579886 DQ Delay:
3448 22:20:08.583121 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3449 22:20:08.586709 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3450 22:20:08.590024 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3451 22:20:08.593091 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3452 22:20:08.593160
3453 22:20:08.593220
3454 22:20:08.599616 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3455 22:20:08.602996 CH1 RK0: MR19=404, MR18=114
3456 22:20:08.609794 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3457 22:20:08.609874
3458 22:20:08.612941 ----->DramcWriteLeveling(PI) begin...
3459 22:20:08.613013 ==
3460 22:20:08.616294 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 22:20:08.619466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 22:20:08.623079 ==
3463 22:20:08.623151 Write leveling (Byte 0): 25 => 25
3464 22:20:08.626195 Write leveling (Byte 1): 29 => 29
3465 22:20:08.629505 DramcWriteLeveling(PI) end<-----
3466 22:20:08.629573
3467 22:20:08.629634 ==
3468 22:20:08.632981 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 22:20:08.639631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 22:20:08.639702 ==
3471 22:20:08.642748 [Gating] SW mode calibration
3472 22:20:08.649267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3473 22:20:08.652640 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3474 22:20:08.659422 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 22:20:08.663624 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 22:20:08.666329 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 22:20:08.673059 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 22:20:08.675891 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 22:20:08.678945 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 22:20:08.685888 0 15 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 0)
3481 22:20:08.689246 0 15 28 | B1->B0 | 2323 2f2f | 0 0 | (1 0) (0 0)
3482 22:20:08.692324 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 22:20:08.698949 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 22:20:08.702280 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 22:20:08.705647 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 22:20:08.712031 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 22:20:08.715438 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 22:20:08.719011 1 0 24 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
3489 22:20:08.725328 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3490 22:20:08.728796 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 22:20:08.732005 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 22:20:08.735279 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 22:20:08.741995 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 22:20:08.745034 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 22:20:08.751757 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 22:20:08.754789 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3497 22:20:08.758501 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3498 22:20:08.765052 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:20:08.768612 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:20:08.771952 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:20:08.777819 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:20:08.781079 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 22:20:08.784715 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 22:20:08.791160 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 22:20:08.794448 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 22:20:08.797660 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 22:20:08.804256 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 22:20:08.807693 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 22:20:08.810712 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 22:20:08.817724 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 22:20:08.820503 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 22:20:08.824245 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 22:20:08.830497 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3514 22:20:08.834076 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 22:20:08.836984 Total UI for P1: 0, mck2ui 16
3516 22:20:08.840304 best dqsien dly found for B0: ( 1, 3, 26)
3517 22:20:08.843640 Total UI for P1: 0, mck2ui 16
3518 22:20:08.846965 best dqsien dly found for B1: ( 1, 3, 26)
3519 22:20:08.850382 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3520 22:20:08.853632 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3521 22:20:08.853726
3522 22:20:08.856799 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3523 22:20:08.860162 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3524 22:20:08.863696 [Gating] SW calibration Done
3525 22:20:08.863779 ==
3526 22:20:08.866716 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 22:20:08.870116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 22:20:08.873652 ==
3529 22:20:08.873723 RX Vref Scan: 0
3530 22:20:08.873786
3531 22:20:08.876747 RX Vref 0 -> 0, step: 1
3532 22:20:08.876850
3533 22:20:08.880205 RX Delay -40 -> 252, step: 8
3534 22:20:08.883609 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3535 22:20:08.886646 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3536 22:20:08.889963 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3537 22:20:08.893060 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3538 22:20:08.899715 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3539 22:20:08.903255 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3540 22:20:08.906236 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3541 22:20:08.909978 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3542 22:20:08.913061 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3543 22:20:08.919959 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3544 22:20:08.922866 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3545 22:20:08.926166 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3546 22:20:08.929744 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3547 22:20:08.932914 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3548 22:20:08.939690 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3549 22:20:08.943210 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3550 22:20:08.943308 ==
3551 22:20:08.946251 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 22:20:08.949767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 22:20:08.949838 ==
3554 22:20:08.952561 DQS Delay:
3555 22:20:08.952648 DQS0 = 0, DQS1 = 0
3556 22:20:08.952736 DQM Delay:
3557 22:20:08.956062 DQM0 = 121, DQM1 = 113
3558 22:20:08.956133 DQ Delay:
3559 22:20:08.959293 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3560 22:20:08.962583 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3561 22:20:08.969177 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3562 22:20:08.972545 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3563 22:20:08.972648
3564 22:20:08.972740
3565 22:20:08.972852 ==
3566 22:20:08.975872 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 22:20:08.979114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 22:20:08.979188 ==
3569 22:20:08.979250
3570 22:20:08.979308
3571 22:20:08.982427 TX Vref Scan disable
3572 22:20:08.985965 == TX Byte 0 ==
3573 22:20:08.988966 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3574 22:20:08.992471 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3575 22:20:08.995362 == TX Byte 1 ==
3576 22:20:08.998937 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3577 22:20:09.002360 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3578 22:20:09.002433 ==
3579 22:20:09.005758 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 22:20:09.008558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 22:20:09.011892 ==
3582 22:20:09.022048 TX Vref=22, minBit 1, minWin=25, winSum=420
3583 22:20:09.025256 TX Vref=24, minBit 1, minWin=26, winSum=423
3584 22:20:09.028967 TX Vref=26, minBit 1, minWin=26, winSum=427
3585 22:20:09.032192 TX Vref=28, minBit 1, minWin=26, winSum=427
3586 22:20:09.035420 TX Vref=30, minBit 1, minWin=26, winSum=431
3587 22:20:09.041943 TX Vref=32, minBit 1, minWin=26, winSum=429
3588 22:20:09.045402 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3589 22:20:09.045476
3590 22:20:09.048561 Final TX Range 1 Vref 30
3591 22:20:09.048658
3592 22:20:09.048745 ==
3593 22:20:09.051823 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 22:20:09.055176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 22:20:09.058620 ==
3596 22:20:09.058692
3597 22:20:09.058752
3598 22:20:09.058810 TX Vref Scan disable
3599 22:20:09.061734 == TX Byte 0 ==
3600 22:20:09.065400 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 22:20:09.071757 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 22:20:09.071857 == TX Byte 1 ==
3603 22:20:09.075057 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3604 22:20:09.081495 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3605 22:20:09.081595
3606 22:20:09.081686 [DATLAT]
3607 22:20:09.081773 Freq=1200, CH1 RK1
3608 22:20:09.081860
3609 22:20:09.085036 DATLAT Default: 0xd
3610 22:20:09.088148 0, 0xFFFF, sum = 0
3611 22:20:09.088225 1, 0xFFFF, sum = 0
3612 22:20:09.091642 2, 0xFFFF, sum = 0
3613 22:20:09.091742 3, 0xFFFF, sum = 0
3614 22:20:09.094855 4, 0xFFFF, sum = 0
3615 22:20:09.094953 5, 0xFFFF, sum = 0
3616 22:20:09.097919 6, 0xFFFF, sum = 0
3617 22:20:09.097991 7, 0xFFFF, sum = 0
3618 22:20:09.101511 8, 0xFFFF, sum = 0
3619 22:20:09.101583 9, 0xFFFF, sum = 0
3620 22:20:09.104616 10, 0xFFFF, sum = 0
3621 22:20:09.104719 11, 0xFFFF, sum = 0
3622 22:20:09.108066 12, 0x0, sum = 1
3623 22:20:09.108138 13, 0x0, sum = 2
3624 22:20:09.111261 14, 0x0, sum = 3
3625 22:20:09.111359 15, 0x0, sum = 4
3626 22:20:09.114870 best_step = 13
3627 22:20:09.114942
3628 22:20:09.115001 ==
3629 22:20:09.117951 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 22:20:09.121185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 22:20:09.121271 ==
3632 22:20:09.124338 RX Vref Scan: 0
3633 22:20:09.124435
3634 22:20:09.124524 RX Vref 0 -> 0, step: 1
3635 22:20:09.124610
3636 22:20:09.127792 RX Delay -13 -> 252, step: 4
3637 22:20:09.134126 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3638 22:20:09.137632 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3639 22:20:09.140934 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3640 22:20:09.144443 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3641 22:20:09.147371 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3642 22:20:09.154282 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3643 22:20:09.157500 iDelay=195, Bit 6, Center 128 (67 ~ 190) 124
3644 22:20:09.160564 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3645 22:20:09.163919 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3646 22:20:09.167462 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3647 22:20:09.173893 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3648 22:20:09.177289 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3649 22:20:09.180519 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3650 22:20:09.183855 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3651 22:20:09.190782 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3652 22:20:09.193585 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3653 22:20:09.193685 ==
3654 22:20:09.197174 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 22:20:09.200184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 22:20:09.200282 ==
3657 22:20:09.203739 DQS Delay:
3658 22:20:09.203817 DQS0 = 0, DQS1 = 0
3659 22:20:09.203906 DQM Delay:
3660 22:20:09.206885 DQM0 = 119, DQM1 = 113
3661 22:20:09.206959 DQ Delay:
3662 22:20:09.210340 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3663 22:20:09.213711 DQ4 =122, DQ5 =130, DQ6 =128, DQ7 =116
3664 22:20:09.216806 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3665 22:20:09.223515 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3666 22:20:09.223615
3667 22:20:09.223706
3668 22:20:09.230197 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3669 22:20:09.233644 CH1 RK1: MR19=403, MR18=7EC
3670 22:20:09.239992 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3671 22:20:09.243234 [RxdqsGatingPostProcess] freq 1200
3672 22:20:09.246762 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3673 22:20:09.249685 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 22:20:09.253138 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 22:20:09.256239 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 22:20:09.259671 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 22:20:09.262940 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 22:20:09.266440 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 22:20:09.269531 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 22:20:09.272856 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 22:20:09.275999 Pre-setting of DQS Precalculation
3682 22:20:09.279516 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3683 22:20:09.289288 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3684 22:20:09.296198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3685 22:20:09.296278
3686 22:20:09.296342
3687 22:20:09.299265 [Calibration Summary] 2400 Mbps
3688 22:20:09.299364 CH 0, Rank 0
3689 22:20:09.302749 SW Impedance : PASS
3690 22:20:09.302846 DUTY Scan : NO K
3691 22:20:09.305644 ZQ Calibration : PASS
3692 22:20:09.309139 Jitter Meter : NO K
3693 22:20:09.309236 CBT Training : PASS
3694 22:20:09.312271 Write leveling : PASS
3695 22:20:09.315570 RX DQS gating : PASS
3696 22:20:09.315669 RX DQ/DQS(RDDQC) : PASS
3697 22:20:09.318984 TX DQ/DQS : PASS
3698 22:20:09.322340 RX DATLAT : PASS
3699 22:20:09.322413 RX DQ/DQS(Engine): PASS
3700 22:20:09.325687 TX OE : NO K
3701 22:20:09.325757 All Pass.
3702 22:20:09.325822
3703 22:20:09.329188 CH 0, Rank 1
3704 22:20:09.329286 SW Impedance : PASS
3705 22:20:09.332026 DUTY Scan : NO K
3706 22:20:09.335455 ZQ Calibration : PASS
3707 22:20:09.335555 Jitter Meter : NO K
3708 22:20:09.338836 CBT Training : PASS
3709 22:20:09.342311 Write leveling : PASS
3710 22:20:09.342408 RX DQS gating : PASS
3711 22:20:09.345501 RX DQ/DQS(RDDQC) : PASS
3712 22:20:09.348478 TX DQ/DQS : PASS
3713 22:20:09.348547 RX DATLAT : PASS
3714 22:20:09.352057 RX DQ/DQS(Engine): PASS
3715 22:20:09.355168 TX OE : NO K
3716 22:20:09.355267 All Pass.
3717 22:20:09.355355
3718 22:20:09.355442 CH 1, Rank 0
3719 22:20:09.358647 SW Impedance : PASS
3720 22:20:09.362089 DUTY Scan : NO K
3721 22:20:09.362160 ZQ Calibration : PASS
3722 22:20:09.365405 Jitter Meter : NO K
3723 22:20:09.365476 CBT Training : PASS
3724 22:20:09.368485 Write leveling : PASS
3725 22:20:09.371539 RX DQS gating : PASS
3726 22:20:09.371609 RX DQ/DQS(RDDQC) : PASS
3727 22:20:09.375108 TX DQ/DQS : PASS
3728 22:20:09.378654 RX DATLAT : PASS
3729 22:20:09.378724 RX DQ/DQS(Engine): PASS
3730 22:20:09.381923 TX OE : NO K
3731 22:20:09.382020 All Pass.
3732 22:20:09.382110
3733 22:20:09.384986 CH 1, Rank 1
3734 22:20:09.385084 SW Impedance : PASS
3735 22:20:09.388566 DUTY Scan : NO K
3736 22:20:09.391573 ZQ Calibration : PASS
3737 22:20:09.391671 Jitter Meter : NO K
3738 22:20:09.394992 CBT Training : PASS
3739 22:20:09.398028 Write leveling : PASS
3740 22:20:09.398127 RX DQS gating : PASS
3741 22:20:09.401449 RX DQ/DQS(RDDQC) : PASS
3742 22:20:09.405114 TX DQ/DQS : PASS
3743 22:20:09.405188 RX DATLAT : PASS
3744 22:20:09.408130 RX DQ/DQS(Engine): PASS
3745 22:20:09.411415 TX OE : NO K
3746 22:20:09.411489 All Pass.
3747 22:20:09.411551
3748 22:20:09.411610 DramC Write-DBI off
3749 22:20:09.414825 PER_BANK_REFRESH: Hybrid Mode
3750 22:20:09.418213 TX_TRACKING: ON
3751 22:20:09.424526 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3752 22:20:09.428039 [FAST_K] Save calibration result to emmc
3753 22:20:09.434617 dramc_set_vcore_voltage set vcore to 650000
3754 22:20:09.434719 Read voltage for 600, 5
3755 22:20:09.438015 Vio18 = 0
3756 22:20:09.438091 Vcore = 650000
3757 22:20:09.438157 Vdram = 0
3758 22:20:09.441287 Vddq = 0
3759 22:20:09.441358 Vmddr = 0
3760 22:20:09.444319 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3761 22:20:09.451194 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3762 22:20:09.454221 MEM_TYPE=3, freq_sel=19
3763 22:20:09.457754 sv_algorithm_assistance_LP4_1600
3764 22:20:09.461041 ============ PULL DRAM RESETB DOWN ============
3765 22:20:09.464116 ========== PULL DRAM RESETB DOWN end =========
3766 22:20:09.470581 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3767 22:20:09.474081 ===================================
3768 22:20:09.474154 LPDDR4 DRAM CONFIGURATION
3769 22:20:09.477468 ===================================
3770 22:20:09.480947 EX_ROW_EN[0] = 0x0
3771 22:20:09.481044 EX_ROW_EN[1] = 0x0
3772 22:20:09.483813 LP4Y_EN = 0x0
3773 22:20:09.483908 WORK_FSP = 0x0
3774 22:20:09.487222 WL = 0x2
3775 22:20:09.490628 RL = 0x2
3776 22:20:09.490728 BL = 0x2
3777 22:20:09.493824 RPST = 0x0
3778 22:20:09.493920 RD_PRE = 0x0
3779 22:20:09.497140 WR_PRE = 0x1
3780 22:20:09.497211 WR_PST = 0x0
3781 22:20:09.500555 DBI_WR = 0x0
3782 22:20:09.500654 DBI_RD = 0x0
3783 22:20:09.504030 OTF = 0x1
3784 22:20:09.507031 ===================================
3785 22:20:09.510359 ===================================
3786 22:20:09.510458 ANA top config
3787 22:20:09.513785 ===================================
3788 22:20:09.517095 DLL_ASYNC_EN = 0
3789 22:20:09.520190 ALL_SLAVE_EN = 1
3790 22:20:09.520287 NEW_RANK_MODE = 1
3791 22:20:09.523494 DLL_IDLE_MODE = 1
3792 22:20:09.526837 LP45_APHY_COMB_EN = 1
3793 22:20:09.530309 TX_ODT_DIS = 1
3794 22:20:09.533406 NEW_8X_MODE = 1
3795 22:20:09.536642 ===================================
3796 22:20:09.540195 ===================================
3797 22:20:09.540268 data_rate = 1200
3798 22:20:09.543822 CKR = 1
3799 22:20:09.546888 DQ_P2S_RATIO = 8
3800 22:20:09.549738 ===================================
3801 22:20:09.553312 CA_P2S_RATIO = 8
3802 22:20:09.556572 DQ_CA_OPEN = 0
3803 22:20:09.559885 DQ_SEMI_OPEN = 0
3804 22:20:09.559957 CA_SEMI_OPEN = 0
3805 22:20:09.563145 CA_FULL_RATE = 0
3806 22:20:09.566681 DQ_CKDIV4_EN = 1
3807 22:20:09.571184 CA_CKDIV4_EN = 1
3808 22:20:09.573503 CA_PREDIV_EN = 0
3809 22:20:09.576593 PH8_DLY = 0
3810 22:20:09.576735 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3811 22:20:09.579948 DQ_AAMCK_DIV = 4
3812 22:20:09.582976 CA_AAMCK_DIV = 4
3813 22:20:09.586251 CA_ADMCK_DIV = 4
3814 22:20:09.589693 DQ_TRACK_CA_EN = 0
3815 22:20:09.593064 CA_PICK = 600
3816 22:20:09.596549 CA_MCKIO = 600
3817 22:20:09.596700 MCKIO_SEMI = 0
3818 22:20:09.599974 PLL_FREQ = 2288
3819 22:20:09.624255 DQ_UI_PI_RATIO = 32
3820 22:20:09.624392 CA_UI_PI_RATIO = 0
3821 22:20:09.624465 ===================================
3822 22:20:09.624529 ===================================
3823 22:20:09.624589 memory_type:LPDDR4
3824 22:20:09.624649 GP_NUM : 10
3825 22:20:09.624706 SRAM_EN : 1
3826 22:20:09.624762 MD32_EN : 0
3827 22:20:09.625685 ===================================
3828 22:20:09.625770 [ANA_INIT] >>>>>>>>>>>>>>
3829 22:20:09.629181 <<<<<< [CONFIGURE PHASE]: ANA_TX
3830 22:20:09.632416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3831 22:20:09.635684 ===================================
3832 22:20:09.639102 data_rate = 1200,PCW = 0X5800
3833 22:20:09.642353 ===================================
3834 22:20:09.645660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3835 22:20:09.652388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 22:20:09.655843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 22:20:09.662074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3838 22:20:09.665553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3839 22:20:09.668912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3840 22:20:09.672056 [ANA_INIT] flow start
3841 22:20:09.672138 [ANA_INIT] PLL >>>>>>>>
3842 22:20:09.675585 [ANA_INIT] PLL <<<<<<<<
3843 22:20:09.678974 [ANA_INIT] MIDPI >>>>>>>>
3844 22:20:09.679057 [ANA_INIT] MIDPI <<<<<<<<
3845 22:20:09.681865 [ANA_INIT] DLL >>>>>>>>
3846 22:20:09.685227 [ANA_INIT] flow end
3847 22:20:09.688516 ============ LP4 DIFF to SE enter ============
3848 22:20:09.691970 ============ LP4 DIFF to SE exit ============
3849 22:20:09.695389 [ANA_INIT] <<<<<<<<<<<<<
3850 22:20:09.698278 [Flow] Enable top DCM control >>>>>
3851 22:20:09.701599 [Flow] Enable top DCM control <<<<<
3852 22:20:09.705382 Enable DLL master slave shuffle
3853 22:20:09.708406 ==============================================================
3854 22:20:09.711815 Gating Mode config
3855 22:20:09.718271 ==============================================================
3856 22:20:09.718355 Config description:
3857 22:20:09.728102 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3858 22:20:09.734581 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3859 22:20:09.741264 SELPH_MODE 0: By rank 1: By Phase
3860 22:20:09.744426 ==============================================================
3861 22:20:09.747902 GAT_TRACK_EN = 1
3862 22:20:09.750929 RX_GATING_MODE = 2
3863 22:20:09.754497 RX_GATING_TRACK_MODE = 2
3864 22:20:09.757809 SELPH_MODE = 1
3865 22:20:09.761115 PICG_EARLY_EN = 1
3866 22:20:09.764484 VALID_LAT_VALUE = 1
3867 22:20:09.768017 ==============================================================
3868 22:20:09.771035 Enter into Gating configuration >>>>
3869 22:20:09.774494 Exit from Gating configuration <<<<
3870 22:20:09.777432 Enter into DVFS_PRE_config >>>>>
3871 22:20:09.790842 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3872 22:20:09.794309 Exit from DVFS_PRE_config <<<<<
3873 22:20:09.797876 Enter into PICG configuration >>>>
3874 22:20:09.800616 Exit from PICG configuration <<<<
3875 22:20:09.800697 [RX_INPUT] configuration >>>>>
3876 22:20:09.804029 [RX_INPUT] configuration <<<<<
3877 22:20:09.810895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3878 22:20:09.813864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3879 22:20:09.820528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 22:20:09.827326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 22:20:09.834254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 22:20:09.840598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 22:20:09.843695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3884 22:20:09.847070 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3885 22:20:09.853534 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3886 22:20:09.857103 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3887 22:20:09.860095 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3888 22:20:09.863632 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 22:20:09.867213 ===================================
3890 22:20:09.870132 LPDDR4 DRAM CONFIGURATION
3891 22:20:09.873671 ===================================
3892 22:20:09.877077 EX_ROW_EN[0] = 0x0
3893 22:20:09.877158 EX_ROW_EN[1] = 0x0
3894 22:20:09.880447 LP4Y_EN = 0x0
3895 22:20:09.880528 WORK_FSP = 0x0
3896 22:20:09.883475 WL = 0x2
3897 22:20:09.883557 RL = 0x2
3898 22:20:09.887069 BL = 0x2
3899 22:20:09.887150 RPST = 0x0
3900 22:20:09.890163 RD_PRE = 0x0
3901 22:20:09.890245 WR_PRE = 0x1
3902 22:20:09.893405 WR_PST = 0x0
3903 22:20:09.897126 DBI_WR = 0x0
3904 22:20:09.897207 DBI_RD = 0x0
3905 22:20:09.899986 OTF = 0x1
3906 22:20:09.903544 ===================================
3907 22:20:09.906709 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3908 22:20:09.910152 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3909 22:20:09.913434 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 22:20:09.916590 ===================================
3911 22:20:09.920156 LPDDR4 DRAM CONFIGURATION
3912 22:20:09.923276 ===================================
3913 22:20:09.926564 EX_ROW_EN[0] = 0x10
3914 22:20:09.926642 EX_ROW_EN[1] = 0x0
3915 22:20:09.929928 LP4Y_EN = 0x0
3916 22:20:09.930021 WORK_FSP = 0x0
3917 22:20:09.933190 WL = 0x2
3918 22:20:09.933308 RL = 0x2
3919 22:20:09.936903 BL = 0x2
3920 22:20:09.936983 RPST = 0x0
3921 22:20:09.939850 RD_PRE = 0x0
3922 22:20:09.939924 WR_PRE = 0x1
3923 22:20:09.942823 WR_PST = 0x0
3924 22:20:09.946316 DBI_WR = 0x0
3925 22:20:09.946420 DBI_RD = 0x0
3926 22:20:09.949589 OTF = 0x1
3927 22:20:09.952851 ===================================
3928 22:20:09.956175 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3929 22:20:09.961560 nWR fixed to 30
3930 22:20:09.964929 [ModeRegInit_LP4] CH0 RK0
3931 22:20:09.965003 [ModeRegInit_LP4] CH0 RK1
3932 22:20:09.967964 [ModeRegInit_LP4] CH1 RK0
3933 22:20:09.971551 [ModeRegInit_LP4] CH1 RK1
3934 22:20:09.971623 match AC timing 17
3935 22:20:09.978070 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3936 22:20:09.981273 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3937 22:20:09.984589 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3938 22:20:09.991433 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3939 22:20:09.994479 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3940 22:20:09.994557 ==
3941 22:20:09.997863 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 22:20:10.001093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 22:20:10.001164 ==
3944 22:20:10.007670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 22:20:10.014554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3946 22:20:10.017751 [CA 0] Center 36 (6~67) winsize 62
3947 22:20:10.021191 [CA 1] Center 36 (6~67) winsize 62
3948 22:20:10.024233 [CA 2] Center 34 (4~65) winsize 62
3949 22:20:10.027975 [CA 3] Center 34 (3~65) winsize 63
3950 22:20:10.030696 [CA 4] Center 33 (3~64) winsize 62
3951 22:20:10.033926 [CA 5] Center 33 (3~64) winsize 62
3952 22:20:10.034003
3953 22:20:10.037569 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3954 22:20:10.037645
3955 22:20:10.040882 [CATrainingPosCal] consider 1 rank data
3956 22:20:10.044163 u2DelayCellTimex100 = 270/100 ps
3957 22:20:10.047508 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 22:20:10.050705 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 22:20:10.054170 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 22:20:10.057189 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3961 22:20:10.064165 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 22:20:10.067149 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 22:20:10.067230
3964 22:20:10.070847 CA PerBit enable=1, Macro0, CA PI delay=33
3965 22:20:10.070932
3966 22:20:10.073885 [CBTSetCACLKResult] CA Dly = 33
3967 22:20:10.073958 CS Dly: 5 (0~36)
3968 22:20:10.074019 ==
3969 22:20:10.077521 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 22:20:10.083989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 22:20:10.084074 ==
3972 22:20:10.087105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 22:20:10.093487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3974 22:20:10.097062 [CA 0] Center 36 (6~67) winsize 62
3975 22:20:10.100490 [CA 1] Center 36 (6~67) winsize 62
3976 22:20:10.103475 [CA 2] Center 35 (4~66) winsize 63
3977 22:20:10.107005 [CA 3] Center 35 (4~66) winsize 63
3978 22:20:10.110237 [CA 4] Center 34 (3~65) winsize 63
3979 22:20:10.113470 [CA 5] Center 34 (3~65) winsize 63
3980 22:20:10.113552
3981 22:20:10.116977 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3982 22:20:10.117060
3983 22:20:10.120285 [CATrainingPosCal] consider 2 rank data
3984 22:20:10.123703 u2DelayCellTimex100 = 270/100 ps
3985 22:20:10.126803 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3986 22:20:10.133331 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3987 22:20:10.136451 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 22:20:10.139951 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 22:20:10.143388 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 22:20:10.146173 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 22:20:10.146256
3992 22:20:10.149517 CA PerBit enable=1, Macro0, CA PI delay=33
3993 22:20:10.149599
3994 22:20:10.153300 [CBTSetCACLKResult] CA Dly = 33
3995 22:20:10.156345 CS Dly: 5 (0~36)
3996 22:20:10.156427
3997 22:20:10.159446 ----->DramcWriteLeveling(PI) begin...
3998 22:20:10.159531 ==
3999 22:20:10.162829 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 22:20:10.166128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 22:20:10.166212 ==
4002 22:20:10.169542 Write leveling (Byte 0): 33 => 33
4003 22:20:10.172718 Write leveling (Byte 1): 29 => 29
4004 22:20:10.176018 DramcWriteLeveling(PI) end<-----
4005 22:20:10.176100
4006 22:20:10.176163 ==
4007 22:20:10.179230 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 22:20:10.182641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 22:20:10.182723 ==
4010 22:20:10.186098 [Gating] SW mode calibration
4011 22:20:10.192335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4012 22:20:10.198913 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4013 22:20:10.202325 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 22:20:10.205410 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 22:20:10.212367 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 22:20:10.215580 0 9 12 | B1->B0 | 3232 3030 | 1 1 | (1 0) (0 1)
4017 22:20:10.218624 0 9 16 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
4018 22:20:10.225303 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 22:20:10.228331 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 22:20:10.235263 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 22:20:10.238187 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 22:20:10.241599 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 22:20:10.248330 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4024 22:20:10.251787 0 10 12 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (0 0)
4025 22:20:10.255017 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4026 22:20:10.258628 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 22:20:10.264911 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 22:20:10.268018 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 22:20:10.271633 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 22:20:10.278056 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 22:20:10.281409 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 22:20:10.284744 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4033 22:20:10.291458 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4034 22:20:10.294594 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:20:10.298002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:20:10.304490 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:20:10.307745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:20:10.310861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 22:20:10.317509 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 22:20:10.321224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 22:20:10.324311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 22:20:10.330708 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 22:20:10.334171 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 22:20:10.340603 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 22:20:10.343653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 22:20:10.346958 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 22:20:10.353849 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 22:20:10.356859 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4049 22:20:10.360125 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 22:20:10.363591 Total UI for P1: 0, mck2ui 16
4051 22:20:10.366921 best dqsien dly found for B0: ( 0, 13, 12)
4052 22:20:10.370031 Total UI for P1: 0, mck2ui 16
4053 22:20:10.373694 best dqsien dly found for B1: ( 0, 13, 14)
4054 22:20:10.376655 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4055 22:20:10.380204 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4056 22:20:10.380283
4057 22:20:10.383576 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4058 22:20:10.389943 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4059 22:20:10.390019 [Gating] SW calibration Done
4060 22:20:10.393388 ==
4061 22:20:10.393460 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 22:20:10.399774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 22:20:10.399875 ==
4064 22:20:10.399967 RX Vref Scan: 0
4065 22:20:10.400053
4066 22:20:10.403351 RX Vref 0 -> 0, step: 1
4067 22:20:10.403421
4068 22:20:10.406547 RX Delay -230 -> 252, step: 16
4069 22:20:10.409644 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4070 22:20:10.413033 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4071 22:20:10.419792 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4072 22:20:10.422861 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4073 22:20:10.426338 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4074 22:20:10.429803 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4075 22:20:10.432677 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4076 22:20:10.439394 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4077 22:20:10.442652 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4078 22:20:10.446060 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4079 22:20:10.449586 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4080 22:20:10.456051 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4081 22:20:10.458974 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4082 22:20:10.462297 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4083 22:20:10.465756 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4084 22:20:10.472370 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4085 22:20:10.472473 ==
4086 22:20:10.475855 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 22:20:10.479110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 22:20:10.479185 ==
4089 22:20:10.479246 DQS Delay:
4090 22:20:10.482146 DQS0 = 0, DQS1 = 0
4091 22:20:10.482216 DQM Delay:
4092 22:20:10.485826 DQM0 = 51, DQM1 = 39
4093 22:20:10.485896 DQ Delay:
4094 22:20:10.488843 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4095 22:20:10.492094 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4096 22:20:10.495398 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4097 22:20:10.498708 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4098 22:20:10.498781
4099 22:20:10.498840
4100 22:20:10.498898 ==
4101 22:20:10.502357 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 22:20:10.508421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 22:20:10.508545 ==
4104 22:20:10.508653
4105 22:20:10.508757
4106 22:20:10.508873 TX Vref Scan disable
4107 22:20:10.512069 == TX Byte 0 ==
4108 22:20:10.515418 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4109 22:20:10.521784 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4110 22:20:10.521886 == TX Byte 1 ==
4111 22:20:10.525279 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4112 22:20:10.531698 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4113 22:20:10.531798 ==
4114 22:20:10.535099 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 22:20:10.538531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 22:20:10.538629 ==
4117 22:20:10.538721
4118 22:20:10.538808
4119 22:20:10.541960 TX Vref Scan disable
4120 22:20:10.545435 == TX Byte 0 ==
4121 22:20:10.548330 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4122 22:20:10.551701 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4123 22:20:10.555011 == TX Byte 1 ==
4124 22:20:10.558464 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4125 22:20:10.561560 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4126 22:20:10.561635
4127 22:20:10.561696 [DATLAT]
4128 22:20:10.564982 Freq=600, CH0 RK0
4129 22:20:10.565072
4130 22:20:10.568262 DATLAT Default: 0x9
4131 22:20:10.568344 0, 0xFFFF, sum = 0
4132 22:20:10.571416 1, 0xFFFF, sum = 0
4133 22:20:10.571500 2, 0xFFFF, sum = 0
4134 22:20:10.575045 3, 0xFFFF, sum = 0
4135 22:20:10.575128 4, 0xFFFF, sum = 0
4136 22:20:10.578343 5, 0xFFFF, sum = 0
4137 22:20:10.578426 6, 0xFFFF, sum = 0
4138 22:20:10.581298 7, 0xFFFF, sum = 0
4139 22:20:10.581381 8, 0x0, sum = 1
4140 22:20:10.584578 9, 0x0, sum = 2
4141 22:20:10.584662 10, 0x0, sum = 3
4142 22:20:10.588190 11, 0x0, sum = 4
4143 22:20:10.588273 best_step = 9
4144 22:20:10.588338
4145 22:20:10.588398 ==
4146 22:20:10.591412 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 22:20:10.594565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 22:20:10.594648 ==
4149 22:20:10.598120 RX Vref Scan: 1
4150 22:20:10.598202
4151 22:20:10.601281 RX Vref 0 -> 0, step: 1
4152 22:20:10.601363
4153 22:20:10.601428 RX Delay -179 -> 252, step: 8
4154 22:20:10.601488
4155 22:20:10.604438 Set Vref, RX VrefLevel [Byte0]: 59
4156 22:20:10.607729 [Byte1]: 49
4157 22:20:10.612512
4158 22:20:10.612593 Final RX Vref Byte 0 = 59 to rank0
4159 22:20:10.615954 Final RX Vref Byte 1 = 49 to rank0
4160 22:20:10.619370 Final RX Vref Byte 0 = 59 to rank1
4161 22:20:10.622384 Final RX Vref Byte 1 = 49 to rank1==
4162 22:20:10.625567 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 22:20:10.632353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 22:20:10.632436 ==
4165 22:20:10.632500 DQS Delay:
4166 22:20:10.632561 DQS0 = 0, DQS1 = 0
4167 22:20:10.635748 DQM Delay:
4168 22:20:10.635829 DQM0 = 48, DQM1 = 39
4169 22:20:10.638797 DQ Delay:
4170 22:20:10.642176 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4171 22:20:10.645384 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4172 22:20:10.648874 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4173 22:20:10.652256 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4174 22:20:10.652338
4175 22:20:10.652402
4176 22:20:10.658637 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4177 22:20:10.661898 CH0 RK0: MR19=808, MR18=5B55
4178 22:20:10.668813 CH0_RK0: MR19=0x808, MR18=0x5B55, DQSOSC=392, MR23=63, INC=170, DEC=113
4179 22:20:10.668937
4180 22:20:10.671671 ----->DramcWriteLeveling(PI) begin...
4181 22:20:10.671754 ==
4182 22:20:10.675442 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 22:20:10.678912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 22:20:10.678995 ==
4185 22:20:10.681664 Write leveling (Byte 0): 33 => 33
4186 22:20:10.685165 Write leveling (Byte 1): 32 => 32
4187 22:20:10.688453 DramcWriteLeveling(PI) end<-----
4188 22:20:10.688535
4189 22:20:10.688599 ==
4190 22:20:10.691527 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 22:20:10.694857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 22:20:10.698170 ==
4193 22:20:10.698251 [Gating] SW mode calibration
4194 22:20:10.708113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4195 22:20:10.711416 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4196 22:20:10.715008 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4197 22:20:10.721539 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 22:20:10.724712 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 22:20:10.728176 0 9 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4200 22:20:10.734629 0 9 16 | B1->B0 | 2626 2424 | 0 0 | (1 1) (0 0)
4201 22:20:10.737957 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 22:20:10.740973 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 22:20:10.747856 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 22:20:10.750971 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 22:20:10.754156 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 22:20:10.761166 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 22:20:10.764413 0 10 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4208 22:20:10.767470 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4209 22:20:10.774292 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 22:20:10.777700 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 22:20:10.781164 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 22:20:10.787426 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 22:20:10.790351 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 22:20:10.794035 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 22:20:10.800576 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4216 22:20:10.804030 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:20:10.807048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:20:10.813818 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:20:10.816927 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:20:10.820632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:20:10.826882 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:20:10.830355 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 22:20:10.833620 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:20:10.839876 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 22:20:10.843410 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 22:20:10.846805 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 22:20:10.853349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 22:20:10.856272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 22:20:10.859871 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 22:20:10.866225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 22:20:10.869619 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4232 22:20:10.873056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 22:20:10.876430 Total UI for P1: 0, mck2ui 16
4234 22:20:10.879851 best dqsien dly found for B0: ( 0, 13, 12)
4235 22:20:10.883209 Total UI for P1: 0, mck2ui 16
4236 22:20:10.886141 best dqsien dly found for B1: ( 0, 13, 14)
4237 22:20:10.889458 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4238 22:20:10.896143 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4239 22:20:10.896225
4240 22:20:10.899378 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4241 22:20:10.903221 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4242 22:20:10.906227 [Gating] SW calibration Done
4243 22:20:10.906308 ==
4244 22:20:10.909581 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 22:20:10.912571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 22:20:10.912653 ==
4247 22:20:10.915736 RX Vref Scan: 0
4248 22:20:10.915817
4249 22:20:10.915881 RX Vref 0 -> 0, step: 1
4250 22:20:10.915942
4251 22:20:10.919096 RX Delay -230 -> 252, step: 16
4252 22:20:10.922495 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4253 22:20:10.929075 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4254 22:20:10.932301 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4255 22:20:10.935948 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4256 22:20:10.939233 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4257 22:20:10.945654 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4258 22:20:10.948676 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4259 22:20:10.952153 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4260 22:20:10.955243 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4261 22:20:10.958665 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4262 22:20:10.965166 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4263 22:20:10.968505 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4264 22:20:10.971999 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4265 22:20:10.978171 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4266 22:20:10.981582 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4267 22:20:10.985363 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4268 22:20:10.985445 ==
4269 22:20:10.988004 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 22:20:10.991483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 22:20:10.991592 ==
4272 22:20:10.994673 DQS Delay:
4273 22:20:10.994773 DQS0 = 0, DQS1 = 0
4274 22:20:10.998045 DQM Delay:
4275 22:20:10.998142 DQM0 = 48, DQM1 = 42
4276 22:20:10.998234 DQ Delay:
4277 22:20:11.001606 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4278 22:20:11.004808 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4279 22:20:11.008247 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4280 22:20:11.011645 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4281 22:20:11.011726
4282 22:20:11.011790
4283 22:20:11.014635 ==
4284 22:20:11.018031 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 22:20:11.021301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 22:20:11.021382 ==
4287 22:20:11.021447
4288 22:20:11.021506
4289 22:20:11.024644 TX Vref Scan disable
4290 22:20:11.024724 == TX Byte 0 ==
4291 22:20:11.031323 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4292 22:20:11.034488 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4293 22:20:11.034570 == TX Byte 1 ==
4294 22:20:11.041125 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4295 22:20:11.044627 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4296 22:20:11.044708 ==
4297 22:20:11.047719 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 22:20:11.051168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 22:20:11.051249 ==
4300 22:20:11.051314
4301 22:20:11.051372
4302 22:20:11.054746 TX Vref Scan disable
4303 22:20:11.057764 == TX Byte 0 ==
4304 22:20:11.061186 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4305 22:20:11.064161 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4306 22:20:11.067651 == TX Byte 1 ==
4307 22:20:11.070643 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4308 22:20:11.074088 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4309 22:20:11.074169
4310 22:20:11.077336 [DATLAT]
4311 22:20:11.077416 Freq=600, CH0 RK1
4312 22:20:11.077481
4313 22:20:11.081080 DATLAT Default: 0x9
4314 22:20:11.081162 0, 0xFFFF, sum = 0
4315 22:20:11.084014 1, 0xFFFF, sum = 0
4316 22:20:11.084096 2, 0xFFFF, sum = 0
4317 22:20:11.087366 3, 0xFFFF, sum = 0
4318 22:20:11.087448 4, 0xFFFF, sum = 0
4319 22:20:11.090619 5, 0xFFFF, sum = 0
4320 22:20:11.090701 6, 0xFFFF, sum = 0
4321 22:20:11.093887 7, 0xFFFF, sum = 0
4322 22:20:11.093969 8, 0x0, sum = 1
4323 22:20:11.097215 9, 0x0, sum = 2
4324 22:20:11.097297 10, 0x0, sum = 3
4325 22:20:11.100825 11, 0x0, sum = 4
4326 22:20:11.100907 best_step = 9
4327 22:20:11.100971
4328 22:20:11.101030 ==
4329 22:20:11.104132 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 22:20:11.110675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 22:20:11.110755 ==
4332 22:20:11.110818 RX Vref Scan: 0
4333 22:20:11.110876
4334 22:20:11.113911 RX Vref 0 -> 0, step: 1
4335 22:20:11.113990
4336 22:20:11.116968 RX Delay -179 -> 252, step: 8
4337 22:20:11.120263 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4338 22:20:11.127077 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4339 22:20:11.130537 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4340 22:20:11.133769 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4341 22:20:11.136573 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4342 22:20:11.140002 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4343 22:20:11.147096 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4344 22:20:11.149965 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4345 22:20:11.153685 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4346 22:20:11.156907 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4347 22:20:11.160014 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4348 22:20:11.166848 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4349 22:20:11.169928 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4350 22:20:11.173359 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4351 22:20:11.176368 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4352 22:20:11.183221 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4353 22:20:11.183300 ==
4354 22:20:11.186276 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 22:20:11.189920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 22:20:11.190000 ==
4357 22:20:11.190062 DQS Delay:
4358 22:20:11.193243 DQS0 = 0, DQS1 = 0
4359 22:20:11.193322 DQM Delay:
4360 22:20:11.196352 DQM0 = 48, DQM1 = 40
4361 22:20:11.196430 DQ Delay:
4362 22:20:11.200000 DQ0 =44, DQ1 =48, DQ2 =48, DQ3 =44
4363 22:20:11.202893 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4364 22:20:11.206101 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4365 22:20:11.209310 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4366 22:20:11.209388
4367 22:20:11.209451
4368 22:20:11.219207 [DQSOSCAuto] RK1, (LSB)MR18= 0x6835, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4369 22:20:11.219290 CH0 RK1: MR19=808, MR18=6835
4370 22:20:11.225912 CH0_RK1: MR19=0x808, MR18=0x6835, DQSOSC=390, MR23=63, INC=172, DEC=114
4371 22:20:11.229277 [RxdqsGatingPostProcess] freq 600
4372 22:20:11.236108 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4373 22:20:11.239020 Pre-setting of DQS Precalculation
4374 22:20:11.242333 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4375 22:20:11.242412 ==
4376 22:20:11.245663 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 22:20:11.252214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 22:20:11.252297 ==
4379 22:20:11.255561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 22:20:11.262200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4381 22:20:11.265582 [CA 0] Center 35 (5~66) winsize 62
4382 22:20:11.268935 [CA 1] Center 35 (5~66) winsize 62
4383 22:20:11.272350 [CA 2] Center 34 (4~65) winsize 62
4384 22:20:11.275385 [CA 3] Center 33 (3~64) winsize 62
4385 22:20:11.278896 [CA 4] Center 34 (3~65) winsize 63
4386 22:20:11.282090 [CA 5] Center 33 (3~64) winsize 62
4387 22:20:11.282171
4388 22:20:11.285539 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4389 22:20:11.285619
4390 22:20:11.288609 [CATrainingPosCal] consider 1 rank data
4391 22:20:11.292006 u2DelayCellTimex100 = 270/100 ps
4392 22:20:11.295060 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 22:20:11.298724 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 22:20:11.305129 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 22:20:11.308467 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 22:20:11.311511 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4397 22:20:11.315218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 22:20:11.315299
4399 22:20:11.318163 CA PerBit enable=1, Macro0, CA PI delay=33
4400 22:20:11.318244
4401 22:20:11.321693 [CBTSetCACLKResult] CA Dly = 33
4402 22:20:11.321774 CS Dly: 4 (0~35)
4403 22:20:11.325234 ==
4404 22:20:11.328275 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 22:20:11.331573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 22:20:11.331655 ==
4407 22:20:11.334736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 22:20:11.341332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4409 22:20:11.345142 [CA 0] Center 35 (5~66) winsize 62
4410 22:20:11.348456 [CA 1] Center 35 (5~66) winsize 62
4411 22:20:11.352090 [CA 2] Center 34 (4~65) winsize 62
4412 22:20:11.355455 [CA 3] Center 34 (4~65) winsize 62
4413 22:20:11.358697 [CA 4] Center 34 (4~65) winsize 62
4414 22:20:11.361848 [CA 5] Center 33 (3~64) winsize 62
4415 22:20:11.361929
4416 22:20:11.365274 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4417 22:20:11.365359
4418 22:20:11.368267 [CATrainingPosCal] consider 2 rank data
4419 22:20:11.371881 u2DelayCellTimex100 = 270/100 ps
4420 22:20:11.375053 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 22:20:11.381573 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 22:20:11.385033 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4423 22:20:11.388104 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4424 22:20:11.391594 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 22:20:11.394969 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 22:20:11.395050
4427 22:20:11.397984 CA PerBit enable=1, Macro0, CA PI delay=33
4428 22:20:11.398065
4429 22:20:11.401302 [CBTSetCACLKResult] CA Dly = 33
4430 22:20:11.404733 CS Dly: 5 (0~37)
4431 22:20:11.404853
4432 22:20:11.408012 ----->DramcWriteLeveling(PI) begin...
4433 22:20:11.408094 ==
4434 22:20:11.411129 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 22:20:11.414736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 22:20:11.414825 ==
4437 22:20:11.417783 Write leveling (Byte 0): 29 => 29
4438 22:20:11.421214 Write leveling (Byte 1): 30 => 30
4439 22:20:11.424551 DramcWriteLeveling(PI) end<-----
4440 22:20:11.424631
4441 22:20:11.424695 ==
4442 22:20:11.427891 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 22:20:11.431395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 22:20:11.431483 ==
4445 22:20:11.434421 [Gating] SW mode calibration
4446 22:20:11.440875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 22:20:11.447929 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4448 22:20:11.451027 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 22:20:11.454287 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 22:20:11.460932 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4451 22:20:11.464036 0 9 12 | B1->B0 | 2e2e 2929 | 0 0 | (1 0) (0 0)
4452 22:20:11.467633 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 22:20:11.474077 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 22:20:11.477774 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 22:20:11.480893 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 22:20:11.487233 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 22:20:11.490560 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 22:20:11.494164 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4459 22:20:11.500820 0 10 12 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
4460 22:20:11.503731 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 22:20:11.507066 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 22:20:11.513746 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 22:20:11.517065 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 22:20:11.520681 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 22:20:11.526969 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 22:20:11.530598 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 22:20:11.534142 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4468 22:20:11.540541 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:20:11.543551 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:20:11.547039 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:20:11.553660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:20:11.557092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:20:11.560106 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:20:11.566757 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:20:11.569951 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:20:11.573551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 22:20:11.580086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 22:20:11.583477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 22:20:11.586694 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 22:20:11.593131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 22:20:11.596691 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 22:20:11.600138 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 22:20:11.606799 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4484 22:20:11.606881 Total UI for P1: 0, mck2ui 16
4485 22:20:11.609876 best dqsien dly found for B1: ( 0, 13, 10)
4486 22:20:11.616279 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 22:20:11.619879 Total UI for P1: 0, mck2ui 16
4488 22:20:11.623268 best dqsien dly found for B0: ( 0, 13, 12)
4489 22:20:11.626426 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4490 22:20:11.629712 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4491 22:20:11.629793
4492 22:20:11.633115 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4493 22:20:11.636386 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4494 22:20:11.639653 [Gating] SW calibration Done
4495 22:20:11.639735 ==
4496 22:20:11.643098 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 22:20:11.646131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 22:20:11.649278 ==
4499 22:20:11.649359 RX Vref Scan: 0
4500 22:20:11.649423
4501 22:20:11.652921 RX Vref 0 -> 0, step: 1
4502 22:20:11.653002
4503 22:20:11.656676 RX Delay -230 -> 252, step: 16
4504 22:20:11.659101 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4505 22:20:11.662573 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4506 22:20:11.665906 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4507 22:20:11.672312 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4508 22:20:11.675769 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4509 22:20:11.678957 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4510 22:20:11.682512 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4511 22:20:11.685662 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4512 22:20:11.692168 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4513 22:20:11.695335 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4514 22:20:11.698686 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4515 22:20:11.702327 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4516 22:20:11.708855 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4517 22:20:11.712218 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4518 22:20:11.715613 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4519 22:20:11.719009 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4520 22:20:11.719091 ==
4521 22:20:11.722043 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 22:20:11.728945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 22:20:11.729028 ==
4524 22:20:11.729092 DQS Delay:
4525 22:20:11.732082 DQS0 = 0, DQS1 = 0
4526 22:20:11.732164 DQM Delay:
4527 22:20:11.735309 DQM0 = 51, DQM1 = 42
4528 22:20:11.735391 DQ Delay:
4529 22:20:11.738594 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4530 22:20:11.741982 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4531 22:20:11.745302 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4532 22:20:11.748416 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4533 22:20:11.748498
4534 22:20:11.748562
4535 22:20:11.748621 ==
4536 22:20:11.751870 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 22:20:11.755247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 22:20:11.755329 ==
4539 22:20:11.755394
4540 22:20:11.755453
4541 22:20:11.758268 TX Vref Scan disable
4542 22:20:11.761527 == TX Byte 0 ==
4543 22:20:11.765166 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4544 22:20:11.768226 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4545 22:20:11.771675 == TX Byte 1 ==
4546 22:20:11.774733 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4547 22:20:11.778087 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4548 22:20:11.778168 ==
4549 22:20:11.781461 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 22:20:11.788087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 22:20:11.788170 ==
4552 22:20:11.788235
4553 22:20:11.788293
4554 22:20:11.788350 TX Vref Scan disable
4555 22:20:11.791982 == TX Byte 0 ==
4556 22:20:11.795315 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4557 22:20:11.802202 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4558 22:20:11.802285 == TX Byte 1 ==
4559 22:20:11.805584 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4560 22:20:11.811927 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4561 22:20:11.812009
4562 22:20:11.812073 [DATLAT]
4563 22:20:11.812132 Freq=600, CH1 RK0
4564 22:20:11.812190
4565 22:20:11.815301 DATLAT Default: 0x9
4566 22:20:11.818074 0, 0xFFFF, sum = 0
4567 22:20:11.818158 1, 0xFFFF, sum = 0
4568 22:20:11.821646 2, 0xFFFF, sum = 0
4569 22:20:11.821728 3, 0xFFFF, sum = 0
4570 22:20:11.824873 4, 0xFFFF, sum = 0
4571 22:20:11.824956 5, 0xFFFF, sum = 0
4572 22:20:11.828087 6, 0xFFFF, sum = 0
4573 22:20:11.828169 7, 0xFFFF, sum = 0
4574 22:20:11.831405 8, 0x0, sum = 1
4575 22:20:11.831488 9, 0x0, sum = 2
4576 22:20:11.834645 10, 0x0, sum = 3
4577 22:20:11.834728 11, 0x0, sum = 4
4578 22:20:11.834794 best_step = 9
4579 22:20:11.837890
4580 22:20:11.837971 ==
4581 22:20:11.841159 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 22:20:11.844652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 22:20:11.844760 ==
4584 22:20:11.844866 RX Vref Scan: 1
4585 22:20:11.844927
4586 22:20:11.847862 RX Vref 0 -> 0, step: 1
4587 22:20:11.847943
4588 22:20:11.851116 RX Delay -179 -> 252, step: 8
4589 22:20:11.851198
4590 22:20:11.854611 Set Vref, RX VrefLevel [Byte0]: 53
4591 22:20:11.857578 [Byte1]: 53
4592 22:20:11.860909
4593 22:20:11.860990 Final RX Vref Byte 0 = 53 to rank0
4594 22:20:11.864529 Final RX Vref Byte 1 = 53 to rank0
4595 22:20:11.867587 Final RX Vref Byte 0 = 53 to rank1
4596 22:20:11.871094 Final RX Vref Byte 1 = 53 to rank1==
4597 22:20:11.873978 Dram Type= 6, Freq= 0, CH_1, rank 0
4598 22:20:11.880733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 22:20:11.880860 ==
4600 22:20:11.880926 DQS Delay:
4601 22:20:11.880984 DQS0 = 0, DQS1 = 0
4602 22:20:11.883860 DQM Delay:
4603 22:20:11.883941 DQM0 = 49, DQM1 = 41
4604 22:20:11.887316 DQ Delay:
4605 22:20:11.890467 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4606 22:20:11.894044 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4607 22:20:11.897195 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4608 22:20:11.900595 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4609 22:20:11.900703
4610 22:20:11.900798
4611 22:20:11.907149 [DQSOSCAuto] RK0, (LSB)MR18= 0x466c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4612 22:20:11.910556 CH1 RK0: MR19=808, MR18=466C
4613 22:20:11.916883 CH1_RK0: MR19=0x808, MR18=0x466C, DQSOSC=389, MR23=63, INC=173, DEC=115
4614 22:20:11.916965
4615 22:20:11.920208 ----->DramcWriteLeveling(PI) begin...
4616 22:20:11.920291 ==
4617 22:20:11.923893 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 22:20:11.927078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 22:20:11.927160 ==
4620 22:20:11.930428 Write leveling (Byte 0): 29 => 29
4621 22:20:11.933367 Write leveling (Byte 1): 30 => 30
4622 22:20:11.936695 DramcWriteLeveling(PI) end<-----
4623 22:20:11.936835
4624 22:20:11.936902 ==
4625 22:20:11.940270 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 22:20:11.943557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 22:20:11.947133 ==
4628 22:20:11.947214 [Gating] SW mode calibration
4629 22:20:11.956488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4630 22:20:11.959872 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4631 22:20:11.963656 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 22:20:11.970035 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4633 22:20:11.973033 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4634 22:20:11.976402 0 9 12 | B1->B0 | 2828 2f2f | 1 1 | (1 1) (1 1)
4635 22:20:11.983073 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 22:20:11.986620 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 22:20:11.989873 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 22:20:11.996252 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 22:20:11.999588 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 22:20:12.002627 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 22:20:12.009275 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4642 22:20:12.012652 0 10 12 | B1->B0 | 3b3b 2c2c | 0 1 | (0 0) (0 0)
4643 22:20:12.016046 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 22:20:12.022572 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 22:20:12.025845 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 22:20:12.029243 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 22:20:12.036069 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 22:20:12.039037 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 22:20:12.042635 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 22:20:12.049136 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4651 22:20:12.052146 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:20:12.055593 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:20:12.062331 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:20:12.065369 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:20:12.068546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:20:12.075454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:20:12.078886 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:20:12.082411 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 22:20:12.088638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 22:20:12.091904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 22:20:12.095178 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 22:20:12.101675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 22:20:12.105087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 22:20:12.108406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 22:20:12.114912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 22:20:12.118251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4667 22:20:12.121762 Total UI for P1: 0, mck2ui 16
4668 22:20:12.125097 best dqsien dly found for B1: ( 0, 13, 10)
4669 22:20:12.128246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 22:20:12.131460 Total UI for P1: 0, mck2ui 16
4671 22:20:12.135058 best dqsien dly found for B0: ( 0, 13, 12)
4672 22:20:12.138577 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4673 22:20:12.141433 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4674 22:20:12.141516
4675 22:20:12.148187 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4676 22:20:12.151426 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4677 22:20:12.154799 [Gating] SW calibration Done
4678 22:20:12.154881 ==
4679 22:20:12.157862 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 22:20:12.161341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 22:20:12.161424 ==
4682 22:20:12.161488 RX Vref Scan: 0
4683 22:20:12.161549
4684 22:20:12.164637 RX Vref 0 -> 0, step: 1
4685 22:20:12.164744
4686 22:20:12.168067 RX Delay -230 -> 252, step: 16
4687 22:20:12.171142 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4688 22:20:12.174363 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4689 22:20:12.180852 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4690 22:20:12.184216 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4691 22:20:12.187488 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4692 22:20:12.191199 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4693 22:20:12.197594 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4694 22:20:12.200842 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4695 22:20:12.204071 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4696 22:20:12.207490 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4697 22:20:12.210969 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4698 22:20:12.217489 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4699 22:20:12.220855 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4700 22:20:12.224208 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4701 22:20:12.227337 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4702 22:20:12.234089 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4703 22:20:12.234162 ==
4704 22:20:12.237519 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 22:20:12.240685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 22:20:12.240822 ==
4707 22:20:12.240888 DQS Delay:
4708 22:20:12.243918 DQS0 = 0, DQS1 = 0
4709 22:20:12.243987 DQM Delay:
4710 22:20:12.247332 DQM0 = 51, DQM1 = 46
4711 22:20:12.247405 DQ Delay:
4712 22:20:12.250778 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4713 22:20:12.253700 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4714 22:20:12.257202 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4715 22:20:12.260383 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4716 22:20:12.260457
4717 22:20:12.260519
4718 22:20:12.260577 ==
4719 22:20:12.263897 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 22:20:12.266979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 22:20:12.270247 ==
4722 22:20:12.270317
4723 22:20:12.270377
4724 22:20:12.270434 TX Vref Scan disable
4725 22:20:12.273811 == TX Byte 0 ==
4726 22:20:12.277149 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4727 22:20:12.284215 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4728 22:20:12.284298 == TX Byte 1 ==
4729 22:20:12.286600 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4730 22:20:12.293140 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4731 22:20:12.293222 ==
4732 22:20:12.296595 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 22:20:12.299726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 22:20:12.299804 ==
4735 22:20:12.299869
4736 22:20:12.299926
4737 22:20:12.303298 TX Vref Scan disable
4738 22:20:12.306490 == TX Byte 0 ==
4739 22:20:12.310048 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4740 22:20:12.313388 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4741 22:20:12.316429 == TX Byte 1 ==
4742 22:20:12.320056 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4743 22:20:12.323029 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4744 22:20:12.323099
4745 22:20:12.323160 [DATLAT]
4746 22:20:12.326149 Freq=600, CH1 RK1
4747 22:20:12.326218
4748 22:20:12.329808 DATLAT Default: 0x9
4749 22:20:12.329875 0, 0xFFFF, sum = 0
4750 22:20:12.333168 1, 0xFFFF, sum = 0
4751 22:20:12.333237 2, 0xFFFF, sum = 0
4752 22:20:12.336259 3, 0xFFFF, sum = 0
4753 22:20:12.336327 4, 0xFFFF, sum = 0
4754 22:20:12.339538 5, 0xFFFF, sum = 0
4755 22:20:12.339606 6, 0xFFFF, sum = 0
4756 22:20:12.342824 7, 0xFFFF, sum = 0
4757 22:20:12.342893 8, 0x0, sum = 1
4758 22:20:12.346353 9, 0x0, sum = 2
4759 22:20:12.346426 10, 0x0, sum = 3
4760 22:20:12.349400 11, 0x0, sum = 4
4761 22:20:12.349467 best_step = 9
4762 22:20:12.349530
4763 22:20:12.349584 ==
4764 22:20:12.352838 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 22:20:12.356198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 22:20:12.356267 ==
4767 22:20:12.359388 RX Vref Scan: 0
4768 22:20:12.359457
4769 22:20:12.362852 RX Vref 0 -> 0, step: 1
4770 22:20:12.362921
4771 22:20:12.362981 RX Delay -163 -> 252, step: 8
4772 22:20:12.370701 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4773 22:20:12.373759 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4774 22:20:12.376996 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4775 22:20:12.380650 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4776 22:20:12.383661 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4777 22:20:12.390508 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4778 22:20:12.393681 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4779 22:20:12.396952 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4780 22:20:12.400165 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4781 22:20:12.406610 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4782 22:20:12.410018 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4783 22:20:12.413527 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4784 22:20:12.416706 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4785 22:20:12.423111 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4786 22:20:12.426503 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4787 22:20:12.429561 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4788 22:20:12.429633 ==
4789 22:20:12.433292 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 22:20:12.436391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 22:20:12.436462 ==
4792 22:20:12.439782 DQS Delay:
4793 22:20:12.439851 DQS0 = 0, DQS1 = 0
4794 22:20:12.443085 DQM Delay:
4795 22:20:12.443155 DQM0 = 49, DQM1 = 43
4796 22:20:12.443218 DQ Delay:
4797 22:20:12.446002 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =48
4798 22:20:12.449463 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4799 22:20:12.452819 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4800 22:20:12.456190 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4801 22:20:12.456263
4802 22:20:12.456323
4803 22:20:12.466013 [DQSOSCAuto] RK1, (LSB)MR18= 0x581f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4804 22:20:12.469147 CH1 RK1: MR19=808, MR18=581F
4805 22:20:12.476009 CH1_RK1: MR19=0x808, MR18=0x581F, DQSOSC=393, MR23=63, INC=169, DEC=113
4806 22:20:12.478943 [RxdqsGatingPostProcess] freq 600
4807 22:20:12.482162 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4808 22:20:12.485781 Pre-setting of DQS Precalculation
4809 22:20:12.492230 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4810 22:20:12.498768 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4811 22:20:12.505490 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4812 22:20:12.505567
4813 22:20:12.505635
4814 22:20:12.508887 [Calibration Summary] 1200 Mbps
4815 22:20:12.508958 CH 0, Rank 0
4816 22:20:12.511965 SW Impedance : PASS
4817 22:20:12.515337 DUTY Scan : NO K
4818 22:20:12.515410 ZQ Calibration : PASS
4819 22:20:12.518525 Jitter Meter : NO K
4820 22:20:12.522083 CBT Training : PASS
4821 22:20:12.522154 Write leveling : PASS
4822 22:20:12.525059 RX DQS gating : PASS
4823 22:20:12.528675 RX DQ/DQS(RDDQC) : PASS
4824 22:20:12.528744 TX DQ/DQS : PASS
4825 22:20:12.531907 RX DATLAT : PASS
4826 22:20:12.531977 RX DQ/DQS(Engine): PASS
4827 22:20:12.534859 TX OE : NO K
4828 22:20:12.534928 All Pass.
4829 22:20:12.534988
4830 22:20:12.538227 CH 0, Rank 1
4831 22:20:12.541453 SW Impedance : PASS
4832 22:20:12.541526 DUTY Scan : NO K
4833 22:20:12.544980 ZQ Calibration : PASS
4834 22:20:12.545052 Jitter Meter : NO K
4835 22:20:12.548124 CBT Training : PASS
4836 22:20:12.551755 Write leveling : PASS
4837 22:20:12.551825 RX DQS gating : PASS
4838 22:20:12.554770 RX DQ/DQS(RDDQC) : PASS
4839 22:20:12.558126 TX DQ/DQS : PASS
4840 22:20:12.558199 RX DATLAT : PASS
4841 22:20:12.561580 RX DQ/DQS(Engine): PASS
4842 22:20:12.564745 TX OE : NO K
4843 22:20:12.564832 All Pass.
4844 22:20:12.564893
4845 22:20:12.564950 CH 1, Rank 0
4846 22:20:12.567818 SW Impedance : PASS
4847 22:20:12.571357 DUTY Scan : NO K
4848 22:20:12.571430 ZQ Calibration : PASS
4849 22:20:12.574819 Jitter Meter : NO K
4850 22:20:12.577942 CBT Training : PASS
4851 22:20:12.578011 Write leveling : PASS
4852 22:20:12.581169 RX DQS gating : PASS
4853 22:20:12.584368 RX DQ/DQS(RDDQC) : PASS
4854 22:20:12.584437 TX DQ/DQS : PASS
4855 22:20:12.587863 RX DATLAT : PASS
4856 22:20:12.591298 RX DQ/DQS(Engine): PASS
4857 22:20:12.591368 TX OE : NO K
4858 22:20:12.591429 All Pass.
4859 22:20:12.594686
4860 22:20:12.594756 CH 1, Rank 1
4861 22:20:12.598227 SW Impedance : PASS
4862 22:20:12.598296 DUTY Scan : NO K
4863 22:20:12.601537 ZQ Calibration : PASS
4864 22:20:12.601606 Jitter Meter : NO K
4865 22:20:12.604347 CBT Training : PASS
4866 22:20:12.607855 Write leveling : PASS
4867 22:20:12.607925 RX DQS gating : PASS
4868 22:20:12.611132 RX DQ/DQS(RDDQC) : PASS
4869 22:20:12.614406 TX DQ/DQS : PASS
4870 22:20:12.614488 RX DATLAT : PASS
4871 22:20:12.617864 RX DQ/DQS(Engine): PASS
4872 22:20:12.621274 TX OE : NO K
4873 22:20:12.621356 All Pass.
4874 22:20:12.621421
4875 22:20:12.624323 DramC Write-DBI off
4876 22:20:12.624405 PER_BANK_REFRESH: Hybrid Mode
4877 22:20:12.627433 TX_TRACKING: ON
4878 22:20:12.637721 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4879 22:20:12.641132 [FAST_K] Save calibration result to emmc
4880 22:20:12.644116 dramc_set_vcore_voltage set vcore to 662500
4881 22:20:12.644197 Read voltage for 933, 3
4882 22:20:12.647366 Vio18 = 0
4883 22:20:12.647447 Vcore = 662500
4884 22:20:12.647511 Vdram = 0
4885 22:20:12.650853 Vddq = 0
4886 22:20:12.650934 Vmddr = 0
4887 22:20:12.653961 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4888 22:20:12.660875 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4889 22:20:12.663678 MEM_TYPE=3, freq_sel=17
4890 22:20:12.667330 sv_algorithm_assistance_LP4_1600
4891 22:20:12.670720 ============ PULL DRAM RESETB DOWN ============
4892 22:20:12.673601 ========== PULL DRAM RESETB DOWN end =========
4893 22:20:12.680256 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4894 22:20:12.683774 ===================================
4895 22:20:12.683857 LPDDR4 DRAM CONFIGURATION
4896 22:20:12.686786 ===================================
4897 22:20:12.690231 EX_ROW_EN[0] = 0x0
4898 22:20:12.693276 EX_ROW_EN[1] = 0x0
4899 22:20:12.693358 LP4Y_EN = 0x0
4900 22:20:12.696963 WORK_FSP = 0x0
4901 22:20:12.697044 WL = 0x3
4902 22:20:12.700083 RL = 0x3
4903 22:20:12.700164 BL = 0x2
4904 22:20:12.703241 RPST = 0x0
4905 22:20:12.703323 RD_PRE = 0x0
4906 22:20:12.707070 WR_PRE = 0x1
4907 22:20:12.707151 WR_PST = 0x0
4908 22:20:12.710039 DBI_WR = 0x0
4909 22:20:12.710120 DBI_RD = 0x0
4910 22:20:12.713337 OTF = 0x1
4911 22:20:12.716357 ===================================
4912 22:20:12.719793 ===================================
4913 22:20:12.719874 ANA top config
4914 22:20:12.722913 ===================================
4915 22:20:12.726417 DLL_ASYNC_EN = 0
4916 22:20:12.729498 ALL_SLAVE_EN = 1
4917 22:20:12.732954 NEW_RANK_MODE = 1
4918 22:20:12.733036 DLL_IDLE_MODE = 1
4919 22:20:12.736384 LP45_APHY_COMB_EN = 1
4920 22:20:12.739447 TX_ODT_DIS = 1
4921 22:20:12.742645 NEW_8X_MODE = 1
4922 22:20:12.746117 ===================================
4923 22:20:12.749876 ===================================
4924 22:20:12.752980 data_rate = 1866
4925 22:20:12.753062 CKR = 1
4926 22:20:12.755954 DQ_P2S_RATIO = 8
4927 22:20:12.759478 ===================================
4928 22:20:12.762728 CA_P2S_RATIO = 8
4929 22:20:12.766166 DQ_CA_OPEN = 0
4930 22:20:12.769527 DQ_SEMI_OPEN = 0
4931 22:20:12.772546 CA_SEMI_OPEN = 0
4932 22:20:12.772628 CA_FULL_RATE = 0
4933 22:20:12.776097 DQ_CKDIV4_EN = 1
4934 22:20:12.779060 CA_CKDIV4_EN = 1
4935 22:20:12.782370 CA_PREDIV_EN = 0
4936 22:20:12.785985 PH8_DLY = 0
4937 22:20:12.789045 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4938 22:20:12.789127 DQ_AAMCK_DIV = 4
4939 22:20:12.792513 CA_AAMCK_DIV = 4
4940 22:20:12.795540 CA_ADMCK_DIV = 4
4941 22:20:12.798949 DQ_TRACK_CA_EN = 0
4942 22:20:12.802594 CA_PICK = 933
4943 22:20:12.805632 CA_MCKIO = 933
4944 22:20:12.809160 MCKIO_SEMI = 0
4945 22:20:12.809241 PLL_FREQ = 3732
4946 22:20:12.812157 DQ_UI_PI_RATIO = 32
4947 22:20:12.815849 CA_UI_PI_RATIO = 0
4948 22:20:12.818942 ===================================
4949 22:20:12.822302 ===================================
4950 22:20:12.825223 memory_type:LPDDR4
4951 22:20:12.828701 GP_NUM : 10
4952 22:20:12.828815 SRAM_EN : 1
4953 22:20:12.831902 MD32_EN : 0
4954 22:20:12.835323 ===================================
4955 22:20:12.835404 [ANA_INIT] >>>>>>>>>>>>>>
4956 22:20:12.838764 <<<<<< [CONFIGURE PHASE]: ANA_TX
4957 22:20:12.841980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4958 22:20:12.845265 ===================================
4959 22:20:12.848611 data_rate = 1866,PCW = 0X8f00
4960 22:20:12.851792 ===================================
4961 22:20:12.855037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4962 22:20:12.861596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 22:20:12.868397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 22:20:12.871834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4965 22:20:12.875153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4966 22:20:12.878339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4967 22:20:12.881371 [ANA_INIT] flow start
4968 22:20:12.881481 [ANA_INIT] PLL >>>>>>>>
4969 22:20:12.884852 [ANA_INIT] PLL <<<<<<<<
4970 22:20:12.888219 [ANA_INIT] MIDPI >>>>>>>>
4971 22:20:12.891549 [ANA_INIT] MIDPI <<<<<<<<
4972 22:20:12.891622 [ANA_INIT] DLL >>>>>>>>
4973 22:20:12.894597 [ANA_INIT] flow end
4974 22:20:12.898084 ============ LP4 DIFF to SE enter ============
4975 22:20:12.901628 ============ LP4 DIFF to SE exit ============
4976 22:20:12.904648 [ANA_INIT] <<<<<<<<<<<<<
4977 22:20:12.907816 [Flow] Enable top DCM control >>>>>
4978 22:20:12.911659 [Flow] Enable top DCM control <<<<<
4979 22:20:12.914672 Enable DLL master slave shuffle
4980 22:20:12.921053 ==============================================================
4981 22:20:12.921140 Gating Mode config
4982 22:20:12.927414 ==============================================================
4983 22:20:12.927492 Config description:
4984 22:20:12.937356 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4985 22:20:12.944139 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4986 22:20:12.950441 SELPH_MODE 0: By rank 1: By Phase
4987 22:20:12.953901 ==============================================================
4988 22:20:12.957373 GAT_TRACK_EN = 1
4989 22:20:12.960664 RX_GATING_MODE = 2
4990 22:20:12.963640 RX_GATING_TRACK_MODE = 2
4991 22:20:12.966985 SELPH_MODE = 1
4992 22:20:12.970502 PICG_EARLY_EN = 1
4993 22:20:12.973486 VALID_LAT_VALUE = 1
4994 22:20:12.980164 ==============================================================
4995 22:20:12.983450 Enter into Gating configuration >>>>
4996 22:20:12.986696 Exit from Gating configuration <<<<
4997 22:20:12.989909 Enter into DVFS_PRE_config >>>>>
4998 22:20:12.999894 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4999 22:20:13.003250 Exit from DVFS_PRE_config <<<<<
5000 22:20:13.006770 Enter into PICG configuration >>>>
5001 22:20:13.009811 Exit from PICG configuration <<<<
5002 22:20:13.013473 [RX_INPUT] configuration >>>>>
5003 22:20:13.016839 [RX_INPUT] configuration <<<<<
5004 22:20:13.019714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5005 22:20:13.026493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5006 22:20:13.032895 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5007 22:20:13.036077 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5008 22:20:13.042694 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 22:20:13.049389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 22:20:13.052762 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5011 22:20:13.059308 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5012 22:20:13.062613 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5013 22:20:13.065926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5014 22:20:13.069114 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5015 22:20:13.075841 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 22:20:13.079065 ===================================
5017 22:20:13.079149 LPDDR4 DRAM CONFIGURATION
5018 22:20:13.082260 ===================================
5019 22:20:13.085714 EX_ROW_EN[0] = 0x0
5020 22:20:13.089133 EX_ROW_EN[1] = 0x0
5021 22:20:13.089241 LP4Y_EN = 0x0
5022 22:20:13.092127 WORK_FSP = 0x0
5023 22:20:13.092209 WL = 0x3
5024 22:20:13.095328 RL = 0x3
5025 22:20:13.095411 BL = 0x2
5026 22:20:13.098863 RPST = 0x0
5027 22:20:13.098946 RD_PRE = 0x0
5028 22:20:13.101888 WR_PRE = 0x1
5029 22:20:13.101970 WR_PST = 0x0
5030 22:20:13.105232 DBI_WR = 0x0
5031 22:20:13.105315 DBI_RD = 0x0
5032 22:20:13.108555 OTF = 0x1
5033 22:20:13.111986 ===================================
5034 22:20:13.115106 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5035 22:20:13.118587 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5036 22:20:13.125380 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 22:20:13.128640 ===================================
5038 22:20:13.128763 LPDDR4 DRAM CONFIGURATION
5039 22:20:13.131837 ===================================
5040 22:20:13.135270 EX_ROW_EN[0] = 0x10
5041 22:20:13.138593 EX_ROW_EN[1] = 0x0
5042 22:20:13.138677 LP4Y_EN = 0x0
5043 22:20:13.141982 WORK_FSP = 0x0
5044 22:20:13.142065 WL = 0x3
5045 22:20:13.145248 RL = 0x3
5046 22:20:13.145347 BL = 0x2
5047 22:20:13.148402 RPST = 0x0
5048 22:20:13.148485 RD_PRE = 0x0
5049 22:20:13.151428 WR_PRE = 0x1
5050 22:20:13.151529 WR_PST = 0x0
5051 22:20:13.154720 DBI_WR = 0x0
5052 22:20:13.154819 DBI_RD = 0x0
5053 22:20:13.158449 OTF = 0x1
5054 22:20:13.161522 ===================================
5055 22:20:13.167869 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5056 22:20:13.171501 nWR fixed to 30
5057 22:20:13.174444 [ModeRegInit_LP4] CH0 RK0
5058 22:20:13.174527 [ModeRegInit_LP4] CH0 RK1
5059 22:20:13.178046 [ModeRegInit_LP4] CH1 RK0
5060 22:20:13.181123 [ModeRegInit_LP4] CH1 RK1
5061 22:20:13.181206 match AC timing 9
5062 22:20:13.188189 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5063 22:20:13.191171 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5064 22:20:13.194371 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5065 22:20:13.200904 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5066 22:20:13.204383 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5067 22:20:13.204466 ==
5068 22:20:13.207287 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 22:20:13.210859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 22:20:13.213890 ==
5071 22:20:13.217350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 22:20:13.223924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 22:20:13.227465 [CA 0] Center 38 (7~69) winsize 63
5074 22:20:13.230460 [CA 1] Center 38 (8~69) winsize 62
5075 22:20:13.234163 [CA 2] Center 35 (5~66) winsize 62
5076 22:20:13.237406 [CA 3] Center 35 (5~65) winsize 61
5077 22:20:13.240602 [CA 4] Center 34 (4~65) winsize 62
5078 22:20:13.244058 [CA 5] Center 33 (3~64) winsize 62
5079 22:20:13.244141
5080 22:20:13.247050 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 22:20:13.247133
5082 22:20:13.250251 [CATrainingPosCal] consider 1 rank data
5083 22:20:13.253690 u2DelayCellTimex100 = 270/100 ps
5084 22:20:13.256690 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5085 22:20:13.260211 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5086 22:20:13.263697 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5087 22:20:13.269931 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5088 22:20:13.273582 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5089 22:20:13.276666 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5090 22:20:13.276749
5091 22:20:13.279985 CA PerBit enable=1, Macro0, CA PI delay=33
5092 22:20:13.280068
5093 22:20:13.283491 [CBTSetCACLKResult] CA Dly = 33
5094 22:20:13.283574 CS Dly: 7 (0~38)
5095 22:20:13.283640 ==
5096 22:20:13.286595 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 22:20:13.293341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 22:20:13.293439 ==
5099 22:20:13.296553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 22:20:13.302873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5101 22:20:13.306546 [CA 0] Center 38 (8~69) winsize 62
5102 22:20:13.309764 [CA 1] Center 38 (8~69) winsize 62
5103 22:20:13.313006 [CA 2] Center 36 (6~66) winsize 61
5104 22:20:13.316493 [CA 3] Center 35 (5~65) winsize 61
5105 22:20:13.319671 [CA 4] Center 34 (4~65) winsize 62
5106 22:20:13.323172 [CA 5] Center 34 (4~64) winsize 61
5107 22:20:13.323255
5108 22:20:13.326233 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5109 22:20:13.326316
5110 22:20:13.329593 [CATrainingPosCal] consider 2 rank data
5111 22:20:13.332913 u2DelayCellTimex100 = 270/100 ps
5112 22:20:13.336102 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5113 22:20:13.342530 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5114 22:20:13.346035 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5115 22:20:13.349394 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5116 22:20:13.352493 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5117 22:20:13.356101 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5118 22:20:13.356184
5119 22:20:13.359015 CA PerBit enable=1, Macro0, CA PI delay=34
5120 22:20:13.359097
5121 22:20:13.362276 [CBTSetCACLKResult] CA Dly = 34
5122 22:20:13.365772 CS Dly: 7 (0~39)
5123 22:20:13.365854
5124 22:20:13.369119 ----->DramcWriteLeveling(PI) begin...
5125 22:20:13.369204 ==
5126 22:20:13.372151 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 22:20:13.375588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 22:20:13.375672 ==
5129 22:20:13.378970 Write leveling (Byte 0): 31 => 31
5130 22:20:13.382307 Write leveling (Byte 1): 31 => 31
5131 22:20:13.385680 DramcWriteLeveling(PI) end<-----
5132 22:20:13.385762
5133 22:20:13.385826 ==
5134 22:20:13.389008 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 22:20:13.392142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 22:20:13.392224 ==
5137 22:20:13.395481 [Gating] SW mode calibration
5138 22:20:13.402063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5139 22:20:13.408685 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5140 22:20:13.412273 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5141 22:20:13.418539 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 22:20:13.421663 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 22:20:13.425422 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 22:20:13.428354 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 22:20:13.435007 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 22:20:13.438602 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5147 22:20:13.441976 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
5148 22:20:13.448113 0 15 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (1 0)
5149 22:20:13.451697 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 22:20:13.455448 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 22:20:13.461724 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 22:20:13.464943 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 22:20:13.468365 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 22:20:13.474897 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5155 22:20:13.478026 0 15 28 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
5156 22:20:13.481317 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5157 22:20:13.488263 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 22:20:13.491270 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 22:20:13.494656 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 22:20:13.501299 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 22:20:13.504356 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 22:20:13.507707 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5163 22:20:13.514637 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5164 22:20:13.517597 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:20:13.520769 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:20:13.527693 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:20:13.531100 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:20:13.534190 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:20:13.540907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:20:13.544156 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:20:13.547300 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 22:20:13.554228 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 22:20:13.557616 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 22:20:13.560487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 22:20:13.567233 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 22:20:13.570757 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 22:20:13.573848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 22:20:13.580271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5179 22:20:13.583941 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5180 22:20:13.587317 Total UI for P1: 0, mck2ui 16
5181 22:20:13.590410 best dqsien dly found for B0: ( 1, 2, 24)
5182 22:20:13.593870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5183 22:20:13.600182 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 22:20:13.600266 Total UI for P1: 0, mck2ui 16
5185 22:20:13.606848 best dqsien dly found for B1: ( 1, 2, 30)
5186 22:20:13.610335 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5187 22:20:13.613737 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5188 22:20:13.613820
5189 22:20:13.616576 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5190 22:20:13.619869 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5191 22:20:13.623327 [Gating] SW calibration Done
5192 22:20:13.623410 ==
5193 22:20:13.626861 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 22:20:13.629885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 22:20:13.629969 ==
5196 22:20:13.633172 RX Vref Scan: 0
5197 22:20:13.633255
5198 22:20:13.633320 RX Vref 0 -> 0, step: 1
5199 22:20:13.636458
5200 22:20:13.636540 RX Delay -80 -> 252, step: 8
5201 22:20:13.643578 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5202 22:20:13.646423 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5203 22:20:13.650169 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5204 22:20:13.653207 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5205 22:20:13.656270 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5206 22:20:13.659478 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5207 22:20:13.666393 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5208 22:20:13.669531 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5209 22:20:13.673047 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5210 22:20:13.676457 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5211 22:20:13.679575 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5212 22:20:13.685989 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5213 22:20:13.689211 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5214 22:20:13.692587 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5215 22:20:13.696400 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5216 22:20:13.699045 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5217 22:20:13.699128 ==
5218 22:20:13.702347 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 22:20:13.708806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 22:20:13.708889 ==
5221 22:20:13.708955 DQS Delay:
5222 22:20:13.712258 DQS0 = 0, DQS1 = 0
5223 22:20:13.712340 DQM Delay:
5224 22:20:13.712405 DQM0 = 105, DQM1 = 90
5225 22:20:13.715549 DQ Delay:
5226 22:20:13.719034 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5227 22:20:13.722505 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5228 22:20:13.725339 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5229 22:20:13.728738 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5230 22:20:13.728828
5231 22:20:13.728894
5232 22:20:13.728952 ==
5233 22:20:13.732402 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 22:20:13.735554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 22:20:13.735638 ==
5236 22:20:13.735703
5237 22:20:13.735763
5238 22:20:13.738692 TX Vref Scan disable
5239 22:20:13.741912 == TX Byte 0 ==
5240 22:20:13.745296 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5241 22:20:13.748421 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5242 22:20:13.751940 == TX Byte 1 ==
5243 22:20:13.755294 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5244 22:20:13.758542 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5245 22:20:13.758628 ==
5246 22:20:13.761606 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 22:20:13.768385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 22:20:13.768468 ==
5249 22:20:13.768534
5250 22:20:13.768593
5251 22:20:13.768652 TX Vref Scan disable
5252 22:20:13.772461 == TX Byte 0 ==
5253 22:20:13.775590 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5254 22:20:13.782309 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5255 22:20:13.782392 == TX Byte 1 ==
5256 22:20:13.785884 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5257 22:20:13.792427 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5258 22:20:13.792511
5259 22:20:13.792576 [DATLAT]
5260 22:20:13.792638 Freq=933, CH0 RK0
5261 22:20:13.792697
5262 22:20:13.795479 DATLAT Default: 0xd
5263 22:20:13.795563 0, 0xFFFF, sum = 0
5264 22:20:13.798709 1, 0xFFFF, sum = 0
5265 22:20:13.798793 2, 0xFFFF, sum = 0
5266 22:20:13.802862 3, 0xFFFF, sum = 0
5267 22:20:13.805629 4, 0xFFFF, sum = 0
5268 22:20:13.805738 5, 0xFFFF, sum = 0
5269 22:20:13.808714 6, 0xFFFF, sum = 0
5270 22:20:13.808835 7, 0xFFFF, sum = 0
5271 22:20:13.812144 8, 0xFFFF, sum = 0
5272 22:20:13.812228 9, 0xFFFF, sum = 0
5273 22:20:13.815513 10, 0x0, sum = 1
5274 22:20:13.815597 11, 0x0, sum = 2
5275 22:20:13.818747 12, 0x0, sum = 3
5276 22:20:13.818831 13, 0x0, sum = 4
5277 22:20:13.818898 best_step = 11
5278 22:20:13.818963
5279 22:20:13.822015 ==
5280 22:20:13.825363 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 22:20:13.828606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 22:20:13.828690 ==
5283 22:20:13.828755 RX Vref Scan: 1
5284 22:20:13.828825
5285 22:20:13.832081 RX Vref 0 -> 0, step: 1
5286 22:20:13.832163
5287 22:20:13.835262 RX Delay -53 -> 252, step: 4
5288 22:20:13.835345
5289 22:20:13.838586 Set Vref, RX VrefLevel [Byte0]: 59
5290 22:20:13.841817 [Byte1]: 49
5291 22:20:13.841899
5292 22:20:13.845279 Final RX Vref Byte 0 = 59 to rank0
5293 22:20:13.848321 Final RX Vref Byte 1 = 49 to rank0
5294 22:20:13.851635 Final RX Vref Byte 0 = 59 to rank1
5295 22:20:13.855105 Final RX Vref Byte 1 = 49 to rank1==
5296 22:20:13.858195 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 22:20:13.861591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 22:20:13.865043 ==
5299 22:20:13.865125 DQS Delay:
5300 22:20:13.865190 DQS0 = 0, DQS1 = 0
5301 22:20:13.868420 DQM Delay:
5302 22:20:13.868502 DQM0 = 107, DQM1 = 92
5303 22:20:13.871446 DQ Delay:
5304 22:20:13.875066 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106
5305 22:20:13.878204 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5306 22:20:13.881467 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5307 22:20:13.884807 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5308 22:20:13.884890
5309 22:20:13.884955
5310 22:20:13.891605 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5311 22:20:13.894513 CH0 RK0: MR19=505, MR18=221E
5312 22:20:13.900947 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5313 22:20:13.901031
5314 22:20:13.904325 ----->DramcWriteLeveling(PI) begin...
5315 22:20:13.904409 ==
5316 22:20:13.907647 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 22:20:13.911019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 22:20:13.911102 ==
5319 22:20:13.914290 Write leveling (Byte 0): 31 => 31
5320 22:20:13.917572 Write leveling (Byte 1): 30 => 30
5321 22:20:13.920660 DramcWriteLeveling(PI) end<-----
5322 22:20:13.920744
5323 22:20:13.920837 ==
5324 22:20:13.924235 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 22:20:13.930712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 22:20:13.930796 ==
5327 22:20:13.930862 [Gating] SW mode calibration
5328 22:20:13.940802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 22:20:13.943698 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 22:20:13.950373 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 22:20:13.953928 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 22:20:13.957348 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 22:20:13.963571 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 22:20:13.967086 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 22:20:13.970443 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 22:20:13.977001 0 14 24 | B1->B0 | 3333 3030 | 0 1 | (0 1) (1 1)
5337 22:20:13.980103 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5338 22:20:13.983517 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 22:20:13.990414 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 22:20:13.993554 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 22:20:13.996592 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 22:20:14.003513 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 22:20:14.006448 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 22:20:14.010058 0 15 24 | B1->B0 | 2626 2929 | 1 0 | (0 0) (0 0)
5345 22:20:14.016614 0 15 28 | B1->B0 | 3938 4343 | 1 1 | (0 0) (0 0)
5346 22:20:14.019838 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 22:20:14.023330 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 22:20:14.029393 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 22:20:14.032736 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 22:20:14.036199 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 22:20:14.042473 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 22:20:14.045954 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5353 22:20:14.049580 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5354 22:20:14.055851 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:20:14.058958 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:20:14.062246 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:20:14.069023 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:20:14.072489 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:20:14.075512 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:20:14.082313 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:20:14.085386 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:20:14.088950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 22:20:14.095527 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 22:20:14.098531 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 22:20:14.101705 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 22:20:14.108487 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 22:20:14.111586 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 22:20:14.115056 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5369 22:20:14.121889 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5370 22:20:14.124892 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 22:20:14.128613 Total UI for P1: 0, mck2ui 16
5372 22:20:14.131740 best dqsien dly found for B0: ( 1, 2, 26)
5373 22:20:14.135058 Total UI for P1: 0, mck2ui 16
5374 22:20:14.138510 best dqsien dly found for B1: ( 1, 2, 26)
5375 22:20:14.141754 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5376 22:20:14.145013 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5377 22:20:14.145096
5378 22:20:14.147872 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5379 22:20:14.151167 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5380 22:20:14.154712 [Gating] SW calibration Done
5381 22:20:14.154812 ==
5382 22:20:14.158047 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 22:20:14.161487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 22:20:14.164589 ==
5385 22:20:14.164671 RX Vref Scan: 0
5386 22:20:14.164736
5387 22:20:14.168261 RX Vref 0 -> 0, step: 1
5388 22:20:14.168343
5389 22:20:14.171145 RX Delay -80 -> 252, step: 8
5390 22:20:14.174705 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5391 22:20:14.177826 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5392 22:20:14.181095 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5393 22:20:14.184630 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5394 22:20:14.187650 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5395 22:20:14.194503 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5396 22:20:14.198055 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5397 22:20:14.200935 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5398 22:20:14.204451 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5399 22:20:14.207592 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5400 22:20:14.214369 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5401 22:20:14.217684 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5402 22:20:14.220981 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5403 22:20:14.224270 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5404 22:20:14.227535 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5405 22:20:14.230675 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5406 22:20:14.234257 ==
5407 22:20:14.234359 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 22:20:14.240572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 22:20:14.240674 ==
5410 22:20:14.240780 DQS Delay:
5411 22:20:14.243664 DQS0 = 0, DQS1 = 0
5412 22:20:14.243735 DQM Delay:
5413 22:20:14.247111 DQM0 = 105, DQM1 = 90
5414 22:20:14.247184 DQ Delay:
5415 22:20:14.250533 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5416 22:20:14.254045 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5417 22:20:14.256950 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5418 22:20:14.260261 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5419 22:20:14.260358
5420 22:20:14.260455
5421 22:20:14.260553 ==
5422 22:20:14.263720 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 22:20:14.267378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 22:20:14.267477 ==
5425 22:20:14.267575
5426 22:20:14.270354
5427 22:20:14.270432 TX Vref Scan disable
5428 22:20:14.273702 == TX Byte 0 ==
5429 22:20:14.277087 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5430 22:20:14.280440 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5431 22:20:14.283971 == TX Byte 1 ==
5432 22:20:14.286892 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5433 22:20:14.290179 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5434 22:20:14.290276 ==
5435 22:20:14.293244 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 22:20:14.300145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 22:20:14.300246 ==
5438 22:20:14.300345
5439 22:20:14.300443
5440 22:20:14.300538 TX Vref Scan disable
5441 22:20:14.304406 == TX Byte 0 ==
5442 22:20:14.307734 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5443 22:20:14.314168 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5444 22:20:14.314269 == TX Byte 1 ==
5445 22:20:14.317737 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5446 22:20:14.324235 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5447 22:20:14.324339
5448 22:20:14.324438 [DATLAT]
5449 22:20:14.324537 Freq=933, CH0 RK1
5450 22:20:14.324633
5451 22:20:14.327369 DATLAT Default: 0xb
5452 22:20:14.327441 0, 0xFFFF, sum = 0
5453 22:20:14.330901 1, 0xFFFF, sum = 0
5454 22:20:14.334000 2, 0xFFFF, sum = 0
5455 22:20:14.334079 3, 0xFFFF, sum = 0
5456 22:20:14.337554 4, 0xFFFF, sum = 0
5457 22:20:14.337632 5, 0xFFFF, sum = 0
5458 22:20:14.340691 6, 0xFFFF, sum = 0
5459 22:20:14.340794 7, 0xFFFF, sum = 0
5460 22:20:14.343895 8, 0xFFFF, sum = 0
5461 22:20:14.343967 9, 0xFFFF, sum = 0
5462 22:20:14.347166 10, 0x0, sum = 1
5463 22:20:14.347239 11, 0x0, sum = 2
5464 22:20:14.350578 12, 0x0, sum = 3
5465 22:20:14.350676 13, 0x0, sum = 4
5466 22:20:14.350774 best_step = 11
5467 22:20:14.354081
5468 22:20:14.354153 ==
5469 22:20:14.357192 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 22:20:14.360241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 22:20:14.360313 ==
5472 22:20:14.360391 RX Vref Scan: 0
5473 22:20:14.360486
5474 22:20:14.363628 RX Vref 0 -> 0, step: 1
5475 22:20:14.363704
5476 22:20:14.367222 RX Delay -53 -> 252, step: 4
5477 22:20:14.373499 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5478 22:20:14.376999 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5479 22:20:14.380618 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5480 22:20:14.383704 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5481 22:20:14.386836 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5482 22:20:14.393518 iDelay=199, Bit 5, Center 100 (15 ~ 186) 172
5483 22:20:14.396813 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5484 22:20:14.400080 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5485 22:20:14.403551 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5486 22:20:14.406717 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5487 22:20:14.410304 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5488 22:20:14.416731 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5489 22:20:14.420085 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5490 22:20:14.423453 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5491 22:20:14.426437 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5492 22:20:14.433003 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5493 22:20:14.433106 ==
5494 22:20:14.436222 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 22:20:14.440130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 22:20:14.440229 ==
5497 22:20:14.440329 DQS Delay:
5498 22:20:14.442727 DQS0 = 0, DQS1 = 0
5499 22:20:14.442824 DQM Delay:
5500 22:20:14.446224 DQM0 = 104, DQM1 = 92
5501 22:20:14.446322 DQ Delay:
5502 22:20:14.449467 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5503 22:20:14.453153 DQ4 =104, DQ5 =100, DQ6 =112, DQ7 =110
5504 22:20:14.456065 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5505 22:20:14.459293 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5506 22:20:14.459391
5507 22:20:14.459489
5508 22:20:14.469456 [DQSOSCAuto] RK1, (LSB)MR18= 0x2608, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5509 22:20:14.472345 CH0 RK1: MR19=505, MR18=2608
5510 22:20:14.475542 CH0_RK1: MR19=0x505, MR18=0x2608, DQSOSC=409, MR23=63, INC=64, DEC=43
5511 22:20:14.479241 [RxdqsGatingPostProcess] freq 933
5512 22:20:14.486076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5513 22:20:14.489145 best DQS0 dly(2T, 0.5T) = (0, 10)
5514 22:20:14.492083 best DQS1 dly(2T, 0.5T) = (0, 10)
5515 22:20:14.495590 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5516 22:20:14.499025 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5517 22:20:14.501989 best DQS0 dly(2T, 0.5T) = (0, 10)
5518 22:20:14.505618 best DQS1 dly(2T, 0.5T) = (0, 10)
5519 22:20:14.508520 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5520 22:20:14.511833 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5521 22:20:14.515623 Pre-setting of DQS Precalculation
5522 22:20:14.518592 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5523 22:20:14.518692 ==
5524 22:20:14.522069 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 22:20:14.525282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 22:20:14.528194 ==
5527 22:20:14.531609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 22:20:14.538374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5529 22:20:14.541566 [CA 0] Center 37 (7~68) winsize 62
5530 22:20:14.544891 [CA 1] Center 37 (7~68) winsize 62
5531 22:20:14.548155 [CA 2] Center 35 (6~65) winsize 60
5532 22:20:14.551482 [CA 3] Center 35 (5~65) winsize 61
5533 22:20:14.554571 [CA 4] Center 35 (5~66) winsize 62
5534 22:20:14.558282 [CA 5] Center 34 (4~65) winsize 62
5535 22:20:14.558382
5536 22:20:14.561535 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5537 22:20:14.561635
5538 22:20:14.564627 [CATrainingPosCal] consider 1 rank data
5539 22:20:14.568148 u2DelayCellTimex100 = 270/100 ps
5540 22:20:14.571091 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5541 22:20:14.574661 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5542 22:20:14.577676 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5543 22:20:14.584657 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5544 22:20:14.587867 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5545 22:20:14.591094 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5546 22:20:14.591168
5547 22:20:14.594274 CA PerBit enable=1, Macro0, CA PI delay=34
5548 22:20:14.594375
5549 22:20:14.597328 [CBTSetCACLKResult] CA Dly = 34
5550 22:20:14.597403 CS Dly: 6 (0~37)
5551 22:20:14.597500 ==
5552 22:20:14.600896 Dram Type= 6, Freq= 0, CH_1, rank 1
5553 22:20:14.607611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 22:20:14.607713 ==
5555 22:20:14.610616 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5556 22:20:14.617189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5557 22:20:14.620763 [CA 0] Center 38 (8~69) winsize 62
5558 22:20:14.624056 [CA 1] Center 38 (7~69) winsize 63
5559 22:20:14.627529 [CA 2] Center 36 (6~66) winsize 61
5560 22:20:14.630796 [CA 3] Center 35 (5~65) winsize 61
5561 22:20:14.633817 [CA 4] Center 35 (5~65) winsize 61
5562 22:20:14.637371 [CA 5] Center 35 (5~65) winsize 61
5563 22:20:14.637453
5564 22:20:14.640576 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5565 22:20:14.640657
5566 22:20:14.643724 [CATrainingPosCal] consider 2 rank data
5567 22:20:14.647283 u2DelayCellTimex100 = 270/100 ps
5568 22:20:14.650449 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5569 22:20:14.656812 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5570 22:20:14.660193 CA2 delay=35 (6~65),Diff = 0 PI (0 cell)
5571 22:20:14.663635 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5572 22:20:14.667062 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5573 22:20:14.670435 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5574 22:20:14.670517
5575 22:20:14.673352 CA PerBit enable=1, Macro0, CA PI delay=35
5576 22:20:14.673434
5577 22:20:14.677013 [CBTSetCACLKResult] CA Dly = 35
5578 22:20:14.679861 CS Dly: 7 (0~39)
5579 22:20:14.679943
5580 22:20:14.683186 ----->DramcWriteLeveling(PI) begin...
5581 22:20:14.683268 ==
5582 22:20:14.686602 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 22:20:14.689979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 22:20:14.690062 ==
5585 22:20:14.693114 Write leveling (Byte 0): 26 => 26
5586 22:20:14.696591 Write leveling (Byte 1): 27 => 27
5587 22:20:14.699906 DramcWriteLeveling(PI) end<-----
5588 22:20:14.699988
5589 22:20:14.700052 ==
5590 22:20:14.703175 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 22:20:14.706346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 22:20:14.706428 ==
5593 22:20:14.709779 [Gating] SW mode calibration
5594 22:20:14.716268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5595 22:20:14.722757 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5596 22:20:14.726045 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 22:20:14.729377 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 22:20:14.736132 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 22:20:14.739353 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 22:20:14.742539 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 22:20:14.749365 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 22:20:14.752776 0 14 24 | B1->B0 | 3131 3131 | 0 0 | (0 1) (0 1)
5603 22:20:14.755712 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 22:20:14.762430 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 22:20:14.765663 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 22:20:14.769128 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 22:20:14.775865 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 22:20:14.778911 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 22:20:14.782147 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 22:20:14.789062 0 15 24 | B1->B0 | 2929 2b2b | 0 1 | (0 0) (0 0)
5611 22:20:14.792250 0 15 28 | B1->B0 | 3d3d 4343 | 0 0 | (1 1) (0 0)
5612 22:20:14.795653 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 22:20:14.802082 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 22:20:14.805240 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 22:20:14.808990 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 22:20:14.815436 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 22:20:14.818488 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 22:20:14.821897 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5619 22:20:14.828255 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5620 22:20:14.831840 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:20:14.834948 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:20:14.841972 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:20:14.845094 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:20:14.848186 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:20:14.854981 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:20:14.858185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:20:14.861370 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:20:14.867903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 22:20:14.871200 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 22:20:14.874681 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 22:20:14.881221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 22:20:14.884560 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 22:20:14.887723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 22:20:14.894251 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5635 22:20:14.897517 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5636 22:20:14.901004 Total UI for P1: 0, mck2ui 16
5637 22:20:14.904433 best dqsien dly found for B0: ( 1, 2, 24)
5638 22:20:14.907740 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 22:20:14.911058 Total UI for P1: 0, mck2ui 16
5640 22:20:14.914262 best dqsien dly found for B1: ( 1, 2, 28)
5641 22:20:14.917365 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5642 22:20:14.920666 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5643 22:20:14.923966
5644 22:20:14.927122 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5645 22:20:14.930783 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5646 22:20:14.933741 [Gating] SW calibration Done
5647 22:20:14.933823 ==
5648 22:20:14.937100 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 22:20:14.940638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 22:20:14.940721 ==
5651 22:20:14.943997 RX Vref Scan: 0
5652 22:20:14.944079
5653 22:20:14.944143 RX Vref 0 -> 0, step: 1
5654 22:20:14.944204
5655 22:20:14.947011 RX Delay -80 -> 252, step: 8
5656 22:20:14.950521 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5657 22:20:14.953606 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5658 22:20:14.960385 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5659 22:20:14.963560 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5660 22:20:14.966755 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5661 22:20:14.970332 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5662 22:20:14.973614 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5663 22:20:14.976902 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5664 22:20:14.983259 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5665 22:20:14.986693 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5666 22:20:14.990177 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5667 22:20:14.993338 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5668 22:20:14.996776 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5669 22:20:15.003215 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5670 22:20:15.006755 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5671 22:20:15.010058 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5672 22:20:15.010141 ==
5673 22:20:15.013408 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 22:20:15.016464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 22:20:15.016573 ==
5676 22:20:15.019852 DQS Delay:
5677 22:20:15.019934 DQS0 = 0, DQS1 = 0
5678 22:20:15.019999 DQM Delay:
5679 22:20:15.023152 DQM0 = 102, DQM1 = 95
5680 22:20:15.023234 DQ Delay:
5681 22:20:15.026924 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5682 22:20:15.030051 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5683 22:20:15.033181 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5684 22:20:15.036570 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5685 22:20:15.036651
5686 22:20:15.039595
5687 22:20:15.039677 ==
5688 22:20:15.043045 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 22:20:15.046297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 22:20:15.046380 ==
5691 22:20:15.046445
5692 22:20:15.046505
5693 22:20:15.049679 TX Vref Scan disable
5694 22:20:15.049761 == TX Byte 0 ==
5695 22:20:15.056124 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5696 22:20:15.059497 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5697 22:20:15.059579 == TX Byte 1 ==
5698 22:20:15.066074 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5699 22:20:15.069466 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5700 22:20:15.069548 ==
5701 22:20:15.072753 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 22:20:15.075710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 22:20:15.075796 ==
5704 22:20:15.075861
5705 22:20:15.075921
5706 22:20:15.079549 TX Vref Scan disable
5707 22:20:15.082598 == TX Byte 0 ==
5708 22:20:15.085770 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5709 22:20:15.089189 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5710 22:20:15.092375 == TX Byte 1 ==
5711 22:20:15.095676 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5712 22:20:15.099122 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5713 22:20:15.099204
5714 22:20:15.102304 [DATLAT]
5715 22:20:15.102386 Freq=933, CH1 RK0
5716 22:20:15.102451
5717 22:20:15.106030 DATLAT Default: 0xd
5718 22:20:15.106111 0, 0xFFFF, sum = 0
5719 22:20:15.109245 1, 0xFFFF, sum = 0
5720 22:20:15.109328 2, 0xFFFF, sum = 0
5721 22:20:15.112454 3, 0xFFFF, sum = 0
5722 22:20:15.112565 4, 0xFFFF, sum = 0
5723 22:20:15.115566 5, 0xFFFF, sum = 0
5724 22:20:15.115650 6, 0xFFFF, sum = 0
5725 22:20:15.119102 7, 0xFFFF, sum = 0
5726 22:20:15.119185 8, 0xFFFF, sum = 0
5727 22:20:15.122569 9, 0xFFFF, sum = 0
5728 22:20:15.122653 10, 0x0, sum = 1
5729 22:20:15.125512 11, 0x0, sum = 2
5730 22:20:15.125596 12, 0x0, sum = 3
5731 22:20:15.128890 13, 0x0, sum = 4
5732 22:20:15.128974 best_step = 11
5733 22:20:15.129038
5734 22:20:15.129098 ==
5735 22:20:15.132225 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 22:20:15.138856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 22:20:15.138938 ==
5738 22:20:15.139003 RX Vref Scan: 1
5739 22:20:15.139063
5740 22:20:15.142112 RX Vref 0 -> 0, step: 1
5741 22:20:15.142194
5742 22:20:15.145347 RX Delay -53 -> 252, step: 4
5743 22:20:15.145432
5744 22:20:15.148955 Set Vref, RX VrefLevel [Byte0]: 53
5745 22:20:15.151970 [Byte1]: 53
5746 22:20:15.152052
5747 22:20:15.155347 Final RX Vref Byte 0 = 53 to rank0
5748 22:20:15.158874 Final RX Vref Byte 1 = 53 to rank0
5749 22:20:15.161806 Final RX Vref Byte 0 = 53 to rank1
5750 22:20:15.165462 Final RX Vref Byte 1 = 53 to rank1==
5751 22:20:15.168284 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 22:20:15.172019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 22:20:15.172101 ==
5754 22:20:15.175266 DQS Delay:
5755 22:20:15.175364 DQS0 = 0, DQS1 = 0
5756 22:20:15.178443 DQM Delay:
5757 22:20:15.178528 DQM0 = 104, DQM1 = 97
5758 22:20:15.178593 DQ Delay:
5759 22:20:15.181847 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5760 22:20:15.188169 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5761 22:20:15.191523 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =92
5762 22:20:15.194780 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5763 22:20:15.194862
5764 22:20:15.194927
5765 22:20:15.201410 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5766 22:20:15.204627 CH1 RK0: MR19=505, MR18=1B33
5767 22:20:15.211614 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5768 22:20:15.211696
5769 22:20:15.214687 ----->DramcWriteLeveling(PI) begin...
5770 22:20:15.214770 ==
5771 22:20:15.217783 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 22:20:15.221435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 22:20:15.221517 ==
5774 22:20:15.224587 Write leveling (Byte 0): 28 => 28
5775 22:20:15.227889 Write leveling (Byte 1): 28 => 28
5776 22:20:15.230984 DramcWriteLeveling(PI) end<-----
5777 22:20:15.231066
5778 22:20:15.231129 ==
5779 22:20:15.234588 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 22:20:15.237925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 22:20:15.240910 ==
5782 22:20:15.240992 [Gating] SW mode calibration
5783 22:20:15.251159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5784 22:20:15.254512 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5785 22:20:15.257644 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5786 22:20:15.264401 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 22:20:15.267321 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 22:20:15.271135 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 22:20:15.277457 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 22:20:15.281035 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 22:20:15.284331 0 14 24 | B1->B0 | 3030 3333 | 0 0 | (1 0) (0 0)
5792 22:20:15.290752 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5793 22:20:15.294043 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 22:20:15.297189 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 22:20:15.303673 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 22:20:15.307000 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 22:20:15.310592 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 22:20:15.317331 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 22:20:15.320522 0 15 24 | B1->B0 | 2a2a 2525 | 0 0 | (1 1) (0 0)
5800 22:20:15.323506 0 15 28 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (1 1)
5801 22:20:15.330333 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5802 22:20:15.333874 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 22:20:15.336796 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 22:20:15.343429 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 22:20:15.346824 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 22:20:15.350074 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 22:20:15.356529 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5808 22:20:15.359719 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5809 22:20:15.363306 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:20:15.369829 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:20:15.373072 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:20:15.376491 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:20:15.383205 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:20:15.386153 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:20:15.389688 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:20:15.396115 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 22:20:15.399488 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 22:20:15.402700 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 22:20:15.409103 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 22:20:15.412426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 22:20:15.416021 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 22:20:15.422392 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 22:20:15.425954 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 22:20:15.428917 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5825 22:20:15.435711 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 22:20:15.439134 Total UI for P1: 0, mck2ui 16
5827 22:20:15.442671 best dqsien dly found for B0: ( 1, 2, 28)
5828 22:20:15.442753 Total UI for P1: 0, mck2ui 16
5829 22:20:15.449112 best dqsien dly found for B1: ( 1, 2, 28)
5830 22:20:15.452069 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5831 22:20:15.455775 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5832 22:20:15.455857
5833 22:20:15.458845 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5834 22:20:15.462266 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5835 22:20:15.465523 [Gating] SW calibration Done
5836 22:20:15.465605 ==
5837 22:20:15.468894 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 22:20:15.472339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 22:20:15.472421 ==
5840 22:20:15.475505 RX Vref Scan: 0
5841 22:20:15.475589
5842 22:20:15.475661 RX Vref 0 -> 0, step: 1
5843 22:20:15.475737
5844 22:20:15.478849 RX Delay -80 -> 252, step: 8
5845 22:20:15.485110 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5846 22:20:15.488757 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5847 22:20:15.491999 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5848 22:20:15.495110 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5849 22:20:15.498625 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5850 22:20:15.502204 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5851 22:20:15.508209 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5852 22:20:15.511570 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5853 22:20:15.515042 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5854 22:20:15.518264 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5855 22:20:15.521581 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5856 22:20:15.524704 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5857 22:20:15.531391 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5858 22:20:15.534723 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5859 22:20:15.538060 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5860 22:20:15.541095 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5861 22:20:15.541177 ==
5862 22:20:15.544646 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 22:20:15.551027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 22:20:15.551110 ==
5865 22:20:15.551175 DQS Delay:
5866 22:20:15.551236 DQS0 = 0, DQS1 = 0
5867 22:20:15.554773 DQM Delay:
5868 22:20:15.554854 DQM0 = 101, DQM1 = 97
5869 22:20:15.557634 DQ Delay:
5870 22:20:15.560898 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5871 22:20:15.564460 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5872 22:20:15.567514 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5873 22:20:15.570953 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5874 22:20:15.571035
5875 22:20:15.571100
5876 22:20:15.571160 ==
5877 22:20:15.574338 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 22:20:15.577418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 22:20:15.577501 ==
5880 22:20:15.577566
5881 22:20:15.577626
5882 22:20:15.580673 TX Vref Scan disable
5883 22:20:15.583851 == TX Byte 0 ==
5884 22:20:15.587537 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 22:20:15.590696 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 22:20:15.594120 == TX Byte 1 ==
5887 22:20:15.597125 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5888 22:20:15.600626 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5889 22:20:15.600707 ==
5890 22:20:15.603860 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 22:20:15.610546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 22:20:15.610629 ==
5893 22:20:15.610694
5894 22:20:15.610755
5895 22:20:15.610813 TX Vref Scan disable
5896 22:20:15.614408 == TX Byte 0 ==
5897 22:20:15.617712 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5898 22:20:15.621423 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5899 22:20:15.624450 == TX Byte 1 ==
5900 22:20:15.627992 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5901 22:20:15.634590 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5902 22:20:15.634673
5903 22:20:15.634738 [DATLAT]
5904 22:20:15.634798 Freq=933, CH1 RK1
5905 22:20:15.634856
5906 22:20:15.637440 DATLAT Default: 0xb
5907 22:20:15.637522 0, 0xFFFF, sum = 0
5908 22:20:15.641107 1, 0xFFFF, sum = 0
5909 22:20:15.644124 2, 0xFFFF, sum = 0
5910 22:20:15.644207 3, 0xFFFF, sum = 0
5911 22:20:15.647675 4, 0xFFFF, sum = 0
5912 22:20:15.647758 5, 0xFFFF, sum = 0
5913 22:20:15.651025 6, 0xFFFF, sum = 0
5914 22:20:15.651108 7, 0xFFFF, sum = 0
5915 22:20:15.654340 8, 0xFFFF, sum = 0
5916 22:20:15.654424 9, 0xFFFF, sum = 0
5917 22:20:15.657527 10, 0x0, sum = 1
5918 22:20:15.657610 11, 0x0, sum = 2
5919 22:20:15.660938 12, 0x0, sum = 3
5920 22:20:15.661021 13, 0x0, sum = 4
5921 22:20:15.661087 best_step = 11
5922 22:20:15.661147
5923 22:20:15.664050 ==
5924 22:20:15.667702 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 22:20:15.670571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 22:20:15.670670 ==
5927 22:20:15.670736 RX Vref Scan: 0
5928 22:20:15.670797
5929 22:20:15.674175 RX Vref 0 -> 0, step: 1
5930 22:20:15.674257
5931 22:20:15.677231 RX Delay -45 -> 252, step: 4
5932 22:20:15.683753 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5933 22:20:15.687688 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5934 22:20:15.690370 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5935 22:20:15.693662 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5936 22:20:15.696966 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5937 22:20:15.700244 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5938 22:20:15.707143 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5939 22:20:15.710182 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5940 22:20:15.713554 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5941 22:20:15.716994 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5942 22:20:15.720229 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5943 22:20:15.726592 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5944 22:20:15.730026 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5945 22:20:15.733433 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5946 22:20:15.736460 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5947 22:20:15.739757 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5948 22:20:15.743068 ==
5949 22:20:15.746499 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 22:20:15.749965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 22:20:15.750047 ==
5952 22:20:15.750113 DQS Delay:
5953 22:20:15.753057 DQS0 = 0, DQS1 = 0
5954 22:20:15.753139 DQM Delay:
5955 22:20:15.756606 DQM0 = 104, DQM1 = 97
5956 22:20:15.756687 DQ Delay:
5957 22:20:15.759749 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5958 22:20:15.763286 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5959 22:20:15.766331 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5960 22:20:15.769750 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =106
5961 22:20:15.769832
5962 22:20:15.769895
5963 22:20:15.779658 [DQSOSCAuto] RK1, (LSB)MR18= 0x1dfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
5964 22:20:15.779740 CH1 RK1: MR19=504, MR18=1DFB
5965 22:20:15.786345 CH1_RK1: MR19=0x504, MR18=0x1DFB, DQSOSC=412, MR23=63, INC=63, DEC=42
5966 22:20:15.790031 [RxdqsGatingPostProcess] freq 933
5967 22:20:15.796070 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5968 22:20:15.799578 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 22:20:15.802995 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 22:20:15.805760 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 22:20:15.809373 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 22:20:15.812656 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 22:20:15.815785 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 22:20:15.819211 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 22:20:15.822436 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 22:20:15.822522 Pre-setting of DQS Precalculation
5977 22:20:15.828920 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5978 22:20:15.835520 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5979 22:20:15.842270 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5980 22:20:15.842365
5981 22:20:15.842443
5982 22:20:15.845818 [Calibration Summary] 1866 Mbps
5983 22:20:15.849005 CH 0, Rank 0
5984 22:20:15.849087 SW Impedance : PASS
5985 22:20:15.852036 DUTY Scan : NO K
5986 22:20:15.855287 ZQ Calibration : PASS
5987 22:20:15.855360 Jitter Meter : NO K
5988 22:20:15.858773 CBT Training : PASS
5989 22:20:15.861900 Write leveling : PASS
5990 22:20:15.861983 RX DQS gating : PASS
5991 22:20:15.865346 RX DQ/DQS(RDDQC) : PASS
5992 22:20:15.869045 TX DQ/DQS : PASS
5993 22:20:15.869120 RX DATLAT : PASS
5994 22:20:15.872091 RX DQ/DQS(Engine): PASS
5995 22:20:15.872172 TX OE : NO K
5996 22:20:15.875486 All Pass.
5997 22:20:15.875559
5998 22:20:15.875643 CH 0, Rank 1
5999 22:20:15.878422 SW Impedance : PASS
6000 22:20:15.878525 DUTY Scan : NO K
6001 22:20:15.881658 ZQ Calibration : PASS
6002 22:20:15.885063 Jitter Meter : NO K
6003 22:20:15.885136 CBT Training : PASS
6004 22:20:15.888506 Write leveling : PASS
6005 22:20:15.891887 RX DQS gating : PASS
6006 22:20:15.891971 RX DQ/DQS(RDDQC) : PASS
6007 22:20:15.895497 TX DQ/DQS : PASS
6008 22:20:15.898858 RX DATLAT : PASS
6009 22:20:15.898933 RX DQ/DQS(Engine): PASS
6010 22:20:15.901793 TX OE : NO K
6011 22:20:15.901867 All Pass.
6012 22:20:15.901949
6013 22:20:15.905061 CH 1, Rank 0
6014 22:20:15.905136 SW Impedance : PASS
6015 22:20:15.908689 DUTY Scan : NO K
6016 22:20:15.912090 ZQ Calibration : PASS
6017 22:20:15.912198 Jitter Meter : NO K
6018 22:20:15.914957 CBT Training : PASS
6019 22:20:15.918514 Write leveling : PASS
6020 22:20:15.918618 RX DQS gating : PASS
6021 22:20:15.922071 RX DQ/DQS(RDDQC) : PASS
6022 22:20:15.924964 TX DQ/DQS : PASS
6023 22:20:15.925045 RX DATLAT : PASS
6024 22:20:15.928176 RX DQ/DQS(Engine): PASS
6025 22:20:15.931362 TX OE : NO K
6026 22:20:15.931438 All Pass.
6027 22:20:15.931524
6028 22:20:15.931597 CH 1, Rank 1
6029 22:20:15.935113 SW Impedance : PASS
6030 22:20:15.938516 DUTY Scan : NO K
6031 22:20:15.938590 ZQ Calibration : PASS
6032 22:20:15.941471 Jitter Meter : NO K
6033 22:20:15.941553 CBT Training : PASS
6034 22:20:15.944664 Write leveling : PASS
6035 22:20:15.948096 RX DQS gating : PASS
6036 22:20:15.948169 RX DQ/DQS(RDDQC) : PASS
6037 22:20:15.951618 TX DQ/DQS : PASS
6038 22:20:15.954922 RX DATLAT : PASS
6039 22:20:15.954996 RX DQ/DQS(Engine): PASS
6040 22:20:15.957972 TX OE : NO K
6041 22:20:15.958053 All Pass.
6042 22:20:15.958130
6043 22:20:15.961465 DramC Write-DBI off
6044 22:20:15.964651 PER_BANK_REFRESH: Hybrid Mode
6045 22:20:15.964733 TX_TRACKING: ON
6046 22:20:15.974579 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6047 22:20:15.977673 [FAST_K] Save calibration result to emmc
6048 22:20:15.980997 dramc_set_vcore_voltage set vcore to 650000
6049 22:20:15.984437 Read voltage for 400, 6
6050 22:20:15.984534 Vio18 = 0
6051 22:20:15.984621 Vcore = 650000
6052 22:20:15.987688 Vdram = 0
6053 22:20:15.987767 Vddq = 0
6054 22:20:15.987844 Vmddr = 0
6055 22:20:15.994499 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6056 22:20:15.997934 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6057 22:20:16.001437 MEM_TYPE=3, freq_sel=20
6058 22:20:16.004748 sv_algorithm_assistance_LP4_800
6059 22:20:16.007572 ============ PULL DRAM RESETB DOWN ============
6060 22:20:16.014516 ========== PULL DRAM RESETB DOWN end =========
6061 22:20:16.017553 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6062 22:20:16.020643 ===================================
6063 22:20:16.024141 LPDDR4 DRAM CONFIGURATION
6064 22:20:16.027271 ===================================
6065 22:20:16.027356 EX_ROW_EN[0] = 0x0
6066 22:20:16.030740 EX_ROW_EN[1] = 0x0
6067 22:20:16.030822 LP4Y_EN = 0x0
6068 22:20:16.033930 WORK_FSP = 0x0
6069 22:20:16.034039 WL = 0x2
6070 22:20:16.037552 RL = 0x2
6071 22:20:16.037627 BL = 0x2
6072 22:20:16.040658 RPST = 0x0
6073 22:20:16.040771 RD_PRE = 0x0
6074 22:20:16.044006 WR_PRE = 0x1
6075 22:20:16.047337 WR_PST = 0x0
6076 22:20:16.047412 DBI_WR = 0x0
6077 22:20:16.050428 DBI_RD = 0x0
6078 22:20:16.050504 OTF = 0x1
6079 22:20:16.053908 ===================================
6080 22:20:16.057282 ===================================
6081 22:20:16.057356 ANA top config
6082 22:20:16.060752 ===================================
6083 22:20:16.064029 DLL_ASYNC_EN = 0
6084 22:20:16.067052 ALL_SLAVE_EN = 1
6085 22:20:16.070470 NEW_RANK_MODE = 1
6086 22:20:16.073928 DLL_IDLE_MODE = 1
6087 22:20:16.074014 LP45_APHY_COMB_EN = 1
6088 22:20:16.077090 TX_ODT_DIS = 1
6089 22:20:16.080309 NEW_8X_MODE = 1
6090 22:20:16.083994 ===================================
6091 22:20:16.087120 ===================================
6092 22:20:16.090698 data_rate = 800
6093 22:20:16.093792 CKR = 1
6094 22:20:16.093875 DQ_P2S_RATIO = 4
6095 22:20:16.097148 ===================================
6096 22:20:16.100153 CA_P2S_RATIO = 4
6097 22:20:16.103634 DQ_CA_OPEN = 0
6098 22:20:16.106955 DQ_SEMI_OPEN = 1
6099 22:20:16.110213 CA_SEMI_OPEN = 1
6100 22:20:16.113752 CA_FULL_RATE = 0
6101 22:20:16.113834 DQ_CKDIV4_EN = 0
6102 22:20:16.117571 CA_CKDIV4_EN = 1
6103 22:20:16.120463 CA_PREDIV_EN = 0
6104 22:20:16.123575 PH8_DLY = 0
6105 22:20:16.126684 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6106 22:20:16.130254 DQ_AAMCK_DIV = 0
6107 22:20:16.130336 CA_AAMCK_DIV = 0
6108 22:20:16.133400 CA_ADMCK_DIV = 4
6109 22:20:16.136580 DQ_TRACK_CA_EN = 0
6110 22:20:16.140039 CA_PICK = 800
6111 22:20:16.143336 CA_MCKIO = 400
6112 22:20:16.146937 MCKIO_SEMI = 400
6113 22:20:16.149968 PLL_FREQ = 3016
6114 22:20:16.153080 DQ_UI_PI_RATIO = 32
6115 22:20:16.153161 CA_UI_PI_RATIO = 32
6116 22:20:16.156513 ===================================
6117 22:20:16.160070 ===================================
6118 22:20:16.162976 memory_type:LPDDR4
6119 22:20:16.166247 GP_NUM : 10
6120 22:20:16.166329 SRAM_EN : 1
6121 22:20:16.169532 MD32_EN : 0
6122 22:20:16.173036 ===================================
6123 22:20:16.176453 [ANA_INIT] >>>>>>>>>>>>>>
6124 22:20:16.179606 <<<<<< [CONFIGURE PHASE]: ANA_TX
6125 22:20:16.182630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6126 22:20:16.186280 ===================================
6127 22:20:16.186362 data_rate = 800,PCW = 0X7400
6128 22:20:16.189458 ===================================
6129 22:20:16.192479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6130 22:20:16.199571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 22:20:16.212356 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 22:20:16.215889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6133 22:20:16.219385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6134 22:20:16.222651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6135 22:20:16.226145 [ANA_INIT] flow start
6136 22:20:16.226228 [ANA_INIT] PLL >>>>>>>>
6137 22:20:16.229067 [ANA_INIT] PLL <<<<<<<<
6138 22:20:16.232691 [ANA_INIT] MIDPI >>>>>>>>
6139 22:20:16.235733 [ANA_INIT] MIDPI <<<<<<<<
6140 22:20:16.235815 [ANA_INIT] DLL >>>>>>>>
6141 22:20:16.238851 [ANA_INIT] flow end
6142 22:20:16.242355 ============ LP4 DIFF to SE enter ============
6143 22:20:16.245453 ============ LP4 DIFF to SE exit ============
6144 22:20:16.249104 [ANA_INIT] <<<<<<<<<<<<<
6145 22:20:16.252306 [Flow] Enable top DCM control >>>>>
6146 22:20:16.255593 [Flow] Enable top DCM control <<<<<
6147 22:20:16.258669 Enable DLL master slave shuffle
6148 22:20:16.265414 ==============================================================
6149 22:20:16.265496 Gating Mode config
6150 22:20:16.271861 ==============================================================
6151 22:20:16.271944 Config description:
6152 22:20:16.281662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6153 22:20:16.288288 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6154 22:20:16.295003 SELPH_MODE 0: By rank 1: By Phase
6155 22:20:16.298353 ==============================================================
6156 22:20:16.301678 GAT_TRACK_EN = 0
6157 22:20:16.304947 RX_GATING_MODE = 2
6158 22:20:16.308331 RX_GATING_TRACK_MODE = 2
6159 22:20:16.311370 SELPH_MODE = 1
6160 22:20:16.314903 PICG_EARLY_EN = 1
6161 22:20:16.318125 VALID_LAT_VALUE = 1
6162 22:20:16.324653 ==============================================================
6163 22:20:16.328016 Enter into Gating configuration >>>>
6164 22:20:16.331566 Exit from Gating configuration <<<<
6165 22:20:16.334489 Enter into DVFS_PRE_config >>>>>
6166 22:20:16.344299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6167 22:20:16.347526 Exit from DVFS_PRE_config <<<<<
6168 22:20:16.350907 Enter into PICG configuration >>>>
6169 22:20:16.354293 Exit from PICG configuration <<<<
6170 22:20:16.357418 [RX_INPUT] configuration >>>>>
6171 22:20:16.357501 [RX_INPUT] configuration <<<<<
6172 22:20:16.364057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6173 22:20:16.370999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6174 22:20:16.377425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 22:20:16.380785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 22:20:16.387233 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 22:20:16.394037 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 22:20:16.397465 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6179 22:20:16.400622 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6180 22:20:16.407235 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6181 22:20:16.410705 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6182 22:20:16.413720 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6183 22:20:16.420288 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 22:20:16.423794 ===================================
6185 22:20:16.423876 LPDDR4 DRAM CONFIGURATION
6186 22:20:16.427078 ===================================
6187 22:20:16.430547 EX_ROW_EN[0] = 0x0
6188 22:20:16.433759 EX_ROW_EN[1] = 0x0
6189 22:20:16.433840 LP4Y_EN = 0x0
6190 22:20:16.436881 WORK_FSP = 0x0
6191 22:20:16.436963 WL = 0x2
6192 22:20:16.440284 RL = 0x2
6193 22:20:16.440364 BL = 0x2
6194 22:20:16.443361 RPST = 0x0
6195 22:20:16.443442 RD_PRE = 0x0
6196 22:20:16.446984 WR_PRE = 0x1
6197 22:20:16.447066 WR_PST = 0x0
6198 22:20:16.449995 DBI_WR = 0x0
6199 22:20:16.450077 DBI_RD = 0x0
6200 22:20:16.453314 OTF = 0x1
6201 22:20:16.456862 ===================================
6202 22:20:16.460072 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6203 22:20:16.463295 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6204 22:20:16.470040 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 22:20:16.472993 ===================================
6206 22:20:16.473075 LPDDR4 DRAM CONFIGURATION
6207 22:20:16.476473 ===================================
6208 22:20:16.479913 EX_ROW_EN[0] = 0x10
6209 22:20:16.483080 EX_ROW_EN[1] = 0x0
6210 22:20:16.483171 LP4Y_EN = 0x0
6211 22:20:16.486064 WORK_FSP = 0x0
6212 22:20:16.486145 WL = 0x2
6213 22:20:16.489554 RL = 0x2
6214 22:20:16.489635 BL = 0x2
6215 22:20:16.492900 RPST = 0x0
6216 22:20:16.492982 RD_PRE = 0x0
6217 22:20:16.496362 WR_PRE = 0x1
6218 22:20:16.496443 WR_PST = 0x0
6219 22:20:16.499521 DBI_WR = 0x0
6220 22:20:16.499603 DBI_RD = 0x0
6221 22:20:16.502898 OTF = 0x1
6222 22:20:16.506014 ===================================
6223 22:20:16.512924 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6224 22:20:16.516212 nWR fixed to 30
6225 22:20:16.519030 [ModeRegInit_LP4] CH0 RK0
6226 22:20:16.519112 [ModeRegInit_LP4] CH0 RK1
6227 22:20:16.522436 [ModeRegInit_LP4] CH1 RK0
6228 22:20:16.525855 [ModeRegInit_LP4] CH1 RK1
6229 22:20:16.525936 match AC timing 19
6230 22:20:16.532988 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6231 22:20:16.535632 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6232 22:20:16.539010 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6233 22:20:16.545883 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6234 22:20:16.548999 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6235 22:20:16.549082 ==
6236 22:20:16.552087 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 22:20:16.555446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 22:20:16.555530 ==
6239 22:20:16.562308 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 22:20:16.568559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 22:20:16.572090 [CA 0] Center 36 (8~64) winsize 57
6242 22:20:16.575253 [CA 1] Center 36 (8~64) winsize 57
6243 22:20:16.578865 [CA 2] Center 36 (8~64) winsize 57
6244 22:20:16.582037 [CA 3] Center 36 (8~64) winsize 57
6245 22:20:16.582111 [CA 4] Center 36 (8~64) winsize 57
6246 22:20:16.585234 [CA 5] Center 36 (8~64) winsize 57
6247 22:20:16.585306
6248 22:20:16.592323 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 22:20:16.592405
6250 22:20:16.595693 [CATrainingPosCal] consider 1 rank data
6251 22:20:16.598517 u2DelayCellTimex100 = 270/100 ps
6252 22:20:16.601966 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 22:20:16.605420 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 22:20:16.608414 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 22:20:16.611738 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 22:20:16.615015 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 22:20:16.618484 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 22:20:16.618556
6259 22:20:16.621849 CA PerBit enable=1, Macro0, CA PI delay=36
6260 22:20:16.621920
6261 22:20:16.625311 [CBTSetCACLKResult] CA Dly = 36
6262 22:20:16.628252 CS Dly: 1 (0~32)
6263 22:20:16.628321 ==
6264 22:20:16.631688 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 22:20:16.635321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 22:20:16.635396 ==
6267 22:20:16.641644 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 22:20:16.648321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6269 22:20:16.648399 [CA 0] Center 36 (8~64) winsize 57
6270 22:20:16.651950 [CA 1] Center 36 (8~64) winsize 57
6271 22:20:16.654818 [CA 2] Center 36 (8~64) winsize 57
6272 22:20:16.658274 [CA 3] Center 36 (8~64) winsize 57
6273 22:20:16.661478 [CA 4] Center 36 (8~64) winsize 57
6274 22:20:16.664799 [CA 5] Center 36 (8~64) winsize 57
6275 22:20:16.664885
6276 22:20:16.667939 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6277 22:20:16.668009
6278 22:20:16.671323 [CATrainingPosCal] consider 2 rank data
6279 22:20:16.675045 u2DelayCellTimex100 = 270/100 ps
6280 22:20:16.677821 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 22:20:16.684326 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 22:20:16.687655 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 22:20:16.691381 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 22:20:16.694528 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 22:20:16.697688 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 22:20:16.697770
6287 22:20:16.701066 CA PerBit enable=1, Macro0, CA PI delay=36
6288 22:20:16.701149
6289 22:20:16.704122 [CBTSetCACLKResult] CA Dly = 36
6290 22:20:16.707556 CS Dly: 1 (0~32)
6291 22:20:16.707638
6292 22:20:16.710862 ----->DramcWriteLeveling(PI) begin...
6293 22:20:16.710944 ==
6294 22:20:16.714117 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 22:20:16.717629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 22:20:16.717712 ==
6297 22:20:16.721108 Write leveling (Byte 0): 40 => 8
6298 22:20:16.724005 Write leveling (Byte 1): 32 => 0
6299 22:20:16.727197 DramcWriteLeveling(PI) end<-----
6300 22:20:16.727279
6301 22:20:16.727343 ==
6302 22:20:16.730567 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 22:20:16.734101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 22:20:16.734184 ==
6305 22:20:16.737199 [Gating] SW mode calibration
6306 22:20:16.744116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6307 22:20:16.750386 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6308 22:20:16.753972 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 22:20:16.757364 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 22:20:16.763960 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 22:20:16.766960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 22:20:16.770820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 22:20:16.777111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 22:20:16.780350 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 22:20:16.783786 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 22:20:16.790253 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 22:20:16.790336 Total UI for P1: 0, mck2ui 16
6318 22:20:16.797040 best dqsien dly found for B0: ( 0, 14, 24)
6319 22:20:16.797121 Total UI for P1: 0, mck2ui 16
6320 22:20:16.803347 best dqsien dly found for B1: ( 0, 14, 24)
6321 22:20:16.806877 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6322 22:20:16.810153 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6323 22:20:16.810224
6324 22:20:16.813225 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 22:20:16.816465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 22:20:16.819986 [Gating] SW calibration Done
6327 22:20:16.820058 ==
6328 22:20:16.823059 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 22:20:16.826358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 22:20:16.826428 ==
6331 22:20:16.830051 RX Vref Scan: 0
6332 22:20:16.830122
6333 22:20:16.832696 RX Vref 0 -> 0, step: 1
6334 22:20:16.832774
6335 22:20:16.832838 RX Delay -410 -> 252, step: 16
6336 22:20:16.839744 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6337 22:20:16.842982 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6338 22:20:16.846575 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6339 22:20:16.852679 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6340 22:20:16.855975 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6341 22:20:16.859264 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6342 22:20:16.862858 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6343 22:20:16.869114 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6344 22:20:16.872460 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6345 22:20:16.875667 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6346 22:20:16.878988 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6347 22:20:16.885855 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6348 22:20:16.888742 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6349 22:20:16.892419 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6350 22:20:16.895472 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6351 22:20:16.902024 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6352 22:20:16.902096 ==
6353 22:20:16.905211 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 22:20:16.908817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 22:20:16.908903 ==
6356 22:20:16.908961 DQS Delay:
6357 22:20:16.912053 DQS0 = 19, DQS1 = 43
6358 22:20:16.912120 DQM Delay:
6359 22:20:16.915058 DQM0 = 5, DQM1 = 15
6360 22:20:16.915124 DQ Delay:
6361 22:20:16.918491 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6362 22:20:16.922157 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6363 22:20:16.925145 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6364 22:20:16.928360 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6365 22:20:16.928427
6366 22:20:16.928483
6367 22:20:16.928538 ==
6368 22:20:16.931811 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 22:20:16.934745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 22:20:16.934814 ==
6371 22:20:16.934870
6372 22:20:16.938258
6373 22:20:16.938322 TX Vref Scan disable
6374 22:20:16.941415 == TX Byte 0 ==
6375 22:20:16.944722 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 22:20:16.948400 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 22:20:16.951650 == TX Byte 1 ==
6378 22:20:16.955059 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 22:20:16.958092 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 22:20:16.958163 ==
6381 22:20:16.961765 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 22:20:16.964734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 22:20:16.967979 ==
6384 22:20:16.968046
6385 22:20:16.968102
6386 22:20:16.968157 TX Vref Scan disable
6387 22:20:16.971506 == TX Byte 0 ==
6388 22:20:16.975061 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 22:20:16.977881 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 22:20:16.981648 == TX Byte 1 ==
6391 22:20:16.984600 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 22:20:16.988035 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 22:20:16.988111
6394 22:20:16.991168 [DATLAT]
6395 22:20:16.991241 Freq=400, CH0 RK0
6396 22:20:16.991346
6397 22:20:16.994386 DATLAT Default: 0xf
6398 22:20:16.994456 0, 0xFFFF, sum = 0
6399 22:20:16.997758 1, 0xFFFF, sum = 0
6400 22:20:16.997827 2, 0xFFFF, sum = 0
6401 22:20:17.001149 3, 0xFFFF, sum = 0
6402 22:20:17.001221 4, 0xFFFF, sum = 0
6403 22:20:17.004567 5, 0xFFFF, sum = 0
6404 22:20:17.004651 6, 0xFFFF, sum = 0
6405 22:20:17.008059 7, 0xFFFF, sum = 0
6406 22:20:17.008131 8, 0xFFFF, sum = 0
6407 22:20:17.011242 9, 0xFFFF, sum = 0
6408 22:20:17.011312 10, 0xFFFF, sum = 0
6409 22:20:17.014409 11, 0xFFFF, sum = 0
6410 22:20:17.017645 12, 0xFFFF, sum = 0
6411 22:20:17.017718 13, 0x0, sum = 1
6412 22:20:17.017777 14, 0x0, sum = 2
6413 22:20:17.020691 15, 0x0, sum = 3
6414 22:20:17.020797 16, 0x0, sum = 4
6415 22:20:17.024182 best_step = 14
6416 22:20:17.024252
6417 22:20:17.024308 ==
6418 22:20:17.027476 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 22:20:17.030943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 22:20:17.031012 ==
6421 22:20:17.034080 RX Vref Scan: 1
6422 22:20:17.034148
6423 22:20:17.034211 RX Vref 0 -> 0, step: 1
6424 22:20:17.037656
6425 22:20:17.037723 RX Delay -327 -> 252, step: 8
6426 22:20:17.037782
6427 22:20:17.040710 Set Vref, RX VrefLevel [Byte0]: 59
6428 22:20:17.043991 [Byte1]: 49
6429 22:20:17.049301
6430 22:20:17.049369 Final RX Vref Byte 0 = 59 to rank0
6431 22:20:17.052425 Final RX Vref Byte 1 = 49 to rank0
6432 22:20:17.055983 Final RX Vref Byte 0 = 59 to rank1
6433 22:20:17.058910 Final RX Vref Byte 1 = 49 to rank1==
6434 22:20:17.062364 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 22:20:17.069221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 22:20:17.069293 ==
6437 22:20:17.069357 DQS Delay:
6438 22:20:17.072200 DQS0 = 28, DQS1 = 48
6439 22:20:17.072272 DQM Delay:
6440 22:20:17.072330 DQM0 = 12, DQM1 = 15
6441 22:20:17.075671 DQ Delay:
6442 22:20:17.078856 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6443 22:20:17.082120 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6444 22:20:17.082190 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6445 22:20:17.088898 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6446 22:20:17.088973
6447 22:20:17.089034
6448 22:20:17.095460 [DQSOSCAuto] RK0, (LSB)MR18= 0xada5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6449 22:20:17.098527 CH0 RK0: MR19=C0C, MR18=ADA5
6450 22:20:17.105348 CH0_RK0: MR19=0xC0C, MR18=0xADA5, DQSOSC=388, MR23=63, INC=392, DEC=261
6451 22:20:17.105443 ==
6452 22:20:17.108481 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 22:20:17.112141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 22:20:17.112222 ==
6455 22:20:17.115091 [Gating] SW mode calibration
6456 22:20:17.121895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 22:20:17.128349 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6458 22:20:17.131966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 22:20:17.135048 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 22:20:17.141632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 22:20:17.144700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 22:20:17.148321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 22:20:17.155326 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 22:20:17.158699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 22:20:17.161656 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 22:20:17.168216 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 22:20:17.168292 Total UI for P1: 0, mck2ui 16
6468 22:20:17.174728 best dqsien dly found for B0: ( 0, 14, 24)
6469 22:20:17.174801 Total UI for P1: 0, mck2ui 16
6470 22:20:17.181134 best dqsien dly found for B1: ( 0, 14, 24)
6471 22:20:17.184608 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6472 22:20:17.187860 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6473 22:20:17.187930
6474 22:20:17.191224 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 22:20:17.194640 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 22:20:17.197973 [Gating] SW calibration Done
6477 22:20:17.198045 ==
6478 22:20:17.201382 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 22:20:17.204157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 22:20:17.204229 ==
6481 22:20:17.207793 RX Vref Scan: 0
6482 22:20:17.207863
6483 22:20:17.207932 RX Vref 0 -> 0, step: 1
6484 22:20:17.210917
6485 22:20:17.210988 RX Delay -410 -> 252, step: 16
6486 22:20:17.217634 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6487 22:20:17.221141 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6488 22:20:17.224120 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6489 22:20:17.227556 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6490 22:20:17.234269 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6491 22:20:17.237354 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6492 22:20:17.240740 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6493 22:20:17.244331 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6494 22:20:17.250637 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6495 22:20:17.253780 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6496 22:20:17.257285 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6497 22:20:17.263878 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6498 22:20:17.267220 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6499 22:20:17.270777 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6500 22:20:17.274068 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6501 22:20:17.280446 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6502 22:20:17.280521 ==
6503 22:20:17.283821 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 22:20:17.287093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 22:20:17.287175 ==
6506 22:20:17.287237 DQS Delay:
6507 22:20:17.290107 DQS0 = 27, DQS1 = 43
6508 22:20:17.290179 DQM Delay:
6509 22:20:17.293425 DQM0 = 9, DQM1 = 15
6510 22:20:17.293503 DQ Delay:
6511 22:20:17.297040 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6512 22:20:17.300055 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6513 22:20:17.303556 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6514 22:20:17.306607 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6515 22:20:17.306689
6516 22:20:17.306753
6517 22:20:17.306812 ==
6518 22:20:17.310235 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 22:20:17.313647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 22:20:17.313730 ==
6521 22:20:17.313795
6522 22:20:17.313854
6523 22:20:17.317014 TX Vref Scan disable
6524 22:20:17.317096 == TX Byte 0 ==
6525 22:20:17.323382 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6526 22:20:17.326498 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6527 22:20:17.326580 == TX Byte 1 ==
6528 22:20:17.333168 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6529 22:20:17.336795 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6530 22:20:17.336892 ==
6531 22:20:17.339968 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 22:20:17.343059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 22:20:17.343141 ==
6534 22:20:17.343205
6535 22:20:17.343264
6536 22:20:17.346729 TX Vref Scan disable
6537 22:20:17.350038 == TX Byte 0 ==
6538 22:20:17.353448 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6539 22:20:17.356500 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6540 22:20:17.356582 == TX Byte 1 ==
6541 22:20:17.363568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6542 22:20:17.366271 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6543 22:20:17.366352
6544 22:20:17.366416 [DATLAT]
6545 22:20:17.369616 Freq=400, CH0 RK1
6546 22:20:17.369698
6547 22:20:17.369763 DATLAT Default: 0xe
6548 22:20:17.373120 0, 0xFFFF, sum = 0
6549 22:20:17.373203 1, 0xFFFF, sum = 0
6550 22:20:17.376349 2, 0xFFFF, sum = 0
6551 22:20:17.376431 3, 0xFFFF, sum = 0
6552 22:20:17.379780 4, 0xFFFF, sum = 0
6553 22:20:17.382941 5, 0xFFFF, sum = 0
6554 22:20:17.383024 6, 0xFFFF, sum = 0
6555 22:20:17.386454 7, 0xFFFF, sum = 0
6556 22:20:17.386538 8, 0xFFFF, sum = 0
6557 22:20:17.389977 9, 0xFFFF, sum = 0
6558 22:20:17.390061 10, 0xFFFF, sum = 0
6559 22:20:17.392657 11, 0xFFFF, sum = 0
6560 22:20:17.392740 12, 0xFFFF, sum = 0
6561 22:20:17.396199 13, 0x0, sum = 1
6562 22:20:17.396283 14, 0x0, sum = 2
6563 22:20:17.399310 15, 0x0, sum = 3
6564 22:20:17.399393 16, 0x0, sum = 4
6565 22:20:17.402609 best_step = 14
6566 22:20:17.402691
6567 22:20:17.402756 ==
6568 22:20:17.406326 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 22:20:17.409472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 22:20:17.409555 ==
6571 22:20:17.409620 RX Vref Scan: 0
6572 22:20:17.412625
6573 22:20:17.412706 RX Vref 0 -> 0, step: 1
6574 22:20:17.412793
6575 22:20:17.415916 RX Delay -327 -> 252, step: 8
6576 22:20:17.423464 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6577 22:20:17.426665 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6578 22:20:17.430063 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6579 22:20:17.436349 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6580 22:20:17.440169 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6581 22:20:17.443162 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6582 22:20:17.446438 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6583 22:20:17.449834 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6584 22:20:17.456431 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6585 22:20:17.459909 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6586 22:20:17.462935 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6587 22:20:17.469612 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6588 22:20:17.473080 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6589 22:20:17.476359 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6590 22:20:17.479786 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6591 22:20:17.486139 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6592 22:20:17.486343 ==
6593 22:20:17.489413 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 22:20:17.492713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 22:20:17.493037 ==
6596 22:20:17.493276 DQS Delay:
6597 22:20:17.496279 DQS0 = 28, DQS1 = 40
6598 22:20:17.496580 DQM Delay:
6599 22:20:17.499571 DQM0 = 10, DQM1 = 12
6600 22:20:17.499960 DQ Delay:
6601 22:20:17.502829 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6602 22:20:17.506076 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6603 22:20:17.509496 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6604 22:20:17.513050 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6605 22:20:17.513609
6606 22:20:17.514042
6607 22:20:17.519391 [DQSOSCAuto] RK1, (LSB)MR18= 0xb66b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6608 22:20:17.522921 CH0 RK1: MR19=C0C, MR18=B66B
6609 22:20:17.529217 CH0_RK1: MR19=0xC0C, MR18=0xB66B, DQSOSC=387, MR23=63, INC=394, DEC=262
6610 22:20:17.532709 [RxdqsGatingPostProcess] freq 400
6611 22:20:17.539184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6612 22:20:17.542379 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 22:20:17.545691 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 22:20:17.549049 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 22:20:17.552350 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 22:20:17.553053 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 22:20:17.555749 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 22:20:17.558834 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 22:20:17.562345 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 22:20:17.565931 Pre-setting of DQS Precalculation
6621 22:20:17.572788 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6622 22:20:17.573542 ==
6623 22:20:17.575924 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 22:20:17.578757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 22:20:17.579220 ==
6626 22:20:17.585221 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 22:20:17.591822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6628 22:20:17.595037 [CA 0] Center 36 (8~64) winsize 57
6629 22:20:17.598309 [CA 1] Center 36 (8~64) winsize 57
6630 22:20:17.598423 [CA 2] Center 36 (8~64) winsize 57
6631 22:20:17.601313 [CA 3] Center 36 (8~64) winsize 57
6632 22:20:17.604852 [CA 4] Center 36 (8~64) winsize 57
6633 22:20:17.607840 [CA 5] Center 36 (8~64) winsize 57
6634 22:20:17.607948
6635 22:20:17.611277 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6636 22:20:17.614879
6637 22:20:17.618059 [CATrainingPosCal] consider 1 rank data
6638 22:20:17.618170 u2DelayCellTimex100 = 270/100 ps
6639 22:20:17.624457 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 22:20:17.627969 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 22:20:17.631126 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 22:20:17.634542 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 22:20:17.637597 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 22:20:17.641379 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 22:20:17.641459
6646 22:20:17.644231 CA PerBit enable=1, Macro0, CA PI delay=36
6647 22:20:17.644334
6648 22:20:17.647563 [CBTSetCACLKResult] CA Dly = 36
6649 22:20:17.651040 CS Dly: 1 (0~32)
6650 22:20:17.651136 ==
6651 22:20:17.654353 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 22:20:17.657506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 22:20:17.657610 ==
6654 22:20:17.664079 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 22:20:17.667398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6656 22:20:17.670795 [CA 0] Center 36 (8~64) winsize 57
6657 22:20:17.674284 [CA 1] Center 36 (8~64) winsize 57
6658 22:20:17.677498 [CA 2] Center 36 (8~64) winsize 57
6659 22:20:17.681244 [CA 3] Center 36 (8~64) winsize 57
6660 22:20:17.683835 [CA 4] Center 36 (8~64) winsize 57
6661 22:20:17.687143 [CA 5] Center 36 (8~64) winsize 57
6662 22:20:17.687241
6663 22:20:17.690620 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6664 22:20:17.690717
6665 22:20:17.693932 [CATrainingPosCal] consider 2 rank data
6666 22:20:17.697398 u2DelayCellTimex100 = 270/100 ps
6667 22:20:17.700654 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 22:20:17.706889 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 22:20:17.710581 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 22:20:17.713902 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 22:20:17.717298 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 22:20:17.720294 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 22:20:17.720403
6674 22:20:17.723599 CA PerBit enable=1, Macro0, CA PI delay=36
6675 22:20:17.723695
6676 22:20:17.726894 [CBTSetCACLKResult] CA Dly = 36
6677 22:20:17.727026 CS Dly: 1 (0~32)
6678 22:20:17.730041
6679 22:20:17.733499 ----->DramcWriteLeveling(PI) begin...
6680 22:20:17.733588 ==
6681 22:20:17.737173 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 22:20:17.740081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 22:20:17.740179 ==
6684 22:20:17.743362 Write leveling (Byte 0): 40 => 8
6685 22:20:17.746850 Write leveling (Byte 1): 32 => 0
6686 22:20:17.749837 DramcWriteLeveling(PI) end<-----
6687 22:20:17.749941
6688 22:20:17.750029 ==
6689 22:20:17.753533 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 22:20:17.756574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 22:20:17.756678 ==
6692 22:20:17.759811 [Gating] SW mode calibration
6693 22:20:17.766736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6694 22:20:17.773254 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6695 22:20:17.776359 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 22:20:17.779745 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 22:20:17.786537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 22:20:17.789605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 22:20:17.792775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 22:20:17.799412 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 22:20:17.802864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 22:20:17.806399 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 22:20:17.812687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 22:20:17.812834 Total UI for P1: 0, mck2ui 16
6705 22:20:17.819375 best dqsien dly found for B0: ( 0, 14, 24)
6706 22:20:17.819479 Total UI for P1: 0, mck2ui 16
6707 22:20:17.826070 best dqsien dly found for B1: ( 0, 14, 24)
6708 22:20:17.829242 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6709 22:20:17.832467 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6710 22:20:17.832564
6711 22:20:17.835896 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 22:20:17.839121 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 22:20:17.842727 [Gating] SW calibration Done
6714 22:20:17.842811 ==
6715 22:20:17.846086 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 22:20:17.849553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 22:20:17.849638 ==
6718 22:20:17.852540 RX Vref Scan: 0
6719 22:20:17.852625
6720 22:20:17.852727 RX Vref 0 -> 0, step: 1
6721 22:20:17.852852
6722 22:20:17.856077 RX Delay -410 -> 252, step: 16
6723 22:20:17.862605 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6724 22:20:17.865757 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6725 22:20:17.869388 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6726 22:20:17.872312 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6727 22:20:17.879157 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6728 22:20:17.882552 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6729 22:20:17.885434 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6730 22:20:17.888896 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6731 22:20:17.895645 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6732 22:20:17.899018 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6733 22:20:17.902469 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6734 22:20:17.905809 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6735 22:20:17.912042 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6736 22:20:17.915408 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6737 22:20:17.918952 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6738 22:20:17.925104 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6739 22:20:17.925178 ==
6740 22:20:17.928383 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 22:20:17.931653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 22:20:17.931752 ==
6743 22:20:17.931842 DQS Delay:
6744 22:20:17.935166 DQS0 = 27, DQS1 = 43
6745 22:20:17.935261 DQM Delay:
6746 22:20:17.938766 DQM0 = 8, DQM1 = 16
6747 22:20:17.938862 DQ Delay:
6748 22:20:17.941937 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6749 22:20:17.944742 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =8
6750 22:20:17.948339 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6751 22:20:17.951598 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6752 22:20:17.951669
6753 22:20:17.951729
6754 22:20:17.951789 ==
6755 22:20:17.955050 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 22:20:17.958067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 22:20:17.958142 ==
6758 22:20:17.958202
6759 22:20:17.958258
6760 22:20:17.961604 TX Vref Scan disable
6761 22:20:17.961699 == TX Byte 0 ==
6762 22:20:17.968448 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 22:20:17.971310 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 22:20:17.971413 == TX Byte 1 ==
6765 22:20:17.978266 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6766 22:20:17.981220 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6767 22:20:17.981294 ==
6768 22:20:17.984667 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 22:20:17.987738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 22:20:17.987814 ==
6771 22:20:17.987875
6772 22:20:17.991193
6773 22:20:17.991262 TX Vref Scan disable
6774 22:20:17.994658 == TX Byte 0 ==
6775 22:20:17.997687 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 22:20:18.001137 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 22:20:18.004119 == TX Byte 1 ==
6778 22:20:18.007502 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6779 22:20:18.011075 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6780 22:20:18.011172
6781 22:20:18.011263 [DATLAT]
6782 22:20:18.014588 Freq=400, CH1 RK0
6783 22:20:18.014685
6784 22:20:18.017397 DATLAT Default: 0xf
6785 22:20:18.017467 0, 0xFFFF, sum = 0
6786 22:20:18.020991 1, 0xFFFF, sum = 0
6787 22:20:18.021063 2, 0xFFFF, sum = 0
6788 22:20:18.023856 3, 0xFFFF, sum = 0
6789 22:20:18.023956 4, 0xFFFF, sum = 0
6790 22:20:18.027289 5, 0xFFFF, sum = 0
6791 22:20:18.027360 6, 0xFFFF, sum = 0
6792 22:20:18.030721 7, 0xFFFF, sum = 0
6793 22:20:18.030820 8, 0xFFFF, sum = 0
6794 22:20:18.033964 9, 0xFFFF, sum = 0
6795 22:20:18.034038 10, 0xFFFF, sum = 0
6796 22:20:18.037391 11, 0xFFFF, sum = 0
6797 22:20:18.037466 12, 0xFFFF, sum = 0
6798 22:20:18.040702 13, 0x0, sum = 1
6799 22:20:18.040836 14, 0x0, sum = 2
6800 22:20:18.043960 15, 0x0, sum = 3
6801 22:20:18.044033 16, 0x0, sum = 4
6802 22:20:18.047490 best_step = 14
6803 22:20:18.047585
6804 22:20:18.047672 ==
6805 22:20:18.050583 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 22:20:18.053916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 22:20:18.053991 ==
6808 22:20:18.057217 RX Vref Scan: 1
6809 22:20:18.057286
6810 22:20:18.057346 RX Vref 0 -> 0, step: 1
6811 22:20:18.057403
6812 22:20:18.060288 RX Delay -327 -> 252, step: 8
6813 22:20:18.060383
6814 22:20:18.063693 Set Vref, RX VrefLevel [Byte0]: 53
6815 22:20:18.067029 [Byte1]: 53
6816 22:20:18.071678
6817 22:20:18.071776 Final RX Vref Byte 0 = 53 to rank0
6818 22:20:18.075271 Final RX Vref Byte 1 = 53 to rank0
6819 22:20:18.078311 Final RX Vref Byte 0 = 53 to rank1
6820 22:20:18.081657 Final RX Vref Byte 1 = 53 to rank1==
6821 22:20:18.085000 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 22:20:18.091913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 22:20:18.091991 ==
6824 22:20:18.092054 DQS Delay:
6825 22:20:18.094976 DQS0 = 28, DQS1 = 40
6826 22:20:18.095073 DQM Delay:
6827 22:20:18.095164 DQM0 = 7, DQM1 = 12
6828 22:20:18.098360 DQ Delay:
6829 22:20:18.101611 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6830 22:20:18.101688 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6831 22:20:18.104983 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6832 22:20:18.108089 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6833 22:20:18.108160
6834 22:20:18.108220
6835 22:20:18.117912 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6836 22:20:18.121329 CH1 RK0: MR19=C0C, MR18=94CF
6837 22:20:18.127849 CH1_RK0: MR19=0xC0C, MR18=0x94CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6838 22:20:18.127922 ==
6839 22:20:18.131515 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 22:20:18.134909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 22:20:18.134982 ==
6842 22:20:18.138074 [Gating] SW mode calibration
6843 22:20:18.144387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6844 22:20:18.151078 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6845 22:20:18.154625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 22:20:18.157642 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 22:20:18.164409 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 22:20:18.167960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 22:20:18.171195 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 22:20:18.177320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 22:20:18.180942 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 22:20:18.183916 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 22:20:18.190628 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 22:20:18.190705 Total UI for P1: 0, mck2ui 16
6855 22:20:18.197453 best dqsien dly found for B0: ( 0, 14, 24)
6856 22:20:18.197565 Total UI for P1: 0, mck2ui 16
6857 22:20:18.200546 best dqsien dly found for B1: ( 0, 14, 24)
6858 22:20:18.207429 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6859 22:20:18.210666 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6860 22:20:18.210765
6861 22:20:18.213832 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 22:20:18.217085 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 22:20:18.220494 [Gating] SW calibration Done
6864 22:20:18.220588 ==
6865 22:20:18.223916 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 22:20:18.226991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 22:20:18.227086 ==
6868 22:20:18.230382 RX Vref Scan: 0
6869 22:20:18.230475
6870 22:20:18.230562 RX Vref 0 -> 0, step: 1
6871 22:20:18.230647
6872 22:20:18.233788 RX Delay -410 -> 252, step: 16
6873 22:20:18.240203 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6874 22:20:18.243468 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6875 22:20:18.247040 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6876 22:20:18.250234 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6877 22:20:18.256841 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6878 22:20:18.260010 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6879 22:20:18.263506 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6880 22:20:18.266715 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6881 22:20:18.273479 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6882 22:20:18.276772 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6883 22:20:18.280056 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6884 22:20:18.283055 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6885 22:20:18.289587 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6886 22:20:18.292832 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6887 22:20:18.296404 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6888 22:20:18.302915 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6889 22:20:18.303020 ==
6890 22:20:18.306089 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 22:20:18.309652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 22:20:18.309748 ==
6893 22:20:18.309837 DQS Delay:
6894 22:20:18.312824 DQS0 = 35, DQS1 = 43
6895 22:20:18.312892 DQM Delay:
6896 22:20:18.316438 DQM0 = 16, DQM1 = 19
6897 22:20:18.316533 DQ Delay:
6898 22:20:18.319721 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6899 22:20:18.322828 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6900 22:20:18.325925 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6901 22:20:18.329471 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6902 22:20:18.329541
6903 22:20:18.329601
6904 22:20:18.329659 ==
6905 22:20:18.332662 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 22:20:18.336047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 22:20:18.336141 ==
6908 22:20:18.336231
6909 22:20:18.336318
6910 22:20:18.339467 TX Vref Scan disable
6911 22:20:18.342627 == TX Byte 0 ==
6912 22:20:18.345909 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6913 22:20:18.349338 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6914 22:20:18.352895 == TX Byte 1 ==
6915 22:20:18.355819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6916 22:20:18.359037 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6917 22:20:18.359132 ==
6918 22:20:18.362195 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 22:20:18.365649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 22:20:18.365721 ==
6921 22:20:18.369170
6922 22:20:18.369240
6923 22:20:18.369299 TX Vref Scan disable
6924 22:20:18.372148 == TX Byte 0 ==
6925 22:20:18.375513 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6926 22:20:18.378890 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6927 22:20:18.382186 == TX Byte 1 ==
6928 22:20:18.385503 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6929 22:20:18.389030 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6930 22:20:18.389128
6931 22:20:18.389216 [DATLAT]
6932 22:20:18.392187 Freq=400, CH1 RK1
6933 22:20:18.392282
6934 22:20:18.396047 DATLAT Default: 0xe
6935 22:20:18.396141 0, 0xFFFF, sum = 0
6936 22:20:18.398620 1, 0xFFFF, sum = 0
6937 22:20:18.398724 2, 0xFFFF, sum = 0
6938 22:20:18.402188 3, 0xFFFF, sum = 0
6939 22:20:18.402258 4, 0xFFFF, sum = 0
6940 22:20:18.405314 5, 0xFFFF, sum = 0
6941 22:20:18.405382 6, 0xFFFF, sum = 0
6942 22:20:18.408569 7, 0xFFFF, sum = 0
6943 22:20:18.408662 8, 0xFFFF, sum = 0
6944 22:20:18.412027 9, 0xFFFF, sum = 0
6945 22:20:18.412106 10, 0xFFFF, sum = 0
6946 22:20:18.415355 11, 0xFFFF, sum = 0
6947 22:20:18.415450 12, 0xFFFF, sum = 0
6948 22:20:18.418482 13, 0x0, sum = 1
6949 22:20:18.418576 14, 0x0, sum = 2
6950 22:20:18.421942 15, 0x0, sum = 3
6951 22:20:18.422008 16, 0x0, sum = 4
6952 22:20:18.425311 best_step = 14
6953 22:20:18.425376
6954 22:20:18.425435 ==
6955 22:20:18.428600 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 22:20:18.432268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 22:20:18.432361 ==
6958 22:20:18.435282 RX Vref Scan: 0
6959 22:20:18.435348
6960 22:20:18.435405 RX Vref 0 -> 0, step: 1
6961 22:20:18.435461
6962 22:20:18.438542 RX Delay -327 -> 252, step: 8
6963 22:20:18.446080 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6964 22:20:18.449379 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6965 22:20:18.452587 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6966 22:20:18.459180 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6967 22:20:18.462547 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6968 22:20:18.465992 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6969 22:20:18.469169 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6970 22:20:18.475669 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6971 22:20:18.479216 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6972 22:20:18.482284 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6973 22:20:18.485590 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6974 22:20:18.492086 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6975 22:20:18.495648 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6976 22:20:18.499222 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6977 22:20:18.502154 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6978 22:20:18.509043 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6979 22:20:18.509134 ==
6980 22:20:18.512143 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 22:20:18.515148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 22:20:18.515256 ==
6983 22:20:18.515348 DQS Delay:
6984 22:20:18.518662 DQS0 = 32, DQS1 = 36
6985 22:20:18.518761 DQM Delay:
6986 22:20:18.522034 DQM0 = 12, DQM1 = 11
6987 22:20:18.522103 DQ Delay:
6988 22:20:18.525428 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6989 22:20:18.528575 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6990 22:20:18.531796 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6991 22:20:18.535013 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6992 22:20:18.535104
6993 22:20:18.535192
6994 22:20:18.544975 [DQSOSCAuto] RK1, (LSB)MR18= 0xa34b, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6995 22:20:18.545071 CH1 RK1: MR19=C0C, MR18=A34B
6996 22:20:18.551758 CH1_RK1: MR19=0xC0C, MR18=0xA34B, DQSOSC=389, MR23=63, INC=390, DEC=260
6997 22:20:18.554999 [RxdqsGatingPostProcess] freq 400
6998 22:20:18.561735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6999 22:20:18.564974 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 22:20:18.568096 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 22:20:18.571625 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 22:20:18.574968 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 22:20:18.578132 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 22:20:18.578201 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 22:20:18.581716 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 22:20:18.584596 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 22:20:18.587796 Pre-setting of DQS Precalculation
7008 22:20:18.594845 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7009 22:20:18.601422 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7010 22:20:18.607574 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7011 22:20:18.607676
7012 22:20:18.607770
7013 22:20:18.610910 [Calibration Summary] 800 Mbps
7014 22:20:18.614161 CH 0, Rank 0
7015 22:20:18.614256 SW Impedance : PASS
7016 22:20:18.617549 DUTY Scan : NO K
7017 22:20:18.617620 ZQ Calibration : PASS
7018 22:20:18.620994 Jitter Meter : NO K
7019 22:20:18.624208 CBT Training : PASS
7020 22:20:18.624304 Write leveling : PASS
7021 22:20:18.627802 RX DQS gating : PASS
7022 22:20:18.630805 RX DQ/DQS(RDDQC) : PASS
7023 22:20:18.630873 TX DQ/DQS : PASS
7024 22:20:18.634366 RX DATLAT : PASS
7025 22:20:18.637815 RX DQ/DQS(Engine): PASS
7026 22:20:18.637886 TX OE : NO K
7027 22:20:18.640742 All Pass.
7028 22:20:18.640876
7029 22:20:18.640966 CH 0, Rank 1
7030 22:20:18.643738 SW Impedance : PASS
7031 22:20:18.643805 DUTY Scan : NO K
7032 22:20:18.647031 ZQ Calibration : PASS
7033 22:20:18.650705 Jitter Meter : NO K
7034 22:20:18.650774 CBT Training : PASS
7035 22:20:18.653564 Write leveling : NO K
7036 22:20:18.656898 RX DQS gating : PASS
7037 22:20:18.656973 RX DQ/DQS(RDDQC) : PASS
7038 22:20:18.660293 TX DQ/DQS : PASS
7039 22:20:18.663756 RX DATLAT : PASS
7040 22:20:18.663851 RX DQ/DQS(Engine): PASS
7041 22:20:18.667083 TX OE : NO K
7042 22:20:18.667154 All Pass.
7043 22:20:18.667217
7044 22:20:18.670508 CH 1, Rank 0
7045 22:20:18.670576 SW Impedance : PASS
7046 22:20:18.673587 DUTY Scan : NO K
7047 22:20:18.676744 ZQ Calibration : PASS
7048 22:20:18.676837 Jitter Meter : NO K
7049 22:20:18.680297 CBT Training : PASS
7050 22:20:18.683299 Write leveling : PASS
7051 22:20:18.683370 RX DQS gating : PASS
7052 22:20:18.686414 RX DQ/DQS(RDDQC) : PASS
7053 22:20:18.689979 TX DQ/DQS : PASS
7054 22:20:18.690050 RX DATLAT : PASS
7055 22:20:18.693313 RX DQ/DQS(Engine): PASS
7056 22:20:18.696827 TX OE : NO K
7057 22:20:18.696923 All Pass.
7058 22:20:18.697010
7059 22:20:18.697096 CH 1, Rank 1
7060 22:20:18.699802 SW Impedance : PASS
7061 22:20:18.703300 DUTY Scan : NO K
7062 22:20:18.703400 ZQ Calibration : PASS
7063 22:20:18.706306 Jitter Meter : NO K
7064 22:20:18.709843 CBT Training : PASS
7065 22:20:18.709944 Write leveling : NO K
7066 22:20:18.713031 RX DQS gating : PASS
7067 22:20:18.713100 RX DQ/DQS(RDDQC) : PASS
7068 22:20:18.716684 TX DQ/DQS : PASS
7069 22:20:18.719496 RX DATLAT : PASS
7070 22:20:18.719593 RX DQ/DQS(Engine): PASS
7071 22:20:18.723124 TX OE : NO K
7072 22:20:18.723220 All Pass.
7073 22:20:18.723307
7074 22:20:18.726468 DramC Write-DBI off
7075 22:20:18.729938 PER_BANK_REFRESH: Hybrid Mode
7076 22:20:18.730006 TX_TRACKING: ON
7077 22:20:18.739462 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7078 22:20:18.742912 [FAST_K] Save calibration result to emmc
7079 22:20:18.746197 dramc_set_vcore_voltage set vcore to 725000
7080 22:20:18.749356 Read voltage for 1600, 0
7081 22:20:18.749425 Vio18 = 0
7082 22:20:18.752744 Vcore = 725000
7083 22:20:18.752877 Vdram = 0
7084 22:20:18.752967 Vddq = 0
7085 22:20:18.753053 Vmddr = 0
7086 22:20:18.759321 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7087 22:20:18.762875 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7088 22:20:18.766246 MEM_TYPE=3, freq_sel=13
7089 22:20:18.769377 sv_algorithm_assistance_LP4_3733
7090 22:20:18.772792 ============ PULL DRAM RESETB DOWN ============
7091 22:20:18.779304 ========== PULL DRAM RESETB DOWN end =========
7092 22:20:18.782325 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7093 22:20:18.785799 ===================================
7094 22:20:18.789203 LPDDR4 DRAM CONFIGURATION
7095 22:20:18.792179 ===================================
7096 22:20:18.792275 EX_ROW_EN[0] = 0x0
7097 22:20:18.795472 EX_ROW_EN[1] = 0x0
7098 22:20:18.795569 LP4Y_EN = 0x0
7099 22:20:18.798817 WORK_FSP = 0x1
7100 22:20:18.802297 WL = 0x5
7101 22:20:18.802396 RL = 0x5
7102 22:20:18.805323 BL = 0x2
7103 22:20:18.805392 RPST = 0x0
7104 22:20:18.809142 RD_PRE = 0x0
7105 22:20:18.809239 WR_PRE = 0x1
7106 22:20:18.812137 WR_PST = 0x1
7107 22:20:18.812233 DBI_WR = 0x0
7108 22:20:18.815366 DBI_RD = 0x0
7109 22:20:18.815465 OTF = 0x1
7110 22:20:18.818554 ===================================
7111 22:20:18.821818 ===================================
7112 22:20:18.825116 ANA top config
7113 22:20:18.828539 ===================================
7114 22:20:18.828608 DLL_ASYNC_EN = 0
7115 22:20:18.831910 ALL_SLAVE_EN = 0
7116 22:20:18.835112 NEW_RANK_MODE = 1
7117 22:20:18.838307 DLL_IDLE_MODE = 1
7118 22:20:18.841938 LP45_APHY_COMB_EN = 1
7119 22:20:18.842036 TX_ODT_DIS = 0
7120 22:20:18.845428 NEW_8X_MODE = 1
7121 22:20:18.848415 ===================================
7122 22:20:18.852016 ===================================
7123 22:20:18.854671 data_rate = 3200
7124 22:20:18.858411 CKR = 1
7125 22:20:18.861463 DQ_P2S_RATIO = 8
7126 22:20:18.864789 ===================================
7127 22:20:18.868240 CA_P2S_RATIO = 8
7128 22:20:18.868338 DQ_CA_OPEN = 0
7129 22:20:18.871771 DQ_SEMI_OPEN = 0
7130 22:20:18.874668 CA_SEMI_OPEN = 0
7131 22:20:18.878220 CA_FULL_RATE = 0
7132 22:20:18.881193 DQ_CKDIV4_EN = 0
7133 22:20:18.884806 CA_CKDIV4_EN = 0
7134 22:20:18.884894 CA_PREDIV_EN = 0
7135 22:20:18.887998 PH8_DLY = 12
7136 22:20:18.891110 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7137 22:20:18.894361 DQ_AAMCK_DIV = 4
7138 22:20:18.897581 CA_AAMCK_DIV = 4
7139 22:20:18.900913 CA_ADMCK_DIV = 4
7140 22:20:18.900992 DQ_TRACK_CA_EN = 0
7141 22:20:18.904252 CA_PICK = 1600
7142 22:20:18.907784 CA_MCKIO = 1600
7143 22:20:18.910867 MCKIO_SEMI = 0
7144 22:20:18.914550 PLL_FREQ = 3068
7145 22:20:18.917354 DQ_UI_PI_RATIO = 32
7146 22:20:18.920916 CA_UI_PI_RATIO = 0
7147 22:20:18.923958 ===================================
7148 22:20:18.927245 ===================================
7149 22:20:18.927343 memory_type:LPDDR4
7150 22:20:18.930692 GP_NUM : 10
7151 22:20:18.933791 SRAM_EN : 1
7152 22:20:18.933861 MD32_EN : 0
7153 22:20:18.937611 ===================================
7154 22:20:18.940570 [ANA_INIT] >>>>>>>>>>>>>>
7155 22:20:18.943941 <<<<<< [CONFIGURE PHASE]: ANA_TX
7156 22:20:18.947236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7157 22:20:18.950333 ===================================
7158 22:20:18.953607 data_rate = 3200,PCW = 0X7600
7159 22:20:18.956800 ===================================
7160 22:20:18.960595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7161 22:20:18.963613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 22:20:18.970190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 22:20:18.973699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7164 22:20:18.980068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7165 22:20:18.983691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7166 22:20:18.983790 [ANA_INIT] flow start
7167 22:20:18.986728 [ANA_INIT] PLL >>>>>>>>
7168 22:20:18.990229 [ANA_INIT] PLL <<<<<<<<
7169 22:20:18.990301 [ANA_INIT] MIDPI >>>>>>>>
7170 22:20:18.993687 [ANA_INIT] MIDPI <<<<<<<<
7171 22:20:18.996737 [ANA_INIT] DLL >>>>>>>>
7172 22:20:18.996874 [ANA_INIT] DLL <<<<<<<<
7173 22:20:18.999979 [ANA_INIT] flow end
7174 22:20:19.003439 ============ LP4 DIFF to SE enter ============
7175 22:20:19.006657 ============ LP4 DIFF to SE exit ============
7176 22:20:19.010128 [ANA_INIT] <<<<<<<<<<<<<
7177 22:20:19.013536 [Flow] Enable top DCM control >>>>>
7178 22:20:19.016710 [Flow] Enable top DCM control <<<<<
7179 22:20:19.019848 Enable DLL master slave shuffle
7180 22:20:19.026401 ==============================================================
7181 22:20:19.026500 Gating Mode config
7182 22:20:19.033041 ==============================================================
7183 22:20:19.033138 Config description:
7184 22:20:19.043364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7185 22:20:19.049626 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7186 22:20:19.056199 SELPH_MODE 0: By rank 1: By Phase
7187 22:20:19.059596 ==============================================================
7188 22:20:19.063013 GAT_TRACK_EN = 1
7189 22:20:19.066200 RX_GATING_MODE = 2
7190 22:20:19.069309 RX_GATING_TRACK_MODE = 2
7191 22:20:19.072951 SELPH_MODE = 1
7192 22:20:19.076279 PICG_EARLY_EN = 1
7193 22:20:19.079286 VALID_LAT_VALUE = 1
7194 22:20:19.086184 ==============================================================
7195 22:20:19.089271 Enter into Gating configuration >>>>
7196 22:20:19.092470 Exit from Gating configuration <<<<
7197 22:20:19.096141 Enter into DVFS_PRE_config >>>>>
7198 22:20:19.105953 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7199 22:20:19.109329 Exit from DVFS_PRE_config <<<<<
7200 22:20:19.112485 Enter into PICG configuration >>>>
7201 22:20:19.116043 Exit from PICG configuration <<<<
7202 22:20:19.119413 [RX_INPUT] configuration >>>>>
7203 22:20:19.119499 [RX_INPUT] configuration <<<<<
7204 22:20:19.125900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7205 22:20:19.132408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7206 22:20:19.138912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 22:20:19.142062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 22:20:19.148642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 22:20:19.155396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 22:20:19.158724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7211 22:20:19.165519 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7212 22:20:19.168406 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7213 22:20:19.171954 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7214 22:20:19.175163 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7215 22:20:19.181539 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 22:20:19.184845 ===================================
7217 22:20:19.184929 LPDDR4 DRAM CONFIGURATION
7218 22:20:19.188353 ===================================
7219 22:20:19.191399 EX_ROW_EN[0] = 0x0
7220 22:20:19.194915 EX_ROW_EN[1] = 0x0
7221 22:20:19.194983 LP4Y_EN = 0x0
7222 22:20:19.198060 WORK_FSP = 0x1
7223 22:20:19.198127 WL = 0x5
7224 22:20:19.201527 RL = 0x5
7225 22:20:19.201602 BL = 0x2
7226 22:20:19.204919 RPST = 0x0
7227 22:20:19.204990 RD_PRE = 0x0
7228 22:20:19.207988 WR_PRE = 0x1
7229 22:20:19.208056 WR_PST = 0x1
7230 22:20:19.211647 DBI_WR = 0x0
7231 22:20:19.211743 DBI_RD = 0x0
7232 22:20:19.214531 OTF = 0x1
7233 22:20:19.218361 ===================================
7234 22:20:19.221279 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7235 22:20:19.224787 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7236 22:20:19.231247 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 22:20:19.234506 ===================================
7238 22:20:19.234578 LPDDR4 DRAM CONFIGURATION
7239 22:20:19.237822 ===================================
7240 22:20:19.241035 EX_ROW_EN[0] = 0x10
7241 22:20:19.244544 EX_ROW_EN[1] = 0x0
7242 22:20:19.244612 LP4Y_EN = 0x0
7243 22:20:19.247887 WORK_FSP = 0x1
7244 22:20:19.247954 WL = 0x5
7245 22:20:19.251776 RL = 0x5
7246 22:20:19.251843 BL = 0x2
7247 22:20:19.254630 RPST = 0x0
7248 22:20:19.254697 RD_PRE = 0x0
7249 22:20:19.257568 WR_PRE = 0x1
7250 22:20:19.257637 WR_PST = 0x1
7251 22:20:19.260999 DBI_WR = 0x0
7252 22:20:19.261093 DBI_RD = 0x0
7253 22:20:19.264325 OTF = 0x1
7254 22:20:19.267833 ===================================
7255 22:20:19.274366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7256 22:20:19.274463 ==
7257 22:20:19.277812 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 22:20:19.280662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7259 22:20:19.280757 ==
7260 22:20:19.284235 [Duty_Offset_Calibration]
7261 22:20:19.284303 B0:2 B1:0 CA:1
7262 22:20:19.284363
7263 22:20:19.287349 [DutyScan_Calibration_Flow] k_type=0
7264 22:20:19.297346
7265 22:20:19.297442 ==CLK 0==
7266 22:20:19.300846 Final CLK duty delay cell = -4
7267 22:20:19.304028 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7268 22:20:19.307556 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7269 22:20:19.310823 [-4] AVG Duty = 4922%(X100)
7270 22:20:19.310920
7271 22:20:19.314153 CH0 CLK Duty spec in!! Max-Min= 218%
7272 22:20:19.317189 [DutyScan_Calibration_Flow] ====Done====
7273 22:20:19.317258
7274 22:20:19.320479 [DutyScan_Calibration_Flow] k_type=1
7275 22:20:19.336726
7276 22:20:19.336818 ==DQS 0 ==
7277 22:20:19.340280 Final DQS duty delay cell = 0
7278 22:20:19.343415 [0] MAX Duty = 5249%(X100), DQS PI = 32
7279 22:20:19.347056 [0] MIN Duty = 4969%(X100), DQS PI = 0
7280 22:20:19.347128 [0] AVG Duty = 5109%(X100)
7281 22:20:19.350191
7282 22:20:19.350258 ==DQS 1 ==
7283 22:20:19.353365 Final DQS duty delay cell = -4
7284 22:20:19.356726 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7285 22:20:19.360298 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7286 22:20:19.363359 [-4] AVG Duty = 5000%(X100)
7287 22:20:19.363455
7288 22:20:19.367036 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7289 22:20:19.367107
7290 22:20:19.370236 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7291 22:20:19.373633 [DutyScan_Calibration_Flow] ====Done====
7292 22:20:19.373728
7293 22:20:19.376496 [DutyScan_Calibration_Flow] k_type=3
7294 22:20:19.393493
7295 22:20:19.393569 ==DQM 0 ==
7296 22:20:19.396973 Final DQM duty delay cell = 0
7297 22:20:19.399911 [0] MAX Duty = 5093%(X100), DQS PI = 26
7298 22:20:19.403361 [0] MIN Duty = 4813%(X100), DQS PI = 50
7299 22:20:19.406874 [0] AVG Duty = 4953%(X100)
7300 22:20:19.406979
7301 22:20:19.407109 ==DQM 1 ==
7302 22:20:19.409862 Final DQM duty delay cell = -4
7303 22:20:19.413263 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7304 22:20:19.416670 [-4] MIN Duty = 4751%(X100), DQS PI = 18
7305 22:20:19.419977 [-4] AVG Duty = 4875%(X100)
7306 22:20:19.420044
7307 22:20:19.423264 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7308 22:20:19.423343
7309 22:20:19.426401 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7310 22:20:19.429787 [DutyScan_Calibration_Flow] ====Done====
7311 22:20:19.429880
7312 22:20:19.432986 [DutyScan_Calibration_Flow] k_type=2
7313 22:20:19.450973
7314 22:20:19.451062 ==DQ 0 ==
7315 22:20:19.454373 Final DQ duty delay cell = 0
7316 22:20:19.457508 [0] MAX Duty = 5156%(X100), DQS PI = 36
7317 22:20:19.461056 [0] MIN Duty = 5000%(X100), DQS PI = 18
7318 22:20:19.463998 [0] AVG Duty = 5078%(X100)
7319 22:20:19.464115
7320 22:20:19.464204 ==DQ 1 ==
7321 22:20:19.467373 Final DQ duty delay cell = 0
7322 22:20:19.470993 [0] MAX Duty = 4969%(X100), DQS PI = 4
7323 22:20:19.473849 [0] MIN Duty = 4875%(X100), DQS PI = 10
7324 22:20:19.473970 [0] AVG Duty = 4922%(X100)
7325 22:20:19.477201
7326 22:20:19.480807 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7327 22:20:19.480887
7328 22:20:19.484025 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7329 22:20:19.487205 [DutyScan_Calibration_Flow] ====Done====
7330 22:20:19.487277 ==
7331 22:20:19.490487 Dram Type= 6, Freq= 0, CH_1, rank 0
7332 22:20:19.494035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 22:20:19.494114 ==
7334 22:20:19.497393 [Duty_Offset_Calibration]
7335 22:20:19.497485 B0:0 B1:-1 CA:2
7336 22:20:19.497571
7337 22:20:19.500340 [DutyScan_Calibration_Flow] k_type=0
7338 22:20:19.511470
7339 22:20:19.511571 ==CLK 0==
7340 22:20:19.514422 Final CLK duty delay cell = 0
7341 22:20:19.517861 [0] MAX Duty = 5156%(X100), DQS PI = 8
7342 22:20:19.521142 [0] MIN Duty = 4938%(X100), DQS PI = 44
7343 22:20:19.524326 [0] AVG Duty = 5047%(X100)
7344 22:20:19.524404
7345 22:20:19.527585 CH1 CLK Duty spec in!! Max-Min= 218%
7346 22:20:19.530896 [DutyScan_Calibration_Flow] ====Done====
7347 22:20:19.530988
7348 22:20:19.534391 [DutyScan_Calibration_Flow] k_type=1
7349 22:20:19.550763
7350 22:20:19.550836 ==DQS 0 ==
7351 22:20:19.554192 Final DQS duty delay cell = 0
7352 22:20:19.557518 [0] MAX Duty = 5124%(X100), DQS PI = 26
7353 22:20:19.561101 [0] MIN Duty = 4969%(X100), DQS PI = 2
7354 22:20:19.564144 [0] AVG Duty = 5046%(X100)
7355 22:20:19.564209
7356 22:20:19.564267 ==DQS 1 ==
7357 22:20:19.567155 Final DQS duty delay cell = 0
7358 22:20:19.570880 [0] MAX Duty = 5187%(X100), DQS PI = 0
7359 22:20:19.574062 [0] MIN Duty = 4844%(X100), DQS PI = 34
7360 22:20:19.577207 [0] AVG Duty = 5015%(X100)
7361 22:20:19.577273
7362 22:20:19.580575 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7363 22:20:19.580638
7364 22:20:19.583775 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7365 22:20:19.587080 [DutyScan_Calibration_Flow] ====Done====
7366 22:20:19.587149
7367 22:20:19.590289 [DutyScan_Calibration_Flow] k_type=3
7368 22:20:19.608452
7369 22:20:19.608552 ==DQM 0 ==
7370 22:20:19.611574 Final DQM duty delay cell = 4
7371 22:20:19.615101 [4] MAX Duty = 5125%(X100), DQS PI = 6
7372 22:20:19.618078 [4] MIN Duty = 4969%(X100), DQS PI = 32
7373 22:20:19.621407 [4] AVG Duty = 5047%(X100)
7374 22:20:19.621474
7375 22:20:19.621532 ==DQM 1 ==
7376 22:20:19.624803 Final DQM duty delay cell = 0
7377 22:20:19.628419 [0] MAX Duty = 5281%(X100), DQS PI = 58
7378 22:20:19.631373 [0] MIN Duty = 4876%(X100), DQS PI = 34
7379 22:20:19.634919 [0] AVG Duty = 5078%(X100)
7380 22:20:19.634987
7381 22:20:19.638194 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7382 22:20:19.638265
7383 22:20:19.641584 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7384 22:20:19.644610 [DutyScan_Calibration_Flow] ====Done====
7385 22:20:19.644736
7386 22:20:19.647955 [DutyScan_Calibration_Flow] k_type=2
7387 22:20:19.665283
7388 22:20:19.665391 ==DQ 0 ==
7389 22:20:19.668919 Final DQ duty delay cell = 0
7390 22:20:19.672035 [0] MAX Duty = 5093%(X100), DQS PI = 22
7391 22:20:19.675290 [0] MIN Duty = 4969%(X100), DQS PI = 46
7392 22:20:19.675390 [0] AVG Duty = 5031%(X100)
7393 22:20:19.678829
7394 22:20:19.678900 ==DQ 1 ==
7395 22:20:19.681690 Final DQ duty delay cell = 0
7396 22:20:19.684924 [0] MAX Duty = 5062%(X100), DQS PI = 2
7397 22:20:19.688395 [0] MIN Duty = 4813%(X100), DQS PI = 34
7398 22:20:19.688463 [0] AVG Duty = 4937%(X100)
7399 22:20:19.691535
7400 22:20:19.694924 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7401 22:20:19.694992
7402 22:20:19.698451 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7403 22:20:19.701312 [DutyScan_Calibration_Flow] ====Done====
7404 22:20:19.704824 nWR fixed to 30
7405 22:20:19.704899 [ModeRegInit_LP4] CH0 RK0
7406 22:20:19.707917 [ModeRegInit_LP4] CH0 RK1
7407 22:20:19.711338 [ModeRegInit_LP4] CH1 RK0
7408 22:20:19.714528 [ModeRegInit_LP4] CH1 RK1
7409 22:20:19.714624 match AC timing 5
7410 22:20:19.721337 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7411 22:20:19.724692 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7412 22:20:19.727643 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7413 22:20:19.734296 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7414 22:20:19.737741 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7415 22:20:19.737813 [MiockJmeterHQA]
7416 22:20:19.737877
7417 22:20:19.741241 [DramcMiockJmeter] u1RxGatingPI = 0
7418 22:20:19.744540 0 : 4252, 4027
7419 22:20:19.744639 4 : 4252, 4027
7420 22:20:19.747646 8 : 4365, 4140
7421 22:20:19.747717 12 : 4252, 4027
7422 22:20:19.750974 16 : 4257, 4032
7423 22:20:19.751080 20 : 4363, 4138
7424 22:20:19.751174 24 : 4253, 4026
7425 22:20:19.754134 28 : 4252, 4027
7426 22:20:19.754204 32 : 4363, 4138
7427 22:20:19.757393 36 : 4252, 4027
7428 22:20:19.757489 40 : 4363, 4138
7429 22:20:19.761094 44 : 4252, 4027
7430 22:20:19.761192 48 : 4252, 4027
7431 22:20:19.764483 52 : 4252, 4027
7432 22:20:19.764555 56 : 4255, 4029
7433 22:20:19.764615 60 : 4363, 4138
7434 22:20:19.767555 64 : 4250, 4027
7435 22:20:19.767654 68 : 4361, 4137
7436 22:20:19.771052 72 : 4363, 4140
7437 22:20:19.771127 76 : 4250, 4026
7438 22:20:19.774081 80 : 4253, 4029
7439 22:20:19.774152 84 : 4361, 4138
7440 22:20:19.774214 88 : 4250, 3575
7441 22:20:19.777751 92 : 4363, 0
7442 22:20:19.777840 96 : 4250, 0
7443 22:20:19.781098 100 : 4252, 0
7444 22:20:19.781172 104 : 4252, 0
7445 22:20:19.781235 108 : 4363, 0
7446 22:20:19.783838 112 : 4360, 0
7447 22:20:19.783909 116 : 4255, 0
7448 22:20:19.787362 120 : 4249, 0
7449 22:20:19.787437 124 : 4250, 0
7450 22:20:19.787497 128 : 4253, 0
7451 22:20:19.790574 132 : 4250, 0
7452 22:20:19.790644 136 : 4250, 0
7453 22:20:19.793830 140 : 4253, 0
7454 22:20:19.793901 144 : 4360, 0
7455 22:20:19.793965 148 : 4361, 0
7456 22:20:19.797124 152 : 4250, 0
7457 22:20:19.797223 156 : 4255, 0
7458 22:20:19.800666 160 : 4360, 0
7459 22:20:19.800775 164 : 4361, 0
7460 22:20:19.800844 168 : 4250, 0
7461 22:20:19.803914 172 : 4250, 0
7462 22:20:19.803987 176 : 4250, 0
7463 22:20:19.804047 180 : 4250, 0
7464 22:20:19.807023 184 : 4249, 0
7465 22:20:19.807121 188 : 4250, 0
7466 22:20:19.810518 192 : 4253, 0
7467 22:20:19.810616 196 : 4363, 0
7468 22:20:19.813939 200 : 4360, 11
7469 22:20:19.814036 204 : 4250, 2729
7470 22:20:19.814126 208 : 4250, 4027
7471 22:20:19.817477 212 : 4253, 4029
7472 22:20:19.817576 216 : 4250, 4027
7473 22:20:19.820204 220 : 4250, 4027
7474 22:20:19.820274 224 : 4248, 4024
7475 22:20:19.823554 228 : 4250, 4027
7476 22:20:19.823653 232 : 4252, 4030
7477 22:20:19.826988 236 : 4361, 4137
7478 22:20:19.827086 240 : 4250, 4027
7479 22:20:19.830038 244 : 4250, 4027
7480 22:20:19.830109 248 : 4364, 4140
7481 22:20:19.833307 252 : 4361, 4138
7482 22:20:19.833377 256 : 4250, 4026
7483 22:20:19.836631 260 : 4250, 4026
7484 22:20:19.836733 264 : 4363, 4140
7485 22:20:19.836845 268 : 4361, 4138
7486 22:20:19.839884 272 : 4250, 4027
7487 22:20:19.839954 276 : 4363, 4140
7488 22:20:19.843473 280 : 4252, 4029
7489 22:20:19.843543 284 : 4253, 4029
7490 22:20:19.846689 288 : 4250, 4027
7491 22:20:19.846788 292 : 4250, 4027
7492 22:20:19.850166 296 : 4250, 4027
7493 22:20:19.850240 300 : 4363, 4140
7494 22:20:19.853282 304 : 4250, 4027
7495 22:20:19.853352 308 : 4250, 4026
7496 22:20:19.856682 312 : 4250, 3887
7497 22:20:19.856818 316 : 4364, 1992
7498 22:20:19.856882
7499 22:20:19.860046 MIOCK jitter meter ch=0
7500 22:20:19.860114
7501 22:20:19.863264 1T = (316-92) = 224 dly cells
7502 22:20:19.866522 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7503 22:20:19.866618 ==
7504 22:20:19.869974 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 22:20:19.876228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 22:20:19.876303 ==
7507 22:20:19.879676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 22:20:19.886047 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 22:20:19.889359 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 22:20:19.896380 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 22:20:19.904292 [CA 0] Center 43 (13~73) winsize 61
7512 22:20:19.907502 [CA 1] Center 43 (13~73) winsize 61
7513 22:20:19.910945 [CA 2] Center 38 (8~68) winsize 61
7514 22:20:19.914203 [CA 3] Center 37 (8~67) winsize 60
7515 22:20:19.917408 [CA 4] Center 36 (6~66) winsize 61
7516 22:20:19.920822 [CA 5] Center 35 (5~65) winsize 61
7517 22:20:19.920898
7518 22:20:19.924027 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 22:20:19.924099
7520 22:20:19.927631 [CATrainingPosCal] consider 1 rank data
7521 22:20:19.930555 u2DelayCellTimex100 = 290/100 ps
7522 22:20:19.934123 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7523 22:20:19.940691 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7524 22:20:19.944209 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7525 22:20:19.947384 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7526 22:20:19.950639 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7527 22:20:19.954132 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7528 22:20:19.954205
7529 22:20:19.957352 CA PerBit enable=1, Macro0, CA PI delay=35
7530 22:20:19.957422
7531 22:20:19.960608 [CBTSetCACLKResult] CA Dly = 35
7532 22:20:19.963676 CS Dly: 9 (0~40)
7533 22:20:19.967109 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 22:20:19.970482 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 22:20:19.970554 ==
7536 22:20:19.973928 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 22:20:19.980322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 22:20:19.980396 ==
7539 22:20:19.983607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 22:20:19.987003 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 22:20:19.993678 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 22:20:20.000122 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 22:20:20.007485 [CA 0] Center 43 (13~73) winsize 61
7544 22:20:20.010936 [CA 1] Center 43 (13~73) winsize 61
7545 22:20:20.014375 [CA 2] Center 37 (8~67) winsize 60
7546 22:20:20.018005 [CA 3] Center 38 (8~68) winsize 61
7547 22:20:20.021186 [CA 4] Center 36 (6~66) winsize 61
7548 22:20:20.024073 [CA 5] Center 36 (6~66) winsize 61
7549 22:20:20.024144
7550 22:20:20.027424 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 22:20:20.027496
7552 22:20:20.030670 [CATrainingPosCal] consider 2 rank data
7553 22:20:20.034194 u2DelayCellTimex100 = 290/100 ps
7554 22:20:20.037577 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7555 22:20:20.043976 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7556 22:20:20.047291 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7557 22:20:20.050631 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7558 22:20:20.054173 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7559 22:20:20.057512 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7560 22:20:20.057609
7561 22:20:20.060494 CA PerBit enable=1, Macro0, CA PI delay=35
7562 22:20:20.060590
7563 22:20:20.063843 [CBTSetCACLKResult] CA Dly = 35
7564 22:20:20.067408 CS Dly: 10 (0~43)
7565 22:20:20.070794 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 22:20:20.074018 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 22:20:20.074118
7568 22:20:20.077384 ----->DramcWriteLeveling(PI) begin...
7569 22:20:20.077484 ==
7570 22:20:20.080531 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 22:20:20.086959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 22:20:20.087032 ==
7573 22:20:20.090296 Write leveling (Byte 0): 34 => 34
7574 22:20:20.090394 Write leveling (Byte 1): 29 => 29
7575 22:20:20.093467 DramcWriteLeveling(PI) end<-----
7576 22:20:20.093540
7577 22:20:20.096930 ==
7578 22:20:20.097027 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 22:20:20.103470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 22:20:20.103574 ==
7581 22:20:20.106728 [Gating] SW mode calibration
7582 22:20:20.113404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 22:20:20.117004 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 22:20:20.123168 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 22:20:20.126744 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 22:20:20.129886 1 4 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7587 22:20:20.136425 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7588 22:20:20.139685 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7589 22:20:20.142851 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7590 22:20:20.149799 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 22:20:20.153289 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 22:20:20.156324 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 22:20:20.163143 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 22:20:20.166182 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
7595 22:20:20.169858 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7596 22:20:20.176039 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7597 22:20:20.179404 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7598 22:20:20.182826 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 22:20:20.189415 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 22:20:20.192516 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 22:20:20.196203 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7602 22:20:20.202556 1 6 8 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
7603 22:20:20.205627 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7604 22:20:20.208972 1 6 16 | B1->B0 | 2f2e 4646 | 1 0 | (0 0) (0 0)
7605 22:20:20.215865 1 6 20 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
7606 22:20:20.219216 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 22:20:20.222317 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 22:20:20.228658 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 22:20:20.232472 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 22:20:20.235482 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 22:20:20.242068 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7612 22:20:20.245205 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 22:20:20.248705 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 22:20:20.255246 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 22:20:20.258531 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 22:20:20.262103 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 22:20:20.268513 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 22:20:20.271980 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 22:20:20.275347 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 22:20:20.281834 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 22:20:20.284964 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 22:20:20.288625 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 22:20:20.294799 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:20:20.298195 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:20:20.301379 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 22:20:20.308473 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 22:20:20.311222 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 22:20:20.314526 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7629 22:20:20.317913 Total UI for P1: 0, mck2ui 16
7630 22:20:20.321286 best dqsien dly found for B0: ( 1, 9, 12)
7631 22:20:20.327797 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 22:20:20.331253 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 22:20:20.334365 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 22:20:20.338143 Total UI for P1: 0, mck2ui 16
7635 22:20:20.341160 best dqsien dly found for B1: ( 1, 9, 22)
7636 22:20:20.344643 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7637 22:20:20.347714 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7638 22:20:20.347810
7639 22:20:20.354483 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7640 22:20:20.357848 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7641 22:20:20.357917 [Gating] SW calibration Done
7642 22:20:20.361081 ==
7643 22:20:20.364694 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 22:20:20.367474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 22:20:20.367569 ==
7646 22:20:20.367657 RX Vref Scan: 0
7647 22:20:20.367748
7648 22:20:20.371067 RX Vref 0 -> 0, step: 1
7649 22:20:20.371160
7650 22:20:20.374124 RX Delay 0 -> 252, step: 8
7651 22:20:20.377812 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7652 22:20:20.381269 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7653 22:20:20.384372 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7654 22:20:20.390763 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7655 22:20:20.394377 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7656 22:20:20.397374 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7657 22:20:20.400678 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7658 22:20:20.404037 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7659 22:20:20.410694 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7660 22:20:20.414061 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7661 22:20:20.417150 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7662 22:20:20.420668 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7663 22:20:20.424114 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7664 22:20:20.430844 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7665 22:20:20.433753 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 22:20:20.437171 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7667 22:20:20.437242 ==
7668 22:20:20.440629 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 22:20:20.443907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 22:20:20.447057 ==
7671 22:20:20.447125 DQS Delay:
7672 22:20:20.447183 DQS0 = 0, DQS1 = 0
7673 22:20:20.450318 DQM Delay:
7674 22:20:20.450388 DQM0 = 138, DQM1 = 126
7675 22:20:20.453730 DQ Delay:
7676 22:20:20.457337 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7677 22:20:20.460506 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7678 22:20:20.463587 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7679 22:20:20.467130 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7680 22:20:20.467199
7681 22:20:20.467261
7682 22:20:20.467319 ==
7683 22:20:20.470186 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 22:20:20.473709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 22:20:20.473794 ==
7686 22:20:20.473878
7687 22:20:20.473956
7688 22:20:20.476703 TX Vref Scan disable
7689 22:20:20.480476 == TX Byte 0 ==
7690 22:20:20.483470 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7691 22:20:20.486843 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7692 22:20:20.490286 == TX Byte 1 ==
7693 22:20:20.493674 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7694 22:20:20.496917 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7695 22:20:20.497002 ==
7696 22:20:20.500182 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 22:20:20.506366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 22:20:20.506448 ==
7699 22:20:20.518774
7700 22:20:20.521890 TX Vref early break, caculate TX vref
7701 22:20:20.524995 TX Vref=16, minBit 12, minWin=22, winSum=377
7702 22:20:20.528457 TX Vref=18, minBit 6, minWin=23, winSum=385
7703 22:20:20.531432 TX Vref=20, minBit 4, minWin=24, winSum=397
7704 22:20:20.534762 TX Vref=22, minBit 8, minWin=24, winSum=406
7705 22:20:20.538083 TX Vref=24, minBit 5, minWin=25, winSum=417
7706 22:20:20.545188 TX Vref=26, minBit 0, minWin=26, winSum=426
7707 22:20:20.548139 TX Vref=28, minBit 0, minWin=26, winSum=431
7708 22:20:20.551685 TX Vref=30, minBit 2, minWin=25, winSum=424
7709 22:20:20.554684 TX Vref=32, minBit 2, minWin=25, winSum=412
7710 22:20:20.558280 TX Vref=34, minBit 6, minWin=24, winSum=403
7711 22:20:20.564658 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7712 22:20:20.564758
7713 22:20:20.568248 Final TX Range 0 Vref 28
7714 22:20:20.568318
7715 22:20:20.568375 ==
7716 22:20:20.571593 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 22:20:20.574771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 22:20:20.574853 ==
7719 22:20:20.574917
7720 22:20:20.574976
7721 22:20:20.577912 TX Vref Scan disable
7722 22:20:20.584535 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7723 22:20:20.584616 == TX Byte 0 ==
7724 22:20:20.588317 u2DelayCellOfst[0]=13 cells (4 PI)
7725 22:20:20.591692 u2DelayCellOfst[1]=16 cells (5 PI)
7726 22:20:20.594803 u2DelayCellOfst[2]=13 cells (4 PI)
7727 22:20:20.597978 u2DelayCellOfst[3]=13 cells (4 PI)
7728 22:20:20.601130 u2DelayCellOfst[4]=10 cells (3 PI)
7729 22:20:20.604828 u2DelayCellOfst[5]=0 cells (0 PI)
7730 22:20:20.607953 u2DelayCellOfst[6]=16 cells (5 PI)
7731 22:20:20.611011 u2DelayCellOfst[7]=16 cells (5 PI)
7732 22:20:20.614593 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7733 22:20:20.617561 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7734 22:20:20.621623 == TX Byte 1 ==
7735 22:20:20.624226 u2DelayCellOfst[8]=0 cells (0 PI)
7736 22:20:20.627639 u2DelayCellOfst[9]=0 cells (0 PI)
7737 22:20:20.627721 u2DelayCellOfst[10]=6 cells (2 PI)
7738 22:20:20.631107 u2DelayCellOfst[11]=3 cells (1 PI)
7739 22:20:20.634345 u2DelayCellOfst[12]=13 cells (4 PI)
7740 22:20:20.637405 u2DelayCellOfst[13]=10 cells (3 PI)
7741 22:20:20.641243 u2DelayCellOfst[14]=13 cells (4 PI)
7742 22:20:20.644007 u2DelayCellOfst[15]=10 cells (3 PI)
7743 22:20:20.650995 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7744 22:20:20.654144 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7745 22:20:20.654226 DramC Write-DBI on
7746 22:20:20.654291 ==
7747 22:20:20.657253 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 22:20:20.663796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 22:20:20.663879 ==
7750 22:20:20.663943
7751 22:20:20.664004
7752 22:20:20.664060 TX Vref Scan disable
7753 22:20:20.667904 == TX Byte 0 ==
7754 22:20:20.671363 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7755 22:20:20.674909 == TX Byte 1 ==
7756 22:20:20.678376 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7757 22:20:20.681186 DramC Write-DBI off
7758 22:20:20.681269
7759 22:20:20.681334 [DATLAT]
7760 22:20:20.681393 Freq=1600, CH0 RK0
7761 22:20:20.681452
7762 22:20:20.684502 DATLAT Default: 0xf
7763 22:20:20.684584 0, 0xFFFF, sum = 0
7764 22:20:20.687740 1, 0xFFFF, sum = 0
7765 22:20:20.691086 2, 0xFFFF, sum = 0
7766 22:20:20.691169 3, 0xFFFF, sum = 0
7767 22:20:20.694555 4, 0xFFFF, sum = 0
7768 22:20:20.694638 5, 0xFFFF, sum = 0
7769 22:20:20.697987 6, 0xFFFF, sum = 0
7770 22:20:20.698071 7, 0xFFFF, sum = 0
7771 22:20:20.701097 8, 0xFFFF, sum = 0
7772 22:20:20.701182 9, 0xFFFF, sum = 0
7773 22:20:20.704504 10, 0xFFFF, sum = 0
7774 22:20:20.704589 11, 0xFFFF, sum = 0
7775 22:20:20.707602 12, 0xFFFF, sum = 0
7776 22:20:20.707686 13, 0xFFFF, sum = 0
7777 22:20:20.711285 14, 0x0, sum = 1
7778 22:20:20.711368 15, 0x0, sum = 2
7779 22:20:20.714644 16, 0x0, sum = 3
7780 22:20:20.714728 17, 0x0, sum = 4
7781 22:20:20.717982 best_step = 15
7782 22:20:20.718064
7783 22:20:20.718129 ==
7784 22:20:20.720949 Dram Type= 6, Freq= 0, CH_0, rank 0
7785 22:20:20.724475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7786 22:20:20.724558 ==
7787 22:20:20.727498 RX Vref Scan: 1
7788 22:20:20.727580
7789 22:20:20.727645 Set Vref Range= 24 -> 127
7790 22:20:20.727705
7791 22:20:20.730955 RX Vref 24 -> 127, step: 1
7792 22:20:20.731038
7793 22:20:20.734268 RX Delay 19 -> 252, step: 4
7794 22:20:20.734350
7795 22:20:20.737480 Set Vref, RX VrefLevel [Byte0]: 24
7796 22:20:20.741027 [Byte1]: 24
7797 22:20:20.741110
7798 22:20:20.744295 Set Vref, RX VrefLevel [Byte0]: 25
7799 22:20:20.747619 [Byte1]: 25
7800 22:20:20.750633
7801 22:20:20.750716 Set Vref, RX VrefLevel [Byte0]: 26
7802 22:20:20.753945 [Byte1]: 26
7803 22:20:20.758591
7804 22:20:20.758674 Set Vref, RX VrefLevel [Byte0]: 27
7805 22:20:20.761485 [Byte1]: 27
7806 22:20:20.765938
7807 22:20:20.766020 Set Vref, RX VrefLevel [Byte0]: 28
7808 22:20:20.769136 [Byte1]: 28
7809 22:20:20.773709
7810 22:20:20.773791 Set Vref, RX VrefLevel [Byte0]: 29
7811 22:20:20.776800 [Byte1]: 29
7812 22:20:20.780986
7813 22:20:20.781067 Set Vref, RX VrefLevel [Byte0]: 30
7814 22:20:20.784700 [Byte1]: 30
7815 22:20:20.788666
7816 22:20:20.788748 Set Vref, RX VrefLevel [Byte0]: 31
7817 22:20:20.791863 [Byte1]: 31
7818 22:20:20.796154
7819 22:20:20.796237 Set Vref, RX VrefLevel [Byte0]: 32
7820 22:20:20.799685 [Byte1]: 32
7821 22:20:20.803899
7822 22:20:20.803981 Set Vref, RX VrefLevel [Byte0]: 33
7823 22:20:20.807133 [Byte1]: 33
7824 22:20:20.811438
7825 22:20:20.811520 Set Vref, RX VrefLevel [Byte0]: 34
7826 22:20:20.814539 [Byte1]: 34
7827 22:20:20.819225
7828 22:20:20.819307 Set Vref, RX VrefLevel [Byte0]: 35
7829 22:20:20.822177 [Byte1]: 35
7830 22:20:20.826713
7831 22:20:20.826795 Set Vref, RX VrefLevel [Byte0]: 36
7832 22:20:20.830017 [Byte1]: 36
7833 22:20:20.834331
7834 22:20:20.834413 Set Vref, RX VrefLevel [Byte0]: 37
7835 22:20:20.837341 [Byte1]: 37
7836 22:20:20.841696
7837 22:20:20.841778 Set Vref, RX VrefLevel [Byte0]: 38
7838 22:20:20.845093 [Byte1]: 38
7839 22:20:20.849250
7840 22:20:20.849332 Set Vref, RX VrefLevel [Byte0]: 39
7841 22:20:20.852760 [Byte1]: 39
7842 22:20:20.857028
7843 22:20:20.857110 Set Vref, RX VrefLevel [Byte0]: 40
7844 22:20:20.860322 [Byte1]: 40
7845 22:20:20.864207
7846 22:20:20.864289 Set Vref, RX VrefLevel [Byte0]: 41
7847 22:20:20.867650 [Byte1]: 41
7848 22:20:20.872074
7849 22:20:20.872156 Set Vref, RX VrefLevel [Byte0]: 42
7850 22:20:20.875392 [Byte1]: 42
7851 22:20:20.879617
7852 22:20:20.879700 Set Vref, RX VrefLevel [Byte0]: 43
7853 22:20:20.882878 [Byte1]: 43
7854 22:20:20.887177
7855 22:20:20.887260 Set Vref, RX VrefLevel [Byte0]: 44
7856 22:20:20.890274 [Byte1]: 44
7857 22:20:20.894603
7858 22:20:20.894684 Set Vref, RX VrefLevel [Byte0]: 45
7859 22:20:20.897939 [Byte1]: 45
7860 22:20:20.902132
7861 22:20:20.902214 Set Vref, RX VrefLevel [Byte0]: 46
7862 22:20:20.905328 [Byte1]: 46
7863 22:20:20.909962
7864 22:20:20.910044 Set Vref, RX VrefLevel [Byte0]: 47
7865 22:20:20.912950 [Byte1]: 47
7866 22:20:20.917507
7867 22:20:20.917590 Set Vref, RX VrefLevel [Byte0]: 48
7868 22:20:20.920594 [Byte1]: 48
7869 22:20:20.924875
7870 22:20:20.924957 Set Vref, RX VrefLevel [Byte0]: 49
7871 22:20:20.928166 [Byte1]: 49
7872 22:20:20.932645
7873 22:20:20.932727 Set Vref, RX VrefLevel [Byte0]: 50
7874 22:20:20.935951 [Byte1]: 50
7875 22:20:20.939903
7876 22:20:20.939985 Set Vref, RX VrefLevel [Byte0]: 51
7877 22:20:20.943339 [Byte1]: 51
7878 22:20:20.947876
7879 22:20:20.947957 Set Vref, RX VrefLevel [Byte0]: 52
7880 22:20:20.950960 [Byte1]: 52
7881 22:20:20.955279
7882 22:20:20.955362 Set Vref, RX VrefLevel [Byte0]: 53
7883 22:20:20.958905 [Byte1]: 53
7884 22:20:20.962942
7885 22:20:20.963024 Set Vref, RX VrefLevel [Byte0]: 54
7886 22:20:20.966280 [Byte1]: 54
7887 22:20:20.970226
7888 22:20:20.970308 Set Vref, RX VrefLevel [Byte0]: 55
7889 22:20:20.973822 [Byte1]: 55
7890 22:20:20.977891
7891 22:20:20.977974 Set Vref, RX VrefLevel [Byte0]: 56
7892 22:20:20.981180 [Byte1]: 56
7893 22:20:20.985347
7894 22:20:20.985429 Set Vref, RX VrefLevel [Byte0]: 57
7895 22:20:20.988848 [Byte1]: 57
7896 22:20:20.993360
7897 22:20:20.993442 Set Vref, RX VrefLevel [Byte0]: 58
7898 22:20:20.996431 [Byte1]: 58
7899 22:20:21.000871
7900 22:20:21.000953 Set Vref, RX VrefLevel [Byte0]: 59
7901 22:20:21.003990 [Byte1]: 59
7902 22:20:21.008400
7903 22:20:21.008482 Set Vref, RX VrefLevel [Byte0]: 60
7904 22:20:21.011614 [Byte1]: 60
7905 22:20:21.015563
7906 22:20:21.015645 Set Vref, RX VrefLevel [Byte0]: 61
7907 22:20:21.018994 [Byte1]: 61
7908 22:20:21.023722
7909 22:20:21.023804 Set Vref, RX VrefLevel [Byte0]: 62
7910 22:20:21.026541 [Byte1]: 62
7911 22:20:21.030936
7912 22:20:21.031019 Set Vref, RX VrefLevel [Byte0]: 63
7913 22:20:21.034344 [Byte1]: 63
7914 22:20:21.038755
7915 22:20:21.038840 Set Vref, RX VrefLevel [Byte0]: 64
7916 22:20:21.042028 [Byte1]: 64
7917 22:20:21.046074
7918 22:20:21.046157 Set Vref, RX VrefLevel [Byte0]: 65
7919 22:20:21.049171 [Byte1]: 65
7920 22:20:21.053612
7921 22:20:21.053694 Set Vref, RX VrefLevel [Byte0]: 66
7922 22:20:21.056791 [Byte1]: 66
7923 22:20:21.061284
7924 22:20:21.061366 Set Vref, RX VrefLevel [Byte0]: 67
7925 22:20:21.064700 [Byte1]: 67
7926 22:20:21.068742
7927 22:20:21.068830 Set Vref, RX VrefLevel [Byte0]: 68
7928 22:20:21.071951 [Byte1]: 68
7929 22:20:21.076524
7930 22:20:21.076606 Set Vref, RX VrefLevel [Byte0]: 69
7931 22:20:21.079633 [Byte1]: 69
7932 22:20:21.083961
7933 22:20:21.084044 Set Vref, RX VrefLevel [Byte0]: 70
7934 22:20:21.087119 [Byte1]: 70
7935 22:20:21.091349
7936 22:20:21.091431 Set Vref, RX VrefLevel [Byte0]: 71
7937 22:20:21.094763 [Byte1]: 71
7938 22:20:21.099172
7939 22:20:21.102394 Set Vref, RX VrefLevel [Byte0]: 72
7940 22:20:21.102477 [Byte1]: 72
7941 22:20:21.106817
7942 22:20:21.106900 Set Vref, RX VrefLevel [Byte0]: 73
7943 22:20:21.110267 [Byte1]: 73
7944 22:20:21.114667
7945 22:20:21.114750 Set Vref, RX VrefLevel [Byte0]: 74
7946 22:20:21.117540 [Byte1]: 74
7947 22:20:21.121672
7948 22:20:21.121755 Set Vref, RX VrefLevel [Byte0]: 75
7949 22:20:21.125290 [Byte1]: 75
7950 22:20:21.129412
7951 22:20:21.129494 Final RX Vref Byte 0 = 56 to rank0
7952 22:20:21.132671 Final RX Vref Byte 1 = 60 to rank0
7953 22:20:21.135909 Final RX Vref Byte 0 = 56 to rank1
7954 22:20:21.139309 Final RX Vref Byte 1 = 60 to rank1==
7955 22:20:21.142605 Dram Type= 6, Freq= 0, CH_0, rank 0
7956 22:20:21.149444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 22:20:21.149528 ==
7958 22:20:21.149594 DQS Delay:
7959 22:20:21.152527 DQS0 = 0, DQS1 = 0
7960 22:20:21.152610 DQM Delay:
7961 22:20:21.152675 DQM0 = 135, DQM1 = 123
7962 22:20:21.155849 DQ Delay:
7963 22:20:21.159399 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7964 22:20:21.162370 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7965 22:20:21.165819 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7966 22:20:21.168915 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =130
7967 22:20:21.169010
7968 22:20:21.169084
7969 22:20:21.169152
7970 22:20:21.172479 [DramC_TX_OE_Calibration] TA2
7971 22:20:21.175666 Original DQ_B0 (3 6) =30, OEN = 27
7972 22:20:21.179139 Original DQ_B1 (3 6) =30, OEN = 27
7973 22:20:21.182227 24, 0x0, End_B0=24 End_B1=24
7974 22:20:21.182340 25, 0x0, End_B0=25 End_B1=25
7975 22:20:21.185796 26, 0x0, End_B0=26 End_B1=26
7976 22:20:21.188942 27, 0x0, End_B0=27 End_B1=27
7977 22:20:21.191931 28, 0x0, End_B0=28 End_B1=28
7978 22:20:21.195269 29, 0x0, End_B0=29 End_B1=29
7979 22:20:21.195359 30, 0x0, End_B0=30 End_B1=30
7980 22:20:21.199072 31, 0x4545, End_B0=30 End_B1=30
7981 22:20:21.201934 Byte0 end_step=30 best_step=27
7982 22:20:21.205175 Byte1 end_step=30 best_step=27
7983 22:20:21.208404 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 22:20:21.212072 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 22:20:21.212184
7986 22:20:21.212271
7987 22:20:21.218720 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7988 22:20:21.222024 CH0 RK0: MR19=303, MR18=1E1C
7989 22:20:21.228454 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7990 22:20:21.228628
7991 22:20:21.231854 ----->DramcWriteLeveling(PI) begin...
7992 22:20:21.232030 ==
7993 22:20:21.235219 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 22:20:21.238690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 22:20:21.238930 ==
7996 22:20:21.241775 Write leveling (Byte 0): 39 => 39
7997 22:20:21.245127 Write leveling (Byte 1): 31 => 31
7998 22:20:21.248139 DramcWriteLeveling(PI) end<-----
7999 22:20:21.248524
8000 22:20:21.248852 ==
8001 22:20:21.251409 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 22:20:21.254978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 22:20:21.258416 ==
8004 22:20:21.258796 [Gating] SW mode calibration
8005 22:20:21.267909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8006 22:20:21.271250 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8007 22:20:21.277669 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 22:20:21.281362 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 22:20:21.284452 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 22:20:21.287852 1 4 12 | B1->B0 | 2323 3030 | 1 1 | (0 0) (1 1)
8011 22:20:21.294514 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 22:20:21.297576 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 22:20:21.300849 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 22:20:21.307356 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 22:20:21.311026 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 22:20:21.314103 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 22:20:21.320630 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8018 22:20:21.323822 1 5 12 | B1->B0 | 3434 2626 | 0 0 | (0 1) (1 0)
8019 22:20:21.327422 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
8020 22:20:21.333542 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 22:20:21.336835 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 22:20:21.340133 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 22:20:21.347093 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 22:20:21.350435 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 22:20:21.353566 1 6 8 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8026 22:20:21.360422 1 6 12 | B1->B0 | 3130 4646 | 1 0 | (0 0) (0 0)
8027 22:20:21.363307 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 22:20:21.366706 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 22:20:21.373356 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 22:20:21.376512 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 22:20:21.379988 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 22:20:21.386302 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 22:20:21.389956 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 22:20:21.392862 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 22:20:21.399624 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8036 22:20:21.403141 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 22:20:21.406101 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 22:20:21.412735 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 22:20:21.416061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 22:20:21.419289 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 22:20:21.425892 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 22:20:21.429446 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 22:20:21.435835 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 22:20:21.438982 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 22:20:21.442326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 22:20:21.445795 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 22:20:21.452491 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 22:20:21.455596 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 22:20:21.458843 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 22:20:21.465425 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8051 22:20:21.469004 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8052 22:20:21.471871 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 22:20:21.475569 Total UI for P1: 0, mck2ui 16
8054 22:20:21.478920 best dqsien dly found for B0: ( 1, 9, 14)
8055 22:20:21.482247 Total UI for P1: 0, mck2ui 16
8056 22:20:21.485314 best dqsien dly found for B1: ( 1, 9, 14)
8057 22:20:21.488759 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8058 22:20:21.495058 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8059 22:20:21.495141
8060 22:20:21.498425 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8061 22:20:21.501657 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8062 22:20:21.505235 [Gating] SW calibration Done
8063 22:20:21.505316 ==
8064 22:20:21.508210 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 22:20:21.511874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 22:20:21.511956 ==
8067 22:20:21.515170 RX Vref Scan: 0
8068 22:20:21.515250
8069 22:20:21.515314 RX Vref 0 -> 0, step: 1
8070 22:20:21.515373
8071 22:20:21.518223 RX Delay 0 -> 252, step: 8
8072 22:20:21.521767 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8073 22:20:21.525268 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8074 22:20:21.531641 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8075 22:20:21.535216 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8076 22:20:21.538034 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8077 22:20:21.541717 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8078 22:20:21.544884 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8079 22:20:21.551674 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8080 22:20:21.554890 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8081 22:20:21.558171 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8082 22:20:21.561225 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8083 22:20:21.568400 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8084 22:20:21.571279 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8085 22:20:21.574496 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8086 22:20:21.577733 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8087 22:20:21.581297 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8088 22:20:21.584405 ==
8089 22:20:21.587671 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 22:20:21.590853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 22:20:21.590960 ==
8092 22:20:21.591053 DQS Delay:
8093 22:20:21.594482 DQS0 = 0, DQS1 = 0
8094 22:20:21.594563 DQM Delay:
8095 22:20:21.597624 DQM0 = 136, DQM1 = 125
8096 22:20:21.597730 DQ Delay:
8097 22:20:21.600733 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8098 22:20:21.604026 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8099 22:20:21.607387 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8100 22:20:21.610906 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8101 22:20:21.610986
8102 22:20:21.611049
8103 22:20:21.611120 ==
8104 22:20:21.614079 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 22:20:21.620997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 22:20:21.621077 ==
8107 22:20:21.621176
8108 22:20:21.621235
8109 22:20:21.621292 TX Vref Scan disable
8110 22:20:21.624476 == TX Byte 0 ==
8111 22:20:21.627444 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8112 22:20:21.634333 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8113 22:20:21.634413 == TX Byte 1 ==
8114 22:20:21.637420 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8115 22:20:21.644469 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8116 22:20:21.644550 ==
8117 22:20:21.647558 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 22:20:21.651044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 22:20:21.651125 ==
8120 22:20:21.664290
8121 22:20:21.667740 TX Vref early break, caculate TX vref
8122 22:20:21.670857 TX Vref=16, minBit 8, minWin=23, winSum=389
8123 22:20:21.674037 TX Vref=18, minBit 0, minWin=23, winSum=396
8124 22:20:21.677420 TX Vref=20, minBit 8, minWin=24, winSum=406
8125 22:20:21.680529 TX Vref=22, minBit 0, minWin=25, winSum=413
8126 22:20:21.683992 TX Vref=24, minBit 0, minWin=25, winSum=424
8127 22:20:21.690436 TX Vref=26, minBit 1, minWin=26, winSum=431
8128 22:20:21.693729 TX Vref=28, minBit 0, minWin=26, winSum=433
8129 22:20:21.697237 TX Vref=30, minBit 0, minWin=25, winSum=426
8130 22:20:21.700326 TX Vref=32, minBit 0, minWin=26, winSum=422
8131 22:20:21.703697 TX Vref=34, minBit 3, minWin=24, winSum=409
8132 22:20:21.710486 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 28
8133 22:20:21.710569
8134 22:20:21.713595 Final TX Range 0 Vref 28
8135 22:20:21.713677
8136 22:20:21.713741 ==
8137 22:20:21.717021 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 22:20:21.720488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 22:20:21.720571 ==
8140 22:20:21.720636
8141 22:20:21.720695
8142 22:20:21.723619 TX Vref Scan disable
8143 22:20:21.730133 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8144 22:20:21.730215 == TX Byte 0 ==
8145 22:20:21.733540 u2DelayCellOfst[0]=13 cells (4 PI)
8146 22:20:21.736792 u2DelayCellOfst[1]=20 cells (6 PI)
8147 22:20:21.740002 u2DelayCellOfst[2]=13 cells (4 PI)
8148 22:20:21.743646 u2DelayCellOfst[3]=13 cells (4 PI)
8149 22:20:21.746606 u2DelayCellOfst[4]=10 cells (3 PI)
8150 22:20:21.749963 u2DelayCellOfst[5]=0 cells (0 PI)
8151 22:20:21.753423 u2DelayCellOfst[6]=20 cells (6 PI)
8152 22:20:21.756522 u2DelayCellOfst[7]=20 cells (6 PI)
8153 22:20:21.759525 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8154 22:20:21.762826 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8155 22:20:21.766354 == TX Byte 1 ==
8156 22:20:21.769505 u2DelayCellOfst[8]=0 cells (0 PI)
8157 22:20:21.772962 u2DelayCellOfst[9]=3 cells (1 PI)
8158 22:20:21.776023 u2DelayCellOfst[10]=6 cells (2 PI)
8159 22:20:21.779522 u2DelayCellOfst[11]=3 cells (1 PI)
8160 22:20:21.782986 u2DelayCellOfst[12]=13 cells (4 PI)
8161 22:20:21.783071 u2DelayCellOfst[13]=13 cells (4 PI)
8162 22:20:21.785953 u2DelayCellOfst[14]=13 cells (4 PI)
8163 22:20:21.789307 u2DelayCellOfst[15]=10 cells (3 PI)
8164 22:20:21.796147 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8165 22:20:21.799494 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8166 22:20:21.799575 DramC Write-DBI on
8167 22:20:21.802652 ==
8168 22:20:21.806094 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 22:20:21.809102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 22:20:21.809185 ==
8171 22:20:21.809250
8172 22:20:21.809310
8173 22:20:21.812392 TX Vref Scan disable
8174 22:20:21.812475 == TX Byte 0 ==
8175 22:20:21.818787 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8176 22:20:21.818870 == TX Byte 1 ==
8177 22:20:21.822239 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8178 22:20:21.825608 DramC Write-DBI off
8179 22:20:21.825689
8180 22:20:21.825754 [DATLAT]
8181 22:20:21.828678 Freq=1600, CH0 RK1
8182 22:20:21.828760
8183 22:20:21.828861 DATLAT Default: 0xf
8184 22:20:21.832255 0, 0xFFFF, sum = 0
8185 22:20:21.832339 1, 0xFFFF, sum = 0
8186 22:20:21.835603 2, 0xFFFF, sum = 0
8187 22:20:21.838562 3, 0xFFFF, sum = 0
8188 22:20:21.838645 4, 0xFFFF, sum = 0
8189 22:20:21.842149 5, 0xFFFF, sum = 0
8190 22:20:21.842233 6, 0xFFFF, sum = 0
8191 22:20:21.845556 7, 0xFFFF, sum = 0
8192 22:20:21.845640 8, 0xFFFF, sum = 0
8193 22:20:21.848545 9, 0xFFFF, sum = 0
8194 22:20:21.848629 10, 0xFFFF, sum = 0
8195 22:20:21.851887 11, 0xFFFF, sum = 0
8196 22:20:21.851971 12, 0xFFFF, sum = 0
8197 22:20:21.855059 13, 0xFFFF, sum = 0
8198 22:20:21.855142 14, 0x0, sum = 1
8199 22:20:21.858683 15, 0x0, sum = 2
8200 22:20:21.858767 16, 0x0, sum = 3
8201 22:20:21.861799 17, 0x0, sum = 4
8202 22:20:21.861882 best_step = 15
8203 22:20:21.861947
8204 22:20:21.862007 ==
8205 22:20:21.865348 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 22:20:21.871461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 22:20:21.871543 ==
8208 22:20:21.871607 RX Vref Scan: 0
8209 22:20:21.871667
8210 22:20:21.875029 RX Vref 0 -> 0, step: 1
8211 22:20:21.875114
8212 22:20:21.878112 RX Delay 11 -> 252, step: 4
8213 22:20:21.881501 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8214 22:20:21.884895 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8215 22:20:21.888181 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8216 22:20:21.894990 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8217 22:20:21.898162 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8218 22:20:21.901503 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8219 22:20:21.904536 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8220 22:20:21.908137 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8221 22:20:21.914514 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8222 22:20:21.917960 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8223 22:20:21.921154 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8224 22:20:21.924561 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8225 22:20:21.928178 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8226 22:20:21.934577 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8227 22:20:21.937767 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8228 22:20:21.941124 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8229 22:20:21.941207 ==
8230 22:20:21.944253 Dram Type= 6, Freq= 0, CH_0, rank 1
8231 22:20:21.947705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 22:20:21.950817 ==
8233 22:20:21.950898 DQS Delay:
8234 22:20:21.950964 DQS0 = 0, DQS1 = 0
8235 22:20:21.953954 DQM Delay:
8236 22:20:21.954036 DQM0 = 133, DQM1 = 123
8237 22:20:21.957795 DQ Delay:
8238 22:20:21.960995 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8239 22:20:21.964087 DQ4 =134, DQ5 =126, DQ6 =140, DQ7 =140
8240 22:20:21.967277 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8241 22:20:21.970774 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8242 22:20:21.970857
8243 22:20:21.970922
8244 22:20:21.970982
8245 22:20:21.974112 [DramC_TX_OE_Calibration] TA2
8246 22:20:21.977178 Original DQ_B0 (3 6) =30, OEN = 27
8247 22:20:21.980709 Original DQ_B1 (3 6) =30, OEN = 27
8248 22:20:21.983753 24, 0x0, End_B0=24 End_B1=24
8249 22:20:21.983837 25, 0x0, End_B0=25 End_B1=25
8250 22:20:21.987251 26, 0x0, End_B0=26 End_B1=26
8251 22:20:21.990437 27, 0x0, End_B0=27 End_B1=27
8252 22:20:21.993891 28, 0x0, End_B0=28 End_B1=28
8253 22:20:21.997042 29, 0x0, End_B0=29 End_B1=29
8254 22:20:21.997126 30, 0x0, End_B0=30 End_B1=30
8255 22:20:22.000537 31, 0x4545, End_B0=30 End_B1=30
8256 22:20:22.003837 Byte0 end_step=30 best_step=27
8257 22:20:22.007441 Byte1 end_step=30 best_step=27
8258 22:20:22.011156 Byte0 TX OE(2T, 0.5T) = (3, 3)
8259 22:20:22.014098 Byte1 TX OE(2T, 0.5T) = (3, 3)
8260 22:20:22.014181
8261 22:20:22.014247
8262 22:20:22.020656 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8263 22:20:22.023888 CH0 RK1: MR19=303, MR18=1F0C
8264 22:20:22.030184 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8265 22:20:22.033374 [RxdqsGatingPostProcess] freq 1600
8266 22:20:22.036660 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8267 22:20:22.040092 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 22:20:22.043560 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 22:20:22.046943 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 22:20:22.050049 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 22:20:22.053466 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 22:20:22.056678 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 22:20:22.059897 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 22:20:22.063314 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 22:20:22.066600 Pre-setting of DQS Precalculation
8276 22:20:22.069973 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8277 22:20:22.070077 ==
8278 22:20:22.073602 Dram Type= 6, Freq= 0, CH_1, rank 0
8279 22:20:22.076654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 22:20:22.080060 ==
8281 22:20:22.083341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8282 22:20:22.086384 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8283 22:20:22.093490 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8284 22:20:22.099686 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8285 22:20:22.107225 [CA 0] Center 40 (11~70) winsize 60
8286 22:20:22.110690 [CA 1] Center 41 (11~71) winsize 61
8287 22:20:22.113991 [CA 2] Center 36 (7~66) winsize 60
8288 22:20:22.116927 [CA 3] Center 36 (6~66) winsize 61
8289 22:20:22.120402 [CA 4] Center 37 (7~67) winsize 61
8290 22:20:22.123583 [CA 5] Center 36 (6~66) winsize 61
8291 22:20:22.124047
8292 22:20:22.127211 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8293 22:20:22.127676
8294 22:20:22.133276 [CATrainingPosCal] consider 1 rank data
8295 22:20:22.133745 u2DelayCellTimex100 = 290/100 ps
8296 22:20:22.140137 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8297 22:20:22.143259 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8298 22:20:22.146633 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8299 22:20:22.149745 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8300 22:20:22.153228 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8301 22:20:22.156165 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8302 22:20:22.156636
8303 22:20:22.159811 CA PerBit enable=1, Macro0, CA PI delay=36
8304 22:20:22.160281
8305 22:20:22.162864 [CBTSetCACLKResult] CA Dly = 36
8306 22:20:22.166386 CS Dly: 8 (0~39)
8307 22:20:22.169643 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8308 22:20:22.173073 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8309 22:20:22.173540 ==
8310 22:20:22.175937 Dram Type= 6, Freq= 0, CH_1, rank 1
8311 22:20:22.182993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 22:20:22.183462 ==
8313 22:20:22.186107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8314 22:20:22.192523 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8315 22:20:22.195891 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8316 22:20:22.202631 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8317 22:20:22.210195 [CA 0] Center 42 (13~72) winsize 60
8318 22:20:22.213576 [CA 1] Center 41 (11~71) winsize 61
8319 22:20:22.216752 [CA 2] Center 37 (8~67) winsize 60
8320 22:20:22.220213 [CA 3] Center 37 (8~66) winsize 59
8321 22:20:22.223908 [CA 4] Center 37 (8~67) winsize 60
8322 22:20:22.226660 [CA 5] Center 36 (7~66) winsize 60
8323 22:20:22.227276
8324 22:20:22.229818 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8325 22:20:22.230387
8326 22:20:22.236643 [CATrainingPosCal] consider 2 rank data
8327 22:20:22.237154 u2DelayCellTimex100 = 290/100 ps
8328 22:20:22.243115 CA0 delay=41 (13~70),Diff = 5 PI (16 cell)
8329 22:20:22.246296 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8330 22:20:22.249211 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 22:20:22.252788 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8332 22:20:22.255832 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8333 22:20:22.259313 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8334 22:20:22.259380
8335 22:20:22.262556 CA PerBit enable=1, Macro0, CA PI delay=36
8336 22:20:22.262652
8337 22:20:22.265980 [CBTSetCACLKResult] CA Dly = 36
8338 22:20:22.268995 CS Dly: 9 (0~41)
8339 22:20:22.272554 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8340 22:20:22.275582 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8341 22:20:22.275674
8342 22:20:22.279091 ----->DramcWriteLeveling(PI) begin...
8343 22:20:22.279192 ==
8344 22:20:22.282462 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 22:20:22.288573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 22:20:22.288648 ==
8347 22:20:22.292126 Write leveling (Byte 0): 25 => 25
8348 22:20:22.295160 Write leveling (Byte 1): 27 => 27
8349 22:20:22.298625 DramcWriteLeveling(PI) end<-----
8350 22:20:22.298695
8351 22:20:22.298754 ==
8352 22:20:22.302080 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 22:20:22.305344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 22:20:22.305421 ==
8355 22:20:22.308840 [Gating] SW mode calibration
8356 22:20:22.315021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8357 22:20:22.321308 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8358 22:20:22.325018 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 22:20:22.328223 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 22:20:22.334683 1 4 8 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
8361 22:20:22.337996 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8362 22:20:22.341543 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 22:20:22.347772 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 22:20:22.351031 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 22:20:22.354544 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 22:20:22.361066 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 22:20:22.364257 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 22:20:22.367611 1 5 8 | B1->B0 | 2e2e 2b2b | 0 0 | (0 0) (0 0)
8369 22:20:22.374500 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8370 22:20:22.377862 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 22:20:22.380674 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 22:20:22.387395 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 22:20:22.391094 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 22:20:22.394139 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 22:20:22.400960 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8376 22:20:22.404224 1 6 8 | B1->B0 | 3434 4141 | 1 0 | (0 0) (0 0)
8377 22:20:22.407125 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 22:20:22.414226 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 22:20:22.417162 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 22:20:22.420433 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 22:20:22.427114 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 22:20:22.430360 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 22:20:22.433910 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8384 22:20:22.440117 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 22:20:22.443507 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8386 22:20:22.446823 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8387 22:20:22.453505 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:20:22.457041 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:20:22.460473 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 22:20:22.466673 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 22:20:22.470102 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 22:20:22.473147 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 22:20:22.479845 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:20:22.483348 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:20:22.486751 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 22:20:22.493190 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 22:20:22.496597 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 22:20:22.499670 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 22:20:22.506100 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8400 22:20:22.509458 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 22:20:22.512865 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8402 22:20:22.519273 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 22:20:22.519374 Total UI for P1: 0, mck2ui 16
8404 22:20:22.523079 best dqsien dly found for B0: ( 1, 9, 8)
8405 22:20:22.526014 Total UI for P1: 0, mck2ui 16
8406 22:20:22.529277 best dqsien dly found for B1: ( 1, 9, 10)
8407 22:20:22.535644 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8408 22:20:22.539080 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8409 22:20:22.539154
8410 22:20:22.542659 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8411 22:20:22.545708 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8412 22:20:22.548965 [Gating] SW calibration Done
8413 22:20:22.549036 ==
8414 22:20:22.552325 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 22:20:22.555556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 22:20:22.555653 ==
8417 22:20:22.559180 RX Vref Scan: 0
8418 22:20:22.559254
8419 22:20:22.559316 RX Vref 0 -> 0, step: 1
8420 22:20:22.559376
8421 22:20:22.562614 RX Delay 0 -> 252, step: 8
8422 22:20:22.565770 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8423 22:20:22.572483 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8424 22:20:22.575548 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8425 22:20:22.578607 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8426 22:20:22.582144 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8427 22:20:22.585508 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8428 22:20:22.591883 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8429 22:20:22.595153 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8430 22:20:22.598917 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8431 22:20:22.601829 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8432 22:20:22.605256 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8433 22:20:22.608342 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8434 22:20:22.615006 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8435 22:20:22.618304 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8436 22:20:22.621678 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8437 22:20:22.624861 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8438 22:20:22.624944 ==
8439 22:20:22.628405 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 22:20:22.634897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 22:20:22.634979 ==
8442 22:20:22.635044 DQS Delay:
8443 22:20:22.638597 DQS0 = 0, DQS1 = 0
8444 22:20:22.638679 DQM Delay:
8445 22:20:22.641538 DQM0 = 137, DQM1 = 130
8446 22:20:22.641619 DQ Delay:
8447 22:20:22.645003 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8448 22:20:22.648333 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8449 22:20:22.651320 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8450 22:20:22.654853 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8451 22:20:22.654934
8452 22:20:22.654998
8453 22:20:22.655057 ==
8454 22:20:22.658079 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 22:20:22.664471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 22:20:22.664553 ==
8457 22:20:22.664618
8458 22:20:22.664679
8459 22:20:22.664736 TX Vref Scan disable
8460 22:20:22.668527 == TX Byte 0 ==
8461 22:20:22.671536 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8462 22:20:22.678117 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8463 22:20:22.678200 == TX Byte 1 ==
8464 22:20:22.681490 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8465 22:20:22.687836 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8466 22:20:22.687918 ==
8467 22:20:22.691411 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 22:20:22.694757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 22:20:22.694840 ==
8470 22:20:22.707324
8471 22:20:22.710270 TX Vref early break, caculate TX vref
8472 22:20:22.713348 TX Vref=16, minBit 8, minWin=22, winSum=376
8473 22:20:22.716796 TX Vref=18, minBit 0, minWin=24, winSum=392
8474 22:20:22.720022 TX Vref=20, minBit 2, minWin=24, winSum=395
8475 22:20:22.723538 TX Vref=22, minBit 9, minWin=24, winSum=406
8476 22:20:22.726462 TX Vref=24, minBit 1, minWin=25, winSum=415
8477 22:20:22.733476 TX Vref=26, minBit 9, minWin=25, winSum=423
8478 22:20:22.736403 TX Vref=28, minBit 0, minWin=26, winSum=430
8479 22:20:22.739740 TX Vref=30, minBit 5, minWin=25, winSum=421
8480 22:20:22.743096 TX Vref=32, minBit 0, minWin=25, winSum=415
8481 22:20:22.746798 TX Vref=34, minBit 10, minWin=24, winSum=405
8482 22:20:22.753077 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8483 22:20:22.753159
8484 22:20:22.756343 Final TX Range 0 Vref 28
8485 22:20:22.756425
8486 22:20:22.756489 ==
8487 22:20:22.759843 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 22:20:22.763242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 22:20:22.763324 ==
8490 22:20:22.763389
8491 22:20:22.763448
8492 22:20:22.766331 TX Vref Scan disable
8493 22:20:22.772803 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8494 22:20:22.772898 == TX Byte 0 ==
8495 22:20:22.776135 u2DelayCellOfst[0]=16 cells (5 PI)
8496 22:20:22.779481 u2DelayCellOfst[1]=10 cells (3 PI)
8497 22:20:22.782971 u2DelayCellOfst[2]=0 cells (0 PI)
8498 22:20:22.786012 u2DelayCellOfst[3]=3 cells (1 PI)
8499 22:20:22.789361 u2DelayCellOfst[4]=6 cells (2 PI)
8500 22:20:22.792983 u2DelayCellOfst[5]=16 cells (5 PI)
8501 22:20:22.796033 u2DelayCellOfst[6]=16 cells (5 PI)
8502 22:20:22.799554 u2DelayCellOfst[7]=6 cells (2 PI)
8503 22:20:22.802403 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8504 22:20:22.805688 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8505 22:20:22.809185 == TX Byte 1 ==
8506 22:20:22.812310 u2DelayCellOfst[8]=0 cells (0 PI)
8507 22:20:22.815782 u2DelayCellOfst[9]=3 cells (1 PI)
8508 22:20:22.815864 u2DelayCellOfst[10]=10 cells (3 PI)
8509 22:20:22.819050 u2DelayCellOfst[11]=6 cells (2 PI)
8510 22:20:22.822318 u2DelayCellOfst[12]=16 cells (5 PI)
8511 22:20:22.825541 u2DelayCellOfst[13]=13 cells (4 PI)
8512 22:20:22.828883 u2DelayCellOfst[14]=16 cells (5 PI)
8513 22:20:22.832338 u2DelayCellOfst[15]=13 cells (4 PI)
8514 22:20:22.838673 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8515 22:20:22.841959 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8516 22:20:22.842041 DramC Write-DBI on
8517 22:20:22.842107 ==
8518 22:20:22.845281 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 22:20:22.852115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 22:20:22.852198 ==
8521 22:20:22.852262
8522 22:20:22.852322
8523 22:20:22.855347 TX Vref Scan disable
8524 22:20:22.855428 == TX Byte 0 ==
8525 22:20:22.861674 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8526 22:20:22.861756 == TX Byte 1 ==
8527 22:20:22.865018 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8528 22:20:22.868332 DramC Write-DBI off
8529 22:20:22.868413
8530 22:20:22.868477 [DATLAT]
8531 22:20:22.871882 Freq=1600, CH1 RK0
8532 22:20:22.871963
8533 22:20:22.872027 DATLAT Default: 0xf
8534 22:20:22.875004 0, 0xFFFF, sum = 0
8535 22:20:22.875088 1, 0xFFFF, sum = 0
8536 22:20:22.878098 2, 0xFFFF, sum = 0
8537 22:20:22.878181 3, 0xFFFF, sum = 0
8538 22:20:22.881966 4, 0xFFFF, sum = 0
8539 22:20:22.882095 5, 0xFFFF, sum = 0
8540 22:20:22.884654 6, 0xFFFF, sum = 0
8541 22:20:22.884738 7, 0xFFFF, sum = 0
8542 22:20:22.888419 8, 0xFFFF, sum = 0
8543 22:20:22.891576 9, 0xFFFF, sum = 0
8544 22:20:22.891658 10, 0xFFFF, sum = 0
8545 22:20:22.894708 11, 0xFFFF, sum = 0
8546 22:20:22.894791 12, 0xFFFF, sum = 0
8547 22:20:22.897898 13, 0xFFFF, sum = 0
8548 22:20:22.897981 14, 0x0, sum = 1
8549 22:20:22.901392 15, 0x0, sum = 2
8550 22:20:22.901475 16, 0x0, sum = 3
8551 22:20:22.904768 17, 0x0, sum = 4
8552 22:20:22.904866 best_step = 15
8553 22:20:22.904931
8554 22:20:22.904991 ==
8555 22:20:22.908033 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 22:20:22.911304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 22:20:22.911387 ==
8558 22:20:22.914419 RX Vref Scan: 1
8559 22:20:22.914499
8560 22:20:22.917952 Set Vref Range= 24 -> 127
8561 22:20:22.918034
8562 22:20:22.918099 RX Vref 24 -> 127, step: 1
8563 22:20:22.920977
8564 22:20:22.921058 RX Delay 19 -> 252, step: 4
8565 22:20:22.921123
8566 22:20:22.924498 Set Vref, RX VrefLevel [Byte0]: 24
8567 22:20:22.927621 [Byte1]: 24
8568 22:20:22.931181
8569 22:20:22.931263 Set Vref, RX VrefLevel [Byte0]: 25
8570 22:20:22.934723 [Byte1]: 25
8571 22:20:22.938897
8572 22:20:22.938978 Set Vref, RX VrefLevel [Byte0]: 26
8573 22:20:22.942209 [Byte1]: 26
8574 22:20:22.946793
8575 22:20:22.946874 Set Vref, RX VrefLevel [Byte0]: 27
8576 22:20:22.949728 [Byte1]: 27
8577 22:20:22.954179
8578 22:20:22.954260 Set Vref, RX VrefLevel [Byte0]: 28
8579 22:20:22.957558 [Byte1]: 28
8580 22:20:22.961951
8581 22:20:22.962033 Set Vref, RX VrefLevel [Byte0]: 29
8582 22:20:22.964889 [Byte1]: 29
8583 22:20:22.969103
8584 22:20:22.969185 Set Vref, RX VrefLevel [Byte0]: 30
8585 22:20:22.972776 [Byte1]: 30
8586 22:20:22.976686
8587 22:20:22.976774 Set Vref, RX VrefLevel [Byte0]: 31
8588 22:20:22.979930 [Byte1]: 31
8589 22:20:22.984552
8590 22:20:22.984633 Set Vref, RX VrefLevel [Byte0]: 32
8591 22:20:22.987746 [Byte1]: 32
8592 22:20:22.991756
8593 22:20:22.991838 Set Vref, RX VrefLevel [Byte0]: 33
8594 22:20:22.995195 [Byte1]: 33
8595 22:20:22.999558
8596 22:20:22.999640 Set Vref, RX VrefLevel [Byte0]: 34
8597 22:20:23.002960 [Byte1]: 34
8598 22:20:23.006928
8599 22:20:23.007010 Set Vref, RX VrefLevel [Byte0]: 35
8600 22:20:23.010215 [Byte1]: 35
8601 22:20:23.014907
8602 22:20:23.014988 Set Vref, RX VrefLevel [Byte0]: 36
8603 22:20:23.018061 [Byte1]: 36
8604 22:20:23.022372
8605 22:20:23.022448 Set Vref, RX VrefLevel [Byte0]: 37
8606 22:20:23.025323 [Byte1]: 37
8607 22:20:23.029656
8608 22:20:23.029726 Set Vref, RX VrefLevel [Byte0]: 38
8609 22:20:23.033039 [Byte1]: 38
8610 22:20:23.037631
8611 22:20:23.037700 Set Vref, RX VrefLevel [Byte0]: 39
8612 22:20:23.040571 [Byte1]: 39
8613 22:20:23.045130
8614 22:20:23.045206 Set Vref, RX VrefLevel [Byte0]: 40
8615 22:20:23.048448 [Byte1]: 40
8616 22:20:23.052671
8617 22:20:23.052775 Set Vref, RX VrefLevel [Byte0]: 41
8618 22:20:23.055554 [Byte1]: 41
8619 22:20:23.059954
8620 22:20:23.060025 Set Vref, RX VrefLevel [Byte0]: 42
8621 22:20:23.063435 [Byte1]: 42
8622 22:20:23.067771
8623 22:20:23.067872 Set Vref, RX VrefLevel [Byte0]: 43
8624 22:20:23.071250 [Byte1]: 43
8625 22:20:23.075187
8626 22:20:23.075284 Set Vref, RX VrefLevel [Byte0]: 44
8627 22:20:23.078469 [Byte1]: 44
8628 22:20:23.082621
8629 22:20:23.082722 Set Vref, RX VrefLevel [Byte0]: 45
8630 22:20:23.086400 [Byte1]: 45
8631 22:20:23.090220
8632 22:20:23.090325 Set Vref, RX VrefLevel [Byte0]: 46
8633 22:20:23.093562 [Byte1]: 46
8634 22:20:23.097966
8635 22:20:23.098068 Set Vref, RX VrefLevel [Byte0]: 47
8636 22:20:23.101133 [Byte1]: 47
8637 22:20:23.105238
8638 22:20:23.105329 Set Vref, RX VrefLevel [Byte0]: 48
8639 22:20:23.108847 [Byte1]: 48
8640 22:20:23.112875
8641 22:20:23.112985 Set Vref, RX VrefLevel [Byte0]: 49
8642 22:20:23.116173 [Byte1]: 49
8643 22:20:23.120462
8644 22:20:23.120569 Set Vref, RX VrefLevel [Byte0]: 50
8645 22:20:23.124101 [Byte1]: 50
8646 22:20:23.128428
8647 22:20:23.128507 Set Vref, RX VrefLevel [Byte0]: 51
8648 22:20:23.131849 [Byte1]: 51
8649 22:20:23.135602
8650 22:20:23.135700 Set Vref, RX VrefLevel [Byte0]: 52
8651 22:20:23.139581 [Byte1]: 52
8652 22:20:23.143534
8653 22:20:23.143631 Set Vref, RX VrefLevel [Byte0]: 53
8654 22:20:23.146871 [Byte1]: 53
8655 22:20:23.150783
8656 22:20:23.150881 Set Vref, RX VrefLevel [Byte0]: 54
8657 22:20:23.154235 [Byte1]: 54
8658 22:20:23.158388
8659 22:20:23.158492 Set Vref, RX VrefLevel [Byte0]: 55
8660 22:20:23.162123 [Byte1]: 55
8661 22:20:23.166136
8662 22:20:23.166234 Set Vref, RX VrefLevel [Byte0]: 56
8663 22:20:23.169404 [Byte1]: 56
8664 22:20:23.173655
8665 22:20:23.173752 Set Vref, RX VrefLevel [Byte0]: 57
8666 22:20:23.177115 [Byte1]: 57
8667 22:20:23.181467
8668 22:20:23.181561 Set Vref, RX VrefLevel [Byte0]: 58
8669 22:20:23.184748 [Byte1]: 58
8670 22:20:23.188944
8671 22:20:23.189047 Set Vref, RX VrefLevel [Byte0]: 59
8672 22:20:23.192513 [Byte1]: 59
8673 22:20:23.196272
8674 22:20:23.196362 Set Vref, RX VrefLevel [Byte0]: 60
8675 22:20:23.199763 [Byte1]: 60
8676 22:20:23.203934
8677 22:20:23.204040 Set Vref, RX VrefLevel [Byte0]: 61
8678 22:20:23.207027 [Byte1]: 61
8679 22:20:23.212069
8680 22:20:23.212167 Set Vref, RX VrefLevel [Byte0]: 62
8681 22:20:23.214604 [Byte1]: 62
8682 22:20:23.218951
8683 22:20:23.219061 Set Vref, RX VrefLevel [Byte0]: 63
8684 22:20:23.222376 [Byte1]: 63
8685 22:20:23.226832
8686 22:20:23.226931 Set Vref, RX VrefLevel [Byte0]: 64
8687 22:20:23.230084 [Byte1]: 64
8688 22:20:23.234364
8689 22:20:23.234460 Set Vref, RX VrefLevel [Byte0]: 65
8690 22:20:23.237487 [Byte1]: 65
8691 22:20:23.242081
8692 22:20:23.242160 Set Vref, RX VrefLevel [Byte0]: 66
8693 22:20:23.244903 [Byte1]: 66
8694 22:20:23.249482
8695 22:20:23.249558 Set Vref, RX VrefLevel [Byte0]: 67
8696 22:20:23.252910 [Byte1]: 67
8697 22:20:23.256973
8698 22:20:23.257073 Set Vref, RX VrefLevel [Byte0]: 68
8699 22:20:23.260343 [Byte1]: 68
8700 22:20:23.264668
8701 22:20:23.264769 Set Vref, RX VrefLevel [Byte0]: 69
8702 22:20:23.267669 [Byte1]: 69
8703 22:20:23.271912
8704 22:20:23.272017 Set Vref, RX VrefLevel [Byte0]: 70
8705 22:20:23.275566 [Byte1]: 70
8706 22:20:23.279854
8707 22:20:23.282697 Set Vref, RX VrefLevel [Byte0]: 71
8708 22:20:23.285918 [Byte1]: 71
8709 22:20:23.286028
8710 22:20:23.289575 Final RX Vref Byte 0 = 53 to rank0
8711 22:20:23.292700 Final RX Vref Byte 1 = 61 to rank0
8712 22:20:23.295890 Final RX Vref Byte 0 = 53 to rank1
8713 22:20:23.299233 Final RX Vref Byte 1 = 61 to rank1==
8714 22:20:23.302283 Dram Type= 6, Freq= 0, CH_1, rank 0
8715 22:20:23.306058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 22:20:23.306172 ==
8717 22:20:23.306262 DQS Delay:
8718 22:20:23.309087 DQS0 = 0, DQS1 = 0
8719 22:20:23.309167 DQM Delay:
8720 22:20:23.312209 DQM0 = 134, DQM1 = 129
8721 22:20:23.312285 DQ Delay:
8722 22:20:23.315834 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8723 22:20:23.318811 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8724 22:20:23.322390 DQ8 =114, DQ9 =118, DQ10 =134, DQ11 =122
8725 22:20:23.325783 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8726 22:20:23.325885
8727 22:20:23.328705
8728 22:20:23.328828
8729 22:20:23.328918 [DramC_TX_OE_Calibration] TA2
8730 22:20:23.332383 Original DQ_B0 (3 6) =30, OEN = 27
8731 22:20:23.335263 Original DQ_B1 (3 6) =30, OEN = 27
8732 22:20:23.338680 24, 0x0, End_B0=24 End_B1=24
8733 22:20:23.341852 25, 0x0, End_B0=25 End_B1=25
8734 22:20:23.345461 26, 0x0, End_B0=26 End_B1=26
8735 22:20:23.345549 27, 0x0, End_B0=27 End_B1=27
8736 22:20:23.348847 28, 0x0, End_B0=28 End_B1=28
8737 22:20:23.352236 29, 0x0, End_B0=29 End_B1=29
8738 22:20:23.355149 30, 0x0, End_B0=30 End_B1=30
8739 22:20:23.358636 31, 0x4545, End_B0=30 End_B1=30
8740 22:20:23.362110 Byte0 end_step=30 best_step=27
8741 22:20:23.362214 Byte1 end_step=30 best_step=27
8742 22:20:23.365025 Byte0 TX OE(2T, 0.5T) = (3, 3)
8743 22:20:23.368475 Byte1 TX OE(2T, 0.5T) = (3, 3)
8744 22:20:23.368581
8745 22:20:23.368669
8746 22:20:23.378204 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8747 22:20:23.378300 CH1 RK0: MR19=303, MR18=1927
8748 22:20:23.385332 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8749 22:20:23.385445
8750 22:20:23.388247 ----->DramcWriteLeveling(PI) begin...
8751 22:20:23.388353 ==
8752 22:20:23.391615 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 22:20:23.398427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 22:20:23.398536 ==
8755 22:20:23.401552 Write leveling (Byte 0): 24 => 24
8756 22:20:23.404979 Write leveling (Byte 1): 29 => 29
8757 22:20:23.405070 DramcWriteLeveling(PI) end<-----
8758 22:20:23.405131
8759 22:20:23.408042 ==
8760 22:20:23.411354 Dram Type= 6, Freq= 0, CH_1, rank 1
8761 22:20:23.414722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 22:20:23.414830 ==
8763 22:20:23.418088 [Gating] SW mode calibration
8764 22:20:23.424647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8765 22:20:23.428123 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8766 22:20:23.434357 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 22:20:23.437865 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 22:20:23.441222 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
8769 22:20:23.447773 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8770 22:20:23.450948 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 22:20:23.454270 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 22:20:23.461043 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 22:20:23.464424 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 22:20:23.467388 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 22:20:23.474362 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 22:20:23.477573 1 5 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)
8777 22:20:23.480958 1 5 12 | B1->B0 | 2323 3030 | 0 1 | (1 0) (1 0)
8778 22:20:23.487749 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 22:20:23.490608 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 22:20:23.494172 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 22:20:23.500520 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 22:20:23.503817 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 22:20:23.507257 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 22:20:23.513794 1 6 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8785 22:20:23.516859 1 6 12 | B1->B0 | 4444 3232 | 0 0 | (0 0) (0 0)
8786 22:20:23.520225 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 22:20:23.526846 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 22:20:23.530269 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 22:20:23.533564 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 22:20:23.540292 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 22:20:23.543602 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 22:20:23.546613 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8793 22:20:23.553117 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 22:20:23.556679 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 22:20:23.559848 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 22:20:23.566409 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 22:20:23.569790 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 22:20:23.572859 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 22:20:23.579554 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 22:20:23.583029 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:20:23.586344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:20:23.592665 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:20:23.596338 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:20:23.599310 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 22:20:23.606149 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 22:20:23.609051 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 22:20:23.612401 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 22:20:23.619417 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8809 22:20:23.622260 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8810 22:20:23.625887 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 22:20:23.629132 Total UI for P1: 0, mck2ui 16
8812 22:20:23.632415 best dqsien dly found for B0: ( 1, 9, 10)
8813 22:20:23.635756 Total UI for P1: 0, mck2ui 16
8814 22:20:23.639007 best dqsien dly found for B1: ( 1, 9, 12)
8815 22:20:23.642503 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8816 22:20:23.645608 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8817 22:20:23.645687
8818 22:20:23.652480 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8819 22:20:23.655502 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8820 22:20:23.658768 [Gating] SW calibration Done
8821 22:20:23.658841 ==
8822 22:20:23.662065 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 22:20:23.665188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 22:20:23.665259 ==
8825 22:20:23.668645 RX Vref Scan: 0
8826 22:20:23.668714
8827 22:20:23.668787 RX Vref 0 -> 0, step: 1
8828 22:20:23.668853
8829 22:20:23.671906 RX Delay 0 -> 252, step: 8
8830 22:20:23.675627 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8831 22:20:23.678788 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8832 22:20:23.685009 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8833 22:20:23.688281 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8834 22:20:23.691590 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8835 22:20:23.694924 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8836 22:20:23.698594 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8837 22:20:23.705096 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8838 22:20:23.708523 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8839 22:20:23.711581 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8840 22:20:23.715069 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8841 22:20:23.718219 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8842 22:20:23.724882 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8843 22:20:23.728174 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8844 22:20:23.731784 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8845 22:20:23.734636 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8846 22:20:23.734709 ==
8847 22:20:23.737836 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 22:20:23.744486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 22:20:23.744563 ==
8850 22:20:23.744623 DQS Delay:
8851 22:20:23.748081 DQS0 = 0, DQS1 = 0
8852 22:20:23.748153 DQM Delay:
8853 22:20:23.751082 DQM0 = 137, DQM1 = 130
8854 22:20:23.751152 DQ Delay:
8855 22:20:23.754636 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8856 22:20:23.757811 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8857 22:20:23.761205 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =127
8858 22:20:23.764333 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8859 22:20:23.764407
8860 22:20:23.764467
8861 22:20:23.764527 ==
8862 22:20:23.767612 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 22:20:23.774050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 22:20:23.774136 ==
8865 22:20:23.774200
8866 22:20:23.774260
8867 22:20:23.774318 TX Vref Scan disable
8868 22:20:23.777893 == TX Byte 0 ==
8869 22:20:23.781143 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8870 22:20:23.787890 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8871 22:20:23.787972 == TX Byte 1 ==
8872 22:20:23.791062 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8873 22:20:23.797871 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8874 22:20:23.797953 ==
8875 22:20:23.800707 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 22:20:23.804256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 22:20:23.804338 ==
8878 22:20:23.816879
8879 22:20:23.820252 TX Vref early break, caculate TX vref
8880 22:20:23.823559 TX Vref=16, minBit 9, minWin=22, winSum=384
8881 22:20:23.826517 TX Vref=18, minBit 9, minWin=22, winSum=391
8882 22:20:23.829965 TX Vref=20, minBit 13, minWin=23, winSum=404
8883 22:20:23.833134 TX Vref=22, minBit 9, minWin=24, winSum=408
8884 22:20:23.840008 TX Vref=24, minBit 13, minWin=24, winSum=416
8885 22:20:23.843431 TX Vref=26, minBit 13, minWin=25, winSum=426
8886 22:20:23.846635 TX Vref=28, minBit 10, minWin=25, winSum=422
8887 22:20:23.849681 TX Vref=30, minBit 9, minWin=25, winSum=421
8888 22:20:23.852866 TX Vref=32, minBit 9, minWin=24, winSum=412
8889 22:20:23.856554 TX Vref=34, minBit 10, minWin=23, winSum=403
8890 22:20:23.862917 [TxChooseVref] Worse bit 13, Min win 25, Win sum 426, Final Vref 26
8891 22:20:23.862999
8892 22:20:23.866149 Final TX Range 0 Vref 26
8893 22:20:23.866231
8894 22:20:23.866295 ==
8895 22:20:23.869597 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 22:20:23.872967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 22:20:23.873050 ==
8898 22:20:23.876118
8899 22:20:23.876199
8900 22:20:23.876263 TX Vref Scan disable
8901 22:20:23.882486 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8902 22:20:23.882570 == TX Byte 0 ==
8903 22:20:23.886279 u2DelayCellOfst[0]=13 cells (4 PI)
8904 22:20:23.889238 u2DelayCellOfst[1]=6 cells (2 PI)
8905 22:20:23.892417 u2DelayCellOfst[2]=0 cells (0 PI)
8906 22:20:23.895853 u2DelayCellOfst[3]=3 cells (1 PI)
8907 22:20:23.899238 u2DelayCellOfst[4]=6 cells (2 PI)
8908 22:20:23.902203 u2DelayCellOfst[5]=16 cells (5 PI)
8909 22:20:23.905622 u2DelayCellOfst[6]=16 cells (5 PI)
8910 22:20:23.909007 u2DelayCellOfst[7]=3 cells (1 PI)
8911 22:20:23.912455 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8912 22:20:23.915681 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8913 22:20:23.919018 == TX Byte 1 ==
8914 22:20:23.922282 u2DelayCellOfst[8]=0 cells (0 PI)
8915 22:20:23.925342 u2DelayCellOfst[9]=6 cells (2 PI)
8916 22:20:23.929003 u2DelayCellOfst[10]=10 cells (3 PI)
8917 22:20:23.932235 u2DelayCellOfst[11]=3 cells (1 PI)
8918 22:20:23.935194 u2DelayCellOfst[12]=13 cells (4 PI)
8919 22:20:23.938650 u2DelayCellOfst[13]=16 cells (5 PI)
8920 22:20:23.941950 u2DelayCellOfst[14]=16 cells (5 PI)
8921 22:20:23.942032 u2DelayCellOfst[15]=13 cells (4 PI)
8922 22:20:23.948576 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8923 22:20:23.951903 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8924 22:20:23.955189 DramC Write-DBI on
8925 22:20:23.955271 ==
8926 22:20:23.958380 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 22:20:23.961858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 22:20:23.961940 ==
8929 22:20:23.962004
8930 22:20:23.962064
8931 22:20:23.964803 TX Vref Scan disable
8932 22:20:23.964884 == TX Byte 0 ==
8933 22:20:23.971371 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8934 22:20:23.971453 == TX Byte 1 ==
8935 22:20:23.975106 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8936 22:20:23.978262 DramC Write-DBI off
8937 22:20:23.978344
8938 22:20:23.978409 [DATLAT]
8939 22:20:23.981724 Freq=1600, CH1 RK1
8940 22:20:23.981806
8941 22:20:23.981871 DATLAT Default: 0xf
8942 22:20:23.984826 0, 0xFFFF, sum = 0
8943 22:20:23.984910 1, 0xFFFF, sum = 0
8944 22:20:23.988071 2, 0xFFFF, sum = 0
8945 22:20:23.991344 3, 0xFFFF, sum = 0
8946 22:20:23.991427 4, 0xFFFF, sum = 0
8947 22:20:23.994814 5, 0xFFFF, sum = 0
8948 22:20:23.994897 6, 0xFFFF, sum = 0
8949 22:20:23.997987 7, 0xFFFF, sum = 0
8950 22:20:23.998071 8, 0xFFFF, sum = 0
8951 22:20:24.001213 9, 0xFFFF, sum = 0
8952 22:20:24.001296 10, 0xFFFF, sum = 0
8953 22:20:24.004490 11, 0xFFFF, sum = 0
8954 22:20:24.004574 12, 0xFFFF, sum = 0
8955 22:20:24.007785 13, 0xFFFF, sum = 0
8956 22:20:24.007868 14, 0x0, sum = 1
8957 22:20:24.010933 15, 0x0, sum = 2
8958 22:20:24.011016 16, 0x0, sum = 3
8959 22:20:24.014321 17, 0x0, sum = 4
8960 22:20:24.014404 best_step = 15
8961 22:20:24.014469
8962 22:20:24.014530 ==
8963 22:20:24.017477 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 22:20:24.024308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 22:20:24.024390 ==
8966 22:20:24.024455 RX Vref Scan: 0
8967 22:20:24.024515
8968 22:20:24.027658 RX Vref 0 -> 0, step: 1
8969 22:20:24.027741
8970 22:20:24.030918 RX Delay 11 -> 252, step: 4
8971 22:20:24.034443 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8972 22:20:24.037395 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8973 22:20:24.041012 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8974 22:20:24.047339 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8975 22:20:24.050602 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8976 22:20:24.053921 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8977 22:20:24.057349 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8978 22:20:24.060447 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8979 22:20:24.063981 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8980 22:20:24.070505 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8981 22:20:24.073859 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8982 22:20:24.076971 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8983 22:20:24.080432 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8984 22:20:24.086898 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8985 22:20:24.090558 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8986 22:20:24.093860 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8987 22:20:24.093942 ==
8988 22:20:24.096833 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 22:20:24.100119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 22:20:24.100202 ==
8991 22:20:24.103896 DQS Delay:
8992 22:20:24.103978 DQS0 = 0, DQS1 = 0
8993 22:20:24.107139 DQM Delay:
8994 22:20:24.107221 DQM0 = 134, DQM1 = 129
8995 22:20:24.107286 DQ Delay:
8996 22:20:24.113718 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8997 22:20:24.116794 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
8998 22:20:24.120344 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8999 22:20:24.123188 DQ12 =136, DQ13 =136, DQ14 =138, DQ15 =140
9000 22:20:24.123270
9001 22:20:24.123333
9002 22:20:24.123393
9003 22:20:24.126508 [DramC_TX_OE_Calibration] TA2
9004 22:20:24.129813 Original DQ_B0 (3 6) =30, OEN = 27
9005 22:20:24.133164 Original DQ_B1 (3 6) =30, OEN = 27
9006 22:20:24.133246 24, 0x0, End_B0=24 End_B1=24
9007 22:20:24.136577 25, 0x0, End_B0=25 End_B1=25
9008 22:20:24.140012 26, 0x0, End_B0=26 End_B1=26
9009 22:20:24.143202 27, 0x0, End_B0=27 End_B1=27
9010 22:20:24.146849 28, 0x0, End_B0=28 End_B1=28
9011 22:20:24.146933 29, 0x0, End_B0=29 End_B1=29
9012 22:20:24.149750 30, 0x0, End_B0=30 End_B1=30
9013 22:20:24.152849 31, 0x4141, End_B0=30 End_B1=30
9014 22:20:24.156505 Byte0 end_step=30 best_step=27
9015 22:20:24.159576 Byte1 end_step=30 best_step=27
9016 22:20:24.163132 Byte0 TX OE(2T, 0.5T) = (3, 3)
9017 22:20:24.163214 Byte1 TX OE(2T, 0.5T) = (3, 3)
9018 22:20:24.163279
9019 22:20:24.166150
9020 22:20:24.172836 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9021 22:20:24.176082 CH1 RK1: MR19=303, MR18=1E09
9022 22:20:24.182790 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9023 22:20:24.185856 [RxdqsGatingPostProcess] freq 1600
9024 22:20:24.189347 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9025 22:20:24.192529 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 22:20:24.195894 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 22:20:24.199448 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 22:20:24.202634 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 22:20:24.206081 best DQS0 dly(2T, 0.5T) = (1, 1)
9030 22:20:24.209157 best DQS1 dly(2T, 0.5T) = (1, 1)
9031 22:20:24.212505 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9032 22:20:24.215801 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9033 22:20:24.219050 Pre-setting of DQS Precalculation
9034 22:20:24.222684 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9035 22:20:24.228912 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9036 22:20:24.235530 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9037 22:20:24.238969
9038 22:20:24.239050
9039 22:20:24.239114 [Calibration Summary] 3200 Mbps
9040 22:20:24.242232 CH 0, Rank 0
9041 22:20:24.242313 SW Impedance : PASS
9042 22:20:24.245306 DUTY Scan : NO K
9043 22:20:24.248491 ZQ Calibration : PASS
9044 22:20:24.248573 Jitter Meter : NO K
9045 22:20:24.252323 CBT Training : PASS
9046 22:20:24.255329 Write leveling : PASS
9047 22:20:24.255411 RX DQS gating : PASS
9048 22:20:24.258684 RX DQ/DQS(RDDQC) : PASS
9049 22:20:24.261990 TX DQ/DQS : PASS
9050 22:20:24.262072 RX DATLAT : PASS
9051 22:20:24.265427 RX DQ/DQS(Engine): PASS
9052 22:20:24.268570 TX OE : PASS
9053 22:20:24.268652 All Pass.
9054 22:20:24.268717
9055 22:20:24.268781 CH 0, Rank 1
9056 22:20:24.271759 SW Impedance : PASS
9057 22:20:24.274936 DUTY Scan : NO K
9058 22:20:24.275017 ZQ Calibration : PASS
9059 22:20:24.278468 Jitter Meter : NO K
9060 22:20:24.281817 CBT Training : PASS
9061 22:20:24.281899 Write leveling : PASS
9062 22:20:24.284972 RX DQS gating : PASS
9063 22:20:24.288132 RX DQ/DQS(RDDQC) : PASS
9064 22:20:24.288213 TX DQ/DQS : PASS
9065 22:20:24.291618 RX DATLAT : PASS
9066 22:20:24.294954 RX DQ/DQS(Engine): PASS
9067 22:20:24.295036 TX OE : PASS
9068 22:20:24.295102 All Pass.
9069 22:20:24.298158
9070 22:20:24.298240 CH 1, Rank 0
9071 22:20:24.301430 SW Impedance : PASS
9072 22:20:24.301513 DUTY Scan : NO K
9073 22:20:24.304919 ZQ Calibration : PASS
9074 22:20:24.305002 Jitter Meter : NO K
9075 22:20:24.308195 CBT Training : PASS
9076 22:20:24.311771 Write leveling : PASS
9077 22:20:24.311854 RX DQS gating : PASS
9078 22:20:24.314957 RX DQ/DQS(RDDQC) : PASS
9079 22:20:24.317980 TX DQ/DQS : PASS
9080 22:20:24.318063 RX DATLAT : PASS
9081 22:20:24.321100 RX DQ/DQS(Engine): PASS
9082 22:20:24.324363 TX OE : PASS
9083 22:20:24.324445 All Pass.
9084 22:20:24.324511
9085 22:20:24.324571 CH 1, Rank 1
9086 22:20:24.328077 SW Impedance : PASS
9087 22:20:24.331171 DUTY Scan : NO K
9088 22:20:24.331254 ZQ Calibration : PASS
9089 22:20:24.334457 Jitter Meter : NO K
9090 22:20:24.337897 CBT Training : PASS
9091 22:20:24.337978 Write leveling : PASS
9092 22:20:24.340964 RX DQS gating : PASS
9093 22:20:24.344413 RX DQ/DQS(RDDQC) : PASS
9094 22:20:24.344494 TX DQ/DQS : PASS
9095 22:20:24.347833 RX DATLAT : PASS
9096 22:20:24.351185 RX DQ/DQS(Engine): PASS
9097 22:20:24.351267 TX OE : PASS
9098 22:20:24.354391 All Pass.
9099 22:20:24.354473
9100 22:20:24.354537 DramC Write-DBI on
9101 22:20:24.357731 PER_BANK_REFRESH: Hybrid Mode
9102 22:20:24.357813 TX_TRACKING: ON
9103 22:20:24.367359 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9104 22:20:24.377257 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9105 22:20:24.383762 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9106 22:20:24.387238 [FAST_K] Save calibration result to emmc
9107 22:20:24.390671 sync common calibartion params.
9108 22:20:24.390779 sync cbt_mode0:1, 1:1
9109 22:20:24.394046 dram_init: ddr_geometry: 2
9110 22:20:24.397433 dram_init: ddr_geometry: 2
9111 22:20:24.397515 dram_init: ddr_geometry: 2
9112 22:20:24.400611 0:dram_rank_size:100000000
9113 22:20:24.403559 1:dram_rank_size:100000000
9114 22:20:24.410160 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9115 22:20:24.410246 DFS_SHUFFLE_HW_MODE: ON
9116 22:20:24.413686 dramc_set_vcore_voltage set vcore to 725000
9117 22:20:24.416918 Read voltage for 1600, 0
9118 22:20:24.417026 Vio18 = 0
9119 22:20:24.420228 Vcore = 725000
9120 22:20:24.420309 Vdram = 0
9121 22:20:24.420373 Vddq = 0
9122 22:20:24.423328 Vmddr = 0
9123 22:20:24.423408 switch to 3200 Mbps bootup
9124 22:20:24.426887 [DramcRunTimeConfig]
9125 22:20:24.426968 PHYPLL
9126 22:20:24.429880 DPM_CONTROL_AFTERK: ON
9127 22:20:24.429962 PER_BANK_REFRESH: ON
9128 22:20:24.433384 REFRESH_OVERHEAD_REDUCTION: ON
9129 22:20:24.436657 CMD_PICG_NEW_MODE: OFF
9130 22:20:24.436754 XRTWTW_NEW_MODE: ON
9131 22:20:24.439845 XRTRTR_NEW_MODE: ON
9132 22:20:24.439927 TX_TRACKING: ON
9133 22:20:24.443320 RDSEL_TRACKING: OFF
9134 22:20:24.446644 DQS Precalculation for DVFS: ON
9135 22:20:24.446725 RX_TRACKING: OFF
9136 22:20:24.450006 HW_GATING DBG: ON
9137 22:20:24.450088 ZQCS_ENABLE_LP4: ON
9138 22:20:24.453140 RX_PICG_NEW_MODE: ON
9139 22:20:24.453222 TX_PICG_NEW_MODE: ON
9140 22:20:24.456751 ENABLE_RX_DCM_DPHY: ON
9141 22:20:24.460003 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9142 22:20:24.463207 DUMMY_READ_FOR_TRACKING: OFF
9143 22:20:24.466273 !!! SPM_CONTROL_AFTERK: OFF
9144 22:20:24.466390 !!! SPM could not control APHY
9145 22:20:24.469624 IMPEDANCE_TRACKING: ON
9146 22:20:24.472839 TEMP_SENSOR: ON
9147 22:20:24.472921 HW_SAVE_FOR_SR: OFF
9148 22:20:24.476309 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9149 22:20:24.479650 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9150 22:20:24.483056 Read ODT Tracking: ON
9151 22:20:24.483138 Refresh Rate DeBounce: ON
9152 22:20:24.486453 DFS_NO_QUEUE_FLUSH: ON
9153 22:20:24.489361 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9154 22:20:24.492749 ENABLE_DFS_RUNTIME_MRW: OFF
9155 22:20:24.492873 DDR_RESERVE_NEW_MODE: ON
9156 22:20:24.496122 MR_CBT_SWITCH_FREQ: ON
9157 22:20:24.499246 =========================
9158 22:20:24.517393 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9159 22:20:24.520964 dram_init: ddr_geometry: 2
9160 22:20:24.539018 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9161 22:20:24.542039 dram_init: dram init end (result: 0)
9162 22:20:24.548971 DRAM-K: Full calibration passed in 24429 msecs
9163 22:20:24.552175 MRC: failed to locate region type 0.
9164 22:20:24.552297 DRAM rank0 size:0x100000000,
9165 22:20:24.555219 DRAM rank1 size=0x100000000
9166 22:20:24.565284 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9167 22:20:24.571814 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9168 22:20:24.578423 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9169 22:20:24.588412 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9170 22:20:24.588521 DRAM rank0 size:0x100000000,
9171 22:20:24.591410 DRAM rank1 size=0x100000000
9172 22:20:24.591485 CBMEM:
9173 22:20:24.595201 IMD: root @ 0xfffff000 254 entries.
9174 22:20:24.598407 IMD: root @ 0xffffec00 62 entries.
9175 22:20:24.601612 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9176 22:20:24.608229 WARNING: RO_VPD is uninitialized or empty.
9177 22:20:24.611601 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9178 22:20:24.618737 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9179 22:20:24.631804 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9180 22:20:24.643014 BS: romstage times (exec / console): total (unknown) / 23956 ms
9181 22:20:24.643123
9182 22:20:24.643189
9183 22:20:24.653019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9184 22:20:24.656309 ARM64: Exception handlers installed.
9185 22:20:24.659593 ARM64: Testing exception
9186 22:20:24.662976 ARM64: Done test exception
9187 22:20:24.663085 Enumerating buses...
9188 22:20:24.666582 Show all devs... Before device enumeration.
9189 22:20:24.669742 Root Device: enabled 1
9190 22:20:24.672747 CPU_CLUSTER: 0: enabled 1
9191 22:20:24.672845 CPU: 00: enabled 1
9192 22:20:24.676289 Compare with tree...
9193 22:20:24.676391 Root Device: enabled 1
9194 22:20:24.679498 CPU_CLUSTER: 0: enabled 1
9195 22:20:24.682511 CPU: 00: enabled 1
9196 22:20:24.682618 Root Device scanning...
9197 22:20:24.685965 scan_static_bus for Root Device
9198 22:20:24.689474 CPU_CLUSTER: 0 enabled
9199 22:20:24.692547 scan_static_bus for Root Device done
9200 22:20:24.696101 scan_bus: bus Root Device finished in 8 msecs
9201 22:20:24.696201 done
9202 22:20:24.702544 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9203 22:20:24.705693 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9204 22:20:24.712357 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9205 22:20:24.716049 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9206 22:20:24.719157 Allocating resources...
9207 22:20:24.722426 Reading resources...
9208 22:20:24.725702 Root Device read_resources bus 0 link: 0
9209 22:20:24.728773 DRAM rank0 size:0x100000000,
9210 22:20:24.728848 DRAM rank1 size=0x100000000
9211 22:20:24.736326 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9212 22:20:24.736408 CPU: 00 missing read_resources
9213 22:20:24.742456 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9214 22:20:24.745362 Root Device read_resources bus 0 link: 0 done
9215 22:20:24.745444 Done reading resources.
9216 22:20:24.752285 Show resources in subtree (Root Device)...After reading.
9217 22:20:24.755302 Root Device child on link 0 CPU_CLUSTER: 0
9218 22:20:24.758696 CPU_CLUSTER: 0 child on link 0 CPU: 00
9219 22:20:24.768450 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9220 22:20:24.768559 CPU: 00
9221 22:20:24.771762 Root Device assign_resources, bus 0 link: 0
9222 22:20:24.775224 CPU_CLUSTER: 0 missing set_resources
9223 22:20:24.782080 Root Device assign_resources, bus 0 link: 0 done
9224 22:20:24.782181 Done setting resources.
9225 22:20:24.788590 Show resources in subtree (Root Device)...After assigning values.
9226 22:20:24.791826 Root Device child on link 0 CPU_CLUSTER: 0
9227 22:20:24.795111 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 22:20:24.804928 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 22:20:24.805012 CPU: 00
9230 22:20:24.808094 Done allocating resources.
9231 22:20:24.814940 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9232 22:20:24.815023 Enabling resources...
9233 22:20:24.815087 done.
9234 22:20:24.821495 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9235 22:20:24.824588 Initializing devices...
9236 22:20:24.824695 Root Device init
9237 22:20:24.828066 init hardware done!
9238 22:20:24.828148 0x00000018: ctrlr->caps
9239 22:20:24.831621 52.000 MHz: ctrlr->f_max
9240 22:20:24.834653 0.400 MHz: ctrlr->f_min
9241 22:20:24.834737 0x40ff8080: ctrlr->voltages
9242 22:20:24.837863 sclk: 390625
9243 22:20:24.837944 Bus Width = 1
9244 22:20:24.838009 sclk: 390625
9245 22:20:24.841472 Bus Width = 1
9246 22:20:24.845101 Early init status = 3
9247 22:20:24.847727 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9248 22:20:24.851850 in-header: 03 fc 00 00 01 00 00 00
9249 22:20:24.854933 in-data: 00
9250 22:20:24.858361 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9251 22:20:24.863960 in-header: 03 fd 00 00 00 00 00 00
9252 22:20:24.867344 in-data:
9253 22:20:24.870367 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9254 22:20:24.874804 in-header: 03 fc 00 00 01 00 00 00
9255 22:20:24.877952 in-data: 00
9256 22:20:24.881132 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9257 22:20:24.887189 in-header: 03 fd 00 00 00 00 00 00
9258 22:20:24.890467 in-data:
9259 22:20:24.893887 [SSUSB] Setting up USB HOST controller...
9260 22:20:24.896952 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9261 22:20:24.900195 [SSUSB] phy power-on done.
9262 22:20:24.903615 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9263 22:20:24.910154 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9264 22:20:24.913491 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9265 22:20:24.920298 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9266 22:20:24.926811 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9267 22:20:24.933132 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9268 22:20:24.939753 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9269 22:20:24.946622 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9270 22:20:24.949699 SPM: binary array size = 0x9dc
9271 22:20:24.953379 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9272 22:20:24.959498 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9273 22:20:24.966045 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9274 22:20:24.972886 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9275 22:20:24.976033 configure_display: Starting display init
9276 22:20:25.010131 anx7625_power_on_init: Init interface.
9277 22:20:25.013743 anx7625_disable_pd_protocol: Disabled PD feature.
9278 22:20:25.016884 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9279 22:20:25.044801 anx7625_start_dp_work: Secure OCM version=00
9280 22:20:25.048080 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9281 22:20:25.062994 sp_tx_get_edid_block: EDID Block = 1
9282 22:20:25.165346 Extracted contents:
9283 22:20:25.168864 header: 00 ff ff ff ff ff ff 00
9284 22:20:25.172279 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9285 22:20:25.175460 version: 01 04
9286 22:20:25.178600 basic params: 95 1f 11 78 0a
9287 22:20:25.182098 chroma info: 76 90 94 55 54 90 27 21 50 54
9288 22:20:25.185136 established: 00 00 00
9289 22:20:25.191739 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9290 22:20:25.195167 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9291 22:20:25.201674 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9292 22:20:25.208301 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9293 22:20:25.214955 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9294 22:20:25.218261 extensions: 00
9295 22:20:25.218344 checksum: fb
9296 22:20:25.218408
9297 22:20:25.224741 Manufacturer: IVO Model 57d Serial Number 0
9298 22:20:25.224829 Made week 0 of 2020
9299 22:20:25.227810 EDID version: 1.4
9300 22:20:25.227892 Digital display
9301 22:20:25.231279 6 bits per primary color channel
9302 22:20:25.234643 DisplayPort interface
9303 22:20:25.234724 Maximum image size: 31 cm x 17 cm
9304 22:20:25.238091 Gamma: 220%
9305 22:20:25.238172 Check DPMS levels
9306 22:20:25.244598 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9307 22:20:25.247960 First detailed timing is preferred timing
9308 22:20:25.248043 Established timings supported:
9309 22:20:25.251237 Standard timings supported:
9310 22:20:25.254213 Detailed timings
9311 22:20:25.257720 Hex of detail: 383680a07038204018303c0035ae10000019
9312 22:20:25.264403 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9313 22:20:25.267703 0780 0798 07c8 0820 hborder 0
9314 22:20:25.270686 0438 043b 0447 0458 vborder 0
9315 22:20:25.274228 -hsync -vsync
9316 22:20:25.274310 Did detailed timing
9317 22:20:25.281116 Hex of detail: 000000000000000000000000000000000000
9318 22:20:25.284099 Manufacturer-specified data, tag 0
9319 22:20:25.287408 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9320 22:20:25.290677 ASCII string: InfoVision
9321 22:20:25.293951 Hex of detail: 000000fe00523134304e574635205248200a
9322 22:20:25.297391 ASCII string: R140NWF5 RH
9323 22:20:25.297471 Checksum
9324 22:20:25.300829 Checksum: 0xfb (valid)
9325 22:20:25.303814 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9326 22:20:25.307462 DSI data_rate: 832800000 bps
9327 22:20:25.313734 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9328 22:20:25.316985 anx7625_parse_edid: pixelclock(138800).
9329 22:20:25.320509 hactive(1920), hsync(48), hfp(24), hbp(88)
9330 22:20:25.323955 vactive(1080), vsync(12), vfp(3), vbp(17)
9331 22:20:25.326991 anx7625_dsi_config: config dsi.
9332 22:20:25.333468 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9333 22:20:25.347348 anx7625_dsi_config: success to config DSI
9334 22:20:25.350776 anx7625_dp_start: MIPI phy setup OK.
9335 22:20:25.354003 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9336 22:20:25.357313 mtk_ddp_mode_set invalid vrefresh 60
9337 22:20:25.360878 main_disp_path_setup
9338 22:20:25.361017 ovl_layer_smi_id_en
9339 22:20:25.363647 ovl_layer_smi_id_en
9340 22:20:25.363796 ccorr_config
9341 22:20:25.363913 aal_config
9342 22:20:25.367265 gamma_config
9343 22:20:25.367394 postmask_config
9344 22:20:25.370597 dither_config
9345 22:20:25.373622 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9346 22:20:25.380550 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9347 22:20:25.383958 Root Device init finished in 555 msecs
9348 22:20:25.386891 CPU_CLUSTER: 0 init
9349 22:20:25.393862 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9350 22:20:25.400405 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9351 22:20:25.400683 APU_MBOX 0x190000b0 = 0x10001
9352 22:20:25.403372 APU_MBOX 0x190001b0 = 0x10001
9353 22:20:25.406956 APU_MBOX 0x190005b0 = 0x10001
9354 22:20:25.410100 APU_MBOX 0x190006b0 = 0x10001
9355 22:20:25.416684 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9356 22:20:25.426684 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9357 22:20:25.439226 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9358 22:20:25.445208 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9359 22:20:25.457220 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9360 22:20:25.466361 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9361 22:20:25.469347 CPU_CLUSTER: 0 init finished in 81 msecs
9362 22:20:25.472731 Devices initialized
9363 22:20:25.476226 Show all devs... After init.
9364 22:20:25.476339 Root Device: enabled 1
9365 22:20:25.479501 CPU_CLUSTER: 0: enabled 1
9366 22:20:25.482926 CPU: 00: enabled 1
9367 22:20:25.486396 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9368 22:20:25.489364 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9369 22:20:25.492723 ELOG: NV offset 0x57f000 size 0x1000
9370 22:20:25.499070 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9371 22:20:25.506077 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9372 22:20:25.508923 ELOG: Event(17) added with size 13 at 2023-06-05 22:20:22 UTC
9373 22:20:25.515794 out: cmd=0x121: 03 db 21 01 00 00 00 00
9374 22:20:25.519157 in-header: 03 5c 00 00 2c 00 00 00
9375 22:20:25.528716 in-data: 03 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9376 22:20:25.535440 ELOG: Event(A1) added with size 10 at 2023-06-05 22:20:22 UTC
9377 22:20:25.541920 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9378 22:20:25.548597 ELOG: Event(A0) added with size 9 at 2023-06-05 22:20:22 UTC
9379 22:20:25.552168 elog_add_boot_reason: Logged dev mode boot
9380 22:20:25.558299 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9381 22:20:25.558374 Finalize devices...
9382 22:20:25.562096 Devices finalized
9383 22:20:25.565007 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9384 22:20:25.568369 Writing coreboot table at 0xffe64000
9385 22:20:25.571595 0. 000000000010a000-0000000000113fff: RAMSTAGE
9386 22:20:25.578368 1. 0000000040000000-00000000400fffff: RAM
9387 22:20:25.581516 2. 0000000040100000-000000004032afff: RAMSTAGE
9388 22:20:25.584880 3. 000000004032b000-00000000545fffff: RAM
9389 22:20:25.587984 4. 0000000054600000-000000005465ffff: BL31
9390 22:20:25.591305 5. 0000000054660000-00000000ffe63fff: RAM
9391 22:20:25.598242 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9392 22:20:25.601430 7. 0000000100000000-000000023fffffff: RAM
9393 22:20:25.604478 Passing 5 GPIOs to payload:
9394 22:20:25.607953 NAME | PORT | POLARITY | VALUE
9395 22:20:25.614748 EC in RW | 0x000000aa | low | undefined
9396 22:20:25.617916 EC interrupt | 0x00000005 | low | undefined
9397 22:20:25.624345 TPM interrupt | 0x000000ab | high | undefined
9398 22:20:25.627892 SD card detect | 0x00000011 | high | undefined
9399 22:20:25.630888 speaker enable | 0x00000093 | high | undefined
9400 22:20:25.634141 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9401 22:20:25.637513 in-header: 03 f9 00 00 02 00 00 00
9402 22:20:25.640903 in-data: 02 00
9403 22:20:25.644395 ADC[4]: Raw value=901032 ID=7
9404 22:20:25.647337 ADC[3]: Raw value=213179 ID=1
9405 22:20:25.647419 RAM Code: 0x71
9406 22:20:25.650880 ADC[6]: Raw value=74502 ID=0
9407 22:20:25.654303 ADC[5]: Raw value=212810 ID=1
9408 22:20:25.654385 SKU Code: 0x1
9409 22:20:25.660655 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9410 22:20:25.660738 coreboot table: 964 bytes.
9411 22:20:25.664157 IMD ROOT 0. 0xfffff000 0x00001000
9412 22:20:25.667100 IMD SMALL 1. 0xffffe000 0x00001000
9413 22:20:25.670601 RO MCACHE 2. 0xffffc000 0x00001104
9414 22:20:25.673856 CONSOLE 3. 0xfff7c000 0x00080000
9415 22:20:25.677429 FMAP 4. 0xfff7b000 0x00000452
9416 22:20:25.680524 TIME STAMP 5. 0xfff7a000 0x00000910
9417 22:20:25.684292 VBOOT WORK 6. 0xfff66000 0x00014000
9418 22:20:25.687460 RAMOOPS 7. 0xffe66000 0x00100000
9419 22:20:25.690503 COREBOOT 8. 0xffe64000 0x00002000
9420 22:20:25.693950 IMD small region:
9421 22:20:25.697086 IMD ROOT 0. 0xffffec00 0x00000400
9422 22:20:25.700381 VPD 1. 0xffffeba0 0x0000004c
9423 22:20:25.703739 MMC STATUS 2. 0xffffeb80 0x00000004
9424 22:20:25.710225 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9425 22:20:25.710309 Probing TPM: done!
9426 22:20:25.713952 Connected to device vid:did:rid of 1ae0:0028:00
9427 22:20:25.724921 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9428 22:20:25.728493 Initialized TPM device CR50 revision 0
9429 22:20:25.731882 Checking cr50 for pending updates
9430 22:20:25.735712 Reading cr50 TPM mode
9431 22:20:25.744136 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9432 22:20:25.751105 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9433 22:20:25.790970 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9434 22:20:25.794277 Checking segment from ROM address 0x40100000
9435 22:20:25.797511 Checking segment from ROM address 0x4010001c
9436 22:20:25.804287 Loading segment from ROM address 0x40100000
9437 22:20:25.804364 code (compression=0)
9438 22:20:25.814521 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9439 22:20:25.821035 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9440 22:20:25.821122 it's not compressed!
9441 22:20:25.827485 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9442 22:20:25.833973 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9443 22:20:25.851622 Loading segment from ROM address 0x4010001c
9444 22:20:25.851706 Entry Point 0x80000000
9445 22:20:25.854763 Loaded segments
9446 22:20:25.858233 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9447 22:20:25.864919 Jumping to boot code at 0x80000000(0xffe64000)
9448 22:20:25.871255 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9449 22:20:25.877861 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9450 22:20:25.886084 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9451 22:20:25.889117 Checking segment from ROM address 0x40100000
9452 22:20:25.892201 Checking segment from ROM address 0x4010001c
9453 22:20:25.899095 Loading segment from ROM address 0x40100000
9454 22:20:25.899172 code (compression=1)
9455 22:20:25.905656 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9456 22:20:25.915401 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9457 22:20:25.915483 using LZMA
9458 22:20:25.924241 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9459 22:20:25.930784 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9460 22:20:25.934371 Loading segment from ROM address 0x4010001c
9461 22:20:25.934447 Entry Point 0x54601000
9462 22:20:25.937507 Loaded segments
9463 22:20:25.940926 NOTICE: MT8192 bl31_setup
9464 22:20:25.947797 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9465 22:20:25.951090 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9466 22:20:25.954488 WARNING: region 0:
9467 22:20:25.957804 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 22:20:25.957879 WARNING: region 1:
9469 22:20:25.964180 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9470 22:20:25.967607 WARNING: region 2:
9471 22:20:25.970952 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9472 22:20:25.974354 WARNING: region 3:
9473 22:20:25.977379 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9474 22:20:25.980879 WARNING: region 4:
9475 22:20:25.987445 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9476 22:20:25.987523 WARNING: region 5:
9477 22:20:25.990733 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 22:20:25.994354 WARNING: region 6:
9479 22:20:25.997507 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 22:20:26.000679 WARNING: region 7:
9481 22:20:26.003715 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9482 22:20:26.010588 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9483 22:20:26.013871 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9484 22:20:26.020365 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9485 22:20:26.023798 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9486 22:20:26.027010 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9487 22:20:26.033762 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9488 22:20:26.037030 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9489 22:20:26.040652 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9490 22:20:26.047008 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9491 22:20:26.050122 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9492 22:20:26.057063 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9493 22:20:26.060491 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9494 22:20:26.063445 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9495 22:20:26.070193 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9496 22:20:26.073389 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9497 22:20:26.076796 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9498 22:20:26.083650 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9499 22:20:26.086642 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9500 22:20:26.093337 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9501 22:20:26.096725 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9502 22:20:26.100055 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9503 22:20:26.106881 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9504 22:20:26.110044 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9505 22:20:26.113985 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9506 22:20:26.120296 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9507 22:20:26.123281 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9508 22:20:26.130085 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9509 22:20:26.133590 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9510 22:20:26.140502 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9511 22:20:26.143334 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9512 22:20:26.146883 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9513 22:20:26.153393 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9514 22:20:26.156563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9515 22:20:26.159926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9516 22:20:26.163322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9517 22:20:26.169875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9518 22:20:26.172971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9519 22:20:26.176406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9520 22:20:26.179960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9521 22:20:26.186486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9522 22:20:26.189926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9523 22:20:26.193055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9524 22:20:26.196455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9525 22:20:26.203070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9526 22:20:26.206158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9527 22:20:26.209828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9528 22:20:26.213249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9529 22:20:26.219666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9530 22:20:26.223017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9531 22:20:26.229627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9532 22:20:26.232972 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9533 22:20:26.239575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9534 22:20:26.242697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9535 22:20:26.246267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9536 22:20:26.252917 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9537 22:20:26.255887 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9538 22:20:26.262673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9539 22:20:26.266270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9540 22:20:26.272527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9541 22:20:26.275800 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9542 22:20:26.279134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9543 22:20:26.285715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9544 22:20:26.289207 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9545 22:20:26.296082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9546 22:20:26.299212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9547 22:20:26.305805 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9548 22:20:26.309030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9549 22:20:26.315658 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9550 22:20:26.318952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9551 22:20:26.322363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9552 22:20:26.329447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9553 22:20:26.332418 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9554 22:20:26.339331 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9555 22:20:26.342149 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9556 22:20:26.348873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9557 22:20:26.352254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9558 22:20:26.355405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9559 22:20:26.362171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9560 22:20:26.365832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9561 22:20:26.372361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9562 22:20:26.375293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9563 22:20:26.382099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9564 22:20:26.385519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9565 22:20:26.392107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9566 22:20:26.395540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9567 22:20:26.398881 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9568 22:20:26.405159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9569 22:20:26.408666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9570 22:20:26.415148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9571 22:20:26.418564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9572 22:20:26.425397 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9573 22:20:26.428419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9574 22:20:26.435075 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9575 22:20:26.438595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9576 22:20:26.441848 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9577 22:20:26.448442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9578 22:20:26.451697 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9579 22:20:26.455130 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9580 22:20:26.461980 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9581 22:20:26.465194 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9582 22:20:26.468380 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9583 22:20:26.474980 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9584 22:20:26.478132 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9585 22:20:26.481466 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9586 22:20:26.488390 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9587 22:20:26.491629 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9588 22:20:26.498252 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9589 22:20:26.501591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9590 22:20:26.504986 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9591 22:20:26.511410 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9592 22:20:26.514845 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9593 22:20:26.521475 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9594 22:20:26.524972 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9595 22:20:26.527936 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9596 22:20:26.534860 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9597 22:20:26.538143 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9598 22:20:26.541550 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9599 22:20:26.548123 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9600 22:20:26.551340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9601 22:20:26.554464 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9602 22:20:26.561026 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9603 22:20:26.564579 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9604 22:20:26.567960 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9605 22:20:26.571179 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9606 22:20:26.577745 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9607 22:20:26.581251 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9608 22:20:26.584448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9609 22:20:26.591515 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9610 22:20:26.594974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9611 22:20:26.601053 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9612 22:20:26.604374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9613 22:20:26.607691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9614 22:20:26.614251 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9615 22:20:26.617871 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9616 22:20:26.624524 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9617 22:20:26.627713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9618 22:20:26.630736 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9619 22:20:26.637668 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9620 22:20:26.640955 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9621 22:20:26.647454 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9622 22:20:26.651024 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9623 22:20:26.654179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9624 22:20:26.660741 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9625 22:20:26.664019 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9626 22:20:26.667510 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9627 22:20:26.674051 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9628 22:20:26.677255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9629 22:20:26.683767 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9630 22:20:26.687074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9631 22:20:26.690690 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9632 22:20:26.697622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9633 22:20:26.700605 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9634 22:20:26.707272 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9635 22:20:26.710655 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9636 22:20:26.714185 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9637 22:20:26.720486 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9638 22:20:26.723798 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9639 22:20:26.730381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9640 22:20:26.734049 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9641 22:20:26.737052 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9642 22:20:26.743707 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9643 22:20:26.747096 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9644 22:20:26.753990 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9645 22:20:26.757462 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9646 22:20:26.760485 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9647 22:20:26.767032 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9648 22:20:26.770130 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9649 22:20:26.776465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9650 22:20:26.780134 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9651 22:20:26.783587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9652 22:20:26.789822 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9653 22:20:26.793049 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9654 22:20:26.799735 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9655 22:20:26.803150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9656 22:20:26.806264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9657 22:20:26.812984 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9658 22:20:26.816391 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9659 22:20:26.822639 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9660 22:20:26.825948 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9661 22:20:26.829659 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9662 22:20:26.835756 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9663 22:20:26.839085 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9664 22:20:26.845721 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9665 22:20:26.849122 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9666 22:20:26.852468 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9667 22:20:26.858966 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9668 22:20:26.862397 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9669 22:20:26.869197 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9670 22:20:26.872627 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9671 22:20:26.875568 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9672 22:20:26.882550 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9673 22:20:26.885591 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9674 22:20:26.892043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9675 22:20:26.895512 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9676 22:20:26.901918 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9677 22:20:26.905275 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9678 22:20:26.908729 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9679 22:20:26.915229 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9680 22:20:26.918674 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9681 22:20:26.925323 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9682 22:20:26.928672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9683 22:20:26.935228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9684 22:20:26.938679 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9685 22:20:26.941820 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9686 22:20:26.948124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9687 22:20:26.951749 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9688 22:20:26.958071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9689 22:20:26.961611 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9690 22:20:26.968155 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9691 22:20:26.971316 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9692 22:20:26.974365 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9693 22:20:26.981101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9694 22:20:26.984405 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9695 22:20:26.990877 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9696 22:20:26.994460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9697 22:20:26.997805 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9698 22:20:27.004475 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9699 22:20:27.007416 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9700 22:20:27.014170 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9701 22:20:27.017317 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9702 22:20:27.024252 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9703 22:20:27.027218 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9704 22:20:27.030531 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9705 22:20:27.037407 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9706 22:20:27.040716 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9707 22:20:27.047126 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9708 22:20:27.050432 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9709 22:20:27.057615 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9710 22:20:27.060110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9711 22:20:27.063517 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9712 22:20:27.066765 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9713 22:20:27.073531 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9714 22:20:27.076790 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9715 22:20:27.080112 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9716 22:20:27.086578 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9717 22:20:27.090150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9718 22:20:27.093118 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9719 22:20:27.099684 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9720 22:20:27.103065 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9721 22:20:27.106512 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9722 22:20:27.112878 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9723 22:20:27.116121 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9724 22:20:27.122747 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9725 22:20:27.126239 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9726 22:20:27.129500 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9727 22:20:27.136199 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9728 22:20:27.139494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9729 22:20:27.146032 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9730 22:20:27.149118 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9731 22:20:27.152605 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9732 22:20:27.159009 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9733 22:20:27.162386 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9734 22:20:27.165745 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9735 22:20:27.172139 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9736 22:20:27.175535 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9737 22:20:27.182161 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9738 22:20:27.185535 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9739 22:20:27.188785 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9740 22:20:27.195282 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9741 22:20:27.198612 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9742 22:20:27.202083 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9743 22:20:27.208534 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9744 22:20:27.211818 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9745 22:20:27.215260 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9746 22:20:27.221596 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9747 22:20:27.225367 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9748 22:20:27.231538 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9749 22:20:27.234963 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9750 22:20:27.238411 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9751 22:20:27.244831 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9752 22:20:27.248064 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9753 22:20:27.251333 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9754 22:20:27.254406 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9755 22:20:27.257758 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9756 22:20:27.264149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9757 22:20:27.267751 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9758 22:20:27.271038 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9759 22:20:27.277560 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9760 22:20:27.280748 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9761 22:20:27.284203 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9762 22:20:27.287598 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9763 22:20:27.294086 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9764 22:20:27.297469 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9765 22:20:27.303913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9766 22:20:27.307410 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9767 22:20:27.310490 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9768 22:20:27.317489 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9769 22:20:27.320335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9770 22:20:27.326902 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9771 22:20:27.330380 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9772 22:20:27.333398 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9773 22:20:27.340226 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9774 22:20:27.343738 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9775 22:20:27.350041 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9776 22:20:27.353326 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9777 22:20:27.360100 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9778 22:20:27.363332 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9779 22:20:27.366419 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9780 22:20:27.373535 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9781 22:20:27.376556 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9782 22:20:27.383276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9783 22:20:27.386685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9784 22:20:27.390198 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9785 22:20:27.396802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9786 22:20:27.399815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9787 22:20:27.406417 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9788 22:20:27.409843 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9789 22:20:27.413248 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9790 22:20:27.419810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9791 22:20:27.423104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9792 22:20:27.429594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9793 22:20:27.433240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9794 22:20:27.439340 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9795 22:20:27.442819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9796 22:20:27.446404 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9797 22:20:27.452620 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9798 22:20:27.456045 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9799 22:20:27.462524 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9800 22:20:27.465995 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9801 22:20:27.472348 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9802 22:20:27.475961 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9803 22:20:27.479100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9804 22:20:27.485824 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9805 22:20:27.488962 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9806 22:20:27.495555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9807 22:20:27.499095 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9808 22:20:27.502192 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9809 22:20:27.508798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9810 22:20:27.512155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9811 22:20:27.518552 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9812 22:20:27.521973 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9813 22:20:27.525493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9814 22:20:27.532009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9815 22:20:27.535307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9816 22:20:27.541955 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9817 22:20:27.544856 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9818 22:20:27.551443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9819 22:20:27.554768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9820 22:20:27.558090 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9821 22:20:27.564605 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9822 22:20:27.568022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9823 22:20:27.574859 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9824 22:20:27.578175 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9825 22:20:27.584393 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9826 22:20:27.587716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9827 22:20:27.591326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9828 22:20:27.597760 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9829 22:20:27.600849 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9830 22:20:27.607750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9831 22:20:27.610824 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9832 22:20:27.617596 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9833 22:20:27.620810 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9834 22:20:27.624285 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9835 22:20:27.630784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9836 22:20:27.633687 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9837 22:20:27.640339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9838 22:20:27.643758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9839 22:20:27.650450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9840 22:20:27.653704 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9841 22:20:27.660289 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9842 22:20:27.663538 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9843 22:20:27.666822 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9844 22:20:27.673713 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9845 22:20:27.676686 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9846 22:20:27.683542 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9847 22:20:27.686642 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9848 22:20:27.693133 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9849 22:20:27.696589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9850 22:20:27.699703 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9851 22:20:27.706367 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9852 22:20:27.709650 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9853 22:20:27.716286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9854 22:20:27.719694 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9855 22:20:27.726239 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9856 22:20:27.729443 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9857 22:20:27.736345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9858 22:20:27.739221 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9859 22:20:27.742651 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9860 22:20:27.749331 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9861 22:20:27.752598 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9862 22:20:27.759189 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9863 22:20:27.762485 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9864 22:20:27.769180 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9865 22:20:27.772299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9866 22:20:27.779214 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9867 22:20:27.782430 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9868 22:20:27.785724 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9869 22:20:27.792205 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9870 22:20:27.795727 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9871 22:20:27.802432 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9872 22:20:27.805436 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9873 22:20:27.812295 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9874 22:20:27.815450 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9875 22:20:27.818902 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9876 22:20:27.825457 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9877 22:20:27.828640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9878 22:20:27.835230 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9879 22:20:27.838780 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9880 22:20:27.845344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9881 22:20:27.848428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9882 22:20:27.855097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9883 22:20:27.858350 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9884 22:20:27.861570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9885 22:20:27.868000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9886 22:20:27.871241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9887 22:20:27.877968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9888 22:20:27.881412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9889 22:20:27.887960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9890 22:20:27.891574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9891 22:20:27.897650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9892 22:20:27.901207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9893 22:20:27.907567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9894 22:20:27.910732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9895 22:20:27.917635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9896 22:20:27.921097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9897 22:20:27.927346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9898 22:20:27.930699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9899 22:20:27.937113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9900 22:20:27.940280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9901 22:20:27.947191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9902 22:20:27.950767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9903 22:20:27.957236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9904 22:20:27.960256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9905 22:20:27.966827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9906 22:20:27.970160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9907 22:20:27.976362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9908 22:20:27.979883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9909 22:20:27.986523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9910 22:20:27.989658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9911 22:20:27.996378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9912 22:20:28.000144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9913 22:20:28.006381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9914 22:20:28.009445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9915 22:20:28.016127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9916 22:20:28.019573 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9917 22:20:28.023081 INFO: [APUAPC] vio 0
9918 22:20:28.026122 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9919 22:20:28.032666 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9920 22:20:28.035706 INFO: [APUAPC] D0_APC_0: 0x400510
9921 22:20:28.039160 INFO: [APUAPC] D0_APC_1: 0x0
9922 22:20:28.039231 INFO: [APUAPC] D0_APC_2: 0x1540
9923 22:20:28.042352 INFO: [APUAPC] D0_APC_3: 0x0
9924 22:20:28.045799 INFO: [APUAPC] D1_APC_0: 0xffffffff
9925 22:20:28.048947 INFO: [APUAPC] D1_APC_1: 0xffffffff
9926 22:20:28.052379 INFO: [APUAPC] D1_APC_2: 0x3fffff
9927 22:20:28.055941 INFO: [APUAPC] D1_APC_3: 0x0
9928 22:20:28.058969 INFO: [APUAPC] D2_APC_0: 0xffffffff
9929 22:20:28.062248 INFO: [APUAPC] D2_APC_1: 0xffffffff
9930 22:20:28.065733 INFO: [APUAPC] D2_APC_2: 0x3fffff
9931 22:20:28.068843 INFO: [APUAPC] D2_APC_3: 0x0
9932 22:20:28.072340 INFO: [APUAPC] D3_APC_0: 0xffffffff
9933 22:20:28.075526 INFO: [APUAPC] D3_APC_1: 0xffffffff
9934 22:20:28.078954 INFO: [APUAPC] D3_APC_2: 0x3fffff
9935 22:20:28.082350 INFO: [APUAPC] D3_APC_3: 0x0
9936 22:20:28.085270 INFO: [APUAPC] D4_APC_0: 0xffffffff
9937 22:20:28.088797 INFO: [APUAPC] D4_APC_1: 0xffffffff
9938 22:20:28.092023 INFO: [APUAPC] D4_APC_2: 0x3fffff
9939 22:20:28.095650 INFO: [APUAPC] D4_APC_3: 0x0
9940 22:20:28.099241 INFO: [APUAPC] D5_APC_0: 0xffffffff
9941 22:20:28.101834 INFO: [APUAPC] D5_APC_1: 0xffffffff
9942 22:20:28.105394 INFO: [APUAPC] D5_APC_2: 0x3fffff
9943 22:20:28.108683 INFO: [APUAPC] D5_APC_3: 0x0
9944 22:20:28.111650 INFO: [APUAPC] D6_APC_0: 0xffffffff
9945 22:20:28.115256 INFO: [APUAPC] D6_APC_1: 0xffffffff
9946 22:20:28.118443 INFO: [APUAPC] D6_APC_2: 0x3fffff
9947 22:20:28.121484 INFO: [APUAPC] D6_APC_3: 0x0
9948 22:20:28.125165 INFO: [APUAPC] D7_APC_0: 0xffffffff
9949 22:20:28.128301 INFO: [APUAPC] D7_APC_1: 0xffffffff
9950 22:20:28.131613 INFO: [APUAPC] D7_APC_2: 0x3fffff
9951 22:20:28.134988 INFO: [APUAPC] D7_APC_3: 0x0
9952 22:20:28.138449 INFO: [APUAPC] D8_APC_0: 0xffffffff
9953 22:20:28.141585 INFO: [APUAPC] D8_APC_1: 0xffffffff
9954 22:20:28.144834 INFO: [APUAPC] D8_APC_2: 0x3fffff
9955 22:20:28.148251 INFO: [APUAPC] D8_APC_3: 0x0
9956 22:20:28.151753 INFO: [APUAPC] D9_APC_0: 0xffffffff
9957 22:20:28.154874 INFO: [APUAPC] D9_APC_1: 0xffffffff
9958 22:20:28.157862 INFO: [APUAPC] D9_APC_2: 0x3fffff
9959 22:20:28.161118 INFO: [APUAPC] D9_APC_3: 0x0
9960 22:20:28.164605 INFO: [APUAPC] D10_APC_0: 0xffffffff
9961 22:20:28.168015 INFO: [APUAPC] D10_APC_1: 0xffffffff
9962 22:20:28.171390 INFO: [APUAPC] D10_APC_2: 0x3fffff
9963 22:20:28.174447 INFO: [APUAPC] D10_APC_3: 0x0
9964 22:20:28.177674 INFO: [APUAPC] D11_APC_0: 0xffffffff
9965 22:20:28.181055 INFO: [APUAPC] D11_APC_1: 0xffffffff
9966 22:20:28.184411 INFO: [APUAPC] D11_APC_2: 0x3fffff
9967 22:20:28.187498 INFO: [APUAPC] D11_APC_3: 0x0
9968 22:20:28.190846 INFO: [APUAPC] D12_APC_0: 0xffffffff
9969 22:20:28.194163 INFO: [APUAPC] D12_APC_1: 0xffffffff
9970 22:20:28.197754 INFO: [APUAPC] D12_APC_2: 0x3fffff
9971 22:20:28.201149 INFO: [APUAPC] D12_APC_3: 0x0
9972 22:20:28.204222 INFO: [APUAPC] D13_APC_0: 0xffffffff
9973 22:20:28.207708 INFO: [APUAPC] D13_APC_1: 0xffffffff
9974 22:20:28.210793 INFO: [APUAPC] D13_APC_2: 0x3fffff
9975 22:20:28.214061 INFO: [APUAPC] D13_APC_3: 0x0
9976 22:20:28.217245 INFO: [APUAPC] D14_APC_0: 0xffffffff
9977 22:20:28.220589 INFO: [APUAPC] D14_APC_1: 0xffffffff
9978 22:20:28.223941 INFO: [APUAPC] D14_APC_2: 0x3fffff
9979 22:20:28.227422 INFO: [APUAPC] D14_APC_3: 0x0
9980 22:20:28.230634 INFO: [APUAPC] D15_APC_0: 0xffffffff
9981 22:20:28.234205 INFO: [APUAPC] D15_APC_1: 0xffffffff
9982 22:20:28.237333 INFO: [APUAPC] D15_APC_2: 0x3fffff
9983 22:20:28.240610 INFO: [APUAPC] D15_APC_3: 0x0
9984 22:20:28.243971 INFO: [APUAPC] APC_CON: 0x4
9985 22:20:28.246967 INFO: [NOCDAPC] D0_APC_0: 0x0
9986 22:20:28.250573 INFO: [NOCDAPC] D0_APC_1: 0x0
9987 22:20:28.253857 INFO: [NOCDAPC] D1_APC_0: 0x0
9988 22:20:28.253940 INFO: [NOCDAPC] D1_APC_1: 0xfff
9989 22:20:28.256920 INFO: [NOCDAPC] D2_APC_0: 0x0
9990 22:20:28.260426 INFO: [NOCDAPC] D2_APC_1: 0xfff
9991 22:20:28.263781 INFO: [NOCDAPC] D3_APC_0: 0x0
9992 22:20:28.267321 INFO: [NOCDAPC] D3_APC_1: 0xfff
9993 22:20:28.270311 INFO: [NOCDAPC] D4_APC_0: 0x0
9994 22:20:28.274149 INFO: [NOCDAPC] D4_APC_1: 0xfff
9995 22:20:28.277102 INFO: [NOCDAPC] D5_APC_0: 0x0
9996 22:20:28.280457 INFO: [NOCDAPC] D5_APC_1: 0xfff
9997 22:20:28.283863 INFO: [NOCDAPC] D6_APC_0: 0x0
9998 22:20:28.287272 INFO: [NOCDAPC] D6_APC_1: 0xfff
9999 22:20:28.290256 INFO: [NOCDAPC] D7_APC_0: 0x0
10000 22:20:28.290339 INFO: [NOCDAPC] D7_APC_1: 0xfff
10001 22:20:28.293593 INFO: [NOCDAPC] D8_APC_0: 0x0
10002 22:20:28.297017 INFO: [NOCDAPC] D8_APC_1: 0xfff
10003 22:20:28.300115 INFO: [NOCDAPC] D9_APC_0: 0x0
10004 22:20:28.303220 INFO: [NOCDAPC] D9_APC_1: 0xfff
10005 22:20:28.306836 INFO: [NOCDAPC] D10_APC_0: 0x0
10006 22:20:28.309965 INFO: [NOCDAPC] D10_APC_1: 0xfff
10007 22:20:28.313395 INFO: [NOCDAPC] D11_APC_0: 0x0
10008 22:20:28.316556 INFO: [NOCDAPC] D11_APC_1: 0xfff
10009 22:20:28.319533 INFO: [NOCDAPC] D12_APC_0: 0x0
10010 22:20:28.322936 INFO: [NOCDAPC] D12_APC_1: 0xfff
10011 22:20:28.326644 INFO: [NOCDAPC] D13_APC_0: 0x0
10012 22:20:28.329820 INFO: [NOCDAPC] D13_APC_1: 0xfff
10013 22:20:28.333005 INFO: [NOCDAPC] D14_APC_0: 0x0
10014 22:20:28.336206 INFO: [NOCDAPC] D14_APC_1: 0xfff
10015 22:20:28.336289 INFO: [NOCDAPC] D15_APC_0: 0x0
10016 22:20:28.339574 INFO: [NOCDAPC] D15_APC_1: 0xfff
10017 22:20:28.342790 INFO: [NOCDAPC] APC_CON: 0x4
10018 22:20:28.346095 INFO: [APUAPC] set_apusys_apc done
10019 22:20:28.349308 INFO: [DEVAPC] devapc_init done
10020 22:20:28.356145 INFO: GICv3 without legacy support detected.
10021 22:20:28.359543 INFO: ARM GICv3 driver initialized in EL3
10022 22:20:28.362446 INFO: Maximum SPI INTID supported: 639
10023 22:20:28.365963 INFO: BL31: Initializing runtime services
10024 22:20:28.372340 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10025 22:20:28.375850 INFO: SPM: enable CPC mode
10026 22:20:28.379243 INFO: mcdi ready for mcusys-off-idle and system suspend
10027 22:20:28.386093 INFO: BL31: Preparing for EL3 exit to normal world
10028 22:20:28.389088 INFO: Entry point address = 0x80000000
10029 22:20:28.389170 INFO: SPSR = 0x8
10030 22:20:28.395709
10031 22:20:28.395791
10032 22:20:28.395856
10033 22:20:28.399010 Starting depthcharge on Spherion...
10034 22:20:28.399092
10035 22:20:28.399157 Wipe memory regions:
10036 22:20:28.399218
10037 22:20:28.399842 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10038 22:20:28.399943 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10039 22:20:28.400029 Setting prompt string to ['asurada:']
10040 22:20:28.400109 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10041 22:20:28.402489 [0x00000040000000, 0x00000054600000)
10042 22:20:28.524710
10043 22:20:28.524890 [0x00000054660000, 0x00000080000000)
10044 22:20:28.785576
10045 22:20:28.785724 [0x000000821a7280, 0x000000ffe64000)
10046 22:20:29.530540
10047 22:20:29.531092 [0x00000100000000, 0x00000240000000)
10048 22:20:31.420648
10049 22:20:31.423983 Initializing XHCI USB controller at 0x11200000.
10050 22:20:32.461568
10051 22:20:32.464774 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10052 22:20:32.464868
10053 22:20:32.464937
10054 22:20:32.465000
10055 22:20:32.465295 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10057 22:20:32.565684 asurada: tftpboot 192.168.201.1 10597287/tftp-deploy-i8g293z_/kernel/image.itb 10597287/tftp-deploy-i8g293z_/kernel/cmdline
10058 22:20:32.565859 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 22:20:32.565973 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10060 22:20:32.569715 tftpboot 192.168.201.1 10597287/tftp-deploy-i8g293z_/kernel/image.ittp-deploy-i8g293z_/kernel/cmdline
10061 22:20:32.569807
10062 22:20:32.569873 Waiting for link
10063 22:20:32.730621
10064 22:20:32.730752 R8152: Initializing
10065 22:20:32.730824
10066 22:20:32.733917 Version 9 (ocp_data = 6010)
10067 22:20:32.733992
10068 22:20:32.736854 R8152: Done initializing
10069 22:20:32.736928
10070 22:20:32.736987 Adding net device
10071 22:20:34.683035
10072 22:20:34.683184 done.
10073 22:20:34.683257
10074 22:20:34.683320 MAC: 00:e0:4c:72:2d:d6
10075 22:20:34.683379
10076 22:20:34.686438 Sending DHCP discover... done.
10077 22:20:34.686546
10078 22:20:34.694165 Waiting for reply... done.
10079 22:20:34.694257
10080 22:20:34.694324 Sending DHCP request... done.
10081 22:20:34.694386
10082 22:20:34.699831 Waiting for reply... done.
10083 22:20:34.699919
10084 22:20:34.699989 My ip is 192.168.201.21
10085 22:20:34.700052
10086 22:20:34.702654 The DHCP server ip is 192.168.201.1
10087 22:20:34.702731
10088 22:20:34.709409 TFTP server IP predefined by user: 192.168.201.1
10089 22:20:34.709486
10090 22:20:34.715844 Bootfile predefined by user: 10597287/tftp-deploy-i8g293z_/kernel/image.itb
10091 22:20:34.715925
10092 22:20:34.719078 Sending tftp read request... done.
10093 22:20:34.719159
10094 22:20:34.722328 Waiting for the transfer...
10095 22:20:34.722407
10096 22:20:35.071721 00000000 ################################################################
10097 22:20:35.071870
10098 22:20:35.417217 00080000 ################################################################
10099 22:20:35.417395
10100 22:20:35.768643 00100000 ################################################################
10101 22:20:35.768829
10102 22:20:36.119362 00180000 ################################################################
10103 22:20:36.119507
10104 22:20:36.470152 00200000 ################################################################
10105 22:20:36.470329
10106 22:20:36.825517 00280000 ################################################################
10107 22:20:36.825744
10108 22:20:37.184033 00300000 ################################################################
10109 22:20:37.184176
10110 22:20:37.528341 00380000 ################################################################
10111 22:20:37.528522
10112 22:20:37.878707 00400000 ################################################################
10113 22:20:37.878884
10114 22:20:38.229758 00480000 ################################################################
10115 22:20:38.229907
10116 22:20:38.574886 00500000 ################################################################
10117 22:20:38.575040
10118 22:20:38.919851 00580000 ################################################################
10119 22:20:38.920031
10120 22:20:39.271539 00600000 ################################################################
10121 22:20:39.271700
10122 22:20:39.625234 00680000 ################################################################
10123 22:20:39.625393
10124 22:20:39.964446 00700000 ################################################################
10125 22:20:39.964611
10126 22:20:40.323426 00780000 ################################################################
10127 22:20:40.323581
10128 22:20:40.682137 00800000 ################################################################
10129 22:20:40.682288
10130 22:20:41.029696 00880000 ################################################################
10131 22:20:41.029865
10132 22:20:41.370889 00900000 ################################################################
10133 22:20:41.371037
10134 22:20:41.720981 00980000 ################################################################
10135 22:20:41.721131
10136 22:20:42.058257 00a00000 ################################################################
10137 22:20:42.058407
10138 22:20:42.397321 00a80000 ################################################################
10139 22:20:42.397470
10140 22:20:42.735590 00b00000 ################################################################
10141 22:20:42.735743
10142 22:20:43.075573 00b80000 ################################################################
10143 22:20:43.075745
10144 22:20:43.422904 00c00000 ################################################################
10145 22:20:43.423055
10146 22:20:43.778084 00c80000 ################################################################
10147 22:20:43.778224
10148 22:20:44.140015 00d00000 ################################################################
10149 22:20:44.140165
10150 22:20:44.492654 00d80000 ################################################################
10151 22:20:44.492885
10152 22:20:44.841283 00e00000 ################################################################
10153 22:20:44.841438
10154 22:20:45.188812 00e80000 ################################################################
10155 22:20:45.189018
10156 22:20:45.544883 00f00000 ################################################################
10157 22:20:45.545034
10158 22:20:45.903012 00f80000 ################################################################
10159 22:20:45.903163
10160 22:20:46.246511 01000000 ################################################################
10161 22:20:46.246662
10162 22:20:46.581447 01080000 ################################################################
10163 22:20:46.581598
10164 22:20:46.917764 01100000 ################################################################
10165 22:20:46.917929
10166 22:20:47.265135 01180000 ################################################################
10167 22:20:47.265287
10168 22:20:47.623312 01200000 ################################################################
10169 22:20:47.623463
10170 22:20:47.977255 01280000 ################################################################
10171 22:20:47.977395
10172 22:20:48.320123 01300000 ################################################################
10173 22:20:48.320304
10174 22:20:48.668074 01380000 ################################################################
10175 22:20:48.668231
10176 22:20:49.016643 01400000 ################################################################
10177 22:20:49.016804
10178 22:20:49.373324 01480000 ################################################################
10179 22:20:49.373488
10180 22:20:49.721895 01500000 ################################################################
10181 22:20:49.722053
10182 22:20:50.060923 01580000 ################################################################
10183 22:20:50.061088
10184 22:20:50.406478 01600000 ################################################################
10185 22:20:50.406649
10186 22:20:50.742508 01680000 ################################################################
10187 22:20:50.742690
10188 22:20:51.091190 01700000 ################################################################
10189 22:20:51.091368
10190 22:20:51.437822 01780000 ################################################################
10191 22:20:51.437974
10192 22:20:51.773520 01800000 ################################################################
10193 22:20:51.773667
10194 22:20:52.110965 01880000 ################################################################
10195 22:20:52.111114
10196 22:20:52.447404 01900000 ################################################################
10197 22:20:52.447548
10198 22:20:52.782125 01980000 ################################################################
10199 22:20:52.782299
10200 22:20:53.110041 01a00000 ############################################################### done.
10201 22:20:53.110187
10202 22:20:53.113650 The bootfile was 27776074 bytes long.
10203 22:20:53.113757
10204 22:20:53.116625 Sending tftp read request... done.
10205 22:20:53.116723
10206 22:20:53.116839 Waiting for the transfer...
10207 22:20:53.116901
10208 22:20:53.119835 00000000 # done.
10209 22:20:53.119911
10210 22:20:53.126590 Command line loaded dynamically from TFTP file: 10597287/tftp-deploy-i8g293z_/kernel/cmdline
10211 22:20:53.126698
10212 22:20:53.146423 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10213 22:20:53.146542
10214 22:20:53.149886 Loading FIT.
10215 22:20:53.149977
10216 22:20:53.153030 Image ramdisk-1 has 17644812 bytes.
10217 22:20:53.153135
10218 22:20:53.153227 Image fdt-1 has 46924 bytes.
10219 22:20:53.153315
10220 22:20:53.156323 Image kernel-1 has 10082307 bytes.
10221 22:20:53.156450
10222 22:20:53.166311 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10223 22:20:53.166415
10224 22:20:53.182658 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10225 22:20:53.182765
10226 22:20:53.189669 Choosing best match conf-1 for compat google,spherion-rev2.
10227 22:20:53.193442
10228 22:20:53.197732 Connected to device vid:did:rid of 1ae0:0028:00
10229 22:20:53.204996
10230 22:20:53.208311 tpm_get_response: command 0x17b, return code 0x0
10231 22:20:53.208384
10232 22:20:53.214826 ec_init: CrosEC protocol v3 supported (256, 248)
10233 22:20:53.214903
10234 22:20:53.218122 tpm_cleanup: add release locality here.
10235 22:20:53.218196
10236 22:20:53.221802 Shutting down all USB controllers.
10237 22:20:53.221878
10238 22:20:53.224939 Removing current net device
10239 22:20:53.225020
10240 22:20:53.227954 Exiting depthcharge with code 4 at timestamp: 54088704
10241 22:20:53.231228
10242 22:20:53.234512 LZMA decompressing kernel-1 to 0x821a6718
10243 22:20:53.234615
10244 22:20:53.237976 LZMA decompressing kernel-1 to 0x40000000
10245 22:20:54.504258
10246 22:20:54.504437 jumping to kernel
10247 22:20:54.505160 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10248 22:20:54.505300 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10249 22:20:54.505406 Setting prompt string to ['Linux version [0-9]']
10250 22:20:54.505514 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10251 22:20:54.505611 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10252 22:20:54.585597
10253 22:20:54.589225 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10254 22:20:54.592484 start: 2.2.5.1 login-action (timeout 00:03:59) [common]
10255 22:20:54.592602 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10256 22:20:54.592715 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10257 22:20:54.592817 Using line separator: #'\n'#
10258 22:20:54.592883 No login prompt set.
10259 22:20:54.592950 Parsing kernel messages
10260 22:20:54.593007 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10261 22:20:54.593112 [login-action] Waiting for messages, (timeout 00:03:59)
10262 22:20:54.611782 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10263 22:20:54.615430 [ 0.000000] random: crng init done
10264 22:20:54.621948 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10265 22:20:54.625064 [ 0.000000] efi: UEFI not found.
10266 22:20:54.631766 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10267 22:20:54.638083 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10268 22:20:54.648092 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10269 22:20:54.658083 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10270 22:20:54.664723 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10271 22:20:54.671236 [ 0.000000] printk: bootconsole [mtk8250] enabled
10272 22:20:54.678407 [ 0.000000] NUMA: No NUMA configuration found
10273 22:20:54.684515 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10274 22:20:54.688056 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10275 22:20:54.691083 [ 0.000000] Zone ranges:
10276 22:20:54.698092 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10277 22:20:54.701086 [ 0.000000] DMA32 empty
10278 22:20:54.707860 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10279 22:20:54.711244 [ 0.000000] Movable zone start for each node
10280 22:20:54.714306 [ 0.000000] Early memory node ranges
10281 22:20:54.721158 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10282 22:20:54.727678 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10283 22:20:54.734252 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10284 22:20:54.740561 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10285 22:20:54.747374 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10286 22:20:54.754090 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10287 22:20:54.809932 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10288 22:20:54.816444 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10289 22:20:54.823459 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10290 22:20:54.826386 [ 0.000000] psci: probing for conduit method from DT.
10291 22:20:54.833069 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10292 22:20:54.836277 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10293 22:20:54.843041 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10294 22:20:54.846169 [ 0.000000] psci: SMC Calling Convention v1.2
10295 22:20:54.852796 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10296 22:20:54.855877 [ 0.000000] Detected VIPT I-cache on CPU0
10297 22:20:54.862532 [ 0.000000] CPU features: detected: GIC system register CPU interface
10298 22:20:54.869151 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10299 22:20:54.875797 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10300 22:20:54.882428 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10301 22:20:54.889305 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10302 22:20:54.899359 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10303 22:20:54.902298 [ 0.000000] alternatives: applying boot alternatives
10304 22:20:54.909053 [ 0.000000] Fallback order for Node 0: 0
10305 22:20:54.915448 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10306 22:20:54.918990 [ 0.000000] Policy zone: Normal
10307 22:20:54.938589 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10308 22:20:54.948616 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10309 22:20:54.959432 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10310 22:20:54.969017 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10311 22:20:54.975869 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10312 22:20:54.979035 <6>[ 0.000000] software IO TLB: area num 8.
10313 22:20:55.035588 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10314 22:20:55.184951 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10315 22:20:55.191531 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10316 22:20:55.197932 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10317 22:20:55.201606 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10318 22:20:55.207758 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10319 22:20:55.214490 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10320 22:20:55.220710 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10321 22:20:55.227616 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10322 22:20:55.234322 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10323 22:20:55.240900 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10324 22:20:55.247531 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10325 22:20:55.250816 <6>[ 0.000000] GICv3: 608 SPIs implemented
10326 22:20:55.254340 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10327 22:20:55.260642 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10328 22:20:55.264019 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10329 22:20:55.270566 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10330 22:20:55.284185 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10331 22:20:55.296966 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10332 22:20:55.303262 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10333 22:20:55.311761 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10334 22:20:55.324801 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10335 22:20:55.331179 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10336 22:20:55.338297 <6>[ 0.009181] Console: colour dummy device 80x25
10337 22:20:55.348168 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10338 22:20:55.354697 <6>[ 0.024380] pid_max: default: 32768 minimum: 301
10339 22:20:55.358086 <6>[ 0.029247] LSM: Security Framework initializing
10340 22:20:55.364769 <6>[ 0.034183] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10341 22:20:55.374794 <6>[ 0.041997] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10342 22:20:55.381089 <6>[ 0.051431] cblist_init_generic: Setting adjustable number of callback queues.
10343 22:20:55.387884 <6>[ 0.058886] cblist_init_generic: Setting shift to 3 and lim to 1.
10344 22:20:55.394290 <6>[ 0.065224] cblist_init_generic: Setting shift to 3 and lim to 1.
10345 22:20:55.400964 <6>[ 0.071672] rcu: Hierarchical SRCU implementation.
10346 22:20:55.407361 <6>[ 0.076685] rcu: Max phase no-delay instances is 1000.
10347 22:20:55.410746 <6>[ 0.083704] EFI services will not be available.
10348 22:20:55.417358 <6>[ 0.088705] smp: Bringing up secondary CPUs ...
10349 22:20:55.425298 <6>[ 0.093761] Detected VIPT I-cache on CPU1
10350 22:20:55.431646 <6>[ 0.093834] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10351 22:20:55.438007 <6>[ 0.093865] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10352 22:20:55.441371 <6>[ 0.094206] Detected VIPT I-cache on CPU2
10353 22:20:55.451577 <6>[ 0.094260] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10354 22:20:55.457772 <6>[ 0.094277] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10355 22:20:55.461147 <6>[ 0.094536] Detected VIPT I-cache on CPU3
10356 22:20:55.468081 <6>[ 0.094583] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10357 22:20:55.474279 <6>[ 0.094597] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10358 22:20:55.477554 <6>[ 0.094903] CPU features: detected: Spectre-v4
10359 22:20:55.484217 <6>[ 0.094910] CPU features: detected: Spectre-BHB
10360 22:20:55.487573 <6>[ 0.094916] Detected PIPT I-cache on CPU4
10361 22:20:55.494224 <6>[ 0.094974] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10362 22:20:55.500708 <6>[ 0.094990] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10363 22:20:55.507543 <6>[ 0.095283] Detected PIPT I-cache on CPU5
10364 22:20:55.514421 <6>[ 0.095346] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10365 22:20:55.520610 <6>[ 0.095363] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10366 22:20:55.524248 <6>[ 0.095647] Detected PIPT I-cache on CPU6
10367 22:20:55.530880 <6>[ 0.095711] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10368 22:20:55.537704 <6>[ 0.095727] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10369 22:20:55.543858 <6>[ 0.096017] Detected PIPT I-cache on CPU7
10370 22:20:55.550681 <6>[ 0.096074] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10371 22:20:55.557377 <6>[ 0.096090] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10372 22:20:55.560512 <6>[ 0.096136] smp: Brought up 1 node, 8 CPUs
10373 22:20:55.566956 <6>[ 0.237397] SMP: Total of 8 processors activated.
10374 22:20:55.570499 <6>[ 0.242349] CPU features: detected: 32-bit EL0 Support
10375 22:20:55.580568 <6>[ 0.247712] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10376 22:20:55.586740 <6>[ 0.256513] CPU features: detected: Common not Private translations
10377 22:20:55.593508 <6>[ 0.262989] CPU features: detected: CRC32 instructions
10378 22:20:55.597021 <6>[ 0.268340] CPU features: detected: RCpc load-acquire (LDAPR)
10379 22:20:55.603338 <6>[ 0.274299] CPU features: detected: LSE atomic instructions
10380 22:20:55.610281 <6>[ 0.280080] CPU features: detected: Privileged Access Never
10381 22:20:55.616730 <6>[ 0.285860] CPU features: detected: RAS Extension Support
10382 22:20:55.623554 <6>[ 0.291469] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10383 22:20:55.626681 <6>[ 0.298689] CPU: All CPU(s) started at EL2
10384 22:20:55.633296 <6>[ 0.303005] alternatives: applying system-wide alternatives
10385 22:20:55.642329 <6>[ 0.313716] devtmpfs: initialized
10386 22:20:55.654829 <6>[ 0.322631] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10387 22:20:55.664993 <6>[ 0.332594] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10388 22:20:55.671700 <6>[ 0.340824] pinctrl core: initialized pinctrl subsystem
10389 22:20:55.674550 <6>[ 0.347428] DMI not present or invalid.
10390 22:20:55.681472 <6>[ 0.351832] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10391 22:20:55.691325 <6>[ 0.358736] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10392 22:20:55.697584 <6>[ 0.366321] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10393 22:20:55.707717 <6>[ 0.374547] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10394 22:20:55.710848 <6>[ 0.382790] audit: initializing netlink subsys (disabled)
10395 22:20:55.720752 <5>[ 0.388485] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10396 22:20:55.727479 <6>[ 0.389185] thermal_sys: Registered thermal governor 'step_wise'
10397 22:20:55.733913 <6>[ 0.396448] thermal_sys: Registered thermal governor 'power_allocator'
10398 22:20:55.737542 <6>[ 0.402704] cpuidle: using governor menu
10399 22:20:55.743943 <6>[ 0.413662] NET: Registered PF_QIPCRTR protocol family
10400 22:20:55.750554 <6>[ 0.419147] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10401 22:20:55.757344 <6>[ 0.426247] ASID allocator initialised with 32768 entries
10402 22:20:55.760465 <6>[ 0.432807] Serial: AMBA PL011 UART driver
10403 22:20:55.770252 <4>[ 0.441426] Trying to register duplicate clock ID: 134
10404 22:20:55.824155 <6>[ 0.498560] KASLR enabled
10405 22:20:55.838442 <6>[ 0.506243] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10406 22:20:55.845204 <6>[ 0.513256] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10407 22:20:55.851462 <6>[ 0.519744] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10408 22:20:55.858189 <6>[ 0.526748] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10409 22:20:55.864903 <6>[ 0.533233] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10410 22:20:55.871338 <6>[ 0.540238] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10411 22:20:55.877915 <6>[ 0.546725] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10412 22:20:55.884906 <6>[ 0.553730] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10413 22:20:55.887779 <6>[ 0.561209] ACPI: Interpreter disabled.
10414 22:20:55.896549 <6>[ 0.567619] iommu: Default domain type: Translated
10415 22:20:55.903253 <6>[ 0.572731] iommu: DMA domain TLB invalidation policy: strict mode
10416 22:20:55.906621 <5>[ 0.579400] SCSI subsystem initialized
10417 22:20:55.913548 <6>[ 0.583634] usbcore: registered new interface driver usbfs
10418 22:20:55.919592 <6>[ 0.589362] usbcore: registered new interface driver hub
10419 22:20:55.923051 <6>[ 0.594913] usbcore: registered new device driver usb
10420 22:20:55.930046 <6>[ 0.601011] pps_core: LinuxPPS API ver. 1 registered
10421 22:20:55.940075 <6>[ 0.606205] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10422 22:20:55.943289 <6>[ 0.615545] PTP clock support registered
10423 22:20:55.946318 <6>[ 0.619783] EDAC MC: Ver: 3.0.0
10424 22:20:55.954013 <6>[ 0.624954] FPGA manager framework
10425 22:20:55.960127 <6>[ 0.628630] Advanced Linux Sound Architecture Driver Initialized.
10426 22:20:55.963565 <6>[ 0.635394] vgaarb: loaded
10427 22:20:55.970162 <6>[ 0.638559] clocksource: Switched to clocksource arch_sys_counter
10428 22:20:55.973694 <5>[ 0.645006] VFS: Disk quotas dquot_6.6.0
10429 22:20:55.980377 <6>[ 0.649187] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10430 22:20:55.983563 <6>[ 0.656372] pnp: PnP ACPI: disabled
10431 22:20:55.991883 <6>[ 0.663030] NET: Registered PF_INET protocol family
10432 22:20:56.001496 <6>[ 0.668613] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10433 22:20:56.012838 <6>[ 0.680918] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10434 22:20:56.022903 <6>[ 0.689732] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10435 22:20:56.029845 <6>[ 0.697701] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10436 22:20:56.039434 <6>[ 0.706402] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10437 22:20:56.046087 <6>[ 0.716129] TCP: Hash tables configured (established 65536 bind 65536)
10438 22:20:56.052613 <6>[ 0.722993] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10439 22:20:56.062462 <6>[ 0.730190] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10440 22:20:56.069223 <6>[ 0.737890] NET: Registered PF_UNIX/PF_LOCAL protocol family
10441 22:20:56.072283 <6>[ 0.744056] RPC: Registered named UNIX socket transport module.
10442 22:20:56.079069 <6>[ 0.750209] RPC: Registered udp transport module.
10443 22:20:56.082358 <6>[ 0.755140] RPC: Registered tcp transport module.
10444 22:20:56.089044 <6>[ 0.760073] RPC: Registered tcp NFSv4.1 backchannel transport module.
10445 22:20:56.095320 <6>[ 0.766739] PCI: CLS 0 bytes, default 64
10446 22:20:56.098921 <6>[ 0.771123] Unpacking initramfs...
10447 22:20:56.108860 <6>[ 0.774939] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10448 22:20:56.115260 <6>[ 0.783549] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10449 22:20:56.121895 <6>[ 0.792372] kvm [1]: IPA Size Limit: 40 bits
10450 22:20:56.125398 <6>[ 0.796897] kvm [1]: GICv3: no GICV resource entry
10451 22:20:56.131523 <6>[ 0.801917] kvm [1]: disabling GICv2 emulation
10452 22:20:56.135145 <6>[ 0.806601] kvm [1]: GIC system register CPU interface enabled
10453 22:20:56.141404 <6>[ 0.812765] kvm [1]: vgic interrupt IRQ18
10454 22:20:56.145069 <6>[ 0.817122] kvm [1]: VHE mode initialized successfully
10455 22:20:56.152795 <5>[ 0.823634] Initialise system trusted keyrings
10456 22:20:56.158852 <6>[ 0.828436] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10457 22:20:56.167251 <6>[ 0.838690] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10458 22:20:56.174538 <5>[ 0.845058] NFS: Registering the id_resolver key type
10459 22:20:56.177483 <5>[ 0.850349] Key type id_resolver registered
10460 22:20:56.184130 <5>[ 0.854763] Key type id_legacy registered
10461 22:20:56.190364 <6>[ 0.859040] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10462 22:20:56.197048 <6>[ 0.865961] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10463 22:20:56.203679 <6>[ 0.873677] 9p: Installing v9fs 9p2000 file system support
10464 22:20:56.239825 <5>[ 0.911205] Key type asymmetric registered
10465 22:20:56.243278 <5>[ 0.915535] Asymmetric key parser 'x509' registered
10466 22:20:56.253288 <6>[ 0.920672] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10467 22:20:56.256348 <6>[ 0.928286] io scheduler mq-deadline registered
10468 22:20:56.259623 <6>[ 0.933048] io scheduler kyber registered
10469 22:20:56.278540 <6>[ 0.949885] EINJ: ACPI disabled.
10470 22:20:56.311020 <4>[ 0.975613] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10471 22:20:56.320756 <4>[ 0.986264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10472 22:20:56.336166 <6>[ 1.007330] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10473 22:20:56.343976 <6>[ 1.015405] printk: console [ttyS0] disabled
10474 22:20:56.371826 <6>[ 1.040052] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10475 22:20:56.378440 <6>[ 1.049529] printk: console [ttyS0] enabled
10476 22:20:56.381941 <6>[ 1.049529] printk: console [ttyS0] enabled
10477 22:20:56.388994 <6>[ 1.058424] printk: bootconsole [mtk8250] disabled
10478 22:20:56.391980 <6>[ 1.058424] printk: bootconsole [mtk8250] disabled
10479 22:20:56.398301 <6>[ 1.069650] SuperH (H)SCI(F) driver initialized
10480 22:20:56.401553 <6>[ 1.074936] msm_serial: driver initialized
10481 22:20:56.416371 <6>[ 1.083888] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10482 22:20:56.425809 <6>[ 1.092433] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10483 22:20:56.432628 <6>[ 1.100974] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10484 22:20:56.442567 <6>[ 1.109602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10485 22:20:56.452238 <6>[ 1.118309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10486 22:20:56.459100 <6>[ 1.127029] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10487 22:20:56.468613 <6>[ 1.135570] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10488 22:20:56.475311 <6>[ 1.144369] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10489 22:20:56.485159 <6>[ 1.152911] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10490 22:20:56.497018 <6>[ 1.168338] loop: module loaded
10491 22:20:56.503467 <6>[ 1.174302] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10492 22:20:56.526486 <4>[ 1.197786] mtk-pmic-keys: Failed to locate of_node [id: -1]
10493 22:20:56.533064 <6>[ 1.204557] megasas: 07.719.03.00-rc1
10494 22:20:56.542731 <6>[ 1.214188] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10495 22:20:56.550786 <6>[ 1.221941] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10496 22:20:56.566730 <6>[ 1.237893] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10497 22:20:56.626656 <6>[ 1.291186] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10498 22:20:56.827448 <6>[ 1.498893] Freeing initrd memory: 17224K
10499 22:20:56.838167 <6>[ 1.509272] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10500 22:20:56.849553 <6>[ 1.520441] tun: Universal TUN/TAP device driver, 1.6
10501 22:20:56.852533 <6>[ 1.526507] thunder_xcv, ver 1.0
10502 22:20:56.855794 <6>[ 1.530011] thunder_bgx, ver 1.0
10503 22:20:56.858869 <6>[ 1.533508] nicpf, ver 1.0
10504 22:20:56.869854 <6>[ 1.537530] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10505 22:20:56.873215 <6>[ 1.545005] hns3: Copyright (c) 2017 Huawei Corporation.
10506 22:20:56.879528 <6>[ 1.550595] hclge is initializing
10507 22:20:56.882820 <6>[ 1.554165] e1000: Intel(R) PRO/1000 Network Driver
10508 22:20:56.889371 <6>[ 1.559295] e1000: Copyright (c) 1999-2006 Intel Corporation.
10509 22:20:56.893100 <6>[ 1.565308] e1000e: Intel(R) PRO/1000 Network Driver
10510 22:20:56.899439 <6>[ 1.570524] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10511 22:20:56.906099 <6>[ 1.576711] igb: Intel(R) Gigabit Ethernet Network Driver
10512 22:20:56.912696 <6>[ 1.582361] igb: Copyright (c) 2007-2014 Intel Corporation.
10513 22:20:56.919612 <6>[ 1.588198] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10514 22:20:56.925995 <6>[ 1.594716] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10515 22:20:56.929296 <6>[ 1.601175] sky2: driver version 1.30
10516 22:20:56.935695 <6>[ 1.606161] VFIO - User Level meta-driver version: 0.3
10517 22:20:56.942728 <6>[ 1.614347] usbcore: registered new interface driver usb-storage
10518 22:20:56.949632 <6>[ 1.620796] usbcore: registered new device driver onboard-usb-hub
10519 22:20:56.958537 <6>[ 1.629917] mt6397-rtc mt6359-rtc: registered as rtc0
10520 22:20:56.968384 <6>[ 1.635385] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:20:54 UTC (1686003654)
10521 22:20:56.971805 <6>[ 1.644942] i2c_dev: i2c /dev entries driver
10522 22:20:56.988664 <6>[ 1.656591] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10523 22:20:56.995450 <6>[ 1.666822] sdhci: Secure Digital Host Controller Interface driver
10524 22:20:57.002223 <6>[ 1.673261] sdhci: Copyright(c) Pierre Ossman
10525 22:20:57.008773 <6>[ 1.678658] Synopsys Designware Multimedia Card Interface Driver
10526 22:20:57.012246 <6>[ 1.685303] mmc0: CQHCI version 5.10
10527 22:20:57.018758 <6>[ 1.685826] sdhci-pltfm: SDHCI platform and OF driver helper
10528 22:20:57.025996 <6>[ 1.697251] ledtrig-cpu: registered to indicate activity on CPUs
10529 22:20:57.036640 <6>[ 1.704544] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10530 22:20:57.043231 <6>[ 1.711946] usbcore: registered new interface driver usbhid
10531 22:20:57.046379 <6>[ 1.717777] usbhid: USB HID core driver
10532 22:20:57.053070 <6>[ 1.722009] spi_master spi0: will run message pump with realtime priority
10533 22:20:57.099511 <6>[ 1.764054] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10534 22:20:57.114555 <6>[ 1.779164] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10535 22:20:57.121796 <6>[ 1.792726] mmc0: Command Queue Engine enabled
10536 22:20:57.128576 <6>[ 1.797512] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10537 22:20:57.135128 <6>[ 1.804646] cros-ec-spi spi0.0: Chrome EC device registered
10538 22:20:57.138521 <6>[ 1.804879] mmcblk0: mmc0:0001 DA4128 116 GiB
10539 22:20:57.151061 <6>[ 1.822150] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10540 22:20:57.158438 <6>[ 1.829721] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10541 22:20:57.165058 <6>[ 1.835673] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10542 22:20:57.171554 <6>[ 1.841718] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10543 22:20:57.188483 <6>[ 1.856610] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10544 22:20:57.196706 <6>[ 1.868086] NET: Registered PF_PACKET protocol family
10545 22:20:57.203577 <6>[ 1.873572] 9pnet: Installing 9P2000 support
10546 22:20:57.206552 <5>[ 1.878158] Key type dns_resolver registered
10547 22:20:57.210063 <6>[ 1.883377] registered taskstats version 1
10548 22:20:57.216710 <5>[ 1.887811] Loading compiled-in X.509 certificates
10549 22:20:57.251977 <4>[ 1.916288] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 22:20:57.262161 <4>[ 1.926964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 22:20:57.271843 <3>[ 1.939737] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10552 22:20:57.283948 <6>[ 1.955231] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10553 22:20:57.290618 <6>[ 1.961992] xhci-mtk 11200000.usb: xHCI Host Controller
10554 22:20:57.297380 <6>[ 1.967498] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10555 22:20:57.307515 <6>[ 1.975352] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10556 22:20:57.313936 <6>[ 1.984791] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10557 22:20:57.320756 <6>[ 1.990984] xhci-mtk 11200000.usb: xHCI Host Controller
10558 22:20:57.327244 <6>[ 1.996477] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10559 22:20:57.333739 <6>[ 2.004146] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10560 22:20:57.340709 <6>[ 2.012046] hub 1-0:1.0: USB hub found
10561 22:20:57.344386 <6>[ 2.016083] hub 1-0:1.0: 1 port detected
10562 22:20:57.353917 <6>[ 2.020435] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10563 22:20:57.357336 <6>[ 2.029277] hub 2-0:1.0: USB hub found
10564 22:20:57.360675 <6>[ 2.033329] hub 2-0:1.0: 1 port detected
10565 22:20:57.368871 <6>[ 2.040379] mtk-msdc 11f70000.mmc: Got CD GPIO
10566 22:20:57.387093 <6>[ 2.055133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10567 22:20:57.393906 <6>[ 2.063162] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10568 22:20:57.403517 <4>[ 2.071133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10569 22:20:57.413644 <6>[ 2.080792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10570 22:20:57.420172 <6>[ 2.088873] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10571 22:20:57.430121 <6>[ 2.096903] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10572 22:20:57.436897 <6>[ 2.104823] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10573 22:20:57.443131 <6>[ 2.112645] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10574 22:20:57.453296 <6>[ 2.120468] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10575 22:20:57.463317 <6>[ 2.131155] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10576 22:20:57.473331 <6>[ 2.139529] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10577 22:20:57.479758 <6>[ 2.147873] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10578 22:20:57.489502 <6>[ 2.156216] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10579 22:20:57.496587 <6>[ 2.164563] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10580 22:20:57.506189 <6>[ 2.172906] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10581 22:20:57.512839 <6>[ 2.181250] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10582 22:20:57.523117 <6>[ 2.189593] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10583 22:20:57.529818 <6>[ 2.197936] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10584 22:20:57.539330 <6>[ 2.206279] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10585 22:20:57.546320 <6>[ 2.214624] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10586 22:20:57.556089 <6>[ 2.222968] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10587 22:20:57.562773 <6>[ 2.231315] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10588 22:20:57.572457 <6>[ 2.239660] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10589 22:20:57.579312 <6>[ 2.248018] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10590 22:20:57.585911 <6>[ 2.256932] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10591 22:20:57.593062 <6>[ 2.264356] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10592 22:20:57.600360 <6>[ 2.271373] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10593 22:20:57.607145 <6>[ 2.278457] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10594 22:20:57.617598 <6>[ 2.285725] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10595 22:20:57.624668 <6>[ 2.292632] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10596 22:20:57.634439 <6>[ 2.301772] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10597 22:20:57.644306 <6>[ 2.310898] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10598 22:20:57.654062 <6>[ 2.320203] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10599 22:20:57.664141 <6>[ 2.329678] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10600 22:20:57.670831 <6>[ 2.339152] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10601 22:20:57.680642 <6>[ 2.348279] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10602 22:20:57.690596 <6>[ 2.357753] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10603 22:20:57.700239 <6>[ 2.366879] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10604 22:20:57.710129 <6>[ 2.376185] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10605 22:20:57.720147 <6>[ 2.386351] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10606 22:20:57.730112 <6>[ 2.398290] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10607 22:20:57.736863 <6>[ 2.408223] Trying to probe devices needed for running init ...
10608 22:20:57.754937 <6>[ 2.422962] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10609 22:20:57.781733 <6>[ 2.452900] hub 2-1:1.0: USB hub found
10610 22:20:57.785102 <6>[ 2.457270] hub 2-1:1.0: 3 ports detected
10611 22:20:57.906422 <6>[ 2.574693] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10612 22:20:58.060810 <6>[ 2.732222] hub 1-1:1.0: USB hub found
10613 22:20:58.064360 <6>[ 2.736693] hub 1-1:1.0: 4 ports detected
10614 22:20:58.139341 <6>[ 2.807073] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10615 22:20:58.386578 <6>[ 3.054830] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10616 22:20:58.519742 <6>[ 3.191114] hub 1-1.4:1.0: USB hub found
10617 22:20:58.522819 <6>[ 3.195776] hub 1-1.4:1.0: 2 ports detected
10618 22:20:58.822382 <6>[ 3.490830] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10619 22:20:59.014449 <6>[ 3.682755] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10620 22:21:10.023795 <6>[ 14.699379] ALSA device list:
10621 22:21:10.030311 <6>[ 14.702636] No soundcards found.
10622 22:21:10.042813 <6>[ 14.714999] Freeing unused kernel memory: 8384K
10623 22:21:10.046427 <6>[ 14.719931] Run /init as init process
10624 22:21:10.056802 Loading, please wait...
10625 22:21:10.076561 Starting version 247.3-7+deb11u2
10626 22:21:10.390276 <6>[ 15.059551] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10627 22:21:10.400290 <6>[ 15.072439] remoteproc remoteproc0: scp is available
10628 22:21:10.410077 <3>[ 15.073343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 22:21:10.420071 <4>[ 15.078127] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10630 22:21:10.426535 <3>[ 15.088917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 22:21:10.433260 <6>[ 15.098915] remoteproc remoteproc0: powering up scp
10632 22:21:10.440270 <3>[ 15.103898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 22:21:10.449396 <4>[ 15.109006] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10634 22:21:10.456495 <6>[ 15.109790] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10635 22:21:10.466140 <6>[ 15.109819] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10636 22:21:10.476424 <6>[ 15.109830] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10637 22:21:10.482875 <3>[ 15.117320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10638 22:21:10.489461 <3>[ 15.126912] remoteproc remoteproc0: request_firmware failed: -2
10639 22:21:10.492637 <6>[ 15.127507] mc: Linux media interface: v0.10
10640 22:21:10.502856 <3>[ 15.134507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10641 22:21:10.505847 <6>[ 15.164141] usbcore: registered new interface driver r8152
10642 22:21:10.515740 <3>[ 15.166246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10643 22:21:10.522373 <6>[ 15.173393] videodev: Linux video capture interface: v2.00
10644 22:21:10.525680 <6>[ 15.175609] Bluetooth: Core ver 2.22
10645 22:21:10.532363 <3>[ 15.178797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10646 22:21:10.542367 <3>[ 15.178806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10647 22:21:10.545478 <6>[ 15.179794] NET: Registered PF_BLUETOOTH protocol family
10648 22:21:10.555919 <3>[ 15.199133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10649 22:21:10.562042 <6>[ 15.202221] Bluetooth: HCI device and connection manager initialized
10650 22:21:10.568927 <4>[ 15.206116] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10651 22:21:10.575267 <6>[ 15.207377] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10652 22:21:10.585026 <4>[ 15.207434] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10653 22:21:10.591379 <3>[ 15.210409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 22:21:10.595321 <6>[ 15.218409] Bluetooth: HCI socket layer initialized
10655 22:21:10.602128 <6>[ 15.218417] Bluetooth: L2CAP socket layer initialized
10656 22:21:10.608969 <3>[ 15.224171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10657 22:21:10.618862 <6>[ 15.228186] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10658 22:21:10.622074 <6>[ 15.228196] pci_bus 0000:00: root bus resource [bus 00-ff]
10659 22:21:10.628993 <6>[ 15.228203] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10660 22:21:10.639221 <6>[ 15.228210] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10661 22:21:10.645860 <6>[ 15.228255] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10662 22:21:10.652153 <6>[ 15.228274] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10663 22:21:10.659034 <6>[ 15.228356] pci 0000:00:00.0: supports D1 D2
10664 22:21:10.665615 <6>[ 15.228361] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10665 22:21:10.669044 <6>[ 15.232165] Bluetooth: SCO socket layer initialized
10666 22:21:10.679156 <3>[ 15.238680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 22:21:10.685582 <3>[ 15.245289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 22:21:10.695479 <6>[ 15.251337] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10669 22:21:10.702344 <3>[ 15.253736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 22:21:10.712282 <4>[ 15.256566] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10671 22:21:10.715334 <4>[ 15.256566] Fallback method does not support PEC.
10672 22:21:10.721721 <6>[ 15.261173] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10673 22:21:10.731407 <3>[ 15.269056] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 22:21:10.738170 <3>[ 15.269066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 22:21:10.748076 <3>[ 15.269074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 22:21:10.754767 <3>[ 15.269128] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 22:21:10.764858 <3>[ 15.276078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10678 22:21:10.771750 <6>[ 15.279802] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10679 22:21:10.781293 <6>[ 15.295490] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10680 22:21:10.788115 <6>[ 15.300500] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10681 22:21:10.797691 <6>[ 15.307929] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10682 22:21:10.804656 <3>[ 15.310813] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10683 22:21:10.814702 <3>[ 15.313212] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10684 22:21:10.820914 <6>[ 15.317340] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10685 22:21:10.827534 <6>[ 15.317531] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10686 22:21:10.830725 <6>[ 15.317663] pci 0000:01:00.0: supports D1 D2
10687 22:21:10.837154 <6>[ 15.317667] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10688 22:21:10.847032 <6>[ 15.330739] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10689 22:21:10.853740 <4>[ 15.354233] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10690 22:21:10.863908 <6>[ 15.355697] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10691 22:21:10.870447 <4>[ 15.363772] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10692 22:21:10.880586 <6>[ 15.372020] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10693 22:21:10.883630 <6>[ 15.398663] r8152 2-1.3:1.0 eth0: v1.12.13
10694 22:21:10.890209 <6>[ 15.399998] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10695 22:21:10.896924 <3>[ 15.414804] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10696 22:21:10.906886 <6>[ 15.416158] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10697 22:21:10.913786 <3>[ 15.522839] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10698 22:21:10.920203 <6>[ 15.523175] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10699 22:21:10.926629 <3>[ 15.532524] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10700 22:21:10.933719 <6>[ 15.540288] pci 0000:00:00.0: PCI bridge to [bus 01]
10701 22:21:10.943229 <6>[ 15.548459] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10702 22:21:10.949812 <6>[ 15.556355] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10703 22:21:10.956802 <6>[ 15.556537] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10704 22:21:10.962820 <6>[ 15.583695] usbcore: registered new interface driver cdc_ether
10705 22:21:10.969519 <6>[ 15.590973] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10706 22:21:10.973136 <6>[ 15.605086] usbcore: registered new interface driver r8153_ecm
10707 22:21:10.980040 <6>[ 15.605875] usbcore: registered new interface driver btusb
10708 22:21:10.989483 <4>[ 15.606351] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10709 22:21:10.996601 <3>[ 15.606360] Bluetooth: hci0: Failed to load firmware file (-2)
10710 22:21:11.002664 <3>[ 15.606363] Bluetooth: hci0: Failed to set up firmware (-2)
10711 22:21:11.012823 <4>[ 15.606368] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10712 22:21:11.019251 <6>[ 15.609934] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10713 22:21:11.026012 <6>[ 15.610303] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10714 22:21:11.039125 <6>[ 15.611605] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10715 22:21:11.045644 <6>[ 15.611782] usbcore: registered new interface driver uvcvideo
10716 22:21:11.048577 <6>[ 15.627424] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10717 22:21:11.055267 <6>[ 15.627945] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10718 22:21:11.095477 <5>[ 15.764578] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10719 22:21:11.113970 <5>[ 15.783066] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10720 22:21:11.120871 <4>[ 15.789950] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10721 22:21:11.127143 <6>[ 15.798833] cfg80211: failed to load regulatory.db
10722 22:21:11.172151 <6>[ 15.841032] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10723 22:21:11.178460 <6>[ 15.848624] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10724 22:21:11.203428 <6>[ 15.875405] mt7921e 0000:01:00.0: ASIC revision: 79610010
10725 22:21:11.308360 <4>[ 15.974133] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10726 22:21:11.322419 Begin: Loading essential drivers ... done.
10727 22:21:11.325412 Begin: Running /scripts/init-premount ... done.
10728 22:21:11.332691 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10729 22:21:11.342142 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10730 22:21:11.345295 Device /sys/class/net/enx00e04c722dd6 found
10731 22:21:11.345818 done.
10732 22:21:11.427976 <4>[ 16.093409] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10733 22:21:11.434268 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10734 22:21:11.546897 <4>[ 16.212599] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10735 22:21:11.662682 <4>[ 16.328415] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10736 22:21:11.778209 <4>[ 16.444358] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 22:21:11.894313 <4>[ 16.560305] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10738 22:21:12.010682 <4>[ 16.676218] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10739 22:21:12.126663 <4>[ 16.792243] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10740 22:21:12.242254 <4>[ 16.908103] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10741 22:21:12.358411 <4>[ 17.024073] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10742 22:21:12.466508 IP-Config: no response after 2 s<3>[ 17.138080] mt7921e 0000:01:00.0: hardware init failed
10743 22:21:12.467034 ecs - giving up
10744 22:21:12.496113 <6>[ 17.168665] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10745 22:21:12.510414 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10746 22:21:13.615903 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10747 22:21:13.622739 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10748 22:21:13.628862 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10749 22:21:13.635458 host : mt8192-asurada-spherion-r0-cbg-1
10750 22:21:13.641999 domain : lava-rack
10751 22:21:13.648497 rootserver: 192.168.201.1 rootpath:
10752 22:21:13.648950 filename :
10753 22:21:13.698185 done.
10754 22:21:13.705831 Begin: Running /scripts/nfs-bottom ... done.
10755 22:21:13.723755 Begin: Running /scripts/init-bottom ... done.
10756 22:21:14.817535 <6>[ 19.490733] NET: Registered PF_INET6 protocol family
10757 22:21:14.825258 <6>[ 19.497669] Segment Routing with IPv6
10758 22:21:14.827788 <6>[ 19.501642] In-situ OAM (IOAM) with IPv6
10759 22:21:14.939266 <30>[ 19.592909] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10760 22:21:14.942392 <30>[ 19.616667] systemd[1]: Detected architecture arm64.
10761 22:21:14.961608
10762 22:21:14.965186 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10763 22:21:14.965367
10764 22:21:14.979902 <30>[ 19.653104] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10765 22:21:15.502240 <30>[ 20.171844] systemd[1]: Queued start job for default target Graphical Interface.
10766 22:21:15.531024 <30>[ 20.204035] systemd[1]: Created slice system-getty.slice.
10767 22:21:15.537553 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10768 22:21:15.554574 <30>[ 20.227471] systemd[1]: Created slice system-modprobe.slice.
10769 22:21:15.560746 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10770 22:21:15.578713 <30>[ 20.252007] systemd[1]: Created slice system-serial\x2dgetty.slice.
10771 22:21:15.588968 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10772 22:21:15.602274 <30>[ 20.275353] systemd[1]: Created slice User and Session Slice.
10773 22:21:15.608877 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10774 22:21:15.629337 <30>[ 20.299481] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10775 22:21:15.639597 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10776 22:21:15.657383 <30>[ 20.327098] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10777 22:21:15.663714 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10778 22:21:15.684625 <30>[ 20.350923] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10779 22:21:15.690745 <30>[ 20.362964] systemd[1]: Reached target Local Encrypted Volumes.
10780 22:21:15.697176 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10781 22:21:15.713615 <30>[ 20.387005] systemd[1]: Reached target Paths.
10782 22:21:15.716716 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10783 22:21:15.734049 <30>[ 20.407137] systemd[1]: Reached target Remote File Systems.
10784 22:21:15.740255 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10785 22:21:15.757519 <30>[ 20.430863] systemd[1]: Reached target Slices.
10786 22:21:15.760799 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10787 22:21:15.777376 <30>[ 20.450821] systemd[1]: Reached target Swap.
10788 22:21:15.780623 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10789 22:21:15.801306 <30>[ 20.471246] systemd[1]: Listening on initctl Compatibility Named Pipe.
10790 22:21:15.807955 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10791 22:21:15.814417 <30>[ 20.486759] systemd[1]: Listening on Journal Audit Socket.
10792 22:21:15.821007 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10793 22:21:15.834908 <30>[ 20.507943] systemd[1]: Listening on Journal Socket (/dev/log).
10794 22:21:15.841292 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10795 22:21:15.857503 <30>[ 20.531170] systemd[1]: Listening on Journal Socket.
10796 22:21:15.864098 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10797 22:21:15.882485 <30>[ 20.552549] systemd[1]: Listening on Network Service Netlink Socket.
10798 22:21:15.888557 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10799 22:21:15.903829 <30>[ 20.577193] systemd[1]: Listening on udev Control Socket.
10800 22:21:15.910081 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10801 22:21:15.925775 <30>[ 20.599153] systemd[1]: Listening on udev Kernel Socket.
10802 22:21:15.932283 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10803 22:21:15.981856 <30>[ 20.655235] systemd[1]: Mounting Huge Pages File System...
10804 22:21:15.988575 Mounting [0;1;39mHuge Pages File System[0m...
10805 22:21:16.004455 <30>[ 20.677464] systemd[1]: Mounting POSIX Message Queue File System...
10806 22:21:16.010921 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10807 22:21:16.027978 <30>[ 20.701421] systemd[1]: Mounting Kernel Debug File System...
10808 22:21:16.034989 Mounting [0;1;39mKernel Debug File System[0m...
10809 22:21:16.052652 <30>[ 20.723135] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10810 22:21:16.066064 <30>[ 20.736178] systemd[1]: Starting Create list of static device nodes for the current kernel...
10811 22:21:16.072702 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10812 22:21:16.096338 <30>[ 20.769473] systemd[1]: Starting Load Kernel Module configfs...
10813 22:21:16.102571 Starting [0;1;39mLoad Kernel Module configfs[0m...
10814 22:21:16.120151 <30>[ 20.793481] systemd[1]: Starting Load Kernel Module drm...
10815 22:21:16.126871 Starting [0;1;39mLoad Kernel Module drm[0m...
10816 22:21:16.148185 <30>[ 20.821541] systemd[1]: Starting Load Kernel Module fuse...
10817 22:21:16.155005 Starting [0;1;39mLoad Kernel Module fuse[0m...
10818 22:21:16.185164 <6>[ 20.858406] fuse: init (API version 7.37)
10819 22:21:16.195271 <30>[ 20.858518] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10820 22:21:16.222298 <30>[ 20.895441] systemd[1]: Starting Journal Service...
10821 22:21:16.225481 Starting [0;1;39mJournal Service[0m...
10822 22:21:16.250537 <30>[ 20.923272] systemd[1]: Starting Load Kernel Modules...
10823 22:21:16.256842 Starting [0;1;39mLoad Kernel Modules[0m...
10824 22:21:16.275286 <30>[ 20.945316] systemd[1]: Starting Remount Root and Kernel File Systems...
10825 22:21:16.282121 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10826 22:21:16.297928 <30>[ 20.970793] systemd[1]: Starting Coldplug All udev Devices...
10827 22:21:16.304018 Starting [0;1;39mColdplug All udev Devices[0m...
10828 22:21:16.320933 <30>[ 20.994044] systemd[1]: Mounted Huge Pages File System.
10829 22:21:16.327339 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10830 22:21:16.342055 <30>[ 21.015302] systemd[1]: Mounted POSIX Message Queue File System.
10831 22:21:16.348564 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10832 22:21:16.370560 <30>[ 21.043621] systemd[1]: Mounted Kernel Debug File System.
10833 22:21:16.376702 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10834 22:21:16.391889 <3>[ 21.061353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 22:21:16.401352 <30>[ 21.071354] systemd[1]: Finished Create list of static device nodes for the current kernel.
10836 22:21:16.411406 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10837 22:21:16.422965 <3>[ 21.092838] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 22:21:16.430695 <30>[ 21.103735] systemd[1]: modprobe@configfs.service: Succeeded.
10839 22:21:16.437269 <30>[ 21.110430] systemd[1]: Finished Load Kernel Module configfs.
10840 22:21:16.444031 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10841 22:21:16.459144 <30>[ 21.131806] systemd[1]: modprobe@drm.service: Succeeded.
10842 22:21:16.469666 <3>[ 21.136474] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 22:21:16.472861 <30>[ 21.138386] systemd[1]: Finished Load Kernel Module drm.
10844 22:21:16.478832 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10845 22:21:16.497343 <3>[ 21.166875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 22:21:16.503890 <30>[ 21.176848] systemd[1]: modprobe@fuse.service: Succeeded.
10847 22:21:16.510500 <30>[ 21.183212] systemd[1]: Finished Load Kernel Module fuse.
10848 22:21:16.517637 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10849 22:21:16.527279 <3>[ 21.196215] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 22:21:16.534989 <30>[ 21.208113] systemd[1]: Finished Load Kernel Modules.
10851 22:21:16.541435 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10852 22:21:16.556019 <3>[ 21.225433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 22:21:16.566264 <30>[ 21.235840] systemd[1]: Finished Remount Root and Kernel File Systems.
10854 22:21:16.573061 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10855 22:21:16.586117 <3>[ 21.255423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 22:21:16.618136 <3>[ 21.287721] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 22:21:16.630039 <30>[ 21.303338] systemd[1]: Mounting FUSE Control File System...
10858 22:21:16.636738 Mounting [0;1;39mFUSE Control File System[0m...
10859 22:21:16.651246 <3>[ 21.320791] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 22:21:16.663060 <30>[ 21.333087] systemd[1]: Mounting Kernel Configuration File System...
10861 22:21:16.666330 Mounting [0;1;39mKernel Configuration File System[0m...
10862 22:21:16.684097 <3>[ 21.353815] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10863 22:21:16.700305 <30>[ 21.369557] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10864 22:21:16.710263 <30>[ 21.378539] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10865 22:21:16.726244 <30>[ 21.399337] systemd[1]: Starting Load/Save Random Seed...
10866 22:21:16.733235 Starting [0;1;39mLoad/Save Random Seed[0m...
10867 22:21:16.752203 <30>[ 21.425462] systemd[1]: Starting Apply Kernel Variables...
10868 22:21:16.758620 Starting [0;1;39mApply Kernel Variables[0m...
10869 22:21:16.781197 <30>[ 21.454434] systemd[1]: Starting Create System Users...
10870 22:21:16.787325 Starting [0;1;39mCreate System Users[0m...
10871 22:21:16.803966 <30>[ 21.476774] systemd[1]: Started Journal Service.
10872 22:21:16.809922 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10873 22:21:16.836922 [[0;32m OK [0m] Mounted [0;<4>[ 21.499503] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10874 22:21:16.846463 1;39mFUSE Contro<3>[ 21.515299] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10875 22:21:16.846905 l File System[0m.
10876 22:21:16.862538 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10877 22:21:16.882837 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10878 22:21:16.894260 See 'systemctl status systemd-udev-trigger.service' for details.
10879 22:21:16.910747 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10880 22:21:16.927177 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10881 22:21:16.942707 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10882 22:21:16.974478 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10883 22:21:16.991981 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10884 22:21:17.030535 <46>[ 21.700486] systemd-journald[293]: Received client request to flush runtime journal.
10885 22:21:17.053776 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10886 22:21:17.066335 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10887 22:21:17.081736 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10888 22:21:17.137509 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10889 22:21:18.414916 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10890 22:21:18.454063 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10891 22:21:18.474098 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10892 22:21:18.500311 Starting [0;1;39mNetwork Service[0m...
10893 22:21:18.858569 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10894 22:21:18.878385 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10895 22:21:18.929672 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10896 22:21:19.075604 <6>[ 23.749247] remoteproc remoteproc0: powering up scp
10897 22:21:19.101725 <4>[ 23.772361] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10898 22:21:19.108698 <3>[ 23.782397] remoteproc remoteproc0: request_firmware failed: -2
10899 22:21:19.118480 <3>[ 23.788595] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10900 22:21:19.227246 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10901 22:21:19.242124 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10902 22:21:19.261128 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10903 22:21:19.303567 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10904 22:21:19.320356 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10905 22:21:19.361730 Starting [0;1;39mNetwork Name Resolution[0m...
10906 22:21:19.383213 Starting [0;1;39mNetwork Time Synchronization[0m...
10907 22:21:19.403430 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10908 22:21:19.424601 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10909 22:21:19.462141 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10910 22:21:19.535624 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10911 22:21:19.626947 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10912 22:21:19.641744 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10913 22:21:19.660295 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10914 22:21:19.673119 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10915 22:21:19.688802 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10916 22:21:19.802500 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10917 22:21:19.849020 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10918 22:21:19.871857 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10919 22:21:19.899194 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10920 22:21:19.913202 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10921 22:21:19.937411 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10922 22:21:19.953218 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10923 22:21:19.972682 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10924 22:21:20.016733 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10925 22:21:20.046388 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10926 22:21:20.105825 Starting [0;1;39mUser Login Management[0m...
10927 22:21:20.126136 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10928 22:21:20.145679 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10929 22:21:20.168600 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10930 22:21:20.209784 Starting [0;1;39mPermit User Sessions[0m...
10931 22:21:20.326941 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10932 22:21:20.374802 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10933 22:21:20.394030 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10934 22:21:20.409314 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10935 22:21:20.434465 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10936 22:21:20.451562 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10937 22:21:20.470266 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10938 22:21:20.486068 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10939 22:21:20.519468 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10940 22:21:20.555712 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10941 22:21:20.613002
10942 22:21:20.613103
10943 22:21:20.616474 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10944 22:21:20.616588
10945 22:21:20.619366 debian-bullseye-arm64 login: root (automatic login)
10946 22:21:20.619477
10947 22:21:20.619571
10948 22:21:20.855604 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
10949 22:21:20.855729
10950 22:21:20.862144 The programs included with the Debian GNU/Linux system are free software;
10951 22:21:20.868601 the exact distribution terms for each program are described in the
10952 22:21:20.872349 individual files in /usr/share/doc/*/copyright.
10953 22:21:20.872431
10954 22:21:20.878777 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10955 22:21:20.881909 permitted by applicable law.
10956 22:21:20.945984 Matched prompt #10: / #
10958 22:21:20.946219 Setting prompt string to ['/ #']
10959 22:21:20.946312 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10961 22:21:20.946503 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10962 22:21:20.946587 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
10963 22:21:20.946657 Setting prompt string to ['/ #']
10964 22:21:20.946715 Forcing a shell prompt, looking for ['/ #']
10966 22:21:20.996895 / #
10967 22:21:20.996991 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10968 22:21:20.997064 Waiting using forced prompt support (timeout 00:02:30)
10969 22:21:21.001750
10970 22:21:21.002017 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10971 22:21:21.002113 start: 2.2.7 export-device-env (timeout 00:03:33) [common]
10973 22:21:21.102457 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5'
10974 22:21:21.107904 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10597287/extract-nfsrootfs-s0lp8jx5'
10976 22:21:21.208417 / # export NFS_SERVER_IP='192.168.201.1'
10977 22:21:21.213480 export NFS_SERVER_IP='192.168.201.1'
10978 22:21:21.213757 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10979 22:21:21.213882 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10980 22:21:21.213966 end: 2 depthcharge-action (duration 00:01:28) [common]
10981 22:21:21.214053 start: 3 lava-test-retry (timeout 00:30:00) [common]
10982 22:21:21.214162 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10983 22:21:21.214235 Using namespace: common
10985 22:21:21.314571 / # #
10986 22:21:21.314680 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10987 22:21:21.319850 #
10988 22:21:21.320110 Using /lava-10597287
10990 22:21:21.420428 / # export SHELL=/bin/sh
10991 22:21:21.425375 export SHELL=/bin/sh
10993 22:21:21.525937 / # . /lava-10597287/environment
10994 22:21:21.531130 . /lava-10597287/environment
10996 22:21:21.635826 / # /lava-10597287/bin/lava-test-runner /lava-10597287/0
10997 22:21:21.635964 Test shell timeout: 10s (minimum of the action and connection timeout)
10998 22:21:21.640951 /lava-10597287/bin/lava-test-runner /lava-10597287/0
10999 22:21:21.828021 + export TESTRUN_ID=0_lc-compliance
11000 22:21:21.834425 + cd /lava-10597287/0/tests/0_lc-compliance
11001 22:21:21.834511 + cat uuid
11002 22:21:21.837994 + UUID=10597287_1.6.2.3.1
11003 22:21:21.838077 + set +x
11004 22:21:21.841115 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10597287_1.6.2.3.1>
11005 22:21:21.841371 Received signal: <STARTRUN> 0_lc-compliance 10597287_1.6.2.3.1
11006 22:21:21.841446 Starting test lava.0_lc-compliance (10597287_1.6.2.3.1)
11007 22:21:21.841534 Skipping test definition patterns.
11008 22:21:21.844208 + /usr/bin/lc-compliance-parser.sh
11009 22:21:22.971965 [0:00:27.431179135] [399] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11010 22:21:22.975096 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11011 22:21:22.984704 [0:00:27.445033341] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11012 22:21:23.039472 [0:00:27.496925773] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11013 22:21:23.047362 [==========] Running 120 tests from 1 test suite.
11014 22:21:23.091318 [0:00:27.547149825] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11015 22:21:23.113854 [----------] Global test environment set-up.
11016 22:21:23.143056 [0:00:27.597285865] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11017 22:21:23.173379 [----------] 120 tests from CaptureTests/SingleStream
11018 22:21:23.236936 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11019 22:21:23.283363 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11020 22:21:23.283632 Received signal: <TESTSET> START CaptureTests/SingleStream
11021 22:21:23.283708 Starting test_set CaptureTests/SingleStream
11022 22:21:23.286749 Camera needs 4 requests, can't test only 1
11023 22:21:23.336950 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11024 22:21:23.392418
11025 22:21:23.454868 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (52 ms)
11026 22:21:23.504172 [0:00:27.946524084] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11027 22:21:23.523567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11028 22:21:23.523825 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11030 22:21:23.535312 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11031 22:21:23.575646 Camera needs 4 requests, can't test only 2
11032 22:21:23.633326 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11033 22:21:23.687901
11034 22:21:23.743687 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (50 ms)
11035 22:21:23.808758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11036 22:21:23.809060 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11038 22:21:23.821771 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11039 22:21:23.860396 Camera needs 4 requests, can't test only 3
11040 22:21:23.915847 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11041 22:21:23.965123 [0:00:28.393881406] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11042 22:21:23.969307
11043 22:21:24.022135 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (50 ms)
11044 22:21:24.079099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11045 22:21:24.079370 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11047 22:21:24.089905 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11048 22:21:24.126695 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (350 ms)
11049 22:21:24.186826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11050 22:21:24.187118 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11052 22:21:24.196581 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11053 22:21:24.232617 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (447 ms)
11054 22:21:24.295053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11055 22:21:24.295323 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11057 22:21:24.305716 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11058 22:21:24.649752 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (673 ms)
11059 22:21:24.659733 [0:00:29.066739105] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11060 22:21:24.716620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11061 22:21:24.716888 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11063 22:21:24.727074 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11064 22:21:25.544187 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (872 ms)
11065 22:21:25.553904 [0:00:29.939276363] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11066 22:21:25.609284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11067 22:21:25.609569 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11069 22:21:25.620928 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11070 22:21:26.936145 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1362 ms)
11071 22:21:26.945978 [0:00:31.300853886] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11072 22:21:26.992489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11073 22:21:26.992805 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11075 22:21:27.001924 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11076 22:21:28.965008 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (1994 ms)
11077 22:21:28.974695 [0:00:33.295086428] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11078 22:21:29.020299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11079 22:21:29.020561 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11081 22:21:29.029866 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11082 22:21:32.190092 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3185 ms)
11083 22:21:32.199817 [0:00:36.479820955] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11084 22:21:32.250483 [0:00:36.531833162] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 22:21:32.253731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11086 22:21:32.254001 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11088 22:21:32.261916 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11089 22:21:32.301959 [0:00:36.582464974] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11090 22:21:32.305028 Camera needs 4 requests, can't test only 1
11091 22:21:32.352922 [0:00:36.633512183] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11092 22:21:32.356570 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11093 22:21:32.395807
11094 22:21:32.451438 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (52 ms)
11095 22:21:32.515306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11096 22:21:32.516051 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11098 22:21:32.529746 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11099 22:21:32.574547 Camera needs 4 requests, can't test only 2
11100 22:21:32.641871 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11101 22:21:32.704124
11102 22:21:32.713899 [0:00:36.991513578] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 22:21:32.784115 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (50 ms)
11104 22:21:32.862471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11105 22:21:32.862777 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11107 22:21:32.875415 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11108 22:21:32.921520 Camera needs 4 requests, can't test only 3
11109 22:21:32.983379 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11110 22:21:33.045304
11111 22:21:33.113932 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (51 ms)
11112 22:21:33.178470 [0:00:37.451269485] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11113 22:21:33.190758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11114 22:21:33.191027 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11116 22:21:33.203522 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11117 22:21:33.253843 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (358 ms)
11118 22:21:33.342014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11119 22:21:33.342821 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11121 22:21:33.355806 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11122 22:21:33.408243 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (460 ms)
11123 22:21:33.488847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11124 22:21:33.489595 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11126 22:21:33.504714 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11127 22:21:33.896144 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (720 ms)
11128 22:21:33.909359 [0:00:38.170400321] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 22:21:33.988191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11130 22:21:33.989066 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11132 22:21:34.000504 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11133 22:21:34.791978 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (889 ms)
11134 22:21:34.804729 [0:00:39.059673480] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11135 22:21:34.851746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11136 22:21:34.852038 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11138 22:21:34.861899 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11139 22:21:36.184368 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1383 ms)
11140 22:21:36.197027 [0:00:40.443141880] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11141 22:21:36.262425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11142 22:21:36.262714 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11144 22:21:36.274442 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11145 22:21:38.212612 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2019 ms)
11146 22:21:38.225979 [0:00:42.461890869] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 22:21:38.310466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11148 22:21:38.311184 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11150 22:21:38.324806 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11151 22:21:41.437218 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3213 ms)
11152 22:21:41.450440 [0:00:45.674794043] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 22:21:41.496358 [0:00:45.726295471] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11154 22:21:41.526613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11155 22:21:41.526879 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11157 22:21:41.540102 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11158 22:21:41.549923 [0:00:45.777280206] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11159 22:21:41.584733 Camera needs 4 requests, can't test only 1
11160 22:21:41.598602 [0:00:45.828214015] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11161 22:21:41.659637 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11162 22:21:41.729907
11163 22:21:41.806018 <6>[ 46.485411] vpu: disabling
11164 22:21:41.809026 <6>[ 46.488469] vproc2: disabling
11165 22:21:41.815724 [ SKIPPED ] Cap<6>[ 46.491750] vproc1: disabling
11166 22:21:41.819399 tureTests/Single<6>[ 46.496387] vaud18: disabling
11167 22:21:41.825864 Stream.Capture/V<6>[ 46.501157] vsram_others: disabling
11168 22:21:41.829024 ideoRecording_1 <6>[ 46.506217] va09: disabling
11169 22:21:41.829498 (51 ms)
11170 22:21:41.832423 <6>[ 46.510569] vsram_md: disabling
11171 22:21:41.835638 <6>[ 46.514787] Vgpu: disabling
11172 22:21:41.886043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11173 22:21:41.886398 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11175 22:21:41.896455 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11176 22:21:41.936084 Camera needs 4 requests, can't test only 2
11177 22:21:41.960468 [0:00:46.188871951] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 22:21:42.010021 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11179 22:21:42.085984
11180 22:21:42.169887 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (51 ms)
11181 22:21:42.261738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11182 22:21:42.262501 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11184 22:21:42.278746 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11185 22:21:42.338619 Camera needs 4 requests, can't test only 3
11186 22:21:42.416335 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11187 22:21:42.425901 [0:00:46.650723764] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11188 22:21:42.479043
11189 22:21:42.554835 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (51 ms)
11190 22:21:42.634699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11191 22:21:42.635498 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11193 22:21:42.648724 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11194 22:21:42.696373 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (361 ms)
11195 22:21:42.776123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11196 22:21:42.776896 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11198 22:21:42.790332 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11199 22:21:42.836745 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (462 ms)
11200 22:21:42.922177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11201 22:21:42.922964 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11203 22:21:42.935395 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11204 22:21:43.145021 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (724 ms)
11205 22:21:43.154729 [0:00:47.374914182] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 22:21:43.235107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11207 22:21:43.235952 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11209 22:21:43.247443 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11210 22:21:44.038054 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (894 ms)
11211 22:21:44.050761 [0:00:48.269236347] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 22:21:44.120326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11213 22:21:44.121130 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11215 22:21:44.135722 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11216 22:21:45.366730 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1327 ms)
11217 22:21:45.379499 [0:00:49.595959013] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 22:21:45.463708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11219 22:21:45.464442 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11221 22:21:45.477663 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11222 22:21:47.494848 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2122 ms)
11223 22:21:47.504743 [0:00:51.718235832] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 22:21:47.563474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11225 22:21:47.564212 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11227 22:21:47.578207 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11228 22:21:50.651936 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3157 ms)
11229 22:21:50.665117 [0:00:54.875182523] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11230 22:21:50.712264 [0:00:54.927362241] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 22:21:50.750629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11232 22:21:50.751323 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11234 22:21:50.763917 [0:00:54.978874324] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 22:21:50.767254 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11236 22:21:50.814597 [0:00:55.029620177] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11237 22:21:50.817746 Camera needs 4 requests, can't test only 1
11238 22:21:50.887105 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11239 22:21:50.950568
11240 22:21:51.022240 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (52 ms)
11241 22:21:51.099858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11242 22:21:51.100573 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11244 22:21:51.117701 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11245 22:21:51.175690 [0:00:55.390599495] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11246 22:21:51.178964 Camera needs 4 requests, can't test only 2
11247 22:21:51.248011 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11248 22:21:51.328616
11249 22:21:51.416199 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (52 ms)
11250 22:21:51.497434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11251 22:21:51.497728 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11253 22:21:51.508286 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11254 22:21:51.558027 Camera needs 4 requests, can't test only 3
11255 22:21:51.636354 [0:00:55.851381233] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11256 22:21:51.639467 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11257 22:21:51.692325
11258 22:21:51.765004 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (50 ms)
11259 22:21:51.838083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11260 22:21:51.838370 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11262 22:21:51.847647 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11263 22:21:51.882334 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (361 ms)
11264 22:21:51.958271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11265 22:21:51.958578 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11267 22:21:51.971912 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11268 22:21:52.015080 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (461 ms)
11269 22:21:52.088992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11270 22:21:52.089795 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11272 22:21:52.101114 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11273 22:21:52.321797 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (692 ms)
11274 22:21:52.334965 [0:00:56.544641551] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 22:21:52.402528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11276 22:21:52.403291 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11278 22:21:52.413724 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11279 22:21:53.216393 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (894 ms)
11280 22:21:53.229786 [0:00:57.439229624] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11281 22:21:53.307861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11282 22:21:53.308566 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11284 22:21:53.320415 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11285 22:21:54.609049 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1393 ms)
11286 22:21:54.622393 [0:00:58.832513472] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 22:21:54.697656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11288 22:21:54.698369 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11290 22:21:54.711448 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11291 22:21:56.709465 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2101 ms)
11292 22:21:56.723077 [0:01:00.933071408] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11293 22:21:56.807471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11294 22:21:56.808329 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11296 22:21:56.820648 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11297 22:21:59.879016 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3170 ms)
11298 22:21:59.892308 [0:01:04.103056899] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11299 22:21:59.939871 [0:01:04.155070620] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 22:21:59.953064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11301 22:21:59.953327 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11303 22:21:59.963358 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11304 22:21:59.991826 [0:01:04.206915417] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11305 22:21:59.999745 Camera needs 4 requests, can't test only 1
11306 22:22:00.043462 [0:01:04.258765753] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11307 22:22:00.050745 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11308 22:22:00.101266
11309 22:22:00.162778 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (53 ms)
11310 22:22:00.238658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11311 22:22:00.239377 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11313 22:22:00.253624 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11314 22:22:00.301529 Camera needs 4 requests, can't test only 2
11315 22:22:00.366520 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11316 22:22:00.433026
11317 22:22:00.499607 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (52 ms)
11318 22:22:00.573012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11319 22:22:00.573332 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11321 22:22:00.583785 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11322 22:22:00.616870 Camera needs 4 requests, can't test only 3
11323 22:22:00.675715 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11324 22:22:00.731627
11325 22:22:00.797497 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (52 ms)
11326 22:22:00.870247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11327 22:22:00.870809 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11329 22:22:00.883602 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11330 22:22:01.181513 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1145 ms)
11331 22:22:01.194249 [0:01:05.405322947] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 22:22:01.273924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11333 22:22:01.274628 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11335 22:22:01.287521 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11336 22:22:02.575473 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1395 ms)
11337 22:22:02.588660 [0:01:06.799917930] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 22:22:02.657942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11339 22:22:02.658232 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11341 22:22:02.667470 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11342 22:22:04.697816 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2122 ms)
11343 22:22:04.711069 [0:01:08.922470414] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11344 22:22:04.776256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11345 22:22:04.776556 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11347 22:22:04.786039 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11348 22:22:07.392573 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2695 ms)
11349 22:22:07.405505 [0:01:11.617248451] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11350 22:22:07.489595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11351 22:22:07.490348 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11353 22:22:07.504451 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11354 22:22:11.579658 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4188 ms)
11355 22:22:11.592716 [0:01:15.805005603] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11356 22:22:11.666400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11357 22:22:11.666722 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11359 22:22:11.677580 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11360 22:22:17.897165 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6318 ms)
11361 22:22:17.910339 [0:01:22.123488371] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11362 22:22:17.996086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11363 22:22:17.996878 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11365 22:22:18.011072 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11366 22:22:27.518878 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9623 ms)
11367 22:22:27.531728 [0:01:31.745675701] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11368 22:22:27.579871 [0:01:31.798105215] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 22:22:27.606752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11370 22:22:27.607441 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11372 22:22:27.623319 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11373 22:22:27.636380 [0:01:31.850156805] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11374 22:22:27.674406 Camera needs 4 requests, can't test only 1
11375 22:22:27.683836 [0:01:31.902239088] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 22:22:27.753314 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11377 22:22:27.829205
11378 22:22:27.899630 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (53 ms)
11379 22:22:27.961100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11380 22:22:27.961390 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11382 22:22:27.968259 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11383 22:22:28.006772 Camera needs 4 requests, can't test only 2
11384 22:22:28.066474 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11385 22:22:28.118776
11386 22:22:28.184455 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (51 ms)
11387 22:22:28.249780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11388 22:22:28.250065 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11390 22:22:28.260612 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11391 22:22:28.299730 Camera needs 4 requests, can't test only 3
11392 22:22:28.361831 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11393 22:22:28.423117
11394 22:22:28.492001 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11395 22:22:28.566461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11396 22:22:28.567369 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11398 22:22:28.576898 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11399 22:22:28.861595 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1183 ms)
11400 22:22:28.871685 [0:01:33.086050085] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11401 22:22:28.936715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11402 22:22:28.937032 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11404 22:22:28.943811 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11405 22:22:30.256684 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1395 ms)
11406 22:22:30.266272 [0:01:34.481304613] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11407 22:22:30.338412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11408 22:22:30.339337 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11410 22:22:30.347406 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11411 22:22:32.345122 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2089 ms)
11412 22:22:32.354862 [0:01:36.569513066] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11413 22:22:32.436063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11414 22:22:32.436870 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11416 22:22:32.446649 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11417 22:22:35.037207 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2692 ms)
11418 22:22:35.046887 [0:01:39.261544584] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11419 22:22:35.124843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11420 22:22:35.125573 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11422 22:22:35.134990 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11423 22:22:39.256121 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4219 ms)
11424 22:22:39.266060 [0:01:43.480711857] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 22:22:39.349482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11426 22:22:39.350233 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11428 22:22:39.360445 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11429 22:22:45.574032 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6318 ms)
11430 22:22:45.584053 [0:01:49.799410517] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11431 22:22:45.652201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11432 22:22:45.652475 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11434 22:22:45.660555 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11435 22:22:55.195009 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9622 ms)
11436 22:22:55.204337 [0:01:59.421066108] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11437 22:22:55.257582 [0:01:59.479480426] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 22:22:55.291857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11439 22:22:55.292160 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11441 22:22:55.300717 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11442 22:22:55.314342 [0:01:59.535713741] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11443 22:22:55.353204 Camera needs 4 requests, can't test only 1
11444 22:22:55.371815 [0:01:59.593704059] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11445 22:22:55.428397 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11446 22:22:55.488700
11447 22:22:55.555637 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (58 ms)
11448 22:22:55.621574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11449 22:22:55.621841 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11451 22:22:55.631102 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11452 22:22:55.671473 Camera needs 4 requests, can't test only 2
11453 22:22:55.738101 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11454 22:22:55.805805
11455 22:22:55.878550 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (57 ms)
11456 22:22:55.958335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11457 22:22:55.959092 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11459 22:22:55.970229 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11460 22:22:56.016729 Camera needs 4 requests, can't test only 3
11461 22:22:56.074389 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11462 22:22:56.138259
11463 22:22:56.207291 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11464 22:22:56.274701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11465 22:22:56.274993 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11467 22:22:56.281159 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11468 22:22:56.489884 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1123 ms)
11469 22:22:56.499781 [0:02:00.716691886] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11470 22:22:56.575820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11471 22:22:56.576517 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11473 22:22:56.587103 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11474 22:22:57.867725 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1378 ms)
11475 22:22:57.877298 [0:02:02.095727786] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11476 22:22:57.962721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11477 22:22:57.963442 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11479 22:22:57.976046 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11480 22:22:59.940972 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2073 ms)
11481 22:22:59.950546 [0:02:04.167952124] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11482 22:23:00.034425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11483 22:23:00.035118 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11485 22:23:00.048269 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11486 22:23:02.716019 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2775 ms)
11487 22:23:02.726036 [0:02:06.943536011] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 22:23:02.810304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11489 22:23:02.811052 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11491 22:23:02.821023 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11492 22:23:06.824518 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4108 ms)
11493 22:23:06.834114 [0:02:11.051549453] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11494 22:23:06.914953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11495 22:23:06.915647 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11497 22:23:06.924920 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11498 22:23:13.063817 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6239 ms)
11499 22:23:13.073519 [0:02:17.288342206] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11500 22:23:13.148541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11501 22:23:13.149264 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11503 22:23:13.160223 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11504 22:23:22.699442 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9635 ms)
11505 22:23:22.708796 [0:02:26.924541565] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11506 22:23:22.756557 [0:02:26.976445955] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 22:23:22.792308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11508 22:23:22.793116 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11510 22:23:22.807359 [0:02:27.027351935] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11511 22:23:22.813879 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11512 22:23:22.859124 [0:02:27.078984675] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 22:23:22.862112 Camera needs 4 requests, can't test only 1
11514 22:23:22.930043 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11515 22:23:23.002116
11516 22:23:23.084345 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11517 22:23:23.167839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11518 22:23:23.168581 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11520 22:23:23.178573 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11521 22:23:23.229728 Camera needs 4 requests, can't test only 2
11522 22:23:23.297384 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11523 22:23:23.360728
11524 22:23:23.435832 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (50 ms)
11525 22:23:23.514901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11526 22:23:23.515180 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11528 22:23:23.523726 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11529 22:23:23.566758 Camera needs 4 requests, can't test only 3
11530 22:23:23.632738 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11531 22:23:23.693734
11532 22:23:23.767607 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11533 22:23:23.852243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11534 22:23:23.853010 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11536 22:23:23.863765 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11537 22:23:23.933239 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1079 ms)
11538 22:23:23.943395 [0:02:28.158768094] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11539 22:23:24.016044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11540 22:23:24.016729 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11542 22:23:24.025850 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11543 22:23:25.311149 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1378 ms)
11544 22:23:25.321181 [0:02:29.536594516] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11545 22:23:25.399797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11546 22:23:25.400514 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11548 22:23:25.410421 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11549 22:23:27.383567 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2072 ms)
11550 22:23:27.393483 [0:02:31.608968232] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11551 22:23:27.483529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11552 22:23:27.484234 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11554 22:23:27.497830 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11555 22:23:30.157805 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2775 ms)
11556 22:23:30.167566 [0:02:34.383510560] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11557 22:23:30.250274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11558 22:23:30.251041 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11560 22:23:30.263083 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11561 22:23:34.265886 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4108 ms)
11562 22:23:34.275944 [0:02:38.492584489] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11563 22:23:34.365698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11564 22:23:34.366437 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11566 22:23:34.375482 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11567 22:23:40.504955 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6239 ms)
11568 22:23:40.514876 [0:02:44.732129180] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11569 22:23:40.601983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11570 22:23:40.602692 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11572 22:23:40.612985 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11573 22:23:50.206930 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9702 ms)
11574 22:23:50.216829 [0:02:54.432173796] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11575 22:23:50.295780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11576 22:23:50.296567 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11578 22:23:50.307072 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11579 22:23:50.496365 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (293 ms)
11580 22:23:50.509430 [0:02:54.724549992] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 22:23:50.588596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11582 22:23:50.589367 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11584 22:23:50.603967 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11585 22:23:50.757523 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (261 ms)
11586 22:23:50.770697 [0:02:54.987268996] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11587 22:23:50.847446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11588 22:23:50.848150 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11590 22:23:50.863710 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11591 22:23:51.053538 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (296 ms)
11592 22:23:51.066369 [0:02:55.283127594] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 22:23:51.145802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11594 22:23:51.146497 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11596 22:23:51.160978 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11597 22:23:51.415448 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (362 ms)
11598 22:23:51.428579 [0:02:55.644196614] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11599 22:23:51.505208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11600 22:23:51.506017 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11602 22:23:51.519864 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11603 22:23:51.877038 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (462 ms)
11604 22:23:51.890124 [0:02:56.107550371] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11605 22:23:51.968291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11606 22:23:51.969083 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11608 22:23:51.983405 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11609 22:23:52.572265 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (695 ms)
11610 22:23:52.585545 [0:02:56.801057761] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11611 22:23:52.664267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11612 22:23:52.664961 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11614 22:23:52.679899 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11615 22:23:53.466384 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (894 ms)
11616 22:23:53.479221 [0:02:57.695174304] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11617 22:23:53.562701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11618 22:23:53.563523 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11620 22:23:53.577950 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11621 22:23:54.858833 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1392 ms)
11622 22:23:54.871632 [0:02:59.087554077] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 22:23:54.952794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11624 22:23:54.953497 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11626 22:23:54.970156 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11627 22:23:56.887134 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2028 ms)
11628 22:23:56.900299 [0:03:01.116122321] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11629 22:23:56.990351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11630 22:23:56.991079 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11632 22:23:57.007598 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11633 22:24:00.111881 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3225 ms)
11634 22:24:00.125048 [0:03:04.341401152] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 22:24:00.216247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11636 22:24:00.216989 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11638 22:24:00.231710 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11639 22:24:00.408691 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (293 ms)
11640 22:24:00.418737 [0:03:04.634874464] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11641 22:24:00.494784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11642 22:24:00.495481 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11644 22:24:00.503711 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11645 22:24:00.671020 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (263 ms)
11646 22:24:00.681238 [0:03:04.896744205] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11647 22:24:00.765307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11648 22:24:00.766009 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11650 22:24:00.776123 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11651 22:24:00.965811 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (295 ms)
11652 22:24:00.975698 [0:03:05.191891961] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11653 22:24:01.060077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11654 22:24:01.060387 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11656 22:24:01.070892 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11657 22:24:01.327541 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (361 ms)
11658 22:24:01.337098 [0:03:05.553963374] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11659 22:24:01.422273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11660 22:24:01.423182 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11662 22:24:01.435504 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11663 22:24:01.791743 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (464 ms)
11664 22:24:01.800935 [0:03:06.018038723] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11665 22:24:01.881685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11666 22:24:01.882385 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11668 22:24:01.892580 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11669 22:24:02.517591 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (727 ms)
11670 22:24:02.527472 [0:03:06.743780119] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11671 22:24:02.606779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11672 22:24:02.607226 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11674 22:24:02.615337 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11675 22:24:03.414345 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (896 ms)
11676 22:24:03.423895 [0:03:07.640144909] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11677 22:24:03.507413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11678 22:24:03.508260 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11680 22:24:03.518513 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11681 22:24:04.806671 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1393 ms)
11682 22:24:04.816275 [0:03:09.032389665] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11683 22:24:04.899254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11684 22:24:04.899956 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11686 22:24:04.910846 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11687 22:24:06.835256 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2029 ms)
11688 22:24:06.845201 [0:03:11.061902767] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11689 22:24:06.935550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11690 22:24:06.936294 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11692 22:24:06.947416 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11693 22:24:10.060815 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3225 ms)
11694 22:24:10.070458 [0:03:14.287185125] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11695 22:24:10.155641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11696 22:24:10.156336 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11698 22:24:10.167956 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11699 22:24:10.354284 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (294 ms)
11700 22:24:10.363918 [0:03:14.580324120] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11701 22:24:10.448224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11702 22:24:10.448503 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11704 22:24:10.459238 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11705 22:24:10.649178 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (295 ms)
11706 22:24:10.658510 [0:03:14.875676852] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11707 22:24:10.734515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11708 22:24:10.734785 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11710 22:24:10.744379 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11711 22:24:10.943728 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (294 ms)
11712 22:24:10.953670 [0:03:15.170658394] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11713 22:24:11.038637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11714 22:24:11.039332 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11716 22:24:11.050479 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11717 22:24:11.305083 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (362 ms)
11718 22:24:11.314985 [0:03:15.531557852] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11719 22:24:11.402652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11720 22:24:11.403356 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11722 22:24:11.416223 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11723 22:24:11.768279 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (463 ms)
11724 22:24:11.778007 [0:03:15.995304640] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11725 22:24:11.860826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11726 22:24:11.861517 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11728 22:24:11.875124 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11729 22:24:12.494207 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (726 ms)
11730 22:24:12.504165 [0:03:16.720878761] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11731 22:24:12.599942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11732 22:24:12.600650 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11734 22:24:12.614624 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11735 22:24:13.390461 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (896 ms)
11736 22:24:13.400120 [0:03:17.617591737] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11737 22:24:13.478882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11738 22:24:13.479301 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11740 22:24:13.491311 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11741 22:24:14.720164 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1330 ms)
11742 22:24:14.729662 [0:03:18.946983742] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11743 22:24:14.815420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11744 22:24:14.816138 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11746 22:24:14.827711 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11747 22:24:16.845541 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2125 ms)
11748 22:24:16.855154 [0:03:21.072714372] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11749 22:24:16.936905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11750 22:24:16.937183 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11752 22:24:16.947325 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11753 22:24:20.005987 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3161 ms)
11754 22:24:20.015240 [0:03:24.232610608] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11755 22:24:20.094273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11756 22:24:20.094984 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11758 22:24:20.106384 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11759 22:24:20.298778 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (293 ms)
11760 22:24:20.308871 [0:03:24.526453420] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11761 22:24:20.388573 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11763 22:24:20.391268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11764 22:24:20.403387 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11765 22:24:20.593609 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (295 ms)
11766 22:24:20.603301 [0:03:24.820828595] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11767 22:24:20.678608 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11769 22:24:20.681485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11770 22:24:20.693753 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11771 22:24:20.888358 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (295 ms)
11772 22:24:20.898198 [0:03:25.115773481] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11773 22:24:20.975398 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11775 22:24:20.977792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11776 22:24:20.990186 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11777 22:24:21.248866 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (360 ms)
11778 22:24:21.258636 [0:03:25.475914391] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11779 22:24:21.344435 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11781 22:24:21.347317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11782 22:24:21.359877 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11783 22:24:21.710407 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (462 ms)
11784 22:24:21.719893 [0:03:25.938182802] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11785 22:24:21.805140 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11787 22:24:21.808430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11788 22:24:21.821398 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11789 22:24:22.403987 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (693 ms)
11790 22:24:22.414020 [0:03:26.631333149] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11791 22:24:22.494523 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11793 22:24:22.497528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11794 22:24:22.508877 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11795 22:24:23.298384 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (895 ms)
11796 22:24:23.308243 [0:03:27.526322672] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11797 22:24:23.393886 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11799 22:24:23.396759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11800 22:24:23.409090 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11801 22:24:24.627719 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1330 ms)
11802 22:24:24.637721 [0:03:28.855491404] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11803 22:24:24.721472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11804 22:24:24.721757 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11806 22:24:24.734338 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11807 22:24:26.752736 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2124 ms)
11808 22:24:26.762140 [0:03:30.980211011] [399] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11809 22:24:26.843866 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11811 22:24:26.846943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11812 22:24:26.858146 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11813 22:24:29.912644 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3161 ms)
11814 22:24:29.989655 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11816 22:24:29.992351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11817 22:24:30.000648 [----------] 120 tests from CaptureTests/SingleStream (186696 ms total)
11818 22:24:30.063326
11819 22:24:30.124231 [----------] Global test environment tear-down
11820 22:24:30.194935 [==========] 120 tests from 1 test suite ran. (186696 ms total)
11821 22:24:30.259266 <LAVA_SIGNAL_TESTSET STOP>
11822 22:24:30.259955 Received signal: <TESTSET> STOP
11823 22:24:30.260365 Closing test_set CaptureTests/SingleStream
11824 22:24:30.267168 + set +x
11825 22:24:30.270523 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10597287_1.6.2.3.1>
11826 22:24:30.271185 Received signal: <ENDRUN> 0_lc-compliance 10597287_1.6.2.3.1
11827 22:24:30.271572 Ending use of test pattern.
11828 22:24:30.271885 Ending test lava.0_lc-compliance (10597287_1.6.2.3.1), duration 188.43
11830 22:24:30.273824 <LAVA_TEST_RUNNER EXIT>
11831 22:24:30.274479 ok: lava_test_shell seems to have completed
11832 22:24:30.283462 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11833 22:24:30.284315 end: 3.1 lava-test-shell (duration 00:03:09) [common]
11834 22:24:30.284751 end: 3 lava-test-retry (duration 00:03:09) [common]
11835 22:24:30.285207 start: 4 finalize (timeout 00:10:00) [common]
11836 22:24:30.285641 start: 4.1 power-off (timeout 00:00:30) [common]
11837 22:24:30.286378 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11838 22:24:30.373166 >> Command sent successfully.
11839 22:24:30.378134 Returned 0 in 0 seconds
11840 22:24:30.479046 end: 4.1 power-off (duration 00:00:00) [common]
11842 22:24:30.480510 start: 4.2 read-feedback (timeout 00:10:00) [common]
11843 22:24:30.481905 Listened to connection for namespace 'common' for up to 1s
11844 22:24:31.482506 Finalising connection for namespace 'common'
11845 22:24:31.483235 Disconnecting from shell: Finalise
11846 22:24:31.483678 / #
11847 22:24:31.584814 end: 4.2 read-feedback (duration 00:00:01) [common]
11848 22:24:31.585676 end: 4 finalize (duration 00:00:01) [common]
11849 22:24:31.586285 Cleaning after the job
11850 22:24:31.586782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/ramdisk
11851 22:24:31.596843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/kernel
11852 22:24:31.624087 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/dtb
11853 22:24:31.624403 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/nfsrootfs
11854 22:24:31.672192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597287/tftp-deploy-i8g293z_/modules
11855 22:24:31.677487 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597287
11856 22:24:31.931001 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597287
11857 22:24:31.931168 Job finished correctly