Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 67
1 22:17:26.145933 lava-dispatcher, installed at version: 2023.05.1
2 22:17:26.146134 start: 0 validate
3 22:17:26.146266 Start time: 2023-06-05 22:17:26.146258+00:00 (UTC)
4 22:17:26.146388 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:17:26.146516 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:17:26.448797 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:17:26.449190 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:17:26.761312 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:17:26.761498 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:17:27.081209 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:17:27.081401 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:17:27.396175 validate duration: 1.25
14 22:17:27.396478 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:17:27.396587 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:17:27.396681 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:17:27.396818 Not decompressing ramdisk as can be used compressed.
18 22:17:27.396904 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 22:17:27.396983 saving as /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/ramdisk/rootfs.cpio.gz
20 22:17:27.397045 total size: 27151647 (25MB)
21 22:17:27.398194 progress 0% (0MB)
22 22:17:27.406439 progress 5% (1MB)
23 22:17:27.413629 progress 10% (2MB)
24 22:17:27.421687 progress 15% (3MB)
25 22:17:27.428905 progress 20% (5MB)
26 22:17:27.436685 progress 25% (6MB)
27 22:17:27.444004 progress 30% (7MB)
28 22:17:27.451717 progress 35% (9MB)
29 22:17:27.459356 progress 40% (10MB)
30 22:17:27.466539 progress 45% (11MB)
31 22:17:27.474812 progress 50% (12MB)
32 22:17:27.482586 progress 55% (14MB)
33 22:17:27.490804 progress 60% (15MB)
34 22:17:27.498416 progress 65% (16MB)
35 22:17:27.506214 progress 70% (18MB)
36 22:17:27.513937 progress 75% (19MB)
37 22:17:27.521556 progress 80% (20MB)
38 22:17:27.529386 progress 85% (22MB)
39 22:17:27.537072 progress 90% (23MB)
40 22:17:27.544746 progress 95% (24MB)
41 22:17:27.551988 progress 100% (25MB)
42 22:17:27.552244 25MB downloaded in 0.16s (166.85MB/s)
43 22:17:27.552460 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:17:27.552739 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:17:27.552887 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:17:27.552996 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:17:27.553135 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:17:27.553217 saving as /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/kernel/Image
50 22:17:27.553281 total size: 45746688 (43MB)
51 22:17:27.553345 No compression specified
52 22:17:27.554566 progress 0% (0MB)
53 22:17:27.567213 progress 5% (2MB)
54 22:17:27.580300 progress 10% (4MB)
55 22:17:27.592721 progress 15% (6MB)
56 22:17:27.605418 progress 20% (8MB)
57 22:17:27.617845 progress 25% (10MB)
58 22:17:27.630191 progress 30% (13MB)
59 22:17:27.642603 progress 35% (15MB)
60 22:17:27.655014 progress 40% (17MB)
61 22:17:27.667667 progress 45% (19MB)
62 22:17:27.680652 progress 50% (21MB)
63 22:17:27.693122 progress 55% (24MB)
64 22:17:27.705324 progress 60% (26MB)
65 22:17:27.717967 progress 65% (28MB)
66 22:17:27.730505 progress 70% (30MB)
67 22:17:27.743085 progress 75% (32MB)
68 22:17:27.755344 progress 80% (34MB)
69 22:17:27.768190 progress 85% (37MB)
70 22:17:27.781338 progress 90% (39MB)
71 22:17:27.794009 progress 95% (41MB)
72 22:17:27.806964 progress 100% (43MB)
73 22:17:27.807180 43MB downloaded in 0.25s (171.84MB/s)
74 22:17:27.807448 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:17:27.807875 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:17:27.808021 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:17:27.808151 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:17:27.808331 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:17:27.808438 saving as /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/dtb/mt8192-asurada-spherion-r0.dtb
81 22:17:27.808551 total size: 46924 (0MB)
82 22:17:27.808644 No compression specified
83 22:17:27.810075 progress 69% (0MB)
84 22:17:27.810369 progress 100% (0MB)
85 22:17:27.810583 0MB downloaded in 0.00s (22.06MB/s)
86 22:17:27.810769 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:17:27.811155 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:17:27.811246 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:17:27.811331 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:17:27.811460 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:17:27.811530 saving as /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/modules/modules.tar
93 22:17:27.811594 total size: 8543056 (8MB)
94 22:17:27.811681 Using unxz to decompress xz
95 22:17:27.815949 progress 0% (0MB)
96 22:17:27.838897 progress 5% (0MB)
97 22:17:27.866179 progress 10% (0MB)
98 22:17:27.892486 progress 15% (1MB)
99 22:17:27.918120 progress 20% (1MB)
100 22:17:27.942072 progress 25% (2MB)
101 22:17:27.970085 progress 30% (2MB)
102 22:17:27.995971 progress 35% (2MB)
103 22:17:28.021221 progress 40% (3MB)
104 22:17:28.046017 progress 45% (3MB)
105 22:17:28.071686 progress 50% (4MB)
106 22:17:28.096128 progress 55% (4MB)
107 22:17:28.121870 progress 60% (4MB)
108 22:17:28.148383 progress 65% (5MB)
109 22:17:28.173984 progress 70% (5MB)
110 22:17:28.198221 progress 75% (6MB)
111 22:17:28.223384 progress 80% (6MB)
112 22:17:28.249332 progress 85% (6MB)
113 22:17:28.281441 progress 90% (7MB)
114 22:17:28.307658 progress 95% (7MB)
115 22:17:28.332735 progress 100% (8MB)
116 22:17:28.338747 8MB downloaded in 0.53s (15.46MB/s)
117 22:17:28.339077 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:17:28.339371 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:17:28.339469 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:17:28.339577 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:17:28.339666 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:17:28.339755 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:17:28.339993 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y
125 22:17:28.340141 makedir: /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin
126 22:17:28.340246 makedir: /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/tests
127 22:17:28.340361 makedir: /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/results
128 22:17:28.340475 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-add-keys
129 22:17:28.340639 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-add-sources
130 22:17:28.340775 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-background-process-start
131 22:17:28.340928 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-background-process-stop
132 22:17:28.341067 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-common-functions
133 22:17:28.341228 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-echo-ipv4
134 22:17:28.341411 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-install-packages
135 22:17:28.341590 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-installed-packages
136 22:17:28.341766 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-os-build
137 22:17:28.341943 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-probe-channel
138 22:17:28.342122 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-probe-ip
139 22:17:28.342296 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-target-ip
140 22:17:28.342467 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-target-mac
141 22:17:28.342642 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-target-storage
142 22:17:28.342823 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-case
143 22:17:28.342978 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-event
144 22:17:28.343119 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-feedback
145 22:17:28.343270 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-raise
146 22:17:28.343430 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-reference
147 22:17:28.343607 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-runner
148 22:17:28.343788 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-set
149 22:17:28.343965 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-test-shell
150 22:17:28.344141 Updating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-install-packages (oe)
151 22:17:28.422667 Updating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/bin/lava-installed-packages (oe)
152 22:17:28.422910 Creating /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/environment
153 22:17:28.423048 LAVA metadata
154 22:17:28.423137 - LAVA_JOB_ID=10597279
155 22:17:28.423221 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:17:28.423376 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:17:28.423481 skipped lava-vland-overlay
158 22:17:28.423611 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:17:28.423740 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:17:28.423840 skipped lava-multinode-overlay
161 22:17:28.423963 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:17:28.424095 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:17:28.424218 Loading test definitions
164 22:17:28.424364 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:17:28.424481 Using /lava-10597279 at stage 0
166 22:17:28.424938 uuid=10597279_1.5.2.3.1 testdef=None
167 22:17:28.425072 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:17:28.425216 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:17:28.425973 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:17:28.426331 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:17:28.427247 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:17:28.427630 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:17:28.457259 runner path: /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10597279_1.5.2.3.1
176 22:17:28.457512 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:17:28.457796 Creating lava-test-runner.conf files
179 22:17:28.457871 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597279/lava-overlay-s_szr56y/lava-10597279/0 for stage 0
180 22:17:28.458008 - 0_v4l2-compliance-mtk-vcodec-enc
181 22:17:28.458161 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:17:28.458299 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:17:28.465866 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:17:28.465980 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:17:28.466078 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:17:28.466169 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:17:28.466266 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:17:29.192838 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:17:29.193265 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:17:29.193426 extracting modules file /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597279/extract-overlay-ramdisk-hzdnq7hc/ramdisk
191 22:17:29.465438 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:17:29.465634 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:17:29.465767 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597279/compress-overlay-sy2qztbs/overlay-1.5.2.4.tar.gz to ramdisk
194 22:17:29.465873 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597279/compress-overlay-sy2qztbs/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597279/extract-overlay-ramdisk-hzdnq7hc/ramdisk
195 22:17:29.475052 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:17:29.475182 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 22:17:29.475292 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:17:29.475384 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 22:17:29.475473 Building ramdisk /var/lib/lava/dispatcher/tmp/10597279/extract-overlay-ramdisk-hzdnq7hc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597279/extract-overlay-ramdisk-hzdnq7hc/ramdisk
200 22:17:30.017760 >> 230342 blocks
201 22:17:34.138979 rename /var/lib/lava/dispatcher/tmp/10597279/extract-overlay-ramdisk-hzdnq7hc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/ramdisk/ramdisk.cpio.gz
202 22:17:34.139413 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:17:34.139537 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 22:17:34.139637 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 22:17:34.139747 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/kernel/Image'
206 22:17:46.369406 Returned 0 in 12 seconds
207 22:17:46.469996 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/kernel/image.itb
208 22:17:47.028444 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:17:47.028818 output: Created: Mon Jun 5 23:17:46 2023
210 22:17:47.028932 output: Image 0 (kernel-1)
211 22:17:47.029027 output: Description:
212 22:17:47.029119 output: Created: Mon Jun 5 23:17:46 2023
213 22:17:47.029212 output: Type: Kernel Image
214 22:17:47.029306 output: Compression: lzma compressed
215 22:17:47.029406 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
216 22:17:47.029498 output: Architecture: AArch64
217 22:17:47.029586 output: OS: Linux
218 22:17:47.029671 output: Load Address: 0x00000000
219 22:17:47.029758 output: Entry Point: 0x00000000
220 22:17:47.029820 output: Hash algo: crc32
221 22:17:47.029894 output: Hash value: c242daf7
222 22:17:47.029979 output: Image 1 (fdt-1)
223 22:17:47.030061 output: Description: mt8192-asurada-spherion-r0
224 22:17:47.030145 output: Created: Mon Jun 5 23:17:46 2023
225 22:17:47.030229 output: Type: Flat Device Tree
226 22:17:47.030323 output: Compression: uncompressed
227 22:17:47.030424 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:17:47.030513 output: Architecture: AArch64
229 22:17:47.030597 output: Hash algo: crc32
230 22:17:47.030712 output: Hash value: 1df858fa
231 22:17:47.030797 output: Image 2 (ramdisk-1)
232 22:17:47.030927 output: Description: unavailable
233 22:17:47.030997 output: Created: Mon Jun 5 23:17:46 2023
234 22:17:47.031051 output: Type: RAMDisk Image
235 22:17:47.031105 output: Compression: Unknown Compression
236 22:17:47.031159 output: Data Size: 40129244 Bytes = 39188.71 KiB = 38.27 MiB
237 22:17:47.031212 output: Architecture: AArch64
238 22:17:47.031268 output: OS: Linux
239 22:17:47.031328 output: Load Address: unavailable
240 22:17:47.031382 output: Entry Point: unavailable
241 22:17:47.031466 output: Hash algo: crc32
242 22:17:47.031525 output: Hash value: af911e81
243 22:17:47.031582 output: Default Configuration: 'conf-1'
244 22:17:47.031634 output: Configuration 0 (conf-1)
245 22:17:47.031687 output: Description: mt8192-asurada-spherion-r0
246 22:17:47.031739 output: Kernel: kernel-1
247 22:17:47.031793 output: Init Ramdisk: ramdisk-1
248 22:17:47.031849 output: FDT: fdt-1
249 22:17:47.031906 output: Loadables: kernel-1
250 22:17:47.031975 output:
251 22:17:47.032202 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 22:17:47.032330 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 22:17:47.032468 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 22:17:47.032572 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 22:17:47.032655 No LXC device requested
256 22:17:47.032753 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:17:47.032874 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 22:17:47.032995 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:17:47.033096 Checking files for TFTP limit of 4294967296 bytes.
260 22:17:47.033772 end: 1 tftp-deploy (duration 00:00:20) [common]
261 22:17:47.033905 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:17:47.034052 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:17:47.034250 substitutions:
264 22:17:47.034346 - {DTB}: 10597279/tftp-deploy-u74z_xer/dtb/mt8192-asurada-spherion-r0.dtb
265 22:17:47.034440 - {INITRD}: 10597279/tftp-deploy-u74z_xer/ramdisk/ramdisk.cpio.gz
266 22:17:47.034541 - {KERNEL}: 10597279/tftp-deploy-u74z_xer/kernel/Image
267 22:17:47.034630 - {LAVA_MAC}: None
268 22:17:47.034716 - {PRESEED_CONFIG}: None
269 22:17:47.034804 - {PRESEED_LOCAL}: None
270 22:17:47.034878 - {RAMDISK}: 10597279/tftp-deploy-u74z_xer/ramdisk/ramdisk.cpio.gz
271 22:17:47.034935 - {ROOT_PART}: None
272 22:17:47.035015 - {ROOT}: None
273 22:17:47.035074 - {SERVER_IP}: 192.168.201.1
274 22:17:47.035130 - {TEE}: None
275 22:17:47.035187 Parsed boot commands:
276 22:17:47.035243 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:17:47.035409 Parsed boot commands: tftpboot 192.168.201.1 10597279/tftp-deploy-u74z_xer/kernel/image.itb 10597279/tftp-deploy-u74z_xer/kernel/cmdline
278 22:17:47.035501 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:17:47.035599 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:17:47.035690 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:17:47.035775 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:17:47.035845 Not connected, no need to disconnect.
283 22:17:47.035919 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:17:47.036002 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:17:47.036084 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 22:17:47.039234 Setting prompt string to ['lava-test: # ']
287 22:17:47.039573 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:17:47.039692 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:17:47.039788 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:17:47.039883 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:17:47.040201 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 22:17:52.171639 >> Command sent successfully.
293 22:17:52.174004 Returned 0 in 5 seconds
294 22:17:52.274384 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:17:52.275063 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:17:52.275163 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:17:52.275263 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:17:52.275332 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:17:52.275543 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:17:52.275986 [Enter `^Ec?' for help]
302 22:17:52.447654
303 22:17:52.447806
304 22:17:52.447884 F0: 102B 0000
305 22:17:52.447962
306 22:17:52.448040 F3: 1001 0000 [0200]
307 22:17:52.448101
308 22:17:52.451197 F3: 1001 0000
309 22:17:52.451297
310 22:17:52.451366 F7: 102D 0000
311 22:17:52.451429
312 22:17:52.451489 F1: 0000 0000
313 22:17:52.455299
314 22:17:52.455387 V0: 0000 0000 [0001]
315 22:17:52.455470
316 22:17:52.455534 00: 0007 8000
317 22:17:52.455606
318 22:17:52.458673 01: 0000 0000
319 22:17:52.458789
320 22:17:52.458886 BP: 0C00 0209 [0000]
321 22:17:52.458950
322 22:17:52.462018 G0: 1182 0000
323 22:17:52.462142
324 22:17:52.462238 EC: 0000 0021 [4000]
325 22:17:52.462341
326 22:17:52.465956 S7: 0000 0000 [0000]
327 22:17:52.466055
328 22:17:52.466125 CC: 0000 0000 [0001]
329 22:17:52.466189
330 22:17:52.469517 T0: 0000 0040 [010F]
331 22:17:52.469618
332 22:17:52.469719 Jump to BL
333 22:17:52.469797
334 22:17:52.493954
335 22:17:52.494092
336 22:17:52.494164
337 22:17:52.501315 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:17:52.504731 ARM64: Exception handlers installed.
339 22:17:52.508297 ARM64: Testing exception
340 22:17:52.511571 ARM64: Done test exception
341 22:17:52.518414 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:17:52.529306 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:17:52.535768 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:17:52.545659 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:17:52.552246 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:17:52.559030 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:17:52.571035 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:17:52.577871 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:17:52.596964 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:17:52.600329 WDT: Last reset was cold boot
351 22:17:52.604052 SPI1(PAD0) initialized at 2873684 Hz
352 22:17:52.607653 SPI5(PAD0) initialized at 992727 Hz
353 22:17:52.610529 VBOOT: Loading verstage.
354 22:17:52.616872 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:17:52.620607 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:17:52.623771 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:17:52.627056 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:17:52.634592 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:17:52.641096 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:17:52.652473 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:17:52.652565
362 22:17:52.652634
363 22:17:52.661900 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:17:52.665646 ARM64: Exception handlers installed.
365 22:17:52.668823 ARM64: Testing exception
366 22:17:52.672052 ARM64: Done test exception
367 22:17:52.676745 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:17:52.679782 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:17:52.692704 Probing TPM: . done!
370 22:17:52.692790 TPM ready after 0 ms
371 22:17:52.699807 Connected to device vid:did:rid of 1ae0:0028:00
372 22:17:52.749135 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:17:52.749297 Initialized TPM device CR50 revision 0
374 22:17:52.760852 tlcl_send_startup: Startup return code is 0
375 22:17:52.760974 TPM: setup succeeded
376 22:17:52.772054 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:17:52.780984 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:17:52.792684 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:17:52.801765 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:17:52.804970 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:17:52.808073 in-header: 03 07 00 00 08 00 00 00
382 22:17:52.811718 in-data: aa e4 47 04 13 02 00 00
383 22:17:52.814902 Chrome EC: UHEPI supported
384 22:17:52.822534 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:17:52.826334 in-header: 03 9d 00 00 08 00 00 00
386 22:17:52.829930 in-data: 10 20 20 08 00 00 00 00
387 22:17:52.830048 Phase 1
388 22:17:52.833824 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:17:52.840739 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:17:52.844440 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:17:52.848194 Recovery requested (1009000e)
392 22:17:52.856621 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:17:52.861639 tlcl_extend: response is 0
394 22:17:52.870006 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:17:52.874768 tlcl_extend: response is 0
396 22:17:52.881754 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:17:52.903140 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:17:52.909867 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:17:52.909989
400 22:17:52.910087
401 22:17:52.920948 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:17:52.921046 ARM64: Exception handlers installed.
403 22:17:52.924743 ARM64: Testing exception
404 22:17:52.927753 ARM64: Done test exception
405 22:17:52.948458 pmic_efuse_setting: Set efuses in 11 msecs
406 22:17:52.951667 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:17:52.955563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:17:52.962678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:17:52.966396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:17:52.972878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:17:52.977298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:17:52.980647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:17:52.987749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:17:52.991299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:17:52.994670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:17:53.001191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:17:53.004446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:17:53.007793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:17:53.014671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:17:53.021034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:17:53.024670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:17:53.031229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:17:53.037862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:17:53.044373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:17:53.048123 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:17:53.054962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:17:53.058935 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:17:53.065471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:17:53.072546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:17:53.075846 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:17:53.083005 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:17:53.085977 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:17:53.093081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:17:53.096120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:17:53.103205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:17:53.106509 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:17:53.113529 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:17:53.117508 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:17:53.120759 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:17:53.127224 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:17:53.131031 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:17:53.138419 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:17:53.141734 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:17:53.145054 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:17:53.151986 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:17:53.155256 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:17:53.158341 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:17:53.164785 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:17:53.168145 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:17:53.172038 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:17:53.178410 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:17:53.181703 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:17:53.185297 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:17:53.191507 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:17:53.194565 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:17:53.198147 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:17:53.201326 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:17:53.211684 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:17:53.218109 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:17:53.224616 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:17:53.231145 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:17:53.241404 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:17:53.244619 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:17:53.247765 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:17:53.254682 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:17:53.261150 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 22:17:53.267542 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:17:53.270704 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 22:17:53.273974 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:17:53.285008 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 22:17:53.288152 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 22:17:53.294956 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 22:17:53.297878 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 22:17:53.301662 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 22:17:53.304602 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 22:17:53.308078 ADC[4]: Raw value=894821 ID=7
477 22:17:53.312117 ADC[3]: Raw value=212700 ID=1
478 22:17:53.315108 RAM Code: 0x71
479 22:17:53.318248 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 22:17:53.321451 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 22:17:53.331761 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 22:17:53.338846 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 22:17:53.341938 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 22:17:53.344912 in-header: 03 07 00 00 08 00 00 00
485 22:17:53.348741 in-data: aa e4 47 04 13 02 00 00
486 22:17:53.351944 Chrome EC: UHEPI supported
487 22:17:53.358850 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 22:17:53.362205 in-header: 03 d5 00 00 08 00 00 00
489 22:17:53.366340 in-data: 98 20 60 08 00 00 00 00
490 22:17:53.366428 MRC: failed to locate region type 0.
491 22:17:53.372960 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 22:17:53.376866 DRAM-K: Running full calibration
493 22:17:53.383307 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 22:17:53.386515 header.status = 0x0
495 22:17:53.386619 header.version = 0x6 (expected: 0x6)
496 22:17:53.393044 header.size = 0xd00 (expected: 0xd00)
497 22:17:53.393124 header.flags = 0x0
498 22:17:53.400022 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 22:17:53.417100 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 22:17:53.423800 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 22:17:53.427649 dram_init: ddr_geometry: 2
502 22:17:53.427759 [EMI] MDL number = 2
503 22:17:53.430981 [EMI] Get MDL freq = 0
504 22:17:53.434784 dram_init: ddr_type: 0
505 22:17:53.434934 is_discrete_lpddr4: 1
506 22:17:53.438109 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 22:17:53.438222
508 22:17:53.438322
509 22:17:53.441979 [Bian_co] ETT version 0.0.0.1
510 22:17:53.445874 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 22:17:53.445986
512 22:17:53.448986 dramc_set_vcore_voltage set vcore to 650000
513 22:17:53.452625 Read voltage for 800, 4
514 22:17:53.452734 Vio18 = 0
515 22:17:53.452833 Vcore = 650000
516 22:17:53.456527 Vdram = 0
517 22:17:53.456636 Vddq = 0
518 22:17:53.456735 Vmddr = 0
519 22:17:53.459677 dram_init: config_dvfs: 1
520 22:17:53.463571 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 22:17:53.470547 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 22:17:53.474597 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 22:17:53.478099 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 22:17:53.481343 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 22:17:53.485264 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 22:17:53.489180 MEM_TYPE=3, freq_sel=18
527 22:17:53.489341 sv_algorithm_assistance_LP4_1600
528 22:17:53.496280 ============ PULL DRAM RESETB DOWN ============
529 22:17:53.500172 ========== PULL DRAM RESETB DOWN end =========
530 22:17:53.503358 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 22:17:53.507238 ===================================
532 22:17:53.507331 LPDDR4 DRAM CONFIGURATION
533 22:17:53.510917 ===================================
534 22:17:53.514589 EX_ROW_EN[0] = 0x0
535 22:17:53.514667 EX_ROW_EN[1] = 0x0
536 22:17:53.518086 LP4Y_EN = 0x0
537 22:17:53.518176 WORK_FSP = 0x0
538 22:17:53.521715 WL = 0x2
539 22:17:53.521794 RL = 0x2
540 22:17:53.524715 BL = 0x2
541 22:17:53.524790 RPST = 0x0
542 22:17:53.528092 RD_PRE = 0x0
543 22:17:53.528170 WR_PRE = 0x1
544 22:17:53.531277 WR_PST = 0x0
545 22:17:53.531368 DBI_WR = 0x0
546 22:17:53.535245 DBI_RD = 0x0
547 22:17:53.538574 OTF = 0x1
548 22:17:53.541637 ===================================
549 22:17:53.544857 ===================================
550 22:17:53.544934 ANA top config
551 22:17:53.548081 ===================================
552 22:17:53.551319 DLL_ASYNC_EN = 0
553 22:17:53.551393 ALL_SLAVE_EN = 1
554 22:17:53.555170 NEW_RANK_MODE = 1
555 22:17:53.558176 DLL_IDLE_MODE = 1
556 22:17:53.561341 LP45_APHY_COMB_EN = 1
557 22:17:53.564541 TX_ODT_DIS = 1
558 22:17:53.564618 NEW_8X_MODE = 1
559 22:17:53.567720 ===================================
560 22:17:53.571049 ===================================
561 22:17:53.574890 data_rate = 1600
562 22:17:53.577966 CKR = 1
563 22:17:53.580966 DQ_P2S_RATIO = 8
564 22:17:53.584511 ===================================
565 22:17:53.588006 CA_P2S_RATIO = 8
566 22:17:53.591114 DQ_CA_OPEN = 0
567 22:17:53.591193 DQ_SEMI_OPEN = 0
568 22:17:53.594313 CA_SEMI_OPEN = 0
569 22:17:53.597618 CA_FULL_RATE = 0
570 22:17:53.600865 DQ_CKDIV4_EN = 1
571 22:17:53.604695 CA_CKDIV4_EN = 1
572 22:17:53.607903 CA_PREDIV_EN = 0
573 22:17:53.608006 PH8_DLY = 0
574 22:17:53.610985 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 22:17:53.614670 DQ_AAMCK_DIV = 4
576 22:17:53.617742 CA_AAMCK_DIV = 4
577 22:17:53.621420 CA_ADMCK_DIV = 4
578 22:17:53.624517 DQ_TRACK_CA_EN = 0
579 22:17:53.624600 CA_PICK = 800
580 22:17:53.627544 CA_MCKIO = 800
581 22:17:53.631278 MCKIO_SEMI = 0
582 22:17:53.634134 PLL_FREQ = 3068
583 22:17:53.637952 DQ_UI_PI_RATIO = 32
584 22:17:53.641239 CA_UI_PI_RATIO = 0
585 22:17:53.644408 ===================================
586 22:17:53.647564 ===================================
587 22:17:53.647641 memory_type:LPDDR4
588 22:17:53.650792 GP_NUM : 10
589 22:17:53.653937 SRAM_EN : 1
590 22:17:53.654040 MD32_EN : 0
591 22:17:53.657892 ===================================
592 22:17:53.660981 [ANA_INIT] >>>>>>>>>>>>>>
593 22:17:53.663959 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 22:17:53.667315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 22:17:53.671155 ===================================
596 22:17:53.674330 data_rate = 1600,PCW = 0X7600
597 22:17:53.677496 ===================================
598 22:17:53.680731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:17:53.683773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 22:17:53.690654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 22:17:53.697601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 22:17:53.700228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 22:17:53.704097 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 22:17:53.704212 [ANA_INIT] flow start
605 22:17:53.707338 [ANA_INIT] PLL >>>>>>>>
606 22:17:53.707465 [ANA_INIT] PLL <<<<<<<<
607 22:17:53.711183 [ANA_INIT] MIDPI >>>>>>>>
608 22:17:53.714367 [ANA_INIT] MIDPI <<<<<<<<
609 22:17:53.714467 [ANA_INIT] DLL >>>>>>>>
610 22:17:53.718138 [ANA_INIT] flow end
611 22:17:53.721749 ============ LP4 DIFF to SE enter ============
612 22:17:53.725555 ============ LP4 DIFF to SE exit ============
613 22:17:53.728600 [ANA_INIT] <<<<<<<<<<<<<
614 22:17:53.732264 [Flow] Enable top DCM control >>>>>
615 22:17:53.736162 [Flow] Enable top DCM control <<<<<
616 22:17:53.739805 Enable DLL master slave shuffle
617 22:17:53.743273 ==============================================================
618 22:17:53.747219 Gating Mode config
619 22:17:53.750341 ==============================================================
620 22:17:53.753590 Config description:
621 22:17:53.763472 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 22:17:53.770426 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 22:17:53.773507 SELPH_MODE 0: By rank 1: By Phase
624 22:17:53.780039 ==============================================================
625 22:17:53.783307 GAT_TRACK_EN = 1
626 22:17:53.786895 RX_GATING_MODE = 2
627 22:17:53.787009 RX_GATING_TRACK_MODE = 2
628 22:17:53.790141 SELPH_MODE = 1
629 22:17:53.793404 PICG_EARLY_EN = 1
630 22:17:53.796645 VALID_LAT_VALUE = 1
631 22:17:53.803700 ==============================================================
632 22:17:53.806609 Enter into Gating configuration >>>>
633 22:17:53.810225 Exit from Gating configuration <<<<
634 22:17:53.813547 Enter into DVFS_PRE_config >>>>>
635 22:17:53.823711 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 22:17:53.826815 Exit from DVFS_PRE_config <<<<<
637 22:17:53.830003 Enter into PICG configuration >>>>
638 22:17:53.833987 Exit from PICG configuration <<<<
639 22:17:53.836770 [RX_INPUT] configuration >>>>>
640 22:17:53.840264 [RX_INPUT] configuration <<<<<
641 22:17:53.843539 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 22:17:53.850135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 22:17:53.856818 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 22:17:53.863173 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 22:17:53.866345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 22:17:53.873259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 22:17:53.876543 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 22:17:53.883262 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 22:17:53.886574 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 22:17:53.889630 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 22:17:53.892710 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 22:17:53.899954 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 22:17:53.903195 ===================================
654 22:17:53.906116 LPDDR4 DRAM CONFIGURATION
655 22:17:53.906243 ===================================
656 22:17:53.909364 EX_ROW_EN[0] = 0x0
657 22:17:53.912975 EX_ROW_EN[1] = 0x0
658 22:17:53.913092 LP4Y_EN = 0x0
659 22:17:53.916343 WORK_FSP = 0x0
660 22:17:53.916459 WL = 0x2
661 22:17:53.919579 RL = 0x2
662 22:17:53.919659 BL = 0x2
663 22:17:53.923173 RPST = 0x0
664 22:17:53.923264 RD_PRE = 0x0
665 22:17:53.926264 WR_PRE = 0x1
666 22:17:53.926368 WR_PST = 0x0
667 22:17:53.929352 DBI_WR = 0x0
668 22:17:53.929450 DBI_RD = 0x0
669 22:17:53.932613 OTF = 0x1
670 22:17:53.935776 ===================================
671 22:17:53.939667 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 22:17:53.942725 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 22:17:53.949549 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 22:17:53.952678 ===================================
675 22:17:53.952791 LPDDR4 DRAM CONFIGURATION
676 22:17:53.955854 ===================================
677 22:17:53.959571 EX_ROW_EN[0] = 0x10
678 22:17:53.962777 EX_ROW_EN[1] = 0x0
679 22:17:53.962876 LP4Y_EN = 0x0
680 22:17:53.966127 WORK_FSP = 0x0
681 22:17:53.966233 WL = 0x2
682 22:17:53.969530 RL = 0x2
683 22:17:53.969611 BL = 0x2
684 22:17:53.972671 RPST = 0x0
685 22:17:53.972777 RD_PRE = 0x0
686 22:17:53.975953 WR_PRE = 0x1
687 22:17:53.976056 WR_PST = 0x0
688 22:17:53.979124 DBI_WR = 0x0
689 22:17:53.979203 DBI_RD = 0x0
690 22:17:53.982339 OTF = 0x1
691 22:17:53.986103 ===================================
692 22:17:53.993007 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 22:17:53.996719 nWR fixed to 40
694 22:17:53.996810 [ModeRegInit_LP4] CH0 RK0
695 22:17:54.000649 [ModeRegInit_LP4] CH0 RK1
696 22:17:54.003957 [ModeRegInit_LP4] CH1 RK0
697 22:17:54.004073 [ModeRegInit_LP4] CH1 RK1
698 22:17:54.007805 match AC timing 13
699 22:17:54.011466 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 22:17:54.014631 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 22:17:54.018437 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 22:17:54.025707 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 22:17:54.029249 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 22:17:54.029375 [EMI DOE] emi_dcm 0
705 22:17:54.032956 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 22:17:54.036780 ==
707 22:17:54.036868 Dram Type= 6, Freq= 0, CH_0, rank 0
708 22:17:54.043805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 22:17:54.043903 ==
710 22:17:54.046924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 22:17:54.054317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 22:17:54.062891 [CA 0] Center 38 (7~69) winsize 63
713 22:17:54.066804 [CA 1] Center 37 (7~68) winsize 62
714 22:17:54.070065 [CA 2] Center 35 (5~66) winsize 62
715 22:17:54.073827 [CA 3] Center 35 (5~66) winsize 62
716 22:17:54.077032 [CA 4] Center 34 (4~65) winsize 62
717 22:17:54.080936 [CA 5] Center 33 (3~64) winsize 62
718 22:17:54.081026
719 22:17:54.084145 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 22:17:54.084233
721 22:17:54.088018 [CATrainingPosCal] consider 1 rank data
722 22:17:54.091128 u2DelayCellTimex100 = 270/100 ps
723 22:17:54.094763 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
724 22:17:54.098474 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
725 22:17:54.102260 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
726 22:17:54.106043 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
727 22:17:54.109824 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
728 22:17:54.113659 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
729 22:17:54.113752
730 22:17:54.117472 CA PerBit enable=1, Macro0, CA PI delay=33
731 22:17:54.117593
732 22:17:54.121126 [CBTSetCACLKResult] CA Dly = 33
733 22:17:54.121249 CS Dly: 6 (0~37)
734 22:17:54.121351 ==
735 22:17:54.124546 Dram Type= 6, Freq= 0, CH_0, rank 1
736 22:17:54.128624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 22:17:54.128743 ==
738 22:17:54.136120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 22:17:54.139345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 22:17:54.149677 [CA 0] Center 38 (7~69) winsize 63
741 22:17:54.153483 [CA 1] Center 38 (7~69) winsize 63
742 22:17:54.156685 [CA 2] Center 35 (5~66) winsize 62
743 22:17:54.160404 [CA 3] Center 35 (5~66) winsize 62
744 22:17:54.164718 [CA 4] Center 34 (4~65) winsize 62
745 22:17:54.168005 [CA 5] Center 34 (4~65) winsize 62
746 22:17:54.168124
747 22:17:54.171561 [CmdBusTrainingLP45] Vref(ca) range 1: 30
748 22:17:54.171673
749 22:17:54.175376 [CATrainingPosCal] consider 2 rank data
750 22:17:54.179105 u2DelayCellTimex100 = 270/100 ps
751 22:17:54.182325 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 22:17:54.186138 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 22:17:54.186257 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 22:17:54.189908 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 22:17:54.193334 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 22:17:54.196924 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 22:17:54.200631
758 22:17:54.204411 CA PerBit enable=1, Macro0, CA PI delay=34
759 22:17:54.204527
760 22:17:54.204625 [CBTSetCACLKResult] CA Dly = 34
761 22:17:54.208243 CS Dly: 6 (0~37)
762 22:17:54.208328
763 22:17:54.212144 ----->DramcWriteLeveling(PI) begin...
764 22:17:54.212265 ==
765 22:17:54.215940 Dram Type= 6, Freq= 0, CH_0, rank 0
766 22:17:54.219478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 22:17:54.219602 ==
768 22:17:54.223291 Write leveling (Byte 0): 33 => 33
769 22:17:54.226614 Write leveling (Byte 1): 28 => 28
770 22:17:54.226702 DramcWriteLeveling(PI) end<-----
771 22:17:54.226800
772 22:17:54.226885 ==
773 22:17:54.230501 Dram Type= 6, Freq= 0, CH_0, rank 0
774 22:17:54.234486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 22:17:54.237650 ==
776 22:17:54.237733 [Gating] SW mode calibration
777 22:17:54.245423 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 22:17:54.252640 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 22:17:54.255743 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 22:17:54.259603 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 22:17:54.263388 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
782 22:17:54.267180 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 22:17:54.274489 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 22:17:54.277939 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 22:17:54.281625 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 22:17:54.284971 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:17:54.288839 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:17:54.296382 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:17:54.299594 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:17:54.303273 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:17:54.306894 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:17:54.313674 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:17:54.316889 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:17:54.320747 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:17:54.327430 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:17:54.330637 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 22:17:54.333977 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 22:17:54.337289 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
799 22:17:54.343558 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:17:54.346856 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:17:54.350345 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:17:54.356921 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:17:54.360658 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:17:54.363824 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:17:54.370301 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:17:54.373369 0 9 12 | B1->B0 | 2e2e 3131 | 0 1 | (0 0) (0 0)
807 22:17:54.377292 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 22:17:54.383360 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 22:17:54.386868 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 22:17:54.390373 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 22:17:54.396723 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:17:54.399915 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:17:54.403166 0 10 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
814 22:17:54.410183 0 10 12 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
815 22:17:54.413080 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:17:54.416705 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:17:54.423096 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:17:54.426942 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:17:54.429916 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:17:54.436799 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:17:54.439906 0 11 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
822 22:17:54.443247 0 11 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
823 22:17:54.449796 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 22:17:54.453128 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 22:17:54.456598 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 22:17:54.463105 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 22:17:54.466120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:17:54.469901 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:17:54.476185 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 22:17:54.479837 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 22:17:54.483240 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 22:17:54.489383 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 22:17:54.492543 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 22:17:54.496263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:17:54.502753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:17:54.505947 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:17:54.509101 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:17:54.515978 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:17:54.519041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:17:54.522597 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:17:54.529358 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:17:54.532505 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:17:54.535557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:17:54.542003 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
845 22:17:54.545826 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 22:17:54.549069 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 22:17:54.552258 Total UI for P1: 0, mck2ui 16
848 22:17:54.555353 best dqsien dly found for B0: ( 0, 14, 6)
849 22:17:54.559160 Total UI for P1: 0, mck2ui 16
850 22:17:54.562300 best dqsien dly found for B1: ( 0, 14, 10)
851 22:17:54.566028 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
852 22:17:54.568823 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 22:17:54.568929
854 22:17:54.572395 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
855 22:17:54.578574 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 22:17:54.578682 [Gating] SW calibration Done
857 22:17:54.578787 ==
858 22:17:54.582131 Dram Type= 6, Freq= 0, CH_0, rank 0
859 22:17:54.588946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 22:17:54.589051 ==
861 22:17:54.589154 RX Vref Scan: 0
862 22:17:54.589246
863 22:17:54.592138 RX Vref 0 -> 0, step: 1
864 22:17:54.592246
865 22:17:54.595312 RX Delay -130 -> 252, step: 16
866 22:17:54.598491 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 22:17:54.602177 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 22:17:54.605094 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
869 22:17:54.612248 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
870 22:17:54.615394 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 22:17:54.618623 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 22:17:54.621696 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 22:17:54.625231 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 22:17:54.631764 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 22:17:54.635392 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
876 22:17:54.638907 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 22:17:54.642249 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 22:17:54.645241 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 22:17:54.651742 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 22:17:54.654904 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 22:17:54.658090 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 22:17:54.658176 ==
883 22:17:54.661954 Dram Type= 6, Freq= 0, CH_0, rank 0
884 22:17:54.665053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 22:17:54.668188 ==
886 22:17:54.668274 DQS Delay:
887 22:17:54.668343 DQS0 = 0, DQS1 = 0
888 22:17:54.671934 DQM Delay:
889 22:17:54.672024 DQM0 = 83, DQM1 = 70
890 22:17:54.674875 DQ Delay:
891 22:17:54.674961 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
892 22:17:54.678336 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 22:17:54.681519 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
894 22:17:54.685183 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 22:17:54.685276
896 22:17:54.688204
897 22:17:54.688301 ==
898 22:17:54.691393 Dram Type= 6, Freq= 0, CH_0, rank 0
899 22:17:54.694666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 22:17:54.694752 ==
901 22:17:54.694820
902 22:17:54.694892
903 22:17:54.698695 TX Vref Scan disable
904 22:17:54.698781 == TX Byte 0 ==
905 22:17:54.702417 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
906 22:17:54.708800 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
907 22:17:54.708887 == TX Byte 1 ==
908 22:17:54.711722 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
909 22:17:54.718594 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
910 22:17:54.718684 ==
911 22:17:54.721813 Dram Type= 6, Freq= 0, CH_0, rank 0
912 22:17:54.725029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 22:17:54.725120 ==
914 22:17:54.739125 TX Vref=22, minBit 1, minWin=27, winSum=438
915 22:17:54.742051 TX Vref=24, minBit 0, minWin=27, winSum=441
916 22:17:54.745334 TX Vref=26, minBit 0, minWin=27, winSum=445
917 22:17:54.748980 TX Vref=28, minBit 0, minWin=28, winSum=449
918 22:17:54.752191 TX Vref=30, minBit 4, minWin=27, winSum=443
919 22:17:54.755367 TX Vref=32, minBit 9, minWin=27, winSum=444
920 22:17:54.762358 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 28
921 22:17:54.762444
922 22:17:54.765598 Final TX Range 1 Vref 28
923 22:17:54.765676
924 22:17:54.765740 ==
925 22:17:54.768650 Dram Type= 6, Freq= 0, CH_0, rank 0
926 22:17:54.771779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 22:17:54.771879 ==
928 22:17:54.771945
929 22:17:54.775615
930 22:17:54.775713 TX Vref Scan disable
931 22:17:54.779072 == TX Byte 0 ==
932 22:17:54.782473 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
933 22:17:54.788759 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
934 22:17:54.788846 == TX Byte 1 ==
935 22:17:54.791715 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
936 22:17:54.798569 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
937 22:17:54.798651
938 22:17:54.798717 [DATLAT]
939 22:17:54.798780 Freq=800, CH0 RK0
940 22:17:54.798857
941 22:17:54.801745 DATLAT Default: 0xa
942 22:17:54.801832 0, 0xFFFF, sum = 0
943 22:17:54.804999 1, 0xFFFF, sum = 0
944 22:17:54.805086 2, 0xFFFF, sum = 0
945 22:17:54.808822 3, 0xFFFF, sum = 0
946 22:17:54.812025 4, 0xFFFF, sum = 0
947 22:17:54.812112 5, 0xFFFF, sum = 0
948 22:17:54.815119 6, 0xFFFF, sum = 0
949 22:17:54.815206 7, 0xFFFF, sum = 0
950 22:17:54.818331 8, 0xFFFF, sum = 0
951 22:17:54.818420 9, 0x0, sum = 1
952 22:17:54.818489 10, 0x0, sum = 2
953 22:17:54.821918 11, 0x0, sum = 3
954 22:17:54.822004 12, 0x0, sum = 4
955 22:17:54.824999 best_step = 10
956 22:17:54.825084
957 22:17:54.825151 ==
958 22:17:54.828757 Dram Type= 6, Freq= 0, CH_0, rank 0
959 22:17:54.831953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 22:17:54.832044 ==
961 22:17:54.835156 RX Vref Scan: 1
962 22:17:54.835241
963 22:17:54.835308 Set Vref Range= 32 -> 127
964 22:17:54.838863
965 22:17:54.838947 RX Vref 32 -> 127, step: 1
966 22:17:54.839014
967 22:17:54.841730 RX Delay -111 -> 252, step: 8
968 22:17:54.841815
969 22:17:54.845323 Set Vref, RX VrefLevel [Byte0]: 32
970 22:17:54.848289 [Byte1]: 32
971 22:17:54.848375
972 22:17:54.852082 Set Vref, RX VrefLevel [Byte0]: 33
973 22:17:54.855444 [Byte1]: 33
974 22:17:54.859240
975 22:17:54.859325 Set Vref, RX VrefLevel [Byte0]: 34
976 22:17:54.862431 [Byte1]: 34
977 22:17:54.866976
978 22:17:54.867061 Set Vref, RX VrefLevel [Byte0]: 35
979 22:17:54.869972 [Byte1]: 35
980 22:17:54.874267
981 22:17:54.874350 Set Vref, RX VrefLevel [Byte0]: 36
982 22:17:54.878117 [Byte1]: 36
983 22:17:54.881856
984 22:17:54.881940 Set Vref, RX VrefLevel [Byte0]: 37
985 22:17:54.885908 [Byte1]: 37
986 22:17:54.889829
987 22:17:54.889930 Set Vref, RX VrefLevel [Byte0]: 38
988 22:17:54.893117 [Byte1]: 38
989 22:17:54.897206
990 22:17:54.897291 Set Vref, RX VrefLevel [Byte0]: 39
991 22:17:54.900815 [Byte1]: 39
992 22:17:54.905071
993 22:17:54.905160 Set Vref, RX VrefLevel [Byte0]: 40
994 22:17:54.908716 [Byte1]: 40
995 22:17:54.912531
996 22:17:54.912632 Set Vref, RX VrefLevel [Byte0]: 41
997 22:17:54.916404 [Byte1]: 41
998 22:17:54.920631
999 22:17:54.920718 Set Vref, RX VrefLevel [Byte0]: 42
1000 22:17:54.923741 [Byte1]: 42
1001 22:17:54.928168
1002 22:17:54.928297 Set Vref, RX VrefLevel [Byte0]: 43
1003 22:17:54.931076 [Byte1]: 43
1004 22:17:54.935519
1005 22:17:54.935603 Set Vref, RX VrefLevel [Byte0]: 44
1006 22:17:54.938795 [Byte1]: 44
1007 22:17:54.943092
1008 22:17:54.946819 Set Vref, RX VrefLevel [Byte0]: 45
1009 22:17:54.946914 [Byte1]: 45
1010 22:17:54.951363
1011 22:17:54.951445 Set Vref, RX VrefLevel [Byte0]: 46
1012 22:17:54.954865 [Byte1]: 46
1013 22:17:54.959013
1014 22:17:54.959110 Set Vref, RX VrefLevel [Byte0]: 47
1015 22:17:54.962303 [Byte1]: 47
1016 22:17:54.966066
1017 22:17:54.969935 Set Vref, RX VrefLevel [Byte0]: 48
1018 22:17:54.970023 [Byte1]: 48
1019 22:17:54.974200
1020 22:17:54.974280 Set Vref, RX VrefLevel [Byte0]: 49
1021 22:17:54.977517 [Byte1]: 49
1022 22:17:54.981898
1023 22:17:54.981975 Set Vref, RX VrefLevel [Byte0]: 50
1024 22:17:54.985143 [Byte1]: 50
1025 22:17:54.989006
1026 22:17:54.989083 Set Vref, RX VrefLevel [Byte0]: 51
1027 22:17:54.992791 [Byte1]: 51
1028 22:17:54.996549
1029 22:17:54.996621 Set Vref, RX VrefLevel [Byte0]: 52
1030 22:17:55.000437 [Byte1]: 52
1031 22:17:55.004631
1032 22:17:55.004746 Set Vref, RX VrefLevel [Byte0]: 53
1033 22:17:55.008151 [Byte1]: 53
1034 22:17:55.011894
1035 22:17:55.011980 Set Vref, RX VrefLevel [Byte0]: 54
1036 22:17:55.015567 [Byte1]: 54
1037 22:17:55.019941
1038 22:17:55.020026 Set Vref, RX VrefLevel [Byte0]: 55
1039 22:17:55.023255 [Byte1]: 55
1040 22:17:55.027618
1041 22:17:55.027697 Set Vref, RX VrefLevel [Byte0]: 56
1042 22:17:55.030609 [Byte1]: 56
1043 22:17:55.034922
1044 22:17:55.035008 Set Vref, RX VrefLevel [Byte0]: 57
1045 22:17:55.038367 [Byte1]: 57
1046 22:17:55.042621
1047 22:17:55.045673 Set Vref, RX VrefLevel [Byte0]: 58
1048 22:17:55.045757 [Byte1]: 58
1049 22:17:55.050037
1050 22:17:55.050130 Set Vref, RX VrefLevel [Byte0]: 59
1051 22:17:55.053756 [Byte1]: 59
1052 22:17:55.057819
1053 22:17:55.057898 Set Vref, RX VrefLevel [Byte0]: 60
1054 22:17:55.061250 [Byte1]: 60
1055 22:17:55.065328
1056 22:17:55.065406 Set Vref, RX VrefLevel [Byte0]: 61
1057 22:17:55.068954 [Byte1]: 61
1058 22:17:55.073118
1059 22:17:55.073211 Set Vref, RX VrefLevel [Byte0]: 62
1060 22:17:55.079482 [Byte1]: 62
1061 22:17:55.079597
1062 22:17:55.083319 Set Vref, RX VrefLevel [Byte0]: 63
1063 22:17:55.086428 [Byte1]: 63
1064 22:17:55.086504
1065 22:17:55.089564 Set Vref, RX VrefLevel [Byte0]: 64
1066 22:17:55.093385 [Byte1]: 64
1067 22:17:55.093463
1068 22:17:55.096527 Set Vref, RX VrefLevel [Byte0]: 65
1069 22:17:55.099691 [Byte1]: 65
1070 22:17:55.104075
1071 22:17:55.104153 Set Vref, RX VrefLevel [Byte0]: 66
1072 22:17:55.107208 [Byte1]: 66
1073 22:17:55.111629
1074 22:17:55.111724 Set Vref, RX VrefLevel [Byte0]: 67
1075 22:17:55.114526 [Byte1]: 67
1076 22:17:55.119361
1077 22:17:55.119454 Set Vref, RX VrefLevel [Byte0]: 68
1078 22:17:55.122404 [Byte1]: 68
1079 22:17:55.126773
1080 22:17:55.126883 Set Vref, RX VrefLevel [Byte0]: 69
1081 22:17:55.129924 [Byte1]: 69
1082 22:17:55.134494
1083 22:17:55.134573 Set Vref, RX VrefLevel [Byte0]: 70
1084 22:17:55.137690 [Byte1]: 70
1085 22:17:55.141826
1086 22:17:55.141908 Set Vref, RX VrefLevel [Byte0]: 71
1087 22:17:55.145149 [Byte1]: 71
1088 22:17:55.149698
1089 22:17:55.149809 Set Vref, RX VrefLevel [Byte0]: 72
1090 22:17:55.152820 [Byte1]: 72
1091 22:17:55.157250
1092 22:17:55.157345 Set Vref, RX VrefLevel [Byte0]: 73
1093 22:17:55.160926 [Byte1]: 73
1094 22:17:55.164682
1095 22:17:55.164760 Set Vref, RX VrefLevel [Byte0]: 74
1096 22:17:55.168375 [Byte1]: 74
1097 22:17:55.172563
1098 22:17:55.172651 Set Vref, RX VrefLevel [Byte0]: 75
1099 22:17:55.176026 [Byte1]: 75
1100 22:17:55.180347
1101 22:17:55.180427 Set Vref, RX VrefLevel [Byte0]: 76
1102 22:17:55.183780 [Byte1]: 76
1103 22:17:55.188172
1104 22:17:55.188266 Set Vref, RX VrefLevel [Byte0]: 77
1105 22:17:55.191307 [Byte1]: 77
1106 22:17:55.195728
1107 22:17:55.195807 Set Vref, RX VrefLevel [Byte0]: 78
1108 22:17:55.198900 [Byte1]: 78
1109 22:17:55.203492
1110 22:17:55.203569 Final RX Vref Byte 0 = 62 to rank0
1111 22:17:55.206902 Final RX Vref Byte 1 = 59 to rank0
1112 22:17:55.209975 Final RX Vref Byte 0 = 62 to rank1
1113 22:17:55.213142 Final RX Vref Byte 1 = 59 to rank1==
1114 22:17:55.216302 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 22:17:55.222950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 22:17:55.223035 ==
1117 22:17:55.223102 DQS Delay:
1118 22:17:55.223192 DQS0 = 0, DQS1 = 0
1119 22:17:55.226734 DQM Delay:
1120 22:17:55.226851 DQM0 = 82, DQM1 = 67
1121 22:17:55.229762 DQ Delay:
1122 22:17:55.233026 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1123 22:17:55.236334 DQ4 =80, DQ5 =72, DQ6 =88, DQ7 =92
1124 22:17:55.239508 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1125 22:17:55.242736 DQ12 =76, DQ13 =68, DQ14 =76, DQ15 =76
1126 22:17:55.242845
1127 22:17:55.242913
1128 22:17:55.249496 [DQSOSCAuto] RK0, (LSB)MR18= 0x2625, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1129 22:17:55.252756 CH0 RK0: MR19=606, MR18=2625
1130 22:17:55.259810 CH0_RK0: MR19=0x606, MR18=0x2625, DQSOSC=400, MR23=63, INC=92, DEC=61
1131 22:17:55.259895
1132 22:17:55.263018 ----->DramcWriteLeveling(PI) begin...
1133 22:17:55.263094 ==
1134 22:17:55.265946 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 22:17:55.269295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 22:17:55.269371 ==
1137 22:17:55.272577 Write leveling (Byte 0): 32 => 32
1138 22:17:55.276377 Write leveling (Byte 1): 28 => 28
1139 22:17:55.279558 DramcWriteLeveling(PI) end<-----
1140 22:17:55.279654
1141 22:17:55.279721 ==
1142 22:17:55.282542 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 22:17:55.286181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 22:17:55.286310 ==
1145 22:17:55.289212 [Gating] SW mode calibration
1146 22:17:55.295889 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 22:17:55.302541 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 22:17:55.305755 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 22:17:55.312414 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 22:17:55.315611 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 22:17:55.319139 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 22:17:55.325950 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 22:17:55.329047 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 22:17:55.332669 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 22:17:55.338939 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 22:17:55.342314 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 22:17:55.345639 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 22:17:55.348921 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:17:55.355277 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:17:55.359125 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:17:55.362268 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:17:55.368842 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:17:55.371883 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:17:55.416184 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:17:55.416483 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 22:17:55.416584 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1167 22:17:55.416654 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:17:55.416728 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:17:55.416817 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:17:55.417067 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:17:55.417175 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:17:55.417277 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:17:55.417380 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:17:55.460415 0 9 8 | B1->B0 | 2424 2f2f | 1 0 | (1 1) (0 0)
1175 22:17:55.460737 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1176 22:17:55.460819 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 22:17:55.460885 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 22:17:55.460960 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 22:17:55.461024 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 22:17:55.461095 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 22:17:55.461338 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1182 22:17:55.461403 0 10 8 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (0 0)
1183 22:17:55.461490 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1184 22:17:55.473770 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:17:55.474039 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:17:55.477058 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:17:55.477143 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:17:55.483550 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:17:55.486785 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1190 22:17:55.490000 0 11 8 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
1191 22:17:55.496884 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 22:17:55.500394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 22:17:55.503497 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 22:17:55.510139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 22:17:55.513338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 22:17:55.516524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 22:17:55.523186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 22:17:55.526948 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 22:17:55.530763 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 22:17:55.533993 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 22:17:55.540937 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 22:17:55.544684 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 22:17:55.547812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 22:17:55.550910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 22:17:55.558242 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 22:17:55.562013 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:17:55.565262 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:17:55.571691 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:17:55.574842 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:17:55.578064 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:17:55.584919 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:17:55.588120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:17:55.591363 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 22:17:55.598550 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 22:17:55.598654 Total UI for P1: 0, mck2ui 16
1216 22:17:55.601662 best dqsien dly found for B0: ( 0, 14, 4)
1217 22:17:55.604718 Total UI for P1: 0, mck2ui 16
1218 22:17:55.608439 best dqsien dly found for B1: ( 0, 14, 6)
1219 22:17:55.614684 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1220 22:17:55.618422 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1221 22:17:55.618564
1222 22:17:55.621158 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1223 22:17:55.624964 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 22:17:55.628063 [Gating] SW calibration Done
1225 22:17:55.628178 ==
1226 22:17:55.631329 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 22:17:55.634658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1228 22:17:55.634765 ==
1229 22:17:55.634865 RX Vref Scan: 0
1230 22:17:55.637905
1231 22:17:55.637997 RX Vref 0 -> 0, step: 1
1232 22:17:55.638083
1233 22:17:55.640993 RX Delay -130 -> 252, step: 16
1234 22:17:55.644832 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1235 22:17:55.648132 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1236 22:17:55.654637 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1237 22:17:55.657691 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1238 22:17:55.661294 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1239 22:17:55.664391 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1240 22:17:55.667789 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1241 22:17:55.674604 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1242 22:17:55.677643 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1243 22:17:55.681128 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1244 22:17:55.684192 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1245 22:17:55.690747 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1246 22:17:55.694507 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1247 22:17:55.697634 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1248 22:17:55.700764 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1249 22:17:55.703965 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1250 22:17:55.704099 ==
1251 22:17:55.707906 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 22:17:55.713841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 22:17:55.713954 ==
1254 22:17:55.714107 DQS Delay:
1255 22:17:55.717461 DQS0 = 0, DQS1 = 0
1256 22:17:55.717566 DQM Delay:
1257 22:17:55.720840 DQM0 = 77, DQM1 = 69
1258 22:17:55.720933 DQ Delay:
1259 22:17:55.723891 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1260 22:17:55.727205 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1261 22:17:55.730938 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1262 22:17:55.733938 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1263 22:17:55.734029
1264 22:17:55.734097
1265 22:17:55.734169 ==
1266 22:17:55.737230 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 22:17:55.740570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 22:17:55.740674 ==
1269 22:17:55.740779
1270 22:17:55.740869
1271 22:17:55.743813 TX Vref Scan disable
1272 22:17:55.746989 == TX Byte 0 ==
1273 22:17:55.750095 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1274 22:17:55.754070 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1275 22:17:55.757216 == TX Byte 1 ==
1276 22:17:55.760394 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1277 22:17:55.763589 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1278 22:17:55.763682 ==
1279 22:17:55.767276 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 22:17:55.773228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 22:17:55.773360 ==
1282 22:17:55.785508 TX Vref=22, minBit 0, minWin=27, winSum=436
1283 22:17:55.788533 TX Vref=24, minBit 13, minWin=26, winSum=438
1284 22:17:55.792167 TX Vref=26, minBit 1, minWin=27, winSum=440
1285 22:17:55.795647 TX Vref=28, minBit 1, minWin=27, winSum=443
1286 22:17:55.798691 TX Vref=30, minBit 10, minWin=27, winSum=447
1287 22:17:55.805618 TX Vref=32, minBit 10, minWin=27, winSum=447
1288 22:17:55.808783 [TxChooseVref] Worse bit 10, Min win 27, Win sum 447, Final Vref 30
1289 22:17:55.808888
1290 22:17:55.812074 Final TX Range 1 Vref 30
1291 22:17:55.812170
1292 22:17:55.812238 ==
1293 22:17:55.815244 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 22:17:55.818479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 22:17:55.821852 ==
1296 22:17:55.821949
1297 22:17:55.822017
1298 22:17:55.822084 TX Vref Scan disable
1299 22:17:55.825567 == TX Byte 0 ==
1300 22:17:55.829086 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1301 22:17:55.835573 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1302 22:17:55.835662 == TX Byte 1 ==
1303 22:17:55.839239 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1304 22:17:55.845654 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1305 22:17:55.845770
1306 22:17:55.845869 [DATLAT]
1307 22:17:55.845961 Freq=800, CH0 RK1
1308 22:17:55.846052
1309 22:17:55.848810 DATLAT Default: 0xa
1310 22:17:55.848915 0, 0xFFFF, sum = 0
1311 22:17:55.852010 1, 0xFFFF, sum = 0
1312 22:17:55.855627 2, 0xFFFF, sum = 0
1313 22:17:55.855738 3, 0xFFFF, sum = 0
1314 22:17:55.858779 4, 0xFFFF, sum = 0
1315 22:17:55.858864 5, 0xFFFF, sum = 0
1316 22:17:55.862049 6, 0xFFFF, sum = 0
1317 22:17:55.862124 7, 0xFFFF, sum = 0
1318 22:17:55.865825 8, 0xFFFF, sum = 0
1319 22:17:55.865944 9, 0x0, sum = 1
1320 22:17:55.868766 10, 0x0, sum = 2
1321 22:17:55.868889 11, 0x0, sum = 3
1322 22:17:55.868989 12, 0x0, sum = 4
1323 22:17:55.871873 best_step = 10
1324 22:17:55.871955
1325 22:17:55.872020 ==
1326 22:17:55.875455 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 22:17:55.878486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 22:17:55.878592 ==
1329 22:17:55.882204 RX Vref Scan: 0
1330 22:17:55.882289
1331 22:17:55.882388 RX Vref 0 -> 0, step: 1
1332 22:17:55.885498
1333 22:17:55.885604 RX Delay -111 -> 252, step: 8
1334 22:17:55.892778 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1335 22:17:55.895864 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1336 22:17:55.899560 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1337 22:17:55.902662 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1338 22:17:55.905763 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1339 22:17:55.912221 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1340 22:17:55.915388 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1341 22:17:55.919229 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1342 22:17:55.922372 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1343 22:17:55.925637 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1344 22:17:55.932468 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1345 22:17:55.935306 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1346 22:17:55.938952 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1347 22:17:55.941957 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1348 22:17:55.949101 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1349 22:17:55.952484 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1350 22:17:55.952604 ==
1351 22:17:55.955564 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 22:17:55.958470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 22:17:55.958588 ==
1354 22:17:55.962289 DQS Delay:
1355 22:17:55.962391 DQS0 = 0, DQS1 = 0
1356 22:17:55.962488 DQM Delay:
1357 22:17:55.965704 DQM0 = 79, DQM1 = 71
1358 22:17:55.965808 DQ Delay:
1359 22:17:55.968695 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1360 22:17:55.971928 DQ4 =76, DQ5 =64, DQ6 =92, DQ7 =88
1361 22:17:55.975460 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1362 22:17:55.978666 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1363 22:17:55.978778
1364 22:17:55.978872
1365 22:17:55.988437 [DQSOSCAuto] RK1, (LSB)MR18= 0x441f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1366 22:17:55.988525 CH0 RK1: MR19=606, MR18=441F
1367 22:17:55.995285 CH0_RK1: MR19=0x606, MR18=0x441F, DQSOSC=392, MR23=63, INC=96, DEC=64
1368 22:17:55.998541 [RxdqsGatingPostProcess] freq 800
1369 22:17:56.005114 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1370 22:17:56.007979 Pre-setting of DQS Precalculation
1371 22:17:56.011582 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1372 22:17:56.011661 ==
1373 22:17:56.014745 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 22:17:56.021854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1375 22:17:56.021994 ==
1376 22:17:56.025121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1377 22:17:56.031354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1378 22:17:56.040518 [CA 0] Center 36 (6~66) winsize 61
1379 22:17:56.044215 [CA 1] Center 36 (6~67) winsize 62
1380 22:17:56.047298 [CA 2] Center 34 (4~64) winsize 61
1381 22:17:56.050542 [CA 3] Center 34 (4~64) winsize 61
1382 22:17:56.053760 [CA 4] Center 35 (5~65) winsize 61
1383 22:17:56.057150 [CA 5] Center 33 (3~64) winsize 62
1384 22:17:56.057256
1385 22:17:56.060842 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1386 22:17:56.060933
1387 22:17:56.064045 [CATrainingPosCal] consider 1 rank data
1388 22:17:56.067115 u2DelayCellTimex100 = 270/100 ps
1389 22:17:56.070366 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1390 22:17:56.077553 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1391 22:17:56.080095 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1392 22:17:56.083488 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1393 22:17:56.087254 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1394 22:17:56.090534 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 22:17:56.090644
1396 22:17:56.093816 CA PerBit enable=1, Macro0, CA PI delay=33
1397 22:17:56.093921
1398 22:17:56.096919 [CBTSetCACLKResult] CA Dly = 33
1399 22:17:56.100203 CS Dly: 5 (0~36)
1400 22:17:56.100323 ==
1401 22:17:56.103275 Dram Type= 6, Freq= 0, CH_1, rank 1
1402 22:17:56.106863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 22:17:56.106961 ==
1404 22:17:56.113458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1405 22:17:56.116937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1406 22:17:56.127313 [CA 0] Center 36 (6~66) winsize 61
1407 22:17:56.130429 [CA 1] Center 36 (6~67) winsize 62
1408 22:17:56.133526 [CA 2] Center 34 (4~65) winsize 62
1409 22:17:56.136762 [CA 3] Center 34 (4~64) winsize 61
1410 22:17:56.140512 [CA 4] Center 34 (4~65) winsize 62
1411 22:17:56.143477 [CA 5] Center 33 (3~64) winsize 62
1412 22:17:56.143592
1413 22:17:56.146523 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1414 22:17:56.146639
1415 22:17:56.150157 [CATrainingPosCal] consider 2 rank data
1416 22:17:56.153786 u2DelayCellTimex100 = 270/100 ps
1417 22:17:56.156931 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1418 22:17:56.160205 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1419 22:17:56.167134 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1420 22:17:56.170300 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1421 22:17:56.173584 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1422 22:17:56.176742 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 22:17:56.176826
1424 22:17:56.179796 CA PerBit enable=1, Macro0, CA PI delay=33
1425 22:17:56.179905
1426 22:17:56.183450 [CBTSetCACLKResult] CA Dly = 33
1427 22:17:56.183551 CS Dly: 6 (0~38)
1428 22:17:56.186684
1429 22:17:56.190670 ----->DramcWriteLeveling(PI) begin...
1430 22:17:56.190756 ==
1431 22:17:56.190824 Dram Type= 6, Freq= 0, CH_1, rank 0
1432 22:17:56.197676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1433 22:17:56.197765 ==
1434 22:17:56.201436 Write leveling (Byte 0): 28 => 28
1435 22:17:56.201521 Write leveling (Byte 1): 33 => 33
1436 22:17:56.204626 DramcWriteLeveling(PI) end<-----
1437 22:17:56.204734
1438 22:17:56.204832 ==
1439 22:17:56.208240 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 22:17:56.211972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 22:17:56.215520 ==
1442 22:17:56.215605 [Gating] SW mode calibration
1443 22:17:56.222865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1444 22:17:56.229612 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1445 22:17:56.232874 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1446 22:17:56.236065 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1447 22:17:56.243098 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1448 22:17:56.246224 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 22:17:56.249321 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 22:17:56.256010 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 22:17:56.258974 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 22:17:56.262812 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 22:17:56.269130 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 22:17:56.272814 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 22:17:56.276044 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 22:17:56.282232 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:17:56.285991 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:17:56.289051 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:17:56.295936 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:17:56.299163 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:17:56.302360 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:17:56.309064 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1463 22:17:56.312184 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1464 22:17:56.316064 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:17:56.319158 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:17:56.325861 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:17:56.328784 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:17:56.332490 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:17:56.338840 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:17:56.342089 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1471 22:17:56.345247 0 9 8 | B1->B0 | 2626 2828 | 0 0 | (0 0) (1 1)
1472 22:17:56.352385 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 22:17:56.355542 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 22:17:56.358960 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 22:17:56.365544 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 22:17:56.368838 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 22:17:56.372061 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 22:17:56.379037 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1479 22:17:56.381799 0 10 8 | B1->B0 | 2b2b 2b2b | 1 0 | (1 1) (1 1)
1480 22:17:56.385529 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:17:56.392089 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:17:56.395255 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:17:56.398475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:17:56.405389 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:17:56.408613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:17:56.411886 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:17:56.418398 0 11 8 | B1->B0 | 3131 3333 | 1 0 | (0 0) (0 0)
1488 22:17:56.421575 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 22:17:56.424841 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 22:17:56.431537 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 22:17:56.434989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 22:17:56.438048 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 22:17:56.444948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 22:17:56.447891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 22:17:56.451264 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1496 22:17:56.458181 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 22:17:56.461233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 22:17:56.464858 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 22:17:56.471455 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 22:17:56.474542 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 22:17:56.477727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 22:17:56.484346 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 22:17:56.488109 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 22:17:56.491357 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:17:56.497987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:17:56.501128 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:17:56.504195 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:17:56.511455 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:17:56.514722 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:17:56.517869 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1511 22:17:56.524299 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1512 22:17:56.524395 Total UI for P1: 0, mck2ui 16
1513 22:17:56.527768 best dqsien dly found for B0: ( 0, 14, 4)
1514 22:17:56.534742 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 22:17:56.537749 Total UI for P1: 0, mck2ui 16
1516 22:17:56.541233 best dqsien dly found for B1: ( 0, 14, 8)
1517 22:17:56.544667 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 22:17:56.547391 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1519 22:17:56.547481
1520 22:17:56.551052 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 22:17:56.554233 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1522 22:17:56.557491 [Gating] SW calibration Done
1523 22:17:56.557576 ==
1524 22:17:56.560813 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 22:17:56.564070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 22:17:56.564159 ==
1527 22:17:56.567724 RX Vref Scan: 0
1528 22:17:56.567807
1529 22:17:56.570727 RX Vref 0 -> 0, step: 1
1530 22:17:56.570804
1531 22:17:56.570875 RX Delay -130 -> 252, step: 16
1532 22:17:56.577336 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1533 22:17:56.580985 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1534 22:17:56.584211 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1535 22:17:56.587374 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1536 22:17:56.590528 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1537 22:17:56.597542 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1538 22:17:56.600834 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1539 22:17:56.603925 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1540 22:17:56.607163 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1541 22:17:56.610816 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1542 22:17:56.617579 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1543 22:17:56.620532 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1544 22:17:56.623716 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1545 22:17:56.626907 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1546 22:17:56.633370 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1547 22:17:56.636649 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1548 22:17:56.636757 ==
1549 22:17:56.640499 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 22:17:56.643923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 22:17:56.644045 ==
1552 22:17:56.646687 DQS Delay:
1553 22:17:56.646812 DQS0 = 0, DQS1 = 0
1554 22:17:56.646919 DQM Delay:
1555 22:17:56.650450 DQM0 = 80, DQM1 = 71
1556 22:17:56.650558 DQ Delay:
1557 22:17:56.653382 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1558 22:17:56.657079 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1559 22:17:56.660012 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1560 22:17:56.663163 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1561 22:17:56.663243
1562 22:17:56.663309
1563 22:17:56.663369 ==
1564 22:17:56.666942 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 22:17:56.673027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 22:17:56.673118 ==
1567 22:17:56.673206
1568 22:17:56.673306
1569 22:17:56.673402 TX Vref Scan disable
1570 22:17:56.676745 == TX Byte 0 ==
1571 22:17:56.679705 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1572 22:17:56.686809 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1573 22:17:56.686905 == TX Byte 1 ==
1574 22:17:56.689993 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1575 22:17:56.696334 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1576 22:17:56.696420 ==
1577 22:17:56.700097 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 22:17:56.703210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 22:17:56.703324 ==
1580 22:17:56.715924 TX Vref=22, minBit 1, minWin=26, winSum=435
1581 22:17:56.719238 TX Vref=24, minBit 1, minWin=27, winSum=440
1582 22:17:56.723000 TX Vref=26, minBit 1, minWin=27, winSum=440
1583 22:17:56.726122 TX Vref=28, minBit 1, minWin=27, winSum=444
1584 22:17:56.729413 TX Vref=30, minBit 5, minWin=27, winSum=445
1585 22:17:56.735922 TX Vref=32, minBit 0, minWin=27, winSum=445
1586 22:17:56.738960 [TxChooseVref] Worse bit 5, Min win 27, Win sum 445, Final Vref 30
1587 22:17:56.739048
1588 22:17:56.742392 Final TX Range 1 Vref 30
1589 22:17:56.742503
1590 22:17:56.742605 ==
1591 22:17:56.745596 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 22:17:56.748868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 22:17:56.752625 ==
1594 22:17:56.752710
1595 22:17:56.752776
1596 22:17:56.752845 TX Vref Scan disable
1597 22:17:56.756185 == TX Byte 0 ==
1598 22:17:56.759259 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 22:17:56.766002 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 22:17:56.766092 == TX Byte 1 ==
1601 22:17:56.769933 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1602 22:17:56.773247 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1603 22:17:56.773360
1604 22:17:56.776379 [DATLAT]
1605 22:17:56.776462 Freq=800, CH1 RK0
1606 22:17:56.776529
1607 22:17:56.779368 DATLAT Default: 0xa
1608 22:17:56.779452 0, 0xFFFF, sum = 0
1609 22:17:56.783039 1, 0xFFFF, sum = 0
1610 22:17:56.783124 2, 0xFFFF, sum = 0
1611 22:17:56.786090 3, 0xFFFF, sum = 0
1612 22:17:56.786175 4, 0xFFFF, sum = 0
1613 22:17:56.789696 5, 0xFFFF, sum = 0
1614 22:17:56.789812 6, 0xFFFF, sum = 0
1615 22:17:56.792632 7, 0xFFFF, sum = 0
1616 22:17:56.796349 8, 0xFFFF, sum = 0
1617 22:17:56.796436 9, 0x0, sum = 1
1618 22:17:56.796504 10, 0x0, sum = 2
1619 22:17:56.799044 11, 0x0, sum = 3
1620 22:17:56.799129 12, 0x0, sum = 4
1621 22:17:56.802792 best_step = 10
1622 22:17:56.802893
1623 22:17:56.802959 ==
1624 22:17:56.806325 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 22:17:56.809307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 22:17:56.809392 ==
1627 22:17:56.812809 RX Vref Scan: 1
1628 22:17:56.812922
1629 22:17:56.813017 Set Vref Range= 32 -> 127
1630 22:17:56.815886
1631 22:17:56.815987 RX Vref 32 -> 127, step: 1
1632 22:17:56.816055
1633 22:17:56.819240 RX Delay -111 -> 252, step: 8
1634 22:17:56.819325
1635 22:17:56.822457 Set Vref, RX VrefLevel [Byte0]: 32
1636 22:17:56.825571 [Byte1]: 32
1637 22:17:56.825656
1638 22:17:56.829360 Set Vref, RX VrefLevel [Byte0]: 33
1639 22:17:56.832626 [Byte1]: 33
1640 22:17:56.836405
1641 22:17:56.836490 Set Vref, RX VrefLevel [Byte0]: 34
1642 22:17:56.839657 [Byte1]: 34
1643 22:17:56.844003
1644 22:17:56.844087 Set Vref, RX VrefLevel [Byte0]: 35
1645 22:17:56.847665 [Byte1]: 35
1646 22:17:56.852143
1647 22:17:56.852244 Set Vref, RX VrefLevel [Byte0]: 36
1648 22:17:56.855233 [Byte1]: 36
1649 22:17:56.859647
1650 22:17:56.859732 Set Vref, RX VrefLevel [Byte0]: 37
1651 22:17:56.862691 [Byte1]: 37
1652 22:17:56.867178
1653 22:17:56.867262 Set Vref, RX VrefLevel [Byte0]: 38
1654 22:17:56.870692 [Byte1]: 38
1655 22:17:56.875209
1656 22:17:56.875318 Set Vref, RX VrefLevel [Byte0]: 39
1657 22:17:56.878160 [Byte1]: 39
1658 22:17:56.882756
1659 22:17:56.882848 Set Vref, RX VrefLevel [Byte0]: 40
1660 22:17:56.885758 [Byte1]: 40
1661 22:17:56.890267
1662 22:17:56.890349 Set Vref, RX VrefLevel [Byte0]: 41
1663 22:17:56.893052 [Byte1]: 41
1664 22:17:56.897851
1665 22:17:56.897934 Set Vref, RX VrefLevel [Byte0]: 42
1666 22:17:56.900821 [Byte1]: 42
1667 22:17:56.905538
1668 22:17:56.905626 Set Vref, RX VrefLevel [Byte0]: 43
1669 22:17:56.908846 [Byte1]: 43
1670 22:17:56.912814
1671 22:17:56.912910 Set Vref, RX VrefLevel [Byte0]: 44
1672 22:17:56.915990 [Byte1]: 44
1673 22:17:56.920407
1674 22:17:56.920513 Set Vref, RX VrefLevel [Byte0]: 45
1675 22:17:56.924247 [Byte1]: 45
1676 22:17:56.928094
1677 22:17:56.928170 Set Vref, RX VrefLevel [Byte0]: 46
1678 22:17:56.931346 [Byte1]: 46
1679 22:17:56.936017
1680 22:17:56.936133 Set Vref, RX VrefLevel [Byte0]: 47
1681 22:17:56.939223 [Byte1]: 47
1682 22:17:56.943724
1683 22:17:56.943801 Set Vref, RX VrefLevel [Byte0]: 48
1684 22:17:56.946809 [Byte1]: 48
1685 22:17:56.951109
1686 22:17:56.951180 Set Vref, RX VrefLevel [Byte0]: 49
1687 22:17:56.954796 [Byte1]: 49
1688 22:17:56.958667
1689 22:17:56.958749 Set Vref, RX VrefLevel [Byte0]: 50
1690 22:17:56.962563 [Byte1]: 50
1691 22:17:56.966275
1692 22:17:56.966357 Set Vref, RX VrefLevel [Byte0]: 51
1693 22:17:56.970139 [Byte1]: 51
1694 22:17:56.974535
1695 22:17:56.974652 Set Vref, RX VrefLevel [Byte0]: 52
1696 22:17:56.977585 [Byte1]: 52
1697 22:17:56.981723
1698 22:17:56.981829 Set Vref, RX VrefLevel [Byte0]: 53
1699 22:17:56.984860 [Byte1]: 53
1700 22:17:56.989306
1701 22:17:56.989390 Set Vref, RX VrefLevel [Byte0]: 54
1702 22:17:56.992793 [Byte1]: 54
1703 22:17:56.996864
1704 22:17:56.996948 Set Vref, RX VrefLevel [Byte0]: 55
1705 22:17:57.000321 [Byte1]: 55
1706 22:17:57.004966
1707 22:17:57.005049 Set Vref, RX VrefLevel [Byte0]: 56
1708 22:17:57.007886 [Byte1]: 56
1709 22:17:57.012615
1710 22:17:57.012698 Set Vref, RX VrefLevel [Byte0]: 57
1711 22:17:57.015665 [Byte1]: 57
1712 22:17:57.019866
1713 22:17:57.019950 Set Vref, RX VrefLevel [Byte0]: 58
1714 22:17:57.023571 [Byte1]: 58
1715 22:17:57.027457
1716 22:17:57.027553 Set Vref, RX VrefLevel [Byte0]: 59
1717 22:17:57.030743 [Byte1]: 59
1718 22:17:57.035297
1719 22:17:57.035379 Set Vref, RX VrefLevel [Byte0]: 60
1720 22:17:57.038408 [Byte1]: 60
1721 22:17:57.042906
1722 22:17:57.043020 Set Vref, RX VrefLevel [Byte0]: 61
1723 22:17:57.046100 [Byte1]: 61
1724 22:17:57.050588
1725 22:17:57.050671 Set Vref, RX VrefLevel [Byte0]: 62
1726 22:17:57.053866 [Byte1]: 62
1727 22:17:57.058492
1728 22:17:57.058576 Set Vref, RX VrefLevel [Byte0]: 63
1729 22:17:57.061680 [Byte1]: 63
1730 22:17:57.065634
1731 22:17:57.065719 Set Vref, RX VrefLevel [Byte0]: 64
1732 22:17:57.069452 [Byte1]: 64
1733 22:17:57.073822
1734 22:17:57.073905 Set Vref, RX VrefLevel [Byte0]: 65
1735 22:17:57.076980 [Byte1]: 65
1736 22:17:57.081529
1737 22:17:57.081612 Set Vref, RX VrefLevel [Byte0]: 66
1738 22:17:57.084505 [Byte1]: 66
1739 22:17:57.088817
1740 22:17:57.088923 Set Vref, RX VrefLevel [Byte0]: 67
1741 22:17:57.092025 [Byte1]: 67
1742 22:17:57.096571
1743 22:17:57.096679 Set Vref, RX VrefLevel [Byte0]: 68
1744 22:17:57.099597 [Byte1]: 68
1745 22:17:57.104233
1746 22:17:57.104338 Set Vref, RX VrefLevel [Byte0]: 69
1747 22:17:57.107492 [Byte1]: 69
1748 22:17:57.112038
1749 22:17:57.112143 Set Vref, RX VrefLevel [Byte0]: 70
1750 22:17:57.115050 [Byte1]: 70
1751 22:17:57.119277
1752 22:17:57.119361 Set Vref, RX VrefLevel [Byte0]: 71
1753 22:17:57.122761 [Byte1]: 71
1754 22:17:57.126966
1755 22:17:57.127047 Set Vref, RX VrefLevel [Byte0]: 72
1756 22:17:57.133830 [Byte1]: 72
1757 22:17:57.133935
1758 22:17:57.136993 Set Vref, RX VrefLevel [Byte0]: 73
1759 22:17:57.140202 [Byte1]: 73
1760 22:17:57.140284
1761 22:17:57.143406 Set Vref, RX VrefLevel [Byte0]: 74
1762 22:17:57.146561 [Byte1]: 74
1763 22:17:57.150428
1764 22:17:57.150539 Set Vref, RX VrefLevel [Byte0]: 75
1765 22:17:57.153478 [Byte1]: 75
1766 22:17:57.158048
1767 22:17:57.158156 Set Vref, RX VrefLevel [Byte0]: 76
1768 22:17:57.161205 [Byte1]: 76
1769 22:17:57.165525
1770 22:17:57.165682 Final RX Vref Byte 0 = 57 to rank0
1771 22:17:57.168419 Final RX Vref Byte 1 = 59 to rank0
1772 22:17:57.172240 Final RX Vref Byte 0 = 57 to rank1
1773 22:17:57.175276 Final RX Vref Byte 1 = 59 to rank1==
1774 22:17:57.178438 Dram Type= 6, Freq= 0, CH_1, rank 0
1775 22:17:57.185453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1776 22:17:57.185563 ==
1777 22:17:57.185657 DQS Delay:
1778 22:17:57.188708 DQS0 = 0, DQS1 = 0
1779 22:17:57.188809 DQM Delay:
1780 22:17:57.188901 DQM0 = 81, DQM1 = 71
1781 22:17:57.191943 DQ Delay:
1782 22:17:57.195386 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1783 22:17:57.198423 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1784 22:17:57.201650 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1785 22:17:57.204828 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1786 22:17:57.204905
1787 22:17:57.204972
1788 22:17:57.211472 [DQSOSCAuto] RK0, (LSB)MR18= 0x141e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1789 22:17:57.214956 CH1 RK0: MR19=606, MR18=141E
1790 22:17:57.221436 CH1_RK0: MR19=0x606, MR18=0x141E, DQSOSC=402, MR23=63, INC=91, DEC=60
1791 22:17:57.221550
1792 22:17:57.224482 ----->DramcWriteLeveling(PI) begin...
1793 22:17:57.224562 ==
1794 22:17:57.228066 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 22:17:57.231626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 22:17:57.231705 ==
1797 22:17:57.234534 Write leveling (Byte 0): 28 => 28
1798 22:17:57.238476 Write leveling (Byte 1): 30 => 30
1799 22:17:57.241607 DramcWriteLeveling(PI) end<-----
1800 22:17:57.241721
1801 22:17:57.241818 ==
1802 22:17:57.245012 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 22:17:57.248280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 22:17:57.248390 ==
1805 22:17:57.252166 [Gating] SW mode calibration
1806 22:17:57.257917 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1807 22:17:57.264329 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1808 22:17:57.267553 0 6 0 | B1->B0 | 2323 2322 | 0 1 | (1 1) (1 0)
1809 22:17:57.274287 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1810 22:17:57.277834 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:17:57.280953 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:17:57.287479 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:17:57.290681 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:17:57.294447 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:17:57.300649 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:17:57.303985 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 22:17:57.307313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:17:57.314387 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:17:57.317390 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:17:57.320713 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:17:57.327629 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:17:57.330586 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:17:57.334135 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:17:57.340773 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1825 22:17:57.343814 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1826 22:17:57.347761 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1827 22:17:57.354039 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:17:57.357298 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:17:57.360675 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:17:57.366964 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:17:57.370394 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:17:57.373547 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:17:57.376855 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1834 22:17:57.383556 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1835 22:17:57.386910 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 22:17:57.390556 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 22:17:57.396632 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 22:17:57.399743 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 22:17:57.403355 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 22:17:57.410218 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1841 22:17:57.413544 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
1842 22:17:57.416904 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 22:17:57.423556 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:17:57.426594 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 22:17:57.429952 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 22:17:57.436287 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:17:57.440083 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:17:57.443069 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1849 22:17:57.449766 0 11 4 | B1->B0 | 2727 3b3b | 0 0 | (0 0) (0 0)
1850 22:17:57.453622 0 11 8 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
1851 22:17:57.456315 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 22:17:57.462988 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 22:17:57.466235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 22:17:57.469479 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 22:17:57.475975 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 22:17:57.479838 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 22:17:57.483081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1858 22:17:57.489394 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1859 22:17:57.492845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:17:57.496397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:17:57.503236 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:17:57.506445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:17:57.509696 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:17:57.516391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 22:17:57.519762 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:17:57.522961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:17:57.529150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:17:57.532866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:17:57.536070 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:17:57.542681 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:17:57.546204 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:17:57.549306 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1873 22:17:57.552902 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1874 22:17:57.559452 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 22:17:57.562687 Total UI for P1: 0, mck2ui 16
1876 22:17:57.565884 best dqsien dly found for B0: ( 0, 14, 2)
1877 22:17:57.569155 Total UI for P1: 0, mck2ui 16
1878 22:17:57.572858 best dqsien dly found for B1: ( 0, 14, 6)
1879 22:17:57.576185 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1880 22:17:57.579360 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1881 22:17:57.579469
1882 22:17:57.582701 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1883 22:17:57.585922 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 22:17:57.589134 [Gating] SW calibration Done
1885 22:17:57.589240 ==
1886 22:17:57.592229 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 22:17:57.596063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 22:17:57.596170 ==
1889 22:17:57.599064 RX Vref Scan: 0
1890 22:17:57.599144
1891 22:17:57.599208 RX Vref 0 -> 0, step: 1
1892 22:17:57.602789
1893 22:17:57.602902 RX Delay -130 -> 252, step: 16
1894 22:17:57.608709 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1895 22:17:57.612665 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1896 22:17:57.615712 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1897 22:17:57.618684 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1898 22:17:57.622422 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1899 22:17:57.628888 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1900 22:17:57.632022 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1901 22:17:57.635769 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1902 22:17:57.638804 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1903 22:17:57.642044 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1904 22:17:57.648783 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1905 22:17:57.652210 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1906 22:17:57.655468 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1907 22:17:57.658904 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1908 22:17:57.661867 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1909 22:17:57.668743 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1910 22:17:57.668828 ==
1911 22:17:57.671981 Dram Type= 6, Freq= 0, CH_1, rank 1
1912 22:17:57.675097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1913 22:17:57.675207 ==
1914 22:17:57.675302 DQS Delay:
1915 22:17:57.679087 DQS0 = 0, DQS1 = 0
1916 22:17:57.679171 DQM Delay:
1917 22:17:57.681752 DQM0 = 78, DQM1 = 72
1918 22:17:57.681867 DQ Delay:
1919 22:17:57.685489 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1920 22:17:57.688742 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1921 22:17:57.691949 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1922 22:17:57.695201 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1923 22:17:57.695289
1924 22:17:57.695353
1925 22:17:57.695413 ==
1926 22:17:57.698270 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 22:17:57.701451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 22:17:57.704732 ==
1929 22:17:57.704841
1930 22:17:57.704932
1931 22:17:57.705024 TX Vref Scan disable
1932 22:17:57.708423 == TX Byte 0 ==
1933 22:17:57.711447 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1934 22:17:57.714951 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1935 22:17:57.718079 == TX Byte 1 ==
1936 22:17:57.721874 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1937 22:17:57.725053 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1938 22:17:57.728179 ==
1939 22:17:57.731943 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 22:17:57.735059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 22:17:57.735145 ==
1942 22:17:57.747401 TX Vref=22, minBit 6, minWin=27, winSum=449
1943 22:17:57.750642 TX Vref=24, minBit 1, minWin=27, winSum=448
1944 22:17:57.753753 TX Vref=26, minBit 1, minWin=27, winSum=454
1945 22:17:57.757311 TX Vref=28, minBit 1, minWin=27, winSum=456
1946 22:17:57.760176 TX Vref=30, minBit 0, minWin=28, winSum=460
1947 22:17:57.767253 TX Vref=32, minBit 1, minWin=27, winSum=458
1948 22:17:57.770096 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1949 22:17:57.770185
1950 22:17:57.773562 Final TX Range 1 Vref 30
1951 22:17:57.773673
1952 22:17:57.773793 ==
1953 22:17:57.776663 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 22:17:57.780260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 22:17:57.783797 ==
1956 22:17:57.783892
1957 22:17:57.783989
1958 22:17:57.784053 TX Vref Scan disable
1959 22:17:57.786904 == TX Byte 0 ==
1960 22:17:57.790708 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1961 22:17:57.796991 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1962 22:17:57.797076 == TX Byte 1 ==
1963 22:17:57.800250 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1964 22:17:57.807219 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1965 22:17:57.807306
1966 22:17:57.807374 [DATLAT]
1967 22:17:57.807438 Freq=800, CH1 RK1
1968 22:17:57.807498
1969 22:17:57.810261 DATLAT Default: 0xa
1970 22:17:57.810344 0, 0xFFFF, sum = 0
1971 22:17:57.813469 1, 0xFFFF, sum = 0
1972 22:17:57.813549 2, 0xFFFF, sum = 0
1973 22:17:57.817252 3, 0xFFFF, sum = 0
1974 22:17:57.820100 4, 0xFFFF, sum = 0
1975 22:17:57.820220 5, 0xFFFF, sum = 0
1976 22:17:57.823714 6, 0xFFFF, sum = 0
1977 22:17:57.823798 7, 0xFFFF, sum = 0
1978 22:17:57.826753 8, 0xFFFF, sum = 0
1979 22:17:57.826845 9, 0x0, sum = 1
1980 22:17:57.830406 10, 0x0, sum = 2
1981 22:17:57.830489 11, 0x0, sum = 3
1982 22:17:57.830557 12, 0x0, sum = 4
1983 22:17:57.833323 best_step = 10
1984 22:17:57.833402
1985 22:17:57.833468 ==
1986 22:17:57.837053 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 22:17:57.840152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 22:17:57.840230 ==
1989 22:17:57.843817 RX Vref Scan: 0
1990 22:17:57.843918
1991 22:17:57.843987 RX Vref 0 -> 0, step: 1
1992 22:17:57.846663
1993 22:17:57.846740 RX Delay -111 -> 252, step: 8
1994 22:17:57.853590 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1995 22:17:57.857362 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1996 22:17:57.860643 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1997 22:17:57.863641 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1998 22:17:57.867251 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1999 22:17:57.873917 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2000 22:17:57.877215 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2001 22:17:57.880187 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2002 22:17:57.883713 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2003 22:17:57.887435 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2004 22:17:57.893682 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2005 22:17:57.896758 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2006 22:17:57.900692 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2007 22:17:57.903874 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2008 22:17:57.910291 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2009 22:17:57.913517 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2010 22:17:57.913599 ==
2011 22:17:57.916613 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 22:17:57.920265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 22:17:57.920393 ==
2014 22:17:57.920519 DQS Delay:
2015 22:17:57.923428 DQS0 = 0, DQS1 = 0
2016 22:17:57.923510 DQM Delay:
2017 22:17:57.926999 DQM0 = 77, DQM1 = 74
2018 22:17:57.927097 DQ Delay:
2019 22:17:57.930040 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2020 22:17:57.933261 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2021 22:17:57.937180 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2022 22:17:57.940454 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2023 22:17:57.940552
2024 22:17:57.940651
2025 22:17:57.950032 [DQSOSCAuto] RK1, (LSB)MR18= 0x233a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2026 22:17:57.950152 CH1 RK1: MR19=606, MR18=233A
2027 22:17:57.956958 CH1_RK1: MR19=0x606, MR18=0x233A, DQSOSC=395, MR23=63, INC=94, DEC=63
2028 22:17:57.960171 [RxdqsGatingPostProcess] freq 800
2029 22:17:57.966612 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2030 22:17:57.969862 Pre-setting of DQS Precalculation
2031 22:17:57.973456 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2032 22:17:57.980111 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2033 22:17:57.989451 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2034 22:17:57.989576
2035 22:17:57.989678
2036 22:17:57.993007 [Calibration Summary] 1600 Mbps
2037 22:17:57.993119 CH 0, Rank 0
2038 22:17:57.996338 SW Impedance : PASS
2039 22:17:57.996449 DUTY Scan : NO K
2040 22:17:57.999534 ZQ Calibration : PASS
2041 22:17:58.003320 Jitter Meter : NO K
2042 22:17:58.003405 CBT Training : PASS
2043 22:17:58.006378 Write leveling : PASS
2044 22:17:58.006485 RX DQS gating : PASS
2045 22:17:58.009574 RX DQ/DQS(RDDQC) : PASS
2046 22:17:58.012793 TX DQ/DQS : PASS
2047 22:17:58.012883 RX DATLAT : PASS
2048 22:17:58.016041 RX DQ/DQS(Engine): PASS
2049 22:17:58.019832 TX OE : NO K
2050 22:17:58.019943 All Pass.
2051 22:17:58.020036
2052 22:17:58.020137 CH 0, Rank 1
2053 22:17:58.022979 SW Impedance : PASS
2054 22:17:58.026033 DUTY Scan : NO K
2055 22:17:58.026137 ZQ Calibration : PASS
2056 22:17:58.029295 Jitter Meter : NO K
2057 22:17:58.032964 CBT Training : PASS
2058 22:17:58.033049 Write leveling : PASS
2059 22:17:58.035825 RX DQS gating : PASS
2060 22:17:58.039759 RX DQ/DQS(RDDQC) : PASS
2061 22:17:58.039844 TX DQ/DQS : PASS
2062 22:17:58.042894 RX DATLAT : PASS
2063 22:17:58.046008 RX DQ/DQS(Engine): PASS
2064 22:17:58.046093 TX OE : NO K
2065 22:17:58.049851 All Pass.
2066 22:17:58.049936
2067 22:17:58.050002 CH 1, Rank 0
2068 22:17:58.052650 SW Impedance : PASS
2069 22:17:58.052735 DUTY Scan : NO K
2070 22:17:58.056135 ZQ Calibration : PASS
2071 22:17:58.059160 Jitter Meter : NO K
2072 22:17:58.059246 CBT Training : PASS
2073 22:17:58.063171 Write leveling : PASS
2074 22:17:58.063256 RX DQS gating : PASS
2075 22:17:58.066287 RX DQ/DQS(RDDQC) : PASS
2076 22:17:58.069497 TX DQ/DQS : PASS
2077 22:17:58.069582 RX DATLAT : PASS
2078 22:17:58.072681 RX DQ/DQS(Engine): PASS
2079 22:17:58.075686 TX OE : NO K
2080 22:17:58.075771 All Pass.
2081 22:17:58.075838
2082 22:17:58.075899 CH 1, Rank 1
2083 22:17:58.079417 SW Impedance : PASS
2084 22:17:58.082456 DUTY Scan : NO K
2085 22:17:58.082543 ZQ Calibration : PASS
2086 22:17:58.086092 Jitter Meter : NO K
2087 22:17:58.089180 CBT Training : PASS
2088 22:17:58.089265 Write leveling : PASS
2089 22:17:58.092256 RX DQS gating : PASS
2090 22:17:58.095827 RX DQ/DQS(RDDQC) : PASS
2091 22:17:58.095911 TX DQ/DQS : PASS
2092 22:17:58.099367 RX DATLAT : PASS
2093 22:17:58.102496 RX DQ/DQS(Engine): PASS
2094 22:17:58.102581 TX OE : NO K
2095 22:17:58.105607 All Pass.
2096 22:17:58.105692
2097 22:17:58.105764 DramC Write-DBI off
2098 22:17:58.108789 PER_BANK_REFRESH: Hybrid Mode
2099 22:17:58.108873 TX_TRACKING: ON
2100 22:17:58.112686 [GetDramInforAfterCalByMRR] Vendor 6.
2101 22:17:58.119094 [GetDramInforAfterCalByMRR] Revision 606.
2102 22:17:58.122247 [GetDramInforAfterCalByMRR] Revision 2 0.
2103 22:17:58.122333 MR0 0x3b3b
2104 22:17:58.122400 MR8 0x5151
2105 22:17:58.125770 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 22:17:58.125855
2107 22:17:58.128768 MR0 0x3b3b
2108 22:17:58.128853 MR8 0x5151
2109 22:17:58.131958 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 22:17:58.132043
2111 22:17:58.142531 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2112 22:17:58.145372 [FAST_K] Save calibration result to emmc
2113 22:17:58.148768 [FAST_K] Save calibration result to emmc
2114 22:17:58.152149 dram_init: config_dvfs: 1
2115 22:17:58.155402 dramc_set_vcore_voltage set vcore to 662500
2116 22:17:58.158957 Read voltage for 1200, 2
2117 22:17:58.159043 Vio18 = 0
2118 22:17:58.159111 Vcore = 662500
2119 22:17:58.161982 Vdram = 0
2120 22:17:58.162067 Vddq = 0
2121 22:17:58.162134 Vmddr = 0
2122 22:17:58.168692 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2123 22:17:58.171945 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2124 22:17:58.175201 MEM_TYPE=3, freq_sel=15
2125 22:17:58.178815 sv_algorithm_assistance_LP4_1600
2126 22:17:58.181849 ============ PULL DRAM RESETB DOWN ============
2127 22:17:58.185049 ========== PULL DRAM RESETB DOWN end =========
2128 22:17:58.191643 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2129 22:17:58.195541 ===================================
2130 22:17:58.198318 LPDDR4 DRAM CONFIGURATION
2131 22:17:58.198403 ===================================
2132 22:17:58.201983 EX_ROW_EN[0] = 0x0
2133 22:17:58.204869 EX_ROW_EN[1] = 0x0
2134 22:17:58.204954 LP4Y_EN = 0x0
2135 22:17:58.208383 WORK_FSP = 0x0
2136 22:17:58.208469 WL = 0x4
2137 22:17:58.211725 RL = 0x4
2138 22:17:58.211810 BL = 0x2
2139 22:17:58.214772 RPST = 0x0
2140 22:17:58.214870 RD_PRE = 0x0
2141 22:17:58.217975 WR_PRE = 0x1
2142 22:17:58.218059 WR_PST = 0x0
2143 22:17:58.221753 DBI_WR = 0x0
2144 22:17:58.221838 DBI_RD = 0x0
2145 22:17:58.224980 OTF = 0x1
2146 22:17:58.228130 ===================================
2147 22:17:58.231117 ===================================
2148 22:17:58.231204 ANA top config
2149 22:17:58.234805 ===================================
2150 22:17:58.238037 DLL_ASYNC_EN = 0
2151 22:17:58.241257 ALL_SLAVE_EN = 0
2152 22:17:58.244417 NEW_RANK_MODE = 1
2153 22:17:58.244503 DLL_IDLE_MODE = 1
2154 22:17:58.248012 LP45_APHY_COMB_EN = 1
2155 22:17:58.250967 TX_ODT_DIS = 1
2156 22:17:58.254859 NEW_8X_MODE = 1
2157 22:17:58.257838 ===================================
2158 22:17:58.261042 ===================================
2159 22:17:58.264650 data_rate = 2400
2160 22:17:58.267853 CKR = 1
2161 22:17:58.267960 DQ_P2S_RATIO = 8
2162 22:17:58.271209 ===================================
2163 22:17:58.274503 CA_P2S_RATIO = 8
2164 22:17:58.277778 DQ_CA_OPEN = 0
2165 22:17:58.281218 DQ_SEMI_OPEN = 0
2166 22:17:58.284260 CA_SEMI_OPEN = 0
2167 22:17:58.287411 CA_FULL_RATE = 0
2168 22:17:58.287494 DQ_CKDIV4_EN = 0
2169 22:17:58.291271 CA_CKDIV4_EN = 0
2170 22:17:58.294347 CA_PREDIV_EN = 0
2171 22:17:58.297601 PH8_DLY = 17
2172 22:17:58.300682 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2173 22:17:58.304539 DQ_AAMCK_DIV = 4
2174 22:17:58.304646 CA_AAMCK_DIV = 4
2175 22:17:58.307412 CA_ADMCK_DIV = 4
2176 22:17:58.311170 DQ_TRACK_CA_EN = 0
2177 22:17:58.314079 CA_PICK = 1200
2178 22:17:58.317806 CA_MCKIO = 1200
2179 22:17:58.320860 MCKIO_SEMI = 0
2180 22:17:58.324160 PLL_FREQ = 2366
2181 22:17:58.327402 DQ_UI_PI_RATIO = 32
2182 22:17:58.327484 CA_UI_PI_RATIO = 0
2183 22:17:58.330509 ===================================
2184 22:17:58.334250 ===================================
2185 22:17:58.337253 memory_type:LPDDR4
2186 22:17:58.340398 GP_NUM : 10
2187 22:17:58.340507 SRAM_EN : 1
2188 22:17:58.344146 MD32_EN : 0
2189 22:17:58.347407 ===================================
2190 22:17:58.350603 [ANA_INIT] >>>>>>>>>>>>>>
2191 22:17:58.350710 <<<<<< [CONFIGURE PHASE]: ANA_TX
2192 22:17:58.357386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2193 22:17:58.360356 ===================================
2194 22:17:58.360462 data_rate = 2400,PCW = 0X5b00
2195 22:17:58.363562 ===================================
2196 22:17:58.367324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2197 22:17:58.374023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2198 22:17:58.380321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 22:17:58.383773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2200 22:17:58.386997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2201 22:17:58.390128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2202 22:17:58.393209 [ANA_INIT] flow start
2203 22:17:58.393319 [ANA_INIT] PLL >>>>>>>>
2204 22:17:58.397002 [ANA_INIT] PLL <<<<<<<<
2205 22:17:58.400105 [ANA_INIT] MIDPI >>>>>>>>
2206 22:17:58.403196 [ANA_INIT] MIDPI <<<<<<<<
2207 22:17:58.403307 [ANA_INIT] DLL >>>>>>>>
2208 22:17:58.406839 [ANA_INIT] DLL <<<<<<<<
2209 22:17:58.410289 [ANA_INIT] flow end
2210 22:17:58.413207 ============ LP4 DIFF to SE enter ============
2211 22:17:58.416838 ============ LP4 DIFF to SE exit ============
2212 22:17:58.420174 [ANA_INIT] <<<<<<<<<<<<<
2213 22:17:58.423314 [Flow] Enable top DCM control >>>>>
2214 22:17:58.426644 [Flow] Enable top DCM control <<<<<
2215 22:17:58.429879 Enable DLL master slave shuffle
2216 22:17:58.433038 ==============================================================
2217 22:17:58.436217 Gating Mode config
2218 22:17:58.443059 ==============================================================
2219 22:17:58.443168 Config description:
2220 22:17:58.453186 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2221 22:17:58.459681 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2222 22:17:58.463169 SELPH_MODE 0: By rank 1: By Phase
2223 22:17:58.469238 ==============================================================
2224 22:17:58.472605 GAT_TRACK_EN = 1
2225 22:17:58.476345 RX_GATING_MODE = 2
2226 22:17:58.479432 RX_GATING_TRACK_MODE = 2
2227 22:17:58.482920 SELPH_MODE = 1
2228 22:17:58.485901 PICG_EARLY_EN = 1
2229 22:17:58.489064 VALID_LAT_VALUE = 1
2230 22:17:58.492797 ==============================================================
2231 22:17:58.495795 Enter into Gating configuration >>>>
2232 22:17:58.499621 Exit from Gating configuration <<<<
2233 22:17:58.502660 Enter into DVFS_PRE_config >>>>>
2234 22:17:58.515929 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2235 22:17:58.516037 Exit from DVFS_PRE_config <<<<<
2236 22:17:58.519356 Enter into PICG configuration >>>>
2237 22:17:58.522154 Exit from PICG configuration <<<<
2238 22:17:58.525640 [RX_INPUT] configuration >>>>>
2239 22:17:58.529113 [RX_INPUT] configuration <<<<<
2240 22:17:58.535767 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2241 22:17:58.538651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2242 22:17:58.545416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 22:17:58.552415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 22:17:58.558762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2245 22:17:58.565167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2246 22:17:58.568976 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2247 22:17:58.571921 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2248 22:17:58.575607 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2249 22:17:58.581927 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2250 22:17:58.585154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2251 22:17:58.588592 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2252 22:17:58.592118 ===================================
2253 22:17:58.594939 LPDDR4 DRAM CONFIGURATION
2254 22:17:58.598590 ===================================
2255 22:17:58.601598 EX_ROW_EN[0] = 0x0
2256 22:17:58.601702 EX_ROW_EN[1] = 0x0
2257 22:17:58.605179 LP4Y_EN = 0x0
2258 22:17:58.605282 WORK_FSP = 0x0
2259 22:17:58.608173 WL = 0x4
2260 22:17:58.608276 RL = 0x4
2261 22:17:58.612069 BL = 0x2
2262 22:17:58.612151 RPST = 0x0
2263 22:17:58.615337 RD_PRE = 0x0
2264 22:17:58.615440 WR_PRE = 0x1
2265 22:17:58.618546 WR_PST = 0x0
2266 22:17:58.618648 DBI_WR = 0x0
2267 22:17:58.621681 DBI_RD = 0x0
2268 22:17:58.621781 OTF = 0x1
2269 22:17:58.624681 ===================================
2270 22:17:58.631864 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2271 22:17:58.634777 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2272 22:17:58.638253 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2273 22:17:58.641995 ===================================
2274 22:17:58.645123 LPDDR4 DRAM CONFIGURATION
2275 22:17:58.648192 ===================================
2276 22:17:58.648294 EX_ROW_EN[0] = 0x10
2277 22:17:58.651257 EX_ROW_EN[1] = 0x0
2278 22:17:58.655121 LP4Y_EN = 0x0
2279 22:17:58.655232 WORK_FSP = 0x0
2280 22:17:58.658275 WL = 0x4
2281 22:17:58.658379 RL = 0x4
2282 22:17:58.661367 BL = 0x2
2283 22:17:58.661465 RPST = 0x0
2284 22:17:58.664523 RD_PRE = 0x0
2285 22:17:58.664627 WR_PRE = 0x1
2286 22:17:58.668268 WR_PST = 0x0
2287 22:17:58.668402 DBI_WR = 0x0
2288 22:17:58.671545 DBI_RD = 0x0
2289 22:17:58.671620 OTF = 0x1
2290 22:17:58.674705 ===================================
2291 22:17:58.681353 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2292 22:17:58.681438 ==
2293 22:17:58.684618 Dram Type= 6, Freq= 0, CH_0, rank 0
2294 22:17:58.691090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2295 22:17:58.691171 ==
2296 22:17:58.691249 [Duty_Offset_Calibration]
2297 22:17:58.694922 B0:2 B1:0 CA:3
2298 22:17:58.695010
2299 22:17:58.698031 [DutyScan_Calibration_Flow] k_type=0
2300 22:17:58.706800
2301 22:17:58.706928 ==CLK 0==
2302 22:17:58.709698 Final CLK duty delay cell = 0
2303 22:17:58.713285 [0] MAX Duty = 5031%(X100), DQS PI = 12
2304 22:17:58.716307 [0] MIN Duty = 4906%(X100), DQS PI = 54
2305 22:17:58.719477 [0] AVG Duty = 4968%(X100)
2306 22:17:58.719557
2307 22:17:58.722673 CH0 CLK Duty spec in!! Max-Min= 125%
2308 22:17:58.726379 [DutyScan_Calibration_Flow] ====Done====
2309 22:17:58.726460
2310 22:17:58.729306 [DutyScan_Calibration_Flow] k_type=1
2311 22:17:58.744840
2312 22:17:58.744981 ==DQS 0 ==
2313 22:17:58.748395 Final DQS duty delay cell = 0
2314 22:17:58.751520 [0] MAX Duty = 5093%(X100), DQS PI = 18
2315 22:17:58.755112 [0] MIN Duty = 4907%(X100), DQS PI = 44
2316 22:17:58.758347 [0] AVG Duty = 5000%(X100)
2317 22:17:58.758427
2318 22:17:58.758502 ==DQS 1 ==
2319 22:17:58.761634 Final DQS duty delay cell = -4
2320 22:17:58.764884 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2321 22:17:58.768670 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2322 22:17:58.771758 [-4] AVG Duty = 4937%(X100)
2323 22:17:58.771872
2324 22:17:58.775062 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2325 22:17:58.775185
2326 22:17:58.778091 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2327 22:17:58.781310 [DutyScan_Calibration_Flow] ====Done====
2328 22:17:58.781389
2329 22:17:58.785159 [DutyScan_Calibration_Flow] k_type=3
2330 22:17:58.802480
2331 22:17:58.802587 ==DQM 0 ==
2332 22:17:58.806216 Final DQM duty delay cell = 0
2333 22:17:58.809131 [0] MAX Duty = 5124%(X100), DQS PI = 28
2334 22:17:58.812751 [0] MIN Duty = 4876%(X100), DQS PI = 0
2335 22:17:58.812828 [0] AVG Duty = 5000%(X100)
2336 22:17:58.816145
2337 22:17:58.816227 ==DQM 1 ==
2338 22:17:58.819024 Final DQM duty delay cell = 4
2339 22:17:58.822781 [4] MAX Duty = 5124%(X100), DQS PI = 50
2340 22:17:58.825852 [4] MIN Duty = 5031%(X100), DQS PI = 12
2341 22:17:58.829117 [4] AVG Duty = 5077%(X100)
2342 22:17:58.829201
2343 22:17:58.832714 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2344 22:17:58.832799
2345 22:17:58.835965 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2346 22:17:58.839040 [DutyScan_Calibration_Flow] ====Done====
2347 22:17:58.839124
2348 22:17:58.842250 [DutyScan_Calibration_Flow] k_type=2
2349 22:17:58.857670
2350 22:17:58.857759 ==DQ 0 ==
2351 22:17:58.860576 Final DQ duty delay cell = -4
2352 22:17:58.863691 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2353 22:17:58.867787 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2354 22:17:58.870763 [-4] AVG Duty = 4969%(X100)
2355 22:17:58.870894
2356 22:17:58.870990 ==DQ 1 ==
2357 22:17:58.873940 Final DQ duty delay cell = -4
2358 22:17:58.877168 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2359 22:17:58.880233 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2360 22:17:58.883563 [-4] AVG Duty = 4938%(X100)
2361 22:17:58.883642
2362 22:17:58.886687 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2363 22:17:58.886773
2364 22:17:58.890713 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2365 22:17:58.893550 [DutyScan_Calibration_Flow] ====Done====
2366 22:17:58.893658 ==
2367 22:17:58.896779 Dram Type= 6, Freq= 0, CH_1, rank 0
2368 22:17:58.900603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 22:17:58.900727 ==
2370 22:17:58.903855 [Duty_Offset_Calibration]
2371 22:17:58.907122 B0:1 B1:-2 CA:0
2372 22:17:58.907251
2373 22:17:58.910211 [DutyScan_Calibration_Flow] k_type=0
2374 22:17:58.918151
2375 22:17:58.918232 ==CLK 0==
2376 22:17:58.921293 Final CLK duty delay cell = 0
2377 22:17:58.924907 [0] MAX Duty = 5062%(X100), DQS PI = 30
2378 22:17:58.927937 [0] MIN Duty = 4844%(X100), DQS PI = 58
2379 22:17:58.931406 [0] AVG Duty = 4953%(X100)
2380 22:17:58.931518
2381 22:17:58.934526 CH1 CLK Duty spec in!! Max-Min= 218%
2382 22:17:58.937757 [DutyScan_Calibration_Flow] ====Done====
2383 22:17:58.937877
2384 22:17:58.941098 [DutyScan_Calibration_Flow] k_type=1
2385 22:17:58.956549
2386 22:17:58.956634 ==DQS 0 ==
2387 22:17:58.959561 Final DQS duty delay cell = -4
2388 22:17:58.963120 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2389 22:17:58.966672 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2390 22:17:58.969870 [-4] AVG Duty = 4969%(X100)
2391 22:17:58.969967
2392 22:17:58.970065 ==DQS 1 ==
2393 22:17:58.972897 Final DQS duty delay cell = 0
2394 22:17:58.975961 [0] MAX Duty = 5062%(X100), DQS PI = 0
2395 22:17:58.979819 [0] MIN Duty = 4875%(X100), DQS PI = 26
2396 22:17:58.983081 [0] AVG Duty = 4968%(X100)
2397 22:17:58.983195
2398 22:17:58.986163 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2399 22:17:58.986304
2400 22:17:58.989877 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2401 22:17:58.993179 [DutyScan_Calibration_Flow] ====Done====
2402 22:17:58.993284
2403 22:17:58.996223 [DutyScan_Calibration_Flow] k_type=3
2404 22:17:59.013217
2405 22:17:59.013330 ==DQM 0 ==
2406 22:17:59.016518 Final DQM duty delay cell = 0
2407 22:17:59.019668 [0] MAX Duty = 5000%(X100), DQS PI = 22
2408 22:17:59.023186 [0] MIN Duty = 4844%(X100), DQS PI = 54
2409 22:17:59.026154 [0] AVG Duty = 4922%(X100)
2410 22:17:59.026257
2411 22:17:59.026348 ==DQM 1 ==
2412 22:17:59.030000 Final DQM duty delay cell = 0
2413 22:17:59.033219 [0] MAX Duty = 5031%(X100), DQS PI = 36
2414 22:17:59.036283 [0] MIN Duty = 4907%(X100), DQS PI = 2
2415 22:17:59.039724 [0] AVG Duty = 4969%(X100)
2416 22:17:59.039854
2417 22:17:59.043260 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2418 22:17:59.043393
2419 22:17:59.045909 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2420 22:17:59.049480 [DutyScan_Calibration_Flow] ====Done====
2421 22:17:59.049624
2422 22:17:59.052991 [DutyScan_Calibration_Flow] k_type=2
2423 22:17:59.069558
2424 22:17:59.069654 ==DQ 0 ==
2425 22:17:59.072511 Final DQ duty delay cell = 0
2426 22:17:59.076072 [0] MAX Duty = 5062%(X100), DQS PI = 18
2427 22:17:59.079125 [0] MIN Duty = 4938%(X100), DQS PI = 54
2428 22:17:59.079205 [0] AVG Duty = 5000%(X100)
2429 22:17:59.082843
2430 22:17:59.082930 ==DQ 1 ==
2431 22:17:59.086002 Final DQ duty delay cell = 0
2432 22:17:59.089138 [0] MAX Duty = 5125%(X100), DQS PI = 46
2433 22:17:59.092426 [0] MIN Duty = 4969%(X100), DQS PI = 26
2434 22:17:59.092511 [0] AVG Duty = 5047%(X100)
2435 22:17:59.095656
2436 22:17:59.098944 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2437 22:17:59.099024
2438 22:17:59.102677 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2439 22:17:59.105734 [DutyScan_Calibration_Flow] ====Done====
2440 22:17:59.109363 nWR fixed to 30
2441 22:17:59.109448 [ModeRegInit_LP4] CH0 RK0
2442 22:17:59.112573 [ModeRegInit_LP4] CH0 RK1
2443 22:17:59.115791 [ModeRegInit_LP4] CH1 RK0
2444 22:17:59.118920 [ModeRegInit_LP4] CH1 RK1
2445 22:17:59.118998 match AC timing 7
2446 22:17:59.125605 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2447 22:17:59.129191 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2448 22:17:59.132180 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2449 22:17:59.139239 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2450 22:17:59.142466 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2451 22:17:59.142546 ==
2452 22:17:59.145656 Dram Type= 6, Freq= 0, CH_0, rank 0
2453 22:17:59.149131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2454 22:17:59.149211 ==
2455 22:17:59.155790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2456 22:17:59.162323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2457 22:17:59.169639 [CA 0] Center 40 (10~71) winsize 62
2458 22:17:59.172738 [CA 1] Center 39 (9~70) winsize 62
2459 22:17:59.176370 [CA 2] Center 36 (6~66) winsize 61
2460 22:17:59.179459 [CA 3] Center 35 (5~66) winsize 62
2461 22:17:59.182927 [CA 4] Center 34 (4~65) winsize 62
2462 22:17:59.185799 [CA 5] Center 33 (3~63) winsize 61
2463 22:17:59.185912
2464 22:17:59.189503 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2465 22:17:59.189584
2466 22:17:59.192654 [CATrainingPosCal] consider 1 rank data
2467 22:17:59.195911 u2DelayCellTimex100 = 270/100 ps
2468 22:17:59.199068 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2469 22:17:59.206087 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2470 22:17:59.209287 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2471 22:17:59.212379 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2472 22:17:59.215430 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2473 22:17:59.219158 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2474 22:17:59.219242
2475 22:17:59.222305 CA PerBit enable=1, Macro0, CA PI delay=33
2476 22:17:59.222414
2477 22:17:59.225324 [CBTSetCACLKResult] CA Dly = 33
2478 22:17:59.229020 CS Dly: 7 (0~38)
2479 22:17:59.229125 ==
2480 22:17:59.232169 Dram Type= 6, Freq= 0, CH_0, rank 1
2481 22:17:59.235292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2482 22:17:59.235375 ==
2483 22:17:59.242224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2484 22:17:59.245524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2485 22:17:59.255598 [CA 0] Center 40 (10~70) winsize 61
2486 22:17:59.258634 [CA 1] Center 39 (9~70) winsize 62
2487 22:17:59.262332 [CA 2] Center 35 (5~66) winsize 62
2488 22:17:59.265251 [CA 3] Center 35 (5~66) winsize 62
2489 22:17:59.268981 [CA 4] Center 34 (4~65) winsize 62
2490 22:17:59.271941 [CA 5] Center 33 (3~64) winsize 62
2491 22:17:59.272024
2492 22:17:59.275742 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2493 22:17:59.275843
2494 22:17:59.278912 [CATrainingPosCal] consider 2 rank data
2495 22:17:59.281989 u2DelayCellTimex100 = 270/100 ps
2496 22:17:59.288472 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2497 22:17:59.292125 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2498 22:17:59.295180 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2499 22:17:59.298382 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2500 22:17:59.301673 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2501 22:17:59.304961 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2502 22:17:59.305044
2503 22:17:59.308706 CA PerBit enable=1, Macro0, CA PI delay=33
2504 22:17:59.308788
2505 22:17:59.311827 [CBTSetCACLKResult] CA Dly = 33
2506 22:17:59.314969 CS Dly: 8 (0~40)
2507 22:17:59.315051
2508 22:17:59.318123 ----->DramcWriteLeveling(PI) begin...
2509 22:17:59.318238 ==
2510 22:17:59.321822 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 22:17:59.325109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 22:17:59.325194 ==
2513 22:17:59.328224 Write leveling (Byte 0): 33 => 33
2514 22:17:59.331890 Write leveling (Byte 1): 30 => 30
2515 22:17:59.334900 DramcWriteLeveling(PI) end<-----
2516 22:17:59.334982
2517 22:17:59.335047 ==
2518 22:17:59.338087 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 22:17:59.341710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 22:17:59.341794 ==
2521 22:17:59.344813 [Gating] SW mode calibration
2522 22:17:59.351370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2523 22:17:59.358212 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2524 22:17:59.361254 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 22:17:59.365044 0 15 4 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
2526 22:17:59.371093 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 22:17:59.374972 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 22:17:59.377880 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 22:17:59.384760 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 22:17:59.387714 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 22:17:59.391333 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2532 22:17:59.397726 1 0 0 | B1->B0 | 3232 2626 | 0 0 | (0 0) (0 0)
2533 22:17:59.401323 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 22:17:59.404432 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 22:17:59.410886 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 22:17:59.414223 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 22:17:59.417490 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 22:17:59.424599 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 22:17:59.427566 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2540 22:17:59.430697 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2541 22:17:59.437353 1 1 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
2542 22:17:59.440517 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 22:17:59.444059 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 22:17:59.450400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 22:17:59.454369 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 22:17:59.457460 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 22:17:59.463753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 22:17:59.466984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 22:17:59.470770 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 22:17:59.477357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:17:59.480427 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:17:59.484069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:17:59.490368 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:17:59.493579 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 22:17:59.497182 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:17:59.503459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:17:59.507088 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:17:59.510299 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:17:59.516828 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:17:59.520065 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:17:59.523312 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:17:59.530228 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:17:59.533230 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:17:59.536419 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 22:17:59.543177 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 22:17:59.543341 Total UI for P1: 0, mck2ui 16
2567 22:17:59.549697 best dqsien dly found for B0: ( 1, 4, 0)
2568 22:17:59.549783 Total UI for P1: 0, mck2ui 16
2569 22:17:59.556692 best dqsien dly found for B1: ( 1, 4, 2)
2570 22:17:59.559925 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2571 22:17:59.563080 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2572 22:17:59.563185
2573 22:17:59.566214 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2574 22:17:59.569734 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2575 22:17:59.572999 [Gating] SW calibration Done
2576 22:17:59.573084 ==
2577 22:17:59.576206 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 22:17:59.580123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 22:17:59.580208 ==
2580 22:17:59.580275 RX Vref Scan: 0
2581 22:17:59.583165
2582 22:17:59.583275 RX Vref 0 -> 0, step: 1
2583 22:17:59.583369
2584 22:17:59.586121 RX Delay -40 -> 252, step: 8
2585 22:17:59.589354 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2586 22:17:59.593121 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2587 22:17:59.599404 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2588 22:17:59.602926 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2589 22:17:59.606227 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2590 22:17:59.609244 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2591 22:17:59.612807 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2592 22:17:59.619124 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2593 22:17:59.623104 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2594 22:17:59.626232 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2595 22:17:59.629680 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2596 22:17:59.632729 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2597 22:17:59.639529 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2598 22:17:59.642362 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2599 22:17:59.646056 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2600 22:17:59.649179 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2601 22:17:59.649256 ==
2602 22:17:59.652924 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 22:17:59.659344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 22:17:59.659435 ==
2605 22:17:59.659502 DQS Delay:
2606 22:17:59.659565 DQS0 = 0, DQS1 = 0
2607 22:17:59.662458 DQM Delay:
2608 22:17:59.662542 DQM0 = 113, DQM1 = 103
2609 22:17:59.665722 DQ Delay:
2610 22:17:59.669368 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2611 22:17:59.672383 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2612 22:17:59.675887 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =95
2613 22:17:59.679306 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2614 22:17:59.679389
2615 22:17:59.679454
2616 22:17:59.679515 ==
2617 22:17:59.682555 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 22:17:59.685748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 22:17:59.685846 ==
2620 22:17:59.688932
2621 22:17:59.689045
2622 22:17:59.689110 TX Vref Scan disable
2623 22:17:59.692744 == TX Byte 0 ==
2624 22:17:59.695971 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2625 22:17:59.699066 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2626 22:17:59.702537 == TX Byte 1 ==
2627 22:17:59.705865 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2628 22:17:59.708893 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2629 22:17:59.708997 ==
2630 22:17:59.712036 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 22:17:59.718803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 22:17:59.718938 ==
2633 22:17:59.729767 TX Vref=22, minBit 1, minWin=25, winSum=416
2634 22:17:59.732708 TX Vref=24, minBit 0, minWin=26, winSum=421
2635 22:17:59.735972 TX Vref=26, minBit 8, minWin=26, winSum=431
2636 22:17:59.740108 TX Vref=28, minBit 4, minWin=26, winSum=430
2637 22:17:59.742825 TX Vref=30, minBit 14, minWin=26, winSum=433
2638 22:17:59.749386 TX Vref=32, minBit 1, minWin=26, winSum=426
2639 22:17:59.752498 [TxChooseVref] Worse bit 14, Min win 26, Win sum 433, Final Vref 30
2640 22:17:59.752585
2641 22:17:59.756207 Final TX Range 1 Vref 30
2642 22:17:59.756285
2643 22:17:59.756356 ==
2644 22:17:59.759178 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 22:17:59.766200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 22:17:59.766279 ==
2647 22:17:59.766348
2648 22:17:59.766411
2649 22:17:59.766476 TX Vref Scan disable
2650 22:17:59.769486 == TX Byte 0 ==
2651 22:17:59.773051 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2652 22:17:59.776154 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2653 22:17:59.780174 == TX Byte 1 ==
2654 22:17:59.783275 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2655 22:17:59.789812 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2656 22:17:59.789898
2657 22:17:59.789964 [DATLAT]
2658 22:17:59.790026 Freq=1200, CH0 RK0
2659 22:17:59.790087
2660 22:17:59.793017 DATLAT Default: 0xd
2661 22:17:59.793101 0, 0xFFFF, sum = 0
2662 22:17:59.796051 1, 0xFFFF, sum = 0
2663 22:17:59.799875 2, 0xFFFF, sum = 0
2664 22:17:59.799961 3, 0xFFFF, sum = 0
2665 22:17:59.803105 4, 0xFFFF, sum = 0
2666 22:17:59.803191 5, 0xFFFF, sum = 0
2667 22:17:59.806160 6, 0xFFFF, sum = 0
2668 22:17:59.806253 7, 0xFFFF, sum = 0
2669 22:17:59.809195 8, 0xFFFF, sum = 0
2670 22:17:59.809281 9, 0xFFFF, sum = 0
2671 22:17:59.813281 10, 0xFFFF, sum = 0
2672 22:17:59.813376 11, 0xFFFF, sum = 0
2673 22:17:59.816229 12, 0x0, sum = 1
2674 22:17:59.816304 13, 0x0, sum = 2
2675 22:17:59.819706 14, 0x0, sum = 3
2676 22:17:59.819780 15, 0x0, sum = 4
2677 22:17:59.822724 best_step = 13
2678 22:17:59.822796
2679 22:17:59.822873 ==
2680 22:17:59.825800 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 22:17:59.829357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 22:17:59.829436 ==
2683 22:17:59.829502 RX Vref Scan: 1
2684 22:17:59.829565
2685 22:17:59.832700 Set Vref Range= 32 -> 127
2686 22:17:59.832770
2687 22:17:59.835860 RX Vref 32 -> 127, step: 1
2688 22:17:59.835938
2689 22:17:59.839127 RX Delay -37 -> 252, step: 4
2690 22:17:59.839203
2691 22:17:59.842923 Set Vref, RX VrefLevel [Byte0]: 32
2692 22:17:59.845977 [Byte1]: 32
2693 22:17:59.846058
2694 22:17:59.849420 Set Vref, RX VrefLevel [Byte0]: 33
2695 22:17:59.852534 [Byte1]: 33
2696 22:17:59.856196
2697 22:17:59.856277 Set Vref, RX VrefLevel [Byte0]: 34
2698 22:17:59.859697 [Byte1]: 34
2699 22:17:59.864606
2700 22:17:59.864681 Set Vref, RX VrefLevel [Byte0]: 35
2701 22:17:59.867896 [Byte1]: 35
2702 22:17:59.872472
2703 22:17:59.872547 Set Vref, RX VrefLevel [Byte0]: 36
2704 22:17:59.875730 [Byte1]: 36
2705 22:17:59.880766
2706 22:17:59.880858 Set Vref, RX VrefLevel [Byte0]: 37
2707 22:17:59.883479 [Byte1]: 37
2708 22:17:59.888116
2709 22:17:59.888201 Set Vref, RX VrefLevel [Byte0]: 38
2710 22:17:59.891423 [Byte1]: 38
2711 22:17:59.896517
2712 22:17:59.896601 Set Vref, RX VrefLevel [Byte0]: 39
2713 22:17:59.899489 [Byte1]: 39
2714 22:17:59.904530
2715 22:17:59.904613 Set Vref, RX VrefLevel [Byte0]: 40
2716 22:17:59.910848 [Byte1]: 40
2717 22:17:59.910932
2718 22:17:59.914089 Set Vref, RX VrefLevel [Byte0]: 41
2719 22:17:59.917710 [Byte1]: 41
2720 22:17:59.917794
2721 22:17:59.921055 Set Vref, RX VrefLevel [Byte0]: 42
2722 22:17:59.923971 [Byte1]: 42
2723 22:17:59.928164
2724 22:17:59.928251 Set Vref, RX VrefLevel [Byte0]: 43
2725 22:17:59.931411 [Byte1]: 43
2726 22:17:59.936561
2727 22:17:59.936649 Set Vref, RX VrefLevel [Byte0]: 44
2728 22:17:59.939782 [Byte1]: 44
2729 22:17:59.944176
2730 22:17:59.944260 Set Vref, RX VrefLevel [Byte0]: 45
2731 22:17:59.947356 [Byte1]: 45
2732 22:17:59.952412
2733 22:17:59.952522 Set Vref, RX VrefLevel [Byte0]: 46
2734 22:17:59.955664 [Byte1]: 46
2735 22:17:59.960579
2736 22:17:59.960689 Set Vref, RX VrefLevel [Byte0]: 47
2737 22:17:59.963698 [Byte1]: 47
2738 22:17:59.968143
2739 22:17:59.968227 Set Vref, RX VrefLevel [Byte0]: 48
2740 22:17:59.971683 [Byte1]: 48
2741 22:17:59.976632
2742 22:17:59.976716 Set Vref, RX VrefLevel [Byte0]: 49
2743 22:17:59.979820 [Byte1]: 49
2744 22:17:59.984019
2745 22:17:59.984102 Set Vref, RX VrefLevel [Byte0]: 50
2746 22:17:59.987517 [Byte1]: 50
2747 22:17:59.992085
2748 22:17:59.992168 Set Vref, RX VrefLevel [Byte0]: 51
2749 22:17:59.995286 [Byte1]: 51
2750 22:18:00.000571
2751 22:18:00.000654 Set Vref, RX VrefLevel [Byte0]: 52
2752 22:18:00.003510 [Byte1]: 52
2753 22:18:00.008618
2754 22:18:00.008701 Set Vref, RX VrefLevel [Byte0]: 53
2755 22:18:00.011712 [Byte1]: 53
2756 22:18:00.016365
2757 22:18:00.016447 Set Vref, RX VrefLevel [Byte0]: 54
2758 22:18:00.019611 [Byte1]: 54
2759 22:18:00.024548
2760 22:18:00.024631 Set Vref, RX VrefLevel [Byte0]: 55
2761 22:18:00.027555 [Byte1]: 55
2762 22:18:00.032289
2763 22:18:00.032372 Set Vref, RX VrefLevel [Byte0]: 56
2764 22:18:00.035248 [Byte1]: 56
2765 22:18:00.040298
2766 22:18:00.040382 Set Vref, RX VrefLevel [Byte0]: 57
2767 22:18:00.043428 [Byte1]: 57
2768 22:18:00.048468
2769 22:18:00.048553 Set Vref, RX VrefLevel [Byte0]: 58
2770 22:18:00.051605 [Byte1]: 58
2771 22:18:00.056024
2772 22:18:00.056107 Set Vref, RX VrefLevel [Byte0]: 59
2773 22:18:00.060034 [Byte1]: 59
2774 22:18:00.064392
2775 22:18:00.064475 Set Vref, RX VrefLevel [Byte0]: 60
2776 22:18:00.067460 [Byte1]: 60
2777 22:18:00.072240
2778 22:18:00.072323 Set Vref, RX VrefLevel [Byte0]: 61
2779 22:18:00.075695 [Byte1]: 61
2780 22:18:00.080384
2781 22:18:00.080467 Set Vref, RX VrefLevel [Byte0]: 62
2782 22:18:00.083348 [Byte1]: 62
2783 22:18:00.088391
2784 22:18:00.088475 Set Vref, RX VrefLevel [Byte0]: 63
2785 22:18:00.091633 [Byte1]: 63
2786 22:18:00.096177
2787 22:18:00.096261 Set Vref, RX VrefLevel [Byte0]: 64
2788 22:18:00.099935 [Byte1]: 64
2789 22:18:00.104364
2790 22:18:00.104476 Set Vref, RX VrefLevel [Byte0]: 65
2791 22:18:00.107485 [Byte1]: 65
2792 22:18:00.112460
2793 22:18:00.112538 Set Vref, RX VrefLevel [Byte0]: 66
2794 22:18:00.115751 [Byte1]: 66
2795 22:18:00.120615
2796 22:18:00.120693 Set Vref, RX VrefLevel [Byte0]: 67
2797 22:18:00.123901 [Byte1]: 67
2798 22:18:00.128128
2799 22:18:00.128244 Set Vref, RX VrefLevel [Byte0]: 68
2800 22:18:00.131269 [Byte1]: 68
2801 22:18:00.136197
2802 22:18:00.136305 Set Vref, RX VrefLevel [Byte0]: 69
2803 22:18:00.142675 [Byte1]: 69
2804 22:18:00.142775
2805 22:18:00.146335 Set Vref, RX VrefLevel [Byte0]: 70
2806 22:18:00.149461 [Byte1]: 70
2807 22:18:00.149542
2808 22:18:00.152763 Set Vref, RX VrefLevel [Byte0]: 71
2809 22:18:00.155838 [Byte1]: 71
2810 22:18:00.160370
2811 22:18:00.160452 Set Vref, RX VrefLevel [Byte0]: 72
2812 22:18:00.163522 [Byte1]: 72
2813 22:18:00.167978
2814 22:18:00.168059 Set Vref, RX VrefLevel [Byte0]: 73
2815 22:18:00.171864 [Byte1]: 73
2816 22:18:00.176065
2817 22:18:00.176146 Set Vref, RX VrefLevel [Byte0]: 74
2818 22:18:00.179660 [Byte1]: 74
2819 22:18:00.184170
2820 22:18:00.184252 Final RX Vref Byte 0 = 60 to rank0
2821 22:18:00.187698 Final RX Vref Byte 1 = 54 to rank0
2822 22:18:00.190770 Final RX Vref Byte 0 = 60 to rank1
2823 22:18:00.194328 Final RX Vref Byte 1 = 54 to rank1==
2824 22:18:00.197271 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 22:18:00.204144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 22:18:00.204228 ==
2827 22:18:00.204326 DQS Delay:
2828 22:18:00.204405 DQS0 = 0, DQS1 = 0
2829 22:18:00.207837 DQM Delay:
2830 22:18:00.207918 DQM0 = 112, DQM1 = 102
2831 22:18:00.211003 DQ Delay:
2832 22:18:00.214035 DQ0 =112, DQ1 =110, DQ2 =112, DQ3 =108
2833 22:18:00.217800 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2834 22:18:00.220969 DQ8 =94, DQ9 =86, DQ10 =102, DQ11 =94
2835 22:18:00.224186 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2836 22:18:00.224268
2837 22:18:00.224332
2838 22:18:00.233706 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2839 22:18:00.233793 CH0 RK0: MR19=303, MR18=FBFB
2840 22:18:00.240282 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2841 22:18:00.240387
2842 22:18:00.243809 ----->DramcWriteLeveling(PI) begin...
2843 22:18:00.243893 ==
2844 22:18:00.246782 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 22:18:00.253880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 22:18:00.253965 ==
2847 22:18:00.256929 Write leveling (Byte 0): 33 => 33
2848 22:18:00.257012 Write leveling (Byte 1): 30 => 30
2849 22:18:00.260157 DramcWriteLeveling(PI) end<-----
2850 22:18:00.260239
2851 22:18:00.263407 ==
2852 22:18:00.263489 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 22:18:00.270457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 22:18:00.270542 ==
2855 22:18:00.273637 [Gating] SW mode calibration
2856 22:18:00.280383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 22:18:00.283575 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 22:18:00.289940 0 15 0 | B1->B0 | 2525 3434 | 0 0 | (1 1) (0 0)
2859 22:18:00.293715 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 22:18:00.296746 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 22:18:00.303595 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 22:18:00.306478 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 22:18:00.310278 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 22:18:00.316551 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2865 22:18:00.319713 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2866 22:18:00.322891 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 22:18:00.330037 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 22:18:00.333295 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 22:18:00.336499 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 22:18:00.343277 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 22:18:00.346226 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 22:18:00.349800 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2873 22:18:00.356122 1 0 28 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
2874 22:18:00.359638 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2875 22:18:00.362770 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 22:18:00.369847 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 22:18:00.372932 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:18:00.376244 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:18:00.383045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 22:18:00.386133 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 22:18:00.389302 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 22:18:00.396307 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 22:18:00.399592 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 22:18:00.402629 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:18:00.406368 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:18:00.412836 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:18:00.415860 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:18:00.419470 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:18:00.426106 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:18:00.429440 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:18:00.432642 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:18:00.439550 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:18:00.442847 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:18:00.446058 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:18:00.452821 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 22:18:00.456042 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 22:18:00.459507 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 22:18:00.466022 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 22:18:00.466147 Total UI for P1: 0, mck2ui 16
2900 22:18:00.472292 best dqsien dly found for B0: ( 1, 3, 28)
2901 22:18:00.475688 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 22:18:00.478860 Total UI for P1: 0, mck2ui 16
2903 22:18:00.482131 best dqsien dly found for B1: ( 1, 4, 0)
2904 22:18:00.485593 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2905 22:18:00.489452 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2906 22:18:00.489563
2907 22:18:00.492449 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2908 22:18:00.495770 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2909 22:18:00.498934 [Gating] SW calibration Done
2910 22:18:00.499017 ==
2911 22:18:00.502142 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 22:18:00.505379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 22:18:00.509179 ==
2914 22:18:00.509262 RX Vref Scan: 0
2915 22:18:00.509328
2916 22:18:00.512241 RX Vref 0 -> 0, step: 1
2917 22:18:00.512328
2918 22:18:00.512398 RX Delay -40 -> 252, step: 8
2919 22:18:00.518923 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2920 22:18:00.522427 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2921 22:18:00.525898 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2922 22:18:00.528931 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2923 22:18:00.532549 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2924 22:18:00.538651 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2925 22:18:00.542253 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2926 22:18:00.545578 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 22:18:00.548799 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2928 22:18:00.552074 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2929 22:18:00.558376 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2930 22:18:00.562098 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2931 22:18:00.565206 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2932 22:18:00.568649 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2933 22:18:00.572288 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2934 22:18:00.578376 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2935 22:18:00.578486 ==
2936 22:18:00.581692 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 22:18:00.585563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 22:18:00.585666 ==
2939 22:18:00.585762 DQS Delay:
2940 22:18:00.588812 DQS0 = 0, DQS1 = 0
2941 22:18:00.588899 DQM Delay:
2942 22:18:00.591979 DQM0 = 112, DQM1 = 102
2943 22:18:00.592063 DQ Delay:
2944 22:18:00.595086 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2945 22:18:00.598798 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2946 22:18:00.601919 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2947 22:18:00.605193 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2948 22:18:00.605279
2949 22:18:00.605345
2950 22:18:00.608718 ==
2951 22:18:00.611716 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 22:18:00.615039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 22:18:00.615150 ==
2954 22:18:00.615245
2955 22:18:00.615336
2956 22:18:00.618249 TX Vref Scan disable
2957 22:18:00.618348 == TX Byte 0 ==
2958 22:18:00.622075 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2959 22:18:00.628281 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2960 22:18:00.628371 == TX Byte 1 ==
2961 22:18:00.634866 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2962 22:18:00.637945 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2963 22:18:00.638068 ==
2964 22:18:00.641324 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 22:18:00.644431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 22:18:00.644517 ==
2967 22:18:00.657450 TX Vref=22, minBit 0, minWin=26, winSum=421
2968 22:18:00.660686 TX Vref=24, minBit 0, minWin=26, winSum=428
2969 22:18:00.663794 TX Vref=26, minBit 1, minWin=26, winSum=435
2970 22:18:00.667497 TX Vref=28, minBit 1, minWin=26, winSum=439
2971 22:18:00.670769 TX Vref=30, minBit 2, minWin=26, winSum=440
2972 22:18:00.676803 TX Vref=32, minBit 13, minWin=26, winSum=439
2973 22:18:00.680537 [TxChooseVref] Worse bit 2, Min win 26, Win sum 440, Final Vref 30
2974 22:18:00.680625
2975 22:18:00.683543 Final TX Range 1 Vref 30
2976 22:18:00.683649
2977 22:18:00.683742 ==
2978 22:18:00.687004 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 22:18:00.690335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 22:18:00.693711 ==
2981 22:18:00.693797
2982 22:18:00.693864
2983 22:18:00.693925 TX Vref Scan disable
2984 22:18:00.696853 == TX Byte 0 ==
2985 22:18:00.700527 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 22:18:00.706748 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 22:18:00.706838 == TX Byte 1 ==
2988 22:18:00.710171 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2989 22:18:00.716710 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2990 22:18:00.716796
2991 22:18:00.716864 [DATLAT]
2992 22:18:00.716927 Freq=1200, CH0 RK1
2993 22:18:00.716987
2994 22:18:00.719929 DATLAT Default: 0xd
2995 22:18:00.720046 0, 0xFFFF, sum = 0
2996 22:18:00.723711 1, 0xFFFF, sum = 0
2997 22:18:00.727108 2, 0xFFFF, sum = 0
2998 22:18:00.727221 3, 0xFFFF, sum = 0
2999 22:18:00.730418 4, 0xFFFF, sum = 0
3000 22:18:00.730523 5, 0xFFFF, sum = 0
3001 22:18:00.733522 6, 0xFFFF, sum = 0
3002 22:18:00.733629 7, 0xFFFF, sum = 0
3003 22:18:00.736884 8, 0xFFFF, sum = 0
3004 22:18:00.736990 9, 0xFFFF, sum = 0
3005 22:18:00.739851 10, 0xFFFF, sum = 0
3006 22:18:00.739964 11, 0xFFFF, sum = 0
3007 22:18:00.743513 12, 0x0, sum = 1
3008 22:18:00.743629 13, 0x0, sum = 2
3009 22:18:00.746625 14, 0x0, sum = 3
3010 22:18:00.746738 15, 0x0, sum = 4
3011 22:18:00.749843 best_step = 13
3012 22:18:00.749943
3013 22:18:00.750017 ==
3014 22:18:00.753048 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 22:18:00.756394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 22:18:00.756508 ==
3017 22:18:00.756607 RX Vref Scan: 0
3018 22:18:00.759600
3019 22:18:00.759712 RX Vref 0 -> 0, step: 1
3020 22:18:00.759815
3021 22:18:00.763479 RX Delay -37 -> 252, step: 4
3022 22:18:00.769575 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3023 22:18:00.772987 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3024 22:18:00.776639 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3025 22:18:00.779968 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3026 22:18:00.782899 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3027 22:18:00.789517 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3028 22:18:00.793193 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3029 22:18:00.796320 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3030 22:18:00.800051 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3031 22:18:00.802976 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3032 22:18:00.806041 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3033 22:18:00.813100 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3034 22:18:00.816480 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3035 22:18:00.819788 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3036 22:18:00.823039 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3037 22:18:00.829315 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3038 22:18:00.829404 ==
3039 22:18:00.832998 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 22:18:00.836022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 22:18:00.836105 ==
3042 22:18:00.836171 DQS Delay:
3043 22:18:00.839178 DQS0 = 0, DQS1 = 0
3044 22:18:00.839261 DQM Delay:
3045 22:18:00.843059 DQM0 = 111, DQM1 = 101
3046 22:18:00.843139 DQ Delay:
3047 22:18:00.846049 DQ0 =108, DQ1 =110, DQ2 =110, DQ3 =110
3048 22:18:00.849373 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3049 22:18:00.852920 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3050 22:18:00.856200 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3051 22:18:00.856278
3052 22:18:00.856345
3053 22:18:00.865865 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3054 22:18:00.869622 CH0 RK1: MR19=403, MR18=12FA
3055 22:18:00.872739 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3056 22:18:00.875931 [RxdqsGatingPostProcess] freq 1200
3057 22:18:00.882567 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 22:18:00.885662 best DQS0 dly(2T, 0.5T) = (0, 12)
3059 22:18:00.889373 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 22:18:00.892995 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3061 22:18:00.895938 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 22:18:00.899298 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 22:18:00.902328 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 22:18:00.905456 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 22:18:00.908899 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 22:18:00.912504 Pre-setting of DQS Precalculation
3067 22:18:00.915373 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 22:18:00.915452 ==
3069 22:18:00.919100 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 22:18:00.922259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 22:18:00.922332 ==
3072 22:18:00.928783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 22:18:00.935593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 22:18:00.943200 [CA 0] Center 37 (7~67) winsize 61
3075 22:18:00.946386 [CA 1] Center 37 (7~68) winsize 62
3076 22:18:00.949958 [CA 2] Center 34 (4~64) winsize 61
3077 22:18:00.953046 [CA 3] Center 34 (4~64) winsize 61
3078 22:18:00.956168 [CA 4] Center 34 (4~64) winsize 61
3079 22:18:00.960001 [CA 5] Center 33 (3~63) winsize 61
3080 22:18:00.960078
3081 22:18:00.962710 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3082 22:18:00.962794
3083 22:18:00.966228 [CATrainingPosCal] consider 1 rank data
3084 22:18:00.969362 u2DelayCellTimex100 = 270/100 ps
3085 22:18:00.972517 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3086 22:18:00.979359 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 22:18:00.982566 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 22:18:00.985796 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 22:18:00.989045 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 22:18:00.992324 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3091 22:18:00.992399
3092 22:18:00.996046 CA PerBit enable=1, Macro0, CA PI delay=33
3093 22:18:00.996156
3094 22:18:00.999056 [CBTSetCACLKResult] CA Dly = 33
3095 22:18:01.002789 CS Dly: 5 (0~36)
3096 22:18:01.002888 ==
3097 22:18:01.006048 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 22:18:01.009382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 22:18:01.009484 ==
3100 22:18:01.015574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 22:18:01.019035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3102 22:18:01.028542 [CA 0] Center 37 (7~68) winsize 62
3103 22:18:01.031904 [CA 1] Center 37 (7~68) winsize 62
3104 22:18:01.034875 [CA 2] Center 34 (4~65) winsize 62
3105 22:18:01.038584 [CA 3] Center 33 (3~64) winsize 62
3106 22:18:01.042051 [CA 4] Center 34 (4~65) winsize 62
3107 22:18:01.045376 [CA 5] Center 33 (3~63) winsize 61
3108 22:18:01.045482
3109 22:18:01.048430 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3110 22:18:01.048513
3111 22:18:01.051506 [CATrainingPosCal] consider 2 rank data
3112 22:18:01.055151 u2DelayCellTimex100 = 270/100 ps
3113 22:18:01.058264 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3114 22:18:01.064705 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3115 22:18:01.067793 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 22:18:01.070986 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 22:18:01.074167 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 22:18:01.078139 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3119 22:18:01.078210
3120 22:18:01.081111 CA PerBit enable=1, Macro0, CA PI delay=33
3121 22:18:01.081180
3122 22:18:01.084396 [CBTSetCACLKResult] CA Dly = 33
3123 22:18:01.087585 CS Dly: 7 (0~40)
3124 22:18:01.087669
3125 22:18:01.091361 ----->DramcWriteLeveling(PI) begin...
3126 22:18:01.091430 ==
3127 22:18:01.094586 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 22:18:01.097774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 22:18:01.097875 ==
3130 22:18:01.100965 Write leveling (Byte 0): 25 => 25
3131 22:18:01.104520 Write leveling (Byte 1): 28 => 28
3132 22:18:01.107755 DramcWriteLeveling(PI) end<-----
3133 22:18:01.107831
3134 22:18:01.107897 ==
3135 22:18:01.110770 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 22:18:01.114393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 22:18:01.114474 ==
3138 22:18:01.117596 [Gating] SW mode calibration
3139 22:18:01.124471 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 22:18:01.131001 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 22:18:01.134447 0 15 0 | B1->B0 | 3232 3030 | 1 1 | (1 1) (0 0)
3142 22:18:01.137730 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 22:18:01.144057 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 22:18:01.147173 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 22:18:01.150757 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 22:18:01.157101 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 22:18:01.160779 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 22:18:01.163957 0 15 28 | B1->B0 | 3030 3434 | 0 0 | (0 1) (0 1)
3149 22:18:01.170468 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3150 22:18:01.173650 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 22:18:01.177041 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 22:18:01.184003 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 22:18:01.187167 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 22:18:01.190358 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 22:18:01.197238 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3156 22:18:01.200672 1 0 28 | B1->B0 | 3d3d 3838 | 0 0 | (1 1) (0 0)
3157 22:18:01.203797 1 1 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3158 22:18:01.210393 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:18:01.213546 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 22:18:01.216741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:18:01.223322 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 22:18:01.226545 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 22:18:01.230297 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 22:18:01.236538 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 22:18:01.240406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3166 22:18:01.243390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:18:01.249907 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:18:01.253054 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:18:01.256829 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:18:01.263259 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:18:01.266376 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:18:01.270072 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:18:01.276614 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:18:01.279849 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:18:01.283160 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:18:01.289576 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:18:01.293371 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 22:18:01.296523 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 22:18:01.303296 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 22:18:01.306665 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3181 22:18:01.309457 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 22:18:01.313087 Total UI for P1: 0, mck2ui 16
3183 22:18:01.316320 best dqsien dly found for B0: ( 1, 3, 28)
3184 22:18:01.319336 Total UI for P1: 0, mck2ui 16
3185 22:18:01.323105 best dqsien dly found for B1: ( 1, 3, 30)
3186 22:18:01.326366 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3187 22:18:01.329583 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3188 22:18:01.329669
3189 22:18:01.332632 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3190 22:18:01.339530 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3191 22:18:01.339612 [Gating] SW calibration Done
3192 22:18:01.339681 ==
3193 22:18:01.342547 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 22:18:01.349216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 22:18:01.349301 ==
3196 22:18:01.349372 RX Vref Scan: 0
3197 22:18:01.349434
3198 22:18:01.352727 RX Vref 0 -> 0, step: 1
3199 22:18:01.352812
3200 22:18:01.355991 RX Delay -40 -> 252, step: 8
3201 22:18:01.359328 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3202 22:18:01.362353 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3203 22:18:01.366016 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3204 22:18:01.372532 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3205 22:18:01.375791 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3206 22:18:01.379049 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3207 22:18:01.382764 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3208 22:18:01.385943 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3209 22:18:01.392271 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3210 22:18:01.395317 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3211 22:18:01.399102 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3212 22:18:01.402477 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3213 22:18:01.405743 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3214 22:18:01.412144 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3215 22:18:01.415263 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3216 22:18:01.418777 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3217 22:18:01.418884 ==
3218 22:18:01.421801 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 22:18:01.425282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 22:18:01.428381 ==
3221 22:18:01.428501 DQS Delay:
3222 22:18:01.428602 DQS0 = 0, DQS1 = 0
3223 22:18:01.432197 DQM Delay:
3224 22:18:01.432306 DQM0 = 113, DQM1 = 105
3225 22:18:01.435243 DQ Delay:
3226 22:18:01.438819 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3227 22:18:01.442022 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =107
3228 22:18:01.445062 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3229 22:18:01.448750 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3230 22:18:01.448862
3231 22:18:01.448967
3232 22:18:01.449070 ==
3233 22:18:01.452004 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 22:18:01.455228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 22:18:01.455334 ==
3236 22:18:01.455430
3237 22:18:01.455525
3238 22:18:01.458913 TX Vref Scan disable
3239 22:18:01.461803 == TX Byte 0 ==
3240 22:18:01.465386 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3241 22:18:01.468605 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3242 22:18:01.471880 == TX Byte 1 ==
3243 22:18:01.475320 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3244 22:18:01.478227 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3245 22:18:01.478330 ==
3246 22:18:01.482161 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 22:18:01.488435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 22:18:01.488518 ==
3249 22:18:01.498716 TX Vref=22, minBit 10, minWin=24, winSum=406
3250 22:18:01.501751 TX Vref=24, minBit 3, minWin=25, winSum=412
3251 22:18:01.504996 TX Vref=26, minBit 9, minWin=25, winSum=417
3252 22:18:01.508462 TX Vref=28, minBit 9, minWin=25, winSum=422
3253 22:18:01.512195 TX Vref=30, minBit 9, minWin=25, winSum=421
3254 22:18:01.518746 TX Vref=32, minBit 9, minWin=24, winSum=426
3255 22:18:01.521746 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
3256 22:18:01.521857
3257 22:18:01.525222 Final TX Range 1 Vref 28
3258 22:18:01.525331
3259 22:18:01.525424 ==
3260 22:18:01.528362 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 22:18:01.531470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 22:18:01.535265 ==
3263 22:18:01.535365
3264 22:18:01.535431
3265 22:18:01.535496 TX Vref Scan disable
3266 22:18:01.538518 == TX Byte 0 ==
3267 22:18:01.541760 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 22:18:01.548393 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 22:18:01.548501 == TX Byte 1 ==
3270 22:18:01.551490 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3271 22:18:01.557966 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3272 22:18:01.558086
3273 22:18:01.558195 [DATLAT]
3274 22:18:01.558308 Freq=1200, CH1 RK0
3275 22:18:01.558407
3276 22:18:01.561308 DATLAT Default: 0xd
3277 22:18:01.564717 0, 0xFFFF, sum = 0
3278 22:18:01.564802 1, 0xFFFF, sum = 0
3279 22:18:01.568294 2, 0xFFFF, sum = 0
3280 22:18:01.568378 3, 0xFFFF, sum = 0
3281 22:18:01.571620 4, 0xFFFF, sum = 0
3282 22:18:01.571708 5, 0xFFFF, sum = 0
3283 22:18:01.574590 6, 0xFFFF, sum = 0
3284 22:18:01.574692 7, 0xFFFF, sum = 0
3285 22:18:01.578080 8, 0xFFFF, sum = 0
3286 22:18:01.578164 9, 0xFFFF, sum = 0
3287 22:18:01.581604 10, 0xFFFF, sum = 0
3288 22:18:01.581718 11, 0xFFFF, sum = 0
3289 22:18:01.584735 12, 0x0, sum = 1
3290 22:18:01.584848 13, 0x0, sum = 2
3291 22:18:01.588102 14, 0x0, sum = 3
3292 22:18:01.588207 15, 0x0, sum = 4
3293 22:18:01.591109 best_step = 13
3294 22:18:01.591192
3295 22:18:01.591256 ==
3296 22:18:01.594415 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 22:18:01.597662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 22:18:01.597771 ==
3299 22:18:01.600813 RX Vref Scan: 1
3300 22:18:01.600915
3301 22:18:01.600979 Set Vref Range= 32 -> 127
3302 22:18:01.601049
3303 22:18:01.603986 RX Vref 32 -> 127, step: 1
3304 22:18:01.604065
3305 22:18:01.607843 RX Delay -21 -> 252, step: 4
3306 22:18:01.607943
3307 22:18:01.610970 Set Vref, RX VrefLevel [Byte0]: 32
3308 22:18:01.614097 [Byte1]: 32
3309 22:18:01.614169
3310 22:18:01.617225 Set Vref, RX VrefLevel [Byte0]: 33
3311 22:18:01.621101 [Byte1]: 33
3312 22:18:01.624688
3313 22:18:01.624773 Set Vref, RX VrefLevel [Byte0]: 34
3314 22:18:01.628339 [Byte1]: 34
3315 22:18:01.632870
3316 22:18:01.632981 Set Vref, RX VrefLevel [Byte0]: 35
3317 22:18:01.636176 [Byte1]: 35
3318 22:18:01.640726
3319 22:18:01.640845 Set Vref, RX VrefLevel [Byte0]: 36
3320 22:18:01.644116 [Byte1]: 36
3321 22:18:01.648455
3322 22:18:01.648573 Set Vref, RX VrefLevel [Byte0]: 37
3323 22:18:01.652025 [Byte1]: 37
3324 22:18:01.657033
3325 22:18:01.657158 Set Vref, RX VrefLevel [Byte0]: 38
3326 22:18:01.659748 [Byte1]: 38
3327 22:18:01.664288
3328 22:18:01.664389 Set Vref, RX VrefLevel [Byte0]: 39
3329 22:18:01.668039 [Byte1]: 39
3330 22:18:01.672397
3331 22:18:01.672505 Set Vref, RX VrefLevel [Byte0]: 40
3332 22:18:01.675653 [Byte1]: 40
3333 22:18:01.680424
3334 22:18:01.680532 Set Vref, RX VrefLevel [Byte0]: 41
3335 22:18:01.683352 [Byte1]: 41
3336 22:18:01.688304
3337 22:18:01.691315 Set Vref, RX VrefLevel [Byte0]: 42
3338 22:18:01.694849 [Byte1]: 42
3339 22:18:01.694950
3340 22:18:01.698105 Set Vref, RX VrefLevel [Byte0]: 43
3341 22:18:01.701324 [Byte1]: 43
3342 22:18:01.701405
3343 22:18:01.704398 Set Vref, RX VrefLevel [Byte0]: 44
3344 22:18:01.708199 [Byte1]: 44
3345 22:18:01.711974
3346 22:18:01.712050 Set Vref, RX VrefLevel [Byte0]: 45
3347 22:18:01.715128 [Byte1]: 45
3348 22:18:01.720180
3349 22:18:01.720256 Set Vref, RX VrefLevel [Byte0]: 46
3350 22:18:01.723352 [Byte1]: 46
3351 22:18:01.727886
3352 22:18:01.727966 Set Vref, RX VrefLevel [Byte0]: 47
3353 22:18:01.731033 [Byte1]: 47
3354 22:18:01.736024
3355 22:18:01.736109 Set Vref, RX VrefLevel [Byte0]: 48
3356 22:18:01.739162 [Byte1]: 48
3357 22:18:01.743837
3358 22:18:01.743928 Set Vref, RX VrefLevel [Byte0]: 49
3359 22:18:01.746908 [Byte1]: 49
3360 22:18:01.751469
3361 22:18:01.751580 Set Vref, RX VrefLevel [Byte0]: 50
3362 22:18:01.755029 [Byte1]: 50
3363 22:18:01.759201
3364 22:18:01.762707 Set Vref, RX VrefLevel [Byte0]: 51
3365 22:18:01.762845 [Byte1]: 51
3366 22:18:01.767734
3367 22:18:01.767831 Set Vref, RX VrefLevel [Byte0]: 52
3368 22:18:01.770836 [Byte1]: 52
3369 22:18:01.775425
3370 22:18:01.775515 Set Vref, RX VrefLevel [Byte0]: 53
3371 22:18:01.778462 [Byte1]: 53
3372 22:18:01.783664
3373 22:18:01.783747 Set Vref, RX VrefLevel [Byte0]: 54
3374 22:18:01.786392 [Byte1]: 54
3375 22:18:01.791225
3376 22:18:01.791308 Set Vref, RX VrefLevel [Byte0]: 55
3377 22:18:01.794157 [Byte1]: 55
3378 22:18:01.798843
3379 22:18:01.798934 Set Vref, RX VrefLevel [Byte0]: 56
3380 22:18:01.802337 [Byte1]: 56
3381 22:18:01.806724
3382 22:18:01.806837 Set Vref, RX VrefLevel [Byte0]: 57
3383 22:18:01.810424 [Byte1]: 57
3384 22:18:01.814970
3385 22:18:01.815052 Set Vref, RX VrefLevel [Byte0]: 58
3386 22:18:01.818150 [Byte1]: 58
3387 22:18:01.822664
3388 22:18:01.822749 Set Vref, RX VrefLevel [Byte0]: 59
3389 22:18:01.829468 [Byte1]: 59
3390 22:18:01.829564
3391 22:18:01.832634 Set Vref, RX VrefLevel [Byte0]: 60
3392 22:18:01.835778 [Byte1]: 60
3393 22:18:01.835862
3394 22:18:01.839415 Set Vref, RX VrefLevel [Byte0]: 61
3395 22:18:01.842588 [Byte1]: 61
3396 22:18:01.846400
3397 22:18:01.846508 Set Vref, RX VrefLevel [Byte0]: 62
3398 22:18:01.850257 [Byte1]: 62
3399 22:18:01.855015
3400 22:18:01.855093 Set Vref, RX VrefLevel [Byte0]: 63
3401 22:18:01.857912 [Byte1]: 63
3402 22:18:01.862422
3403 22:18:01.862516 Set Vref, RX VrefLevel [Byte0]: 64
3404 22:18:01.865536 [Byte1]: 64
3405 22:18:01.870188
3406 22:18:01.870298 Set Vref, RX VrefLevel [Byte0]: 65
3407 22:18:01.873634 [Byte1]: 65
3408 22:18:01.878207
3409 22:18:01.878313 Set Vref, RX VrefLevel [Byte0]: 66
3410 22:18:01.882150 [Byte1]: 66
3411 22:18:01.886250
3412 22:18:01.886358 Final RX Vref Byte 0 = 55 to rank0
3413 22:18:01.889367 Final RX Vref Byte 1 = 49 to rank0
3414 22:18:01.892647 Final RX Vref Byte 0 = 55 to rank1
3415 22:18:01.896331 Final RX Vref Byte 1 = 49 to rank1==
3416 22:18:01.899489 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 22:18:01.906129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 22:18:01.906216 ==
3419 22:18:01.906290 DQS Delay:
3420 22:18:01.909053 DQS0 = 0, DQS1 = 0
3421 22:18:01.909141 DQM Delay:
3422 22:18:01.909206 DQM0 = 114, DQM1 = 105
3423 22:18:01.912749 DQ Delay:
3424 22:18:01.915615 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3425 22:18:01.919353 DQ4 =110, DQ5 =122, DQ6 =128, DQ7 =112
3426 22:18:01.922542 DQ8 =92, DQ9 =98, DQ10 =106, DQ11 =100
3427 22:18:01.925924 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3428 22:18:01.926008
3429 22:18:01.926087
3430 22:18:01.935703 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3431 22:18:01.935793 CH1 RK0: MR19=303, MR18=EDF4
3432 22:18:01.942011 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3433 22:18:01.942094
3434 22:18:01.945776 ----->DramcWriteLeveling(PI) begin...
3435 22:18:01.945854 ==
3436 22:18:01.948888 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 22:18:01.955463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 22:18:01.955554 ==
3439 22:18:01.959243 Write leveling (Byte 0): 24 => 24
3440 22:18:01.962193 Write leveling (Byte 1): 26 => 26
3441 22:18:01.962296 DramcWriteLeveling(PI) end<-----
3442 22:18:01.962388
3443 22:18:01.965312 ==
3444 22:18:01.968578 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 22:18:01.971725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 22:18:01.971811 ==
3447 22:18:01.975415 [Gating] SW mode calibration
3448 22:18:01.981840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 22:18:01.984994 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 22:18:01.991828 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3451 22:18:01.995054 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 22:18:01.998240 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 22:18:02.004659 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 22:18:02.008220 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 22:18:02.011839 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 22:18:02.018225 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 1)
3457 22:18:02.021172 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
3458 22:18:02.025032 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 22:18:02.031432 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 22:18:02.034542 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 22:18:02.038276 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 22:18:02.044561 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 22:18:02.048097 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3464 22:18:02.051292 1 0 24 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
3465 22:18:02.057993 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 22:18:02.060972 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 22:18:02.064661 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 22:18:02.071233 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 22:18:02.074348 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 22:18:02.077659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 22:18:02.084263 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 22:18:02.087778 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3473 22:18:02.090747 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 22:18:02.097793 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 22:18:02.101103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 22:18:02.104112 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 22:18:02.110605 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 22:18:02.113798 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:18:02.117516 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:18:02.123635 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:18:02.127177 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:18:02.130448 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:18:02.137372 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:18:02.140556 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:18:02.143691 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 22:18:02.150004 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 22:18:02.153866 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3488 22:18:02.157077 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3489 22:18:02.163486 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3490 22:18:02.166537 Total UI for P1: 0, mck2ui 16
3491 22:18:02.170251 best dqsien dly found for B0: ( 1, 3, 22)
3492 22:18:02.173359 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 22:18:02.176547 Total UI for P1: 0, mck2ui 16
3494 22:18:02.179653 best dqsien dly found for B1: ( 1, 3, 26)
3495 22:18:02.183527 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3496 22:18:02.186597 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3497 22:18:02.186673
3498 22:18:02.189605 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3499 22:18:02.193257 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 22:18:02.196352 [Gating] SW calibration Done
3501 22:18:02.196430 ==
3502 22:18:02.199479 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 22:18:02.206038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 22:18:02.206125 ==
3505 22:18:02.206190 RX Vref Scan: 0
3506 22:18:02.206252
3507 22:18:02.209612 RX Vref 0 -> 0, step: 1
3508 22:18:02.209696
3509 22:18:02.212497 RX Delay -40 -> 252, step: 8
3510 22:18:02.216189 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3511 22:18:02.219324 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3512 22:18:02.222681 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3513 22:18:02.228712 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3514 22:18:02.232168 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3515 22:18:02.235634 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3516 22:18:02.239125 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3517 22:18:02.242206 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3518 22:18:02.248868 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3519 22:18:02.251867 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3520 22:18:02.255636 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3521 22:18:02.258651 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3522 22:18:02.261960 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3523 22:18:02.268773 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3524 22:18:02.272067 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3525 22:18:02.275154 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3526 22:18:02.275229 ==
3527 22:18:02.278308 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 22:18:02.281622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 22:18:02.284791 ==
3530 22:18:02.284872 DQS Delay:
3531 22:18:02.284934 DQS0 = 0, DQS1 = 0
3532 22:18:02.288019 DQM Delay:
3533 22:18:02.288096 DQM0 = 110, DQM1 = 105
3534 22:18:02.291174 DQ Delay:
3535 22:18:02.294951 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3536 22:18:02.298072 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3537 22:18:02.301204 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3538 22:18:02.305044 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3539 22:18:02.305118
3540 22:18:02.305179
3541 22:18:02.305237 ==
3542 22:18:02.308229 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 22:18:02.311277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 22:18:02.311352 ==
3545 22:18:02.311414
3546 22:18:02.314270
3547 22:18:02.314342 TX Vref Scan disable
3548 22:18:02.317721 == TX Byte 0 ==
3549 22:18:02.321445 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3550 22:18:02.324626 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3551 22:18:02.327577 == TX Byte 1 ==
3552 22:18:02.331057 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3553 22:18:02.334153 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3554 22:18:02.334257 ==
3555 22:18:02.337812 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 22:18:02.344319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 22:18:02.344398 ==
3558 22:18:02.354911 TX Vref=22, minBit 9, minWin=25, winSum=418
3559 22:18:02.357980 TX Vref=24, minBit 0, minWin=25, winSum=425
3560 22:18:02.361056 TX Vref=26, minBit 9, minWin=25, winSum=428
3561 22:18:02.364787 TX Vref=28, minBit 9, minWin=26, winSum=434
3562 22:18:02.367981 TX Vref=30, minBit 1, minWin=26, winSum=431
3563 22:18:02.374191 TX Vref=32, minBit 1, minWin=26, winSum=426
3564 22:18:02.377941 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3565 22:18:02.378016
3566 22:18:02.381074 Final TX Range 1 Vref 28
3567 22:18:02.381157
3568 22:18:02.381222 ==
3569 22:18:02.384293 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 22:18:02.390603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 22:18:02.390689 ==
3572 22:18:02.390814
3573 22:18:02.390906
3574 22:18:02.390982 TX Vref Scan disable
3575 22:18:02.394430 == TX Byte 0 ==
3576 22:18:02.397595 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3577 22:18:02.404895 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3578 22:18:02.405036 == TX Byte 1 ==
3579 22:18:02.407863 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3580 22:18:02.414158 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3581 22:18:02.414242
3582 22:18:02.414322 [DATLAT]
3583 22:18:02.414426 Freq=1200, CH1 RK1
3584 22:18:02.414582
3585 22:18:02.417413 DATLAT Default: 0xd
3586 22:18:02.421173 0, 0xFFFF, sum = 0
3587 22:18:02.421258 1, 0xFFFF, sum = 0
3588 22:18:02.424293 2, 0xFFFF, sum = 0
3589 22:18:02.424376 3, 0xFFFF, sum = 0
3590 22:18:02.427582 4, 0xFFFF, sum = 0
3591 22:18:02.427695 5, 0xFFFF, sum = 0
3592 22:18:02.430663 6, 0xFFFF, sum = 0
3593 22:18:02.430777 7, 0xFFFF, sum = 0
3594 22:18:02.433930 8, 0xFFFF, sum = 0
3595 22:18:02.434033 9, 0xFFFF, sum = 0
3596 22:18:02.437255 10, 0xFFFF, sum = 0
3597 22:18:02.437354 11, 0xFFFF, sum = 0
3598 22:18:02.440324 12, 0x0, sum = 1
3599 22:18:02.440438 13, 0x0, sum = 2
3600 22:18:02.443938 14, 0x0, sum = 3
3601 22:18:02.444047 15, 0x0, sum = 4
3602 22:18:02.447730 best_step = 13
3603 22:18:02.447808
3604 22:18:02.447872 ==
3605 22:18:02.450457 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 22:18:02.453842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 22:18:02.453952 ==
3608 22:18:02.457176 RX Vref Scan: 0
3609 22:18:02.457257
3610 22:18:02.457337 RX Vref 0 -> 0, step: 1
3611 22:18:02.457398
3612 22:18:02.460226 RX Delay -21 -> 252, step: 4
3613 22:18:02.466804 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3614 22:18:02.469959 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3615 22:18:02.473734 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3616 22:18:02.476965 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3617 22:18:02.480254 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3618 22:18:02.486645 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3619 22:18:02.489867 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3620 22:18:02.493031 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3621 22:18:02.496790 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3622 22:18:02.499958 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3623 22:18:02.506794 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3624 22:18:02.509646 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3625 22:18:02.512845 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3626 22:18:02.516612 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3627 22:18:02.522961 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3628 22:18:02.526209 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3629 22:18:02.526293 ==
3630 22:18:02.529905 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 22:18:02.532802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 22:18:02.532888 ==
3633 22:18:02.536387 DQS Delay:
3634 22:18:02.536472 DQS0 = 0, DQS1 = 0
3635 22:18:02.536539 DQM Delay:
3636 22:18:02.539423 DQM0 = 112, DQM1 = 109
3637 22:18:02.539539 DQ Delay:
3638 22:18:02.542574 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3639 22:18:02.546182 DQ4 =110, DQ5 =122, DQ6 =122, DQ7 =110
3640 22:18:02.549154 DQ8 =98, DQ9 =102, DQ10 =110, DQ11 =104
3641 22:18:02.556079 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3642 22:18:02.556165
3643 22:18:02.556231
3644 22:18:02.562526 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3645 22:18:02.566133 CH1 RK1: MR19=304, MR18=FB0B
3646 22:18:02.572705 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3647 22:18:02.575723 [RxdqsGatingPostProcess] freq 1200
3648 22:18:02.578918 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3649 22:18:02.582760 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 22:18:02.585907 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 22:18:02.589005 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 22:18:02.592228 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 22:18:02.595400 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 22:18:02.599237 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 22:18:02.602367 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 22:18:02.605562 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 22:18:02.608720 Pre-setting of DQS Precalculation
3658 22:18:02.612565 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3659 22:18:02.621825 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3660 22:18:02.628157 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3661 22:18:02.628242
3662 22:18:02.628310
3663 22:18:02.631397 [Calibration Summary] 2400 Mbps
3664 22:18:02.631480 CH 0, Rank 0
3665 22:18:02.635384 SW Impedance : PASS
3666 22:18:02.638231 DUTY Scan : NO K
3667 22:18:02.638308 ZQ Calibration : PASS
3668 22:18:02.641289 Jitter Meter : NO K
3669 22:18:02.644913 CBT Training : PASS
3670 22:18:02.645012 Write leveling : PASS
3671 22:18:02.648387 RX DQS gating : PASS
3672 22:18:02.651504 RX DQ/DQS(RDDQC) : PASS
3673 22:18:02.651609 TX DQ/DQS : PASS
3674 22:18:02.654529 RX DATLAT : PASS
3675 22:18:02.654638 RX DQ/DQS(Engine): PASS
3676 22:18:02.658204 TX OE : NO K
3677 22:18:02.658302 All Pass.
3678 22:18:02.658395
3679 22:18:02.661563 CH 0, Rank 1
3680 22:18:02.661662 SW Impedance : PASS
3681 22:18:02.664643 DUTY Scan : NO K
3682 22:18:02.668245 ZQ Calibration : PASS
3683 22:18:02.668316 Jitter Meter : NO K
3684 22:18:02.671208 CBT Training : PASS
3685 22:18:02.674715 Write leveling : PASS
3686 22:18:02.674837 RX DQS gating : PASS
3687 22:18:02.678005 RX DQ/DQS(RDDQC) : PASS
3688 22:18:02.680873 TX DQ/DQS : PASS
3689 22:18:02.680961 RX DATLAT : PASS
3690 22:18:02.684401 RX DQ/DQS(Engine): PASS
3691 22:18:02.687588 TX OE : NO K
3692 22:18:02.687678 All Pass.
3693 22:18:02.687744
3694 22:18:02.687802 CH 1, Rank 0
3695 22:18:02.690865 SW Impedance : PASS
3696 22:18:02.694690 DUTY Scan : NO K
3697 22:18:02.694810 ZQ Calibration : PASS
3698 22:18:02.697950 Jitter Meter : NO K
3699 22:18:02.701196 CBT Training : PASS
3700 22:18:02.701284 Write leveling : PASS
3701 22:18:02.704427 RX DQS gating : PASS
3702 22:18:02.707604 RX DQ/DQS(RDDQC) : PASS
3703 22:18:02.707684 TX DQ/DQS : PASS
3704 22:18:02.710693 RX DATLAT : PASS
3705 22:18:02.713848 RX DQ/DQS(Engine): PASS
3706 22:18:02.713928 TX OE : NO K
3707 22:18:02.717548 All Pass.
3708 22:18:02.717628
3709 22:18:02.717692 CH 1, Rank 1
3710 22:18:02.720758 SW Impedance : PASS
3711 22:18:02.720839 DUTY Scan : NO K
3712 22:18:02.723813 ZQ Calibration : PASS
3713 22:18:02.727081 Jitter Meter : NO K
3714 22:18:02.727161 CBT Training : PASS
3715 22:18:02.731030 Write leveling : PASS
3716 22:18:02.731112 RX DQS gating : PASS
3717 22:18:02.734265 RX DQ/DQS(RDDQC) : PASS
3718 22:18:02.737393 TX DQ/DQS : PASS
3719 22:18:02.737475 RX DATLAT : PASS
3720 22:18:02.740534 RX DQ/DQS(Engine): PASS
3721 22:18:02.743774 TX OE : NO K
3722 22:18:02.743857 All Pass.
3723 22:18:02.743922
3724 22:18:02.746767 DramC Write-DBI off
3725 22:18:02.746890 PER_BANK_REFRESH: Hybrid Mode
3726 22:18:02.750393 TX_TRACKING: ON
3727 22:18:02.760435 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3728 22:18:02.763906 [FAST_K] Save calibration result to emmc
3729 22:18:02.767066 dramc_set_vcore_voltage set vcore to 650000
3730 22:18:02.770367 Read voltage for 600, 5
3731 22:18:02.770452 Vio18 = 0
3732 22:18:02.770517 Vcore = 650000
3733 22:18:02.770577 Vdram = 0
3734 22:18:02.773351 Vddq = 0
3735 22:18:02.773426 Vmddr = 0
3736 22:18:02.779866 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3737 22:18:02.783365 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3738 22:18:02.786860 MEM_TYPE=3, freq_sel=19
3739 22:18:02.789763 sv_algorithm_assistance_LP4_1600
3740 22:18:02.793439 ============ PULL DRAM RESETB DOWN ============
3741 22:18:02.796606 ========== PULL DRAM RESETB DOWN end =========
3742 22:18:02.803076 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3743 22:18:02.806290 ===================================
3744 22:18:02.806399 LPDDR4 DRAM CONFIGURATION
3745 22:18:02.810055 ===================================
3746 22:18:02.813179 EX_ROW_EN[0] = 0x0
3747 22:18:02.816392 EX_ROW_EN[1] = 0x0
3748 22:18:02.816465 LP4Y_EN = 0x0
3749 22:18:02.819612 WORK_FSP = 0x0
3750 22:18:02.819696 WL = 0x2
3751 22:18:02.823216 RL = 0x2
3752 22:18:02.823302 BL = 0x2
3753 22:18:02.826184 RPST = 0x0
3754 22:18:02.826282 RD_PRE = 0x0
3755 22:18:02.829413 WR_PRE = 0x1
3756 22:18:02.829520 WR_PST = 0x0
3757 22:18:02.832614 DBI_WR = 0x0
3758 22:18:02.832718 DBI_RD = 0x0
3759 22:18:02.836327 OTF = 0x1
3760 22:18:02.839615 ===================================
3761 22:18:02.842940 ===================================
3762 22:18:02.843045 ANA top config
3763 22:18:02.845857 ===================================
3764 22:18:02.849183 DLL_ASYNC_EN = 0
3765 22:18:02.853072 ALL_SLAVE_EN = 1
3766 22:18:02.856206 NEW_RANK_MODE = 1
3767 22:18:02.856299 DLL_IDLE_MODE = 1
3768 22:18:02.859086 LP45_APHY_COMB_EN = 1
3769 22:18:02.862689 TX_ODT_DIS = 1
3770 22:18:02.865935 NEW_8X_MODE = 1
3771 22:18:02.869276 ===================================
3772 22:18:02.872700 ===================================
3773 22:18:02.875827 data_rate = 1200
3774 22:18:02.878758 CKR = 1
3775 22:18:02.878864 DQ_P2S_RATIO = 8
3776 22:18:02.882428 ===================================
3777 22:18:02.885586 CA_P2S_RATIO = 8
3778 22:18:02.888830 DQ_CA_OPEN = 0
3779 22:18:02.892424 DQ_SEMI_OPEN = 0
3780 22:18:02.895145 CA_SEMI_OPEN = 0
3781 22:18:02.898453 CA_FULL_RATE = 0
3782 22:18:02.898536 DQ_CKDIV4_EN = 1
3783 22:18:02.902277 CA_CKDIV4_EN = 1
3784 22:18:02.905452 CA_PREDIV_EN = 0
3785 22:18:02.908710 PH8_DLY = 0
3786 22:18:02.911961 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3787 22:18:02.915207 DQ_AAMCK_DIV = 4
3788 22:18:02.915289 CA_AAMCK_DIV = 4
3789 22:18:02.918375 CA_ADMCK_DIV = 4
3790 22:18:02.921703 DQ_TRACK_CA_EN = 0
3791 22:18:02.925191 CA_PICK = 600
3792 22:18:02.928109 CA_MCKIO = 600
3793 22:18:02.931340 MCKIO_SEMI = 0
3794 22:18:02.934534 PLL_FREQ = 2288
3795 22:18:02.937781 DQ_UI_PI_RATIO = 32
3796 22:18:02.937889 CA_UI_PI_RATIO = 0
3797 22:18:02.941252 ===================================
3798 22:18:02.944866 ===================================
3799 22:18:02.948008 memory_type:LPDDR4
3800 22:18:02.951155 GP_NUM : 10
3801 22:18:02.951238 SRAM_EN : 1
3802 22:18:02.954493 MD32_EN : 0
3803 22:18:02.957374 ===================================
3804 22:18:02.961260 [ANA_INIT] >>>>>>>>>>>>>>
3805 22:18:02.964457 <<<<<< [CONFIGURE PHASE]: ANA_TX
3806 22:18:02.967412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3807 22:18:02.971079 ===================================
3808 22:18:02.971161 data_rate = 1200,PCW = 0X5800
3809 22:18:02.974116 ===================================
3810 22:18:02.977636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3811 22:18:02.983863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 22:18:02.990572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 22:18:02.993817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3814 22:18:02.997353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3815 22:18:03.000293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3816 22:18:03.003838 [ANA_INIT] flow start
3817 22:18:03.006730 [ANA_INIT] PLL >>>>>>>>
3818 22:18:03.006811 [ANA_INIT] PLL <<<<<<<<
3819 22:18:03.010425 [ANA_INIT] MIDPI >>>>>>>>
3820 22:18:03.013711 [ANA_INIT] MIDPI <<<<<<<<
3821 22:18:03.016830 [ANA_INIT] DLL >>>>>>>>
3822 22:18:03.016911 [ANA_INIT] flow end
3823 22:18:03.020007 ============ LP4 DIFF to SE enter ============
3824 22:18:03.026724 ============ LP4 DIFF to SE exit ============
3825 22:18:03.026808 [ANA_INIT] <<<<<<<<<<<<<
3826 22:18:03.029793 [Flow] Enable top DCM control >>>>>
3827 22:18:03.033406 [Flow] Enable top DCM control <<<<<
3828 22:18:03.036646 Enable DLL master slave shuffle
3829 22:18:03.043202 ==============================================================
3830 22:18:03.043284 Gating Mode config
3831 22:18:03.049506 ==============================================================
3832 22:18:03.053278 Config description:
3833 22:18:03.062739 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3834 22:18:03.069704 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3835 22:18:03.073101 SELPH_MODE 0: By rank 1: By Phase
3836 22:18:03.079134 ==============================================================
3837 22:18:03.082754 GAT_TRACK_EN = 1
3838 22:18:03.086328 RX_GATING_MODE = 2
3839 22:18:03.089133 RX_GATING_TRACK_MODE = 2
3840 22:18:03.089214 SELPH_MODE = 1
3841 22:18:03.092701 PICG_EARLY_EN = 1
3842 22:18:03.095885 VALID_LAT_VALUE = 1
3843 22:18:03.102243 ==============================================================
3844 22:18:03.105807 Enter into Gating configuration >>>>
3845 22:18:03.108786 Exit from Gating configuration <<<<
3846 22:18:03.112358 Enter into DVFS_PRE_config >>>>>
3847 22:18:03.122512 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3848 22:18:03.125676 Exit from DVFS_PRE_config <<<<<
3849 22:18:03.128855 Enter into PICG configuration >>>>
3850 22:18:03.132092 Exit from PICG configuration <<<<
3851 22:18:03.135220 [RX_INPUT] configuration >>>>>
3852 22:18:03.138784 [RX_INPUT] configuration <<<<<
3853 22:18:03.141988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3854 22:18:03.148493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3855 22:18:03.155420 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3856 22:18:03.161549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3857 22:18:03.168636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3858 22:18:03.171799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3859 22:18:03.178525 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3860 22:18:03.181568 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3861 22:18:03.184914 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3862 22:18:03.187998 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3863 22:18:03.194745 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3864 22:18:03.197788 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3865 22:18:03.201648 ===================================
3866 22:18:03.204785 LPDDR4 DRAM CONFIGURATION
3867 22:18:03.207976 ===================================
3868 22:18:03.208058 EX_ROW_EN[0] = 0x0
3869 22:18:03.210966 EX_ROW_EN[1] = 0x0
3870 22:18:03.211047 LP4Y_EN = 0x0
3871 22:18:03.214506 WORK_FSP = 0x0
3872 22:18:03.214605 WL = 0x2
3873 22:18:03.218135 RL = 0x2
3874 22:18:03.221173 BL = 0x2
3875 22:18:03.221255 RPST = 0x0
3876 22:18:03.224612 RD_PRE = 0x0
3877 22:18:03.224694 WR_PRE = 0x1
3878 22:18:03.227810 WR_PST = 0x0
3879 22:18:03.227892 DBI_WR = 0x0
3880 22:18:03.231294 DBI_RD = 0x0
3881 22:18:03.231377 OTF = 0x1
3882 22:18:03.234412 ===================================
3883 22:18:03.237574 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3884 22:18:03.244358 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3885 22:18:03.247731 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3886 22:18:03.250901 ===================================
3887 22:18:03.254254 LPDDR4 DRAM CONFIGURATION
3888 22:18:03.257390 ===================================
3889 22:18:03.257472 EX_ROW_EN[0] = 0x10
3890 22:18:03.260613 EX_ROW_EN[1] = 0x0
3891 22:18:03.260694 LP4Y_EN = 0x0
3892 22:18:03.264274 WORK_FSP = 0x0
3893 22:18:03.267464 WL = 0x2
3894 22:18:03.267545 RL = 0x2
3895 22:18:03.270670 BL = 0x2
3896 22:18:03.270751 RPST = 0x0
3897 22:18:03.273796 RD_PRE = 0x0
3898 22:18:03.273876 WR_PRE = 0x1
3899 22:18:03.277658 WR_PST = 0x0
3900 22:18:03.277739 DBI_WR = 0x0
3901 22:18:03.280630 DBI_RD = 0x0
3902 22:18:03.280712 OTF = 0x1
3903 22:18:03.283661 ===================================
3904 22:18:03.290042 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3905 22:18:03.294397 nWR fixed to 30
3906 22:18:03.297524 [ModeRegInit_LP4] CH0 RK0
3907 22:18:03.297599 [ModeRegInit_LP4] CH0 RK1
3908 22:18:03.301074 [ModeRegInit_LP4] CH1 RK0
3909 22:18:03.304823 [ModeRegInit_LP4] CH1 RK1
3910 22:18:03.304896 match AC timing 17
3911 22:18:03.311078 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3912 22:18:03.314043 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3913 22:18:03.317658 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3914 22:18:03.323984 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3915 22:18:03.327605 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3916 22:18:03.327680 ==
3917 22:18:03.330508 Dram Type= 6, Freq= 0, CH_0, rank 0
3918 22:18:03.334033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3919 22:18:03.334111 ==
3920 22:18:03.340490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3921 22:18:03.347334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3922 22:18:03.350451 [CA 0] Center 37 (7~67) winsize 61
3923 22:18:03.353600 [CA 1] Center 37 (7~67) winsize 61
3924 22:18:03.357352 [CA 2] Center 35 (5~65) winsize 61
3925 22:18:03.360551 [CA 3] Center 35 (5~65) winsize 61
3926 22:18:03.363750 [CA 4] Center 34 (4~65) winsize 62
3927 22:18:03.366885 [CA 5] Center 34 (4~64) winsize 61
3928 22:18:03.366968
3929 22:18:03.370368 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3930 22:18:03.370444
3931 22:18:03.373519 [CATrainingPosCal] consider 1 rank data
3932 22:18:03.376712 u2DelayCellTimex100 = 270/100 ps
3933 22:18:03.379995 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3934 22:18:03.383777 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3935 22:18:03.386687 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3936 22:18:03.392995 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3937 22:18:03.396793 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3938 22:18:03.399977 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3939 22:18:03.400049
3940 22:18:03.403119 CA PerBit enable=1, Macro0, CA PI delay=34
3941 22:18:03.403189
3942 22:18:03.406214 [CBTSetCACLKResult] CA Dly = 34
3943 22:18:03.406282 CS Dly: 4 (0~35)
3944 22:18:03.406341 ==
3945 22:18:03.409795 Dram Type= 6, Freq= 0, CH_0, rank 1
3946 22:18:03.416236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 22:18:03.416312 ==
3948 22:18:03.419400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3949 22:18:03.426088 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3950 22:18:03.429703 [CA 0] Center 37 (7~67) winsize 61
3951 22:18:03.433287 [CA 1] Center 37 (7~67) winsize 61
3952 22:18:03.436253 [CA 2] Center 35 (5~65) winsize 61
3953 22:18:03.439989 [CA 3] Center 35 (5~65) winsize 61
3954 22:18:03.443028 [CA 4] Center 34 (4~65) winsize 62
3955 22:18:03.446372 [CA 5] Center 33 (3~64) winsize 62
3956 22:18:03.446447
3957 22:18:03.449830 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3958 22:18:03.449912
3959 22:18:03.452937 [CATrainingPosCal] consider 2 rank data
3960 22:18:03.456250 u2DelayCellTimex100 = 270/100 ps
3961 22:18:03.459341 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3962 22:18:03.465862 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3963 22:18:03.469562 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3964 22:18:03.472571 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3965 22:18:03.475692 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3966 22:18:03.479047 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3967 22:18:03.479129
3968 22:18:03.482211 CA PerBit enable=1, Macro0, CA PI delay=34
3969 22:18:03.482293
3970 22:18:03.486035 [CBTSetCACLKResult] CA Dly = 34
3971 22:18:03.489175 CS Dly: 5 (0~38)
3972 22:18:03.489257
3973 22:18:03.492285 ----->DramcWriteLeveling(PI) begin...
3974 22:18:03.492369 ==
3975 22:18:03.495410 Dram Type= 6, Freq= 0, CH_0, rank 0
3976 22:18:03.499220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 22:18:03.499304 ==
3978 22:18:03.502428 Write leveling (Byte 0): 34 => 34
3979 22:18:03.505591 Write leveling (Byte 1): 29 => 29
3980 22:18:03.508712 DramcWriteLeveling(PI) end<-----
3981 22:18:03.508795
3982 22:18:03.508860 ==
3983 22:18:03.512548 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 22:18:03.515442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 22:18:03.515526 ==
3986 22:18:03.518664 [Gating] SW mode calibration
3987 22:18:03.525431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3988 22:18:03.531617 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3989 22:18:03.535516 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 22:18:03.538539 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 22:18:03.545153 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 22:18:03.548172 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3993 22:18:03.554635 0 9 16 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (1 1)
3994 22:18:03.558261 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 22:18:03.561650 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 22:18:03.567745 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 22:18:03.571642 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 22:18:03.574777 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:18:03.580860 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:18:03.584133 0 10 12 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (1 1)
4001 22:18:03.587807 0 10 16 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
4002 22:18:03.594107 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4003 22:18:03.597793 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 22:18:03.601039 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 22:18:03.607491 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 22:18:03.610793 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:18:03.614316 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:18:03.620558 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4009 22:18:03.623847 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4010 22:18:03.627538 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:18:03.634128 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 22:18:03.636952 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 22:18:03.640678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:18:03.647515 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:18:03.650487 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:18:03.653557 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:18:03.660229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:18:03.663798 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:18:03.666845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:18:03.673345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:18:03.676401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:18:03.680073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:18:03.686403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:18:03.689638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4025 22:18:03.692831 Total UI for P1: 0, mck2ui 16
4026 22:18:03.696617 best dqsien dly found for B0: ( 0, 13, 10)
4027 22:18:03.699733 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4028 22:18:03.703436 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 22:18:03.706588 Total UI for P1: 0, mck2ui 16
4030 22:18:03.709748 best dqsien dly found for B1: ( 0, 13, 16)
4031 22:18:03.716211 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4032 22:18:03.719411 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4033 22:18:03.719493
4034 22:18:03.722571 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4035 22:18:03.726342 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4036 22:18:03.729634 [Gating] SW calibration Done
4037 22:18:03.729715 ==
4038 22:18:03.732774 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 22:18:03.736002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 22:18:03.736084 ==
4041 22:18:03.739301 RX Vref Scan: 0
4042 22:18:03.739382
4043 22:18:03.739446 RX Vref 0 -> 0, step: 1
4044 22:18:03.739505
4045 22:18:03.742602 RX Delay -230 -> 252, step: 16
4046 22:18:03.748958 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4047 22:18:03.752595 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4048 22:18:03.755630 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4049 22:18:03.759055 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4050 22:18:03.762132 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4051 22:18:03.769128 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4052 22:18:03.772172 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4053 22:18:03.775297 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4054 22:18:03.778504 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4055 22:18:03.785271 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4056 22:18:03.788403 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4057 22:18:03.791601 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4058 22:18:03.794806 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4059 22:18:03.801776 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4060 22:18:03.804901 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4061 22:18:03.808096 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4062 22:18:03.808178 ==
4063 22:18:03.811363 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 22:18:03.817967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 22:18:03.818051 ==
4066 22:18:03.818116 DQS Delay:
4067 22:18:03.821089 DQS0 = 0, DQS1 = 0
4068 22:18:03.821164 DQM Delay:
4069 22:18:03.821225 DQM0 = 38, DQM1 = 30
4070 22:18:03.824832 DQ Delay:
4071 22:18:03.827985 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4072 22:18:03.831146 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4073 22:18:03.834459 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4074 22:18:03.837535 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4075 22:18:03.837619
4076 22:18:03.837683
4077 22:18:03.837742 ==
4078 22:18:03.840727 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 22:18:03.843930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 22:18:03.844006 ==
4081 22:18:03.844069
4082 22:18:03.844127
4083 22:18:03.847775 TX Vref Scan disable
4084 22:18:03.850713 == TX Byte 0 ==
4085 22:18:03.853759 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4086 22:18:03.857411 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4087 22:18:03.860285 == TX Byte 1 ==
4088 22:18:03.863915 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4089 22:18:03.866901 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4090 22:18:03.866976 ==
4091 22:18:03.870326 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 22:18:03.876708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 22:18:03.876791 ==
4094 22:18:03.876855
4095 22:18:03.876914
4096 22:18:03.876978 TX Vref Scan disable
4097 22:18:03.881582 == TX Byte 0 ==
4098 22:18:03.884786 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4099 22:18:03.891173 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4100 22:18:03.891281 == TX Byte 1 ==
4101 22:18:03.894255 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4102 22:18:03.901474 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4103 22:18:03.901558
4104 22:18:03.901622 [DATLAT]
4105 22:18:03.901700 Freq=600, CH0 RK0
4106 22:18:03.901759
4107 22:18:03.904672 DATLAT Default: 0x9
4108 22:18:03.907848 0, 0xFFFF, sum = 0
4109 22:18:03.907930 1, 0xFFFF, sum = 0
4110 22:18:03.910895 2, 0xFFFF, sum = 0
4111 22:18:03.910978 3, 0xFFFF, sum = 0
4112 22:18:03.914127 4, 0xFFFF, sum = 0
4113 22:18:03.914209 5, 0xFFFF, sum = 0
4114 22:18:03.917494 6, 0xFFFF, sum = 0
4115 22:18:03.917577 7, 0xFFFF, sum = 0
4116 22:18:03.921019 8, 0x0, sum = 1
4117 22:18:03.921102 9, 0x0, sum = 2
4118 22:18:03.924261 10, 0x0, sum = 3
4119 22:18:03.924343 11, 0x0, sum = 4
4120 22:18:03.924409 best_step = 9
4121 22:18:03.924468
4122 22:18:03.927612 ==
4123 22:18:03.930606 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 22:18:03.933695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 22:18:03.933780 ==
4126 22:18:03.933844 RX Vref Scan: 1
4127 22:18:03.933904
4128 22:18:03.937537 RX Vref 0 -> 0, step: 1
4129 22:18:03.937618
4130 22:18:03.940697 RX Delay -195 -> 252, step: 8
4131 22:18:03.940778
4132 22:18:03.943934 Set Vref, RX VrefLevel [Byte0]: 60
4133 22:18:03.947181 [Byte1]: 54
4134 22:18:03.947263
4135 22:18:03.950253 Final RX Vref Byte 0 = 60 to rank0
4136 22:18:03.953957 Final RX Vref Byte 1 = 54 to rank0
4137 22:18:03.957094 Final RX Vref Byte 0 = 60 to rank1
4138 22:18:03.960606 Final RX Vref Byte 1 = 54 to rank1==
4139 22:18:03.963825 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 22:18:03.970046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 22:18:03.970130 ==
4142 22:18:03.970195 DQS Delay:
4143 22:18:03.970255 DQS0 = 0, DQS1 = 0
4144 22:18:03.973665 DQM Delay:
4145 22:18:03.973747 DQM0 = 34, DQM1 = 29
4146 22:18:03.976558 DQ Delay:
4147 22:18:03.980154 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4148 22:18:03.983095 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4149 22:18:03.986597 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4150 22:18:03.990112 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4151 22:18:03.990194
4152 22:18:03.990258
4153 22:18:03.996882 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4154 22:18:04.000225 CH0 RK0: MR19=808, MR18=3838
4155 22:18:04.006526 CH0_RK0: MR19=0x808, MR18=0x3838, DQSOSC=399, MR23=63, INC=164, DEC=109
4156 22:18:04.006610
4157 22:18:04.009811 ----->DramcWriteLeveling(PI) begin...
4158 22:18:04.009894 ==
4159 22:18:04.012834 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 22:18:04.016151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 22:18:04.016235 ==
4162 22:18:04.019801 Write leveling (Byte 0): 30 => 30
4163 22:18:04.022889 Write leveling (Byte 1): 33 => 33
4164 22:18:04.026227 DramcWriteLeveling(PI) end<-----
4165 22:18:04.026309
4166 22:18:04.026373 ==
4167 22:18:04.029455 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 22:18:04.032573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 22:18:04.036361 ==
4170 22:18:04.036443 [Gating] SW mode calibration
4171 22:18:04.042789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 22:18:04.049125 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 22:18:04.052915 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 22:18:04.059294 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 22:18:04.062221 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 22:18:04.065943 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 1) (1 1)
4177 22:18:04.072059 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4178 22:18:04.075243 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 22:18:04.079027 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 22:18:04.085372 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 22:18:04.088875 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 22:18:04.091784 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 22:18:04.098907 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4184 22:18:04.101796 0 10 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
4185 22:18:04.104868 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4186 22:18:04.111861 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 22:18:04.115130 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 22:18:04.118234 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 22:18:04.124915 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 22:18:04.128156 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:18:04.131408 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4192 22:18:04.138298 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4193 22:18:04.141310 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4194 22:18:04.144709 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:18:04.151625 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:18:04.154723 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:18:04.157851 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:18:04.164868 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:18:04.168099 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:18:04.171211 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:18:04.177754 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:18:04.181398 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:18:04.184522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:18:04.190951 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:18:04.194453 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:18:04.197829 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:18:04.203919 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:18:04.207320 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4209 22:18:04.210635 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 22:18:04.214280 Total UI for P1: 0, mck2ui 16
4211 22:18:04.217594 best dqsien dly found for B0: ( 0, 13, 12)
4212 22:18:04.220732 Total UI for P1: 0, mck2ui 16
4213 22:18:04.224269 best dqsien dly found for B1: ( 0, 13, 14)
4214 22:18:04.227195 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4215 22:18:04.230368 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4216 22:18:04.233686
4217 22:18:04.236848 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4218 22:18:04.240577 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4219 22:18:04.243685 [Gating] SW calibration Done
4220 22:18:04.243801 ==
4221 22:18:04.247250 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 22:18:04.250592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 22:18:04.250681 ==
4224 22:18:04.250745 RX Vref Scan: 0
4225 22:18:04.253679
4226 22:18:04.253800 RX Vref 0 -> 0, step: 1
4227 22:18:04.253912
4228 22:18:04.256906 RX Delay -230 -> 252, step: 16
4229 22:18:04.260267 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4230 22:18:04.267063 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4231 22:18:04.270102 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4232 22:18:04.273458 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4233 22:18:04.276706 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4234 22:18:04.282997 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4235 22:18:04.286531 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4236 22:18:04.289687 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4237 22:18:04.292937 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4238 22:18:04.296589 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4239 22:18:04.303068 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4240 22:18:04.306485 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4241 22:18:04.309399 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4242 22:18:04.312733 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4243 22:18:04.319847 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4244 22:18:04.322758 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4245 22:18:04.322845 ==
4246 22:18:04.325958 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 22:18:04.329263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 22:18:04.329348 ==
4249 22:18:04.332881 DQS Delay:
4250 22:18:04.332969 DQS0 = 0, DQS1 = 0
4251 22:18:04.333039 DQM Delay:
4252 22:18:04.336013 DQM0 = 35, DQM1 = 29
4253 22:18:04.336092 DQ Delay:
4254 22:18:04.339359 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4255 22:18:04.342674 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4256 22:18:04.345938 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4257 22:18:04.348972 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4258 22:18:04.349052
4259 22:18:04.349155
4260 22:18:04.352735 ==
4261 22:18:04.352822 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 22:18:04.359156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 22:18:04.359240 ==
4264 22:18:04.359306
4265 22:18:04.359367
4266 22:18:04.362283 TX Vref Scan disable
4267 22:18:04.362366 == TX Byte 0 ==
4268 22:18:04.368673 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 22:18:04.372509 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 22:18:04.372594 == TX Byte 1 ==
4271 22:18:04.378461 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4272 22:18:04.381862 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4273 22:18:04.381946 ==
4274 22:18:04.385108 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 22:18:04.388338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 22:18:04.388423 ==
4277 22:18:04.388489
4278 22:18:04.388550
4279 22:18:04.391919 TX Vref Scan disable
4280 22:18:04.395253 == TX Byte 0 ==
4281 22:18:04.398360 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4282 22:18:04.401500 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4283 22:18:04.405080 == TX Byte 1 ==
4284 22:18:04.408245 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4285 22:18:04.411328 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4286 22:18:04.415118
4287 22:18:04.415226 [DATLAT]
4288 22:18:04.415325 Freq=600, CH0 RK1
4289 22:18:04.415391
4290 22:18:04.418301 DATLAT Default: 0x9
4291 22:18:04.418384 0, 0xFFFF, sum = 0
4292 22:18:04.421736 1, 0xFFFF, sum = 0
4293 22:18:04.421850 2, 0xFFFF, sum = 0
4294 22:18:04.424811 3, 0xFFFF, sum = 0
4295 22:18:04.427863 4, 0xFFFF, sum = 0
4296 22:18:04.427981 5, 0xFFFF, sum = 0
4297 22:18:04.431415 6, 0xFFFF, sum = 0
4298 22:18:04.431507 7, 0xFFFF, sum = 0
4299 22:18:04.434513 8, 0x0, sum = 1
4300 22:18:04.434638 9, 0x0, sum = 2
4301 22:18:04.434754 10, 0x0, sum = 3
4302 22:18:04.437873 11, 0x0, sum = 4
4303 22:18:04.437980 best_step = 9
4304 22:18:04.438074
4305 22:18:04.438176 ==
4306 22:18:04.441078 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 22:18:04.447618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 22:18:04.447737 ==
4309 22:18:04.447833 RX Vref Scan: 0
4310 22:18:04.447934
4311 22:18:04.450989 RX Vref 0 -> 0, step: 1
4312 22:18:04.451096
4313 22:18:04.454110 RX Delay -195 -> 252, step: 8
4314 22:18:04.460694 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4315 22:18:04.464502 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4316 22:18:04.467709 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4317 22:18:04.471015 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4318 22:18:04.474128 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4319 22:18:04.480451 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4320 22:18:04.484279 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4321 22:18:04.487473 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4322 22:18:04.490603 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4323 22:18:04.496925 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4324 22:18:04.500546 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4325 22:18:04.503472 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4326 22:18:04.506838 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4327 22:18:04.513432 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4328 22:18:04.517139 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4329 22:18:04.520062 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4330 22:18:04.520173 ==
4331 22:18:04.523582 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 22:18:04.526990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 22:18:04.530534 ==
4334 22:18:04.530639 DQS Delay:
4335 22:18:04.530731 DQS0 = 0, DQS1 = 0
4336 22:18:04.533586 DQM Delay:
4337 22:18:04.533691 DQM0 = 33, DQM1 = 28
4338 22:18:04.536888 DQ Delay:
4339 22:18:04.536991 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4340 22:18:04.540394 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4341 22:18:04.543470 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4342 22:18:04.546832 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4343 22:18:04.546912
4344 22:18:04.550411
4345 22:18:04.556574 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4346 22:18:04.559659 CH0 RK1: MR19=808, MR18=6E3D
4347 22:18:04.566544 CH0_RK1: MR19=0x808, MR18=0x6E3D, DQSOSC=389, MR23=63, INC=173, DEC=115
4348 22:18:04.569961 [RxdqsGatingPostProcess] freq 600
4349 22:18:04.573291 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 22:18:04.576272 Pre-setting of DQS Precalculation
4351 22:18:04.583257 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 22:18:04.583351 ==
4353 22:18:04.586460 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 22:18:04.589628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 22:18:04.589701 ==
4356 22:18:04.596198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 22:18:04.599398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4358 22:18:04.603794 [CA 0] Center 35 (5~66) winsize 62
4359 22:18:04.607351 [CA 1] Center 36 (6~66) winsize 61
4360 22:18:04.610363 [CA 2] Center 34 (4~65) winsize 62
4361 22:18:04.613629 [CA 3] Center 34 (3~65) winsize 63
4362 22:18:04.617113 [CA 4] Center 34 (4~65) winsize 62
4363 22:18:04.620670 [CA 5] Center 33 (3~64) winsize 62
4364 22:18:04.620747
4365 22:18:04.623751 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4366 22:18:04.623862
4367 22:18:04.626902 [CATrainingPosCal] consider 1 rank data
4368 22:18:04.629978 u2DelayCellTimex100 = 270/100 ps
4369 22:18:04.633448 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 22:18:04.640372 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4371 22:18:04.643302 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 22:18:04.646775 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4373 22:18:04.650353 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 22:18:04.653412 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 22:18:04.653511
4376 22:18:04.656914 CA PerBit enable=1, Macro0, CA PI delay=33
4377 22:18:04.657010
4378 22:18:04.659879 [CBTSetCACLKResult] CA Dly = 33
4379 22:18:04.663521 CS Dly: 5 (0~36)
4380 22:18:04.663602 ==
4381 22:18:04.666683 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 22:18:04.669932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 22:18:04.670038 ==
4384 22:18:04.676200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 22:18:04.679441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4386 22:18:04.683807 [CA 0] Center 36 (6~66) winsize 61
4387 22:18:04.687033 [CA 1] Center 35 (5~66) winsize 62
4388 22:18:04.690280 [CA 2] Center 34 (4~65) winsize 62
4389 22:18:04.693548 [CA 3] Center 34 (3~65) winsize 63
4390 22:18:04.696947 [CA 4] Center 34 (4~65) winsize 62
4391 22:18:04.700691 [CA 5] Center 33 (3~64) winsize 62
4392 22:18:04.700800
4393 22:18:04.703927 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4394 22:18:04.704041
4395 22:18:04.707148 [CATrainingPosCal] consider 2 rank data
4396 22:18:04.710177 u2DelayCellTimex100 = 270/100 ps
4397 22:18:04.713894 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4398 22:18:04.720003 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4399 22:18:04.723626 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 22:18:04.726618 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4401 22:18:04.730129 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 22:18:04.733207 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 22:18:04.733293
4404 22:18:04.737005 CA PerBit enable=1, Macro0, CA PI delay=33
4405 22:18:04.737090
4406 22:18:04.740001 [CBTSetCACLKResult] CA Dly = 33
4407 22:18:04.743644 CS Dly: 5 (0~37)
4408 22:18:04.743727
4409 22:18:04.746702 ----->DramcWriteLeveling(PI) begin...
4410 22:18:04.746814 ==
4411 22:18:04.750125 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 22:18:04.753015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 22:18:04.753099 ==
4414 22:18:04.756503 Write leveling (Byte 0): 29 => 29
4415 22:18:04.760045 Write leveling (Byte 1): 31 => 31
4416 22:18:04.763299 DramcWriteLeveling(PI) end<-----
4417 22:18:04.763383
4418 22:18:04.763449 ==
4419 22:18:04.766725 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 22:18:04.769560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 22:18:04.769645 ==
4422 22:18:04.773228 [Gating] SW mode calibration
4423 22:18:04.779372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 22:18:04.786619 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 22:18:04.789755 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 22:18:04.792954 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 22:18:04.799457 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 22:18:04.802625 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
4429 22:18:04.805796 0 9 16 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
4430 22:18:04.812874 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 22:18:04.815812 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 22:18:04.819621 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 22:18:04.825973 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 22:18:04.829035 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 22:18:04.832626 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 22:18:04.838657 0 10 12 | B1->B0 | 2e2e 3131 | 0 1 | (0 0) (0 0)
4437 22:18:04.842277 0 10 16 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
4438 22:18:04.845882 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 22:18:04.852276 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:18:04.855277 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:18:04.858662 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:18:04.865394 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:18:04.868737 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 22:18:04.871861 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 22:18:04.878740 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4446 22:18:04.881799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:18:04.884728 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 22:18:04.891282 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:18:04.894526 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:18:04.900918 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:18:04.904199 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:18:04.908025 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:18:04.911278 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:18:04.917991 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:18:04.920828 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:18:04.924561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:18:04.930823 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:18:04.934057 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:18:04.937759 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 22:18:04.943924 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4461 22:18:04.947597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4462 22:18:04.950595 Total UI for P1: 0, mck2ui 16
4463 22:18:04.954113 best dqsien dly found for B1: ( 0, 13, 12)
4464 22:18:04.957342 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 22:18:04.960364 Total UI for P1: 0, mck2ui 16
4466 22:18:04.964019 best dqsien dly found for B0: ( 0, 13, 14)
4467 22:18:04.970672 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4468 22:18:04.973524 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4469 22:18:04.973608
4470 22:18:04.976909 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4471 22:18:04.980413 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 22:18:04.983512 [Gating] SW calibration Done
4473 22:18:04.983592 ==
4474 22:18:04.987084 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 22:18:04.990169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 22:18:04.990263 ==
4477 22:18:04.993244 RX Vref Scan: 0
4478 22:18:04.993320
4479 22:18:04.993385 RX Vref 0 -> 0, step: 1
4480 22:18:04.993473
4481 22:18:04.996566 RX Delay -230 -> 252, step: 16
4482 22:18:05.003328 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4483 22:18:05.006725 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4484 22:18:05.010250 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4485 22:18:05.013324 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4486 22:18:05.016483 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4487 22:18:05.023189 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4488 22:18:05.026274 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4489 22:18:05.029529 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4490 22:18:05.033294 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4491 22:18:05.039529 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4492 22:18:05.043315 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4493 22:18:05.046444 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4494 22:18:05.049533 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4495 22:18:05.056093 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4496 22:18:05.059698 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4497 22:18:05.062770 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4498 22:18:05.062870 ==
4499 22:18:05.065895 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 22:18:05.069071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 22:18:05.072802 ==
4502 22:18:05.072906 DQS Delay:
4503 22:18:05.072975 DQS0 = 0, DQS1 = 0
4504 22:18:05.076054 DQM Delay:
4505 22:18:05.076131 DQM0 = 38, DQM1 = 28
4506 22:18:05.079024 DQ Delay:
4507 22:18:05.079103 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4508 22:18:05.082549 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4509 22:18:05.086023 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4510 22:18:05.088992 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4511 22:18:05.092820
4512 22:18:05.092925
4513 22:18:05.093032 ==
4514 22:18:05.095560 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 22:18:05.098783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 22:18:05.098878 ==
4517 22:18:05.098967
4518 22:18:05.099060
4519 22:18:05.102152 TX Vref Scan disable
4520 22:18:05.102237 == TX Byte 0 ==
4521 22:18:05.109181 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 22:18:05.112332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 22:18:05.112418 == TX Byte 1 ==
4524 22:18:05.118605 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4525 22:18:05.121848 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4526 22:18:05.121934 ==
4527 22:18:05.125580 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 22:18:05.128759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 22:18:05.128844 ==
4530 22:18:05.128912
4531 22:18:05.131780
4532 22:18:05.131864 TX Vref Scan disable
4533 22:18:05.135682 == TX Byte 0 ==
4534 22:18:05.138853 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4535 22:18:05.145193 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4536 22:18:05.145278 == TX Byte 1 ==
4537 22:18:05.148605 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4538 22:18:05.155446 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4539 22:18:05.155566
4540 22:18:05.155662 [DATLAT]
4541 22:18:05.155757 Freq=600, CH1 RK0
4542 22:18:05.155851
4543 22:18:05.158531 DATLAT Default: 0x9
4544 22:18:05.158641 0, 0xFFFF, sum = 0
4545 22:18:05.161574 1, 0xFFFF, sum = 0
4546 22:18:05.165038 2, 0xFFFF, sum = 0
4547 22:18:05.165124 3, 0xFFFF, sum = 0
4548 22:18:05.168606 4, 0xFFFF, sum = 0
4549 22:18:05.168697 5, 0xFFFF, sum = 0
4550 22:18:05.171935 6, 0xFFFF, sum = 0
4551 22:18:05.172018 7, 0xFFFF, sum = 0
4552 22:18:05.174987 8, 0x0, sum = 1
4553 22:18:05.175086 9, 0x0, sum = 2
4554 22:18:05.175180 10, 0x0, sum = 3
4555 22:18:05.178178 11, 0x0, sum = 4
4556 22:18:05.178252 best_step = 9
4557 22:18:05.178313
4558 22:18:05.181298 ==
4559 22:18:05.181368 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 22:18:05.188068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 22:18:05.188156 ==
4562 22:18:05.188223 RX Vref Scan: 1
4563 22:18:05.188283
4564 22:18:05.191679 RX Vref 0 -> 0, step: 1
4565 22:18:05.191761
4566 22:18:05.194675 RX Delay -195 -> 252, step: 8
4567 22:18:05.194789
4568 22:18:05.198307 Set Vref, RX VrefLevel [Byte0]: 55
4569 22:18:05.201355 [Byte1]: 49
4570 22:18:05.201445
4571 22:18:05.204407 Final RX Vref Byte 0 = 55 to rank0
4572 22:18:05.207908 Final RX Vref Byte 1 = 49 to rank0
4573 22:18:05.210997 Final RX Vref Byte 0 = 55 to rank1
4574 22:18:05.214205 Final RX Vref Byte 1 = 49 to rank1==
4575 22:18:05.218094 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 22:18:05.221452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 22:18:05.224459 ==
4578 22:18:05.224541 DQS Delay:
4579 22:18:05.224621 DQS0 = 0, DQS1 = 0
4580 22:18:05.227551 DQM Delay:
4581 22:18:05.227633 DQM0 = 39, DQM1 = 28
4582 22:18:05.230886 DQ Delay:
4583 22:18:05.233881 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4584 22:18:05.233999 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4585 22:18:05.237715 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4586 22:18:05.240989 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4587 22:18:05.244096
4588 22:18:05.244180
4589 22:18:05.250822 [DQSOSCAuto] RK0, (LSB)MR18= 0x2431, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4590 22:18:05.254038 CH1 RK0: MR19=808, MR18=2431
4591 22:18:05.260318 CH1_RK0: MR19=0x808, MR18=0x2431, DQSOSC=400, MR23=63, INC=163, DEC=109
4592 22:18:05.260403
4593 22:18:05.264199 ----->DramcWriteLeveling(PI) begin...
4594 22:18:05.264283 ==
4595 22:18:05.267385 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 22:18:05.270416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 22:18:05.270502 ==
4598 22:18:05.273861 Write leveling (Byte 0): 31 => 31
4599 22:18:05.276832 Write leveling (Byte 1): 29 => 29
4600 22:18:05.280461 DramcWriteLeveling(PI) end<-----
4601 22:18:05.280547
4602 22:18:05.280613 ==
4603 22:18:05.283737 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 22:18:05.287350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 22:18:05.287435 ==
4606 22:18:05.290248 [Gating] SW mode calibration
4607 22:18:05.297028 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 22:18:05.303812 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 22:18:05.307319 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 22:18:05.313364 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 22:18:05.316444 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4612 22:18:05.320402 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
4613 22:18:05.326816 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4614 22:18:05.329825 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 22:18:05.333114 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 22:18:05.339321 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 22:18:05.343148 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 22:18:05.346217 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 22:18:05.352975 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4620 22:18:05.356096 0 10 12 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
4621 22:18:05.359279 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4622 22:18:05.366623 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 22:18:05.369349 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 22:18:05.373001 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:18:05.379244 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:18:05.382612 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 22:18:05.385617 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 22:18:05.392252 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4629 22:18:05.395923 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 22:18:05.398945 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:18:05.405384 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:18:05.408897 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:18:05.411942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:18:05.419026 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:18:05.421963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:18:05.425587 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:18:05.431819 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:18:05.435012 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:18:05.438234 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:18:05.444976 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:18:05.448771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:18:05.452003 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:18:05.458174 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:18:05.461292 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 22:18:05.465171 Total UI for P1: 0, mck2ui 16
4646 22:18:05.468341 best dqsien dly found for B0: ( 0, 13, 10)
4647 22:18:05.471548 Total UI for P1: 0, mck2ui 16
4648 22:18:05.474670 best dqsien dly found for B1: ( 0, 13, 10)
4649 22:18:05.477842 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4650 22:18:05.481619 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4651 22:18:05.481702
4652 22:18:05.484545 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4653 22:18:05.488115 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4654 22:18:05.491103 [Gating] SW calibration Done
4655 22:18:05.491185 ==
4656 22:18:05.494743 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 22:18:05.501512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 22:18:05.501594 ==
4659 22:18:05.501658 RX Vref Scan: 0
4660 22:18:05.501718
4661 22:18:05.504663 RX Vref 0 -> 0, step: 1
4662 22:18:05.504744
4663 22:18:05.507991 RX Delay -230 -> 252, step: 16
4664 22:18:05.511472 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4665 22:18:05.514268 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4666 22:18:05.517865 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4667 22:18:05.524218 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4668 22:18:05.527314 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4669 22:18:05.530931 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4670 22:18:05.533875 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4671 22:18:05.540326 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4672 22:18:05.543683 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4673 22:18:05.547420 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4674 22:18:05.550485 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4675 22:18:05.557087 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4676 22:18:05.560062 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4677 22:18:05.563682 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4678 22:18:05.566857 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4679 22:18:05.573783 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4680 22:18:05.573860 ==
4681 22:18:05.576880 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 22:18:05.580052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 22:18:05.580130 ==
4684 22:18:05.580193 DQS Delay:
4685 22:18:05.583296 DQS0 = 0, DQS1 = 0
4686 22:18:05.583365 DQM Delay:
4687 22:18:05.586458 DQM0 = 35, DQM1 = 29
4688 22:18:05.586552 DQ Delay:
4689 22:18:05.590219 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4690 22:18:05.593099 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4691 22:18:05.596667 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4692 22:18:05.599664 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4693 22:18:05.599765
4694 22:18:05.599855
4695 22:18:05.599944 ==
4696 22:18:05.603103 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 22:18:05.606632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 22:18:05.606737 ==
4699 22:18:05.609636
4700 22:18:05.609725
4701 22:18:05.609794 TX Vref Scan disable
4702 22:18:05.613368 == TX Byte 0 ==
4703 22:18:05.616615 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4704 22:18:05.619651 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4705 22:18:05.623306 == TX Byte 1 ==
4706 22:18:05.626630 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 22:18:05.629540 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 22:18:05.632788 ==
4709 22:18:05.636395 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 22:18:05.639553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 22:18:05.639637 ==
4712 22:18:05.639701
4713 22:18:05.639761
4714 22:18:05.642818 TX Vref Scan disable
4715 22:18:05.642942 == TX Byte 0 ==
4716 22:18:05.649217 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4717 22:18:05.652321 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4718 22:18:05.656156 == TX Byte 1 ==
4719 22:18:05.659255 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4720 22:18:05.662518 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4721 22:18:05.662601
4722 22:18:05.662666 [DATLAT]
4723 22:18:05.665424 Freq=600, CH1 RK1
4724 22:18:05.665541
4725 22:18:05.669112 DATLAT Default: 0x9
4726 22:18:05.669198 0, 0xFFFF, sum = 0
4727 22:18:05.672244 1, 0xFFFF, sum = 0
4728 22:18:05.672329 2, 0xFFFF, sum = 0
4729 22:18:05.675507 3, 0xFFFF, sum = 0
4730 22:18:05.675590 4, 0xFFFF, sum = 0
4731 22:18:05.679192 5, 0xFFFF, sum = 0
4732 22:18:05.679277 6, 0xFFFF, sum = 0
4733 22:18:05.682320 7, 0xFFFF, sum = 0
4734 22:18:05.682435 8, 0x0, sum = 1
4735 22:18:05.685570 9, 0x0, sum = 2
4736 22:18:05.685654 10, 0x0, sum = 3
4737 22:18:05.685720 11, 0x0, sum = 4
4738 22:18:05.688816 best_step = 9
4739 22:18:05.688898
4740 22:18:05.688963 ==
4741 22:18:05.691982 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 22:18:05.695774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 22:18:05.695871 ==
4744 22:18:05.698854 RX Vref Scan: 0
4745 22:18:05.698952
4746 22:18:05.702289 RX Vref 0 -> 0, step: 1
4747 22:18:05.702407
4748 22:18:05.702472 RX Delay -195 -> 252, step: 8
4749 22:18:05.709685 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4750 22:18:05.713356 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4751 22:18:05.716285 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4752 22:18:05.719528 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4753 22:18:05.726459 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4754 22:18:05.729461 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4755 22:18:05.733273 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4756 22:18:05.736225 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4757 22:18:05.742949 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4758 22:18:05.746130 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4759 22:18:05.749173 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4760 22:18:05.752938 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4761 22:18:05.759070 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4762 22:18:05.762437 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4763 22:18:05.765713 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4764 22:18:05.769526 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4765 22:18:05.769602 ==
4766 22:18:05.772487 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 22:18:05.778967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 22:18:05.779049 ==
4769 22:18:05.779113 DQS Delay:
4770 22:18:05.782171 DQS0 = 0, DQS1 = 0
4771 22:18:05.782252 DQM Delay:
4772 22:18:05.782316 DQM0 = 36, DQM1 = 30
4773 22:18:05.786036 DQ Delay:
4774 22:18:05.789195 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4775 22:18:05.792461 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4776 22:18:05.795724 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4777 22:18:05.798881 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4778 22:18:05.798975
4779 22:18:05.799039
4780 22:18:05.805245 [DQSOSCAuto] RK1, (LSB)MR18= 0x3655, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4781 22:18:05.808994 CH1 RK1: MR19=808, MR18=3655
4782 22:18:05.815253 CH1_RK1: MR19=0x808, MR18=0x3655, DQSOSC=393, MR23=63, INC=169, DEC=113
4783 22:18:05.818635 [RxdqsGatingPostProcess] freq 600
4784 22:18:05.824935 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 22:18:05.825020 Pre-setting of DQS Precalculation
4786 22:18:05.831836 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 22:18:05.838579 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 22:18:05.844671 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 22:18:05.844795
4790 22:18:05.844890
4791 22:18:05.848115 [Calibration Summary] 1200 Mbps
4792 22:18:05.851411 CH 0, Rank 0
4793 22:18:05.851484 SW Impedance : PASS
4794 22:18:05.854615 DUTY Scan : NO K
4795 22:18:05.857819 ZQ Calibration : PASS
4796 22:18:05.857900 Jitter Meter : NO K
4797 22:18:05.861553 CBT Training : PASS
4798 22:18:05.864783 Write leveling : PASS
4799 22:18:05.864902 RX DQS gating : PASS
4800 22:18:05.867969 RX DQ/DQS(RDDQC) : PASS
4801 22:18:05.868048 TX DQ/DQS : PASS
4802 22:18:05.871121 RX DATLAT : PASS
4803 22:18:05.874813 RX DQ/DQS(Engine): PASS
4804 22:18:05.874946 TX OE : NO K
4805 22:18:05.877907 All Pass.
4806 22:18:05.877989
4807 22:18:05.878076 CH 0, Rank 1
4808 22:18:05.880993 SW Impedance : PASS
4809 22:18:05.881085 DUTY Scan : NO K
4810 22:18:05.884653 ZQ Calibration : PASS
4811 22:18:05.887870 Jitter Meter : NO K
4812 22:18:05.887957 CBT Training : PASS
4813 22:18:05.891178 Write leveling : PASS
4814 22:18:05.894402 RX DQS gating : PASS
4815 22:18:05.894475 RX DQ/DQS(RDDQC) : PASS
4816 22:18:05.897649 TX DQ/DQS : PASS
4817 22:18:05.900919 RX DATLAT : PASS
4818 22:18:05.901030 RX DQ/DQS(Engine): PASS
4819 22:18:05.904022 TX OE : NO K
4820 22:18:05.904137 All Pass.
4821 22:18:05.904229
4822 22:18:05.907780 CH 1, Rank 0
4823 22:18:05.907862 SW Impedance : PASS
4824 22:18:05.910718 DUTY Scan : NO K
4825 22:18:05.914371 ZQ Calibration : PASS
4826 22:18:05.914472 Jitter Meter : NO K
4827 22:18:05.917523 CBT Training : PASS
4828 22:18:05.920646 Write leveling : PASS
4829 22:18:05.920727 RX DQS gating : PASS
4830 22:18:05.924275 RX DQ/DQS(RDDQC) : PASS
4831 22:18:05.927396 TX DQ/DQS : PASS
4832 22:18:05.927472 RX DATLAT : PASS
4833 22:18:05.930300 RX DQ/DQS(Engine): PASS
4834 22:18:05.933822 TX OE : NO K
4835 22:18:05.933940 All Pass.
4836 22:18:05.934034
4837 22:18:05.934140 CH 1, Rank 1
4838 22:18:05.936841 SW Impedance : PASS
4839 22:18:05.940434 DUTY Scan : NO K
4840 22:18:05.940585 ZQ Calibration : PASS
4841 22:18:05.943495 Jitter Meter : NO K
4842 22:18:05.947059 CBT Training : PASS
4843 22:18:05.947172 Write leveling : PASS
4844 22:18:05.950373 RX DQS gating : PASS
4845 22:18:05.950488 RX DQ/DQS(RDDQC) : PASS
4846 22:18:05.953458 TX DQ/DQS : PASS
4847 22:18:05.957005 RX DATLAT : PASS
4848 22:18:05.957080 RX DQ/DQS(Engine): PASS
4849 22:18:05.960041 TX OE : NO K
4850 22:18:05.960124 All Pass.
4851 22:18:05.960208
4852 22:18:05.963326 DramC Write-DBI off
4853 22:18:05.966945 PER_BANK_REFRESH: Hybrid Mode
4854 22:18:05.967017 TX_TRACKING: ON
4855 22:18:05.976303 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 22:18:05.980072 [FAST_K] Save calibration result to emmc
4857 22:18:05.983098 dramc_set_vcore_voltage set vcore to 662500
4858 22:18:05.986173 Read voltage for 933, 3
4859 22:18:05.986260 Vio18 = 0
4860 22:18:05.989975 Vcore = 662500
4861 22:18:05.990057 Vdram = 0
4862 22:18:05.990119 Vddq = 0
4863 22:18:05.990183 Vmddr = 0
4864 22:18:05.996516 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 22:18:06.002771 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 22:18:06.002909 MEM_TYPE=3, freq_sel=17
4867 22:18:06.006012 sv_algorithm_assistance_LP4_1600
4868 22:18:06.009161 ============ PULL DRAM RESETB DOWN ============
4869 22:18:06.016129 ========== PULL DRAM RESETB DOWN end =========
4870 22:18:06.019340 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 22:18:06.022539 ===================================
4872 22:18:06.025682 LPDDR4 DRAM CONFIGURATION
4873 22:18:06.029443 ===================================
4874 22:18:06.029553 EX_ROW_EN[0] = 0x0
4875 22:18:06.032695 EX_ROW_EN[1] = 0x0
4876 22:18:06.035689 LP4Y_EN = 0x0
4877 22:18:06.035793 WORK_FSP = 0x0
4878 22:18:06.039321 WL = 0x3
4879 22:18:06.039426 RL = 0x3
4880 22:18:06.042204 BL = 0x2
4881 22:18:06.042312 RPST = 0x0
4882 22:18:06.045590 RD_PRE = 0x0
4883 22:18:06.045693 WR_PRE = 0x1
4884 22:18:06.049092 WR_PST = 0x0
4885 22:18:06.049196 DBI_WR = 0x0
4886 22:18:06.052139 DBI_RD = 0x0
4887 22:18:06.052247 OTF = 0x1
4888 22:18:06.055281 ===================================
4889 22:18:06.058698 ===================================
4890 22:18:06.062636 ANA top config
4891 22:18:06.065564 ===================================
4892 22:18:06.065671 DLL_ASYNC_EN = 0
4893 22:18:06.068651 ALL_SLAVE_EN = 1
4894 22:18:06.072307 NEW_RANK_MODE = 1
4895 22:18:06.075425 DLL_IDLE_MODE = 1
4896 22:18:06.078641 LP45_APHY_COMB_EN = 1
4897 22:18:06.078725 TX_ODT_DIS = 1
4898 22:18:06.081716 NEW_8X_MODE = 1
4899 22:18:06.085301 ===================================
4900 22:18:06.088656 ===================================
4901 22:18:06.091743 data_rate = 1866
4902 22:18:06.094835 CKR = 1
4903 22:18:06.098720 DQ_P2S_RATIO = 8
4904 22:18:06.101901 ===================================
4905 22:18:06.105147 CA_P2S_RATIO = 8
4906 22:18:06.105238 DQ_CA_OPEN = 0
4907 22:18:06.108376 DQ_SEMI_OPEN = 0
4908 22:18:06.111564 CA_SEMI_OPEN = 0
4909 22:18:06.114722 CA_FULL_RATE = 0
4910 22:18:06.117890 DQ_CKDIV4_EN = 1
4911 22:18:06.121594 CA_CKDIV4_EN = 1
4912 22:18:06.121673 CA_PREDIV_EN = 0
4913 22:18:06.124706 PH8_DLY = 0
4914 22:18:06.127914 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 22:18:06.131083 DQ_AAMCK_DIV = 4
4916 22:18:06.134754 CA_AAMCK_DIV = 4
4917 22:18:06.138027 CA_ADMCK_DIV = 4
4918 22:18:06.138126 DQ_TRACK_CA_EN = 0
4919 22:18:06.141147 CA_PICK = 933
4920 22:18:06.144200 CA_MCKIO = 933
4921 22:18:06.147772 MCKIO_SEMI = 0
4922 22:18:06.150804 PLL_FREQ = 3732
4923 22:18:06.154108 DQ_UI_PI_RATIO = 32
4924 22:18:06.157267 CA_UI_PI_RATIO = 0
4925 22:18:06.160909 ===================================
4926 22:18:06.164310 ===================================
4927 22:18:06.164392 memory_type:LPDDR4
4928 22:18:06.167474 GP_NUM : 10
4929 22:18:06.170678 SRAM_EN : 1
4930 22:18:06.170785 MD32_EN : 0
4931 22:18:06.174305 ===================================
4932 22:18:06.177430 [ANA_INIT] >>>>>>>>>>>>>>
4933 22:18:06.180337 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 22:18:06.184105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 22:18:06.187267 ===================================
4936 22:18:06.190214 data_rate = 1866,PCW = 0X8f00
4937 22:18:06.193791 ===================================
4938 22:18:06.197012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 22:18:06.200212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 22:18:06.207213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 22:18:06.213476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 22:18:06.216561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 22:18:06.219876 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 22:18:06.219953 [ANA_INIT] flow start
4945 22:18:06.223629 [ANA_INIT] PLL >>>>>>>>
4946 22:18:06.226672 [ANA_INIT] PLL <<<<<<<<
4947 22:18:06.226744 [ANA_INIT] MIDPI >>>>>>>>
4948 22:18:06.229910 [ANA_INIT] MIDPI <<<<<<<<
4949 22:18:06.233067 [ANA_INIT] DLL >>>>>>>>
4950 22:18:06.233164 [ANA_INIT] flow end
4951 22:18:06.240046 ============ LP4 DIFF to SE enter ============
4952 22:18:06.243389 ============ LP4 DIFF to SE exit ============
4953 22:18:06.246338 [ANA_INIT] <<<<<<<<<<<<<
4954 22:18:06.249666 [Flow] Enable top DCM control >>>>>
4955 22:18:06.253358 [Flow] Enable top DCM control <<<<<
4956 22:18:06.253442 Enable DLL master slave shuffle
4957 22:18:06.259588 ==============================================================
4958 22:18:06.263499 Gating Mode config
4959 22:18:06.266489 ==============================================================
4960 22:18:06.269552 Config description:
4961 22:18:06.279775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 22:18:06.286463 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 22:18:06.289157 SELPH_MODE 0: By rank 1: By Phase
4964 22:18:06.295992 ==============================================================
4965 22:18:06.299016 GAT_TRACK_EN = 1
4966 22:18:06.302841 RX_GATING_MODE = 2
4967 22:18:06.306087 RX_GATING_TRACK_MODE = 2
4968 22:18:06.309292 SELPH_MODE = 1
4969 22:18:06.312560 PICG_EARLY_EN = 1
4970 22:18:06.312636 VALID_LAT_VALUE = 1
4971 22:18:06.318988 ==============================================================
4972 22:18:06.322104 Enter into Gating configuration >>>>
4973 22:18:06.325244 Exit from Gating configuration <<<<
4974 22:18:06.328832 Enter into DVFS_PRE_config >>>>>
4975 22:18:06.341982 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 22:18:06.342069 Exit from DVFS_PRE_config <<<<<
4977 22:18:06.345186 Enter into PICG configuration >>>>
4978 22:18:06.348927 Exit from PICG configuration <<<<
4979 22:18:06.351890 [RX_INPUT] configuration >>>>>
4980 22:18:06.354987 [RX_INPUT] configuration <<<<<
4981 22:18:06.361768 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 22:18:06.365379 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 22:18:06.371673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 22:18:06.378508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 22:18:06.384639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 22:18:06.391766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 22:18:06.394593 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 22:18:06.398111 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 22:18:06.401122 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 22:18:06.407724 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 22:18:06.411022 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 22:18:06.414745 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 22:18:06.418005 ===================================
4994 22:18:06.421248 LPDDR4 DRAM CONFIGURATION
4995 22:18:06.424394 ===================================
4996 22:18:06.427653 EX_ROW_EN[0] = 0x0
4997 22:18:06.427735 EX_ROW_EN[1] = 0x0
4998 22:18:06.430773 LP4Y_EN = 0x0
4999 22:18:06.430893 WORK_FSP = 0x0
5000 22:18:06.434579 WL = 0x3
5001 22:18:06.434662 RL = 0x3
5002 22:18:06.437616 BL = 0x2
5003 22:18:06.437698 RPST = 0x0
5004 22:18:06.440892 RD_PRE = 0x0
5005 22:18:06.440973 WR_PRE = 0x1
5006 22:18:06.443969 WR_PST = 0x0
5007 22:18:06.444050 DBI_WR = 0x0
5008 22:18:06.447626 DBI_RD = 0x0
5009 22:18:06.447707 OTF = 0x1
5010 22:18:06.450821 ===================================
5011 22:18:06.457481 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 22:18:06.460764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 22:18:06.463876 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 22:18:06.467056 ===================================
5015 22:18:06.470703 LPDDR4 DRAM CONFIGURATION
5016 22:18:06.473746 ===================================
5017 22:18:06.477026 EX_ROW_EN[0] = 0x10
5018 22:18:06.477108 EX_ROW_EN[1] = 0x0
5019 22:18:06.480286 LP4Y_EN = 0x0
5020 22:18:06.480398 WORK_FSP = 0x0
5021 22:18:06.483375 WL = 0x3
5022 22:18:06.483478 RL = 0x3
5023 22:18:06.486967 BL = 0x2
5024 22:18:06.487046 RPST = 0x0
5025 22:18:06.490012 RD_PRE = 0x0
5026 22:18:06.490117 WR_PRE = 0x1
5027 22:18:06.493281 WR_PST = 0x0
5028 22:18:06.497099 DBI_WR = 0x0
5029 22:18:06.497199 DBI_RD = 0x0
5030 22:18:06.499946 OTF = 0x1
5031 22:18:06.503437 ===================================
5032 22:18:06.506407 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 22:18:06.512041 nWR fixed to 30
5034 22:18:06.514947 [ModeRegInit_LP4] CH0 RK0
5035 22:18:06.515029 [ModeRegInit_LP4] CH0 RK1
5036 22:18:06.518217 [ModeRegInit_LP4] CH1 RK0
5037 22:18:06.522008 [ModeRegInit_LP4] CH1 RK1
5038 22:18:06.522106 match AC timing 9
5039 22:18:06.528469 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 22:18:06.531729 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 22:18:06.535007 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 22:18:06.541876 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 22:18:06.545092 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 22:18:06.545175 ==
5045 22:18:06.548208 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 22:18:06.551405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 22:18:06.551488 ==
5048 22:18:06.557710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 22:18:06.564821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5050 22:18:06.568121 [CA 0] Center 38 (8~69) winsize 62
5051 22:18:06.571195 [CA 1] Center 37 (7~68) winsize 62
5052 22:18:06.574318 [CA 2] Center 35 (5~66) winsize 62
5053 22:18:06.577999 [CA 3] Center 35 (5~66) winsize 62
5054 22:18:06.580971 [CA 4] Center 34 (4~65) winsize 62
5055 22:18:06.584806 [CA 5] Center 33 (3~64) winsize 62
5056 22:18:06.584891
5057 22:18:06.587804 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5058 22:18:06.587888
5059 22:18:06.590811 [CATrainingPosCal] consider 1 rank data
5060 22:18:06.594437 u2DelayCellTimex100 = 270/100 ps
5061 22:18:06.597713 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 22:18:06.600728 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5063 22:18:06.603836 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5064 22:18:06.610620 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5065 22:18:06.613934 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5066 22:18:06.617078 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5067 22:18:06.617164
5068 22:18:06.620668 CA PerBit enable=1, Macro0, CA PI delay=33
5069 22:18:06.620764
5070 22:18:06.623930 [CBTSetCACLKResult] CA Dly = 33
5071 22:18:06.624015 CS Dly: 6 (0~37)
5072 22:18:06.624095 ==
5073 22:18:06.627374 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 22:18:06.633943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 22:18:06.634062 ==
5076 22:18:06.637124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 22:18:06.643427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5078 22:18:06.647284 [CA 0] Center 38 (8~69) winsize 62
5079 22:18:06.650318 [CA 1] Center 38 (8~69) winsize 62
5080 22:18:06.653525 [CA 2] Center 35 (5~66) winsize 62
5081 22:18:06.656745 [CA 3] Center 35 (5~66) winsize 62
5082 22:18:06.660556 [CA 4] Center 34 (4~65) winsize 62
5083 22:18:06.663713 [CA 5] Center 33 (3~64) winsize 62
5084 22:18:06.663817
5085 22:18:06.666710 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5086 22:18:06.666815
5087 22:18:06.670317 [CATrainingPosCal] consider 2 rank data
5088 22:18:06.673586 u2DelayCellTimex100 = 270/100 ps
5089 22:18:06.676820 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5090 22:18:06.683481 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5091 22:18:06.686331 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5092 22:18:06.689838 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5093 22:18:06.693015 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5094 22:18:06.696829 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5095 22:18:06.696912
5096 22:18:06.699792 CA PerBit enable=1, Macro0, CA PI delay=33
5097 22:18:06.699897
5098 22:18:06.703332 [CBTSetCACLKResult] CA Dly = 33
5099 22:18:06.706435 CS Dly: 7 (0~39)
5100 22:18:06.706541
5101 22:18:06.709609 ----->DramcWriteLeveling(PI) begin...
5102 22:18:06.709716 ==
5103 22:18:06.713147 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 22:18:06.716297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 22:18:06.716410 ==
5106 22:18:06.719561 Write leveling (Byte 0): 30 => 30
5107 22:18:06.722638 Write leveling (Byte 1): 29 => 29
5108 22:18:06.726147 DramcWriteLeveling(PI) end<-----
5109 22:18:06.726255
5110 22:18:06.726351 ==
5111 22:18:06.729617 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 22:18:06.732971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 22:18:06.733079 ==
5114 22:18:06.736177 [Gating] SW mode calibration
5115 22:18:06.742592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 22:18:06.749406 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 22:18:06.752580 0 14 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
5118 22:18:06.758864 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5119 22:18:06.762654 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 22:18:06.765835 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 22:18:06.772042 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 22:18:06.775277 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 22:18:06.778508 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5124 22:18:06.785561 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 22:18:06.788632 0 15 0 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (1 1)
5126 22:18:06.791627 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
5127 22:18:06.798581 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 22:18:06.801734 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 22:18:06.804880 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 22:18:06.811831 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 22:18:06.815025 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 22:18:06.818024 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5133 22:18:06.825134 1 0 0 | B1->B0 | 2f2f 3b3b | 1 0 | (0 0) (1 1)
5134 22:18:06.828237 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5135 22:18:06.831322 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 22:18:06.838138 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 22:18:06.841135 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:18:06.844938 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 22:18:06.851182 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 22:18:06.854343 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 22:18:06.858145 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5142 22:18:06.864207 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 22:18:06.868016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 22:18:06.871240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:18:06.878000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:18:06.881141 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:18:06.884459 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:18:06.891101 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:18:06.894320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:18:06.897386 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:18:06.904006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:18:06.907554 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:18:06.910897 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:18:06.917307 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:18:06.920883 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:18:06.923937 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5157 22:18:06.930369 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 22:18:06.933502 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 22:18:06.937045 Total UI for P1: 0, mck2ui 16
5160 22:18:06.940141 best dqsien dly found for B0: ( 1, 2, 30)
5161 22:18:06.943889 Total UI for P1: 0, mck2ui 16
5162 22:18:06.946968 best dqsien dly found for B1: ( 1, 3, 2)
5163 22:18:06.949968 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5164 22:18:06.953641 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5165 22:18:06.953752
5166 22:18:06.956682 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5167 22:18:06.959907 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5168 22:18:06.963152 [Gating] SW calibration Done
5169 22:18:06.963238 ==
5170 22:18:06.966706 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 22:18:06.969659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 22:18:06.969774 ==
5173 22:18:06.973685 RX Vref Scan: 0
5174 22:18:06.973764
5175 22:18:06.976599 RX Vref 0 -> 0, step: 1
5176 22:18:06.976724
5177 22:18:06.976817 RX Delay -80 -> 252, step: 8
5178 22:18:06.983386 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5179 22:18:06.986701 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5180 22:18:06.989837 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5181 22:18:06.993085 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5182 22:18:06.996334 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5183 22:18:07.003273 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5184 22:18:07.006535 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5185 22:18:07.009620 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5186 22:18:07.012672 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5187 22:18:07.016410 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5188 22:18:07.022722 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5189 22:18:07.025731 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5190 22:18:07.029188 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5191 22:18:07.032294 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5192 22:18:07.036401 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5193 22:18:07.042456 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5194 22:18:07.042602 ==
5195 22:18:07.045574 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 22:18:07.049287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 22:18:07.049393 ==
5198 22:18:07.049494 DQS Delay:
5199 22:18:07.052410 DQS0 = 0, DQS1 = 0
5200 22:18:07.052518 DQM Delay:
5201 22:18:07.055435 DQM0 = 93, DQM1 = 82
5202 22:18:07.055542 DQ Delay:
5203 22:18:07.058954 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5204 22:18:07.061957 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5205 22:18:07.065223 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5206 22:18:07.068932 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5207 22:18:07.069040
5208 22:18:07.069131
5209 22:18:07.069234 ==
5210 22:18:07.072040 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 22:18:07.075487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 22:18:07.078670 ==
5213 22:18:07.078768
5214 22:18:07.078870
5215 22:18:07.078933 TX Vref Scan disable
5216 22:18:07.081789 == TX Byte 0 ==
5217 22:18:07.084872 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5218 22:18:07.091972 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5219 22:18:07.092055 == TX Byte 1 ==
5220 22:18:07.095075 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5221 22:18:07.101368 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5222 22:18:07.101451 ==
5223 22:18:07.104581 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 22:18:07.107803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 22:18:07.107887 ==
5226 22:18:07.107953
5227 22:18:07.108013
5228 22:18:07.111529 TX Vref Scan disable
5229 22:18:07.111612 == TX Byte 0 ==
5230 22:18:07.118367 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5231 22:18:07.121528 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5232 22:18:07.124560 == TX Byte 1 ==
5233 22:18:07.127694 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5234 22:18:07.131333 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5235 22:18:07.131416
5236 22:18:07.131482 [DATLAT]
5237 22:18:07.134706 Freq=933, CH0 RK0
5238 22:18:07.134789
5239 22:18:07.134864 DATLAT Default: 0xd
5240 22:18:07.137565 0, 0xFFFF, sum = 0
5241 22:18:07.141301 1, 0xFFFF, sum = 0
5242 22:18:07.141388 2, 0xFFFF, sum = 0
5243 22:18:07.144312 3, 0xFFFF, sum = 0
5244 22:18:07.144391 4, 0xFFFF, sum = 0
5245 22:18:07.147511 5, 0xFFFF, sum = 0
5246 22:18:07.147596 6, 0xFFFF, sum = 0
5247 22:18:07.150662 7, 0xFFFF, sum = 0
5248 22:18:07.150747 8, 0xFFFF, sum = 0
5249 22:18:07.153877 9, 0xFFFF, sum = 0
5250 22:18:07.153962 10, 0x0, sum = 1
5251 22:18:07.157102 11, 0x0, sum = 2
5252 22:18:07.157186 12, 0x0, sum = 3
5253 22:18:07.160770 13, 0x0, sum = 4
5254 22:18:07.160854 best_step = 11
5255 22:18:07.160920
5256 22:18:07.160980 ==
5257 22:18:07.163851 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 22:18:07.167327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 22:18:07.170547 ==
5260 22:18:07.170631 RX Vref Scan: 1
5261 22:18:07.170696
5262 22:18:07.173500 RX Vref 0 -> 0, step: 1
5263 22:18:07.173584
5264 22:18:07.177102 RX Delay -69 -> 252, step: 4
5265 22:18:07.177185
5266 22:18:07.180228 Set Vref, RX VrefLevel [Byte0]: 60
5267 22:18:07.183393 [Byte1]: 54
5268 22:18:07.183479
5269 22:18:07.186564 Final RX Vref Byte 0 = 60 to rank0
5270 22:18:07.190222 Final RX Vref Byte 1 = 54 to rank0
5271 22:18:07.193540 Final RX Vref Byte 0 = 60 to rank1
5272 22:18:07.196588 Final RX Vref Byte 1 = 54 to rank1==
5273 22:18:07.199712 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 22:18:07.202844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 22:18:07.202947 ==
5276 22:18:07.206711 DQS Delay:
5277 22:18:07.206819 DQS0 = 0, DQS1 = 0
5278 22:18:07.209914 DQM Delay:
5279 22:18:07.210020 DQM0 = 96, DQM1 = 83
5280 22:18:07.210111 DQ Delay:
5281 22:18:07.213152 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5282 22:18:07.216263 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5283 22:18:07.220066 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5284 22:18:07.222939 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5285 22:18:07.223031
5286 22:18:07.223115
5287 22:18:07.232907 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5288 22:18:07.236118 CH0 RK0: MR19=505, MR18=1615
5289 22:18:07.239659 CH0_RK0: MR19=0x505, MR18=0x1615, DQSOSC=414, MR23=63, INC=63, DEC=42
5290 22:18:07.242859
5291 22:18:07.246324 ----->DramcWriteLeveling(PI) begin...
5292 22:18:07.246407 ==
5293 22:18:07.249256 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 22:18:07.252976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 22:18:07.253056 ==
5296 22:18:07.256157 Write leveling (Byte 0): 30 => 30
5297 22:18:07.259639 Write leveling (Byte 1): 30 => 30
5298 22:18:07.262567 DramcWriteLeveling(PI) end<-----
5299 22:18:07.262643
5300 22:18:07.262705 ==
5301 22:18:07.265616 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 22:18:07.269409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 22:18:07.269489 ==
5304 22:18:07.272287 [Gating] SW mode calibration
5305 22:18:07.279286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5306 22:18:07.285606 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5307 22:18:07.289289 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5308 22:18:07.292363 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 22:18:07.298766 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 22:18:07.301967 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 22:18:07.305681 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 22:18:07.312148 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 22:18:07.315194 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5314 22:18:07.318495 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5315 22:18:07.325507 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5316 22:18:07.328713 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5317 22:18:07.331867 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 22:18:07.338701 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 22:18:07.342032 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 22:18:07.344751 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 22:18:07.351529 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 22:18:07.354982 0 15 28 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
5323 22:18:07.358592 1 0 0 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
5324 22:18:07.365218 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 22:18:07.368311 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 22:18:07.371532 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 22:18:07.378243 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 22:18:07.381248 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 22:18:07.384756 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 22:18:07.391294 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5331 22:18:07.394500 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5332 22:18:07.397636 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 22:18:07.404762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:18:07.407756 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:18:07.410981 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:18:07.417986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:18:07.420867 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:18:07.424260 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:18:07.430866 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:18:07.434139 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:18:07.437209 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:18:07.444062 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:18:07.447081 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:18:07.450706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 22:18:07.457095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:18:07.460822 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 22:18:07.463787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5348 22:18:07.466957 Total UI for P1: 0, mck2ui 16
5349 22:18:07.470541 best dqsien dly found for B0: ( 1, 2, 28)
5350 22:18:07.477184 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 22:18:07.480109 Total UI for P1: 0, mck2ui 16
5352 22:18:07.483878 best dqsien dly found for B1: ( 1, 3, 0)
5353 22:18:07.486696 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5354 22:18:07.490316 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5355 22:18:07.490401
5356 22:18:07.493390 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5357 22:18:07.496897 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5358 22:18:07.499839 [Gating] SW calibration Done
5359 22:18:07.499924 ==
5360 22:18:07.503647 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 22:18:07.506555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 22:18:07.506641 ==
5363 22:18:07.509663 RX Vref Scan: 0
5364 22:18:07.509743
5365 22:18:07.512881 RX Vref 0 -> 0, step: 1
5366 22:18:07.512959
5367 22:18:07.513024 RX Delay -80 -> 252, step: 8
5368 22:18:07.519229 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5369 22:18:07.523083 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5370 22:18:07.526159 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5371 22:18:07.529239 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5372 22:18:07.532969 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5373 22:18:07.539340 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5374 22:18:07.542626 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5375 22:18:07.545747 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5376 22:18:07.549338 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5377 22:18:07.552456 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5378 22:18:07.558677 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5379 22:18:07.562546 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5380 22:18:07.565568 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5381 22:18:07.568896 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5382 22:18:07.572186 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5383 22:18:07.578813 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5384 22:18:07.578913 ==
5385 22:18:07.582213 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 22:18:07.585254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 22:18:07.585362 ==
5388 22:18:07.585456 DQS Delay:
5389 22:18:07.588428 DQS0 = 0, DQS1 = 0
5390 22:18:07.588536 DQM Delay:
5391 22:18:07.592009 DQM0 = 91, DQM1 = 82
5392 22:18:07.592115 DQ Delay:
5393 22:18:07.595052 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5394 22:18:07.598483 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5395 22:18:07.601548 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5396 22:18:07.605092 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5397 22:18:07.605199
5398 22:18:07.605295
5399 22:18:07.605390 ==
5400 22:18:07.608695 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 22:18:07.615012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 22:18:07.615120 ==
5403 22:18:07.615223
5404 22:18:07.615316
5405 22:18:07.615414 TX Vref Scan disable
5406 22:18:07.618301 == TX Byte 0 ==
5407 22:18:07.621469 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5408 22:18:07.627865 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5409 22:18:07.627952 == TX Byte 1 ==
5410 22:18:07.631666 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5411 22:18:07.637840 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5412 22:18:07.637959 ==
5413 22:18:07.640990 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 22:18:07.644761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 22:18:07.644872 ==
5416 22:18:07.644975
5417 22:18:07.645065
5418 22:18:07.647960 TX Vref Scan disable
5419 22:18:07.648037 == TX Byte 0 ==
5420 22:18:07.654282 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5421 22:18:07.657866 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5422 22:18:07.660760 == TX Byte 1 ==
5423 22:18:07.664489 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5424 22:18:07.667674 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5425 22:18:07.667755
5426 22:18:07.667839 [DATLAT]
5427 22:18:07.670772 Freq=933, CH0 RK1
5428 22:18:07.670874
5429 22:18:07.670946 DATLAT Default: 0xb
5430 22:18:07.674106 0, 0xFFFF, sum = 0
5431 22:18:07.677647 1, 0xFFFF, sum = 0
5432 22:18:07.677729 2, 0xFFFF, sum = 0
5433 22:18:07.680459 3, 0xFFFF, sum = 0
5434 22:18:07.680542 4, 0xFFFF, sum = 0
5435 22:18:07.683976 5, 0xFFFF, sum = 0
5436 22:18:07.684062 6, 0xFFFF, sum = 0
5437 22:18:07.687669 7, 0xFFFF, sum = 0
5438 22:18:07.687754 8, 0xFFFF, sum = 0
5439 22:18:07.690974 9, 0xFFFF, sum = 0
5440 22:18:07.691059 10, 0x0, sum = 1
5441 22:18:07.694049 11, 0x0, sum = 2
5442 22:18:07.694135 12, 0x0, sum = 3
5443 22:18:07.697151 13, 0x0, sum = 4
5444 22:18:07.697238 best_step = 11
5445 22:18:07.697323
5446 22:18:07.697406 ==
5447 22:18:07.700781 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 22:18:07.703930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 22:18:07.706838 ==
5450 22:18:07.706922 RX Vref Scan: 0
5451 22:18:07.707010
5452 22:18:07.710408 RX Vref 0 -> 0, step: 1
5453 22:18:07.710513
5454 22:18:07.713790 RX Delay -77 -> 252, step: 4
5455 22:18:07.716755 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5456 22:18:07.719919 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5457 22:18:07.723870 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5458 22:18:07.730236 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5459 22:18:07.733460 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5460 22:18:07.736688 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5461 22:18:07.740412 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5462 22:18:07.743437 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5463 22:18:07.750526 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5464 22:18:07.753735 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5465 22:18:07.756821 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5466 22:18:07.760032 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5467 22:18:07.763210 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5468 22:18:07.770229 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5469 22:18:07.773235 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5470 22:18:07.776388 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5471 22:18:07.776472 ==
5472 22:18:07.780077 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 22:18:07.783252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 22:18:07.783332 ==
5475 22:18:07.786261 DQS Delay:
5476 22:18:07.786368 DQS0 = 0, DQS1 = 0
5477 22:18:07.790146 DQM Delay:
5478 22:18:07.790252 DQM0 = 92, DQM1 = 84
5479 22:18:07.790353 DQ Delay:
5480 22:18:07.792950 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =90
5481 22:18:07.796058 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5482 22:18:07.799771 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5483 22:18:07.802845 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92
5484 22:18:07.802927
5485 22:18:07.806443
5486 22:18:07.812972 [DQSOSCAuto] RK1, (LSB)MR18= 0x3114, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5487 22:18:07.815971 CH0 RK1: MR19=505, MR18=3114
5488 22:18:07.822390 CH0_RK1: MR19=0x505, MR18=0x3114, DQSOSC=406, MR23=63, INC=65, DEC=43
5489 22:18:07.825591 [RxdqsGatingPostProcess] freq 933
5490 22:18:07.829445 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 22:18:07.832532 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 22:18:07.835610 best DQS1 dly(2T, 0.5T) = (0, 11)
5493 22:18:07.838846 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 22:18:07.842192 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5495 22:18:07.845840 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 22:18:07.849037 best DQS1 dly(2T, 0.5T) = (0, 11)
5497 22:18:07.852190 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 22:18:07.855607 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5499 22:18:07.858542 Pre-setting of DQS Precalculation
5500 22:18:07.862386 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 22:18:07.862469 ==
5502 22:18:07.865520 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 22:18:07.871837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 22:18:07.871920 ==
5505 22:18:07.874860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 22:18:07.881444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5507 22:18:07.885162 [CA 0] Center 37 (7~68) winsize 62
5508 22:18:07.888617 [CA 1] Center 37 (7~68) winsize 62
5509 22:18:07.891690 [CA 2] Center 34 (5~64) winsize 60
5510 22:18:07.894694 [CA 3] Center 34 (4~64) winsize 61
5511 22:18:07.898335 [CA 4] Center 35 (5~65) winsize 61
5512 22:18:07.901356 [CA 5] Center 33 (4~63) winsize 60
5513 22:18:07.901462
5514 22:18:07.905245 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5515 22:18:07.905351
5516 22:18:07.908574 [CATrainingPosCal] consider 1 rank data
5517 22:18:07.911273 u2DelayCellTimex100 = 270/100 ps
5518 22:18:07.914961 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5519 22:18:07.921535 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5520 22:18:07.924590 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5521 22:18:07.928144 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 22:18:07.931252 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5523 22:18:07.934523 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5524 22:18:07.934629
5525 22:18:07.937524 CA PerBit enable=1, Macro0, CA PI delay=33
5526 22:18:07.937606
5527 22:18:07.941286 [CBTSetCACLKResult] CA Dly = 33
5528 22:18:07.944464 CS Dly: 6 (0~37)
5529 22:18:07.944573 ==
5530 22:18:07.947604 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 22:18:07.951336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 22:18:07.951441 ==
5533 22:18:07.957782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 22:18:07.960879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 22:18:07.965298 [CA 0] Center 37 (8~67) winsize 60
5536 22:18:07.968551 [CA 1] Center 37 (7~68) winsize 62
5537 22:18:07.971771 [CA 2] Center 35 (6~65) winsize 60
5538 22:18:07.975019 [CA 3] Center 34 (4~64) winsize 61
5539 22:18:07.978048 [CA 4] Center 34 (4~65) winsize 62
5540 22:18:07.981778 [CA 5] Center 34 (4~64) winsize 61
5541 22:18:07.981865
5542 22:18:07.984821 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 22:18:07.984930
5544 22:18:07.988335 [CATrainingPosCal] consider 2 rank data
5545 22:18:07.991577 u2DelayCellTimex100 = 270/100 ps
5546 22:18:07.994455 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5547 22:18:08.001044 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5548 22:18:08.004761 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5549 22:18:08.007860 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5550 22:18:08.011419 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5551 22:18:08.014335 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5552 22:18:08.014419
5553 22:18:08.017743 CA PerBit enable=1, Macro0, CA PI delay=33
5554 22:18:08.017826
5555 22:18:08.020930 [CBTSetCACLKResult] CA Dly = 33
5556 22:18:08.024281 CS Dly: 7 (0~39)
5557 22:18:08.024365
5558 22:18:08.027799 ----->DramcWriteLeveling(PI) begin...
5559 22:18:08.027883 ==
5560 22:18:08.030983 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 22:18:08.034376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 22:18:08.034472 ==
5563 22:18:08.037785 Write leveling (Byte 0): 29 => 29
5564 22:18:08.041008 Write leveling (Byte 1): 25 => 25
5565 22:18:08.044218 DramcWriteLeveling(PI) end<-----
5566 22:18:08.044297
5567 22:18:08.044362 ==
5568 22:18:08.047428 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 22:18:08.050617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 22:18:08.050730 ==
5571 22:18:08.053889 [Gating] SW mode calibration
5572 22:18:08.060664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 22:18:08.066855 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 22:18:08.070152 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5575 22:18:08.077202 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 22:18:08.080535 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 22:18:08.083421 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 22:18:08.090404 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 22:18:08.093724 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 22:18:08.096569 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 22:18:08.103717 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
5582 22:18:08.106569 0 15 0 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
5583 22:18:08.110139 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 22:18:08.116307 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 22:18:08.120346 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 22:18:08.123519 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 22:18:08.129893 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 22:18:08.132826 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 22:18:08.136423 0 15 28 | B1->B0 | 2c2c 2f2f | 0 0 | (0 0) (0 0)
5590 22:18:08.143503 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 22:18:08.146305 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 22:18:08.149966 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:18:08.153139 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 22:18:08.159334 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 22:18:08.163110 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 22:18:08.166227 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5597 22:18:08.172571 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5598 22:18:08.176314 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:18:08.179537 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:18:08.186036 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:18:08.189574 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:18:08.192833 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:18:08.199229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:18:08.202484 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:18:08.205981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:18:08.212669 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:18:08.215414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:18:08.219098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:18:08.225409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 22:18:08.228836 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 22:18:08.231858 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:18:08.238412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 22:18:08.242150 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 22:18:08.245719 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5615 22:18:08.251989 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 22:18:08.255062 Total UI for P1: 0, mck2ui 16
5617 22:18:08.258298 best dqsien dly found for B0: ( 1, 2, 30)
5618 22:18:08.261411 Total UI for P1: 0, mck2ui 16
5619 22:18:08.265059 best dqsien dly found for B1: ( 1, 2, 30)
5620 22:18:08.268174 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5621 22:18:08.271412 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5622 22:18:08.271522
5623 22:18:08.274636 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5624 22:18:08.277811 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5625 22:18:08.281015 [Gating] SW calibration Done
5626 22:18:08.281124 ==
5627 22:18:08.284908 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 22:18:08.288097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 22:18:08.291154 ==
5630 22:18:08.291266 RX Vref Scan: 0
5631 22:18:08.291363
5632 22:18:08.294285 RX Vref 0 -> 0, step: 1
5633 22:18:08.294397
5634 22:18:08.297553 RX Delay -80 -> 252, step: 8
5635 22:18:08.300790 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5636 22:18:08.304083 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5637 22:18:08.307608 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5638 22:18:08.310781 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5639 22:18:08.317625 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5640 22:18:08.320599 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5641 22:18:08.324203 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5642 22:18:08.327076 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5643 22:18:08.330692 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5644 22:18:08.333749 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5645 22:18:08.340250 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5646 22:18:08.343684 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5647 22:18:08.346865 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5648 22:18:08.350271 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5649 22:18:08.356768 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5650 22:18:08.359785 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5651 22:18:08.359900 ==
5652 22:18:08.363142 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 22:18:08.366719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 22:18:08.366838 ==
5655 22:18:08.369711 DQS Delay:
5656 22:18:08.369821 DQS0 = 0, DQS1 = 0
5657 22:18:08.369917 DQM Delay:
5658 22:18:08.373459 DQM0 = 94, DQM1 = 86
5659 22:18:08.373565 DQ Delay:
5660 22:18:08.376565 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5661 22:18:08.379869 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5662 22:18:08.383098 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5663 22:18:08.386280 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5664 22:18:08.386385
5665 22:18:08.386480
5666 22:18:08.386570 ==
5667 22:18:08.389592 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 22:18:08.396480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 22:18:08.396591 ==
5670 22:18:08.396693
5671 22:18:08.396785
5672 22:18:08.396878 TX Vref Scan disable
5673 22:18:08.399585 == TX Byte 0 ==
5674 22:18:08.402780 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5675 22:18:08.409706 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5676 22:18:08.409816 == TX Byte 1 ==
5677 22:18:08.412784 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5678 22:18:08.419203 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5679 22:18:08.419309 ==
5680 22:18:08.422875 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 22:18:08.426047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 22:18:08.426163 ==
5683 22:18:08.426265
5684 22:18:08.426358
5685 22:18:08.429111 TX Vref Scan disable
5686 22:18:08.432686 == TX Byte 0 ==
5687 22:18:08.435613 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5688 22:18:08.439320 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5689 22:18:08.442371 == TX Byte 1 ==
5690 22:18:08.445928 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5691 22:18:08.449105 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5692 22:18:08.449184
5693 22:18:08.452494 [DATLAT]
5694 22:18:08.452571 Freq=933, CH1 RK0
5695 22:18:08.452645
5696 22:18:08.455319 DATLAT Default: 0xd
5697 22:18:08.455414 0, 0xFFFF, sum = 0
5698 22:18:08.458731 1, 0xFFFF, sum = 0
5699 22:18:08.458841 2, 0xFFFF, sum = 0
5700 22:18:08.462278 3, 0xFFFF, sum = 0
5701 22:18:08.462355 4, 0xFFFF, sum = 0
5702 22:18:08.465348 5, 0xFFFF, sum = 0
5703 22:18:08.465426 6, 0xFFFF, sum = 0
5704 22:18:08.468356 7, 0xFFFF, sum = 0
5705 22:18:08.468431 8, 0xFFFF, sum = 0
5706 22:18:08.471956 9, 0xFFFF, sum = 0
5707 22:18:08.472038 10, 0x0, sum = 1
5708 22:18:08.475079 11, 0x0, sum = 2
5709 22:18:08.475157 12, 0x0, sum = 3
5710 22:18:08.478251 13, 0x0, sum = 4
5711 22:18:08.478354 best_step = 11
5712 22:18:08.478444
5713 22:18:08.478539 ==
5714 22:18:08.482113 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 22:18:08.488561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 22:18:08.488640 ==
5717 22:18:08.488711 RX Vref Scan: 1
5718 22:18:08.488772
5719 22:18:08.491746 RX Vref 0 -> 0, step: 1
5720 22:18:08.491819
5721 22:18:08.494967 RX Delay -61 -> 252, step: 4
5722 22:18:08.495040
5723 22:18:08.498649 Set Vref, RX VrefLevel [Byte0]: 55
5724 22:18:08.501777 [Byte1]: 49
5725 22:18:08.501856
5726 22:18:08.504874 Final RX Vref Byte 0 = 55 to rank0
5727 22:18:08.508565 Final RX Vref Byte 1 = 49 to rank0
5728 22:18:08.511646 Final RX Vref Byte 0 = 55 to rank1
5729 22:18:08.514766 Final RX Vref Byte 1 = 49 to rank1==
5730 22:18:08.518003 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 22:18:08.521281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 22:18:08.521355 ==
5733 22:18:08.524468 DQS Delay:
5734 22:18:08.524545 DQS0 = 0, DQS1 = 0
5735 22:18:08.528169 DQM Delay:
5736 22:18:08.528245 DQM0 = 95, DQM1 = 88
5737 22:18:08.528322 DQ Delay:
5738 22:18:08.531588 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5739 22:18:08.534564 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5740 22:18:08.537550 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5741 22:18:08.541262 DQ12 =96, DQ13 =92, DQ14 =94, DQ15 =94
5742 22:18:08.541347
5743 22:18:08.544193
5744 22:18:08.550971 [DQSOSCAuto] RK0, (LSB)MR18= 0x40d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5745 22:18:08.554004 CH1 RK0: MR19=505, MR18=40D
5746 22:18:08.560608 CH1_RK0: MR19=0x505, MR18=0x40D, DQSOSC=417, MR23=63, INC=62, DEC=41
5747 22:18:08.560691
5748 22:18:08.563910 ----->DramcWriteLeveling(PI) begin...
5749 22:18:08.563985 ==
5750 22:18:08.567477 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 22:18:08.570520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 22:18:08.570603 ==
5753 22:18:08.573923 Write leveling (Byte 0): 27 => 27
5754 22:18:08.577449 Write leveling (Byte 1): 27 => 27
5755 22:18:08.580657 DramcWriteLeveling(PI) end<-----
5756 22:18:08.580784
5757 22:18:08.580862 ==
5758 22:18:08.583895 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 22:18:08.587132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 22:18:08.587214 ==
5761 22:18:08.590387 [Gating] SW mode calibration
5762 22:18:08.597348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 22:18:08.603603 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 22:18:08.607226 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 22:18:08.610435 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 22:18:08.617244 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 22:18:08.620264 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 22:18:08.623513 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 22:18:08.629867 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 22:18:08.633609 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 0)
5771 22:18:08.636822 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (1 0)
5772 22:18:08.643037 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 22:18:08.646539 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 22:18:08.649547 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 22:18:08.656183 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 22:18:08.659499 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 22:18:08.662842 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 22:18:08.669952 0 15 24 | B1->B0 | 2929 3333 | 1 1 | (0 0) (0 0)
5779 22:18:08.673088 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5780 22:18:08.675955 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:18:08.683081 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 22:18:08.686287 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 22:18:08.689562 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 22:18:08.695951 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 22:18:08.699088 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 22:18:08.702246 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5787 22:18:08.709081 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5788 22:18:08.712257 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:18:08.715472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:18:08.722493 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:18:08.725537 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:18:08.728759 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:18:08.735574 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:18:08.738808 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:18:08.742030 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:18:08.748654 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:18:08.752265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:18:08.755429 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 22:18:08.762203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 22:18:08.765283 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 22:18:08.768272 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 22:18:08.774919 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5803 22:18:08.778338 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 22:18:08.782232 Total UI for P1: 0, mck2ui 16
5805 22:18:08.784857 best dqsien dly found for B0: ( 1, 2, 24)
5806 22:18:08.788473 Total UI for P1: 0, mck2ui 16
5807 22:18:08.791336 best dqsien dly found for B1: ( 1, 2, 26)
5808 22:18:08.795082 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5809 22:18:08.798229 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5810 22:18:08.798311
5811 22:18:08.801434 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5812 22:18:08.804524 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 22:18:08.807759 [Gating] SW calibration Done
5814 22:18:08.807856 ==
5815 22:18:08.811388 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 22:18:08.818012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 22:18:08.818097 ==
5818 22:18:08.818163 RX Vref Scan: 0
5819 22:18:08.818224
5820 22:18:08.821238 RX Vref 0 -> 0, step: 1
5821 22:18:08.821320
5822 22:18:08.824440 RX Delay -80 -> 252, step: 8
5823 22:18:08.827603 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5824 22:18:08.830734 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5825 22:18:08.834546 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5826 22:18:08.841256 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5827 22:18:08.844513 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5828 22:18:08.847712 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5829 22:18:08.850759 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5830 22:18:08.853991 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5831 22:18:08.857669 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5832 22:18:08.864302 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5833 22:18:08.867394 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5834 22:18:08.870465 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5835 22:18:08.874085 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5836 22:18:08.877408 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5837 22:18:08.883905 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5838 22:18:08.887496 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5839 22:18:08.887595 ==
5840 22:18:08.890601 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 22:18:08.893625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 22:18:08.893725 ==
5843 22:18:08.897101 DQS Delay:
5844 22:18:08.897200 DQS0 = 0, DQS1 = 0
5845 22:18:08.897291 DQM Delay:
5846 22:18:08.900237 DQM0 = 93, DQM1 = 88
5847 22:18:08.900306 DQ Delay:
5848 22:18:08.903469 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5849 22:18:08.907155 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5850 22:18:08.910407 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5851 22:18:08.913563 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5852 22:18:08.913669
5853 22:18:08.913760
5854 22:18:08.913849 ==
5855 22:18:08.916836 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:18:08.923354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:18:08.923440 ==
5858 22:18:08.923506
5859 22:18:08.923566
5860 22:18:08.923625 TX Vref Scan disable
5861 22:18:08.927221 == TX Byte 0 ==
5862 22:18:08.930301 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5863 22:18:08.936756 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5864 22:18:08.936869 == TX Byte 1 ==
5865 22:18:08.939960 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5866 22:18:08.946837 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5867 22:18:08.946954 ==
5868 22:18:08.950010 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 22:18:08.953236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 22:18:08.953347 ==
5871 22:18:08.953457
5872 22:18:08.953562
5873 22:18:08.957002 TX Vref Scan disable
5874 22:18:08.957106 == TX Byte 0 ==
5875 22:18:08.963327 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5876 22:18:08.966526 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5877 22:18:08.970085 == TX Byte 1 ==
5878 22:18:08.973094 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5879 22:18:08.976742 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5880 22:18:08.976850
5881 22:18:08.976952 [DATLAT]
5882 22:18:08.979872 Freq=933, CH1 RK1
5883 22:18:08.979976
5884 22:18:08.980078 DATLAT Default: 0xb
5885 22:18:08.982836 0, 0xFFFF, sum = 0
5886 22:18:08.986576 1, 0xFFFF, sum = 0
5887 22:18:08.986681 2, 0xFFFF, sum = 0
5888 22:18:08.989561 3, 0xFFFF, sum = 0
5889 22:18:08.989665 4, 0xFFFF, sum = 0
5890 22:18:08.992853 5, 0xFFFF, sum = 0
5891 22:18:08.992960 6, 0xFFFF, sum = 0
5892 22:18:08.996523 7, 0xFFFF, sum = 0
5893 22:18:08.996628 8, 0xFFFF, sum = 0
5894 22:18:08.999484 9, 0xFFFF, sum = 0
5895 22:18:08.999597 10, 0x0, sum = 1
5896 22:18:09.003008 11, 0x0, sum = 2
5897 22:18:09.003091 12, 0x0, sum = 3
5898 22:18:09.006269 13, 0x0, sum = 4
5899 22:18:09.006380 best_step = 11
5900 22:18:09.006475
5901 22:18:09.006566 ==
5902 22:18:09.009537 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 22:18:09.012644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 22:18:09.016368 ==
5905 22:18:09.016485 RX Vref Scan: 0
5906 22:18:09.016583
5907 22:18:09.019761 RX Vref 0 -> 0, step: 1
5908 22:18:09.019871
5909 22:18:09.019969 RX Delay -69 -> 252, step: 4
5910 22:18:09.027541 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5911 22:18:09.030592 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5912 22:18:09.033815 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5913 22:18:09.037526 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5914 22:18:09.040673 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5915 22:18:09.046983 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5916 22:18:09.050476 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5917 22:18:09.053662 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5918 22:18:09.056775 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5919 22:18:09.059980 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5920 22:18:09.066792 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5921 22:18:09.069929 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5922 22:18:09.073458 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5923 22:18:09.076518 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5924 22:18:09.080018 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5925 22:18:09.083117 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5926 22:18:09.086803 ==
5927 22:18:09.089690 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 22:18:09.093367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 22:18:09.093451 ==
5930 22:18:09.093516 DQS Delay:
5931 22:18:09.096304 DQS0 = 0, DQS1 = 0
5932 22:18:09.096387 DQM Delay:
5933 22:18:09.099895 DQM0 = 91, DQM1 = 90
5934 22:18:09.099978 DQ Delay:
5935 22:18:09.102882 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5936 22:18:09.106581 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
5937 22:18:09.109752 DQ8 =76, DQ9 =84, DQ10 =92, DQ11 =84
5938 22:18:09.113022 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =96
5939 22:18:09.113106
5940 22:18:09.113170
5941 22:18:09.119331 [DQSOSCAuto] RK1, (LSB)MR18= 0xd22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5942 22:18:09.123055 CH1 RK1: MR19=505, MR18=D22
5943 22:18:09.129277 CH1_RK1: MR19=0x505, MR18=0xD22, DQSOSC=411, MR23=63, INC=64, DEC=42
5944 22:18:09.132424 [RxdqsGatingPostProcess] freq 933
5945 22:18:09.139108 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 22:18:09.142285 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 22:18:09.146103 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 22:18:09.146186 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 22:18:09.149227 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 22:18:09.152495 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 22:18:09.155513 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 22:18:09.159229 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 22:18:09.162599 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 22:18:09.165633 Pre-setting of DQS Precalculation
5955 22:18:09.172000 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 22:18:09.178803 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 22:18:09.185537 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 22:18:09.185636
5959 22:18:09.185703
5960 22:18:09.188527 [Calibration Summary] 1866 Mbps
5961 22:18:09.188601 CH 0, Rank 0
5962 22:18:09.192177 SW Impedance : PASS
5963 22:18:09.195076 DUTY Scan : NO K
5964 22:18:09.195230 ZQ Calibration : PASS
5965 22:18:09.198663 Jitter Meter : NO K
5966 22:18:09.201818 CBT Training : PASS
5967 22:18:09.201911 Write leveling : PASS
5968 22:18:09.205317 RX DQS gating : PASS
5969 22:18:09.208113 RX DQ/DQS(RDDQC) : PASS
5970 22:18:09.208197 TX DQ/DQS : PASS
5971 22:18:09.211763 RX DATLAT : PASS
5972 22:18:09.214746 RX DQ/DQS(Engine): PASS
5973 22:18:09.214822 TX OE : NO K
5974 22:18:09.218042 All Pass.
5975 22:18:09.218132
5976 22:18:09.218197 CH 0, Rank 1
5977 22:18:09.221842 SW Impedance : PASS
5978 22:18:09.221917 DUTY Scan : NO K
5979 22:18:09.224955 ZQ Calibration : PASS
5980 22:18:09.228164 Jitter Meter : NO K
5981 22:18:09.228266 CBT Training : PASS
5982 22:18:09.231214 Write leveling : PASS
5983 22:18:09.234759 RX DQS gating : PASS
5984 22:18:09.234866 RX DQ/DQS(RDDQC) : PASS
5985 22:18:09.238122 TX DQ/DQS : PASS
5986 22:18:09.241321 RX DATLAT : PASS
5987 22:18:09.241442 RX DQ/DQS(Engine): PASS
5988 22:18:09.244405 TX OE : NO K
5989 22:18:09.244496 All Pass.
5990 22:18:09.244562
5991 22:18:09.248130 CH 1, Rank 0
5992 22:18:09.248222 SW Impedance : PASS
5993 22:18:09.251449 DUTY Scan : NO K
5994 22:18:09.254630 ZQ Calibration : PASS
5995 22:18:09.254706 Jitter Meter : NO K
5996 22:18:09.257662 CBT Training : PASS
5997 22:18:09.257735 Write leveling : PASS
5998 22:18:09.261427 RX DQS gating : PASS
5999 22:18:09.264589 RX DQ/DQS(RDDQC) : PASS
6000 22:18:09.264697 TX DQ/DQS : PASS
6001 22:18:09.267752 RX DATLAT : PASS
6002 22:18:09.270881 RX DQ/DQS(Engine): PASS
6003 22:18:09.270979 TX OE : NO K
6004 22:18:09.274608 All Pass.
6005 22:18:09.274701
6006 22:18:09.274769 CH 1, Rank 1
6007 22:18:09.277828 SW Impedance : PASS
6008 22:18:09.277912 DUTY Scan : NO K
6009 22:18:09.281033 ZQ Calibration : PASS
6010 22:18:09.284205 Jitter Meter : NO K
6011 22:18:09.284301 CBT Training : PASS
6012 22:18:09.287209 Write leveling : PASS
6013 22:18:09.290993 RX DQS gating : PASS
6014 22:18:09.291078 RX DQ/DQS(RDDQC) : PASS
6015 22:18:09.293864 TX DQ/DQS : PASS
6016 22:18:09.297798 RX DATLAT : PASS
6017 22:18:09.297879 RX DQ/DQS(Engine): PASS
6018 22:18:09.300907 TX OE : NO K
6019 22:18:09.300984 All Pass.
6020 22:18:09.301049
6021 22:18:09.303796 DramC Write-DBI off
6022 22:18:09.307143 PER_BANK_REFRESH: Hybrid Mode
6023 22:18:09.307222 TX_TRACKING: ON
6024 22:18:09.317143 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 22:18:09.320635 [FAST_K] Save calibration result to emmc
6026 22:18:09.323766 dramc_set_vcore_voltage set vcore to 650000
6027 22:18:09.326864 Read voltage for 400, 6
6028 22:18:09.326949 Vio18 = 0
6029 22:18:09.327014 Vcore = 650000
6030 22:18:09.330171 Vdram = 0
6031 22:18:09.330256 Vddq = 0
6032 22:18:09.330319 Vmddr = 0
6033 22:18:09.336851 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 22:18:09.339904 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 22:18:09.343806 MEM_TYPE=3, freq_sel=20
6036 22:18:09.347006 sv_algorithm_assistance_LP4_800
6037 22:18:09.350153 ============ PULL DRAM RESETB DOWN ============
6038 22:18:09.353296 ========== PULL DRAM RESETB DOWN end =========
6039 22:18:09.360204 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 22:18:09.363393 ===================================
6041 22:18:09.366625 LPDDR4 DRAM CONFIGURATION
6042 22:18:09.369767 ===================================
6043 22:18:09.369850 EX_ROW_EN[0] = 0x0
6044 22:18:09.373056 EX_ROW_EN[1] = 0x0
6045 22:18:09.373133 LP4Y_EN = 0x0
6046 22:18:09.376764 WORK_FSP = 0x0
6047 22:18:09.376846 WL = 0x2
6048 22:18:09.379921 RL = 0x2
6049 22:18:09.379995 BL = 0x2
6050 22:18:09.383137 RPST = 0x0
6051 22:18:09.383212 RD_PRE = 0x0
6052 22:18:09.386252 WR_PRE = 0x1
6053 22:18:09.389625 WR_PST = 0x0
6054 22:18:09.389712 DBI_WR = 0x0
6055 22:18:09.393349 DBI_RD = 0x0
6056 22:18:09.393435 OTF = 0x1
6057 22:18:09.396464 ===================================
6058 22:18:09.399261 ===================================
6059 22:18:09.399345 ANA top config
6060 22:18:09.402902 ===================================
6061 22:18:09.405993 DLL_ASYNC_EN = 0
6062 22:18:09.409630 ALL_SLAVE_EN = 1
6063 22:18:09.413021 NEW_RANK_MODE = 1
6064 22:18:09.415769 DLL_IDLE_MODE = 1
6065 22:18:09.415862 LP45_APHY_COMB_EN = 1
6066 22:18:09.419266 TX_ODT_DIS = 1
6067 22:18:09.422845 NEW_8X_MODE = 1
6068 22:18:09.425724 ===================================
6069 22:18:09.429181 ===================================
6070 22:18:09.432814 data_rate = 800
6071 22:18:09.435926 CKR = 1
6072 22:18:09.439095 DQ_P2S_RATIO = 4
6073 22:18:09.442161 ===================================
6074 22:18:09.442270 CA_P2S_RATIO = 4
6075 22:18:09.445881 DQ_CA_OPEN = 0
6076 22:18:09.449101 DQ_SEMI_OPEN = 1
6077 22:18:09.452230 CA_SEMI_OPEN = 1
6078 22:18:09.455435 CA_FULL_RATE = 0
6079 22:18:09.458638 DQ_CKDIV4_EN = 0
6080 22:18:09.458742 CA_CKDIV4_EN = 1
6081 22:18:09.462381 CA_PREDIV_EN = 0
6082 22:18:09.465300 PH8_DLY = 0
6083 22:18:09.468533 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 22:18:09.472328 DQ_AAMCK_DIV = 0
6085 22:18:09.475507 CA_AAMCK_DIV = 0
6086 22:18:09.475587 CA_ADMCK_DIV = 4
6087 22:18:09.478653 DQ_TRACK_CA_EN = 0
6088 22:18:09.482036 CA_PICK = 800
6089 22:18:09.485103 CA_MCKIO = 400
6090 22:18:09.488915 MCKIO_SEMI = 400
6091 22:18:09.492032 PLL_FREQ = 3016
6092 22:18:09.495222 DQ_UI_PI_RATIO = 32
6093 22:18:09.498436 CA_UI_PI_RATIO = 32
6094 22:18:09.501896 ===================================
6095 22:18:09.504871 ===================================
6096 22:18:09.504979 memory_type:LPDDR4
6097 22:18:09.508524 GP_NUM : 10
6098 22:18:09.511649 SRAM_EN : 1
6099 22:18:09.511757 MD32_EN : 0
6100 22:18:09.514913 ===================================
6101 22:18:09.518133 [ANA_INIT] >>>>>>>>>>>>>>
6102 22:18:09.521740 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 22:18:09.524714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 22:18:09.528141 ===================================
6105 22:18:09.531174 data_rate = 800,PCW = 0X7400
6106 22:18:09.534764 ===================================
6107 22:18:09.537764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 22:18:09.541282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 22:18:09.554524 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 22:18:09.557632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 22:18:09.560833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 22:18:09.564052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 22:18:09.567209 [ANA_INIT] flow start
6114 22:18:09.570963 [ANA_INIT] PLL >>>>>>>>
6115 22:18:09.571044 [ANA_INIT] PLL <<<<<<<<
6116 22:18:09.574110 [ANA_INIT] MIDPI >>>>>>>>
6117 22:18:09.577348 [ANA_INIT] MIDPI <<<<<<<<
6118 22:18:09.577468 [ANA_INIT] DLL >>>>>>>>
6119 22:18:09.580499 [ANA_INIT] flow end
6120 22:18:09.583756 ============ LP4 DIFF to SE enter ============
6121 22:18:09.587552 ============ LP4 DIFF to SE exit ============
6122 22:18:09.590733 [ANA_INIT] <<<<<<<<<<<<<
6123 22:18:09.593869 [Flow] Enable top DCM control >>>>>
6124 22:18:09.597197 [Flow] Enable top DCM control <<<<<
6125 22:18:09.600200 Enable DLL master slave shuffle
6126 22:18:09.606823 ==============================================================
6127 22:18:09.606949 Gating Mode config
6128 22:18:09.613424 ==============================================================
6129 22:18:09.617152 Config description:
6130 22:18:09.623398 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 22:18:09.630296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 22:18:09.636733 SELPH_MODE 0: By rank 1: By Phase
6133 22:18:09.643753 ==============================================================
6134 22:18:09.643871 GAT_TRACK_EN = 0
6135 22:18:09.646931 RX_GATING_MODE = 2
6136 22:18:09.649744 RX_GATING_TRACK_MODE = 2
6137 22:18:09.653227 SELPH_MODE = 1
6138 22:18:09.656637 PICG_EARLY_EN = 1
6139 22:18:09.659738 VALID_LAT_VALUE = 1
6140 22:18:09.666408 ==============================================================
6141 22:18:09.669579 Enter into Gating configuration >>>>
6142 22:18:09.672681 Exit from Gating configuration <<<<
6143 22:18:09.676458 Enter into DVFS_PRE_config >>>>>
6144 22:18:09.685991 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 22:18:09.689174 Exit from DVFS_PRE_config <<<<<
6146 22:18:09.693038 Enter into PICG configuration >>>>
6147 22:18:09.696271 Exit from PICG configuration <<<<
6148 22:18:09.699506 [RX_INPUT] configuration >>>>>
6149 22:18:09.702734 [RX_INPUT] configuration <<<<<
6150 22:18:09.705909 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 22:18:09.712177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 22:18:09.718925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 22:18:09.725592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 22:18:09.729307 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 22:18:09.735751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 22:18:09.738695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 22:18:09.745882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 22:18:09.748668 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 22:18:09.752050 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 22:18:09.755526 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 22:18:09.761967 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 22:18:09.765659 ===================================
6163 22:18:09.768711 LPDDR4 DRAM CONFIGURATION
6164 22:18:09.771810 ===================================
6165 22:18:09.771894 EX_ROW_EN[0] = 0x0
6166 22:18:09.775057 EX_ROW_EN[1] = 0x0
6167 22:18:09.775134 LP4Y_EN = 0x0
6168 22:18:09.778215 WORK_FSP = 0x0
6169 22:18:09.778291 WL = 0x2
6170 22:18:09.781938 RL = 0x2
6171 22:18:09.782020 BL = 0x2
6172 22:18:09.785098 RPST = 0x0
6173 22:18:09.785176 RD_PRE = 0x0
6174 22:18:09.788196 WR_PRE = 0x1
6175 22:18:09.788273 WR_PST = 0x0
6176 22:18:09.791439 DBI_WR = 0x0
6177 22:18:09.795279 DBI_RD = 0x0
6178 22:18:09.795355 OTF = 0x1
6179 22:18:09.798547 ===================================
6180 22:18:09.801759 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 22:18:09.804931 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 22:18:09.811341 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 22:18:09.814418 ===================================
6184 22:18:09.818146 LPDDR4 DRAM CONFIGURATION
6185 22:18:09.821201 ===================================
6186 22:18:09.821278 EX_ROW_EN[0] = 0x10
6187 22:18:09.824793 EX_ROW_EN[1] = 0x0
6188 22:18:09.824874 LP4Y_EN = 0x0
6189 22:18:09.827707 WORK_FSP = 0x0
6190 22:18:09.827781 WL = 0x2
6191 22:18:09.831218 RL = 0x2
6192 22:18:09.831297 BL = 0x2
6193 22:18:09.834388 RPST = 0x0
6194 22:18:09.837644 RD_PRE = 0x0
6195 22:18:09.837725 WR_PRE = 0x1
6196 22:18:09.840742 WR_PST = 0x0
6197 22:18:09.840836 DBI_WR = 0x0
6198 22:18:09.844303 DBI_RD = 0x0
6199 22:18:09.844390 OTF = 0x1
6200 22:18:09.847518 ===================================
6201 22:18:09.854148 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 22:18:09.857862 nWR fixed to 30
6203 22:18:09.861693 [ModeRegInit_LP4] CH0 RK0
6204 22:18:09.861780 [ModeRegInit_LP4] CH0 RK1
6205 22:18:09.864632 [ModeRegInit_LP4] CH1 RK0
6206 22:18:09.868189 [ModeRegInit_LP4] CH1 RK1
6207 22:18:09.868277 match AC timing 19
6208 22:18:09.874591 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 22:18:09.877848 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 22:18:09.880878 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 22:18:09.887214 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 22:18:09.891030 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 22:18:09.891114 ==
6214 22:18:09.894259 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 22:18:09.897473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 22:18:09.897558 ==
6217 22:18:09.903914 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 22:18:09.910700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6219 22:18:09.913889 [CA 0] Center 36 (8~64) winsize 57
6220 22:18:09.917061 [CA 1] Center 36 (8~64) winsize 57
6221 22:18:09.920246 [CA 2] Center 36 (8~64) winsize 57
6222 22:18:09.923988 [CA 3] Center 36 (8~64) winsize 57
6223 22:18:09.927105 [CA 4] Center 36 (8~64) winsize 57
6224 22:18:09.930205 [CA 5] Center 36 (8~64) winsize 57
6225 22:18:09.930289
6226 22:18:09.933328 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6227 22:18:09.933412
6228 22:18:09.936884 [CATrainingPosCal] consider 1 rank data
6229 22:18:09.940396 u2DelayCellTimex100 = 270/100 ps
6230 22:18:09.943566 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:18:09.946657 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:18:09.950302 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:18:09.953306 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:18:09.956545 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:18:09.960473 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:18:09.960553
6237 22:18:09.966477 CA PerBit enable=1, Macro0, CA PI delay=36
6238 22:18:09.966590
6239 22:18:09.966686 [CBTSetCACLKResult] CA Dly = 36
6240 22:18:09.970077 CS Dly: 1 (0~32)
6241 22:18:09.970176 ==
6242 22:18:09.973049 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 22:18:09.976584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 22:18:09.976667 ==
6245 22:18:09.983284 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 22:18:09.989450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6247 22:18:09.992618 [CA 0] Center 36 (8~64) winsize 57
6248 22:18:09.996461 [CA 1] Center 36 (8~64) winsize 57
6249 22:18:09.999672 [CA 2] Center 36 (8~64) winsize 57
6250 22:18:10.002868 [CA 3] Center 36 (8~64) winsize 57
6251 22:18:10.006171 [CA 4] Center 36 (8~64) winsize 57
6252 22:18:10.006275 [CA 5] Center 36 (8~64) winsize 57
6253 22:18:10.009350
6254 22:18:10.012443 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6255 22:18:10.012520
6256 22:18:10.015649 [CATrainingPosCal] consider 2 rank data
6257 22:18:10.019397 u2DelayCellTimex100 = 270/100 ps
6258 22:18:10.022691 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 22:18:10.025707 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:18:10.028850 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:18:10.032511 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 22:18:10.035653 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:18:10.038921 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:18:10.039004
6265 22:18:10.041989 CA PerBit enable=1, Macro0, CA PI delay=36
6266 22:18:10.045500
6267 22:18:10.045615 [CBTSetCACLKResult] CA Dly = 36
6268 22:18:10.048980 CS Dly: 1 (0~32)
6269 22:18:10.049091
6270 22:18:10.052127 ----->DramcWriteLeveling(PI) begin...
6271 22:18:10.052236 ==
6272 22:18:10.055733 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 22:18:10.058728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 22:18:10.058844 ==
6275 22:18:10.061966 Write leveling (Byte 0): 40 => 8
6276 22:18:10.065104 Write leveling (Byte 1): 40 => 8
6277 22:18:10.068782 DramcWriteLeveling(PI) end<-----
6278 22:18:10.068893
6279 22:18:10.068988 ==
6280 22:18:10.071848 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 22:18:10.075442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 22:18:10.078266 ==
6283 22:18:10.078392 [Gating] SW mode calibration
6284 22:18:10.085226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 22:18:10.091851 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 22:18:10.094871 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 22:18:10.101848 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 22:18:10.104977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 22:18:10.108438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 22:18:10.114847 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 22:18:10.117997 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 22:18:10.121172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 22:18:10.128123 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 22:18:10.131319 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 22:18:10.134583 Total UI for P1: 0, mck2ui 16
6296 22:18:10.138224 best dqsien dly found for B0: ( 0, 14, 24)
6297 22:18:10.141310 Total UI for P1: 0, mck2ui 16
6298 22:18:10.144558 best dqsien dly found for B1: ( 0, 14, 24)
6299 22:18:10.148202 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 22:18:10.151243 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 22:18:10.151345
6302 22:18:10.154678 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 22:18:10.157624 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 22:18:10.161321 [Gating] SW calibration Done
6305 22:18:10.161429 ==
6306 22:18:10.164529 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 22:18:10.170963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 22:18:10.171048 ==
6309 22:18:10.171112 RX Vref Scan: 0
6310 22:18:10.171173
6311 22:18:10.174513 RX Vref 0 -> 0, step: 1
6312 22:18:10.174614
6313 22:18:10.177549 RX Delay -410 -> 252, step: 16
6314 22:18:10.180637 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6315 22:18:10.184173 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6316 22:18:10.190552 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6317 22:18:10.194430 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6318 22:18:10.197433 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6319 22:18:10.200474 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6320 22:18:10.207394 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6321 22:18:10.210623 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6322 22:18:10.213803 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6323 22:18:10.216922 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6324 22:18:10.223829 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6325 22:18:10.227137 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6326 22:18:10.230168 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6327 22:18:10.233466 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6328 22:18:10.240524 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6329 22:18:10.243540 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6330 22:18:10.243623 ==
6331 22:18:10.246529 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 22:18:10.249749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 22:18:10.253010 ==
6334 22:18:10.253122 DQS Delay:
6335 22:18:10.253215 DQS0 = 59, DQS1 = 67
6336 22:18:10.256709 DQM Delay:
6337 22:18:10.256783 DQM0 = 18, DQM1 = 17
6338 22:18:10.259745 DQ Delay:
6339 22:18:10.259822 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6340 22:18:10.262825 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6341 22:18:10.266555 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6342 22:18:10.269543 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6343 22:18:10.269622
6344 22:18:10.269686
6345 22:18:10.273110 ==
6346 22:18:10.276178 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:18:10.280122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:18:10.280199 ==
6349 22:18:10.280265
6350 22:18:10.280325
6351 22:18:10.283022 TX Vref Scan disable
6352 22:18:10.283121 == TX Byte 0 ==
6353 22:18:10.286462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 22:18:10.292915 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 22:18:10.293022 == TX Byte 1 ==
6356 22:18:10.296007 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 22:18:10.302981 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 22:18:10.303090 ==
6359 22:18:10.306013 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 22:18:10.309040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 22:18:10.309119 ==
6362 22:18:10.309183
6363 22:18:10.309242
6364 22:18:10.312294 TX Vref Scan disable
6365 22:18:10.312369 == TX Byte 0 ==
6366 22:18:10.316267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 22:18:10.322455 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 22:18:10.322560 == TX Byte 1 ==
6369 22:18:10.325918 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6370 22:18:10.332303 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6371 22:18:10.332380
6372 22:18:10.332443 [DATLAT]
6373 22:18:10.335469 Freq=400, CH0 RK0
6374 22:18:10.335558
6375 22:18:10.335623 DATLAT Default: 0xf
6376 22:18:10.339422 0, 0xFFFF, sum = 0
6377 22:18:10.339516 1, 0xFFFF, sum = 0
6378 22:18:10.342424 2, 0xFFFF, sum = 0
6379 22:18:10.342503 3, 0xFFFF, sum = 0
6380 22:18:10.345613 4, 0xFFFF, sum = 0
6381 22:18:10.345716 5, 0xFFFF, sum = 0
6382 22:18:10.348855 6, 0xFFFF, sum = 0
6383 22:18:10.348960 7, 0xFFFF, sum = 0
6384 22:18:10.351839 8, 0xFFFF, sum = 0
6385 22:18:10.351921 9, 0xFFFF, sum = 0
6386 22:18:10.355596 10, 0xFFFF, sum = 0
6387 22:18:10.358725 11, 0xFFFF, sum = 0
6388 22:18:10.358853 12, 0xFFFF, sum = 0
6389 22:18:10.361822 13, 0x0, sum = 1
6390 22:18:10.361928 14, 0x0, sum = 2
6391 22:18:10.364822 15, 0x0, sum = 3
6392 22:18:10.364929 16, 0x0, sum = 4
6393 22:18:10.365024 best_step = 14
6394 22:18:10.365117
6395 22:18:10.368492 ==
6396 22:18:10.371633 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 22:18:10.374675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 22:18:10.374778 ==
6399 22:18:10.374871 RX Vref Scan: 1
6400 22:18:10.374934
6401 22:18:10.378355 RX Vref 0 -> 0, step: 1
6402 22:18:10.378455
6403 22:18:10.381696 RX Delay -375 -> 252, step: 8
6404 22:18:10.381794
6405 22:18:10.384716 Set Vref, RX VrefLevel [Byte0]: 60
6406 22:18:10.388558 [Byte1]: 54
6407 22:18:10.392382
6408 22:18:10.392498 Final RX Vref Byte 0 = 60 to rank0
6409 22:18:10.395056 Final RX Vref Byte 1 = 54 to rank0
6410 22:18:10.398469 Final RX Vref Byte 0 = 60 to rank1
6411 22:18:10.402031 Final RX Vref Byte 1 = 54 to rank1==
6412 22:18:10.405459 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 22:18:10.411773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 22:18:10.411863 ==
6415 22:18:10.411931 DQS Delay:
6416 22:18:10.414939 DQS0 = 60, DQS1 = 68
6417 22:18:10.415020 DQM Delay:
6418 22:18:10.415085 DQM0 = 15, DQM1 = 13
6419 22:18:10.418674 DQ Delay:
6420 22:18:10.421927 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =16
6421 22:18:10.425230 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6422 22:18:10.428379 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6423 22:18:10.431563 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6424 22:18:10.431654
6425 22:18:10.431723
6426 22:18:10.438018 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6427 22:18:10.441182 CH0 RK0: MR19=C0C, MR18=7E7D
6428 22:18:10.448153 CH0_RK0: MR19=0xC0C, MR18=0x7E7D, DQSOSC=393, MR23=63, INC=382, DEC=254
6429 22:18:10.448238 ==
6430 22:18:10.451382 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 22:18:10.454578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 22:18:10.454659 ==
6433 22:18:10.457568 [Gating] SW mode calibration
6434 22:18:10.464308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 22:18:10.470970 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 22:18:10.474197 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 22:18:10.477900 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 22:18:10.484102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 22:18:10.487141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 22:18:10.493730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 22:18:10.497545 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 22:18:10.500782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 22:18:10.507043 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 22:18:10.510436 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 22:18:10.513757 Total UI for P1: 0, mck2ui 16
6446 22:18:10.516751 best dqsien dly found for B0: ( 0, 14, 24)
6447 22:18:10.520200 Total UI for P1: 0, mck2ui 16
6448 22:18:10.523202 best dqsien dly found for B1: ( 0, 14, 24)
6449 22:18:10.526942 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 22:18:10.530112 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 22:18:10.530197
6452 22:18:10.533309 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 22:18:10.536613 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 22:18:10.539753 [Gating] SW calibration Done
6455 22:18:10.539835 ==
6456 22:18:10.543059 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 22:18:10.546247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 22:18:10.549582 ==
6459 22:18:10.549668 RX Vref Scan: 0
6460 22:18:10.549735
6461 22:18:10.553352 RX Vref 0 -> 0, step: 1
6462 22:18:10.553437
6463 22:18:10.556564 RX Delay -410 -> 252, step: 16
6464 22:18:10.559699 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6465 22:18:10.562794 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6466 22:18:10.566606 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6467 22:18:10.573004 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6468 22:18:10.576009 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6469 22:18:10.579254 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6470 22:18:10.583098 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6471 22:18:10.589468 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6472 22:18:10.592509 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6473 22:18:10.596135 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6474 22:18:10.599254 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6475 22:18:10.605730 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6476 22:18:10.609599 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6477 22:18:10.612873 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6478 22:18:10.619279 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6479 22:18:10.622705 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6480 22:18:10.622814 ==
6481 22:18:10.625814 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 22:18:10.628825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 22:18:10.628931 ==
6484 22:18:10.632432 DQS Delay:
6485 22:18:10.632537 DQS0 = 59, DQS1 = 59
6486 22:18:10.635576 DQM Delay:
6487 22:18:10.635654 DQM0 = 17, DQM1 = 10
6488 22:18:10.635749 DQ Delay:
6489 22:18:10.638798 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6490 22:18:10.642122 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6491 22:18:10.645529 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6492 22:18:10.648610 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6493 22:18:10.648692
6494 22:18:10.648758
6495 22:18:10.648818 ==
6496 22:18:10.651875 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:18:10.658446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:18:10.658531 ==
6499 22:18:10.658597
6500 22:18:10.658658
6501 22:18:10.658717 TX Vref Scan disable
6502 22:18:10.661731 == TX Byte 0 ==
6503 22:18:10.665436 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6504 22:18:10.668629 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6505 22:18:10.671652 == TX Byte 1 ==
6506 22:18:10.675507 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6507 22:18:10.678212 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6508 22:18:10.681794 ==
6509 22:18:10.684951 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 22:18:10.688209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 22:18:10.688289 ==
6512 22:18:10.688354
6513 22:18:10.688416
6514 22:18:10.691589 TX Vref Scan disable
6515 22:18:10.691670 == TX Byte 0 ==
6516 22:18:10.694535 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6517 22:18:10.701450 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6518 22:18:10.701531 == TX Byte 1 ==
6519 22:18:10.704567 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6520 22:18:10.711547 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6521 22:18:10.711630
6522 22:18:10.711697 [DATLAT]
6523 22:18:10.711758 Freq=400, CH0 RK1
6524 22:18:10.711818
6525 22:18:10.714481 DATLAT Default: 0xe
6526 22:18:10.717516 0, 0xFFFF, sum = 0
6527 22:18:10.717593 1, 0xFFFF, sum = 0
6528 22:18:10.721072 2, 0xFFFF, sum = 0
6529 22:18:10.721149 3, 0xFFFF, sum = 0
6530 22:18:10.724698 4, 0xFFFF, sum = 0
6531 22:18:10.724776 5, 0xFFFF, sum = 0
6532 22:18:10.727650 6, 0xFFFF, sum = 0
6533 22:18:10.727726 7, 0xFFFF, sum = 0
6534 22:18:10.730906 8, 0xFFFF, sum = 0
6535 22:18:10.730992 9, 0xFFFF, sum = 0
6536 22:18:10.734339 10, 0xFFFF, sum = 0
6537 22:18:10.734417 11, 0xFFFF, sum = 0
6538 22:18:10.737329 12, 0xFFFF, sum = 0
6539 22:18:10.737406 13, 0x0, sum = 1
6540 22:18:10.741224 14, 0x0, sum = 2
6541 22:18:10.741337 15, 0x0, sum = 3
6542 22:18:10.744365 16, 0x0, sum = 4
6543 22:18:10.744450 best_step = 14
6544 22:18:10.744536
6545 22:18:10.744603 ==
6546 22:18:10.747552 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 22:18:10.753850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 22:18:10.753947 ==
6549 22:18:10.754014 RX Vref Scan: 0
6550 22:18:10.754077
6551 22:18:10.757747 RX Vref 0 -> 0, step: 1
6552 22:18:10.757824
6553 22:18:10.760866 RX Delay -359 -> 252, step: 8
6554 22:18:10.767153 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6555 22:18:10.770284 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6556 22:18:10.774242 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6557 22:18:10.777237 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6558 22:18:10.784026 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6559 22:18:10.786943 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6560 22:18:10.790088 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6561 22:18:10.793342 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6562 22:18:10.800166 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6563 22:18:10.803316 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6564 22:18:10.806471 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6565 22:18:10.813118 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6566 22:18:10.816546 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6567 22:18:10.819750 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6568 22:18:10.823327 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6569 22:18:10.829700 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6570 22:18:10.829813 ==
6571 22:18:10.833267 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 22:18:10.836249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 22:18:10.836339 ==
6574 22:18:10.836406 DQS Delay:
6575 22:18:10.839780 DQS0 = 60, DQS1 = 72
6576 22:18:10.839856 DQM Delay:
6577 22:18:10.843364 DQM0 = 11, DQM1 = 17
6578 22:18:10.843468 DQ Delay:
6579 22:18:10.846497 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6580 22:18:10.849661 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6581 22:18:10.852971 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6582 22:18:10.856168 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6583 22:18:10.856247
6584 22:18:10.856323
6585 22:18:10.862540 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6586 22:18:10.866375 CH0 RK1: MR19=C0C, MR18=C87E
6587 22:18:10.872786 CH0_RK1: MR19=0xC0C, MR18=0xC87E, DQSOSC=385, MR23=63, INC=398, DEC=265
6588 22:18:10.875880 [RxdqsGatingPostProcess] freq 400
6589 22:18:10.882824 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 22:18:10.886069 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 22:18:10.889230 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 22:18:10.892209 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 22:18:10.895706 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 22:18:10.895790 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 22:18:10.898976 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 22:18:10.902630 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 22:18:10.905582 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 22:18:10.909234 Pre-setting of DQS Precalculation
6599 22:18:10.915535 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 22:18:10.915623 ==
6601 22:18:10.919340 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 22:18:10.922157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 22:18:10.922241 ==
6604 22:18:10.929087 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 22:18:10.935198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6606 22:18:10.938543 [CA 0] Center 36 (8~64) winsize 57
6607 22:18:10.942084 [CA 1] Center 36 (8~64) winsize 57
6608 22:18:10.942168 [CA 2] Center 36 (8~64) winsize 57
6609 22:18:10.945162 [CA 3] Center 36 (8~64) winsize 57
6610 22:18:10.948679 [CA 4] Center 36 (8~64) winsize 57
6611 22:18:10.951582 [CA 5] Center 36 (8~64) winsize 57
6612 22:18:10.951674
6613 22:18:10.955022 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6614 22:18:10.958257
6615 22:18:10.961589 [CATrainingPosCal] consider 1 rank data
6616 22:18:10.961677 u2DelayCellTimex100 = 270/100 ps
6617 22:18:10.968595 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:18:10.971703 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:18:10.974970 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:18:10.978122 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:18:10.981267 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:18:10.984521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:18:10.984595
6624 22:18:10.988324 CA PerBit enable=1, Macro0, CA PI delay=36
6625 22:18:10.988407
6626 22:18:10.991510 [CBTSetCACLKResult] CA Dly = 36
6627 22:18:10.994722 CS Dly: 1 (0~32)
6628 22:18:10.994802 ==
6629 22:18:10.997798 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 22:18:11.001350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 22:18:11.001435 ==
6632 22:18:11.007554 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 22:18:11.014441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 22:18:11.017565 [CA 0] Center 36 (8~64) winsize 57
6635 22:18:11.017644 [CA 1] Center 36 (8~64) winsize 57
6636 22:18:11.021369 [CA 2] Center 36 (8~64) winsize 57
6637 22:18:11.024546 [CA 3] Center 36 (8~64) winsize 57
6638 22:18:11.027557 [CA 4] Center 36 (8~64) winsize 57
6639 22:18:11.031114 [CA 5] Center 36 (8~64) winsize 57
6640 22:18:11.031195
6641 22:18:11.034024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 22:18:11.034099
6643 22:18:11.040447 [CATrainingPosCal] consider 2 rank data
6644 22:18:11.040539 u2DelayCellTimex100 = 270/100 ps
6645 22:18:11.047513 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 22:18:11.050430 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:18:11.054098 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:18:11.057443 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 22:18:11.060370 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:18:11.064007 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:18:11.064092
6652 22:18:11.067133 CA PerBit enable=1, Macro0, CA PI delay=36
6653 22:18:11.067217
6654 22:18:11.070595 [CBTSetCACLKResult] CA Dly = 36
6655 22:18:11.073648 CS Dly: 1 (0~32)
6656 22:18:11.073758
6657 22:18:11.076949 ----->DramcWriteLeveling(PI) begin...
6658 22:18:11.077033 ==
6659 22:18:11.080104 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 22:18:11.083251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 22:18:11.083341 ==
6662 22:18:11.086501 Write leveling (Byte 0): 40 => 8
6663 22:18:11.090199 Write leveling (Byte 1): 40 => 8
6664 22:18:11.093464 DramcWriteLeveling(PI) end<-----
6665 22:18:11.093544
6666 22:18:11.093607 ==
6667 22:18:11.096624 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 22:18:11.099856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 22:18:11.099934 ==
6670 22:18:11.103625 [Gating] SW mode calibration
6671 22:18:11.109705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 22:18:11.116265 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 22:18:11.119574 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 22:18:11.123211 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 22:18:11.129606 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 22:18:11.132695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 22:18:11.139512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 22:18:11.142933 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 22:18:11.146067 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 22:18:11.152484 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 22:18:11.155904 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 22:18:11.158743 Total UI for P1: 0, mck2ui 16
6683 22:18:11.162276 best dqsien dly found for B0: ( 0, 14, 24)
6684 22:18:11.165866 Total UI for P1: 0, mck2ui 16
6685 22:18:11.168975 best dqsien dly found for B1: ( 0, 14, 24)
6686 22:18:11.172496 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 22:18:11.175523 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 22:18:11.175634
6689 22:18:11.178630 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 22:18:11.181806 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 22:18:11.185020 [Gating] SW calibration Done
6692 22:18:11.185135 ==
6693 22:18:11.188847 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 22:18:11.192062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 22:18:11.195362 ==
6696 22:18:11.195447 RX Vref Scan: 0
6697 22:18:11.195516
6698 22:18:11.198435 RX Vref 0 -> 0, step: 1
6699 22:18:11.198508
6700 22:18:11.201691 RX Delay -410 -> 252, step: 16
6701 22:18:11.205414 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6702 22:18:11.208416 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6703 22:18:11.211472 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6704 22:18:11.218269 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6705 22:18:11.221786 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6706 22:18:11.224885 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6707 22:18:11.228149 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6708 22:18:11.234964 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6709 22:18:11.237828 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6710 22:18:11.241036 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6711 22:18:11.247684 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6712 22:18:11.251347 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6713 22:18:11.254546 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6714 22:18:11.257777 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6715 22:18:11.264326 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6716 22:18:11.267625 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6717 22:18:11.267710 ==
6718 22:18:11.271234 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 22:18:11.274263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 22:18:11.274348 ==
6721 22:18:11.277191 DQS Delay:
6722 22:18:11.277276 DQS0 = 51, DQS1 = 67
6723 22:18:11.280928 DQM Delay:
6724 22:18:11.281013 DQM0 = 12, DQM1 = 18
6725 22:18:11.283996 DQ Delay:
6726 22:18:11.284085 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6727 22:18:11.287129 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6728 22:18:11.290375 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6729 22:18:11.293563 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6730 22:18:11.293644
6731 22:18:11.293734
6732 22:18:11.293797 ==
6733 22:18:11.296842 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:18:11.304016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:18:11.304105 ==
6736 22:18:11.304184
6737 22:18:11.304246
6738 22:18:11.304305 TX Vref Scan disable
6739 22:18:11.307334 == TX Byte 0 ==
6740 22:18:11.310360 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 22:18:11.317006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 22:18:11.317091 == TX Byte 1 ==
6743 22:18:11.320140 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 22:18:11.326845 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 22:18:11.326948 ==
6746 22:18:11.329967 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 22:18:11.333191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 22:18:11.333280 ==
6749 22:18:11.333347
6750 22:18:11.333419
6751 22:18:11.336276 TX Vref Scan disable
6752 22:18:11.336354 == TX Byte 0 ==
6753 22:18:11.339998 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 22:18:11.346305 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 22:18:11.346397 == TX Byte 1 ==
6756 22:18:11.349464 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6757 22:18:11.356136 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6758 22:18:11.356218
6759 22:18:11.356284 [DATLAT]
6760 22:18:11.356345 Freq=400, CH1 RK0
6761 22:18:11.356404
6762 22:18:11.359954 DATLAT Default: 0xf
6763 22:18:11.363070 0, 0xFFFF, sum = 0
6764 22:18:11.363146 1, 0xFFFF, sum = 0
6765 22:18:11.366189 2, 0xFFFF, sum = 0
6766 22:18:11.366268 3, 0xFFFF, sum = 0
6767 22:18:11.369803 4, 0xFFFF, sum = 0
6768 22:18:11.369878 5, 0xFFFF, sum = 0
6769 22:18:11.372749 6, 0xFFFF, sum = 0
6770 22:18:11.372830 7, 0xFFFF, sum = 0
6771 22:18:11.376348 8, 0xFFFF, sum = 0
6772 22:18:11.376425 9, 0xFFFF, sum = 0
6773 22:18:11.379348 10, 0xFFFF, sum = 0
6774 22:18:11.379433 11, 0xFFFF, sum = 0
6775 22:18:11.382971 12, 0xFFFF, sum = 0
6776 22:18:11.383055 13, 0x0, sum = 1
6777 22:18:11.385980 14, 0x0, sum = 2
6778 22:18:11.386094 15, 0x0, sum = 3
6779 22:18:11.389564 16, 0x0, sum = 4
6780 22:18:11.389648 best_step = 14
6781 22:18:11.389713
6782 22:18:11.389774 ==
6783 22:18:11.392773 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 22:18:11.399092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 22:18:11.399177 ==
6786 22:18:11.399242 RX Vref Scan: 1
6787 22:18:11.399303
6788 22:18:11.402383 RX Vref 0 -> 0, step: 1
6789 22:18:11.402465
6790 22:18:11.405558 RX Delay -375 -> 252, step: 8
6791 22:18:11.405641
6792 22:18:11.408800 Set Vref, RX VrefLevel [Byte0]: 55
6793 22:18:11.412003 [Byte1]: 49
6794 22:18:11.415786
6795 22:18:11.415869 Final RX Vref Byte 0 = 55 to rank0
6796 22:18:11.418765 Final RX Vref Byte 1 = 49 to rank0
6797 22:18:11.422073 Final RX Vref Byte 0 = 55 to rank1
6798 22:18:11.425750 Final RX Vref Byte 1 = 49 to rank1==
6799 22:18:11.429161 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 22:18:11.435552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 22:18:11.435638 ==
6802 22:18:11.435703 DQS Delay:
6803 22:18:11.438939 DQS0 = 52, DQS1 = 68
6804 22:18:11.439022 DQM Delay:
6805 22:18:11.439087 DQM0 = 10, DQM1 = 14
6806 22:18:11.441875 DQ Delay:
6807 22:18:11.445582 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6808 22:18:11.445696 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6809 22:18:11.448662 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6810 22:18:11.451787 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6811 22:18:11.451873
6812 22:18:11.455482
6813 22:18:11.461555 [DQSOSCAuto] RK0, (LSB)MR18= 0x576b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6814 22:18:11.465208 CH1 RK0: MR19=C0C, MR18=576B
6815 22:18:11.471484 CH1_RK0: MR19=0xC0C, MR18=0x576B, DQSOSC=396, MR23=63, INC=376, DEC=251
6816 22:18:11.471569 ==
6817 22:18:11.475120 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 22:18:11.478170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 22:18:11.478256 ==
6820 22:18:11.481760 [Gating] SW mode calibration
6821 22:18:11.488030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 22:18:11.494600 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 22:18:11.498181 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 22:18:11.501261 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 22:18:11.508256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 22:18:11.511439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 22:18:11.514597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 22:18:11.521545 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 22:18:11.524665 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 22:18:11.527741 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 22:18:11.534057 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 22:18:11.534168 Total UI for P1: 0, mck2ui 16
6833 22:18:11.540856 best dqsien dly found for B0: ( 0, 14, 24)
6834 22:18:11.540941 Total UI for P1: 0, mck2ui 16
6835 22:18:11.547569 best dqsien dly found for B1: ( 0, 14, 24)
6836 22:18:11.550625 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 22:18:11.554194 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 22:18:11.554309
6839 22:18:11.557304 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 22:18:11.560687 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 22:18:11.563750 [Gating] SW calibration Done
6842 22:18:11.563834 ==
6843 22:18:11.567432 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 22:18:11.570619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 22:18:11.570703 ==
6846 22:18:11.573802 RX Vref Scan: 0
6847 22:18:11.573885
6848 22:18:11.576939 RX Vref 0 -> 0, step: 1
6849 22:18:11.577048
6850 22:18:11.577146 RX Delay -410 -> 252, step: 16
6851 22:18:11.583572 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6852 22:18:11.587166 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6853 22:18:11.590138 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6854 22:18:11.596823 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6855 22:18:11.600337 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6856 22:18:11.603312 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6857 22:18:11.606493 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6858 22:18:11.613383 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6859 22:18:11.616633 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6860 22:18:11.619854 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6861 22:18:11.623441 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6862 22:18:11.629692 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6863 22:18:11.632950 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6864 22:18:11.636600 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6865 22:18:11.639836 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6866 22:18:11.645990 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6867 22:18:11.646079 ==
6868 22:18:11.649812 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 22:18:11.652794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 22:18:11.652872 ==
6871 22:18:11.652936 DQS Delay:
6872 22:18:11.655803 DQS0 = 59, DQS1 = 59
6873 22:18:11.655888 DQM Delay:
6874 22:18:11.659401 DQM0 = 19, DQM1 = 13
6875 22:18:11.659512 DQ Delay:
6876 22:18:11.662540 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6877 22:18:11.666318 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6878 22:18:11.669495 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6879 22:18:11.672652 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6880 22:18:11.672737
6881 22:18:11.672802
6882 22:18:11.672864 ==
6883 22:18:11.675654 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:18:11.679474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:18:11.682636 ==
6886 22:18:11.682721
6887 22:18:11.682787
6888 22:18:11.682861 TX Vref Scan disable
6889 22:18:11.685657 == TX Byte 0 ==
6890 22:18:11.689277 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 22:18:11.692334 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 22:18:11.695612 == TX Byte 1 ==
6893 22:18:11.699212 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6894 22:18:11.702216 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6895 22:18:11.702325 ==
6896 22:18:11.705201 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 22:18:11.712057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 22:18:11.712166 ==
6899 22:18:11.712280
6900 22:18:11.712375
6901 22:18:11.712474 TX Vref Scan disable
6902 22:18:11.715268 == TX Byte 0 ==
6903 22:18:11.718525 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6904 22:18:11.722295 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6905 22:18:11.725522 == TX Byte 1 ==
6906 22:18:11.728611 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6907 22:18:11.731652 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6908 22:18:11.731763
6909 22:18:11.735714 [DATLAT]
6910 22:18:11.735825 Freq=400, CH1 RK1
6911 22:18:11.735922
6912 22:18:11.738596 DATLAT Default: 0xe
6913 22:18:11.738702 0, 0xFFFF, sum = 0
6914 22:18:11.741852 1, 0xFFFF, sum = 0
6915 22:18:11.741937 2, 0xFFFF, sum = 0
6916 22:18:11.745345 3, 0xFFFF, sum = 0
6917 22:18:11.745467 4, 0xFFFF, sum = 0
6918 22:18:11.748236 5, 0xFFFF, sum = 0
6919 22:18:11.748346 6, 0xFFFF, sum = 0
6920 22:18:11.751416 7, 0xFFFF, sum = 0
6921 22:18:11.751526 8, 0xFFFF, sum = 0
6922 22:18:11.755145 9, 0xFFFF, sum = 0
6923 22:18:11.758254 10, 0xFFFF, sum = 0
6924 22:18:11.758360 11, 0xFFFF, sum = 0
6925 22:18:11.761343 12, 0xFFFF, sum = 0
6926 22:18:11.761450 13, 0x0, sum = 1
6927 22:18:11.765053 14, 0x0, sum = 2
6928 22:18:11.765162 15, 0x0, sum = 3
6929 22:18:11.767998 16, 0x0, sum = 4
6930 22:18:11.768108 best_step = 14
6931 22:18:11.768206
6932 22:18:11.768295 ==
6933 22:18:11.771130 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 22:18:11.774489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 22:18:11.774575 ==
6936 22:18:11.778114 RX Vref Scan: 0
6937 22:18:11.778188
6938 22:18:11.781096 RX Vref 0 -> 0, step: 1
6939 22:18:11.781179
6940 22:18:11.781245 RX Delay -359 -> 252, step: 8
6941 22:18:11.789858 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6942 22:18:11.793295 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6943 22:18:11.796887 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6944 22:18:11.803566 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6945 22:18:11.806779 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6946 22:18:11.809789 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6947 22:18:11.813497 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6948 22:18:11.819828 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6949 22:18:11.822965 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6950 22:18:11.826275 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6951 22:18:11.829506 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6952 22:18:11.836212 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6953 22:18:11.839341 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6954 22:18:11.842735 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6955 22:18:11.846507 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6956 22:18:11.852535 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6957 22:18:11.852653 ==
6958 22:18:11.856234 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 22:18:11.859336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 22:18:11.859449 ==
6961 22:18:11.859553 DQS Delay:
6962 22:18:11.863075 DQS0 = 60, DQS1 = 64
6963 22:18:11.863159 DQM Delay:
6964 22:18:11.866090 DQM0 = 13, DQM1 = 10
6965 22:18:11.866204 DQ Delay:
6966 22:18:11.868928 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6967 22:18:11.872611 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6968 22:18:11.875845 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6969 22:18:11.879049 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6970 22:18:11.879159
6971 22:18:11.879245
6972 22:18:11.889138 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
6973 22:18:11.889228 CH1 RK1: MR19=C0C, MR18=77A7
6974 22:18:11.895798 CH1_RK1: MR19=0xC0C, MR18=0x77A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6975 22:18:11.899113 [RxdqsGatingPostProcess] freq 400
6976 22:18:11.906015 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 22:18:11.908563 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 22:18:11.912290 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 22:18:11.915650 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 22:18:11.918687 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 22:18:11.922161 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 22:18:11.922246 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 22:18:11.925334 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 22:18:11.928556 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 22:18:11.931822 Pre-setting of DQS Precalculation
6986 22:18:11.938120 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 22:18:11.944851 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 22:18:11.951910 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 22:18:11.951999
6990 22:18:11.952066
6991 22:18:11.955025 [Calibration Summary] 800 Mbps
6992 22:18:11.958047 CH 0, Rank 0
6993 22:18:11.958131 SW Impedance : PASS
6994 22:18:11.961237 DUTY Scan : NO K
6995 22:18:11.965042 ZQ Calibration : PASS
6996 22:18:11.965127 Jitter Meter : NO K
6997 22:18:11.968248 CBT Training : PASS
6998 22:18:11.968332 Write leveling : PASS
6999 22:18:11.971334 RX DQS gating : PASS
7000 22:18:11.974821 RX DQ/DQS(RDDQC) : PASS
7001 22:18:11.974940 TX DQ/DQS : PASS
7002 22:18:11.977859 RX DATLAT : PASS
7003 22:18:11.981010 RX DQ/DQS(Engine): PASS
7004 22:18:11.981093 TX OE : NO K
7005 22:18:11.984854 All Pass.
7006 22:18:11.984938
7007 22:18:11.985005 CH 0, Rank 1
7008 22:18:11.988161 SW Impedance : PASS
7009 22:18:11.988244 DUTY Scan : NO K
7010 22:18:11.991173 ZQ Calibration : PASS
7011 22:18:11.994727 Jitter Meter : NO K
7012 22:18:11.994843 CBT Training : PASS
7013 22:18:11.997922 Write leveling : NO K
7014 22:18:12.001038 RX DQS gating : PASS
7015 22:18:12.001122 RX DQ/DQS(RDDQC) : PASS
7016 22:18:12.004354 TX DQ/DQS : PASS
7017 22:18:12.007856 RX DATLAT : PASS
7018 22:18:12.007939 RX DQ/DQS(Engine): PASS
7019 22:18:12.011127 TX OE : NO K
7020 22:18:12.011210 All Pass.
7021 22:18:12.011276
7022 22:18:12.014126 CH 1, Rank 0
7023 22:18:12.014227 SW Impedance : PASS
7024 22:18:12.017444 DUTY Scan : NO K
7025 22:18:12.021047 ZQ Calibration : PASS
7026 22:18:12.021131 Jitter Meter : NO K
7027 22:18:12.024363 CBT Training : PASS
7028 22:18:12.027167 Write leveling : PASS
7029 22:18:12.027254 RX DQS gating : PASS
7030 22:18:12.030625 RX DQ/DQS(RDDQC) : PASS
7031 22:18:12.033856 TX DQ/DQS : PASS
7032 22:18:12.033965 RX DATLAT : PASS
7033 22:18:12.037115 RX DQ/DQS(Engine): PASS
7034 22:18:12.040236 TX OE : NO K
7035 22:18:12.040324 All Pass.
7036 22:18:12.040388
7037 22:18:12.040447 CH 1, Rank 1
7038 22:18:12.043785 SW Impedance : PASS
7039 22:18:12.046816 DUTY Scan : NO K
7040 22:18:12.046918 ZQ Calibration : PASS
7041 22:18:12.050066 Jitter Meter : NO K
7042 22:18:12.053849 CBT Training : PASS
7043 22:18:12.053933 Write leveling : NO K
7044 22:18:12.056996 RX DQS gating : PASS
7045 22:18:12.057079 RX DQ/DQS(RDDQC) : PASS
7046 22:18:12.060100 TX DQ/DQS : PASS
7047 22:18:12.063287 RX DATLAT : PASS
7048 22:18:12.063371 RX DQ/DQS(Engine): PASS
7049 22:18:12.066340 TX OE : NO K
7050 22:18:12.066424 All Pass.
7051 22:18:12.070065
7052 22:18:12.070148 DramC Write-DBI off
7053 22:18:12.073252 PER_BANK_REFRESH: Hybrid Mode
7054 22:18:12.073336 TX_TRACKING: ON
7055 22:18:12.083195 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 22:18:12.086510 [FAST_K] Save calibration result to emmc
7057 22:18:12.089643 dramc_set_vcore_voltage set vcore to 725000
7058 22:18:12.092771 Read voltage for 1600, 0
7059 22:18:12.092885 Vio18 = 0
7060 22:18:12.096415 Vcore = 725000
7061 22:18:12.096524 Vdram = 0
7062 22:18:12.096599 Vddq = 0
7063 22:18:12.096662 Vmddr = 0
7064 22:18:12.103247 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 22:18:12.109716 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 22:18:12.109798 MEM_TYPE=3, freq_sel=13
7067 22:18:12.112821 sv_algorithm_assistance_LP4_3733
7068 22:18:12.119472 ============ PULL DRAM RESETB DOWN ============
7069 22:18:12.122921 ========== PULL DRAM RESETB DOWN end =========
7070 22:18:12.125692 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 22:18:12.129399 ===================================
7072 22:18:12.132326 LPDDR4 DRAM CONFIGURATION
7073 22:18:12.135764 ===================================
7074 22:18:12.135869 EX_ROW_EN[0] = 0x0
7075 22:18:12.139336 EX_ROW_EN[1] = 0x0
7076 22:18:12.142574 LP4Y_EN = 0x0
7077 22:18:12.142706 WORK_FSP = 0x1
7078 22:18:12.145809 WL = 0x5
7079 22:18:12.145929 RL = 0x5
7080 22:18:12.149220 BL = 0x2
7081 22:18:12.149337 RPST = 0x0
7082 22:18:12.152587 RD_PRE = 0x0
7083 22:18:12.152670 WR_PRE = 0x1
7084 22:18:12.155481 WR_PST = 0x1
7085 22:18:12.155562 DBI_WR = 0x0
7086 22:18:12.158556 DBI_RD = 0x0
7087 22:18:12.158662 OTF = 0x1
7088 22:18:12.162452 ===================================
7089 22:18:12.165468 ===================================
7090 22:18:12.168469 ANA top config
7091 22:18:12.171647 ===================================
7092 22:18:12.175422 DLL_ASYNC_EN = 0
7093 22:18:12.175532 ALL_SLAVE_EN = 0
7094 22:18:12.178682 NEW_RANK_MODE = 1
7095 22:18:12.181819 DLL_IDLE_MODE = 1
7096 22:18:12.184993 LP45_APHY_COMB_EN = 1
7097 22:18:12.185097 TX_ODT_DIS = 0
7098 22:18:12.188744 NEW_8X_MODE = 1
7099 22:18:12.191676 ===================================
7100 22:18:12.195165 ===================================
7101 22:18:12.198259 data_rate = 3200
7102 22:18:12.201750 CKR = 1
7103 22:18:12.205185 DQ_P2S_RATIO = 8
7104 22:18:12.208195 ===================================
7105 22:18:12.211439 CA_P2S_RATIO = 8
7106 22:18:12.214551 DQ_CA_OPEN = 0
7107 22:18:12.214655 DQ_SEMI_OPEN = 0
7108 22:18:12.218341 CA_SEMI_OPEN = 0
7109 22:18:12.221664 CA_FULL_RATE = 0
7110 22:18:12.224740 DQ_CKDIV4_EN = 0
7111 22:18:12.228179 CA_CKDIV4_EN = 0
7112 22:18:12.230979 CA_PREDIV_EN = 0
7113 22:18:12.231092 PH8_DLY = 12
7114 22:18:12.234407 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 22:18:12.237948 DQ_AAMCK_DIV = 4
7116 22:18:12.240813 CA_AAMCK_DIV = 4
7117 22:18:12.244364 CA_ADMCK_DIV = 4
7118 22:18:12.248127 DQ_TRACK_CA_EN = 0
7119 22:18:12.248235 CA_PICK = 1600
7120 22:18:12.250952 CA_MCKIO = 1600
7121 22:18:12.254585 MCKIO_SEMI = 0
7122 22:18:12.257772 PLL_FREQ = 3068
7123 22:18:12.260979 DQ_UI_PI_RATIO = 32
7124 22:18:12.264123 CA_UI_PI_RATIO = 0
7125 22:18:12.267334 ===================================
7126 22:18:12.271013 ===================================
7127 22:18:12.274164 memory_type:LPDDR4
7128 22:18:12.274268 GP_NUM : 10
7129 22:18:12.277584 SRAM_EN : 1
7130 22:18:12.277668 MD32_EN : 0
7131 22:18:12.280712 ===================================
7132 22:18:12.284019 [ANA_INIT] >>>>>>>>>>>>>>
7133 22:18:12.287259 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 22:18:12.290446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 22:18:12.293574 ===================================
7136 22:18:12.297271 data_rate = 3200,PCW = 0X7600
7137 22:18:12.300343 ===================================
7138 22:18:12.303989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 22:18:12.310243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 22:18:12.313263 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 22:18:12.320252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 22:18:12.323398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 22:18:12.326645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 22:18:12.326726 [ANA_INIT] flow start
7145 22:18:12.329772 [ANA_INIT] PLL >>>>>>>>
7146 22:18:12.332913 [ANA_INIT] PLL <<<<<<<<
7147 22:18:12.337049 [ANA_INIT] MIDPI >>>>>>>>
7148 22:18:12.337156 [ANA_INIT] MIDPI <<<<<<<<
7149 22:18:12.339781 [ANA_INIT] DLL >>>>>>>>
7150 22:18:12.343202 [ANA_INIT] DLL <<<<<<<<
7151 22:18:12.343315 [ANA_INIT] flow end
7152 22:18:12.346124 ============ LP4 DIFF to SE enter ============
7153 22:18:12.353158 ============ LP4 DIFF to SE exit ============
7154 22:18:12.353251 [ANA_INIT] <<<<<<<<<<<<<
7155 22:18:12.356109 [Flow] Enable top DCM control >>>>>
7156 22:18:12.359446 [Flow] Enable top DCM control <<<<<
7157 22:18:12.362913 Enable DLL master slave shuffle
7158 22:18:12.369197 ==============================================================
7159 22:18:12.372388 Gating Mode config
7160 22:18:12.376190 ==============================================================
7161 22:18:12.379278 Config description:
7162 22:18:12.389437 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 22:18:12.395777 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 22:18:12.398798 SELPH_MODE 0: By rank 1: By Phase
7165 22:18:12.405728 ==============================================================
7166 22:18:12.408739 GAT_TRACK_EN = 1
7167 22:18:12.412487 RX_GATING_MODE = 2
7168 22:18:12.415525 RX_GATING_TRACK_MODE = 2
7169 22:18:12.419157 SELPH_MODE = 1
7170 22:18:12.419243 PICG_EARLY_EN = 1
7171 22:18:12.422147 VALID_LAT_VALUE = 1
7172 22:18:12.428504 ==============================================================
7173 22:18:12.432320 Enter into Gating configuration >>>>
7174 22:18:12.435415 Exit from Gating configuration <<<<
7175 22:18:12.438584 Enter into DVFS_PRE_config >>>>>
7176 22:18:12.448483 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 22:18:12.451708 Exit from DVFS_PRE_config <<<<<
7178 22:18:12.455354 Enter into PICG configuration >>>>
7179 22:18:12.458129 Exit from PICG configuration <<<<
7180 22:18:12.461559 [RX_INPUT] configuration >>>>>
7181 22:18:12.465126 [RX_INPUT] configuration <<<<<
7182 22:18:12.471568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 22:18:12.474686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 22:18:12.481504 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 22:18:12.487957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 22:18:12.494956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 22:18:12.501379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 22:18:12.505055 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 22:18:12.508107 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 22:18:12.511455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 22:18:12.518212 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 22:18:12.521498 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 22:18:12.524598 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 22:18:12.527816 ===================================
7195 22:18:12.531153 LPDDR4 DRAM CONFIGURATION
7196 22:18:12.534234 ===================================
7197 22:18:12.534316 EX_ROW_EN[0] = 0x0
7198 22:18:12.537525 EX_ROW_EN[1] = 0x0
7199 22:18:12.541221 LP4Y_EN = 0x0
7200 22:18:12.541302 WORK_FSP = 0x1
7201 22:18:12.544394 WL = 0x5
7202 22:18:12.544500 RL = 0x5
7203 22:18:12.547562 BL = 0x2
7204 22:18:12.547644 RPST = 0x0
7205 22:18:12.550586 RD_PRE = 0x0
7206 22:18:12.550672 WR_PRE = 0x1
7207 22:18:12.554385 WR_PST = 0x1
7208 22:18:12.554467 DBI_WR = 0x0
7209 22:18:12.557757 DBI_RD = 0x0
7210 22:18:12.557838 OTF = 0x1
7211 22:18:12.560737 ===================================
7212 22:18:12.563909 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 22:18:12.570784 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 22:18:12.573691 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 22:18:12.577163 ===================================
7216 22:18:12.580717 LPDDR4 DRAM CONFIGURATION
7217 22:18:12.583798 ===================================
7218 22:18:12.583878 EX_ROW_EN[0] = 0x10
7219 22:18:12.586923 EX_ROW_EN[1] = 0x0
7220 22:18:12.590180 LP4Y_EN = 0x0
7221 22:18:12.590254 WORK_FSP = 0x1
7222 22:18:12.593983 WL = 0x5
7223 22:18:12.594057 RL = 0x5
7224 22:18:12.597240 BL = 0x2
7225 22:18:12.597311 RPST = 0x0
7226 22:18:12.600330 RD_PRE = 0x0
7227 22:18:12.600432 WR_PRE = 0x1
7228 22:18:12.603633 WR_PST = 0x1
7229 22:18:12.603712 DBI_WR = 0x0
7230 22:18:12.606672 DBI_RD = 0x0
7231 22:18:12.606787 OTF = 0x1
7232 22:18:12.610318 ===================================
7233 22:18:12.616614 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 22:18:12.616695 ==
7235 22:18:12.619665 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 22:18:12.626612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 22:18:12.626694 ==
7238 22:18:12.626762 [Duty_Offset_Calibration]
7239 22:18:12.629736 B0:2 B1:0 CA:3
7240 22:18:12.629809
7241 22:18:12.633316 [DutyScan_Calibration_Flow] k_type=0
7242 22:18:12.642535
7243 22:18:12.642613 ==CLK 0==
7244 22:18:12.645745 Final CLK duty delay cell = 0
7245 22:18:12.648848 [0] MAX Duty = 5031%(X100), DQS PI = 12
7246 22:18:12.652163 [0] MIN Duty = 4907%(X100), DQS PI = 2
7247 22:18:12.655540 [0] AVG Duty = 4969%(X100)
7248 22:18:12.655634
7249 22:18:12.658665 CH0 CLK Duty spec in!! Max-Min= 124%
7250 22:18:12.662152 [DutyScan_Calibration_Flow] ====Done====
7251 22:18:12.662284
7252 22:18:12.665269 [DutyScan_Calibration_Flow] k_type=1
7253 22:18:12.681986
7254 22:18:12.682074 ==DQS 0 ==
7255 22:18:12.685532 Final DQS duty delay cell = 0
7256 22:18:12.688546 [0] MAX Duty = 5094%(X100), DQS PI = 12
7257 22:18:12.692135 [0] MIN Duty = 4906%(X100), DQS PI = 46
7258 22:18:12.695289 [0] AVG Duty = 5000%(X100)
7259 22:18:12.695391
7260 22:18:12.695482 ==DQS 1 ==
7261 22:18:12.698498 Final DQS duty delay cell = 0
7262 22:18:12.701608 [0] MAX Duty = 5156%(X100), DQS PI = 32
7263 22:18:12.705484 [0] MIN Duty = 5062%(X100), DQS PI = 0
7264 22:18:12.708729 [0] AVG Duty = 5109%(X100)
7265 22:18:12.708829
7266 22:18:12.711745 CH0 DQS 0 Duty spec in!! Max-Min= 188%
7267 22:18:12.711836
7268 22:18:12.714984 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7269 22:18:12.718102 [DutyScan_Calibration_Flow] ====Done====
7270 22:18:12.718233
7271 22:18:12.721464 [DutyScan_Calibration_Flow] k_type=3
7272 22:18:12.740014
7273 22:18:12.740100 ==DQM 0 ==
7274 22:18:12.743104 Final DQM duty delay cell = 0
7275 22:18:12.746768 [0] MAX Duty = 5156%(X100), DQS PI = 30
7276 22:18:12.750123 [0] MIN Duty = 4875%(X100), DQS PI = 0
7277 22:18:12.753465 [0] AVG Duty = 5015%(X100)
7278 22:18:12.753561
7279 22:18:12.753654 ==DQM 1 ==
7280 22:18:12.756699 Final DQM duty delay cell = 4
7281 22:18:12.759600 [4] MAX Duty = 5187%(X100), DQS PI = 62
7282 22:18:12.762806 [4] MIN Duty = 5031%(X100), DQS PI = 12
7283 22:18:12.766583 [4] AVG Duty = 5109%(X100)
7284 22:18:12.766665
7285 22:18:12.769672 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7286 22:18:12.769756
7287 22:18:12.772922 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7288 22:18:12.775991 [DutyScan_Calibration_Flow] ====Done====
7289 22:18:12.776075
7290 22:18:12.779672 [DutyScan_Calibration_Flow] k_type=2
7291 22:18:12.796631
7292 22:18:12.796722 ==DQ 0 ==
7293 22:18:12.799740 Final DQ duty delay cell = -4
7294 22:18:12.803206 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7295 22:18:12.806573 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7296 22:18:12.809623 [-4] AVG Duty = 4938%(X100)
7297 22:18:12.809695
7298 22:18:12.809755 ==DQ 1 ==
7299 22:18:12.812862 Final DQ duty delay cell = 0
7300 22:18:12.816465 [0] MAX Duty = 5156%(X100), DQS PI = 60
7301 22:18:12.819592 [0] MIN Duty = 5000%(X100), DQS PI = 16
7302 22:18:12.822811 [0] AVG Duty = 5078%(X100)
7303 22:18:12.822929
7304 22:18:12.826076 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7305 22:18:12.826158
7306 22:18:12.829292 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7307 22:18:12.832885 [DutyScan_Calibration_Flow] ====Done====
7308 22:18:12.832997 ==
7309 22:18:12.835789 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 22:18:12.839598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 22:18:12.839707 ==
7312 22:18:12.842909 [Duty_Offset_Calibration]
7313 22:18:12.842991 B0:1 B1:-2 CA:0
7314 22:18:12.843055
7315 22:18:12.846013 [DutyScan_Calibration_Flow] k_type=0
7316 22:18:12.857258
7317 22:18:12.857346 ==CLK 0==
7318 22:18:12.860328 Final CLK duty delay cell = 0
7319 22:18:12.863373 [0] MAX Duty = 5062%(X100), DQS PI = 20
7320 22:18:12.867236 [0] MIN Duty = 4844%(X100), DQS PI = 0
7321 22:18:12.867319 [0] AVG Duty = 4953%(X100)
7322 22:18:12.870399
7323 22:18:12.873631 CH1 CLK Duty spec in!! Max-Min= 218%
7324 22:18:12.876828 [DutyScan_Calibration_Flow] ====Done====
7325 22:18:12.876906
7326 22:18:12.879842 [DutyScan_Calibration_Flow] k_type=1
7327 22:18:12.896865
7328 22:18:12.896949 ==DQS 0 ==
7329 22:18:12.899869 Final DQS duty delay cell = 0
7330 22:18:12.903537 [0] MAX Duty = 5187%(X100), DQS PI = 24
7331 22:18:12.906512 [0] MIN Duty = 5031%(X100), DQS PI = 54
7332 22:18:12.909621 [0] AVG Duty = 5109%(X100)
7333 22:18:12.909704
7334 22:18:12.909769 ==DQS 1 ==
7335 22:18:12.912810 Final DQS duty delay cell = 0
7336 22:18:12.916140 [0] MAX Duty = 5093%(X100), DQS PI = 60
7337 22:18:12.919928 [0] MIN Duty = 4844%(X100), DQS PI = 24
7338 22:18:12.922783 [0] AVG Duty = 4968%(X100)
7339 22:18:12.922885
7340 22:18:12.926176 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7341 22:18:12.926258
7342 22:18:12.930072 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7343 22:18:12.933269 [DutyScan_Calibration_Flow] ====Done====
7344 22:18:12.933372
7345 22:18:12.936341 [DutyScan_Calibration_Flow] k_type=3
7346 22:18:12.953645
7347 22:18:12.953736 ==DQM 0 ==
7348 22:18:12.957264 Final DQM duty delay cell = 0
7349 22:18:12.960486 [0] MAX Duty = 5031%(X100), DQS PI = 24
7350 22:18:12.963571 [0] MIN Duty = 4813%(X100), DQS PI = 54
7351 22:18:12.966678 [0] AVG Duty = 4922%(X100)
7352 22:18:12.966779
7353 22:18:12.966870 ==DQM 1 ==
7354 22:18:12.970254 Final DQM duty delay cell = 0
7355 22:18:12.973406 [0] MAX Duty = 5062%(X100), DQS PI = 34
7356 22:18:12.977192 [0] MIN Duty = 4875%(X100), DQS PI = 24
7357 22:18:12.980176 [0] AVG Duty = 4968%(X100)
7358 22:18:12.980275
7359 22:18:12.983262 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7360 22:18:12.983341
7361 22:18:12.986986 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7362 22:18:12.990174 [DutyScan_Calibration_Flow] ====Done====
7363 22:18:12.990252
7364 22:18:12.993313 [DutyScan_Calibration_Flow] k_type=2
7365 22:18:13.010947
7366 22:18:13.011038 ==DQ 0 ==
7367 22:18:13.014134 Final DQ duty delay cell = 0
7368 22:18:13.016957 [0] MAX Duty = 5093%(X100), DQS PI = 22
7369 22:18:13.020934 [0] MIN Duty = 4907%(X100), DQS PI = 62
7370 22:18:13.023892 [0] AVG Duty = 5000%(X100)
7371 22:18:13.024002
7372 22:18:13.024095 ==DQ 1 ==
7373 22:18:13.026824 Final DQ duty delay cell = 0
7374 22:18:13.030712 [0] MAX Duty = 5125%(X100), DQS PI = 34
7375 22:18:13.033997 [0] MIN Duty = 4969%(X100), DQS PI = 24
7376 22:18:13.034102 [0] AVG Duty = 5047%(X100)
7377 22:18:13.037193
7378 22:18:13.040333 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7379 22:18:13.040408
7380 22:18:13.043505 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7381 22:18:13.047125 [DutyScan_Calibration_Flow] ====Done====
7382 22:18:13.050132 nWR fixed to 30
7383 22:18:13.050237 [ModeRegInit_LP4] CH0 RK0
7384 22:18:13.053843 [ModeRegInit_LP4] CH0 RK1
7385 22:18:13.056584 [ModeRegInit_LP4] CH1 RK0
7386 22:18:13.060297 [ModeRegInit_LP4] CH1 RK1
7387 22:18:13.060398 match AC timing 5
7388 22:18:13.066863 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 22:18:13.070012 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 22:18:13.073676 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 22:18:13.079715 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 22:18:13.082861 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 22:18:13.082935 [MiockJmeterHQA]
7394 22:18:13.082998
7395 22:18:13.086164 [DramcMiockJmeter] u1RxGatingPI = 0
7396 22:18:13.089817 0 : 4255, 4027
7397 22:18:13.089918 4 : 4253, 4026
7398 22:18:13.093071 8 : 4252, 4027
7399 22:18:13.093175 12 : 4255, 4029
7400 22:18:13.096383 16 : 4252, 4027
7401 22:18:13.096485 20 : 4252, 4027
7402 22:18:13.096577 24 : 4253, 4027
7403 22:18:13.099389 28 : 4253, 4026
7404 22:18:13.099488 32 : 4255, 4030
7405 22:18:13.103273 36 : 4363, 4137
7406 22:18:13.103346 40 : 4253, 4027
7407 22:18:13.106263 44 : 4252, 4027
7408 22:18:13.106341 48 : 4252, 4027
7409 22:18:13.109342 52 : 4255, 4029
7410 22:18:13.109442 56 : 4252, 4027
7411 22:18:13.109534 60 : 4363, 4138
7412 22:18:13.113160 64 : 4363, 4137
7413 22:18:13.113263 68 : 4250, 4026
7414 22:18:13.115925 72 : 4252, 4027
7415 22:18:13.116001 76 : 4252, 4027
7416 22:18:13.119599 80 : 4250, 4026
7417 22:18:13.119701 84 : 4252, 4029
7418 22:18:13.122390 88 : 4361, 4137
7419 22:18:13.122489 92 : 4250, 4027
7420 22:18:13.122583 96 : 4250, 4026
7421 22:18:13.125865 100 : 4250, 4026
7422 22:18:13.125967 104 : 4250, 3593
7423 22:18:13.129315 108 : 4252, 0
7424 22:18:13.129394 112 : 4361, 0
7425 22:18:13.132430 116 : 4361, 0
7426 22:18:13.132503 120 : 4360, 0
7427 22:18:13.132565 124 : 4360, 0
7428 22:18:13.136107 128 : 4361, 0
7429 22:18:13.136183 132 : 4363, 0
7430 22:18:13.139323 136 : 4250, 0
7431 22:18:13.139395 140 : 4250, 0
7432 22:18:13.139462 144 : 4250, 0
7433 22:18:13.142453 148 : 4252, 0
7434 22:18:13.142523 152 : 4250, 0
7435 22:18:13.145590 156 : 4250, 0
7436 22:18:13.145690 160 : 4252, 0
7437 22:18:13.145781 164 : 4252, 0
7438 22:18:13.148807 168 : 4250, 0
7439 22:18:13.148911 172 : 4363, 0
7440 22:18:13.149007 176 : 4250, 0
7441 22:18:13.152473 180 : 4361, 0
7442 22:18:13.152546 184 : 4249, 0
7443 22:18:13.155516 188 : 4250, 0
7444 22:18:13.155620 192 : 4250, 0
7445 22:18:13.155713 196 : 4250, 0
7446 22:18:13.158600 200 : 4250, 0
7447 22:18:13.158717 204 : 4250, 0
7448 22:18:13.161807 208 : 4250, 0
7449 22:18:13.161913 212 : 4252, 0
7450 22:18:13.162011 216 : 4250, 0
7451 22:18:13.165276 220 : 4250, 0
7452 22:18:13.165380 224 : 4253, 0
7453 22:18:13.168893 228 : 4360, 0
7454 22:18:13.169003 232 : 4361, 0
7455 22:18:13.169098 236 : 4361, 1062
7456 22:18:13.171874 240 : 4360, 4137
7457 22:18:13.171948 244 : 4250, 4027
7458 22:18:13.175425 248 : 4250, 4027
7459 22:18:13.175532 252 : 4360, 4138
7460 22:18:13.178512 256 : 4249, 4027
7461 22:18:13.178620 260 : 4250, 4026
7462 22:18:13.181688 264 : 4250, 4027
7463 22:18:13.181794 268 : 4252, 4030
7464 22:18:13.185355 272 : 4249, 4027
7465 22:18:13.185468 276 : 4250, 4026
7466 22:18:13.188688 280 : 4363, 4140
7467 22:18:13.188795 284 : 4250, 4027
7468 22:18:13.191873 288 : 4249, 4027
7469 22:18:13.191949 292 : 4361, 4137
7470 22:18:13.195109 296 : 4250, 4026
7471 22:18:13.195211 300 : 4250, 4027
7472 22:18:13.195278 304 : 4363, 4140
7473 22:18:13.198195 308 : 4250, 4027
7474 22:18:13.198281 312 : 4250, 4026
7475 22:18:13.201419 316 : 4250, 4027
7476 22:18:13.201525 320 : 4252, 4030
7477 22:18:13.204601 324 : 4249, 4027
7478 22:18:13.204710 328 : 4252, 4029
7479 22:18:13.208286 332 : 4361, 4138
7480 22:18:13.208392 336 : 4250, 4027
7481 22:18:13.211584 340 : 4249, 4027
7482 22:18:13.211660 344 : 4361, 4137
7483 22:18:13.214712 348 : 4250, 4026
7484 22:18:13.214818 352 : 4250, 4008
7485 22:18:13.217897 356 : 4360, 2875
7486 22:18:13.217992 360 : 4249, 0
7487 22:18:13.218094
7488 22:18:13.221557 MIOCK jitter meter ch=0
7489 22:18:13.221641
7490 22:18:13.224577 1T = (360-108) = 252 dly cells
7491 22:18:13.228187 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7492 22:18:13.228271 ==
7493 22:18:13.231315 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 22:18:13.237713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 22:18:13.237829 ==
7496 22:18:13.240938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 22:18:13.247866 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 22:18:13.251156 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 22:18:13.257498 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 22:18:13.265492 [CA 0] Center 44 (14~75) winsize 62
7501 22:18:13.268619 [CA 1] Center 43 (13~74) winsize 62
7502 22:18:13.271937 [CA 2] Center 40 (11~69) winsize 59
7503 22:18:13.275929 [CA 3] Center 39 (10~69) winsize 60
7504 22:18:13.278731 [CA 4] Center 37 (8~67) winsize 60
7505 22:18:13.281709 [CA 5] Center 37 (7~67) winsize 61
7506 22:18:13.281792
7507 22:18:13.285300 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 22:18:13.285383
7509 22:18:13.292158 [CATrainingPosCal] consider 1 rank data
7510 22:18:13.292245 u2DelayCellTimex100 = 258/100 ps
7511 22:18:13.298315 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7512 22:18:13.301489 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7513 22:18:13.305388 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7514 22:18:13.308435 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7515 22:18:13.311448 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7516 22:18:13.315238 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 22:18:13.315321
7518 22:18:13.318595 CA PerBit enable=1, Macro0, CA PI delay=37
7519 22:18:13.318675
7520 22:18:13.321562 [CBTSetCACLKResult] CA Dly = 37
7521 22:18:13.324689 CS Dly: 11 (0~42)
7522 22:18:13.328376 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 22:18:13.331737 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 22:18:13.331820 ==
7525 22:18:13.334846 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 22:18:13.341729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 22:18:13.341811 ==
7528 22:18:13.344622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 22:18:13.351130 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 22:18:13.354326 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 22:18:13.361177 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 22:18:13.369146 [CA 0] Center 43 (13~74) winsize 62
7533 22:18:13.373077 [CA 1] Center 43 (13~74) winsize 62
7534 22:18:13.376260 [CA 2] Center 39 (10~68) winsize 59
7535 22:18:13.379438 [CA 3] Center 39 (10~68) winsize 59
7536 22:18:13.382713 [CA 4] Center 36 (6~66) winsize 61
7537 22:18:13.385784 [CA 5] Center 36 (6~66) winsize 61
7538 22:18:13.385867
7539 22:18:13.389361 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 22:18:13.389448
7541 22:18:13.395771 [CATrainingPosCal] consider 2 rank data
7542 22:18:13.395884 u2DelayCellTimex100 = 258/100 ps
7543 22:18:13.402260 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7544 22:18:13.405662 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7545 22:18:13.408903 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7546 22:18:13.412224 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7547 22:18:13.415491 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7548 22:18:13.418717 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7549 22:18:13.418842
7550 22:18:13.421963 CA PerBit enable=1, Macro0, CA PI delay=36
7551 22:18:13.422081
7552 22:18:13.425274 [CBTSetCACLKResult] CA Dly = 36
7553 22:18:13.429117 CS Dly: 11 (0~43)
7554 22:18:13.431808 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 22:18:13.435577 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 22:18:13.435686
7557 22:18:13.438657 ----->DramcWriteLeveling(PI) begin...
7558 22:18:13.441902 ==
7559 22:18:13.445536 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 22:18:13.448510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 22:18:13.448594 ==
7562 22:18:13.451613 Write leveling (Byte 0): 35 => 35
7563 22:18:13.455071 Write leveling (Byte 1): 29 => 29
7564 22:18:13.458195 DramcWriteLeveling(PI) end<-----
7565 22:18:13.458274
7566 22:18:13.458339 ==
7567 22:18:13.462090 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 22:18:13.464800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 22:18:13.464878 ==
7570 22:18:13.468171 [Gating] SW mode calibration
7571 22:18:13.474981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 22:18:13.481382 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 22:18:13.484656 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 22:18:13.487935 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 22:18:13.494410 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 22:18:13.498042 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 22:18:13.501051 1 4 16 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7578 22:18:13.507876 1 4 20 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7579 22:18:13.511242 1 4 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7580 22:18:13.514593 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 22:18:13.521009 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 22:18:13.524214 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 22:18:13.527535 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 22:18:13.534149 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 22:18:13.537257 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7586 22:18:13.540569 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7587 22:18:13.547779 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7588 22:18:13.550716 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 22:18:13.553849 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 22:18:13.560313 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 22:18:13.563540 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 22:18:13.567202 1 6 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7593 22:18:13.573611 1 6 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7594 22:18:13.576906 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7595 22:18:13.580064 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7596 22:18:13.587010 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 22:18:13.590239 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 22:18:13.593528 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 22:18:13.600064 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 22:18:13.603098 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 22:18:13.606636 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 22:18:13.613416 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7603 22:18:13.616660 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 22:18:13.619906 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 22:18:13.626455 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 22:18:13.629791 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 22:18:13.633024 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 22:18:13.639611 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 22:18:13.642767 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 22:18:13.645955 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 22:18:13.653029 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 22:18:13.656331 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 22:18:13.659039 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 22:18:13.665692 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 22:18:13.669469 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 22:18:13.672499 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 22:18:13.679521 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 22:18:13.682183 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7619 22:18:13.685419 Total UI for P1: 0, mck2ui 16
7620 22:18:13.689219 best dqsien dly found for B0: ( 1, 9, 14)
7621 22:18:13.692234 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 22:18:13.698899 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 22:18:13.699009 Total UI for P1: 0, mck2ui 16
7624 22:18:13.705512 best dqsien dly found for B1: ( 1, 9, 24)
7625 22:18:13.708607 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7626 22:18:13.712013 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7627 22:18:13.712127
7628 22:18:13.715693 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7629 22:18:13.718817 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7630 22:18:13.721897 [Gating] SW calibration Done
7631 22:18:13.722009 ==
7632 22:18:13.725389 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 22:18:13.728386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 22:18:13.728469 ==
7635 22:18:13.732178 RX Vref Scan: 0
7636 22:18:13.732266
7637 22:18:13.732344 RX Vref 0 -> 0, step: 1
7638 22:18:13.735471
7639 22:18:13.735548 RX Delay 0 -> 252, step: 8
7640 22:18:13.741449 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7641 22:18:13.744838 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7642 22:18:13.748233 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7643 22:18:13.751691 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7644 22:18:13.755001 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7645 22:18:13.761346 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7646 22:18:13.765005 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7647 22:18:13.768050 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7648 22:18:13.771079 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7649 22:18:13.774696 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7650 22:18:13.780954 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7651 22:18:13.784243 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7652 22:18:13.787608 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7653 22:18:13.790889 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7654 22:18:13.797740 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7655 22:18:13.801055 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7656 22:18:13.801142 ==
7657 22:18:13.804308 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 22:18:13.807582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 22:18:13.807690 ==
7660 22:18:13.810679 DQS Delay:
7661 22:18:13.810781 DQS0 = 0, DQS1 = 0
7662 22:18:13.810890 DQM Delay:
7663 22:18:13.814037 DQM0 = 127, DQM1 = 123
7664 22:18:13.814120 DQ Delay:
7665 22:18:13.817274 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7666 22:18:13.820593 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7667 22:18:13.827184 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7668 22:18:13.830087 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7669 22:18:13.830171
7670 22:18:13.830236
7671 22:18:13.830297 ==
7672 22:18:13.833634 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 22:18:13.836858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 22:18:13.836946 ==
7675 22:18:13.837033
7676 22:18:13.837113
7677 22:18:13.840107 TX Vref Scan disable
7678 22:18:13.843347 == TX Byte 0 ==
7679 22:18:13.846611 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7680 22:18:13.849951 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7681 22:18:13.853037 == TX Byte 1 ==
7682 22:18:13.856732 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7683 22:18:13.860007 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7684 22:18:13.860116 ==
7685 22:18:13.863211 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 22:18:13.869623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 22:18:13.869710 ==
7688 22:18:13.881751
7689 22:18:13.884931 TX Vref early break, caculate TX vref
7690 22:18:13.887976 TX Vref=16, minBit 8, minWin=21, winSum=360
7691 22:18:13.891346 TX Vref=18, minBit 11, minWin=22, winSum=369
7692 22:18:13.894485 TX Vref=20, minBit 0, minWin=23, winSum=379
7693 22:18:13.897770 TX Vref=22, minBit 0, minWin=24, winSum=387
7694 22:18:13.901458 TX Vref=24, minBit 4, minWin=24, winSum=402
7695 22:18:13.907643 TX Vref=26, minBit 4, minWin=24, winSum=408
7696 22:18:13.910991 TX Vref=28, minBit 1, minWin=25, winSum=411
7697 22:18:13.914173 TX Vref=30, minBit 8, minWin=24, winSum=400
7698 22:18:13.917608 TX Vref=32, minBit 4, minWin=24, winSum=394
7699 22:18:13.921021 TX Vref=34, minBit 8, minWin=23, winSum=387
7700 22:18:13.927901 [TxChooseVref] Worse bit 1, Min win 25, Win sum 411, Final Vref 28
7701 22:18:13.928017
7702 22:18:13.930815 Final TX Range 0 Vref 28
7703 22:18:13.930924
7704 22:18:13.931016 ==
7705 22:18:13.933953 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 22:18:13.937819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 22:18:13.937934 ==
7708 22:18:13.938030
7709 22:18:13.938121
7710 22:18:13.940853 TX Vref Scan disable
7711 22:18:13.947539 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7712 22:18:13.947669 == TX Byte 0 ==
7713 22:18:13.950776 u2DelayCellOfst[0]=15 cells (4 PI)
7714 22:18:13.954080 u2DelayCellOfst[1]=18 cells (5 PI)
7715 22:18:13.957274 u2DelayCellOfst[2]=15 cells (4 PI)
7716 22:18:13.960434 u2DelayCellOfst[3]=15 cells (4 PI)
7717 22:18:13.963756 u2DelayCellOfst[4]=11 cells (3 PI)
7718 22:18:13.967126 u2DelayCellOfst[5]=0 cells (0 PI)
7719 22:18:13.970285 u2DelayCellOfst[6]=22 cells (6 PI)
7720 22:18:13.973591 u2DelayCellOfst[7]=18 cells (5 PI)
7721 22:18:13.977234 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7722 22:18:13.980376 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7723 22:18:13.983437 == TX Byte 1 ==
7724 22:18:13.986592 u2DelayCellOfst[8]=0 cells (0 PI)
7725 22:18:13.989763 u2DelayCellOfst[9]=0 cells (0 PI)
7726 22:18:13.993485 u2DelayCellOfst[10]=3 cells (1 PI)
7727 22:18:13.996711 u2DelayCellOfst[11]=0 cells (0 PI)
7728 22:18:14.000069 u2DelayCellOfst[12]=7 cells (2 PI)
7729 22:18:14.003325 u2DelayCellOfst[13]=7 cells (2 PI)
7730 22:18:14.006479 u2DelayCellOfst[14]=11 cells (3 PI)
7731 22:18:14.006588 u2DelayCellOfst[15]=7 cells (2 PI)
7732 22:18:14.012834 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7733 22:18:14.016193 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7734 22:18:14.019435 DramC Write-DBI on
7735 22:18:14.019541 ==
7736 22:18:14.022581 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 22:18:14.025846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 22:18:14.025967 ==
7739 22:18:14.026068
7740 22:18:14.026170
7741 22:18:14.029213 TX Vref Scan disable
7742 22:18:14.029329 == TX Byte 0 ==
7743 22:18:14.036233 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7744 22:18:14.036349 == TX Byte 1 ==
7745 22:18:14.039663 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7746 22:18:14.042839 DramC Write-DBI off
7747 22:18:14.042935
7748 22:18:14.043030 [DATLAT]
7749 22:18:14.046256 Freq=1600, CH0 RK0
7750 22:18:14.046341
7751 22:18:14.046407 DATLAT Default: 0xf
7752 22:18:14.048963 0, 0xFFFF, sum = 0
7753 22:18:14.052542 1, 0xFFFF, sum = 0
7754 22:18:14.052629 2, 0xFFFF, sum = 0
7755 22:18:14.055877 3, 0xFFFF, sum = 0
7756 22:18:14.055964 4, 0xFFFF, sum = 0
7757 22:18:14.059108 5, 0xFFFF, sum = 0
7758 22:18:14.059195 6, 0xFFFF, sum = 0
7759 22:18:14.062212 7, 0xFFFF, sum = 0
7760 22:18:14.062327 8, 0xFFFF, sum = 0
7761 22:18:14.065494 9, 0xFFFF, sum = 0
7762 22:18:14.065609 10, 0xFFFF, sum = 0
7763 22:18:14.068784 11, 0xFFFF, sum = 0
7764 22:18:14.068892 12, 0xFFFF, sum = 0
7765 22:18:14.072035 13, 0xCFFF, sum = 0
7766 22:18:14.072148 14, 0x0, sum = 1
7767 22:18:14.075277 15, 0x0, sum = 2
7768 22:18:14.075390 16, 0x0, sum = 3
7769 22:18:14.078703 17, 0x0, sum = 4
7770 22:18:14.078805 best_step = 15
7771 22:18:14.078902
7772 22:18:14.078993 ==
7773 22:18:14.081907 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 22:18:14.088701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 22:18:14.088793 ==
7776 22:18:14.088887 RX Vref Scan: 1
7777 22:18:14.088977
7778 22:18:14.091632 Set Vref Range= 24 -> 127
7779 22:18:14.091722
7780 22:18:14.095517 RX Vref 24 -> 127, step: 1
7781 22:18:14.095634
7782 22:18:14.098462 RX Delay 11 -> 252, step: 4
7783 22:18:14.098571
7784 22:18:14.098671 Set Vref, RX VrefLevel [Byte0]: 24
7785 22:18:14.102103 [Byte1]: 24
7786 22:18:14.106036
7787 22:18:14.106154 Set Vref, RX VrefLevel [Byte0]: 25
7788 22:18:14.109317 [Byte1]: 25
7789 22:18:14.113955
7790 22:18:14.114060 Set Vref, RX VrefLevel [Byte0]: 26
7791 22:18:14.117009 [Byte1]: 26
7792 22:18:14.121495
7793 22:18:14.121626 Set Vref, RX VrefLevel [Byte0]: 27
7794 22:18:14.124616 [Byte1]: 27
7795 22:18:14.129188
7796 22:18:14.129313 Set Vref, RX VrefLevel [Byte0]: 28
7797 22:18:14.132515 [Byte1]: 28
7798 22:18:14.136481
7799 22:18:14.136599 Set Vref, RX VrefLevel [Byte0]: 29
7800 22:18:14.139615 [Byte1]: 29
7801 22:18:14.144228
7802 22:18:14.144311 Set Vref, RX VrefLevel [Byte0]: 30
7803 22:18:14.150785 [Byte1]: 30
7804 22:18:14.150880
7805 22:18:14.153964 Set Vref, RX VrefLevel [Byte0]: 31
7806 22:18:14.157625 [Byte1]: 31
7807 22:18:14.157734
7808 22:18:14.160555 Set Vref, RX VrefLevel [Byte0]: 32
7809 22:18:14.163760 [Byte1]: 32
7810 22:18:14.166947
7811 22:18:14.167022 Set Vref, RX VrefLevel [Byte0]: 33
7812 22:18:14.170534 [Byte1]: 33
7813 22:18:14.174554
7814 22:18:14.174658 Set Vref, RX VrefLevel [Byte0]: 34
7815 22:18:14.177833 [Byte1]: 34
7816 22:18:14.182460
7817 22:18:14.182573 Set Vref, RX VrefLevel [Byte0]: 35
7818 22:18:14.185614 [Byte1]: 35
7819 22:18:14.189958
7820 22:18:14.190042 Set Vref, RX VrefLevel [Byte0]: 36
7821 22:18:14.192937 [Byte1]: 36
7822 22:18:14.197849
7823 22:18:14.197933 Set Vref, RX VrefLevel [Byte0]: 37
7824 22:18:14.200995 [Byte1]: 37
7825 22:18:14.205159
7826 22:18:14.205247 Set Vref, RX VrefLevel [Byte0]: 38
7827 22:18:14.208114 [Byte1]: 38
7828 22:18:14.212715
7829 22:18:14.212808 Set Vref, RX VrefLevel [Byte0]: 39
7830 22:18:14.216025 [Byte1]: 39
7831 22:18:14.220524
7832 22:18:14.220611 Set Vref, RX VrefLevel [Byte0]: 40
7833 22:18:14.223539 [Byte1]: 40
7834 22:18:14.228030
7835 22:18:14.228113 Set Vref, RX VrefLevel [Byte0]: 41
7836 22:18:14.231175 [Byte1]: 41
7837 22:18:14.235880
7838 22:18:14.235990 Set Vref, RX VrefLevel [Byte0]: 42
7839 22:18:14.238759 [Byte1]: 42
7840 22:18:14.242926
7841 22:18:14.243030 Set Vref, RX VrefLevel [Byte0]: 43
7842 22:18:14.246227 [Byte1]: 43
7843 22:18:14.250724
7844 22:18:14.250858 Set Vref, RX VrefLevel [Byte0]: 44
7845 22:18:14.254104 [Byte1]: 44
7846 22:18:14.258477
7847 22:18:14.258587 Set Vref, RX VrefLevel [Byte0]: 45
7848 22:18:14.261773 [Byte1]: 45
7849 22:18:14.266131
7850 22:18:14.266209 Set Vref, RX VrefLevel [Byte0]: 46
7851 22:18:14.269334 [Byte1]: 46
7852 22:18:14.273693
7853 22:18:14.273806 Set Vref, RX VrefLevel [Byte0]: 47
7854 22:18:14.276947 [Byte1]: 47
7855 22:18:14.281389
7856 22:18:14.281493 Set Vref, RX VrefLevel [Byte0]: 48
7857 22:18:14.284559 [Byte1]: 48
7858 22:18:14.289032
7859 22:18:14.289140 Set Vref, RX VrefLevel [Byte0]: 49
7860 22:18:14.292137 [Byte1]: 49
7861 22:18:14.296392
7862 22:18:14.296469 Set Vref, RX VrefLevel [Byte0]: 50
7863 22:18:14.299503 [Byte1]: 50
7864 22:18:14.303959
7865 22:18:14.304053 Set Vref, RX VrefLevel [Byte0]: 51
7866 22:18:14.307194 [Byte1]: 51
7867 22:18:14.311733
7868 22:18:14.311810 Set Vref, RX VrefLevel [Byte0]: 52
7869 22:18:14.314705 [Byte1]: 52
7870 22:18:14.319151
7871 22:18:14.319253 Set Vref, RX VrefLevel [Byte0]: 53
7872 22:18:14.322275 [Byte1]: 53
7873 22:18:14.326647
7874 22:18:14.326748 Set Vref, RX VrefLevel [Byte0]: 54
7875 22:18:14.330524 [Byte1]: 54
7876 22:18:14.334701
7877 22:18:14.334809 Set Vref, RX VrefLevel [Byte0]: 55
7878 22:18:14.337838 [Byte1]: 55
7879 22:18:14.342303
7880 22:18:14.342404 Set Vref, RX VrefLevel [Byte0]: 56
7881 22:18:14.348551 [Byte1]: 56
7882 22:18:14.348663
7883 22:18:14.351682 Set Vref, RX VrefLevel [Byte0]: 57
7884 22:18:14.355520 [Byte1]: 57
7885 22:18:14.355626
7886 22:18:14.358665 Set Vref, RX VrefLevel [Byte0]: 58
7887 22:18:14.361624 [Byte1]: 58
7888 22:18:14.365339
7889 22:18:14.365441 Set Vref, RX VrefLevel [Byte0]: 59
7890 22:18:14.368798 [Byte1]: 59
7891 22:18:14.372305
7892 22:18:14.372408 Set Vref, RX VrefLevel [Byte0]: 60
7893 22:18:14.375848 [Byte1]: 60
7894 22:18:14.379989
7895 22:18:14.380097 Set Vref, RX VrefLevel [Byte0]: 61
7896 22:18:14.383233 [Byte1]: 61
7897 22:18:14.387609
7898 22:18:14.387716 Set Vref, RX VrefLevel [Byte0]: 62
7899 22:18:14.391327 [Byte1]: 62
7900 22:18:14.395634
7901 22:18:14.395751 Set Vref, RX VrefLevel [Byte0]: 63
7902 22:18:14.398807 [Byte1]: 63
7903 22:18:14.403341
7904 22:18:14.403456 Set Vref, RX VrefLevel [Byte0]: 64
7905 22:18:14.406308 [Byte1]: 64
7906 22:18:14.410921
7907 22:18:14.410996 Set Vref, RX VrefLevel [Byte0]: 65
7908 22:18:14.413691 [Byte1]: 65
7909 22:18:14.418366
7910 22:18:14.418468 Set Vref, RX VrefLevel [Byte0]: 66
7911 22:18:14.421326 [Byte1]: 66
7912 22:18:14.426087
7913 22:18:14.426163 Set Vref, RX VrefLevel [Byte0]: 67
7914 22:18:14.429282 [Byte1]: 67
7915 22:18:14.433612
7916 22:18:14.433724 Set Vref, RX VrefLevel [Byte0]: 68
7917 22:18:14.436653 [Byte1]: 68
7918 22:18:14.441323
7919 22:18:14.441431 Set Vref, RX VrefLevel [Byte0]: 69
7920 22:18:14.447770 [Byte1]: 69
7921 22:18:14.447851
7922 22:18:14.450973 Set Vref, RX VrefLevel [Byte0]: 70
7923 22:18:14.453994 [Byte1]: 70
7924 22:18:14.454093
7925 22:18:14.457732 Set Vref, RX VrefLevel [Byte0]: 71
7926 22:18:14.460923 [Byte1]: 71
7927 22:18:14.464095
7928 22:18:14.464201 Set Vref, RX VrefLevel [Byte0]: 72
7929 22:18:14.467131 [Byte1]: 72
7930 22:18:14.471476
7931 22:18:14.471581 Set Vref, RX VrefLevel [Byte0]: 73
7932 22:18:14.474704 [Byte1]: 73
7933 22:18:14.479118
7934 22:18:14.479196 Set Vref, RX VrefLevel [Byte0]: 74
7935 22:18:14.482709 [Byte1]: 74
7936 22:18:14.486759
7937 22:18:14.486861 Set Vref, RX VrefLevel [Byte0]: 75
7938 22:18:14.489810 [Byte1]: 75
7939 22:18:14.494208
7940 22:18:14.494283 Set Vref, RX VrefLevel [Byte0]: 76
7941 22:18:14.497432 [Byte1]: 76
7942 22:18:14.501922
7943 22:18:14.502019 Final RX Vref Byte 0 = 63 to rank0
7944 22:18:14.505084 Final RX Vref Byte 1 = 58 to rank0
7945 22:18:14.508864 Final RX Vref Byte 0 = 63 to rank1
7946 22:18:14.512095 Final RX Vref Byte 1 = 58 to rank1==
7947 22:18:14.515009 Dram Type= 6, Freq= 0, CH_0, rank 0
7948 22:18:14.521551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 22:18:14.521664 ==
7950 22:18:14.521757 DQS Delay:
7951 22:18:14.525117 DQS0 = 0, DQS1 = 0
7952 22:18:14.525225 DQM Delay:
7953 22:18:14.525315 DQM0 = 126, DQM1 = 119
7954 22:18:14.528526 DQ Delay:
7955 22:18:14.531391 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7956 22:18:14.535193 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7957 22:18:14.538327 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7958 22:18:14.541461 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7959 22:18:14.541560
7960 22:18:14.541652
7961 22:18:14.541745
7962 22:18:14.545025 [DramC_TX_OE_Calibration] TA2
7963 22:18:14.547835 Original DQ_B0 (3 6) =30, OEN = 27
7964 22:18:14.551284 Original DQ_B1 (3 6) =30, OEN = 27
7965 22:18:14.554411 24, 0x0, End_B0=24 End_B1=24
7966 22:18:14.558290 25, 0x0, End_B0=25 End_B1=25
7967 22:18:14.558393 26, 0x0, End_B0=26 End_B1=26
7968 22:18:14.561520 27, 0x0, End_B0=27 End_B1=27
7969 22:18:14.564549 28, 0x0, End_B0=28 End_B1=28
7970 22:18:14.567670 29, 0x0, End_B0=29 End_B1=29
7971 22:18:14.567753 30, 0x0, End_B0=30 End_B1=30
7972 22:18:14.571444 31, 0x4141, End_B0=30 End_B1=30
7973 22:18:14.574667 Byte0 end_step=30 best_step=27
7974 22:18:14.577702 Byte1 end_step=30 best_step=27
7975 22:18:14.580916 Byte0 TX OE(2T, 0.5T) = (3, 3)
7976 22:18:14.584094 Byte1 TX OE(2T, 0.5T) = (3, 3)
7977 22:18:14.584195
7978 22:18:14.584283
7979 22:18:14.590947 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7980 22:18:14.594477 CH0 RK0: MR19=303, MR18=1514
7981 22:18:14.601052 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
7982 22:18:14.601155
7983 22:18:14.604259 ----->DramcWriteLeveling(PI) begin...
7984 22:18:14.604364 ==
7985 22:18:14.607509 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 22:18:14.610783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 22:18:14.610923 ==
7988 22:18:14.613970 Write leveling (Byte 0): 36 => 36
7989 22:18:14.617057 Write leveling (Byte 1): 29 => 29
7990 22:18:14.620641 DramcWriteLeveling(PI) end<-----
7991 22:18:14.620711
7992 22:18:14.620770 ==
7993 22:18:14.623657 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 22:18:14.627367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 22:18:14.630445 ==
7996 22:18:14.630545 [Gating] SW mode calibration
7997 22:18:14.640555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7998 22:18:14.643773 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7999 22:18:14.647050 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 22:18:14.653725 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 22:18:14.656738 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 22:18:14.660494 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8003 22:18:14.666757 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8004 22:18:14.669858 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 22:18:14.673675 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 22:18:14.679885 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 22:18:14.683193 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 22:18:14.686379 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 22:18:14.693341 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8010 22:18:14.696425 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
8011 22:18:14.699981 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8012 22:18:14.706315 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8013 22:18:14.709581 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 22:18:14.712725 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 22:18:14.719595 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 22:18:14.722728 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 22:18:14.726207 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 22:18:14.732545 1 6 12 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (1 1)
8019 22:18:14.735673 1 6 16 | B1->B0 | 3131 4646 | 1 0 | (1 1) (0 0)
8020 22:18:14.739404 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8021 22:18:14.746096 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 22:18:14.749298 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 22:18:14.752508 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 22:18:14.758674 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 22:18:14.762466 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8026 22:18:14.765308 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8027 22:18:14.772021 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8028 22:18:14.775288 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8029 22:18:14.778508 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:18:14.785414 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:18:14.788484 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:18:14.791667 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 22:18:14.798672 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 22:18:14.801667 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 22:18:14.805207 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 22:18:14.811394 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 22:18:14.815175 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 22:18:14.818383 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 22:18:14.824781 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 22:18:14.828564 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 22:18:14.831644 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8042 22:18:14.837951 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8043 22:18:14.841661 Total UI for P1: 0, mck2ui 16
8044 22:18:14.844682 best dqsien dly found for B0: ( 1, 9, 8)
8045 22:18:14.848139 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8046 22:18:14.851089 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8047 22:18:14.858035 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 22:18:14.861121 Total UI for P1: 0, mck2ui 16
8049 22:18:14.864890 best dqsien dly found for B1: ( 1, 9, 20)
8050 22:18:14.868110 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8051 22:18:14.871251 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8052 22:18:14.871351
8053 22:18:14.874736 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8054 22:18:14.877696 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8055 22:18:14.881211 [Gating] SW calibration Done
8056 22:18:14.881322 ==
8057 22:18:14.884414 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 22:18:14.887590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 22:18:14.887663 ==
8060 22:18:14.890693 RX Vref Scan: 0
8061 22:18:14.890788
8062 22:18:14.893948 RX Vref 0 -> 0, step: 1
8063 22:18:14.894044
8064 22:18:14.894108 RX Delay 0 -> 252, step: 8
8065 22:18:14.901121 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8066 22:18:14.904149 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8067 22:18:14.907819 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8068 22:18:14.910915 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8069 22:18:14.914092 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8070 22:18:14.920891 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8071 22:18:14.923961 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8072 22:18:14.927118 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8073 22:18:14.930304 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8074 22:18:14.934015 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8075 22:18:14.940200 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8076 22:18:14.944092 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8077 22:18:14.947331 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8078 22:18:14.950580 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8079 22:18:14.956900 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8080 22:18:14.960341 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8081 22:18:14.960424 ==
8082 22:18:14.963381 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 22:18:14.966999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 22:18:14.967081 ==
8085 22:18:14.967146 DQS Delay:
8086 22:18:14.970167 DQS0 = 0, DQS1 = 0
8087 22:18:14.970249 DQM Delay:
8088 22:18:14.973468 DQM0 = 128, DQM1 = 121
8089 22:18:14.973550 DQ Delay:
8090 22:18:14.976697 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8091 22:18:14.980204 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8092 22:18:14.983242 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8093 22:18:14.989699 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8094 22:18:14.989781
8095 22:18:14.989846
8096 22:18:14.989906 ==
8097 22:18:14.993512 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 22:18:14.996516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 22:18:14.996598 ==
8100 22:18:14.996662
8101 22:18:14.996721
8102 22:18:14.999708 TX Vref Scan disable
8103 22:18:14.999790 == TX Byte 0 ==
8104 22:18:15.006036 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8105 22:18:15.009674 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8106 22:18:15.012697 == TX Byte 1 ==
8107 22:18:15.016306 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8108 22:18:15.019477 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8109 22:18:15.019559 ==
8110 22:18:15.022580 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 22:18:15.026169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 22:18:15.029150 ==
8113 22:18:15.042349
8114 22:18:15.045554 TX Vref early break, caculate TX vref
8115 22:18:15.048591 TX Vref=16, minBit 8, minWin=22, winSum=372
8116 22:18:15.051867 TX Vref=18, minBit 2, minWin=23, winSum=383
8117 22:18:15.055597 TX Vref=20, minBit 8, minWin=23, winSum=388
8118 22:18:15.058653 TX Vref=22, minBit 8, minWin=23, winSum=399
8119 22:18:15.061720 TX Vref=24, minBit 10, minWin=24, winSum=405
8120 22:18:15.068822 TX Vref=26, minBit 4, minWin=25, winSum=412
8121 22:18:15.071829 TX Vref=28, minBit 0, minWin=25, winSum=413
8122 22:18:15.074978 TX Vref=30, minBit 8, minWin=24, winSum=416
8123 22:18:15.078143 TX Vref=32, minBit 8, minWin=23, winSum=403
8124 22:18:15.081961 TX Vref=34, minBit 8, minWin=24, winSum=397
8125 22:18:15.088027 TX Vref=36, minBit 8, minWin=22, winSum=387
8126 22:18:15.091533 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8127 22:18:15.091616
8128 22:18:15.094582 Final TX Range 0 Vref 28
8129 22:18:15.094663
8130 22:18:15.094727 ==
8131 22:18:15.098450 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 22:18:15.101287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 22:18:15.104486 ==
8134 22:18:15.104567
8135 22:18:15.104631
8136 22:18:15.104690 TX Vref Scan disable
8137 22:18:15.111912 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8138 22:18:15.111993 == TX Byte 0 ==
8139 22:18:15.115025 u2DelayCellOfst[0]=11 cells (3 PI)
8140 22:18:15.118003 u2DelayCellOfst[1]=18 cells (5 PI)
8141 22:18:15.121732 u2DelayCellOfst[2]=11 cells (3 PI)
8142 22:18:15.125030 u2DelayCellOfst[3]=11 cells (3 PI)
8143 22:18:15.128119 u2DelayCellOfst[4]=7 cells (2 PI)
8144 22:18:15.131540 u2DelayCellOfst[5]=0 cells (0 PI)
8145 22:18:15.134374 u2DelayCellOfst[6]=18 cells (5 PI)
8146 22:18:15.137589 u2DelayCellOfst[7]=18 cells (5 PI)
8147 22:18:15.141364 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8148 22:18:15.144547 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8149 22:18:15.147688 == TX Byte 1 ==
8150 22:18:15.150970 u2DelayCellOfst[8]=0 cells (0 PI)
8151 22:18:15.154240 u2DelayCellOfst[9]=0 cells (0 PI)
8152 22:18:15.157536 u2DelayCellOfst[10]=7 cells (2 PI)
8153 22:18:15.160695 u2DelayCellOfst[11]=7 cells (2 PI)
8154 22:18:15.164331 u2DelayCellOfst[12]=11 cells (3 PI)
8155 22:18:15.167383 u2DelayCellOfst[13]=11 cells (3 PI)
8156 22:18:15.170521 u2DelayCellOfst[14]=11 cells (3 PI)
8157 22:18:15.174500 u2DelayCellOfst[15]=7 cells (2 PI)
8158 22:18:15.177099 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8159 22:18:15.180699 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8160 22:18:15.183853 DramC Write-DBI on
8161 22:18:15.183942 ==
8162 22:18:15.187018 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 22:18:15.190214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 22:18:15.190293 ==
8165 22:18:15.190357
8166 22:18:15.190415
8167 22:18:15.193439 TX Vref Scan disable
8168 22:18:15.196878 == TX Byte 0 ==
8169 22:18:15.200496 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8170 22:18:15.200589 == TX Byte 1 ==
8171 22:18:15.206525 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8172 22:18:15.206613 DramC Write-DBI off
8173 22:18:15.206708
8174 22:18:15.206795 [DATLAT]
8175 22:18:15.210358 Freq=1600, CH0 RK1
8176 22:18:15.210439
8177 22:18:15.213539 DATLAT Default: 0xf
8178 22:18:15.213619 0, 0xFFFF, sum = 0
8179 22:18:15.216602 1, 0xFFFF, sum = 0
8180 22:18:15.216685 2, 0xFFFF, sum = 0
8181 22:18:15.220191 3, 0xFFFF, sum = 0
8182 22:18:15.220273 4, 0xFFFF, sum = 0
8183 22:18:15.223270 5, 0xFFFF, sum = 0
8184 22:18:15.223345 6, 0xFFFF, sum = 0
8185 22:18:15.226558 7, 0xFFFF, sum = 0
8186 22:18:15.226630 8, 0xFFFF, sum = 0
8187 22:18:15.230278 9, 0xFFFF, sum = 0
8188 22:18:15.230349 10, 0xFFFF, sum = 0
8189 22:18:15.233348 11, 0xFFFF, sum = 0
8190 22:18:15.233444 12, 0xFFFF, sum = 0
8191 22:18:15.236494 13, 0xCFFF, sum = 0
8192 22:18:15.236565 14, 0x0, sum = 1
8193 22:18:15.240115 15, 0x0, sum = 2
8194 22:18:15.240189 16, 0x0, sum = 3
8195 22:18:15.243292 17, 0x0, sum = 4
8196 22:18:15.243368 best_step = 15
8197 22:18:15.243429
8198 22:18:15.243487 ==
8199 22:18:15.246481 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 22:18:15.253284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 22:18:15.253370 ==
8202 22:18:15.253434 RX Vref Scan: 0
8203 22:18:15.253494
8204 22:18:15.256590 RX Vref 0 -> 0, step: 1
8205 22:18:15.256671
8206 22:18:15.259780 RX Delay 3 -> 252, step: 4
8207 22:18:15.263031 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8208 22:18:15.266150 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8209 22:18:15.272933 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8210 22:18:15.276238 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8211 22:18:15.279462 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8212 22:18:15.282743 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8213 22:18:15.286405 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8214 22:18:15.292815 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8215 22:18:15.296052 iDelay=191, Bit 8, Center 110 (51 ~ 170) 120
8216 22:18:15.299059 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8217 22:18:15.302621 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8218 22:18:15.306071 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8219 22:18:15.312732 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8220 22:18:15.315704 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8221 22:18:15.318735 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8222 22:18:15.322499 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8223 22:18:15.322580 ==
8224 22:18:15.325420 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 22:18:15.332320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 22:18:15.332403 ==
8227 22:18:15.332507 DQS Delay:
8228 22:18:15.335500 DQS0 = 0, DQS1 = 0
8229 22:18:15.335581 DQM Delay:
8230 22:18:15.338612 DQM0 = 124, DQM1 = 118
8231 22:18:15.338693 DQ Delay:
8232 22:18:15.341718 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8233 22:18:15.345392 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8234 22:18:15.348516 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8235 22:18:15.351996 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8236 22:18:15.352131
8237 22:18:15.352226
8238 22:18:15.352315
8239 22:18:15.355143 [DramC_TX_OE_Calibration] TA2
8240 22:18:15.358350 Original DQ_B0 (3 6) =30, OEN = 27
8241 22:18:15.361605 Original DQ_B1 (3 6) =30, OEN = 27
8242 22:18:15.364792 24, 0x0, End_B0=24 End_B1=24
8243 22:18:15.368556 25, 0x0, End_B0=25 End_B1=25
8244 22:18:15.368671 26, 0x0, End_B0=26 End_B1=26
8245 22:18:15.371703 27, 0x0, End_B0=27 End_B1=27
8246 22:18:15.374727 28, 0x0, End_B0=28 End_B1=28
8247 22:18:15.377998 29, 0x0, End_B0=29 End_B1=29
8248 22:18:15.381190 30, 0x0, End_B0=30 End_B1=30
8249 22:18:15.381292 31, 0x5151, End_B0=30 End_B1=30
8250 22:18:15.385218 Byte0 end_step=30 best_step=27
8251 22:18:15.388131 Byte1 end_step=30 best_step=27
8252 22:18:15.391102 Byte0 TX OE(2T, 0.5T) = (3, 3)
8253 22:18:15.394523 Byte1 TX OE(2T, 0.5T) = (3, 3)
8254 22:18:15.394654
8255 22:18:15.394750
8256 22:18:15.401486 [DQSOSCAuto] RK1, (LSB)MR18= 0x2311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8257 22:18:15.404571 CH0 RK1: MR19=303, MR18=2311
8258 22:18:15.411293 CH0_RK1: MR19=0x303, MR18=0x2311, DQSOSC=392, MR23=63, INC=24, DEC=16
8259 22:18:15.414279 [RxdqsGatingPostProcess] freq 1600
8260 22:18:15.420781 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8261 22:18:15.423961 best DQS0 dly(2T, 0.5T) = (1, 1)
8262 22:18:15.424061 best DQS1 dly(2T, 0.5T) = (1, 1)
8263 22:18:15.427813 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8264 22:18:15.430629 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8265 22:18:15.434321 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 22:18:15.437639 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 22:18:15.440508 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 22:18:15.443700 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 22:18:15.447680 Pre-setting of DQS Precalculation
8270 22:18:15.454150 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8271 22:18:15.454233 ==
8272 22:18:15.457193 Dram Type= 6, Freq= 0, CH_1, rank 0
8273 22:18:15.460767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 22:18:15.460849 ==
8275 22:18:15.467296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 22:18:15.470494 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 22:18:15.473707 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 22:18:15.480518 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 22:18:15.488609 [CA 0] Center 41 (13~70) winsize 58
8280 22:18:15.491763 [CA 1] Center 42 (12~72) winsize 61
8281 22:18:15.495428 [CA 2] Center 37 (9~66) winsize 58
8282 22:18:15.498462 [CA 3] Center 36 (7~66) winsize 60
8283 22:18:15.501610 [CA 4] Center 37 (8~67) winsize 60
8284 22:18:15.505410 [CA 5] Center 36 (7~66) winsize 60
8285 22:18:15.505491
8286 22:18:15.508130 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 22:18:15.508212
8288 22:18:15.515088 [CATrainingPosCal] consider 1 rank data
8289 22:18:15.515171 u2DelayCellTimex100 = 258/100 ps
8290 22:18:15.521594 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8291 22:18:15.524657 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8292 22:18:15.528221 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8293 22:18:15.531131 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8294 22:18:15.534535 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8295 22:18:15.538041 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8296 22:18:15.538123
8297 22:18:15.540988 CA PerBit enable=1, Macro0, CA PI delay=36
8298 22:18:15.541070
8299 22:18:15.544626 [CBTSetCACLKResult] CA Dly = 36
8300 22:18:15.547926 CS Dly: 10 (0~41)
8301 22:18:15.551167 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 22:18:15.554308 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 22:18:15.554389 ==
8304 22:18:15.557897 Dram Type= 6, Freq= 0, CH_1, rank 1
8305 22:18:15.564511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 22:18:15.564593 ==
8307 22:18:15.567607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 22:18:15.574508 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 22:18:15.577867 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 22:18:15.584133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 22:18:15.591783 [CA 0] Center 41 (12~71) winsize 60
8312 22:18:15.595060 [CA 1] Center 42 (12~72) winsize 61
8313 22:18:15.598192 [CA 2] Center 37 (8~67) winsize 60
8314 22:18:15.601908 [CA 3] Center 36 (7~66) winsize 60
8315 22:18:15.605196 [CA 4] Center 37 (7~67) winsize 61
8316 22:18:15.608085 [CA 5] Center 36 (6~66) winsize 61
8317 22:18:15.608166
8318 22:18:15.611739 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 22:18:15.611819
8320 22:18:15.618501 [CATrainingPosCal] consider 2 rank data
8321 22:18:15.618611 u2DelayCellTimex100 = 258/100 ps
8322 22:18:15.624582 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8323 22:18:15.628299 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8324 22:18:15.631232 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8325 22:18:15.635047 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 22:18:15.638104 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8327 22:18:15.641130 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8328 22:18:15.641228
8329 22:18:15.644702 CA PerBit enable=1, Macro0, CA PI delay=36
8330 22:18:15.644773
8331 22:18:15.647740 [CBTSetCACLKResult] CA Dly = 36
8332 22:18:15.651260 CS Dly: 11 (0~43)
8333 22:18:15.654326 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 22:18:15.657623 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 22:18:15.657695
8336 22:18:15.660732 ----->DramcWriteLeveling(PI) begin...
8337 22:18:15.660803 ==
8338 22:18:15.664453 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 22:18:15.671072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 22:18:15.671156 ==
8341 22:18:15.674102 Write leveling (Byte 0): 26 => 26
8342 22:18:15.677353 Write leveling (Byte 1): 29 => 29
8343 22:18:15.680535 DramcWriteLeveling(PI) end<-----
8344 22:18:15.680618
8345 22:18:15.680683 ==
8346 22:18:15.684245 Dram Type= 6, Freq= 0, CH_1, rank 0
8347 22:18:15.687264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8348 22:18:15.687347 ==
8349 22:18:15.690523 [Gating] SW mode calibration
8350 22:18:15.697690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8351 22:18:15.700734 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8352 22:18:15.707606 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 22:18:15.710682 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 22:18:15.713858 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 22:18:15.720528 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8356 22:18:15.723741 1 4 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
8357 22:18:15.726793 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 22:18:15.733425 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 22:18:15.737109 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 22:18:15.739991 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 22:18:15.746636 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 22:18:15.750145 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 22:18:15.753150 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
8364 22:18:15.760172 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
8365 22:18:15.763460 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 22:18:15.766603 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 22:18:15.773054 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 22:18:15.776737 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 22:18:15.779610 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 22:18:15.786657 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 22:18:15.789723 1 6 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8372 22:18:15.792883 1 6 16 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8373 22:18:15.799887 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 22:18:15.803118 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 22:18:15.806381 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 22:18:15.812988 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 22:18:15.816339 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 22:18:15.819693 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 22:18:15.825664 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 22:18:15.829427 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8381 22:18:15.835621 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:18:15.838811 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:18:15.842757 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 22:18:15.849198 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 22:18:15.852075 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 22:18:15.855442 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 22:18:15.862077 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 22:18:15.865229 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 22:18:15.868466 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 22:18:15.875271 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 22:18:15.878413 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 22:18:15.881966 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 22:18:15.888313 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 22:18:15.891325 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 22:18:15.895048 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8396 22:18:15.901760 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8397 22:18:15.904767 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 22:18:15.907898 Total UI for P1: 0, mck2ui 16
8399 22:18:15.911936 best dqsien dly found for B0: ( 1, 9, 14)
8400 22:18:15.914708 Total UI for P1: 0, mck2ui 16
8401 22:18:15.918067 best dqsien dly found for B1: ( 1, 9, 14)
8402 22:18:15.921734 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8403 22:18:15.924874 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8404 22:18:15.924956
8405 22:18:15.928078 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8406 22:18:15.931094 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8407 22:18:15.934161 [Gating] SW calibration Done
8408 22:18:15.934243 ==
8409 22:18:15.937843 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 22:18:15.940793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 22:18:15.944587 ==
8412 22:18:15.944678 RX Vref Scan: 0
8413 22:18:15.944744
8414 22:18:15.947266 RX Vref 0 -> 0, step: 1
8415 22:18:15.947348
8416 22:18:15.951368 RX Delay 0 -> 252, step: 8
8417 22:18:15.953899 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8418 22:18:15.957427 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8419 22:18:15.961013 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8420 22:18:15.964059 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8421 22:18:15.970209 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8422 22:18:15.973896 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8423 22:18:15.977221 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8424 22:18:15.980563 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8425 22:18:15.983785 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8426 22:18:15.990502 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8427 22:18:15.993433 iDelay=208, Bit 10, Center 127 (80 ~ 175) 96
8428 22:18:15.997024 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8429 22:18:16.000058 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8430 22:18:16.006450 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8431 22:18:16.009700 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8432 22:18:16.013564 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8433 22:18:16.013646 ==
8434 22:18:16.016633 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 22:18:16.019657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 22:18:16.019740 ==
8437 22:18:16.023646 DQS Delay:
8438 22:18:16.023727 DQS0 = 0, DQS1 = 0
8439 22:18:16.026623 DQM Delay:
8440 22:18:16.026706 DQM0 = 132, DQM1 = 126
8441 22:18:16.029906 DQ Delay:
8442 22:18:16.033194 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8443 22:18:16.036304 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8444 22:18:16.039251 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8445 22:18:16.042798 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8446 22:18:16.042925
8447 22:18:16.042989
8448 22:18:16.043077 ==
8449 22:18:16.046226 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 22:18:16.049409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 22:18:16.049491 ==
8452 22:18:16.049555
8453 22:18:16.052644
8454 22:18:16.052726 TX Vref Scan disable
8455 22:18:16.055784 == TX Byte 0 ==
8456 22:18:16.059079 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8457 22:18:16.062757 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8458 22:18:16.065831 == TX Byte 1 ==
8459 22:18:16.069159 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8460 22:18:16.072739 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8461 22:18:16.072822 ==
8462 22:18:16.075752 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 22:18:16.082156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 22:18:16.082240 ==
8465 22:18:16.095052
8466 22:18:16.098267 TX Vref early break, caculate TX vref
8467 22:18:16.101851 TX Vref=16, minBit 8, minWin=21, winSum=363
8468 22:18:16.104737 TX Vref=18, minBit 10, minWin=21, winSum=369
8469 22:18:16.108482 TX Vref=20, minBit 8, minWin=23, winSum=383
8470 22:18:16.111705 TX Vref=22, minBit 9, minWin=23, winSum=391
8471 22:18:16.114793 TX Vref=24, minBit 8, minWin=24, winSum=402
8472 22:18:16.121702 TX Vref=26, minBit 1, minWin=25, winSum=412
8473 22:18:16.124773 TX Vref=28, minBit 1, minWin=25, winSum=413
8474 22:18:16.128547 TX Vref=30, minBit 1, minWin=25, winSum=412
8475 22:18:16.131751 TX Vref=32, minBit 0, minWin=24, winSum=403
8476 22:18:16.135011 TX Vref=34, minBit 9, minWin=23, winSum=393
8477 22:18:16.138110 TX Vref=36, minBit 9, minWin=22, winSum=382
8478 22:18:16.144746 [TxChooseVref] Worse bit 1, Min win 25, Win sum 413, Final Vref 28
8479 22:18:16.144829
8480 22:18:16.147615 Final TX Range 0 Vref 28
8481 22:18:16.147715
8482 22:18:16.147814 ==
8483 22:18:16.151041 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 22:18:16.154438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 22:18:16.157514 ==
8486 22:18:16.157595
8487 22:18:16.157659
8488 22:18:16.157719 TX Vref Scan disable
8489 22:18:16.164252 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8490 22:18:16.164336 == TX Byte 0 ==
8491 22:18:16.167534 u2DelayCellOfst[0]=22 cells (6 PI)
8492 22:18:16.170585 u2DelayCellOfst[1]=15 cells (4 PI)
8493 22:18:16.174106 u2DelayCellOfst[2]=0 cells (0 PI)
8494 22:18:16.177969 u2DelayCellOfst[3]=7 cells (2 PI)
8495 22:18:16.180822 u2DelayCellOfst[4]=7 cells (2 PI)
8496 22:18:16.184279 u2DelayCellOfst[5]=22 cells (6 PI)
8497 22:18:16.187198 u2DelayCellOfst[6]=18 cells (5 PI)
8498 22:18:16.190890 u2DelayCellOfst[7]=7 cells (2 PI)
8499 22:18:16.194030 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8500 22:18:16.196995 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8501 22:18:16.200222 == TX Byte 1 ==
8502 22:18:16.203476 u2DelayCellOfst[8]=0 cells (0 PI)
8503 22:18:16.207171 u2DelayCellOfst[9]=7 cells (2 PI)
8504 22:18:16.210067 u2DelayCellOfst[10]=15 cells (4 PI)
8505 22:18:16.213512 u2DelayCellOfst[11]=7 cells (2 PI)
8506 22:18:16.217134 u2DelayCellOfst[12]=15 cells (4 PI)
8507 22:18:16.220226 u2DelayCellOfst[13]=22 cells (6 PI)
8508 22:18:16.223486 u2DelayCellOfst[14]=18 cells (5 PI)
8509 22:18:16.226573 u2DelayCellOfst[15]=18 cells (5 PI)
8510 22:18:16.230055 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8511 22:18:16.233582 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8512 22:18:16.236578 DramC Write-DBI on
8513 22:18:16.236681 ==
8514 22:18:16.239782 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 22:18:16.243008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 22:18:16.243107 ==
8517 22:18:16.243201
8518 22:18:16.243288
8519 22:18:16.246722 TX Vref Scan disable
8520 22:18:16.246815 == TX Byte 0 ==
8521 22:18:16.253499 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8522 22:18:16.253588 == TX Byte 1 ==
8523 22:18:16.256350 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8524 22:18:16.259731 DramC Write-DBI off
8525 22:18:16.259834
8526 22:18:16.259921 [DATLAT]
8527 22:18:16.262983 Freq=1600, CH1 RK0
8528 22:18:16.263083
8529 22:18:16.263164 DATLAT Default: 0xf
8530 22:18:16.266730 0, 0xFFFF, sum = 0
8531 22:18:16.269862 1, 0xFFFF, sum = 0
8532 22:18:16.269951 2, 0xFFFF, sum = 0
8533 22:18:16.273053 3, 0xFFFF, sum = 0
8534 22:18:16.273139 4, 0xFFFF, sum = 0
8535 22:18:16.276175 5, 0xFFFF, sum = 0
8536 22:18:16.276261 6, 0xFFFF, sum = 0
8537 22:18:16.279937 7, 0xFFFF, sum = 0
8538 22:18:16.280023 8, 0xFFFF, sum = 0
8539 22:18:16.282878 9, 0xFFFF, sum = 0
8540 22:18:16.282964 10, 0xFFFF, sum = 0
8541 22:18:16.286368 11, 0xFFFF, sum = 0
8542 22:18:16.286454 12, 0xFFFF, sum = 0
8543 22:18:16.289375 13, 0x8FFF, sum = 0
8544 22:18:16.289461 14, 0x0, sum = 1
8545 22:18:16.292988 15, 0x0, sum = 2
8546 22:18:16.293074 16, 0x0, sum = 3
8547 22:18:16.295863 17, 0x0, sum = 4
8548 22:18:16.295949 best_step = 15
8549 22:18:16.296043
8550 22:18:16.296140 ==
8551 22:18:16.299828 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 22:18:16.305905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 22:18:16.305992 ==
8554 22:18:16.306078 RX Vref Scan: 1
8555 22:18:16.306177
8556 22:18:16.309138 Set Vref Range= 24 -> 127
8557 22:18:16.309248
8558 22:18:16.312316 RX Vref 24 -> 127, step: 1
8559 22:18:16.312424
8560 22:18:16.312509 RX Delay 11 -> 252, step: 4
8561 22:18:16.316059
8562 22:18:16.316168 Set Vref, RX VrefLevel [Byte0]: 24
8563 22:18:16.318929 [Byte1]: 24
8564 22:18:16.323257
8565 22:18:16.323366 Set Vref, RX VrefLevel [Byte0]: 25
8566 22:18:16.326579 [Byte1]: 25
8567 22:18:16.331117
8568 22:18:16.331219 Set Vref, RX VrefLevel [Byte0]: 26
8569 22:18:16.334668 [Byte1]: 26
8570 22:18:16.338456
8571 22:18:16.338541 Set Vref, RX VrefLevel [Byte0]: 27
8572 22:18:16.341726 [Byte1]: 27
8573 22:18:16.346236
8574 22:18:16.346321 Set Vref, RX VrefLevel [Byte0]: 28
8575 22:18:16.349485 [Byte1]: 28
8576 22:18:16.354242
8577 22:18:16.354329 Set Vref, RX VrefLevel [Byte0]: 29
8578 22:18:16.357272 [Byte1]: 29
8579 22:18:16.361449
8580 22:18:16.361558 Set Vref, RX VrefLevel [Byte0]: 30
8581 22:18:16.364919 [Byte1]: 30
8582 22:18:16.369241
8583 22:18:16.369346 Set Vref, RX VrefLevel [Byte0]: 31
8584 22:18:16.372425 [Byte1]: 31
8585 22:18:16.376996
8586 22:18:16.377098 Set Vref, RX VrefLevel [Byte0]: 32
8587 22:18:16.380139 [Byte1]: 32
8588 22:18:16.384527
8589 22:18:16.384636 Set Vref, RX VrefLevel [Byte0]: 33
8590 22:18:16.387641 [Byte1]: 33
8591 22:18:16.391891
8592 22:18:16.392000 Set Vref, RX VrefLevel [Byte0]: 34
8593 22:18:16.395048 [Byte1]: 34
8594 22:18:16.399331
8595 22:18:16.399416 Set Vref, RX VrefLevel [Byte0]: 35
8596 22:18:16.402941 [Byte1]: 35
8597 22:18:16.407083
8598 22:18:16.407168 Set Vref, RX VrefLevel [Byte0]: 36
8599 22:18:16.410684 [Byte1]: 36
8600 22:18:16.414574
8601 22:18:16.414677 Set Vref, RX VrefLevel [Byte0]: 37
8602 22:18:16.417767 [Byte1]: 37
8603 22:18:16.422238
8604 22:18:16.422342 Set Vref, RX VrefLevel [Byte0]: 38
8605 22:18:16.425871 [Byte1]: 38
8606 22:18:16.430103
8607 22:18:16.430216 Set Vref, RX VrefLevel [Byte0]: 39
8608 22:18:16.433350 [Byte1]: 39
8609 22:18:16.437656
8610 22:18:16.437771 Set Vref, RX VrefLevel [Byte0]: 40
8611 22:18:16.440775 [Byte1]: 40
8612 22:18:16.445271
8613 22:18:16.445349 Set Vref, RX VrefLevel [Byte0]: 41
8614 22:18:16.448626 [Byte1]: 41
8615 22:18:16.453283
8616 22:18:16.453392 Set Vref, RX VrefLevel [Byte0]: 42
8617 22:18:16.456154 [Byte1]: 42
8618 22:18:16.460556
8619 22:18:16.460633 Set Vref, RX VrefLevel [Byte0]: 43
8620 22:18:16.463729 [Byte1]: 43
8621 22:18:16.468237
8622 22:18:16.468321 Set Vref, RX VrefLevel [Byte0]: 44
8623 22:18:16.471305 [Byte1]: 44
8624 22:18:16.475583
8625 22:18:16.475665 Set Vref, RX VrefLevel [Byte0]: 45
8626 22:18:16.479243 [Byte1]: 45
8627 22:18:16.483018
8628 22:18:16.483097 Set Vref, RX VrefLevel [Byte0]: 46
8629 22:18:16.486855 [Byte1]: 46
8630 22:18:16.490732
8631 22:18:16.490859 Set Vref, RX VrefLevel [Byte0]: 47
8632 22:18:16.494107 [Byte1]: 47
8633 22:18:16.498477
8634 22:18:16.498578 Set Vref, RX VrefLevel [Byte0]: 48
8635 22:18:16.501428 [Byte1]: 48
8636 22:18:16.506277
8637 22:18:16.506402 Set Vref, RX VrefLevel [Byte0]: 49
8638 22:18:16.509276 [Byte1]: 49
8639 22:18:16.513562
8640 22:18:16.513659 Set Vref, RX VrefLevel [Byte0]: 50
8641 22:18:16.516726 [Byte1]: 50
8642 22:18:16.521238
8643 22:18:16.521334 Set Vref, RX VrefLevel [Byte0]: 51
8644 22:18:16.524352 [Byte1]: 51
8645 22:18:16.529209
8646 22:18:16.529280 Set Vref, RX VrefLevel [Byte0]: 52
8647 22:18:16.532246 [Byte1]: 52
8648 22:18:16.536479
8649 22:18:16.536554 Set Vref, RX VrefLevel [Byte0]: 53
8650 22:18:16.540107 [Byte1]: 53
8651 22:18:16.544414
8652 22:18:16.544502 Set Vref, RX VrefLevel [Byte0]: 54
8653 22:18:16.547515 [Byte1]: 54
8654 22:18:16.551941
8655 22:18:16.552094 Set Vref, RX VrefLevel [Byte0]: 55
8656 22:18:16.555175 [Byte1]: 55
8657 22:18:16.559627
8658 22:18:16.559728 Set Vref, RX VrefLevel [Byte0]: 56
8659 22:18:16.562774 [Byte1]: 56
8660 22:18:16.567224
8661 22:18:16.567336 Set Vref, RX VrefLevel [Byte0]: 57
8662 22:18:16.570292 [Byte1]: 57
8663 22:18:16.574484
8664 22:18:16.574587 Set Vref, RX VrefLevel [Byte0]: 58
8665 22:18:16.578060 [Byte1]: 58
8666 22:18:16.582304
8667 22:18:16.582409 Set Vref, RX VrefLevel [Byte0]: 59
8668 22:18:16.585480 [Byte1]: 59
8669 22:18:16.589970
8670 22:18:16.590071 Set Vref, RX VrefLevel [Byte0]: 60
8671 22:18:16.593231 [Byte1]: 60
8672 22:18:16.597517
8673 22:18:16.597614 Set Vref, RX VrefLevel [Byte0]: 61
8674 22:18:16.600682 [Byte1]: 61
8675 22:18:16.605016
8676 22:18:16.605149 Set Vref, RX VrefLevel [Byte0]: 62
8677 22:18:16.608109 [Byte1]: 62
8678 22:18:16.612358
8679 22:18:16.612458 Set Vref, RX VrefLevel [Byte0]: 63
8680 22:18:16.615916 [Byte1]: 63
8681 22:18:16.620168
8682 22:18:16.620272 Set Vref, RX VrefLevel [Byte0]: 64
8683 22:18:16.623421 [Byte1]: 64
8684 22:18:16.627787
8685 22:18:16.627892 Set Vref, RX VrefLevel [Byte0]: 65
8686 22:18:16.631328 [Byte1]: 65
8687 22:18:16.635752
8688 22:18:16.635862 Set Vref, RX VrefLevel [Byte0]: 66
8689 22:18:16.638978 [Byte1]: 66
8690 22:18:16.643150
8691 22:18:16.643224 Set Vref, RX VrefLevel [Byte0]: 67
8692 22:18:16.646342 [Byte1]: 67
8693 22:18:16.650496
8694 22:18:16.650603 Set Vref, RX VrefLevel [Byte0]: 68
8695 22:18:16.654175 [Byte1]: 68
8696 22:18:16.658535
8697 22:18:16.658608 Set Vref, RX VrefLevel [Byte0]: 69
8698 22:18:16.661687 [Byte1]: 69
8699 22:18:16.666030
8700 22:18:16.666145 Set Vref, RX VrefLevel [Byte0]: 70
8701 22:18:16.669374 [Byte1]: 70
8702 22:18:16.673640
8703 22:18:16.673722 Set Vref, RX VrefLevel [Byte0]: 71
8704 22:18:16.676795 [Byte1]: 71
8705 22:18:16.680929
8706 22:18:16.681016 Final RX Vref Byte 0 = 55 to rank0
8707 22:18:16.684378 Final RX Vref Byte 1 = 56 to rank0
8708 22:18:16.687933 Final RX Vref Byte 0 = 55 to rank1
8709 22:18:16.690982 Final RX Vref Byte 1 = 56 to rank1==
8710 22:18:16.694263 Dram Type= 6, Freq= 0, CH_1, rank 0
8711 22:18:16.701304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8712 22:18:16.701386 ==
8713 22:18:16.701454 DQS Delay:
8714 22:18:16.704478 DQS0 = 0, DQS1 = 0
8715 22:18:16.704560 DQM Delay:
8716 22:18:16.704625 DQM0 = 130, DQM1 = 123
8717 22:18:16.707741 DQ Delay:
8718 22:18:16.710731 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8719 22:18:16.714279 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8720 22:18:16.717325 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8721 22:18:16.720526 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8722 22:18:16.720598
8723 22:18:16.720661
8724 22:18:16.720720
8725 22:18:16.724007 [DramC_TX_OE_Calibration] TA2
8726 22:18:16.726996 Original DQ_B0 (3 6) =30, OEN = 27
8727 22:18:16.730222 Original DQ_B1 (3 6) =30, OEN = 27
8728 22:18:16.733896 24, 0x0, End_B0=24 End_B1=24
8729 22:18:16.736964 25, 0x0, End_B0=25 End_B1=25
8730 22:18:16.737069 26, 0x0, End_B0=26 End_B1=26
8731 22:18:16.740888 27, 0x0, End_B0=27 End_B1=27
8732 22:18:16.743968 28, 0x0, End_B0=28 End_B1=28
8733 22:18:16.747150 29, 0x0, End_B0=29 End_B1=29
8734 22:18:16.747234 30, 0x0, End_B0=30 End_B1=30
8735 22:18:16.750155 31, 0x4141, End_B0=30 End_B1=30
8736 22:18:16.753795 Byte0 end_step=30 best_step=27
8737 22:18:16.756944 Byte1 end_step=30 best_step=27
8738 22:18:16.760117 Byte0 TX OE(2T, 0.5T) = (3, 3)
8739 22:18:16.763241 Byte1 TX OE(2T, 0.5T) = (3, 3)
8740 22:18:16.763364
8741 22:18:16.763458
8742 22:18:16.770210 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8743 22:18:16.773287 CH1 RK0: MR19=303, MR18=A0E
8744 22:18:16.780242 CH1_RK0: MR19=0x303, MR18=0xA0E, DQSOSC=402, MR23=63, INC=22, DEC=15
8745 22:18:16.780353
8746 22:18:16.783532 ----->DramcWriteLeveling(PI) begin...
8747 22:18:16.783652 ==
8748 22:18:16.786817 Dram Type= 6, Freq= 0, CH_1, rank 1
8749 22:18:16.789631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8750 22:18:16.789739 ==
8751 22:18:16.793161 Write leveling (Byte 0): 23 => 23
8752 22:18:16.796552 Write leveling (Byte 1): 30 => 30
8753 22:18:16.799665 DramcWriteLeveling(PI) end<-----
8754 22:18:16.799772
8755 22:18:16.799862 ==
8756 22:18:16.802821 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 22:18:16.806714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 22:18:16.809867 ==
8759 22:18:16.809945 [Gating] SW mode calibration
8760 22:18:16.819635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8761 22:18:16.822568 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8762 22:18:16.826148 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 22:18:16.832534 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 22:18:16.836133 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8765 22:18:16.839184 1 4 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8766 22:18:16.845888 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 22:18:16.849203 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 22:18:16.852437 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 22:18:16.859179 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 22:18:16.862519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 22:18:16.865391 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8772 22:18:16.872266 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8773 22:18:16.875445 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
8774 22:18:16.878572 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 22:18:16.885589 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 22:18:16.888227 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 22:18:16.895257 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 22:18:16.898253 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 22:18:16.901653 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8780 22:18:16.907948 1 6 8 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8781 22:18:16.911164 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8782 22:18:16.915006 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 22:18:16.921319 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 22:18:16.924380 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 22:18:16.928182 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 22:18:16.934735 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 22:18:16.937701 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 22:18:16.941066 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8789 22:18:16.948033 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8790 22:18:16.951140 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 22:18:16.954087 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 22:18:16.960905 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 22:18:16.964612 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 22:18:16.967532 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 22:18:16.974208 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 22:18:16.977409 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 22:18:16.980610 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 22:18:16.984261 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 22:18:16.990626 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 22:18:16.993837 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:18:16.997079 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 22:18:17.003938 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 22:18:17.007093 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 22:18:17.010204 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8805 22:18:17.016744 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8806 22:18:17.020536 Total UI for P1: 0, mck2ui 16
8807 22:18:17.023775 best dqsien dly found for B0: ( 1, 9, 8)
8808 22:18:17.027003 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 22:18:17.030115 Total UI for P1: 0, mck2ui 16
8810 22:18:17.033282 best dqsien dly found for B1: ( 1, 9, 12)
8811 22:18:17.036989 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8812 22:18:17.040273 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8813 22:18:17.040349
8814 22:18:17.043317 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8815 22:18:17.049715 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8816 22:18:17.049826 [Gating] SW calibration Done
8817 22:18:17.049909 ==
8818 22:18:17.052909 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 22:18:17.059607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 22:18:17.059694 ==
8821 22:18:17.059775 RX Vref Scan: 0
8822 22:18:17.059839
8823 22:18:17.062986 RX Vref 0 -> 0, step: 1
8824 22:18:17.063082
8825 22:18:17.066027 RX Delay 0 -> 252, step: 8
8826 22:18:17.069316 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8827 22:18:17.072980 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8828 22:18:17.076033 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8829 22:18:17.082342 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8830 22:18:17.086054 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8831 22:18:17.089161 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8832 22:18:17.092300 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8833 22:18:17.095527 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8834 22:18:17.102475 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8835 22:18:17.105596 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8836 22:18:17.108817 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8837 22:18:17.112626 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8838 22:18:17.118682 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8839 22:18:17.122372 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8840 22:18:17.125279 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8841 22:18:17.128571 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8842 22:18:17.128686 ==
8843 22:18:17.132260 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 22:18:17.138634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 22:18:17.138743 ==
8846 22:18:17.138862 DQS Delay:
8847 22:18:17.141643 DQS0 = 0, DQS1 = 0
8848 22:18:17.141754 DQM Delay:
8849 22:18:17.141847 DQM0 = 131, DQM1 = 130
8850 22:18:17.145533 DQ Delay:
8851 22:18:17.148653 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8852 22:18:17.151597 DQ4 =123, DQ5 =143, DQ6 =139, DQ7 =131
8853 22:18:17.155188 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8854 22:18:17.158265 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8855 22:18:17.158340
8856 22:18:17.158402
8857 22:18:17.158461 ==
8858 22:18:17.161719 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 22:18:17.168371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 22:18:17.168489 ==
8861 22:18:17.168583
8862 22:18:17.168681
8863 22:18:17.168768 TX Vref Scan disable
8864 22:18:17.171486 == TX Byte 0 ==
8865 22:18:17.174911 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8866 22:18:17.181594 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8867 22:18:17.181719 == TX Byte 1 ==
8868 22:18:17.184681 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8869 22:18:17.191282 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8870 22:18:17.191375 ==
8871 22:18:17.194436 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 22:18:17.198287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 22:18:17.198409 ==
8874 22:18:17.210955
8875 22:18:17.214222 TX Vref early break, caculate TX vref
8876 22:18:17.217427 TX Vref=16, minBit 0, minWin=22, winSum=372
8877 22:18:17.221169 TX Vref=18, minBit 0, minWin=23, winSum=381
8878 22:18:17.224102 TX Vref=20, minBit 0, minWin=23, winSum=390
8879 22:18:17.227135 TX Vref=22, minBit 8, minWin=23, winSum=398
8880 22:18:17.230707 TX Vref=24, minBit 8, minWin=23, winSum=401
8881 22:18:17.237138 TX Vref=26, minBit 0, minWin=25, winSum=413
8882 22:18:17.240758 TX Vref=28, minBit 8, minWin=24, winSum=410
8883 22:18:17.243890 TX Vref=30, minBit 5, minWin=24, winSum=413
8884 22:18:17.247252 TX Vref=32, minBit 8, minWin=23, winSum=401
8885 22:18:17.250380 TX Vref=34, minBit 5, minWin=22, winSum=390
8886 22:18:17.256721 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 26
8887 22:18:17.256857
8888 22:18:17.260580 Final TX Range 0 Vref 26
8889 22:18:17.260688
8890 22:18:17.260768 ==
8891 22:18:17.263522 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 22:18:17.266991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 22:18:17.267100 ==
8894 22:18:17.267167
8895 22:18:17.267228
8896 22:18:17.269806 TX Vref Scan disable
8897 22:18:17.276859 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8898 22:18:17.276974 == TX Byte 0 ==
8899 22:18:17.279834 u2DelayCellOfst[0]=18 cells (5 PI)
8900 22:18:17.283471 u2DelayCellOfst[1]=11 cells (3 PI)
8901 22:18:17.286303 u2DelayCellOfst[2]=0 cells (0 PI)
8902 22:18:17.289913 u2DelayCellOfst[3]=3 cells (1 PI)
8903 22:18:17.292923 u2DelayCellOfst[4]=7 cells (2 PI)
8904 22:18:17.296268 u2DelayCellOfst[5]=22 cells (6 PI)
8905 22:18:17.299480 u2DelayCellOfst[6]=18 cells (5 PI)
8906 22:18:17.303255 u2DelayCellOfst[7]=3 cells (1 PI)
8907 22:18:17.306397 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8908 22:18:17.309503 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8909 22:18:17.313343 == TX Byte 1 ==
8910 22:18:17.316532 u2DelayCellOfst[8]=0 cells (0 PI)
8911 22:18:17.319645 u2DelayCellOfst[9]=7 cells (2 PI)
8912 22:18:17.322770 u2DelayCellOfst[10]=11 cells (3 PI)
8913 22:18:17.322901 u2DelayCellOfst[11]=7 cells (2 PI)
8914 22:18:17.325884 u2DelayCellOfst[12]=11 cells (3 PI)
8915 22:18:17.329726 u2DelayCellOfst[13]=15 cells (4 PI)
8916 22:18:17.332596 u2DelayCellOfst[14]=18 cells (5 PI)
8917 22:18:17.336201 u2DelayCellOfst[15]=15 cells (4 PI)
8918 22:18:17.342518 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8919 22:18:17.345662 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8920 22:18:17.345773 DramC Write-DBI on
8921 22:18:17.349334 ==
8922 22:18:17.352743 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 22:18:17.355646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 22:18:17.355760 ==
8925 22:18:17.355854
8926 22:18:17.355951
8927 22:18:17.358770 TX Vref Scan disable
8928 22:18:17.358897 == TX Byte 0 ==
8929 22:18:17.365773 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8930 22:18:17.365886 == TX Byte 1 ==
8931 22:18:17.368829 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8932 22:18:17.371953 DramC Write-DBI off
8933 22:18:17.372057
8934 22:18:17.372151 [DATLAT]
8935 22:18:17.375670 Freq=1600, CH1 RK1
8936 22:18:17.375789
8937 22:18:17.375881 DATLAT Default: 0xf
8938 22:18:17.378622 0, 0xFFFF, sum = 0
8939 22:18:17.378741 1, 0xFFFF, sum = 0
8940 22:18:17.382119 2, 0xFFFF, sum = 0
8941 22:18:17.382226 3, 0xFFFF, sum = 0
8942 22:18:17.385012 4, 0xFFFF, sum = 0
8943 22:18:17.388596 5, 0xFFFF, sum = 0
8944 22:18:17.388733 6, 0xFFFF, sum = 0
8945 22:18:17.392288 7, 0xFFFF, sum = 0
8946 22:18:17.392394 8, 0xFFFF, sum = 0
8947 22:18:17.395222 9, 0xFFFF, sum = 0
8948 22:18:17.395340 10, 0xFFFF, sum = 0
8949 22:18:17.398753 11, 0xFFFF, sum = 0
8950 22:18:17.398876 12, 0xFFFF, sum = 0
8951 22:18:17.401723 13, 0x8FFF, sum = 0
8952 22:18:17.401831 14, 0x0, sum = 1
8953 22:18:17.404979 15, 0x0, sum = 2
8954 22:18:17.405082 16, 0x0, sum = 3
8955 22:18:17.408167 17, 0x0, sum = 4
8956 22:18:17.408254 best_step = 15
8957 22:18:17.408321
8958 22:18:17.408387 ==
8959 22:18:17.411974 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 22:18:17.415104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 22:18:17.418438 ==
8962 22:18:17.418591 RX Vref Scan: 0
8963 22:18:17.418711
8964 22:18:17.421577 RX Vref 0 -> 0, step: 1
8965 22:18:17.421659
8966 22:18:17.424774 RX Delay 11 -> 252, step: 4
8967 22:18:17.428471 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8968 22:18:17.431563 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8969 22:18:17.434619 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8970 22:18:17.441410 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8971 22:18:17.444994 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8972 22:18:17.448152 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8973 22:18:17.451190 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8974 22:18:17.454872 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8975 22:18:17.461387 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8976 22:18:17.464489 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8977 22:18:17.467642 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8978 22:18:17.470848 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8979 22:18:17.474649 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
8980 22:18:17.480953 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8981 22:18:17.484602 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8982 22:18:17.487530 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8983 22:18:17.487613 ==
8984 22:18:17.491102 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 22:18:17.494145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 22:18:17.497609 ==
8987 22:18:17.497696 DQS Delay:
8988 22:18:17.497802 DQS0 = 0, DQS1 = 0
8989 22:18:17.500568 DQM Delay:
8990 22:18:17.500650 DQM0 = 129, DQM1 = 125
8991 22:18:17.504176 DQ Delay:
8992 22:18:17.507614 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
8993 22:18:17.510617 DQ4 =124, DQ5 =142, DQ6 =142, DQ7 =124
8994 22:18:17.513878 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
8995 22:18:17.516995 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =134
8996 22:18:17.517077
8997 22:18:17.517140
8998 22:18:17.517198
8999 22:18:17.520823 [DramC_TX_OE_Calibration] TA2
9000 22:18:17.524022 Original DQ_B0 (3 6) =30, OEN = 27
9001 22:18:17.527197 Original DQ_B1 (3 6) =30, OEN = 27
9002 22:18:17.530479 24, 0x0, End_B0=24 End_B1=24
9003 22:18:17.530561 25, 0x0, End_B0=25 End_B1=25
9004 22:18:17.533635 26, 0x0, End_B0=26 End_B1=26
9005 22:18:17.537311 27, 0x0, End_B0=27 End_B1=27
9006 22:18:17.540484 28, 0x0, End_B0=28 End_B1=28
9007 22:18:17.543654 29, 0x0, End_B0=29 End_B1=29
9008 22:18:17.543736 30, 0x0, End_B0=30 End_B1=30
9009 22:18:17.546742 31, 0x4545, End_B0=30 End_B1=30
9010 22:18:17.550395 Byte0 end_step=30 best_step=27
9011 22:18:17.553563 Byte1 end_step=30 best_step=27
9012 22:18:17.556648 Byte0 TX OE(2T, 0.5T) = (3, 3)
9013 22:18:17.559863 Byte1 TX OE(2T, 0.5T) = (3, 3)
9014 22:18:17.559974
9015 22:18:17.560066
9016 22:18:17.566894 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9017 22:18:17.570096 CH1 RK1: MR19=303, MR18=111D
9018 22:18:17.576616 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9019 22:18:17.579747 [RxdqsGatingPostProcess] freq 1600
9020 22:18:17.583271 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9021 22:18:17.586169 best DQS0 dly(2T, 0.5T) = (1, 1)
9022 22:18:17.589580 best DQS1 dly(2T, 0.5T) = (1, 1)
9023 22:18:17.593077 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9024 22:18:17.596553 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9025 22:18:17.599587 best DQS0 dly(2T, 0.5T) = (1, 1)
9026 22:18:17.603207 best DQS1 dly(2T, 0.5T) = (1, 1)
9027 22:18:17.605850 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9028 22:18:17.609463 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9029 22:18:17.613049 Pre-setting of DQS Precalculation
9030 22:18:17.615959 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9031 22:18:17.625785 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9032 22:18:17.632254 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9033 22:18:17.632342
9034 22:18:17.632420
9035 22:18:17.635552 [Calibration Summary] 3200 Mbps
9036 22:18:17.635657 CH 0, Rank 0
9037 22:18:17.638644 SW Impedance : PASS
9038 22:18:17.638746 DUTY Scan : NO K
9039 22:18:17.642245 ZQ Calibration : PASS
9040 22:18:17.645511 Jitter Meter : NO K
9041 22:18:17.645618 CBT Training : PASS
9042 22:18:17.648623 Write leveling : PASS
9043 22:18:17.651846 RX DQS gating : PASS
9044 22:18:17.651950 RX DQ/DQS(RDDQC) : PASS
9045 22:18:17.655370 TX DQ/DQS : PASS
9046 22:18:17.658465 RX DATLAT : PASS
9047 22:18:17.658573 RX DQ/DQS(Engine): PASS
9048 22:18:17.662024 TX OE : PASS
9049 22:18:17.662131 All Pass.
9050 22:18:17.662207
9051 22:18:17.665142 CH 0, Rank 1
9052 22:18:17.665246 SW Impedance : PASS
9053 22:18:17.668556 DUTY Scan : NO K
9054 22:18:17.671556 ZQ Calibration : PASS
9055 22:18:17.671670 Jitter Meter : NO K
9056 22:18:17.674749 CBT Training : PASS
9057 22:18:17.677999 Write leveling : PASS
9058 22:18:17.678104 RX DQS gating : PASS
9059 22:18:17.681183 RX DQ/DQS(RDDQC) : PASS
9060 22:18:17.684580 TX DQ/DQS : PASS
9061 22:18:17.684683 RX DATLAT : PASS
9062 22:18:17.687620 RX DQ/DQS(Engine): PASS
9063 22:18:17.691238 TX OE : PASS
9064 22:18:17.691340 All Pass.
9065 22:18:17.691436
9066 22:18:17.691528 CH 1, Rank 0
9067 22:18:17.694294 SW Impedance : PASS
9068 22:18:17.697921 DUTY Scan : NO K
9069 22:18:17.697999 ZQ Calibration : PASS
9070 22:18:17.701515 Jitter Meter : NO K
9071 22:18:17.704368 CBT Training : PASS
9072 22:18:17.704478 Write leveling : PASS
9073 22:18:17.707914 RX DQS gating : PASS
9074 22:18:17.711413 RX DQ/DQS(RDDQC) : PASS
9075 22:18:17.711518 TX DQ/DQS : PASS
9076 22:18:17.714435 RX DATLAT : PASS
9077 22:18:17.714543 RX DQ/DQS(Engine): PASS
9078 22:18:17.717537 TX OE : PASS
9079 22:18:17.717647 All Pass.
9080 22:18:17.717738
9081 22:18:17.721150 CH 1, Rank 1
9082 22:18:17.721257 SW Impedance : PASS
9083 22:18:17.724143 DUTY Scan : NO K
9084 22:18:17.727577 ZQ Calibration : PASS
9085 22:18:17.727696 Jitter Meter : NO K
9086 22:18:17.730776 CBT Training : PASS
9087 22:18:17.734527 Write leveling : PASS
9088 22:18:17.734630 RX DQS gating : PASS
9089 22:18:17.737823 RX DQ/DQS(RDDQC) : PASS
9090 22:18:17.741188 TX DQ/DQS : PASS
9091 22:18:17.741294 RX DATLAT : PASS
9092 22:18:17.744086 RX DQ/DQS(Engine): PASS
9093 22:18:17.747636 TX OE : PASS
9094 22:18:17.747726 All Pass.
9095 22:18:17.747792
9096 22:18:17.750804 DramC Write-DBI on
9097 22:18:17.750930 PER_BANK_REFRESH: Hybrid Mode
9098 22:18:17.754198 TX_TRACKING: ON
9099 22:18:17.763904 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9100 22:18:17.770661 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9101 22:18:17.777264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 22:18:17.780526 [FAST_K] Save calibration result to emmc
9103 22:18:17.783719 sync common calibartion params.
9104 22:18:17.786821 sync cbt_mode0:1, 1:1
9105 22:18:17.786944 dram_init: ddr_geometry: 2
9106 22:18:17.790240 dram_init: ddr_geometry: 2
9107 22:18:17.793857 dram_init: ddr_geometry: 2
9108 22:18:17.796913 0:dram_rank_size:100000000
9109 22:18:17.796996 1:dram_rank_size:100000000
9110 22:18:17.803258 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9111 22:18:17.806941 DFS_SHUFFLE_HW_MODE: ON
9112 22:18:17.809799 dramc_set_vcore_voltage set vcore to 725000
9113 22:18:17.813310 Read voltage for 1600, 0
9114 22:18:17.813392 Vio18 = 0
9115 22:18:17.813456 Vcore = 725000
9116 22:18:17.816927 Vdram = 0
9117 22:18:17.817007 Vddq = 0
9118 22:18:17.817071 Vmddr = 0
9119 22:18:17.819820 switch to 3200 Mbps bootup
9120 22:18:17.819902 [DramcRunTimeConfig]
9121 22:18:17.823312 PHYPLL
9122 22:18:17.823393 DPM_CONTROL_AFTERK: ON
9123 22:18:17.826092 PER_BANK_REFRESH: ON
9124 22:18:17.829753 REFRESH_OVERHEAD_REDUCTION: ON
9125 22:18:17.829860 CMD_PICG_NEW_MODE: OFF
9126 22:18:17.833291 XRTWTW_NEW_MODE: ON
9127 22:18:17.833371 XRTRTR_NEW_MODE: ON
9128 22:18:17.836332 TX_TRACKING: ON
9129 22:18:17.836434 RDSEL_TRACKING: OFF
9130 22:18:17.839475 DQS Precalculation for DVFS: ON
9131 22:18:17.842729 RX_TRACKING: OFF
9132 22:18:17.842813 HW_GATING DBG: ON
9133 22:18:17.846487 ZQCS_ENABLE_LP4: ON
9134 22:18:17.846569 RX_PICG_NEW_MODE: ON
9135 22:18:17.849530 TX_PICG_NEW_MODE: ON
9136 22:18:17.852705 ENABLE_RX_DCM_DPHY: ON
9137 22:18:17.852786 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9138 22:18:17.855829 DUMMY_READ_FOR_TRACKING: OFF
9139 22:18:17.859885 !!! SPM_CONTROL_AFTERK: OFF
9140 22:18:17.862874 !!! SPM could not control APHY
9141 22:18:17.866094 IMPEDANCE_TRACKING: ON
9142 22:18:17.866199 TEMP_SENSOR: ON
9143 22:18:17.866272 HW_SAVE_FOR_SR: OFF
9144 22:18:17.869726 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9145 22:18:17.876156 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9146 22:18:17.876238 Read ODT Tracking: ON
9147 22:18:17.879414 Refresh Rate DeBounce: ON
9148 22:18:17.879496 DFS_NO_QUEUE_FLUSH: ON
9149 22:18:17.882691 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9150 22:18:17.885813 ENABLE_DFS_RUNTIME_MRW: OFF
9151 22:18:17.888997 DDR_RESERVE_NEW_MODE: ON
9152 22:18:17.892258 MR_CBT_SWITCH_FREQ: ON
9153 22:18:17.892338 =========================
9154 22:18:17.911946 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9155 22:18:17.915031 dram_init: ddr_geometry: 2
9156 22:18:17.933190 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9157 22:18:17.936647 dram_init: dram init end (result: 0)
9158 22:18:17.943098 DRAM-K: Full calibration passed in 24554 msecs
9159 22:18:17.946780 MRC: failed to locate region type 0.
9160 22:18:17.947021 DRAM rank0 size:0x100000000,
9161 22:18:17.950066 DRAM rank1 size=0x100000000
9162 22:18:17.960303 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9163 22:18:17.966616 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9164 22:18:17.973832 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9165 22:18:17.982945 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9166 22:18:17.983579 DRAM rank0 size:0x100000000,
9167 22:18:17.986038 DRAM rank1 size=0x100000000
9168 22:18:17.986627 CBMEM:
9169 22:18:17.989889 IMD: root @ 0xfffff000 254 entries.
9170 22:18:17.993070 IMD: root @ 0xffffec00 62 entries.
9171 22:18:17.996172 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9172 22:18:18.003103 WARNING: RO_VPD is uninitialized or empty.
9173 22:18:18.005938 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9174 22:18:18.013645 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9175 22:18:18.026496 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9176 22:18:18.037632 BS: romstage times (exec / console): total (unknown) / 24016 ms
9177 22:18:18.038413
9178 22:18:18.039137
9179 22:18:18.047730 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9180 22:18:18.051170 ARM64: Exception handlers installed.
9181 22:18:18.054126 ARM64: Testing exception
9182 22:18:18.057521 ARM64: Done test exception
9183 22:18:18.058097 Enumerating buses...
9184 22:18:18.060687 Show all devs... Before device enumeration.
9185 22:18:18.063858 Root Device: enabled 1
9186 22:18:18.067096 CPU_CLUSTER: 0: enabled 1
9187 22:18:18.067456 CPU: 00: enabled 1
9188 22:18:18.070801 Compare with tree...
9189 22:18:18.071213 Root Device: enabled 1
9190 22:18:18.073953 CPU_CLUSTER: 0: enabled 1
9191 22:18:18.077137 CPU: 00: enabled 1
9192 22:18:18.077467 Root Device scanning...
9193 22:18:18.080160 scan_static_bus for Root Device
9194 22:18:18.083576 CPU_CLUSTER: 0 enabled
9195 22:18:18.087024 scan_static_bus for Root Device done
9196 22:18:18.090487 scan_bus: bus Root Device finished in 8 msecs
9197 22:18:18.090731 done
9198 22:18:18.096774 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9199 22:18:18.100628 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9200 22:18:18.107009 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9201 22:18:18.110067 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9202 22:18:18.113365 Allocating resources...
9203 22:18:18.116703 Reading resources...
9204 22:18:18.119965 Root Device read_resources bus 0 link: 0
9205 22:18:18.123316 DRAM rank0 size:0x100000000,
9206 22:18:18.123530 DRAM rank1 size=0x100000000
9207 22:18:18.129977 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9208 22:18:18.130198 CPU: 00 missing read_resources
9209 22:18:18.136445 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9210 22:18:18.140075 Root Device read_resources bus 0 link: 0 done
9211 22:18:18.143173 Done reading resources.
9212 22:18:18.146838 Show resources in subtree (Root Device)...After reading.
9213 22:18:18.149490 Root Device child on link 0 CPU_CLUSTER: 0
9214 22:18:18.152828 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 22:18:18.162945 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 22:18:18.163045 CPU: 00
9217 22:18:18.166223 Root Device assign_resources, bus 0 link: 0
9218 22:18:18.169239 CPU_CLUSTER: 0 missing set_resources
9219 22:18:18.176079 Root Device assign_resources, bus 0 link: 0 done
9220 22:18:18.176160 Done setting resources.
9221 22:18:18.183111 Show resources in subtree (Root Device)...After assigning values.
9222 22:18:18.186131 Root Device child on link 0 CPU_CLUSTER: 0
9223 22:18:18.189268 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 22:18:18.199563 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 22:18:18.199645 CPU: 00
9226 22:18:18.202774 Done allocating resources.
9227 22:18:18.209123 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9228 22:18:18.209205 Enabling resources...
9229 22:18:18.212339 done.
9230 22:18:18.215859 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9231 22:18:18.219116 Initializing devices...
9232 22:18:18.219196 Root Device init
9233 22:18:18.222302 init hardware done!
9234 22:18:18.222385 0x00000018: ctrlr->caps
9235 22:18:18.225530 52.000 MHz: ctrlr->f_max
9236 22:18:18.229041 0.400 MHz: ctrlr->f_min
9237 22:18:18.229132 0x40ff8080: ctrlr->voltages
9238 22:18:18.232281 sclk: 390625
9239 22:18:18.232364 Bus Width = 1
9240 22:18:18.235819 sclk: 390625
9241 22:18:18.235902 Bus Width = 1
9242 22:18:18.239045 Early init status = 3
9243 22:18:18.242183 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9244 22:18:18.245358 in-header: 03 fc 00 00 01 00 00 00
9245 22:18:18.248444 in-data: 00
9246 22:18:18.252049 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9247 22:18:18.256095 in-header: 03 fd 00 00 00 00 00 00
9248 22:18:18.259644 in-data:
9249 22:18:18.262756 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9250 22:18:18.266308 in-header: 03 fc 00 00 01 00 00 00
9251 22:18:18.269328 in-data: 00
9252 22:18:18.272813 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9253 22:18:18.277392 in-header: 03 fd 00 00 00 00 00 00
9254 22:18:18.281063 in-data:
9255 22:18:18.284272 [SSUSB] Setting up USB HOST controller...
9256 22:18:18.287531 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9257 22:18:18.290535 [SSUSB] phy power-on done.
9258 22:18:18.293724 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9259 22:18:18.300516 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9260 22:18:18.303789 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9261 22:18:18.310481 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9262 22:18:18.316615 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9263 22:18:18.323578 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9264 22:18:18.329811 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9265 22:18:18.336500 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9266 22:18:18.339599 SPM: binary array size = 0x9dc
9267 22:18:18.343416 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9268 22:18:18.349633 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9269 22:18:18.356633 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9270 22:18:18.362682 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9271 22:18:18.366023 configure_display: Starting display init
9272 22:18:18.400707 anx7625_power_on_init: Init interface.
9273 22:18:18.403784 anx7625_disable_pd_protocol: Disabled PD feature.
9274 22:18:18.407531 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9275 22:18:18.434955 anx7625_start_dp_work: Secure OCM version=00
9276 22:18:18.438151 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9277 22:18:18.453325 sp_tx_get_edid_block: EDID Block = 1
9278 22:18:18.555929 Extracted contents:
9279 22:18:18.559161 header: 00 ff ff ff ff ff ff 00
9280 22:18:18.562340 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9281 22:18:18.565543 version: 01 04
9282 22:18:18.569165 basic params: 95 1f 11 78 0a
9283 22:18:18.572145 chroma info: 76 90 94 55 54 90 27 21 50 54
9284 22:18:18.575836 established: 00 00 00
9285 22:18:18.582231 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9286 22:18:18.585676 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9287 22:18:18.592295 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9288 22:18:18.599124 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9289 22:18:18.605374 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9290 22:18:18.608606 extensions: 00
9291 22:18:18.608696 checksum: fb
9292 22:18:18.608762
9293 22:18:18.611790 Manufacturer: IVO Model 57d Serial Number 0
9294 22:18:18.615074 Made week 0 of 2020
9295 22:18:18.618732 EDID version: 1.4
9296 22:18:18.618816 Digital display
9297 22:18:18.621950 6 bits per primary color channel
9298 22:18:18.622031 DisplayPort interface
9299 22:18:18.625203 Maximum image size: 31 cm x 17 cm
9300 22:18:18.628601 Gamma: 220%
9301 22:18:18.628681 Check DPMS levels
9302 22:18:18.631677 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9303 22:18:18.638387 First detailed timing is preferred timing
9304 22:18:18.638469 Established timings supported:
9305 22:18:18.641497 Standard timings supported:
9306 22:18:18.644637 Detailed timings
9307 22:18:18.648343 Hex of detail: 383680a07038204018303c0035ae10000019
9308 22:18:18.654651 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9309 22:18:18.657804 0780 0798 07c8 0820 hborder 0
9310 22:18:18.661149 0438 043b 0447 0458 vborder 0
9311 22:18:18.664859 -hsync -vsync
9312 22:18:18.664957 Did detailed timing
9313 22:18:18.671434 Hex of detail: 000000000000000000000000000000000000
9314 22:18:18.674478 Manufacturer-specified data, tag 0
9315 22:18:18.677480 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9316 22:18:18.681348 ASCII string: InfoVision
9317 22:18:18.684541 Hex of detail: 000000fe00523134304e574635205248200a
9318 22:18:18.687815 ASCII string: R140NWF5 RH
9319 22:18:18.687887 Checksum
9320 22:18:18.690821 Checksum: 0xfb (valid)
9321 22:18:18.694399 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9322 22:18:18.697268 DSI data_rate: 832800000 bps
9323 22:18:18.703918 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9324 22:18:18.707178 anx7625_parse_edid: pixelclock(138800).
9325 22:18:18.710651 hactive(1920), hsync(48), hfp(24), hbp(88)
9326 22:18:18.714181 vactive(1080), vsync(12), vfp(3), vbp(17)
9327 22:18:18.717272 anx7625_dsi_config: config dsi.
9328 22:18:18.723555 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9329 22:18:18.738263 anx7625_dsi_config: success to config DSI
9330 22:18:18.741126 anx7625_dp_start: MIPI phy setup OK.
9331 22:18:18.744229 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9332 22:18:18.748003 mtk_ddp_mode_set invalid vrefresh 60
9333 22:18:18.751091 main_disp_path_setup
9334 22:18:18.751174 ovl_layer_smi_id_en
9335 22:18:18.754162 ovl_layer_smi_id_en
9336 22:18:18.754235 ccorr_config
9337 22:18:18.754306 aal_config
9338 22:18:18.757222 gamma_config
9339 22:18:18.757311 postmask_config
9340 22:18:18.760913 dither_config
9341 22:18:18.764180 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9342 22:18:18.770594 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9343 22:18:18.773620 Root Device init finished in 551 msecs
9344 22:18:18.777278 CPU_CLUSTER: 0 init
9345 22:18:18.783663 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9346 22:18:18.790727 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9347 22:18:18.790810 APU_MBOX 0x190000b0 = 0x10001
9348 22:18:18.793909 APU_MBOX 0x190001b0 = 0x10001
9349 22:18:18.797047 APU_MBOX 0x190005b0 = 0x10001
9350 22:18:18.800539 APU_MBOX 0x190006b0 = 0x10001
9351 22:18:18.807209 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9352 22:18:18.816589 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9353 22:18:18.829013 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9354 22:18:18.835472 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9355 22:18:18.847497 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9356 22:18:18.856376 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9357 22:18:18.860072 CPU_CLUSTER: 0 init finished in 81 msecs
9358 22:18:18.863142 Devices initialized
9359 22:18:18.866204 Show all devs... After init.
9360 22:18:18.866290 Root Device: enabled 1
9361 22:18:18.870067 CPU_CLUSTER: 0: enabled 1
9362 22:18:18.873185 CPU: 00: enabled 1
9363 22:18:18.876433 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9364 22:18:18.879715 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9365 22:18:18.882698 ELOG: NV offset 0x57f000 size 0x1000
9366 22:18:18.889751 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9367 22:18:18.896047 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9368 22:18:18.899258 ELOG: Event(17) added with size 13 at 2023-06-05 22:18:23 UTC
9369 22:18:18.906036 out: cmd=0x121: 03 db 21 01 00 00 00 00
9370 22:18:18.909720 in-header: 03 6a 00 00 2c 00 00 00
9371 22:18:18.922515 in-data: f5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 22:18:18.926277 ELOG: Event(A1) added with size 10 at 2023-06-05 22:18:23 UTC
9373 22:18:18.932853 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9374 22:18:18.939357 ELOG: Event(A0) added with size 9 at 2023-06-05 22:18:23 UTC
9375 22:18:18.942445 elog_add_boot_reason: Logged dev mode boot
9376 22:18:18.949002 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9377 22:18:18.949084 Finalize devices...
9378 22:18:18.952490 Devices finalized
9379 22:18:18.955563 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9380 22:18:18.958726 Writing coreboot table at 0xffe64000
9381 22:18:18.965501 0. 000000000010a000-0000000000113fff: RAMSTAGE
9382 22:18:18.968686 1. 0000000040000000-00000000400fffff: RAM
9383 22:18:18.972525 2. 0000000040100000-000000004032afff: RAMSTAGE
9384 22:18:18.975673 3. 000000004032b000-00000000545fffff: RAM
9385 22:18:18.978770 4. 0000000054600000-000000005465ffff: BL31
9386 22:18:18.985774 5. 0000000054660000-00000000ffe63fff: RAM
9387 22:18:18.988761 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9388 22:18:18.991897 7. 0000000100000000-000000023fffffff: RAM
9389 22:18:18.995154 Passing 5 GPIOs to payload:
9390 22:18:18.998792 NAME | PORT | POLARITY | VALUE
9391 22:18:19.005281 EC in RW | 0x000000aa | low | undefined
9392 22:18:19.008429 EC interrupt | 0x00000005 | low | undefined
9393 22:18:19.015310 TPM interrupt | 0x000000ab | high | undefined
9394 22:18:19.018359 SD card detect | 0x00000011 | high | undefined
9395 22:18:19.024951 speaker enable | 0x00000093 | high | undefined
9396 22:18:19.027949 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9397 22:18:19.031636 in-header: 03 f9 00 00 02 00 00 00
9398 22:18:19.031743 in-data: 02 00
9399 22:18:19.034761 ADC[4]: Raw value=892971 ID=7
9400 22:18:19.037839 ADC[3]: Raw value=213810 ID=1
9401 22:18:19.037924 RAM Code: 0x71
9402 22:18:19.041556 ADC[6]: Raw value=74722 ID=0
9403 22:18:19.044576 ADC[5]: Raw value=212330 ID=1
9404 22:18:19.044679 SKU Code: 0x1
9405 22:18:19.050942 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9406 22:18:19.054973 coreboot table: 964 bytes.
9407 22:18:19.057520 IMD ROOT 0. 0xfffff000 0x00001000
9408 22:18:19.060993 IMD SMALL 1. 0xffffe000 0x00001000
9409 22:18:19.064602 RO MCACHE 2. 0xffffc000 0x00001104
9410 22:18:19.067649 CONSOLE 3. 0xfff7c000 0x00080000
9411 22:18:19.070728 FMAP 4. 0xfff7b000 0x00000452
9412 22:18:19.074007 TIME STAMP 5. 0xfff7a000 0x00000910
9413 22:18:19.077159 VBOOT WORK 6. 0xfff66000 0x00014000
9414 22:18:19.081006 RAMOOPS 7. 0xffe66000 0x00100000
9415 22:18:19.084238 COREBOOT 8. 0xffe64000 0x00002000
9416 22:18:19.084321 IMD small region:
9417 22:18:19.087391 IMD ROOT 0. 0xffffec00 0x00000400
9418 22:18:19.090436 VPD 1. 0xffffeba0 0x0000004c
9419 22:18:19.094205 MMC STATUS 2. 0xffffeb80 0x00000004
9420 22:18:19.100620 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9421 22:18:19.100703 Probing TPM: done!
9422 22:18:19.107722 Connected to device vid:did:rid of 1ae0:0028:00
9423 22:18:19.117508 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9424 22:18:19.120676 Initialized TPM device CR50 revision 0
9425 22:18:19.120758 Checking cr50 for pending updates
9426 22:18:19.127375 Reading cr50 TPM mode
9427 22:18:19.135789 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9428 22:18:19.142612 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9429 22:18:19.182656 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9430 22:18:19.185890 Checking segment from ROM address 0x40100000
9431 22:18:19.189162 Checking segment from ROM address 0x4010001c
9432 22:18:19.195470 Loading segment from ROM address 0x40100000
9433 22:18:19.195552 code (compression=0)
9434 22:18:19.205533 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9435 22:18:19.212694 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9436 22:18:19.212777 it's not compressed!
9437 22:18:19.219200 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9438 22:18:19.225642 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9439 22:18:19.243104 Loading segment from ROM address 0x4010001c
9440 22:18:19.243232 Entry Point 0x80000000
9441 22:18:19.245820 Loaded segments
9442 22:18:19.249805 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9443 22:18:19.255977 Jumping to boot code at 0x80000000(0xffe64000)
9444 22:18:19.262591 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9445 22:18:19.269529 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9446 22:18:19.277290 read SPI 0x8eb68 0x74a8: 3225 us, 9260 KB/s, 74.080 Mbps
9447 22:18:19.280814 Checking segment from ROM address 0x40100000
9448 22:18:19.284058 Checking segment from ROM address 0x4010001c
9449 22:18:19.290805 Loading segment from ROM address 0x40100000
9450 22:18:19.290899 code (compression=1)
9451 22:18:19.297146 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9452 22:18:19.307182 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9453 22:18:19.307266 using LZMA
9454 22:18:19.315678 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9455 22:18:19.321914 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9456 22:18:19.325836 Loading segment from ROM address 0x4010001c
9457 22:18:19.325939 Entry Point 0x54601000
9458 22:18:19.329003 Loaded segments
9459 22:18:19.332116 NOTICE: MT8192 bl31_setup
9460 22:18:19.339666 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9461 22:18:19.342662 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9462 22:18:19.346215 WARNING: region 0:
9463 22:18:19.349089 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 22:18:19.349215 WARNING: region 1:
9465 22:18:19.355728 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9466 22:18:19.358869 WARNING: region 2:
9467 22:18:19.362603 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9468 22:18:19.365651 WARNING: region 3:
9469 22:18:19.369313 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 22:18:19.372450 WARNING: region 4:
9471 22:18:19.378741 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 22:18:19.378824 WARNING: region 5:
9473 22:18:19.382567 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 22:18:19.385598 WARNING: region 6:
9475 22:18:19.388923 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 22:18:19.392386 WARNING: region 7:
9477 22:18:19.395540 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 22:18:19.402340 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9479 22:18:19.405321 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9480 22:18:19.408650 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9481 22:18:19.415859 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9482 22:18:19.419092 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9483 22:18:19.425369 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9484 22:18:19.428535 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9485 22:18:19.431797 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9486 22:18:19.438817 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9487 22:18:19.442023 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9488 22:18:19.448724 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9489 22:18:19.451568 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9490 22:18:19.455185 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9491 22:18:19.461642 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9492 22:18:19.465152 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9493 22:18:19.468316 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9494 22:18:19.474494 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9495 22:18:19.478388 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9496 22:18:19.484681 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9497 22:18:19.487777 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9498 22:18:19.491550 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9499 22:18:19.497769 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9500 22:18:19.501355 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9501 22:18:19.507775 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9502 22:18:19.510772 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9503 22:18:19.514620 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9504 22:18:19.521054 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9505 22:18:19.524284 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9506 22:18:19.531062 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9507 22:18:19.534176 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9508 22:18:19.537341 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9509 22:18:19.544387 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9510 22:18:19.547642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9511 22:18:19.550722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9512 22:18:19.557279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9513 22:18:19.561067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9514 22:18:19.563797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9515 22:18:19.567439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9516 22:18:19.573686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9517 22:18:19.577295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9518 22:18:19.580297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9519 22:18:19.584058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9520 22:18:19.590277 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9521 22:18:19.593473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9522 22:18:19.597049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9523 22:18:19.600251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9524 22:18:19.607007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9525 22:18:19.610289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9526 22:18:19.613672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9527 22:18:19.620350 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9528 22:18:19.623592 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9529 22:18:19.629859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9530 22:18:19.633679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9531 22:18:19.640001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9532 22:18:19.643179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9533 22:18:19.647041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9534 22:18:19.653345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9535 22:18:19.656472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9536 22:18:19.663331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9537 22:18:19.666262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9538 22:18:19.673418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9539 22:18:19.676640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9540 22:18:19.683077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9541 22:18:19.686651 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9542 22:18:19.689652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9543 22:18:19.696099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9544 22:18:19.699793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9545 22:18:19.706036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9546 22:18:19.709775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9547 22:18:19.716102 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9548 22:18:19.719133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9549 22:18:19.726051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9550 22:18:19.729308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9551 22:18:19.732505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9552 22:18:19.739085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9553 22:18:19.742984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9554 22:18:19.749556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9555 22:18:19.752681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9556 22:18:19.759107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9557 22:18:19.762626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9558 22:18:19.769342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9559 22:18:19.772356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9560 22:18:19.775993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9561 22:18:19.782340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9562 22:18:19.785675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9563 22:18:19.792306 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9564 22:18:19.795868 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9565 22:18:19.802517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9566 22:18:19.805702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9567 22:18:19.808921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9568 22:18:19.815717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9569 22:18:19.818707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9570 22:18:19.825615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9571 22:18:19.828951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9572 22:18:19.835328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9573 22:18:19.838401 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9574 22:18:19.842010 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9575 22:18:19.848865 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9576 22:18:19.851889 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9577 22:18:19.855673 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9578 22:18:19.858748 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9579 22:18:19.865034 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9580 22:18:19.868505 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9581 22:18:19.875253 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9582 22:18:19.878235 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9583 22:18:19.885278 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9584 22:18:19.888055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9585 22:18:19.891720 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9586 22:18:19.898126 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9587 22:18:19.901288 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9588 22:18:19.908211 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9589 22:18:19.911864 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9590 22:18:19.914819 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9591 22:18:19.921591 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9592 22:18:19.924695 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9593 22:18:19.931608 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9594 22:18:19.934353 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9595 22:18:19.937919 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9596 22:18:19.944567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9597 22:18:19.947498 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9598 22:18:19.951139 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9599 22:18:19.954201 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9600 22:18:19.957966 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9601 22:18:19.964137 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9602 22:18:19.967240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9603 22:18:19.974167 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9604 22:18:19.977751 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9605 22:18:19.981177 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9606 22:18:19.987119 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9607 22:18:19.990798 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9608 22:18:19.997075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9609 22:18:20.000660 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9610 22:18:20.004163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9611 22:18:20.010569 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9612 22:18:20.013910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9613 22:18:20.020254 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9614 22:18:20.023837 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9615 22:18:20.026779 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9616 22:18:20.033865 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9617 22:18:20.036725 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9618 22:18:20.043329 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9619 22:18:20.046783 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9620 22:18:20.050509 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9621 22:18:20.057211 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9622 22:18:20.059978 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9623 22:18:20.066866 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9624 22:18:20.070066 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9625 22:18:20.073214 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9626 22:18:20.079699 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9627 22:18:20.083147 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9628 22:18:20.089869 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9629 22:18:20.092987 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9630 22:18:20.096628 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9631 22:18:20.103007 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9632 22:18:20.106443 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9633 22:18:20.109522 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9634 22:18:20.116634 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9635 22:18:20.119507 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9636 22:18:20.125919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9637 22:18:20.129536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9638 22:18:20.132623 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9639 22:18:20.139262 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9640 22:18:20.142938 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9641 22:18:20.149500 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9642 22:18:20.152459 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9643 22:18:20.155857 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9644 22:18:20.162342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9645 22:18:20.165485 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9646 22:18:20.172307 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9647 22:18:20.175449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9648 22:18:20.178960 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9649 22:18:20.185501 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9650 22:18:20.189221 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9651 22:18:20.195239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9652 22:18:20.199001 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9653 22:18:20.202025 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9654 22:18:20.208577 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9655 22:18:20.212069 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9656 22:18:20.218573 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9657 22:18:20.221671 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9658 22:18:20.225313 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9659 22:18:20.231516 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9660 22:18:20.234969 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9661 22:18:20.241622 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9662 22:18:20.245133 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9663 22:18:20.251127 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9664 22:18:20.254771 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9665 22:18:20.258017 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9666 22:18:20.264742 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9667 22:18:20.267730 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9668 22:18:20.274515 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9669 22:18:20.277598 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9670 22:18:20.284164 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9671 22:18:20.287356 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9672 22:18:20.290963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9673 22:18:20.297565 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9674 22:18:20.301104 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9675 22:18:20.307879 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9676 22:18:20.310898 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9677 22:18:20.317344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9678 22:18:20.320968 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9679 22:18:20.323866 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9680 22:18:20.330340 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9681 22:18:20.333537 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9682 22:18:20.340306 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9683 22:18:20.343781 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9684 22:18:20.347196 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9685 22:18:20.353174 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9686 22:18:20.356952 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9687 22:18:20.363062 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9688 22:18:20.366581 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9689 22:18:20.373071 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9690 22:18:20.376151 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9691 22:18:20.382856 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9692 22:18:20.386061 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9693 22:18:20.389770 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9694 22:18:20.395852 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9695 22:18:20.399414 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9696 22:18:20.406309 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9697 22:18:20.409285 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9698 22:18:20.416114 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9699 22:18:20.419323 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9700 22:18:20.422513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9701 22:18:20.428818 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9702 22:18:20.432300 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9703 22:18:20.439064 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9704 22:18:20.441997 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9705 22:18:20.449003 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9706 22:18:20.452426 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9707 22:18:20.455409 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9708 22:18:20.458892 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9709 22:18:20.465848 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9710 22:18:20.468877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9711 22:18:20.472047 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9712 22:18:20.475894 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9713 22:18:20.482109 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9714 22:18:20.485205 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9715 22:18:20.492092 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9716 22:18:20.495102 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9717 22:18:20.498746 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9718 22:18:20.505216 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9719 22:18:20.508354 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9720 22:18:20.514606 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9721 22:18:20.518271 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9722 22:18:20.521490 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9723 22:18:20.528197 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9724 22:18:20.531755 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9725 22:18:20.534601 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9726 22:18:20.541188 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9727 22:18:20.544893 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9728 22:18:20.550961 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9729 22:18:20.554279 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9730 22:18:20.557740 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9731 22:18:20.564119 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9732 22:18:20.567629 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9733 22:18:20.571112 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9734 22:18:20.577490 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9735 22:18:20.580777 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9736 22:18:20.584208 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9737 22:18:20.590624 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9738 22:18:20.594081 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9739 22:18:20.600616 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9740 22:18:20.603794 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9741 22:18:20.607241 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9742 22:18:20.613792 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9743 22:18:20.616819 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9744 22:18:20.623894 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9745 22:18:20.626776 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9746 22:18:20.629875 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9747 22:18:20.633493 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9748 22:18:20.639916 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9749 22:18:20.643330 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9750 22:18:20.646231 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9751 22:18:20.649981 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9752 22:18:20.656787 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9753 22:18:20.659783 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9754 22:18:20.663371 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9755 22:18:20.666444 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9756 22:18:20.672977 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9757 22:18:20.676199 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9758 22:18:20.679812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9759 22:18:20.685898 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9760 22:18:20.689633 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9761 22:18:20.692607 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9762 22:18:20.699642 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9763 22:18:20.702657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9764 22:18:20.708947 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9765 22:18:20.712361 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9766 22:18:20.718978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9767 22:18:20.722107 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9768 22:18:20.725809 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9769 22:18:20.731983 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9770 22:18:20.735683 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9771 22:18:20.742319 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9772 22:18:20.745227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9773 22:18:20.751779 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9774 22:18:20.755485 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9775 22:18:20.758524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9776 22:18:20.765255 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9777 22:18:20.768237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9778 22:18:20.775123 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9779 22:18:20.778478 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9780 22:18:20.781968 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9781 22:18:20.788367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9782 22:18:20.791380 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9783 22:18:20.798114 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9784 22:18:20.801598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9785 22:18:20.804606 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9786 22:18:20.810994 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9787 22:18:20.814449 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9788 22:18:20.820802 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9789 22:18:20.824584 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9790 22:18:20.831237 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9791 22:18:20.834334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9792 22:18:20.837587 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9793 22:18:20.844332 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9794 22:18:20.847387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9795 22:18:20.853699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9796 22:18:20.857173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9797 22:18:20.863889 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9798 22:18:20.866960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9799 22:18:20.870074 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9800 22:18:20.876826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9801 22:18:20.880356 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9802 22:18:20.886555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9803 22:18:20.890068 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9804 22:18:20.896991 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9805 22:18:20.900110 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9806 22:18:20.903415 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9807 22:18:20.909660 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9808 22:18:20.913234 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9809 22:18:20.919848 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9810 22:18:20.923105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9811 22:18:20.926453 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9812 22:18:20.932567 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9813 22:18:20.935714 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9814 22:18:20.942556 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9815 22:18:20.945708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9816 22:18:20.952546 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9817 22:18:20.955859 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9818 22:18:20.958753 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9819 22:18:20.966080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9820 22:18:20.968869 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9821 22:18:20.975668 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9822 22:18:20.978722 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9823 22:18:20.981871 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9824 22:18:20.988377 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9825 22:18:20.991750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9826 22:18:20.998200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9827 22:18:21.001629 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9828 22:18:21.008400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9829 22:18:21.011742 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9830 22:18:21.017790 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9831 22:18:21.021453 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9832 22:18:21.024385 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9833 22:18:21.031388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9834 22:18:21.034566 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9835 22:18:21.041225 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9836 22:18:21.044279 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9837 22:18:21.051231 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9838 22:18:21.054284 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9839 22:18:21.057325 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9840 22:18:21.064391 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9841 22:18:21.067335 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9842 22:18:21.073774 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9843 22:18:21.077439 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9844 22:18:21.083728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9845 22:18:21.087350 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9846 22:18:21.093998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9847 22:18:21.096862 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9848 22:18:21.100525 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9849 22:18:21.107107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9850 22:18:21.109966 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9851 22:18:21.116886 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9852 22:18:21.120321 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9853 22:18:21.126522 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9854 22:18:21.130258 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9855 22:18:21.136721 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9856 22:18:21.139600 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9857 22:18:21.146665 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9858 22:18:21.149786 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9859 22:18:21.152930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9860 22:18:21.159726 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9861 22:18:21.162791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9862 22:18:21.169378 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9863 22:18:21.172746 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9864 22:18:21.179059 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9865 22:18:21.182684 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9866 22:18:21.188935 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9867 22:18:21.192627 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9868 22:18:21.195631 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9869 22:18:21.202295 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9870 22:18:21.205691 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9871 22:18:21.212031 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9872 22:18:21.215454 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9873 22:18:21.221930 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9874 22:18:21.225296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9875 22:18:21.232065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9876 22:18:21.235165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9877 22:18:21.241902 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9878 22:18:21.245259 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9879 22:18:21.248419 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9880 22:18:21.255202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9881 22:18:21.258173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9882 22:18:21.264858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9883 22:18:21.267967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9884 22:18:21.275049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9885 22:18:21.278241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9886 22:18:21.284531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9887 22:18:21.288192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9888 22:18:21.294984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9889 22:18:21.297795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9890 22:18:21.304578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9891 22:18:21.307583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9892 22:18:21.311160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9893 22:18:21.317655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9894 22:18:21.321027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9895 22:18:21.327875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9896 22:18:21.330652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9897 22:18:21.337179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9898 22:18:21.340898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9899 22:18:21.347596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9900 22:18:21.350623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9901 22:18:21.357187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9902 22:18:21.360353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9903 22:18:21.367096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9904 22:18:21.370695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9905 22:18:21.376850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9906 22:18:21.383776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9907 22:18:21.386689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9908 22:18:21.393188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9909 22:18:21.397022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9910 22:18:21.403200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9911 22:18:21.406359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9912 22:18:21.410139 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9913 22:18:21.413189 INFO: [APUAPC] vio 0
9914 22:18:21.419672 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9915 22:18:21.423191 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9916 22:18:21.426328 INFO: [APUAPC] D0_APC_0: 0x400510
9917 22:18:21.429698 INFO: [APUAPC] D0_APC_1: 0x0
9918 22:18:21.432980 INFO: [APUAPC] D0_APC_2: 0x1540
9919 22:18:21.436289 INFO: [APUAPC] D0_APC_3: 0x0
9920 22:18:21.439717 INFO: [APUAPC] D1_APC_0: 0xffffffff
9921 22:18:21.442848 INFO: [APUAPC] D1_APC_1: 0xffffffff
9922 22:18:21.446050 INFO: [APUAPC] D1_APC_2: 0x3fffff
9923 22:18:21.449531 INFO: [APUAPC] D1_APC_3: 0x0
9924 22:18:21.452504 INFO: [APUAPC] D2_APC_0: 0xffffffff
9925 22:18:21.456204 INFO: [APUAPC] D2_APC_1: 0xffffffff
9926 22:18:21.459113 INFO: [APUAPC] D2_APC_2: 0x3fffff
9927 22:18:21.459210 INFO: [APUAPC] D2_APC_3: 0x0
9928 22:18:21.465730 INFO: [APUAPC] D3_APC_0: 0xffffffff
9929 22:18:21.469606 INFO: [APUAPC] D3_APC_1: 0xffffffff
9930 22:18:21.472450 INFO: [APUAPC] D3_APC_2: 0x3fffff
9931 22:18:21.472550 INFO: [APUAPC] D3_APC_3: 0x0
9932 22:18:21.475588 INFO: [APUAPC] D4_APC_0: 0xffffffff
9933 22:18:21.479273 INFO: [APUAPC] D4_APC_1: 0xffffffff
9934 22:18:21.482551 INFO: [APUAPC] D4_APC_2: 0x3fffff
9935 22:18:21.485558 INFO: [APUAPC] D4_APC_3: 0x0
9936 22:18:21.488894 INFO: [APUAPC] D5_APC_0: 0xffffffff
9937 22:18:21.492545 INFO: [APUAPC] D5_APC_1: 0xffffffff
9938 22:18:21.495561 INFO: [APUAPC] D5_APC_2: 0x3fffff
9939 22:18:21.499164 INFO: [APUAPC] D5_APC_3: 0x0
9940 22:18:21.502287 INFO: [APUAPC] D6_APC_0: 0xffffffff
9941 22:18:21.505281 INFO: [APUAPC] D6_APC_1: 0xffffffff
9942 22:18:21.508833 INFO: [APUAPC] D6_APC_2: 0x3fffff
9943 22:18:21.511931 INFO: [APUAPC] D6_APC_3: 0x0
9944 22:18:21.515555 INFO: [APUAPC] D7_APC_0: 0xffffffff
9945 22:18:21.518630 INFO: [APUAPC] D7_APC_1: 0xffffffff
9946 22:18:21.522177 INFO: [APUAPC] D7_APC_2: 0x3fffff
9947 22:18:21.525056 INFO: [APUAPC] D7_APC_3: 0x0
9948 22:18:21.528781 INFO: [APUAPC] D8_APC_0: 0xffffffff
9949 22:18:21.531857 INFO: [APUAPC] D8_APC_1: 0xffffffff
9950 22:18:21.535069 INFO: [APUAPC] D8_APC_2: 0x3fffff
9951 22:18:21.538504 INFO: [APUAPC] D8_APC_3: 0x0
9952 22:18:21.541920 INFO: [APUAPC] D9_APC_0: 0xffffffff
9953 22:18:21.544953 INFO: [APUAPC] D9_APC_1: 0xffffffff
9954 22:18:21.548289 INFO: [APUAPC] D9_APC_2: 0x3fffff
9955 22:18:21.551453 INFO: [APUAPC] D9_APC_3: 0x0
9956 22:18:21.555016 INFO: [APUAPC] D10_APC_0: 0xffffffff
9957 22:18:21.558022 INFO: [APUAPC] D10_APC_1: 0xffffffff
9958 22:18:21.561668 INFO: [APUAPC] D10_APC_2: 0x3fffff
9959 22:18:21.564852 INFO: [APUAPC] D10_APC_3: 0x0
9960 22:18:21.568209 INFO: [APUAPC] D11_APC_0: 0xffffffff
9961 22:18:21.571254 INFO: [APUAPC] D11_APC_1: 0xffffffff
9962 22:18:21.574994 INFO: [APUAPC] D11_APC_2: 0x3fffff
9963 22:18:21.577956 INFO: [APUAPC] D11_APC_3: 0x0
9964 22:18:21.581652 INFO: [APUAPC] D12_APC_0: 0xffffffff
9965 22:18:21.584718 INFO: [APUAPC] D12_APC_1: 0xffffffff
9966 22:18:21.588275 INFO: [APUAPC] D12_APC_2: 0x3fffff
9967 22:18:21.591371 INFO: [APUAPC] D12_APC_3: 0x0
9968 22:18:21.594815 INFO: [APUAPC] D13_APC_0: 0xffffffff
9969 22:18:21.597723 INFO: [APUAPC] D13_APC_1: 0xffffffff
9970 22:18:21.601155 INFO: [APUAPC] D13_APC_2: 0x3fffff
9971 22:18:21.604798 INFO: [APUAPC] D13_APC_3: 0x0
9972 22:18:21.607812 INFO: [APUAPC] D14_APC_0: 0xffffffff
9973 22:18:21.611371 INFO: [APUAPC] D14_APC_1: 0xffffffff
9974 22:18:21.614407 INFO: [APUAPC] D14_APC_2: 0x3fffff
9975 22:18:21.617513 INFO: [APUAPC] D14_APC_3: 0x0
9976 22:18:21.621155 INFO: [APUAPC] D15_APC_0: 0xffffffff
9977 22:18:21.624276 INFO: [APUAPC] D15_APC_1: 0xffffffff
9978 22:18:21.627905 INFO: [APUAPC] D15_APC_2: 0x3fffff
9979 22:18:21.630755 INFO: [APUAPC] D15_APC_3: 0x0
9980 22:18:21.634535 INFO: [APUAPC] APC_CON: 0x4
9981 22:18:21.637295 INFO: [NOCDAPC] D0_APC_0: 0x0
9982 22:18:21.640866 INFO: [NOCDAPC] D0_APC_1: 0x0
9983 22:18:21.643862 INFO: [NOCDAPC] D1_APC_0: 0x0
9984 22:18:21.647454 INFO: [NOCDAPC] D1_APC_1: 0xfff
9985 22:18:21.650874 INFO: [NOCDAPC] D2_APC_0: 0x0
9986 22:18:21.653979 INFO: [NOCDAPC] D2_APC_1: 0xfff
9987 22:18:21.656945 INFO: [NOCDAPC] D3_APC_0: 0x0
9988 22:18:21.660544 INFO: [NOCDAPC] D3_APC_1: 0xfff
9989 22:18:21.660655 INFO: [NOCDAPC] D4_APC_0: 0x0
9990 22:18:21.663579 INFO: [NOCDAPC] D4_APC_1: 0xfff
9991 22:18:21.667278 INFO: [NOCDAPC] D5_APC_0: 0x0
9992 22:18:21.670306 INFO: [NOCDAPC] D5_APC_1: 0xfff
9993 22:18:21.673785 INFO: [NOCDAPC] D6_APC_0: 0x0
9994 22:18:21.676893 INFO: [NOCDAPC] D6_APC_1: 0xfff
9995 22:18:21.680527 INFO: [NOCDAPC] D7_APC_0: 0x0
9996 22:18:21.683681 INFO: [NOCDAPC] D7_APC_1: 0xfff
9997 22:18:21.686647 INFO: [NOCDAPC] D8_APC_0: 0x0
9998 22:18:21.690437 INFO: [NOCDAPC] D8_APC_1: 0xfff
9999 22:18:21.693394 INFO: [NOCDAPC] D9_APC_0: 0x0
10000 22:18:21.693476 INFO: [NOCDAPC] D9_APC_1: 0xfff
10001 22:18:21.696537 INFO: [NOCDAPC] D10_APC_0: 0x0
10002 22:18:21.700266 INFO: [NOCDAPC] D10_APC_1: 0xfff
10003 22:18:21.703191 INFO: [NOCDAPC] D11_APC_0: 0x0
10004 22:18:21.706437 INFO: [NOCDAPC] D11_APC_1: 0xfff
10005 22:18:21.709745 INFO: [NOCDAPC] D12_APC_0: 0x0
10006 22:18:21.713346 INFO: [NOCDAPC] D12_APC_1: 0xfff
10007 22:18:21.716254 INFO: [NOCDAPC] D13_APC_0: 0x0
10008 22:18:21.720011 INFO: [NOCDAPC] D13_APC_1: 0xfff
10009 22:18:21.723190 INFO: [NOCDAPC] D14_APC_0: 0x0
10010 22:18:21.726177 INFO: [NOCDAPC] D14_APC_1: 0xfff
10011 22:18:21.729864 INFO: [NOCDAPC] D15_APC_0: 0x0
10012 22:18:21.732827 INFO: [NOCDAPC] D15_APC_1: 0xfff
10013 22:18:21.736339 INFO: [NOCDAPC] APC_CON: 0x4
10014 22:18:21.739758 INFO: [APUAPC] set_apusys_apc done
10015 22:18:21.742639 INFO: [DEVAPC] devapc_init done
10016 22:18:21.746058 INFO: GICv3 without legacy support detected.
10017 22:18:21.749521 INFO: ARM GICv3 driver initialized in EL3
10018 22:18:21.752927 INFO: Maximum SPI INTID supported: 639
10019 22:18:21.756204 INFO: BL31: Initializing runtime services
10020 22:18:21.762715 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10021 22:18:21.765803 INFO: SPM: enable CPC mode
10022 22:18:21.772635 INFO: mcdi ready for mcusys-off-idle and system suspend
10023 22:18:21.775739 INFO: BL31: Preparing for EL3 exit to normal world
10024 22:18:21.779139 INFO: Entry point address = 0x80000000
10025 22:18:21.782171 INFO: SPSR = 0x8
10026 22:18:21.787236
10027 22:18:21.787317
10028 22:18:21.787381
10029 22:18:21.790257 Starting depthcharge on Spherion...
10030 22:18:21.790339
10031 22:18:21.790402 Wipe memory regions:
10032 22:18:21.790462
10033 22:18:21.791142 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10034 22:18:21.791244 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10035 22:18:21.791324 Setting prompt string to ['asurada:']
10036 22:18:21.791401 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10037 22:18:21.794031 [0x00000040000000, 0x00000054600000)
10038 22:18:21.916142
10039 22:18:21.916273 [0x00000054660000, 0x00000080000000)
10040 22:18:22.176487
10041 22:18:22.176626 [0x000000821a7280, 0x000000ffe64000)
10042 22:18:22.921631
10043 22:18:22.922178 [0x00000100000000, 0x00000240000000)
10044 22:18:24.810259
10045 22:18:24.813081 Initializing XHCI USB controller at 0x11200000.
10046 22:18:25.851119
10047 22:18:25.853878 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10048 22:18:25.853965
10049 22:18:25.854029
10050 22:18:25.854088
10051 22:18:25.854363 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 22:18:25.954739 asurada: tftpboot 192.168.201.1 10597279/tftp-deploy-u74z_xer/kernel/image.itb 10597279/tftp-deploy-u74z_xer/kernel/cmdline
10054 22:18:25.954944 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 22:18:25.955055 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10056 22:18:25.959119 tftpboot 192.168.201.1 10597279/tftp-deploy-u74z_xer/kernel/image.itp-deploy-u74z_xer/kernel/cmdline
10057 22:18:25.959207
10058 22:18:25.959273 Waiting for link
10059 22:18:26.119602
10060 22:18:26.119741 R8152: Initializing
10061 22:18:26.119809
10062 22:18:26.122639 Version 6 (ocp_data = 5c30)
10063 22:18:26.122722
10064 22:18:26.126098 R8152: Done initializing
10065 22:18:26.126181
10066 22:18:26.126246 Adding net device
10067 22:18:28.030392
10068 22:18:28.030533 done.
10069 22:18:28.030600
10070 22:18:28.030662 MAC: 00:24:32:30:78:ff
10071 22:18:28.030722
10072 22:18:28.033374 Sending DHCP discover... done.
10073 22:18:28.033459
10074 22:18:28.037036 Waiting for reply... done.
10075 22:18:28.037121
10076 22:18:28.040270 Sending DHCP request... done.
10077 22:18:28.040355
10078 22:18:28.040421 Waiting for reply... done.
10079 22:18:28.040482
10080 22:18:28.043103 My ip is 192.168.201.21
10081 22:18:28.043186
10082 22:18:28.046681 The DHCP server ip is 192.168.201.1
10083 22:18:28.046765
10084 22:18:28.050183 TFTP server IP predefined by user: 192.168.201.1
10085 22:18:28.050267
10086 22:18:28.056780 Bootfile predefined by user: 10597279/tftp-deploy-u74z_xer/kernel/image.itb
10087 22:18:28.056868
10088 22:18:28.059551 Sending tftp read request... done.
10089 22:18:28.059637
10090 22:18:28.063216 Waiting for the transfer...
10091 22:18:28.063305
10092 22:18:28.598722 00000000 ################################################################
10093 22:18:28.598903
10094 22:18:29.121429 00080000 ################################################################
10095 22:18:29.121583
10096 22:18:29.660708 00100000 ################################################################
10097 22:18:29.660853
10098 22:18:30.202245 00180000 ################################################################
10099 22:18:30.202385
10100 22:18:30.745736 00200000 ################################################################
10101 22:18:30.745908
10102 22:18:31.310292 00280000 ################################################################
10103 22:18:31.310459
10104 22:18:31.862203 00300000 ################################################################
10105 22:18:31.862341
10106 22:18:32.403617 00380000 ################################################################
10107 22:18:32.403792
10108 22:18:32.966039 00400000 ################################################################
10109 22:18:32.966186
10110 22:18:33.526256 00480000 ################################################################
10111 22:18:33.526394
10112 22:18:34.082823 00500000 ################################################################
10113 22:18:34.082993
10114 22:18:34.607336 00580000 ################################################################
10115 22:18:34.607522
10116 22:18:35.131090 00600000 ################################################################
10117 22:18:35.131270
10118 22:18:35.656677 00680000 ################################################################
10119 22:18:35.656826
10120 22:18:36.188381 00700000 ################################################################
10121 22:18:36.188520
10122 22:18:36.734563 00780000 ################################################################
10123 22:18:36.734754
10124 22:18:37.288239 00800000 ################################################################
10125 22:18:37.288393
10126 22:18:37.826502 00880000 ################################################################
10127 22:18:37.826648
10128 22:18:38.375306 00900000 ################################################################
10129 22:18:38.375456
10130 22:18:38.980956 00980000 ################################################################
10131 22:18:38.981088
10132 22:18:39.536487 00a00000 ################################################################
10133 22:18:39.536624
10134 22:18:40.104103 00a80000 ################################################################
10135 22:18:40.104237
10136 22:18:40.656936 00b00000 ################################################################
10137 22:18:40.657105
10138 22:18:41.215782 00b80000 ################################################################
10139 22:18:41.215966
10140 22:18:41.754087 00c00000 ################################################################
10141 22:18:41.754228
10142 22:18:42.322186 00c80000 ################################################################
10143 22:18:42.322338
10144 22:18:42.877216 00d00000 ################################################################
10145 22:18:42.877412
10146 22:18:43.417243 00d80000 ################################################################
10147 22:18:43.417436
10148 22:18:43.972384 00e00000 ################################################################
10149 22:18:43.972575
10150 22:18:44.501016 00e80000 ################################################################
10151 22:18:44.501207
10152 22:18:45.043070 00f00000 ################################################################
10153 22:18:45.043260
10154 22:18:45.570517 00f80000 ################################################################
10155 22:18:45.570711
10156 22:18:46.097536 01000000 ################################################################
10157 22:18:46.097724
10158 22:18:46.626420 01080000 ################################################################
10159 22:18:46.626564
10160 22:18:47.176888 01100000 ################################################################
10161 22:18:47.177030
10162 22:18:47.731037 01180000 ################################################################
10163 22:18:47.731213
10164 22:18:48.250103 01200000 ################################################################
10165 22:18:48.250258
10166 22:18:48.790820 01280000 ################################################################
10167 22:18:48.790988
10168 22:18:49.309377 01300000 ################################################################
10169 22:18:49.309565
10170 22:18:49.845744 01380000 ################################################################
10171 22:18:49.845938
10172 22:18:50.384564 01400000 ################################################################
10173 22:18:50.384746
10174 22:18:50.917535 01480000 ################################################################
10175 22:18:50.917689
10176 22:18:51.458036 01500000 ################################################################
10177 22:18:51.458306
10178 22:18:52.012657 01580000 ################################################################
10179 22:18:52.012965
10180 22:18:52.550752 01600000 ################################################################
10181 22:18:52.550942
10182 22:18:53.105538 01680000 ################################################################
10183 22:18:53.105694
10184 22:18:53.657040 01700000 ################################################################
10185 22:18:53.657201
10186 22:18:54.177803 01780000 ################################################################
10187 22:18:54.177989
10188 22:18:54.700658 01800000 ################################################################
10189 22:18:54.700818
10190 22:18:55.221011 01880000 ################################################################
10191 22:18:55.221196
10192 22:18:55.740808 01900000 ################################################################
10193 22:18:55.740971
10194 22:18:56.258390 01980000 ################################################################
10195 22:18:56.258545
10196 22:18:56.797220 01a00000 ################################################################
10197 22:18:56.797388
10198 22:18:57.318255 01a80000 ################################################################
10199 22:18:57.318447
10200 22:18:57.838033 01b00000 ################################################################
10201 22:18:57.838215
10202 22:18:58.375271 01b80000 ################################################################
10203 22:18:58.375428
10204 22:18:58.914251 01c00000 ################################################################
10205 22:18:58.914418
10206 22:18:59.437447 01c80000 ################################################################
10207 22:18:59.437594
10208 22:18:59.966627 01d00000 ################################################################
10209 22:18:59.966797
10210 22:19:00.491619 01d80000 ################################################################
10211 22:19:00.491760
10212 22:19:01.018331 01e00000 ################################################################
10213 22:19:01.018533
10214 22:19:01.537171 01e80000 ################################################################
10215 22:19:01.537352
10216 22:19:02.060042 01f00000 ################################################################
10217 22:19:02.060241
10218 22:19:02.579715 01f80000 ################################################################
10219 22:19:02.579880
10220 22:19:03.105787 02000000 ################################################################
10221 22:19:03.105940
10222 22:19:03.647693 02080000 ################################################################
10223 22:19:03.647877
10224 22:19:04.195219 02100000 ################################################################
10225 22:19:04.195372
10226 22:19:04.717490 02180000 ################################################################
10227 22:19:04.717678
10228 22:19:05.239970 02200000 ################################################################
10229 22:19:05.240138
10230 22:19:05.778070 02280000 ################################################################
10231 22:19:05.778208
10232 22:19:06.323534 02300000 ################################################################
10233 22:19:06.323715
10234 22:19:06.864401 02380000 ################################################################
10235 22:19:06.864544
10236 22:19:07.406650 02400000 ################################################################
10237 22:19:07.406792
10238 22:19:07.944958 02480000 ################################################################
10239 22:19:07.945096
10240 22:19:08.479285 02500000 ################################################################
10241 22:19:08.479451
10242 22:19:09.018602 02580000 ################################################################
10243 22:19:09.018799
10244 22:19:09.555297 02600000 ################################################################
10245 22:19:09.555482
10246 22:19:10.086840 02680000 ################################################################
10247 22:19:10.086984
10248 22:19:10.619393 02700000 ################################################################
10249 22:19:10.619536
10250 22:19:11.142766 02780000 ################################################################
10251 22:19:11.142921
10252 22:19:11.669315 02800000 ################################################################
10253 22:19:11.669499
10254 22:19:12.199560 02880000 ################################################################
10255 22:19:12.199698
10256 22:19:12.719387 02900000 ################################################################
10257 22:19:12.719551
10258 22:19:13.242596 02980000 ################################################################
10259 22:19:13.242789
10260 22:19:13.764948 02a00000 ################################################################
10261 22:19:13.765125
10262 22:19:14.313631 02a80000 ################################################################
10263 22:19:14.313839
10264 22:19:14.857355 02b00000 ################################################################
10265 22:19:14.857526
10266 22:19:15.384134 02b80000 ################################################################
10267 22:19:15.384305
10268 22:19:15.914648 02c00000 ################################################################
10269 22:19:15.914823
10270 22:19:16.446118 02c80000 ################################################################
10271 22:19:16.446267
10272 22:19:16.981237 02d00000 ################################################################
10273 22:19:16.981369
10274 22:19:17.515573 02d80000 ################################################################
10275 22:19:17.515743
10276 22:19:18.043088 02e00000 ################################################################
10277 22:19:18.043226
10278 22:19:18.575045 02e80000 ################################################################
10279 22:19:18.575214
10280 22:19:19.102267 02f00000 ################################################################
10281 22:19:19.102404
10282 22:19:19.563450 02f80000 ######################################################## done.
10283 22:19:19.566587
10284 22:19:19.569905 The bootfile was 50260506 bytes long.
10285 22:19:19.570010
10286 22:19:19.570099 Sending tftp read request... done.
10287 22:19:19.573060
10288 22:19:19.573149 Waiting for the transfer...
10289 22:19:19.573235
10290 22:19:19.576181 00000000 # done.
10291 22:19:19.576270
10292 22:19:19.582629 Command line loaded dynamically from TFTP file: 10597279/tftp-deploy-u74z_xer/kernel/cmdline
10293 22:19:19.582742
10294 22:19:19.596337 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10295 22:19:19.596441
10296 22:19:19.596529 Loading FIT.
10297 22:19:19.596610
10298 22:19:19.599411 Image ramdisk-1 has 40129244 bytes.
10299 22:19:19.599516
10300 22:19:19.602763 Image fdt-1 has 46924 bytes.
10301 22:19:19.602885
10302 22:19:19.606336 Image kernel-1 has 10082307 bytes.
10303 22:19:19.606448
10304 22:19:19.612489 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10305 22:19:19.612612
10306 22:19:19.632127 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10307 22:19:19.632253
10308 22:19:19.635546 Choosing best match conf-1 for compat google,spherion-rev2.
10309 22:19:19.640687
10310 22:19:19.645049 Connected to device vid:did:rid of 1ae0:0028:00
10311 22:19:19.651994
10312 22:19:19.655561 tpm_get_response: command 0x17b, return code 0x0
10313 22:19:19.655650
10314 22:19:19.658779 ec_init: CrosEC protocol v3 supported (256, 248)
10315 22:19:19.664087
10316 22:19:19.667110 tpm_cleanup: add release locality here.
10317 22:19:19.667199
10318 22:19:19.667285 Shutting down all USB controllers.
10319 22:19:19.670242
10320 22:19:19.670330 Removing current net device
10321 22:19:19.670431
10322 22:19:19.677372 Exiting depthcharge with code 4 at timestamp: 87179132
10323 22:19:19.677484
10324 22:19:19.680513 LZMA decompressing kernel-1 to 0x821a6718
10325 22:19:19.680615
10326 22:19:19.683751 LZMA decompressing kernel-1 to 0x40000000
10327 22:19:20.950912
10328 22:19:20.951073 jumping to kernel
10329 22:19:20.951801 end: 2.2.4 bootloader-commands (duration 00:00:59) [common]
10330 22:19:20.951935 start: 2.2.5 auto-login-action (timeout 00:03:26) [common]
10331 22:19:20.952023 Setting prompt string to ['Linux version [0-9]']
10332 22:19:20.952133 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10333 22:19:20.952240 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10334 22:19:21.033862
10335 22:19:21.036681 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10336 22:19:21.040020 start: 2.2.5.1 login-action (timeout 00:03:26) [common]
10337 22:19:21.040156 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10338 22:19:21.040287 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10339 22:19:21.040407 Using line separator: #'\n'#
10340 22:19:21.040508 No login prompt set.
10341 22:19:21.040613 Parsing kernel messages
10342 22:19:21.040709 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10343 22:19:21.040904 [login-action] Waiting for messages, (timeout 00:03:26)
10344 22:19:21.059747 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10345 22:19:21.062914 [ 0.000000] random: crng init done
10346 22:19:21.069740 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10347 22:19:21.072971 [ 0.000000] efi: UEFI not found.
10348 22:19:21.079429 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10349 22:19:21.085943 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10350 22:19:21.095867 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10351 22:19:21.106010 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10352 22:19:21.112407 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10353 22:19:21.119076 [ 0.000000] printk: bootconsole [mtk8250] enabled
10354 22:19:21.125623 [ 0.000000] NUMA: No NUMA configuration found
10355 22:19:21.132386 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10356 22:19:21.135580 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcca00-0x23efcefff]
10357 22:19:21.138617 [ 0.000000] Zone ranges:
10358 22:19:21.145339 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10359 22:19:21.148452 [ 0.000000] DMA32 empty
10360 22:19:21.155440 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10361 22:19:21.158504 [ 0.000000] Movable zone start for each node
10362 22:19:21.162017 [ 0.000000] Early memory node ranges
10363 22:19:21.168925 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10364 22:19:21.174772 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10365 22:19:21.181685 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10366 22:19:21.188092 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10367 22:19:21.194459 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10368 22:19:21.201193 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10369 22:19:21.256682 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10370 22:19:21.263468 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10371 22:19:21.270242 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10372 22:19:21.273613 [ 0.000000] psci: probing for conduit method from DT.
10373 22:19:21.279990 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10374 22:19:21.283199 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10375 22:19:21.289476 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10376 22:19:21.293297 [ 0.000000] psci: SMC Calling Convention v1.2
10377 22:19:21.299901 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10378 22:19:21.303085 [ 0.000000] Detected VIPT I-cache on CPU0
10379 22:19:21.309714 [ 0.000000] CPU features: detected: GIC system register CPU interface
10380 22:19:21.316215 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10381 22:19:21.322529 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10382 22:19:21.329540 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10383 22:19:21.339429 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10384 22:19:21.345791 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10385 22:19:21.348995 [ 0.000000] alternatives: applying boot alternatives
10386 22:19:21.355803 [ 0.000000] Fallback order for Node 0: 0
10387 22:19:21.362394 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10388 22:19:21.365485 [ 0.000000] Policy zone: Normal
10389 22:19:21.378445 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10390 22:19:21.388408 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10391 22:19:21.398939 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10392 22:19:21.409080 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10393 22:19:21.415407 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10394 22:19:21.418667 <6>[ 0.000000] software IO TLB: area num 8.
10395 22:19:21.476021 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10396 22:19:21.625346 <6>[ 0.000000] Memory: 7933748K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419020K reserved, 32768K cma-reserved)
10397 22:19:21.631862 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10398 22:19:21.638019 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10399 22:19:21.641359 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10400 22:19:21.648415 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10401 22:19:21.654734 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10402 22:19:21.661527 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10403 22:19:21.667856 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10404 22:19:21.674220 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10405 22:19:21.681229 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10406 22:19:21.687540 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10407 22:19:21.691093 <6>[ 0.000000] GICv3: 608 SPIs implemented
10408 22:19:21.694016 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10409 22:19:21.701107 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10410 22:19:21.703909 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10411 22:19:21.710734 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10412 22:19:21.723961 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10413 22:19:21.737169 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10414 22:19:21.743825 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10415 22:19:21.751857 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10416 22:19:21.764796 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10417 22:19:21.771207 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10418 22:19:21.778529 <6>[ 0.009177] Console: colour dummy device 80x25
10419 22:19:21.787989 <6>[ 0.013934] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10420 22:19:21.794684 <6>[ 0.024377] pid_max: default: 32768 minimum: 301
10421 22:19:21.798115 <6>[ 0.029249] LSM: Security Framework initializing
10422 22:19:21.804782 <6>[ 0.034215] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 22:19:21.814609 <6>[ 0.042030] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 22:19:21.824044 <6>[ 0.051517] cblist_init_generic: Setting adjustable number of callback queues.
10425 22:19:21.831264 <6>[ 0.059020] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 22:19:21.834303 <6>[ 0.065397] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 22:19:21.840925 <6>[ 0.071805] rcu: Hierarchical SRCU implementation.
10428 22:19:21.847907 <6>[ 0.076818] rcu: Max phase no-delay instances is 1000.
10429 22:19:21.854349 <6>[ 0.083837] EFI services will not be available.
10430 22:19:21.857394 <6>[ 0.088837] smp: Bringing up secondary CPUs ...
10431 22:19:21.865920 <6>[ 0.093889] Detected VIPT I-cache on CPU1
10432 22:19:21.872290 <6>[ 0.093962] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 22:19:21.878472 <6>[ 0.093993] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 22:19:21.881993 <6>[ 0.094333] Detected VIPT I-cache on CPU2
10435 22:19:21.891627 <6>[ 0.094387] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 22:19:21.898025 <6>[ 0.094403] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 22:19:21.901832 <6>[ 0.094664] Detected VIPT I-cache on CPU3
10438 22:19:21.908171 <6>[ 0.094709] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 22:19:21.914825 <6>[ 0.094723] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 22:19:21.918023 <6>[ 0.095029] CPU features: detected: Spectre-v4
10441 22:19:21.924854 <6>[ 0.095035] CPU features: detected: Spectre-BHB
10442 22:19:21.927910 <6>[ 0.095042] Detected PIPT I-cache on CPU4
10443 22:19:21.934326 <6>[ 0.095099] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 22:19:21.944321 <6>[ 0.095115] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 22:19:21.947806 <6>[ 0.095409] Detected PIPT I-cache on CPU5
10446 22:19:21.954163 <6>[ 0.095471] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 22:19:21.960477 <6>[ 0.095487] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 22:19:21.963733 <6>[ 0.095769] Detected PIPT I-cache on CPU6
10449 22:19:21.973786 <6>[ 0.095834] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 22:19:21.980326 <6>[ 0.095849] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 22:19:21.983928 <6>[ 0.096147] Detected PIPT I-cache on CPU7
10452 22:19:21.990010 <6>[ 0.096212] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 22:19:21.997044 <6>[ 0.096228] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 22:19:22.003002 <6>[ 0.096274] smp: Brought up 1 node, 8 CPUs
10455 22:19:22.006643 <6>[ 0.237561] SMP: Total of 8 processors activated.
10456 22:19:22.013015 <6>[ 0.242512] CPU features: detected: 32-bit EL0 Support
10457 22:19:22.019797 <6>[ 0.247876] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 22:19:22.026295 <6>[ 0.256676] CPU features: detected: Common not Private translations
10459 22:19:22.033137 <6>[ 0.263151] CPU features: detected: CRC32 instructions
10460 22:19:22.039564 <6>[ 0.268536] CPU features: detected: RCpc load-acquire (LDAPR)
10461 22:19:22.042648 <6>[ 0.274495] CPU features: detected: LSE atomic instructions
10462 22:19:22.049416 <6>[ 0.280277] CPU features: detected: Privileged Access Never
10463 22:19:22.056350 <6>[ 0.286056] CPU features: detected: RAS Extension Support
10464 22:19:22.062803 <6>[ 0.291665] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 22:19:22.066433 <6>[ 0.298887] CPU: All CPU(s) started at EL2
10466 22:19:22.072790 <6>[ 0.303230] alternatives: applying system-wide alternatives
10467 22:19:22.082736 <6>[ 0.313936] devtmpfs: initialized
10468 22:19:22.098717 <6>[ 0.322899] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 22:19:22.104870 <6>[ 0.332863] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10470 22:19:22.111596 <6>[ 0.340872] pinctrl core: initialized pinctrl subsystem
10471 22:19:22.114823 <6>[ 0.347519] DMI not present or invalid.
10472 22:19:22.121534 <6>[ 0.351928] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10473 22:19:22.131261 <6>[ 0.358770] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10474 22:19:22.137946 <6>[ 0.366351] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10475 22:19:22.148176 <6>[ 0.374560] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10476 22:19:22.151340 <6>[ 0.382797] audit: initializing netlink subsys (disabled)
10477 22:19:22.160687 <5>[ 0.388491] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10478 22:19:22.167620 <6>[ 0.389194] thermal_sys: Registered thermal governor 'step_wise'
10479 22:19:22.174278 <6>[ 0.396458] thermal_sys: Registered thermal governor 'power_allocator'
10480 22:19:22.177502 <6>[ 0.402715] cpuidle: using governor menu
10481 22:19:22.183993 <6>[ 0.413676] NET: Registered PF_QIPCRTR protocol family
10482 22:19:22.190324 <6>[ 0.419152] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10483 22:19:22.197037 <6>[ 0.426256] ASID allocator initialised with 32768 entries
10484 22:19:22.200524 <6>[ 0.432824] Serial: AMBA PL011 UART driver
10485 22:19:22.210670 <4>[ 0.441464] Trying to register duplicate clock ID: 134
10486 22:19:22.266251 <6>[ 0.500792] KASLR enabled
10487 22:19:22.281218 <6>[ 0.508544] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10488 22:19:22.287531 <6>[ 0.515558] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10489 22:19:22.293924 <6>[ 0.522047] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10490 22:19:22.300562 <6>[ 0.529050] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10491 22:19:22.307391 <6>[ 0.535537] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10492 22:19:22.313731 <6>[ 0.542545] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10493 22:19:22.320595 <6>[ 0.549030] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10494 22:19:22.327124 <6>[ 0.556037] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10495 22:19:22.330477 <6>[ 0.563518] ACPI: Interpreter disabled.
10496 22:19:22.338759 <6>[ 0.569900] iommu: Default domain type: Translated
10497 22:19:22.345624 <6>[ 0.575063] iommu: DMA domain TLB invalidation policy: strict mode
10498 22:19:22.348914 <5>[ 0.581717] SCSI subsystem initialized
10499 22:19:22.355664 <6>[ 0.585962] usbcore: registered new interface driver usbfs
10500 22:19:22.362178 <6>[ 0.591695] usbcore: registered new interface driver hub
10501 22:19:22.365257 <6>[ 0.597247] usbcore: registered new device driver usb
10502 22:19:22.372161 <6>[ 0.603348] pps_core: LinuxPPS API ver. 1 registered
10503 22:19:22.382138 <6>[ 0.608542] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10504 22:19:22.385474 <6>[ 0.617885] PTP clock support registered
10505 22:19:22.388883 <6>[ 0.622126] EDAC MC: Ver: 3.0.0
10506 22:19:22.396140 <6>[ 0.627290] FPGA manager framework
10507 22:19:22.403049 <6>[ 0.630966] Advanced Linux Sound Architecture Driver Initialized.
10508 22:19:22.406197 <6>[ 0.637735] vgaarb: loaded
10509 22:19:22.412721 <6>[ 0.640900] clocksource: Switched to clocksource arch_sys_counter
10510 22:19:22.416158 <5>[ 0.647352] VFS: Disk quotas dquot_6.6.0
10511 22:19:22.422531 <6>[ 0.651538] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10512 22:19:22.425993 <6>[ 0.658731] pnp: PnP ACPI: disabled
10513 22:19:22.434710 <6>[ 0.665406] NET: Registered PF_INET protocol family
10514 22:19:22.444380 <6>[ 0.670988] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10515 22:19:22.455752 <6>[ 0.683282] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10516 22:19:22.465665 <6>[ 0.692094] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10517 22:19:22.471826 <6>[ 0.700065] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10518 22:19:22.481863 <6>[ 0.708763] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10519 22:19:22.488494 <6>[ 0.718509] TCP: Hash tables configured (established 65536 bind 65536)
10520 22:19:22.495063 <6>[ 0.725366] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 22:19:22.505340 <6>[ 0.732567] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 22:19:22.511573 <6>[ 0.740269] NET: Registered PF_UNIX/PF_LOCAL protocol family
10523 22:19:22.517893 <6>[ 0.746430] RPC: Registered named UNIX socket transport module.
10524 22:19:22.521434 <6>[ 0.752582] RPC: Registered udp transport module.
10525 22:19:22.527915 <6>[ 0.757514] RPC: Registered tcp transport module.
10526 22:19:22.534322 <6>[ 0.762443] RPC: Registered tcp NFSv4.1 backchannel transport module.
10527 22:19:22.537753 <6>[ 0.769109] PCI: CLS 0 bytes, default 64
10528 22:19:22.540962 <6>[ 0.773457] Unpacking initramfs...
10529 22:19:22.561771 <6>[ 0.789619] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10530 22:19:22.571909 <6>[ 0.798254] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10531 22:19:22.575417 <6>[ 0.807081] kvm [1]: IPA Size Limit: 40 bits
10532 22:19:22.581733 <6>[ 0.811606] kvm [1]: GICv3: no GICV resource entry
10533 22:19:22.584863 <6>[ 0.816630] kvm [1]: disabling GICv2 emulation
10534 22:19:22.591391 <6>[ 0.821316] kvm [1]: GIC system register CPU interface enabled
10535 22:19:22.595330 <6>[ 0.827468] kvm [1]: vgic interrupt IRQ18
10536 22:19:22.601217 <6>[ 0.831816] kvm [1]: VHE mode initialized successfully
10537 22:19:22.608264 <5>[ 0.838186] Initialise system trusted keyrings
10538 22:19:22.614517 <6>[ 0.842980] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10539 22:19:22.621832 <6>[ 0.853021] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10540 22:19:22.628536 <5>[ 0.859435] NFS: Registering the id_resolver key type
10541 22:19:22.632155 <5>[ 0.864741] Key type id_resolver registered
10542 22:19:22.638312 <5>[ 0.869157] Key type id_legacy registered
10543 22:19:22.645533 <6>[ 0.873441] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10544 22:19:22.651746 <6>[ 0.880365] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10545 22:19:22.658138 <6>[ 0.888100] 9p: Installing v9fs 9p2000 file system support
10546 22:19:22.695614 <5>[ 0.926598] Key type asymmetric registered
10547 22:19:22.698865 <5>[ 0.930928] Asymmetric key parser 'x509' registered
10548 22:19:22.708532 <6>[ 0.936084] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10549 22:19:22.712365 <6>[ 0.943697] io scheduler mq-deadline registered
10550 22:19:22.715550 <6>[ 0.948464] io scheduler kyber registered
10551 22:19:22.734736 <6>[ 0.965761] EINJ: ACPI disabled.
10552 22:19:22.767258 <4>[ 0.991462] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 22:19:22.776837 <4>[ 1.002083] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 22:19:22.791936 <6>[ 1.023043] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10555 22:19:22.800241 <6>[ 1.031113] printk: console [ttyS0] disabled
10556 22:19:22.828240 <6>[ 1.055760] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10557 22:19:22.834801 <6>[ 1.065239] printk: console [ttyS0] enabled
10558 22:19:22.837694 <6>[ 1.065239] printk: console [ttyS0] enabled
10559 22:19:22.844212 <6>[ 1.074133] printk: bootconsole [mtk8250] disabled
10560 22:19:22.847947 <6>[ 1.074133] printk: bootconsole [mtk8250] disabled
10561 22:19:22.854607 <6>[ 1.085442] SuperH (H)SCI(F) driver initialized
10562 22:19:22.857804 <6>[ 1.090704] msm_serial: driver initialized
10563 22:19:22.872168 <6>[ 1.099605] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10564 22:19:22.881943 <6>[ 1.108153] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10565 22:19:22.888627 <6>[ 1.116696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10566 22:19:22.898445 <6>[ 1.125325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10567 22:19:22.908249 <6>[ 1.134032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10568 22:19:22.914696 <6>[ 1.142752] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10569 22:19:22.924645 <6>[ 1.151294] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10570 22:19:22.931828 <6>[ 1.160102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10571 22:19:22.941046 <6>[ 1.168646] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10572 22:19:22.953010 <6>[ 1.184181] loop: module loaded
10573 22:19:22.959728 <6>[ 1.190151] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10574 22:19:22.982377 <4>[ 1.213523] mtk-pmic-keys: Failed to locate of_node [id: -1]
10575 22:19:22.989122 <6>[ 1.220532] megasas: 07.719.03.00-rc1
10576 22:19:22.999161 <6>[ 1.230403] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10577 22:19:23.005778 <6>[ 1.236300] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10578 22:19:23.021745 <6>[ 1.252241] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10579 22:19:23.079555 <6>[ 1.303791] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10580 22:19:24.197836 <6>[ 2.428786] Freeing initrd memory: 39184K
10581 22:19:24.207855 <6>[ 2.439048] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10582 22:19:24.218704 <6>[ 2.449970] tun: Universal TUN/TAP device driver, 1.6
10583 22:19:24.221931 <6>[ 2.456012] thunder_xcv, ver 1.0
10584 22:19:24.225144 <6>[ 2.459518] thunder_bgx, ver 1.0
10585 22:19:24.228991 <6>[ 2.463014] nicpf, ver 1.0
10586 22:19:24.238980 <6>[ 2.467021] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10587 22:19:24.242778 <6>[ 2.474497] hns3: Copyright (c) 2017 Huawei Corporation.
10588 22:19:24.249237 <6>[ 2.480084] hclge is initializing
10589 22:19:24.252489 <6>[ 2.483665] e1000: Intel(R) PRO/1000 Network Driver
10590 22:19:24.259093 <6>[ 2.488794] e1000: Copyright (c) 1999-2006 Intel Corporation.
10591 22:19:24.262573 <6>[ 2.494810] e1000e: Intel(R) PRO/1000 Network Driver
10592 22:19:24.269296 <6>[ 2.500026] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10593 22:19:24.275423 <6>[ 2.506214] igb: Intel(R) Gigabit Ethernet Network Driver
10594 22:19:24.282287 <6>[ 2.511864] igb: Copyright (c) 2007-2014 Intel Corporation.
10595 22:19:24.288990 <6>[ 2.517700] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10596 22:19:24.295733 <6>[ 2.524218] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10597 22:19:24.299015 <6>[ 2.530678] sky2: driver version 1.30
10598 22:19:24.305396 <6>[ 2.535666] VFIO - User Level meta-driver version: 0.3
10599 22:19:24.312877 <6>[ 2.543913] usbcore: registered new interface driver usb-storage
10600 22:19:24.319355 <6>[ 2.550362] usbcore: registered new device driver onboard-usb-hub
10601 22:19:24.328431 <6>[ 2.559446] mt6397-rtc mt6359-rtc: registered as rtc0
10602 22:19:24.338033 <6>[ 2.564912] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:19:28 UTC (1686003568)
10603 22:19:24.341442 <6>[ 2.574470] i2c_dev: i2c /dev entries driver
10604 22:19:24.358558 <6>[ 2.586147] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10605 22:19:24.365376 <6>[ 2.596357] sdhci: Secure Digital Host Controller Interface driver
10606 22:19:24.371905 <6>[ 2.602795] sdhci: Copyright(c) Pierre Ossman
10607 22:19:24.378335 <6>[ 2.608221] Synopsys Designware Multimedia Card Interface Driver
10608 22:19:24.381282 <6>[ 2.614938] mmc0: CQHCI version 5.10
10609 22:19:24.388233 <6>[ 2.615375] sdhci-pltfm: SDHCI platform and OF driver helper
10610 22:19:24.395736 <6>[ 2.626814] ledtrig-cpu: registered to indicate activity on CPUs
10611 22:19:24.406451 <6>[ 2.634154] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10612 22:19:24.412951 <6>[ 2.641551] usbcore: registered new interface driver usbhid
10613 22:19:24.416052 <6>[ 2.647383] usbhid: USB HID core driver
10614 22:19:24.422333 <6>[ 2.651649] spi_master spi0: will run message pump with realtime priority
10615 22:19:24.468548 <6>[ 2.693334] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10616 22:19:24.488022 <6>[ 2.709043] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10617 22:19:24.491746 <6>[ 2.722679] mmc0: Command Queue Engine enabled
10618 22:19:24.498563 <6>[ 2.724126] cros-ec-spi spi0.0: Chrome EC device registered
10619 22:19:24.504969 <6>[ 2.727416] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10620 22:19:24.508070 <6>[ 2.740731] mmcblk0: mmc0:0001 DA4128 116 GiB
10621 22:19:24.523517 <6>[ 2.751265] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10622 22:19:24.530011 <6>[ 2.751436] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10623 22:19:24.536429 <6>[ 2.762746] NET: Registered PF_PACKET protocol family
10624 22:19:24.539707 <6>[ 2.768606] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10625 22:19:24.546767 <6>[ 2.771923] 9pnet: Installing 9P2000 support
10626 22:19:24.549815 <6>[ 2.777956] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10627 22:19:24.556694 <5>[ 2.781616] Key type dns_resolver registered
10628 22:19:24.563536 <6>[ 2.787552] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10629 22:19:24.566630 <6>[ 2.791907] registered taskstats version 1
10630 22:19:24.569778 <5>[ 2.802235] Loading compiled-in X.509 certificates
10631 22:19:24.604857 <4>[ 2.829134] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 22:19:24.614461 <4>[ 2.839798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 22:19:24.624083 <3>[ 2.852353] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10634 22:19:24.635620 <6>[ 2.867109] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10635 22:19:24.642956 <6>[ 2.873906] xhci-mtk 11200000.usb: xHCI Host Controller
10636 22:19:24.649233 <6>[ 2.879407] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10637 22:19:24.659693 <6>[ 2.887249] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10638 22:19:24.666395 <6>[ 2.896682] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10639 22:19:24.672366 <6>[ 2.902782] xhci-mtk 11200000.usb: xHCI Host Controller
10640 22:19:24.679250 <6>[ 2.908271] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10641 22:19:24.685497 <6>[ 2.915924] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10642 22:19:24.692698 <6>[ 2.923662] hub 1-0:1.0: USB hub found
10643 22:19:24.695820 <6>[ 2.927689] hub 1-0:1.0: 1 port detected
10644 22:19:24.706033 <6>[ 2.932023] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10645 22:19:24.708724 <6>[ 2.940629] hub 2-0:1.0: USB hub found
10646 22:19:24.711926 <6>[ 2.944645] hub 2-0:1.0: 1 port detected
10647 22:19:24.720578 <6>[ 2.951919] mtk-msdc 11f70000.mmc: Got CD GPIO
10648 22:19:24.738175 <6>[ 2.966133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10649 22:19:24.744591 <6>[ 2.974163] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10650 22:19:24.754878 <4>[ 2.982137] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10651 22:19:24.764452 <6>[ 2.991802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10652 22:19:24.771133 <6>[ 2.999884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10653 22:19:24.781070 <6>[ 3.007915] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10654 22:19:24.787783 <6>[ 3.015832] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10655 22:19:24.794398 <6>[ 3.023653] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10656 22:19:24.804330 <6>[ 3.031475] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10657 22:19:24.814371 <6>[ 3.042113] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10658 22:19:24.824352 <6>[ 3.050491] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10659 22:19:24.830777 <6>[ 3.058836] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10660 22:19:24.840595 <6>[ 3.067179] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10661 22:19:24.847011 <6>[ 3.075527] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10662 22:19:24.857314 <6>[ 3.083877] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10663 22:19:24.863640 <6>[ 3.092220] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10664 22:19:24.873668 <6>[ 3.100563] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10665 22:19:24.880284 <6>[ 3.108907] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10666 22:19:24.890002 <6>[ 3.117250] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10667 22:19:24.896491 <6>[ 3.125593] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10668 22:19:24.906655 <6>[ 3.133936] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10669 22:19:24.912945 <6>[ 3.142279] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10670 22:19:24.922881 <6>[ 3.150624] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10671 22:19:24.929499 <6>[ 3.158971] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10672 22:19:24.936833 <6>[ 3.167884] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10673 22:19:24.944188 <6>[ 3.175279] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10674 22:19:24.951107 <6>[ 3.182387] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10675 22:19:24.961387 <6>[ 3.189549] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10676 22:19:24.967840 <6>[ 3.196878] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10677 22:19:24.977848 <6>[ 3.203801] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10678 22:19:24.984676 <6>[ 3.212944] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10679 22:19:24.994289 <6>[ 3.222071] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10680 22:19:25.004481 <6>[ 3.231372] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10681 22:19:25.014185 <6>[ 3.240847] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10682 22:19:25.023769 <6>[ 3.250347] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10683 22:19:25.034147 <6>[ 3.259477] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10684 22:19:25.040845 <6>[ 3.268952] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10685 22:19:25.050676 <6>[ 3.278078] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10686 22:19:25.060220 <6>[ 3.287383] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10687 22:19:25.070375 <6>[ 3.297550] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10688 22:19:25.080622 <6>[ 3.308874] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10689 22:19:25.105214 <6>[ 3.333182] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10690 22:19:25.132663 <6>[ 3.363673] hub 2-1:1.0: USB hub found
10691 22:19:25.135791 <6>[ 3.368074] hub 2-1:1.0: 3 ports detected
10692 22:19:25.256978 <6>[ 3.485171] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10693 22:19:25.411759 <6>[ 3.642913] hub 1-1:1.0: USB hub found
10694 22:19:25.414719 <6>[ 3.647368] hub 1-1:1.0: 4 ports detected
10695 22:19:25.493719 <6>[ 3.721412] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10696 22:19:25.737146 <6>[ 3.965171] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10697 22:19:25.869928 <6>[ 4.101409] hub 1-1.4:1.0: USB hub found
10698 22:19:25.873512 <6>[ 4.106095] hub 1-1.4:1.0: 2 ports detected
10699 22:19:26.169119 <6>[ 4.397175] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10700 22:19:26.360696 <6>[ 4.589174] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10701 22:19:37.365710 <6>[ 15.601720] ALSA device list:
10702 22:19:37.372261 <6>[ 15.604976] No soundcards found.
10703 22:19:37.384886 <6>[ 15.617399] Freeing unused kernel memory: 8384K
10704 22:19:37.387772 <6>[ 15.622329] Run /init as init process
10705 22:19:37.418344 <6>[ 15.651203] NET: Registered PF_INET6 protocol family
10706 22:19:37.425111 <6>[ 15.657527] Segment Routing with IPv6
10707 22:19:37.428511 <6>[ 15.661526] In-situ OAM (IOAM) with IPv6
10708 22:19:37.463352 <30>[ 15.676245] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10709 22:19:37.466529 <30>[ 15.700238] systemd[1]: Detected architecture arm64.
10710 22:19:37.470250
10711 22:19:37.473204 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10712 22:19:37.473314
10713 22:19:37.488551 <30>[ 15.721299] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10714 22:19:37.620927 <30>[ 15.849927] systemd[1]: Queued start job for default target Graphical Interface.
10715 22:19:37.665359 <30>[ 15.898381] systemd[1]: Created slice system-getty.slice.
10716 22:19:37.672109 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10717 22:19:37.688982 <30>[ 15.921788] systemd[1]: Created slice system-modprobe.slice.
10718 22:19:37.695513 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10719 22:19:37.713814 <30>[ 15.946323] systemd[1]: Created slice system-serial\x2dgetty.slice.
10720 22:19:37.723740 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10721 22:19:37.736963 <30>[ 15.969643] systemd[1]: Created slice User and Session Slice.
10722 22:19:37.743521 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10723 22:19:37.763978 <30>[ 15.993404] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10724 22:19:37.773847 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10725 22:19:37.787833 <30>[ 16.017313] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10726 22:19:37.794489 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10727 22:19:37.815471 <30>[ 16.041250] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10728 22:19:37.821796 <30>[ 16.053264] systemd[1]: Reached target Local Encrypted Volumes.
10729 22:19:37.828480 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10730 22:19:37.844620 <30>[ 16.077274] systemd[1]: Reached target Paths.
10731 22:19:37.847604 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10732 22:19:37.864822 <30>[ 16.097217] systemd[1]: Reached target Remote File Systems.
10733 22:19:37.871105 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10734 22:19:37.884476 <30>[ 16.117198] systemd[1]: Reached target Slices.
10735 22:19:37.887824 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10736 22:19:37.904422 <30>[ 16.137219] systemd[1]: Reached target Swap.
10737 22:19:37.907590 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10738 22:19:37.927789 <30>[ 16.157403] systemd[1]: Listening on initctl Compatibility Named Pipe.
10739 22:19:37.934442 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10740 22:19:37.941435 <30>[ 16.172081] systemd[1]: Listening on Journal Audit Socket.
10741 22:19:37.947516 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10742 22:19:37.960446 <30>[ 16.193461] systemd[1]: Listening on Journal Socket (/dev/log).
10743 22:19:37.967730 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10744 22:19:37.985383 <30>[ 16.217961] systemd[1]: Listening on Journal Socket.
10745 22:19:37.991636 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10746 22:19:38.008323 <30>[ 16.237596] systemd[1]: Listening on Network Service Netlink Socket.
10747 22:19:38.014849 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10748 22:19:38.029349 <30>[ 16.261961] systemd[1]: Listening on udev Control Socket.
10749 22:19:38.035795 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10750 22:19:38.053415 <30>[ 16.285887] systemd[1]: Listening on udev Kernel Socket.
10751 22:19:38.059615 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10752 22:19:38.092940 <30>[ 16.325300] systemd[1]: Mounting Huge Pages File System...
10753 22:19:38.098959 Mounting [0;1;39mHuge Pages File System[0m...
10754 22:19:38.114610 <30>[ 16.347360] systemd[1]: Mounting POSIX Message Queue File System...
10755 22:19:38.121340 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10756 22:19:38.138388 <30>[ 16.371289] systemd[1]: Mounting Kernel Debug File System...
10757 22:19:38.145021 Mounting [0;1;39mKernel Debug File System[0m...
10758 22:19:38.164101 <30>[ 16.393522] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10759 22:19:38.175210 <30>[ 16.404473] systemd[1]: Starting Create list of static device nodes for the current kernel...
10760 22:19:38.181496 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10761 22:19:38.216834 <30>[ 16.449692] systemd[1]: Starting Load Kernel Module configfs...
10762 22:19:38.223252 Starting [0;1;39mLoad Kernel Module configfs[0m...
10763 22:19:38.238970 <30>[ 16.471640] systemd[1]: Starting Load Kernel Module drm...
10764 22:19:38.245268 Starting [0;1;39mLoad Kernel Module drm[0m...
10765 22:19:38.264495 <30>[ 16.493394] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10766 22:19:38.274685 <30>[ 16.507085] systemd[1]: Starting Journal Service...
10767 22:19:38.277766 Starting [0;1;39mJournal Service[0m...
10768 22:19:38.294586 <30>[ 16.527606] systemd[1]: Starting Load Kernel Modules...
10769 22:19:38.301212 Starting [0;1;39mLoad Kernel Modules[0m...
10770 22:19:38.322405 <30>[ 16.551994] systemd[1]: Starting Remount Root and Kernel File Systems...
10771 22:19:38.329220 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10772 22:19:38.346817 <30>[ 16.579605] systemd[1]: Starting Coldplug All udev Devices...
10773 22:19:38.353127 Starting [0;1;39mColdplug All udev Devices[0m...
10774 22:19:38.371367 <30>[ 16.603960] systemd[1]: Mounted Huge Pages File System.
10775 22:19:38.377658 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10776 22:19:38.393092 <30>[ 16.625815] systemd[1]: Started Journal Service.
10777 22:19:38.399315 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10778 22:19:38.414349 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10779 22:19:38.429253 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10780 22:19:38.449386 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10781 22:19:38.466475 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10782 22:19:38.482324 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10783 22:19:38.497796 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10784 22:19:38.517170 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10785 22:19:38.532945 See 'systemctl status systemd-remount-fs.service' for details.
10786 22:19:38.576751 Mounting [0;1;39mKernel Configuration File System[0m...
10787 22:19:38.599245 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10788 22:19:38.617210 <46>[ 16.846433] systemd-journald[173]: Received client request to flush runtime journal.
10789 22:19:38.625312 Starting [0;1;39mLoad/Save Random Seed[0m...
10790 22:19:38.643510 Starting [0;1;39mApply Kernel Variables[0m...
10791 22:19:38.659601 Starting [0;1;39mCreate System Users[0m...
10792 22:19:38.680665 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10793 22:19:38.701122 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10794 22:19:38.713646 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10795 22:19:38.729526 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10796 22:19:38.745411 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10797 22:19:38.762014 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10798 22:19:38.801757 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10799 22:19:38.824413 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10800 22:19:38.837292 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10801 22:19:38.852526 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10802 22:19:38.892874 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10803 22:19:38.916376 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10804 22:19:38.937298 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10805 22:19:38.956718 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10806 22:19:39.033881 Starting [0;1;39mNetwork Service[0m...
10807 22:19:39.055896 Starting [0;1;39mNetwork Time Synchronization[0m...
10808 22:19:39.069764 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10809 22:19:39.095106 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10810 22:19:39.120740 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10811 22:19:39.139154 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10812 22:19:39.153975 <6>[ 17.383543] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10813 22:19:39.169539 [[0;32m OK [0m] Finished [0<3>[ 17.396673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10814 22:19:39.175623 ;1;39mLoad/Save <6>[ 17.400322] remoteproc remoteproc0: scp is available
10815 22:19:39.186034 Screen …s of l<3>[ 17.406477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 22:19:39.192526 eds:white:kbd_ba<6>[ 17.414417] remoteproc remoteproc0: powering up scp
10817 22:19:39.192691 cklight[0m.
10818 22:19:39.198714 <3>[ 17.422479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 22:19:39.208741 <6>[ 17.428874] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10820 22:19:39.215167 <6>[ 17.433663] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10821 22:19:39.225247 <3>[ 17.442367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 22:19:39.231697 <6>[ 17.447251] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10823 22:19:39.235313 <6>[ 17.447368] mc: Linux media interface: v0.10
10824 22:19:39.241946 <4>[ 17.449085] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10825 22:19:39.248918 <4>[ 17.449352] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10826 22:19:39.258772 <3>[ 17.454278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 22:19:39.265706 <3>[ 17.454291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10828 22:19:39.273399 <6>[ 17.455170] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10829 22:19:39.283330 <6>[ 17.455196] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10830 22:19:39.289888 <6>[ 17.455207] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10831 22:19:39.300479 <4>[ 17.458579] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10832 22:19:39.304146 <4>[ 17.458579] Fallback method does not support PEC.
10833 22:19:39.310378 <6>[ 17.475927] videodev: Linux video capture interface: v2.00
10834 22:19:39.320964 <3>[ 17.476222] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 22:19:39.327255 <3>[ 17.479939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10836 22:19:39.337358 <3>[ 17.508446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 22:19:39.343768 <3>[ 17.510980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 22:19:39.353538 <3>[ 17.511114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 22:19:39.357342 <6>[ 17.530345] usbcore: registered new interface driver r8152
10840 22:19:39.367896 <3>[ 17.534581] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10841 22:19:39.374443 <3>[ 17.544565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 22:19:39.384404 <6>[ 17.555833] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10843 22:19:39.390940 <3>[ 17.557030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 22:19:39.400869 <3>[ 17.557044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 22:19:39.407426 <3>[ 17.557203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 22:19:39.417464 <3>[ 17.565515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 22:19:39.427375 <3>[ 17.574032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10848 22:19:39.434031 <3>[ 17.574046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 22:19:39.440427 <6>[ 17.574528] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10850 22:19:39.447421 <6>[ 17.574539] pci_bus 0000:00: root bus resource [bus 00-ff]
10851 22:19:39.453734 <6>[ 17.574548] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10852 22:19:39.463671 <6>[ 17.574554] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10853 22:19:39.469840 <6>[ 17.574608] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10854 22:19:39.476533 <6>[ 17.574639] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10855 22:19:39.483174 <6>[ 17.574747] pci 0000:00:00.0: supports D1 D2
10856 22:19:39.490186 <6>[ 17.574756] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10857 22:19:39.496261 <6>[ 17.576670] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10858 22:19:39.502754 <6>[ 17.576847] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10859 22:19:39.509590 <6>[ 17.576879] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10860 22:19:39.519536 <6>[ 17.576960] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10861 22:19:39.526512 <6>[ 17.576980] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10862 22:19:39.529517 <6>[ 17.577107] pci 0000:01:00.0: supports D1 D2
10863 22:19:39.536230 <6>[ 17.577111] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10864 22:19:39.546270 <6>[ 17.587850] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10865 22:19:39.552591 <6>[ 17.587851] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10866 22:19:39.559496 <6>[ 17.589057] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10867 22:19:39.569381 <6>[ 17.589132] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10868 22:19:39.576212 <6>[ 17.589141] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10869 22:19:39.582957 <6>[ 17.589157] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10870 22:19:39.590169 <6>[ 17.589175] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10871 22:19:39.600115 <6>[ 17.589191] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10872 22:19:39.603537 <6>[ 17.589209] pci 0000:00:00.0: PCI bridge to [bus 01]
10873 22:19:39.613384 <6>[ 17.589223] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10874 22:19:39.620132 <6>[ 17.589591] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10875 22:19:39.627006 <3>[ 17.590638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 22:19:39.633350 <6>[ 17.596484] remoteproc remoteproc0: remote processor scp is now up
10877 22:19:39.639899 <6>[ 17.599527] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10878 22:19:39.646852 <6>[ 17.601701] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10879 22:19:39.653308 <3>[ 17.604668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 22:19:39.663859 <3>[ 17.605327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 22:19:39.673457 <6>[ 17.605431] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10882 22:19:39.680447 <6>[ 17.605872] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10883 22:19:39.690195 <6>[ 17.634349] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10884 22:19:39.697427 <3>[ 17.638538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 22:19:39.703796 <6>[ 17.639902] usbcore: registered new interface driver cdc_ether
10886 22:19:39.710693 <6>[ 17.656384] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10887 22:19:39.717502 <6>[ 17.656779] usbcore: registered new interface driver r8153_ecm
10888 22:19:39.727209 <5>[ 17.658089] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10889 22:19:39.730362 <6>[ 17.665103] Bluetooth: Core ver 2.22
10890 22:19:39.737301 <5>[ 17.670001] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10891 22:19:39.746892 <4>[ 17.670082] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10892 22:19:39.750554 <6>[ 17.670090] cfg80211: failed to load regulatory.db
10893 22:19:39.756733 <6>[ 17.675031] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10894 22:19:39.767225 <6>[ 17.677670] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10895 22:19:39.769842 <6>[ 17.678670] NET: Registered PF_BLUETOOTH protocol family
10896 22:19:39.783362 <6>[ 17.685837] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10897 22:19:39.790293 <6>[ 17.691400] Bluetooth: HCI device and connection manager initialized
10898 22:19:39.796324 <6>[ 17.693837] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10899 22:19:39.802851 <6>[ 17.701823] usbcore: registered new interface driver uvcvideo
10900 22:19:39.806548 <6>[ 17.707636] Bluetooth: HCI socket layer initialized
10901 22:19:39.816389 <4>[ 17.710655] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10902 22:19:39.826204 <4>[ 17.710665] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10903 22:19:39.829623 <6>[ 17.757467] r8152 2-1.3:1.0 eth0: v1.12.13
10904 22:19:39.836552 <6>[ 17.763516] Bluetooth: L2CAP socket layer initialized
10905 22:19:39.842776 <6>[ 17.767891] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10906 22:19:39.849655 <6>[ 17.767994] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10907 22:19:39.852823 <6>[ 17.774903] Bluetooth: SCO socket layer initialized
10908 22:19:39.860145 <6>[ 17.780504] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10909 22:19:39.863913 <6>[ 17.801040] mt7921e 0000:01:00.0: ASIC revision: 79610010
10910 22:19:39.873194 <3>[ 17.825907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 22:19:39.880906 <3>[ 17.826925] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10912 22:19:39.890697 <3>[ 17.835982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 22:19:39.897590 <6>[ 17.851761] usbcore: registered new interface driver btusb
10914 22:19:39.907734 <4>[ 17.871934] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10915 22:19:39.914739 <3>[ 17.896426] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 22:19:39.921489 <3>[ 17.900688] Bluetooth: hci0: Failed to load firmware file (-2)
10917 22:19:39.934001 <4>[ 17.925602] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10918 22:19:39.940640 <3>[ 17.927352] Bluetooth: hci0: Failed to set up firmware (-2)
10919 22:19:39.947493 <3>[ 17.944064] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 22:19:39.957315 <4>[ 17.949975] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10921 22:19:39.970211 <4>[ 18.047257] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10922 22:19:39.977050 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10923 22:19:40.005339 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10924 22:19:40.038295 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10925 22:19:40.088755 <4>[ 18.315436] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10926 22:19:40.208800 [[0;32m OK [<4>[ 18.435078] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10927 22:19:40.211849 0m] Reached target [0;1;39mBluetooth[0m.
10928 22:19:40.232603 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10929 22:19:40.251565 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10930 22:19:40.268377 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10931 22:19:40.284267 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10932 22:19:40.308121 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10933 22:19:40.329150 <4>[ 18.555278] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 22:19:40.335306 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10935 22:19:40.356449 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10936 22:19:40.372317 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10937 22:19:40.388450 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10938 22:19:40.408150 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10939 22:19:40.448844 <4>[ 18.675409] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10940 22:19:40.467179 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10941 22:19:40.495160 Starting [0;1;39mUser Login Management[0m...
10942 22:19:40.511860 Starting [0;1;39mNetwork Name Resolution[0m...
10943 22:19:40.531879 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10944 22:19:40.552875 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10945 22:19:40.572010 <4>[ 18.798554] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10946 22:19:40.600709 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10947 22:19:40.624155 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10948 22:19:40.641083 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10949 22:19:40.659790 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10950 22:19:40.696911 <4>[ 18.923319] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 22:19:40.715669 Starting [0;1;39mPermit User Sessions[0m...
10952 22:19:40.734009 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10953 22:19:40.743789 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10954 22:19:40.763692 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10955 22:19:40.770111 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10956 22:19:40.784408 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10957 22:19:40.802651 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10958 22:19:40.817712 <4>[ 19.044441] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10959 22:19:40.860630 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10960 22:19:40.885530 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10961 22:19:40.902712
10962 22:19:40.902887
10963 22:19:40.906121 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10964 22:19:40.906211
10965 22:19:40.908939 debian-bullseye-arm64 login: root (automatic login)
10966 22:19:40.909027
10967 22:19:40.909095
10968 22:19:40.932226 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
10969 22:19:40.932346
10970 22:19:40.942101 The pr<4>[ 19.169021] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10971 22:19:40.948642 ograms included with the Debian GNU/Linux system are free software;
10972 22:19:40.955276 the exact distribution terms for each program are described in the
10973 22:19:40.958449 individual files in /usr/share/doc/*/copyright.
10974 22:19:40.958552
10975 22:19:40.965273 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10976 22:19:40.968201 permitted by applicable law.
10977 22:19:40.968555 Matched prompt #10: / #
10979 22:19:40.968784 Setting prompt string to ['/ #']
10980 22:19:40.968888 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10982 22:19:40.969112 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10983 22:19:40.969207 start: 2.2.6 expect-shell-connection (timeout 00:03:06) [common]
10984 22:19:40.969324 Setting prompt string to ['/ #']
10985 22:19:40.969399 Forcing a shell prompt, looking for ['/ #']
10987 22:19:41.019599 / #
10988 22:19:41.019762 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10989 22:19:41.019852 Waiting using forced prompt support (timeout 00:02:30)
10990 22:19:41.024296
10991 22:19:41.024610 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10992 22:19:41.024736 start: 2.2.7 export-device-env (timeout 00:03:06) [common]
10993 22:19:41.024870 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10994 22:19:41.024987 end: 2.2 depthcharge-retry (duration 00:01:54) [common]
10995 22:19:41.025111 end: 2 depthcharge-action (duration 00:01:54) [common]
10996 22:19:41.025227 start: 3 lava-test-retry (timeout 00:07:46) [common]
10997 22:19:41.025386 start: 3.1 lava-test-shell (timeout 00:07:46) [common]
10998 22:19:41.025485 Using namespace: common
11000 22:19:41.125834 / # #
11001 22:19:41.126012 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11002 22:19:41.126168 <3>[ 19.293487] mt7921e 0000:01:00.0: hardware init failed
11003 22:19:41.130494 #
11004 22:19:41.130786 Using /lava-10597279
11006 22:19:41.231181 / # export SHELL=/bin/sh
11007 22:19:41.240938 export SHELL=/bin/sh<6>[ 19.470624] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11008 22:19:41.241059
11009 22:19:41.247607 <6>[ 19.478778] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11011 22:19:41.348095 / # . /lava-10597279/environment
11012 22:19:41.353147 . /lava-10597279/environment
11014 22:19:41.453649 / # /lava-10597279/bin/lava-test-runner /lava-10597279/0
11015 22:19:41.453813 Test shell timeout: 10s (minimum of the action and connection timeout)
11016 22:19:41.458264 /lava-10597279/bin/lava-test-runner /lava-10597279/0
11017 22:19:41.480934 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11018 22:19:41.487571 + cd /lava-10597279/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11019 22:19:41.487667 + cat uuid
11020 22:19:41.491272 + UUID=10597279_1.5.2.3.1
11021 22:19:41.491360 + set +x
11022 22:19:41.497527 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10597279_1.5.2.3.1>
11023 22:19:41.497778 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10597279_1.5.2.3.1
11024 22:19:41.497854 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10597279_1.5.2.3.1)
11025 22:19:41.497949 Skipping test definition patterns.
11026 22:19:41.500541 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11027 22:19:41.507210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11028 22:19:41.507468 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11030 22:19:41.514148 d<4>[ 19.743992] use of bytesused == 0 is deprecated and will be removed in the future,
11031 22:19:41.520291 evice: /dev/vide<4>[ 19.752568] use the actual size instead.
11032 22:19:41.520408 o2
11033 22:19:41.527225 <4>[ 19.759719] ------------[ cut here ]------------
11034 22:19:41.534087 <4>[ 19.764605] get_vaddr_frames() cannot follow VM_IO mapping
11035 22:19:41.543673 <4>[ 19.764767] WARNING: CPU: 1 PID: 306 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11036 22:19:41.593310 <4>[ 19.782912] Modules linked in: btusb btintel btmtk btrtl btbcm mt7921e mt7921_common mt76_connac_lib mt76 mtk_vcodec_enc mac80211 mtk_vcodec_common libarc4 mtk_vpu uvcvideo v4l2_mem2mem cfg80211 videobuf2_vmalloc videobuf2_dma_contig r8153_ecm bluetooth cros_ec_rpmsg videobuf2_memops cdc_ether usbnet videobuf2_v4l2 ecdh_generic crct10dif_ce r8152 videobuf2_common cros_ec_chardev elan_i2c pcie_mediatek_gen3 videodev ecc mc elants_i2c rfkill sbs_battery cros_ec_typec hid_google_hammer hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11037 22:19:41.599613 <4>[ 19.832296] CPU: 1 PID: 306 Comm: v4l2-compliance Not tainted 6.1.31 #1
11038 22:19:41.606411 <4>[ 19.839160] Hardware name: Google Spherion (rev0 - 3) (DT)
11039 22:19:41.613172 <4>[ 19.844896] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11040 22:19:41.619258 <4>[ 19.852107] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11041 22:19:41.625869 <4>[ 19.858198] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11042 22:19:41.629604 <4>[ 19.864289] sp : ffff80000909b850
11043 22:19:41.635838 <4>[ 19.867852] x29: ffff80000909b850 x28: ffffbdc55da17000 x27: ffffbdc55da13238
11044 22:19:41.645822 <4>[ 19.875239] x26: 0000000000000000 x25: ffffbdc5812db3b8 x24: ffff0d484e5a1298
11045 22:19:41.652557 <4>[ 19.882626] x23: ffff0d48408cac00 x22: ffff0d4840d48010 x21: 0000000000000000
11046 22:19:41.659355 <4>[ 19.890014] x20: 00000000fffffff2 x19: ffff0d484e0ab400 x18: fffffffffffe95b0
11047 22:19:41.665536 <4>[ 19.897400] x17: 0000000000000000 x16: ffffbdc57f48bb60 x15: 0000000000000038
11048 22:19:41.675999 <4>[ 19.904787] x14: ffffbdc581bc34a8 x13: 000000000000063c x12: 0000000000000214
11049 22:19:41.682173 <4>[ 19.912173] x11: fffffffffffe95b0 x10: fffffffffffe9578 x9 : 00000000fffff214
11050 22:19:41.688954 <4>[ 19.919560] x8 : ffffbdc581bc34a8 x7 : ffffbdc581c1b4a8 x6 : 00000000000018f0
11051 22:19:41.695415 <4>[ 19.926946] x5 : ffff0d497ef26a18 x4 : 00000000fffff214 x3 : ffff4f83fda23000
11052 22:19:41.701962 <4>[ 19.934332] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0d4849fa49c0
11053 22:19:41.705534 <4>[ 19.941719] Call trace:
11054 22:19:41.711783 <4>[ 19.944414] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11055 22:19:41.718441 <4>[ 19.950159] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11056 22:19:41.725329 <4>[ 19.956161] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11057 22:19:41.731964 <4>[ 19.962513] __prepare_userptr+0x280/0x410 [videobuf2_common]
11058 22:19:41.734927 <4>[ 19.968516] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11059 22:19:41.741768 <4>[ 19.974172] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11060 22:19:41.748506 <4>[ 19.980349] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11061 22:19:41.754814 <4>[ 19.985850] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11062 22:19:41.758259 <4>[ 19.991624] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11063 22:19:41.764755 <4>[ 19.997889] v4l_prepare_buf+0x48/0x60 [videodev]
11064 22:19:41.771559 <4>[ 20.002917] __video_do_ioctl+0x184/0x3d0 [videodev]
11065 22:19:41.775067 <4>[ 20.008161] video_usercopy+0x358/0x680 [videodev]
11066 22:19:41.778421 <4>[ 20.013232] video_ioctl2+0x18/0x30 [videodev]
11067 22:19:41.784776 <4>[ 20.017955] v4l2_ioctl+0x40/0x60 [videodev]
11068 22:19:41.788451 <4>[ 20.022505] __arm64_sys_ioctl+0xa8/0xf0
11069 22:19:41.791872 <4>[ 20.026686] invoke_syscall+0x48/0x114
11070 22:19:41.798159 <4>[ 20.030692] el0_svc_common.constprop.0+0x44/0xec
11071 22:19:41.801044 <4>[ 20.035647] do_el0_svc+0x2c/0xd0
11072 22:19:41.804986 <4>[ 20.039213] el0_svc+0x2c/0x84
11073 22:19:41.807781 <4>[ 20.042523] el0t_64_sync_handler+0xb8/0xc0
11074 22:19:41.811390 <4>[ 20.046957] el0t_64_sync+0x18c/0x190
11075 22:19:41.818126 <4>[ 20.050871] ---[ end trace 0000000000000000 ]---
11076 22:19:41.831126 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11077 22:19:41.840868 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11078 22:19:41.845889
11079 22:19:41.858772 Compliance test for mtk-vcodec-enc device /dev/video2:
11080 22:19:41.865709
11081 22:19:41.875087 Driver Info:
11082 22:19:41.885122 Driver name : mtk-vcodec-enc
11083 22:19:41.897295 Card type : MT8192 video encoder
11084 22:19:41.907005 Bus info : platform:17020000.vcodec
11085 22:19:41.912893 Driver version : 6.1.31
11086 22:19:41.922763 Capabilities : 0x84204000
11087 22:19:41.932081 Video Memory-to-Memory Multiplanar
11088 22:19:41.941182 Streaming
11089 22:19:41.949797 Extended Pix Format
11090 22:19:41.958965 Device Capabilities
11091 22:19:41.968928 Device Caps : 0x04204000
11092 22:19:41.978974 Video Memory-to-Memory Multiplanar
11093 22:19:41.988244 Streaming
11094 22:19:41.997635 Extended Pix Format
11095 22:19:42.007445 Detected Stateful Encoder
11096 22:19:42.017723
11097 22:19:42.028689 Required ioctls:
11098 22:19:42.043427 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11099 22:19:42.043516 test VIDIOC_QUERYCAP: OK
11100 22:19:42.043836 Received signal: <TESTSET> START Required-ioctls
11101 22:19:42.043939 Starting test_set Required-ioctls
11102 22:19:42.066185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11103 22:19:42.066457 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11105 22:19:42.069226 test invalid ioctls: OK
11106 22:19:42.090809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11107 22:19:42.090927
11108 22:19:42.091163 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11110 22:19:42.100107 Allow for multiple opens:
11111 22:19:42.107657 <LAVA_SIGNAL_TESTSET STOP>
11112 22:19:42.107943 Received signal: <TESTSET> STOP
11113 22:19:42.108017 Closing test_set Required-ioctls
11114 22:19:42.116954 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11115 22:19:42.117208 Received signal: <TESTSET> START Allow-for-multiple-opens
11116 22:19:42.117278 Starting test_set Allow-for-multiple-opens
11117 22:19:42.119973 test second /dev/video2 open: OK
11118 22:19:42.141437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11119 22:19:42.141706 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11121 22:19:42.144432 test VIDIOC_QUERYCAP: OK
11122 22:19:42.163761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11123 22:19:42.164030 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11125 22:19:42.166759 test VIDIOC_G/S_PRIORITY: OK
11126 22:19:42.186206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11127 22:19:42.186473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11129 22:19:42.189169 test for unlimited opens: OK
11130 22:19:42.209661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11131 22:19:42.209765
11132 22:19:42.210037 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11134 22:19:42.219628 Debug ioctls:
11135 22:19:42.226767 <LAVA_SIGNAL_TESTSET STOP>
11136 22:19:42.227070 Received signal: <TESTSET> STOP
11137 22:19:42.227167 Closing test_set Allow-for-multiple-opens
11138 22:19:42.236161 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11139 22:19:42.236430 Received signal: <TESTSET> START Debug-ioctls
11140 22:19:42.236517 Starting test_set Debug-ioctls
11141 22:19:42.239034 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11142 22:19:42.258874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11143 22:19:42.259153 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11145 22:19:42.265099 test VIDIOC_LOG_STATUS: OK (Not Supported)
11146 22:19:42.282229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11147 22:19:42.282368
11148 22:19:42.282638 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11150 22:19:42.291978 Input ioctls:
11151 22:19:42.298594 <LAVA_SIGNAL_TESTSET STOP>
11152 22:19:42.298858 Received signal: <TESTSET> STOP
11153 22:19:42.298934 Closing test_set Debug-ioctls
11154 22:19:42.307147 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11155 22:19:42.307439 Received signal: <TESTSET> START Input-ioctls
11156 22:19:42.307517 Starting test_set Input-ioctls
11157 22:19:42.310579 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11158 22:19:42.334261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11159 22:19:42.334531 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11161 22:19:42.337362 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11162 22:19:42.353536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11163 22:19:42.353795 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11165 22:19:42.360316 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11166 22:19:42.378190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11167 22:19:42.378459 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11169 22:19:42.384961 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11170 22:19:42.403137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11171 22:19:42.403407 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11173 22:19:42.406109 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11174 22:19:42.427068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11175 22:19:42.427350 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11177 22:19:42.430396 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11178 22:19:42.450996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11179 22:19:42.451249 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11181 22:19:42.454211 Inputs: 0 Audio Inputs: 0 Tuners: 0
11182 22:19:42.461569
11183 22:19:42.478263 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11184 22:19:42.498553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11185 22:19:42.498822 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11187 22:19:42.505402 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11188 22:19:42.522387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11189 22:19:42.522664 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11191 22:19:42.528751 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11192 22:19:42.546345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11193 22:19:42.546604 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11195 22:19:42.552855 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11196 22:19:42.570066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11197 22:19:42.570339 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11199 22:19:42.576313 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11200 22:19:42.594600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11201 22:19:42.594697
11202 22:19:42.594970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11204 22:19:42.613453 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11205 22:19:42.634748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11206 22:19:42.635027 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11208 22:19:42.641265 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11209 22:19:42.661724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11210 22:19:42.662040 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11212 22:19:42.664790 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11213 22:19:42.683344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11214 22:19:42.683652 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11216 22:19:42.686341 test VIDIOC_G/S_EDID: OK (Not Supported)
11217 22:19:42.706280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11218 22:19:42.706371
11219 22:19:42.706608 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11221 22:19:42.717051 Control ioctls:
11222 22:19:42.723881 <LAVA_SIGNAL_TESTSET STOP>
11223 22:19:42.724142 Received signal: <TESTSET> STOP
11224 22:19:42.724213 Closing test_set Input-ioctls
11225 22:19:42.732335 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11226 22:19:42.732590 Received signal: <TESTSET> START Control-ioctls
11227 22:19:42.732663 Starting test_set Control-ioctls
11228 22:19:42.735643 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11229 22:19:42.759442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11230 22:19:42.759566 test VIDIOC_QUERYCTRL: OK
11231 22:19:42.759842 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11233 22:19:42.781317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11234 22:19:42.781605 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11236 22:19:42.784044 test VIDIOC_G/S_CTRL: OK
11237 22:19:42.804532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11238 22:19:42.804824 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11240 22:19:42.807832 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11241 22:19:42.829494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11242 22:19:42.829784 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11244 22:19:42.839168 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11245 22:19:42.842363 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11246 22:19:42.865916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11247 22:19:42.866196 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11249 22:19:42.869012 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11250 22:19:42.885635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11251 22:19:42.885921 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11253 22:19:42.889191 Standard Controls: 16 Private Controls: 0
11254 22:19:42.895776
11255 22:19:42.912652 Format ioctls:
11256 22:19:42.920626 <LAVA_SIGNAL_TESTSET STOP>
11257 22:19:42.920895 Received signal: <TESTSET> STOP
11258 22:19:42.921011 Closing test_set Control-ioctls
11259 22:19:42.930568 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11260 22:19:42.930847 Received signal: <TESTSET> START Format-ioctls
11261 22:19:42.930938 Starting test_set Format-ioctls
11262 22:19:42.933655 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11263 22:19:42.962042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11264 22:19:42.962305 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11266 22:19:42.965024 test VIDIOC_G/S_PARM: OK
11267 22:19:42.981576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11268 22:19:42.981842 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11270 22:19:42.985272 test VIDIOC_G_FBUF: OK (Not Supported)
11271 22:19:43.004254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11272 22:19:43.004518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11274 22:19:43.007352 test VIDIOC_G_FMT: OK
11275 22:19:43.029893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11276 22:19:43.030195 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11278 22:19:43.033320 test VIDIOC_TRY_FMT: OK
11279 22:19:43.057536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11280 22:19:43.057796 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11282 22:19:43.067480 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11283 22:19:43.067568 test VIDIOC_S_FMT: FAIL
11284 22:19:43.090159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11285 22:19:43.090426 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11287 22:19:43.093602 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11288 22:19:43.114116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11289 22:19:43.114417 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11291 22:19:43.117607 test Cropping: OK
11292 22:19:43.137714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11293 22:19:43.137975 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11295 22:19:43.140861 test Composing: OK (Not Supported)
11296 22:19:43.161392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11297 22:19:43.161653 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11299 22:19:43.164894 test Scaling: OK (Not Supported)
11300 22:19:43.185917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11301 22:19:43.186019
11302 22:19:43.186257 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11304 22:19:43.195333 Codec ioctls:
11305 22:19:43.201207 <LAVA_SIGNAL_TESTSET STOP>
11306 22:19:43.201505 Received signal: <TESTSET> STOP
11307 22:19:43.201605 Closing test_set Format-ioctls
11308 22:19:43.210429 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11309 22:19:43.210728 Received signal: <TESTSET> START Codec-ioctls
11310 22:19:43.210825 Starting test_set Codec-ioctls
11311 22:19:43.213933 test VIDIOC_(TRY_)ENCODER_CMD: OK
11312 22:19:43.232890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11313 22:19:43.233153 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11315 22:19:43.239441 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11316 22:19:43.255332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11317 22:19:43.255626 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11319 22:19:43.262196 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11320 22:19:43.280016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11321 22:19:43.280123
11322 22:19:43.280401 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11324 22:19:43.290803 Buffer ioctls:
11325 22:19:43.298087 <LAVA_SIGNAL_TESTSET STOP>
11326 22:19:43.298356 Received signal: <TESTSET> STOP
11327 22:19:43.298437 Closing test_set Codec-ioctls
11328 22:19:43.307488 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11329 22:19:43.307743 Received signal: <TESTSET> START Buffer-ioctls
11330 22:19:43.307853 Starting test_set Buffer-ioctls
11331 22:19:43.310694 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11332 22:19:43.333290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11333 22:19:43.333430 test VIDIOC_EXPBUF: OK
11334 22:19:43.333690 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11336 22:19:43.353926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11337 22:19:43.354189 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11339 22:19:43.356870 test Requests: OK (Not Supported)
11340 22:19:43.377913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11341 22:19:43.378016
11342 22:19:43.378256 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11344 22:19:43.387468 Test input 0:
11345 22:19:43.397189
11346 22:19:43.407505 Streaming ioctls:
11347 22:19:43.413211 <LAVA_SIGNAL_TESTSET STOP>
11348 22:19:43.413476 Received signal: <TESTSET> STOP
11349 22:19:43.413555 Closing test_set Buffer-ioctls
11350 22:19:43.422279 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11351 22:19:43.422534 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11352 22:19:43.422613 Starting test_set Streaming-ioctls_Test-input-0
11353 22:19:43.425850 test read/write: OK (Not Supported)
11354 22:19:43.445918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11355 22:19:43.446178 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11357 22:19:43.452102 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11358 22:19:43.463054 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11359 22:19:43.467345 test blocking wait: FAIL
11360 22:19:43.490684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11361 22:19:43.490985 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11363 22:19:43.500453 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11364 22:19:43.500565 test MMAP (select): FAIL
11365 22:19:43.523622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11366 22:19:43.523918 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11368 22:19:43.529520 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11369 22:19:43.534071 test MMAP (epoll): FAIL
11370 22:19:43.558334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11371 22:19:43.558630 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11373 22:19:43.568871 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11374 22:19:43.574771 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11375 22:19:43.577941 test USERPTR (select): FAIL
11376 22:19:43.601038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11377 22:19:43.601297 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11379 22:19:43.607437 test DMABUF: Cannot test, specify --expbuf-device
11380 22:19:43.611383
11381 22:19:43.628534 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11382 22:19:43.631438 <LAVA_TEST_RUNNER EXIT>
11383 22:19:43.631694 ok: lava_test_shell seems to have completed
11384 22:19:43.631772 Marking unfinished test run as failed
11386 22:19:43.633573 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11387 22:19:43.633731 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11388 22:19:43.633858 end: 3 lava-test-retry (duration 00:00:03) [common]
11389 22:19:43.633979 start: 4 finalize (timeout 00:07:44) [common]
11390 22:19:43.634108 start: 4.1 power-off (timeout 00:00:30) [common]
11391 22:19:43.634397 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11392 22:19:43.711580 >> Command sent successfully.
11393 22:19:43.714684 Returned 0 in 0 seconds
11394 22:19:43.815098 end: 4.1 power-off (duration 00:00:00) [common]
11396 22:19:43.815433 start: 4.2 read-feedback (timeout 00:07:44) [common]
11397 22:19:43.815738 Listened to connection for namespace 'common' for up to 1s
11398 22:19:44.816645 Finalising connection for namespace 'common'
11399 22:19:44.816823 Disconnecting from shell: Finalise
11400 22:19:44.816912 / #
11401 22:19:44.917227 end: 4.2 read-feedback (duration 00:00:01) [common]
11402 22:19:44.917452 end: 4 finalize (duration 00:00:01) [common]
11403 22:19:44.917625 Cleaning after the job
11404 22:19:44.917758 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/ramdisk
11405 22:19:44.922258 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/kernel
11406 22:19:44.928342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/dtb
11407 22:19:44.928555 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597279/tftp-deploy-u74z_xer/modules
11408 22:19:44.934497 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597279
11409 22:19:44.995011 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597279
11410 22:19:44.995188 Job finished correctly