Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 70
1 22:19:23.915097 lava-dispatcher, installed at version: 2023.05.1
2 22:19:23.915309 start: 0 validate
3 22:19:23.915440 Start time: 2023-06-05 22:19:23.915433+00:00 (UTC)
4 22:19:23.915569 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:19:23.915702 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:19:24.232698 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:19:24.232879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:19:24.525115 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:19:24.525297 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:19:24.837836 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:19:24.838016 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1314-g1ab0ac1d7e2e3%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:19:25.144011 validate duration: 1.23
14 22:19:25.144279 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:19:25.144377 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:19:25.144474 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:19:25.144641 Not decompressing ramdisk as can be used compressed.
18 22:19:25.144733 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 22:19:25.144798 saving as /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/ramdisk/rootfs.cpio.gz
20 22:19:25.144858 total size: 27151647 (25MB)
21 22:19:25.145913 progress 0% (0MB)
22 22:19:25.153046 progress 5% (1MB)
23 22:19:25.159972 progress 10% (2MB)
24 22:19:25.167095 progress 15% (3MB)
25 22:19:25.174053 progress 20% (5MB)
26 22:19:25.181124 progress 25% (6MB)
27 22:19:25.187995 progress 30% (7MB)
28 22:19:25.195072 progress 35% (9MB)
29 22:19:25.202004 progress 40% (10MB)
30 22:19:25.208962 progress 45% (11MB)
31 22:19:25.216040 progress 50% (12MB)
32 22:19:25.223002 progress 55% (14MB)
33 22:19:25.230166 progress 60% (15MB)
34 22:19:25.237269 progress 65% (16MB)
35 22:19:25.244390 progress 70% (18MB)
36 22:19:25.251484 progress 75% (19MB)
37 22:19:25.258421 progress 80% (20MB)
38 22:19:25.265533 progress 85% (22MB)
39 22:19:25.272347 progress 90% (23MB)
40 22:19:25.279351 progress 95% (24MB)
41 22:19:25.286134 progress 100% (25MB)
42 22:19:25.286329 25MB downloaded in 0.14s (183.04MB/s)
43 22:19:25.286493 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:19:25.286744 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:19:25.286831 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:19:25.286921 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:19:25.287057 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:19:25.287129 saving as /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/kernel/Image
50 22:19:25.287198 total size: 45746688 (43MB)
51 22:19:25.287259 No compression specified
52 22:19:25.288381 progress 0% (0MB)
53 22:19:25.300086 progress 5% (2MB)
54 22:19:25.311915 progress 10% (4MB)
55 22:19:25.323777 progress 15% (6MB)
56 22:19:25.335745 progress 20% (8MB)
57 22:19:25.347636 progress 25% (10MB)
58 22:19:25.359399 progress 30% (13MB)
59 22:19:25.371181 progress 35% (15MB)
60 22:19:25.383051 progress 40% (17MB)
61 22:19:25.394808 progress 45% (19MB)
62 22:19:25.406559 progress 50% (21MB)
63 22:19:25.418213 progress 55% (24MB)
64 22:19:25.430185 progress 60% (26MB)
65 22:19:25.442129 progress 65% (28MB)
66 22:19:25.454051 progress 70% (30MB)
67 22:19:25.465926 progress 75% (32MB)
68 22:19:25.477552 progress 80% (34MB)
69 22:19:25.489409 progress 85% (37MB)
70 22:19:25.501241 progress 90% (39MB)
71 22:19:25.512948 progress 95% (41MB)
72 22:19:25.524640 progress 100% (43MB)
73 22:19:25.524763 43MB downloaded in 0.24s (183.65MB/s)
74 22:19:25.524914 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:19:25.525151 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:19:25.525237 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:19:25.525329 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:19:25.525470 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:19:25.525553 saving as /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/dtb/mt8192-asurada-spherion-r0.dtb
81 22:19:25.525616 total size: 46924 (0MB)
82 22:19:25.525676 No compression specified
83 22:19:25.526798 progress 69% (0MB)
84 22:19:25.527070 progress 100% (0MB)
85 22:19:25.527225 0MB downloaded in 0.00s (27.87MB/s)
86 22:19:25.527352 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:19:25.527580 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:19:25.527664 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:19:25.527746 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:19:25.527863 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1314-g1ab0ac1d7e2e3/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:19:25.527932 saving as /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/modules/modules.tar
93 22:19:25.527992 total size: 8543056 (8MB)
94 22:19:25.528060 Using unxz to decompress xz
95 22:19:25.531649 progress 0% (0MB)
96 22:19:25.553140 progress 5% (0MB)
97 22:19:25.578477 progress 10% (0MB)
98 22:19:25.603903 progress 15% (1MB)
99 22:19:25.628636 progress 20% (1MB)
100 22:19:25.651949 progress 25% (2MB)
101 22:19:25.678392 progress 30% (2MB)
102 22:19:25.703980 progress 35% (2MB)
103 22:19:25.728041 progress 40% (3MB)
104 22:19:25.751961 progress 45% (3MB)
105 22:19:25.776993 progress 50% (4MB)
106 22:19:25.800101 progress 55% (4MB)
107 22:19:25.824312 progress 60% (4MB)
108 22:19:25.849585 progress 65% (5MB)
109 22:19:25.873977 progress 70% (5MB)
110 22:19:25.896952 progress 75% (6MB)
111 22:19:25.920774 progress 80% (6MB)
112 22:19:25.945439 progress 85% (6MB)
113 22:19:25.974171 progress 90% (7MB)
114 22:19:25.999198 progress 95% (7MB)
115 22:19:26.024087 progress 100% (8MB)
116 22:19:26.029965 8MB downloaded in 0.50s (16.23MB/s)
117 22:19:26.030247 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:19:26.030518 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:19:26.030613 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:19:26.030705 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:19:26.030787 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:19:26.030876 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:19:26.031098 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw
125 22:19:26.031228 makedir: /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin
126 22:19:26.031335 makedir: /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/tests
127 22:19:26.031434 makedir: /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/results
128 22:19:26.031548 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-add-keys
129 22:19:26.031694 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-add-sources
130 22:19:26.031826 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-background-process-start
131 22:19:26.031953 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-background-process-stop
132 22:19:26.032076 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-common-functions
133 22:19:26.032195 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-echo-ipv4
134 22:19:26.032318 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-install-packages
135 22:19:26.032437 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-installed-packages
136 22:19:26.032597 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-os-build
137 22:19:26.032718 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-probe-channel
138 22:19:26.032841 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-probe-ip
139 22:19:26.032958 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-target-ip
140 22:19:26.033079 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-target-mac
141 22:19:26.033223 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-target-storage
142 22:19:26.033373 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-case
143 22:19:26.033495 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-event
144 22:19:26.033618 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-feedback
145 22:19:26.033751 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-raise
146 22:19:26.033919 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-reference
147 22:19:26.034088 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-runner
148 22:19:26.034254 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-set
149 22:19:26.034408 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-test-shell
150 22:19:26.034586 Updating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-install-packages (oe)
151 22:19:26.034744 Updating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/bin/lava-installed-packages (oe)
152 22:19:26.034872 Creating /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/environment
153 22:19:26.034986 LAVA metadata
154 22:19:26.035092 - LAVA_JOB_ID=10597286
155 22:19:26.035191 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:19:26.035338 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:19:26.035437 skipped lava-vland-overlay
158 22:19:26.035528 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:19:26.035634 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:19:26.035727 skipped lava-multinode-overlay
161 22:19:26.035841 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:19:26.035967 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:19:26.036085 Loading test definitions
164 22:19:26.036205 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:19:26.036282 Using /lava-10597286 at stage 0
166 22:19:26.036698 uuid=10597286_1.5.2.3.1 testdef=None
167 22:19:26.036824 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:19:26.036952 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:19:26.037598 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:19:26.037856 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:19:26.038608 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:19:26.038888 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:19:26.039802 runner path: /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/0/tests/0_v4l2-compliance-uvc test_uuid 10597286_1.5.2.3.1
176 22:19:26.039991 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:19:26.040316 Creating lava-test-runner.conf files
179 22:19:26.040413 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10597286/lava-overlay-6v_ctjlw/lava-10597286/0 for stage 0
180 22:19:26.040575 - 0_v4l2-compliance-uvc
181 22:19:26.040710 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:19:26.040835 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:19:26.049362 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:19:26.049469 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:19:26.049554 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:19:26.049644 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:19:26.049752 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:19:26.770382 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:19:26.770738 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 22:19:26.770853 extracting modules file /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10597286/extract-overlay-ramdisk-ydom63sq/ramdisk
191 22:19:26.988153 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:19:26.988321 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 22:19:26.988461 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597286/compress-overlay-f4eo02tg/overlay-1.5.2.4.tar.gz to ramdisk
194 22:19:26.988603 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10597286/compress-overlay-f4eo02tg/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10597286/extract-overlay-ramdisk-ydom63sq/ramdisk
195 22:19:26.995249 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:19:26.995362 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 22:19:26.995465 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:19:26.995561 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 22:19:26.995639 Building ramdisk /var/lib/lava/dispatcher/tmp/10597286/extract-overlay-ramdisk-ydom63sq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10597286/extract-overlay-ramdisk-ydom63sq/ramdisk
200 22:19:27.735691 >> 230342 blocks
201 22:19:31.802511 rename /var/lib/lava/dispatcher/tmp/10597286/extract-overlay-ramdisk-ydom63sq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/ramdisk/ramdisk.cpio.gz
202 22:19:31.802927 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:19:31.803052 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 22:19:31.803155 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 22:19:31.803264 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/kernel/Image'
206 22:19:43.558726 Returned 0 in 11 seconds
207 22:19:43.659332 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/kernel/image.itb
208 22:19:44.219639 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:19:44.220092 output: Created: Mon Jun 5 23:19:44 2023
210 22:19:44.220210 output: Image 0 (kernel-1)
211 22:19:44.220292 output: Description:
212 22:19:44.220387 output: Created: Mon Jun 5 23:19:44 2023
213 22:19:44.220476 output: Type: Kernel Image
214 22:19:44.220588 output: Compression: lzma compressed
215 22:19:44.220652 output: Data Size: 10082307 Bytes = 9846.00 KiB = 9.62 MiB
216 22:19:44.220713 output: Architecture: AArch64
217 22:19:44.220772 output: OS: Linux
218 22:19:44.220828 output: Load Address: 0x00000000
219 22:19:44.220886 output: Entry Point: 0x00000000
220 22:19:44.220948 output: Hash algo: crc32
221 22:19:44.221001 output: Hash value: c242daf7
222 22:19:44.221054 output: Image 1 (fdt-1)
223 22:19:44.221122 output: Description: mt8192-asurada-spherion-r0
224 22:19:44.221190 output: Created: Mon Jun 5 23:19:44 2023
225 22:19:44.221245 output: Type: Flat Device Tree
226 22:19:44.221299 output: Compression: uncompressed
227 22:19:44.221356 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 22:19:44.221411 output: Architecture: AArch64
229 22:19:44.221464 output: Hash algo: crc32
230 22:19:44.221535 output: Hash value: 1df858fa
231 22:19:44.221591 output: Image 2 (ramdisk-1)
232 22:19:44.221644 output: Description: unavailable
233 22:19:44.221697 output: Created: Mon Jun 5 23:19:44 2023
234 22:19:44.221749 output: Type: RAMDisk Image
235 22:19:44.221802 output: Compression: Unknown Compression
236 22:19:44.221854 output: Data Size: 40144451 Bytes = 39203.57 KiB = 38.28 MiB
237 22:19:44.221910 output: Architecture: AArch64
238 22:19:44.221964 output: OS: Linux
239 22:19:44.222016 output: Load Address: unavailable
240 22:19:44.222068 output: Entry Point: unavailable
241 22:19:44.222120 output: Hash algo: crc32
242 22:19:44.222174 output: Hash value: 94bd2f03
243 22:19:44.222226 output: Default Configuration: 'conf-1'
244 22:19:44.222279 output: Configuration 0 (conf-1)
245 22:19:44.222333 output: Description: mt8192-asurada-spherion-r0
246 22:19:44.222388 output: Kernel: kernel-1
247 22:19:44.222440 output: Init Ramdisk: ramdisk-1
248 22:19:44.222492 output: FDT: fdt-1
249 22:19:44.222544 output: Loadables: kernel-1
250 22:19:44.222599 output:
251 22:19:44.222795 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 22:19:44.222899 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 22:19:44.223004 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 22:19:44.223097 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 22:19:44.223182 No LXC device requested
256 22:19:44.223261 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:19:44.223350 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 22:19:44.223426 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:19:44.223501 Checking files for TFTP limit of 4294967296 bytes.
260 22:19:44.223995 end: 1 tftp-deploy (duration 00:00:19) [common]
261 22:19:44.224103 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:19:44.224194 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:19:44.224317 substitutions:
264 22:19:44.224385 - {DTB}: 10597286/tftp-deploy-lv8lul9s/dtb/mt8192-asurada-spherion-r0.dtb
265 22:19:44.224448 - {INITRD}: 10597286/tftp-deploy-lv8lul9s/ramdisk/ramdisk.cpio.gz
266 22:19:44.224509 - {KERNEL}: 10597286/tftp-deploy-lv8lul9s/kernel/Image
267 22:19:44.224608 - {LAVA_MAC}: None
268 22:19:44.224665 - {PRESEED_CONFIG}: None
269 22:19:44.224721 - {PRESEED_LOCAL}: None
270 22:19:44.224776 - {RAMDISK}: 10597286/tftp-deploy-lv8lul9s/ramdisk/ramdisk.cpio.gz
271 22:19:44.224833 - {ROOT_PART}: None
272 22:19:44.224887 - {ROOT}: None
273 22:19:44.224943 - {SERVER_IP}: 192.168.201.1
274 22:19:44.224997 - {TEE}: None
275 22:19:44.225051 Parsed boot commands:
276 22:19:44.225108 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:19:44.225297 Parsed boot commands: tftpboot 192.168.201.1 10597286/tftp-deploy-lv8lul9s/kernel/image.itb 10597286/tftp-deploy-lv8lul9s/kernel/cmdline
278 22:19:44.225388 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:19:44.225475 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:19:44.225565 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:19:44.225654 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:19:44.225726 Not connected, no need to disconnect.
283 22:19:44.225798 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:19:44.225873 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:19:44.225939 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
286 22:19:44.229355 Setting prompt string to ['lava-test: # ']
287 22:19:44.229704 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:19:44.229809 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:19:44.229907 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:19:44.230003 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:19:44.230209 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 22:19:49.366110 >> Command sent successfully.
293 22:19:49.368488 Returned 0 in 5 seconds
294 22:19:49.468852 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:19:49.469433 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:19:49.469539 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:19:49.469630 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:19:49.469700 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:19:49.469770 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:19:49.470023 [Enter `^Ec?' for help]
302 22:19:49.641038
303 22:19:49.641194
304 22:19:49.641267 F0: 102B 0000
305 22:19:49.641335
306 22:19:49.641398 F3: 1001 0000 [0200]
307 22:19:49.641456
308 22:19:49.645300 F3: 1001 0000
309 22:19:49.645376
310 22:19:49.645439 F7: 102D 0000
311 22:19:49.645497
312 22:19:49.645554 F1: 0000 0000
313 22:19:49.645612
314 22:19:49.648229 V0: 0000 0000 [0001]
315 22:19:49.648306
316 22:19:49.648367 00: 0007 8000
317 22:19:49.648428
318 22:19:49.651888 01: 0000 0000
319 22:19:49.651961
320 22:19:49.652022 BP: 0C00 0209 [0000]
321 22:19:49.652083
322 22:19:49.655612 G0: 1182 0000
323 22:19:49.655684
324 22:19:49.655749 EC: 0000 0021 [4000]
325 22:19:49.655809
326 22:19:49.659109 S7: 0000 0000 [0000]
327 22:19:49.659181
328 22:19:49.659244 CC: 0000 0000 [0001]
329 22:19:49.659302
330 22:19:49.662239 T0: 0000 0040 [010F]
331 22:19:49.662311
332 22:19:49.662374 Jump to BL
333 22:19:49.662434
334 22:19:49.688029
335 22:19:49.688130
336 22:19:49.688196
337 22:19:49.695341 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:19:49.699136 ARM64: Exception handlers installed.
339 22:19:49.702405 ARM64: Testing exception
340 22:19:49.705855 ARM64: Done test exception
341 22:19:49.712795 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:19:49.723886 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:19:49.727834 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:19:49.739314 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:19:49.746465 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:19:49.753046 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:19:49.764315 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:19:49.770787 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:19:49.790683 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:19:49.794156 WDT: Last reset was cold boot
351 22:19:49.797659 SPI1(PAD0) initialized at 2873684 Hz
352 22:19:49.800922 SPI5(PAD0) initialized at 992727 Hz
353 22:19:49.804038 VBOOT: Loading verstage.
354 22:19:49.810658 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:19:49.814231 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:19:49.817033 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:19:49.820337 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:19:49.827853 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:19:49.835015 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:19:49.845555 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 22:19:49.845639
362 22:19:49.845705
363 22:19:49.855546 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:19:49.858788 ARM64: Exception handlers installed.
365 22:19:49.862423 ARM64: Testing exception
366 22:19:49.862506 ARM64: Done test exception
367 22:19:49.868492 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:19:49.872000 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:19:49.886458 Probing TPM: . done!
370 22:19:49.886544 TPM ready after 0 ms
371 22:19:49.893065 Connected to device vid:did:rid of 1ae0:0028:00
372 22:19:49.903015 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 22:19:49.941483 Initialized TPM device CR50 revision 0
374 22:19:49.953767 tlcl_send_startup: Startup return code is 0
375 22:19:49.953859 TPM: setup succeeded
376 22:19:49.965963 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:19:49.974373 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:19:49.981015 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:19:49.993735 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:19:49.996758 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:19:50.000380 in-header: 03 07 00 00 08 00 00 00
382 22:19:50.004016 in-data: aa e4 47 04 13 02 00 00
383 22:19:50.007168 Chrome EC: UHEPI supported
384 22:19:50.013848 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:19:50.016872 in-header: 03 ad 00 00 08 00 00 00
386 22:19:50.020382 in-data: 00 20 20 08 00 00 00 00
387 22:19:50.020491 Phase 1
388 22:19:50.023873 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:19:50.030401 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:19:50.036692 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:19:50.040422 Recovery requested (1009000e)
392 22:19:50.043989 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:19:50.053418 tlcl_extend: response is 0
394 22:19:50.060694 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:19:50.066453 tlcl_extend: response is 0
396 22:19:50.072401 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:19:50.093369 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:19:50.100247 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:19:50.100333
400 22:19:50.100399
401 22:19:50.110755 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:19:50.114195 ARM64: Exception handlers installed.
403 22:19:50.114278 ARM64: Testing exception
404 22:19:50.117432 ARM64: Done test exception
405 22:19:50.139187 pmic_efuse_setting: Set efuses in 11 msecs
406 22:19:50.142566 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:19:50.146029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:19:50.152986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:19:50.156336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:19:50.163491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:19:50.166645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:19:50.172899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:19:50.176359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:19:50.183074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:19:50.186137 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:19:50.189619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:19:50.196381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:19:50.199932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:19:50.202783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:19:50.210436 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:19:50.216561 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:19:50.223562 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:19:50.226598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:19:50.233252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:19:50.239690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:19:50.246550 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:19:50.249763 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:19:50.257153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:19:50.261026 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:19:50.268150 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:19:50.272079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:19:50.278172 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:19:50.281741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:19:50.288707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:19:50.292411 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:19:50.299253 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:19:50.302817 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:19:50.307637 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:19:50.313950 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:19:50.317602 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:19:50.323838 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:19:50.327120 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:19:50.333907 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:19:50.337749 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:19:50.341379 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:19:50.347813 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:19:50.351715 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:19:50.355255 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:19:50.358551 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:19:50.366040 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:19:50.368967 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:19:50.372098 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:19:50.375231 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:19:50.382071 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:19:50.385132 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:19:50.388851 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:19:50.392062 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:19:50.402044 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:19:50.408451 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:19:50.415476 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:19:50.421688 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:19:50.431705 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:19:50.435286 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:19:50.441709 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:19:50.445076 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:19:50.451983 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
467 22:19:50.457869 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:19:50.461358 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 22:19:50.464535 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:19:50.476458 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 22:19:50.485487 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 22:19:50.495003 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 22:19:50.504349 [RTC]rtc_get_frequency_meter,154: input=13, output=804
474 22:19:50.514431 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 22:19:50.523283 [RTC]rtc_get_frequency_meter,154: input=12, output=787
476 22:19:50.532876 [RTC]rtc_get_frequency_meter,154: input=13, output=804
477 22:19:50.536116 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 22:19:50.543503 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 22:19:50.547089 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:19:50.550325 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:19:50.556491 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:19:50.560210 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:19:50.563226 ADC[4]: Raw value=904139 ID=7
484 22:19:50.563309 ADC[3]: Raw value=213282 ID=1
485 22:19:50.566941 RAM Code: 0x71
486 22:19:50.570034 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:19:50.576440 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:19:50.583354 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:19:50.589988 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:19:50.593337 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:19:50.596794 in-header: 03 07 00 00 08 00 00 00
492 22:19:50.599890 in-data: aa e4 47 04 13 02 00 00
493 22:19:50.603356 Chrome EC: UHEPI supported
494 22:19:50.610066 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:19:50.613324 in-header: 03 dd 00 00 08 00 00 00
496 22:19:50.616410 in-data: 90 20 60 08 00 00 00 00
497 22:19:50.619819 MRC: failed to locate region type 0.
498 22:19:50.626794 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:19:50.629771 DRAM-K: Running full calibration
500 22:19:50.636438 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:19:50.636586 header.status = 0x0
502 22:19:50.639907 header.version = 0x6 (expected: 0x6)
503 22:19:50.643050 header.size = 0xd00 (expected: 0xd00)
504 22:19:50.646636 header.flags = 0x0
505 22:19:50.653145 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:19:50.669885 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 22:19:50.676865 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:19:50.679817 dram_init: ddr_geometry: 2
509 22:19:50.682776 [EMI] MDL number = 2
510 22:19:50.682859 [EMI] Get MDL freq = 0
511 22:19:50.686217 dram_init: ddr_type: 0
512 22:19:50.686300 is_discrete_lpddr4: 1
513 22:19:50.689848 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:19:50.689931
515 22:19:50.689997
516 22:19:50.693075 [Bian_co] ETT version 0.0.0.1
517 22:19:50.699980 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:19:50.700064
519 22:19:50.702583 dramc_set_vcore_voltage set vcore to 650000
520 22:19:50.705893 Read voltage for 800, 4
521 22:19:50.705976 Vio18 = 0
522 22:19:50.706041 Vcore = 650000
523 22:19:50.709629 Vdram = 0
524 22:19:50.709711 Vddq = 0
525 22:19:50.709777 Vmddr = 0
526 22:19:50.712891 dram_init: config_dvfs: 1
527 22:19:50.715953 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:19:50.722927 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:19:50.725848 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 22:19:50.729529 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 22:19:50.732707 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 22:19:50.736033 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 22:19:50.739135 MEM_TYPE=3, freq_sel=18
534 22:19:50.742344 sv_algorithm_assistance_LP4_1600
535 22:19:50.745974 ============ PULL DRAM RESETB DOWN ============
536 22:19:50.752731 ========== PULL DRAM RESETB DOWN end =========
537 22:19:50.756201 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:19:50.759252 ===================================
539 22:19:50.762731 LPDDR4 DRAM CONFIGURATION
540 22:19:50.765583 ===================================
541 22:19:50.765666 EX_ROW_EN[0] = 0x0
542 22:19:50.768900 EX_ROW_EN[1] = 0x0
543 22:19:50.768983 LP4Y_EN = 0x0
544 22:19:50.772474 WORK_FSP = 0x0
545 22:19:50.772610 WL = 0x2
546 22:19:50.775589 RL = 0x2
547 22:19:50.775659 BL = 0x2
548 22:19:50.779448 RPST = 0x0
549 22:19:50.779531 RD_PRE = 0x0
550 22:19:50.782385 WR_PRE = 0x1
551 22:19:50.782467 WR_PST = 0x0
552 22:19:50.785837 DBI_WR = 0x0
553 22:19:50.789220 DBI_RD = 0x0
554 22:19:50.789303 OTF = 0x1
555 22:19:50.792223 ===================================
556 22:19:50.795791 ===================================
557 22:19:50.795874 ANA top config
558 22:19:50.799022 ===================================
559 22:19:50.802393 DLL_ASYNC_EN = 0
560 22:19:50.805752 ALL_SLAVE_EN = 1
561 22:19:50.809194 NEW_RANK_MODE = 1
562 22:19:50.812369 DLL_IDLE_MODE = 1
563 22:19:50.812477 LP45_APHY_COMB_EN = 1
564 22:19:50.815614 TX_ODT_DIS = 1
565 22:19:50.818953 NEW_8X_MODE = 1
566 22:19:50.822224 ===================================
567 22:19:50.825964 ===================================
568 22:19:50.829458 data_rate = 1600
569 22:19:50.832328 CKR = 1
570 22:19:50.832411 DQ_P2S_RATIO = 8
571 22:19:50.835702 ===================================
572 22:19:50.838698 CA_P2S_RATIO = 8
573 22:19:50.842112 DQ_CA_OPEN = 0
574 22:19:50.845382 DQ_SEMI_OPEN = 0
575 22:19:50.849119 CA_SEMI_OPEN = 0
576 22:19:50.852071 CA_FULL_RATE = 0
577 22:19:50.852154 DQ_CKDIV4_EN = 1
578 22:19:50.855596 CA_CKDIV4_EN = 1
579 22:19:50.858944 CA_PREDIV_EN = 0
580 22:19:50.861968 PH8_DLY = 0
581 22:19:50.865700 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:19:50.868931 DQ_AAMCK_DIV = 4
583 22:19:50.869014 CA_AAMCK_DIV = 4
584 22:19:50.871999 CA_ADMCK_DIV = 4
585 22:19:50.875525 DQ_TRACK_CA_EN = 0
586 22:19:50.879077 CA_PICK = 800
587 22:19:50.882070 CA_MCKIO = 800
588 22:19:50.885198 MCKIO_SEMI = 0
589 22:19:50.888472 PLL_FREQ = 3068
590 22:19:50.888581 DQ_UI_PI_RATIO = 32
591 22:19:50.891698 CA_UI_PI_RATIO = 0
592 22:19:50.895352 ===================================
593 22:19:50.898464 ===================================
594 22:19:50.901553 memory_type:LPDDR4
595 22:19:50.905189 GP_NUM : 10
596 22:19:50.905273 SRAM_EN : 1
597 22:19:50.908279 MD32_EN : 0
598 22:19:50.911767 ===================================
599 22:19:50.914909 [ANA_INIT] >>>>>>>>>>>>>>
600 22:19:50.914993 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:19:50.918368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:19:50.921809 ===================================
603 22:19:50.924826 data_rate = 1600,PCW = 0X7600
604 22:19:50.928743 ===================================
605 22:19:50.931574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:19:50.938633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:19:50.944726 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:19:50.948065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:19:50.951775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:19:50.955202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:19:50.958315 [ANA_INIT] flow start
612 22:19:50.958399 [ANA_INIT] PLL >>>>>>>>
613 22:19:50.961423 [ANA_INIT] PLL <<<<<<<<
614 22:19:50.964715 [ANA_INIT] MIDPI >>>>>>>>
615 22:19:50.967827 [ANA_INIT] MIDPI <<<<<<<<
616 22:19:50.967910 [ANA_INIT] DLL >>>>>>>>
617 22:19:50.971642 [ANA_INIT] flow end
618 22:19:50.974442 ============ LP4 DIFF to SE enter ============
619 22:19:50.977956 ============ LP4 DIFF to SE exit ============
620 22:19:50.981156 [ANA_INIT] <<<<<<<<<<<<<
621 22:19:50.984472 [Flow] Enable top DCM control >>>>>
622 22:19:50.988470 [Flow] Enable top DCM control <<<<<
623 22:19:50.991226 Enable DLL master slave shuffle
624 22:19:50.994964 ==============================================================
625 22:19:50.998306 Gating Mode config
626 22:19:51.004737 ==============================================================
627 22:19:51.004821 Config description:
628 22:19:51.014481 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:19:51.021349 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:19:51.027760 SELPH_MODE 0: By rank 1: By Phase
631 22:19:51.031419 ==============================================================
632 22:19:51.034614 GAT_TRACK_EN = 1
633 22:19:51.038241 RX_GATING_MODE = 2
634 22:19:51.041181 RX_GATING_TRACK_MODE = 2
635 22:19:51.044670 SELPH_MODE = 1
636 22:19:51.047853 PICG_EARLY_EN = 1
637 22:19:51.050974 VALID_LAT_VALUE = 1
638 22:19:51.054168 ==============================================================
639 22:19:51.057506 Enter into Gating configuration >>>>
640 22:19:51.061048 Exit from Gating configuration <<<<
641 22:19:51.064129 Enter into DVFS_PRE_config >>>>>
642 22:19:51.077682 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:19:51.080583 Exit from DVFS_PRE_config <<<<<
644 22:19:51.084429 Enter into PICG configuration >>>>
645 22:19:51.084582 Exit from PICG configuration <<<<
646 22:19:51.087560 [RX_INPUT] configuration >>>>>
647 22:19:51.090919 [RX_INPUT] configuration <<<<<
648 22:19:51.097453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:19:51.101377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:19:51.108648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:19:51.116799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:19:51.120301 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:19:51.127171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:19:51.130620 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:19:51.134462 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:19:51.137698 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:19:51.144967 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:19:51.148587 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:19:51.152342 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:19:51.156425 ===================================
661 22:19:51.157056 LPDDR4 DRAM CONFIGURATION
662 22:19:51.160096 ===================================
663 22:19:51.163340 EX_ROW_EN[0] = 0x0
664 22:19:51.167060 EX_ROW_EN[1] = 0x0
665 22:19:51.167640 LP4Y_EN = 0x0
666 22:19:51.168024 WORK_FSP = 0x0
667 22:19:51.170737 WL = 0x2
668 22:19:51.171324 RL = 0x2
669 22:19:51.174984 BL = 0x2
670 22:19:51.175568 RPST = 0x0
671 22:19:51.178168 RD_PRE = 0x0
672 22:19:51.178645 WR_PRE = 0x1
673 22:19:51.181414 WR_PST = 0x0
674 22:19:51.181888 DBI_WR = 0x0
675 22:19:51.185169 DBI_RD = 0x0
676 22:19:51.185643 OTF = 0x1
677 22:19:51.189005 ===================================
678 22:19:51.192577 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:19:51.196954 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:19:51.200297 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:19:51.203650 ===================================
682 22:19:51.206885 LPDDR4 DRAM CONFIGURATION
683 22:19:51.210469 ===================================
684 22:19:51.214602 EX_ROW_EN[0] = 0x10
685 22:19:51.215191 EX_ROW_EN[1] = 0x0
686 22:19:51.217674 LP4Y_EN = 0x0
687 22:19:51.218148 WORK_FSP = 0x0
688 22:19:51.221622 WL = 0x2
689 22:19:51.222214 RL = 0x2
690 22:19:51.222628 BL = 0x2
691 22:19:51.225038 RPST = 0x0
692 22:19:51.225542 RD_PRE = 0x0
693 22:19:51.228957 WR_PRE = 0x1
694 22:19:51.229515 WR_PST = 0x0
695 22:19:51.232559 DBI_WR = 0x0
696 22:19:51.232990 DBI_RD = 0x0
697 22:19:51.236511 OTF = 0x1
698 22:19:51.240237 ===================================
699 22:19:51.244020 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:19:51.249430 nWR fixed to 40
701 22:19:51.252722 [ModeRegInit_LP4] CH0 RK0
702 22:19:51.253152 [ModeRegInit_LP4] CH0 RK1
703 22:19:51.256307 [ModeRegInit_LP4] CH1 RK0
704 22:19:51.256878 [ModeRegInit_LP4] CH1 RK1
705 22:19:51.259891 match AC timing 13
706 22:19:51.263108 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:19:51.266510 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:19:51.273538 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:19:51.276968 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:19:51.279795 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:19:51.283788 [EMI DOE] emi_dcm 0
712 22:19:51.286761 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:19:51.287237 ==
714 22:19:51.289964 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:19:51.297853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:19:51.298299 ==
717 22:19:51.300924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:19:51.307532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:19:51.316230 [CA 0] Center 37 (6~68) winsize 63
720 22:19:51.319515 [CA 1] Center 37 (6~68) winsize 63
721 22:19:51.322418 [CA 2] Center 34 (4~65) winsize 62
722 22:19:51.326210 [CA 3] Center 34 (4~65) winsize 62
723 22:19:51.329642 [CA 4] Center 33 (3~64) winsize 62
724 22:19:51.333333 [CA 5] Center 33 (3~64) winsize 62
725 22:19:51.333905
726 22:19:51.336713 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 22:19:51.337186
728 22:19:51.340248 [CATrainingPosCal] consider 1 rank data
729 22:19:51.343092 u2DelayCellTimex100 = 270/100 ps
730 22:19:51.347183 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 22:19:51.350361 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 22:19:51.353468 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 22:19:51.357119 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 22:19:51.363618 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 22:19:51.366457 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 22:19:51.366930
737 22:19:51.369960 CA PerBit enable=1, Macro0, CA PI delay=33
738 22:19:51.370540
739 22:19:51.373181 [CBTSetCACLKResult] CA Dly = 33
740 22:19:51.373659 CS Dly: 6 (0~37)
741 22:19:51.374040 ==
742 22:19:51.376622 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:19:51.380126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:19:51.383050 ==
745 22:19:51.387003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:19:51.393182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:19:51.402199 [CA 0] Center 37 (6~68) winsize 63
748 22:19:51.405341 [CA 1] Center 37 (7~68) winsize 62
749 22:19:51.408824 [CA 2] Center 34 (4~65) winsize 62
750 22:19:51.411855 [CA 3] Center 34 (4~65) winsize 62
751 22:19:51.415412 [CA 4] Center 33 (3~64) winsize 62
752 22:19:51.418481 [CA 5] Center 33 (2~64) winsize 63
753 22:19:51.418957
754 22:19:51.422228 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 22:19:51.422809
756 22:19:51.425377 [CATrainingPosCal] consider 2 rank data
757 22:19:51.428798 u2DelayCellTimex100 = 270/100 ps
758 22:19:51.432173 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 22:19:51.438399 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 22:19:51.441781 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 22:19:51.445504 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 22:19:51.449134 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 22:19:51.453301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 22:19:51.454026
765 22:19:51.456927 CA PerBit enable=1, Macro0, CA PI delay=33
766 22:19:51.457711
767 22:19:51.458248 [CBTSetCACLKResult] CA Dly = 33
768 22:19:51.460361 CS Dly: 6 (0~38)
769 22:19:51.461013
770 22:19:51.464617 ----->DramcWriteLeveling(PI) begin...
771 22:19:51.465343 ==
772 22:19:51.467480 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:19:51.471911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:19:51.472575 ==
775 22:19:51.474776 Write leveling (Byte 0): 35 => 35
776 22:19:51.478048 Write leveling (Byte 1): 31 => 31
777 22:19:51.481238 DramcWriteLeveling(PI) end<-----
778 22:19:51.481715
779 22:19:51.482090 ==
780 22:19:51.484511 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:19:51.487937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:19:51.488627 ==
783 22:19:51.491591 [Gating] SW mode calibration
784 22:19:51.498443 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:19:51.504787 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:19:51.508505 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:19:51.511248 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 22:19:51.518400 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 22:19:51.521027 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 22:19:51.524401 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:19:51.531171 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:19:51.533893 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:19:51.537501 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:19:51.544131 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:19:51.547235 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:19:51.550862 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:19:51.557166 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:19:51.560706 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:19:51.563752 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:19:51.570184 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:19:51.573813 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:19:51.577367 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:19:51.584146 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 22:19:51.586880 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 22:19:51.590472 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
806 22:19:51.594006 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:19:51.600468 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:19:51.603335 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:19:51.607354 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:19:51.613192 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:19:51.616397 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:19:51.620043 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
813 22:19:51.626478 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
814 22:19:51.630062 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:19:51.633099 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:19:51.639917 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:19:51.643463 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:19:51.646486 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:19:51.653294 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 22:19:51.656502 0 10 8 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 1)
821 22:19:51.659682 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
822 22:19:51.666680 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:19:51.669728 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:19:51.673362 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:19:51.679246 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:19:51.683258 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:19:51.686184 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
828 22:19:51.693364 0 11 8 | B1->B0 | 2525 3737 | 0 1 | (0 0) (0 0)
829 22:19:51.696336 0 11 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
830 22:19:51.699913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:19:51.706252 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:19:51.709984 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:19:51.712625 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:19:51.719095 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:19:51.722599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:19:51.725677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 22:19:51.732672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:19:51.735865 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:19:51.739240 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:19:51.746162 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:19:51.749270 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:19:51.752175 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:19:51.759298 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:19:51.762431 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:19:51.765734 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:19:51.772279 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:19:51.775390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:19:51.778818 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:19:51.785674 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:19:51.789073 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:19:51.792147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 22:19:51.799064 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 22:19:51.802079 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 22:19:51.806028 Total UI for P1: 0, mck2ui 16
855 22:19:51.808773 best dqsien dly found for B0: ( 0, 14, 6)
856 22:19:51.812260 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 22:19:51.815904 Total UI for P1: 0, mck2ui 16
858 22:19:51.818734 best dqsien dly found for B1: ( 0, 14, 12)
859 22:19:51.822646 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 22:19:51.825682 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 22:19:51.825765
862 22:19:51.829024 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 22:19:51.832884 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 22:19:51.836166 [Gating] SW calibration Done
865 22:19:51.836258 ==
866 22:19:51.840004 Dram Type= 6, Freq= 0, CH_0, rank 0
867 22:19:51.842522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 22:19:51.846121 ==
869 22:19:51.846207 RX Vref Scan: 0
870 22:19:51.846292
871 22:19:51.849391 RX Vref 0 -> 0, step: 1
872 22:19:51.849477
873 22:19:51.852380 RX Delay -130 -> 252, step: 16
874 22:19:51.855870 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 22:19:51.859161 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 22:19:51.862434 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 22:19:51.865426 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 22:19:51.872047 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 22:19:51.875463 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 22:19:51.879018 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
881 22:19:51.882179 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 22:19:51.885504 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
883 22:19:51.892678 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
884 22:19:51.895160 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 22:19:51.899172 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 22:19:51.902381 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
887 22:19:51.906364 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 22:19:51.909737 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 22:19:51.916854 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
890 22:19:51.916933 ==
891 22:19:51.920701 Dram Type= 6, Freq= 0, CH_0, rank 0
892 22:19:51.923848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 22:19:51.923919 ==
894 22:19:51.923980 DQS Delay:
895 22:19:51.927556 DQS0 = 0, DQS1 = 0
896 22:19:51.927627 DQM Delay:
897 22:19:51.927688 DQM0 = 84, DQM1 = 71
898 22:19:51.930950 DQ Delay:
899 22:19:51.934908 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 22:19:51.934980 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
901 22:19:51.938446 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
902 22:19:51.941830 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
903 22:19:51.941903
904 22:19:51.941966
905 22:19:51.942024 ==
906 22:19:51.946295 Dram Type= 6, Freq= 0, CH_0, rank 0
907 22:19:51.949457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 22:19:51.949527 ==
909 22:19:51.953080
910 22:19:51.953153
911 22:19:51.953215 TX Vref Scan disable
912 22:19:51.956969 == TX Byte 0 ==
913 22:19:51.960718 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
914 22:19:51.964637 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
915 22:19:51.964710 == TX Byte 1 ==
916 22:19:51.971364 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 22:19:51.975147 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 22:19:51.975227 ==
919 22:19:51.979166 Dram Type= 6, Freq= 0, CH_0, rank 0
920 22:19:51.982617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 22:19:51.982696 ==
922 22:19:51.995120 TX Vref=22, minBit 2, minWin=27, winSum=442
923 22:19:51.998897 TX Vref=24, minBit 2, minWin=27, winSum=444
924 22:19:52.002714 TX Vref=26, minBit 0, minWin=27, winSum=444
925 22:19:52.006913 TX Vref=28, minBit 3, minWin=27, winSum=446
926 22:19:52.009609 TX Vref=30, minBit 0, minWin=27, winSum=445
927 22:19:52.012927 TX Vref=32, minBit 0, minWin=27, winSum=443
928 22:19:52.020276 [TxChooseVref] Worse bit 3, Min win 27, Win sum 446, Final Vref 28
929 22:19:52.020360
930 22:19:52.020426 Final TX Range 1 Vref 28
931 22:19:52.024055
932 22:19:52.024137 ==
933 22:19:52.024203 Dram Type= 6, Freq= 0, CH_0, rank 0
934 22:19:52.030711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 22:19:52.030794 ==
936 22:19:52.030860
937 22:19:52.030919
938 22:19:52.030976 TX Vref Scan disable
939 22:19:52.034978 == TX Byte 0 ==
940 22:19:52.039028 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 22:19:52.042273 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 22:19:52.045875 == TX Byte 1 ==
943 22:19:52.049936 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
944 22:19:52.053161 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
945 22:19:52.053246
946 22:19:52.053390 [DATLAT]
947 22:19:52.056423 Freq=800, CH0 RK0
948 22:19:52.056505
949 22:19:52.056577 DATLAT Default: 0xa
950 22:19:52.059746 0, 0xFFFF, sum = 0
951 22:19:52.063502 1, 0xFFFF, sum = 0
952 22:19:52.063586 2, 0xFFFF, sum = 0
953 22:19:52.066689 3, 0xFFFF, sum = 0
954 22:19:52.066773 4, 0xFFFF, sum = 0
955 22:19:52.069527 5, 0xFFFF, sum = 0
956 22:19:52.069610 6, 0xFFFF, sum = 0
957 22:19:52.072736 7, 0xFFFF, sum = 0
958 22:19:52.072820 8, 0xFFFF, sum = 0
959 22:19:52.076334 9, 0x0, sum = 1
960 22:19:52.076434 10, 0x0, sum = 2
961 22:19:52.079505 11, 0x0, sum = 3
962 22:19:52.079605 12, 0x0, sum = 4
963 22:19:52.079686 best_step = 10
964 22:19:52.079761
965 22:19:52.083363 ==
966 22:19:52.086372 Dram Type= 6, Freq= 0, CH_0, rank 0
967 22:19:52.090046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 22:19:52.090129 ==
969 22:19:52.090194 RX Vref Scan: 1
970 22:19:52.090253
971 22:19:52.093393 Set Vref Range= 32 -> 127
972 22:19:52.093475
973 22:19:52.096427 RX Vref 32 -> 127, step: 1
974 22:19:52.096510
975 22:19:52.099493 RX Delay -111 -> 252, step: 8
976 22:19:52.099590
977 22:19:52.102805 Set Vref, RX VrefLevel [Byte0]: 32
978 22:19:52.106269 [Byte1]: 32
979 22:19:52.106353
980 22:19:52.109315 Set Vref, RX VrefLevel [Byte0]: 33
981 22:19:52.113255 [Byte1]: 33
982 22:19:52.113331
983 22:19:52.115896 Set Vref, RX VrefLevel [Byte0]: 34
984 22:19:52.119788 [Byte1]: 34
985 22:19:52.123103
986 22:19:52.123188 Set Vref, RX VrefLevel [Byte0]: 35
987 22:19:52.126396 [Byte1]: 35
988 22:19:52.131183
989 22:19:52.131266 Set Vref, RX VrefLevel [Byte0]: 36
990 22:19:52.134329 [Byte1]: 36
991 22:19:52.138195
992 22:19:52.138267 Set Vref, RX VrefLevel [Byte0]: 37
993 22:19:52.141706 [Byte1]: 37
994 22:19:52.146440
995 22:19:52.146516 Set Vref, RX VrefLevel [Byte0]: 38
996 22:19:52.149556 [Byte1]: 38
997 22:19:52.154036
998 22:19:52.154115 Set Vref, RX VrefLevel [Byte0]: 39
999 22:19:52.157294 [Byte1]: 39
1000 22:19:52.161236
1001 22:19:52.161309 Set Vref, RX VrefLevel [Byte0]: 40
1002 22:19:52.164853 [Byte1]: 40
1003 22:19:52.169222
1004 22:19:52.169294 Set Vref, RX VrefLevel [Byte0]: 41
1005 22:19:52.172501 [Byte1]: 41
1006 22:19:52.176593
1007 22:19:52.176689 Set Vref, RX VrefLevel [Byte0]: 42
1008 22:19:52.179909 [Byte1]: 42
1009 22:19:52.184133
1010 22:19:52.184222 Set Vref, RX VrefLevel [Byte0]: 43
1011 22:19:52.187661 [Byte1]: 43
1012 22:19:52.192194
1013 22:19:52.192279 Set Vref, RX VrefLevel [Byte0]: 44
1014 22:19:52.195149 [Byte1]: 44
1015 22:19:52.199548
1016 22:19:52.199619 Set Vref, RX VrefLevel [Byte0]: 45
1017 22:19:52.202751 [Byte1]: 45
1018 22:19:52.207105
1019 22:19:52.207178 Set Vref, RX VrefLevel [Byte0]: 46
1020 22:19:52.210656 [Byte1]: 46
1021 22:19:52.214907
1022 22:19:52.214980 Set Vref, RX VrefLevel [Byte0]: 47
1023 22:19:52.218147 [Byte1]: 47
1024 22:19:52.222740
1025 22:19:52.222835 Set Vref, RX VrefLevel [Byte0]: 48
1026 22:19:52.225797 [Byte1]: 48
1027 22:19:52.229937
1028 22:19:52.230008 Set Vref, RX VrefLevel [Byte0]: 49
1029 22:19:52.236764 [Byte1]: 49
1030 22:19:52.236845
1031 22:19:52.239916 Set Vref, RX VrefLevel [Byte0]: 50
1032 22:19:52.243074 [Byte1]: 50
1033 22:19:52.243157
1034 22:19:52.246317 Set Vref, RX VrefLevel [Byte0]: 51
1035 22:19:52.249711 [Byte1]: 51
1036 22:19:52.253406
1037 22:19:52.253474 Set Vref, RX VrefLevel [Byte0]: 52
1038 22:19:52.256576 [Byte1]: 52
1039 22:19:52.260914
1040 22:19:52.260986 Set Vref, RX VrefLevel [Byte0]: 53
1041 22:19:52.263964 [Byte1]: 53
1042 22:19:52.268327
1043 22:19:52.268395 Set Vref, RX VrefLevel [Byte0]: 54
1044 22:19:52.271560 [Byte1]: 54
1045 22:19:52.276146
1046 22:19:52.276222 Set Vref, RX VrefLevel [Byte0]: 55
1047 22:19:52.279447 [Byte1]: 55
1048 22:19:52.284327
1049 22:19:52.284402 Set Vref, RX VrefLevel [Byte0]: 56
1050 22:19:52.286819 [Byte1]: 56
1051 22:19:52.291381
1052 22:19:52.291459 Set Vref, RX VrefLevel [Byte0]: 57
1053 22:19:52.294943 [Byte1]: 57
1054 22:19:52.298891
1055 22:19:52.302014 Set Vref, RX VrefLevel [Byte0]: 58
1056 22:19:52.305353 [Byte1]: 58
1057 22:19:52.305425
1058 22:19:52.308710 Set Vref, RX VrefLevel [Byte0]: 59
1059 22:19:52.311906 [Byte1]: 59
1060 22:19:52.311978
1061 22:19:52.315334 Set Vref, RX VrefLevel [Byte0]: 60
1062 22:19:52.318848 [Byte1]: 60
1063 22:19:52.321926
1064 22:19:52.321999 Set Vref, RX VrefLevel [Byte0]: 61
1065 22:19:52.325472 [Byte1]: 61
1066 22:19:52.329545
1067 22:19:52.329621 Set Vref, RX VrefLevel [Byte0]: 62
1068 22:19:52.336339 [Byte1]: 62
1069 22:19:52.336414
1070 22:19:52.339644 Set Vref, RX VrefLevel [Byte0]: 63
1071 22:19:52.342828 [Byte1]: 63
1072 22:19:52.342904
1073 22:19:52.346353 Set Vref, RX VrefLevel [Byte0]: 64
1074 22:19:52.348993 [Byte1]: 64
1075 22:19:52.352307
1076 22:19:52.352382 Set Vref, RX VrefLevel [Byte0]: 65
1077 22:19:52.355915 [Byte1]: 65
1078 22:19:52.359917
1079 22:19:52.359987 Set Vref, RX VrefLevel [Byte0]: 66
1080 22:19:52.363565 [Byte1]: 66
1081 22:19:52.368059
1082 22:19:52.368139 Set Vref, RX VrefLevel [Byte0]: 67
1083 22:19:52.371429 [Byte1]: 67
1084 22:19:52.375374
1085 22:19:52.375455 Set Vref, RX VrefLevel [Byte0]: 68
1086 22:19:52.378680 [Byte1]: 68
1087 22:19:52.383034
1088 22:19:52.383114 Set Vref, RX VrefLevel [Byte0]: 69
1089 22:19:52.386659 [Byte1]: 69
1090 22:19:52.390436
1091 22:19:52.390517 Set Vref, RX VrefLevel [Byte0]: 70
1092 22:19:52.393894 [Byte1]: 70
1093 22:19:52.398236
1094 22:19:52.401637 Set Vref, RX VrefLevel [Byte0]: 71
1095 22:19:52.401718 [Byte1]: 71
1096 22:19:52.406561
1097 22:19:52.406642 Set Vref, RX VrefLevel [Byte0]: 72
1098 22:19:52.409132 [Byte1]: 72
1099 22:19:52.413544
1100 22:19:52.413625 Set Vref, RX VrefLevel [Byte0]: 73
1101 22:19:52.417129 [Byte1]: 73
1102 22:19:52.421442
1103 22:19:52.421522 Set Vref, RX VrefLevel [Byte0]: 74
1104 22:19:52.424789 [Byte1]: 74
1105 22:19:52.429232
1106 22:19:52.429312 Set Vref, RX VrefLevel [Byte0]: 75
1107 22:19:52.432563 [Byte1]: 75
1108 22:19:52.436495
1109 22:19:52.436611 Set Vref, RX VrefLevel [Byte0]: 76
1110 22:19:52.440155 [Byte1]: 76
1111 22:19:52.444357
1112 22:19:52.444437 Set Vref, RX VrefLevel [Byte0]: 77
1113 22:19:52.447403 [Byte1]: 77
1114 22:19:52.451701
1115 22:19:52.451781 Set Vref, RX VrefLevel [Byte0]: 78
1116 22:19:52.455212 [Byte1]: 78
1117 22:19:52.459649
1118 22:19:52.459729 Set Vref, RX VrefLevel [Byte0]: 79
1119 22:19:52.462794 [Byte1]: 79
1120 22:19:52.467188
1121 22:19:52.467268 Set Vref, RX VrefLevel [Byte0]: 80
1122 22:19:52.470551 [Byte1]: 80
1123 22:19:52.474697
1124 22:19:52.474777 Set Vref, RX VrefLevel [Byte0]: 81
1125 22:19:52.478309 [Byte1]: 81
1126 22:19:52.482833
1127 22:19:52.482914 Final RX Vref Byte 0 = 61 to rank0
1128 22:19:52.486143 Final RX Vref Byte 1 = 53 to rank0
1129 22:19:52.489784 Final RX Vref Byte 0 = 61 to rank1
1130 22:19:52.493508 Final RX Vref Byte 1 = 53 to rank1==
1131 22:19:52.497425 Dram Type= 6, Freq= 0, CH_0, rank 0
1132 22:19:52.501322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 22:19:52.501405 ==
1134 22:19:52.501469 DQS Delay:
1135 22:19:52.504780 DQS0 = 0, DQS1 = 0
1136 22:19:52.504867 DQM Delay:
1137 22:19:52.507924 DQM0 = 87, DQM1 = 75
1138 22:19:52.508004 DQ Delay:
1139 22:19:52.511756 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1140 22:19:52.515847 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1141 22:19:52.518761 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1142 22:19:52.522928 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1143 22:19:52.523016
1144 22:19:52.523101
1145 22:19:52.530344 [DQSOSCAuto] RK0, (LSB)MR18= 0x4425, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1146 22:19:52.533715 CH0 RK0: MR19=606, MR18=4425
1147 22:19:52.537487 CH0_RK0: MR19=0x606, MR18=0x4425, DQSOSC=392, MR23=63, INC=96, DEC=64
1148 22:19:52.537587
1149 22:19:52.541421 ----->DramcWriteLeveling(PI) begin...
1150 22:19:52.541520 ==
1151 22:19:52.544847 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 22:19:52.548536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 22:19:52.548632 ==
1154 22:19:52.552389 Write leveling (Byte 0): 29 => 29
1155 22:19:52.555678 Write leveling (Byte 1): 32 => 32
1156 22:19:52.559655 DramcWriteLeveling(PI) end<-----
1157 22:19:52.559736
1158 22:19:52.559800 ==
1159 22:19:52.563645 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 22:19:52.607396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 22:19:52.607511 ==
1162 22:19:52.607627 [Gating] SW mode calibration
1163 22:19:52.608268 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1164 22:19:52.608350 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1165 22:19:52.609000 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 22:19:52.609268 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1167 22:19:52.609789 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 22:19:52.610408 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1169 22:19:52.610489 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:19:52.610731 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:19:52.651623 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:19:52.651907 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:19:52.651989 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:19:52.652053 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:19:52.652419 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:19:52.653200 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:19:52.653497 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:19:52.654257 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:19:52.654338 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:19:52.654629 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:19:52.679694 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:19:52.679967 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1183 22:19:52.680037 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:19:52.680106 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:19:52.680394 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 22:19:52.680813 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 22:19:52.683601 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 22:19:52.686702 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 22:19:52.690486 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 22:19:52.696817 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 22:19:52.700120 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1192 22:19:52.703350 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1193 22:19:52.710346 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 22:19:52.713392 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 22:19:52.716943 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 22:19:52.723418 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 22:19:52.726636 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 22:19:52.730067 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 1)
1199 22:19:52.736835 0 10 8 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (1 1)
1200 22:19:52.740132 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:19:52.743307 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 22:19:52.750113 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 22:19:52.753700 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 22:19:52.756464 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 22:19:52.762915 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 22:19:52.766324 0 11 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
1207 22:19:52.769694 0 11 8 | B1->B0 | 2929 3e3e | 0 0 | (0 0) (0 0)
1208 22:19:52.772959 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1209 22:19:52.779615 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 22:19:52.783097 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 22:19:52.786650 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 22:19:52.793434 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 22:19:52.796561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 22:19:52.799797 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 22:19:52.806498 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1216 22:19:52.809858 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:19:52.812948 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:19:52.819606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:19:52.823327 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:19:52.826247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:19:52.833038 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:19:52.836235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:19:52.839223 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 22:19:52.845963 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 22:19:52.849213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 22:19:52.852757 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 22:19:52.859278 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 22:19:52.862857 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 22:19:52.865916 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 22:19:52.872903 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 22:19:52.876005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1232 22:19:52.879066 Total UI for P1: 0, mck2ui 16
1233 22:19:52.882951 best dqsien dly found for B0: ( 0, 14, 6)
1234 22:19:52.885895 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 22:19:52.889202 Total UI for P1: 0, mck2ui 16
1236 22:19:52.892303 best dqsien dly found for B1: ( 0, 14, 8)
1237 22:19:52.895861 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1238 22:19:52.898886 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1239 22:19:52.898997
1240 22:19:52.902281 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1241 22:19:52.909372 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1242 22:19:52.909454 [Gating] SW calibration Done
1243 22:19:52.909518 ==
1244 22:19:52.912706 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 22:19:52.918724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 22:19:52.918836 ==
1247 22:19:52.918901 RX Vref Scan: 0
1248 22:19:52.918961
1249 22:19:52.922521 RX Vref 0 -> 0, step: 1
1250 22:19:52.922601
1251 22:19:52.925777 RX Delay -130 -> 252, step: 16
1252 22:19:52.928898 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1253 22:19:52.932711 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1254 22:19:52.935806 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1255 22:19:52.942543 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1256 22:19:52.945698 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1257 22:19:52.948947 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1258 22:19:52.952222 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1259 22:19:52.955498 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1260 22:19:52.962220 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1261 22:19:52.965396 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1262 22:19:52.969317 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1263 22:19:52.972147 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1264 22:19:52.975533 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1265 22:19:52.982391 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1266 22:19:52.985724 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1267 22:19:52.989215 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1268 22:19:52.989317 ==
1269 22:19:52.992130 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 22:19:52.995680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 22:19:52.998744 ==
1272 22:19:52.998848 DQS Delay:
1273 22:19:52.998950 DQS0 = 0, DQS1 = 0
1274 22:19:53.002604 DQM Delay:
1275 22:19:53.002706 DQM0 = 87, DQM1 = 78
1276 22:19:53.002800 DQ Delay:
1277 22:19:53.005339 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1278 22:19:53.008911 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1279 22:19:53.012326 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1280 22:19:53.015580 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1281 22:19:53.015684
1282 22:19:53.018681
1283 22:19:53.018775 ==
1284 22:19:53.022117 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 22:19:53.025608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 22:19:53.025704 ==
1287 22:19:53.025804
1288 22:19:53.025864
1289 22:19:53.029653 TX Vref Scan disable
1290 22:19:53.029780 == TX Byte 0 ==
1291 22:19:53.032908 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1292 22:19:53.037257 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1293 22:19:53.040825 == TX Byte 1 ==
1294 22:19:53.043803 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1295 22:19:53.047510 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1296 22:19:53.047581 ==
1297 22:19:53.051301 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 22:19:53.054359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 22:19:53.054440 ==
1300 22:19:53.069005 TX Vref=22, minBit 14, minWin=27, winSum=448
1301 22:19:53.072731 TX Vref=24, minBit 11, minWin=27, winSum=448
1302 22:19:53.075987 TX Vref=26, minBit 0, minWin=28, winSum=450
1303 22:19:53.079995 TX Vref=28, minBit 9, minWin=27, winSum=449
1304 22:19:53.083230 TX Vref=30, minBit 9, minWin=27, winSum=448
1305 22:19:53.087132 TX Vref=32, minBit 9, minWin=27, winSum=446
1306 22:19:53.094179 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 26
1307 22:19:53.094260
1308 22:19:53.094323 Final TX Range 1 Vref 26
1309 22:19:53.097851
1310 22:19:53.097930 ==
1311 22:19:53.097993 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 22:19:53.104513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 22:19:53.104637 ==
1314 22:19:53.104701
1315 22:19:53.104758
1316 22:19:53.104813 TX Vref Scan disable
1317 22:19:53.109382 == TX Byte 0 ==
1318 22:19:53.112134 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1319 22:19:53.116396 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1320 22:19:53.119411 == TX Byte 1 ==
1321 22:19:53.123484 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1322 22:19:53.126973 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1323 22:19:53.127055
1324 22:19:53.127130 [DATLAT]
1325 22:19:53.130705 Freq=800, CH0 RK1
1326 22:19:53.130788
1327 22:19:53.130849 DATLAT Default: 0xa
1328 22:19:53.134425 0, 0xFFFF, sum = 0
1329 22:19:53.134498 1, 0xFFFF, sum = 0
1330 22:19:53.138160 2, 0xFFFF, sum = 0
1331 22:19:53.138241 3, 0xFFFF, sum = 0
1332 22:19:53.141651 4, 0xFFFF, sum = 0
1333 22:19:53.141735 5, 0xFFFF, sum = 0
1334 22:19:53.144947 6, 0xFFFF, sum = 0
1335 22:19:53.145029 7, 0xFFFF, sum = 0
1336 22:19:53.148809 8, 0xFFFF, sum = 0
1337 22:19:53.148887 9, 0x0, sum = 1
1338 22:19:53.148950 10, 0x0, sum = 2
1339 22:19:53.152715 11, 0x0, sum = 3
1340 22:19:53.152786 12, 0x0, sum = 4
1341 22:19:53.156400 best_step = 10
1342 22:19:53.156477
1343 22:19:53.156574 ==
1344 22:19:53.160206 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 22:19:53.163811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 22:19:53.163886 ==
1347 22:19:53.163956 RX Vref Scan: 0
1348 22:19:53.164016
1349 22:19:53.167324 RX Vref 0 -> 0, step: 1
1350 22:19:53.167391
1351 22:19:53.170686 RX Delay -111 -> 252, step: 8
1352 22:19:53.174348 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1353 22:19:53.177287 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1354 22:19:53.181046 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1355 22:19:53.188241 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1356 22:19:53.192072 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1357 22:19:53.195576 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1358 22:19:53.199346 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1359 22:19:53.202754 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1360 22:19:53.206702 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1361 22:19:53.210776 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1362 22:19:53.213953 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1363 22:19:53.217583 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1364 22:19:53.221046 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1365 22:19:53.225341 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1366 22:19:53.232550 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1367 22:19:53.236215 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1368 22:19:53.236297 ==
1369 22:19:53.239899 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 22:19:53.243372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 22:19:53.243455 ==
1372 22:19:53.243521 DQS Delay:
1373 22:19:53.247264 DQS0 = 0, DQS1 = 0
1374 22:19:53.247346 DQM Delay:
1375 22:19:53.247413 DQM0 = 84, DQM1 = 77
1376 22:19:53.250606 DQ Delay:
1377 22:19:53.254245 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1378 22:19:53.254327 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1379 22:19:53.258250 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1380 22:19:53.261659 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1381 22:19:53.261740
1382 22:19:53.261802
1383 22:19:53.272899 [DQSOSCAuto] RK1, (LSB)MR18= 0x4007, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1384 22:19:53.272978 CH0 RK1: MR19=606, MR18=4007
1385 22:19:53.279807 CH0_RK1: MR19=0x606, MR18=0x4007, DQSOSC=393, MR23=63, INC=95, DEC=63
1386 22:19:53.283508 [RxdqsGatingPostProcess] freq 800
1387 22:19:53.287059 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 22:19:53.290436 Pre-setting of DQS Precalculation
1389 22:19:53.294656 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 22:19:53.298073 ==
1391 22:19:53.298146 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 22:19:53.304823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 22:19:53.304912 ==
1394 22:19:53.308436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 22:19:53.315461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 22:19:53.324408 [CA 0] Center 36 (6~67) winsize 62
1397 22:19:53.327306 [CA 1] Center 36 (6~67) winsize 62
1398 22:19:53.330835 [CA 2] Center 34 (4~65) winsize 62
1399 22:19:53.334495 [CA 3] Center 34 (3~65) winsize 63
1400 22:19:53.338122 [CA 4] Center 34 (4~65) winsize 62
1401 22:19:53.341415 [CA 5] Center 34 (4~65) winsize 62
1402 22:19:53.341489
1403 22:19:53.345154 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 22:19:53.345241
1405 22:19:53.348748 [CATrainingPosCal] consider 1 rank data
1406 22:19:53.352400 u2DelayCellTimex100 = 270/100 ps
1407 22:19:53.356645 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 22:19:53.359785 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 22:19:53.363272 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 22:19:53.366961 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1411 22:19:53.369531 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 22:19:53.372865 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 22:19:53.372947
1414 22:19:53.376498 CA PerBit enable=1, Macro0, CA PI delay=34
1415 22:19:53.376616
1416 22:19:53.379391 [CBTSetCACLKResult] CA Dly = 34
1417 22:19:53.383177 CS Dly: 4 (0~35)
1418 22:19:53.383259 ==
1419 22:19:53.386634 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 22:19:53.389461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 22:19:53.389545 ==
1422 22:19:53.395963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 22:19:53.402599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 22:19:53.410574 [CA 0] Center 36 (6~67) winsize 62
1425 22:19:53.413594 [CA 1] Center 36 (6~67) winsize 62
1426 22:19:53.416703 [CA 2] Center 34 (4~65) winsize 62
1427 22:19:53.419924 [CA 3] Center 34 (3~65) winsize 63
1428 22:19:53.423590 [CA 4] Center 34 (4~65) winsize 62
1429 22:19:53.427144 [CA 5] Center 33 (3~64) winsize 62
1430 22:19:53.427227
1431 22:19:53.429920 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 22:19:53.430002
1433 22:19:53.432973 [CATrainingPosCal] consider 2 rank data
1434 22:19:53.436440 u2DelayCellTimex100 = 270/100 ps
1435 22:19:53.439703 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 22:19:53.446566 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1437 22:19:53.449795 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 22:19:53.453064 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1439 22:19:53.456237 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 22:19:53.459593 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1441 22:19:53.459676
1442 22:19:53.462972 CA PerBit enable=1, Macro0, CA PI delay=34
1443 22:19:53.463049
1444 22:19:53.466262 [CBTSetCACLKResult] CA Dly = 34
1445 22:19:53.466333 CS Dly: 5 (0~38)
1446 22:19:53.469746
1447 22:19:53.473018 ----->DramcWriteLeveling(PI) begin...
1448 22:19:53.473102 ==
1449 22:19:53.476500 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 22:19:53.479565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 22:19:53.479652 ==
1452 22:19:53.483226 Write leveling (Byte 0): 25 => 25
1453 22:19:53.486587 Write leveling (Byte 1): 29 => 29
1454 22:19:53.489716 DramcWriteLeveling(PI) end<-----
1455 22:19:53.489796
1456 22:19:53.489858 ==
1457 22:19:53.492887 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 22:19:53.496704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 22:19:53.496777 ==
1460 22:19:53.499550 [Gating] SW mode calibration
1461 22:19:53.506249 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 22:19:53.513035 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 22:19:53.516120 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1464 22:19:53.519654 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1465 22:19:53.526282 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1466 22:19:53.529418 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:19:53.532752 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:19:53.539263 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:19:53.542565 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:19:53.546240 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:19:53.552575 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:19:53.556038 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:19:53.559405 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:19:53.566904 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:19:53.569266 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:19:53.572493 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:19:53.578851 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:19:53.582270 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:19:53.585516 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1480 22:19:53.589426 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1481 22:19:53.595856 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1482 22:19:53.599182 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:19:53.602723 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 22:19:53.609139 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 22:19:53.612449 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 22:19:53.615593 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 22:19:53.622181 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 22:19:53.626135 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:19:53.629149 0 9 8 | B1->B0 | 2e2e 3131 | 1 1 | (1 1) (1 1)
1490 22:19:53.635541 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 22:19:53.639496 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 22:19:53.642476 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 22:19:53.649402 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 22:19:53.652157 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 22:19:53.655908 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 22:19:53.662627 0 10 4 | B1->B0 | 3434 3131 | 0 1 | (0 1) (1 0)
1497 22:19:53.665674 0 10 8 | B1->B0 | 2e2e 2828 | 0 0 | (1 1) (0 0)
1498 22:19:53.669168 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:19:53.675772 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 22:19:53.678818 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 22:19:53.682006 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 22:19:53.688618 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 22:19:53.692613 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 22:19:53.695888 0 11 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1505 22:19:53.702908 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1506 22:19:53.706338 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 22:19:53.708770 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 22:19:53.711975 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 22:19:53.718934 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 22:19:53.722170 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 22:19:53.725507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 22:19:53.731750 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1513 22:19:53.735022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1514 22:19:53.738286 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:19:53.745209 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:19:53.748720 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:19:53.751535 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:19:53.758317 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:19:53.761932 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 22:19:53.764961 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 22:19:53.771582 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 22:19:53.774781 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 22:19:53.778349 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 22:19:53.784637 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 22:19:53.788250 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 22:19:53.791632 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 22:19:53.798254 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 22:19:53.801352 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1529 22:19:53.804879 Total UI for P1: 0, mck2ui 16
1530 22:19:53.808490 best dqsien dly found for B0: ( 0, 14, 2)
1531 22:19:53.811637 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 22:19:53.814725 Total UI for P1: 0, mck2ui 16
1533 22:19:53.817886 best dqsien dly found for B1: ( 0, 14, 4)
1534 22:19:53.821199 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1535 22:19:53.824709 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1536 22:19:53.824791
1537 22:19:53.831289 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1538 22:19:53.834563 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1539 22:19:53.834646 [Gating] SW calibration Done
1540 22:19:53.838116 ==
1541 22:19:53.841505 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 22:19:53.844392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 22:19:53.844474 ==
1544 22:19:53.844581 RX Vref Scan: 0
1545 22:19:53.844643
1546 22:19:53.848111 RX Vref 0 -> 0, step: 1
1547 22:19:53.848192
1548 22:19:53.851078 RX Delay -130 -> 252, step: 16
1549 22:19:53.854475 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1550 22:19:53.857934 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1551 22:19:53.864756 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1552 22:19:53.868081 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1553 22:19:53.871009 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1554 22:19:53.874466 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1555 22:19:53.877921 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1556 22:19:53.884129 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1557 22:19:53.887620 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1558 22:19:53.890796 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1559 22:19:53.894124 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1560 22:19:53.897590 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1561 22:19:53.904674 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1562 22:19:53.907244 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1563 22:19:53.910966 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1564 22:19:53.914338 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1565 22:19:53.914446 ==
1566 22:19:53.917339 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 22:19:53.924144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 22:19:53.924252 ==
1569 22:19:53.924371 DQS Delay:
1570 22:19:53.927729 DQS0 = 0, DQS1 = 0
1571 22:19:53.927835 DQM Delay:
1572 22:19:53.927925 DQM0 = 88, DQM1 = 78
1573 22:19:53.930741 DQ Delay:
1574 22:19:53.933921 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1575 22:19:53.937276 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1576 22:19:53.940390 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1577 22:19:53.943976 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1578 22:19:53.944083
1579 22:19:53.944175
1580 22:19:53.944264 ==
1581 22:19:53.947255 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 22:19:53.950279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 22:19:53.950377 ==
1584 22:19:53.950477
1585 22:19:53.950563
1586 22:19:53.953670 TX Vref Scan disable
1587 22:19:53.956913 == TX Byte 0 ==
1588 22:19:53.960145 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1589 22:19:53.963462 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1590 22:19:53.966830 == TX Byte 1 ==
1591 22:19:53.970037 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1592 22:19:53.973776 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1593 22:19:53.973858 ==
1594 22:19:53.976738 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 22:19:53.980216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 22:19:53.983698 ==
1597 22:19:53.994872 TX Vref=22, minBit 10, minWin=26, winSum=436
1598 22:19:53.998342 TX Vref=24, minBit 1, minWin=27, winSum=443
1599 22:19:54.001676 TX Vref=26, minBit 3, minWin=27, winSum=447
1600 22:19:54.004984 TX Vref=28, minBit 9, minWin=27, winSum=448
1601 22:19:54.008219 TX Vref=30, minBit 15, minWin=27, winSum=449
1602 22:19:54.015119 TX Vref=32, minBit 1, minWin=27, winSum=443
1603 22:19:54.018398 [TxChooseVref] Worse bit 15, Min win 27, Win sum 449, Final Vref 30
1604 22:19:54.018499
1605 22:19:54.021444 Final TX Range 1 Vref 30
1606 22:19:54.021541
1607 22:19:54.021630 ==
1608 22:19:54.024537 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 22:19:54.028422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 22:19:54.031440 ==
1611 22:19:54.031538
1612 22:19:54.031631
1613 22:19:54.031719 TX Vref Scan disable
1614 22:19:54.034863 == TX Byte 0 ==
1615 22:19:54.038768 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1616 22:19:54.045260 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1617 22:19:54.045338 == TX Byte 1 ==
1618 22:19:54.048259 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 22:19:54.054939 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 22:19:54.055041
1621 22:19:54.055107 [DATLAT]
1622 22:19:54.055166 Freq=800, CH1 RK0
1623 22:19:54.055224
1624 22:19:54.058293 DATLAT Default: 0xa
1625 22:19:54.058373 0, 0xFFFF, sum = 0
1626 22:19:54.062124 1, 0xFFFF, sum = 0
1627 22:19:54.062205 2, 0xFFFF, sum = 0
1628 22:19:54.065040 3, 0xFFFF, sum = 0
1629 22:19:54.065122 4, 0xFFFF, sum = 0
1630 22:19:54.069564 5, 0xFFFF, sum = 0
1631 22:19:54.071607 6, 0xFFFF, sum = 0
1632 22:19:54.071688 7, 0xFFFF, sum = 0
1633 22:19:54.075159 8, 0xFFFF, sum = 0
1634 22:19:54.075241 9, 0x0, sum = 1
1635 22:19:54.075305 10, 0x0, sum = 2
1636 22:19:54.078232 11, 0x0, sum = 3
1637 22:19:54.078314 12, 0x0, sum = 4
1638 22:19:54.082432 best_step = 10
1639 22:19:54.082512
1640 22:19:54.082576 ==
1641 22:19:54.084931 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 22:19:54.088463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 22:19:54.088585 ==
1644 22:19:54.091962 RX Vref Scan: 1
1645 22:19:54.092042
1646 22:19:54.092104 Set Vref Range= 32 -> 127
1647 22:19:54.094824
1648 22:19:54.094904 RX Vref 32 -> 127, step: 1
1649 22:19:54.094969
1650 22:19:54.098141 RX Delay -95 -> 252, step: 8
1651 22:19:54.098221
1652 22:19:54.101779 Set Vref, RX VrefLevel [Byte0]: 32
1653 22:19:54.104930 [Byte1]: 32
1654 22:19:54.105011
1655 22:19:54.108164 Set Vref, RX VrefLevel [Byte0]: 33
1656 22:19:54.111620 [Byte1]: 33
1657 22:19:54.115620
1658 22:19:54.115699 Set Vref, RX VrefLevel [Byte0]: 34
1659 22:19:54.118776 [Byte1]: 34
1660 22:19:54.123161
1661 22:19:54.123241 Set Vref, RX VrefLevel [Byte0]: 35
1662 22:19:54.126416 [Byte1]: 35
1663 22:19:54.130598
1664 22:19:54.130678 Set Vref, RX VrefLevel [Byte0]: 36
1665 22:19:54.134042 [Byte1]: 36
1666 22:19:54.138451
1667 22:19:54.138536 Set Vref, RX VrefLevel [Byte0]: 37
1668 22:19:54.141449 [Byte1]: 37
1669 22:19:54.145801
1670 22:19:54.145881 Set Vref, RX VrefLevel [Byte0]: 38
1671 22:19:54.149118 [Byte1]: 38
1672 22:19:54.153398
1673 22:19:54.153477 Set Vref, RX VrefLevel [Byte0]: 39
1674 22:19:54.156936 [Byte1]: 39
1675 22:19:54.161356
1676 22:19:54.161436 Set Vref, RX VrefLevel [Byte0]: 40
1677 22:19:54.164335 [Byte1]: 40
1678 22:19:54.168675
1679 22:19:54.168755 Set Vref, RX VrefLevel [Byte0]: 41
1680 22:19:54.172542 [Byte1]: 41
1681 22:19:54.176354
1682 22:19:54.176433 Set Vref, RX VrefLevel [Byte0]: 42
1683 22:19:54.179616 [Byte1]: 42
1684 22:19:54.184006
1685 22:19:54.184085 Set Vref, RX VrefLevel [Byte0]: 43
1686 22:19:54.187136 [Byte1]: 43
1687 22:19:54.191688
1688 22:19:54.191768 Set Vref, RX VrefLevel [Byte0]: 44
1689 22:19:54.194726 [Byte1]: 44
1690 22:19:54.199062
1691 22:19:54.199142 Set Vref, RX VrefLevel [Byte0]: 45
1692 22:19:54.202578 [Byte1]: 45
1693 22:19:54.207077
1694 22:19:54.207157 Set Vref, RX VrefLevel [Byte0]: 46
1695 22:19:54.210281 [Byte1]: 46
1696 22:19:54.214669
1697 22:19:54.214749 Set Vref, RX VrefLevel [Byte0]: 47
1698 22:19:54.217850 [Byte1]: 47
1699 22:19:54.221967
1700 22:19:54.222047 Set Vref, RX VrefLevel [Byte0]: 48
1701 22:19:54.225343 [Byte1]: 48
1702 22:19:54.229871
1703 22:19:54.229951 Set Vref, RX VrefLevel [Byte0]: 49
1704 22:19:54.233145 [Byte1]: 49
1705 22:19:54.237967
1706 22:19:54.238046 Set Vref, RX VrefLevel [Byte0]: 50
1707 22:19:54.240667 [Byte1]: 50
1708 22:19:54.244752
1709 22:19:54.244832 Set Vref, RX VrefLevel [Byte0]: 51
1710 22:19:54.247773 [Byte1]: 51
1711 22:19:54.252447
1712 22:19:54.252583 Set Vref, RX VrefLevel [Byte0]: 52
1713 22:19:54.255966 [Byte1]: 52
1714 22:19:54.259771
1715 22:19:54.259850 Set Vref, RX VrefLevel [Byte0]: 53
1716 22:19:54.263034 [Byte1]: 53
1717 22:19:54.267772
1718 22:19:54.267852 Set Vref, RX VrefLevel [Byte0]: 54
1719 22:19:54.270714 [Byte1]: 54
1720 22:19:54.274997
1721 22:19:54.275076 Set Vref, RX VrefLevel [Byte0]: 55
1722 22:19:54.278160 [Byte1]: 55
1723 22:19:54.282738
1724 22:19:54.282818 Set Vref, RX VrefLevel [Byte0]: 56
1725 22:19:54.286008 [Byte1]: 56
1726 22:19:54.290857
1727 22:19:54.290937 Set Vref, RX VrefLevel [Byte0]: 57
1728 22:19:54.293514 [Byte1]: 57
1729 22:19:54.298119
1730 22:19:54.298204 Set Vref, RX VrefLevel [Byte0]: 58
1731 22:19:54.301047 [Byte1]: 58
1732 22:19:54.305490
1733 22:19:54.305569 Set Vref, RX VrefLevel [Byte0]: 59
1734 22:19:54.309078 [Byte1]: 59
1735 22:19:54.313353
1736 22:19:54.313433 Set Vref, RX VrefLevel [Byte0]: 60
1737 22:19:54.316468 [Byte1]: 60
1738 22:19:54.321070
1739 22:19:54.321151 Set Vref, RX VrefLevel [Byte0]: 61
1740 22:19:54.324047 [Byte1]: 61
1741 22:19:54.328543
1742 22:19:54.328636 Set Vref, RX VrefLevel [Byte0]: 62
1743 22:19:54.331745 [Byte1]: 62
1744 22:19:54.336214
1745 22:19:54.336293 Set Vref, RX VrefLevel [Byte0]: 63
1746 22:19:54.339616 [Byte1]: 63
1747 22:19:54.343310
1748 22:19:54.343390 Set Vref, RX VrefLevel [Byte0]: 64
1749 22:19:54.346875 [Byte1]: 64
1750 22:19:54.351429
1751 22:19:54.351508 Set Vref, RX VrefLevel [Byte0]: 65
1752 22:19:54.354345 [Byte1]: 65
1753 22:19:54.358548
1754 22:19:54.358627 Set Vref, RX VrefLevel [Byte0]: 66
1755 22:19:54.362365 [Byte1]: 66
1756 22:19:54.366121
1757 22:19:54.366201 Set Vref, RX VrefLevel [Byte0]: 67
1758 22:19:54.369277 [Byte1]: 67
1759 22:19:54.373680
1760 22:19:54.373760 Set Vref, RX VrefLevel [Byte0]: 68
1761 22:19:54.377207 [Byte1]: 68
1762 22:19:54.381409
1763 22:19:54.381488 Set Vref, RX VrefLevel [Byte0]: 69
1764 22:19:54.385080 [Byte1]: 69
1765 22:19:54.388863
1766 22:19:54.388943 Set Vref, RX VrefLevel [Byte0]: 70
1767 22:19:54.392388 [Byte1]: 70
1768 22:19:54.396842
1769 22:19:54.396922 Set Vref, RX VrefLevel [Byte0]: 71
1770 22:19:54.399801 [Byte1]: 71
1771 22:19:54.404014
1772 22:19:54.404094 Set Vref, RX VrefLevel [Byte0]: 72
1773 22:19:54.407964 [Byte1]: 72
1774 22:19:54.412103
1775 22:19:54.412182 Set Vref, RX VrefLevel [Byte0]: 73
1776 22:19:54.415139 [Byte1]: 73
1777 22:19:54.419573
1778 22:19:54.419660 Final RX Vref Byte 0 = 56 to rank0
1779 22:19:54.423308 Final RX Vref Byte 1 = 63 to rank0
1780 22:19:54.426391 Final RX Vref Byte 0 = 56 to rank1
1781 22:19:54.429265 Final RX Vref Byte 1 = 63 to rank1==
1782 22:19:54.432942 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 22:19:54.439207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 22:19:54.439321 ==
1785 22:19:54.439412 DQS Delay:
1786 22:19:54.442660 DQS0 = 0, DQS1 = 0
1787 22:19:54.442773 DQM Delay:
1788 22:19:54.442862 DQM0 = 86, DQM1 = 79
1789 22:19:54.445896 DQ Delay:
1790 22:19:54.448917 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1791 22:19:54.452339 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1792 22:19:54.455533 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1793 22:19:54.459173 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1794 22:19:54.459307
1795 22:19:54.459429
1796 22:19:54.465570 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1797 22:19:54.468817 CH1 RK0: MR19=606, MR18=301C
1798 22:19:54.475336 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1799 22:19:54.475437
1800 22:19:54.479068 ----->DramcWriteLeveling(PI) begin...
1801 22:19:54.479170 ==
1802 22:19:54.482094 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 22:19:54.485359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 22:19:54.485437 ==
1805 22:19:54.488948 Write leveling (Byte 0): 28 => 28
1806 22:19:54.491976 Write leveling (Byte 1): 29 => 29
1807 22:19:54.495592 DramcWriteLeveling(PI) end<-----
1808 22:19:54.495703
1809 22:19:54.495798 ==
1810 22:19:54.498647 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 22:19:54.502057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 22:19:54.502154 ==
1813 22:19:54.505341 [Gating] SW mode calibration
1814 22:19:54.511971 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 22:19:54.518779 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 22:19:54.521979 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 22:19:54.528534 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 22:19:54.532123 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:19:54.535390 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:19:54.541782 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:19:54.545311 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:19:54.548432 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:19:54.555208 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:19:54.558155 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:19:54.561843 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:19:54.568085 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:19:54.571885 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:19:54.574945 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:19:54.581472 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:19:54.584995 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:19:54.588056 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:19:54.594490 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:19:54.598401 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1834 22:19:54.601153 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1835 22:19:54.608081 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:19:54.611071 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:19:54.614413 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:19:54.621256 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:19:54.624284 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:19:54.627884 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:19:54.631384 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (1 1) (0 0)
1842 22:19:54.637874 0 9 8 | B1->B0 | 3333 2c2c | 1 0 | (0 0) (0 0)
1843 22:19:54.641289 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 22:19:54.644502 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:19:54.651351 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 22:19:54.654368 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:19:54.657398 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 22:19:54.664566 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 22:19:54.667684 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
1850 22:19:54.670937 0 10 8 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 1)
1851 22:19:54.677745 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:19:54.680747 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:19:54.684240 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:19:54.691005 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 22:19:54.694622 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 22:19:54.697970 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 22:19:54.703825 0 11 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1858 22:19:54.707082 0 11 8 | B1->B0 | 4343 3535 | 0 1 | (0 0) (0 0)
1859 22:19:54.710400 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:19:54.717187 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:19:54.720551 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:19:54.724346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 22:19:54.730806 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 22:19:54.733924 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 22:19:54.738023 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 22:19:54.743673 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1867 22:19:54.747337 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:19:54.750389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:19:54.757736 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:19:54.760393 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:19:54.763649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:19:54.770210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:19:54.773597 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:19:54.777004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:19:54.784331 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:19:54.787365 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:19:54.790473 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:19:54.796758 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:19:54.800043 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:19:54.803990 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:19:54.809797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1882 22:19:54.813544 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1883 22:19:54.816690 Total UI for P1: 0, mck2ui 16
1884 22:19:54.820053 best dqsien dly found for B1: ( 0, 14, 4)
1885 22:19:54.823325 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 22:19:54.826455 Total UI for P1: 0, mck2ui 16
1887 22:19:54.830588 best dqsien dly found for B0: ( 0, 14, 6)
1888 22:19:54.833210 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1889 22:19:54.836456 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1890 22:19:54.836564
1891 22:19:54.839686 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1892 22:19:54.846299 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 22:19:54.846376 [Gating] SW calibration Done
1894 22:19:54.846439 ==
1895 22:19:54.849575 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 22:19:54.856398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 22:19:54.856505 ==
1898 22:19:54.856579 RX Vref Scan: 0
1899 22:19:54.856647
1900 22:19:54.859798 RX Vref 0 -> 0, step: 1
1901 22:19:54.859866
1902 22:19:54.863074 RX Delay -130 -> 252, step: 16
1903 22:19:54.866353 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1904 22:19:54.869714 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1905 22:19:54.872819 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1906 22:19:54.879443 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1907 22:19:54.883156 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1908 22:19:54.886282 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1909 22:19:54.889549 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1910 22:19:54.893113 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1911 22:19:54.899272 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1912 22:19:54.902816 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1913 22:19:54.905923 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1914 22:19:54.909625 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1915 22:19:54.912715 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1916 22:19:54.919439 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1917 22:19:54.922660 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1918 22:19:54.925959 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1919 22:19:54.926041 ==
1920 22:19:54.929637 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 22:19:54.932469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 22:19:54.936384 ==
1923 22:19:54.936466 DQS Delay:
1924 22:19:54.936556 DQS0 = 0, DQS1 = 0
1925 22:19:54.939397 DQM Delay:
1926 22:19:54.939478 DQM0 = 87, DQM1 = 77
1927 22:19:54.943003 DQ Delay:
1928 22:19:54.943085 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1929 22:19:54.945926 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1930 22:19:54.949651 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1931 22:19:54.952636 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1932 22:19:54.955648
1933 22:19:54.955729
1934 22:19:54.955794 ==
1935 22:19:54.959183 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 22:19:54.962576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 22:19:54.962659 ==
1938 22:19:54.962724
1939 22:19:54.962785
1940 22:19:54.965876 TX Vref Scan disable
1941 22:19:54.965958 == TX Byte 0 ==
1942 22:19:54.972465 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1943 22:19:54.975773 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1944 22:19:54.975855 == TX Byte 1 ==
1945 22:19:54.982500 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1946 22:19:54.985680 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1947 22:19:54.985762 ==
1948 22:19:54.988661 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 22:19:54.992412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 22:19:54.992542 ==
1951 22:19:55.006352 TX Vref=22, minBit 8, minWin=27, winSum=444
1952 22:19:55.010249 TX Vref=24, minBit 9, minWin=26, winSum=446
1953 22:19:55.012742 TX Vref=26, minBit 8, minWin=27, winSum=448
1954 22:19:55.016595 TX Vref=28, minBit 8, minWin=27, winSum=448
1955 22:19:55.019864 TX Vref=30, minBit 8, minWin=27, winSum=452
1956 22:19:55.026333 TX Vref=32, minBit 8, minWin=27, winSum=451
1957 22:19:55.029409 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
1958 22:19:55.029535
1959 22:19:55.032913 Final TX Range 1 Vref 30
1960 22:19:55.033002
1961 22:19:55.033072 ==
1962 22:19:55.035917 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:19:55.039900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:19:55.040004 ==
1965 22:19:55.042503
1966 22:19:55.042604
1967 22:19:55.042684 TX Vref Scan disable
1968 22:19:55.046333 == TX Byte 0 ==
1969 22:19:55.049561 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1970 22:19:55.055985 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1971 22:19:55.056196 == TX Byte 1 ==
1972 22:19:55.059858 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1973 22:19:55.066207 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1974 22:19:55.066447
1975 22:19:55.066597 [DATLAT]
1976 22:19:55.066731 Freq=800, CH1 RK1
1977 22:19:55.066858
1978 22:19:55.069656 DATLAT Default: 0xa
1979 22:19:55.069862 0, 0xFFFF, sum = 0
1980 22:19:55.072979 1, 0xFFFF, sum = 0
1981 22:19:55.073272 2, 0xFFFF, sum = 0
1982 22:19:55.076612 3, 0xFFFF, sum = 0
1983 22:19:55.076937 4, 0xFFFF, sum = 0
1984 22:19:55.079805 5, 0xFFFF, sum = 0
1985 22:19:55.083070 6, 0xFFFF, sum = 0
1986 22:19:55.083383 7, 0xFFFF, sum = 0
1987 22:19:55.086450 8, 0xFFFF, sum = 0
1988 22:19:55.086845 9, 0x0, sum = 1
1989 22:19:55.087161 10, 0x0, sum = 2
1990 22:19:55.089669 11, 0x0, sum = 3
1991 22:19:55.090284 12, 0x0, sum = 4
1992 22:19:55.093214 best_step = 10
1993 22:19:55.093636
1994 22:19:55.093999 ==
1995 22:19:55.096323 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 22:19:55.099685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 22:19:55.100253 ==
1998 22:19:55.103082 RX Vref Scan: 0
1999 22:19:55.103639
2000 22:19:55.104007 RX Vref 0 -> 0, step: 1
2001 22:19:55.104351
2002 22:19:55.106627 RX Delay -111 -> 252, step: 8
2003 22:19:55.113150 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2004 22:19:55.117063 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2005 22:19:55.120486 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2006 22:19:55.123265 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2007 22:19:55.127065 iDelay=217, Bit 4, Center 88 (-23 ~ 200) 224
2008 22:19:55.133358 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2009 22:19:55.137538 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2010 22:19:55.139903 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2011 22:19:55.143452 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2012 22:19:55.146185 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2013 22:19:55.153839 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2014 22:19:55.156620 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2015 22:19:55.159755 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2016 22:19:55.162872 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2017 22:19:55.169713 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2018 22:19:55.173144 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2019 22:19:55.173614 ==
2020 22:19:55.176477 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 22:19:55.180052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 22:19:55.180678 ==
2023 22:19:55.183045 DQS Delay:
2024 22:19:55.183588 DQS0 = 0, DQS1 = 0
2025 22:19:55.183960 DQM Delay:
2026 22:19:55.186029 DQM0 = 87, DQM1 = 78
2027 22:19:55.186489 DQ Delay:
2028 22:19:55.189513 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2029 22:19:55.192656 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =84
2030 22:19:55.196748 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2031 22:19:55.199516 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2032 22:19:55.200069
2033 22:19:55.200431
2034 22:19:55.209920 [DQSOSCAuto] RK1, (LSB)MR18= 0x170f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2035 22:19:55.210479 CH1 RK1: MR19=606, MR18=170F
2036 22:19:55.216450 CH1_RK1: MR19=0x606, MR18=0x170F, DQSOSC=404, MR23=63, INC=90, DEC=60
2037 22:19:55.219780 [RxdqsGatingPostProcess] freq 800
2038 22:19:55.226469 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 22:19:55.229236 Pre-setting of DQS Precalculation
2040 22:19:55.232873 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 22:19:55.239589 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 22:19:55.249147 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 22:19:55.249695
2044 22:19:55.250062
2045 22:19:55.252497 [Calibration Summary] 1600 Mbps
2046 22:19:55.252998 CH 0, Rank 0
2047 22:19:55.255899 SW Impedance : PASS
2048 22:19:55.256476 DUTY Scan : NO K
2049 22:19:55.259391 ZQ Calibration : PASS
2050 22:19:55.262901 Jitter Meter : NO K
2051 22:19:55.263362 CBT Training : PASS
2052 22:19:55.265626 Write leveling : PASS
2053 22:19:55.269113 RX DQS gating : PASS
2054 22:19:55.269573 RX DQ/DQS(RDDQC) : PASS
2055 22:19:55.272698 TX DQ/DQS : PASS
2056 22:19:55.273161 RX DATLAT : PASS
2057 22:19:55.276063 RX DQ/DQS(Engine): PASS
2058 22:19:55.279210 TX OE : NO K
2059 22:19:55.279675 All Pass.
2060 22:19:55.280039
2061 22:19:55.280373 CH 0, Rank 1
2062 22:19:55.282411 SW Impedance : PASS
2063 22:19:55.285930 DUTY Scan : NO K
2064 22:19:55.286393 ZQ Calibration : PASS
2065 22:19:55.288774 Jitter Meter : NO K
2066 22:19:55.292679 CBT Training : PASS
2067 22:19:55.293244 Write leveling : PASS
2068 22:19:55.295917 RX DQS gating : PASS
2069 22:19:55.299277 RX DQ/DQS(RDDQC) : PASS
2070 22:19:55.299849 TX DQ/DQS : PASS
2071 22:19:55.302222 RX DATLAT : PASS
2072 22:19:55.305934 RX DQ/DQS(Engine): PASS
2073 22:19:55.306498 TX OE : NO K
2074 22:19:55.308860 All Pass.
2075 22:19:55.309318
2076 22:19:55.309679 CH 1, Rank 0
2077 22:19:55.312467 SW Impedance : PASS
2078 22:19:55.313095 DUTY Scan : NO K
2079 22:19:55.316347 ZQ Calibration : PASS
2080 22:19:55.319085 Jitter Meter : NO K
2081 22:19:55.319669 CBT Training : PASS
2082 22:19:55.322444 Write leveling : PASS
2083 22:19:55.323031 RX DQS gating : PASS
2084 22:19:55.325829 RX DQ/DQS(RDDQC) : PASS
2085 22:19:55.329179 TX DQ/DQS : PASS
2086 22:19:55.329750 RX DATLAT : PASS
2087 22:19:55.332608 RX DQ/DQS(Engine): PASS
2088 22:19:55.335505 TX OE : NO K
2089 22:19:55.335974 All Pass.
2090 22:19:55.336340
2091 22:19:55.336812 CH 1, Rank 1
2092 22:19:55.339254 SW Impedance : PASS
2093 22:19:55.342637 DUTY Scan : NO K
2094 22:19:55.343179 ZQ Calibration : PASS
2095 22:19:55.345573 Jitter Meter : NO K
2096 22:19:55.349390 CBT Training : PASS
2097 22:19:55.349883 Write leveling : PASS
2098 22:19:55.352079 RX DQS gating : PASS
2099 22:19:55.355955 RX DQ/DQS(RDDQC) : PASS
2100 22:19:55.356554 TX DQ/DQS : PASS
2101 22:19:55.359136 RX DATLAT : PASS
2102 22:19:55.362393 RX DQ/DQS(Engine): PASS
2103 22:19:55.362957 TX OE : NO K
2104 22:19:55.363327 All Pass.
2105 22:19:55.365830
2106 22:19:55.366285 DramC Write-DBI off
2107 22:19:55.369576 PER_BANK_REFRESH: Hybrid Mode
2108 22:19:55.370153 TX_TRACKING: ON
2109 22:19:55.372080 [GetDramInforAfterCalByMRR] Vendor 6.
2110 22:19:55.375874 [GetDramInforAfterCalByMRR] Revision 606.
2111 22:19:55.382136 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 22:19:55.382699 MR0 0x3b3b
2113 22:19:55.383067 MR8 0x5151
2114 22:19:55.385746 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 22:19:55.386206
2116 22:19:55.388670 MR0 0x3b3b
2117 22:19:55.389196 MR8 0x5151
2118 22:19:55.392327 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 22:19:55.392934
2120 22:19:55.402550 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 22:19:55.405209 [FAST_K] Save calibration result to emmc
2122 22:19:55.408749 [FAST_K] Save calibration result to emmc
2123 22:19:55.412034 dram_init: config_dvfs: 1
2124 22:19:55.416152 dramc_set_vcore_voltage set vcore to 662500
2125 22:19:55.419140 Read voltage for 1200, 2
2126 22:19:55.419706 Vio18 = 0
2127 22:19:55.420074 Vcore = 662500
2128 22:19:55.422187 Vdram = 0
2129 22:19:55.422653 Vddq = 0
2130 22:19:55.423022 Vmddr = 0
2131 22:19:55.428864 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 22:19:55.432195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 22:19:55.435137 MEM_TYPE=3, freq_sel=15
2134 22:19:55.439135 sv_algorithm_assistance_LP4_1600
2135 22:19:55.441660 ============ PULL DRAM RESETB DOWN ============
2136 22:19:55.445204 ========== PULL DRAM RESETB DOWN end =========
2137 22:19:55.451897 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 22:19:55.454920 ===================================
2139 22:19:55.455395 LPDDR4 DRAM CONFIGURATION
2140 22:19:55.458157 ===================================
2141 22:19:55.462284 EX_ROW_EN[0] = 0x0
2142 22:19:55.465138 EX_ROW_EN[1] = 0x0
2143 22:19:55.465601 LP4Y_EN = 0x0
2144 22:19:55.468113 WORK_FSP = 0x0
2145 22:19:55.468591 WL = 0x4
2146 22:19:55.471959 RL = 0x4
2147 22:19:55.472557 BL = 0x2
2148 22:19:55.474803 RPST = 0x0
2149 22:19:55.475374 RD_PRE = 0x0
2150 22:19:55.478627 WR_PRE = 0x1
2151 22:19:55.479192 WR_PST = 0x0
2152 22:19:55.481701 DBI_WR = 0x0
2153 22:19:55.482189 DBI_RD = 0x0
2154 22:19:55.485178 OTF = 0x1
2155 22:19:55.488258 ===================================
2156 22:19:55.491658 ===================================
2157 22:19:55.492128 ANA top config
2158 22:19:55.494995 ===================================
2159 22:19:55.498312 DLL_ASYNC_EN = 0
2160 22:19:55.502102 ALL_SLAVE_EN = 0
2161 22:19:55.505120 NEW_RANK_MODE = 1
2162 22:19:55.505688 DLL_IDLE_MODE = 1
2163 22:19:55.508420 LP45_APHY_COMB_EN = 1
2164 22:19:55.511878 TX_ODT_DIS = 1
2165 22:19:55.514788 NEW_8X_MODE = 1
2166 22:19:55.518605 ===================================
2167 22:19:55.521408 ===================================
2168 22:19:55.524394 data_rate = 2400
2169 22:19:55.525068 CKR = 1
2170 22:19:55.528014 DQ_P2S_RATIO = 8
2171 22:19:55.531391 ===================================
2172 22:19:55.534433 CA_P2S_RATIO = 8
2173 22:19:55.537752 DQ_CA_OPEN = 0
2174 22:19:55.541141 DQ_SEMI_OPEN = 0
2175 22:19:55.544825 CA_SEMI_OPEN = 0
2176 22:19:55.545344 CA_FULL_RATE = 0
2177 22:19:55.548031 DQ_CKDIV4_EN = 0
2178 22:19:55.551026 CA_CKDIV4_EN = 0
2179 22:19:55.554626 CA_PREDIV_EN = 0
2180 22:19:55.557570 PH8_DLY = 17
2181 22:19:55.560797 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 22:19:55.561163 DQ_AAMCK_DIV = 4
2183 22:19:55.564028 CA_AAMCK_DIV = 4
2184 22:19:55.567512 CA_ADMCK_DIV = 4
2185 22:19:55.570928 DQ_TRACK_CA_EN = 0
2186 22:19:55.574171 CA_PICK = 1200
2187 22:19:55.577524 CA_MCKIO = 1200
2188 22:19:55.580811 MCKIO_SEMI = 0
2189 22:19:55.581217 PLL_FREQ = 2366
2190 22:19:55.583948 DQ_UI_PI_RATIO = 32
2191 22:19:55.587442 CA_UI_PI_RATIO = 0
2192 22:19:55.590362 ===================================
2193 22:19:55.594209 ===================================
2194 22:19:55.597562 memory_type:LPDDR4
2195 22:19:55.597733 GP_NUM : 10
2196 22:19:55.600718 SRAM_EN : 1
2197 22:19:55.603828 MD32_EN : 0
2198 22:19:55.607246 ===================================
2199 22:19:55.607466 [ANA_INIT] >>>>>>>>>>>>>>
2200 22:19:55.610507 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 22:19:55.614342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 22:19:55.617726 ===================================
2203 22:19:55.620919 data_rate = 2400,PCW = 0X5b00
2204 22:19:55.623882 ===================================
2205 22:19:55.626914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 22:19:55.633809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 22:19:55.637157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 22:19:55.643868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 22:19:55.647403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 22:19:55.649986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 22:19:55.653358 [ANA_INIT] flow start
2212 22:19:55.653428 [ANA_INIT] PLL >>>>>>>>
2213 22:19:55.656864 [ANA_INIT] PLL <<<<<<<<
2214 22:19:55.659855 [ANA_INIT] MIDPI >>>>>>>>
2215 22:19:55.659924 [ANA_INIT] MIDPI <<<<<<<<
2216 22:19:55.663497 [ANA_INIT] DLL >>>>>>>>
2217 22:19:55.667022 [ANA_INIT] DLL <<<<<<<<
2218 22:19:55.667117 [ANA_INIT] flow end
2219 22:19:55.670071 ============ LP4 DIFF to SE enter ============
2220 22:19:55.676704 ============ LP4 DIFF to SE exit ============
2221 22:19:55.676803 [ANA_INIT] <<<<<<<<<<<<<
2222 22:19:55.680041 [Flow] Enable top DCM control >>>>>
2223 22:19:55.683115 [Flow] Enable top DCM control <<<<<
2224 22:19:55.686558 Enable DLL master slave shuffle
2225 22:19:55.693105 ==============================================================
2226 22:19:55.696891 Gating Mode config
2227 22:19:55.699716 ==============================================================
2228 22:19:55.703339 Config description:
2229 22:19:55.713316 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 22:19:55.720020 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 22:19:55.723703 SELPH_MODE 0: By rank 1: By Phase
2232 22:19:55.730035 ==============================================================
2233 22:19:55.733241 GAT_TRACK_EN = 1
2234 22:19:55.736468 RX_GATING_MODE = 2
2235 22:19:55.736595 RX_GATING_TRACK_MODE = 2
2236 22:19:55.739925 SELPH_MODE = 1
2237 22:19:55.743233 PICG_EARLY_EN = 1
2238 22:19:55.746426 VALID_LAT_VALUE = 1
2239 22:19:55.753134 ==============================================================
2240 22:19:55.756713 Enter into Gating configuration >>>>
2241 22:19:55.759497 Exit from Gating configuration <<<<
2242 22:19:55.762950 Enter into DVFS_PRE_config >>>>>
2243 22:19:55.773285 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 22:19:55.776617 Exit from DVFS_PRE_config <<<<<
2245 22:19:55.779609 Enter into PICG configuration >>>>
2246 22:19:55.782800 Exit from PICG configuration <<<<
2247 22:19:55.786230 [RX_INPUT] configuration >>>>>
2248 22:19:55.789786 [RX_INPUT] configuration <<<<<
2249 22:19:55.792454 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 22:19:55.799215 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 22:19:55.805936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 22:19:55.812555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 22:19:55.818831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 22:19:55.822653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 22:19:55.828824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 22:19:55.832303 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 22:19:55.835520 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 22:19:55.839354 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 22:19:55.845311 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 22:19:55.848770 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 22:19:55.852271 ===================================
2262 22:19:55.855634 LPDDR4 DRAM CONFIGURATION
2263 22:19:55.858637 ===================================
2264 22:19:55.858717 EX_ROW_EN[0] = 0x0
2265 22:19:55.861778 EX_ROW_EN[1] = 0x0
2266 22:19:55.861858 LP4Y_EN = 0x0
2267 22:19:55.865478 WORK_FSP = 0x0
2268 22:19:55.865558 WL = 0x4
2269 22:19:55.868875 RL = 0x4
2270 22:19:55.868956 BL = 0x2
2271 22:19:55.871846 RPST = 0x0
2272 22:19:55.871926 RD_PRE = 0x0
2273 22:19:55.875152 WR_PRE = 0x1
2274 22:19:55.878725 WR_PST = 0x0
2275 22:19:55.878805 DBI_WR = 0x0
2276 22:19:55.882119 DBI_RD = 0x0
2277 22:19:55.882199 OTF = 0x1
2278 22:19:55.885370 ===================================
2279 22:19:55.888713 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 22:19:55.895086 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 22:19:55.898162 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 22:19:55.901381 ===================================
2283 22:19:55.904914 LPDDR4 DRAM CONFIGURATION
2284 22:19:55.908285 ===================================
2285 22:19:55.908365 EX_ROW_EN[0] = 0x10
2286 22:19:55.911573 EX_ROW_EN[1] = 0x0
2287 22:19:55.911653 LP4Y_EN = 0x0
2288 22:19:55.914733 WORK_FSP = 0x0
2289 22:19:55.914814 WL = 0x4
2290 22:19:55.918142 RL = 0x4
2291 22:19:55.918222 BL = 0x2
2292 22:19:55.921439 RPST = 0x0
2293 22:19:55.921517 RD_PRE = 0x0
2294 22:19:55.924928 WR_PRE = 0x1
2295 22:19:55.928123 WR_PST = 0x0
2296 22:19:55.928201 DBI_WR = 0x0
2297 22:19:55.931344 DBI_RD = 0x0
2298 22:19:55.931422 OTF = 0x1
2299 22:19:55.934782 ===================================
2300 22:19:55.941337 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 22:19:55.941416 ==
2302 22:19:55.944632 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 22:19:55.948080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 22:19:55.948160 ==
2305 22:19:55.951276 [Duty_Offset_Calibration]
2306 22:19:55.954629 B0:1 B1:-1 CA:0
2307 22:19:55.954707
2308 22:19:55.957658 [DutyScan_Calibration_Flow] k_type=0
2309 22:19:55.965956
2310 22:19:55.966035 ==CLK 0==
2311 22:19:55.969059 Final CLK duty delay cell = 0
2312 22:19:55.972367 [0] MAX Duty = 5094%(X100), DQS PI = 16
2313 22:19:55.975974 [0] MIN Duty = 4907%(X100), DQS PI = 8
2314 22:19:55.976053 [0] AVG Duty = 5000%(X100)
2315 22:19:55.979017
2316 22:19:55.979096 CH0 CLK Duty spec in!! Max-Min= 187%
2317 22:19:55.986026 [DutyScan_Calibration_Flow] ====Done====
2318 22:19:55.986105
2319 22:19:55.988893 [DutyScan_Calibration_Flow] k_type=1
2320 22:19:56.003264
2321 22:19:56.003344 ==DQS 0 ==
2322 22:19:56.006705 Final DQS duty delay cell = -4
2323 22:19:56.010380 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2324 22:19:56.013211 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2325 22:19:56.016881 [-4] AVG Duty = 4968%(X100)
2326 22:19:56.016961
2327 22:19:56.017023 ==DQS 1 ==
2328 22:19:56.020260 Final DQS duty delay cell = -4
2329 22:19:56.023688 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2330 22:19:56.026727 [-4] MIN Duty = 4876%(X100), DQS PI = 24
2331 22:19:56.030061 [-4] AVG Duty = 4938%(X100)
2332 22:19:56.030140
2333 22:19:56.033289 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2334 22:19:56.033367
2335 22:19:56.037018 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2336 22:19:56.040470 [DutyScan_Calibration_Flow] ====Done====
2337 22:19:56.040583
2338 22:19:56.043444 [DutyScan_Calibration_Flow] k_type=3
2339 22:19:56.061149
2340 22:19:56.061235 ==DQM 0 ==
2341 22:19:56.064499 Final DQM duty delay cell = 0
2342 22:19:56.067877 [0] MAX Duty = 5062%(X100), DQS PI = 18
2343 22:19:56.071464 [0] MIN Duty = 4875%(X100), DQS PI = 6
2344 22:19:56.071540 [0] AVG Duty = 4968%(X100)
2345 22:19:56.074851
2346 22:19:56.074971 ==DQM 1 ==
2347 22:19:56.077932 Final DQM duty delay cell = 4
2348 22:19:56.080963 [4] MAX Duty = 5187%(X100), DQS PI = 16
2349 22:19:56.084567 [4] MIN Duty = 4969%(X100), DQS PI = 26
2350 22:19:56.087590 [4] AVG Duty = 5078%(X100)
2351 22:19:56.087690
2352 22:19:56.091179 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2353 22:19:56.091287
2354 22:19:56.094316 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2355 22:19:56.098205 [DutyScan_Calibration_Flow] ====Done====
2356 22:19:56.098283
2357 22:19:56.101236 [DutyScan_Calibration_Flow] k_type=2
2358 22:19:56.117309
2359 22:19:56.117419 ==DQ 0 ==
2360 22:19:56.120285 Final DQ duty delay cell = -4
2361 22:19:56.123698 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2362 22:19:56.127144 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2363 22:19:56.130264 [-4] AVG Duty = 4969%(X100)
2364 22:19:56.130362
2365 22:19:56.130478 ==DQ 1 ==
2366 22:19:56.133468 Final DQ duty delay cell = 0
2367 22:19:56.137076 [0] MAX Duty = 5093%(X100), DQS PI = 4
2368 22:19:56.140000 [0] MIN Duty = 4969%(X100), DQS PI = 42
2369 22:19:56.143358 [0] AVG Duty = 5031%(X100)
2370 22:19:56.143468
2371 22:19:56.147093 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2372 22:19:56.147195
2373 22:19:56.149723 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2374 22:19:56.153343 [DutyScan_Calibration_Flow] ====Done====
2375 22:19:56.153431 ==
2376 22:19:56.157099 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 22:19:56.160266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 22:19:56.160383 ==
2379 22:19:56.163224 [Duty_Offset_Calibration]
2380 22:19:56.163299 B0:-1 B1:1 CA:2
2381 22:19:56.163360
2382 22:19:56.167145 [DutyScan_Calibration_Flow] k_type=0
2383 22:19:56.177372
2384 22:19:56.177473 ==CLK 0==
2385 22:19:56.180440 Final CLK duty delay cell = 0
2386 22:19:56.184256 [0] MAX Duty = 5156%(X100), DQS PI = 22
2387 22:19:56.187503 [0] MIN Duty = 4969%(X100), DQS PI = 60
2388 22:19:56.187578 [0] AVG Duty = 5062%(X100)
2389 22:19:56.190303
2390 22:19:56.194095 CH1 CLK Duty spec in!! Max-Min= 187%
2391 22:19:56.197052 [DutyScan_Calibration_Flow] ====Done====
2392 22:19:56.197129
2393 22:19:56.200255 [DutyScan_Calibration_Flow] k_type=1
2394 22:19:56.216832
2395 22:19:56.216934 ==DQS 0 ==
2396 22:19:56.220088 Final DQS duty delay cell = 0
2397 22:19:56.222936 [0] MAX Duty = 5156%(X100), DQS PI = 48
2398 22:19:56.226704 [0] MIN Duty = 4907%(X100), DQS PI = 8
2399 22:19:56.229901 [0] AVG Duty = 5031%(X100)
2400 22:19:56.230002
2401 22:19:56.230107 ==DQS 1 ==
2402 22:19:56.233164 Final DQS duty delay cell = 0
2403 22:19:56.236506 [0] MAX Duty = 5062%(X100), DQS PI = 8
2404 22:19:56.239565 [0] MIN Duty = 4969%(X100), DQS PI = 56
2405 22:19:56.242869 [0] AVG Duty = 5015%(X100)
2406 22:19:56.242982
2407 22:19:56.246539 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2408 22:19:56.246642
2409 22:19:56.249540 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2410 22:19:56.253298 [DutyScan_Calibration_Flow] ====Done====
2411 22:19:56.253397
2412 22:19:56.256173 [DutyScan_Calibration_Flow] k_type=3
2413 22:19:56.271745
2414 22:19:56.271821 ==DQM 0 ==
2415 22:19:56.275033 Final DQM duty delay cell = -4
2416 22:19:56.278785 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2417 22:19:56.282174 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2418 22:19:56.285334 [-4] AVG Duty = 4969%(X100)
2419 22:19:56.285409
2420 22:19:56.285472 ==DQM 1 ==
2421 22:19:56.288905 Final DQM duty delay cell = 0
2422 22:19:56.292024 [0] MAX Duty = 5187%(X100), DQS PI = 6
2423 22:19:56.295410 [0] MIN Duty = 5000%(X100), DQS PI = 28
2424 22:19:56.298340 [0] AVG Duty = 5093%(X100)
2425 22:19:56.298423
2426 22:19:56.301808 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2427 22:19:56.301884
2428 22:19:56.305551 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2429 22:19:56.308464 [DutyScan_Calibration_Flow] ====Done====
2430 22:19:56.308538
2431 22:19:56.311838 [DutyScan_Calibration_Flow] k_type=2
2432 22:19:56.328648
2433 22:19:56.328732 ==DQ 0 ==
2434 22:19:56.332340 Final DQ duty delay cell = 0
2435 22:19:56.335780 [0] MAX Duty = 5187%(X100), DQS PI = 28
2436 22:19:56.338594 [0] MIN Duty = 4907%(X100), DQS PI = 6
2437 22:19:56.338664 [0] AVG Duty = 5047%(X100)
2438 22:19:56.338740
2439 22:19:56.342187 ==DQ 1 ==
2440 22:19:56.345497 Final DQ duty delay cell = 0
2441 22:19:56.348881 [0] MAX Duty = 5124%(X100), DQS PI = 10
2442 22:19:56.351792 [0] MIN Duty = 4969%(X100), DQS PI = 0
2443 22:19:56.351860 [0] AVG Duty = 5046%(X100)
2444 22:19:56.351921
2445 22:19:56.355385 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2446 22:19:56.355465
2447 22:19:56.362206 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2448 22:19:56.365668 [DutyScan_Calibration_Flow] ====Done====
2449 22:19:56.369015 nWR fixed to 30
2450 22:19:56.369097 [ModeRegInit_LP4] CH0 RK0
2451 22:19:56.372371 [ModeRegInit_LP4] CH0 RK1
2452 22:19:56.375014 [ModeRegInit_LP4] CH1 RK0
2453 22:19:56.375084 [ModeRegInit_LP4] CH1 RK1
2454 22:19:56.378360 match AC timing 7
2455 22:19:56.382197 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 22:19:56.385029 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 22:19:56.392368 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 22:19:56.395170 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 22:19:56.402613 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 22:19:56.402696 ==
2461 22:19:56.405096 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 22:19:56.408690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 22:19:56.408772 ==
2464 22:19:56.414995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 22:19:56.421497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2466 22:19:56.428467 [CA 0] Center 39 (9~70) winsize 62
2467 22:19:56.432014 [CA 1] Center 39 (9~70) winsize 62
2468 22:19:56.434993 [CA 2] Center 35 (5~66) winsize 62
2469 22:19:56.438716 [CA 3] Center 35 (5~66) winsize 62
2470 22:19:56.441678 [CA 4] Center 34 (4~64) winsize 61
2471 22:19:56.444904 [CA 5] Center 33 (4~63) winsize 60
2472 22:19:56.445004
2473 22:19:56.448808 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2474 22:19:56.448884
2475 22:19:56.451544 [CATrainingPosCal] consider 1 rank data
2476 22:19:56.455096 u2DelayCellTimex100 = 270/100 ps
2477 22:19:56.458265 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2478 22:19:56.464928 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2479 22:19:56.468211 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2480 22:19:56.471851 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2481 22:19:56.475120 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2482 22:19:56.478860 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2483 22:19:56.478957
2484 22:19:56.481543 CA PerBit enable=1, Macro0, CA PI delay=33
2485 22:19:56.481644
2486 22:19:56.484868 [CBTSetCACLKResult] CA Dly = 33
2487 22:19:56.484969 CS Dly: 8 (0~39)
2488 22:19:56.488468 ==
2489 22:19:56.488562 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 22:19:56.495072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 22:19:56.495155 ==
2492 22:19:56.498554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 22:19:56.504708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 22:19:56.514284 [CA 0] Center 39 (9~70) winsize 62
2495 22:19:56.517774 [CA 1] Center 39 (9~70) winsize 62
2496 22:19:56.520827 [CA 2] Center 35 (5~66) winsize 62
2497 22:19:56.524166 [CA 3] Center 34 (4~65) winsize 62
2498 22:19:56.527441 [CA 4] Center 33 (3~64) winsize 62
2499 22:19:56.530946 [CA 5] Center 33 (3~63) winsize 61
2500 22:19:56.531016
2501 22:19:56.534588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 22:19:56.534658
2503 22:19:56.537679 [CATrainingPosCal] consider 2 rank data
2504 22:19:56.541044 u2DelayCellTimex100 = 270/100 ps
2505 22:19:56.544300 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2506 22:19:56.547610 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2507 22:19:56.554406 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2508 22:19:56.557467 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2509 22:19:56.561014 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2510 22:19:56.564288 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2511 22:19:56.564361
2512 22:19:56.567303 CA PerBit enable=1, Macro0, CA PI delay=33
2513 22:19:56.567371
2514 22:19:56.570630 [CBTSetCACLKResult] CA Dly = 33
2515 22:19:56.570699 CS Dly: 8 (0~40)
2516 22:19:56.574173
2517 22:19:56.577165 ----->DramcWriteLeveling(PI) begin...
2518 22:19:56.577235 ==
2519 22:19:56.580746 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 22:19:56.583752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 22:19:56.583823 ==
2522 22:19:56.586965 Write leveling (Byte 0): 33 => 33
2523 22:19:56.590509 Write leveling (Byte 1): 29 => 29
2524 22:19:56.593615 DramcWriteLeveling(PI) end<-----
2525 22:19:56.593688
2526 22:19:56.593753 ==
2527 22:19:56.597257 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 22:19:56.600438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 22:19:56.600506 ==
2530 22:19:56.603488 [Gating] SW mode calibration
2531 22:19:56.610370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 22:19:56.616858 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 22:19:56.620335 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2534 22:19:56.623916 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2535 22:19:56.630407 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2536 22:19:56.633409 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 22:19:56.637232 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 22:19:56.643551 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 22:19:56.646706 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 22:19:56.650508 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2541 22:19:56.657144 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
2542 22:19:56.660117 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2543 22:19:56.663282 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:19:56.669906 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 22:19:56.673671 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 22:19:56.676482 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 22:19:56.683342 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 22:19:56.686767 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2549 22:19:56.690203 1 1 0 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
2550 22:19:56.696622 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2551 22:19:56.699767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:19:56.702943 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 22:19:56.709400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 22:19:56.712882 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 22:19:56.716165 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 22:19:56.723301 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2557 22:19:56.726316 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 22:19:56.729318 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 22:19:56.733368 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:19:56.739512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:19:56.742821 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:19:56.746304 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:19:56.752853 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:19:56.756487 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:19:56.759551 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:19:56.766019 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:19:56.769343 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:19:56.772487 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:19:56.779150 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:19:56.783142 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:19:56.786027 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:19:56.792687 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 22:19:56.795875 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 22:19:56.799240 Total UI for P1: 0, mck2ui 16
2575 22:19:56.802792 best dqsien dly found for B0: ( 1, 3, 28)
2576 22:19:56.806143 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 22:19:56.812511 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 22:19:56.812632 Total UI for P1: 0, mck2ui 16
2579 22:19:56.818927 best dqsien dly found for B1: ( 1, 4, 2)
2580 22:19:56.822624 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2581 22:19:56.825823 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2582 22:19:56.825904
2583 22:19:56.829345 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2584 22:19:56.833008 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2585 22:19:56.835684 [Gating] SW calibration Done
2586 22:19:56.835764 ==
2587 22:19:56.838875 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 22:19:56.842620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 22:19:56.842701 ==
2590 22:19:56.845988 RX Vref Scan: 0
2591 22:19:56.846068
2592 22:19:56.846131 RX Vref 0 -> 0, step: 1
2593 22:19:56.846188
2594 22:19:56.848989 RX Delay -40 -> 252, step: 8
2595 22:19:56.852398 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2596 22:19:56.859222 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2597 22:19:56.862404 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2598 22:19:56.865638 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2599 22:19:56.868984 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2600 22:19:56.872194 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2601 22:19:56.878690 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2602 22:19:56.882010 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2603 22:19:56.885633 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2604 22:19:56.888690 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2605 22:19:56.892013 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2606 22:19:56.898561 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2607 22:19:56.901815 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2608 22:19:56.905062 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2609 22:19:56.908959 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2610 22:19:56.915035 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2611 22:19:56.915125 ==
2612 22:19:56.918465 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 22:19:56.922188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 22:19:56.922269 ==
2615 22:19:56.922331 DQS Delay:
2616 22:19:56.924869 DQS0 = 0, DQS1 = 0
2617 22:19:56.924948 DQM Delay:
2618 22:19:56.928186 DQM0 = 119, DQM1 = 107
2619 22:19:56.928266 DQ Delay:
2620 22:19:56.931451 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2621 22:19:56.935014 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2622 22:19:56.937928 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2623 22:19:56.941359 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2624 22:19:56.941440
2625 22:19:56.941503
2626 22:19:56.941560 ==
2627 22:19:56.944948 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 22:19:56.951532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 22:19:56.951613 ==
2630 22:19:56.951677
2631 22:19:56.951735
2632 22:19:56.951790 TX Vref Scan disable
2633 22:19:56.955878 == TX Byte 0 ==
2634 22:19:56.958276 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2635 22:19:56.965389 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2636 22:19:56.965469 == TX Byte 1 ==
2637 22:19:56.968745 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2638 22:19:56.975051 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2639 22:19:56.975159 ==
2640 22:19:56.978671 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 22:19:56.981346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 22:19:56.981440 ==
2643 22:19:56.992986 TX Vref=22, minBit 13, minWin=24, winSum=415
2644 22:19:56.996697 TX Vref=24, minBit 13, minWin=25, winSum=424
2645 22:19:57.000004 TX Vref=26, minBit 1, minWin=25, winSum=425
2646 22:19:57.003189 TX Vref=28, minBit 5, minWin=26, winSum=430
2647 22:19:57.006464 TX Vref=30, minBit 4, minWin=26, winSum=431
2648 22:19:57.013360 TX Vref=32, minBit 5, minWin=26, winSum=429
2649 22:19:57.016385 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 30
2650 22:19:57.016466
2651 22:19:57.019628 Final TX Range 1 Vref 30
2652 22:19:57.019708
2653 22:19:57.019771 ==
2654 22:19:57.023196 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 22:19:57.026234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 22:19:57.026315 ==
2657 22:19:57.029633
2658 22:19:57.029714
2659 22:19:57.029777 TX Vref Scan disable
2660 22:19:57.033559 == TX Byte 0 ==
2661 22:19:57.036353 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2662 22:19:57.039816 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2663 22:19:57.042889 == TX Byte 1 ==
2664 22:19:57.046633 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2665 22:19:57.053544 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2666 22:19:57.053624
2667 22:19:57.053686 [DATLAT]
2668 22:19:57.053745 Freq=1200, CH0 RK0
2669 22:19:57.053804
2670 22:19:57.056843 DATLAT Default: 0xd
2671 22:19:57.056923 0, 0xFFFF, sum = 0
2672 22:19:57.059800 1, 0xFFFF, sum = 0
2673 22:19:57.063190 2, 0xFFFF, sum = 0
2674 22:19:57.063271 3, 0xFFFF, sum = 0
2675 22:19:57.065970 4, 0xFFFF, sum = 0
2676 22:19:57.066052 5, 0xFFFF, sum = 0
2677 22:19:57.069553 6, 0xFFFF, sum = 0
2678 22:19:57.069634 7, 0xFFFF, sum = 0
2679 22:19:57.072827 8, 0xFFFF, sum = 0
2680 22:19:57.072908 9, 0xFFFF, sum = 0
2681 22:19:57.076458 10, 0xFFFF, sum = 0
2682 22:19:57.076578 11, 0xFFFF, sum = 0
2683 22:19:57.079749 12, 0x0, sum = 1
2684 22:19:57.079830 13, 0x0, sum = 2
2685 22:19:57.082746 14, 0x0, sum = 3
2686 22:19:57.082827 15, 0x0, sum = 4
2687 22:19:57.086211 best_step = 13
2688 22:19:57.086291
2689 22:19:57.086354 ==
2690 22:19:57.089599 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 22:19:57.092752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 22:19:57.092833 ==
2693 22:19:57.092897 RX Vref Scan: 1
2694 22:19:57.092955
2695 22:19:57.096171 Set Vref Range= 32 -> 127
2696 22:19:57.096250
2697 22:19:57.099533 RX Vref 32 -> 127, step: 1
2698 22:19:57.099613
2699 22:19:57.102804 RX Delay -21 -> 252, step: 4
2700 22:19:57.102883
2701 22:19:57.106130 Set Vref, RX VrefLevel [Byte0]: 32
2702 22:19:57.109749 [Byte1]: 32
2703 22:19:57.109829
2704 22:19:57.112700 Set Vref, RX VrefLevel [Byte0]: 33
2705 22:19:57.116344 [Byte1]: 33
2706 22:19:57.119697
2707 22:19:57.119777 Set Vref, RX VrefLevel [Byte0]: 34
2708 22:19:57.123082 [Byte1]: 34
2709 22:19:57.127902
2710 22:19:57.127986 Set Vref, RX VrefLevel [Byte0]: 35
2711 22:19:57.131072 [Byte1]: 35
2712 22:19:57.135812
2713 22:19:57.135893 Set Vref, RX VrefLevel [Byte0]: 36
2714 22:19:57.138713 [Byte1]: 36
2715 22:19:57.143424
2716 22:19:57.143523 Set Vref, RX VrefLevel [Byte0]: 37
2717 22:19:57.149865 [Byte1]: 37
2718 22:19:57.149975
2719 22:19:57.152916 Set Vref, RX VrefLevel [Byte0]: 38
2720 22:19:57.156200 [Byte1]: 38
2721 22:19:57.156302
2722 22:19:57.159607 Set Vref, RX VrefLevel [Byte0]: 39
2723 22:19:57.162968 [Byte1]: 39
2724 22:19:57.167696
2725 22:19:57.167775 Set Vref, RX VrefLevel [Byte0]: 40
2726 22:19:57.170505 [Byte1]: 40
2727 22:19:57.174961
2728 22:19:57.175062 Set Vref, RX VrefLevel [Byte0]: 41
2729 22:19:57.178530 [Byte1]: 41
2730 22:19:57.183067
2731 22:19:57.183183 Set Vref, RX VrefLevel [Byte0]: 42
2732 22:19:57.186401 [Byte1]: 42
2733 22:19:57.191288
2734 22:19:57.191392 Set Vref, RX VrefLevel [Byte0]: 43
2735 22:19:57.194198 [Byte1]: 43
2736 22:19:57.198632
2737 22:19:57.198745 Set Vref, RX VrefLevel [Byte0]: 44
2738 22:19:57.202276 [Byte1]: 44
2739 22:19:57.206640
2740 22:19:57.206740 Set Vref, RX VrefLevel [Byte0]: 45
2741 22:19:57.209901 [Byte1]: 45
2742 22:19:57.214583
2743 22:19:57.214681 Set Vref, RX VrefLevel [Byte0]: 46
2744 22:19:57.218210 [Byte1]: 46
2745 22:19:57.223140
2746 22:19:57.223208 Set Vref, RX VrefLevel [Byte0]: 47
2747 22:19:57.226315 [Byte1]: 47
2748 22:19:57.230695
2749 22:19:57.230791 Set Vref, RX VrefLevel [Byte0]: 48
2750 22:19:57.234339 [Byte1]: 48
2751 22:19:57.238894
2752 22:19:57.238967 Set Vref, RX VrefLevel [Byte0]: 49
2753 22:19:57.241844 [Byte1]: 49
2754 22:19:57.246797
2755 22:19:57.246878 Set Vref, RX VrefLevel [Byte0]: 50
2756 22:19:57.250054 [Byte1]: 50
2757 22:19:57.254604
2758 22:19:57.254678 Set Vref, RX VrefLevel [Byte0]: 51
2759 22:19:57.257737 [Byte1]: 51
2760 22:19:57.262022
2761 22:19:57.262124 Set Vref, RX VrefLevel [Byte0]: 52
2762 22:19:57.265844 [Byte1]: 52
2763 22:19:57.270134
2764 22:19:57.270230 Set Vref, RX VrefLevel [Byte0]: 53
2765 22:19:57.273360 [Byte1]: 53
2766 22:19:57.278008
2767 22:19:57.278104 Set Vref, RX VrefLevel [Byte0]: 54
2768 22:19:57.281378 [Byte1]: 54
2769 22:19:57.286130
2770 22:19:57.286239 Set Vref, RX VrefLevel [Byte0]: 55
2771 22:19:57.289259 [Byte1]: 55
2772 22:19:57.294250
2773 22:19:57.294331 Set Vref, RX VrefLevel [Byte0]: 56
2774 22:19:57.298438 [Byte1]: 56
2775 22:19:57.302185
2776 22:19:57.302285 Set Vref, RX VrefLevel [Byte0]: 57
2777 22:19:57.305083 [Byte1]: 57
2778 22:19:57.310139
2779 22:19:57.310213 Set Vref, RX VrefLevel [Byte0]: 58
2780 22:19:57.313008 [Byte1]: 58
2781 22:19:57.317812
2782 22:19:57.317881 Set Vref, RX VrefLevel [Byte0]: 59
2783 22:19:57.321336 [Byte1]: 59
2784 22:19:57.325942
2785 22:19:57.326038 Set Vref, RX VrefLevel [Byte0]: 60
2786 22:19:57.329155 [Byte1]: 60
2787 22:19:57.333459
2788 22:19:57.333552 Set Vref, RX VrefLevel [Byte0]: 61
2789 22:19:57.337173 [Byte1]: 61
2790 22:19:57.341469
2791 22:19:57.341608 Set Vref, RX VrefLevel [Byte0]: 62
2792 22:19:57.345018 [Byte1]: 62
2793 22:19:57.349438
2794 22:19:57.349509 Set Vref, RX VrefLevel [Byte0]: 63
2795 22:19:57.353020 [Byte1]: 63
2796 22:19:57.357330
2797 22:19:57.357425 Set Vref, RX VrefLevel [Byte0]: 64
2798 22:19:57.360696 [Byte1]: 64
2799 22:19:57.365314
2800 22:19:57.365387 Set Vref, RX VrefLevel [Byte0]: 65
2801 22:19:57.368713 [Byte1]: 65
2802 22:19:57.373135
2803 22:19:57.373224 Set Vref, RX VrefLevel [Byte0]: 66
2804 22:19:57.376593 [Byte1]: 66
2805 22:19:57.381492
2806 22:19:57.381589 Set Vref, RX VrefLevel [Byte0]: 67
2807 22:19:57.385180 [Byte1]: 67
2808 22:19:57.389633
2809 22:19:57.389737 Set Vref, RX VrefLevel [Byte0]: 68
2810 22:19:57.392432 [Byte1]: 68
2811 22:19:57.397417
2812 22:19:57.397520 Set Vref, RX VrefLevel [Byte0]: 69
2813 22:19:57.400237 [Byte1]: 69
2814 22:19:57.404817
2815 22:19:57.404891 Set Vref, RX VrefLevel [Byte0]: 70
2816 22:19:57.407996 [Byte1]: 70
2817 22:19:57.412882
2818 22:19:57.412958 Set Vref, RX VrefLevel [Byte0]: 71
2819 22:19:57.416321 [Byte1]: 71
2820 22:19:57.421273
2821 22:19:57.421342 Set Vref, RX VrefLevel [Byte0]: 72
2822 22:19:57.423934 [Byte1]: 72
2823 22:19:57.428909
2824 22:19:57.428978 Set Vref, RX VrefLevel [Byte0]: 73
2825 22:19:57.431887 [Byte1]: 73
2826 22:19:57.436909
2827 22:19:57.437048 Set Vref, RX VrefLevel [Byte0]: 74
2828 22:19:57.439853 [Byte1]: 74
2829 22:19:57.444571
2830 22:19:57.444662 Set Vref, RX VrefLevel [Byte0]: 75
2831 22:19:57.447724 [Byte1]: 75
2832 22:19:57.452839
2833 22:19:57.452953 Set Vref, RX VrefLevel [Byte0]: 76
2834 22:19:57.456269 [Byte1]: 76
2835 22:19:57.460466
2836 22:19:57.460615 Set Vref, RX VrefLevel [Byte0]: 77
2837 22:19:57.463976 [Byte1]: 77
2838 22:19:57.468725
2839 22:19:57.468804 Final RX Vref Byte 0 = 61 to rank0
2840 22:19:57.471514 Final RX Vref Byte 1 = 57 to rank0
2841 22:19:57.475164 Final RX Vref Byte 0 = 61 to rank1
2842 22:19:57.478779 Final RX Vref Byte 1 = 57 to rank1==
2843 22:19:57.481520 Dram Type= 6, Freq= 0, CH_0, rank 0
2844 22:19:57.488726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 22:19:57.488831 ==
2846 22:19:57.488897 DQS Delay:
2847 22:19:57.488956 DQS0 = 0, DQS1 = 0
2848 22:19:57.491786 DQM Delay:
2849 22:19:57.491890 DQM0 = 119, DQM1 = 107
2850 22:19:57.494722 DQ Delay:
2851 22:19:57.498503 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2852 22:19:57.501443 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2853 22:19:57.504812 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =104
2854 22:19:57.508728 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2855 22:19:57.508825
2856 22:19:57.508913
2857 22:19:57.514768 [DQSOSCAuto] RK0, (LSB)MR18= 0xcf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2858 22:19:57.518327 CH0 RK0: MR19=403, MR18=CF8
2859 22:19:57.524650 CH0_RK0: MR19=0x403, MR18=0xCF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2860 22:19:57.524751
2861 22:19:57.528268 ----->DramcWriteLeveling(PI) begin...
2862 22:19:57.528365 ==
2863 22:19:57.531341 Dram Type= 6, Freq= 0, CH_0, rank 1
2864 22:19:57.534791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2865 22:19:57.537775 ==
2866 22:19:57.537845 Write leveling (Byte 0): 33 => 33
2867 22:19:57.541183 Write leveling (Byte 1): 31 => 31
2868 22:19:57.544809 DramcWriteLeveling(PI) end<-----
2869 22:19:57.544884
2870 22:19:57.544944 ==
2871 22:19:57.547752 Dram Type= 6, Freq= 0, CH_0, rank 1
2872 22:19:57.554288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 22:19:57.554386 ==
2874 22:19:57.557587 [Gating] SW mode calibration
2875 22:19:57.564712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2876 22:19:57.568091 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2877 22:19:57.574653 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2878 22:19:57.577438 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2879 22:19:57.580892 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 22:19:57.587790 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 22:19:57.591547 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 22:19:57.594291 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 22:19:57.600914 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2884 22:19:57.604331 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2885 22:19:57.607495 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2886 22:19:57.610767 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 22:19:57.617584 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 22:19:57.620830 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 22:19:57.624170 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 22:19:57.630905 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 22:19:57.634190 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 22:19:57.637366 1 0 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2893 22:19:57.644071 1 1 0 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
2894 22:19:57.647770 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 22:19:57.650669 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 22:19:57.657507 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 22:19:57.660839 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 22:19:57.663857 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 22:19:57.670555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 22:19:57.673970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2901 22:19:57.676950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 22:19:57.683715 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 22:19:57.686963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 22:19:57.690528 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 22:19:57.697324 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 22:19:57.700626 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 22:19:57.703801 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 22:19:57.710430 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 22:19:57.713978 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 22:19:57.717151 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 22:19:57.723652 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 22:19:57.726911 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 22:19:57.730264 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 22:19:57.736779 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 22:19:57.740142 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 22:19:57.743623 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2917 22:19:57.750162 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2918 22:19:57.753532 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 22:19:57.756887 Total UI for P1: 0, mck2ui 16
2920 22:19:57.760353 best dqsien dly found for B0: ( 1, 3, 30)
2921 22:19:57.763532 Total UI for P1: 0, mck2ui 16
2922 22:19:57.766836 best dqsien dly found for B1: ( 1, 3, 30)
2923 22:19:57.770125 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2924 22:19:57.773495 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2925 22:19:57.773575
2926 22:19:57.776503 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2927 22:19:57.779751 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2928 22:19:57.783224 [Gating] SW calibration Done
2929 22:19:57.783304 ==
2930 22:19:57.786657 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 22:19:57.789944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 22:19:57.790026 ==
2933 22:19:57.793427 RX Vref Scan: 0
2934 22:19:57.793507
2935 22:19:57.796877 RX Vref 0 -> 0, step: 1
2936 22:19:57.796957
2937 22:19:57.797021 RX Delay -40 -> 252, step: 8
2938 22:19:57.803361 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2939 22:19:57.807285 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2940 22:19:57.810525 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2941 22:19:57.813260 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2942 22:19:57.816505 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2943 22:19:57.823652 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2944 22:19:57.826338 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2945 22:19:57.829665 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2946 22:19:57.832860 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2947 22:19:57.837048 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2948 22:19:57.843450 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2949 22:19:57.846697 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2950 22:19:57.849624 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2951 22:19:57.853287 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2952 22:19:57.856531 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2953 22:19:57.863205 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2954 22:19:57.863286 ==
2955 22:19:57.866185 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 22:19:57.869918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 22:19:57.870000 ==
2958 22:19:57.870064 DQS Delay:
2959 22:19:57.873168 DQS0 = 0, DQS1 = 0
2960 22:19:57.873249 DQM Delay:
2961 22:19:57.876069 DQM0 = 117, DQM1 = 109
2962 22:19:57.876150 DQ Delay:
2963 22:19:57.879959 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2964 22:19:57.883378 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2965 22:19:57.886198 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2966 22:19:57.889821 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2967 22:19:57.889901
2968 22:19:57.889965
2969 22:19:57.893157 ==
2970 22:19:57.896413 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 22:19:57.899626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 22:19:57.899708 ==
2973 22:19:57.899773
2974 22:19:57.899832
2975 22:19:57.903321 TX Vref Scan disable
2976 22:19:57.903403 == TX Byte 0 ==
2977 22:19:57.909565 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2978 22:19:57.912660 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2979 22:19:57.912741 == TX Byte 1 ==
2980 22:19:57.916377 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2981 22:19:57.923031 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2982 22:19:57.923113 ==
2983 22:19:57.926371 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 22:19:57.929199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 22:19:57.929280 ==
2986 22:19:57.941572 TX Vref=22, minBit 1, minWin=26, winSum=419
2987 22:19:57.944828 TX Vref=24, minBit 1, minWin=26, winSum=424
2988 22:19:57.948220 TX Vref=26, minBit 12, minWin=25, winSum=428
2989 22:19:57.951958 TX Vref=28, minBit 13, minWin=25, winSum=432
2990 22:19:57.954979 TX Vref=30, minBit 10, minWin=26, winSum=431
2991 22:19:57.961405 TX Vref=32, minBit 10, minWin=25, winSum=427
2992 22:19:57.965293 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
2993 22:19:57.965374
2994 22:19:57.968317 Final TX Range 1 Vref 30
2995 22:19:57.968398
2996 22:19:57.968462 ==
2997 22:19:57.971963 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 22:19:57.974751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 22:19:57.977925 ==
3000 22:19:57.978005
3001 22:19:57.978068
3002 22:19:57.978127 TX Vref Scan disable
3003 22:19:57.981576 == TX Byte 0 ==
3004 22:19:57.985258 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3005 22:19:57.988687 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3006 22:19:57.991998 == TX Byte 1 ==
3007 22:19:57.995098 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3008 22:19:58.001991 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3009 22:19:58.002123
3010 22:19:58.002216 [DATLAT]
3011 22:19:58.002326 Freq=1200, CH0 RK1
3012 22:19:58.002414
3013 22:19:58.005185 DATLAT Default: 0xd
3014 22:19:58.005284 0, 0xFFFF, sum = 0
3015 22:19:58.008417 1, 0xFFFF, sum = 0
3016 22:19:58.011827 2, 0xFFFF, sum = 0
3017 22:19:58.011941 3, 0xFFFF, sum = 0
3018 22:19:58.014748 4, 0xFFFF, sum = 0
3019 22:19:58.014853 5, 0xFFFF, sum = 0
3020 22:19:58.018454 6, 0xFFFF, sum = 0
3021 22:19:58.018566 7, 0xFFFF, sum = 0
3022 22:19:58.021214 8, 0xFFFF, sum = 0
3023 22:19:58.021315 9, 0xFFFF, sum = 0
3024 22:19:58.024622 10, 0xFFFF, sum = 0
3025 22:19:58.024702 11, 0xFFFF, sum = 0
3026 22:19:58.028204 12, 0x0, sum = 1
3027 22:19:58.028319 13, 0x0, sum = 2
3028 22:19:58.032034 14, 0x0, sum = 3
3029 22:19:58.032145 15, 0x0, sum = 4
3030 22:19:58.034891 best_step = 13
3031 22:19:58.034998
3032 22:19:58.035089 ==
3033 22:19:58.038007 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 22:19:58.041721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 22:19:58.041822 ==
3036 22:19:58.041923 RX Vref Scan: 0
3037 22:19:58.042012
3038 22:19:58.045025 RX Vref 0 -> 0, step: 1
3039 22:19:58.045099
3040 22:19:58.048449 RX Delay -21 -> 252, step: 4
3041 22:19:58.051891 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3042 22:19:58.058288 iDelay=199, Bit 1, Center 120 (47 ~ 194) 148
3043 22:19:58.061854 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3044 22:19:58.064882 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3045 22:19:58.068241 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3046 22:19:58.071303 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3047 22:19:58.077820 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3048 22:19:58.081049 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3049 22:19:58.084710 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3050 22:19:58.087615 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3051 22:19:58.091106 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3052 22:19:58.098116 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3053 22:19:58.100767 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3054 22:19:58.104486 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3055 22:19:58.107590 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3056 22:19:58.114168 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3057 22:19:58.114286 ==
3058 22:19:58.117511 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 22:19:58.120520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 22:19:58.120627 ==
3061 22:19:58.120701 DQS Delay:
3062 22:19:58.124472 DQS0 = 0, DQS1 = 0
3063 22:19:58.124578 DQM Delay:
3064 22:19:58.127572 DQM0 = 116, DQM1 = 109
3065 22:19:58.127647 DQ Delay:
3066 22:19:58.130603 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3067 22:19:58.133926 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3068 22:19:58.137658 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =102
3069 22:19:58.140648 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3070 22:19:58.140723
3071 22:19:58.140783
3072 22:19:58.150510 [DQSOSCAuto] RK1, (LSB)MR18= 0xae3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 406 ps
3073 22:19:58.154348 CH0 RK1: MR19=403, MR18=AE3
3074 22:19:58.157184 CH0_RK1: MR19=0x403, MR18=0xAE3, DQSOSC=406, MR23=63, INC=39, DEC=26
3075 22:19:58.160449 [RxdqsGatingPostProcess] freq 1200
3076 22:19:58.167066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3077 22:19:58.170798 best DQS0 dly(2T, 0.5T) = (0, 11)
3078 22:19:58.174036 best DQS1 dly(2T, 0.5T) = (0, 12)
3079 22:19:58.177140 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3080 22:19:58.180438 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3081 22:19:58.184030 best DQS0 dly(2T, 0.5T) = (0, 11)
3082 22:19:58.186925 best DQS1 dly(2T, 0.5T) = (0, 11)
3083 22:19:58.190316 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3084 22:19:58.193752 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3085 22:19:58.196785 Pre-setting of DQS Precalculation
3086 22:19:58.200095 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3087 22:19:58.200211 ==
3088 22:19:58.203557 Dram Type= 6, Freq= 0, CH_1, rank 0
3089 22:19:58.206749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 22:19:58.206850 ==
3091 22:19:58.213434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 22:19:58.220204 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 22:19:58.227965 [CA 0] Center 37 (7~68) winsize 62
3094 22:19:58.231172 [CA 1] Center 37 (7~68) winsize 62
3095 22:19:58.234424 [CA 2] Center 34 (4~64) winsize 61
3096 22:19:58.237985 [CA 3] Center 33 (3~64) winsize 62
3097 22:19:58.240917 [CA 4] Center 34 (4~64) winsize 61
3098 22:19:58.244426 [CA 5] Center 33 (3~64) winsize 62
3099 22:19:58.244562
3100 22:19:58.247855 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 22:19:58.247927
3102 22:19:58.251295 [CATrainingPosCal] consider 1 rank data
3103 22:19:58.254626 u2DelayCellTimex100 = 270/100 ps
3104 22:19:58.257779 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 22:19:58.264011 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 22:19:58.267688 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 22:19:58.271119 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3108 22:19:58.274577 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3109 22:19:58.277929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3110 22:19:58.278003
3111 22:19:58.281101 CA PerBit enable=1, Macro0, CA PI delay=33
3112 22:19:58.281173
3113 22:19:58.284118 [CBTSetCACLKResult] CA Dly = 33
3114 22:19:58.288107 CS Dly: 5 (0~36)
3115 22:19:58.288220 ==
3116 22:19:58.291264 Dram Type= 6, Freq= 0, CH_1, rank 1
3117 22:19:58.294048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 22:19:58.294148 ==
3119 22:19:58.300788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 22:19:58.303934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 22:19:58.313704 [CA 0] Center 37 (7~67) winsize 61
3122 22:19:58.317217 [CA 1] Center 37 (7~68) winsize 62
3123 22:19:58.320094 [CA 2] Center 34 (4~65) winsize 62
3124 22:19:58.323818 [CA 3] Center 33 (3~64) winsize 62
3125 22:19:58.326694 [CA 4] Center 34 (4~64) winsize 61
3126 22:19:58.330066 [CA 5] Center 33 (3~64) winsize 62
3127 22:19:58.330179
3128 22:19:58.333666 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 22:19:58.333766
3130 22:19:58.336575 [CATrainingPosCal] consider 2 rank data
3131 22:19:58.339777 u2DelayCellTimex100 = 270/100 ps
3132 22:19:58.343037 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3133 22:19:58.350069 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 22:19:58.353198 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 22:19:58.356817 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3136 22:19:58.359964 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 22:19:58.363195 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3138 22:19:58.363291
3139 22:19:58.367119 CA PerBit enable=1, Macro0, CA PI delay=33
3140 22:19:58.367220
3141 22:19:58.369821 [CBTSetCACLKResult] CA Dly = 33
3142 22:19:58.369893 CS Dly: 7 (0~40)
3143 22:19:58.373335
3144 22:19:58.376439 ----->DramcWriteLeveling(PI) begin...
3145 22:19:58.376558 ==
3146 22:19:58.379565 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 22:19:58.382847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 22:19:58.382947 ==
3149 22:19:58.386461 Write leveling (Byte 0): 24 => 24
3150 22:19:58.390032 Write leveling (Byte 1): 28 => 28
3151 22:19:58.393118 DramcWriteLeveling(PI) end<-----
3152 22:19:58.393212
3153 22:19:58.393298 ==
3154 22:19:58.396964 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 22:19:58.399894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 22:19:58.399963 ==
3157 22:19:58.403058 [Gating] SW mode calibration
3158 22:19:58.409601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3159 22:19:58.416139 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3160 22:19:58.419433 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3161 22:19:58.423089 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 22:19:58.429617 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 22:19:58.433342 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 22:19:58.436380 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 22:19:58.443443 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 22:19:58.446289 0 15 24 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
3167 22:19:58.449571 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
3168 22:19:58.456583 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 22:19:58.459913 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 22:19:58.462952 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 22:19:58.466214 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 22:19:58.472657 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 22:19:58.476373 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 22:19:58.482766 1 0 24 | B1->B0 | 2a2a 3838 | 0 0 | (1 1) (0 0)
3175 22:19:58.485996 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3176 22:19:58.489103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 22:19:58.492909 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 22:19:58.499180 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 22:19:58.502643 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 22:19:58.505852 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 22:19:58.512365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 22:19:58.516247 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3183 22:19:58.518937 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3184 22:19:58.525860 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 22:19:58.529789 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 22:19:58.532161 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 22:19:58.538749 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 22:19:58.542520 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 22:19:58.545668 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 22:19:58.552442 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 22:19:58.555472 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 22:19:58.559344 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 22:19:58.565658 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 22:19:58.569305 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 22:19:58.572395 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 22:19:58.579205 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 22:19:58.582470 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 22:19:58.585582 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3199 22:19:58.592499 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3200 22:19:58.595398 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 22:19:58.599248 Total UI for P1: 0, mck2ui 16
3202 22:19:58.602814 best dqsien dly found for B0: ( 1, 3, 26)
3203 22:19:58.605714 Total UI for P1: 0, mck2ui 16
3204 22:19:58.608892 best dqsien dly found for B1: ( 1, 3, 26)
3205 22:19:58.612008 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3206 22:19:58.615357 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3207 22:19:58.615454
3208 22:19:58.618987 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3209 22:19:58.622147 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3210 22:19:58.625106 [Gating] SW calibration Done
3211 22:19:58.625176 ==
3212 22:19:58.628404 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 22:19:58.632225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 22:19:58.632327 ==
3215 22:19:58.635088 RX Vref Scan: 0
3216 22:19:58.635200
3217 22:19:58.638420 RX Vref 0 -> 0, step: 1
3218 22:19:58.638516
3219 22:19:58.638604 RX Delay -40 -> 252, step: 8
3220 22:19:58.645293 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3221 22:19:58.648469 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3222 22:19:58.652326 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3223 22:19:58.655110 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3224 22:19:58.658521 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3225 22:19:58.665210 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3226 22:19:58.668174 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3227 22:19:58.672045 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3228 22:19:58.675067 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3229 22:19:58.678216 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3230 22:19:58.684988 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3231 22:19:58.688764 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3232 22:19:58.691632 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3233 22:19:58.695395 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3234 22:19:58.698623 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3235 22:19:58.705026 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3236 22:19:58.705100 ==
3237 22:19:58.708605 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 22:19:58.711659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 22:19:58.711775 ==
3240 22:19:58.711869 DQS Delay:
3241 22:19:58.715050 DQS0 = 0, DQS1 = 0
3242 22:19:58.715151 DQM Delay:
3243 22:19:58.718265 DQM0 = 118, DQM1 = 109
3244 22:19:58.718362 DQ Delay:
3245 22:19:58.721731 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3246 22:19:58.724954 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3247 22:19:58.728905 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3248 22:19:58.731979 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3249 22:19:58.732067
3250 22:19:58.732156
3251 22:19:58.735370 ==
3252 22:19:58.735473 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 22:19:58.741718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 22:19:58.741794 ==
3255 22:19:58.741890
3256 22:19:58.741977
3257 22:19:58.745050 TX Vref Scan disable
3258 22:19:58.745138 == TX Byte 0 ==
3259 22:19:58.748291 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3260 22:19:58.755244 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3261 22:19:58.755353 == TX Byte 1 ==
3262 22:19:58.758147 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3263 22:19:58.764753 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3264 22:19:58.764830 ==
3265 22:19:58.767995 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 22:19:58.771704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 22:19:58.771817 ==
3268 22:19:58.783445 TX Vref=22, minBit 10, minWin=24, winSum=411
3269 22:19:58.787239 TX Vref=24, minBit 8, minWin=25, winSum=425
3270 22:19:58.790006 TX Vref=26, minBit 9, minWin=25, winSum=427
3271 22:19:58.793723 TX Vref=28, minBit 9, minWin=25, winSum=429
3272 22:19:58.797076 TX Vref=30, minBit 9, minWin=25, winSum=428
3273 22:19:58.803619 TX Vref=32, minBit 8, minWin=25, winSum=423
3274 22:19:58.806724 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 28
3275 22:19:58.806831
3276 22:19:58.810239 Final TX Range 1 Vref 28
3277 22:19:58.810337
3278 22:19:58.810446 ==
3279 22:19:58.813916 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 22:19:58.816625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 22:19:58.816701 ==
3282 22:19:58.820133
3283 22:19:58.820235
3284 22:19:58.820323 TX Vref Scan disable
3285 22:19:58.823558 == TX Byte 0 ==
3286 22:19:58.827145 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3287 22:19:58.830004 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3288 22:19:58.833292 == TX Byte 1 ==
3289 22:19:58.836717 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3290 22:19:58.843552 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3291 22:19:58.843646
3292 22:19:58.843709 [DATLAT]
3293 22:19:58.843774 Freq=1200, CH1 RK0
3294 22:19:58.843868
3295 22:19:58.846390 DATLAT Default: 0xd
3296 22:19:58.846495 0, 0xFFFF, sum = 0
3297 22:19:58.849745 1, 0xFFFF, sum = 0
3298 22:19:58.853415 2, 0xFFFF, sum = 0
3299 22:19:58.853516 3, 0xFFFF, sum = 0
3300 22:19:58.856466 4, 0xFFFF, sum = 0
3301 22:19:58.856574 5, 0xFFFF, sum = 0
3302 22:19:58.859988 6, 0xFFFF, sum = 0
3303 22:19:58.860081 7, 0xFFFF, sum = 0
3304 22:19:58.863472 8, 0xFFFF, sum = 0
3305 22:19:58.863563 9, 0xFFFF, sum = 0
3306 22:19:58.866208 10, 0xFFFF, sum = 0
3307 22:19:58.866304 11, 0xFFFF, sum = 0
3308 22:19:58.869848 12, 0x0, sum = 1
3309 22:19:58.869948 13, 0x0, sum = 2
3310 22:19:58.872901 14, 0x0, sum = 3
3311 22:19:58.872974 15, 0x0, sum = 4
3312 22:19:58.876498 best_step = 13
3313 22:19:58.876591
3314 22:19:58.876695 ==
3315 22:19:58.879676 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 22:19:58.883078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 22:19:58.883176 ==
3318 22:19:58.883264 RX Vref Scan: 1
3319 22:19:58.886639
3320 22:19:58.886735 Set Vref Range= 32 -> 127
3321 22:19:58.886798
3322 22:19:58.889792 RX Vref 32 -> 127, step: 1
3323 22:19:58.889862
3324 22:19:58.892997 RX Delay -21 -> 252, step: 4
3325 22:19:58.893088
3326 22:19:58.896684 Set Vref, RX VrefLevel [Byte0]: 32
3327 22:19:58.899686 [Byte1]: 32
3328 22:19:58.899756
3329 22:19:58.902764 Set Vref, RX VrefLevel [Byte0]: 33
3330 22:19:58.906225 [Byte1]: 33
3331 22:19:58.909634
3332 22:19:58.909701 Set Vref, RX VrefLevel [Byte0]: 34
3333 22:19:58.912959 [Byte1]: 34
3334 22:19:58.917718
3335 22:19:58.917812 Set Vref, RX VrefLevel [Byte0]: 35
3336 22:19:58.920890 [Byte1]: 35
3337 22:19:58.925907
3338 22:19:58.925983 Set Vref, RX VrefLevel [Byte0]: 36
3339 22:19:58.928744 [Byte1]: 36
3340 22:19:58.933727
3341 22:19:58.933824 Set Vref, RX VrefLevel [Byte0]: 37
3342 22:19:58.937184 [Byte1]: 37
3343 22:19:58.941763
3344 22:19:58.941872 Set Vref, RX VrefLevel [Byte0]: 38
3345 22:19:58.945008 [Byte1]: 38
3346 22:19:58.949857
3347 22:19:58.949961 Set Vref, RX VrefLevel [Byte0]: 39
3348 22:19:58.952458 [Byte1]: 39
3349 22:19:58.957605
3350 22:19:58.957703 Set Vref, RX VrefLevel [Byte0]: 40
3351 22:19:58.961046 [Byte1]: 40
3352 22:19:58.965294
3353 22:19:58.965391 Set Vref, RX VrefLevel [Byte0]: 41
3354 22:19:58.969158 [Byte1]: 41
3355 22:19:58.973218
3356 22:19:58.973335 Set Vref, RX VrefLevel [Byte0]: 42
3357 22:19:58.976623 [Byte1]: 42
3358 22:19:58.981057
3359 22:19:58.981161 Set Vref, RX VrefLevel [Byte0]: 43
3360 22:19:58.984620 [Byte1]: 43
3361 22:19:58.989262
3362 22:19:58.989364 Set Vref, RX VrefLevel [Byte0]: 44
3363 22:19:58.992441 [Byte1]: 44
3364 22:19:58.996496
3365 22:19:59.000032 Set Vref, RX VrefLevel [Byte0]: 45
3366 22:19:59.003546 [Byte1]: 45
3367 22:19:59.003628
3368 22:19:59.006722 Set Vref, RX VrefLevel [Byte0]: 46
3369 22:19:59.010049 [Byte1]: 46
3370 22:19:59.010143
3371 22:19:59.013172 Set Vref, RX VrefLevel [Byte0]: 47
3372 22:19:59.016442 [Byte1]: 47
3373 22:19:59.020771
3374 22:19:59.020881 Set Vref, RX VrefLevel [Byte0]: 48
3375 22:19:59.024397 [Byte1]: 48
3376 22:19:59.028607
3377 22:19:59.028797 Set Vref, RX VrefLevel [Byte0]: 49
3378 22:19:59.032088 [Byte1]: 49
3379 22:19:59.036432
3380 22:19:59.036537 Set Vref, RX VrefLevel [Byte0]: 50
3381 22:19:59.040243 [Byte1]: 50
3382 22:19:59.044308
3383 22:19:59.044389 Set Vref, RX VrefLevel [Byte0]: 51
3384 22:19:59.047571 [Byte1]: 51
3385 22:19:59.052451
3386 22:19:59.052565 Set Vref, RX VrefLevel [Byte0]: 52
3387 22:19:59.055711 [Byte1]: 52
3388 22:19:59.060778
3389 22:19:59.060880 Set Vref, RX VrefLevel [Byte0]: 53
3390 22:19:59.063751 [Byte1]: 53
3391 22:19:59.068365
3392 22:19:59.068475 Set Vref, RX VrefLevel [Byte0]: 54
3393 22:19:59.071713 [Byte1]: 54
3394 22:19:59.076165
3395 22:19:59.076315 Set Vref, RX VrefLevel [Byte0]: 55
3396 22:19:59.079410 [Byte1]: 55
3397 22:19:59.084222
3398 22:19:59.084478 Set Vref, RX VrefLevel [Byte0]: 56
3399 22:19:59.087587 [Byte1]: 56
3400 22:19:59.092311
3401 22:19:59.092511 Set Vref, RX VrefLevel [Byte0]: 57
3402 22:19:59.095306 [Byte1]: 57
3403 22:19:59.101024
3404 22:19:59.101324 Set Vref, RX VrefLevel [Byte0]: 58
3405 22:19:59.103298 [Byte1]: 58
3406 22:19:59.108105
3407 22:19:59.108560 Set Vref, RX VrefLevel [Byte0]: 59
3408 22:19:59.111650 [Byte1]: 59
3409 22:19:59.116436
3410 22:19:59.116890 Set Vref, RX VrefLevel [Byte0]: 60
3411 22:19:59.119375 [Byte1]: 60
3412 22:19:59.123969
3413 22:19:59.124386 Set Vref, RX VrefLevel [Byte0]: 61
3414 22:19:59.127511 [Byte1]: 61
3415 22:19:59.131868
3416 22:19:59.132409 Set Vref, RX VrefLevel [Byte0]: 62
3417 22:19:59.135052 [Byte1]: 62
3418 22:19:59.139971
3419 22:19:59.140390 Set Vref, RX VrefLevel [Byte0]: 63
3420 22:19:59.143387 [Byte1]: 63
3421 22:19:59.147721
3422 22:19:59.148247 Set Vref, RX VrefLevel [Byte0]: 64
3423 22:19:59.150990 [Byte1]: 64
3424 22:19:59.156428
3425 22:19:59.157026 Set Vref, RX VrefLevel [Byte0]: 65
3426 22:19:59.159135 [Byte1]: 65
3427 22:19:59.164003
3428 22:19:59.164466 Set Vref, RX VrefLevel [Byte0]: 66
3429 22:19:59.166948 [Byte1]: 66
3430 22:19:59.171997
3431 22:19:59.172458 Final RX Vref Byte 0 = 50 to rank0
3432 22:19:59.175127 Final RX Vref Byte 1 = 53 to rank0
3433 22:19:59.178149 Final RX Vref Byte 0 = 50 to rank1
3434 22:19:59.182004 Final RX Vref Byte 1 = 53 to rank1==
3435 22:19:59.184714 Dram Type= 6, Freq= 0, CH_1, rank 0
3436 22:19:59.191670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 22:19:59.192254 ==
3438 22:19:59.192681 DQS Delay:
3439 22:19:59.194416 DQS0 = 0, DQS1 = 0
3440 22:19:59.194881 DQM Delay:
3441 22:19:59.195247 DQM0 = 115, DQM1 = 110
3442 22:19:59.198057 DQ Delay:
3443 22:19:59.201367 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =110
3444 22:19:59.204630 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3445 22:19:59.208335 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3446 22:19:59.211216 DQ12 =116, DQ13 =116, DQ14 =120, DQ15 =118
3447 22:19:59.211638
3448 22:19:59.211973
3449 22:19:59.221360 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 408 ps
3450 22:19:59.221971 CH1 RK0: MR19=403, MR18=5F9
3451 22:19:59.227631 CH1_RK0: MR19=0x403, MR18=0x5F9, DQSOSC=408, MR23=63, INC=39, DEC=26
3452 22:19:59.228214
3453 22:19:59.231384 ----->DramcWriteLeveling(PI) begin...
3454 22:19:59.231898 ==
3455 22:19:59.234232 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 22:19:59.237636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 22:19:59.240998 ==
3458 22:19:59.241549 Write leveling (Byte 0): 24 => 24
3459 22:19:59.244684 Write leveling (Byte 1): 28 => 28
3460 22:19:59.248076 DramcWriteLeveling(PI) end<-----
3461 22:19:59.248697
3462 22:19:59.249124 ==
3463 22:19:59.251125 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 22:19:59.257534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 22:19:59.257953 ==
3466 22:19:59.261499 [Gating] SW mode calibration
3467 22:19:59.268222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3468 22:19:59.270678 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3469 22:19:59.278144 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3470 22:19:59.281029 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 22:19:59.284482 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 22:19:59.290979 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3473 22:19:59.294710 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3474 22:19:59.297372 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 22:19:59.303966 0 15 24 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (0 0)
3476 22:19:59.307309 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3477 22:19:59.310449 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 22:19:59.317493 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 22:19:59.320444 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 22:19:59.323636 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3481 22:19:59.330572 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3482 22:19:59.333922 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 22:19:59.337236 1 0 24 | B1->B0 | 3535 2424 | 1 1 | (1 1) (0 0)
3484 22:19:59.343904 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 22:19:59.346669 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 22:19:59.349951 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 22:19:59.357029 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 22:19:59.359901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 22:19:59.363511 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 22:19:59.369719 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 22:19:59.373196 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3492 22:19:59.376605 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3493 22:19:59.383395 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 22:19:59.386509 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 22:19:59.390180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 22:19:59.396544 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 22:19:59.399692 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 22:19:59.403235 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 22:19:59.409306 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 22:19:59.412793 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 22:19:59.416021 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 22:19:59.423013 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 22:19:59.425905 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 22:19:59.429100 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 22:19:59.436155 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 22:19:59.439343 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 22:19:59.442465 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3508 22:19:59.449106 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3509 22:19:59.449612 Total UI for P1: 0, mck2ui 16
3510 22:19:59.452129 best dqsien dly found for B1: ( 1, 3, 24)
3511 22:19:59.459271 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 22:19:59.462154 Total UI for P1: 0, mck2ui 16
3513 22:19:59.465858 best dqsien dly found for B0: ( 1, 3, 28)
3514 22:19:59.468707 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3515 22:19:59.472011 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3516 22:19:59.472566
3517 22:19:59.475261 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3518 22:19:59.478701 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3519 22:19:59.482282 [Gating] SW calibration Done
3520 22:19:59.482844 ==
3521 22:19:59.485398 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 22:19:59.488849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 22:19:59.489421 ==
3524 22:19:59.492202 RX Vref Scan: 0
3525 22:19:59.492656
3526 22:19:59.495527 RX Vref 0 -> 0, step: 1
3527 22:19:59.496106
3528 22:19:59.496618 RX Delay -40 -> 252, step: 8
3529 22:19:59.501721 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3530 22:19:59.505402 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3531 22:19:59.508670 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3532 22:19:59.512025 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3533 22:19:59.518348 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3534 22:19:59.521801 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3535 22:19:59.525437 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3536 22:19:59.528013 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3537 22:19:59.531476 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3538 22:19:59.538186 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3539 22:19:59.541296 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3540 22:19:59.544851 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3541 22:19:59.547848 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3542 22:19:59.551725 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3543 22:19:59.558095 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3544 22:19:59.561276 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3545 22:19:59.561754 ==
3546 22:19:59.564936 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 22:19:59.567810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 22:19:59.568231 ==
3549 22:19:59.571218 DQS Delay:
3550 22:19:59.571777 DQS0 = 0, DQS1 = 0
3551 22:19:59.572232 DQM Delay:
3552 22:19:59.574737 DQM0 = 116, DQM1 = 110
3553 22:19:59.575161 DQ Delay:
3554 22:19:59.577803 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3555 22:19:59.581045 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3556 22:19:59.588075 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3557 22:19:59.590647 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3558 22:19:59.591066
3559 22:19:59.591399
3560 22:19:59.591709 ==
3561 22:19:59.594077 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 22:19:59.597330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 22:19:59.597926 ==
3564 22:19:59.598481
3565 22:19:59.598984
3566 22:19:59.600786 TX Vref Scan disable
3567 22:19:59.604792 == TX Byte 0 ==
3568 22:19:59.607880 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3569 22:19:59.610764 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3570 22:19:59.614162 == TX Byte 1 ==
3571 22:19:59.617355 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3572 22:19:59.621003 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3573 22:19:59.621419 ==
3574 22:19:59.623973 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 22:19:59.627081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 22:19:59.630792 ==
3577 22:19:59.640655 TX Vref=22, minBit 8, minWin=25, winSum=428
3578 22:19:59.643736 TX Vref=24, minBit 8, minWin=25, winSum=430
3579 22:19:59.647397 TX Vref=26, minBit 8, minWin=25, winSum=431
3580 22:19:59.650849 TX Vref=28, minBit 8, minWin=26, winSum=433
3581 22:19:59.653793 TX Vref=30, minBit 8, minWin=26, winSum=436
3582 22:19:59.660150 TX Vref=32, minBit 8, minWin=26, winSum=431
3583 22:19:59.663710 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3584 22:19:59.664212
3585 22:19:59.666890 Final TX Range 1 Vref 30
3586 22:19:59.667437
3587 22:19:59.667887 ==
3588 22:19:59.670663 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 22:19:59.673613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 22:19:59.676859 ==
3591 22:19:59.677275
3592 22:19:59.677602
3593 22:19:59.677904 TX Vref Scan disable
3594 22:19:59.680631 == TX Byte 0 ==
3595 22:19:59.684079 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3596 22:19:59.689887 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3597 22:19:59.690369 == TX Byte 1 ==
3598 22:19:59.694159 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3599 22:19:59.700434 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3600 22:19:59.700911
3601 22:19:59.701238 [DATLAT]
3602 22:19:59.701542 Freq=1200, CH1 RK1
3603 22:19:59.701836
3604 22:19:59.703440 DATLAT Default: 0xd
3605 22:19:59.706765 0, 0xFFFF, sum = 0
3606 22:19:59.707185 1, 0xFFFF, sum = 0
3607 22:19:59.709673 2, 0xFFFF, sum = 0
3608 22:19:59.710091 3, 0xFFFF, sum = 0
3609 22:19:59.713145 4, 0xFFFF, sum = 0
3610 22:19:59.713585 5, 0xFFFF, sum = 0
3611 22:19:59.716365 6, 0xFFFF, sum = 0
3612 22:19:59.716954 7, 0xFFFF, sum = 0
3613 22:19:59.719715 8, 0xFFFF, sum = 0
3614 22:19:59.720346 9, 0xFFFF, sum = 0
3615 22:19:59.722931 10, 0xFFFF, sum = 0
3616 22:19:59.723358 11, 0xFFFF, sum = 0
3617 22:19:59.726380 12, 0x0, sum = 1
3618 22:19:59.726806 13, 0x0, sum = 2
3619 22:19:59.730194 14, 0x0, sum = 3
3620 22:19:59.730746 15, 0x0, sum = 4
3621 22:19:59.733192 best_step = 13
3622 22:19:59.733612
3623 22:19:59.733943 ==
3624 22:19:59.736281 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 22:19:59.739813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 22:19:59.740290 ==
3627 22:19:59.743018 RX Vref Scan: 0
3628 22:19:59.743489
3629 22:19:59.743829 RX Vref 0 -> 0, step: 1
3630 22:19:59.744139
3631 22:19:59.746407 RX Delay -21 -> 252, step: 4
3632 22:19:59.752965 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3633 22:19:59.756244 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3634 22:19:59.759435 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3635 22:19:59.762739 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3636 22:19:59.765771 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3637 22:19:59.772756 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3638 22:19:59.775873 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3639 22:19:59.779885 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3640 22:19:59.782277 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3641 22:19:59.785686 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3642 22:19:59.792574 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3643 22:19:59.795447 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3644 22:19:59.799148 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3645 22:19:59.802254 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3646 22:19:59.809209 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3647 22:19:59.811813 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3648 22:19:59.812477 ==
3649 22:19:59.815390 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 22:19:59.819075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 22:19:59.819673 ==
3652 22:19:59.822148 DQS Delay:
3653 22:19:59.822734 DQS0 = 0, DQS1 = 0
3654 22:19:59.823285 DQM Delay:
3655 22:19:59.825124 DQM0 = 116, DQM1 = 110
3656 22:19:59.825775 DQ Delay:
3657 22:19:59.828340 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3658 22:19:59.831948 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =114
3659 22:19:59.835617 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =98
3660 22:19:59.841698 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =120
3661 22:19:59.842344
3662 22:19:59.842956
3663 22:19:59.848145 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
3664 22:19:59.851504 CH1 RK1: MR19=303, MR18=F6F2
3665 22:19:59.857851 CH1_RK1: MR19=0x303, MR18=0xF6F2, DQSOSC=414, MR23=63, INC=38, DEC=25
3666 22:19:59.861003 [RxdqsGatingPostProcess] freq 1200
3667 22:19:59.864255 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3668 22:19:59.867762 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 22:19:59.871214 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 22:19:59.874243 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 22:19:59.877903 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 22:19:59.881219 best DQS0 dly(2T, 0.5T) = (0, 11)
3673 22:19:59.884248 best DQS1 dly(2T, 0.5T) = (0, 11)
3674 22:19:59.887989 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3675 22:19:59.891148 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3676 22:19:59.894134 Pre-setting of DQS Precalculation
3677 22:19:59.897363 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3678 22:19:59.907966 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3679 22:19:59.913987 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3680 22:19:59.914219
3681 22:19:59.914475
3682 22:19:59.917788 [Calibration Summary] 2400 Mbps
3683 22:19:59.918055 CH 0, Rank 0
3684 22:19:59.920452 SW Impedance : PASS
3685 22:19:59.923988 DUTY Scan : NO K
3686 22:19:59.924209 ZQ Calibration : PASS
3687 22:19:59.927349 Jitter Meter : NO K
3688 22:19:59.927570 CBT Training : PASS
3689 22:19:59.930736 Write leveling : PASS
3690 22:19:59.934054 RX DQS gating : PASS
3691 22:19:59.934405 RX DQ/DQS(RDDQC) : PASS
3692 22:19:59.937576 TX DQ/DQS : PASS
3693 22:19:59.940766 RX DATLAT : PASS
3694 22:19:59.941180 RX DQ/DQS(Engine): PASS
3695 22:19:59.944460 TX OE : NO K
3696 22:19:59.944904 All Pass.
3697 22:19:59.945231
3698 22:19:59.947063 CH 0, Rank 1
3699 22:19:59.947478 SW Impedance : PASS
3700 22:19:59.950645 DUTY Scan : NO K
3701 22:19:59.953903 ZQ Calibration : PASS
3702 22:19:59.954317 Jitter Meter : NO K
3703 22:19:59.957271 CBT Training : PASS
3704 22:19:59.960442 Write leveling : PASS
3705 22:19:59.960893 RX DQS gating : PASS
3706 22:19:59.963915 RX DQ/DQS(RDDQC) : PASS
3707 22:19:59.967275 TX DQ/DQS : PASS
3708 22:19:59.967693 RX DATLAT : PASS
3709 22:19:59.970483 RX DQ/DQS(Engine): PASS
3710 22:19:59.973636 TX OE : NO K
3711 22:19:59.974050 All Pass.
3712 22:19:59.974376
3713 22:19:59.974674 CH 1, Rank 0
3714 22:19:59.976845 SW Impedance : PASS
3715 22:19:59.980510 DUTY Scan : NO K
3716 22:19:59.980952 ZQ Calibration : PASS
3717 22:19:59.983892 Jitter Meter : NO K
3718 22:19:59.986729 CBT Training : PASS
3719 22:19:59.987143 Write leveling : PASS
3720 22:19:59.990177 RX DQS gating : PASS
3721 22:19:59.993474 RX DQ/DQS(RDDQC) : PASS
3722 22:19:59.993886 TX DQ/DQS : PASS
3723 22:19:59.996933 RX DATLAT : PASS
3724 22:19:59.997347 RX DQ/DQS(Engine): PASS
3725 22:20:00.000405 TX OE : NO K
3726 22:20:00.000864 All Pass.
3727 22:20:00.001195
3728 22:20:00.003451 CH 1, Rank 1
3729 22:20:00.003864 SW Impedance : PASS
3730 22:20:00.006463 DUTY Scan : NO K
3731 22:20:00.009697 ZQ Calibration : PASS
3732 22:20:00.010112 Jitter Meter : NO K
3733 22:20:00.013061 CBT Training : PASS
3734 22:20:00.016674 Write leveling : PASS
3735 22:20:00.017091 RX DQS gating : PASS
3736 22:20:00.019670 RX DQ/DQS(RDDQC) : PASS
3737 22:20:00.023095 TX DQ/DQS : PASS
3738 22:20:00.023549 RX DATLAT : PASS
3739 22:20:00.026246 RX DQ/DQS(Engine): PASS
3740 22:20:00.029655 TX OE : NO K
3741 22:20:00.030077 All Pass.
3742 22:20:00.030408
3743 22:20:00.032951 DramC Write-DBI off
3744 22:20:00.033380 PER_BANK_REFRESH: Hybrid Mode
3745 22:20:00.036182 TX_TRACKING: ON
3746 22:20:00.046120 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3747 22:20:00.049551 [FAST_K] Save calibration result to emmc
3748 22:20:00.052897 dramc_set_vcore_voltage set vcore to 650000
3749 22:20:00.053467 Read voltage for 600, 5
3750 22:20:00.055924 Vio18 = 0
3751 22:20:00.056338 Vcore = 650000
3752 22:20:00.056728 Vdram = 0
3753 22:20:00.059434 Vddq = 0
3754 22:20:00.059851 Vmddr = 0
3755 22:20:00.065893 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3756 22:20:00.069092 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3757 22:20:00.072219 MEM_TYPE=3, freq_sel=19
3758 22:20:00.075352 sv_algorithm_assistance_LP4_1600
3759 22:20:00.078696 ============ PULL DRAM RESETB DOWN ============
3760 22:20:00.081963 ========== PULL DRAM RESETB DOWN end =========
3761 22:20:00.089022 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3762 22:20:00.092134 ===================================
3763 22:20:00.092581 LPDDR4 DRAM CONFIGURATION
3764 22:20:00.095228 ===================================
3765 22:20:00.098945 EX_ROW_EN[0] = 0x0
3766 22:20:00.102099 EX_ROW_EN[1] = 0x0
3767 22:20:00.102516 LP4Y_EN = 0x0
3768 22:20:00.105090 WORK_FSP = 0x0
3769 22:20:00.105507 WL = 0x2
3770 22:20:00.108460 RL = 0x2
3771 22:20:00.108941 BL = 0x2
3772 22:20:00.111643 RPST = 0x0
3773 22:20:00.112063 RD_PRE = 0x0
3774 22:20:00.115113 WR_PRE = 0x1
3775 22:20:00.115532 WR_PST = 0x0
3776 22:20:00.118554 DBI_WR = 0x0
3777 22:20:00.119143 DBI_RD = 0x0
3778 22:20:00.121656 OTF = 0x1
3779 22:20:00.124914 ===================================
3780 22:20:00.128279 ===================================
3781 22:20:00.128864 ANA top config
3782 22:20:00.131507 ===================================
3783 22:20:00.134941 DLL_ASYNC_EN = 0
3784 22:20:00.138501 ALL_SLAVE_EN = 1
3785 22:20:00.141359 NEW_RANK_MODE = 1
3786 22:20:00.141643 DLL_IDLE_MODE = 1
3787 22:20:00.144678 LP45_APHY_COMB_EN = 1
3788 22:20:00.148252 TX_ODT_DIS = 1
3789 22:20:00.151513 NEW_8X_MODE = 1
3790 22:20:00.154630 ===================================
3791 22:20:00.157944 ===================================
3792 22:20:00.161104 data_rate = 1200
3793 22:20:00.161261 CKR = 1
3794 22:20:00.164686 DQ_P2S_RATIO = 8
3795 22:20:00.167828 ===================================
3796 22:20:00.171764 CA_P2S_RATIO = 8
3797 22:20:00.174400 DQ_CA_OPEN = 0
3798 22:20:00.178331 DQ_SEMI_OPEN = 0
3799 22:20:00.181173 CA_SEMI_OPEN = 0
3800 22:20:00.181343 CA_FULL_RATE = 0
3801 22:20:00.184551 DQ_CKDIV4_EN = 1
3802 22:20:00.187646 CA_CKDIV4_EN = 1
3803 22:20:00.191096 CA_PREDIV_EN = 0
3804 22:20:00.194260 PH8_DLY = 0
3805 22:20:00.197513 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3806 22:20:00.197685 DQ_AAMCK_DIV = 4
3807 22:20:00.200691 CA_AAMCK_DIV = 4
3808 22:20:00.204174 CA_ADMCK_DIV = 4
3809 22:20:00.207808 DQ_TRACK_CA_EN = 0
3810 22:20:00.210906 CA_PICK = 600
3811 22:20:00.214049 CA_MCKIO = 600
3812 22:20:00.217835 MCKIO_SEMI = 0
3813 22:20:00.218001 PLL_FREQ = 2288
3814 22:20:00.220641 DQ_UI_PI_RATIO = 32
3815 22:20:00.223850 CA_UI_PI_RATIO = 0
3816 22:20:00.227292 ===================================
3817 22:20:00.230725 ===================================
3818 22:20:00.234211 memory_type:LPDDR4
3819 22:20:00.237016 GP_NUM : 10
3820 22:20:00.237178 SRAM_EN : 1
3821 22:20:00.240704 MD32_EN : 0
3822 22:20:00.243848 ===================================
3823 22:20:00.244013 [ANA_INIT] >>>>>>>>>>>>>>
3824 22:20:00.247408 <<<<<< [CONFIGURE PHASE]: ANA_TX
3825 22:20:00.250979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3826 22:20:00.253387 ===================================
3827 22:20:00.256762 data_rate = 1200,PCW = 0X5800
3828 22:20:00.260544 ===================================
3829 22:20:00.263608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3830 22:20:00.270074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3831 22:20:00.276978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3832 22:20:00.279981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3833 22:20:00.283207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3834 22:20:00.286358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3835 22:20:00.289981 [ANA_INIT] flow start
3836 22:20:00.290105 [ANA_INIT] PLL >>>>>>>>
3837 22:20:00.293275 [ANA_INIT] PLL <<<<<<<<
3838 22:20:00.296452 [ANA_INIT] MIDPI >>>>>>>>
3839 22:20:00.299872 [ANA_INIT] MIDPI <<<<<<<<
3840 22:20:00.299987 [ANA_INIT] DLL >>>>>>>>
3841 22:20:00.303263 [ANA_INIT] flow end
3842 22:20:00.306738 ============ LP4 DIFF to SE enter ============
3843 22:20:00.309393 ============ LP4 DIFF to SE exit ============
3844 22:20:00.312897 [ANA_INIT] <<<<<<<<<<<<<
3845 22:20:00.316340 [Flow] Enable top DCM control >>>>>
3846 22:20:00.319506 [Flow] Enable top DCM control <<<<<
3847 22:20:00.322704 Enable DLL master slave shuffle
3848 22:20:00.329795 ==============================================================
3849 22:20:00.330156 Gating Mode config
3850 22:20:00.336251 ==============================================================
3851 22:20:00.336705 Config description:
3852 22:20:00.346001 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3853 22:20:00.352419 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3854 22:20:00.358996 SELPH_MODE 0: By rank 1: By Phase
3855 22:20:00.362052 ==============================================================
3856 22:20:00.365915 GAT_TRACK_EN = 1
3857 22:20:00.369499 RX_GATING_MODE = 2
3858 22:20:00.372073 RX_GATING_TRACK_MODE = 2
3859 22:20:00.375388 SELPH_MODE = 1
3860 22:20:00.378909 PICG_EARLY_EN = 1
3861 22:20:00.382127 VALID_LAT_VALUE = 1
3862 22:20:00.388785 ==============================================================
3863 22:20:00.392190 Enter into Gating configuration >>>>
3864 22:20:00.395541 Exit from Gating configuration <<<<
3865 22:20:00.398568 Enter into DVFS_PRE_config >>>>>
3866 22:20:00.408727 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3867 22:20:00.411899 Exit from DVFS_PRE_config <<<<<
3868 22:20:00.414929 Enter into PICG configuration >>>>
3869 22:20:00.418467 Exit from PICG configuration <<<<
3870 22:20:00.421930 [RX_INPUT] configuration >>>>>
3871 22:20:00.422012 [RX_INPUT] configuration <<<<<
3872 22:20:00.428176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3873 22:20:00.434920 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3874 22:20:00.441444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 22:20:00.444962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 22:20:00.451463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3877 22:20:00.458279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3878 22:20:00.461299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3879 22:20:00.467993 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3880 22:20:00.471310 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3881 22:20:00.474572 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3882 22:20:00.478218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3883 22:20:00.484665 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3884 22:20:00.487923 ===================================
3885 22:20:00.488004 LPDDR4 DRAM CONFIGURATION
3886 22:20:00.490783 ===================================
3887 22:20:00.494618 EX_ROW_EN[0] = 0x0
3888 22:20:00.497307 EX_ROW_EN[1] = 0x0
3889 22:20:00.497387 LP4Y_EN = 0x0
3890 22:20:00.500792 WORK_FSP = 0x0
3891 22:20:00.500873 WL = 0x2
3892 22:20:00.503914 RL = 0x2
3893 22:20:00.503994 BL = 0x2
3894 22:20:00.507418 RPST = 0x0
3895 22:20:00.507498 RD_PRE = 0x0
3896 22:20:00.510527 WR_PRE = 0x1
3897 22:20:00.510607 WR_PST = 0x0
3898 22:20:00.513719 DBI_WR = 0x0
3899 22:20:00.513799 DBI_RD = 0x0
3900 22:20:00.517344 OTF = 0x1
3901 22:20:00.520442 ===================================
3902 22:20:00.523919 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3903 22:20:00.527354 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3904 22:20:00.533935 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3905 22:20:00.536882 ===================================
3906 22:20:00.536962 LPDDR4 DRAM CONFIGURATION
3907 22:20:00.540429 ===================================
3908 22:20:00.543440 EX_ROW_EN[0] = 0x10
3909 22:20:00.547112 EX_ROW_EN[1] = 0x0
3910 22:20:00.547193 LP4Y_EN = 0x0
3911 22:20:00.550251 WORK_FSP = 0x0
3912 22:20:00.550331 WL = 0x2
3913 22:20:00.553475 RL = 0x2
3914 22:20:00.553615 BL = 0x2
3915 22:20:00.556880 RPST = 0x0
3916 22:20:00.556960 RD_PRE = 0x0
3917 22:20:00.559846 WR_PRE = 0x1
3918 22:20:00.559927 WR_PST = 0x0
3919 22:20:00.563366 DBI_WR = 0x0
3920 22:20:00.563447 DBI_RD = 0x0
3921 22:20:00.566685 OTF = 0x1
3922 22:20:00.569731 ===================================
3923 22:20:00.576210 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3924 22:20:00.579897 nWR fixed to 30
3925 22:20:00.583527 [ModeRegInit_LP4] CH0 RK0
3926 22:20:00.583621 [ModeRegInit_LP4] CH0 RK1
3927 22:20:00.586540 [ModeRegInit_LP4] CH1 RK0
3928 22:20:00.589715 [ModeRegInit_LP4] CH1 RK1
3929 22:20:00.589798 match AC timing 17
3930 22:20:00.597003 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3931 22:20:00.599639 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3932 22:20:00.603468 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3933 22:20:00.609383 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3934 22:20:00.612732 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3935 22:20:00.612815 ==
3936 22:20:00.616655 Dram Type= 6, Freq= 0, CH_0, rank 0
3937 22:20:00.619374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 22:20:00.619458 ==
3939 22:20:00.626187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 22:20:00.632804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 22:20:00.635677 [CA 0] Center 36 (6~66) winsize 61
3942 22:20:00.639426 [CA 1] Center 36 (6~66) winsize 61
3943 22:20:00.642515 [CA 2] Center 34 (4~64) winsize 61
3944 22:20:00.645785 [CA 3] Center 34 (4~65) winsize 62
3945 22:20:00.648828 [CA 4] Center 33 (3~64) winsize 62
3946 22:20:00.652147 [CA 5] Center 33 (3~64) winsize 62
3947 22:20:00.652228
3948 22:20:00.655726 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 22:20:00.655808
3950 22:20:00.658736 [CATrainingPosCal] consider 1 rank data
3951 22:20:00.662505 u2DelayCellTimex100 = 270/100 ps
3952 22:20:00.665444 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3953 22:20:00.669053 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3954 22:20:00.672169 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3955 22:20:00.679036 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 22:20:00.682017 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3957 22:20:00.685126 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 22:20:00.685201
3959 22:20:00.688717 CA PerBit enable=1, Macro0, CA PI delay=33
3960 22:20:00.688792
3961 22:20:00.691683 [CBTSetCACLKResult] CA Dly = 33
3962 22:20:00.691801 CS Dly: 5 (0~36)
3963 22:20:00.691861 ==
3964 22:20:00.694976 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 22:20:00.701630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 22:20:00.701709 ==
3967 22:20:00.705359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 22:20:00.711598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3969 22:20:00.715331 [CA 0] Center 36 (6~66) winsize 61
3970 22:20:00.718632 [CA 1] Center 36 (6~66) winsize 61
3971 22:20:00.721677 [CA 2] Center 34 (3~65) winsize 63
3972 22:20:00.725341 [CA 3] Center 34 (4~64) winsize 61
3973 22:20:00.728287 [CA 4] Center 33 (3~64) winsize 62
3974 22:20:00.732162 [CA 5] Center 33 (3~64) winsize 62
3975 22:20:00.732242
3976 22:20:00.735011 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3977 22:20:00.735092
3978 22:20:00.738071 [CATrainingPosCal] consider 2 rank data
3979 22:20:00.741465 u2DelayCellTimex100 = 270/100 ps
3980 22:20:00.745114 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3981 22:20:00.751312 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3982 22:20:00.755000 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3983 22:20:00.758052 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3984 22:20:00.761425 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3985 22:20:00.764764 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3986 22:20:00.764844
3987 22:20:00.768244 CA PerBit enable=1, Macro0, CA PI delay=33
3988 22:20:00.768325
3989 22:20:00.771489 [CBTSetCACLKResult] CA Dly = 33
3990 22:20:00.771569 CS Dly: 6 (0~38)
3991 22:20:00.775118
3992 22:20:00.778220 ----->DramcWriteLeveling(PI) begin...
3993 22:20:00.778301 ==
3994 22:20:00.781230 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 22:20:00.784451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 22:20:00.784554 ==
3997 22:20:00.787932 Write leveling (Byte 0): 35 => 35
3998 22:20:00.791329 Write leveling (Byte 1): 31 => 31
3999 22:20:00.794735 DramcWriteLeveling(PI) end<-----
4000 22:20:00.794815
4001 22:20:00.794878 ==
4002 22:20:00.798036 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 22:20:00.800809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 22:20:00.800892 ==
4005 22:20:00.804118 [Gating] SW mode calibration
4006 22:20:00.811088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4007 22:20:00.818179 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4008 22:20:00.820910 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 22:20:00.824155 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4010 22:20:00.830778 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4011 22:20:00.834180 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4012 22:20:00.837678 0 9 16 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
4013 22:20:00.844438 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 22:20:00.847352 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 22:20:00.850962 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 22:20:00.857221 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 22:20:00.860493 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4018 22:20:00.864070 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 22:20:00.870551 0 10 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4020 22:20:00.873847 0 10 16 | B1->B0 | 3535 4343 | 0 0 | (0 0) (1 1)
4021 22:20:00.877218 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 22:20:00.883905 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 22:20:00.886951 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 22:20:00.890422 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 22:20:00.897780 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 22:20:00.900068 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 22:20:00.903341 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4028 22:20:00.910040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4029 22:20:00.913490 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 22:20:00.917392 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 22:20:00.923251 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 22:20:00.926854 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 22:20:00.930217 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 22:20:00.936219 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 22:20:00.939890 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 22:20:00.942897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 22:20:00.949697 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 22:20:00.952619 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 22:20:00.956180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 22:20:00.962995 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 22:20:00.966367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 22:20:00.969250 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 22:20:00.976177 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4044 22:20:00.976270 Total UI for P1: 0, mck2ui 16
4045 22:20:00.982617 best dqsien dly found for B0: ( 0, 13, 10)
4046 22:20:00.985872 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 22:20:00.989199 Total UI for P1: 0, mck2ui 16
4048 22:20:00.992258 best dqsien dly found for B1: ( 0, 13, 14)
4049 22:20:00.995640 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4050 22:20:00.999104 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4051 22:20:00.999184
4052 22:20:01.002317 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4053 22:20:01.005798 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4054 22:20:01.008942 [Gating] SW calibration Done
4055 22:20:01.009026 ==
4056 22:20:01.012195 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 22:20:01.015440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 22:20:01.019179 ==
4059 22:20:01.019254 RX Vref Scan: 0
4060 22:20:01.019325
4061 22:20:01.022832 RX Vref 0 -> 0, step: 1
4062 22:20:01.022934
4063 22:20:01.025443 RX Delay -230 -> 252, step: 16
4064 22:20:01.028955 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4065 22:20:01.032169 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4066 22:20:01.035141 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4067 22:20:01.042319 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4068 22:20:01.045269 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4069 22:20:01.048607 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4070 22:20:01.051746 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4071 22:20:01.058781 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4072 22:20:01.061784 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4073 22:20:01.064880 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4074 22:20:01.068392 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4075 22:20:01.071769 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4076 22:20:01.078126 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4077 22:20:01.081746 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4078 22:20:01.084989 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4079 22:20:01.091514 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4080 22:20:01.091596 ==
4081 22:20:01.094480 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 22:20:01.098363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 22:20:01.098440 ==
4084 22:20:01.098504 DQS Delay:
4085 22:20:01.101094 DQS0 = 0, DQS1 = 0
4086 22:20:01.101170 DQM Delay:
4087 22:20:01.104521 DQM0 = 44, DQM1 = 34
4088 22:20:01.104635 DQ Delay:
4089 22:20:01.107645 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4090 22:20:01.110887 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4091 22:20:01.114632 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4092 22:20:01.117621 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4093 22:20:01.117694
4094 22:20:01.117757
4095 22:20:01.117817 ==
4096 22:20:01.121211 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 22:20:01.124432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 22:20:01.124506 ==
4099 22:20:01.124592
4100 22:20:01.128179
4101 22:20:01.128243 TX Vref Scan disable
4102 22:20:01.131032 == TX Byte 0 ==
4103 22:20:01.134355 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4104 22:20:01.137408 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4105 22:20:01.141161 == TX Byte 1 ==
4106 22:20:01.144417 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4107 22:20:01.147888 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4108 22:20:01.147960 ==
4109 22:20:01.150776 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 22:20:01.157657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 22:20:01.157738 ==
4112 22:20:01.157862
4113 22:20:01.157920
4114 22:20:01.160743 TX Vref Scan disable
4115 22:20:01.160853 == TX Byte 0 ==
4116 22:20:01.167030 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4117 22:20:01.170250 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4118 22:20:01.170317 == TX Byte 1 ==
4119 22:20:01.177505 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4120 22:20:01.180664 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4121 22:20:01.180736
4122 22:20:01.180796 [DATLAT]
4123 22:20:01.183589 Freq=600, CH0 RK0
4124 22:20:01.183653
4125 22:20:01.183714 DATLAT Default: 0x9
4126 22:20:01.187272 0, 0xFFFF, sum = 0
4127 22:20:01.187339 1, 0xFFFF, sum = 0
4128 22:20:01.190311 2, 0xFFFF, sum = 0
4129 22:20:01.193816 3, 0xFFFF, sum = 0
4130 22:20:01.193888 4, 0xFFFF, sum = 0
4131 22:20:01.197004 5, 0xFFFF, sum = 0
4132 22:20:01.197068 6, 0xFFFF, sum = 0
4133 22:20:01.200219 7, 0xFFFF, sum = 0
4134 22:20:01.200336 8, 0x0, sum = 1
4135 22:20:01.200425 9, 0x0, sum = 2
4136 22:20:01.203953 10, 0x0, sum = 3
4137 22:20:01.204035 11, 0x0, sum = 4
4138 22:20:01.206720 best_step = 9
4139 22:20:01.206800
4140 22:20:01.206864 ==
4141 22:20:01.210379 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 22:20:01.213224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 22:20:01.213302 ==
4144 22:20:01.216696 RX Vref Scan: 1
4145 22:20:01.216767
4146 22:20:01.216828 RX Vref 0 -> 0, step: 1
4147 22:20:01.216896
4148 22:20:01.219927 RX Delay -195 -> 252, step: 8
4149 22:20:01.220011
4150 22:20:01.223116 Set Vref, RX VrefLevel [Byte0]: 61
4151 22:20:01.226474 [Byte1]: 57
4152 22:20:01.231169
4153 22:20:01.231252 Final RX Vref Byte 0 = 61 to rank0
4154 22:20:01.234449 Final RX Vref Byte 1 = 57 to rank0
4155 22:20:01.237375 Final RX Vref Byte 0 = 61 to rank1
4156 22:20:01.240635 Final RX Vref Byte 1 = 57 to rank1==
4157 22:20:01.244664 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 22:20:01.250819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 22:20:01.250903 ==
4160 22:20:01.250969 DQS Delay:
4161 22:20:01.253921 DQS0 = 0, DQS1 = 0
4162 22:20:01.254003 DQM Delay:
4163 22:20:01.254068 DQM0 = 43, DQM1 = 31
4164 22:20:01.257481 DQ Delay:
4165 22:20:01.260414 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4166 22:20:01.263651 DQ4 =44, DQ5 =36, DQ6 =48, DQ7 =52
4167 22:20:01.267476 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4168 22:20:01.270442 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4169 22:20:01.270517
4170 22:20:01.270580
4171 22:20:01.276786 [DQSOSCAuto] RK0, (LSB)MR18= 0x663e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4172 22:20:01.280806 CH0 RK0: MR19=808, MR18=663E
4173 22:20:01.286960 CH0_RK0: MR19=0x808, MR18=0x663E, DQSOSC=390, MR23=63, INC=172, DEC=114
4174 22:20:01.287036
4175 22:20:01.290254 ----->DramcWriteLeveling(PI) begin...
4176 22:20:01.290328 ==
4177 22:20:01.293406 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 22:20:01.296894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 22:20:01.296968 ==
4180 22:20:01.300069 Write leveling (Byte 0): 31 => 31
4181 22:20:01.303642 Write leveling (Byte 1): 31 => 31
4182 22:20:01.306534 DramcWriteLeveling(PI) end<-----
4183 22:20:01.306609
4184 22:20:01.306671 ==
4185 22:20:01.309836 Dram Type= 6, Freq= 0, CH_0, rank 1
4186 22:20:01.316495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 22:20:01.316601 ==
4188 22:20:01.316667 [Gating] SW mode calibration
4189 22:20:01.326249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4190 22:20:01.329331 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4191 22:20:01.332823 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 22:20:01.339459 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 22:20:01.342715 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4194 22:20:01.349154 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4195 22:20:01.352632 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (0 0)
4196 22:20:01.355787 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 22:20:01.362145 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 22:20:01.365437 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 22:20:01.368816 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 22:20:01.375346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 22:20:01.379264 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4202 22:20:01.382854 0 10 12 | B1->B0 | 2726 2b2b | 1 0 | (0 0) (0 0)
4203 22:20:01.388872 0 10 16 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
4204 22:20:01.391920 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 22:20:01.395361 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 22:20:01.402165 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 22:20:01.405089 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 22:20:01.408701 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 22:20:01.415254 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4210 22:20:01.418397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4211 22:20:01.422140 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4212 22:20:01.425650 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 22:20:01.431991 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 22:20:01.435152 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 22:20:01.442142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 22:20:01.444732 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 22:20:01.448022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 22:20:01.454892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 22:20:01.457894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 22:20:01.461295 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 22:20:01.468087 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 22:20:01.471519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 22:20:01.474531 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 22:20:01.477858 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 22:20:01.484823 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 22:20:01.487958 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4227 22:20:01.491299 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 22:20:01.494424 Total UI for P1: 0, mck2ui 16
4229 22:20:01.497589 best dqsien dly found for B0: ( 0, 13, 12)
4230 22:20:01.500961 Total UI for P1: 0, mck2ui 16
4231 22:20:01.504284 best dqsien dly found for B1: ( 0, 13, 14)
4232 22:20:01.508116 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4233 22:20:01.514055 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4234 22:20:01.514168
4235 22:20:01.517507 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4236 22:20:01.520765 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 22:20:01.524158 [Gating] SW calibration Done
4238 22:20:01.524269 ==
4239 22:20:01.527179 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 22:20:01.530296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 22:20:01.530411 ==
4242 22:20:01.533874 RX Vref Scan: 0
4243 22:20:01.533992
4244 22:20:01.534085 RX Vref 0 -> 0, step: 1
4245 22:20:01.534192
4246 22:20:01.536809 RX Delay -230 -> 252, step: 16
4247 22:20:01.543999 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4248 22:20:01.546936 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4249 22:20:01.550346 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4250 22:20:01.553649 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4251 22:20:01.556809 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4252 22:20:01.563969 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4253 22:20:01.566877 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4254 22:20:01.569879 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4255 22:20:01.573417 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4256 22:20:01.580046 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4257 22:20:01.583776 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4258 22:20:01.586551 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4259 22:20:01.590519 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4260 22:20:01.596565 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4261 22:20:01.599839 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4262 22:20:01.602959 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4263 22:20:01.603071 ==
4264 22:20:01.606875 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 22:20:01.609625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 22:20:01.609738 ==
4267 22:20:01.613645 DQS Delay:
4268 22:20:01.613720 DQS0 = 0, DQS1 = 0
4269 22:20:01.616293 DQM Delay:
4270 22:20:01.616392 DQM0 = 42, DQM1 = 35
4271 22:20:01.616498 DQ Delay:
4272 22:20:01.619855 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4273 22:20:01.623216 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4274 22:20:01.626776 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4275 22:20:01.629436 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4276 22:20:01.629549
4277 22:20:01.629640
4278 22:20:01.632887 ==
4279 22:20:01.636490 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 22:20:01.639586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 22:20:01.639667 ==
4282 22:20:01.639771
4283 22:20:01.639866
4284 22:20:01.642705 TX Vref Scan disable
4285 22:20:01.642822 == TX Byte 0 ==
4286 22:20:01.649395 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4287 22:20:01.652629 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4288 22:20:01.652741 == TX Byte 1 ==
4289 22:20:01.659722 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4290 22:20:01.662436 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4291 22:20:01.662544 ==
4292 22:20:01.666095 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 22:20:01.669244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 22:20:01.669364 ==
4295 22:20:01.669456
4296 22:20:01.669559
4297 22:20:01.672844 TX Vref Scan disable
4298 22:20:01.675756 == TX Byte 0 ==
4299 22:20:01.679517 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4300 22:20:01.682194 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4301 22:20:01.685491 == TX Byte 1 ==
4302 22:20:01.689031 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4303 22:20:01.692444 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4304 22:20:01.695997
4305 22:20:01.696095 [DATLAT]
4306 22:20:01.696193 Freq=600, CH0 RK1
4307 22:20:01.696281
4308 22:20:01.699034 DATLAT Default: 0x9
4309 22:20:01.699141 0, 0xFFFF, sum = 0
4310 22:20:01.702474 1, 0xFFFF, sum = 0
4311 22:20:01.702598 2, 0xFFFF, sum = 0
4312 22:20:01.705462 3, 0xFFFF, sum = 0
4313 22:20:01.708894 4, 0xFFFF, sum = 0
4314 22:20:01.708974 5, 0xFFFF, sum = 0
4315 22:20:01.712408 6, 0xFFFF, sum = 0
4316 22:20:01.712559 7, 0xFFFF, sum = 0
4317 22:20:01.715088 8, 0x0, sum = 1
4318 22:20:01.715202 9, 0x0, sum = 2
4319 22:20:01.715295 10, 0x0, sum = 3
4320 22:20:01.718539 11, 0x0, sum = 4
4321 22:20:01.718618 best_step = 9
4322 22:20:01.718697
4323 22:20:01.718755 ==
4324 22:20:01.721748 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 22:20:01.728875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 22:20:01.728960 ==
4327 22:20:01.729042 RX Vref Scan: 0
4328 22:20:01.729131
4329 22:20:01.731716 RX Vref 0 -> 0, step: 1
4330 22:20:01.731818
4331 22:20:01.735109 RX Delay -195 -> 252, step: 8
4332 22:20:01.738846 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4333 22:20:01.744990 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4334 22:20:01.748593 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4335 22:20:01.751797 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4336 22:20:01.755276 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4337 22:20:01.761909 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4338 22:20:01.764869 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4339 22:20:01.768145 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4340 22:20:01.771491 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4341 22:20:01.774620 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4342 22:20:01.781386 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4343 22:20:01.784608 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4344 22:20:01.787989 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4345 22:20:01.794774 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4346 22:20:01.798014 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4347 22:20:01.801292 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4348 22:20:01.801410 ==
4349 22:20:01.804732 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 22:20:01.808129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:20:01.808259 ==
4352 22:20:01.811248 DQS Delay:
4353 22:20:01.811381 DQS0 = 0, DQS1 = 0
4354 22:20:01.814644 DQM Delay:
4355 22:20:01.814738 DQM0 = 41, DQM1 = 36
4356 22:20:01.814825 DQ Delay:
4357 22:20:01.817655 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4358 22:20:01.821043 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4359 22:20:01.824367 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4360 22:20:01.827519 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4361 22:20:01.827612
4362 22:20:01.827697
4363 22:20:01.837569 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4364 22:20:01.841187 CH0 RK1: MR19=808, MR18=5D11
4365 22:20:01.847415 CH0_RK1: MR19=0x808, MR18=0x5D11, DQSOSC=392, MR23=63, INC=170, DEC=113
4366 22:20:01.850628 [RxdqsGatingPostProcess] freq 600
4367 22:20:01.853847 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 22:20:01.857375 Pre-setting of DQS Precalculation
4369 22:20:01.863743 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 22:20:01.863843 ==
4371 22:20:01.867263 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 22:20:01.870943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 22:20:01.871038 ==
4374 22:20:01.877334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 22:20:01.880419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4376 22:20:01.884662 [CA 0] Center 35 (5~66) winsize 62
4377 22:20:01.887810 [CA 1] Center 35 (5~66) winsize 62
4378 22:20:01.891086 [CA 2] Center 34 (4~65) winsize 62
4379 22:20:01.895264 [CA 3] Center 33 (3~64) winsize 62
4380 22:20:01.897735 [CA 4] Center 34 (4~64) winsize 61
4381 22:20:01.901076 [CA 5] Center 33 (3~64) winsize 62
4382 22:20:01.901170
4383 22:20:01.904843 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4384 22:20:01.904944
4385 22:20:01.907864 [CATrainingPosCal] consider 1 rank data
4386 22:20:01.911138 u2DelayCellTimex100 = 270/100 ps
4387 22:20:01.914398 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4388 22:20:01.921076 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 22:20:01.924439 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 22:20:01.927862 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 22:20:01.931519 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4392 22:20:01.934117 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4393 22:20:01.934235
4394 22:20:01.937975 CA PerBit enable=1, Macro0, CA PI delay=33
4395 22:20:01.938085
4396 22:20:01.941087 [CBTSetCACLKResult] CA Dly = 33
4397 22:20:01.941187 CS Dly: 4 (0~35)
4398 22:20:01.944415 ==
4399 22:20:01.947563 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 22:20:01.950856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 22:20:01.950957 ==
4402 22:20:01.957205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 22:20:01.960398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4404 22:20:01.964496 [CA 0] Center 35 (5~66) winsize 62
4405 22:20:01.968866 [CA 1] Center 36 (6~66) winsize 61
4406 22:20:01.971383 [CA 2] Center 34 (4~65) winsize 62
4407 22:20:01.974880 [CA 3] Center 34 (3~65) winsize 63
4408 22:20:01.978109 [CA 4] Center 34 (4~65) winsize 62
4409 22:20:01.981184 [CA 5] Center 34 (4~65) winsize 62
4410 22:20:01.981256
4411 22:20:01.984461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4412 22:20:01.984570
4413 22:20:01.987936 [CATrainingPosCal] consider 2 rank data
4414 22:20:01.991228 u2DelayCellTimex100 = 270/100 ps
4415 22:20:01.995190 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 22:20:01.998277 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4417 22:20:02.004794 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 22:20:02.007765 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4419 22:20:02.011612 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4420 22:20:02.014678 CA5 delay=34 (4~64),Diff = 1 PI (9 cell)
4421 22:20:02.014782
4422 22:20:02.017967 CA PerBit enable=1, Macro0, CA PI delay=33
4423 22:20:02.018069
4424 22:20:02.021064 [CBTSetCACLKResult] CA Dly = 33
4425 22:20:02.021161 CS Dly: 4 (0~36)
4426 22:20:02.021248
4427 22:20:02.024451 ----->DramcWriteLeveling(PI) begin...
4428 22:20:02.027604 ==
4429 22:20:02.031329 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 22:20:02.034278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 22:20:02.034372 ==
4432 22:20:02.037627 Write leveling (Byte 0): 29 => 29
4433 22:20:02.041156 Write leveling (Byte 1): 32 => 32
4434 22:20:02.044655 DramcWriteLeveling(PI) end<-----
4435 22:20:02.044722
4436 22:20:02.044785 ==
4437 22:20:02.047329 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 22:20:02.051261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 22:20:02.051354 ==
4440 22:20:02.054273 [Gating] SW mode calibration
4441 22:20:02.060866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 22:20:02.067509 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 22:20:02.070620 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 22:20:02.073782 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 22:20:02.080428 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 22:20:02.083924 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (0 1)
4447 22:20:02.086979 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 22:20:02.093780 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 22:20:02.097121 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 22:20:02.100727 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 22:20:02.107165 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 22:20:02.110717 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 22:20:02.113514 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 22:20:02.120445 0 10 12 | B1->B0 | 2f2f 3f3f | 0 1 | (1 1) (0 0)
4455 22:20:02.123337 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 22:20:02.126683 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 22:20:02.133142 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 22:20:02.136419 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 22:20:02.139877 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 22:20:02.146322 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 22:20:02.149777 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 22:20:02.153541 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4463 22:20:02.159561 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 22:20:02.163033 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 22:20:02.166433 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 22:20:02.172940 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 22:20:02.176218 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 22:20:02.179685 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 22:20:02.186341 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 22:20:02.189396 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 22:20:02.192718 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 22:20:02.199172 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 22:20:02.202906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 22:20:02.205842 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 22:20:02.212308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 22:20:02.215811 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 22:20:02.219175 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 22:20:02.225389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 22:20:02.225465 Total UI for P1: 0, mck2ui 16
4480 22:20:02.232034 best dqsien dly found for B0: ( 0, 13, 10)
4481 22:20:02.232117 Total UI for P1: 0, mck2ui 16
4482 22:20:02.239146 best dqsien dly found for B1: ( 0, 13, 10)
4483 22:20:02.241989 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4484 22:20:02.245551 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4485 22:20:02.245623
4486 22:20:02.248526 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4487 22:20:02.251744 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4488 22:20:02.255268 [Gating] SW calibration Done
4489 22:20:02.255377 ==
4490 22:20:02.258631 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 22:20:02.262193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 22:20:02.262273 ==
4493 22:20:02.265649 RX Vref Scan: 0
4494 22:20:02.265727
4495 22:20:02.265815 RX Vref 0 -> 0, step: 1
4496 22:20:02.265904
4497 22:20:02.268594 RX Delay -230 -> 252, step: 16
4498 22:20:02.271972 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4499 22:20:02.279000 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4500 22:20:02.282444 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4501 22:20:02.285205 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4502 22:20:02.288661 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4503 22:20:02.295161 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4504 22:20:02.298532 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4505 22:20:02.301907 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4506 22:20:02.305530 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4507 22:20:02.308625 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4508 22:20:02.314949 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4509 22:20:02.318253 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4510 22:20:02.321683 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4511 22:20:02.328366 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4512 22:20:02.331722 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4513 22:20:02.334691 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4514 22:20:02.334762 ==
4515 22:20:02.338378 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 22:20:02.341573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 22:20:02.341678 ==
4518 22:20:02.345042 DQS Delay:
4519 22:20:02.345115 DQS0 = 0, DQS1 = 0
4520 22:20:02.348616 DQM Delay:
4521 22:20:02.348694 DQM0 = 50, DQM1 = 35
4522 22:20:02.348756 DQ Delay:
4523 22:20:02.351269 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4524 22:20:02.354971 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4525 22:20:02.358347 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4526 22:20:02.361363 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =57
4527 22:20:02.361436
4528 22:20:02.361498
4529 22:20:02.364432 ==
4530 22:20:02.368118 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 22:20:02.371202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 22:20:02.371275 ==
4533 22:20:02.371345
4534 22:20:02.371405
4535 22:20:02.374737 TX Vref Scan disable
4536 22:20:02.374813 == TX Byte 0 ==
4537 22:20:02.380997 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4538 22:20:02.384237 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4539 22:20:02.384309 == TX Byte 1 ==
4540 22:20:02.390890 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4541 22:20:02.394111 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4542 22:20:02.394196 ==
4543 22:20:02.397954 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 22:20:02.401144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 22:20:02.401226 ==
4546 22:20:02.401290
4547 22:20:02.401350
4548 22:20:02.404226 TX Vref Scan disable
4549 22:20:02.407665 == TX Byte 0 ==
4550 22:20:02.410887 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4551 22:20:02.413956 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4552 22:20:02.417736 == TX Byte 1 ==
4553 22:20:02.420720 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4554 22:20:02.425176 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4555 22:20:02.425258
4556 22:20:02.427770 [DATLAT]
4557 22:20:02.427850 Freq=600, CH1 RK0
4558 22:20:02.427916
4559 22:20:02.430950 DATLAT Default: 0x9
4560 22:20:02.431032 0, 0xFFFF, sum = 0
4561 22:20:02.434377 1, 0xFFFF, sum = 0
4562 22:20:02.434460 2, 0xFFFF, sum = 0
4563 22:20:02.437109 3, 0xFFFF, sum = 0
4564 22:20:02.437192 4, 0xFFFF, sum = 0
4565 22:20:02.440453 5, 0xFFFF, sum = 0
4566 22:20:02.443727 6, 0xFFFF, sum = 0
4567 22:20:02.443809 7, 0xFFFF, sum = 0
4568 22:20:02.443875 8, 0x0, sum = 1
4569 22:20:02.447034 9, 0x0, sum = 2
4570 22:20:02.447117 10, 0x0, sum = 3
4571 22:20:02.450535 11, 0x0, sum = 4
4572 22:20:02.450618 best_step = 9
4573 22:20:02.450682
4574 22:20:02.450741 ==
4575 22:20:02.454088 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 22:20:02.460630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 22:20:02.460711 ==
4578 22:20:02.460776 RX Vref Scan: 1
4579 22:20:02.460836
4580 22:20:02.464039 RX Vref 0 -> 0, step: 1
4581 22:20:02.464120
4582 22:20:02.466959 RX Delay -195 -> 252, step: 8
4583 22:20:02.467039
4584 22:20:02.470503 Set Vref, RX VrefLevel [Byte0]: 50
4585 22:20:02.474338 [Byte1]: 53
4586 22:20:02.474419
4587 22:20:02.477027 Final RX Vref Byte 0 = 50 to rank0
4588 22:20:02.480828 Final RX Vref Byte 1 = 53 to rank0
4589 22:20:02.483862 Final RX Vref Byte 0 = 50 to rank1
4590 22:20:02.487303 Final RX Vref Byte 1 = 53 to rank1==
4591 22:20:02.490148 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 22:20:02.493232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 22:20:02.493314 ==
4594 22:20:02.497181 DQS Delay:
4595 22:20:02.497262 DQS0 = 0, DQS1 = 0
4596 22:20:02.500090 DQM Delay:
4597 22:20:02.500170 DQM0 = 48, DQM1 = 38
4598 22:20:02.500238 DQ Delay:
4599 22:20:02.503547 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4600 22:20:02.506622 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4601 22:20:02.510221 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4602 22:20:02.513820 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4603 22:20:02.513895
4604 22:20:02.513959
4605 22:20:02.523506 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4606 22:20:02.526473 CH1 RK0: MR19=808, MR18=4B30
4607 22:20:02.533188 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4608 22:20:02.533263
4609 22:20:02.536329 ----->DramcWriteLeveling(PI) begin...
4610 22:20:02.536429 ==
4611 22:20:02.540043 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 22:20:02.542825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 22:20:02.542894 ==
4614 22:20:02.546484 Write leveling (Byte 0): 31 => 31
4615 22:20:02.549859 Write leveling (Byte 1): 31 => 31
4616 22:20:02.553052 DramcWriteLeveling(PI) end<-----
4617 22:20:02.553119
4618 22:20:02.553183 ==
4619 22:20:02.556618 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 22:20:02.560079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 22:20:02.560144 ==
4622 22:20:02.562903 [Gating] SW mode calibration
4623 22:20:02.569750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4624 22:20:02.576261 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4625 22:20:02.579563 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 22:20:02.583180 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 22:20:02.589631 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 22:20:02.592830 0 9 12 | B1->B0 | 2f2f 3333 | 1 1 | (1 0) (1 0)
4629 22:20:02.596003 0 9 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 0)
4630 22:20:02.603452 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 22:20:02.606117 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 22:20:02.609672 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 22:20:02.615819 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 22:20:02.619036 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 22:20:02.622364 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 22:20:02.628868 0 10 12 | B1->B0 | 3939 2c2c | 0 1 | (0 0) (1 1)
4637 22:20:02.632450 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 22:20:02.635563 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 22:20:02.642632 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 22:20:02.645863 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 22:20:02.649453 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 22:20:02.655937 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 22:20:02.658611 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 22:20:02.663104 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4645 22:20:02.669008 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 22:20:02.672042 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 22:20:02.675165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 22:20:02.681905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 22:20:02.685152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 22:20:02.688284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 22:20:02.694751 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 22:20:02.698489 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 22:20:02.701825 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 22:20:02.707898 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 22:20:02.711499 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 22:20:02.714790 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 22:20:02.721250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 22:20:02.724492 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 22:20:02.728379 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 22:20:02.734873 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4661 22:20:02.737708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 22:20:02.741175 Total UI for P1: 0, mck2ui 16
4663 22:20:02.744822 best dqsien dly found for B0: ( 0, 13, 14)
4664 22:20:02.748011 Total UI for P1: 0, mck2ui 16
4665 22:20:02.751271 best dqsien dly found for B1: ( 0, 13, 12)
4666 22:20:02.754229 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4667 22:20:02.757991 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4668 22:20:02.758086
4669 22:20:02.761024 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4670 22:20:02.764373 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4671 22:20:02.767530 [Gating] SW calibration Done
4672 22:20:02.767610 ==
4673 22:20:02.770772 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 22:20:02.774611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 22:20:02.777635 ==
4676 22:20:02.777716 RX Vref Scan: 0
4677 22:20:02.777779
4678 22:20:02.781117 RX Vref 0 -> 0, step: 1
4679 22:20:02.781215
4680 22:20:02.784505 RX Delay -230 -> 252, step: 16
4681 22:20:02.787995 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4682 22:20:02.790831 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4683 22:20:02.794018 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4684 22:20:02.800724 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4685 22:20:02.804119 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4686 22:20:02.807138 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4687 22:20:02.810388 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4688 22:20:02.814231 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4689 22:20:02.820708 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4690 22:20:02.823699 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4691 22:20:02.826988 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4692 22:20:02.831094 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4693 22:20:02.837067 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4694 22:20:02.840183 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4695 22:20:02.843915 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4696 22:20:02.850327 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4697 22:20:02.850439 ==
4698 22:20:02.853168 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 22:20:02.856579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 22:20:02.856665 ==
4701 22:20:02.856730 DQS Delay:
4702 22:20:02.860387 DQS0 = 0, DQS1 = 0
4703 22:20:02.860468 DQM Delay:
4704 22:20:02.863445 DQM0 = 45, DQM1 = 39
4705 22:20:02.863526 DQ Delay:
4706 22:20:02.866521 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4707 22:20:02.870035 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4708 22:20:02.873029 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =25
4709 22:20:02.876848 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4710 22:20:02.876929
4711 22:20:02.876992
4712 22:20:02.877050 ==
4713 22:20:02.880237 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 22:20:02.883206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 22:20:02.883303 ==
4716 22:20:02.883369
4717 22:20:02.886469
4718 22:20:02.886550 TX Vref Scan disable
4719 22:20:02.889584 == TX Byte 0 ==
4720 22:20:02.892822 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4721 22:20:02.896101 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4722 22:20:02.899820 == TX Byte 1 ==
4723 22:20:02.902485 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4724 22:20:02.905910 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4725 22:20:02.909439 ==
4726 22:20:02.909521 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 22:20:02.915710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 22:20:02.915792 ==
4729 22:20:02.915856
4730 22:20:02.915914
4731 22:20:02.919077 TX Vref Scan disable
4732 22:20:02.919157 == TX Byte 0 ==
4733 22:20:02.925807 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4734 22:20:02.929538 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4735 22:20:02.929618 == TX Byte 1 ==
4736 22:20:02.935678 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4737 22:20:02.938741 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4738 22:20:02.938822
4739 22:20:02.938885 [DATLAT]
4740 22:20:02.942287 Freq=600, CH1 RK1
4741 22:20:02.942367
4742 22:20:02.942430 DATLAT Default: 0x9
4743 22:20:02.945292 0, 0xFFFF, sum = 0
4744 22:20:02.945374 1, 0xFFFF, sum = 0
4745 22:20:02.949362 2, 0xFFFF, sum = 0
4746 22:20:02.952210 3, 0xFFFF, sum = 0
4747 22:20:02.952291 4, 0xFFFF, sum = 0
4748 22:20:02.955296 5, 0xFFFF, sum = 0
4749 22:20:02.955378 6, 0xFFFF, sum = 0
4750 22:20:02.958813 7, 0xFFFF, sum = 0
4751 22:20:02.958895 8, 0x0, sum = 1
4752 22:20:02.961889 9, 0x0, sum = 2
4753 22:20:02.961970 10, 0x0, sum = 3
4754 22:20:02.962036 11, 0x0, sum = 4
4755 22:20:02.965549 best_step = 9
4756 22:20:02.965629
4757 22:20:02.965692 ==
4758 22:20:02.968819 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 22:20:02.971968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 22:20:02.972049 ==
4761 22:20:02.975385 RX Vref Scan: 0
4762 22:20:02.975455
4763 22:20:02.975515 RX Vref 0 -> 0, step: 1
4764 22:20:02.978463
4765 22:20:02.978542 RX Delay -195 -> 252, step: 8
4766 22:20:02.986383 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4767 22:20:02.989261 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4768 22:20:02.992959 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4769 22:20:02.996122 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4770 22:20:03.002480 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4771 22:20:03.005827 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4772 22:20:03.009124 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4773 22:20:03.012790 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4774 22:20:03.019028 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4775 22:20:03.022438 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4776 22:20:03.025736 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4777 22:20:03.028702 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4778 22:20:03.035432 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4779 22:20:03.038588 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4780 22:20:03.042209 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4781 22:20:03.045404 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4782 22:20:03.045474 ==
4783 22:20:03.048777 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 22:20:03.055222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 22:20:03.055296 ==
4786 22:20:03.055367 DQS Delay:
4787 22:20:03.058406 DQS0 = 0, DQS1 = 0
4788 22:20:03.058493 DQM Delay:
4789 22:20:03.058554 DQM0 = 45, DQM1 = 37
4790 22:20:03.061976 DQ Delay:
4791 22:20:03.064911 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4792 22:20:03.068419 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4793 22:20:03.071777 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4794 22:20:03.074877 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4795 22:20:03.074949
4796 22:20:03.075012
4797 22:20:03.081456 [DQSOSCAuto] RK1, (LSB)MR18= 0x291e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4798 22:20:03.084958 CH1 RK1: MR19=808, MR18=291E
4799 22:20:03.091446 CH1_RK1: MR19=0x808, MR18=0x291E, DQSOSC=402, MR23=63, INC=162, DEC=108
4800 22:20:03.094653 [RxdqsGatingPostProcess] freq 600
4801 22:20:03.101264 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4802 22:20:03.101345 Pre-setting of DQS Precalculation
4803 22:20:03.107652 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4804 22:20:03.114492 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4805 22:20:03.121165 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4806 22:20:03.121245
4807 22:20:03.121308
4808 22:20:03.124657 [Calibration Summary] 1200 Mbps
4809 22:20:03.127972 CH 0, Rank 0
4810 22:20:03.128050 SW Impedance : PASS
4811 22:20:03.130844 DUTY Scan : NO K
4812 22:20:03.130911 ZQ Calibration : PASS
4813 22:20:03.134539 Jitter Meter : NO K
4814 22:20:03.137656 CBT Training : PASS
4815 22:20:03.137724 Write leveling : PASS
4816 22:20:03.140924 RX DQS gating : PASS
4817 22:20:03.144794 RX DQ/DQS(RDDQC) : PASS
4818 22:20:03.144882 TX DQ/DQS : PASS
4819 22:20:03.147501 RX DATLAT : PASS
4820 22:20:03.150653 RX DQ/DQS(Engine): PASS
4821 22:20:03.150721 TX OE : NO K
4822 22:20:03.154088 All Pass.
4823 22:20:03.154161
4824 22:20:03.154222 CH 0, Rank 1
4825 22:20:03.157832 SW Impedance : PASS
4826 22:20:03.157896 DUTY Scan : NO K
4827 22:20:03.160899 ZQ Calibration : PASS
4828 22:20:03.163957 Jitter Meter : NO K
4829 22:20:03.164027 CBT Training : PASS
4830 22:20:03.167194 Write leveling : PASS
4831 22:20:03.170529 RX DQS gating : PASS
4832 22:20:03.170594 RX DQ/DQS(RDDQC) : PASS
4833 22:20:03.173900 TX DQ/DQS : PASS
4834 22:20:03.177279 RX DATLAT : PASS
4835 22:20:03.177350 RX DQ/DQS(Engine): PASS
4836 22:20:03.180508 TX OE : NO K
4837 22:20:03.180596 All Pass.
4838 22:20:03.180657
4839 22:20:03.184189 CH 1, Rank 0
4840 22:20:03.184261 SW Impedance : PASS
4841 22:20:03.187782 DUTY Scan : NO K
4842 22:20:03.190446 ZQ Calibration : PASS
4843 22:20:03.190515 Jitter Meter : NO K
4844 22:20:03.193733 CBT Training : PASS
4845 22:20:03.193801 Write leveling : PASS
4846 22:20:03.197248 RX DQS gating : PASS
4847 22:20:03.200333 RX DQ/DQS(RDDQC) : PASS
4848 22:20:03.200408 TX DQ/DQS : PASS
4849 22:20:03.203857 RX DATLAT : PASS
4850 22:20:03.207819 RX DQ/DQS(Engine): PASS
4851 22:20:03.207896 TX OE : NO K
4852 22:20:03.210657 All Pass.
4853 22:20:03.210732
4854 22:20:03.210798 CH 1, Rank 1
4855 22:20:03.213513 SW Impedance : PASS
4856 22:20:03.213585 DUTY Scan : NO K
4857 22:20:03.216914 ZQ Calibration : PASS
4858 22:20:03.220403 Jitter Meter : NO K
4859 22:20:03.220484 CBT Training : PASS
4860 22:20:03.223662 Write leveling : PASS
4861 22:20:03.226883 RX DQS gating : PASS
4862 22:20:03.226949 RX DQ/DQS(RDDQC) : PASS
4863 22:20:03.230720 TX DQ/DQS : PASS
4864 22:20:03.233616 RX DATLAT : PASS
4865 22:20:03.233681 RX DQ/DQS(Engine): PASS
4866 22:20:03.236724 TX OE : NO K
4867 22:20:03.236797 All Pass.
4868 22:20:03.236864
4869 22:20:03.240198 DramC Write-DBI off
4870 22:20:03.243795 PER_BANK_REFRESH: Hybrid Mode
4871 22:20:03.243863 TX_TRACKING: ON
4872 22:20:03.253192 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4873 22:20:03.256788 [FAST_K] Save calibration result to emmc
4874 22:20:03.259925 dramc_set_vcore_voltage set vcore to 662500
4875 22:20:03.263641 Read voltage for 933, 3
4876 22:20:03.263716 Vio18 = 0
4877 22:20:03.263777 Vcore = 662500
4878 22:20:03.266578 Vdram = 0
4879 22:20:03.266643 Vddq = 0
4880 22:20:03.266701 Vmddr = 0
4881 22:20:03.273112 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4882 22:20:03.276283 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4883 22:20:03.280183 MEM_TYPE=3, freq_sel=17
4884 22:20:03.282977 sv_algorithm_assistance_LP4_1600
4885 22:20:03.286009 ============ PULL DRAM RESETB DOWN ============
4886 22:20:03.289400 ========== PULL DRAM RESETB DOWN end =========
4887 22:20:03.296103 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4888 22:20:03.299547 ===================================
4889 22:20:03.303253 LPDDR4 DRAM CONFIGURATION
4890 22:20:03.306130 ===================================
4891 22:20:03.306206 EX_ROW_EN[0] = 0x0
4892 22:20:03.309355 EX_ROW_EN[1] = 0x0
4893 22:20:03.309431 LP4Y_EN = 0x0
4894 22:20:03.312392 WORK_FSP = 0x0
4895 22:20:03.312468 WL = 0x3
4896 22:20:03.315916 RL = 0x3
4897 22:20:03.315984 BL = 0x2
4898 22:20:03.319251 RPST = 0x0
4899 22:20:03.319316 RD_PRE = 0x0
4900 22:20:03.322388 WR_PRE = 0x1
4901 22:20:03.322455 WR_PST = 0x0
4902 22:20:03.325554 DBI_WR = 0x0
4903 22:20:03.329367 DBI_RD = 0x0
4904 22:20:03.329433 OTF = 0x1
4905 22:20:03.332612 ===================================
4906 22:20:03.335384 ===================================
4907 22:20:03.335453 ANA top config
4908 22:20:03.338785 ===================================
4909 22:20:03.342024 DLL_ASYNC_EN = 0
4910 22:20:03.345300 ALL_SLAVE_EN = 1
4911 22:20:03.348599 NEW_RANK_MODE = 1
4912 22:20:03.352357 DLL_IDLE_MODE = 1
4913 22:20:03.352463 LP45_APHY_COMB_EN = 1
4914 22:20:03.355338 TX_ODT_DIS = 1
4915 22:20:03.358749 NEW_8X_MODE = 1
4916 22:20:03.361772 ===================================
4917 22:20:03.364994 ===================================
4918 22:20:03.368703 data_rate = 1866
4919 22:20:03.372106 CKR = 1
4920 22:20:03.375365 DQ_P2S_RATIO = 8
4921 22:20:03.378214 ===================================
4922 22:20:03.378295 CA_P2S_RATIO = 8
4923 22:20:03.381772 DQ_CA_OPEN = 0
4924 22:20:03.385573 DQ_SEMI_OPEN = 0
4925 22:20:03.388598 CA_SEMI_OPEN = 0
4926 22:20:03.391484 CA_FULL_RATE = 0
4927 22:20:03.394658 DQ_CKDIV4_EN = 1
4928 22:20:03.394739 CA_CKDIV4_EN = 1
4929 22:20:03.398404 CA_PREDIV_EN = 0
4930 22:20:03.401245 PH8_DLY = 0
4931 22:20:03.404974 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4932 22:20:03.408292 DQ_AAMCK_DIV = 4
4933 22:20:03.411329 CA_AAMCK_DIV = 4
4934 22:20:03.411413 CA_ADMCK_DIV = 4
4935 22:20:03.414743 DQ_TRACK_CA_EN = 0
4936 22:20:03.418158 CA_PICK = 933
4937 22:20:03.421632 CA_MCKIO = 933
4938 22:20:03.425110 MCKIO_SEMI = 0
4939 22:20:03.427744 PLL_FREQ = 3732
4940 22:20:03.431724 DQ_UI_PI_RATIO = 32
4941 22:20:03.431804 CA_UI_PI_RATIO = 0
4942 22:20:03.434447 ===================================
4943 22:20:03.437647 ===================================
4944 22:20:03.440912 memory_type:LPDDR4
4945 22:20:03.444197 GP_NUM : 10
4946 22:20:03.444278 SRAM_EN : 1
4947 22:20:03.447684 MD32_EN : 0
4948 22:20:03.451266 ===================================
4949 22:20:03.454668 [ANA_INIT] >>>>>>>>>>>>>>
4950 22:20:03.458048 <<<<<< [CONFIGURE PHASE]: ANA_TX
4951 22:20:03.461201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4952 22:20:03.464354 ===================================
4953 22:20:03.467681 data_rate = 1866,PCW = 0X8f00
4954 22:20:03.471483 ===================================
4955 22:20:03.474220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4956 22:20:03.477649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 22:20:03.484418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 22:20:03.486890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4959 22:20:03.490837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4960 22:20:03.493764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4961 22:20:03.496937 [ANA_INIT] flow start
4962 22:20:03.500331 [ANA_INIT] PLL >>>>>>>>
4963 22:20:03.500411 [ANA_INIT] PLL <<<<<<<<
4964 22:20:03.503587 [ANA_INIT] MIDPI >>>>>>>>
4965 22:20:03.506823 [ANA_INIT] MIDPI <<<<<<<<
4966 22:20:03.506932 [ANA_INIT] DLL >>>>>>>>
4967 22:20:03.510109 [ANA_INIT] flow end
4968 22:20:03.513308 ============ LP4 DIFF to SE enter ============
4969 22:20:03.520296 ============ LP4 DIFF to SE exit ============
4970 22:20:03.520378 [ANA_INIT] <<<<<<<<<<<<<
4971 22:20:03.523541 [Flow] Enable top DCM control >>>>>
4972 22:20:03.526942 [Flow] Enable top DCM control <<<<<
4973 22:20:03.530087 Enable DLL master slave shuffle
4974 22:20:03.536725 ==============================================================
4975 22:20:03.536806 Gating Mode config
4976 22:20:03.542919 ==============================================================
4977 22:20:03.546300 Config description:
4978 22:20:03.556539 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4979 22:20:03.563121 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4980 22:20:03.566102 SELPH_MODE 0: By rank 1: By Phase
4981 22:20:03.573001 ==============================================================
4982 22:20:03.575769 GAT_TRACK_EN = 1
4983 22:20:03.579496 RX_GATING_MODE = 2
4984 22:20:03.582645 RX_GATING_TRACK_MODE = 2
4985 22:20:03.582750 SELPH_MODE = 1
4986 22:20:03.585917 PICG_EARLY_EN = 1
4987 22:20:03.589085 VALID_LAT_VALUE = 1
4988 22:20:03.595796 ==============================================================
4989 22:20:03.599338 Enter into Gating configuration >>>>
4990 22:20:03.602440 Exit from Gating configuration <<<<
4991 22:20:03.605700 Enter into DVFS_PRE_config >>>>>
4992 22:20:03.615565 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4993 22:20:03.618870 Exit from DVFS_PRE_config <<<<<
4994 22:20:03.622174 Enter into PICG configuration >>>>
4995 22:20:03.625767 Exit from PICG configuration <<<<
4996 22:20:03.628677 [RX_INPUT] configuration >>>>>
4997 22:20:03.632360 [RX_INPUT] configuration <<<<<
4998 22:20:03.635229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4999 22:20:03.642102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5000 22:20:03.648750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 22:20:03.655241 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 22:20:03.662460 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5003 22:20:03.665102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5004 22:20:03.671977 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5005 22:20:03.675211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5006 22:20:03.678697 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5007 22:20:03.681527 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5008 22:20:03.688293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5009 22:20:03.691651 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 22:20:03.694838 ===================================
5011 22:20:03.698295 LPDDR4 DRAM CONFIGURATION
5012 22:20:03.701935 ===================================
5013 22:20:03.702101 EX_ROW_EN[0] = 0x0
5014 22:20:03.704711 EX_ROW_EN[1] = 0x0
5015 22:20:03.704799 LP4Y_EN = 0x0
5016 22:20:03.708093 WORK_FSP = 0x0
5017 22:20:03.708210 WL = 0x3
5018 22:20:03.711411 RL = 0x3
5019 22:20:03.711513 BL = 0x2
5020 22:20:03.714769 RPST = 0x0
5021 22:20:03.714891 RD_PRE = 0x0
5022 22:20:03.718503 WR_PRE = 0x1
5023 22:20:03.721373 WR_PST = 0x0
5024 22:20:03.721478 DBI_WR = 0x0
5025 22:20:03.725321 DBI_RD = 0x0
5026 22:20:03.725425 OTF = 0x1
5027 22:20:03.728026 ===================================
5028 22:20:03.731650 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5029 22:20:03.734947 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5030 22:20:03.741179 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 22:20:03.744400 ===================================
5032 22:20:03.747810 LPDDR4 DRAM CONFIGURATION
5033 22:20:03.751670 ===================================
5034 22:20:03.751764 EX_ROW_EN[0] = 0x10
5035 22:20:03.754569 EX_ROW_EN[1] = 0x0
5036 22:20:03.754680 LP4Y_EN = 0x0
5037 22:20:03.757625 WORK_FSP = 0x0
5038 22:20:03.757731 WL = 0x3
5039 22:20:03.761349 RL = 0x3
5040 22:20:03.761449 BL = 0x2
5041 22:20:03.764420 RPST = 0x0
5042 22:20:03.764544 RD_PRE = 0x0
5043 22:20:03.768161 WR_PRE = 0x1
5044 22:20:03.770750 WR_PST = 0x0
5045 22:20:03.770847 DBI_WR = 0x0
5046 22:20:03.774187 DBI_RD = 0x0
5047 22:20:03.774259 OTF = 0x1
5048 22:20:03.777520 ===================================
5049 22:20:03.784582 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5050 22:20:03.787972 nWR fixed to 30
5051 22:20:03.791255 [ModeRegInit_LP4] CH0 RK0
5052 22:20:03.791375 [ModeRegInit_LP4] CH0 RK1
5053 22:20:03.794393 [ModeRegInit_LP4] CH1 RK0
5054 22:20:03.797876 [ModeRegInit_LP4] CH1 RK1
5055 22:20:03.797949 match AC timing 9
5056 22:20:03.804377 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5057 22:20:03.807597 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5058 22:20:03.810849 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5059 22:20:03.817946 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5060 22:20:03.820957 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5061 22:20:03.821035 ==
5062 22:20:03.824511 Dram Type= 6, Freq= 0, CH_0, rank 0
5063 22:20:03.827627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5064 22:20:03.827702 ==
5065 22:20:03.834454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5066 22:20:03.841038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5067 22:20:03.844278 [CA 0] Center 37 (7~68) winsize 62
5068 22:20:03.847703 [CA 1] Center 37 (7~68) winsize 62
5069 22:20:03.850593 [CA 2] Center 34 (4~65) winsize 62
5070 22:20:03.854036 [CA 3] Center 35 (5~65) winsize 61
5071 22:20:03.857155 [CA 4] Center 33 (3~64) winsize 62
5072 22:20:03.860791 [CA 5] Center 33 (4~63) winsize 60
5073 22:20:03.860892
5074 22:20:03.863999 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5075 22:20:03.864103
5076 22:20:03.867385 [CATrainingPosCal] consider 1 rank data
5077 22:20:03.870742 u2DelayCellTimex100 = 270/100 ps
5078 22:20:03.873640 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5079 22:20:03.877159 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5080 22:20:03.880301 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5081 22:20:03.883766 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5082 22:20:03.890318 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5083 22:20:03.893638 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5084 22:20:03.893717
5085 22:20:03.897325 CA PerBit enable=1, Macro0, CA PI delay=33
5086 22:20:03.897426
5087 22:20:03.900231 [CBTSetCACLKResult] CA Dly = 33
5088 22:20:03.900307 CS Dly: 7 (0~38)
5089 22:20:03.900409 ==
5090 22:20:03.903552 Dram Type= 6, Freq= 0, CH_0, rank 1
5091 22:20:03.910440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 22:20:03.910560 ==
5093 22:20:03.913171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 22:20:03.920107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5095 22:20:03.923277 [CA 0] Center 37 (7~68) winsize 62
5096 22:20:03.926699 [CA 1] Center 37 (7~68) winsize 62
5097 22:20:03.929802 [CA 2] Center 34 (4~65) winsize 62
5098 22:20:03.932879 [CA 3] Center 34 (4~65) winsize 62
5099 22:20:03.936322 [CA 4] Center 33 (3~64) winsize 62
5100 22:20:03.939930 [CA 5] Center 32 (2~63) winsize 62
5101 22:20:03.940028
5102 22:20:03.942795 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5103 22:20:03.942898
5104 22:20:03.946509 [CATrainingPosCal] consider 2 rank data
5105 22:20:03.949647 u2DelayCellTimex100 = 270/100 ps
5106 22:20:03.953099 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5107 22:20:03.959108 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5108 22:20:03.962631 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5109 22:20:03.966151 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5110 22:20:03.969274 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5111 22:20:03.973196 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5112 22:20:03.973299
5113 22:20:03.976311 CA PerBit enable=1, Macro0, CA PI delay=33
5114 22:20:03.976424
5115 22:20:03.978985 [CBTSetCACLKResult] CA Dly = 33
5116 22:20:03.982389 CS Dly: 7 (0~39)
5117 22:20:03.982489
5118 22:20:03.985775 ----->DramcWriteLeveling(PI) begin...
5119 22:20:03.985966 ==
5120 22:20:03.988954 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 22:20:03.992454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 22:20:03.992596 ==
5123 22:20:03.995484 Write leveling (Byte 0): 34 => 34
5124 22:20:03.999781 Write leveling (Byte 1): 29 => 29
5125 22:20:04.002116 DramcWriteLeveling(PI) end<-----
5126 22:20:04.002228
5127 22:20:04.002320 ==
5128 22:20:04.005475 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 22:20:04.008911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 22:20:04.008991 ==
5131 22:20:04.012189 [Gating] SW mode calibration
5132 22:20:04.018618 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5133 22:20:04.025298 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5134 22:20:04.028810 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5135 22:20:04.031887 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5136 22:20:04.038704 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 22:20:04.041890 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 22:20:04.045550 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 22:20:04.052004 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 22:20:04.054945 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 22:20:04.058448 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5142 22:20:04.064901 0 15 0 | B1->B0 | 3131 2424 | 0 0 | (1 0) (1 0)
5143 22:20:04.068183 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 22:20:04.071526 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 22:20:04.078748 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 22:20:04.081368 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 22:20:04.085339 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 22:20:04.091425 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5149 22:20:04.095319 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5150 22:20:04.098133 1 0 0 | B1->B0 | 2f2f 4444 | 1 0 | (0 0) (0 0)
5151 22:20:04.104361 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 22:20:04.107527 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 22:20:04.110927 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 22:20:04.117688 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 22:20:04.120937 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 22:20:04.124220 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 22:20:04.130937 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5158 22:20:04.134027 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5159 22:20:04.137574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5160 22:20:04.144331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 22:20:04.147092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 22:20:04.150701 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 22:20:04.157471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 22:20:04.160773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 22:20:04.164142 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 22:20:04.170575 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 22:20:04.174769 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 22:20:04.177526 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 22:20:04.184048 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 22:20:04.186944 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 22:20:04.190594 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 22:20:04.196768 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 22:20:04.200658 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5174 22:20:04.203626 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 22:20:04.206893 Total UI for P1: 0, mck2ui 16
5176 22:20:04.210741 best dqsien dly found for B0: ( 1, 2, 26)
5177 22:20:04.213819 Total UI for P1: 0, mck2ui 16
5178 22:20:04.217127 best dqsien dly found for B1: ( 1, 2, 30)
5179 22:20:04.220336 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5180 22:20:04.223621 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5181 22:20:04.223721
5182 22:20:04.230199 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5183 22:20:04.233196 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5184 22:20:04.236369 [Gating] SW calibration Done
5185 22:20:04.236472 ==
5186 22:20:04.240131 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 22:20:04.243041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 22:20:04.243145 ==
5189 22:20:04.243246 RX Vref Scan: 0
5190 22:20:04.243346
5191 22:20:04.246321 RX Vref 0 -> 0, step: 1
5192 22:20:04.246422
5193 22:20:04.249847 RX Delay -80 -> 252, step: 8
5194 22:20:04.253732 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5195 22:20:04.256282 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5196 22:20:04.262977 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5197 22:20:04.266082 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5198 22:20:04.269881 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5199 22:20:04.272717 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5200 22:20:04.276038 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5201 22:20:04.279659 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5202 22:20:04.286006 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5203 22:20:04.289615 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5204 22:20:04.292680 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5205 22:20:04.296258 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5206 22:20:04.299473 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5207 22:20:04.305879 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5208 22:20:04.309297 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5209 22:20:04.312819 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5210 22:20:04.312928 ==
5211 22:20:04.316082 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 22:20:04.319038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 22:20:04.319142 ==
5214 22:20:04.322564 DQS Delay:
5215 22:20:04.322671 DQS0 = 0, DQS1 = 0
5216 22:20:04.325939 DQM Delay:
5217 22:20:04.326046 DQM0 = 97, DQM1 = 85
5218 22:20:04.326146 DQ Delay:
5219 22:20:04.329046 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5220 22:20:04.332354 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5221 22:20:04.335908 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5222 22:20:04.339201 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5223 22:20:04.339299
5224 22:20:04.339401
5225 22:20:04.342662 ==
5226 22:20:04.345774 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 22:20:04.349143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 22:20:04.349247 ==
5229 22:20:04.349349
5230 22:20:04.349438
5231 22:20:04.352405 TX Vref Scan disable
5232 22:20:04.352504 == TX Byte 0 ==
5233 22:20:04.355559 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5234 22:20:04.362011 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5235 22:20:04.362115 == TX Byte 1 ==
5236 22:20:04.368967 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5237 22:20:04.372306 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5238 22:20:04.372424 ==
5239 22:20:04.375468 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 22:20:04.378793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 22:20:04.378872 ==
5242 22:20:04.378938
5243 22:20:04.378999
5244 22:20:04.381907 TX Vref Scan disable
5245 22:20:04.385500 == TX Byte 0 ==
5246 22:20:04.388546 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5247 22:20:04.391529 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5248 22:20:04.395290 == TX Byte 1 ==
5249 22:20:04.398420 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5250 22:20:04.401855 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5251 22:20:04.401929
5252 22:20:04.404956 [DATLAT]
5253 22:20:04.405031 Freq=933, CH0 RK0
5254 22:20:04.405096
5255 22:20:04.408996 DATLAT Default: 0xd
5256 22:20:04.409071 0, 0xFFFF, sum = 0
5257 22:20:04.411861 1, 0xFFFF, sum = 0
5258 22:20:04.411933 2, 0xFFFF, sum = 0
5259 22:20:04.415029 3, 0xFFFF, sum = 0
5260 22:20:04.415106 4, 0xFFFF, sum = 0
5261 22:20:04.418103 5, 0xFFFF, sum = 0
5262 22:20:04.418175 6, 0xFFFF, sum = 0
5263 22:20:04.421280 7, 0xFFFF, sum = 0
5264 22:20:04.421350 8, 0xFFFF, sum = 0
5265 22:20:04.424467 9, 0xFFFF, sum = 0
5266 22:20:04.424600 10, 0x0, sum = 1
5267 22:20:04.427815 11, 0x0, sum = 2
5268 22:20:04.427892 12, 0x0, sum = 3
5269 22:20:04.431193 13, 0x0, sum = 4
5270 22:20:04.431264 best_step = 11
5271 22:20:04.431325
5272 22:20:04.431389 ==
5273 22:20:04.434358 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 22:20:04.441006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 22:20:04.441080 ==
5276 22:20:04.441142 RX Vref Scan: 1
5277 22:20:04.441200
5278 22:20:04.444586 RX Vref 0 -> 0, step: 1
5279 22:20:04.444686
5280 22:20:04.447556 RX Delay -61 -> 252, step: 4
5281 22:20:04.447653
5282 22:20:04.451169 Set Vref, RX VrefLevel [Byte0]: 61
5283 22:20:04.454311 [Byte1]: 57
5284 22:20:04.454407
5285 22:20:04.457609 Final RX Vref Byte 0 = 61 to rank0
5286 22:20:04.461265 Final RX Vref Byte 1 = 57 to rank0
5287 22:20:04.464117 Final RX Vref Byte 0 = 61 to rank1
5288 22:20:04.467928 Final RX Vref Byte 1 = 57 to rank1==
5289 22:20:04.470924 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 22:20:04.473868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 22:20:04.477315 ==
5292 22:20:04.477391 DQS Delay:
5293 22:20:04.477454 DQS0 = 0, DQS1 = 0
5294 22:20:04.481036 DQM Delay:
5295 22:20:04.481136 DQM0 = 97, DQM1 = 86
5296 22:20:04.484037 DQ Delay:
5297 22:20:04.484133 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5298 22:20:04.487488 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5299 22:20:04.490439 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =82
5300 22:20:04.497618 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5301 22:20:04.497729
5302 22:20:04.497820
5303 22:20:04.504075 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5304 22:20:04.507077 CH0 RK0: MR19=505, MR18=2C13
5305 22:20:04.514942 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5306 22:20:04.515051
5307 22:20:04.517000 ----->DramcWriteLeveling(PI) begin...
5308 22:20:04.517073 ==
5309 22:20:04.520386 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 22:20:04.523708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 22:20:04.523781 ==
5312 22:20:04.526643 Write leveling (Byte 0): 33 => 33
5313 22:20:04.530052 Write leveling (Byte 1): 32 => 32
5314 22:20:04.533413 DramcWriteLeveling(PI) end<-----
5315 22:20:04.533518
5316 22:20:04.533606 ==
5317 22:20:04.536490 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 22:20:04.539907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 22:20:04.539981 ==
5320 22:20:04.543879 [Gating] SW mode calibration
5321 22:20:04.550523 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5322 22:20:04.556616 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5323 22:20:04.560235 0 14 0 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
5324 22:20:04.566776 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 22:20:04.569775 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 22:20:04.573550 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 22:20:04.580001 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 22:20:04.582809 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 22:20:04.586303 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 22:20:04.592801 0 14 28 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 1)
5331 22:20:04.596012 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
5332 22:20:04.599295 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 22:20:04.606273 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 22:20:04.609258 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 22:20:04.612647 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 22:20:04.618860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 22:20:04.622551 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 22:20:04.625856 0 15 28 | B1->B0 | 2b2b 3232 | 0 1 | (0 0) (0 0)
5339 22:20:04.632334 1 0 0 | B1->B0 | 3c3c 4343 | 0 1 | (0 0) (0 0)
5340 22:20:04.635354 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 22:20:04.638995 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 22:20:04.645654 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 22:20:04.648899 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 22:20:04.652057 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 22:20:04.659066 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 22:20:04.662289 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 22:20:04.665322 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 22:20:04.672023 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 22:20:04.675522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 22:20:04.678750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 22:20:04.685426 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 22:20:04.688386 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 22:20:04.691556 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 22:20:04.698160 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 22:20:04.701775 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 22:20:04.704935 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 22:20:04.711823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 22:20:04.714807 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 22:20:04.718259 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 22:20:04.725069 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 22:20:04.728231 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 22:20:04.731492 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5363 22:20:04.737896 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5364 22:20:04.737977 Total UI for P1: 0, mck2ui 16
5365 22:20:04.741635 best dqsien dly found for B0: ( 1, 2, 28)
5366 22:20:04.747976 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 22:20:04.751426 Total UI for P1: 0, mck2ui 16
5368 22:20:04.754564 best dqsien dly found for B1: ( 1, 3, 0)
5369 22:20:04.757506 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5370 22:20:04.761051 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5371 22:20:04.761122
5372 22:20:04.764577 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5373 22:20:04.767621 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5374 22:20:04.771093 [Gating] SW calibration Done
5375 22:20:04.771191 ==
5376 22:20:04.774366 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 22:20:04.777246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 22:20:04.777344 ==
5379 22:20:04.780982 RX Vref Scan: 0
5380 22:20:04.781055
5381 22:20:04.784372 RX Vref 0 -> 0, step: 1
5382 22:20:04.784467
5383 22:20:04.784563 RX Delay -80 -> 252, step: 8
5384 22:20:04.790895 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5385 22:20:04.794095 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5386 22:20:04.797359 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5387 22:20:04.800499 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5388 22:20:04.804401 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5389 22:20:04.810436 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5390 22:20:04.813648 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5391 22:20:04.816903 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5392 22:20:04.820315 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5393 22:20:04.823946 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5394 22:20:04.826888 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5395 22:20:04.833810 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5396 22:20:04.837008 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5397 22:20:04.840064 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5398 22:20:04.843559 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5399 22:20:04.846706 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5400 22:20:04.849806 ==
5401 22:20:04.853145 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 22:20:04.856397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 22:20:04.856479 ==
5404 22:20:04.856584 DQS Delay:
5405 22:20:04.859632 DQS0 = 0, DQS1 = 0
5406 22:20:04.859706 DQM Delay:
5407 22:20:04.862986 DQM0 = 97, DQM1 = 89
5408 22:20:04.863058 DQ Delay:
5409 22:20:04.866725 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5410 22:20:04.870673 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5411 22:20:04.873100 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5412 22:20:04.876171 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5413 22:20:04.876246
5414 22:20:04.876306
5415 22:20:04.876363 ==
5416 22:20:04.880281 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 22:20:04.882533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 22:20:04.882608 ==
5419 22:20:04.882668
5420 22:20:04.885959
5421 22:20:04.886032 TX Vref Scan disable
5422 22:20:04.889631 == TX Byte 0 ==
5423 22:20:04.893135 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5424 22:20:04.896555 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5425 22:20:04.899648 == TX Byte 1 ==
5426 22:20:04.903001 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5427 22:20:04.906151 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5428 22:20:04.906231 ==
5429 22:20:04.909277 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 22:20:04.915634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 22:20:04.915708 ==
5432 22:20:04.915782
5433 22:20:04.915842
5434 22:20:04.915898 TX Vref Scan disable
5435 22:20:04.919849 == TX Byte 0 ==
5436 22:20:04.923831 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5437 22:20:04.929891 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5438 22:20:04.929976 == TX Byte 1 ==
5439 22:20:04.934080 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5440 22:20:04.939780 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5441 22:20:04.939851
5442 22:20:04.939913 [DATLAT]
5443 22:20:04.939980 Freq=933, CH0 RK1
5444 22:20:04.940039
5445 22:20:04.943047 DATLAT Default: 0xb
5446 22:20:04.943113 0, 0xFFFF, sum = 0
5447 22:20:04.946322 1, 0xFFFF, sum = 0
5448 22:20:04.949617 2, 0xFFFF, sum = 0
5449 22:20:04.949689 3, 0xFFFF, sum = 0
5450 22:20:04.953310 4, 0xFFFF, sum = 0
5451 22:20:04.953381 5, 0xFFFF, sum = 0
5452 22:20:04.956358 6, 0xFFFF, sum = 0
5453 22:20:04.956426 7, 0xFFFF, sum = 0
5454 22:20:04.959667 8, 0xFFFF, sum = 0
5455 22:20:04.959747 9, 0xFFFF, sum = 0
5456 22:20:04.963093 10, 0x0, sum = 1
5457 22:20:04.963169 11, 0x0, sum = 2
5458 22:20:04.966306 12, 0x0, sum = 3
5459 22:20:04.966377 13, 0x0, sum = 4
5460 22:20:04.969666 best_step = 11
5461 22:20:04.969740
5462 22:20:04.969832 ==
5463 22:20:04.972658 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 22:20:04.976271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 22:20:04.976340 ==
5466 22:20:04.976401 RX Vref Scan: 0
5467 22:20:04.976467
5468 22:20:04.979827 RX Vref 0 -> 0, step: 1
5469 22:20:04.979902
5470 22:20:04.983093 RX Delay -61 -> 252, step: 4
5471 22:20:04.989285 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5472 22:20:04.992954 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5473 22:20:04.996111 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5474 22:20:04.999178 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5475 22:20:05.002839 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5476 22:20:05.005769 iDelay=203, Bit 5, Center 88 (-9 ~ 186) 196
5477 22:20:05.012678 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5478 22:20:05.015917 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5479 22:20:05.018984 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5480 22:20:05.022234 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5481 22:20:05.025679 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5482 22:20:05.032242 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5483 22:20:05.036096 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5484 22:20:05.038613 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5485 22:20:05.041824 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5486 22:20:05.045189 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5487 22:20:05.045263 ==
5488 22:20:05.048951 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 22:20:05.055222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 22:20:05.055294 ==
5491 22:20:05.055360 DQS Delay:
5492 22:20:05.058363 DQS0 = 0, DQS1 = 0
5493 22:20:05.058459 DQM Delay:
5494 22:20:05.061940 DQM0 = 95, DQM1 = 88
5495 22:20:05.062013 DQ Delay:
5496 22:20:05.065030 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5497 22:20:05.068359 DQ4 =96, DQ5 =88, DQ6 =104, DQ7 =104
5498 22:20:05.071370 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5499 22:20:05.075239 DQ12 =92, DQ13 =94, DQ14 =96, DQ15 =92
5500 22:20:05.075308
5501 22:20:05.075371
5502 22:20:05.081242 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5503 22:20:05.084675 CH0 RK1: MR19=504, MR18=25F6
5504 22:20:05.091125 CH0_RK1: MR19=0x504, MR18=0x25F6, DQSOSC=410, MR23=63, INC=64, DEC=42
5505 22:20:05.095267 [RxdqsGatingPostProcess] freq 933
5506 22:20:05.101540 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 22:20:05.104980 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 22:20:05.105068 best DQS1 dly(2T, 0.5T) = (0, 10)
5509 22:20:05.107693 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 22:20:05.111154 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5511 22:20:05.114307 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 22:20:05.117983 best DQS1 dly(2T, 0.5T) = (0, 11)
5513 22:20:05.120933 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 22:20:05.124676 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5515 22:20:05.127626 Pre-setting of DQS Precalculation
5516 22:20:05.134570 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 22:20:05.134658 ==
5518 22:20:05.138458 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 22:20:05.141155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 22:20:05.141258 ==
5521 22:20:05.148106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 22:20:05.150902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 22:20:05.155066 [CA 0] Center 36 (6~67) winsize 62
5524 22:20:05.159016 [CA 1] Center 37 (6~68) winsize 63
5525 22:20:05.161755 [CA 2] Center 34 (4~65) winsize 62
5526 22:20:05.165095 [CA 3] Center 33 (3~64) winsize 62
5527 22:20:05.168408 [CA 4] Center 34 (4~64) winsize 61
5528 22:20:05.171723 [CA 5] Center 33 (3~64) winsize 62
5529 22:20:05.171806
5530 22:20:05.175044 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 22:20:05.175126
5532 22:20:05.178589 [CATrainingPosCal] consider 1 rank data
5533 22:20:05.181707 u2DelayCellTimex100 = 270/100 ps
5534 22:20:05.184746 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 22:20:05.191460 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5536 22:20:05.194766 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5537 22:20:05.197770 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 22:20:05.201445 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5539 22:20:05.204861 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 22:20:05.204944
5541 22:20:05.207584 CA PerBit enable=1, Macro0, CA PI delay=33
5542 22:20:05.207700
5543 22:20:05.211654 [CBTSetCACLKResult] CA Dly = 33
5544 22:20:05.214973 CS Dly: 5 (0~36)
5545 22:20:05.215054 ==
5546 22:20:05.217847 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 22:20:05.221003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 22:20:05.221085 ==
5549 22:20:05.227620 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 22:20:05.231175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5551 22:20:05.234892 [CA 0] Center 36 (6~67) winsize 62
5552 22:20:05.238370 [CA 1] Center 36 (6~67) winsize 62
5553 22:20:05.241692 [CA 2] Center 34 (3~65) winsize 63
5554 22:20:05.245868 [CA 3] Center 33 (3~64) winsize 62
5555 22:20:05.248061 [CA 4] Center 34 (3~65) winsize 63
5556 22:20:05.251809 [CA 5] Center 33 (3~64) winsize 62
5557 22:20:05.251889
5558 22:20:05.254856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5559 22:20:05.254938
5560 22:20:05.258032 [CATrainingPosCal] consider 2 rank data
5561 22:20:05.261597 u2DelayCellTimex100 = 270/100 ps
5562 22:20:05.265059 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 22:20:05.271292 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 22:20:05.274606 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 22:20:05.277647 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 22:20:05.281193 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5567 22:20:05.284489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5568 22:20:05.284584
5569 22:20:05.287840 CA PerBit enable=1, Macro0, CA PI delay=33
5570 22:20:05.287921
5571 22:20:05.291165 [CBTSetCACLKResult] CA Dly = 33
5572 22:20:05.294852 CS Dly: 6 (0~39)
5573 22:20:05.294931
5574 22:20:05.297617 ----->DramcWriteLeveling(PI) begin...
5575 22:20:05.297699 ==
5576 22:20:05.301469 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 22:20:05.304385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 22:20:05.304490 ==
5579 22:20:05.307290 Write leveling (Byte 0): 25 => 25
5580 22:20:05.311097 Write leveling (Byte 1): 30 => 30
5581 22:20:05.314255 DramcWriteLeveling(PI) end<-----
5582 22:20:05.314335
5583 22:20:05.314398 ==
5584 22:20:05.317808 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 22:20:05.320448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 22:20:05.320594 ==
5587 22:20:05.323843 [Gating] SW mode calibration
5588 22:20:05.330507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 22:20:05.337009 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 22:20:05.340479 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5591 22:20:05.347532 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 22:20:05.350473 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 22:20:05.353735 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 22:20:05.360267 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 22:20:05.363321 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5596 22:20:05.366582 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 1)
5597 22:20:05.373237 0 14 28 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (1 1)
5598 22:20:05.376494 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5599 22:20:05.380088 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 22:20:05.387294 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 22:20:05.390104 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 22:20:05.393661 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 22:20:05.399784 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 22:20:05.403265 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5605 22:20:05.406413 0 15 28 | B1->B0 | 3535 3c3c | 0 0 | (0 0) (0 0)
5606 22:20:05.409708 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 22:20:05.416453 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 22:20:05.419584 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 22:20:05.425993 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 22:20:05.429193 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 22:20:05.432479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 22:20:05.438857 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5613 22:20:05.442542 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 22:20:05.445961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 22:20:05.452416 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 22:20:05.456156 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 22:20:05.459096 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 22:20:05.462231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 22:20:05.468808 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 22:20:05.472571 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 22:20:05.475626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 22:20:05.482048 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 22:20:05.485470 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 22:20:05.492203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 22:20:05.495681 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 22:20:05.498832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 22:20:05.501976 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 22:20:05.508488 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5629 22:20:05.512110 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 22:20:05.515045 Total UI for P1: 0, mck2ui 16
5631 22:20:05.518439 best dqsien dly found for B0: ( 1, 2, 24)
5632 22:20:05.521902 Total UI for P1: 0, mck2ui 16
5633 22:20:05.525113 best dqsien dly found for B1: ( 1, 2, 24)
5634 22:20:05.528609 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5635 22:20:05.531663 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5636 22:20:05.531765
5637 22:20:05.535130 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5638 22:20:05.541412 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5639 22:20:05.541517 [Gating] SW calibration Done
5640 22:20:05.541614 ==
5641 22:20:05.544767 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 22:20:05.551222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 22:20:05.551337 ==
5644 22:20:05.551431 RX Vref Scan: 0
5645 22:20:05.551528
5646 22:20:05.555047 RX Vref 0 -> 0, step: 1
5647 22:20:05.555137
5648 22:20:05.557969 RX Delay -80 -> 252, step: 8
5649 22:20:05.561228 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5650 22:20:05.564896 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5651 22:20:05.567743 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5652 22:20:05.574379 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5653 22:20:05.577892 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5654 22:20:05.581146 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5655 22:20:05.584445 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5656 22:20:05.587835 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5657 22:20:05.591022 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5658 22:20:05.597538 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5659 22:20:05.601005 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5660 22:20:05.603800 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5661 22:20:05.607553 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5662 22:20:05.610814 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5663 22:20:05.617614 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5664 22:20:05.620547 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5665 22:20:05.620622 ==
5666 22:20:05.624153 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 22:20:05.627032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 22:20:05.627140 ==
5669 22:20:05.630621 DQS Delay:
5670 22:20:05.630733 DQS0 = 0, DQS1 = 0
5671 22:20:05.630843 DQM Delay:
5672 22:20:05.633690 DQM0 = 101, DQM1 = 91
5673 22:20:05.633802 DQ Delay:
5674 22:20:05.636885 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5675 22:20:05.640420 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =95
5676 22:20:05.643361 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5677 22:20:05.647056 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5678 22:20:05.647164
5679 22:20:05.647268
5680 22:20:05.650426 ==
5681 22:20:05.650542 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 22:20:05.657364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 22:20:05.657474 ==
5684 22:20:05.657583
5685 22:20:05.657673
5686 22:20:05.660128 TX Vref Scan disable
5687 22:20:05.660254 == TX Byte 0 ==
5688 22:20:05.663158 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5689 22:20:05.670059 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5690 22:20:05.670177 == TX Byte 1 ==
5691 22:20:05.676373 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5692 22:20:05.679981 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5693 22:20:05.680094 ==
5694 22:20:05.683034 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 22:20:05.686123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 22:20:05.686237 ==
5697 22:20:05.686335
5698 22:20:05.686429
5699 22:20:05.689633 TX Vref Scan disable
5700 22:20:05.692825 == TX Byte 0 ==
5701 22:20:05.696372 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 22:20:05.700004 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 22:20:05.703090 == TX Byte 1 ==
5704 22:20:05.706470 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5705 22:20:05.709417 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5706 22:20:05.709499
5707 22:20:05.712843 [DATLAT]
5708 22:20:05.712926 Freq=933, CH1 RK0
5709 22:20:05.712992
5710 22:20:05.716219 DATLAT Default: 0xd
5711 22:20:05.716327 0, 0xFFFF, sum = 0
5712 22:20:05.719361 1, 0xFFFF, sum = 0
5713 22:20:05.719470 2, 0xFFFF, sum = 0
5714 22:20:05.722613 3, 0xFFFF, sum = 0
5715 22:20:05.722726 4, 0xFFFF, sum = 0
5716 22:20:05.726155 5, 0xFFFF, sum = 0
5717 22:20:05.726242 6, 0xFFFF, sum = 0
5718 22:20:05.729648 7, 0xFFFF, sum = 0
5719 22:20:05.729732 8, 0xFFFF, sum = 0
5720 22:20:05.733277 9, 0xFFFF, sum = 0
5721 22:20:05.733364 10, 0x0, sum = 1
5722 22:20:05.736231 11, 0x0, sum = 2
5723 22:20:05.736314 12, 0x0, sum = 3
5724 22:20:05.739282 13, 0x0, sum = 4
5725 22:20:05.739366 best_step = 11
5726 22:20:05.739430
5727 22:20:05.739491 ==
5728 22:20:05.742947 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 22:20:05.749239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 22:20:05.749322 ==
5731 22:20:05.749396 RX Vref Scan: 1
5732 22:20:05.749459
5733 22:20:05.753528 RX Vref 0 -> 0, step: 1
5734 22:20:05.753610
5735 22:20:05.755963 RX Delay -61 -> 252, step: 4
5736 22:20:05.756035
5737 22:20:05.759359 Set Vref, RX VrefLevel [Byte0]: 50
5738 22:20:05.762394 [Byte1]: 53
5739 22:20:05.762496
5740 22:20:05.765615 Final RX Vref Byte 0 = 50 to rank0
5741 22:20:05.768779 Final RX Vref Byte 1 = 53 to rank0
5742 22:20:05.772443 Final RX Vref Byte 0 = 50 to rank1
5743 22:20:05.775263 Final RX Vref Byte 1 = 53 to rank1==
5744 22:20:05.778755 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 22:20:05.782109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 22:20:05.782181 ==
5747 22:20:05.785243 DQS Delay:
5748 22:20:05.785313 DQS0 = 0, DQS1 = 0
5749 22:20:05.788694 DQM Delay:
5750 22:20:05.788768 DQM0 = 101, DQM1 = 94
5751 22:20:05.788828 DQ Delay:
5752 22:20:05.791782 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5753 22:20:05.795330 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5754 22:20:05.798521 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =86
5755 22:20:05.805128 DQ12 =102, DQ13 =98, DQ14 =104, DQ15 =104
5756 22:20:05.805205
5757 22:20:05.805267
5758 22:20:05.811493 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5759 22:20:05.814759 CH1 RK0: MR19=505, MR18=1E0E
5760 22:20:05.821314 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5761 22:20:05.821397
5762 22:20:05.824791 ----->DramcWriteLeveling(PI) begin...
5763 22:20:05.824864 ==
5764 22:20:05.828146 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 22:20:05.831103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 22:20:05.831174 ==
5767 22:20:05.834967 Write leveling (Byte 0): 25 => 25
5768 22:20:05.837934 Write leveling (Byte 1): 30 => 30
5769 22:20:05.841556 DramcWriteLeveling(PI) end<-----
5770 22:20:05.841634
5771 22:20:05.841698 ==
5772 22:20:05.844861 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 22:20:05.847966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 22:20:05.848037 ==
5775 22:20:05.851264 [Gating] SW mode calibration
5776 22:20:05.858096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5777 22:20:05.864282 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5778 22:20:05.867698 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 22:20:05.874052 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 22:20:05.877583 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 22:20:05.880980 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 22:20:05.887382 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 22:20:05.890824 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5784 22:20:05.893829 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
5785 22:20:05.900630 0 14 28 | B1->B0 | 2e2e 3131 | 1 1 | (1 0) (1 0)
5786 22:20:05.903798 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 22:20:05.907130 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 22:20:05.913599 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 22:20:05.917068 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 22:20:05.920479 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 22:20:05.926856 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 22:20:05.930115 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5793 22:20:05.933513 0 15 28 | B1->B0 | 3a3a 3535 | 0 1 | (0 0) (0 0)
5794 22:20:05.940335 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 22:20:05.943787 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 22:20:05.946702 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 22:20:05.953732 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 22:20:05.956430 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 22:20:05.960088 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 22:20:05.966444 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 22:20:05.969753 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5802 22:20:05.973182 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 22:20:05.979745 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 22:20:05.983004 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 22:20:05.986257 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 22:20:05.993076 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 22:20:05.996163 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 22:20:05.999991 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 22:20:06.006063 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 22:20:06.009566 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 22:20:06.012819 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 22:20:06.019111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 22:20:06.023232 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 22:20:06.026497 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 22:20:06.032672 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 22:20:06.036210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5817 22:20:06.039118 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5818 22:20:06.046108 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 22:20:06.046195 Total UI for P1: 0, mck2ui 16
5820 22:20:06.052299 best dqsien dly found for B0: ( 1, 2, 30)
5821 22:20:06.052384 Total UI for P1: 0, mck2ui 16
5822 22:20:06.059010 best dqsien dly found for B1: ( 1, 2, 26)
5823 22:20:06.062488 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5824 22:20:06.065684 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5825 22:20:06.065766
5826 22:20:06.068924 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5827 22:20:06.072307 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5828 22:20:06.075469 [Gating] SW calibration Done
5829 22:20:06.075551 ==
5830 22:20:06.078689 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 22:20:06.082433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 22:20:06.082540 ==
5833 22:20:06.085315 RX Vref Scan: 0
5834 22:20:06.085397
5835 22:20:06.085461 RX Vref 0 -> 0, step: 1
5836 22:20:06.085520
5837 22:20:06.088524 RX Delay -80 -> 252, step: 8
5838 22:20:06.092372 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5839 22:20:06.098344 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5840 22:20:06.101734 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5841 22:20:06.105103 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5842 22:20:06.108663 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5843 22:20:06.112206 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5844 22:20:06.115028 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5845 22:20:06.121342 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5846 22:20:06.125276 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5847 22:20:06.128245 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5848 22:20:06.131271 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5849 22:20:06.134527 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5850 22:20:06.141437 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5851 22:20:06.144377 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5852 22:20:06.148030 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5853 22:20:06.151673 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5854 22:20:06.151754 ==
5855 22:20:06.154310 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:20:06.161013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:20:06.161096 ==
5858 22:20:06.161161 DQS Delay:
5859 22:20:06.161222 DQS0 = 0, DQS1 = 0
5860 22:20:06.164464 DQM Delay:
5861 22:20:06.164581 DQM0 = 99, DQM1 = 90
5862 22:20:06.167451 DQ Delay:
5863 22:20:06.170868 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =95
5864 22:20:06.174651 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5865 22:20:06.177293 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5866 22:20:06.180579 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5867 22:20:06.180661
5868 22:20:06.180726
5869 22:20:06.180786 ==
5870 22:20:06.184576 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 22:20:06.187277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 22:20:06.187359 ==
5873 22:20:06.187424
5874 22:20:06.187484
5875 22:20:06.190500 TX Vref Scan disable
5876 22:20:06.190582 == TX Byte 0 ==
5877 22:20:06.197386 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5878 22:20:06.200899 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5879 22:20:06.204197 == TX Byte 1 ==
5880 22:20:06.207094 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5881 22:20:06.210621 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5882 22:20:06.210703 ==
5883 22:20:06.213765 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 22:20:06.217264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 22:20:06.217348 ==
5886 22:20:06.220405
5887 22:20:06.220487
5888 22:20:06.220591 TX Vref Scan disable
5889 22:20:06.223869 == TX Byte 0 ==
5890 22:20:06.227140 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5891 22:20:06.234054 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5892 22:20:06.234137 == TX Byte 1 ==
5893 22:20:06.236951 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5894 22:20:06.243462 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5895 22:20:06.243544
5896 22:20:06.243608 [DATLAT]
5897 22:20:06.243668 Freq=933, CH1 RK1
5898 22:20:06.243727
5899 22:20:06.247118 DATLAT Default: 0xb
5900 22:20:06.247201 0, 0xFFFF, sum = 0
5901 22:20:06.250200 1, 0xFFFF, sum = 0
5902 22:20:06.253353 2, 0xFFFF, sum = 0
5903 22:20:06.253436 3, 0xFFFF, sum = 0
5904 22:20:06.256936 4, 0xFFFF, sum = 0
5905 22:20:06.257023 5, 0xFFFF, sum = 0
5906 22:20:06.260503 6, 0xFFFF, sum = 0
5907 22:20:06.260621 7, 0xFFFF, sum = 0
5908 22:20:06.263444 8, 0xFFFF, sum = 0
5909 22:20:06.263518 9, 0xFFFF, sum = 0
5910 22:20:06.266696 10, 0x0, sum = 1
5911 22:20:06.266769 11, 0x0, sum = 2
5912 22:20:06.270074 12, 0x0, sum = 3
5913 22:20:06.270150 13, 0x0, sum = 4
5914 22:20:06.270229 best_step = 11
5915 22:20:06.273457
5916 22:20:06.273530 ==
5917 22:20:06.276826 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 22:20:06.280092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 22:20:06.280166 ==
5920 22:20:06.280264 RX Vref Scan: 0
5921 22:20:06.280362
5922 22:20:06.283249 RX Vref 0 -> 0, step: 1
5923 22:20:06.283324
5924 22:20:06.286422 RX Delay -69 -> 252, step: 4
5925 22:20:06.293054 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5926 22:20:06.296434 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5927 22:20:06.299811 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5928 22:20:06.303011 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5929 22:20:06.306661 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5930 22:20:06.309527 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5931 22:20:06.316277 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5932 22:20:06.320114 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5933 22:20:06.323014 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5934 22:20:06.326021 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5935 22:20:06.329540 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5936 22:20:06.336230 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5937 22:20:06.339294 iDelay=207, Bit 12, Center 100 (7 ~ 194) 188
5938 22:20:06.342693 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5939 22:20:06.346037 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5940 22:20:06.349513 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5941 22:20:06.349626 ==
5942 22:20:06.352678 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 22:20:06.359101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 22:20:06.359185 ==
5945 22:20:06.359249 DQS Delay:
5946 22:20:06.362516 DQS0 = 0, DQS1 = 0
5947 22:20:06.362596 DQM Delay:
5948 22:20:06.362661 DQM0 = 101, DQM1 = 93
5949 22:20:06.365949 DQ Delay:
5950 22:20:06.368918 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5951 22:20:06.372320 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
5952 22:20:06.375703 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5953 22:20:06.379195 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5954 22:20:06.379276
5955 22:20:06.379339
5956 22:20:06.385636 [DQSOSCAuto] RK1, (LSB)MR18= 0x4fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5957 22:20:06.388917 CH1 RK1: MR19=504, MR18=4FE
5958 22:20:06.395604 CH1_RK1: MR19=0x504, MR18=0x4FE, DQSOSC=420, MR23=63, INC=61, DEC=40
5959 22:20:06.399354 [RxdqsGatingPostProcess] freq 933
5960 22:20:06.405882 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5961 22:20:06.405964 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 22:20:06.408561 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 22:20:06.412315 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 22:20:06.415219 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 22:20:06.418882 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 22:20:06.421909 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 22:20:06.425155 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 22:20:06.428749 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 22:20:06.431762 Pre-setting of DQS Precalculation
5970 22:20:06.438512 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5971 22:20:06.445039 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5972 22:20:06.452267 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5973 22:20:06.452348
5974 22:20:06.452413
5975 22:20:06.455151 [Calibration Summary] 1866 Mbps
5976 22:20:06.455232 CH 0, Rank 0
5977 22:20:06.458558 SW Impedance : PASS
5978 22:20:06.461767 DUTY Scan : NO K
5979 22:20:06.461848 ZQ Calibration : PASS
5980 22:20:06.465151 Jitter Meter : NO K
5981 22:20:06.468373 CBT Training : PASS
5982 22:20:06.468454 Write leveling : PASS
5983 22:20:06.472224 RX DQS gating : PASS
5984 22:20:06.472305 RX DQ/DQS(RDDQC) : PASS
5985 22:20:06.475343 TX DQ/DQS : PASS
5986 22:20:06.478296 RX DATLAT : PASS
5987 22:20:06.478377 RX DQ/DQS(Engine): PASS
5988 22:20:06.481618 TX OE : NO K
5989 22:20:06.481699 All Pass.
5990 22:20:06.481764
5991 22:20:06.484537 CH 0, Rank 1
5992 22:20:06.484618 SW Impedance : PASS
5993 22:20:06.488250 DUTY Scan : NO K
5994 22:20:06.491190 ZQ Calibration : PASS
5995 22:20:06.491271 Jitter Meter : NO K
5996 22:20:06.495241 CBT Training : PASS
5997 22:20:06.497811 Write leveling : PASS
5998 22:20:06.497893 RX DQS gating : PASS
5999 22:20:06.501431 RX DQ/DQS(RDDQC) : PASS
6000 22:20:06.504954 TX DQ/DQS : PASS
6001 22:20:06.505034 RX DATLAT : PASS
6002 22:20:06.507672 RX DQ/DQS(Engine): PASS
6003 22:20:06.511176 TX OE : NO K
6004 22:20:06.511257 All Pass.
6005 22:20:06.511320
6006 22:20:06.511379 CH 1, Rank 0
6007 22:20:06.514587 SW Impedance : PASS
6008 22:20:06.518281 DUTY Scan : NO K
6009 22:20:06.518362 ZQ Calibration : PASS
6010 22:20:06.521216 Jitter Meter : NO K
6011 22:20:06.524724 CBT Training : PASS
6012 22:20:06.524805 Write leveling : PASS
6013 22:20:06.527870 RX DQS gating : PASS
6014 22:20:06.530891 RX DQ/DQS(RDDQC) : PASS
6015 22:20:06.530972 TX DQ/DQS : PASS
6016 22:20:06.534580 RX DATLAT : PASS
6017 22:20:06.537475 RX DQ/DQS(Engine): PASS
6018 22:20:06.537556 TX OE : NO K
6019 22:20:06.537621 All Pass.
6020 22:20:06.540984
6021 22:20:06.541064 CH 1, Rank 1
6022 22:20:06.544042 SW Impedance : PASS
6023 22:20:06.544122 DUTY Scan : NO K
6024 22:20:06.547355 ZQ Calibration : PASS
6025 22:20:06.550774 Jitter Meter : NO K
6026 22:20:06.550855 CBT Training : PASS
6027 22:20:06.554310 Write leveling : PASS
6028 22:20:06.554392 RX DQS gating : PASS
6029 22:20:06.557264 RX DQ/DQS(RDDQC) : PASS
6030 22:20:06.560811 TX DQ/DQS : PASS
6031 22:20:06.560892 RX DATLAT : PASS
6032 22:20:06.563759 RX DQ/DQS(Engine): PASS
6033 22:20:06.567080 TX OE : NO K
6034 22:20:06.567187 All Pass.
6035 22:20:06.567269
6036 22:20:06.570365 DramC Write-DBI off
6037 22:20:06.570445 PER_BANK_REFRESH: Hybrid Mode
6038 22:20:06.573597 TX_TRACKING: ON
6039 22:20:06.583949 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6040 22:20:06.587224 [FAST_K] Save calibration result to emmc
6041 22:20:06.590485 dramc_set_vcore_voltage set vcore to 650000
6042 22:20:06.590565 Read voltage for 400, 6
6043 22:20:06.593554 Vio18 = 0
6044 22:20:06.593635 Vcore = 650000
6045 22:20:06.593699 Vdram = 0
6046 22:20:06.596817 Vddq = 0
6047 22:20:06.596896 Vmddr = 0
6048 22:20:06.603488 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6049 22:20:06.607137 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6050 22:20:06.610007 MEM_TYPE=3, freq_sel=20
6051 22:20:06.613658 sv_algorithm_assistance_LP4_800
6052 22:20:06.616427 ============ PULL DRAM RESETB DOWN ============
6053 22:20:06.620251 ========== PULL DRAM RESETB DOWN end =========
6054 22:20:06.626946 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6055 22:20:06.630192 ===================================
6056 22:20:06.630275 LPDDR4 DRAM CONFIGURATION
6057 22:20:06.633225 ===================================
6058 22:20:06.636464 EX_ROW_EN[0] = 0x0
6059 22:20:06.639848 EX_ROW_EN[1] = 0x0
6060 22:20:06.639931 LP4Y_EN = 0x0
6061 22:20:06.643007 WORK_FSP = 0x0
6062 22:20:06.643089 WL = 0x2
6063 22:20:06.646252 RL = 0x2
6064 22:20:06.646334 BL = 0x2
6065 22:20:06.649744 RPST = 0x0
6066 22:20:06.649826 RD_PRE = 0x0
6067 22:20:06.653334 WR_PRE = 0x1
6068 22:20:06.653417 WR_PST = 0x0
6069 22:20:06.656769 DBI_WR = 0x0
6070 22:20:06.656851 DBI_RD = 0x0
6071 22:20:06.659498 OTF = 0x1
6072 22:20:06.662900 ===================================
6073 22:20:06.666348 ===================================
6074 22:20:06.666430 ANA top config
6075 22:20:06.669697 ===================================
6076 22:20:06.673026 DLL_ASYNC_EN = 0
6077 22:20:06.676253 ALL_SLAVE_EN = 1
6078 22:20:06.679395 NEW_RANK_MODE = 1
6079 22:20:06.679479 DLL_IDLE_MODE = 1
6080 22:20:06.682852 LP45_APHY_COMB_EN = 1
6081 22:20:06.686235 TX_ODT_DIS = 1
6082 22:20:06.689417 NEW_8X_MODE = 1
6083 22:20:06.693027 ===================================
6084 22:20:06.696203 ===================================
6085 22:20:06.699361 data_rate = 800
6086 22:20:06.699444 CKR = 1
6087 22:20:06.702777 DQ_P2S_RATIO = 4
6088 22:20:06.706258 ===================================
6089 22:20:06.709252 CA_P2S_RATIO = 4
6090 22:20:06.712894 DQ_CA_OPEN = 0
6091 22:20:06.715677 DQ_SEMI_OPEN = 1
6092 22:20:06.719434 CA_SEMI_OPEN = 1
6093 22:20:06.719516 CA_FULL_RATE = 0
6094 22:20:06.722460 DQ_CKDIV4_EN = 0
6095 22:20:06.725709 CA_CKDIV4_EN = 1
6096 22:20:06.729320 CA_PREDIV_EN = 0
6097 22:20:06.732767 PH8_DLY = 0
6098 22:20:06.735821 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6099 22:20:06.735903 DQ_AAMCK_DIV = 0
6100 22:20:06.739021 CA_AAMCK_DIV = 0
6101 22:20:06.742129 CA_ADMCK_DIV = 4
6102 22:20:06.745223 DQ_TRACK_CA_EN = 0
6103 22:20:06.748784 CA_PICK = 800
6104 22:20:06.752043 CA_MCKIO = 400
6105 22:20:06.755215 MCKIO_SEMI = 400
6106 22:20:06.758471 PLL_FREQ = 3016
6107 22:20:06.758552 DQ_UI_PI_RATIO = 32
6108 22:20:06.761924 CA_UI_PI_RATIO = 32
6109 22:20:06.765075 ===================================
6110 22:20:06.768519 ===================================
6111 22:20:06.771521 memory_type:LPDDR4
6112 22:20:06.774835 GP_NUM : 10
6113 22:20:06.774916 SRAM_EN : 1
6114 22:20:06.778845 MD32_EN : 0
6115 22:20:06.781323 ===================================
6116 22:20:06.785164 [ANA_INIT] >>>>>>>>>>>>>>
6117 22:20:06.785239 <<<<<< [CONFIGURE PHASE]: ANA_TX
6118 22:20:06.791689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6119 22:20:06.794721 ===================================
6120 22:20:06.794804 data_rate = 800,PCW = 0X7400
6121 22:20:06.798102 ===================================
6122 22:20:06.801944 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6123 22:20:06.808459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 22:20:06.818216 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 22:20:06.824449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6126 22:20:06.828095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6127 22:20:06.831173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6128 22:20:06.834341 [ANA_INIT] flow start
6129 22:20:06.834442 [ANA_INIT] PLL >>>>>>>>
6130 22:20:06.837780 [ANA_INIT] PLL <<<<<<<<
6131 22:20:06.841137 [ANA_INIT] MIDPI >>>>>>>>
6132 22:20:06.841211 [ANA_INIT] MIDPI <<<<<<<<
6133 22:20:06.844986 [ANA_INIT] DLL >>>>>>>>
6134 22:20:06.847703 [ANA_INIT] flow end
6135 22:20:06.850965 ============ LP4 DIFF to SE enter ============
6136 22:20:06.854264 ============ LP4 DIFF to SE exit ============
6137 22:20:06.857589 [ANA_INIT] <<<<<<<<<<<<<
6138 22:20:06.861124 [Flow] Enable top DCM control >>>>>
6139 22:20:06.863983 [Flow] Enable top DCM control <<<<<
6140 22:20:06.867789 Enable DLL master slave shuffle
6141 22:20:06.871225 ==============================================================
6142 22:20:06.874191 Gating Mode config
6143 22:20:06.880975 ==============================================================
6144 22:20:06.881074 Config description:
6145 22:20:06.890952 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6146 22:20:06.897274 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6147 22:20:06.903916 SELPH_MODE 0: By rank 1: By Phase
6148 22:20:06.907145 ==============================================================
6149 22:20:06.910526 GAT_TRACK_EN = 0
6150 22:20:06.913814 RX_GATING_MODE = 2
6151 22:20:06.917339 RX_GATING_TRACK_MODE = 2
6152 22:20:06.920209 SELPH_MODE = 1
6153 22:20:06.923331 PICG_EARLY_EN = 1
6154 22:20:06.926920 VALID_LAT_VALUE = 1
6155 22:20:06.929928 ==============================================================
6156 22:20:06.933705 Enter into Gating configuration >>>>
6157 22:20:06.936876 Exit from Gating configuration <<<<
6158 22:20:06.940209 Enter into DVFS_PRE_config >>>>>
6159 22:20:06.953238 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6160 22:20:06.956466 Exit from DVFS_PRE_config <<<<<
6161 22:20:06.959705 Enter into PICG configuration >>>>
6162 22:20:06.962931 Exit from PICG configuration <<<<
6163 22:20:06.963021 [RX_INPUT] configuration >>>>>
6164 22:20:06.966244 [RX_INPUT] configuration <<<<<
6165 22:20:06.972984 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6166 22:20:06.976437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6167 22:20:06.982814 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 22:20:06.989362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 22:20:06.996091 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 22:20:07.002933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 22:20:07.005724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6172 22:20:07.009283 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6173 22:20:07.016433 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6174 22:20:07.018729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6175 22:20:07.022501 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6176 22:20:07.028989 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 22:20:07.032310 ===================================
6178 22:20:07.032422 LPDDR4 DRAM CONFIGURATION
6179 22:20:07.035655 ===================================
6180 22:20:07.038770 EX_ROW_EN[0] = 0x0
6181 22:20:07.038851 EX_ROW_EN[1] = 0x0
6182 22:20:07.042308 LP4Y_EN = 0x0
6183 22:20:07.045101 WORK_FSP = 0x0
6184 22:20:07.045175 WL = 0x2
6185 22:20:07.048437 RL = 0x2
6186 22:20:07.048578 BL = 0x2
6187 22:20:07.052285 RPST = 0x0
6188 22:20:07.052393 RD_PRE = 0x0
6189 22:20:07.055528 WR_PRE = 0x1
6190 22:20:07.055609 WR_PST = 0x0
6191 22:20:07.058800 DBI_WR = 0x0
6192 22:20:07.058882 DBI_RD = 0x0
6193 22:20:07.062059 OTF = 0x1
6194 22:20:07.065491 ===================================
6195 22:20:07.068488 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6196 22:20:07.072006 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6197 22:20:07.078098 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 22:20:07.081476 ===================================
6199 22:20:07.081558 LPDDR4 DRAM CONFIGURATION
6200 22:20:07.085225 ===================================
6201 22:20:07.088131 EX_ROW_EN[0] = 0x10
6202 22:20:07.091971 EX_ROW_EN[1] = 0x0
6203 22:20:07.092058 LP4Y_EN = 0x0
6204 22:20:07.094979 WORK_FSP = 0x0
6205 22:20:07.095074 WL = 0x2
6206 22:20:07.097930 RL = 0x2
6207 22:20:07.098025 BL = 0x2
6208 22:20:07.101348 RPST = 0x0
6209 22:20:07.101450 RD_PRE = 0x0
6210 22:20:07.104623 WR_PRE = 0x1
6211 22:20:07.104733 WR_PST = 0x0
6212 22:20:07.108207 DBI_WR = 0x0
6213 22:20:07.108317 DBI_RD = 0x0
6214 22:20:07.111373 OTF = 0x1
6215 22:20:07.114793 ===================================
6216 22:20:07.122128 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6217 22:20:07.124738 nWR fixed to 30
6218 22:20:07.124923 [ModeRegInit_LP4] CH0 RK0
6219 22:20:07.127604 [ModeRegInit_LP4] CH0 RK1
6220 22:20:07.130688 [ModeRegInit_LP4] CH1 RK0
6221 22:20:07.134097 [ModeRegInit_LP4] CH1 RK1
6222 22:20:07.134200 match AC timing 19
6223 22:20:07.141090 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6224 22:20:07.144244 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6225 22:20:07.147155 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6226 22:20:07.153770 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6227 22:20:07.157634 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6228 22:20:07.157716 ==
6229 22:20:07.160859 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 22:20:07.163684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 22:20:07.163790 ==
6232 22:20:07.170382 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 22:20:07.176811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 22:20:07.180009 [CA 0] Center 36 (8~64) winsize 57
6235 22:20:07.183583 [CA 1] Center 36 (8~64) winsize 57
6236 22:20:07.187184 [CA 2] Center 36 (8~64) winsize 57
6237 22:20:07.189937 [CA 3] Center 36 (8~64) winsize 57
6238 22:20:07.190017 [CA 4] Center 36 (8~64) winsize 57
6239 22:20:07.193577 [CA 5] Center 36 (8~64) winsize 57
6240 22:20:07.193657
6241 22:20:07.199993 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 22:20:07.200074
6243 22:20:07.203087 [CATrainingPosCal] consider 1 rank data
6244 22:20:07.206382 u2DelayCellTimex100 = 270/100 ps
6245 22:20:07.210035 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 22:20:07.213519 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:20:07.216253 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:20:07.219826 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:20:07.224129 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:20:07.226437 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:20:07.226518
6252 22:20:07.229764 CA PerBit enable=1, Macro0, CA PI delay=36
6253 22:20:07.229844
6254 22:20:07.232929 [CBTSetCACLKResult] CA Dly = 36
6255 22:20:07.236664 CS Dly: 1 (0~32)
6256 22:20:07.236744 ==
6257 22:20:07.239473 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 22:20:07.242639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 22:20:07.242720 ==
6260 22:20:07.249600 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 22:20:07.256414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 22:20:07.259337 [CA 0] Center 36 (8~64) winsize 57
6263 22:20:07.262766 [CA 1] Center 36 (8~64) winsize 57
6264 22:20:07.262846 [CA 2] Center 36 (8~64) winsize 57
6265 22:20:07.265946 [CA 3] Center 36 (8~64) winsize 57
6266 22:20:07.269081 [CA 4] Center 36 (8~64) winsize 57
6267 22:20:07.272657 [CA 5] Center 36 (8~64) winsize 57
6268 22:20:07.272738
6269 22:20:07.276267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 22:20:07.279370
6271 22:20:07.282289 [CATrainingPosCal] consider 2 rank data
6272 22:20:07.285357 u2DelayCellTimex100 = 270/100 ps
6273 22:20:07.289085 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 22:20:07.292117 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:20:07.295352 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:20:07.298694 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 22:20:07.302075 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 22:20:07.305531 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 22:20:07.305611
6280 22:20:07.308912 CA PerBit enable=1, Macro0, CA PI delay=36
6281 22:20:07.308992
6282 22:20:07.311806 [CBTSetCACLKResult] CA Dly = 36
6283 22:20:07.315646 CS Dly: 1 (0~32)
6284 22:20:07.315727
6285 22:20:07.318697 ----->DramcWriteLeveling(PI) begin...
6286 22:20:07.318780 ==
6287 22:20:07.322115 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 22:20:07.325302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 22:20:07.325384 ==
6290 22:20:07.329249 Write leveling (Byte 0): 40 => 8
6291 22:20:07.332027 Write leveling (Byte 1): 32 => 0
6292 22:20:07.335397 DramcWriteLeveling(PI) end<-----
6293 22:20:07.335477
6294 22:20:07.335539 ==
6295 22:20:07.338782 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 22:20:07.341872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 22:20:07.341951 ==
6298 22:20:07.345089 [Gating] SW mode calibration
6299 22:20:07.351754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6300 22:20:07.358050 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6301 22:20:07.361536 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 22:20:07.367858 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 22:20:07.371085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 22:20:07.374579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 22:20:07.381566 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 22:20:07.384314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 22:20:07.388186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 22:20:07.394235 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 22:20:07.397774 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 22:20:07.400889 Total UI for P1: 0, mck2ui 16
6311 22:20:07.404465 best dqsien dly found for B0: ( 0, 14, 24)
6312 22:20:07.407872 Total UI for P1: 0, mck2ui 16
6313 22:20:07.410933 best dqsien dly found for B1: ( 0, 14, 24)
6314 22:20:07.414832 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6315 22:20:07.417836 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6316 22:20:07.417914
6317 22:20:07.421238 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 22:20:07.424344 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 22:20:07.427223 [Gating] SW calibration Done
6320 22:20:07.427293 ==
6321 22:20:07.430574 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 22:20:07.434000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 22:20:07.437783 ==
6324 22:20:07.437853 RX Vref Scan: 0
6325 22:20:07.437915
6326 22:20:07.441056 RX Vref 0 -> 0, step: 1
6327 22:20:07.441122
6328 22:20:07.444282 RX Delay -410 -> 252, step: 16
6329 22:20:07.447120 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6330 22:20:07.450199 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6331 22:20:07.453872 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6332 22:20:07.460297 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6333 22:20:07.463844 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6334 22:20:07.466848 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6335 22:20:07.470002 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6336 22:20:07.476921 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6337 22:20:07.479919 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6338 22:20:07.483797 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6339 22:20:07.486710 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6340 22:20:07.493264 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6341 22:20:07.496650 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6342 22:20:07.499848 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6343 22:20:07.506487 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6344 22:20:07.510217 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6345 22:20:07.510292 ==
6346 22:20:07.513187 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:20:07.516393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:20:07.516476 ==
6349 22:20:07.519788 DQS Delay:
6350 22:20:07.519869 DQS0 = 43, DQS1 = 59
6351 22:20:07.519933 DQM Delay:
6352 22:20:07.523575 DQM0 = 9, DQM1 = 11
6353 22:20:07.523655 DQ Delay:
6354 22:20:07.526148 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6355 22:20:07.529698 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =16
6356 22:20:07.533303 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6357 22:20:07.536088 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6358 22:20:07.536168
6359 22:20:07.536231
6360 22:20:07.536290 ==
6361 22:20:07.539865 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 22:20:07.542941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 22:20:07.546369 ==
6364 22:20:07.546451
6365 22:20:07.546515
6366 22:20:07.546573 TX Vref Scan disable
6367 22:20:07.549468 == TX Byte 0 ==
6368 22:20:07.552713 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 22:20:07.555940 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 22:20:07.559291 == TX Byte 1 ==
6371 22:20:07.562626 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6372 22:20:07.565751 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6373 22:20:07.565856 ==
6374 22:20:07.568937 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 22:20:07.575841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 22:20:07.575915 ==
6377 22:20:07.575994
6378 22:20:07.576081
6379 22:20:07.578842 TX Vref Scan disable
6380 22:20:07.578937 == TX Byte 0 ==
6381 22:20:07.582194 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 22:20:07.585995 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 22:20:07.589253 == TX Byte 1 ==
6384 22:20:07.592641 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6385 22:20:07.598893 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6386 22:20:07.598967
6387 22:20:07.599029 [DATLAT]
6388 22:20:07.599111 Freq=400, CH0 RK0
6389 22:20:07.599186
6390 22:20:07.602118 DATLAT Default: 0xf
6391 22:20:07.602187 0, 0xFFFF, sum = 0
6392 22:20:07.605318 1, 0xFFFF, sum = 0
6393 22:20:07.605387 2, 0xFFFF, sum = 0
6394 22:20:07.608992 3, 0xFFFF, sum = 0
6395 22:20:07.612248 4, 0xFFFF, sum = 0
6396 22:20:07.612349 5, 0xFFFF, sum = 0
6397 22:20:07.615305 6, 0xFFFF, sum = 0
6398 22:20:07.615405 7, 0xFFFF, sum = 0
6399 22:20:07.618444 8, 0xFFFF, sum = 0
6400 22:20:07.618540 9, 0xFFFF, sum = 0
6401 22:20:07.622204 10, 0xFFFF, sum = 0
6402 22:20:07.622303 11, 0xFFFF, sum = 0
6403 22:20:07.625385 12, 0xFFFF, sum = 0
6404 22:20:07.625483 13, 0x0, sum = 1
6405 22:20:07.628322 14, 0x0, sum = 2
6406 22:20:07.628434 15, 0x0, sum = 3
6407 22:20:07.631816 16, 0x0, sum = 4
6408 22:20:07.631899 best_step = 14
6409 22:20:07.631962
6410 22:20:07.632020 ==
6411 22:20:07.635172 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 22:20:07.638363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 22:20:07.641851 ==
6414 22:20:07.641932 RX Vref Scan: 1
6415 22:20:07.641996
6416 22:20:07.645051 RX Vref 0 -> 0, step: 1
6417 22:20:07.645130
6418 22:20:07.648290 RX Delay -359 -> 252, step: 8
6419 22:20:07.648371
6420 22:20:07.651523 Set Vref, RX VrefLevel [Byte0]: 61
6421 22:20:07.654862 [Byte1]: 57
6422 22:20:07.654941
6423 22:20:07.658283 Final RX Vref Byte 0 = 61 to rank0
6424 22:20:07.661269 Final RX Vref Byte 1 = 57 to rank0
6425 22:20:07.665175 Final RX Vref Byte 0 = 61 to rank1
6426 22:20:07.667997 Final RX Vref Byte 1 = 57 to rank1==
6427 22:20:07.671919 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 22:20:07.674818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 22:20:07.678151 ==
6430 22:20:07.678234 DQS Delay:
6431 22:20:07.678298 DQS0 = 48, DQS1 = 60
6432 22:20:07.681780 DQM Delay:
6433 22:20:07.681862 DQM0 = 11, DQM1 = 11
6434 22:20:07.684500 DQ Delay:
6435 22:20:07.684608 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6436 22:20:07.688161 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6437 22:20:07.691516 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6438 22:20:07.694815 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6439 22:20:07.694897
6440 22:20:07.694963
6441 22:20:07.704924 [DQSOSCAuto] RK0, (LSB)MR18= 0xb77a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6442 22:20:07.707545 CH0 RK0: MR19=C0C, MR18=B77A
6443 22:20:07.714081 CH0_RK0: MR19=0xC0C, MR18=0xB77A, DQSOSC=387, MR23=63, INC=394, DEC=262
6444 22:20:07.714164 ==
6445 22:20:07.717426 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 22:20:07.721017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 22:20:07.721100 ==
6448 22:20:07.724631 [Gating] SW mode calibration
6449 22:20:07.730615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6450 22:20:07.737422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6451 22:20:07.740796 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 22:20:07.743903 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 22:20:07.750841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 22:20:07.753829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 22:20:07.757609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 22:20:07.764013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 22:20:07.767017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 22:20:07.770434 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 22:20:07.776924 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 22:20:07.777009 Total UI for P1: 0, mck2ui 16
6461 22:20:07.780199 best dqsien dly found for B0: ( 0, 14, 24)
6462 22:20:07.783435 Total UI for P1: 0, mck2ui 16
6463 22:20:07.787231 best dqsien dly found for B1: ( 0, 14, 24)
6464 22:20:07.793276 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6465 22:20:07.797231 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6466 22:20:07.797312
6467 22:20:07.800172 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 22:20:07.803557 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 22:20:07.806832 [Gating] SW calibration Done
6470 22:20:07.806908 ==
6471 22:20:07.810253 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 22:20:07.813259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 22:20:07.813338 ==
6474 22:20:07.816795 RX Vref Scan: 0
6475 22:20:07.816872
6476 22:20:07.816952 RX Vref 0 -> 0, step: 1
6477 22:20:07.817029
6478 22:20:07.819668 RX Delay -410 -> 252, step: 16
6479 22:20:07.826245 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6480 22:20:07.830232 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6481 22:20:07.833807 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6482 22:20:07.836318 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6483 22:20:07.842936 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6484 22:20:07.846346 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6485 22:20:07.849516 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6486 22:20:07.853380 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6487 22:20:07.859332 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6488 22:20:07.863019 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6489 22:20:07.866319 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6490 22:20:07.869427 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6491 22:20:07.875928 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6492 22:20:07.879421 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6493 22:20:07.883088 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6494 22:20:07.889251 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6495 22:20:07.889326 ==
6496 22:20:07.892486 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:20:07.895932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:20:07.896008 ==
6499 22:20:07.896088 DQS Delay:
6500 22:20:07.899281 DQS0 = 43, DQS1 = 59
6501 22:20:07.899355 DQM Delay:
6502 22:20:07.902375 DQM0 = 10, DQM1 = 15
6503 22:20:07.902451 DQ Delay:
6504 22:20:07.905750 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6505 22:20:07.909325 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6506 22:20:07.912420 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6507 22:20:07.915665 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6508 22:20:07.915743
6509 22:20:07.915829
6510 22:20:07.915910 ==
6511 22:20:07.919100 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 22:20:07.922051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 22:20:07.922124 ==
6514 22:20:07.922205
6515 22:20:07.922280
6516 22:20:07.925478 TX Vref Scan disable
6517 22:20:07.925551 == TX Byte 0 ==
6518 22:20:07.932492 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6519 22:20:07.935490 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6520 22:20:07.935564 == TX Byte 1 ==
6521 22:20:07.941853 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6522 22:20:07.945415 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6523 22:20:07.945493 ==
6524 22:20:07.948330 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 22:20:07.951934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 22:20:07.952008 ==
6527 22:20:07.952088
6528 22:20:07.952165
6529 22:20:07.955122 TX Vref Scan disable
6530 22:20:07.958353 == TX Byte 0 ==
6531 22:20:07.961975 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6532 22:20:07.965339 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6533 22:20:07.968455 == TX Byte 1 ==
6534 22:20:07.971602 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6535 22:20:07.974850 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6536 22:20:07.974930
6537 22:20:07.974994 [DATLAT]
6538 22:20:07.978315 Freq=400, CH0 RK1
6539 22:20:07.978397
6540 22:20:07.978461 DATLAT Default: 0xe
6541 22:20:07.981708 0, 0xFFFF, sum = 0
6542 22:20:07.981790 1, 0xFFFF, sum = 0
6543 22:20:07.984786 2, 0xFFFF, sum = 0
6544 22:20:07.988364 3, 0xFFFF, sum = 0
6545 22:20:07.988446 4, 0xFFFF, sum = 0
6546 22:20:07.991300 5, 0xFFFF, sum = 0
6547 22:20:07.991382 6, 0xFFFF, sum = 0
6548 22:20:07.994729 7, 0xFFFF, sum = 0
6549 22:20:07.994812 8, 0xFFFF, sum = 0
6550 22:20:07.998394 9, 0xFFFF, sum = 0
6551 22:20:07.998480 10, 0xFFFF, sum = 0
6552 22:20:08.001682 11, 0xFFFF, sum = 0
6553 22:20:08.001764 12, 0xFFFF, sum = 0
6554 22:20:08.004889 13, 0x0, sum = 1
6555 22:20:08.004971 14, 0x0, sum = 2
6556 22:20:08.008103 15, 0x0, sum = 3
6557 22:20:08.008185 16, 0x0, sum = 4
6558 22:20:08.011353 best_step = 14
6559 22:20:08.011435
6560 22:20:08.011499 ==
6561 22:20:08.014337 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 22:20:08.017833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 22:20:08.017916 ==
6564 22:20:08.021327 RX Vref Scan: 0
6565 22:20:08.021408
6566 22:20:08.021472 RX Vref 0 -> 0, step: 1
6567 22:20:08.021531
6568 22:20:08.024444 RX Delay -359 -> 252, step: 8
6569 22:20:08.032607 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6570 22:20:08.035415 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6571 22:20:08.038474 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6572 22:20:08.045715 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6573 22:20:08.048968 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6574 22:20:08.051867 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6575 22:20:08.055387 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6576 22:20:08.062155 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6577 22:20:08.065482 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6578 22:20:08.068553 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6579 22:20:08.071782 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
6580 22:20:08.078686 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6581 22:20:08.081931 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6582 22:20:08.085120 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6583 22:20:08.087835 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6584 22:20:08.094788 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6585 22:20:08.094870 ==
6586 22:20:08.097882 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 22:20:08.101633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 22:20:08.101729 ==
6589 22:20:08.101794 DQS Delay:
6590 22:20:08.104445 DQS0 = 44, DQS1 = 56
6591 22:20:08.104549 DQM Delay:
6592 22:20:08.107652 DQM0 = 7, DQM1 = 10
6593 22:20:08.107732 DQ Delay:
6594 22:20:08.111224 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6595 22:20:08.114411 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6596 22:20:08.117740 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6597 22:20:08.120676 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6598 22:20:08.120759
6599 22:20:08.120823
6600 22:20:08.127669 [DQSOSCAuto] RK1, (LSB)MR18= 0xb440, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6601 22:20:08.130733 CH0 RK1: MR19=C0C, MR18=B440
6602 22:20:08.137285 CH0_RK1: MR19=0xC0C, MR18=0xB440, DQSOSC=387, MR23=63, INC=394, DEC=262
6603 22:20:08.140880 [RxdqsGatingPostProcess] freq 400
6604 22:20:08.146984 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6605 22:20:08.150491 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 22:20:08.154090 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 22:20:08.156912 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 22:20:08.160442 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 22:20:08.163854 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 22:20:08.167184 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 22:20:08.167265 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 22:20:08.170108 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 22:20:08.173389 Pre-setting of DQS Precalculation
6614 22:20:08.180342 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6615 22:20:08.180424 ==
6616 22:20:08.183264 Dram Type= 6, Freq= 0, CH_1, rank 0
6617 22:20:08.186469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 22:20:08.186552 ==
6619 22:20:08.193437 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 22:20:08.199836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6621 22:20:08.202867 [CA 0] Center 36 (8~64) winsize 57
6622 22:20:08.206167 [CA 1] Center 36 (8~64) winsize 57
6623 22:20:08.209616 [CA 2] Center 36 (8~64) winsize 57
6624 22:20:08.213077 [CA 3] Center 36 (8~64) winsize 57
6625 22:20:08.216159 [CA 4] Center 36 (8~64) winsize 57
6626 22:20:08.216284 [CA 5] Center 36 (8~64) winsize 57
6627 22:20:08.219491
6628 22:20:08.222821 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6629 22:20:08.222948
6630 22:20:08.226052 [CATrainingPosCal] consider 1 rank data
6631 22:20:08.229093 u2DelayCellTimex100 = 270/100 ps
6632 22:20:08.232827 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 22:20:08.235854 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:20:08.239294 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:20:08.242657 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:20:08.245656 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:20:08.249059 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:20:08.249160
6639 22:20:08.252276 CA PerBit enable=1, Macro0, CA PI delay=36
6640 22:20:08.252381
6641 22:20:08.255494 [CBTSetCACLKResult] CA Dly = 36
6642 22:20:08.259243 CS Dly: 1 (0~32)
6643 22:20:08.259362 ==
6644 22:20:08.262765 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 22:20:08.265581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 22:20:08.265688 ==
6647 22:20:08.272157 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 22:20:08.278849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6649 22:20:08.281924 [CA 0] Center 36 (8~64) winsize 57
6650 22:20:08.285592 [CA 1] Center 36 (8~64) winsize 57
6651 22:20:08.288635 [CA 2] Center 36 (8~64) winsize 57
6652 22:20:08.288706 [CA 3] Center 36 (8~64) winsize 57
6653 22:20:08.291874 [CA 4] Center 36 (8~64) winsize 57
6654 22:20:08.295292 [CA 5] Center 36 (8~64) winsize 57
6655 22:20:08.295385
6656 22:20:08.301849 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6657 22:20:08.301946
6658 22:20:08.305072 [CATrainingPosCal] consider 2 rank data
6659 22:20:08.308154 u2DelayCellTimex100 = 270/100 ps
6660 22:20:08.311777 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 22:20:08.314931 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:20:08.318372 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:20:08.321307 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 22:20:08.324656 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 22:20:08.328277 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 22:20:08.328376
6667 22:20:08.331992 CA PerBit enable=1, Macro0, CA PI delay=36
6668 22:20:08.332093
6669 22:20:08.334843 [CBTSetCACLKResult] CA Dly = 36
6670 22:20:08.338109 CS Dly: 1 (0~32)
6671 22:20:08.338206
6672 22:20:08.341133 ----->DramcWriteLeveling(PI) begin...
6673 22:20:08.341231 ==
6674 22:20:08.344505 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 22:20:08.348380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 22:20:08.348477 ==
6677 22:20:08.351241 Write leveling (Byte 0): 40 => 8
6678 22:20:08.354677 Write leveling (Byte 1): 32 => 0
6679 22:20:08.357641 DramcWriteLeveling(PI) end<-----
6680 22:20:08.357710
6681 22:20:08.357769 ==
6682 22:20:08.361555 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 22:20:08.364382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 22:20:08.364477 ==
6685 22:20:08.367948 [Gating] SW mode calibration
6686 22:20:08.374554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6687 22:20:08.380792 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6688 22:20:08.383989 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 22:20:08.390703 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 22:20:08.394101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 22:20:08.397429 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 22:20:08.404358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 22:20:08.407141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 22:20:08.410280 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 22:20:08.416871 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 22:20:08.420139 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 22:20:08.423745 Total UI for P1: 0, mck2ui 16
6698 22:20:08.426994 best dqsien dly found for B0: ( 0, 14, 24)
6699 22:20:08.430701 Total UI for P1: 0, mck2ui 16
6700 22:20:08.433989 best dqsien dly found for B1: ( 0, 14, 24)
6701 22:20:08.436832 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6702 22:20:08.440342 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6703 22:20:08.440423
6704 22:20:08.443352 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 22:20:08.446869 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 22:20:08.450274 [Gating] SW calibration Done
6707 22:20:08.450355 ==
6708 22:20:08.453741 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 22:20:08.456722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 22:20:08.460055 ==
6711 22:20:08.460136 RX Vref Scan: 0
6712 22:20:08.460199
6713 22:20:08.463570 RX Vref 0 -> 0, step: 1
6714 22:20:08.463651
6715 22:20:08.467062 RX Delay -410 -> 252, step: 16
6716 22:20:08.470369 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6717 22:20:08.473523 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6718 22:20:08.476493 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6719 22:20:08.483369 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6720 22:20:08.486773 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6721 22:20:08.490138 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6722 22:20:08.493115 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6723 22:20:08.500458 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6724 22:20:08.502935 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6725 22:20:08.506238 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6726 22:20:08.512711 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6727 22:20:08.516182 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6728 22:20:08.519185 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6729 22:20:08.522345 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6730 22:20:08.529227 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6731 22:20:08.532794 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6732 22:20:08.532868 ==
6733 22:20:08.536288 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:20:08.539069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:20:08.539187 ==
6736 22:20:08.542312 DQS Delay:
6737 22:20:08.542435 DQS0 = 43, DQS1 = 51
6738 22:20:08.545864 DQM Delay:
6739 22:20:08.545966 DQM0 = 12, DQM1 = 14
6740 22:20:08.546082 DQ Delay:
6741 22:20:08.548988 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6742 22:20:08.551886 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6743 22:20:08.555456 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6744 22:20:08.559216 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6745 22:20:08.559299
6746 22:20:08.559364
6747 22:20:08.559423 ==
6748 22:20:08.562148 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 22:20:08.568611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 22:20:08.568694 ==
6751 22:20:08.568759
6752 22:20:08.568820
6753 22:20:08.568878 TX Vref Scan disable
6754 22:20:08.571611 == TX Byte 0 ==
6755 22:20:08.575244 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 22:20:08.578366 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 22:20:08.581487 == TX Byte 1 ==
6758 22:20:08.584992 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6759 22:20:08.588301 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6760 22:20:08.591553 ==
6761 22:20:08.595088 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 22:20:08.598017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 22:20:08.598093 ==
6764 22:20:08.598173
6765 22:20:08.598251
6766 22:20:08.601581 TX Vref Scan disable
6767 22:20:08.601656 == TX Byte 0 ==
6768 22:20:08.604590 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 22:20:08.611256 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 22:20:08.611335 == TX Byte 1 ==
6771 22:20:08.614530 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6772 22:20:08.621332 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6773 22:20:08.621414
6774 22:20:08.621479 [DATLAT]
6775 22:20:08.621537 Freq=400, CH1 RK0
6776 22:20:08.624675
6777 22:20:08.624755 DATLAT Default: 0xf
6778 22:20:08.627971 0, 0xFFFF, sum = 0
6779 22:20:08.628054 1, 0xFFFF, sum = 0
6780 22:20:08.631585 2, 0xFFFF, sum = 0
6781 22:20:08.631666 3, 0xFFFF, sum = 0
6782 22:20:08.634880 4, 0xFFFF, sum = 0
6783 22:20:08.634961 5, 0xFFFF, sum = 0
6784 22:20:08.637742 6, 0xFFFF, sum = 0
6785 22:20:08.637825 7, 0xFFFF, sum = 0
6786 22:20:08.641001 8, 0xFFFF, sum = 0
6787 22:20:08.641083 9, 0xFFFF, sum = 0
6788 22:20:08.644333 10, 0xFFFF, sum = 0
6789 22:20:08.644415 11, 0xFFFF, sum = 0
6790 22:20:08.648057 12, 0xFFFF, sum = 0
6791 22:20:08.648139 13, 0x0, sum = 1
6792 22:20:08.651144 14, 0x0, sum = 2
6793 22:20:08.651226 15, 0x0, sum = 3
6794 22:20:08.654258 16, 0x0, sum = 4
6795 22:20:08.654341 best_step = 14
6796 22:20:08.654443
6797 22:20:08.654503 ==
6798 22:20:08.657693 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 22:20:08.664618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 22:20:08.664701 ==
6801 22:20:08.664765 RX Vref Scan: 1
6802 22:20:08.664826
6803 22:20:08.667794 RX Vref 0 -> 0, step: 1
6804 22:20:08.667875
6805 22:20:08.670888 RX Delay -343 -> 252, step: 8
6806 22:20:08.670969
6807 22:20:08.673974 Set Vref, RX VrefLevel [Byte0]: 50
6808 22:20:08.677482 [Byte1]: 53
6809 22:20:08.677564
6810 22:20:08.680632 Final RX Vref Byte 0 = 50 to rank0
6811 22:20:08.684277 Final RX Vref Byte 1 = 53 to rank0
6812 22:20:08.687698 Final RX Vref Byte 0 = 50 to rank1
6813 22:20:08.690822 Final RX Vref Byte 1 = 53 to rank1==
6814 22:20:08.693773 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 22:20:08.700422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 22:20:08.700535 ==
6817 22:20:08.700603 DQS Delay:
6818 22:20:08.703697 DQS0 = 44, DQS1 = 52
6819 22:20:08.703778 DQM Delay:
6820 22:20:08.703843 DQM0 = 9, DQM1 = 9
6821 22:20:08.707147 DQ Delay:
6822 22:20:08.707228 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6823 22:20:08.710607 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6824 22:20:08.713418 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6825 22:20:08.717310 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =16
6826 22:20:08.717423
6827 22:20:08.717523
6828 22:20:08.726887 [DQSOSCAuto] RK0, (LSB)MR18= 0x9d73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6829 22:20:08.729990 CH1 RK0: MR19=C0C, MR18=9D73
6830 22:20:08.736896 CH1_RK0: MR19=0xC0C, MR18=0x9D73, DQSOSC=390, MR23=63, INC=388, DEC=258
6831 22:20:08.736979 ==
6832 22:20:08.739799 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 22:20:08.743711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 22:20:08.743785 ==
6835 22:20:08.746657 [Gating] SW mode calibration
6836 22:20:08.753050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6837 22:20:08.759920 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6838 22:20:08.763030 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 22:20:08.766787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 22:20:08.772942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 22:20:08.776166 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 22:20:08.779674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 22:20:08.786998 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 22:20:08.790020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 22:20:08.792756 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 22:20:08.799679 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 22:20:08.799762 Total UI for P1: 0, mck2ui 16
6848 22:20:08.803126 best dqsien dly found for B0: ( 0, 14, 24)
6849 22:20:08.806330 Total UI for P1: 0, mck2ui 16
6850 22:20:08.809425 best dqsien dly found for B1: ( 0, 14, 24)
6851 22:20:08.816118 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6852 22:20:08.819590 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6853 22:20:08.819673
6854 22:20:08.822713 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 22:20:08.826214 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 22:20:08.829417 [Gating] SW calibration Done
6857 22:20:08.829499 ==
6858 22:20:08.832801 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 22:20:08.836250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 22:20:08.836332 ==
6861 22:20:08.839249 RX Vref Scan: 0
6862 22:20:08.839330
6863 22:20:08.839395 RX Vref 0 -> 0, step: 1
6864 22:20:08.839456
6865 22:20:08.842525 RX Delay -410 -> 252, step: 16
6866 22:20:08.846272 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6867 22:20:08.852431 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6868 22:20:08.855956 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6869 22:20:08.858966 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6870 22:20:08.865686 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6871 22:20:08.868936 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6872 22:20:08.872108 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6873 22:20:08.876197 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6874 22:20:08.882319 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6875 22:20:08.885419 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6876 22:20:08.889035 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6877 22:20:08.892953 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6878 22:20:08.899086 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6879 22:20:08.902595 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6880 22:20:08.905684 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6881 22:20:08.908772 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6882 22:20:08.912350 ==
6883 22:20:08.912432 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:20:08.918721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:20:08.918820 ==
6886 22:20:08.918886 DQS Delay:
6887 22:20:08.921966 DQS0 = 51, DQS1 = 51
6888 22:20:08.922048 DQM Delay:
6889 22:20:08.925416 DQM0 = 20, DQM1 = 14
6890 22:20:08.925504 DQ Delay:
6891 22:20:08.928606 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6892 22:20:08.931823 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6893 22:20:08.935469 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6894 22:20:08.938776 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6895 22:20:08.938954
6896 22:20:08.939054
6897 22:20:08.939144 ==
6898 22:20:08.941906 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 22:20:08.945112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 22:20:08.945236 ==
6901 22:20:08.945333
6902 22:20:08.945424
6903 22:20:08.948253 TX Vref Scan disable
6904 22:20:08.948368 == TX Byte 0 ==
6905 22:20:08.955270 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6906 22:20:08.958503 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6907 22:20:08.958574 == TX Byte 1 ==
6908 22:20:08.965068 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6909 22:20:08.968141 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6910 22:20:08.968217 ==
6911 22:20:08.971489 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 22:20:08.974988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 22:20:08.975062 ==
6914 22:20:08.975124
6915 22:20:08.975180
6916 22:20:08.978399 TX Vref Scan disable
6917 22:20:08.978512 == TX Byte 0 ==
6918 22:20:08.984625 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6919 22:20:08.987850 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6920 22:20:08.987957 == TX Byte 1 ==
6921 22:20:08.994931 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6922 22:20:08.997984 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6923 22:20:08.998090
6924 22:20:08.998182 [DATLAT]
6925 22:20:09.001411 Freq=400, CH1 RK1
6926 22:20:09.001510
6927 22:20:09.001599 DATLAT Default: 0xe
6928 22:20:09.004508 0, 0xFFFF, sum = 0
6929 22:20:09.004587 1, 0xFFFF, sum = 0
6930 22:20:09.008030 2, 0xFFFF, sum = 0
6931 22:20:09.008127 3, 0xFFFF, sum = 0
6932 22:20:09.011008 4, 0xFFFF, sum = 0
6933 22:20:09.011103 5, 0xFFFF, sum = 0
6934 22:20:09.014867 6, 0xFFFF, sum = 0
6935 22:20:09.018016 7, 0xFFFF, sum = 0
6936 22:20:09.018115 8, 0xFFFF, sum = 0
6937 22:20:09.020906 9, 0xFFFF, sum = 0
6938 22:20:09.020976 10, 0xFFFF, sum = 0
6939 22:20:09.024022 11, 0xFFFF, sum = 0
6940 22:20:09.024117 12, 0xFFFF, sum = 0
6941 22:20:09.027376 13, 0x0, sum = 1
6942 22:20:09.027472 14, 0x0, sum = 2
6943 22:20:09.031274 15, 0x0, sum = 3
6944 22:20:09.031370 16, 0x0, sum = 4
6945 22:20:09.034327 best_step = 14
6946 22:20:09.034420
6947 22:20:09.034507 ==
6948 22:20:09.037867 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 22:20:09.040987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 22:20:09.041058 ==
6951 22:20:09.041117 RX Vref Scan: 0
6952 22:20:09.041173
6953 22:20:09.044126 RX Vref 0 -> 0, step: 1
6954 22:20:09.044217
6955 22:20:09.047526 RX Delay -343 -> 252, step: 8
6956 22:20:09.054699 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6957 22:20:09.058118 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6958 22:20:09.061060 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6959 22:20:09.067875 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
6960 22:20:09.071198 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6961 22:20:09.074384 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6962 22:20:09.077762 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6963 22:20:09.084721 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6964 22:20:09.087377 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6965 22:20:09.091162 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6966 22:20:09.093738 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6967 22:20:09.100227 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6968 22:20:09.103578 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6969 22:20:09.106819 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6970 22:20:09.113538 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6971 22:20:09.117179 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
6972 22:20:09.117257 ==
6973 22:20:09.120230 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 22:20:09.123423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 22:20:09.123519 ==
6976 22:20:09.126635 DQS Delay:
6977 22:20:09.126731 DQS0 = 44, DQS1 = 56
6978 22:20:09.126819 DQM Delay:
6979 22:20:09.130562 DQM0 = 10, DQM1 = 11
6980 22:20:09.130655 DQ Delay:
6981 22:20:09.133403 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6982 22:20:09.136767 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6983 22:20:09.139982 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6984 22:20:09.143258 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6985 22:20:09.143354
6986 22:20:09.143443
6987 22:20:09.153207 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
6988 22:20:09.153312 CH1 RK1: MR19=C0C, MR18=6B59
6989 22:20:09.159567 CH1_RK1: MR19=0xC0C, MR18=0x6B59, DQSOSC=396, MR23=63, INC=376, DEC=251
6990 22:20:09.162799 [RxdqsGatingPostProcess] freq 400
6991 22:20:09.169726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6992 22:20:09.172807 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 22:20:09.176299 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 22:20:09.179627 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 22:20:09.182753 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 22:20:09.186406 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 22:20:09.189686 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 22:20:09.192466 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 22:20:09.196198 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 22:20:09.199563 Pre-setting of DQS Precalculation
7001 22:20:09.203017 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7002 22:20:09.209048 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7003 22:20:09.216143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7004 22:20:09.216248
7005 22:20:09.216340
7006 22:20:09.218934 [Calibration Summary] 800 Mbps
7007 22:20:09.222336 CH 0, Rank 0
7008 22:20:09.222433 SW Impedance : PASS
7009 22:20:09.225690 DUTY Scan : NO K
7010 22:20:09.228998 ZQ Calibration : PASS
7011 22:20:09.229066 Jitter Meter : NO K
7012 22:20:09.232282 CBT Training : PASS
7013 22:20:09.235463 Write leveling : PASS
7014 22:20:09.235558 RX DQS gating : PASS
7015 22:20:09.238657 RX DQ/DQS(RDDQC) : PASS
7016 22:20:09.242674 TX DQ/DQS : PASS
7017 22:20:09.242771 RX DATLAT : PASS
7018 22:20:09.245317 RX DQ/DQS(Engine): PASS
7019 22:20:09.248671 TX OE : NO K
7020 22:20:09.248766 All Pass.
7021 22:20:09.248853
7022 22:20:09.248949 CH 0, Rank 1
7023 22:20:09.252133 SW Impedance : PASS
7024 22:20:09.255307 DUTY Scan : NO K
7025 22:20:09.255408 ZQ Calibration : PASS
7026 22:20:09.258574 Jitter Meter : NO K
7027 22:20:09.258669 CBT Training : PASS
7028 22:20:09.261830 Write leveling : NO K
7029 22:20:09.265325 RX DQS gating : PASS
7030 22:20:09.265394 RX DQ/DQS(RDDQC) : PASS
7031 22:20:09.269184 TX DQ/DQS : PASS
7032 22:20:09.271926 RX DATLAT : PASS
7033 22:20:09.271996 RX DQ/DQS(Engine): PASS
7034 22:20:09.275468 TX OE : NO K
7035 22:20:09.275564 All Pass.
7036 22:20:09.275651
7037 22:20:09.278666 CH 1, Rank 0
7038 22:20:09.278733 SW Impedance : PASS
7039 22:20:09.281920 DUTY Scan : NO K
7040 22:20:09.285252 ZQ Calibration : PASS
7041 22:20:09.285348 Jitter Meter : NO K
7042 22:20:09.289029 CBT Training : PASS
7043 22:20:09.291730 Write leveling : PASS
7044 22:20:09.291824 RX DQS gating : PASS
7045 22:20:09.295520 RX DQ/DQS(RDDQC) : PASS
7046 22:20:09.298156 TX DQ/DQS : PASS
7047 22:20:09.298253 RX DATLAT : PASS
7048 22:20:09.301410 RX DQ/DQS(Engine): PASS
7049 22:20:09.304667 TX OE : NO K
7050 22:20:09.304748 All Pass.
7051 22:20:09.304811
7052 22:20:09.304869 CH 1, Rank 1
7053 22:20:09.308407 SW Impedance : PASS
7054 22:20:09.311846 DUTY Scan : NO K
7055 22:20:09.311927 ZQ Calibration : PASS
7056 22:20:09.314735 Jitter Meter : NO K
7057 22:20:09.318498 CBT Training : PASS
7058 22:20:09.318579 Write leveling : NO K
7059 22:20:09.321604 RX DQS gating : PASS
7060 22:20:09.321685 RX DQ/DQS(RDDQC) : PASS
7061 22:20:09.324806 TX DQ/DQS : PASS
7062 22:20:09.328234 RX DATLAT : PASS
7063 22:20:09.328340 RX DQ/DQS(Engine): PASS
7064 22:20:09.331240 TX OE : NO K
7065 22:20:09.331320 All Pass.
7066 22:20:09.331384
7067 22:20:09.334654 DramC Write-DBI off
7068 22:20:09.338079 PER_BANK_REFRESH: Hybrid Mode
7069 22:20:09.338159 TX_TRACKING: ON
7070 22:20:09.348105 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7071 22:20:09.351272 [FAST_K] Save calibration result to emmc
7072 22:20:09.354541 dramc_set_vcore_voltage set vcore to 725000
7073 22:20:09.357910 Read voltage for 1600, 0
7074 22:20:09.357990 Vio18 = 0
7075 22:20:09.361407 Vcore = 725000
7076 22:20:09.361487 Vdram = 0
7077 22:20:09.361550 Vddq = 0
7078 22:20:09.361608 Vmddr = 0
7079 22:20:09.367689 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7080 22:20:09.374470 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7081 22:20:09.374551 MEM_TYPE=3, freq_sel=13
7082 22:20:09.377838 sv_algorithm_assistance_LP4_3733
7083 22:20:09.381139 ============ PULL DRAM RESETB DOWN ============
7084 22:20:09.387810 ========== PULL DRAM RESETB DOWN end =========
7085 22:20:09.390867 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7086 22:20:09.394288 ===================================
7087 22:20:09.397502 LPDDR4 DRAM CONFIGURATION
7088 22:20:09.400814 ===================================
7089 22:20:09.400895 EX_ROW_EN[0] = 0x0
7090 22:20:09.404048 EX_ROW_EN[1] = 0x0
7091 22:20:09.404128 LP4Y_EN = 0x0
7092 22:20:09.407560 WORK_FSP = 0x1
7093 22:20:09.410459 WL = 0x5
7094 22:20:09.410571 RL = 0x5
7095 22:20:09.413904 BL = 0x2
7096 22:20:09.413985 RPST = 0x0
7097 22:20:09.417507 RD_PRE = 0x0
7098 22:20:09.417588 WR_PRE = 0x1
7099 22:20:09.420913 WR_PST = 0x1
7100 22:20:09.420993 DBI_WR = 0x0
7101 22:20:09.423778 DBI_RD = 0x0
7102 22:20:09.423858 OTF = 0x1
7103 22:20:09.427253 ===================================
7104 22:20:09.430582 ===================================
7105 22:20:09.433712 ANA top config
7106 22:20:09.437017 ===================================
7107 22:20:09.437098 DLL_ASYNC_EN = 0
7108 22:20:09.440296 ALL_SLAVE_EN = 0
7109 22:20:09.443492 NEW_RANK_MODE = 1
7110 22:20:09.447241 DLL_IDLE_MODE = 1
7111 22:20:09.450454 LP45_APHY_COMB_EN = 1
7112 22:20:09.450535 TX_ODT_DIS = 0
7113 22:20:09.453226 NEW_8X_MODE = 1
7114 22:20:09.456895 ===================================
7115 22:20:09.460237 ===================================
7116 22:20:09.463376 data_rate = 3200
7117 22:20:09.466808 CKR = 1
7118 22:20:09.470006 DQ_P2S_RATIO = 8
7119 22:20:09.473710 ===================================
7120 22:20:09.473792 CA_P2S_RATIO = 8
7121 22:20:09.476931 DQ_CA_OPEN = 0
7122 22:20:09.479771 DQ_SEMI_OPEN = 0
7123 22:20:09.483051 CA_SEMI_OPEN = 0
7124 22:20:09.486485 CA_FULL_RATE = 0
7125 22:20:09.490405 DQ_CKDIV4_EN = 0
7126 22:20:09.492940 CA_CKDIV4_EN = 0
7127 22:20:09.493021 CA_PREDIV_EN = 0
7128 22:20:09.496438 PH8_DLY = 12
7129 22:20:09.499623 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7130 22:20:09.503030 DQ_AAMCK_DIV = 4
7131 22:20:09.506327 CA_AAMCK_DIV = 4
7132 22:20:09.510177 CA_ADMCK_DIV = 4
7133 22:20:09.510286 DQ_TRACK_CA_EN = 0
7134 22:20:09.513025 CA_PICK = 1600
7135 22:20:09.516379 CA_MCKIO = 1600
7136 22:20:09.519829 MCKIO_SEMI = 0
7137 22:20:09.522895 PLL_FREQ = 3068
7138 22:20:09.526290 DQ_UI_PI_RATIO = 32
7139 22:20:09.529319 CA_UI_PI_RATIO = 0
7140 22:20:09.532895 ===================================
7141 22:20:09.535955 ===================================
7142 22:20:09.536036 memory_type:LPDDR4
7143 22:20:09.539729 GP_NUM : 10
7144 22:20:09.542699 SRAM_EN : 1
7145 22:20:09.542780 MD32_EN : 0
7146 22:20:09.546191 ===================================
7147 22:20:09.549201 [ANA_INIT] >>>>>>>>>>>>>>
7148 22:20:09.552479 <<<<<< [CONFIGURE PHASE]: ANA_TX
7149 22:20:09.555857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7150 22:20:09.559290 ===================================
7151 22:20:09.562687 data_rate = 3200,PCW = 0X7600
7152 22:20:09.565862 ===================================
7153 22:20:09.568972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7154 22:20:09.573066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 22:20:09.579252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 22:20:09.582558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7157 22:20:09.585701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7158 22:20:09.588866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7159 22:20:09.592406 [ANA_INIT] flow start
7160 22:20:09.595425 [ANA_INIT] PLL >>>>>>>>
7161 22:20:09.595506 [ANA_INIT] PLL <<<<<<<<
7162 22:20:09.598832 [ANA_INIT] MIDPI >>>>>>>>
7163 22:20:09.602113 [ANA_INIT] MIDPI <<<<<<<<
7164 22:20:09.605725 [ANA_INIT] DLL >>>>>>>>
7165 22:20:09.605806 [ANA_INIT] DLL <<<<<<<<
7166 22:20:09.609339 [ANA_INIT] flow end
7167 22:20:09.612243 ============ LP4 DIFF to SE enter ============
7168 22:20:09.615362 ============ LP4 DIFF to SE exit ============
7169 22:20:09.618887 [ANA_INIT] <<<<<<<<<<<<<
7170 22:20:09.622529 [Flow] Enable top DCM control >>>>>
7171 22:20:09.625499 [Flow] Enable top DCM control <<<<<
7172 22:20:09.629151 Enable DLL master slave shuffle
7173 22:20:09.635100 ==============================================================
7174 22:20:09.635213 Gating Mode config
7175 22:20:09.641805 ==============================================================
7176 22:20:09.641898 Config description:
7177 22:20:09.651939 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7178 22:20:09.658273 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7179 22:20:09.665274 SELPH_MODE 0: By rank 1: By Phase
7180 22:20:09.668592 ==============================================================
7181 22:20:09.671991 GAT_TRACK_EN = 1
7182 22:20:09.674904 RX_GATING_MODE = 2
7183 22:20:09.678721 RX_GATING_TRACK_MODE = 2
7184 22:20:09.681749 SELPH_MODE = 1
7185 22:20:09.685238 PICG_EARLY_EN = 1
7186 22:20:09.688420 VALID_LAT_VALUE = 1
7187 22:20:09.695540 ==============================================================
7188 22:20:09.698356 Enter into Gating configuration >>>>
7189 22:20:09.701508 Exit from Gating configuration <<<<
7190 22:20:09.705509 Enter into DVFS_PRE_config >>>>>
7191 22:20:09.715462 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7192 22:20:09.717896 Exit from DVFS_PRE_config <<<<<
7193 22:20:09.721274 Enter into PICG configuration >>>>
7194 22:20:09.725009 Exit from PICG configuration <<<<
7195 22:20:09.727767 [RX_INPUT] configuration >>>>>
7196 22:20:09.727848 [RX_INPUT] configuration <<<<<
7197 22:20:09.734957 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7198 22:20:09.741747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7199 22:20:09.744530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 22:20:09.750920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 22:20:09.757444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 22:20:09.764416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 22:20:09.767419 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7204 22:20:09.770797 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7205 22:20:09.777552 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7206 22:20:09.780799 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7207 22:20:09.783851 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7208 22:20:09.790846 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 22:20:09.794062 ===================================
7210 22:20:09.794206 LPDDR4 DRAM CONFIGURATION
7211 22:20:09.797058 ===================================
7212 22:20:09.800436 EX_ROW_EN[0] = 0x0
7213 22:20:09.803917 EX_ROW_EN[1] = 0x0
7214 22:20:09.803998 LP4Y_EN = 0x0
7215 22:20:09.806830 WORK_FSP = 0x1
7216 22:20:09.806910 WL = 0x5
7217 22:20:09.810264 RL = 0x5
7218 22:20:09.810344 BL = 0x2
7219 22:20:09.814078 RPST = 0x0
7220 22:20:09.814175 RD_PRE = 0x0
7221 22:20:09.816754 WR_PRE = 0x1
7222 22:20:09.816834 WR_PST = 0x1
7223 22:20:09.820027 DBI_WR = 0x0
7224 22:20:09.820112 DBI_RD = 0x0
7225 22:20:09.823607 OTF = 0x1
7226 22:20:09.826646 ===================================
7227 22:20:09.829946 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7228 22:20:09.833625 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7229 22:20:09.840174 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 22:20:09.843297 ===================================
7231 22:20:09.843378 LPDDR4 DRAM CONFIGURATION
7232 22:20:09.846525 ===================================
7233 22:20:09.850407 EX_ROW_EN[0] = 0x10
7234 22:20:09.853234 EX_ROW_EN[1] = 0x0
7235 22:20:09.853314 LP4Y_EN = 0x0
7236 22:20:09.856685 WORK_FSP = 0x1
7237 22:20:09.856765 WL = 0x5
7238 22:20:09.860845 RL = 0x5
7239 22:20:09.860926 BL = 0x2
7240 22:20:09.863140 RPST = 0x0
7241 22:20:09.863219 RD_PRE = 0x0
7242 22:20:09.866955 WR_PRE = 0x1
7243 22:20:09.867035 WR_PST = 0x1
7244 22:20:09.869762 DBI_WR = 0x0
7245 22:20:09.869842 DBI_RD = 0x0
7246 22:20:09.873080 OTF = 0x1
7247 22:20:09.876380 ===================================
7248 22:20:09.882864 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7249 22:20:09.882945 ==
7250 22:20:09.886699 Dram Type= 6, Freq= 0, CH_0, rank 0
7251 22:20:09.889438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7252 22:20:09.889520 ==
7253 22:20:09.893055 [Duty_Offset_Calibration]
7254 22:20:09.893136 B0:1 B1:-1 CA:0
7255 22:20:09.893200
7256 22:20:09.896088 [DutyScan_Calibration_Flow] k_type=0
7257 22:20:09.906822
7258 22:20:09.906905 ==CLK 0==
7259 22:20:09.910332 Final CLK duty delay cell = 0
7260 22:20:09.914180 [0] MAX Duty = 5156%(X100), DQS PI = 22
7261 22:20:09.916780 [0] MIN Duty = 4907%(X100), DQS PI = 6
7262 22:20:09.916893 [0] AVG Duty = 5031%(X100)
7263 22:20:09.920120
7264 22:20:09.923190 CH0 CLK Duty spec in!! Max-Min= 249%
7265 22:20:09.926516 [DutyScan_Calibration_Flow] ====Done====
7266 22:20:09.926620
7267 22:20:09.929845 [DutyScan_Calibration_Flow] k_type=1
7268 22:20:09.945818
7269 22:20:09.945898 ==DQS 0 ==
7270 22:20:09.949352 Final DQS duty delay cell = -4
7271 22:20:09.952400 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7272 22:20:09.955823 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7273 22:20:09.959165 [-4] AVG Duty = 4922%(X100)
7274 22:20:09.959245
7275 22:20:09.959309 ==DQS 1 ==
7276 22:20:09.962727 Final DQS duty delay cell = 0
7277 22:20:09.965714 [0] MAX Duty = 5156%(X100), DQS PI = 0
7278 22:20:09.969458 [0] MIN Duty = 5031%(X100), DQS PI = 18
7279 22:20:09.973182 [0] AVG Duty = 5093%(X100)
7280 22:20:09.973263
7281 22:20:09.975653 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7282 22:20:09.975734
7283 22:20:09.978868 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7284 22:20:09.982439 [DutyScan_Calibration_Flow] ====Done====
7285 22:20:09.982519
7286 22:20:09.985605 [DutyScan_Calibration_Flow] k_type=3
7287 22:20:10.003859
7288 22:20:10.003941 ==DQM 0 ==
7289 22:20:10.006848 Final DQM duty delay cell = 0
7290 22:20:10.010356 [0] MAX Duty = 5124%(X100), DQS PI = 24
7291 22:20:10.013418 [0] MIN Duty = 4907%(X100), DQS PI = 10
7292 22:20:10.017147 [0] AVG Duty = 5015%(X100)
7293 22:20:10.017240
7294 22:20:10.017304 ==DQM 1 ==
7295 22:20:10.020240 Final DQM duty delay cell = 0
7296 22:20:10.023227 [0] MAX Duty = 5000%(X100), DQS PI = 6
7297 22:20:10.026313 [0] MIN Duty = 4782%(X100), DQS PI = 20
7298 22:20:10.029908 [0] AVG Duty = 4891%(X100)
7299 22:20:10.030007
7300 22:20:10.033219 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7301 22:20:10.033299
7302 22:20:10.036830 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7303 22:20:10.039977 [DutyScan_Calibration_Flow] ====Done====
7304 22:20:10.040056
7305 22:20:10.042822 [DutyScan_Calibration_Flow] k_type=2
7306 22:20:10.059708
7307 22:20:10.059786 ==DQ 0 ==
7308 22:20:10.063428 Final DQ duty delay cell = -4
7309 22:20:10.066773 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7310 22:20:10.069686 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7311 22:20:10.072946 [-4] AVG Duty = 4953%(X100)
7312 22:20:10.073025
7313 22:20:10.073087 ==DQ 1 ==
7314 22:20:10.076433 Final DQ duty delay cell = 0
7315 22:20:10.079780 [0] MAX Duty = 5125%(X100), DQS PI = 2
7316 22:20:10.082916 [0] MIN Duty = 5000%(X100), DQS PI = 36
7317 22:20:10.086508 [0] AVG Duty = 5062%(X100)
7318 22:20:10.086587
7319 22:20:10.089632 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7320 22:20:10.089712
7321 22:20:10.092891 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7322 22:20:10.095903 [DutyScan_Calibration_Flow] ====Done====
7323 22:20:10.095981 ==
7324 22:20:10.099234 Dram Type= 6, Freq= 0, CH_1, rank 0
7325 22:20:10.102536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 22:20:10.102616 ==
7327 22:20:10.106153 [Duty_Offset_Calibration]
7328 22:20:10.106233 B0:-1 B1:1 CA:2
7329 22:20:10.106295
7330 22:20:10.109644 [DutyScan_Calibration_Flow] k_type=0
7331 22:20:10.120697
7332 22:20:10.120779 ==CLK 0==
7333 22:20:10.124149 Final CLK duty delay cell = 0
7334 22:20:10.127162 [0] MAX Duty = 5187%(X100), DQS PI = 24
7335 22:20:10.130684 [0] MIN Duty = 4969%(X100), DQS PI = 62
7336 22:20:10.133860 [0] AVG Duty = 5078%(X100)
7337 22:20:10.133939
7338 22:20:10.136995 CH1 CLK Duty spec in!! Max-Min= 218%
7339 22:20:10.140149 [DutyScan_Calibration_Flow] ====Done====
7340 22:20:10.140228
7341 22:20:10.144149 [DutyScan_Calibration_Flow] k_type=1
7342 22:20:10.160304
7343 22:20:10.160383 ==DQS 0 ==
7344 22:20:10.163535 Final DQS duty delay cell = 0
7345 22:20:10.166691 [0] MAX Duty = 5124%(X100), DQS PI = 18
7346 22:20:10.170421 [0] MIN Duty = 4938%(X100), DQS PI = 8
7347 22:20:10.173431 [0] AVG Duty = 5031%(X100)
7348 22:20:10.173510
7349 22:20:10.173573 ==DQS 1 ==
7350 22:20:10.177070 Final DQS duty delay cell = 0
7351 22:20:10.179979 [0] MAX Duty = 5093%(X100), DQS PI = 26
7352 22:20:10.183195 [0] MIN Duty = 4969%(X100), DQS PI = 54
7353 22:20:10.186660 [0] AVG Duty = 5031%(X100)
7354 22:20:10.186739
7355 22:20:10.189984 CH1 DQS 0 Duty spec in!! Max-Min= 186%
7356 22:20:10.190082
7357 22:20:10.193325 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7358 22:20:10.196837 [DutyScan_Calibration_Flow] ====Done====
7359 22:20:10.196921
7360 22:20:10.200037 [DutyScan_Calibration_Flow] k_type=3
7361 22:20:10.216749
7362 22:20:10.216834 ==DQM 0 ==
7363 22:20:10.219846 Final DQM duty delay cell = -4
7364 22:20:10.222787 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7365 22:20:10.226204 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7366 22:20:10.229557 [-4] AVG Duty = 4922%(X100)
7367 22:20:10.229637
7368 22:20:10.229702 ==DQM 1 ==
7369 22:20:10.233141 Final DQM duty delay cell = 0
7370 22:20:10.236005 [0] MAX Duty = 5156%(X100), DQS PI = 2
7371 22:20:10.239627 [0] MIN Duty = 4969%(X100), DQS PI = 34
7372 22:20:10.243200 [0] AVG Duty = 5062%(X100)
7373 22:20:10.243293
7374 22:20:10.246188 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7375 22:20:10.246289
7376 22:20:10.249131 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7377 22:20:10.252338 [DutyScan_Calibration_Flow] ====Done====
7378 22:20:10.252419
7379 22:20:10.255745 [DutyScan_Calibration_Flow] k_type=2
7380 22:20:10.273341
7381 22:20:10.273421 ==DQ 0 ==
7382 22:20:10.276710 Final DQ duty delay cell = 0
7383 22:20:10.280076 [0] MAX Duty = 5187%(X100), DQS PI = 32
7384 22:20:10.283344 [0] MIN Duty = 4906%(X100), DQS PI = 8
7385 22:20:10.283425 [0] AVG Duty = 5046%(X100)
7386 22:20:10.286591
7387 22:20:10.286670 ==DQ 1 ==
7388 22:20:10.289834 Final DQ duty delay cell = 0
7389 22:20:10.293631 [0] MAX Duty = 5156%(X100), DQS PI = 8
7390 22:20:10.296446 [0] MIN Duty = 4969%(X100), DQS PI = 56
7391 22:20:10.296581 [0] AVG Duty = 5062%(X100)
7392 22:20:10.296677
7393 22:20:10.299937 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7394 22:20:10.303220
7395 22:20:10.306836 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7396 22:20:10.309719 [DutyScan_Calibration_Flow] ====Done====
7397 22:20:10.312950 nWR fixed to 30
7398 22:20:10.313032 [ModeRegInit_LP4] CH0 RK0
7399 22:20:10.316631 [ModeRegInit_LP4] CH0 RK1
7400 22:20:10.319565 [ModeRegInit_LP4] CH1 RK0
7401 22:20:10.323501 [ModeRegInit_LP4] CH1 RK1
7402 22:20:10.323582 match AC timing 5
7403 22:20:10.329725 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7404 22:20:10.332863 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7405 22:20:10.336130 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7406 22:20:10.342536 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7407 22:20:10.346080 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7408 22:20:10.346161 [MiockJmeterHQA]
7409 22:20:10.346224
7410 22:20:10.349362 [DramcMiockJmeter] u1RxGatingPI = 0
7411 22:20:10.352807 0 : 4252, 4027
7412 22:20:10.352889 4 : 4363, 4137
7413 22:20:10.355619 8 : 4255, 4029
7414 22:20:10.355700 12 : 4363, 4137
7415 22:20:10.359335 16 : 4252, 4027
7416 22:20:10.359416 20 : 4253, 4027
7417 22:20:10.359480 24 : 4253, 4026
7418 22:20:10.362922 28 : 4255, 4029
7419 22:20:10.363004 32 : 4364, 4137
7420 22:20:10.365983 36 : 4252, 4027
7421 22:20:10.366064 40 : 4252, 4027
7422 22:20:10.369318 44 : 4250, 4026
7423 22:20:10.369399 48 : 4255, 4029
7424 22:20:10.369464 52 : 4249, 4027
7425 22:20:10.372338 56 : 4361, 4138
7426 22:20:10.372419 60 : 4360, 4138
7427 22:20:10.375602 64 : 4250, 4026
7428 22:20:10.375684 68 : 4250, 4027
7429 22:20:10.379051 72 : 4249, 4027
7430 22:20:10.379132 76 : 4250, 4026
7431 22:20:10.382642 80 : 4252, 4029
7432 22:20:10.382740 84 : 4360, 4137
7433 22:20:10.382834 88 : 4250, 4027
7434 22:20:10.385529 92 : 4250, 540
7435 22:20:10.385611 96 : 4361, 0
7436 22:20:10.388603 100 : 4252, 0
7437 22:20:10.388684 104 : 4250, 0
7438 22:20:10.388749 108 : 4250, 0
7439 22:20:10.392057 112 : 4252, 0
7440 22:20:10.392157 116 : 4250, 0
7441 22:20:10.395404 120 : 4252, 0
7442 22:20:10.395485 124 : 4361, 0
7443 22:20:10.395550 128 : 4361, 0
7444 22:20:10.398767 132 : 4363, 0
7445 22:20:10.398848 136 : 4250, 0
7446 22:20:10.402297 140 : 4250, 0
7447 22:20:10.402378 144 : 4250, 0
7448 22:20:10.402443 148 : 4250, 0
7449 22:20:10.405048 152 : 4250, 0
7450 22:20:10.405130 156 : 4250, 0
7451 22:20:10.409046 160 : 4250, 0
7452 22:20:10.409129 164 : 4250, 0
7453 22:20:10.409194 168 : 4249, 0
7454 22:20:10.411650 172 : 4252, 0
7455 22:20:10.411732 176 : 4361, 0
7456 22:20:10.415477 180 : 4361, 0
7457 22:20:10.415558 184 : 4363, 0
7458 22:20:10.415624 188 : 4363, 0
7459 22:20:10.418439 192 : 4250, 0
7460 22:20:10.418522 196 : 4249, 0
7461 22:20:10.421378 200 : 4250, 0
7462 22:20:10.421460 204 : 4250, 0
7463 22:20:10.421526 208 : 4250, 0
7464 22:20:10.424723 212 : 4252, 0
7465 22:20:10.424805 216 : 4250, 0
7466 22:20:10.428292 220 : 4249, 0
7467 22:20:10.428373 224 : 4253, 245
7468 22:20:10.428440 228 : 4361, 3307
7469 22:20:10.432125 232 : 4250, 4027
7470 22:20:10.432207 236 : 4250, 4027
7471 22:20:10.434865 240 : 4363, 4140
7472 22:20:10.434947 244 : 4250, 4027
7473 22:20:10.437889 248 : 4250, 4027
7474 22:20:10.437972 252 : 4250, 4027
7475 22:20:10.441558 256 : 4252, 4029
7476 22:20:10.441658 260 : 4250, 4027
7477 22:20:10.444411 264 : 4253, 4026
7478 22:20:10.444493 268 : 4361, 4137
7479 22:20:10.448315 272 : 4250, 4027
7480 22:20:10.448398 276 : 4250, 4027
7481 22:20:10.451010 280 : 4360, 4137
7482 22:20:10.451092 284 : 4250, 4026
7483 22:20:10.454400 288 : 4250, 4027
7484 22:20:10.454482 292 : 4363, 4140
7485 22:20:10.454547 296 : 4250, 4027
7486 22:20:10.457685 300 : 4250, 4027
7487 22:20:10.457767 304 : 4250, 4027
7488 22:20:10.461028 308 : 4252, 4029
7489 22:20:10.461110 312 : 4250, 4027
7490 22:20:10.464247 316 : 4250, 4026
7491 22:20:10.464329 320 : 4361, 4137
7492 22:20:10.467858 324 : 4250, 4027
7493 22:20:10.467940 328 : 4249, 4027
7494 22:20:10.470987 332 : 4360, 4137
7495 22:20:10.471069 336 : 4250, 3774
7496 22:20:10.474196 340 : 4250, 1714
7497 22:20:10.474278
7498 22:20:10.474343 MIOCK jitter meter ch=0
7499 22:20:10.474402
7500 22:20:10.477468 1T = (340-92) = 248 dly cells
7501 22:20:10.484010 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7502 22:20:10.484092 ==
7503 22:20:10.487556 Dram Type= 6, Freq= 0, CH_0, rank 0
7504 22:20:10.490448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 22:20:10.490530 ==
7506 22:20:10.497359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 22:20:10.500831 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 22:20:10.507075 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 22:20:10.510093 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 22:20:10.520314 [CA 0] Center 43 (12~74) winsize 63
7511 22:20:10.523953 [CA 1] Center 42 (12~73) winsize 62
7512 22:20:10.527442 [CA 2] Center 38 (9~68) winsize 60
7513 22:20:10.530426 [CA 3] Center 38 (8~68) winsize 61
7514 22:20:10.533837 [CA 4] Center 36 (7~66) winsize 60
7515 22:20:10.537428 [CA 5] Center 35 (6~65) winsize 60
7516 22:20:10.537509
7517 22:20:10.540233 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 22:20:10.540315
7519 22:20:10.543511 [CATrainingPosCal] consider 1 rank data
7520 22:20:10.547150 u2DelayCellTimex100 = 262/100 ps
7521 22:20:10.550760 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7522 22:20:10.557100 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7523 22:20:10.560623 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7524 22:20:10.563375 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7525 22:20:10.567362 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7526 22:20:10.570038 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7527 22:20:10.570119
7528 22:20:10.573989 CA PerBit enable=1, Macro0, CA PI delay=35
7529 22:20:10.574071
7530 22:20:10.577078 [CBTSetCACLKResult] CA Dly = 35
7531 22:20:10.580242 CS Dly: 12 (0~43)
7532 22:20:10.583503 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 22:20:10.586546 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 22:20:10.586629 ==
7535 22:20:10.589929 Dram Type= 6, Freq= 0, CH_0, rank 1
7536 22:20:10.596333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 22:20:10.596415 ==
7538 22:20:10.599631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 22:20:10.606683 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 22:20:10.609522 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 22:20:10.616070 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 22:20:10.624227 [CA 0] Center 43 (13~74) winsize 62
7543 22:20:10.627320 [CA 1] Center 44 (14~74) winsize 61
7544 22:20:10.630755 [CA 2] Center 38 (9~68) winsize 60
7545 22:20:10.633768 [CA 3] Center 38 (9~68) winsize 60
7546 22:20:10.637255 [CA 4] Center 36 (7~66) winsize 60
7547 22:20:10.640868 [CA 5] Center 36 (6~66) winsize 61
7548 22:20:10.640961
7549 22:20:10.644258 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 22:20:10.644331
7551 22:20:10.647069 [CATrainingPosCal] consider 2 rank data
7552 22:20:10.650247 u2DelayCellTimex100 = 262/100 ps
7553 22:20:10.656966 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7554 22:20:10.660396 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7555 22:20:10.664626 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7556 22:20:10.667526 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7557 22:20:10.670325 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7558 22:20:10.673958 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7559 22:20:10.674041
7560 22:20:10.677435 CA PerBit enable=1, Macro0, CA PI delay=35
7561 22:20:10.677517
7562 22:20:10.680342 [CBTSetCACLKResult] CA Dly = 35
7563 22:20:10.683259 CS Dly: 12 (0~44)
7564 22:20:10.686726 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 22:20:10.690430 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 22:20:10.690507
7567 22:20:10.693583 ----->DramcWriteLeveling(PI) begin...
7568 22:20:10.693659 ==
7569 22:20:10.696800 Dram Type= 6, Freq= 0, CH_0, rank 0
7570 22:20:10.703404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7571 22:20:10.703485 ==
7572 22:20:10.706640 Write leveling (Byte 0): 35 => 35
7573 22:20:10.709605 Write leveling (Byte 1): 28 => 28
7574 22:20:10.709677 DramcWriteLeveling(PI) end<-----
7575 22:20:10.713494
7576 22:20:10.713565 ==
7577 22:20:10.716272 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 22:20:10.719986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 22:20:10.720061 ==
7580 22:20:10.722842 [Gating] SW mode calibration
7581 22:20:10.729629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7582 22:20:10.736454 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7583 22:20:10.739529 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 22:20:10.743408 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 22:20:10.748897 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 22:20:10.752918 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
7587 22:20:10.755992 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7588 22:20:10.759363 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7589 22:20:10.766123 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7590 22:20:10.769699 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 22:20:10.772689 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 22:20:10.779172 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 22:20:10.782542 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7594 22:20:10.786122 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7595 22:20:10.792075 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7596 22:20:10.795460 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7597 22:20:10.802403 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7598 22:20:10.805476 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 22:20:10.808561 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 22:20:10.815296 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 22:20:10.818498 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7602 22:20:10.821638 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7603 22:20:10.828797 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7604 22:20:10.831896 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7605 22:20:10.835039 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7606 22:20:10.841311 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 22:20:10.844672 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 22:20:10.848098 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 22:20:10.854423 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 22:20:10.857829 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 22:20:10.861250 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7612 22:20:10.868087 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 22:20:10.870862 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 22:20:10.874689 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 22:20:10.880520 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 22:20:10.884365 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 22:20:10.887330 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 22:20:10.894044 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 22:20:10.897569 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 22:20:10.900791 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 22:20:10.907018 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 22:20:10.910323 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 22:20:10.913845 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 22:20:10.920627 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 22:20:10.924242 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 22:20:10.926942 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 22:20:10.933825 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 22:20:10.936725 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7629 22:20:10.940318 Total UI for P1: 0, mck2ui 16
7630 22:20:10.943773 best dqsien dly found for B0: ( 1, 9, 12)
7631 22:20:10.946794 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 22:20:10.953481 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 22:20:10.953553 Total UI for P1: 0, mck2ui 16
7634 22:20:10.956500 best dqsien dly found for B1: ( 1, 9, 22)
7635 22:20:10.963859 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7636 22:20:10.966981 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7637 22:20:10.967055
7638 22:20:10.970061 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7639 22:20:10.973180 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7640 22:20:10.976803 [Gating] SW calibration Done
7641 22:20:10.976874 ==
7642 22:20:10.979779 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 22:20:10.983480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 22:20:10.983553 ==
7645 22:20:10.986212 RX Vref Scan: 0
7646 22:20:10.986284
7647 22:20:10.986343 RX Vref 0 -> 0, step: 1
7648 22:20:10.986400
7649 22:20:10.989911 RX Delay 0 -> 252, step: 8
7650 22:20:10.993140 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7651 22:20:10.999659 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7652 22:20:11.002757 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7653 22:20:11.006063 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7654 22:20:11.009174 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7655 22:20:11.012360 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7656 22:20:11.019318 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7657 22:20:11.022745 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7658 22:20:11.025871 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7659 22:20:11.028911 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7660 22:20:11.035825 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7661 22:20:11.038826 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7662 22:20:11.042194 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7663 22:20:11.045538 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7664 22:20:11.048898 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7665 22:20:11.056047 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7666 22:20:11.056122 ==
7667 22:20:11.058607 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 22:20:11.062497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 22:20:11.062568 ==
7670 22:20:11.062628 DQS Delay:
7671 22:20:11.065116 DQS0 = 0, DQS1 = 0
7672 22:20:11.065186 DQM Delay:
7673 22:20:11.068794 DQM0 = 135, DQM1 = 126
7674 22:20:11.068866 DQ Delay:
7675 22:20:11.071855 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7676 22:20:11.075378 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7677 22:20:11.078288 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7678 22:20:11.081875 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7679 22:20:11.085580
7680 22:20:11.085647
7681 22:20:11.085706 ==
7682 22:20:11.088681 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 22:20:11.092091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 22:20:11.092162 ==
7685 22:20:11.092224
7686 22:20:11.092279
7687 22:20:11.095719 TX Vref Scan disable
7688 22:20:11.095786 == TX Byte 0 ==
7689 22:20:11.101563 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7690 22:20:11.105490 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7691 22:20:11.105560 == TX Byte 1 ==
7692 22:20:11.111566 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7693 22:20:11.115197 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7694 22:20:11.115269 ==
7695 22:20:11.118435 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 22:20:11.121392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 22:20:11.121468 ==
7698 22:20:11.135511
7699 22:20:11.138957 TX Vref early break, caculate TX vref
7700 22:20:11.142400 TX Vref=16, minBit 1, minWin=21, winSum=372
7701 22:20:11.145319 TX Vref=18, minBit 1, minWin=23, winSum=382
7702 22:20:11.149006 TX Vref=20, minBit 3, minWin=24, winSum=396
7703 22:20:11.152051 TX Vref=22, minBit 6, minWin=23, winSum=398
7704 22:20:11.155497 TX Vref=24, minBit 0, minWin=25, winSum=412
7705 22:20:11.161641 TX Vref=26, minBit 0, minWin=24, winSum=417
7706 22:20:11.165345 TX Vref=28, minBit 0, minWin=26, winSum=419
7707 22:20:11.168710 TX Vref=30, minBit 5, minWin=24, winSum=410
7708 22:20:11.172108 TX Vref=32, minBit 0, minWin=24, winSum=404
7709 22:20:11.175237 TX Vref=34, minBit 4, minWin=22, winSum=386
7710 22:20:11.181550 [TxChooseVref] Worse bit 0, Min win 26, Win sum 419, Final Vref 28
7711 22:20:11.181623
7712 22:20:11.185325 Final TX Range 0 Vref 28
7713 22:20:11.185395
7714 22:20:11.185454 ==
7715 22:20:11.188234 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 22:20:11.191451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 22:20:11.191522 ==
7718 22:20:11.191582
7719 22:20:11.191639
7720 22:20:11.194817 TX Vref Scan disable
7721 22:20:11.201252 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7722 22:20:11.201325 == TX Byte 0 ==
7723 22:20:11.204736 u2DelayCellOfst[0]=11 cells (3 PI)
7724 22:20:11.208136 u2DelayCellOfst[1]=14 cells (4 PI)
7725 22:20:11.211302 u2DelayCellOfst[2]=11 cells (3 PI)
7726 22:20:11.214350 u2DelayCellOfst[3]=11 cells (3 PI)
7727 22:20:11.217645 u2DelayCellOfst[4]=7 cells (2 PI)
7728 22:20:11.221493 u2DelayCellOfst[5]=0 cells (0 PI)
7729 22:20:11.224924 u2DelayCellOfst[6]=18 cells (5 PI)
7730 22:20:11.227353 u2DelayCellOfst[7]=18 cells (5 PI)
7731 22:20:11.231169 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7732 22:20:11.234291 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7733 22:20:11.237402 == TX Byte 1 ==
7734 22:20:11.240891 u2DelayCellOfst[8]=0 cells (0 PI)
7735 22:20:11.244216 u2DelayCellOfst[9]=0 cells (0 PI)
7736 22:20:11.247230 u2DelayCellOfst[10]=3 cells (1 PI)
7737 22:20:11.250576 u2DelayCellOfst[11]=0 cells (0 PI)
7738 22:20:11.254112 u2DelayCellOfst[12]=11 cells (3 PI)
7739 22:20:11.254534 u2DelayCellOfst[13]=11 cells (3 PI)
7740 22:20:11.257795 u2DelayCellOfst[14]=14 cells (4 PI)
7741 22:20:11.261138 u2DelayCellOfst[15]=11 cells (3 PI)
7742 22:20:11.267263 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7743 22:20:11.271161 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7744 22:20:11.271250 DramC Write-DBI on
7745 22:20:11.273900 ==
7746 22:20:11.276995 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 22:20:11.280276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 22:20:11.280358 ==
7749 22:20:11.280422
7750 22:20:11.280481
7751 22:20:11.283715 TX Vref Scan disable
7752 22:20:11.283795 == TX Byte 0 ==
7753 22:20:11.290730 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7754 22:20:11.290859 == TX Byte 1 ==
7755 22:20:11.293475 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7756 22:20:11.297183 DramC Write-DBI off
7757 22:20:11.297283
7758 22:20:11.297362 [DATLAT]
7759 22:20:11.300181 Freq=1600, CH0 RK0
7760 22:20:11.300291
7761 22:20:11.300383 DATLAT Default: 0xf
7762 22:20:11.303799 0, 0xFFFF, sum = 0
7763 22:20:11.303934 1, 0xFFFF, sum = 0
7764 22:20:11.307050 2, 0xFFFF, sum = 0
7765 22:20:11.310606 3, 0xFFFF, sum = 0
7766 22:20:11.310741 4, 0xFFFF, sum = 0
7767 22:20:11.313133 5, 0xFFFF, sum = 0
7768 22:20:11.313272 6, 0xFFFF, sum = 0
7769 22:20:11.316763 7, 0xFFFF, sum = 0
7770 22:20:11.316914 8, 0xFFFF, sum = 0
7771 22:20:11.319867 9, 0xFFFF, sum = 0
7772 22:20:11.320039 10, 0xFFFF, sum = 0
7773 22:20:11.323191 11, 0xFFFF, sum = 0
7774 22:20:11.323364 12, 0xFFFF, sum = 0
7775 22:20:11.326345 13, 0xFFFF, sum = 0
7776 22:20:11.326546 14, 0x0, sum = 1
7777 22:20:11.330030 15, 0x0, sum = 2
7778 22:20:11.330270 16, 0x0, sum = 3
7779 22:20:11.333057 17, 0x0, sum = 4
7780 22:20:11.333297 best_step = 15
7781 22:20:11.333483
7782 22:20:11.333655 ==
7783 22:20:11.336776 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 22:20:11.343577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 22:20:11.343998 ==
7786 22:20:11.344393 RX Vref Scan: 1
7787 22:20:11.344933
7788 22:20:11.346694 Set Vref Range= 24 -> 127
7789 22:20:11.347110
7790 22:20:11.349895 RX Vref 24 -> 127, step: 1
7791 22:20:11.350405
7792 22:20:11.350749 RX Delay 19 -> 252, step: 4
7793 22:20:11.351058
7794 22:20:11.353216 Set Vref, RX VrefLevel [Byte0]: 24
7795 22:20:11.356254 [Byte1]: 24
7796 22:20:11.360781
7797 22:20:11.361198 Set Vref, RX VrefLevel [Byte0]: 25
7798 22:20:11.363908 [Byte1]: 25
7799 22:20:11.368262
7800 22:20:11.368718 Set Vref, RX VrefLevel [Byte0]: 26
7801 22:20:11.371470 [Byte1]: 26
7802 22:20:11.375636
7803 22:20:11.376223 Set Vref, RX VrefLevel [Byte0]: 27
7804 22:20:11.379401 [Byte1]: 27
7805 22:20:11.382734
7806 22:20:11.382834 Set Vref, RX VrefLevel [Byte0]: 28
7807 22:20:11.386076 [Byte1]: 28
7808 22:20:11.390606
7809 22:20:11.390707 Set Vref, RX VrefLevel [Byte0]: 29
7810 22:20:11.394215 [Byte1]: 29
7811 22:20:11.398131
7812 22:20:11.398204 Set Vref, RX VrefLevel [Byte0]: 30
7813 22:20:11.401473 [Byte1]: 30
7814 22:20:11.406040
7815 22:20:11.406113 Set Vref, RX VrefLevel [Byte0]: 31
7816 22:20:11.409215 [Byte1]: 31
7817 22:20:11.412973
7818 22:20:11.413046 Set Vref, RX VrefLevel [Byte0]: 32
7819 22:20:11.416751 [Byte1]: 32
7820 22:20:11.421279
7821 22:20:11.421351 Set Vref, RX VrefLevel [Byte0]: 33
7822 22:20:11.423936 [Byte1]: 33
7823 22:20:11.428331
7824 22:20:11.428428 Set Vref, RX VrefLevel [Byte0]: 34
7825 22:20:11.431707 [Byte1]: 34
7826 22:20:11.436098
7827 22:20:11.436203 Set Vref, RX VrefLevel [Byte0]: 35
7828 22:20:11.439244 [Byte1]: 35
7829 22:20:11.443291
7830 22:20:11.443386 Set Vref, RX VrefLevel [Byte0]: 36
7831 22:20:11.446892 [Byte1]: 36
7832 22:20:11.451131
7833 22:20:11.451227 Set Vref, RX VrefLevel [Byte0]: 37
7834 22:20:11.454501 [Byte1]: 37
7835 22:20:11.458951
7836 22:20:11.459053 Set Vref, RX VrefLevel [Byte0]: 38
7837 22:20:11.461910 [Byte1]: 38
7838 22:20:11.466354
7839 22:20:11.466453 Set Vref, RX VrefLevel [Byte0]: 39
7840 22:20:11.469693 [Byte1]: 39
7841 22:20:11.473616
7842 22:20:11.473691 Set Vref, RX VrefLevel [Byte0]: 40
7843 22:20:11.476870 [Byte1]: 40
7844 22:20:11.481748
7845 22:20:11.481820 Set Vref, RX VrefLevel [Byte0]: 41
7846 22:20:11.485167 [Byte1]: 41
7847 22:20:11.489144
7848 22:20:11.489242 Set Vref, RX VrefLevel [Byte0]: 42
7849 22:20:11.492078 [Byte1]: 42
7850 22:20:11.496829
7851 22:20:11.496899 Set Vref, RX VrefLevel [Byte0]: 43
7852 22:20:11.499952 [Byte1]: 43
7853 22:20:11.504141
7854 22:20:11.504209 Set Vref, RX VrefLevel [Byte0]: 44
7855 22:20:11.507297 [Byte1]: 44
7856 22:20:11.511615
7857 22:20:11.511686 Set Vref, RX VrefLevel [Byte0]: 45
7858 22:20:11.515024 [Byte1]: 45
7859 22:20:11.519263
7860 22:20:11.519341 Set Vref, RX VrefLevel [Byte0]: 46
7861 22:20:11.522312 [Byte1]: 46
7862 22:20:11.526657
7863 22:20:11.526734 Set Vref, RX VrefLevel [Byte0]: 47
7864 22:20:11.530422 [Byte1]: 47
7865 22:20:11.534424
7866 22:20:11.534536 Set Vref, RX VrefLevel [Byte0]: 48
7867 22:20:11.537427 [Byte1]: 48
7868 22:20:11.542009
7869 22:20:11.544905 Set Vref, RX VrefLevel [Byte0]: 49
7870 22:20:11.548306 [Byte1]: 49
7871 22:20:11.548402
7872 22:20:11.551666 Set Vref, RX VrefLevel [Byte0]: 50
7873 22:20:11.554910 [Byte1]: 50
7874 22:20:11.555015
7875 22:20:11.558253 Set Vref, RX VrefLevel [Byte0]: 51
7876 22:20:11.561391 [Byte1]: 51
7877 22:20:11.561477
7878 22:20:11.565041 Set Vref, RX VrefLevel [Byte0]: 52
7879 22:20:11.568261 [Byte1]: 52
7880 22:20:11.572795
7881 22:20:11.572894 Set Vref, RX VrefLevel [Byte0]: 53
7882 22:20:11.575559 [Byte1]: 53
7883 22:20:11.579833
7884 22:20:11.579927 Set Vref, RX VrefLevel [Byte0]: 54
7885 22:20:11.583111 [Byte1]: 54
7886 22:20:11.587346
7887 22:20:11.587442 Set Vref, RX VrefLevel [Byte0]: 55
7888 22:20:11.590620 [Byte1]: 55
7889 22:20:11.594909
7890 22:20:11.594977 Set Vref, RX VrefLevel [Byte0]: 56
7891 22:20:11.598158 [Byte1]: 56
7892 22:20:11.602613
7893 22:20:11.602708 Set Vref, RX VrefLevel [Byte0]: 57
7894 22:20:11.606175 [Byte1]: 57
7895 22:20:11.610197
7896 22:20:11.610292 Set Vref, RX VrefLevel [Byte0]: 58
7897 22:20:11.613366 [Byte1]: 58
7898 22:20:11.617825
7899 22:20:11.617927 Set Vref, RX VrefLevel [Byte0]: 59
7900 22:20:11.620896 [Byte1]: 59
7901 22:20:11.625115
7902 22:20:11.625210 Set Vref, RX VrefLevel [Byte0]: 60
7903 22:20:11.628382 [Byte1]: 60
7904 22:20:11.632616
7905 22:20:11.632684 Set Vref, RX VrefLevel [Byte0]: 61
7906 22:20:11.636770 [Byte1]: 61
7907 22:20:11.640327
7908 22:20:11.643407 Set Vref, RX VrefLevel [Byte0]: 62
7909 22:20:11.646762 [Byte1]: 62
7910 22:20:11.646857
7911 22:20:11.649935 Set Vref, RX VrefLevel [Byte0]: 63
7912 22:20:11.653470 [Byte1]: 63
7913 22:20:11.653573
7914 22:20:11.656996 Set Vref, RX VrefLevel [Byte0]: 64
7915 22:20:11.659881 [Byte1]: 64
7916 22:20:11.659975
7917 22:20:11.663691 Set Vref, RX VrefLevel [Byte0]: 65
7918 22:20:11.666932 [Byte1]: 65
7919 22:20:11.670516
7920 22:20:11.670612 Set Vref, RX VrefLevel [Byte0]: 66
7921 22:20:11.676928 [Byte1]: 66
7922 22:20:11.677001
7923 22:20:11.680244 Set Vref, RX VrefLevel [Byte0]: 67
7924 22:20:11.684043 [Byte1]: 67
7925 22:20:11.684117
7926 22:20:11.687008 Set Vref, RX VrefLevel [Byte0]: 68
7927 22:20:11.690742 [Byte1]: 68
7928 22:20:11.690829
7929 22:20:11.693747 Set Vref, RX VrefLevel [Byte0]: 69
7930 22:20:11.697442 [Byte1]: 69
7931 22:20:11.701039
7932 22:20:11.701164 Set Vref, RX VrefLevel [Byte0]: 70
7933 22:20:11.704428 [Byte1]: 70
7934 22:20:11.708925
7935 22:20:11.709026 Set Vref, RX VrefLevel [Byte0]: 71
7936 22:20:11.711825 [Byte1]: 71
7937 22:20:11.716361
7938 22:20:11.716471 Set Vref, RX VrefLevel [Byte0]: 72
7939 22:20:11.719191 [Byte1]: 72
7940 22:20:11.723712
7941 22:20:11.723787 Set Vref, RX VrefLevel [Byte0]: 73
7942 22:20:11.727027 [Byte1]: 73
7943 22:20:11.731370
7944 22:20:11.731466 Set Vref, RX VrefLevel [Byte0]: 74
7945 22:20:11.734779 [Byte1]: 74
7946 22:20:11.738804
7947 22:20:11.738878 Set Vref, RX VrefLevel [Byte0]: 75
7948 22:20:11.742130 [Byte1]: 75
7949 22:20:11.746913
7950 22:20:11.747001 Set Vref, RX VrefLevel [Byte0]: 76
7951 22:20:11.749692 [Byte1]: 76
7952 22:20:11.753790
7953 22:20:11.753883 Set Vref, RX VrefLevel [Byte0]: 77
7954 22:20:11.757414 [Byte1]: 77
7955 22:20:11.761725
7956 22:20:11.761885 Set Vref, RX VrefLevel [Byte0]: 78
7957 22:20:11.764874 [Byte1]: 78
7958 22:20:11.770018
7959 22:20:11.770184 Set Vref, RX VrefLevel [Byte0]: 79
7960 22:20:11.772214 [Byte1]: 79
7961 22:20:11.777027
7962 22:20:11.777130 Final RX Vref Byte 0 = 66 to rank0
7963 22:20:11.780279 Final RX Vref Byte 1 = 57 to rank0
7964 22:20:11.783630 Final RX Vref Byte 0 = 66 to rank1
7965 22:20:11.786944 Final RX Vref Byte 1 = 57 to rank1==
7966 22:20:11.790014 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 22:20:11.796757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 22:20:11.797176 ==
7969 22:20:11.797522 DQS Delay:
7970 22:20:11.799870 DQS0 = 0, DQS1 = 0
7971 22:20:11.800003 DQM Delay:
7972 22:20:11.803140 DQM0 = 133, DQM1 = 123
7973 22:20:11.803240 DQ Delay:
7974 22:20:11.805876 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7975 22:20:11.809468 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =144
7976 22:20:11.813262 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
7977 22:20:11.815633 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =130
7978 22:20:11.815734
7979 22:20:11.815823
7980 22:20:11.815909
7981 22:20:11.818980 [DramC_TX_OE_Calibration] TA2
7982 22:20:11.822693 Original DQ_B0 (3 6) =30, OEN = 27
7983 22:20:11.825555 Original DQ_B1 (3 6) =30, OEN = 27
7984 22:20:11.829161 24, 0x0, End_B0=24 End_B1=24
7985 22:20:11.832410 25, 0x0, End_B0=25 End_B1=25
7986 22:20:11.832510 26, 0x0, End_B0=26 End_B1=26
7987 22:20:11.835749 27, 0x0, End_B0=27 End_B1=27
7988 22:20:11.838649 28, 0x0, End_B0=28 End_B1=28
7989 22:20:11.842522 29, 0x0, End_B0=29 End_B1=29
7990 22:20:11.845641 30, 0x0, End_B0=30 End_B1=30
7991 22:20:11.845742 31, 0x4141, End_B0=30 End_B1=30
7992 22:20:11.848590 Byte0 end_step=30 best_step=27
7993 22:20:11.851903 Byte1 end_step=30 best_step=27
7994 22:20:11.854968 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 22:20:11.858500 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 22:20:11.858572
7997 22:20:11.858654
7998 22:20:11.865795 [DQSOSCAuto] RK0, (LSB)MR18= 0x2213, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
7999 22:20:11.868141 CH0 RK0: MR19=303, MR18=2213
8000 22:20:11.874709 CH0_RK0: MR19=0x303, MR18=0x2213, DQSOSC=392, MR23=63, INC=24, DEC=16
8001 22:20:11.874809
8002 22:20:11.878167 ----->DramcWriteLeveling(PI) begin...
8003 22:20:11.878266 ==
8004 22:20:11.881301 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 22:20:11.888177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 22:20:11.888277 ==
8007 22:20:11.891458 Write leveling (Byte 0): 36 => 36
8008 22:20:11.891558 Write leveling (Byte 1): 28 => 28
8009 22:20:11.894731 DramcWriteLeveling(PI) end<-----
8010 22:20:11.894828
8011 22:20:11.894914 ==
8012 22:20:11.897738 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 22:20:11.904658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 22:20:11.904735 ==
8015 22:20:11.907668 [Gating] SW mode calibration
8016 22:20:11.914860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 22:20:11.917990 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 22:20:11.924111 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 22:20:11.927534 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 22:20:11.931055 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 22:20:11.937798 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8022 22:20:11.940832 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8023 22:20:11.943912 1 4 20 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
8024 22:20:11.950957 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 22:20:11.954433 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 22:20:11.957295 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 22:20:11.963781 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 22:20:11.967377 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 22:20:11.970454 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8030 22:20:11.977345 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8031 22:20:11.980815 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8032 22:20:11.984015 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 22:20:11.990570 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 22:20:11.993514 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 22:20:11.997893 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 22:20:12.004142 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 22:20:12.007372 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8038 22:20:12.010337 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8039 22:20:12.017006 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8040 22:20:12.020221 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 22:20:12.023450 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 22:20:12.030405 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 22:20:12.033701 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 22:20:12.036897 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 22:20:12.043673 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 22:20:12.046634 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 22:20:12.049912 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 22:20:12.056428 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 22:20:12.059980 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 22:20:12.062886 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 22:20:12.069728 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 22:20:12.072988 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 22:20:12.076205 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 22:20:12.083253 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 22:20:12.085905 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 22:20:12.089477 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 22:20:12.096004 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 22:20:12.099634 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 22:20:12.102581 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 22:20:12.109339 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 22:20:12.112834 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8062 22:20:12.115676 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8063 22:20:12.122332 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8064 22:20:12.122439 Total UI for P1: 0, mck2ui 16
8065 22:20:12.125776 best dqsien dly found for B0: ( 1, 9, 12)
8066 22:20:12.132122 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 22:20:12.135814 Total UI for P1: 0, mck2ui 16
8068 22:20:12.138955 best dqsien dly found for B1: ( 1, 9, 20)
8069 22:20:12.142176 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8070 22:20:12.145669 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8071 22:20:12.145741
8072 22:20:12.148530 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8073 22:20:12.151940 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8074 22:20:12.155470 [Gating] SW calibration Done
8075 22:20:12.155565 ==
8076 22:20:12.158892 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 22:20:12.162043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 22:20:12.165581 ==
8079 22:20:12.165675 RX Vref Scan: 0
8080 22:20:12.165761
8081 22:20:12.168748 RX Vref 0 -> 0, step: 1
8082 22:20:12.168817
8083 22:20:12.168876 RX Delay 0 -> 252, step: 8
8084 22:20:12.175347 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8085 22:20:12.178735 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8086 22:20:12.182239 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8087 22:20:12.184900 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8088 22:20:12.191902 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8089 22:20:12.195086 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8090 22:20:12.198244 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8091 22:20:12.201886 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8092 22:20:12.205100 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8093 22:20:12.211690 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8094 22:20:12.214759 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8095 22:20:12.218102 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8096 22:20:12.221874 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8097 22:20:12.225202 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8098 22:20:12.231601 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8099 22:20:12.234649 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8100 22:20:12.234745 ==
8101 22:20:12.238229 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 22:20:12.241343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 22:20:12.241412 ==
8104 22:20:12.244637 DQS Delay:
8105 22:20:12.244730 DQS0 = 0, DQS1 = 0
8106 22:20:12.244818 DQM Delay:
8107 22:20:12.247958 DQM0 = 133, DQM1 = 129
8108 22:20:12.248024 DQ Delay:
8109 22:20:12.251077 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8110 22:20:12.254446 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8111 22:20:12.261331 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8112 22:20:12.264796 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8113 22:20:12.264891
8114 22:20:12.264981
8115 22:20:12.265066 ==
8116 22:20:12.268436 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 22:20:12.271008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 22:20:12.271102 ==
8119 22:20:12.271191
8120 22:20:12.271274
8121 22:20:12.274363 TX Vref Scan disable
8122 22:20:12.277714 == TX Byte 0 ==
8123 22:20:12.280692 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8124 22:20:12.284427 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8125 22:20:12.287738 == TX Byte 1 ==
8126 22:20:12.290961 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8127 22:20:12.294018 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8128 22:20:12.294116 ==
8129 22:20:12.297331 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 22:20:12.300904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 22:20:12.304206 ==
8132 22:20:12.315712
8133 22:20:12.319414 TX Vref early break, caculate TX vref
8134 22:20:12.322491 TX Vref=16, minBit 2, minWin=22, winSum=375
8135 22:20:12.326224 TX Vref=18, minBit 0, minWin=23, winSum=383
8136 22:20:12.329410 TX Vref=20, minBit 2, minWin=23, winSum=395
8137 22:20:12.332283 TX Vref=22, minBit 1, minWin=22, winSum=402
8138 22:20:12.336042 TX Vref=24, minBit 3, minWin=24, winSum=412
8139 22:20:12.342306 TX Vref=26, minBit 1, minWin=24, winSum=416
8140 22:20:12.345492 TX Vref=28, minBit 0, minWin=24, winSum=413
8141 22:20:12.348971 TX Vref=30, minBit 0, minWin=24, winSum=403
8142 22:20:12.352114 TX Vref=32, minBit 0, minWin=24, winSum=396
8143 22:20:12.356025 TX Vref=34, minBit 0, minWin=23, winSum=386
8144 22:20:12.362180 [TxChooseVref] Worse bit 1, Min win 24, Win sum 416, Final Vref 26
8145 22:20:12.362281
8146 22:20:12.365245 Final TX Range 0 Vref 26
8147 22:20:12.365348
8148 22:20:12.365436 ==
8149 22:20:12.368823 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 22:20:12.371852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 22:20:12.371946 ==
8152 22:20:12.372035
8153 22:20:12.372121
8154 22:20:12.375056 TX Vref Scan disable
8155 22:20:12.382051 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8156 22:20:12.382154 == TX Byte 0 ==
8157 22:20:12.385226 u2DelayCellOfst[0]=11 cells (3 PI)
8158 22:20:12.388484 u2DelayCellOfst[1]=14 cells (4 PI)
8159 22:20:12.391592 u2DelayCellOfst[2]=11 cells (3 PI)
8160 22:20:12.394879 u2DelayCellOfst[3]=14 cells (4 PI)
8161 22:20:12.398147 u2DelayCellOfst[4]=7 cells (2 PI)
8162 22:20:12.401602 u2DelayCellOfst[5]=0 cells (0 PI)
8163 22:20:12.405085 u2DelayCellOfst[6]=14 cells (4 PI)
8164 22:20:12.408078 u2DelayCellOfst[7]=18 cells (5 PI)
8165 22:20:12.411622 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8166 22:20:12.414911 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8167 22:20:12.417932 == TX Byte 1 ==
8168 22:20:12.421721 u2DelayCellOfst[8]=0 cells (0 PI)
8169 22:20:12.424491 u2DelayCellOfst[9]=3 cells (1 PI)
8170 22:20:12.428079 u2DelayCellOfst[10]=7 cells (2 PI)
8171 22:20:12.428151 u2DelayCellOfst[11]=3 cells (1 PI)
8172 22:20:12.431434 u2DelayCellOfst[12]=11 cells (3 PI)
8173 22:20:12.434608 u2DelayCellOfst[13]=14 cells (4 PI)
8174 22:20:12.437705 u2DelayCellOfst[14]=18 cells (5 PI)
8175 22:20:12.441124 u2DelayCellOfst[15]=11 cells (3 PI)
8176 22:20:12.447713 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8177 22:20:12.451211 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8178 22:20:12.451317 DramC Write-DBI on
8179 22:20:12.454176 ==
8180 22:20:12.454287 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 22:20:12.461153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 22:20:12.461226 ==
8183 22:20:12.461291
8184 22:20:12.461352
8185 22:20:12.464297 TX Vref Scan disable
8186 22:20:12.464389 == TX Byte 0 ==
8187 22:20:12.470506 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8188 22:20:12.470603 == TX Byte 1 ==
8189 22:20:12.474042 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8190 22:20:12.477462 DramC Write-DBI off
8191 22:20:12.477557
8192 22:20:12.477645 [DATLAT]
8193 22:20:12.480429 Freq=1600, CH0 RK1
8194 22:20:12.480556
8195 22:20:12.480618 DATLAT Default: 0xf
8196 22:20:12.484184 0, 0xFFFF, sum = 0
8197 22:20:12.484257 1, 0xFFFF, sum = 0
8198 22:20:12.487131 2, 0xFFFF, sum = 0
8199 22:20:12.487230 3, 0xFFFF, sum = 0
8200 22:20:12.490812 4, 0xFFFF, sum = 0
8201 22:20:12.490921 5, 0xFFFF, sum = 0
8202 22:20:12.493938 6, 0xFFFF, sum = 0
8203 22:20:12.497279 7, 0xFFFF, sum = 0
8204 22:20:12.497385 8, 0xFFFF, sum = 0
8205 22:20:12.500803 9, 0xFFFF, sum = 0
8206 22:20:12.500872 10, 0xFFFF, sum = 0
8207 22:20:12.503813 11, 0xFFFF, sum = 0
8208 22:20:12.503924 12, 0xFFFF, sum = 0
8209 22:20:12.507507 13, 0xFFFF, sum = 0
8210 22:20:12.507639 14, 0x0, sum = 1
8211 22:20:12.510654 15, 0x0, sum = 2
8212 22:20:12.510766 16, 0x0, sum = 3
8213 22:20:12.513745 17, 0x0, sum = 4
8214 22:20:12.513812 best_step = 15
8215 22:20:12.513873
8216 22:20:12.513929 ==
8217 22:20:12.517394 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 22:20:12.520384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 22:20:12.520488 ==
8220 22:20:12.523842 RX Vref Scan: 0
8221 22:20:12.523910
8222 22:20:12.527326 RX Vref 0 -> 0, step: 1
8223 22:20:12.527422
8224 22:20:12.527510 RX Delay 11 -> 252, step: 4
8225 22:20:12.534383 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8226 22:20:12.537443 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8227 22:20:12.541111 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8228 22:20:12.544332 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8229 22:20:12.550698 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8230 22:20:12.553922 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8231 22:20:12.557236 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8232 22:20:12.560557 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8233 22:20:12.564004 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8234 22:20:12.570180 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8235 22:20:12.573689 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8236 22:20:12.576950 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8237 22:20:12.580040 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8238 22:20:12.583529 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8239 22:20:12.590042 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8240 22:20:12.593375 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8241 22:20:12.593445 ==
8242 22:20:12.596915 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 22:20:12.600207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 22:20:12.600300 ==
8245 22:20:12.603688 DQS Delay:
8246 22:20:12.603771 DQS0 = 0, DQS1 = 0
8247 22:20:12.603857 DQM Delay:
8248 22:20:12.606928 DQM0 = 130, DQM1 = 125
8249 22:20:12.607021 DQ Delay:
8250 22:20:12.610125 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8251 22:20:12.613218 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =140
8252 22:20:12.620075 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8253 22:20:12.623377 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8254 22:20:12.623477
8255 22:20:12.623566
8256 22:20:12.623642
8257 22:20:12.626762 [DramC_TX_OE_Calibration] TA2
8258 22:20:12.629982 Original DQ_B0 (3 6) =30, OEN = 27
8259 22:20:12.633050 Original DQ_B1 (3 6) =30, OEN = 27
8260 22:20:12.633146 24, 0x0, End_B0=24 End_B1=24
8261 22:20:12.636741 25, 0x0, End_B0=25 End_B1=25
8262 22:20:12.639858 26, 0x0, End_B0=26 End_B1=26
8263 22:20:12.643462 27, 0x0, End_B0=27 End_B1=27
8264 22:20:12.643544 28, 0x0, End_B0=28 End_B1=28
8265 22:20:12.646775 29, 0x0, End_B0=29 End_B1=29
8266 22:20:12.650096 30, 0x0, End_B0=30 End_B1=30
8267 22:20:12.653506 31, 0x4141, End_B0=30 End_B1=30
8268 22:20:12.656273 Byte0 end_step=30 best_step=27
8269 22:20:12.659693 Byte1 end_step=30 best_step=27
8270 22:20:12.659775 Byte0 TX OE(2T, 0.5T) = (3, 3)
8271 22:20:12.662930 Byte1 TX OE(2T, 0.5T) = (3, 3)
8272 22:20:12.663010
8273 22:20:12.663073
8274 22:20:12.672676 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8275 22:20:12.676128 CH0 RK1: MR19=303, MR18=2104
8276 22:20:12.679465 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8277 22:20:12.682812 [RxdqsGatingPostProcess] freq 1600
8278 22:20:12.689198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8279 22:20:12.692727 best DQS0 dly(2T, 0.5T) = (1, 1)
8280 22:20:12.695924 best DQS1 dly(2T, 0.5T) = (1, 1)
8281 22:20:12.699352 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8282 22:20:12.702498 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8283 22:20:12.705589 best DQS0 dly(2T, 0.5T) = (1, 1)
8284 22:20:12.708964 best DQS1 dly(2T, 0.5T) = (1, 1)
8285 22:20:12.712386 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8286 22:20:12.715507 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8287 22:20:12.715588 Pre-setting of DQS Precalculation
8288 22:20:12.722027 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8289 22:20:12.722113 ==
8290 22:20:12.725549 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 22:20:12.729256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 22:20:12.729341 ==
8293 22:20:12.735915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 22:20:12.739219 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 22:20:12.742265 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 22:20:12.749104 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 22:20:12.758686 [CA 0] Center 41 (12~71) winsize 60
8298 22:20:12.762289 [CA 1] Center 42 (12~72) winsize 61
8299 22:20:12.765062 [CA 2] Center 36 (7~66) winsize 60
8300 22:20:12.768450 [CA 3] Center 35 (6~65) winsize 60
8301 22:20:12.771647 [CA 4] Center 36 (7~66) winsize 60
8302 22:20:12.775113 [CA 5] Center 36 (6~66) winsize 61
8303 22:20:12.775193
8304 22:20:12.778139 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8305 22:20:12.778218
8306 22:20:12.781888 [CATrainingPosCal] consider 1 rank data
8307 22:20:12.785156 u2DelayCellTimex100 = 262/100 ps
8308 22:20:12.788636 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8309 22:20:12.794863 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8310 22:20:12.798182 CA2 delay=36 (7~66),Diff = 1 PI (3 cell)
8311 22:20:12.801682 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8312 22:20:12.804639 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8313 22:20:12.807861 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8314 22:20:12.807940
8315 22:20:12.811367 CA PerBit enable=1, Macro0, CA PI delay=35
8316 22:20:12.811447
8317 22:20:12.814692 [CBTSetCACLKResult] CA Dly = 35
8318 22:20:12.818471 CS Dly: 9 (0~40)
8319 22:20:12.821152 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 22:20:12.824628 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 22:20:12.824707 ==
8322 22:20:12.827858 Dram Type= 6, Freq= 0, CH_1, rank 1
8323 22:20:12.834150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 22:20:12.834230 ==
8325 22:20:12.837572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 22:20:12.843980 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 22:20:12.847396 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 22:20:12.854769 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 22:20:12.861544 [CA 0] Center 42 (14~71) winsize 58
8330 22:20:12.865095 [CA 1] Center 42 (12~72) winsize 61
8331 22:20:12.868094 [CA 2] Center 38 (9~67) winsize 59
8332 22:20:12.871450 [CA 3] Center 37 (7~67) winsize 61
8333 22:20:12.874738 [CA 4] Center 38 (9~67) winsize 59
8334 22:20:12.878204 [CA 5] Center 37 (8~66) winsize 59
8335 22:20:12.878287
8336 22:20:12.881904 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 22:20:12.881987
8338 22:20:12.885219 [CATrainingPosCal] consider 2 rank data
8339 22:20:12.888116 u2DelayCellTimex100 = 262/100 ps
8340 22:20:12.891299 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8341 22:20:12.898385 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8342 22:20:12.901230 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8343 22:20:12.904700 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8344 22:20:12.908166 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8345 22:20:12.911509 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8346 22:20:12.911593
8347 22:20:12.914635 CA PerBit enable=1, Macro0, CA PI delay=36
8348 22:20:12.914727
8349 22:20:12.918318 [CBTSetCACLKResult] CA Dly = 36
8350 22:20:12.921179 CS Dly: 10 (0~43)
8351 22:20:12.924814 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 22:20:12.927816 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 22:20:12.927900
8354 22:20:12.930877 ----->DramcWriteLeveling(PI) begin...
8355 22:20:12.930961 ==
8356 22:20:12.934322 Dram Type= 6, Freq= 0, CH_1, rank 0
8357 22:20:12.941064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8358 22:20:12.941148 ==
8359 22:20:12.943946 Write leveling (Byte 0): 25 => 25
8360 22:20:12.947243 Write leveling (Byte 1): 27 => 27
8361 22:20:12.947326 DramcWriteLeveling(PI) end<-----
8362 22:20:12.950456
8363 22:20:12.950538 ==
8364 22:20:12.954096 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 22:20:12.957394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 22:20:12.957478 ==
8367 22:20:12.960721 [Gating] SW mode calibration
8368 22:20:12.967340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8369 22:20:12.970464 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8370 22:20:12.977472 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 22:20:12.980551 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 22:20:12.983385 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 22:20:12.990255 1 4 12 | B1->B0 | 2a2a 3232 | 1 0 | (1 1) (0 0)
8374 22:20:12.993602 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 22:20:12.996744 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 22:20:13.003824 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 22:20:13.006853 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 22:20:13.010191 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 22:20:13.016754 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 22:20:13.019809 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8381 22:20:13.023307 1 5 12 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 1)
8382 22:20:13.030128 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8383 22:20:13.033132 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 22:20:13.036266 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 22:20:13.043066 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 22:20:13.046485 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 22:20:13.049764 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 22:20:13.056057 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
8389 22:20:13.059935 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8390 22:20:13.063505 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 22:20:13.070064 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 22:20:13.072932 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 22:20:13.075873 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 22:20:13.082643 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 22:20:13.085704 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 22:20:13.089135 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 22:20:13.095517 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8398 22:20:13.099312 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8399 22:20:13.102509 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 22:20:13.108788 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 22:20:13.111900 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 22:20:13.118484 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 22:20:13.121911 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 22:20:13.125625 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 22:20:13.132136 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 22:20:13.135286 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 22:20:13.138863 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 22:20:13.145236 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 22:20:13.148664 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 22:20:13.152075 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 22:20:13.154949 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 22:20:13.161396 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8413 22:20:13.164989 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 22:20:13.168438 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 22:20:13.171302 Total UI for P1: 0, mck2ui 16
8416 22:20:13.174679 best dqsien dly found for B0: ( 1, 9, 10)
8417 22:20:13.177973 Total UI for P1: 0, mck2ui 16
8418 22:20:13.181477 best dqsien dly found for B1: ( 1, 9, 12)
8419 22:20:13.184763 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8420 22:20:13.191184 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8421 22:20:13.191260
8422 22:20:13.194450 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8423 22:20:13.197762 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8424 22:20:13.201236 [Gating] SW calibration Done
8425 22:20:13.201310 ==
8426 22:20:13.204179 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 22:20:13.207875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 22:20:13.207958 ==
8429 22:20:13.211055 RX Vref Scan: 0
8430 22:20:13.211164
8431 22:20:13.211257 RX Vref 0 -> 0, step: 1
8432 22:20:13.211360
8433 22:20:13.214200 RX Delay 0 -> 252, step: 8
8434 22:20:13.217441 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8435 22:20:13.224408 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8436 22:20:13.227591 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8437 22:20:13.230814 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8438 22:20:13.234350 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8439 22:20:13.237224 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8440 22:20:13.243980 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8441 22:20:13.247365 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8442 22:20:13.250666 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8443 22:20:13.253788 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8444 22:20:13.257465 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8445 22:20:13.263823 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8446 22:20:13.267026 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8447 22:20:13.271118 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8448 22:20:13.274616 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8449 22:20:13.280186 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8450 22:20:13.280290 ==
8451 22:20:13.283914 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 22:20:13.287231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 22:20:13.287332 ==
8454 22:20:13.287422 DQS Delay:
8455 22:20:13.290630 DQS0 = 0, DQS1 = 0
8456 22:20:13.290725 DQM Delay:
8457 22:20:13.293964 DQM0 = 138, DQM1 = 130
8458 22:20:13.294063 DQ Delay:
8459 22:20:13.296835 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8460 22:20:13.299865 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8461 22:20:13.304057 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8462 22:20:13.306790 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8463 22:20:13.306864
8464 22:20:13.306926
8465 22:20:13.309735 ==
8466 22:20:13.313009 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 22:20:13.316411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 22:20:13.316508 ==
8469 22:20:13.316606
8470 22:20:13.316664
8471 22:20:13.319414 TX Vref Scan disable
8472 22:20:13.319484 == TX Byte 0 ==
8473 22:20:13.326422 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8474 22:20:13.329849 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8475 22:20:13.329953 == TX Byte 1 ==
8476 22:20:13.336091 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 22:20:13.339670 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 22:20:13.339772 ==
8479 22:20:13.343168 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 22:20:13.345911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 22:20:13.345984 ==
8482 22:20:13.359395
8483 22:20:13.362794 TX Vref early break, caculate TX vref
8484 22:20:13.366069 TX Vref=16, minBit 6, minWin=22, winSum=378
8485 22:20:13.369508 TX Vref=18, minBit 0, minWin=23, winSum=386
8486 22:20:13.372822 TX Vref=20, minBit 0, minWin=23, winSum=397
8487 22:20:13.376374 TX Vref=22, minBit 0, minWin=25, winSum=407
8488 22:20:13.378976 TX Vref=24, minBit 0, minWin=25, winSum=417
8489 22:20:13.385670 TX Vref=26, minBit 0, minWin=25, winSum=424
8490 22:20:13.389537 TX Vref=28, minBit 0, minWin=26, winSum=425
8491 22:20:13.392408 TX Vref=30, minBit 0, minWin=24, winSum=412
8492 22:20:13.395606 TX Vref=32, minBit 5, minWin=24, winSum=409
8493 22:20:13.398830 TX Vref=34, minBit 5, minWin=23, winSum=400
8494 22:20:13.405621 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8495 22:20:13.405700
8496 22:20:13.409039 Final TX Range 0 Vref 28
8497 22:20:13.409122
8498 22:20:13.409187 ==
8499 22:20:13.412214 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 22:20:13.415628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 22:20:13.415734 ==
8502 22:20:13.415825
8503 22:20:13.415916
8504 22:20:13.418974 TX Vref Scan disable
8505 22:20:13.425492 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8506 22:20:13.425573 == TX Byte 0 ==
8507 22:20:13.429140 u2DelayCellOfst[0]=18 cells (5 PI)
8508 22:20:13.431931 u2DelayCellOfst[1]=11 cells (3 PI)
8509 22:20:13.434983 u2DelayCellOfst[2]=0 cells (0 PI)
8510 22:20:13.438602 u2DelayCellOfst[3]=7 cells (2 PI)
8511 22:20:13.442048 u2DelayCellOfst[4]=7 cells (2 PI)
8512 22:20:13.445019 u2DelayCellOfst[5]=22 cells (6 PI)
8513 22:20:13.448323 u2DelayCellOfst[6]=22 cells (6 PI)
8514 22:20:13.451835 u2DelayCellOfst[7]=3 cells (1 PI)
8515 22:20:13.455297 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8516 22:20:13.458411 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8517 22:20:13.461802 == TX Byte 1 ==
8518 22:20:13.465526 u2DelayCellOfst[8]=0 cells (0 PI)
8519 22:20:13.465602 u2DelayCellOfst[9]=3 cells (1 PI)
8520 22:20:13.468282 u2DelayCellOfst[10]=11 cells (3 PI)
8521 22:20:13.471349 u2DelayCellOfst[11]=3 cells (1 PI)
8522 22:20:13.475234 u2DelayCellOfst[12]=14 cells (4 PI)
8523 22:20:13.477974 u2DelayCellOfst[13]=18 cells (5 PI)
8524 22:20:13.482084 u2DelayCellOfst[14]=18 cells (5 PI)
8525 22:20:13.485014 u2DelayCellOfst[15]=18 cells (5 PI)
8526 22:20:13.488409 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8527 22:20:13.494774 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8528 22:20:13.494878 DramC Write-DBI on
8529 22:20:13.494972 ==
8530 22:20:13.498291 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 22:20:13.504730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 22:20:13.504834 ==
8533 22:20:13.504926
8534 22:20:13.505012
8535 22:20:13.505098 TX Vref Scan disable
8536 22:20:13.508454 == TX Byte 0 ==
8537 22:20:13.511728 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8538 22:20:13.515297 == TX Byte 1 ==
8539 22:20:13.518502 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8540 22:20:13.521870 DramC Write-DBI off
8541 22:20:13.521966
8542 22:20:13.522054 [DATLAT]
8543 22:20:13.522145 Freq=1600, CH1 RK0
8544 22:20:13.522230
8545 22:20:13.524915 DATLAT Default: 0xf
8546 22:20:13.528134 0, 0xFFFF, sum = 0
8547 22:20:13.528234 1, 0xFFFF, sum = 0
8548 22:20:13.531695 2, 0xFFFF, sum = 0
8549 22:20:13.531775 3, 0xFFFF, sum = 0
8550 22:20:13.534651 4, 0xFFFF, sum = 0
8551 22:20:13.534752 5, 0xFFFF, sum = 0
8552 22:20:13.538364 6, 0xFFFF, sum = 0
8553 22:20:13.538462 7, 0xFFFF, sum = 0
8554 22:20:13.541709 8, 0xFFFF, sum = 0
8555 22:20:13.541807 9, 0xFFFF, sum = 0
8556 22:20:13.544977 10, 0xFFFF, sum = 0
8557 22:20:13.545047 11, 0xFFFF, sum = 0
8558 22:20:13.548316 12, 0xFFFF, sum = 0
8559 22:20:13.548414 13, 0xFFFF, sum = 0
8560 22:20:13.551576 14, 0x0, sum = 1
8561 22:20:13.551673 15, 0x0, sum = 2
8562 22:20:13.554483 16, 0x0, sum = 3
8563 22:20:13.554553 17, 0x0, sum = 4
8564 22:20:13.557729 best_step = 15
8565 22:20:13.557819
8566 22:20:13.557877 ==
8567 22:20:13.561612 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 22:20:13.564726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 22:20:13.564801 ==
8570 22:20:13.568232 RX Vref Scan: 1
8571 22:20:13.568300
8572 22:20:13.568358 Set Vref Range= 24 -> 127
8573 22:20:13.568414
8574 22:20:13.571411 RX Vref 24 -> 127, step: 1
8575 22:20:13.571499
8576 22:20:13.574441 RX Delay 19 -> 252, step: 4
8577 22:20:13.574514
8578 22:20:13.578200 Set Vref, RX VrefLevel [Byte0]: 24
8579 22:20:13.581428 [Byte1]: 24
8580 22:20:13.581498
8581 22:20:13.584837 Set Vref, RX VrefLevel [Byte0]: 25
8582 22:20:13.587747 [Byte1]: 25
8583 22:20:13.591193
8584 22:20:13.591280 Set Vref, RX VrefLevel [Byte0]: 26
8585 22:20:13.594636 [Byte1]: 26
8586 22:20:13.598721
8587 22:20:13.598802 Set Vref, RX VrefLevel [Byte0]: 27
8588 22:20:13.601929 [Byte1]: 27
8589 22:20:13.606550
8590 22:20:13.606624 Set Vref, RX VrefLevel [Byte0]: 28
8591 22:20:13.609444 [Byte1]: 28
8592 22:20:13.614072
8593 22:20:13.614146 Set Vref, RX VrefLevel [Byte0]: 29
8594 22:20:13.617305 [Byte1]: 29
8595 22:20:13.621586
8596 22:20:13.621656 Set Vref, RX VrefLevel [Byte0]: 30
8597 22:20:13.624739 [Byte1]: 30
8598 22:20:13.629054
8599 22:20:13.629129 Set Vref, RX VrefLevel [Byte0]: 31
8600 22:20:13.632250 [Byte1]: 31
8601 22:20:13.636640
8602 22:20:13.636722 Set Vref, RX VrefLevel [Byte0]: 32
8603 22:20:13.639959 [Byte1]: 32
8604 22:20:13.644386
8605 22:20:13.644462 Set Vref, RX VrefLevel [Byte0]: 33
8606 22:20:13.647672 [Byte1]: 33
8607 22:20:13.651581
8608 22:20:13.651651 Set Vref, RX VrefLevel [Byte0]: 34
8609 22:20:13.655239 [Byte1]: 34
8610 22:20:13.659612
8611 22:20:13.659681 Set Vref, RX VrefLevel [Byte0]: 35
8612 22:20:13.663004 [Byte1]: 35
8613 22:20:13.666915
8614 22:20:13.667022 Set Vref, RX VrefLevel [Byte0]: 36
8615 22:20:13.670794 [Byte1]: 36
8616 22:20:13.674253
8617 22:20:13.674351 Set Vref, RX VrefLevel [Byte0]: 37
8618 22:20:13.677961 [Byte1]: 37
8619 22:20:13.681855
8620 22:20:13.681953 Set Vref, RX VrefLevel [Byte0]: 38
8621 22:20:13.685351 [Byte1]: 38
8622 22:20:13.689810
8623 22:20:13.689907 Set Vref, RX VrefLevel [Byte0]: 39
8624 22:20:13.692716 [Byte1]: 39
8625 22:20:13.697449
8626 22:20:13.697521 Set Vref, RX VrefLevel [Byte0]: 40
8627 22:20:13.700519 [Byte1]: 40
8628 22:20:13.704977
8629 22:20:13.705074 Set Vref, RX VrefLevel [Byte0]: 41
8630 22:20:13.708345 [Byte1]: 41
8631 22:20:13.712481
8632 22:20:13.712597 Set Vref, RX VrefLevel [Byte0]: 42
8633 22:20:13.715480 [Byte1]: 42
8634 22:20:13.719744
8635 22:20:13.719814 Set Vref, RX VrefLevel [Byte0]: 43
8636 22:20:13.723410 [Byte1]: 43
8637 22:20:13.727422
8638 22:20:13.727530 Set Vref, RX VrefLevel [Byte0]: 44
8639 22:20:13.730819 [Byte1]: 44
8640 22:20:13.735014
8641 22:20:13.735118 Set Vref, RX VrefLevel [Byte0]: 45
8642 22:20:13.738927 [Byte1]: 45
8643 22:20:13.742854
8644 22:20:13.742925 Set Vref, RX VrefLevel [Byte0]: 46
8645 22:20:13.745844 [Byte1]: 46
8646 22:20:13.749965
8647 22:20:13.750040 Set Vref, RX VrefLevel [Byte0]: 47
8648 22:20:13.753337 [Byte1]: 47
8649 22:20:13.757951
8650 22:20:13.758021 Set Vref, RX VrefLevel [Byte0]: 48
8651 22:20:13.761367 [Byte1]: 48
8652 22:20:13.765297
8653 22:20:13.765370 Set Vref, RX VrefLevel [Byte0]: 49
8654 22:20:13.768683 [Byte1]: 49
8655 22:20:13.772673
8656 22:20:13.772772 Set Vref, RX VrefLevel [Byte0]: 50
8657 22:20:13.776006 [Byte1]: 50
8658 22:20:13.780510
8659 22:20:13.780603 Set Vref, RX VrefLevel [Byte0]: 51
8660 22:20:13.784098 [Byte1]: 51
8661 22:20:13.788209
8662 22:20:13.788283 Set Vref, RX VrefLevel [Byte0]: 52
8663 22:20:13.791490 [Byte1]: 52
8664 22:20:13.795941
8665 22:20:13.796032 Set Vref, RX VrefLevel [Byte0]: 53
8666 22:20:13.798716 [Byte1]: 53
8667 22:20:13.803322
8668 22:20:13.803421 Set Vref, RX VrefLevel [Byte0]: 54
8669 22:20:13.806635 [Byte1]: 54
8670 22:20:13.810726
8671 22:20:13.810797 Set Vref, RX VrefLevel [Byte0]: 55
8672 22:20:13.813830 [Byte1]: 55
8673 22:20:13.818201
8674 22:20:13.821448 Set Vref, RX VrefLevel [Byte0]: 56
8675 22:20:13.824733 [Byte1]: 56
8676 22:20:13.824808
8677 22:20:13.827875 Set Vref, RX VrefLevel [Byte0]: 57
8678 22:20:13.831863 [Byte1]: 57
8679 22:20:13.831934
8680 22:20:13.834662 Set Vref, RX VrefLevel [Byte0]: 58
8681 22:20:13.837944 [Byte1]: 58
8682 22:20:13.838014
8683 22:20:13.841544 Set Vref, RX VrefLevel [Byte0]: 59
8684 22:20:13.844692 [Byte1]: 59
8685 22:20:13.848544
8686 22:20:13.848632 Set Vref, RX VrefLevel [Byte0]: 60
8687 22:20:13.852322 [Byte1]: 60
8688 22:20:13.856426
8689 22:20:13.856495 Set Vref, RX VrefLevel [Byte0]: 61
8690 22:20:13.859586 [Byte1]: 61
8691 22:20:13.863748
8692 22:20:13.863829 Set Vref, RX VrefLevel [Byte0]: 62
8693 22:20:13.866889 [Byte1]: 62
8694 22:20:13.871518
8695 22:20:13.871604 Set Vref, RX VrefLevel [Byte0]: 63
8696 22:20:13.874461 [Byte1]: 63
8697 22:20:13.878797
8698 22:20:13.878880 Set Vref, RX VrefLevel [Byte0]: 64
8699 22:20:13.882098 [Byte1]: 64
8700 22:20:13.886608
8701 22:20:13.886689 Set Vref, RX VrefLevel [Byte0]: 65
8702 22:20:13.889829 [Byte1]: 65
8703 22:20:13.894199
8704 22:20:13.894302 Set Vref, RX VrefLevel [Byte0]: 66
8705 22:20:13.898180 [Byte1]: 66
8706 22:20:13.901982
8707 22:20:13.902053 Set Vref, RX VrefLevel [Byte0]: 67
8708 22:20:13.905057 [Byte1]: 67
8709 22:20:13.909387
8710 22:20:13.909460 Set Vref, RX VrefLevel [Byte0]: 68
8711 22:20:13.912420 [Byte1]: 68
8712 22:20:13.916713
8713 22:20:13.916794 Set Vref, RX VrefLevel [Byte0]: 69
8714 22:20:13.920097 [Byte1]: 69
8715 22:20:13.924668
8716 22:20:13.924750 Set Vref, RX VrefLevel [Byte0]: 70
8717 22:20:13.927566 [Byte1]: 70
8718 22:20:13.932048
8719 22:20:13.932140 Set Vref, RX VrefLevel [Byte0]: 71
8720 22:20:13.935486 [Byte1]: 71
8721 22:20:13.939370
8722 22:20:13.939457 Set Vref, RX VrefLevel [Byte0]: 72
8723 22:20:13.942977 [Byte1]: 72
8724 22:20:13.947635
8725 22:20:13.947717 Set Vref, RX VrefLevel [Byte0]: 73
8726 22:20:13.950239 [Byte1]: 73
8727 22:20:13.954700
8728 22:20:13.954785 Set Vref, RX VrefLevel [Byte0]: 74
8729 22:20:13.957884 [Byte1]: 74
8730 22:20:13.962159
8731 22:20:13.962240 Set Vref, RX VrefLevel [Byte0]: 75
8732 22:20:13.965413 [Byte1]: 75
8733 22:20:13.969941
8734 22:20:13.970042 Final RX Vref Byte 0 = 53 to rank0
8735 22:20:13.972906 Final RX Vref Byte 1 = 58 to rank0
8736 22:20:13.976076 Final RX Vref Byte 0 = 53 to rank1
8737 22:20:13.980006 Final RX Vref Byte 1 = 58 to rank1==
8738 22:20:13.983066 Dram Type= 6, Freq= 0, CH_1, rank 0
8739 22:20:13.989472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 22:20:13.989548 ==
8741 22:20:13.989610 DQS Delay:
8742 22:20:13.992821 DQS0 = 0, DQS1 = 0
8743 22:20:13.992904 DQM Delay:
8744 22:20:13.992969 DQM0 = 135, DQM1 = 129
8745 22:20:13.996475 DQ Delay:
8746 22:20:13.999388 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8747 22:20:14.002470 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8748 22:20:14.005947 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =118
8749 22:20:14.009556 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8750 22:20:14.009639
8751 22:20:14.009704
8752 22:20:14.009774
8753 22:20:14.012922 [DramC_TX_OE_Calibration] TA2
8754 22:20:14.016218 Original DQ_B0 (3 6) =30, OEN = 27
8755 22:20:14.019168 Original DQ_B1 (3 6) =30, OEN = 27
8756 22:20:14.022587 24, 0x0, End_B0=24 End_B1=24
8757 22:20:14.026054 25, 0x0, End_B0=25 End_B1=25
8758 22:20:14.026143 26, 0x0, End_B0=26 End_B1=26
8759 22:20:14.029352 27, 0x0, End_B0=27 End_B1=27
8760 22:20:14.032389 28, 0x0, End_B0=28 End_B1=28
8761 22:20:14.035846 29, 0x0, End_B0=29 End_B1=29
8762 22:20:14.035930 30, 0x0, End_B0=30 End_B1=30
8763 22:20:14.039020 31, 0x4141, End_B0=30 End_B1=30
8764 22:20:14.042531 Byte0 end_step=30 best_step=27
8765 22:20:14.045520 Byte1 end_step=30 best_step=27
8766 22:20:14.049031 Byte0 TX OE(2T, 0.5T) = (3, 3)
8767 22:20:14.052214 Byte1 TX OE(2T, 0.5T) = (3, 3)
8768 22:20:14.052297
8769 22:20:14.052362
8770 22:20:14.058927 [DQSOSCAuto] RK0, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8771 22:20:14.062141 CH1 RK0: MR19=303, MR18=190E
8772 22:20:14.068546 CH1_RK0: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8773 22:20:14.068643
8774 22:20:14.071917 ----->DramcWriteLeveling(PI) begin...
8775 22:20:14.072008 ==
8776 22:20:14.075594 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 22:20:14.079054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 22:20:14.079137 ==
8779 22:20:14.081941 Write leveling (Byte 0): 26 => 26
8780 22:20:14.085287 Write leveling (Byte 1): 27 => 27
8781 22:20:14.088523 DramcWriteLeveling(PI) end<-----
8782 22:20:14.088606
8783 22:20:14.088676 ==
8784 22:20:14.092023 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 22:20:14.095423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 22:20:14.098568 ==
8787 22:20:14.098655 [Gating] SW mode calibration
8788 22:20:14.108574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8789 22:20:14.111741 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8790 22:20:14.115239 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 22:20:14.121762 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 22:20:14.125192 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8793 22:20:14.128205 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8794 22:20:14.135070 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8795 22:20:14.137950 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 22:20:14.141740 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 22:20:14.148111 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 22:20:14.151504 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 22:20:14.154521 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 22:20:14.161150 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8801 22:20:14.164373 1 5 12 | B1->B0 | 2a2a 3434 | 0 0 | (1 0) (0 1)
8802 22:20:14.167640 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8803 22:20:14.174928 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 22:20:14.177909 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 22:20:14.180989 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 22:20:14.188139 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 22:20:14.191105 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 22:20:14.194875 1 6 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8809 22:20:14.200804 1 6 12 | B1->B0 | 4646 3232 | 0 0 | (0 0) (0 0)
8810 22:20:14.203944 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 22:20:14.207417 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 22:20:14.214143 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 22:20:14.217429 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 22:20:14.220399 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 22:20:14.227494 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 22:20:14.230588 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8817 22:20:14.233694 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8818 22:20:14.240411 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8819 22:20:14.243509 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 22:20:14.247214 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 22:20:14.253531 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 22:20:14.257464 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 22:20:14.260169 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 22:20:14.267040 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 22:20:14.270197 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 22:20:14.273300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 22:20:14.280166 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 22:20:14.283126 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 22:20:14.286345 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 22:20:14.292956 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 22:20:14.296437 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 22:20:14.299740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8833 22:20:14.306113 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8834 22:20:14.309366 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 22:20:14.312819 Total UI for P1: 0, mck2ui 16
8836 22:20:14.316553 best dqsien dly found for B0: ( 1, 9, 10)
8837 22:20:14.319338 Total UI for P1: 0, mck2ui 16
8838 22:20:14.322698 best dqsien dly found for B1: ( 1, 9, 10)
8839 22:20:14.326151 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8840 22:20:14.329567 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8841 22:20:14.329642
8842 22:20:14.333017 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8843 22:20:14.339102 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8844 22:20:14.339181 [Gating] SW calibration Done
8845 22:20:14.339257 ==
8846 22:20:14.342677 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 22:20:14.349306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 22:20:14.349379 ==
8849 22:20:14.349450 RX Vref Scan: 0
8850 22:20:14.349512
8851 22:20:14.352285 RX Vref 0 -> 0, step: 1
8852 22:20:14.352359
8853 22:20:14.355921 RX Delay 0 -> 252, step: 8
8854 22:20:14.359181 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8855 22:20:14.362181 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8856 22:20:14.365860 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8857 22:20:14.368810 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8858 22:20:14.375409 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8859 22:20:14.378759 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8860 22:20:14.382271 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8861 22:20:14.385224 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8862 22:20:14.388607 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8863 22:20:14.395360 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8864 22:20:14.399190 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8865 22:20:14.402170 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8866 22:20:14.405844 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8867 22:20:14.412016 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8868 22:20:14.415135 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8869 22:20:14.418101 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8870 22:20:14.418177 ==
8871 22:20:14.422630 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 22:20:14.425292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 22:20:14.425373 ==
8874 22:20:14.428462 DQS Delay:
8875 22:20:14.428551 DQS0 = 0, DQS1 = 0
8876 22:20:14.431713 DQM Delay:
8877 22:20:14.431779 DQM0 = 137, DQM1 = 129
8878 22:20:14.435278 DQ Delay:
8879 22:20:14.438240 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8880 22:20:14.441479 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8881 22:20:14.444987 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8882 22:20:14.447861 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8883 22:20:14.447933
8884 22:20:14.447995
8885 22:20:14.448063 ==
8886 22:20:14.451445 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 22:20:14.454707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 22:20:14.454789 ==
8889 22:20:14.454851
8890 22:20:14.457984
8891 22:20:14.458092 TX Vref Scan disable
8892 22:20:14.461478 == TX Byte 0 ==
8893 22:20:14.464433 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8894 22:20:14.468089 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8895 22:20:14.471347 == TX Byte 1 ==
8896 22:20:14.474799 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8897 22:20:14.477668 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8898 22:20:14.477749 ==
8899 22:20:14.481103 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 22:20:14.488028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 22:20:14.488104 ==
8902 22:20:14.500896
8903 22:20:14.504076 TX Vref early break, caculate TX vref
8904 22:20:14.507093 TX Vref=16, minBit 1, minWin=23, winSum=387
8905 22:20:14.510702 TX Vref=18, minBit 1, minWin=23, winSum=396
8906 22:20:14.513966 TX Vref=20, minBit 0, minWin=24, winSum=407
8907 22:20:14.516878 TX Vref=22, minBit 8, minWin=24, winSum=415
8908 22:20:14.520409 TX Vref=24, minBit 1, minWin=25, winSum=420
8909 22:20:14.527207 TX Vref=26, minBit 3, minWin=26, winSum=426
8910 22:20:14.530774 TX Vref=28, minBit 0, minWin=25, winSum=425
8911 22:20:14.534244 TX Vref=30, minBit 3, minWin=25, winSum=423
8912 22:20:14.536916 TX Vref=32, minBit 0, minWin=25, winSum=410
8913 22:20:14.540125 TX Vref=34, minBit 0, minWin=24, winSum=404
8914 22:20:14.543344 TX Vref=36, minBit 0, minWin=23, winSum=393
8915 22:20:14.550322 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 26
8916 22:20:14.550400
8917 22:20:14.554112 Final TX Range 0 Vref 26
8918 22:20:14.554185
8919 22:20:14.554266 ==
8920 22:20:14.556805 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 22:20:14.559910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 22:20:14.559982 ==
8923 22:20:14.560060
8924 22:20:14.563412
8925 22:20:14.563489 TX Vref Scan disable
8926 22:20:14.569740 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8927 22:20:14.569816 == TX Byte 0 ==
8928 22:20:14.573269 u2DelayCellOfst[0]=22 cells (6 PI)
8929 22:20:14.577014 u2DelayCellOfst[1]=14 cells (4 PI)
8930 22:20:14.579815 u2DelayCellOfst[2]=0 cells (0 PI)
8931 22:20:14.583127 u2DelayCellOfst[3]=11 cells (3 PI)
8932 22:20:14.586828 u2DelayCellOfst[4]=11 cells (3 PI)
8933 22:20:14.589977 u2DelayCellOfst[5]=22 cells (6 PI)
8934 22:20:14.592989 u2DelayCellOfst[6]=22 cells (6 PI)
8935 22:20:14.596077 u2DelayCellOfst[7]=7 cells (2 PI)
8936 22:20:14.599706 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8937 22:20:14.602789 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8938 22:20:14.606361 == TX Byte 1 ==
8939 22:20:14.609650 u2DelayCellOfst[8]=0 cells (0 PI)
8940 22:20:14.612758 u2DelayCellOfst[9]=3 cells (1 PI)
8941 22:20:14.616338 u2DelayCellOfst[10]=11 cells (3 PI)
8942 22:20:14.619483 u2DelayCellOfst[11]=7 cells (2 PI)
8943 22:20:14.622594 u2DelayCellOfst[12]=14 cells (4 PI)
8944 22:20:14.626086 u2DelayCellOfst[13]=18 cells (5 PI)
8945 22:20:14.626170 u2DelayCellOfst[14]=18 cells (5 PI)
8946 22:20:14.629815 u2DelayCellOfst[15]=18 cells (5 PI)
8947 22:20:14.635832 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8948 22:20:14.639184 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8949 22:20:14.642442 DramC Write-DBI on
8950 22:20:14.642523 ==
8951 22:20:14.645670 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 22:20:14.649793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 22:20:14.649875 ==
8954 22:20:14.649939
8955 22:20:14.649998
8956 22:20:14.652399 TX Vref Scan disable
8957 22:20:14.652505 == TX Byte 0 ==
8958 22:20:14.659037 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8959 22:20:14.659119 == TX Byte 1 ==
8960 22:20:14.662522 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8961 22:20:14.665384 DramC Write-DBI off
8962 22:20:14.665464
8963 22:20:14.665527 [DATLAT]
8964 22:20:14.668682 Freq=1600, CH1 RK1
8965 22:20:14.668762
8966 22:20:14.668825 DATLAT Default: 0xf
8967 22:20:14.672135 0, 0xFFFF, sum = 0
8968 22:20:14.672217 1, 0xFFFF, sum = 0
8969 22:20:14.675360 2, 0xFFFF, sum = 0
8970 22:20:14.675442 3, 0xFFFF, sum = 0
8971 22:20:14.679059 4, 0xFFFF, sum = 0
8972 22:20:14.682341 5, 0xFFFF, sum = 0
8973 22:20:14.682423 6, 0xFFFF, sum = 0
8974 22:20:14.685767 7, 0xFFFF, sum = 0
8975 22:20:14.685849 8, 0xFFFF, sum = 0
8976 22:20:14.689160 9, 0xFFFF, sum = 0
8977 22:20:14.689241 10, 0xFFFF, sum = 0
8978 22:20:14.692181 11, 0xFFFF, sum = 0
8979 22:20:14.692263 12, 0xFFFF, sum = 0
8980 22:20:14.695577 13, 0xFFFF, sum = 0
8981 22:20:14.695659 14, 0x0, sum = 1
8982 22:20:14.698626 15, 0x0, sum = 2
8983 22:20:14.698737 16, 0x0, sum = 3
8984 22:20:14.701820 17, 0x0, sum = 4
8985 22:20:14.701929 best_step = 15
8986 22:20:14.702020
8987 22:20:14.702110 ==
8988 22:20:14.705122 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 22:20:14.708749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 22:20:14.712123 ==
8991 22:20:14.712219 RX Vref Scan: 0
8992 22:20:14.712306
8993 22:20:14.715170 RX Vref 0 -> 0, step: 1
8994 22:20:14.715238
8995 22:20:14.718191 RX Delay 11 -> 252, step: 4
8996 22:20:14.722058 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
8997 22:20:14.724988 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
8998 22:20:14.728506 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
8999 22:20:14.735816 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9000 22:20:14.738018 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9001 22:20:14.742058 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9002 22:20:14.744757 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9003 22:20:14.748281 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9004 22:20:14.754686 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9005 22:20:14.758115 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9006 22:20:14.761567 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9007 22:20:14.765040 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9008 22:20:14.768229 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9009 22:20:14.775147 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9010 22:20:14.778493 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9011 22:20:14.781164 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9012 22:20:14.781248 ==
9013 22:20:14.785031 Dram Type= 6, Freq= 0, CH_1, rank 1
9014 22:20:14.787793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9015 22:20:14.790971 ==
9016 22:20:14.791078 DQS Delay:
9017 22:20:14.791180 DQS0 = 0, DQS1 = 0
9018 22:20:14.794446 DQM Delay:
9019 22:20:14.794526 DQM0 = 134, DQM1 = 126
9020 22:20:14.797724 DQ Delay:
9021 22:20:14.801117 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9022 22:20:14.804538 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =130
9023 22:20:14.807941 DQ8 =114, DQ9 =116, DQ10 =126, DQ11 =116
9024 22:20:14.811119 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9025 22:20:14.811208
9026 22:20:14.811309
9027 22:20:14.811368
9028 22:20:14.814249 [DramC_TX_OE_Calibration] TA2
9029 22:20:14.817766 Original DQ_B0 (3 6) =30, OEN = 27
9030 22:20:14.820891 Original DQ_B1 (3 6) =30, OEN = 27
9031 22:20:14.824272 24, 0x0, End_B0=24 End_B1=24
9032 22:20:14.824355 25, 0x0, End_B0=25 End_B1=25
9033 22:20:14.827988 26, 0x0, End_B0=26 End_B1=26
9034 22:20:14.830690 27, 0x0, End_B0=27 End_B1=27
9035 22:20:14.834030 28, 0x0, End_B0=28 End_B1=28
9036 22:20:14.834140 29, 0x0, End_B0=29 End_B1=29
9037 22:20:14.837371 30, 0x0, End_B0=30 End_B1=30
9038 22:20:14.840742 31, 0x4141, End_B0=30 End_B1=30
9039 22:20:14.844295 Byte0 end_step=30 best_step=27
9040 22:20:14.847434 Byte1 end_step=30 best_step=27
9041 22:20:14.851343 Byte0 TX OE(2T, 0.5T) = (3, 3)
9042 22:20:14.854282 Byte1 TX OE(2T, 0.5T) = (3, 3)
9043 22:20:14.854362
9044 22:20:14.854426
9045 22:20:14.860357 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9046 22:20:14.864224 CH1 RK1: MR19=303, MR18=D09
9047 22:20:14.870432 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9048 22:20:14.874418 [RxdqsGatingPostProcess] freq 1600
9049 22:20:14.877405 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9050 22:20:14.880706 best DQS0 dly(2T, 0.5T) = (1, 1)
9051 22:20:14.883452 best DQS1 dly(2T, 0.5T) = (1, 1)
9052 22:20:14.886746 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9053 22:20:14.890042 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9054 22:20:14.893422 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 22:20:14.897151 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 22:20:14.900718 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 22:20:14.903526 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 22:20:14.907021 Pre-setting of DQS Precalculation
9059 22:20:14.910037 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9060 22:20:14.916827 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9061 22:20:14.926282 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9062 22:20:14.926365
9063 22:20:14.926429
9064 22:20:14.926489 [Calibration Summary] 3200 Mbps
9065 22:20:14.930122 CH 0, Rank 0
9066 22:20:14.932962 SW Impedance : PASS
9067 22:20:14.933042 DUTY Scan : NO K
9068 22:20:14.936714 ZQ Calibration : PASS
9069 22:20:14.936794 Jitter Meter : NO K
9070 22:20:14.939825 CBT Training : PASS
9071 22:20:14.942876 Write leveling : PASS
9072 22:20:14.942957 RX DQS gating : PASS
9073 22:20:14.946205 RX DQ/DQS(RDDQC) : PASS
9074 22:20:14.949603 TX DQ/DQS : PASS
9075 22:20:14.949685 RX DATLAT : PASS
9076 22:20:14.952876 RX DQ/DQS(Engine): PASS
9077 22:20:14.956356 TX OE : PASS
9078 22:20:14.956463 All Pass.
9079 22:20:14.956583
9080 22:20:14.956645 CH 0, Rank 1
9081 22:20:14.959452 SW Impedance : PASS
9082 22:20:14.962915 DUTY Scan : NO K
9083 22:20:14.962996 ZQ Calibration : PASS
9084 22:20:14.966060 Jitter Meter : NO K
9085 22:20:14.969529 CBT Training : PASS
9086 22:20:14.969610 Write leveling : PASS
9087 22:20:14.972961 RX DQS gating : PASS
9088 22:20:14.975950 RX DQ/DQS(RDDQC) : PASS
9089 22:20:14.976031 TX DQ/DQS : PASS
9090 22:20:14.979529 RX DATLAT : PASS
9091 22:20:14.983045 RX DQ/DQS(Engine): PASS
9092 22:20:14.983126 TX OE : PASS
9093 22:20:14.985609 All Pass.
9094 22:20:14.985690
9095 22:20:14.985752 CH 1, Rank 0
9096 22:20:14.989025 SW Impedance : PASS
9097 22:20:14.989107 DUTY Scan : NO K
9098 22:20:14.992758 ZQ Calibration : PASS
9099 22:20:14.995881 Jitter Meter : NO K
9100 22:20:14.995963 CBT Training : PASS
9101 22:20:14.998819 Write leveling : PASS
9102 22:20:15.002096 RX DQS gating : PASS
9103 22:20:15.002177 RX DQ/DQS(RDDQC) : PASS
9104 22:20:15.005734 TX DQ/DQS : PASS
9105 22:20:15.008969 RX DATLAT : PASS
9106 22:20:15.009049 RX DQ/DQS(Engine): PASS
9107 22:20:15.012106 TX OE : PASS
9108 22:20:15.012187 All Pass.
9109 22:20:15.012251
9110 22:20:15.015546 CH 1, Rank 1
9111 22:20:15.015627 SW Impedance : PASS
9112 22:20:15.018539 DUTY Scan : NO K
9113 22:20:15.018620 ZQ Calibration : PASS
9114 22:20:15.022027 Jitter Meter : NO K
9115 22:20:15.025327 CBT Training : PASS
9116 22:20:15.025414 Write leveling : PASS
9117 22:20:15.029159 RX DQS gating : PASS
9118 22:20:15.031879 RX DQ/DQS(RDDQC) : PASS
9119 22:20:15.031966 TX DQ/DQS : PASS
9120 22:20:15.035547 RX DATLAT : PASS
9121 22:20:15.038431 RX DQ/DQS(Engine): PASS
9122 22:20:15.038512 TX OE : PASS
9123 22:20:15.041751 All Pass.
9124 22:20:15.041832
9125 22:20:15.041896 DramC Write-DBI on
9126 22:20:15.045496 PER_BANK_REFRESH: Hybrid Mode
9127 22:20:15.045578 TX_TRACKING: ON
9128 22:20:15.055437 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9129 22:20:15.065007 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9130 22:20:15.071742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 22:20:15.075043 [FAST_K] Save calibration result to emmc
9132 22:20:15.078237 sync common calibartion params.
9133 22:20:15.078319 sync cbt_mode0:1, 1:1
9134 22:20:15.081395 dram_init: ddr_geometry: 2
9135 22:20:15.084962 dram_init: ddr_geometry: 2
9136 22:20:15.085082 dram_init: ddr_geometry: 2
9137 22:20:15.088077 0:dram_rank_size:100000000
9138 22:20:15.091862 1:dram_rank_size:100000000
9139 22:20:15.098235 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9140 22:20:15.098318 DFS_SHUFFLE_HW_MODE: ON
9141 22:20:15.101224 dramc_set_vcore_voltage set vcore to 725000
9142 22:20:15.104873 Read voltage for 1600, 0
9143 22:20:15.104954 Vio18 = 0
9144 22:20:15.108270 Vcore = 725000
9145 22:20:15.108350 Vdram = 0
9146 22:20:15.108413 Vddq = 0
9147 22:20:15.111428 Vmddr = 0
9148 22:20:15.111509 switch to 3200 Mbps bootup
9149 22:20:15.114783 [DramcRunTimeConfig]
9150 22:20:15.114864 PHYPLL
9151 22:20:15.117998 DPM_CONTROL_AFTERK: ON
9152 22:20:15.118079 PER_BANK_REFRESH: ON
9153 22:20:15.121307 REFRESH_OVERHEAD_REDUCTION: ON
9154 22:20:15.124680 CMD_PICG_NEW_MODE: OFF
9155 22:20:15.124763 XRTWTW_NEW_MODE: ON
9156 22:20:15.127943 XRTRTR_NEW_MODE: ON
9157 22:20:15.128025 TX_TRACKING: ON
9158 22:20:15.131663 RDSEL_TRACKING: OFF
9159 22:20:15.134864 DQS Precalculation for DVFS: ON
9160 22:20:15.134946 RX_TRACKING: OFF
9161 22:20:15.138326 HW_GATING DBG: ON
9162 22:20:15.138407 ZQCS_ENABLE_LP4: ON
9163 22:20:15.140789 RX_PICG_NEW_MODE: ON
9164 22:20:15.140870 TX_PICG_NEW_MODE: ON
9165 22:20:15.144410 ENABLE_RX_DCM_DPHY: ON
9166 22:20:15.148015 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9167 22:20:15.150879 DUMMY_READ_FOR_TRACKING: OFF
9168 22:20:15.154441 !!! SPM_CONTROL_AFTERK: OFF
9169 22:20:15.154531 !!! SPM could not control APHY
9170 22:20:15.157400 IMPEDANCE_TRACKING: ON
9171 22:20:15.157481 TEMP_SENSOR: ON
9172 22:20:15.160990 HW_SAVE_FOR_SR: OFF
9173 22:20:15.164319 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9174 22:20:15.167353 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9175 22:20:15.170544 Read ODT Tracking: ON
9176 22:20:15.170624 Refresh Rate DeBounce: ON
9177 22:20:15.173750 DFS_NO_QUEUE_FLUSH: ON
9178 22:20:15.177225 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9179 22:20:15.180607 ENABLE_DFS_RUNTIME_MRW: OFF
9180 22:20:15.180703 DDR_RESERVE_NEW_MODE: ON
9181 22:20:15.184046 MR_CBT_SWITCH_FREQ: ON
9182 22:20:15.187312 =========================
9183 22:20:15.205083 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9184 22:20:15.208692 dram_init: ddr_geometry: 2
9185 22:20:15.226965 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9186 22:20:15.230547 dram_init: dram init end (result: 0)
9187 22:20:15.237023 DRAM-K: Full calibration passed in 24595 msecs
9188 22:20:15.239856 MRC: failed to locate region type 0.
9189 22:20:15.239938 DRAM rank0 size:0x100000000,
9190 22:20:15.243147 DRAM rank1 size=0x100000000
9191 22:20:15.253444 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9192 22:20:15.259382 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9193 22:20:15.269199 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9194 22:20:15.276014 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9195 22:20:15.276097 DRAM rank0 size:0x100000000,
9196 22:20:15.279551 DRAM rank1 size=0x100000000
9197 22:20:15.279632 CBMEM:
9198 22:20:15.282735 IMD: root @ 0xfffff000 254 entries.
9199 22:20:15.285692 IMD: root @ 0xffffec00 62 entries.
9200 22:20:15.292429 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9201 22:20:15.296234 WARNING: RO_VPD is uninitialized or empty.
9202 22:20:15.299231 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9203 22:20:15.309872 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9204 22:20:15.319461 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9205 22:20:15.330877 BS: romstage times (exec / console): total (unknown) / 24093 ms
9206 22:20:15.330995
9207 22:20:15.331091
9208 22:20:15.340828 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9209 22:20:15.343957 ARM64: Exception handlers installed.
9210 22:20:15.347652 ARM64: Testing exception
9211 22:20:15.350866 ARM64: Done test exception
9212 22:20:15.350968 Enumerating buses...
9213 22:20:15.354130 Show all devs... Before device enumeration.
9214 22:20:15.357260 Root Device: enabled 1
9215 22:20:15.361095 CPU_CLUSTER: 0: enabled 1
9216 22:20:15.361179 CPU: 00: enabled 1
9217 22:20:15.364231 Compare with tree...
9218 22:20:15.364330 Root Device: enabled 1
9219 22:20:15.367608 CPU_CLUSTER: 0: enabled 1
9220 22:20:15.370710 CPU: 00: enabled 1
9221 22:20:15.370810 Root Device scanning...
9222 22:20:15.373888 scan_static_bus for Root Device
9223 22:20:15.377334 CPU_CLUSTER: 0 enabled
9224 22:20:15.380507 scan_static_bus for Root Device done
9225 22:20:15.384044 scan_bus: bus Root Device finished in 8 msecs
9226 22:20:15.384141 done
9227 22:20:15.391045 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9228 22:20:15.393689 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9229 22:20:15.400328 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9230 22:20:15.403708 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9231 22:20:15.406817 Allocating resources...
9232 22:20:15.410203 Reading resources...
9233 22:20:15.413296 Root Device read_resources bus 0 link: 0
9234 22:20:15.417010 DRAM rank0 size:0x100000000,
9235 22:20:15.417115 DRAM rank1 size=0x100000000
9236 22:20:15.420113 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9237 22:20:15.423270 CPU: 00 missing read_resources
9238 22:20:15.430200 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9239 22:20:15.433308 Root Device read_resources bus 0 link: 0 done
9240 22:20:15.433411 Done reading resources.
9241 22:20:15.440214 Show resources in subtree (Root Device)...After reading.
9242 22:20:15.443076 Root Device child on link 0 CPU_CLUSTER: 0
9243 22:20:15.446447 CPU_CLUSTER: 0 child on link 0 CPU: 00
9244 22:20:15.456277 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9245 22:20:15.456381 CPU: 00
9246 22:20:15.459755 Root Device assign_resources, bus 0 link: 0
9247 22:20:15.463155 CPU_CLUSTER: 0 missing set_resources
9248 22:20:15.469527 Root Device assign_resources, bus 0 link: 0 done
9249 22:20:15.469615 Done setting resources.
9250 22:20:15.475948 Show resources in subtree (Root Device)...After assigning values.
9251 22:20:15.479518 Root Device child on link 0 CPU_CLUSTER: 0
9252 22:20:15.483045 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 22:20:15.492598 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 22:20:15.492703 CPU: 00
9255 22:20:15.496211 Done allocating resources.
9256 22:20:15.502460 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9257 22:20:15.502543 Enabling resources...
9258 22:20:15.502608 done.
9259 22:20:15.509354 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9260 22:20:15.512411 Initializing devices...
9261 22:20:15.512491 Root Device init
9262 22:20:15.516000 init hardware done!
9263 22:20:15.516080 0x00000018: ctrlr->caps
9264 22:20:15.519214 52.000 MHz: ctrlr->f_max
9265 22:20:15.522417 0.400 MHz: ctrlr->f_min
9266 22:20:15.522500 0x40ff8080: ctrlr->voltages
9267 22:20:15.525871 sclk: 390625
9268 22:20:15.525952 Bus Width = 1
9269 22:20:15.526015 sclk: 390625
9270 22:20:15.529205 Bus Width = 1
9271 22:20:15.532390 Early init status = 3
9272 22:20:15.535545 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9273 22:20:15.539431 in-header: 03 fc 00 00 01 00 00 00
9274 22:20:15.542717 in-data: 00
9275 22:20:15.545536 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9276 22:20:15.551551 in-header: 03 fd 00 00 00 00 00 00
9277 22:20:15.554718 in-data:
9278 22:20:15.557627 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9279 22:20:15.561920 in-header: 03 fc 00 00 01 00 00 00
9280 22:20:15.564624 in-data: 00
9281 22:20:15.568010 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9282 22:20:15.572493 in-header: 03 fd 00 00 00 00 00 00
9283 22:20:15.575816 in-data:
9284 22:20:15.579675 [SSUSB] Setting up USB HOST controller...
9285 22:20:15.582338 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9286 22:20:15.585794 [SSUSB] phy power-on done.
9287 22:20:15.589524 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9288 22:20:15.596352 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9289 22:20:15.598802 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9290 22:20:15.605428 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9291 22:20:15.612140 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9292 22:20:15.618990 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9293 22:20:15.625456 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9294 22:20:15.631960 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9295 22:20:15.635330 SPM: binary array size = 0x9dc
9296 22:20:15.638567 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9297 22:20:15.645283 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9298 22:20:15.651825 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9299 22:20:15.658416 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9300 22:20:15.661777 configure_display: Starting display init
9301 22:20:15.696301 anx7625_power_on_init: Init interface.
9302 22:20:15.699524 anx7625_disable_pd_protocol: Disabled PD feature.
9303 22:20:15.702693 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9304 22:20:15.730006 anx7625_start_dp_work: Secure OCM version=00
9305 22:20:15.733638 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9306 22:20:15.748783 sp_tx_get_edid_block: EDID Block = 1
9307 22:20:15.851348 Extracted contents:
9308 22:20:15.854482 header: 00 ff ff ff ff ff ff 00
9309 22:20:15.857510 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9310 22:20:15.861201 version: 01 04
9311 22:20:15.864022 basic params: 95 1f 11 78 0a
9312 22:20:15.867337 chroma info: 76 90 94 55 54 90 27 21 50 54
9313 22:20:15.870782 established: 00 00 00
9314 22:20:15.877603 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9315 22:20:15.881472 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9316 22:20:15.887136 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9317 22:20:15.893892 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9318 22:20:15.900870 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9319 22:20:15.904279 extensions: 00
9320 22:20:15.904360 checksum: fb
9321 22:20:15.904424
9322 22:20:15.907066 Manufacturer: IVO Model 57d Serial Number 0
9323 22:20:15.910652 Made week 0 of 2020
9324 22:20:15.913914 EDID version: 1.4
9325 22:20:15.913994 Digital display
9326 22:20:15.917030 6 bits per primary color channel
9327 22:20:15.917112 DisplayPort interface
9328 22:20:15.920223 Maximum image size: 31 cm x 17 cm
9329 22:20:15.923443 Gamma: 220%
9330 22:20:15.923522 Check DPMS levels
9331 22:20:15.930324 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9332 22:20:15.933698 First detailed timing is preferred timing
9333 22:20:15.933781 Established timings supported:
9334 22:20:15.937143 Standard timings supported:
9335 22:20:15.939872 Detailed timings
9336 22:20:15.943590 Hex of detail: 383680a07038204018303c0035ae10000019
9337 22:20:15.950261 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9338 22:20:15.952877 0780 0798 07c8 0820 hborder 0
9339 22:20:15.956796 0438 043b 0447 0458 vborder 0
9340 22:20:15.959908 -hsync -vsync
9341 22:20:15.959990 Did detailed timing
9342 22:20:15.966520 Hex of detail: 000000000000000000000000000000000000
9343 22:20:15.969654 Manufacturer-specified data, tag 0
9344 22:20:15.972824 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9345 22:20:15.976961 ASCII string: InfoVision
9346 22:20:15.979329 Hex of detail: 000000fe00523134304e574635205248200a
9347 22:20:15.982789 ASCII string: R140NWF5 RH
9348 22:20:15.982870 Checksum
9349 22:20:15.986610 Checksum: 0xfb (valid)
9350 22:20:15.989751 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9351 22:20:15.992837 DSI data_rate: 832800000 bps
9352 22:20:15.999084 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9353 22:20:16.002542 anx7625_parse_edid: pixelclock(138800).
9354 22:20:16.006153 hactive(1920), hsync(48), hfp(24), hbp(88)
9355 22:20:16.009295 vactive(1080), vsync(12), vfp(3), vbp(17)
9356 22:20:16.012454 anx7625_dsi_config: config dsi.
9357 22:20:16.019009 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9358 22:20:16.033035 anx7625_dsi_config: success to config DSI
9359 22:20:16.036293 anx7625_dp_start: MIPI phy setup OK.
9360 22:20:16.039590 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9361 22:20:16.042829 mtk_ddp_mode_set invalid vrefresh 60
9362 22:20:16.046175 main_disp_path_setup
9363 22:20:16.046261 ovl_layer_smi_id_en
9364 22:20:16.049200 ovl_layer_smi_id_en
9365 22:20:16.049273 ccorr_config
9366 22:20:16.049344 aal_config
9367 22:20:16.052705 gamma_config
9368 22:20:16.052784 postmask_config
9369 22:20:16.056182 dither_config
9370 22:20:16.059064 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9371 22:20:16.066376 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9372 22:20:16.069036 Root Device init finished in 553 msecs
9373 22:20:16.072273 CPU_CLUSTER: 0 init
9374 22:20:16.079410 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9375 22:20:16.085666 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9376 22:20:16.085750 APU_MBOX 0x190000b0 = 0x10001
9377 22:20:16.088641 APU_MBOX 0x190001b0 = 0x10001
9378 22:20:16.092735 APU_MBOX 0x190005b0 = 0x10001
9379 22:20:16.095501 APU_MBOX 0x190006b0 = 0x10001
9380 22:20:16.102301 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9381 22:20:16.111798 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9382 22:20:16.124838 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9383 22:20:16.131215 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9384 22:20:16.142808 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9385 22:20:16.152081 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9386 22:20:16.155278 CPU_CLUSTER: 0 init finished in 81 msecs
9387 22:20:16.158780 Devices initialized
9388 22:20:16.161941 Show all devs... After init.
9389 22:20:16.162014 Root Device: enabled 1
9390 22:20:16.165047 CPU_CLUSTER: 0: enabled 1
9391 22:20:16.168762 CPU: 00: enabled 1
9392 22:20:16.171527 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9393 22:20:16.174931 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9394 22:20:16.178257 ELOG: NV offset 0x57f000 size 0x1000
9395 22:20:16.184750 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9396 22:20:16.191446 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9397 22:20:16.195106 ELOG: Event(17) added with size 13 at 2023-06-05 22:20:15 UTC
9398 22:20:16.201587 out: cmd=0x121: 03 db 21 01 00 00 00 00
9399 22:20:16.205018 in-header: 03 da 00 00 2c 00 00 00
9400 22:20:16.217770 in-data: 85 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9401 22:20:16.224550 ELOG: Event(A1) added with size 10 at 2023-06-05 22:20:15 UTC
9402 22:20:16.230902 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9403 22:20:16.237552 ELOG: Event(A0) added with size 9 at 2023-06-05 22:20:15 UTC
9404 22:20:16.240686 elog_add_boot_reason: Logged dev mode boot
9405 22:20:16.244118 BS: BS_POST_DEVICE entry times (exec / console): 4 / 64 ms
9406 22:20:16.247165 Finalize devices...
9407 22:20:16.247247 Devices finalized
9408 22:20:16.254271 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9409 22:20:16.257474 Writing coreboot table at 0xffe64000
9410 22:20:16.260702 0. 000000000010a000-0000000000113fff: RAMSTAGE
9411 22:20:16.263930 1. 0000000040000000-00000000400fffff: RAM
9412 22:20:16.270700 2. 0000000040100000-000000004032afff: RAMSTAGE
9413 22:20:16.274248 3. 000000004032b000-00000000545fffff: RAM
9414 22:20:16.277243 4. 0000000054600000-000000005465ffff: BL31
9415 22:20:16.280670 5. 0000000054660000-00000000ffe63fff: RAM
9416 22:20:16.287240 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9417 22:20:16.290551 7. 0000000100000000-000000023fffffff: RAM
9418 22:20:16.293628 Passing 5 GPIOs to payload:
9419 22:20:16.296937 NAME | PORT | POLARITY | VALUE
9420 22:20:16.300832 EC in RW | 0x000000aa | low | undefined
9421 22:20:16.307017 EC interrupt | 0x00000005 | low | undefined
9422 22:20:16.310181 TPM interrupt | 0x000000ab | high | undefined
9423 22:20:16.316712 SD card detect | 0x00000011 | high | undefined
9424 22:20:16.319911 speaker enable | 0x00000093 | high | undefined
9425 22:20:16.323229 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9426 22:20:16.326271 in-header: 03 f9 00 00 02 00 00 00
9427 22:20:16.329644 in-data: 02 00
9428 22:20:16.329727 ADC[4]: Raw value=901552 ID=7
9429 22:20:16.332827 ADC[3]: Raw value=213652 ID=1
9430 22:20:16.336318 RAM Code: 0x71
9431 22:20:16.336400 ADC[6]: Raw value=75406 ID=0
9432 22:20:16.339516 ADC[5]: Raw value=212912 ID=1
9433 22:20:16.343792 SKU Code: 0x1
9434 22:20:16.346226 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9435 22:20:16.349769 coreboot table: 964 bytes.
9436 22:20:16.352864 IMD ROOT 0. 0xfffff000 0x00001000
9437 22:20:16.356090 IMD SMALL 1. 0xffffe000 0x00001000
9438 22:20:16.359465 RO MCACHE 2. 0xffffc000 0x00001104
9439 22:20:16.362668 CONSOLE 3. 0xfff7c000 0x00080000
9440 22:20:16.366022 FMAP 4. 0xfff7b000 0x00000452
9441 22:20:16.369421 TIME STAMP 5. 0xfff7a000 0x00000910
9442 22:20:16.372479 VBOOT WORK 6. 0xfff66000 0x00014000
9443 22:20:16.375916 RAMOOPS 7. 0xffe66000 0x00100000
9444 22:20:16.379453 COREBOOT 8. 0xffe64000 0x00002000
9445 22:20:16.382614 IMD small region:
9446 22:20:16.386017 IMD ROOT 0. 0xffffec00 0x00000400
9447 22:20:16.388929 VPD 1. 0xffffeba0 0x0000004c
9448 22:20:16.392065 MMC STATUS 2. 0xffffeb80 0x00000004
9449 22:20:16.396000 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9450 22:20:16.398707 Probing TPM: done!
9451 22:20:16.402485 Connected to device vid:did:rid of 1ae0:0028:00
9452 22:20:16.413123 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9453 22:20:16.416186 Initialized TPM device CR50 revision 0
9454 22:20:16.419673 Checking cr50 for pending updates
9455 22:20:16.423760 Reading cr50 TPM mode
9456 22:20:16.432048 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9457 22:20:16.439055 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9458 22:20:16.478898 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9459 22:20:16.482414 Checking segment from ROM address 0x40100000
9460 22:20:16.485559 Checking segment from ROM address 0x4010001c
9461 22:20:16.492032 Loading segment from ROM address 0x40100000
9462 22:20:16.492111 code (compression=0)
9463 22:20:16.501950 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9464 22:20:16.509060 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9465 22:20:16.511541 it's not compressed!
9466 22:20:16.514931 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9467 22:20:16.521633 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9468 22:20:16.539538 Loading segment from ROM address 0x4010001c
9469 22:20:16.539642 Entry Point 0x80000000
9470 22:20:16.542555 Loaded segments
9471 22:20:16.546454 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9472 22:20:16.552776 Jumping to boot code at 0x80000000(0xffe64000)
9473 22:20:16.559681 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9474 22:20:16.566248 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9475 22:20:16.573981 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9476 22:20:16.577205 Checking segment from ROM address 0x40100000
9477 22:20:16.580487 Checking segment from ROM address 0x4010001c
9478 22:20:16.587349 Loading segment from ROM address 0x40100000
9479 22:20:16.587455 code (compression=1)
9480 22:20:16.593994 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9481 22:20:16.603353 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9482 22:20:16.603438 using LZMA
9483 22:20:16.613224 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9484 22:20:16.618977 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9485 22:20:16.621882 Loading segment from ROM address 0x4010001c
9486 22:20:16.621992 Entry Point 0x54601000
9487 22:20:16.625501 Loaded segments
9488 22:20:16.628670 NOTICE: MT8192 bl31_setup
9489 22:20:16.635918 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9490 22:20:16.639239 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9491 22:20:16.642347 WARNING: region 0:
9492 22:20:16.646164 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 22:20:16.646307 WARNING: region 1:
9494 22:20:16.652297 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9495 22:20:16.655640 WARNING: region 2:
9496 22:20:16.659150 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9497 22:20:16.662566 WARNING: region 3:
9498 22:20:16.665676 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9499 22:20:16.669111 WARNING: region 4:
9500 22:20:16.675706 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 22:20:16.675789 WARNING: region 5:
9502 22:20:16.678984 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 22:20:16.682466 WARNING: region 6:
9504 22:20:16.685836 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 22:20:16.688695 WARNING: region 7:
9506 22:20:16.692388 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 22:20:16.698967 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9508 22:20:16.702163 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9509 22:20:16.705405 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9510 22:20:16.712144 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9511 22:20:16.715261 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9512 22:20:16.721997 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9513 22:20:16.725067 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9514 22:20:16.728329 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9515 22:20:16.735494 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9516 22:20:16.738204 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9517 22:20:16.741846 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9518 22:20:16.748458 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9519 22:20:16.751786 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9520 22:20:16.758328 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9521 22:20:16.761394 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9522 22:20:16.765053 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9523 22:20:16.771910 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9524 22:20:16.774663 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9525 22:20:16.778279 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9526 22:20:16.784683 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9527 22:20:16.787927 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9528 22:20:16.794894 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9529 22:20:16.798061 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9530 22:20:16.801213 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9531 22:20:16.807885 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9532 22:20:16.811025 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9533 22:20:16.818733 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9534 22:20:16.821149 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9535 22:20:16.827862 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9536 22:20:16.831300 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9537 22:20:16.834710 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9538 22:20:16.841362 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9539 22:20:16.844849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9540 22:20:16.847720 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9541 22:20:16.851114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9542 22:20:16.857702 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9543 22:20:16.861021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9544 22:20:16.864394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9545 22:20:16.867591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9546 22:20:16.874185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9547 22:20:16.877312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9548 22:20:16.880975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9549 22:20:16.884017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9550 22:20:16.890792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9551 22:20:16.893877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9552 22:20:16.897424 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9553 22:20:16.903941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9554 22:20:16.907319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9555 22:20:16.910778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9556 22:20:16.917404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9557 22:20:16.920663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9558 22:20:16.927607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9559 22:20:16.930646 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9560 22:20:16.933580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9561 22:20:16.940265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9562 22:20:16.943817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9563 22:20:16.950130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9564 22:20:16.953765 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9565 22:20:16.960029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9566 22:20:16.963326 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9567 22:20:16.970083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9568 22:20:16.973383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9569 22:20:16.976768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9570 22:20:16.983638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9571 22:20:16.986639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9572 22:20:16.993774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9573 22:20:16.996691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9574 22:20:17.003967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9575 22:20:17.006901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9576 22:20:17.010213 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9577 22:20:17.017425 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9578 22:20:17.020124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9579 22:20:17.026917 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9580 22:20:17.029923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9581 22:20:17.036815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9582 22:20:17.040124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9583 22:20:17.043412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9584 22:20:17.050049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9585 22:20:17.053441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9586 22:20:17.060540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9587 22:20:17.063371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9588 22:20:17.069745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9589 22:20:17.073186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9590 22:20:17.080077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9591 22:20:17.083254 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9592 22:20:17.086704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9593 22:20:17.093232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9594 22:20:17.096438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9595 22:20:17.103103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9596 22:20:17.106406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9597 22:20:17.112805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9598 22:20:17.116269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9599 22:20:17.119866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9600 22:20:17.126488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9601 22:20:17.130001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9602 22:20:17.136422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9603 22:20:17.140120 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9604 22:20:17.142777 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9605 22:20:17.149477 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9606 22:20:17.152863 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9607 22:20:17.155903 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9608 22:20:17.162616 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9609 22:20:17.165990 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9610 22:20:17.169278 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9611 22:20:17.175904 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9612 22:20:17.179292 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9613 22:20:17.185941 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9614 22:20:17.189437 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9615 22:20:17.192754 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9616 22:20:17.199396 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9617 22:20:17.202779 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9618 22:20:17.209213 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9619 22:20:17.212656 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9620 22:20:17.216008 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9621 22:20:17.222666 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9622 22:20:17.225682 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9623 22:20:17.229005 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9624 22:20:17.235740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9625 22:20:17.238985 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9626 22:20:17.242583 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9627 22:20:17.248943 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9628 22:20:17.252426 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9629 22:20:17.255864 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9630 22:20:17.258825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9631 22:20:17.265970 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9632 22:20:17.269122 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9633 22:20:17.272281 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9634 22:20:17.278941 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9635 22:20:17.282372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9636 22:20:17.289038 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9637 22:20:17.292112 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9638 22:20:17.295590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9639 22:20:17.302211 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9640 22:20:17.305572 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9641 22:20:17.312222 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9642 22:20:17.315670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9643 22:20:17.318573 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9644 22:20:17.325823 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9645 22:20:17.328827 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9646 22:20:17.335578 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9647 22:20:17.338721 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9648 22:20:17.341896 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9649 22:20:17.348227 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9650 22:20:17.351737 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9651 22:20:17.358780 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9652 22:20:17.362194 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9653 22:20:17.364871 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9654 22:20:17.371655 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9655 22:20:17.374884 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9656 22:20:17.381571 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9657 22:20:17.384644 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9658 22:20:17.388413 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9659 22:20:17.394571 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9660 22:20:17.398034 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9661 22:20:17.401490 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9662 22:20:17.408475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9663 22:20:17.411652 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9664 22:20:17.417726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9665 22:20:17.421542 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9666 22:20:17.424864 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9667 22:20:17.431377 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9668 22:20:17.434575 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9669 22:20:17.440794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9670 22:20:17.444546 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9671 22:20:17.450807 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9672 22:20:17.454140 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9673 22:20:17.457511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9674 22:20:17.464115 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9675 22:20:17.467194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9676 22:20:17.474037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9677 22:20:17.477044 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9678 22:20:17.480581 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9679 22:20:17.486973 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9680 22:20:17.490639 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9681 22:20:17.493978 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9682 22:20:17.500263 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9683 22:20:17.503741 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9684 22:20:17.510130 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9685 22:20:17.513966 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9686 22:20:17.516880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9687 22:20:17.523494 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9688 22:20:17.526654 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9689 22:20:17.533613 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9690 22:20:17.536405 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9691 22:20:17.543204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9692 22:20:17.546647 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9693 22:20:17.549980 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9694 22:20:17.556764 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9695 22:20:17.560042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9696 22:20:17.566866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9697 22:20:17.569916 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9698 22:20:17.573128 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9699 22:20:17.579652 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9700 22:20:17.583268 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9701 22:20:17.589552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9702 22:20:17.593705 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9703 22:20:17.596582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9704 22:20:17.602972 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9705 22:20:17.606241 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9706 22:20:17.612912 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9707 22:20:17.616234 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9708 22:20:17.622534 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9709 22:20:17.626283 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9710 22:20:17.629199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9711 22:20:17.636243 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9712 22:20:17.639108 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9713 22:20:17.645427 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9714 22:20:17.649412 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9715 22:20:17.655698 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9716 22:20:17.659308 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9717 22:20:17.662352 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9718 22:20:17.669010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9719 22:20:17.672265 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9720 22:20:17.678960 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9721 22:20:17.682071 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9722 22:20:17.685577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9723 22:20:17.691906 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9724 22:20:17.695154 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9725 22:20:17.701609 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9726 22:20:17.705098 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9727 22:20:17.711887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9728 22:20:17.715630 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9729 22:20:17.721544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9730 22:20:17.725015 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9731 22:20:17.728215 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9732 22:20:17.734660 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9733 22:20:17.738308 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9734 22:20:17.744672 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9735 22:20:17.747905 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9736 22:20:17.751317 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9737 22:20:17.758028 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9738 22:20:17.761849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9739 22:20:17.764416 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9740 22:20:17.767909 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9741 22:20:17.774301 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9742 22:20:17.777794 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9743 22:20:17.781292 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9744 22:20:17.787546 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9745 22:20:17.790719 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9746 22:20:17.797656 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9747 22:20:17.800944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9748 22:20:17.804170 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9749 22:20:17.810673 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9750 22:20:17.813716 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9751 22:20:17.817559 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9752 22:20:17.823936 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9753 22:20:17.827008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9754 22:20:17.833769 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9755 22:20:17.837498 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9756 22:20:17.840550 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9757 22:20:17.846843 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9758 22:20:17.850120 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9759 22:20:17.856465 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9760 22:20:17.860250 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9761 22:20:17.863593 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9762 22:20:17.869523 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9763 22:20:17.873021 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9764 22:20:17.876201 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9765 22:20:17.883423 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9766 22:20:17.886108 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9767 22:20:17.892452 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9768 22:20:17.896035 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9769 22:20:17.899131 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9770 22:20:17.905854 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9771 22:20:17.909266 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9772 22:20:17.912437 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9773 22:20:17.919206 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9774 22:20:17.922476 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9775 22:20:17.925357 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9776 22:20:17.932337 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9777 22:20:17.935611 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9778 22:20:17.938855 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9779 22:20:17.942165 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9780 22:20:17.945478 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9781 22:20:17.951999 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9782 22:20:17.955140 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9783 22:20:17.958704 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9784 22:20:17.965299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9785 22:20:17.968286 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9786 22:20:17.972304 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9787 22:20:17.975138 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9788 22:20:17.981956 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9789 22:20:17.985188 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9790 22:20:17.991851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9791 22:20:17.995168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9792 22:20:17.998189 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9793 22:20:18.004624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9794 22:20:18.008527 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9795 22:20:18.014811 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9796 22:20:18.018270 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9797 22:20:18.021611 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9798 22:20:18.028166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9799 22:20:18.031193 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9800 22:20:18.038412 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9801 22:20:18.041113 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9802 22:20:18.047887 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9803 22:20:18.051326 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9804 22:20:18.054318 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9805 22:20:18.060967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9806 22:20:18.064224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9807 22:20:18.070720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9808 22:20:18.073923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9809 22:20:18.080818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9810 22:20:18.084178 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9811 22:20:18.087540 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9812 22:20:18.093846 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9813 22:20:18.097275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9814 22:20:18.104900 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9815 22:20:18.107433 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9816 22:20:18.110839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9817 22:20:18.117146 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9818 22:20:18.120432 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9819 22:20:18.127209 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9820 22:20:18.130380 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9821 22:20:18.133934 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9822 22:20:18.140296 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9823 22:20:18.143845 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9824 22:20:18.150304 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9825 22:20:18.153348 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9826 22:20:18.160669 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9827 22:20:18.163219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9828 22:20:18.166806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9829 22:20:18.172953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9830 22:20:18.176705 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9831 22:20:18.182944 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9832 22:20:18.186346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9833 22:20:18.193546 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9834 22:20:18.196266 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9835 22:20:18.199641 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9836 22:20:18.206082 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9837 22:20:18.209787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9838 22:20:18.216499 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9839 22:20:18.219361 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9840 22:20:18.222615 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9841 22:20:18.229390 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9842 22:20:18.232682 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9843 22:20:18.239870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9844 22:20:18.242504 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9845 22:20:18.246005 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9846 22:20:18.252934 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9847 22:20:18.255641 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9848 22:20:18.262865 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9849 22:20:18.265985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9850 22:20:18.272156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9851 22:20:18.275735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9852 22:20:18.279029 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9853 22:20:18.285563 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9854 22:20:18.289424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9855 22:20:18.295604 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9856 22:20:18.298664 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9857 22:20:18.302013 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9858 22:20:18.308687 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9859 22:20:18.311913 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9860 22:20:18.319063 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9861 22:20:18.321986 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9862 22:20:18.328712 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9863 22:20:18.331939 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9864 22:20:18.335111 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9865 22:20:18.342530 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9866 22:20:18.345204 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9867 22:20:18.351938 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9868 22:20:18.355098 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9869 22:20:18.361805 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9870 22:20:18.365157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9871 22:20:18.371434 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9872 22:20:18.375669 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9873 22:20:18.378102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9874 22:20:18.384673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9875 22:20:18.388172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9876 22:20:18.394875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9877 22:20:18.397868 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9878 22:20:18.404783 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9879 22:20:18.407899 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9880 22:20:18.411275 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9881 22:20:18.417954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9882 22:20:18.420831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9883 22:20:18.427454 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9884 22:20:18.431469 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9885 22:20:18.437842 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9886 22:20:18.440897 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9887 22:20:18.447713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9888 22:20:18.450660 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9889 22:20:18.457241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9890 22:20:18.460358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9891 22:20:18.464093 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9892 22:20:18.470657 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9893 22:20:18.473795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9894 22:20:18.480344 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9895 22:20:18.483665 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9896 22:20:18.490341 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9897 22:20:18.493846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9898 22:20:18.496839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9899 22:20:18.503587 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9900 22:20:18.507263 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9901 22:20:18.513651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9902 22:20:18.517124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9903 22:20:18.523504 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9904 22:20:18.526879 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9905 22:20:18.533668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9906 22:20:18.537002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9907 22:20:18.540148 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9908 22:20:18.547389 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9909 22:20:18.550486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9910 22:20:18.556359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9911 22:20:18.560050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9912 22:20:18.566633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9913 22:20:18.569745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9914 22:20:18.575954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9915 22:20:18.579620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9916 22:20:18.586260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9917 22:20:18.589392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9918 22:20:18.596154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9919 22:20:18.599172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9920 22:20:18.602938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9921 22:20:18.609346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9922 22:20:18.612460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9923 22:20:18.618893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9924 22:20:18.622068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9925 22:20:18.629086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9926 22:20:18.632433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9927 22:20:18.638559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9928 22:20:18.642022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9929 22:20:18.648389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9930 22:20:18.651984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9931 22:20:18.658344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9932 22:20:18.661599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9933 22:20:18.668235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9934 22:20:18.674993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9935 22:20:18.678275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9936 22:20:18.684928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9937 22:20:18.688177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9938 22:20:18.694891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9939 22:20:18.697875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9940 22:20:18.704449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9941 22:20:18.707905 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9942 22:20:18.710925 INFO: [APUAPC] vio 0
9943 22:20:18.714403 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9944 22:20:18.717794 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9945 22:20:18.721168 INFO: [APUAPC] D0_APC_0: 0x400510
9946 22:20:18.724741 INFO: [APUAPC] D0_APC_1: 0x0
9947 22:20:18.727775 INFO: [APUAPC] D0_APC_2: 0x1540
9948 22:20:18.730927 INFO: [APUAPC] D0_APC_3: 0x0
9949 22:20:18.734245 INFO: [APUAPC] D1_APC_0: 0xffffffff
9950 22:20:18.737284 INFO: [APUAPC] D1_APC_1: 0xffffffff
9951 22:20:18.740511 INFO: [APUAPC] D1_APC_2: 0x3fffff
9952 22:20:18.744455 INFO: [APUAPC] D1_APC_3: 0x0
9953 22:20:18.747558 INFO: [APUAPC] D2_APC_0: 0xffffffff
9954 22:20:18.750482 INFO: [APUAPC] D2_APC_1: 0xffffffff
9955 22:20:18.754147 INFO: [APUAPC] D2_APC_2: 0x3fffff
9956 22:20:18.757456 INFO: [APUAPC] D2_APC_3: 0x0
9957 22:20:18.760953 INFO: [APUAPC] D3_APC_0: 0xffffffff
9958 22:20:18.764067 INFO: [APUAPC] D3_APC_1: 0xffffffff
9959 22:20:18.767171 INFO: [APUAPC] D3_APC_2: 0x3fffff
9960 22:20:18.771095 INFO: [APUAPC] D3_APC_3: 0x0
9961 22:20:18.773658 INFO: [APUAPC] D4_APC_0: 0xffffffff
9962 22:20:18.777099 INFO: [APUAPC] D4_APC_1: 0xffffffff
9963 22:20:18.780633 INFO: [APUAPC] D4_APC_2: 0x3fffff
9964 22:20:18.783815 INFO: [APUAPC] D4_APC_3: 0x0
9965 22:20:18.786959 INFO: [APUAPC] D5_APC_0: 0xffffffff
9966 22:20:18.790265 INFO: [APUAPC] D5_APC_1: 0xffffffff
9967 22:20:18.793862 INFO: [APUAPC] D5_APC_2: 0x3fffff
9968 22:20:18.796838 INFO: [APUAPC] D5_APC_3: 0x0
9969 22:20:18.800225 INFO: [APUAPC] D6_APC_0: 0xffffffff
9970 22:20:18.803542 INFO: [APUAPC] D6_APC_1: 0xffffffff
9971 22:20:18.806807 INFO: [APUAPC] D6_APC_2: 0x3fffff
9972 22:20:18.809783 INFO: [APUAPC] D6_APC_3: 0x0
9973 22:20:18.813949 INFO: [APUAPC] D7_APC_0: 0xffffffff
9974 22:20:18.816690 INFO: [APUAPC] D7_APC_1: 0xffffffff
9975 22:20:18.819760 INFO: [APUAPC] D7_APC_2: 0x3fffff
9976 22:20:18.823276 INFO: [APUAPC] D7_APC_3: 0x0
9977 22:20:18.826436 INFO: [APUAPC] D8_APC_0: 0xffffffff
9978 22:20:18.829565 INFO: [APUAPC] D8_APC_1: 0xffffffff
9979 22:20:18.832891 INFO: [APUAPC] D8_APC_2: 0x3fffff
9980 22:20:18.836117 INFO: [APUAPC] D8_APC_3: 0x0
9981 22:20:18.839667 INFO: [APUAPC] D9_APC_0: 0xffffffff
9982 22:20:18.843031 INFO: [APUAPC] D9_APC_1: 0xffffffff
9983 22:20:18.846067 INFO: [APUAPC] D9_APC_2: 0x3fffff
9984 22:20:18.849278 INFO: [APUAPC] D9_APC_3: 0x0
9985 22:20:18.852794 INFO: [APUAPC] D10_APC_0: 0xffffffff
9986 22:20:18.856047 INFO: [APUAPC] D10_APC_1: 0xffffffff
9987 22:20:18.859316 INFO: [APUAPC] D10_APC_2: 0x3fffff
9988 22:20:18.862604 INFO: [APUAPC] D10_APC_3: 0x0
9989 22:20:18.866168 INFO: [APUAPC] D11_APC_0: 0xffffffff
9990 22:20:18.869241 INFO: [APUAPC] D11_APC_1: 0xffffffff
9991 22:20:18.872472 INFO: [APUAPC] D11_APC_2: 0x3fffff
9992 22:20:18.875696 INFO: [APUAPC] D11_APC_3: 0x0
9993 22:20:18.879130 INFO: [APUAPC] D12_APC_0: 0xffffffff
9994 22:20:18.882281 INFO: [APUAPC] D12_APC_1: 0xffffffff
9995 22:20:18.885505 INFO: [APUAPC] D12_APC_2: 0x3fffff
9996 22:20:18.888890 INFO: [APUAPC] D12_APC_3: 0x0
9997 22:20:18.892107 INFO: [APUAPC] D13_APC_0: 0xffffffff
9998 22:20:18.895657 INFO: [APUAPC] D13_APC_1: 0xffffffff
9999 22:20:18.899011 INFO: [APUAPC] D13_APC_2: 0x3fffff
10000 22:20:18.902976 INFO: [APUAPC] D13_APC_3: 0x0
10001 22:20:18.905651 INFO: [APUAPC] D14_APC_0: 0xffffffff
10002 22:20:18.909112 INFO: [APUAPC] D14_APC_1: 0xffffffff
10003 22:20:18.912192 INFO: [APUAPC] D14_APC_2: 0x3fffff
10004 22:20:18.915239 INFO: [APUAPC] D14_APC_3: 0x0
10005 22:20:18.918838 INFO: [APUAPC] D15_APC_0: 0xffffffff
10006 22:20:18.921730 INFO: [APUAPC] D15_APC_1: 0xffffffff
10007 22:20:18.925368 INFO: [APUAPC] D15_APC_2: 0x3fffff
10008 22:20:18.928234 INFO: [APUAPC] D15_APC_3: 0x0
10009 22:20:18.931818 INFO: [APUAPC] APC_CON: 0x4
10010 22:20:18.935387 INFO: [NOCDAPC] D0_APC_0: 0x0
10011 22:20:18.938617 INFO: [NOCDAPC] D0_APC_1: 0x0
10012 22:20:18.941793 INFO: [NOCDAPC] D1_APC_0: 0x0
10013 22:20:18.941888 INFO: [NOCDAPC] D1_APC_1: 0xfff
10014 22:20:18.944857 INFO: [NOCDAPC] D2_APC_0: 0x0
10015 22:20:18.948343 INFO: [NOCDAPC] D2_APC_1: 0xfff
10016 22:20:18.951836 INFO: [NOCDAPC] D3_APC_0: 0x0
10017 22:20:18.954984 INFO: [NOCDAPC] D3_APC_1: 0xfff
10018 22:20:18.958186 INFO: [NOCDAPC] D4_APC_0: 0x0
10019 22:20:18.961344 INFO: [NOCDAPC] D4_APC_1: 0xfff
10020 22:20:18.964948 INFO: [NOCDAPC] D5_APC_0: 0x0
10021 22:20:18.968432 INFO: [NOCDAPC] D5_APC_1: 0xfff
10022 22:20:18.971883 INFO: [NOCDAPC] D6_APC_0: 0x0
10023 22:20:18.974581 INFO: [NOCDAPC] D6_APC_1: 0xfff
10024 22:20:18.974682 INFO: [NOCDAPC] D7_APC_0: 0x0
10025 22:20:18.978024 INFO: [NOCDAPC] D7_APC_1: 0xfff
10026 22:20:18.981643 INFO: [NOCDAPC] D8_APC_0: 0x0
10027 22:20:18.984441 INFO: [NOCDAPC] D8_APC_1: 0xfff
10028 22:20:18.987755 INFO: [NOCDAPC] D9_APC_0: 0x0
10029 22:20:18.991437 INFO: [NOCDAPC] D9_APC_1: 0xfff
10030 22:20:18.994462 INFO: [NOCDAPC] D10_APC_0: 0x0
10031 22:20:18.997972 INFO: [NOCDAPC] D10_APC_1: 0xfff
10032 22:20:19.001068 INFO: [NOCDAPC] D11_APC_0: 0x0
10033 22:20:19.004840 INFO: [NOCDAPC] D11_APC_1: 0xfff
10034 22:20:19.008212 INFO: [NOCDAPC] D12_APC_0: 0x0
10035 22:20:19.011339 INFO: [NOCDAPC] D12_APC_1: 0xfff
10036 22:20:19.014227 INFO: [NOCDAPC] D13_APC_0: 0x0
10037 22:20:19.017714 INFO: [NOCDAPC] D13_APC_1: 0xfff
10038 22:20:19.017786 INFO: [NOCDAPC] D14_APC_0: 0x0
10039 22:20:19.021124 INFO: [NOCDAPC] D14_APC_1: 0xfff
10040 22:20:19.024180 INFO: [NOCDAPC] D15_APC_0: 0x0
10041 22:20:19.027886 INFO: [NOCDAPC] D15_APC_1: 0xfff
10042 22:20:19.031031 INFO: [NOCDAPC] APC_CON: 0x4
10043 22:20:19.034355 INFO: [APUAPC] set_apusys_apc done
10044 22:20:19.037462 INFO: [DEVAPC] devapc_init done
10045 22:20:19.040873 INFO: GICv3 without legacy support detected.
10046 22:20:19.047531 INFO: ARM GICv3 driver initialized in EL3
10047 22:20:19.050998 INFO: Maximum SPI INTID supported: 639
10048 22:20:19.054077 INFO: BL31: Initializing runtime services
10049 22:20:19.060627 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10050 22:20:19.060703 INFO: SPM: enable CPC mode
10051 22:20:19.067340 INFO: mcdi ready for mcusys-off-idle and system suspend
10052 22:20:19.070720 INFO: BL31: Preparing for EL3 exit to normal world
10053 22:20:19.077143 INFO: Entry point address = 0x80000000
10054 22:20:19.077252 INFO: SPSR = 0x8
10055 22:20:19.083445
10056 22:20:19.083543
10057 22:20:19.083610
10058 22:20:19.087233 Starting depthcharge on Spherion...
10059 22:20:19.087331
10060 22:20:19.087428 Wipe memory regions:
10061 22:20:19.087514
10062 22:20:19.088302 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10063 22:20:19.088437 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10064 22:20:19.088592 Setting prompt string to ['asurada:']
10065 22:20:19.088699 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10066 22:20:19.090192 [0x00000040000000, 0x00000054600000)
10067 22:20:19.212682
10068 22:20:19.212810 [0x00000054660000, 0x00000080000000)
10069 22:20:19.472900
10070 22:20:19.473040 [0x000000821a7280, 0x000000ffe64000)
10071 22:20:20.216630
10072 22:20:20.216780 [0x00000100000000, 0x00000240000000)
10073 22:20:22.104390
10074 22:20:22.107984 Initializing XHCI USB controller at 0x11200000.
10075 22:20:23.088667
10076 22:20:23.088865 R8152: Initializing
10077 22:20:23.088967
10078 22:20:23.092568 Version 9 (ocp_data = 6010)
10079 22:20:23.092754
10080 22:20:23.095378 R8152: Done initializing
10081 22:20:23.095559
10082 22:20:23.095685 Adding net device
10083 22:20:23.616912
10084 22:20:23.620296 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10085 22:20:23.620391
10086 22:20:23.620455
10087 22:20:23.620519
10088 22:20:23.620835 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 22:20:23.721185 asurada: tftpboot 192.168.201.1 10597286/tftp-deploy-lv8lul9s/kernel/image.itb 10597286/tftp-deploy-lv8lul9s/kernel/cmdline
10091 22:20:23.721345 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 22:20:23.721437 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10093 22:20:23.726235 tftpboot 192.168.201.1 10597286/tftp-deploy-lv8lul9s/kernel/image.ittp-deploy-lv8lul9s/kernel/cmdline
10094 22:20:23.726319
10095 22:20:23.726384 Waiting for link
10096 22:20:23.927904
10097 22:20:23.928044 done.
10098 22:20:23.928111
10099 22:20:23.928171 MAC: f4:f5:e8:50:de:0a
10100 22:20:23.928231
10101 22:20:23.931270 Sending DHCP discover... done.
10102 22:20:23.931356
10103 22:20:23.934563 Waiting for reply... done.
10104 22:20:23.934644
10105 22:20:23.938076 Sending DHCP request... done.
10106 22:20:23.938159
10107 22:20:23.938224 Waiting for reply... done.
10108 22:20:23.938284
10109 22:20:23.940988 My ip is 192.168.201.14
10110 22:20:23.941069
10111 22:20:23.944653 The DHCP server ip is 192.168.201.1
10112 22:20:23.944753
10113 22:20:23.947567 TFTP server IP predefined by user: 192.168.201.1
10114 22:20:23.947651
10115 22:20:23.954499 Bootfile predefined by user: 10597286/tftp-deploy-lv8lul9s/kernel/image.itb
10116 22:20:23.954579
10117 22:20:23.957624 Sending tftp read request... done.
10118 22:20:23.957701
10119 22:20:23.961096 Waiting for the transfer...
10120 22:20:23.961168
10121 22:20:24.202262 00000000 ################################################################
10122 22:20:24.202404
10123 22:20:24.432979 00080000 ################################################################
10124 22:20:24.433128
10125 22:20:24.663830 00100000 ################################################################
10126 22:20:24.663986
10127 22:20:24.897798 00180000 ################################################################
10128 22:20:24.897935
10129 22:20:25.127772 00200000 ################################################################
10130 22:20:25.127921
10131 22:20:25.362290 00280000 ################################################################
10132 22:20:25.362446
10133 22:20:25.593348 00300000 ################################################################
10134 22:20:25.593501
10135 22:20:25.818645 00380000 ################################################################
10136 22:20:25.818813
10137 22:20:26.048675 00400000 ################################################################
10138 22:20:26.048836
10139 22:20:26.271860 00480000 ################################################################
10140 22:20:26.272009
10141 22:20:26.497492 00500000 ################################################################
10142 22:20:26.497662
10143 22:20:26.723066 00580000 ################################################################
10144 22:20:26.723217
10145 22:20:26.949425 00600000 ################################################################
10146 22:20:26.949571
10147 22:20:27.177608 00680000 ################################################################
10148 22:20:27.177757
10149 22:20:27.411883 00700000 ################################################################
10150 22:20:27.412032
10151 22:20:27.644867 00780000 ################################################################
10152 22:20:27.645076
10153 22:20:27.869715 00800000 ################################################################
10154 22:20:27.869865
10155 22:20:28.094964 00880000 ################################################################
10156 22:20:28.095115
10157 22:20:28.319259 00900000 ################################################################
10158 22:20:28.319403
10159 22:20:28.547684 00980000 ################################################################
10160 22:20:28.547866
10161 22:20:28.774738 00a00000 ################################################################
10162 22:20:28.774890
10163 22:20:28.998874 00a80000 ################################################################
10164 22:20:28.999023
10165 22:20:29.221840 00b00000 ################################################################
10166 22:20:29.221987
10167 22:20:29.448788 00b80000 ################################################################
10168 22:20:29.448967
10169 22:20:29.672186 00c00000 ################################################################
10170 22:20:29.672337
10171 22:20:29.899485 00c80000 ################################################################
10172 22:20:29.899647
10173 22:20:30.130298 00d00000 ################################################################
10174 22:20:30.130482
10175 22:20:30.359953 00d80000 ################################################################
10176 22:20:30.360102
10177 22:20:30.582252 00e00000 ################################################################
10178 22:20:30.582400
10179 22:20:30.823018 00e80000 ################################################################
10180 22:20:30.823161
10181 22:20:31.049790 00f00000 ################################################################
10182 22:20:31.049936
10183 22:20:31.276647 00f80000 ################################################################
10184 22:20:31.276799
10185 22:20:31.507355 01000000 ################################################################
10186 22:20:31.507490
10187 22:20:31.731969 01080000 ################################################################
10188 22:20:31.732119
10189 22:20:31.959449 01100000 ################################################################
10190 22:20:31.959615
10191 22:20:32.190235 01180000 ################################################################
10192 22:20:32.190399
10193 22:20:32.421414 01200000 ################################################################
10194 22:20:32.421586
10195 22:20:32.648744 01280000 ################################################################
10196 22:20:32.648879
10197 22:20:32.890312 01300000 ################################################################
10198 22:20:32.890465
10199 22:20:33.126522 01380000 ################################################################
10200 22:20:33.126656
10201 22:20:33.357175 01400000 ################################################################
10202 22:20:33.357327
10203 22:20:33.587776 01480000 ################################################################
10204 22:20:33.587912
10205 22:20:33.815237 01500000 ################################################################
10206 22:20:33.815403
10207 22:20:34.044532 01580000 ################################################################
10208 22:20:34.044678
10209 22:20:34.275975 01600000 ################################################################
10210 22:20:34.276116
10211 22:20:34.511493 01680000 ################################################################
10212 22:20:34.511653
10213 22:20:34.744957 01700000 ################################################################
10214 22:20:34.745093
10215 22:20:34.973896 01780000 ################################################################
10216 22:20:34.974034
10217 22:20:35.204697 01800000 ################################################################
10218 22:20:35.204843
10219 22:20:35.436656 01880000 ################################################################
10220 22:20:35.436811
10221 22:20:35.664450 01900000 ################################################################
10222 22:20:35.664646
10223 22:20:35.892613 01980000 ################################################################
10224 22:20:35.892770
10225 22:20:36.121749 01a00000 ################################################################
10226 22:20:36.121900
10227 22:20:36.347829 01a80000 ################################################################
10228 22:20:36.347973
10229 22:20:36.586095 01b00000 ################################################################
10230 22:20:36.586222
10231 22:20:36.820016 01b80000 ################################################################
10232 22:20:36.820153
10233 22:20:37.046457 01c00000 ################################################################
10234 22:20:37.046597
10235 22:20:37.271326 01c80000 ################################################################
10236 22:20:37.271485
10237 22:20:37.500417 01d00000 ################################################################
10238 22:20:37.500621
10239 22:20:37.740524 01d80000 ################################################################
10240 22:20:37.740698
10241 22:20:37.990965 01e00000 ################################################################
10242 22:20:37.991129
10243 22:20:38.217292 01e80000 ################################################################
10244 22:20:38.217452
10245 22:20:38.444505 01f00000 ################################################################
10246 22:20:38.444720
10247 22:20:38.672382 01f80000 ################################################################
10248 22:20:38.672599
10249 22:20:38.902079 02000000 ################################################################
10250 22:20:38.902244
10251 22:20:39.135879 02080000 ################################################################
10252 22:20:39.136051
10253 22:20:39.378817 02100000 ################################################################
10254 22:20:39.378979
10255 22:20:39.607103 02180000 ################################################################
10256 22:20:39.607240
10257 22:20:39.836079 02200000 ################################################################
10258 22:20:39.836216
10259 22:20:40.063258 02280000 ################################################################
10260 22:20:40.063456
10261 22:20:40.292339 02300000 ################################################################
10262 22:20:40.292491
10263 22:20:40.522974 02380000 ################################################################
10264 22:20:40.523110
10265 22:20:40.750754 02400000 ################################################################
10266 22:20:40.750899
10267 22:20:40.978627 02480000 ################################################################
10268 22:20:40.978758
10269 22:20:41.206531 02500000 ################################################################
10270 22:20:41.206663
10271 22:20:41.435972 02580000 ################################################################
10272 22:20:41.436141
10273 22:20:41.664989 02600000 ################################################################
10274 22:20:41.665138
10275 22:20:41.892277 02680000 ################################################################
10276 22:20:41.892444
10277 22:20:42.117662 02700000 ################################################################
10278 22:20:42.117813
10279 22:20:42.349496 02780000 ################################################################
10280 22:20:42.349627
10281 22:20:42.578541 02800000 ################################################################
10282 22:20:42.578685
10283 22:20:42.800894 02880000 ################################################################
10284 22:20:42.801040
10285 22:20:43.026559 02900000 ################################################################
10286 22:20:43.026706
10287 22:20:43.263378 02980000 ################################################################
10288 22:20:43.263600
10289 22:20:43.489601 02a00000 ################################################################
10290 22:20:43.489775
10291 22:20:43.719631 02a80000 ################################################################
10292 22:20:43.719800
10293 22:20:43.952723 02b00000 ################################################################
10294 22:20:43.952870
10295 22:20:44.181599 02b80000 ################################################################
10296 22:20:44.181768
10297 22:20:44.408486 02c00000 ################################################################
10298 22:20:44.408700
10299 22:20:44.636369 02c80000 ################################################################
10300 22:20:44.636543
10301 22:20:44.865531 02d00000 ################################################################
10302 22:20:44.865709
10303 22:20:45.093323 02d80000 ################################################################
10304 22:20:45.093456
10305 22:20:45.327756 02e00000 ################################################################
10306 22:20:45.327933
10307 22:20:45.564872 02e80000 ################################################################
10308 22:20:45.565007
10309 22:20:45.787658 02f00000 ################################################################
10310 22:20:45.787807
10311 22:20:45.987195 02f80000 ########################################################## done.
10312 22:20:45.987335
10313 22:20:45.990312 The bootfile was 50275714 bytes long.
10314 22:20:45.990397
10315 22:20:45.993652 Sending tftp read request... done.
10316 22:20:45.993736
10317 22:20:45.997479 Waiting for the transfer...
10318 22:20:45.997562
10319 22:20:45.997627 00000000 # done.
10320 22:20:45.997691
10321 22:20:46.007018 Command line loaded dynamically from TFTP file: 10597286/tftp-deploy-lv8lul9s/kernel/cmdline
10322 22:20:46.007115
10323 22:20:46.017251 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10324 22:20:46.017438
10325 22:20:46.017541 Loading FIT.
10326 22:20:46.017634
10327 22:20:46.020113 Image ramdisk-1 has 40144451 bytes.
10328 22:20:46.020247
10329 22:20:46.023547 Image fdt-1 has 46924 bytes.
10330 22:20:46.023691
10331 22:20:46.026879 Image kernel-1 has 10082307 bytes.
10332 22:20:46.027029
10333 22:20:46.036640 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10334 22:20:46.036892
10335 22:20:46.053140 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10336 22:20:46.053239
10337 22:20:46.059531 Choosing best match conf-1 for compat google,spherion-rev2.
10338 22:20:46.059615
10339 22:20:46.066816 Connected to device vid:did:rid of 1ae0:0028:00
10340 22:20:46.074891
10341 22:20:46.077860 tpm_get_response: command 0x17b, return code 0x0
10342 22:20:46.077944
10343 22:20:46.084106 ec_init: CrosEC protocol v3 supported (256, 248)
10344 22:20:46.084216
10345 22:20:46.087245 tpm_cleanup: add release locality here.
10346 22:20:46.087329
10347 22:20:46.090814 Shutting down all USB controllers.
10348 22:20:46.090897
10349 22:20:46.094179 Removing current net device
10350 22:20:46.094262
10351 22:20:46.097058 Exiting depthcharge with code 4 at timestamp: 56407059
10352 22:20:46.097142
10353 22:20:46.100941 LZMA decompressing kernel-1 to 0x821a6718
10354 22:20:46.101024
10355 22:20:46.103473 LZMA decompressing kernel-1 to 0x40000000
10356 22:20:47.372379
10357 22:20:47.372577 jumping to kernel
10358 22:20:47.373003 end: 2.2.4 bootloader-commands (duration 00:00:28) [common]
10359 22:20:47.373103 start: 2.2.5 auto-login-action (timeout 00:03:57) [common]
10360 22:20:47.373178 Setting prompt string to ['Linux version [0-9]']
10361 22:20:47.373246 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10362 22:20:47.373316 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10363 22:20:47.454378
10364 22:20:47.457681 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10365 22:20:47.461915 start: 2.2.5.1 login-action (timeout 00:03:57) [common]
10366 22:20:47.462362 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10367 22:20:47.462791 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10368 22:20:47.463177 Using line separator: #'\n'#
10369 22:20:47.463487 No login prompt set.
10370 22:20:47.463791 Parsing kernel messages
10371 22:20:47.464077 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10372 22:20:47.464618 [login-action] Waiting for messages, (timeout 00:03:57)
10373 22:20:47.480421 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1612341-arm64-gcc-10-defconfig-arm64-chromebook-n674v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023
10374 22:20:47.483393 [ 0.000000] random: crng init done
10375 22:20:47.490433 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10376 22:20:47.493830 [ 0.000000] efi: UEFI not found.
10377 22:20:47.499954 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10378 22:20:47.506861 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10379 22:20:47.516532 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10380 22:20:47.526840 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10381 22:20:47.533237 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10382 22:20:47.539853 [ 0.000000] printk: bootconsole [mtk8250] enabled
10383 22:20:47.546310 [ 0.000000] NUMA: No NUMA configuration found
10384 22:20:47.552488 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10385 22:20:47.555876 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10386 22:20:47.559604 [ 0.000000] Zone ranges:
10387 22:20:47.566246 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10388 22:20:47.569256 [ 0.000000] DMA32 empty
10389 22:20:47.575681 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10390 22:20:47.579242 [ 0.000000] Movable zone start for each node
10391 22:20:47.582459 [ 0.000000] Early memory node ranges
10392 22:20:47.589254 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10393 22:20:47.595375 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10394 22:20:47.602461 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10395 22:20:47.608895 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10396 22:20:47.615696 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10397 22:20:47.621650 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10398 22:20:47.678059 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10399 22:20:47.684340 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10400 22:20:47.690969 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10401 22:20:47.694506 [ 0.000000] psci: probing for conduit method from DT.
10402 22:20:47.701053 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10403 22:20:47.704501 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10404 22:20:47.710902 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10405 22:20:47.714406 [ 0.000000] psci: SMC Calling Convention v1.2
10406 22:20:47.720567 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10407 22:20:47.724388 [ 0.000000] Detected VIPT I-cache on CPU0
10408 22:20:47.730785 [ 0.000000] CPU features: detected: GIC system register CPU interface
10409 22:20:47.737241 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10410 22:20:47.743847 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10411 22:20:47.750906 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10412 22:20:47.757129 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10413 22:20:47.766814 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10414 22:20:47.770057 [ 0.000000] alternatives: applying boot alternatives
10415 22:20:47.776949 [ 0.000000] Fallback order for Node 0: 0
10416 22:20:47.783876 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10417 22:20:47.786563 [ 0.000000] Policy zone: Normal
10418 22:20:47.796550 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10419 22:20:47.810122 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10420 22:20:47.819731 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10421 22:20:47.829377 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10422 22:20:47.836190 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10423 22:20:47.839655 <6>[ 0.000000] software IO TLB: area num 8.
10424 22:20:47.896389 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10425 22:20:48.045224 <6>[ 0.000000] Memory: 7933736K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419032K reserved, 32768K cma-reserved)
10426 22:20:48.052044 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10427 22:20:48.059313 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10428 22:20:48.062044 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10429 22:20:48.068524 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10430 22:20:48.075954 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10431 22:20:48.079028 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10432 22:20:48.088512 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10433 22:20:48.094889 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10434 22:20:48.101399 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10435 22:20:48.107797 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10436 22:20:48.111260 <6>[ 0.000000] GICv3: 608 SPIs implemented
10437 22:20:48.114336 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10438 22:20:48.121770 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10439 22:20:48.124250 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10440 22:20:48.130810 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10441 22:20:48.144251 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10442 22:20:48.157561 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10443 22:20:48.163746 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10444 22:20:48.172039 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10445 22:20:48.185011 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10446 22:20:48.191324 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10447 22:20:48.198612 <6>[ 0.009175] Console: colour dummy device 80x25
10448 22:20:48.207896 <6>[ 0.013900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10449 22:20:48.215206 <6>[ 0.024406] pid_max: default: 32768 minimum: 301
10450 22:20:48.218502 <6>[ 0.029280] LSM: Security Framework initializing
10451 22:20:48.224664 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 22:20:48.234765 <6>[ 0.042081] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 22:20:48.244690 <6>[ 0.051506] cblist_init_generic: Setting adjustable number of callback queues.
10454 22:20:48.251718 <6>[ 0.059008] cblist_init_generic: Setting shift to 3 and lim to 1.
10455 22:20:48.254574 <6>[ 0.065387] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 22:20:48.260924 <6>[ 0.071794] rcu: Hierarchical SRCU implementation.
10457 22:20:48.267810 <6>[ 0.076808] rcu: Max phase no-delay instances is 1000.
10458 22:20:48.274092 <6>[ 0.083833] EFI services will not be available.
10459 22:20:48.277180 <6>[ 0.088840] smp: Bringing up secondary CPUs ...
10460 22:20:48.285482 <6>[ 0.093895] Detected VIPT I-cache on CPU1
10461 22:20:48.291991 <6>[ 0.093966] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10462 22:20:48.298965 <6>[ 0.093997] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10463 22:20:48.301604 <6>[ 0.094338] Detected VIPT I-cache on CPU2
10464 22:20:48.311539 <6>[ 0.094392] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10465 22:20:48.317913 <6>[ 0.094409] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10466 22:20:48.321269 <6>[ 0.094668] Detected VIPT I-cache on CPU3
10467 22:20:48.328643 <6>[ 0.094714] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10468 22:20:48.334865 <6>[ 0.094728] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10469 22:20:48.341210 <6>[ 0.095032] CPU features: detected: Spectre-v4
10470 22:20:48.344311 <6>[ 0.095039] CPU features: detected: Spectre-BHB
10471 22:20:48.347628 <6>[ 0.095045] Detected PIPT I-cache on CPU4
10472 22:20:48.354558 <6>[ 0.095102] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10473 22:20:48.361422 <6>[ 0.095118] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10474 22:20:48.367441 <6>[ 0.095415] Detected PIPT I-cache on CPU5
10475 22:20:48.374257 <6>[ 0.095479] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10476 22:20:48.381084 <6>[ 0.095495] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10477 22:20:48.384356 <6>[ 0.095778] Detected PIPT I-cache on CPU6
10478 22:20:48.390967 <6>[ 0.095842] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10479 22:20:48.400758 <6>[ 0.095858] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10480 22:20:48.404233 <6>[ 0.096153] Detected PIPT I-cache on CPU7
10481 22:20:48.410587 <6>[ 0.096217] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10482 22:20:48.416828 <6>[ 0.096233] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10483 22:20:48.420324 <6>[ 0.096280] smp: Brought up 1 node, 8 CPUs
10484 22:20:48.427275 <6>[ 0.237583] SMP: Total of 8 processors activated.
10485 22:20:48.433337 <6>[ 0.242504] CPU features: detected: 32-bit EL0 Support
10486 22:20:48.440205 <6>[ 0.247901] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10487 22:20:48.446652 <6>[ 0.256755] CPU features: detected: Common not Private translations
10488 22:20:48.453742 <6>[ 0.263231] CPU features: detected: CRC32 instructions
10489 22:20:48.460275 <6>[ 0.268582] CPU features: detected: RCpc load-acquire (LDAPR)
10490 22:20:48.463496 <6>[ 0.274542] CPU features: detected: LSE atomic instructions
10491 22:20:48.469983 <6>[ 0.280323] CPU features: detected: Privileged Access Never
10492 22:20:48.476447 <6>[ 0.286139] CPU features: detected: RAS Extension Support
10493 22:20:48.483312 <6>[ 0.291782] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10494 22:20:48.486278 <6>[ 0.299048] CPU: All CPU(s) started at EL2
10495 22:20:48.492871 <6>[ 0.303364] alternatives: applying system-wide alternatives
10496 22:20:48.503646 <6>[ 0.314065] devtmpfs: initialized
10497 22:20:48.518478 <6>[ 0.322903] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10498 22:20:48.525664 <6>[ 0.332866] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10499 22:20:48.531812 <6>[ 0.341035] pinctrl core: initialized pinctrl subsystem
10500 22:20:48.535937 <6>[ 0.347675] DMI not present or invalid.
10501 22:20:48.541637 <6>[ 0.352079] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10502 22:20:48.551563 <6>[ 0.358943] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10503 22:20:48.557866 <6>[ 0.366528] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10504 22:20:48.567710 <6>[ 0.374745] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10505 22:20:48.571340 <6>[ 0.382986] audit: initializing netlink subsys (disabled)
10506 22:20:48.580981 <5>[ 0.388680] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10507 22:20:48.588021 <6>[ 0.389376] thermal_sys: Registered thermal governor 'step_wise'
10508 22:20:48.594851 <6>[ 0.396643] thermal_sys: Registered thermal governor 'power_allocator'
10509 22:20:48.597717 <6>[ 0.402900] cpuidle: using governor menu
10510 22:20:48.604795 <6>[ 0.413864] NET: Registered PF_QIPCRTR protocol family
10511 22:20:48.611058 <6>[ 0.419344] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10512 22:20:48.617384 <6>[ 0.426443] ASID allocator initialised with 32768 entries
10513 22:20:48.620956 <6>[ 0.433005] Serial: AMBA PL011 UART driver
10514 22:20:48.631273 <4>[ 0.441592] Trying to register duplicate clock ID: 134
10515 22:20:48.684841 <6>[ 0.498743] KASLR enabled
10516 22:20:48.698863 <6>[ 0.506420] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10517 22:20:48.705581 <6>[ 0.513435] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10518 22:20:48.711623 <6>[ 0.519923] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10519 22:20:48.718581 <6>[ 0.526928] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10520 22:20:48.725094 <6>[ 0.533414] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10521 22:20:48.731493 <6>[ 0.540415] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10522 22:20:48.738127 <6>[ 0.546899] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10523 22:20:48.745090 <6>[ 0.553903] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10524 22:20:48.748031 <6>[ 0.561377] ACPI: Interpreter disabled.
10525 22:20:48.756844 <6>[ 0.567808] iommu: Default domain type: Translated
10526 22:20:48.763225 <6>[ 0.572919] iommu: DMA domain TLB invalidation policy: strict mode
10527 22:20:48.766507 <5>[ 0.579582] SCSI subsystem initialized
10528 22:20:48.773360 <6>[ 0.583823] usbcore: registered new interface driver usbfs
10529 22:20:48.779888 <6>[ 0.589553] usbcore: registered new interface driver hub
10530 22:20:48.782976 <6>[ 0.595108] usbcore: registered new device driver usb
10531 22:20:48.790073 <6>[ 0.601210] pps_core: LinuxPPS API ver. 1 registered
10532 22:20:48.800161 <6>[ 0.606403] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10533 22:20:48.803503 <6>[ 0.615745] PTP clock support registered
10534 22:20:48.806574 <6>[ 0.619986] EDAC MC: Ver: 3.0.0
10535 22:20:48.814364 <6>[ 0.625157] FPGA manager framework
10536 22:20:48.817500 <6>[ 0.628834] Advanced Linux Sound Architecture Driver Initialized.
10537 22:20:48.821294 <6>[ 0.635595] vgaarb: loaded
10538 22:20:48.828264 <6>[ 0.638761] clocksource: Switched to clocksource arch_sys_counter
10539 22:20:48.834376 <5>[ 0.645208] VFS: Disk quotas dquot_6.6.0
10540 22:20:48.841328 <6>[ 0.649395] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10541 22:20:48.844666 <6>[ 0.656587] pnp: PnP ACPI: disabled
10542 22:20:48.852122 <6>[ 0.663238] NET: Registered PF_INET protocol family
10543 22:20:48.862378 <6>[ 0.668821] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10544 22:20:48.873326 <6>[ 0.681113] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10545 22:20:48.883402 <6>[ 0.689926] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10546 22:20:48.889696 <6>[ 0.697895] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10547 22:20:48.899754 <6>[ 0.706592] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10548 22:20:48.906750 <6>[ 0.716328] TCP: Hash tables configured (established 65536 bind 65536)
10549 22:20:48.913027 <6>[ 0.723184] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10550 22:20:48.922604 <6>[ 0.730379] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 22:20:48.929032 <6>[ 0.738081] NET: Registered PF_UNIX/PF_LOCAL protocol family
10552 22:20:48.935871 <6>[ 0.744252] RPC: Registered named UNIX socket transport module.
10553 22:20:48.939055 <6>[ 0.750406] RPC: Registered udp transport module.
10554 22:20:48.945681 <6>[ 0.755340] RPC: Registered tcp transport module.
10555 22:20:48.952385 <6>[ 0.760272] RPC: Registered tcp NFSv4.1 backchannel transport module.
10556 22:20:48.955796 <6>[ 0.766942] PCI: CLS 0 bytes, default 64
10557 22:20:48.959227 <6>[ 0.771325] Unpacking initramfs...
10558 22:20:48.983067 <6>[ 0.790846] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10559 22:20:48.993416 <6>[ 0.799518] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10560 22:20:48.996372 <6>[ 0.808367] kvm [1]: IPA Size Limit: 40 bits
10561 22:20:49.003265 <6>[ 0.812897] kvm [1]: GICv3: no GICV resource entry
10562 22:20:49.006069 <6>[ 0.817916] kvm [1]: disabling GICv2 emulation
10563 22:20:49.012657 <6>[ 0.822599] kvm [1]: GIC system register CPU interface enabled
10564 22:20:49.016185 <6>[ 0.828766] kvm [1]: vgic interrupt IRQ18
10565 22:20:49.022948 <6>[ 0.833118] kvm [1]: VHE mode initialized successfully
10566 22:20:49.029181 <5>[ 0.839571] Initialise system trusted keyrings
10567 22:20:49.036552 <6>[ 0.844399] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10568 22:20:49.043355 <6>[ 0.854446] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10569 22:20:49.049872 <5>[ 0.860836] NFS: Registering the id_resolver key type
10570 22:20:49.053332 <5>[ 0.866139] Key type id_resolver registered
10571 22:20:49.059777 <5>[ 0.870556] Key type id_legacy registered
10572 22:20:49.066295 <6>[ 0.874857] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10573 22:20:49.072925 <6>[ 0.881777] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10574 22:20:49.079459 <6>[ 0.889485] 9p: Installing v9fs 9p2000 file system support
10575 22:20:49.116243 <5>[ 0.927405] Key type asymmetric registered
10576 22:20:49.119687 <5>[ 0.931737] Asymmetric key parser 'x509' registered
10577 22:20:49.129583 <6>[ 0.936877] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10578 22:20:49.132834 <6>[ 0.944493] io scheduler mq-deadline registered
10579 22:20:49.136119 <6>[ 0.949276] io scheduler kyber registered
10580 22:20:49.155147 <6>[ 0.965990] EINJ: ACPI disabled.
10581 22:20:49.186691 <4>[ 0.991193] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 22:20:49.196880 <4>[ 1.001820] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 22:20:49.211467 <6>[ 1.022502] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10584 22:20:49.219644 <6>[ 1.030547] printk: console [ttyS0] disabled
10585 22:20:49.247796 <6>[ 1.055196] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10586 22:20:49.254224 <6>[ 1.064690] printk: console [ttyS0] enabled
10587 22:20:49.257495 <6>[ 1.064690] printk: console [ttyS0] enabled
10588 22:20:49.263792 <6>[ 1.073583] printk: bootconsole [mtk8250] disabled
10589 22:20:49.267478 <6>[ 1.073583] printk: bootconsole [mtk8250] disabled
10590 22:20:49.273845 <6>[ 1.084777] SuperH (H)SCI(F) driver initialized
10591 22:20:49.276737 <6>[ 1.090041] msm_serial: driver initialized
10592 22:20:49.291191 <6>[ 1.098995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10593 22:20:49.301001 <6>[ 1.107552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10594 22:20:49.307900 <6>[ 1.116095] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10595 22:20:49.318133 <6>[ 1.124723] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10596 22:20:49.327565 <6>[ 1.133429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10597 22:20:49.334080 <6>[ 1.142143] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10598 22:20:49.343939 <6>[ 1.150683] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10599 22:20:49.350631 <6>[ 1.159485] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10600 22:20:49.360348 <6>[ 1.168030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10601 22:20:49.373238 <6>[ 1.183908] loop: module loaded
10602 22:20:49.379270 <6>[ 1.189850] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10603 22:20:49.402267 <4>[ 1.213263] mtk-pmic-keys: Failed to locate of_node [id: -1]
10604 22:20:49.409580 <6>[ 1.220284] megasas: 07.719.03.00-rc1
10605 22:20:49.419166 <6>[ 1.230024] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10606 22:20:49.427935 <6>[ 1.238159] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10607 22:20:49.444250 <6>[ 1.254798] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10608 22:20:49.504787 <6>[ 1.309026] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10609 22:20:50.566724 <6>[ 2.378066] Freeing initrd memory: 39200K
10610 22:20:50.577300 <6>[ 2.388329] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10611 22:20:50.588457 <6>[ 2.399206] tun: Universal TUN/TAP device driver, 1.6
10612 22:20:50.591324 <6>[ 2.405254] thunder_xcv, ver 1.0
10613 22:20:50.595184 <6>[ 2.408760] thunder_bgx, ver 1.0
10614 22:20:50.598154 <6>[ 2.412253] nicpf, ver 1.0
10615 22:20:50.608340 <6>[ 2.416253] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10616 22:20:50.611590 <6>[ 2.423728] hns3: Copyright (c) 2017 Huawei Corporation.
10617 22:20:50.618331 <6>[ 2.429313] hclge is initializing
10618 22:20:50.622078 <6>[ 2.432897] e1000: Intel(R) PRO/1000 Network Driver
10619 22:20:50.628487 <6>[ 2.438026] e1000: Copyright (c) 1999-2006 Intel Corporation.
10620 22:20:50.632117 <6>[ 2.444039] e1000e: Intel(R) PRO/1000 Network Driver
10621 22:20:50.638047 <6>[ 2.449255] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10622 22:20:50.644952 <6>[ 2.455442] igb: Intel(R) Gigabit Ethernet Network Driver
10623 22:20:50.651775 <6>[ 2.461091] igb: Copyright (c) 2007-2014 Intel Corporation.
10624 22:20:50.658646 <6>[ 2.466927] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10625 22:20:50.664725 <6>[ 2.473445] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10626 22:20:50.668527 <6>[ 2.479899] sky2: driver version 1.30
10627 22:20:50.674598 <6>[ 2.484881] VFIO - User Level meta-driver version: 0.3
10628 22:20:50.682145 <6>[ 2.493108] usbcore: registered new interface driver usb-storage
10629 22:20:50.688559 <6>[ 2.499550] usbcore: registered new device driver onboard-usb-hub
10630 22:20:50.698533 <6>[ 2.508638] mt6397-rtc mt6359-rtc: registered as rtc0
10631 22:20:50.707415 <6>[ 2.514121] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T22:20:50 UTC (1686003650)
10632 22:20:50.711054 <6>[ 2.523697] i2c_dev: i2c /dev entries driver
10633 22:20:50.727670 <6>[ 2.535302] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10634 22:20:50.735007 <6>[ 2.545494] sdhci: Secure Digital Host Controller Interface driver
10635 22:20:50.741261 <6>[ 2.551933] sdhci: Copyright(c) Pierre Ossman
10636 22:20:50.747822 <6>[ 2.557337] Synopsys Designware Multimedia Card Interface Driver
10637 22:20:50.751318 <6>[ 2.563928] mmc0: CQHCI version 5.10
10638 22:20:50.757772 <6>[ 2.564481] sdhci-pltfm: SDHCI platform and OF driver helper
10639 22:20:50.764595 <6>[ 2.575735] ledtrig-cpu: registered to indicate activity on CPUs
10640 22:20:50.775595 <6>[ 2.583115] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10641 22:20:50.781863 <6>[ 2.590504] usbcore: registered new interface driver usbhid
10642 22:20:50.785161 <6>[ 2.596335] usbhid: USB HID core driver
10643 22:20:50.791654 <6>[ 2.600573] spi_master spi0: will run message pump with realtime priority
10644 22:20:50.837814 <6>[ 2.642259] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10645 22:20:50.856684 <6>[ 2.657558] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10646 22:20:50.859770 <6>[ 2.671130] mmc0: Command Queue Engine enabled
10647 22:20:50.866733 <6>[ 2.672639] cros-ec-spi spi0.0: Chrome EC device registered
10648 22:20:50.873622 <6>[ 2.675881] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10649 22:20:50.876499 <6>[ 2.689072] mmcblk0: mmc0:0001 DA4128 116 GiB
10650 22:20:50.889873 <6>[ 2.697874] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10651 22:20:50.896729 <6>[ 2.701932] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10652 22:20:50.903018 <6>[ 2.709285] NET: Registered PF_PACKET protocol family
10653 22:20:50.906704 <6>[ 2.714448] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10654 22:20:50.913172 <6>[ 2.718523] 9pnet: Installing 9P2000 support
10655 22:20:50.916332 <6>[ 2.724338] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10656 22:20:50.923358 <5>[ 2.728209] Key type dns_resolver registered
10657 22:20:50.929610 <6>[ 2.734044] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10658 22:20:50.933403 <6>[ 2.738391] registered taskstats version 1
10659 22:20:50.936055 <5>[ 2.748812] Loading compiled-in X.509 certificates
10660 22:20:50.970546 <4>[ 2.774918] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10661 22:20:50.980040 <4>[ 2.785647] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 22:20:50.990725 <3>[ 2.798438] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10663 22:20:51.003486 <6>[ 2.814098] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10664 22:20:51.009872 <6>[ 2.820858] xhci-mtk 11200000.usb: xHCI Host Controller
10665 22:20:51.019655 <6>[ 2.826360] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10666 22:20:51.026175 <6>[ 2.834211] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10667 22:20:51.032766 <6>[ 2.843664] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10668 22:20:51.039930 <6>[ 2.849867] xhci-mtk 11200000.usb: xHCI Host Controller
10669 22:20:51.046588 <6>[ 2.855364] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10670 22:20:51.056405 <6>[ 2.863022] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10671 22:20:51.060216 <6>[ 2.870929] hub 1-0:1.0: USB hub found
10672 22:20:51.062670 <6>[ 2.874957] hub 1-0:1.0: 1 port detected
10673 22:20:51.072390 <6>[ 2.879308] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10674 22:20:51.075674 <6>[ 2.888122] hub 2-0:1.0: USB hub found
10675 22:20:51.078756 <6>[ 2.892164] hub 2-0:1.0: 1 port detected
10676 22:20:51.088356 <6>[ 2.899226] mtk-msdc 11f70000.mmc: Got CD GPIO
10677 22:20:51.104569 <6>[ 2.912615] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10678 22:20:51.111631 <6>[ 2.920671] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10679 22:20:51.121009 <4>[ 2.928636] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10680 22:20:51.130962 <6>[ 2.938311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10681 22:20:51.137682 <6>[ 2.946393] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10682 22:20:51.147722 <6>[ 2.954415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10683 22:20:51.154518 <6>[ 2.962336] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10684 22:20:51.160788 <6>[ 2.970158] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10685 22:20:51.170983 <6>[ 2.977985] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10686 22:20:51.181151 <6>[ 2.988685] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10687 22:20:51.190396 <6>[ 2.997085] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10688 22:20:51.197264 <6>[ 3.005439] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10689 22:20:51.207305 <6>[ 3.013786] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10690 22:20:51.213911 <6>[ 3.022129] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10691 22:20:51.223412 <6>[ 3.030472] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10692 22:20:51.230419 <6>[ 3.038816] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10693 22:20:51.240429 <6>[ 3.047160] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10694 22:20:51.246735 <6>[ 3.055502] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10695 22:20:51.256845 <6>[ 3.063846] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10696 22:20:51.263681 <6>[ 3.072190] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10697 22:20:51.273505 <6>[ 3.080534] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10698 22:20:51.280298 <6>[ 3.088877] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10699 22:20:51.290221 <6>[ 3.097220] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10700 22:20:51.296836 <6>[ 3.105569] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10701 22:20:51.303798 <6>[ 3.114482] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10702 22:20:51.310881 <6>[ 3.121904] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10703 22:20:51.317811 <6>[ 3.128940] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10704 22:20:51.328883 <6>[ 3.136043] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10705 22:20:51.334986 <6>[ 3.143338] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10706 22:20:51.344948 <6>[ 3.150180] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10707 22:20:51.351991 <6>[ 3.159318] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10708 22:20:51.361232 <6>[ 3.168445] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10709 22:20:51.371489 <6>[ 3.177747] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10710 22:20:51.380953 <6>[ 3.187222] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10711 22:20:51.390996 <6>[ 3.196702] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10712 22:20:51.397945 <6>[ 3.205830] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10713 22:20:51.407268 <6>[ 3.215307] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10714 22:20:51.417388 <6>[ 3.224434] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10715 22:20:51.427143 <6>[ 3.233743] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10716 22:20:51.437014 <6>[ 3.243910] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10717 22:20:51.447516 <6>[ 3.255385] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10718 22:20:51.495094 <6>[ 3.303033] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10719 22:20:51.649198 <6>[ 3.460572] hub 1-1:1.0: USB hub found
10720 22:20:51.652735 <6>[ 3.465029] hub 1-1:1.0: 4 ports detected
10721 22:20:51.775602 <6>[ 3.583056] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10722 22:20:51.799579 <6>[ 3.611093] hub 2-1:1.0: USB hub found
10723 22:20:51.802968 <6>[ 3.615488] hub 2-1:1.0: 3 ports detected
10724 22:20:51.974773 <6>[ 3.783031] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10725 22:20:52.105860 <6>[ 3.916908] hub 1-1.1:1.0: USB hub found
10726 22:20:52.109647 <6>[ 3.921181] hub 1-1.1:1.0: 4 ports detected
10727 22:20:52.222937 <6>[ 4.030809] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10728 22:20:52.355603 <6>[ 4.167092] hub 1-1.4:1.0: USB hub found
10729 22:20:52.359168 <6>[ 4.171756] hub 1-1.4:1.0: 2 ports detected
10730 22:20:52.434727 <6>[ 4.243031] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10731 22:20:52.623319 <6>[ 4.431030] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10732 22:20:52.707601 <3>[ 4.519121] usb 1-1.1.4: device descriptor read/64, error -32
10733 22:20:52.899851 <3>[ 4.711239] usb 1-1.1.4: device descriptor read/64, error -32
10734 22:20:53.094748 <6>[ 4.903035] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10735 22:20:53.282807 <6>[ 5.091034] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10736 22:20:53.367795 <3>[ 5.179246] usb 1-1.1.4: device descriptor read/64, error -32
10737 22:20:53.559542 <3>[ 5.371243] usb 1-1.1.4: device descriptor read/64, error -32
10738 22:20:53.672207 <6>[ 5.483456] usb 1-1.1-port4: attempt power cycle
10739 22:20:53.758914 <6>[ 5.567043] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10740 22:20:54.282740 <6>[ 6.091032] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10741 22:20:54.289241 <4>[ 6.098366] usb 1-1.1.4: Device not responding to setup address.
10742 22:20:54.499600 <4>[ 6.311298] usb 1-1.1.4: Device not responding to setup address.
10743 22:20:54.711322 <3>[ 6.523020] usb 1-1.1.4: device not accepting address 10, error -71
10744 22:20:54.798461 <6>[ 6.607040] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10745 22:20:54.805738 <4>[ 6.614486] usb 1-1.1.4: Device not responding to setup address.
10746 22:20:55.016177 <4>[ 6.827290] usb 1-1.1.4: Device not responding to setup address.
10747 22:20:55.227112 <3>[ 7.039048] usb 1-1.1.4: device not accepting address 11, error -71
10748 22:20:55.233970 <3>[ 7.045989] usb 1-1.1-port4: unable to enumerate USB device
10749 22:21:03.747399 <6>[ 15.563600] ALSA device list:
10750 22:21:03.754216 <6>[ 15.566855] No soundcards found.
10751 22:21:03.766568 <6>[ 15.579289] Freeing unused kernel memory: 8384K
10752 22:21:03.769871 <6>[ 15.584221] Run /init as init process
10753 22:21:03.800427 <6>[ 15.613024] NET: Registered PF_INET6 protocol family
10754 22:21:03.807274 <6>[ 15.619293] Segment Routing with IPv6
10755 22:21:03.810449 <6>[ 15.623243] In-situ OAM (IOAM) with IPv6
10756 22:21:03.844747 <30>[ 15.637603] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10757 22:21:03.848423 <30>[ 15.661574] systemd[1]: Detected architecture arm64.
10758 22:21:03.851403
10759 22:21:03.854694 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10760 22:21:03.855126
10761 22:21:03.870772 <30>[ 15.683117] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10762 22:21:04.038418 <30>[ 15.848104] systemd[1]: Queued start job for default target Graphical Interface.
10763 22:21:04.088226 <30>[ 15.900447] systemd[1]: Created slice system-getty.slice.
10764 22:21:04.094738 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10765 22:21:04.110803 <30>[ 15.923628] systemd[1]: Created slice system-modprobe.slice.
10766 22:21:04.117404 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10767 22:21:04.135539 <30>[ 15.948171] systemd[1]: Created slice system-serial\x2dgetty.slice.
10768 22:21:04.145536 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10769 22:21:04.158949 <30>[ 15.971547] systemd[1]: Created slice User and Session Slice.
10770 22:21:04.165932 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10771 22:21:04.186089 <30>[ 15.995591] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10772 22:21:04.196171 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10773 22:21:04.213872 <30>[ 16.023197] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10774 22:21:04.220468 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10775 22:21:04.241213 <30>[ 16.047115] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10776 22:21:04.247553 <30>[ 16.059146] systemd[1]: Reached target Local Encrypted Volumes.
10777 22:21:04.254347 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10778 22:21:04.270222 <30>[ 16.083121] systemd[1]: Reached target Paths.
10779 22:21:04.273340 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10780 22:21:04.290361 <30>[ 16.103066] systemd[1]: Reached target Remote File Systems.
10781 22:21:04.296699 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10782 22:21:04.314829 <30>[ 16.127324] systemd[1]: Reached target Slices.
10783 22:21:04.321269 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10784 22:21:04.334400 <30>[ 16.147080] systemd[1]: Reached target Swap.
10785 22:21:04.338047 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10786 22:21:04.358201 <30>[ 16.167377] systemd[1]: Listening on initctl Compatibility Named Pipe.
10787 22:21:04.364259 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10788 22:21:04.371393 <30>[ 16.182134] systemd[1]: Listening on Journal Audit Socket.
10789 22:21:04.377322 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10790 22:21:04.390530 <30>[ 16.203337] systemd[1]: Listening on Journal Socket (/dev/log).
10791 22:21:04.397919 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10792 22:21:04.414663 <30>[ 16.227350] systemd[1]: Listening on Journal Socket.
10793 22:21:04.421606 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10794 22:21:04.438094 <30>[ 16.247402] systemd[1]: Listening on Network Service Netlink Socket.
10795 22:21:04.444651 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10796 22:21:04.459397 <30>[ 16.271807] systemd[1]: Listening on udev Control Socket.
10797 22:21:04.466623 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10798 22:21:04.482828 <30>[ 16.295736] systemd[1]: Listening on udev Kernel Socket.
10799 22:21:04.489408 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10800 22:21:04.522886 <30>[ 16.335190] systemd[1]: Mounting Huge Pages File System...
10801 22:21:04.529193 Mounting [0;1;39mHuge Pages File System[0m...
10802 22:21:04.544793 <30>[ 16.357227] systemd[1]: Mounting POSIX Message Queue File System...
10803 22:21:04.551110 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10804 22:21:04.568373 <30>[ 16.381072] systemd[1]: Mounting Kernel Debug File System...
10805 22:21:04.574706 Mounting [0;1;39mKernel Debug File System[0m...
10806 22:21:04.593803 <30>[ 16.403354] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10807 22:21:04.605346 <30>[ 16.414332] systemd[1]: Starting Create list of static device nodes for the current kernel...
10808 22:21:04.611794 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10809 22:21:04.628433 <30>[ 16.441385] systemd[1]: Starting Load Kernel Module configfs...
10810 22:21:04.635334 Starting [0;1;39mLoad Kernel Module configfs[0m...
10811 22:21:04.652559 <30>[ 16.465370] systemd[1]: Starting Load Kernel Module drm...
10812 22:21:04.658911 Starting [0;1;39mLoad Kernel Module drm[0m...
10813 22:21:04.678319 <30>[ 16.487274] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10814 22:21:04.688055 <30>[ 16.501143] systemd[1]: Starting Journal Service...
10815 22:21:04.691771 Starting [0;1;39mJournal Service[0m...
10816 22:21:04.708927 <30>[ 16.521743] systemd[1]: Starting Load Kernel Modules...
10817 22:21:04.715500 Starting [0;1;39mLoad Kernel Modules[0m...
10818 22:21:04.736349 <30>[ 16.545913] systemd[1]: Starting Remount Root and Kernel File Systems...
10819 22:21:04.742832 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10820 22:21:04.760951 <30>[ 16.573687] systemd[1]: Starting Coldplug All udev Devices...
10821 22:21:04.767621 Starting [0;1;39mColdplug All udev Devices[0m...
10822 22:21:04.784997 <30>[ 16.597787] systemd[1]: Mounted Huge Pages File System.
10823 22:21:04.791507 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10824 22:21:04.806865 <30>[ 16.619505] systemd[1]: Started Journal Service.
10825 22:21:04.813452 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10826 22:21:04.827902 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10827 22:21:04.846791 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10828 22:21:04.867245 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10829 22:21:04.884091 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10830 22:21:04.900312 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10831 22:21:04.920300 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10832 22:21:04.940295 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10833 22:21:04.954929 See 'systemctl status systemd-remount-fs.service' for details.
10834 22:21:04.999663 Mounting [0;1;39mKernel Configuration File System[0m...
10835 22:21:05.016985 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10836 22:21:05.034379 <46>[ 16.843990] systemd-journald[178]: Received client request to flush runtime journal.
10837 22:21:05.043329 Starting [0;1;39mLoad/Save Random Seed[0m...
10838 22:21:05.065137 Starting [0;1;39mApply Kernel Variables[0m...
10839 22:21:05.081680 Starting [0;1;39mCreate System Users[0m...
10840 22:21:05.103331 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10841 22:21:05.127174 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10842 22:21:05.143634 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10843 22:21:05.160383 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10844 22:21:05.179332 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10845 22:21:05.199732 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10846 22:21:05.258752 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10847 22:21:05.281608 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10848 22:21:05.294798 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10849 22:21:05.314376 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10850 22:21:05.370605 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10851 22:21:05.398105 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10852 22:21:05.423233 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10853 22:21:05.442947 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10854 22:21:05.495870 Starting [0;1;39mNetwork Service[0m...
10855 22:21:05.519728 Starting [0;1;39mNetwork Time Synchronization[0m...
10856 22:21:05.541850 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10857 22:21:05.581601 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10858 22:21:05.595469 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10859 22:21:05.629389 [[0;32m OK [<6>[ 17.440066] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10860 22:21:05.636076 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10861 22:21:05.652007 <3>[ 17.461424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10862 22:21:05.658621 <3>[ 17.469706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10863 22:21:05.668463 <3>[ 17.477942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 22:21:05.675003 <6>[ 17.487173] remoteproc remoteproc0: scp is available
10865 22:21:05.681545 <6>[ 17.493296] remoteproc remoteproc0: powering up scp
10866 22:21:05.687904 <3>[ 17.495149] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 22:21:05.698267 <6>[ 17.498441] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10868 22:21:05.704543 <3>[ 17.506889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 22:21:05.712036 <6>[ 17.514979] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10870 22:21:05.717557 <6>[ 17.521275] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10871 22:21:05.727631 <6>[ 17.521319] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10872 22:21:05.734285 <6>[ 17.521330] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10873 22:21:05.744029 <3>[ 17.523047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 22:21:05.750791 <6>[ 17.540759] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10875 22:21:05.760427 <3>[ 17.544964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 22:21:05.767079 <3>[ 17.544973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 22:21:05.777269 <3>[ 17.567421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 22:21:05.780537 <6>[ 17.584119] usbcore: registered new interface driver r8152
10879 22:21:05.790458 <4>[ 17.591424] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10880 22:21:05.794137 <4>[ 17.591424] Fallback method does not support PEC.
10881 22:21:05.804433 <4>[ 17.594355] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10882 22:21:05.810274 <3>[ 17.615830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 22:21:05.820324 <3>[ 17.621881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 22:21:05.823486 <6>[ 17.625741] mc: Linux media interface: v0.10
10885 22:21:05.830138 <4>[ 17.635085] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10886 22:21:05.840740 <3>[ 17.637400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 22:21:05.847415 <6>[ 17.654096] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10888 22:21:05.853752 <6>[ 17.654109] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10889 22:21:05.860876 <6>[ 17.655832] videodev: Linux video capture interface: v2.00
10890 22:21:05.870632 <3>[ 17.657272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 22:21:05.877058 <3>[ 17.659059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 22:21:05.883647 <6>[ 17.665809] remoteproc remoteproc0: remote processor scp is now up
10893 22:21:05.890021 <6>[ 17.674876] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10894 22:21:05.896884 <3>[ 17.678721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 22:21:05.903725 <6>[ 17.686911] pci_bus 0000:00: root bus resource [bus 00-ff]
10896 22:21:05.910669 <6>[ 17.691281] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10897 22:21:05.920361 <3>[ 17.694854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10898 22:21:05.930531 <6>[ 17.697585] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10899 22:21:05.940364 <6>[ 17.698312] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10900 22:21:05.947196 <6>[ 17.701561] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10901 22:21:05.953931 <3>[ 17.708218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 22:21:05.963572 <6>[ 17.716522] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10903 22:21:05.973863 <3>[ 17.722046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 22:21:05.979989 <6>[ 17.729457] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10905 22:21:05.986679 <3>[ 17.742722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 22:21:05.993483 <6>[ 17.747808] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10907 22:21:06.003012 <6>[ 17.767760] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10908 22:21:06.009519 <6>[ 17.771909] pci 0000:00:00.0: supports D1 D2
10909 22:21:06.016473 <6>[ 17.785457] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10910 22:21:06.023457 <6>[ 17.789851] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10911 22:21:06.032819 <6>[ 17.792375] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10912 22:21:06.039206 <3>[ 17.796328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 22:21:06.049061 <6>[ 17.802541] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10914 22:21:06.055628 <6>[ 17.804775] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10915 22:21:06.059078 <6>[ 17.806090] Bluetooth: Core ver 2.22
10916 22:21:06.065630 <6>[ 17.806236] NET: Registered PF_BLUETOOTH protocol family
10917 22:21:06.072573 <6>[ 17.806239] Bluetooth: HCI device and connection manager initialized
10918 22:21:06.075575 <6>[ 17.806272] Bluetooth: HCI socket layer initialized
10919 22:21:06.082885 <6>[ 17.806282] Bluetooth: L2CAP socket layer initialized
10920 22:21:06.086426 <6>[ 17.806335] Bluetooth: SCO socket layer initialized
10921 22:21:06.092817 <6>[ 17.821901] usbcore: registered new interface driver cdc_ether
10922 22:21:06.100144 <6>[ 17.826138] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10923 22:21:06.109561 <3>[ 17.826159] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10924 22:21:06.116642 <4>[ 17.829775] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10925 22:21:06.126755 <4>[ 17.829787] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10926 22:21:06.133654 <6>[ 17.841605] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10927 22:21:06.140701 <6>[ 17.849560] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10928 22:21:06.146790 <6>[ 17.849969] usbcore: registered new interface driver r8153_ecm
10929 22:21:06.159725 <6>[ 17.859747] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10930 22:21:06.166622 <6>[ 17.866561] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10931 22:21:06.173387 <6>[ 17.867575] usbcore: registered new interface driver btusb
10932 22:21:06.179837 <6>[ 17.867733] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10933 22:21:06.190329 <4>[ 17.868413] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10934 22:21:06.193866 <3>[ 17.868425] Bluetooth: hci0: Failed to load firmware file (-2)
10935 22:21:06.200146 <3>[ 17.868431] Bluetooth: hci0: Failed to set up firmware (-2)
10936 22:21:06.210792 <4>[ 17.868436] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10937 22:21:06.217041 <6>[ 17.873192] usbcore: registered new interface driver uvcvideo
10938 22:21:06.223312 <6>[ 17.876802] pci 0000:01:00.0: supports D1 D2
10939 22:21:06.230764 <3>[ 17.910218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10940 22:21:06.237090 <6>[ 17.910559] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10941 22:21:06.240546 <6>[ 17.931125] r8152 1-1.1.1:1.0 eth0: v1.12.13
10942 22:21:06.251020 <3>[ 17.948302] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 22:21:06.257504 <6>[ 17.950938] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10944 22:21:06.264052 <6>[ 17.963573] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10945 22:21:06.270775 <6>[ 17.964466] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10946 22:21:06.281440 <3>[ 18.006121] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 22:21:06.288218 <3>[ 18.006970] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10948 22:21:06.297820 <6>[ 18.007083] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10949 22:21:06.304183 <6>[ 18.007099] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10950 22:21:06.314148 <3>[ 18.068662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 22:21:06.321781 <6>[ 18.068884] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10952 22:21:06.330803 <3>[ 18.069354] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10953 22:21:06.338342 <3>[ 18.100393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 22:21:06.345046 <6>[ 18.106499] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10955 22:21:06.351500 <6>[ 18.164293] pci 0000:00:00.0: PCI bridge to [bus 01]
10956 22:21:06.357989 <6>[ 18.169521] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10957 22:21:06.368113 Startin<6>[ 18.177718] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10958 22:21:06.375431 g [0;1;39mLoad/<6>[ 18.186242] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10959 22:21:06.382277 Save Screen …o<6>[ 18.193311] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10960 22:21:06.385134 f leds:white:kbd_backlight[0m...
10961 22:21:06.402142 <5>[ 18.212131] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10962 22:21:06.423684 <5>[ 18.233061] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10963 22:21:06.431154 <4>[ 18.239977] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10964 22:21:06.437286 <6>[ 18.248872] cfg80211: failed to load regulatory.db
10965 22:21:06.440409 Starting [0;1;39mNetwork Name Resolution[0m...
10966 22:21:06.456296 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10967 22:21:06.484278 <6>[ 18.293483] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10968 22:21:06.490503 <6>[ 18.301048] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10969 22:21:06.497245 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10970 22:21:06.513648 <6>[ 18.326834] mt7921e 0000:01:00.0: ASIC revision: 79610010
10971 22:21:06.520488 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10972 22:21:06.559054 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10973 22:21:06.620278 <4>[ 18.426869] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10974 22:21:06.741015 [[0;32m OK [0m] Reached targ<4>[ 18.545193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 22:21:06.744199 et [0;1;39mBluetooth[0m.
10976 22:21:06.759192 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10977 22:21:06.781163 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10978 22:21:06.794353 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10979 22:21:06.813675 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10980 22:21:06.827025 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10981 22:21:06.846862 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10982 22:21:06.859774 <4>[ 18.665555] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 22:21:06.866213 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10984 22:21:06.882981 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10985 22:21:06.902783 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10986 22:21:06.914626 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10987 22:21:06.931049 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10988 22:21:06.950749 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10989 22:21:06.980558 <4>[ 18.786093] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 22:21:07.007806 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10991 22:21:07.033713 Starting [0;1;39mUser Login Management[0m...
10992 22:21:07.049249 Starting [0;1;39mPermit User Sessions[0m...
10993 22:21:07.066524 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10994 22:21:07.088780 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10995 22:21:07.102338 <4>[ 18.907222] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 22:21:07.113289 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10997 22:21:07.134043 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10998 22:21:07.150138 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10999 22:21:07.166500 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11000 22:21:07.183746 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11001 22:21:07.199853 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11002 22:21:07.207487 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11003 22:21:07.224228 <4>[ 19.029956] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11004 22:21:07.274673 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11005 22:21:07.299744 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11006 22:21:07.343054 <4>[ 19.149445] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 22:21:07.357596
11008 22:21:07.358149
11009 22:21:07.360258 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11010 22:21:07.360870
11011 22:21:07.363762 debian-bullseye-arm64 login: root (automatic login)
11012 22:21:07.364316
11013 22:21:07.364746
11014 22:21:07.383579 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 22:04:07 UTC 2023 aarch64
11015 22:21:07.384151
11016 22:21:07.389792 The programs included with the Debian GNU/Linux system are free software;
11017 22:21:07.396587 the exact distribution terms for each program are described in the
11018 22:21:07.400473 individual files in /usr/share/doc/*/copyright.
11019 22:21:07.401075
11020 22:21:07.406206 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11021 22:21:07.409223 permitted by applicable law.
11022 22:21:07.410402 Matched prompt #10: / #
11024 22:21:07.411495 Setting prompt string to ['/ #']
11025 22:21:07.411961 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11027 22:21:07.413072 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11028 22:21:07.413550 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11029 22:21:07.413952 Setting prompt string to ['/ #']
11030 22:21:07.414290 Forcing a shell prompt, looking for ['/ #']
11032 22:21:07.465131 / #
11033 22:21:07.465795 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11034 22:21:07.466254 Waiting using forced prompt support (timeout 00:02:30)
11035 22:21:07.467301 <4>[ 19.273509] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11036 22:21:07.509185
11037 22:21:07.510133 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11038 22:21:07.510651 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11039 22:21:07.511217 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11040 22:21:07.511881 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11041 22:21:07.512369 end: 2 depthcharge-action (duration 00:01:23) [common]
11042 22:21:07.512922 start: 3 lava-test-retry (timeout 00:08:18) [common]
11043 22:21:07.513394 start: 3.1 lava-test-shell (timeout 00:08:18) [common]
11044 22:21:07.513786 Using namespace: common
11046 22:21:07.615065 / # #
11047 22:21:07.615737 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11048 22:21:07.616344 #<4>[ 19.393333] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11049 22:21:07.621411
11050 22:21:07.622167 Using /lava-10597286
11052 22:21:07.723428 / # export SHELL=/bin/sh
11053 22:21:07.724217 export SHELL=/bin/sh<4>[ 19.512746] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11054 22:21:07.724722 <6>[ 19.515248] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11055 22:21:07.725096 <6>[ 19.531798] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11056 22:21:07.729340
11058 22:21:07.874300 / # . /lava-10597286/environment
11059 22:21:07.875129 <3>[ 19.638959] mt7921e 0000:01:00.0: hardware init failed
11060 22:21:07.881219 . /lava-10597286/environment
11062 22:21:07.983011 / # /lava-10597286/bin/lava-test-runner /lava-10597286/0
11063 22:21:07.983657 Test shell timeout: 10s (minimum of the action and connection timeout)
11064 22:21:07.990243 /lava-10597286/bin/lava-test-runner /lava-10597286/0
11065 22:21:08.011156 + export TESTRUN_ID=0_v4l2-compliance-uvc
11066 22:21:08.014410 + cd /lava-10597286/0/tests/0_v4l2-compliance-uvc
11067 22:21:08.014879 + cat uuid
11068 22:21:08.017604 + UUID=10597286_1.5.2.3.1
11069 22:21:08.018071 + set +x
11070 22:21:08.024607 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10597286_1.5.2.3.1>
11071 22:21:08.025472 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10597286_1.5.2.3.1
11072 22:21:08.025881 Starting test lava.0_v4l2-compliance-uvc (10597286_1.5.2.3.1)
11073 22:21:08.026338 Skipping test definition patterns.
11074 22:21:08.027525 + /usr/bin/v4l2-parser.sh -d uvcvideo
11075 22:21:08.034514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11076 22:21:08.035092 device: /dev/video0
11077 22:21:08.035734 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11079 22:21:12.087390 <4>[ 23.899974] ------------[ cut here ]------------
11080 22:21:12.093247 <4>[ 23.904898] get_vaddr_frames() cannot follow VM_IO mapping
11081 22:21:12.103419 <4>[ 23.905043] WARNING: CPU: 1 PID: 304 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11082 22:21:12.153336 <4>[ 23.923146] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc btusb mtk_vcodec_common mtk_vpu btintel r8153_ecm v4l2_mem2mem btmtk uvcvideo videobuf2_vmalloc btrtl videobuf2_dma_contig btbcm videobuf2_memops bluetooth cdc_ether videobuf2_v4l2 videobuf2_common usbnet ecdh_generic cros_ec_rpmsg ecc crct10dif_ce videodev rfkill elants_i2c mc r8152 elan_i2c hid_google_hammer sbs_battery pcie_mediatek_gen3 cros_ec_typec cros_ec_chardev hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11083 22:21:12.163069 <4>[ 23.972531] CPU: 1 PID: 304 Comm: v4l2-compliance Not tainted 6.1.31 #1
11084 22:21:12.167039 <4>[ 23.979396] Hardware name: Google Spherion (rev0 - 3) (DT)
11085 22:21:12.172441 <4>[ 23.985129] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11086 22:21:12.179505 <4>[ 23.992341] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11087 22:21:12.186412 <4>[ 23.998432] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11088 22:21:12.189130 <4>[ 24.004522] sp : ffff8000091a3810
11089 22:21:12.196207 <4>[ 24.008086] x29: ffff8000091a3810 x28: ffffb547dd2d0000 x27: ffffb547dd2cc238
11090 22:21:12.205911 <4>[ 24.015474] x26: 0000000000000000 x25: ffffb547dd2d04c0 x24: ffff466e40174538
11091 22:21:12.212470 <4>[ 24.022861] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11092 22:21:12.219124 <4>[ 24.030247] x20: 00000000fffffff2 x19: ffff466e4ee2b000 x18: fffffffffffe99f8
11093 22:21:12.225668 <4>[ 24.037633] x17: 0000000000000000 x16: ffffb547ea28bb60 x15: 0000000000000038
11094 22:21:12.235541 <4>[ 24.045020] x14: ffffb547ec9c34a8 x13: 000000000000066f x12: 0000000000000225
11095 22:21:12.242797 <4>[ 24.052407] x11: fffffffffffe99f8 x10: fffffffffffe99c0 x9 : 00000000fffff225
11096 22:21:12.248846 <4>[ 24.059794] x8 : ffffb547ec9c34a8 x7 : ffffb547eca1b4a8 x6 : 00000000000019bc
11097 22:21:12.255547 <4>[ 24.067180] x5 : ffff466f7ef27a18 x4 : 00000000fffff225 x3 : ffff912792c24000
11098 22:21:12.265243 <4>[ 24.074566] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff466e49fae740
11099 22:21:12.265815 <4>[ 24.081953] Call trace:
11100 22:21:12.271917 <4>[ 24.084650] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11101 22:21:12.278479 <4>[ 24.090393] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11102 22:21:12.285312 <4>[ 24.096395] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11103 22:21:12.291604 <4>[ 24.102917] __prepare_userptr+0x280/0x410 [videobuf2_common]
11104 22:21:12.295121 <4>[ 24.108921] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11105 22:21:12.301444 <4>[ 24.114577] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11106 22:21:12.308913 <4>[ 24.120234] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11107 22:21:12.311655 <4>[ 24.125128] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11108 22:21:12.318262 <4>[ 24.130193] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11109 22:21:12.321837 <4>[ 24.135069] v4l_qbuf+0x48/0x60 [videodev]
11110 22:21:12.327913 <4>[ 24.139489] __video_do_ioctl+0x184/0x3d0 [videodev]
11111 22:21:12.331457 <4>[ 24.144733] video_usercopy+0x358/0x680 [videodev]
11112 22:21:12.337816 <4>[ 24.149803] video_ioctl2+0x18/0x30 [videodev]
11113 22:21:12.340916 <4>[ 24.154526] v4l2_ioctl+0x40/0x60 [videodev]
11114 22:21:12.344612 <4>[ 24.159076] __arm64_sys_ioctl+0xa8/0xf0
11115 22:21:12.348030 <4>[ 24.163256] invoke_syscall+0x48/0x114
11116 22:21:12.354418 <4>[ 24.167261] el0_svc_common.constprop.0+0x44/0xec
11117 22:21:12.357313 <4>[ 24.172217] do_el0_svc+0x2c/0xd0
11118 22:21:12.361322 <4>[ 24.175783] el0_svc+0x2c/0x84
11119 22:21:12.364993 <4>[ 24.179093] el0t_64_sync_handler+0xb8/0xc0
11120 22:21:12.371227 <4>[ 24.183526] el0t_64_sync+0x18c/0x190
11121 22:21:12.374891 <4>[ 24.187441] ---[ end trace 0000000000000000 ]---
11122 22:21:14.796131 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11123 22:21:14.806234 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11124 22:21:14.812072
11125 22:21:14.824102 Compliance test for uvcvideo device /dev/video0:
11126 22:21:14.830370
11127 22:21:14.839300 Driver Info:
11128 22:21:14.849375 Driver name : uvcvideo
11129 22:21:14.862354 Card type : HD User Facing: HD User Facing
11130 22:21:14.872388 Bus info : usb-11200000.usb-1.4.1
11131 22:21:14.879940 Driver version : 6.1.31
11132 22:21:14.889277 Capabilities : 0x84a00001
11133 22:21:14.901817 Metadata Capture
11134 22:21:14.912925 Streaming
11135 22:21:14.923094 Extended Pix Format
11136 22:21:14.933068 Device Capabilities
11137 22:21:14.942963 Device Caps : 0x04200001
11138 22:21:14.955908 Streaming
11139 22:21:14.964831 Extended Pix Format
11140 22:21:14.975436 Media Driver Info:
11141 22:21:14.984775 Driver name : uvcvideo
11142 22:21:14.999345 Model : HD User Facing: HD User Facing
11143 22:21:15.005184 Serial : 200901010001
11144 22:21:15.018491 Bus info : usb-11200000.usb-1.4.1
11145 22:21:15.025573 Media version : 6.1.31
11146 22:21:15.038657 Hardware revision: 0x00009758 (38744)
11147 22:21:15.045157 Driver version : 6.1.31
11148 22:21:15.053701 Interface Info:
11149 22:21:15.068816 <LAVA_SIGNAL_TESTSET START Interface-Info>
11150 22:21:15.069382 ID : 0x03000002
11151 22:21:15.070079 Received signal: <TESTSET> START Interface-Info
11152 22:21:15.070477 Starting test_set Interface-Info
11153 22:21:15.076854 Type : V4L Video
11154 22:21:15.086362 Entity Info:
11155 22:21:15.092876 <LAVA_SIGNAL_TESTSET STOP>
11156 22:21:15.093708 Received signal: <TESTSET> STOP
11157 22:21:15.094110 Closing test_set Interface-Info
11158 22:21:15.102466 <LAVA_SIGNAL_TESTSET START Entity-Info>
11159 22:21:15.103047 ID : 0x00000001 (1)
11160 22:21:15.103687 Received signal: <TESTSET> START Entity-Info
11161 22:21:15.104055 Starting test_set Entity-Info
11162 22:21:15.113890 Name : HD User Facing: HD User Facing
11163 22:21:15.120020 Function : V4L2 I/O
11164 22:21:15.129696 Flags : default
11165 22:21:15.139285 Pad 0x01000007 : 0: Sink
11166 22:21:15.158149 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11167 22:21:15.158709
11168 22:21:15.167407 Required ioctls:
11169 22:21:15.173689 <LAVA_SIGNAL_TESTSET STOP>
11170 22:21:15.174527 Received signal: <TESTSET> STOP
11171 22:21:15.174907 Closing test_set Entity-Info
11172 22:21:15.182976 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11173 22:21:15.183814 Received signal: <TESTSET> START Required-ioctls
11174 22:21:15.184203 Starting test_set Required-ioctls
11175 22:21:15.186104 test MC information (see 'Media Driver Info' above): OK
11176 22:21:15.209422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11177 22:21:15.210226 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11179 22:21:15.212650 test VIDIOC_QUERYCAP: OK
11180 22:21:15.229768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11181 22:21:15.230613 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11183 22:21:15.232980 test invalid ioctls: OK
11184 22:21:15.252197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11185 22:21:15.252802
11186 22:21:15.253433 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11188 22:21:15.262105 Allow for multiple opens:
11189 22:21:15.269416 <LAVA_SIGNAL_TESTSET STOP>
11190 22:21:15.270241 Received signal: <TESTSET> STOP
11191 22:21:15.270628 Closing test_set Required-ioctls
11192 22:21:15.276989 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11193 22:21:15.277815 Received signal: <TESTSET> START Allow-for-multiple-opens
11194 22:21:15.278299 Starting test_set Allow-for-multiple-opens
11195 22:21:15.280033 test second /dev/video0 open: OK
11196 22:21:15.301558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11197 22:21:15.302385 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11199 22:21:15.304137 test VIDIOC_QUERYCAP: OK
11200 22:21:15.325885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11201 22:21:15.326726 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11203 22:21:15.328318 test VIDIOC_G/S_PRIORITY: OK
11204 22:21:15.350536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11205 22:21:15.351363 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11207 22:21:15.353794 test for unlimited opens: OK
11208 22:21:15.373560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11209 22:21:15.374111
11210 22:21:15.374749 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11212 22:21:15.383671 Debug ioctls:
11213 22:21:15.390462 <LAVA_SIGNAL_TESTSET STOP>
11214 22:21:15.391279 Received signal: <TESTSET> STOP
11215 22:21:15.391665 Closing test_set Allow-for-multiple-opens
11216 22:21:15.400111 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11217 22:21:15.400970 Received signal: <TESTSET> START Debug-ioctls
11218 22:21:15.401363 Starting test_set Debug-ioctls
11219 22:21:15.403079 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11220 22:21:15.424374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11221 22:21:15.425249 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11223 22:21:15.431375 test VIDIOC_LOG_STATUS: OK (Not Supported)
11224 22:21:15.448569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11225 22:21:15.449126
11226 22:21:15.449762 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11228 22:21:15.458330 Input ioctls:
11229 22:21:15.465105 <LAVA_SIGNAL_TESTSET STOP>
11230 22:21:15.465835 Received signal: <TESTSET> STOP
11231 22:21:15.466219 Closing test_set Debug-ioctls
11232 22:21:15.474319 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11233 22:21:15.475140 Received signal: <TESTSET> START Input-ioctls
11234 22:21:15.475536 Starting test_set Input-ioctls
11235 22:21:15.477957 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11236 22:21:15.502703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11237 22:21:15.503518 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11239 22:21:15.505609 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11240 22:21:15.523714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11241 22:21:15.524564 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11243 22:21:15.529968 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11244 22:21:15.547903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11245 22:21:15.548722 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11247 22:21:15.554018 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11248 22:21:15.571472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11249 22:21:15.572349 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11251 22:21:15.575456 test VIDIOC_G/S/ENUMINPUT: OK
11252 22:21:15.596429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11253 22:21:15.597296 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11255 22:21:15.602511 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11256 22:21:15.620311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11257 22:21:15.621180 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11259 22:21:15.623314 Inputs: 1 Audio Inputs: 0 Tuners: 0
11260 22:21:15.629816
11261 22:21:15.645393 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11262 22:21:15.665532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11263 22:21:15.666326 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11265 22:21:15.672381 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11266 22:21:15.689281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11267 22:21:15.690093 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11269 22:21:15.695381 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11270 22:21:15.712793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11271 22:21:15.713588 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11273 22:21:15.719576 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11274 22:21:15.738174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11275 22:21:15.738985 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11277 22:21:15.744873 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11278 22:21:15.763663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11279 22:21:15.764215
11280 22:21:15.764924 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11282 22:21:15.782189 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11283 22:21:15.803701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11284 22:21:15.804568 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11286 22:21:15.810161 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11287 22:21:15.831404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11288 22:21:15.832232 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11290 22:21:15.833904 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11291 22:21:15.852134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11292 22:21:15.852967 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11294 22:21:15.855867 test VIDIOC_G/S_EDID: OK (Not Supported)
11295 22:21:15.876813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11296 22:21:15.877373
11297 22:21:15.878005 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11299 22:21:15.885433 Control ioctls (Input 0):
11300 22:21:15.891893 <LAVA_SIGNAL_TESTSET STOP>
11301 22:21:15.892732 Received signal: <TESTSET> STOP
11302 22:21:15.893123 Closing test_set Input-ioctls
11303 22:21:15.900795 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11304 22:21:15.901604 Received signal: <TESTSET> START Control-ioctls-Input-0
11305 22:21:15.902002 Starting test_set Control-ioctls-Input-0
11306 22:21:15.904343 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11307 22:21:15.928236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11308 22:21:15.928826 test VIDIOC_QUERYCTRL: OK
11309 22:21:15.929462 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11311 22:21:15.948279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11312 22:21:15.949151 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11314 22:21:15.950666 test VIDIOC_G/S_CTRL: OK
11315 22:21:15.972073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11316 22:21:15.972875 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11318 22:21:15.975968 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11319 22:21:15.996468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11320 22:21:15.997357 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11322 22:21:16.002737 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11323 22:21:16.023495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11324 22:21:16.024322 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11326 22:21:16.026637 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11327 22:21:16.044594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11328 22:21:16.045430 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11330 22:21:16.047728 Standard Controls: 16 Private Controls: 0
11331 22:21:16.054240
11332 22:21:16.064354 Format ioctls (Input 0):
11333 22:21:16.070842 <LAVA_SIGNAL_TESTSET STOP>
11334 22:21:16.071665 Received signal: <TESTSET> STOP
11335 22:21:16.072058 Closing test_set Control-ioctls-Input-0
11336 22:21:16.080456 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11337 22:21:16.081357 Received signal: <TESTSET> START Format-ioctls-Input-0
11338 22:21:16.081768 Starting test_set Format-ioctls-Input-0
11339 22:21:16.084115 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11340 22:21:16.107534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11341 22:21:16.108368 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11343 22:21:16.110558 test VIDIOC_G/S_PARM: OK
11344 22:21:16.127862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11345 22:21:16.128716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11347 22:21:16.131330 test VIDIOC_G_FBUF: OK (Not Supported)
11348 22:21:16.152483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11349 22:21:16.153345 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11351 22:21:16.155979 test VIDIOC_G_FMT: OK
11352 22:21:16.176553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11353 22:21:16.177415 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11355 22:21:16.179447 test VIDIOC_TRY_FMT: OK
11356 22:21:16.200462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11357 22:21:16.201325 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11359 22:21:16.206988 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11360 22:21:16.211291 test VIDIOC_S_FMT: OK
11361 22:21:16.235421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11362 22:21:16.236245 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11364 22:21:16.238620 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11365 22:21:16.259590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11366 22:21:16.260403 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11368 22:21:16.262937 test Cropping: OK (Not Supported)
11369 22:21:16.295263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11370 22:21:16.296136 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11372 22:21:16.299027 test Composing: OK (Not Supported)
11373 22:21:16.320778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11374 22:21:16.321601 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11376 22:21:16.323329 test Scaling: OK (Not Supported)
11377 22:21:16.344835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11378 22:21:16.345486
11379 22:21:16.346119 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11381 22:21:16.353184 Codec ioctls (Input 0):
11382 22:21:16.359437 <LAVA_SIGNAL_TESTSET STOP>
11383 22:21:16.360258 Received signal: <TESTSET> STOP
11384 22:21:16.360661 Closing test_set Format-ioctls-Input-0
11385 22:21:16.368609 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11386 22:21:16.369346 Received signal: <TESTSET> START Codec-ioctls-Input-0
11387 22:21:16.369766 Starting test_set Codec-ioctls-Input-0
11388 22:21:16.372180 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11389 22:21:16.393327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11390 22:21:16.394188 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11392 22:21:16.399446 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11393 22:21:16.417485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11394 22:21:16.418341 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11396 22:21:16.424769 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11397 22:21:16.442672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11398 22:21:16.443251
11399 22:21:16.444000 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11401 22:21:16.451729 Buffer ioctls (Input 0):
11402 22:21:16.458532 <LAVA_SIGNAL_TESTSET STOP>
11403 22:21:16.459396 Received signal: <TESTSET> STOP
11404 22:21:16.459875 Closing test_set Codec-ioctls-Input-0
11405 22:21:16.467823 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11406 22:21:16.468600 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11407 22:21:16.469022 Starting test_set Buffer-ioctls-Input-0
11408 22:21:16.471056 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11409 22:21:16.495074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11410 22:21:16.495648 test VIDIOC_EXPBUF: OK
11411 22:21:16.496396 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11413 22:21:16.516347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11414 22:21:16.517262 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11416 22:21:16.520014 test Requests: OK (Not Supported)
11417 22:21:16.540211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11418 22:21:16.540834
11419 22:21:16.541585 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11421 22:21:16.550208 Test input 0:
11422 22:21:16.559955
11423 22:21:16.569852 Streaming ioctls:
11424 22:21:16.576700 <LAVA_SIGNAL_TESTSET STOP>
11425 22:21:16.577527 Received signal: <TESTSET> STOP
11426 22:21:16.577913 Closing test_set Buffer-ioctls-Input-0
11427 22:21:16.586538 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11428 22:21:16.587366 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11429 22:21:16.587759 Starting test_set Streaming-ioctls_Test-input-0
11430 22:21:16.590334 test read/write: OK (Not Supported)
11431 22:21:16.610597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11432 22:21:16.611409 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11434 22:21:16.613495 test blocking wait: OK
11435 22:21:16.634035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11436 22:21:16.634868 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11438 22:21:16.643993 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11439 22:21:16.648117 test MMAP (no poll): FAIL
11440 22:21:16.668659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11441 22:21:16.669490 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11443 22:21:16.678100 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11444 22:21:16.678573 test MMAP (select): FAIL
11445 22:21:16.702183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11446 22:21:16.703095 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11448 22:21:16.712105 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11449 22:21:16.712711 test MMAP (epoll): FAIL
11450 22:21:16.737662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11451 22:21:16.738227
11452 22:21:16.738859 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11454 22:21:16.749040
11455 22:21:16.922293
11456 22:21:16.928664 test USERPTR (no poll): OK
11457 22:21:16.952177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11458 22:21:16.952787
11459 22:21:16.953430 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11461 22:21:16.965042
11462 22:21:17.120414
11463 22:21:17.125774 test USERPTR (select): OK
11464 22:21:17.148682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11465 22:21:17.149488 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11467 22:21:17.155053 test DMABUF: Cannot test, specify --expbuf-device
11468 22:21:17.159076
11469 22:21:17.177107 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11470 22:21:17.179825 <LAVA_TEST_RUNNER EXIT>
11471 22:21:17.180645 ok: lava_test_shell seems to have completed
11472 22:21:17.181038 Marking unfinished test run as failed
11474 22:21:17.186453 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11475 22:21:17.187149 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11476 22:21:17.187615 end: 3 lava-test-retry (duration 00:00:10) [common]
11477 22:21:17.188084 start: 4 finalize (timeout 00:08:08) [common]
11478 22:21:17.188609 start: 4.1 power-off (timeout 00:00:30) [common]
11479 22:21:17.189426 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11480 22:21:17.310697 >> Command sent successfully.
11481 22:21:17.315164 Returned 0 in 0 seconds
11482 22:21:17.416103 end: 4.1 power-off (duration 00:00:00) [common]
11484 22:21:17.417676 start: 4.2 read-feedback (timeout 00:08:08) [common]
11485 22:21:17.418977 Listened to connection for namespace 'common' for up to 1s
11486 22:21:18.419612 Finalising connection for namespace 'common'
11487 22:21:18.420284 Disconnecting from shell: Finalise
11488 22:21:18.420753 / #
11489 22:21:18.521755 end: 4.2 read-feedback (duration 00:00:01) [common]
11490 22:21:18.522463 end: 4 finalize (duration 00:00:01) [common]
11491 22:21:18.523071 Cleaning after the job
11492 22:21:18.523577 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/ramdisk
11493 22:21:18.530481 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/kernel
11494 22:21:18.541277 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/dtb
11495 22:21:18.541461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10597286/tftp-deploy-lv8lul9s/modules
11496 22:21:18.546635 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10597286
11497 22:21:18.600119 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10597286
11498 22:21:18.600301 Job finished correctly