Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 12:26:31.508133 lava-dispatcher, installed at version: 2023.01
2 12:26:31.508348 start: 0 validate
3 12:26:31.508464 Start time: 2023-06-06 12:26:31.508457+00:00 (UTC)
4 12:26:31.509532 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image exists
5 12:26:31.870817 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 12:26:32.051395 cmd: ['docker', 'pull', 'kernelci/qemu']
7 12:26:32.051585 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 12:26:32.210503 >> Using default tag: latest
9 12:26:33.311097 >> latest: Pulling from kernelci/qemu
10 12:26:33.350009 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 12:26:33.350148 >> Status: Image is up to date for kernelci/qemu:latest
12 12:26:33.383288 >> docker.io/kernelci/qemu:latest
13 12:26:33.386902 Returned 0 in 1 seconds
14 12:26:33.524499 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 12:26:33.524965 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 12:26:37.057839 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 12:26:37.058289 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 12:26:39.795942 Returned 0 in 6 seconds
19 12:26:39.897015 validate duration: 8.39
21 12:26:39.897388 start: 1 deployimages (timeout 00:03:00) [common]
22 12:26:39.897531 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 12:26:39.897931 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu
24 12:26:39.898132 makedir: /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin
25 12:26:39.898293 makedir: /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/tests
26 12:26:39.898450 makedir: /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/results
27 12:26:39.898618 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-add-keys
28 12:26:39.898821 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-add-sources
29 12:26:39.899008 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-background-process-start
30 12:26:39.899198 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-background-process-stop
31 12:26:39.899380 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-common-functions
32 12:26:39.899608 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-echo-ipv4
33 12:26:39.899800 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-install-packages
34 12:26:39.899984 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-installed-packages
35 12:26:39.900162 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-os-build
36 12:26:39.900341 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-probe-channel
37 12:26:39.900521 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-probe-ip
38 12:26:39.900750 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-target-ip
39 12:26:39.900972 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-target-mac
40 12:26:39.901267 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-target-storage
41 12:26:39.901515 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-case
42 12:26:39.901756 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-event
43 12:26:39.901985 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-feedback
44 12:26:39.902214 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-raise
45 12:26:39.902445 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-reference
46 12:26:39.902669 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-runner
47 12:26:39.902892 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-set
48 12:26:39.903115 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-test-shell
49 12:26:39.903349 Updating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-install-packages (oe)
50 12:26:39.903610 Updating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/bin/lava-installed-packages (oe)
51 12:26:39.903831 Creating /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/environment
52 12:26:39.904018 LAVA metadata
53 12:26:39.904151 - LAVA_JOB_ID=568844
54 12:26:39.904278 - LAVA_DISPATCHER_IP=172.27.0.2
55 12:26:39.904466 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 12:26:39.904598 skipped lava-vland-overlay
57 12:26:39.904743 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 12:26:39.904896 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 12:26:39.905020 skipped lava-multinode-overlay
60 12:26:39.905160 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 12:26:39.905314 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 12:26:39.905461 Loading test definitions
63 12:26:39.905639 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 12:26:39.905792 Using /lava-568844 at stage 0
65 12:26:39.906354 uuid=568844_1.1.3.1 testdef=None
66 12:26:39.906527 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 12:26:39.906687 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 12:26:39.907550 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 12:26:39.908008 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 12:26:39.909017 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 12:26:39.909481 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 12:26:39.946546 runner path: /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/0/tests/0_timesync-off test_uuid 568844_1.1.3.1
75 12:26:39.946930 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 12:26:39.947557 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 12:26:39.947720 Using /lava-568844 at stage 0
79 12:26:39.947949 Fetching tests from https://github.com/kernelci/test-definitions.git
80 12:26:39.948114 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/0/tests/1_kselftest-arm64_qemu'
81 12:26:42.755205 Running '/usr/bin/git checkout kernelci.org
82 12:26:42.921847 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 12:26:42.922998 uuid=568844_1.1.3.5 testdef=None
84 12:26:42.923249 end: 1.1.3.5 git-repo-action (duration 00:00:03) [common]
86 12:26:42.923789 start: 1.1.3.6 test-overlay (timeout 00:02:57) [common]
87 12:26:42.925604 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 12:26:42.926217 start: 1.1.3.7 test-install-overlay (timeout 00:02:57) [common]
90 12:26:42.928645 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 12:26:42.929163 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:57) [common]
93 12:26:42.931257 runner path: /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/0/tests/1_kselftest-arm64_qemu test_uuid 568844_1.1.3.5
94 12:26:42.931440 BOARD='qemu_arm64-virt-gicv3'
95 12:26:42.931568 BRANCH='cip-gitlab'
96 12:26:42.931689 SKIPFILE='/dev/null'
97 12:26:42.931809 SKIP_INSTALL='True'
98 12:26:42.931927 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
99 12:26:42.932050 TST_CASENAME=''
100 12:26:42.932167 TST_CMDFILES='arm64'
101 12:26:42.932447 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 12:26:42.932915 Creating lava-test-runner.conf files
104 12:26:42.933048 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/568844/lava-overlay-ijd5c8xu/lava-568844/0 for stage 0
105 12:26:42.933232 - 0_timesync-off
106 12:26:42.933372 - 1_kselftest-arm64_qemu
107 12:26:42.933559 end: 1.1.3 test-definition (duration 00:00:03) [common]
108 12:26:42.933749 start: 1.1.4 compress-overlay (timeout 00:02:57) [common]
109 12:26:51.631755 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 12:26:51.631956 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:48) [common]
111 12:26:51.632070 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 12:26:51.632191 end: 1.1 lava-overlay (duration 00:00:12) [common]
113 12:26:51.632292 start: 1.2 apply-overlay-guest (timeout 00:02:48) [common]
114 12:26:51.632378 Overlay: /var/lib/lava/dispatcher/tmp/568844/compress-overlay-k6bctmim/overlay-1.1.4.tar.gz
115 12:27:06.940367 end: 1.2 apply-overlay-guest (duration 00:00:15) [common]
117 12:27:06.941113 start: 1.3 deploy-device-env (timeout 00:02:33) [common]
118 12:27:06.941279 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 12:27:06.941443 start: 1.4 download-retry (timeout 00:02:33) [common]
120 12:27:06.941611 start: 1.4.1 http-download (timeout 00:02:33) [common]
121 12:27:06.942024 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
122 12:27:06.942171 saving as /var/lib/lava/dispatcher/tmp/568844/deployimages-r4n_h3ap/kernel/Image
123 12:27:06.942295 total size: 45746688 (43MB)
124 12:27:06.942453 No compression specified
125 12:27:07.302130 progress 0% (0MB)
126 12:27:08.378574 progress 5% (2MB)
127 12:27:08.758953 progress 10% (4MB)
128 12:27:09.094397 progress 15% (6MB)
129 12:27:09.455744 progress 20% (8MB)
130 12:27:09.631275 progress 25% (10MB)
131 12:27:09.832179 progress 30% (13MB)
132 12:27:10.175578 progress 35% (15MB)
133 12:27:10.531203 progress 40% (17MB)
134 12:27:10.727655 progress 45% (19MB)
135 12:27:11.082761 progress 50% (21MB)
136 12:27:11.432182 progress 55% (24MB)
137 12:27:11.786726 progress 60% (26MB)
138 12:27:11.987712 progress 65% (28MB)
139 12:27:12.331128 progress 70% (30MB)
140 12:27:12.685056 progress 75% (32MB)
141 12:27:12.881707 progress 80% (34MB)
142 12:27:13.225330 progress 85% (37MB)
143 12:27:13.589369 progress 90% (39MB)
144 12:27:13.776219 progress 95% (41MB)
145 12:27:14.129082 progress 100% (43MB)
146 12:27:14.129355 43MB downloaded in 7.19s (6.07MB/s)
147 12:27:14.129580 end: 1.4.1 http-download (duration 00:00:07) [common]
149 12:27:14.129978 end: 1.4 download-retry (duration 00:00:07) [common]
150 12:27:14.130108 start: 1.5 download-retry (timeout 00:02:26) [common]
151 12:27:14.130231 start: 1.5.1 http-download (timeout 00:02:26) [common]
152 12:27:14.130407 Not decompressing ramdisk as can be used compressed.
153 12:27:14.130537 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 12:27:14.130635 saving as /var/lib/lava/dispatcher/tmp/568844/deployimages-r4n_h3ap/ramdisk/rootfs.cpio.gz
155 12:27:14.130729 total size: 88976554 (84MB)
156 12:27:14.130823 No compression specified
157 12:27:14.311073 progress 0% (0MB)
158 12:27:14.867956 progress 5% (4MB)
159 12:27:15.577486 progress 10% (8MB)
160 12:27:16.300359 progress 15% (12MB)
161 12:27:17.020143 progress 20% (17MB)
162 12:27:17.734298 progress 25% (21MB)
163 12:27:18.451657 progress 30% (25MB)
164 12:27:18.999899 progress 35% (29MB)
165 12:27:19.712994 progress 40% (33MB)
166 12:27:20.423166 progress 45% (38MB)
167 12:27:20.982345 progress 50% (42MB)
168 12:27:21.693715 progress 55% (46MB)
169 12:27:22.403457 progress 60% (50MB)
170 12:27:22.955183 progress 65% (55MB)
171 12:27:23.660208 progress 70% (59MB)
172 12:27:24.217315 progress 75% (63MB)
173 12:27:24.921492 progress 80% (67MB)
174 12:27:25.631809 progress 85% (72MB)
175 12:27:26.180101 progress 90% (76MB)
176 12:27:26.890059 progress 95% (80MB)
177 12:27:27.436885 progress 100% (84MB)
178 12:27:27.437267 84MB downloaded in 13.31s (6.38MB/s)
179 12:27:27.437527 end: 1.5.1 http-download (duration 00:00:13) [common]
181 12:27:27.438031 end: 1.5 download-retry (duration 00:00:13) [common]
182 12:27:27.438187 end: 1 deployimages (duration 00:00:48) [common]
183 12:27:27.438361 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 12:27:27.438551 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 12:27:27.438761 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 12:27:27.439140 Extending command line for qcow2 test overlay
187 12:27:27.439854 Pulling docker image
188 12:27:27.440079 cmd: ['docker', 'pull', 'kernelci/qemu']
189 12:27:27.440275 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 12:27:27.601235 >> Using default tag: latest
191 12:27:28.705208 >> latest: Pulling from kernelci/qemu
192 12:27:28.737438 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 12:27:28.737743 >> Status: Image is up to date for kernelci/qemu:latest
194 12:27:28.770653 >> docker.io/kernelci/qemu:latest
195 12:27:28.773839 Returned 0 in 1 seconds
196 12:27:28.911513 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-568844-2.1.1-huisqkbmbp --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/568844/deployimages-r4n_h3ap/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/568844/deployimages-r4n_h3ap/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/568844/apply-overlay-guest-vxbaet0g/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 12:27:29.046034 started a shell command
198 12:27:29.046581 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 12:27:29.046773 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 12:27:29.046953 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 12:27:29.047128 Setting prompt string to ['Linux version [0-9]']
202 12:27:29.047267 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 12:27:30.521874 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 12:27:30.522512 start: 2.2.1 login-action (timeout 00:04:57) [common]
205 12:27:30.522733 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
206 12:27:30.522925 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
207 12:27:30.523082 Using line separator: #'\n'#
208 12:27:30.523208 No login prompt set.
209 12:27:30.523338 Parsing kernel messages
210 12:27:30.523459 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
211 12:27:30.523684 [login-action] Waiting for messages, (timeout 00:04:57)
212 12:27:30.524943 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
213 12:27:30.525097 [ 0.000000] random: crng init done
214 12:27:30.525222 [ 0.000000] Machine model: linux,dummy-virt
215 12:27:30.525341 [ 0.000000] efi: UEFI not found.
216 12:27:30.525458 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 12:27:30.525577 [ 0.000000] printk: bootconsole [pl11] enabled
218 12:27:30.530394 [ 0.000000] NUMA: No NUMA configuration found
219 12:27:30.531100 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 12:27:30.532344 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf3a00-0x7fdf5fff]
221 12:27:30.536717 [ 0.000000] Zone ranges:
222 12:27:30.538248 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 12:27:30.538602 [ 0.000000] DMA32 empty
224 12:27:30.538733 [ 0.000000] Normal empty
225 12:27:30.538874 [ 0.000000] Movable zone start for each node
226 12:27:30.539211 [ 0.000000] Early memory node ranges
227 12:27:30.539778 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 12:27:30.540639 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 12:27:30.559500 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 12:27:30.560731 [ 0.000000] psci: probing for conduit method from DT.
231 12:27:30.561317 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 12:27:30.561491 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 12:27:30.561671 [ 0.000000] psci: Trusted OS migration not required
234 12:27:30.561852 [ 0.000000] psci: SMC Calling Convention v1.0
235 12:27:30.564947 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
236 12:27:30.565534 [ 0.000000] pcpu-alloc: s45224 r8192 d32600 u86016 alloc=21*4096
237 12:27:30.566168 [ 0.000000] pcpu-alloc: [0] 0
238 12:27:30.568932 [ 0.000000] Detected PIPT I-cache on CPU0
239 12:27:30.576528 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 12:27:30.577229 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 12:27:30.577464 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 12:27:30.577738 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 12:27:30.577927 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 12:27:30.578125 [ 0.000000] CPU features: detected: Spectre-v4
245 12:27:30.581901 [ 0.000000] alternatives: applying boot alternatives
246 12:27:30.584614 [ 0.000000] Fallback order for Node 0: 0
247 12:27:30.585025 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 12:27:30.585159 [ 0.000000] Policy zone: DMA
249 12:27:30.585576 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 12:27:30.588064 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 12:27:30.590927 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 12:27:30.591148 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 12:27:30.591552 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 12:27:30.601106 <6>[ 0.000000] Memory: 862480K/1048576K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 153328K reserved, 32768K cma-reserved)
255 12:27:30.606679 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 12:27:30.613510 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 12:27:30.613773 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 12:27:30.613894 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 12:27:30.613990 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 12:27:30.614100 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 12:27:30.614208 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 12:27:30.614540 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 12:27:30.615260 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 12:27:30.621998 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 12:27:30.622334 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 12:27:30.623744 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 12:27:30.624071 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 12:27:30.624852 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 12:27:30.629293 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 12:27:30.630227 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43030000 (indirect, esz 8, psz 64K, shr 1)
271 12:27:30.630558 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43040000 (flat, esz 8, psz 64K, shr 1)
272 12:27:30.631486 <6>[ 0.000000] GICv3: using LPI property table @0x0000000043050000
273 12:27:30.632168 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043060000
274 12:27:30.633449 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 12:27:30.641603 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 12:27:30.642083 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 12:27:30.642823 <6>[ 0.000076] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 12:27:30.662726 <6>[ 0.017513] Console: colour dummy device 80x25
279 12:27:30.666764 <6>[ 0.023538] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 12:27:30.667130 <6>[ 0.024533] pid_max: default: 32768 minimum: 301
281 12:27:30.668787 <6>[ 0.026158] LSM: Security Framework initializing
282 12:27:30.673228 <6>[ 0.030526] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 12:27:30.673604 <6>[ 0.030822] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 12:27:30.705908 <4>[ 0.063304] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 12:27:30.712015 <6>[ 0.069220] cblist_init_generic: Setting adjustable number of callback queues.
286 12:27:30.712156 <6>[ 0.069540] cblist_init_generic: Setting shift to 0 and lim to 1.
287 12:27:30.712864 <6>[ 0.070159] cblist_init_generic: Setting shift to 0 and lim to 1.
288 12:27:30.714316 <6>[ 0.071865] rcu: Hierarchical SRCU implementation.
289 12:27:30.714788 <6>[ 0.072041] rcu: Max phase no-delay instances is 1000.
290 12:27:30.719510 <6>[ 0.076823] Platform MSI: its@8080000 domain created
291 12:27:30.720264 <6>[ 0.077438] PCI/MSI: /intc@8000000/its@8080000 domain created
292 12:27:30.720491 <6>[ 0.078022] fsl-mc MSI: its@8080000 domain created
293 12:27:30.724118 <6>[ 0.081397] EFI services will not be available.
294 12:27:30.725408 <6>[ 0.082264] smp: Bringing up secondary CPUs ...
295 12:27:30.725603 <6>[ 0.082894] smp: Brought up 1 node, 1 CPU
296 12:27:30.725822 <6>[ 0.083040] SMP: Total of 1 processors activated.
297 12:27:30.726027 <6>[ 0.083363] CPU features: detected: Branch Target Identification
298 12:27:30.726197 <6>[ 0.083558] CPU features: detected: 32-bit EL0 Support
299 12:27:30.726449 <6>[ 0.083727] CPU features: detected: 32-bit EL1 Support
300 12:27:30.726622 <6>[ 0.083883] CPU features: detected: ARMv8.4 Translation Table Level
301 12:27:30.726802 <6>[ 0.084119] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 12:27:30.727063 <6>[ 0.084383] CPU features: detected: Common not Private translations
303 12:27:30.727243 <6>[ 0.084566] CPU features: detected: CRC32 instructions
304 12:27:30.727465 <6>[ 0.084720] CPU features: detected: E0PD
305 12:27:30.727647 <6>[ 0.084908] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 12:27:30.727859 <6>[ 0.085123] CPU features: detected: RCpc load-acquire (LDAPR)
307 12:27:30.728043 <6>[ 0.085291] CPU features: detected: LSE atomic instructions
308 12:27:30.728253 <6>[ 0.085427] CPU features: detected: Privileged Access Never
309 12:27:30.728444 <6>[ 0.085620] CPU features: detected: RAS Extension Support
310 12:27:30.728660 <6>[ 0.085785] CPU features: detected: Random Number Generator
311 12:27:30.728818 <6>[ 0.085958] CPU features: detected: Speculation barrier (SB)
312 12:27:30.728954 <6>[ 0.086115] CPU features: detected: Stage-2 Force Write-Back
313 12:27:30.729136 <6>[ 0.086289] CPU features: detected: TLB range maintenance instructions
314 12:27:30.729277 <6>[ 0.086628] CPU features: detected: Scalable Matrix Extension
315 12:27:30.729491 <6>[ 0.086804] CPU features: detected: FA64
316 12:27:30.729702 <6>[ 0.086974] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 12:27:30.729911 <6>[ 0.087163] CPU features: detected: Scalable Vector Extension
318 12:27:30.741160 <6>[ 0.095900] SVE: maximum available vector length 256 bytes per vector
319 12:27:30.741906 <6>[ 0.099181] SVE: default vector length 64 bytes per vector
320 12:27:30.743737 <6>[ 0.101026] SME: minimum available vector length 16 bytes per vector
321 12:27:30.743893 <6>[ 0.101223] SME: maximum available vector length 256 bytes per vector
322 12:27:30.744058 <6>[ 0.101421] SME: default vector length 32 bytes per vector
323 12:27:30.744398 <6>[ 0.101865] CPU: All CPU(s) started at EL1
324 12:27:30.744765 <6>[ 0.102225] alternatives: applying system-wide alternatives
325 12:27:30.798067 <6>[ 0.155356] devtmpfs: initialized
326 12:27:30.818155 <6>[ 0.175170] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 12:27:30.818616 <6>[ 0.175985] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 12:27:30.824507 <6>[ 0.181800] pinctrl core: initialized pinctrl subsystem
329 12:27:30.835316 <6>[ 0.192841] DMI not present or invalid.
330 12:27:30.844516 <6>[ 0.201989] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 12:27:30.856256 <6>[ 0.213329] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 12:27:30.856819 <6>[ 0.214079] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 12:27:30.857119 <6>[ 0.214539] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 12:27:30.857653 <6>[ 0.215015] audit: initializing netlink subsys (disabled)
335 12:27:30.864125 <5>[ 0.221419] audit: type=2000 audit(0.180:1): state=initialized audit_enabled=0 res=1
336 12:27:30.865484 <6>[ 0.222759] thermal_sys: Registered thermal governor 'step_wise'
337 12:27:30.865965 <6>[ 0.222826] thermal_sys: Registered thermal governor 'power_allocator'
338 12:27:30.866173 <6>[ 0.223417] cpuidle: using governor menu
339 12:27:30.867012 <6>[ 0.224326] NET: Registered PF_QIPCRTR protocol family
340 12:27:30.869849 <6>[ 0.227162] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
341 12:27:30.870293 <6>[ 0.227772] ASID allocator initialised with 65536 entries
342 12:27:30.876260 <6>[ 0.233544] Serial: AMBA PL011 UART driver
343 12:27:30.923810 <6>[ 0.280949] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
344 12:27:30.925430 <6>[ 0.282639] printk: console [ttyAMA0] enabled
345 12:27:30.925628 <6>[ 0.282639] printk: console [ttyAMA0] enabled
346 12:27:30.925808 <6>[ 0.283130] printk: bootconsole [pl11] disabled
347 12:27:30.925936 <6>[ 0.283130] printk: bootconsole [pl11] disabled
348 12:27:30.936354 <6>[ 0.293661] KASLR enabled
349 12:27:30.970538 <6>[ 0.327740] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
350 12:27:30.970731 <6>[ 0.327948] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
351 12:27:30.970926 <6>[ 0.328111] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
352 12:27:30.971139 <6>[ 0.328340] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
353 12:27:30.971368 <6>[ 0.328532] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
354 12:27:30.971544 <6>[ 0.328712] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
355 12:27:30.971713 <6>[ 0.328856] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
356 12:27:30.971851 <6>[ 0.329039] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
357 12:27:30.980714 <6>[ 0.338203] ACPI: Interpreter disabled.
358 12:27:30.988940 <6>[ 0.346251] iommu: Default domain type: Translated
359 12:27:30.989049 <6>[ 0.346462] iommu: DMA domain TLB invalidation policy: strict mode
360 12:27:30.990671 <5>[ 0.348240] SCSI subsystem initialized
361 12:27:30.991514 <7>[ 0.349075] libata version 3.00 loaded.
362 12:27:30.993154 <6>[ 0.350416] usbcore: registered new interface driver usbfs
363 12:27:30.993346 <6>[ 0.350805] usbcore: registered new interface driver hub
364 12:27:30.993778 <6>[ 0.351134] usbcore: registered new device driver usb
365 12:27:30.997231 <6>[ 0.354504] pps_core: LinuxPPS API ver. 1 registered
366 12:27:30.997438 <6>[ 0.354656] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
367 12:27:30.997627 <6>[ 0.355024] PTP clock support registered
368 12:27:30.998057 <6>[ 0.355597] EDAC MC: Ver: 3.0.0
369 12:27:31.003659 <6>[ 0.361223] FPGA manager framework
370 12:27:31.004648 <6>[ 0.362017] Advanced Linux Sound Architecture Driver Initialized.
371 12:27:31.013482 <6>[ 0.371021] vgaarb: loaded
372 12:27:31.017777 <6>[ 0.375085] clocksource: Switched to clocksource arch_sys_counter
373 12:27:31.018763 <5>[ 0.376335] VFS: Disk quotas dquot_6.6.0
374 12:27:31.019218 <6>[ 0.376606] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
375 12:27:31.022495 <6>[ 0.379807] pnp: PnP ACPI: disabled
376 12:27:31.040004 <6>[ 0.397279] NET: Registered PF_INET protocol family
377 12:27:31.042092 <6>[ 0.399530] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
378 12:27:31.047096 <6>[ 0.404369] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
379 12:27:31.047296 <6>[ 0.404673] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
380 12:27:31.047696 <6>[ 0.404951] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
381 12:27:31.048111 <6>[ 0.405357] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
382 12:27:31.048535 <6>[ 0.405960] TCP: Hash tables configured (established 8192 bind 8192)
383 12:27:31.050006 <6>[ 0.407330] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
384 12:27:31.050285 <6>[ 0.407767] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
385 12:27:31.051600 <6>[ 0.408926] NET: Registered PF_UNIX/PF_LOCAL protocol family
386 12:27:31.054042 <6>[ 0.411277] RPC: Registered named UNIX socket transport module.
387 12:27:31.054224 <6>[ 0.411531] RPC: Registered udp transport module.
388 12:27:31.054430 <6>[ 0.411676] RPC: Registered tcp transport module.
389 12:27:31.054570 <6>[ 0.411823] RPC: Registered tcp NFSv4.1 backchannel transport module.
390 12:27:31.054746 <6>[ 0.412090] PCI: CLS 0 bytes, default 64
391 12:27:31.059108 <6>[ 0.416660] Unpacking initramfs...
392 12:27:31.069897 <6>[ 0.427195] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
393 12:27:31.070645 <6>[ 0.427952] kvm [1]: HYP mode not available
394 12:27:31.078353 <5>[ 0.435878] Initialise system trusted keyrings
395 12:27:31.079932 <6>[ 0.437280] workingset: timestamp_bits=42 max_order=18 bucket_order=0
396 12:27:31.118965 <6>[ 0.476419] squashfs: version 4.0 (2009/01/31) Phillip Lougher
397 12:27:31.126860 <5>[ 0.484177] NFS: Registering the id_resolver key type
398 12:27:31.127213 <5>[ 0.484583] Key type id_resolver registered
399 12:27:31.127310 <5>[ 0.484741] Key type id_legacy registered
400 12:27:31.127682 <6>[ 0.485236] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
401 12:27:31.128020 <6>[ 0.485464] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
402 12:27:31.128913 <6>[ 0.486268] 9p: Installing v9fs 9p2000 file system support
403 12:27:31.194096 <5>[ 0.551594] Key type asymmetric registered
404 12:27:31.194436 <5>[ 0.551818] Asymmetric key parser 'x509' registered
405 12:27:31.194791 <6>[ 0.552278] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
406 12:27:31.195115 <6>[ 0.552591] io scheduler mq-deadline registered
407 12:27:31.195441 <6>[ 0.552788] io scheduler kyber registered
408 12:27:31.266362 <6>[ 0.623642] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
409 12:27:31.282217 <6>[ 0.639486] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
410 12:27:31.283205 <6>[ 0.640554] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
411 12:27:31.284141 <6>[ 0.641296] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
412 12:27:31.284359 <6>[ 0.641633] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
413 12:27:31.284926 <4>[ 0.642370] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
414 12:27:31.290120 <6>[ 0.647224] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
415 12:27:31.291577 <6>[ 0.648852] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
416 12:27:31.291937 <6>[ 0.649334] pci_bus 0000:00: root bus resource [bus 00-ff]
417 12:27:31.292293 <6>[ 0.649624] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
418 12:27:31.292632 <6>[ 0.649901] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
419 12:27:31.292734 <6>[ 0.650145] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
420 12:27:31.298586 <6>[ 0.655870] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
421 12:27:31.306222 <6>[ 0.663557] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
422 12:27:31.306597 <6>[ 0.663988] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
423 12:27:31.306716 <6>[ 0.664215] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
424 12:27:31.307407 <6>[ 0.664529] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
425 12:27:31.307589 <6>[ 0.664852] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
426 12:27:31.308119 <6>[ 0.665523] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
427 12:27:31.308355 <6>[ 0.665715] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
428 12:27:31.308592 <6>[ 0.665933] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
429 12:27:31.308803 <6>[ 0.666228] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
430 12:27:31.315752 <6>[ 0.673128] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
431 12:27:31.316481 <6>[ 0.673724] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
432 12:27:31.317008 <6>[ 0.674104] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
433 12:27:31.317473 <6>[ 0.674445] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
434 12:27:31.317635 <6>[ 0.674704] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
435 12:27:31.321726 <6>[ 0.678896] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
436 12:27:31.321899 <6>[ 0.679094] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
437 12:27:31.338908 <6>[ 0.696350] EINJ: ACPI disabled.
438 12:27:31.433925 <6>[ 0.791305] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
439 12:27:31.437227 <6>[ 0.794460] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
440 12:27:31.472106 <6>[ 0.829306] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
441 12:27:31.483721 <6>[ 0.841025] SuperH (H)SCI(F) driver initialized
442 12:27:31.485264 <6>[ 0.842548] msm_serial: driver initialized
443 12:27:31.527230 <4>[ 0.884606] cacheinfo: Unable to detect cache hierarchy for CPU 0
444 12:27:31.556635 <6>[ 0.914024] loop: module loaded
445 12:27:31.561971 <6>[ 0.919208] virtio_blk virtio1: 1/0/0 default/read/poll queues
446 12:27:31.579130 <5>[ 0.936335] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
447 12:27:31.610383 <6>[ 0.967790] megasas: 07.719.03.00-rc1
448 12:27:31.626391 <5>[ 0.983588] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
449 12:27:31.627923 <6>[ 0.985131] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
450 12:27:31.628399 <6>[ 0.985822] Intel/Sharp Extended Query Table at 0x0031
451 12:27:31.629330 <6>[ 0.986641] Using buffer write method
452 12:27:31.633861 <7>[ 0.991137] erase region 0: offset=0x0,size=0x40000,blocks=256
453 12:27:31.634364 <5>[ 0.991521] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
454 12:27:31.634865 <6>[ 0.992247] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
455 12:27:31.635070 <6>[ 0.992554] Intel/Sharp Extended Query Table at 0x0031
456 12:27:31.635855 <6>[ 0.993158] Using buffer write method
457 12:27:31.636030 <7>[ 0.993302] erase region 0: offset=0x0,size=0x40000,blocks=256
458 12:27:31.636238 <5>[ 0.993574] Concatenating MTD devices:
459 12:27:31.636412 <5>[ 0.993718] (0): \"0.flash\"
460 12:27:31.636623 <5>[ 0.993845] (1): \"0.flash\"
461 12:27:31.636781 <5>[ 0.993971] into device \"0.flash\"
462 12:27:36.349970 <6>[ 5.707340] Freeing initrd memory: 86888K
463 12:27:36.468404 <6>[ 5.825578] tun: Universal TUN/TAP device driver, 1.6
464 12:27:36.478287 <6>[ 5.835774] thunder_xcv, ver 1.0
465 12:27:36.478795 <6>[ 5.836072] thunder_bgx, ver 1.0
466 12:27:36.478976 <6>[ 5.836298] nicpf, ver 1.0
467 12:27:36.482476 <6>[ 5.839681] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
468 12:27:36.482643 <6>[ 5.839961] hns3: Copyright (c) 2017 Huawei Corporation.
469 12:27:36.483066 <6>[ 5.840446] hclge is initializing
470 12:27:36.483291 <6>[ 5.840705] e1000: Intel(R) PRO/1000 Network Driver
471 12:27:36.483461 <6>[ 5.840882] e1000: Copyright (c) 1999-2006 Intel Corporation.
472 12:27:36.483927 <6>[ 5.841190] e1000e: Intel(R) PRO/1000 Network Driver
473 12:27:36.484120 <6>[ 5.841301] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
474 12:27:36.484351 <6>[ 5.841578] igb: Intel(R) Gigabit Ethernet Network Driver
475 12:27:36.484576 <6>[ 5.841727] igb: Copyright (c) 2007-2014 Intel Corporation.
476 12:27:36.484801 <6>[ 5.842045] igbvf: Intel(R) Gigabit Virtual Function Network Driver
477 12:27:36.484951 <6>[ 5.842233] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
478 12:27:36.486075 <6>[ 5.843380] sky2: driver version 1.30
479 12:27:36.489779 <6>[ 5.847059] VFIO - User Level meta-driver version: 0.3
480 12:27:36.499084 <6>[ 5.856536] usbcore: registered new interface driver usb-storage
481 12:27:36.499963 <6>[ 5.857331] usbcore: registered new device driver onboard-usb-hub
482 12:27:36.510111 <6>[ 5.867326] rtc-pl031 9010000.pl031: registered as rtc0
483 12:27:36.511112 <6>[ 5.868164] rtc-pl031 9010000.pl031: setting system clock to 2023-06-06T12:27:36 UTC (1686054456)
484 12:27:36.513337 <6>[ 5.870694] i2c_dev: i2c /dev entries driver
485 12:27:36.531959 <6>[ 5.889215] sdhci: Secure Digital Host Controller Interface driver
486 12:27:36.532114 <6>[ 5.889451] sdhci: Copyright(c) Pierre Ossman
487 12:27:36.534206 <6>[ 5.891521] Synopsys Designware Multimedia Card Interface Driver
488 12:27:36.536790 <6>[ 5.894075] sdhci-pltfm: SDHCI platform and OF driver helper
489 12:27:36.542604 <6>[ 5.899884] ledtrig-cpu: registered to indicate activity on CPUs
490 12:27:36.548620 <6>[ 5.906041] usbcore: registered new interface driver usbhid
491 12:27:36.549125 <6>[ 5.906256] usbhid: USB HID core driver
492 12:27:36.574101 <6>[ 5.931520] NET: Registered PF_PACKET protocol family
493 12:27:36.575219 <6>[ 5.932725] 9pnet: Installing 9P2000 support
494 12:27:36.575707 <5>[ 5.933165] Key type dns_resolver registered
495 12:27:36.577354 <6>[ 5.934634] registered taskstats version 1
496 12:27:36.577579 <5>[ 5.935106] Loading compiled-in X.509 certificates
497 12:27:36.599547 <6>[ 5.956935] input: gpio-keys as /devices/platform/gpio-keys/input/input0
498 12:27:36.607016 <6>[ 5.964512] ALSA device list:
499 12:27:36.607542 <6>[ 5.964694] No soundcards found.
500 12:27:36.610287 <6>[ 5.967552] uart-pl011 9000000.pl011: no DMA platform data
501 12:27:36.668238 <6>[ 6.025676] Freeing unused kernel memory: 8384K
502 12:27:36.669592 <6>[ 6.026855] Run /init as init process
503 12:27:36.669796 <7>[ 6.027014] with arguments:
504 12:27:36.669960 <7>[ 6.027135] /init
505 12:27:36.670118 <7>[ 6.027211] verbose
506 12:27:36.670246 <7>[ 6.027283] with environment:
507 12:27:36.670367 <7>[ 6.027407] HOME=/
508 12:27:36.670488 <7>[ 6.027502] TERM=linux
509 12:27:36.808384 <30>[ 6.165373] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
510 12:27:36.809780 <31>[ 6.167059] systemd[1]: No virtualization found in DMI
511 12:27:36.810613 <31>[ 6.168120] systemd[1]: UML virtualization not found in /proc/cpuinfo.
512 12:27:36.811100 <31>[ 6.168443] systemd[1]: No virtualization found in CPUID
513 12:27:36.811464 <31>[ 6.168802] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
514 12:27:36.812705 <31>[ 6.170054] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
515 12:27:36.813150 <31>[ 6.170384] systemd[1]: Found VM virtualization qemu
516 12:27:36.813344 <30>[ 6.170657] systemd[1]: Detected virtualization qemu.
517 12:27:36.814069 <30>[ 6.171350] systemd[1]: Detected architecture arm64.
518 12:27:36.814548 <31>[ 6.171830] systemd[1]: Detected initialized system, this is not the first boot.
519 12:27:36.818554
520 12:27:36.819082 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
521 12:27:36.819241
522 12:27:36.820937 <30>[ 6.178195] systemd[1]: Set hostname to <debian-bullseye-arm64>.
523 12:27:36.840692 <31>[ 6.197828] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
524 12:27:36.842064 <31>[ 6.199331] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
525 12:27:36.842544 <31>[ 6.199894] systemd[1]: Successfully brought loopback interface up
526 12:27:36.847497 <31>[ 6.204751] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
527 12:27:36.860148 <31>[ 6.217268] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
528 12:27:36.860448 <31>[ 6.217611] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
529 12:27:36.902274 <31>[ 6.259460] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
530 12:27:36.903716 <31>[ 6.261048] systemd[1]: Controller 'cpu' supported: yes
531 12:27:36.903849 <31>[ 6.261260] systemd[1]: Controller 'cpuacct' supported: no
532 12:27:36.904202 <31>[ 6.261449] systemd[1]: Controller 'cpuset' supported: yes
533 12:27:36.904310 <31>[ 6.261689] systemd[1]: Controller 'io' supported: yes
534 12:27:36.904419 <31>[ 6.261883] systemd[1]: Controller 'blkio' supported: no
535 12:27:36.904768 <31>[ 6.262110] systemd[1]: Controller 'memory' supported: yes
536 12:27:36.904890 <31>[ 6.262345] systemd[1]: Controller 'devices' supported: no
537 12:27:36.905228 <31>[ 6.262525] systemd[1]: Controller 'pids' supported: yes
538 12:27:36.905881 <31>[ 6.263107] systemd[1]: Controller 'bpf-firewall' supported: yes
539 12:27:36.906051 <31>[ 6.263347] systemd[1]: Controller 'bpf-devices' supported: yes
540 12:27:36.907349 <31>[ 6.264565] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
541 12:27:36.907617 <31>[ 6.264909] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
542 12:27:36.908058 <31>[ 6.265399] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
543 12:27:36.915649 <31>[ 6.273126] systemd[1]: Enabling (yes) showing of status (commandline).
544 12:27:36.923869 <31>[ 6.281071] systemd[1]: Successfully forked off '(sd-executor)' as PID 98.
545 12:27:36.933281 <31>[ 6.290502] systemd[98]: Successfully forked off '(direxec)' as PID 99.
546 12:27:36.936252 <31>[ 6.293520] systemd[98]: Successfully forked off '(direxec)' as PID 100.
547 12:27:36.942633 <31>[ 6.299874] systemd[98]: Successfully forked off '(direxec)' as PID 101.
548 12:27:36.944604 <31>[ 6.301862] systemd[98]: Successfully forked off '(direxec)' as PID 102.
549 12:27:36.962804 <31>[ 6.320202] systemd[98]: Successfully forked off '(direxec)' as PID 103.
550 12:27:37.111457 <31>[ 6.468557] systemd-bless-boot-generator[99]: Skipping generator, not an EFI boot.
551 12:27:37.115251 <31>[ 6.472500] systemd-fstab-generator[100]: Parsing /etc/fstab...
552 12:27:37.126213 <31>[ 6.483351] systemd-getty-generator[101]: Automatically adding serial getty for /dev/ttyAMA0.
553 12:27:37.127706 <31>[ 6.484987] systemd-getty-generator[101]: SELinux enabled state cached to: disabled
554 12:27:37.134273 <31>[ 6.491085] systemd-fstab-generator[100]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
555 12:27:37.136811 <31>[ 6.493909] systemd-fstab-generator[100]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
556 12:27:37.138870 <31>[ 6.495983] systemd[98]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
557 12:27:37.148851 <31>[ 6.506157] systemd[98]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
558 12:27:37.149952 <31>[ 6.506729] systemd[98]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
559 12:27:37.153228 <31>[ 6.510306] systemd-fstab-generator[100]: SELinux enabled state cached to: disabled
560 12:27:37.159926 <31>[ 6.516995] systemd[98]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
561 12:27:37.160206 <31>[ 6.517530] systemd[98]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
562 12:27:37.163525 <31>[ 6.520768] systemd[1]: (sd-executor) succeeded.
563 12:27:37.165207 <31>[ 6.522534] systemd[1]: Looking for unit files in (higher priority first):
564 12:27:37.165718 <31>[ 6.523176] systemd[1]: /etc/systemd/system.control
565 12:27:37.166076 <31>[ 6.523413] systemd[1]: /run/systemd/system.control
566 12:27:37.166425 <31>[ 6.523624] systemd[1]: /run/systemd/transient
567 12:27:37.166532 <31>[ 6.523845] systemd[1]: /run/systemd/generator.early
568 12:27:37.166639 <31>[ 6.524077] systemd[1]: /etc/systemd/system
569 12:27:37.167011 <31>[ 6.524276] systemd[1]: /etc/systemd/system.attached
570 12:27:37.167133 <31>[ 6.524565] systemd[1]: /run/systemd/system
571 12:27:37.167515 <31>[ 6.524780] systemd[1]: /run/systemd/system.attached
572 12:27:37.167814 <31>[ 6.525009] systemd[1]: /run/systemd/generator
573 12:27:37.168202 <31>[ 6.525222] systemd[1]: /usr/local/lib/systemd/system
574 12:27:37.168312 <31>[ 6.525476] systemd[1]: /lib/systemd/system
575 12:27:37.168649 <31>[ 6.525699] systemd[1]: /usr/lib/systemd/system
576 12:27:37.168756 <31>[ 6.525975] systemd[1]: /run/systemd/generator.late
577 12:27:37.206390 <31>[ 6.563776] systemd[1]: Modification times have changed, need to update cache.
578 12:27:37.208347 <31>[ 6.565546] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
579 12:27:37.209735 <31>[ 6.566724] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
580 12:27:37.210877 <31>[ 6.568118] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
581 12:27:37.211745 <31>[ 6.569086] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
582 12:27:37.212669 <31>[ 6.569975] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
583 12:27:37.213356 <31>[ 6.570397] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
584 12:27:37.214009 <31>[ 6.571338] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
585 12:27:37.214669 <31>[ 6.571855] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
586 12:27:37.215058 <31>[ 6.572284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
587 12:27:37.215483 <31>[ 6.572727] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
588 12:27:37.215891 <31>[ 6.573263] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
589 12:27:37.216950 <31>[ 6.574184] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
590 12:27:37.217354 <31>[ 6.574608] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
591 12:27:37.218662 <31>[ 6.575949] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
592 12:27:37.219789 <31>[ 6.576997] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
593 12:27:37.220403 <31>[ 6.577436] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
594 12:27:37.220669 <31>[ 6.577813] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
595 12:27:37.221224 <31>[ 6.578312] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
596 12:27:37.222059 <31>[ 6.579201] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
597 12:27:37.222628 <31>[ 6.579915] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
598 12:27:37.222982 <31>[ 6.580324] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
599 12:27:37.223998 <31>[ 6.581008] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
600 12:27:37.224211 <31>[ 6.581327] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
601 12:27:37.224424 <31>[ 6.581605] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
602 12:27:37.224683 <31>[ 6.581931] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
603 12:27:37.225192 <31>[ 6.582291] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
604 12:27:37.225809 <31>[ 6.582714] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
605 12:27:37.226681 <31>[ 6.583839] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
606 12:27:37.227437 <31>[ 6.584525] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
607 12:27:37.227685 <31>[ 6.585000] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
608 12:27:37.228273 <31>[ 6.585329] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
609 12:27:37.228530 <31>[ 6.585861] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
610 12:27:37.229110 <31>[ 6.586280] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
611 12:27:37.229335 <31>[ 6.586650] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
612 12:27:37.230714 <31>[ 6.587656] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
613 12:27:37.231192 <31>[ 6.588350] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
614 12:27:37.231645 <31>[ 6.588856] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
615 12:27:37.232309 <31>[ 6.589405] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
616 12:27:37.232962 <31>[ 6.589998] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
617 12:27:37.233347 <31>[ 6.590519] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
618 12:27:37.234075 <31>[ 6.591431] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
619 12:27:37.234424 <31>[ 6.591810] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
620 12:27:37.234773 <31>[ 6.592135] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
621 12:27:37.235158 <31>[ 6.592465] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
622 12:27:37.235497 <31>[ 6.592741] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
623 12:27:37.236168 <31>[ 6.593503] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
624 12:27:37.236554 <31>[ 6.593882] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
625 12:27:37.237284 <31>[ 6.594621] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
626 12:27:37.237948 <31>[ 6.595305] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
627 12:27:37.238561 <31>[ 6.595776] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
628 12:27:37.238933 <31>[ 6.596177] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
629 12:27:37.239323 <31>[ 6.596553] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
630 12:27:37.239968 <31>[ 6.597291] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
631 12:27:37.240337 <31>[ 6.597666] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
632 12:27:37.240711 <31>[ 6.598052] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
633 12:27:37.241091 <31>[ 6.598402] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
634 12:27:37.242090 <31>[ 6.599419] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
635 12:27:37.242729 <31>[ 6.599795] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
636 12:27:37.242855 <31>[ 6.600184] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
637 12:27:37.243888 <31>[ 6.600980] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
638 12:27:37.244260 <31>[ 6.601437] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
639 12:27:37.244642 <31>[ 6.601848] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
640 12:27:37.245018 <31>[ 6.602199] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
641 12:27:37.245388 <31>[ 6.602581] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
642 12:27:37.246002 <31>[ 6.603352] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
643 12:27:37.246366 <31>[ 6.603722] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
644 12:27:37.246737 <31>[ 6.604018] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
645 12:27:37.247119 <31>[ 6.604301] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
646 12:27:37.247244 <31>[ 6.604626] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
647 12:27:37.247607 <31>[ 6.604956] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
648 12:27:37.247981 <31>[ 6.605268] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
649 12:27:37.248434 <31>[ 6.605654] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
650 12:27:37.248677 <31>[ 6.606047] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
651 12:27:37.249179 <31>[ 6.606430] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
652 12:27:37.250189 <31>[ 6.607329] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
653 12:27:37.250391 <31>[ 6.607719] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
654 12:27:37.250882 <31>[ 6.608075] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
655 12:27:37.251741 <31>[ 6.608799] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
656 12:27:37.251949 <31>[ 6.609233] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
657 12:27:37.252301 <31>[ 6.609565] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
658 12:27:37.252544 <31>[ 6.609945] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
659 12:27:37.253157 <31>[ 6.610441] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
660 12:27:37.254457 <31>[ 6.611575] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
661 12:27:37.254692 <31>[ 6.612012] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
662 12:27:37.254904 <31>[ 6.612274] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
663 12:27:37.255358 <31>[ 6.612581] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
664 12:27:37.255819 <31>[ 6.612920] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
665 12:27:37.256024 <31>[ 6.613251] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
666 12:27:37.256219 <31>[ 6.613595] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
667 12:27:37.256695 <31>[ 6.613928] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
668 12:27:37.257160 <31>[ 6.614301] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
669 12:27:37.257345 <31>[ 6.614716] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
670 12:27:37.258176 <31>[ 6.615354] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
671 12:27:37.258625 <31>[ 6.615702] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
672 12:27:37.258726 <31>[ 6.616038] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
673 12:27:37.259186 <31>[ 6.616338] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
674 12:27:37.259370 <31>[ 6.616618] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
675 12:27:37.259939 <31>[ 6.617083] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
676 12:27:37.260135 <31>[ 6.617404] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
677 12:27:37.260312 <31>[ 6.617709] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
678 12:27:37.261385 <31>[ 6.618490] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
679 12:27:37.261749 <31>[ 6.619165] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
680 12:27:37.262107 <31>[ 6.619494] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
681 12:27:37.262518 <31>[ 6.619826] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
682 12:27:37.262854 <31>[ 6.620150] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
683 12:27:37.263234 <31>[ 6.620490] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
684 12:27:37.263715 <31>[ 6.620829] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
685 12:27:37.263944 <31>[ 6.621185] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
686 12:27:37.264136 <31>[ 6.621534] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
687 12:27:37.264609 <31>[ 6.621844] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
688 12:27:37.264829 <31>[ 6.622198] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
689 12:27:37.265315 <31>[ 6.622576] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
690 12:27:37.266163 <31>[ 6.623278] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
691 12:27:37.266341 <31>[ 6.623652] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
692 12:27:37.266889 <31>[ 6.624054] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
693 12:27:37.267074 <31>[ 6.624430] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
694 12:27:37.267527 <31>[ 6.624750] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
695 12:27:37.267655 <31>[ 6.625052] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
696 12:27:37.268025 <31>[ 6.625396] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
697 12:27:37.268392 <31>[ 6.625754] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
698 12:27:37.268770 <31>[ 6.626058] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
699 12:27:37.269139 <31>[ 6.626398] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
700 12:27:37.269517 <31>[ 6.626712] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
701 12:27:37.269915 <31>[ 6.627187] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
702 12:27:37.270282 <31>[ 6.627594] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
703 12:27:37.270898 <31>[ 6.628034] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
704 12:27:37.271283 <31>[ 6.628409] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
705 12:27:37.271410 <31>[ 6.628747] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
706 12:27:37.271778 <31>[ 6.629047] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
707 12:27:37.271993 <31>[ 6.629343] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
708 12:27:37.272444 <31>[ 6.629868] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
709 12:27:37.272805 <31>[ 6.630143] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
710 12:27:37.273940 <31>[ 6.631085] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
711 12:27:37.274072 <31>[ 6.631480] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
712 12:27:37.274474 <31>[ 6.631714] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
713 12:27:37.274604 <31>[ 6.631937] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
714 12:27:37.274992 <31>[ 6.632236] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
715 12:27:37.275113 <31>[ 6.632517] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
716 12:27:37.275696 <31>[ 6.632852] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
717 12:27:37.275829 <31>[ 6.633249] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
718 12:27:37.276544 <31>[ 6.633582] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
719 12:27:37.276664 <31>[ 6.634002] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
720 12:27:37.277105 <31>[ 6.634379] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
721 12:27:37.277989 <31>[ 6.635123] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
722 12:27:37.278209 <31>[ 6.635592] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
723 12:27:37.278798 <31>[ 6.635922] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
724 12:27:37.279003 <31>[ 6.636254] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
725 12:27:37.279223 <31>[ 6.636594] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
726 12:27:37.279537 <31>[ 6.636956] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
727 12:27:37.280179 <31>[ 6.637284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
728 12:27:37.280407 <31>[ 6.637572] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
729 12:27:37.702848 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
730 12:27:37.708198 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
731 12:27:37.712170 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
732 12:27:37.715929 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
733 12:27:37.719781 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
734 12:27:37.721156 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
735 12:27:37.723867 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
736 12:27:37.724905 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
737 12:27:37.725996 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
738 12:27:37.726499 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
739 12:27:37.727363 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
740 12:27:37.731100 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
741 12:27:37.735394 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
742 12:27:37.738345 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
743 12:27:37.740537 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
744 12:27:37.743415 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
745 12:27:37.746350 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
746 12:27:37.748196 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
747 12:27:37.775471 Mounting [0;1;39mHuge Pages File System[0m...
748 12:27:37.811078 Mounting [0;1;39mPOSIX Message Queue File System[0m...
749 12:27:37.854881 Mounting [0;1;39mKernel Debug File System[0m...
750 12:27:37.892149 Starting [0;1;39mLoad Kernel Module configfs[0m...
751 12:27:37.931260 Starting [0;1;39mLoad Kernel Module drm[0m...
752 12:27:37.995378 Starting [0;1;39mJournal Service[0m...
753 12:27:38.027415 Starting [0;1;39mLoad Kernel Modules[0m...
754 12:27:38.063785 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
755 12:27:38.127622 Starting [0;1;39mColdplug All udev Devices[0m...
756 12:27:38.237782 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
757 12:27:38.244095 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
758 12:27:38.256568 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
759 12:27:38.306884 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
760 12:27:38.366772 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
761 12:27:38.395385 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
762 12:27:38.482987 Mounting [0;1;39mKernel Configuration File System[0m...
763 12:27:38.590961 Starting [0;1;39mApply Kernel Variables[0m...
764 12:27:38.676447 <47>[ 8.033551] systemd-journald[109]: SELinux enabled state cached to: disabled
765 12:27:38.683669 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
766 12:27:38.690558 <47>[ 8.047766] systemd-journald[109]: Auditing in kernel turned off.
767 12:27:38.710968 <47>[ 8.068096] systemd-journald[109]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
768 12:27:38.768241 <47>[ 8.125556] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
769 12:27:38.783236 <47>[ 8.140329] systemd-journald[109]: Fixed min_use=3.8M max_use=19.3M max_size=2.4M min_size=512.0K keep_free=9.6M n_max_files=100
770 12:27:38.784728 <47>[ 8.141911] systemd-journald[109]: Reserving 333 entries in field hash table.
771 12:27:38.810510 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
772 12:27:38.811293 See 'systemctl status systemd-remount-fs.service' for details.
773 12:27:38.838157 <47>[ 8.195524] systemd-journald[109]: Reserving 4408 entries in data hash table.
774 12:27:38.840082 <47>[ 8.197370] systemd-journald[109]: Vacuuming...
775 12:27:38.840594 <47>[ 8.197956] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
776 12:27:38.841077 <47>[ 8.198550] systemd-journald[109]: Flushing /dev/kmsg...
777 12:27:38.855147 Starting [0;1;39mLoad/Save Random Seed[0m...
778 12:27:38.910786 Starting [0;1;39mCreate System Users[0m...
779 12:27:38.950368 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
780 12:27:39.070101 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
781 12:27:39.242532 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
782 12:27:39.287176 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
783 12:27:39.384557 <47>[ 8.741900] systemd-journald[109]: systemd-journald running as PID 109 for the system.
784 12:27:39.394424 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
785 12:27:39.409735 <47>[ 8.767137] systemd-journald[109]: Sent READY=1 notification.
786 12:27:39.410303 <47>[ 8.767566] systemd-journald[109]: Sent WATCHDOG=1 notification.
787 12:27:39.435308 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
788 12:27:39.454927 <47>[ 8.812313] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
789 12:27:39.476383 <47>[ 8.833444] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
790 12:27:39.493940 <47>[ 8.851101] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
791 12:27:39.505886 <47>[ 8.863062] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
792 12:27:39.522153 <47>[ 8.879511] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
793 12:27:39.537812 <47>[ 8.894942] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
794 12:27:39.543630 <47>[ 8.901022] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
795 12:27:39.562957 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
796 12:27:39.565039 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
797 12:27:39.574463 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
798 12:27:39.575954 <47>[ 8.933251] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
799 12:27:39.583853 <47>[ 8.941120] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
800 12:27:39.602288 <47>[ 8.959476] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
801 12:27:39.604361 <47>[ 8.961551] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
802 12:27:39.614847 <47>[ 8.971941] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
803 12:27:39.615142 <47>[ 8.972384] systemd-journald[109]: n/a: New incoming connection.
804 12:27:39.615568 <47>[ 8.972931] systemd-journald[109]: varlink-20: varlink: setting state idle-server
805 12:27:39.634903 <47>[ 8.991941] systemd-journald[109]: varlink-20: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
806 12:27:39.637288 <47>[ 8.994499] systemd-journald[109]: varlink-20: varlink: changing state idle-server → processing-method
807 12:27:39.640042 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
808 12:27:39.641928 <46>[ 8.999128] systemd-journald[109]: Received client request to flush runtime journal.
809 12:27:39.642583 <47>[ 8.999629] systemd-journald[109]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
810 12:27:39.643082 <47>[ 9.000510] systemd-journald[109]: Vacuuming...
811 12:27:39.643645 <47>[ 9.000923] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
812 12:27:39.644957 <47>[ 9.002180] systemd-journald[109]: varlink-20: Sending message: {\"parameters\":{}}
813 12:27:39.645245 <47>[ 9.002474] systemd-journald[109]: varlink-20: varlink: changing state processing-method → processed-method
814 12:27:39.662381 <47>[ 9.019479] systemd-journald[109]: varlink-20: varlink: changing state processed-method → idle-server
815 12:27:39.674388 <47>[ 9.031558] systemd-journald[109]: varlink-20: varlink: changing state idle-server → pending-disconnect
816 12:27:39.674704 <47>[ 9.031978] systemd-journald[109]: varlink-20: varlink: changing state pending-disconnect → processing-disconnect
817 12:27:39.674940 <47>[ 9.032314] systemd-journald[109]: varlink-20: varlink: changing state processing-disconnect → disconnected
818 12:27:39.690738 <47>[ 9.047903] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
819 12:27:39.692728 <47>[ 9.049978] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
820 12:27:39.699517 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
821 12:27:39.711457 <47>[ 9.068588] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
822 12:27:39.766845 Starting [0;1;39mCreate Volatile Files and Directories[0m...
823 12:27:39.794054 <47>[ 9.151112] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
824 12:27:40.214434 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
825 12:27:40.299142 Starting [0;1;39mNetwork Service[0m...
826 12:27:40.320432 <47>[ 9.677780] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
827 12:27:40.327407 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
828 12:27:40.423159 Starting [0;1;39mNetwork Time Synchronization[0m...
829 12:27:40.440315 <47>[ 9.797388] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
830 12:27:40.495007 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
831 12:27:40.500063 <47>[ 9.857291] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
832 12:27:40.924124 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
833 12:27:41.898420 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
834 12:27:41.902569 <47>[ 11.259519] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
835 12:27:41.903368 <47>[ 11.260284] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
836 12:27:41.903534 <47>[ 11.260776] systemd-journald[109]: Rotating...
837 12:27:41.904559 <47>[ 11.261786] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
838 12:27:41.922740 <47>[ 11.280033] systemd-journald[109]: Reserving 333 entries in field hash table.
839 12:27:41.957389 <47>[ 11.314620] systemd-journald[109]: Reserving 4408 entries in data hash table.
840 12:27:41.976894 <47>[ 11.334244] systemd-journald[109]: Vacuuming...
841 12:27:42.011754 <47>[ 11.369021] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
842 12:27:42.020139 Starting [0;1;39mNetwork Name Resolution[0m...
843 12:27:42.050193 <47>[ 11.407293] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
844 12:27:42.412709 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
845 12:27:42.415104 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
846 12:27:42.422715 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
847 12:27:42.986099 <47>[ 12.343210] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
848 12:27:44.183436 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
849 12:27:44.198005 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
850 12:27:44.226112 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
851 12:27:44.244830 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
852 12:27:44.254909 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
853 12:27:44.258403 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
854 12:27:44.287865 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
855 12:27:44.288701 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
856 12:27:44.301829 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
857 12:27:44.347370 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
858 12:27:44.360229 <47>[ 13.717419] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
859 12:27:44.479252 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
860 12:27:44.487756 <47>[ 13.844956] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
861 12:27:44.687931 Starting [0;1;39mUser Login Management[0m...
862 12:27:44.699508 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
863 12:27:44.711210 <47>[ 14.068383] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
864 12:27:44.721036 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
865 12:27:44.742782 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
866 12:27:44.852271 Starting [0;1;39mPermit User Sessions[0m...
867 12:27:44.893893 <47>[ 14.251007] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
868 12:27:45.150150 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
869 12:27:45.217112 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
870 12:27:45.412082 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
871 12:27:45.844746 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
872 12:27:47.993984 [[0m[0;31m* [0m] A start job is running for /dev/ttyAMA0 (10s / 1min 30s)
873 12:27:48.376877 M[K[[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
874 12:27:48.447970 [K[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
875 12:27:48.470732 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
876 12:27:48.482274 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
877 12:27:48.496059 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
878 12:27:48.543416 <47>[ 17.900813] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
879 12:27:48.558955 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
880 12:27:48.752343 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
881 12:27:48.787622 <47>[ 18.145006] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
882 12:27:48.796970 <47>[ 18.154253] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
883 12:27:48.875852
884 12:27:48.876475 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
885 12:27:48.876641
886 12:27:48.876798 debian-bullseye-arm64 login: root (automatic login)
887 12:27:48.876986
888 12:27:48.921936 <6>[ 18.279308] virtio_net virtio0 enp0s1: renamed from eth0
889 12:27:49.139697 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
890 12:27:49.140308
891 12:27:49.140524 The programs included with the Debian GNU/Linux system are free software;
892 12:27:49.140775 the exact distribution terms for each program are described in the
893 12:27:49.140968 individual files in /usr/share/doc/*/copyright.
894 12:27:49.141122
895 12:27:49.141277 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
896 12:27:49.141406 permitted by applicable law.
897 12:27:49.666722 <47>[ 19.023993] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
898 12:27:49.791886 <47>[ 19.148950] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.1 (3309 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
899 12:27:49.792407 <47>[ 19.149519] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
900 12:27:49.792525 <47>[ 19.149900] systemd-journald[109]: Rotating...
901 12:27:49.809885 <47>[ 19.167039] systemd-journald[109]: Reserving 333 entries in field hash table.
902 12:27:49.841196 <47>[ 19.198383] systemd-journald[109]: Reserving 4408 entries in data hash table.
903 12:27:49.858929 <47>[ 19.216365] systemd-journald[109]: Vacuuming...
904 12:27:49.860507 <47>[ 19.217804] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
905 12:27:49.993428 <47>[ 19.350552] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
906 12:27:51.845537 <47>[ 21.202575] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
907 12:27:52.244355 Matched prompt #10: / #
909 12:27:52.244768 Setting prompt string to ['/ #']
910 12:27:52.244893 end: 2.2.1 login-action (duration 00:00:22) [common]
912 12:27:52.245164 end: 2.2 auto-login-action (duration 00:00:23) [common]
913 12:27:52.245273 start: 2.3 expect-shell-connection (timeout 00:04:35) [common]
914 12:27:52.245362 Setting prompt string to ['/ #']
915 12:27:52.245441 Forcing a shell prompt, looking for ['/ #']
917 12:27:52.295889 / #
918 12:27:52.296116 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
919 12:27:52.296313 Waiting using forced prompt support (timeout 00:02:30)
920 12:27:52.298088
921 12:27:52.303758 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
922 12:27:52.303892 start: 2.4 export-device-env (timeout 00:04:35) [common]
923 12:27:52.303995 end: 2.4 export-device-env (duration 00:00:00) [common]
924 12:27:52.304084 end: 2 boot-image-retry (duration 00:00:25) [common]
925 12:27:52.304174 start: 3 lava-test-retry (timeout 00:08:48) [common]
926 12:27:52.304264 start: 3.1 lava-test-shell (timeout 00:08:48) [common]
927 12:27:52.304342 Using namespace: common
929 12:27:52.405056 / # #
930 12:27:52.405252 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
931 12:27:52.405685 #
933 12:27:52.510508 / # mkdir /lava-568844
934 12:27:52.511196 mkdir /lava-568844
936 12:27:52.641128 / # mount /dev/disk/by-uuid/f8d49991-354e-43d9-a426-b57094c56b9a -t ext2 /lava-568844
937 12:27:52.641872 mount /dev/disk/by-uuid/f8d49991-354e-43d9-a426-b57094c56b9a -t ext2 /lava-568844
938 12:27:52.678918 <4>[ 22.035994] ext2 filesystem being mounted at /lava-568844 supports timestamps until 2038 (0x7fffffff)
940 12:27:52.823028 / # ls -la /lava-568844/bin/lava-test-runner
941 12:27:52.823952 ls -la /lava-568844/bin/lava-test-runner
942 12:27:52.861964 -rwxr-xr-x 1 root root 1039 Jun 6 12:26 /lava-568844/bin/lava-test-runner
943 12:27:52.872813 Using /lava-568844
945 12:27:52.973753 / # export SHELL=/bin/sh
946 12:27:52.974613 export SHELL=/bin/sh
948 12:27:53.082060 / # . /lava-568844/environment
949 12:27:53.082795 . /lava-568844/environment
951 12:27:53.193339 / # /lava-568844/bin/lava-test-runner /lava-568844/0
952 12:27:53.193666 Test shell timeout: 10s (minimum of the action and connection timeout)
953 12:27:53.194537 /lava-568844/bin/lava-test-runner /lava-568844/0
954 12:27:53.357978 + export TESTRUN_ID=0_timesync-off
955 12:27:53.358371 + cd /lava-568844/0/tests/0_timesync-off
956 12:27:53.360160 + cat uuid
957 12:27:53.368037 + UUID=568844_1.1.3.1
958 12:27:53.368344 + set +x
959 12:27:53.368868 <LAVA_SIGNAL_STARTRUN 0_timesync-off 568844_1.1.3.1>
960 12:27:53.369341 Received signal: <STARTRUN> 0_timesync-off 568844_1.1.3.1
961 12:27:53.369515 Starting test lava.0_timesync-off (568844_1.1.3.1)
962 12:27:53.369749 Skipping test definition patterns.
963 12:27:53.369981 + systemctl stop systemd-timesyncd
964 12:27:53.624339 + set +x
965 12:27:53.624582 <LAVA_SIGNAL_ENDRUN 0_timesync-off 568844_1.1.3.1>
966 12:27:53.624863 Received signal: <ENDRUN> 0_timesync-off 568844_1.1.3.1
967 12:27:53.624977 Ending use of test pattern.
968 12:27:53.625066 Ending test lava.0_timesync-off (568844_1.1.3.1), duration 0.26
970 12:27:53.671491 + export TESTRUN_ID=1_kselftest-arm64_qemu
971 12:27:53.671711 + cd /lava-568844/0/tests/1_kselftest-arm64_qemu
972 12:27:53.673583 + cat uuid
973 12:27:53.681411 + UUID=568844_1.1.3.5
974 12:27:53.681546 + set +x
975 12:27:53.681776 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 568844_1.1.3.5>
976 12:27:53.681888 + cd ./automated/linux/kselftest/
977 12:27:53.682176 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 568844_1.1.3.5
978 12:27:53.682278 Starting test lava.1_kselftest-arm64_qemu (568844_1.1.3.5)
979 12:27:53.682400 Skipping test definition patterns.
980 12:27:53.686030 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip-gitlab -e -p /opt/kselftests/mainline/ -n 1 -i 1
981 12:27:53.777425 INFO: install_deps skipped
982 12:27:53.808749 --2023-06-06 12:27:53-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
983 12:27:53.905873 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
984 12:27:54.110303 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
985 12:27:54.309040 HTTP request sent, awaiting response... 200 OK
986 12:27:54.311686 Length: 2704052 (2.6M) [application/octet-stream]
987 12:27:54.313414 Saving to: 'kselftest.tar.xz'
988 12:27:54.314864
989 12:27:55.638030 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 148KB/s kselftest.tar.xz 8%[> ] 211.35K 301KB/s kselftest.tar.xz 28%[====> ] 749.12K 829KB/s kselftest.tar.xz 58%[==========> ] 1.52M 1.37MB/s kselftest.tar.xz 88%[================> ] 2.28M 1.75MB/s kselftest.tar.xz 100%[===================>] 2.58M 1.95MB/s in 1.3s
990 12:27:55.638326
991 12:27:55.645905 2023-06-06 12:27:55 (1.95 MB/s) - 'kselftest.tar.xz' saved [2704052/2704052]
992 12:27:55.646090
993 12:27:58.744358 skiplist:
994 12:27:58.744804 ========================================
995 12:27:58.745376 ========================================
996 12:27:58.797830 arm64:tags_test
997 12:27:58.798215 arm64:run_tags_test.sh
998 12:27:58.798430 arm64:fake_sigreturn_bad_magic
999 12:27:58.798607 arm64:fake_sigreturn_bad_size
1000 12:27:58.798774 arm64:fake_sigreturn_bad_size_for_magic0
1001 12:27:58.798961 arm64:fake_sigreturn_duplicated_fpsimd
1002 12:27:58.799182 arm64:fake_sigreturn_misaligned_sp
1003 12:27:58.799395 arm64:fake_sigreturn_missing_fpsimd
1004 12:27:58.799600 arm64:fake_sigreturn_sme_change_vl
1005 12:27:58.800090 arm64:fake_sigreturn_sve_change_vl
1006 12:27:58.800327 arm64:mangle_pstate_invalid_compat_toggle
1007 12:27:58.800562 arm64:mangle_pstate_invalid_daif_bits
1008 12:27:58.800781 arm64:mangle_pstate_invalid_mode_el1h
1009 12:27:58.800995 arm64:mangle_pstate_invalid_mode_el1t
1010 12:27:58.801164 arm64:mangle_pstate_invalid_mode_el2h
1011 12:27:58.801319 arm64:mangle_pstate_invalid_mode_el2t
1012 12:27:58.801471 arm64:mangle_pstate_invalid_mode_el3h
1013 12:27:58.801628 arm64:mangle_pstate_invalid_mode_el3t
1014 12:27:58.801764 arm64:sme_trap_no_sm
1015 12:27:58.801903 arm64:sme_trap_non_streaming
1016 12:27:58.802045 arm64:sme_trap_za
1017 12:27:58.802165 arm64:sme_vl
1018 12:27:58.802357 arm64:ssve_regs
1019 12:27:58.802487 arm64:sve_regs
1020 12:27:58.802603 arm64:sve_vl
1021 12:27:58.802718 arm64:za_no_regs
1022 12:27:58.802840 arm64:za_regs
1023 12:27:58.802991 arm64:pac
1024 12:27:58.803115 arm64:fp-stress
1025 12:27:58.803284 arm64:sve-ptrace
1026 12:27:58.803409 arm64:sve-probe-vls
1027 12:27:58.803528 arm64:vec-syscfg
1028 12:27:58.803644 arm64:za-fork
1029 12:27:58.803757 arm64:za-ptrace
1030 12:27:58.803911 arm64:check_buffer_fill
1031 12:27:58.804069 arm64:check_child_memory
1032 12:27:58.804190 arm64:check_gcr_el1_cswitch
1033 12:27:58.804305 arm64:check_ksm_options
1034 12:27:58.804419 arm64:check_mmap_options
1035 12:27:58.804534 arm64:check_prctl
1036 12:27:58.804654 arm64:check_tags_inclusion
1037 12:27:58.804808 arm64:check_user_mem
1038 12:27:58.804930 arm64:btitest
1039 12:27:58.805087 arm64:nobtitest
1040 12:27:58.805208 arm64:hwcap
1041 12:27:58.805322 arm64:ptrace
1042 12:27:58.805448 arm64:syscall-abi
1043 12:27:58.805582 arm64:tpidr2
1044 12:27:58.812966 ============== Tests to run ===============
1045 12:27:58.817873 arm64:tags_test
1046 12:27:58.818189 arm64:run_tags_test.sh
1047 12:27:58.818302 arm64:fake_sigreturn_bad_magic
1048 12:27:58.818398 arm64:fake_sigreturn_bad_size
1049 12:27:58.818506 arm64:fake_sigreturn_bad_size_for_magic0
1050 12:27:58.819019 arm64:fake_sigreturn_duplicated_fpsimd
1051 12:27:58.819381 arm64:fake_sigreturn_misaligned_sp
1052 12:27:58.819645 arm64:fake_sigreturn_missing_fpsimd
1053 12:27:58.819805 arm64:fake_sigreturn_sme_change_vl
1054 12:27:58.819935 arm64:fake_sigreturn_sve_change_vl
1055 12:27:58.820140 arm64:mangle_pstate_invalid_compat_toggle
1056 12:27:58.820332 arm64:mangle_pstate_invalid_daif_bits
1057 12:27:58.820534 arm64:mangle_pstate_invalid_mode_el1h
1058 12:27:58.820713 arm64:mangle_pstate_invalid_mode_el1t
1059 12:27:58.820863 arm64:mangle_pstate_invalid_mode_el2h
1060 12:27:58.821038 arm64:mangle_pstate_invalid_mode_el2t
1061 12:27:58.821224 arm64:mangle_pstate_invalid_mode_el3h
1062 12:27:58.821381 arm64:mangle_pstate_invalid_mode_el3t
1063 12:27:58.821505 arm64:sme_trap_no_sm
1064 12:27:58.821619 arm64:sme_trap_non_streaming
1065 12:27:58.821866 arm64:sme_trap_za
1066 12:27:58.822055 arm64:sme_vl
1067 12:27:58.822209 arm64:ssve_regs
1068 12:27:58.822352 arm64:sve_regs
1069 12:27:58.822496 arm64:sve_vl
1070 12:27:58.822637 arm64:za_no_regs
1071 12:27:58.822778 arm64:za_regs
1072 12:27:58.822921 arm64:pac
1073 12:27:58.823060 arm64:fp-stress
1074 12:27:58.823200 arm64:sve-ptrace
1075 12:27:58.823342 arm64:sve-probe-vls
1076 12:27:58.823504 arm64:vec-syscfg
1077 12:27:58.823676 arm64:za-fork
1078 12:27:58.823820 arm64:za-ptrace
1079 12:27:58.823960 arm64:check_buffer_fill
1080 12:27:58.824099 arm64:check_child_memory
1081 12:27:58.824239 arm64:check_gcr_el1_cswitch
1082 12:27:58.824379 arm64:check_ksm_options
1083 12:27:58.824519 arm64:check_mmap_options
1084 12:27:58.824659 arm64:check_prctl
1085 12:27:58.824800 arm64:check_tags_inclusion
1086 12:27:58.824940 arm64:check_user_mem
1087 12:27:58.825080 arm64:btitest
1088 12:27:58.825221 arm64:nobtitest
1089 12:27:58.825360 arm64:hwcap
1090 12:27:58.825500 arm64:ptrace
1091 12:27:58.825640 arm64:syscall-abi
1092 12:27:58.825798 arm64:tpidr2
1093 12:27:58.825978 ===========End Tests to run ===============
1094 12:27:59.775710 <12>[ 29.133070] kselftest: Running tests in arm64
1095 12:27:59.804165 TAP version 13
1096 12:27:59.822489 1..48
1097 12:27:59.868997 # selftests: arm64: tags_test
1098 12:27:59.924185 ok 1 selftests: arm64: tags_test
1099 12:27:59.967810 # selftests: arm64: run_tags_test.sh
1100 12:28:00.018713 # --------------------
1101 12:28:00.018957 # running tags test
1102 12:28:00.019278 # --------------------
1103 12:28:00.019386 # [PASS]
1104 12:28:00.026170 ok 2 selftests: arm64: run_tags_test.sh
1105 12:28:00.071715 # selftests: arm64: fake_sigreturn_bad_magic
1106 12:28:00.118244 # Registered handlers for all signals.
1107 12:28:00.118918 # Detected MINSTKSIGSZ:10000
1108 12:28:00.119125 # Testcase initialized.
1109 12:28:00.119303 # uc context validated.
1110 12:28:00.119480 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1111 12:28:00.119657 # Handled SIG_COPYCTX
1112 12:28:00.119802 # Available space:3536
1113 12:28:00.119921 # Using badly built context - ERR: BAD MAGIC !
1114 12:28:00.120062 # SIG_OK -- SP:0xFFFFD328CDB0 si_addr@:0xffffd328cdb0 si_code:2 token@:0xffffd328bb50 offset:-4704
1115 12:28:00.120185 # ==>> completed. PASS(1)
1116 12:28:00.120299 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1117 12:28:00.120415 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD328BB50
1118 12:28:00.129257 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1119 12:28:00.174343 # selftests: arm64: fake_sigreturn_bad_size
1120 12:28:00.230857 # Registered handlers for all signals.
1121 12:28:00.231174 # Detected MINSTKSIGSZ:10000
1122 12:28:00.231917 # Testcase initialized.
1123 12:28:00.232042 # uc context validated.
1124 12:28:00.232145 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1125 12:28:00.232232 # Handled SIG_COPYCTX
1126 12:28:00.232313 # Available space:3536
1127 12:28:00.232394 # uc context validated.
1128 12:28:00.232475 # Using badly built context - ERR: Bad size for esr_context
1129 12:28:00.232558 # SIG_OK -- SP:0xFFFFC0FFC9B0 si_addr@:0xffffc0ffc9b0 si_code:2 token@:0xffffc0ffb750 offset:-4704
1130 12:28:00.232643 # ==>> completed. PASS(1)
1131 12:28:00.232727 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1132 12:28:00.232813 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC0FFB750
1133 12:28:00.245334 ok 4 selftests: arm64: fake_sigreturn_bad_size
1134 12:28:00.309056 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1135 12:28:00.358518 # Registered handlers for all signals.
1136 12:28:00.358797 # Detected MINSTKSIGSZ:10000
1137 12:28:00.358901 # Testcase initialized.
1138 12:28:00.358995 # uc context validated.
1139 12:28:00.359417 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1140 12:28:00.359541 # Handled SIG_COPYCTX
1141 12:28:00.359637 # Available space:3536
1142 12:28:00.359756 # Using badly built context - ERR: Bad size for terminator
1143 12:28:00.359862 # SIG_OK -- SP:0xFFFFD983B560 si_addr@:0xffffd983b560 si_code:2 token@:0xffffd983a300 offset:-4704
1144 12:28:00.359956 # ==>> completed. PASS(1)
1145 12:28:00.360069 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1146 12:28:00.360180 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD983A300
1147 12:28:00.367275 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1148 12:28:00.412870 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1149 12:28:00.464449 # Registered handlers for all signals.
1150 12:28:00.464902 # Detected MINSTKSIGSZ:10000
1151 12:28:00.465009 # Testcase initialized.
1152 12:28:00.465137 # uc context validated.
1153 12:28:00.465269 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1154 12:28:00.465358 # Handled SIG_COPYCTX
1155 12:28:00.465445 # Available space:3536
1156 12:28:00.465554 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1157 12:28:00.465653 # SIG_OK -- SP:0xFFFFDAE10B70 si_addr@:0xffffdae10b70 si_code:2 token@:0xffffdae0f910 offset:-4704
1158 12:28:00.465746 # ==>> completed. PASS(1)
1159 12:28:00.465835 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1160 12:28:00.465943 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDAE0F910
1161 12:28:00.473294 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1162 12:28:00.520851 # selftests: arm64: fake_sigreturn_misaligned_sp
1163 12:28:00.570395 # Registered handlers for all signals.
1164 12:28:00.570776 # Detected MINSTKSIGSZ:10000
1165 12:28:00.571241 # Testcase initialized.
1166 12:28:00.571355 # uc context validated.
1167 12:28:00.571450 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1168 12:28:00.571540 # Handled SIG_COPYCTX
1169 12:28:00.571630 # SIG_OK -- SP:0xFFFFE7E8E873 si_addr@:0xffffe7e8e873 si_code:2 token@:0xffffe7e8e873 offset:0
1170 12:28:00.571722 # ==>> completed. PASS(1)
1171 12:28:00.571813 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1172 12:28:00.571903 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE7E8E873
1173 12:28:00.579423 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1174 12:28:00.626281 # selftests: arm64: fake_sigreturn_missing_fpsimd
1175 12:28:00.679733 # Registered handlers for all signals.
1176 12:28:00.680320 # Detected MINSTKSIGSZ:10000
1177 12:28:00.680431 # Testcase initialized.
1178 12:28:00.680523 # uc context validated.
1179 12:28:00.680611 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1180 12:28:00.680696 # Handled SIG_COPYCTX
1181 12:28:00.680780 # Mangling template header. Spare space:4096
1182 12:28:00.680864 # Using badly built context - ERR: Missing FPSIMD
1183 12:28:00.680967 # SIG_OK -- SP:0xFFFFDB4215F0 si_addr@:0xffffdb4215f0 si_code:2 token@:0xffffdb420390 offset:-4704
1184 12:28:00.681062 # ==>> completed. PASS(1)
1185 12:28:00.681146 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1186 12:28:00.681247 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB420390
1187 12:28:00.691127 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1188 12:28:00.739844 # selftests: arm64: fake_sigreturn_sme_change_vl
1189 12:28:00.793243 # Registered handlers for all signals.
1190 12:28:00.793485 # Detected MINSTKSIGSZ:10000
1191 12:28:00.793798 # Required Features: [ SME ] supported
1192 12:28:00.793909 # Incompatible Features: [] absent
1193 12:28:00.794006 # Testcase initialized.
1194 12:28:00.795354 # uc context validated.
1195 12:28:00.795780 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1196 12:28:00.795923 # Handled SIG_COPYCTX
1197 12:28:00.796085 # Attempting to change VL from 16 to 256
1198 12:28:00.796279 # SIG_OK -- SP:0xFFFFFC1631C0 si_addr@:0xfffffc1631c0 si_code:2 token@:0xfffffc161f60 offset:-4704
1199 12:28:00.796380 # ==>> completed. PASS(1)
1200 12:28:00.796469 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1201 12:28:00.796576 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFC161F60
1202 12:28:00.803509 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1203 12:28:00.850118 # selftests: arm64: fake_sigreturn_sve_change_vl
1204 12:28:00.902227 # Registered handlers for all signals.
1205 12:28:00.902578 # Detected MINSTKSIGSZ:10000
1206 12:28:00.902991 # Required Features: [ SVE ] supported
1207 12:28:00.903178 # Incompatible Features: [] absent
1208 12:28:00.903349 # Testcase initialized.
1209 12:28:00.903490 # uc context validated.
1210 12:28:00.903610 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1211 12:28:00.903735 # Handled SIG_COPYCTX
1212 12:28:00.903910 # Attempting to change VL from 16 to 256
1213 12:28:00.904097 # SIG_OK -- SP:0xFFFFC39D34C0 si_addr@:0xffffc39d34c0 si_code:2 token@:0xffffc39d2260 offset:-4704
1214 12:28:00.904236 # ==>> completed. PASS(1)
1215 12:28:00.904383 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1216 12:28:00.904527 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC39D2260
1217 12:28:00.911641 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1218 12:28:00.962072 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1219 12:28:01.011825 # Registered handlers for all signals.
1220 12:28:01.012288 # Detected MINSTKSIGSZ:10000
1221 12:28:01.012397 # Testcase initialized.
1222 12:28:01.012492 # uc context validated.
1223 12:28:01.012587 # Handled SIG_TRIG
1224 12:28:01.012696 # SIG_OK -- SP:0xFFFFD312FDE0 si_addr@:0xffffd312fde0 si_code:2 token@:(nil) offset:-281474222980576
1225 12:28:01.012791 # ==>> completed. PASS(1)
1226 12:28:01.012879 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1227 12:28:01.021152 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1228 12:28:01.073251 # selftests: arm64: mangle_pstate_invalid_daif_bits
1229 12:28:01.131935 # Registered handlers for all signals.
1230 12:28:01.132309 # Detected MINSTKSIGSZ:10000
1231 12:28:01.132689 # Testcase initialized.
1232 12:28:01.132823 # uc context validated.
1233 12:28:01.132943 # Handled SIG_TRIG
1234 12:28:01.133061 # SIG_OK -- SP:0xFFFFCDCD2F50 si_addr@:0xffffcdcd2f50 si_code:2 token@:(nil) offset:-281474134519632
1235 12:28:01.133179 # ==>> completed. PASS(1)
1236 12:28:01.133295 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1237 12:28:01.143764 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1238 12:28:01.201921 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1239 12:28:01.271802 # Registered handlers for all signals.
1240 12:28:01.272112 # Detected MINSTKSIGSZ:10000
1241 12:28:01.272502 # Testcase initialized.
1242 12:28:01.272675 # uc context validated.
1243 12:28:01.272813 # Handled SIG_TRIG
1244 12:28:01.272978 # SIG_OK -- SP:0xFFFFFB4C27C0 si_addr@:0xfffffb4c27c0 si_code:2 token@:(nil) offset:-281474897815488
1245 12:28:01.273116 # ==>> completed. PASS(1)
1246 12:28:01.273253 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1247 12:28:01.282388 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1248 12:28:01.334047 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1249 12:28:01.384332 # Registered handlers for all signals.
1250 12:28:01.384684 # Detected MINSTKSIGSZ:10000
1251 12:28:01.385137 # Testcase initialized.
1252 12:28:01.385334 # uc context validated.
1253 12:28:01.385510 # Handled SIG_TRIG
1254 12:28:01.385731 # SIG_OK -- SP:0xFFFFC4647880 si_addr@:0xffffc4647880 si_code:2 token@:(nil) offset:-281473976662144
1255 12:28:01.385924 # ==>> completed. PASS(1)
1256 12:28:01.386097 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1257 12:28:01.392918 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1258 12:28:01.440319 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1259 12:28:01.493489 # Registered handlers for all signals.
1260 12:28:01.493820 # Detected MINSTKSIGSZ:10000
1261 12:28:01.493977 # Testcase initialized.
1262 12:28:01.495972 # uc context validated.
1263 12:28:01.496372 # Handled SIG_TRIG
1264 12:28:01.496492 # SIG_OK -- SP:0xFFFFDA8C1860 si_addr@:0xffffda8c1860 si_code:2 token@:(nil) offset:-281474348357728
1265 12:28:01.496586 # ==>> completed. PASS(1)
1266 12:28:01.496676 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1267 12:28:01.503520 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1268 12:28:01.561112 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1269 12:28:01.618017 # Registered handlers for all signals.
1270 12:28:01.618235 # Detected MINSTKSIGSZ:10000
1271 12:28:01.618336 # Testcase initialized.
1272 12:28:01.618444 # uc context validated.
1273 12:28:01.618535 # Handled SIG_TRIG
1274 12:28:01.618623 # SIG_OK -- SP:0xFFFFC0893630 si_addr@:0xffffc0893630 si_code:2 token@:(nil) offset:-281473911961136
1275 12:28:01.618729 # ==>> completed. PASS(1)
1276 12:28:01.618820 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1277 12:28:01.628159 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1278 12:28:01.676670 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1279 12:28:01.728290 # Registered handlers for all signals.
1280 12:28:01.728755 # Detected MINSTKSIGSZ:10000
1281 12:28:01.728872 # Testcase initialized.
1282 12:28:01.728965 # uc context validated.
1283 12:28:01.729054 # Handled SIG_TRIG
1284 12:28:01.729156 # SIG_OK -- SP:0xFFFFFE2CFCC0 si_addr@:0xfffffe2cfcc0 si_code:2 token@:(nil) offset:-281474946104512
1285 12:28:01.729246 # ==>> completed. PASS(1)
1286 12:28:01.729331 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1287 12:28:01.736965 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1288 12:28:01.785074 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1289 12:28:01.835624 # Registered handlers for all signals.
1290 12:28:01.835857 # Detected MINSTKSIGSZ:10000
1291 12:28:01.836169 # Testcase initialized.
1292 12:28:01.836279 # uc context validated.
1293 12:28:01.836372 # Handled SIG_TRIG
1294 12:28:01.836462 # SIG_OK -- SP:0xFFFFEC3C3110 si_addr@:0xffffec3c3110 si_code:2 token@:(nil) offset:-281474645111056
1295 12:28:01.836550 # ==>> completed. PASS(1)
1296 12:28:01.836651 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1297 12:28:01.844253 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1298 12:28:01.893899 # selftests: arm64: sme_trap_no_sm
1299 12:28:02.016260 # Registered handlers for all signals.
1300 12:28:02.016804 # Detected MINSTKSIGSZ:10000
1301 12:28:02.016914 # Required Features: [ SME ] supported
1302 12:28:02.017000 # Incompatible Features: [] absent
1303 12:28:02.017089 # Testcase initialized.
1304 12:28:02.017194 # SIG_OK -- SP:0xFFFFE9EE3A00 si_addr@:0xaaaabcba2514 si_code:1 token@:(nil) offset:-187650287478036
1305 12:28:02.017280 # ==>> completed. PASS(1)
1306 12:28:02.020710 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1307 12:28:02.033776 ok 19 selftests: arm64: sme_trap_no_sm
1308 12:28:02.133806 # selftests: arm64: sme_trap_non_streaming
1309 12:28:02.196452 # Registered handlers for all signals.
1310 12:28:02.196615 # Detected MINSTKSIGSZ:10000
1311 12:28:02.196912 # Required Features: [] NOT supported
1312 12:28:02.197024 # Incompatible Features: [] supported
1313 12:28:02.197106 # ==>> completed. SKIP.
1314 12:28:02.197181 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1315 12:28:02.206795 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1316 12:28:02.259845 # selftests: arm64: sme_trap_za
1317 12:28:02.312431 # Registered handlers for all signals.
1318 12:28:02.313033 # Detected MINSTKSIGSZ:10000
1319 12:28:02.313210 # Testcase initialized.
1320 12:28:02.313387 # SIG_OK -- SP:0xFFFFDEBA2650 si_addr@:0xaaaac7ac2510 si_code:1 token@:(nil) offset:-187650471109904
1321 12:28:02.313541 # ==>> completed. PASS(1)
1322 12:28:02.313738 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1323 12:28:02.322724 ok 21 selftests: arm64: sme_trap_za
1324 12:28:02.373459 # selftests: arm64: sme_vl
1325 12:28:02.428349 # Registered handlers for all signals.
1326 12:28:02.428602 # Detected MINSTKSIGSZ:10000
1327 12:28:02.428912 # Required Features: [ SME ] supported
1328 12:28:02.429019 # Incompatible Features: [] absent
1329 12:28:02.429109 # Testcase initialized.
1330 12:28:02.429197 # uc context validated.
1331 12:28:02.429299 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1332 12:28:02.430767 # Handled SIG_COPYCTX
1333 12:28:02.430877 # got expected VL 32
1334 12:28:02.431194 # ==>> completed. PASS(1)
1335 12:28:02.431289 # # SME VL :: Check that we get the right SME VL reported
1336 12:28:02.438931 ok 22 selftests: arm64: sme_vl
1337 12:28:02.487856 # selftests: arm64: ssve_regs
1338 12:28:02.677396 # Registered handlers for all signals.
1339 12:28:02.677866 # Detected MINSTKSIGSZ:10000
1340 12:28:02.677983 # Required Features: [ SME FA64 ] supported
1341 12:28:02.678078 # Incompatible Features: [] absent
1342 12:28:02.678168 # Testcase initialized.
1343 12:28:02.678255 # Testing VL 256
1344 12:28:02.678342 # Validating EXTRA...
1345 12:28:02.678430 # uc context validated.
1346 12:28:02.678540 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1347 12:28:02.678631 # Handled SIG_COPYCTX
1348 12:28:02.678718 # Got expected size 8752 and VL 256
1349 12:28:02.678806 # Testing VL 128
1350 12:28:02.678891 # Validating EXTRA...
1351 12:28:02.678975 # uc context validated.
1352 12:28:02.679080 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1353 12:28:02.679169 # Handled SIG_COPYCTX
1354 12:28:02.679255 # Got expected size 4384 and VL 128
1355 12:28:02.679340 # Testing VL 64
1356 12:28:02.679423 # uc context validated.
1357 12:28:02.679525 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1358 12:28:02.679613 # Handled SIG_COPYCTX
1359 12:28:02.679696 # Got expected size 2208 and VL 64
1360 12:28:02.679782 # Testing VL 32
1361 12:28:02.679864 # uc context validated.
1362 12:28:02.679963 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1363 12:28:02.680050 # Handled SIG_COPYCTX
1364 12:28:02.680135 # Got expected size 1120 and VL 32
1365 12:28:02.680221 # Testing VL 16
1366 12:28:02.680305 # uc context validated.
1367 12:28:02.680403 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1368 12:28:02.680487 # Handled SIG_COPYCTX
1369 12:28:02.680569 # Got expected size 576 and VL 16
1370 12:28:02.680655 # ==>> completed. PASS(1)
1371 12:28:02.680761 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1372 12:28:02.689727 ok 23 selftests: arm64: ssve_regs
1373 12:28:02.739946 # selftests: arm64: sve_regs
1374 12:28:03.217931 # Registered handlers for all signals.
1375 12:28:03.218194 # Detected MINSTKSIGSZ:10000
1376 12:28:03.218508 # Required Features: [ SVE ] supported
1377 12:28:03.218613 # Incompatible Features: [] absent
1378 12:28:03.218706 # Testcase initialized.
1379 12:28:03.218796 # Testing VL 256
1380 12:28:03.218887 # Validating EXTRA...
1381 12:28:03.218977 # uc context validated.
1382 12:28:03.219090 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1383 12:28:03.219183 # Handled SIG_COPYCTX
1384 12:28:03.219273 # Got expected size 8752 and VL 256
1385 12:28:03.219361 # Testing VL 240
1386 12:28:03.219449 # Validating EXTRA...
1387 12:28:03.219540 # uc context validated.
1388 12:28:03.219628 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1389 12:28:03.219715 # Handled SIG_COPYCTX
1390 12:28:03.219802 # Got expected size 8208 and VL 240
1391 12:28:03.219890 # Testing VL 224
1392 12:28:03.219982 # Validating EXTRA...
1393 12:28:03.220095 # uc context validated.
1394 12:28:03.220187 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1395 12:28:03.220276 # Handled SIG_COPYCTX
1396 12:28:03.220363 # Got expected size 7664 and VL 224
1397 12:28:03.220452 # Testing VL 208
1398 12:28:03.220543 # Validating EXTRA...
1399 12:28:03.220632 # uc context validated.
1400 12:28:03.220719 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1401 12:28:03.220807 # Handled SIG_COPYCTX
1402 12:28:03.220894 # Got expected size 7120 and VL 208
1403 12:28:03.220986 # Testing VL 192
1404 12:28:03.221077 # Validating EXTRA...
1405 12:28:03.221164 # uc context validated.
1406 12:28:03.221252 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1407 12:28:03.221359 # Handled SIG_COPYCTX
1408 12:28:03.221454 # Got expected size 6576 and VL 192
1409 12:28:03.221541 # Testing VL 176
1410 12:28:03.221623 # Validating EXTRA...
1411 12:28:03.221712 # uc context validated.
1412 12:28:03.221803 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1413 12:28:03.221896 # Handled SIG_COPYCTX
1414 12:28:03.221981 # Got expected size 6032 and VL 176
1415 12:28:03.222066 # Testing VL 160
1416 12:28:03.222152 # Validating EXTRA...
1417 12:28:03.222238 # uc context validated.
1418 12:28:03.247023 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1419 12:28:03.247313 # Handled SIG_COPYCTX
1420 12:28:03.247456 # Got expected size 5488 and VL 160
1421 12:28:03.247580 # Testing VL 144
1422 12:28:03.247932 # Validating EXTRA...
1423 12:28:03.248066 # uc context validated.
1424 12:28:03.248189 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1425 12:28:03.248309 # Handled SIG_COPYCTX
1426 12:28:03.248428 # Got expected size 4944 and VL 144
1427 12:28:03.248547 # Testing VL 128
1428 12:28:03.248665 # Validating EXTRA...
1429 12:28:03.248780 # uc context validated.
1430 12:28:03.248898 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1431 12:28:03.249016 # Handled SIG_COPYCTX
1432 12:28:03.249134 # Got expected size 4384 and VL 128
1433 12:28:03.249251 # Testing VL 112
1434 12:28:03.249368 # Validating EXTRA...
1435 12:28:03.249486 # uc context validated.
1436 12:28:03.249602 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1437 12:28:03.249739 # Handled SIG_COPYCTX
1438 12:28:03.249862 # Got expected size 3840 and VL 112
1439 12:28:03.249979 # Testing VL 96
1440 12:28:03.250098 # uc context validated.
1441 12:28:03.250242 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1442 12:28:03.250360 # Handled SIG_COPYCTX
1443 12:28:03.250473 # Got expected size 3296 and VL 96
1444 12:28:03.250589 # Testing VL 80
1445 12:28:03.250703 # uc context validated.
1446 12:28:03.250816 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1447 12:28:03.250933 # Handled SIG_COPYCTX
1448 12:28:03.251046 # Got expected size 2752 and VL 80
1449 12:28:03.251160 # Testing VL 64
1450 12:28:03.251272 # uc context validated.
1451 12:28:03.251384 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1452 12:28:03.251498 # Handled SIG_COPYCTX
1453 12:28:03.251610 # Got expected size 2208 and VL 64
1454 12:28:03.269019 # Testing VL 48
1455 12:28:03.269283 # uc context validated.
1456 12:28:03.269597 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1457 12:28:03.269712 # Handled SIG_COPYCTX
1458 12:28:03.269810 # Got expected size 1664 and VL 48
1459 12:28:03.269902 # Testing VL 32
1460 12:28:03.269989 # uc context validated.
1461 12:28:03.270076 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1462 12:28:03.270183 # Handled SIG_COPYCTX
1463 12:28:03.270277 # Got expected size 1120 and VL 32
1464 12:28:03.270367 # Testing VL 16
1465 12:28:03.270454 # uc context validated.
1466 12:28:03.270541 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1467 12:28:03.270628 # Handled SIG_COPYCTX
1468 12:28:03.270715 # Got expected size 576 and VL 16
1469 12:28:03.270823 # ==>> completed. PASS(1)
1470 12:28:03.270912 # # SVE registers :: Check that we get the right SVE registers reported
1471 12:28:03.271000 ok 24 selftests: arm64: sve_regs
1472 12:28:03.319392 # selftests: arm64: sve_vl
1473 12:28:03.372118 # Registered handlers for all signals.
1474 12:28:03.372445 # Detected MINSTKSIGSZ:10000
1475 12:28:03.372628 # Required Features: [ SVE ] supported
1476 12:28:03.373077 # Incompatible Features: [] absent
1477 12:28:03.373247 # Testcase initialized.
1478 12:28:03.373405 # uc context validated.
1479 12:28:03.373572 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1480 12:28:03.373774 # Handled SIG_COPYCTX
1481 12:28:03.373917 # got expected VL 64
1482 12:28:03.374102 # ==>> completed. PASS(1)
1483 12:28:03.374488 # # SVE VL :: Check that we get the right SVE VL reported
1484 12:28:03.380657 ok 25 selftests: arm64: sve_vl
1485 12:28:03.429312 # selftests: arm64: za_no_regs
1486 12:28:03.492708 # Registered handlers for all signals.
1487 12:28:03.494274 # Detected MINSTKSIGSZ:10000
1488 12:28:03.494658 # Required Features: [ SME ] supported
1489 12:28:03.494799 # Incompatible Features: [] absent
1490 12:28:03.494930 # Testcase initialized.
1491 12:28:03.495055 # Testing VL 256
1492 12:28:03.495182 # uc context validated.
1493 12:28:03.495310 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1494 12:28:03.495497 # Handled SIG_COPYCTX
1495 12:28:03.495686 # Got expected size 16 and VL 256
1496 12:28:03.495821 # Testing VL 128
1497 12:28:03.495951 # uc context validated.
1498 12:28:03.496076 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1499 12:28:03.496203 # Handled SIG_COPYCTX
1500 12:28:03.496331 # Got expected size 16 and VL 128
1501 12:28:03.496451 # Testing VL 64
1502 12:28:03.496574 # uc context validated.
1503 12:28:03.496693 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1504 12:28:03.496816 # Handled SIG_COPYCTX
1505 12:28:03.496933 # Got expected size 16 and VL 64
1506 12:28:03.497049 # Testing VL 32
1507 12:28:03.497168 # uc context validated.
1508 12:28:03.497288 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1509 12:28:03.497403 # Handled SIG_COPYCTX
1510 12:28:03.497520 # Got expected size 16 and VL 32
1511 12:28:03.497681 # Testing VL 16
1512 12:28:03.497808 # uc context validated.
1513 12:28:03.497934 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1514 12:28:03.498053 # Handled SIG_COPYCTX
1515 12:28:03.498169 # Got expected size 16 and VL 16
1516 12:28:03.498288 # ==>> completed. PASS(1)
1517 12:28:03.498404 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1518 12:28:03.503445 ok 26 selftests: arm64: za_no_regs
1519 12:28:03.552494 # selftests: arm64: za_regs
1520 12:28:03.733113 # Registered handlers for all signals.
1521 12:28:03.733406 # Detected MINSTKSIGSZ:10000
1522 12:28:03.733765 # Required Features: [ SME ] supported
1523 12:28:03.733878 # Incompatible Features: [] absent
1524 12:28:03.733973 # Testcase initialized.
1525 12:28:03.734064 # Testing VL 256
1526 12:28:03.734157 # Validating EXTRA...
1527 12:28:03.734251 # uc context validated.
1528 12:28:03.734342 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1529 12:28:03.734431 # Handled SIG_COPYCTX
1530 12:28:03.734540 # Got expected size 65552 and VL 256
1531 12:28:03.734633 # Testing VL 128
1532 12:28:03.734725 # Validating EXTRA...
1533 12:28:03.734815 # uc context validated.
1534 12:28:03.734903 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1535 12:28:03.734993 # Handled SIG_COPYCTX
1536 12:28:03.735081 # Got expected size 16400 and VL 128
1537 12:28:03.735173 # Testing VL 64
1538 12:28:03.735265 # Validating EXTRA...
1539 12:28:03.735355 # uc context validated.
1540 12:28:03.735465 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1541 12:28:03.735559 # Handled SIG_COPYCTX
1542 12:28:03.735648 # Got expected size 4112 and VL 64
1543 12:28:03.735741 # Testing VL 32
1544 12:28:03.735831 # uc context validated.
1545 12:28:03.735919 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1546 12:28:03.736009 # Handled SIG_COPYCTX
1547 12:28:03.736097 # Got expected size 1040 and VL 32
1548 12:28:03.736189 # Testing VL 16
1549 12:28:03.736281 # uc context validated.
1550 12:28:03.736371 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1551 12:28:03.736467 # Handled SIG_COPYCTX
1552 12:28:03.736554 # Got expected size 272 and VL 16
1553 12:28:03.736640 # ==>> completed. PASS(1)
1554 12:28:03.736732 # # ZA register :: Check that we get the right ZA registers reported
1555 12:28:03.744177 ok 27 selftests: arm64: za_regs
1556 12:28:03.791941 # selftests: arm64: pac
1557 12:28:03.949524 # TAP version 13
1558 12:28:03.949878 # 1..7
1559 12:28:03.950075 # # Starting 7 tests from 1 test cases.
1560 12:28:03.950525 # # RUN global.corrupt_pac ...
1561 12:28:03.950749 # # OK global.corrupt_pac
1562 12:28:03.950962 # ok 1 global.corrupt_pac
1563 12:28:03.951186 # # RUN global.pac_instructions_not_nop ...
1564 12:28:03.951400 # # OK global.pac_instructions_not_nop
1565 12:28:03.951624 # ok 2 global.pac_instructions_not_nop
1566 12:28:03.951849 # # RUN global.pac_instructions_not_nop_generic ...
1567 12:28:03.952066 # # OK global.pac_instructions_not_nop_generic
1568 12:28:03.952336 # ok 3 global.pac_instructions_not_nop_generic
1569 12:28:03.952529 # # RUN global.single_thread_different_keys ...
1570 12:28:03.952693 # # OK global.single_thread_different_keys
1571 12:28:03.952854 # ok 4 global.single_thread_different_keys
1572 12:28:03.952980 # # RUN global.exec_changed_keys ...
1573 12:28:03.953107 # # OK global.exec_changed_keys
1574 12:28:03.953231 # ok 5 global.exec_changed_keys
1575 12:28:03.953348 # # RUN global.context_switch_keep_keys ...
1576 12:28:03.953478 # # OK global.context_switch_keep_keys
1577 12:28:03.953596 # ok 6 global.context_switch_keep_keys
1578 12:28:03.953730 # # RUN global.context_switch_keep_keys_generic ...
1579 12:28:03.953847 # # OK global.context_switch_keep_keys_generic
1580 12:28:03.953979 # ok 7 global.context_switch_keep_keys_generic
1581 12:28:03.954097 # # PASSED: 7 / 7 tests passed.
1582 12:28:03.954249 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1583 12:28:03.960966 ok 28 selftests: arm64: pac
1584 12:28:04.008246 # selftests: arm64: fp-stress
1585 12:28:19.147355 # TAP version 13
1586 12:28:19.148438 # 1..27
1587 12:28:19.148549 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1588 12:28:19.148628 # # Will run for 10s
1589 12:28:19.148708 # # Started FPSIMD-0-0
1590 12:28:19.148789 # # Started SVE-VL-256-0
1591 12:28:19.148879 # # Started SVE-VL-240-0
1592 12:28:19.148972 # # Started SVE-VL-224-0
1593 12:28:19.149061 # # Started SVE-VL-208-0
1594 12:28:19.149145 # # Started SVE-VL-192-0
1595 12:28:19.149230 # # Started SVE-VL-176-0
1596 12:28:19.149310 # # Started SVE-VL-160-0
1597 12:28:19.149389 # # Started SVE-VL-144-0
1598 12:28:19.149469 # # Started SVE-VL-128-0
1599 12:28:19.149553 # # Started SVE-VL-112-0
1600 12:28:19.149833 # # Started SVE-VL-96-0
1601 12:28:19.149930 # # Started SVE-VL-80-0
1602 12:28:19.150017 # # Started SVE-VL-64-0
1603 12:28:19.150107 # # Started SVE-VL-48-0
1604 12:28:19.150190 # # Started SVE-VL-32-0
1605 12:28:19.150284 # # Started SVE-VL-16-0
1606 12:28:19.150366 # # Started SSVE-VL-256-0
1607 12:28:19.150445 # # Started ZA-VL-256-0
1608 12:28:19.150511 # # Started SSVE-VL-128-0
1609 12:28:19.150570 # # Started ZA-VL-128-0
1610 12:28:19.150657 # # Started SSVE-VL-64-0
1611 12:28:19.150751 # # Started ZA-VL-64-0
1612 12:28:19.150843 # # Started SSVE-VL-32-0
1613 12:28:19.150941 # # Started ZA-VL-32-0
1614 12:28:19.151024 # # Started SSVE-VL-16-0
1615 12:28:19.151099 # # Started ZA-VL-16-0
1616 12:28:19.162735 # # SVE-VL-256-0: Vector length: 2048 bits
1617 12:28:19.162986 # # SVE-VL-256-0: PID: 912
1618 12:28:19.163112 # # FPSIMD-0-0: Vector length: 128 bits
1619 12:28:19.163438 # # FPSIMD-0-0: PID: 911
1620 12:28:19.163548 # # SVE-VL-208-0: Vector length: 1664 bits
1621 12:28:19.163651 # # SVE-VL-208-0: PID: 915
1622 12:28:19.163738 # # SVE-VL-192-0: Vector length: 1536 bits
1623 12:28:19.163852 # # SVE-VL-192-0: PID: 916
1624 12:28:19.163940 # # SVE-VL-64-0: Vector length: 512 bits
1625 12:28:19.164037 # # SVE-VL-64-0: PID: 924
1626 12:28:19.164116 # # SVE-VL-240-0: Vector length: 1920 bits
1627 12:28:19.164214 # # SVE-VL-240-0: PID: 913
1628 12:28:19.164315 # # SVE-VL-144-0: Vector length: 1152 bits
1629 12:28:19.164425 # # SVE-VL-144-0: PID: 919
1630 12:28:19.164526 # # SVE-VL-80-0: Vector length: 640 bits
1631 12:28:19.164654 # # SVE-VL-80-0: PID: 923
1632 12:28:19.164754 # # SVE-VL-224-0: Vector length: 1792 bits
1633 12:28:19.164837 # # SVE-VL-224-0: PID: 914
1634 12:28:19.164928 # # SVE-VL-96-0: Vector length: 768 bits
1635 12:28:19.165008 # # SVE-VL-96-0: PID: 922
1636 12:28:19.165088 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1637 12:28:19.165182 # # SSVE-VL-32-0: PID: 934
1638 12:28:19.165264 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1639 12:28:19.165356 # # ZA-VL-256-0: PID: 929
1640 12:28:19.165456 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1641 12:28:19.165563 # # SSVE-VL-256-0: PID: 928
1642 12:28:19.167800 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1643 12:28:19.167954 # # SSVE-VL-128-0: PID: 930
1644 12:28:19.168089 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1645 12:28:19.168206 # # SVE-VL-16-0: Vector length: 128 bits
1646 12:28:19.168334 # # SVE-VL-16-0: PID: 927
1647 12:28:19.168442 # # SVE-VL-160-0: Vector length: 1280 bits
1648 12:28:19.168563 # # SVE-VL-32-0: Vector length: 256 bits
1649 12:28:19.168689 # # SVE-VL-32-0: PID: 926
1650 12:28:19.169020 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1651 12:28:19.169344 # # ZA-VL-64-0: PID: 933
1652 12:28:19.169464 # # SVE-VL-48-0: Vector length: 384 bits
1653 12:28:19.169579 # # SVE-VL-48-0: PID: 925
1654 12:28:19.169694 # # SVE-VL-160-0: PID: 918
1655 12:28:19.169798 # # SVE-VL-112-0: Vector length: 896 bits
1656 12:28:19.169908 # # SVE-VL-112-0: PID: 921
1657 12:28:19.170531 # # ZA-VL-128-0: PID: 931
1658 12:28:19.170619 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1659 12:28:19.170709 # # SSVE-VL-64-0: PID: 932
1660 12:28:19.170787 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1661 12:28:19.170862 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1662 12:28:19.179641 # # SSVE-VL-16-0: PID: 936
1663 12:28:19.179867 # # SVE-VL-128-0: Vector length: 1024 bits
1664 12:28:19.179989 # # SVE-VL-128-0: PID: 920
1665 12:28:19.180083 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1666 12:28:19.180176 # # ZA-VL-32-0: PID: 935
1667 12:28:19.180276 # # SVE-VL-176-0: Vector length: 1408 bits
1668 12:28:19.180364 # # SVE-VL-176-0: PID: 917
1669 12:28:19.180461 # # ZA-VL-16-0: PID: 937
1670 12:28:19.180574 # # Finishing up...
1671 12:28:19.180686 # ok 1 FPSIMD-0-0
1672 12:28:19.180778 # ok 2 SVE-VL-256-0
1673 12:28:19.180883 # ok 3 SVE-VL-240-0
1674 12:28:19.180965 # ok 4 SVE-VL-224-0
1675 12:28:19.181055 # ok 5 SVE-VL-208-0
1676 12:28:19.181133 # ok 6 SVE-VL-192-0
1677 12:28:19.181215 # ok 7 SVE-VL-176-0
1678 12:28:19.181337 # ok 8 SVE-VL-160-0
1679 12:28:19.181420 # ok 9 SVE-VL-144-0
1680 12:28:19.181509 # ok 10 SVE-VL-128-0
1681 12:28:19.181609 # ok 11 SVE-VL-112-0
1682 12:28:19.181701 # ok 12 SVE-VL-96-0
1683 12:28:19.181765 # ok 13 SVE-VL-80-0
1684 12:28:19.181827 # ok 14 SVE-VL-64-0
1685 12:28:19.181889 # ok 15 SVE-VL-48-0
1686 12:28:19.181949 # ok 16 SVE-VL-32-0
1687 12:28:19.182024 # ok 17 SVE-VL-16-0
1688 12:28:19.182092 # ok 18 SSVE-VL-256-0
1689 12:28:19.182181 # ok 19 ZA-VL-256-0
1690 12:28:19.182261 # ok 20 SSVE-VL-128-0
1691 12:28:19.199470 # ok 21 ZA-VL-128-0
1692 12:28:19.199906 # ok 22 SSVE-VL-64-0
1693 12:28:19.200004 # ok 23 ZA-VL-64-0
1694 12:28:19.200088 # ok 24 SSVE-VL-32-0
1695 12:28:19.200174 # ok 25 ZA-VL-32-0
1696 12:28:19.200266 # ok 26 SSVE-VL-16-0
1697 12:28:19.200344 # ok 27 ZA-VL-16-0
1698 12:28:19.200427 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=2745, signals=9
1699 12:28:19.200496 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1477, signals=9
1700 12:28:19.200759 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=2941, signals=9
1701 12:28:19.200854 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=10386, signals=9
1702 12:28:19.200959 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2685, signals=9
1703 12:28:19.201078 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=9799, signals=9
1704 12:28:19.201390 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3741, signals=9
1705 12:28:19.201690 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3003, signals=9
1706 12:28:19.220686 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5112, signals=9
1707 12:28:19.368117 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2210, signals=9
1708 12:28:19.368597 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2494, signals=9
1709 12:28:19.368705 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=219, signals=9
1710 12:28:19.368817 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2284, signals=9
1711 12:28:19.368925 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=978, signals=9
1712 12:28:19.369219 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=7290, signals=9
1713 12:28:19.369365 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1165, signals=9
1714 12:28:19.369675 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=3576, signals=9
1715 12:28:19.383540 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=2803, signals=9
1716 12:28:19.384224 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2248, signals=9
1717 12:28:19.384339 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=9000, signals=9
1718 12:28:19.384435 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6195, signals=9
1719 12:28:19.384537 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=5965, signals=9
1720 12:28:19.384640 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=5978, signals=9
1721 12:28:19.384930 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=3869, signals=9
1722 12:28:19.385299 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=528, signals=9
1723 12:28:19.385424 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=4657, signals=9
1724 12:28:19.385533 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=1941, signals=9
1725 12:28:19.385670 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1726 12:28:19.390769 ok 29 selftests: arm64: fp-stress
1727 12:28:19.591396 # selftests: arm64: sve-ptrace
1728 12:28:19.809184 # TAP version 13
1729 12:28:19.809696 # 1..4104
1730 12:28:19.809926 # # Parent is 954, child is 955
1731 12:28:19.810137 # ok 1 SVE FPSIMD set via SVE: 0
1732 12:28:19.810560 # ok 2 SVE get_fpsimd() gave same state
1733 12:28:19.810672 # ok 3 SVE SVE_PT_VL_INHERIT set
1734 12:28:19.810766 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1735 12:28:19.810854 # ok 5 Set SVE VL 16
1736 12:28:19.810940 # ok 6 Set and get SVE data for VL 16
1737 12:28:19.811024 # ok 7 Set and get FPSIMD data for SVE VL 16
1738 12:28:19.811109 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1739 12:28:19.811194 # ok 9 Set SVE VL 32
1740 12:28:19.811280 # ok 10 Set and get SVE data for VL 32
1741 12:28:19.811383 # ok 11 Set and get FPSIMD data for SVE VL 32
1742 12:28:19.811472 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1743 12:28:19.811559 # ok 13 Set SVE VL 48
1744 12:28:19.811643 # ok 14 Set and get SVE data for VL 48
1745 12:28:19.811727 # ok 15 Set and get FPSIMD data for SVE VL 48
1746 12:28:19.811811 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1747 12:28:19.811919 # ok 17 Set SVE VL 64
1748 12:28:19.812006 # ok 18 Set and get SVE data for VL 64
1749 12:28:19.812091 # ok 19 Set and get FPSIMD data for SVE VL 64
1750 12:28:19.812175 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1751 12:28:19.812267 # ok 21 Set SVE VL 80
1752 12:28:19.812368 # ok 22 Set and get SVE data for VL 80
1753 12:28:19.812457 # ok 23 Set and get FPSIMD data for SVE VL 80
1754 12:28:19.812558 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1755 12:28:19.812646 # ok 25 Set SVE VL 96
1756 12:28:19.812801 # ok 26 Set and get SVE data for VL 96
1757 12:28:19.812908 # ok 27 Set and get FPSIMD data for SVE VL 96
1758 12:28:19.813096 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1759 12:28:19.813190 # ok 29 Set SVE VL 112
1760 12:28:19.813278 # ok 30 Set and get SVE data for VL 112
1761 12:28:19.813380 # ok 31 Set and get FPSIMD data for SVE VL 112
1762 12:28:19.813752 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1763 12:28:19.813853 # ok 33 Set SVE VL 128
1764 12:28:19.814121 # ok 34 Set and get SVE data for VL 128
1765 12:28:19.819296 # ok 35 Set and get FPSIMD data for SVE VL 128
1766 12:28:19.819754 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1767 12:28:19.819862 # ok 37 Set SVE VL 144
1768 12:28:19.819955 # ok 38 Set and get SVE data for VL 144
1769 12:28:19.820041 # ok 39 Set and get FPSIMD data for SVE VL 144
1770 12:28:19.820140 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1771 12:28:19.820222 # ok 41 Set SVE VL 160
1772 12:28:19.820305 # ok 42 Set and get SVE data for VL 160
1773 12:28:19.820384 # ok 43 Set and get FPSIMD data for SVE VL 160
1774 12:28:19.820458 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1775 12:28:19.820553 # ok 45 Set SVE VL 176
1776 12:28:19.820641 # ok 46 Set and get SVE data for VL 176
1777 12:28:19.820727 # ok 47 Set and get FPSIMD data for SVE VL 176
1778 12:28:19.820810 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1779 12:28:19.820907 # ok 49 Set SVE VL 192
1780 12:28:19.820991 # ok 50 Set and get SVE data for VL 192
1781 12:28:19.821071 # ok 51 Set and get FPSIMD data for SVE VL 192
1782 12:28:19.821171 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1783 12:28:19.821263 # ok 53 Set SVE VL 208
1784 12:28:19.821347 # ok 54 Set and get SVE data for VL 208
1785 12:28:19.821446 # ok 55 Set and get FPSIMD data for SVE VL 208
1786 12:28:19.821533 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1787 12:28:19.821634 # ok 57 Set SVE VL 224
1788 12:28:19.822182 # ok 58 Set and get SVE data for VL 224
1789 12:28:19.822513 # ok 59 Set and get FPSIMD data for SVE VL 224
1790 12:28:19.822617 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1791 12:28:19.822707 # ok 61 Set SVE VL 240
1792 12:28:19.822789 # ok 62 Set and get SVE data for VL 240
1793 12:28:19.822884 # ok 63 Set and get FPSIMD data for SVE VL 240
1794 12:28:19.822968 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1795 12:28:19.823055 # ok 65 Set SVE VL 256
1796 12:28:19.823160 # ok 66 Set and get SVE data for VL 256
1797 12:28:19.823252 # ok 67 Set and get FPSIMD data for SVE VL 256
1798 12:28:19.823355 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1799 12:28:19.823433 # ok 69 Set SVE VL 272
1800 12:28:19.823527 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1801 12:28:19.823836 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1802 12:28:19.823970 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1803 12:28:19.824089 # ok 73 Set SVE VL 288
1804 12:28:19.824405 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1805 12:28:19.824549 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1806 12:28:19.824670 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1807 12:28:19.824794 # ok 77 Set SVE VL 304
1808 12:28:19.824914 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1809 12:28:19.825035 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1810 12:28:19.825177 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1811 12:28:19.825513 # ok 81 Set SVE VL 320
1812 12:28:19.825621 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1813 12:28:19.825724 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1814 12:28:19.825811 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1815 12:28:19.825897 # ok 85 Set SVE VL 336
1816 12:28:19.825982 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1817 12:28:19.826066 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1818 12:28:19.826152 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1819 12:28:19.826236 # ok 89 Set SVE VL 352
1820 12:28:19.826322 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1821 12:28:19.826405 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1822 12:28:19.826491 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1823 12:28:19.826593 # ok 93 Set SVE VL 368
1824 12:28:19.836985 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1825 12:28:19.837233 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1826 12:28:19.837554 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1827 12:28:19.837698 # ok 97 Set SVE VL 384
1828 12:28:19.837835 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1829 12:28:19.837937 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1830 12:28:19.838048 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1831 12:28:19.838143 # ok 101 Set SVE VL 400
1832 12:28:19.839715 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1833 12:28:19.839866 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1834 12:28:19.840219 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1835 12:28:19.840327 # ok 105 Set SVE VL 416
1836 12:28:19.840420 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1837 12:28:19.840511 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1838 12:28:19.840613 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1839 12:28:19.840703 # ok 109 Set SVE VL 432
1840 12:28:19.840790 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1841 12:28:19.840895 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1842 12:28:19.840986 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1843 12:28:19.841071 # ok 113 Set SVE VL 448
1844 12:28:19.841173 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1845 12:28:19.841265 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1846 12:28:19.841367 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1847 12:28:19.841452 # ok 117 Set SVE VL 464
1848 12:28:19.841551 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1849 12:28:19.849151 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1850 12:28:19.849593 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1851 12:28:19.849714 # ok 121 Set SVE VL 480
1852 12:28:19.849805 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1853 12:28:19.849894 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1854 12:28:19.850258 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1855 12:28:19.850567 # ok 125 Set SVE VL 496
1856 12:28:19.850672 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1857 12:28:19.850789 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1858 12:28:19.850887 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1859 12:28:19.851001 # ok 129 Set SVE VL 512
1860 12:28:19.851097 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1861 12:28:19.851208 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1862 12:28:19.851302 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1863 12:28:19.851412 # ok 133 Set SVE VL 528
1864 12:28:19.851529 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1865 12:28:19.851879 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1866 12:28:19.852019 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1867 12:28:19.852190 # ok 137 Set SVE VL 544
1868 12:28:19.852359 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1869 12:28:19.852617 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1870 12:28:19.852744 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1871 12:28:19.852916 # ok 141 Set SVE VL 560
1872 12:28:19.853090 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1873 12:28:19.853181 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1874 12:28:19.853266 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1875 12:28:19.853362 # ok 145 Set SVE VL 576
1876 12:28:19.853445 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1877 12:28:19.853526 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1878 12:28:19.853603 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1879 12:28:19.853689 # ok 149 Set SVE VL 592
1880 12:28:19.853781 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1881 12:28:19.853857 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1882 12:28:19.861267 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1883 12:28:19.861569 # ok 153 Set SVE VL 608
1884 12:28:19.861724 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1885 12:28:19.862064 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1886 12:28:19.862234 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1887 12:28:19.862427 # ok 157 Set SVE VL 624
1888 12:28:19.862630 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1889 12:28:19.862850 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1890 12:28:19.863048 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1891 12:28:19.863228 # ok 161 Set SVE VL 640
1892 12:28:19.863429 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1893 12:28:19.863681 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1894 12:28:19.863857 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1895 12:28:19.864055 # ok 165 Set SVE VL 656
1896 12:28:19.864269 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1897 12:28:19.864480 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1898 12:28:19.864722 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1899 12:28:19.864934 # ok 169 Set SVE VL 672
1900 12:28:19.865153 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1901 12:28:19.865365 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1902 12:28:19.865539 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1903 12:28:19.865743 # ok 173 Set SVE VL 688
1904 12:28:19.865954 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1905 12:28:19.866142 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1906 12:28:19.866330 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1907 12:28:19.866504 # ok 177 Set SVE VL 704
1908 12:28:19.866695 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1909 12:28:19.866828 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1910 12:28:19.866972 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1911 12:28:19.867114 # ok 181 Set SVE VL 720
1912 12:28:19.867256 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1913 12:28:19.867403 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1914 12:28:19.867546 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1915 12:28:19.872723 # ok 185 Set SVE VL 736
1916 12:28:19.873170 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1917 12:28:19.873316 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1918 12:28:19.873419 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1919 12:28:19.873510 # ok 189 Set SVE VL 752
1920 12:28:19.873607 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1921 12:28:19.873700 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1922 12:28:19.873779 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1923 12:28:19.874323 # ok 193 Set SVE VL 768
1924 12:28:19.874487 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1925 12:28:19.874871 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1926 12:28:19.875056 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1927 12:28:19.875203 # ok 197 Set SVE VL 784
1928 12:28:19.875385 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1929 12:28:19.875625 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1930 12:28:19.875770 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1931 12:28:19.875955 # ok 201 Set SVE VL 800
1932 12:28:19.876076 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1933 12:28:19.876245 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1934 12:28:19.876478 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1935 12:28:19.876607 # ok 205 Set SVE VL 816
1936 12:28:19.876779 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1937 12:28:19.876948 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1938 12:28:19.877135 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1939 12:28:19.877319 # ok 209 Set SVE VL 832
1940 12:28:19.877489 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1941 12:28:19.877579 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1942 12:28:19.877692 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1943 12:28:19.877781 # ok 213 Set SVE VL 848
1944 12:28:19.877870 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1945 12:28:19.877954 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1946 12:28:19.878035 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1947 12:28:19.878116 # ok 217 Set SVE VL 864
1948 12:28:19.878199 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1949 12:28:19.878275 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1950 12:28:19.878349 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1951 12:28:19.878424 # ok 221 Set SVE VL 880
1952 12:28:19.885026 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1953 12:28:19.885500 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1954 12:28:19.885622 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1955 12:28:19.885734 # ok 225 Set SVE VL 896
1956 12:28:19.885835 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1957 12:28:19.885949 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1958 12:28:19.886321 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1959 12:28:19.886552 # ok 229 Set SVE VL 912
1960 12:28:19.886803 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1961 12:28:19.887002 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1962 12:28:19.887272 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1963 12:28:19.887447 # ok 233 Set SVE VL 928
1964 12:28:19.887642 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1965 12:28:19.887817 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1966 12:28:19.887965 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1967 12:28:19.888137 # ok 237 Set SVE VL 944
1968 12:28:19.888290 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1969 12:28:19.888450 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1970 12:28:19.888617 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1971 12:28:19.888805 # ok 241 Set SVE VL 960
1972 12:28:19.888987 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1973 12:28:19.889151 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1974 12:28:19.889329 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1975 12:28:19.889548 # ok 245 Set SVE VL 976
1976 12:28:19.889768 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1977 12:28:19.889969 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1978 12:28:19.890116 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1979 12:28:19.890260 # ok 249 Set SVE VL 992
1980 12:28:19.890404 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1981 12:28:19.890589 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1982 12:28:19.890725 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1983 12:28:19.890870 # ok 253 Set SVE VL 1008
1984 12:28:19.891013 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1985 12:28:19.891157 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1986 12:28:19.891299 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1987 12:28:19.891444 # ok 257 Set SVE VL 1024
1988 12:28:19.897561 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1989 12:28:19.898298 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1990 12:28:19.898763 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1991 12:28:19.898967 # ok 261 Set SVE VL 1040
1992 12:28:19.899140 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1993 12:28:19.899280 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1994 12:28:19.899460 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1995 12:28:19.899603 # ok 265 Set SVE VL 1056
1996 12:28:19.899725 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1997 12:28:19.899851 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1998 12:28:19.900064 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1999 12:28:19.900235 # ok 269 Set SVE VL 1072
2000 12:28:19.900426 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
2001 12:28:19.900600 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
2002 12:28:19.900746 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2003 12:28:19.900927 # ok 273 Set SVE VL 1088
2004 12:28:19.901064 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2005 12:28:19.901208 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2006 12:28:19.901353 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2007 12:28:19.901497 # ok 277 Set SVE VL 1104
2008 12:28:19.901640 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2009 12:28:19.901835 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2010 12:28:19.901972 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2011 12:28:19.902114 # ok 281 Set SVE VL 1120
2012 12:28:19.902257 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2013 12:28:19.902399 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2014 12:28:19.902542 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2015 12:28:19.909466 # ok 285 Set SVE VL 1136
2016 12:28:19.909761 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2017 12:28:19.909872 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2018 12:28:19.909964 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2019 12:28:19.910051 # ok 289 Set SVE VL 1152
2020 12:28:19.910137 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2021 12:28:19.910240 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2022 12:28:19.910655 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2023 12:28:19.912157 # ok 293 Set SVE VL 1168
2024 12:28:19.912620 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2025 12:28:19.912813 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2026 12:28:19.912984 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2027 12:28:19.913141 # ok 297 Set SVE VL 1184
2028 12:28:19.913335 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2029 12:28:19.913727 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2030 12:28:19.913892 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2031 12:28:19.914036 # ok 301 Set SVE VL 1200
2032 12:28:19.914180 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2033 12:28:19.914360 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2034 12:28:19.914497 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2035 12:28:19.914642 # ok 305 Set SVE VL 1216
2036 12:28:19.921287 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2037 12:28:19.921701 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2038 12:28:19.921807 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2039 12:28:19.921906 # ok 309 Set SVE VL 1232
2040 12:28:19.923045 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2041 12:28:19.923165 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2042 12:28:19.923504 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2043 12:28:19.923784 # ok 313 Set SVE VL 1248
2044 12:28:19.923979 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2045 12:28:19.924154 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2046 12:28:19.924320 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2047 12:28:19.924499 # ok 317 Set SVE VL 1264
2048 12:28:19.924664 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2049 12:28:19.924827 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2050 12:28:19.925026 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2051 12:28:19.925195 # ok 321 Set SVE VL 1280
2052 12:28:19.925362 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2053 12:28:19.925533 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2054 12:28:19.925686 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2055 12:28:19.925895 # ok 325 Set SVE VL 1296
2056 12:28:19.926082 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2057 12:28:19.926240 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2058 12:28:19.926386 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2059 12:28:19.926530 # ok 329 Set SVE VL 1312
2060 12:28:19.926672 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2061 12:28:19.926814 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2062 12:28:19.926999 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2063 12:28:19.927134 # ok 333 Set SVE VL 1328
2064 12:28:19.927278 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2065 12:28:19.927421 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2066 12:28:19.929623 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2067 12:28:19.930304 # ok 337 Set SVE VL 1344
2068 12:28:19.930622 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2069 12:28:19.930722 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2070 12:28:19.930827 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2071 12:28:19.931125 # ok 341 Set SVE VL 1360
2072 12:28:19.931260 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2073 12:28:19.931436 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2074 12:28:19.931586 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2075 12:28:19.931719 # ok 345 Set SVE VL 1376
2076 12:28:19.931856 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2077 12:28:19.931996 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2078 12:28:19.932137 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2079 12:28:19.932270 # ok 349 Set SVE VL 1392
2080 12:28:19.932387 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2081 12:28:19.932497 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2082 12:28:19.932578 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2083 12:28:19.932659 # ok 353 Set SVE VL 1408
2084 12:28:19.932753 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2085 12:28:19.932833 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2086 12:28:19.932908 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2087 12:28:19.932982 # ok 357 Set SVE VL 1424
2088 12:28:19.933074 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2089 12:28:19.933158 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2090 12:28:19.933255 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2091 12:28:19.933341 # ok 361 Set SVE VL 1440
2092 12:28:19.933434 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2093 12:28:19.933579 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2094 12:28:19.938381 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2095 12:28:19.938895 # ok 365 Set SVE VL 1456
2096 12:28:19.939022 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2097 12:28:19.939124 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2098 12:28:19.939218 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2099 12:28:19.939311 # ok 369 Set SVE VL 1472
2100 12:28:19.939428 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2101 12:28:19.939522 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2102 12:28:19.939614 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2103 12:28:19.939708 # ok 373 Set SVE VL 1488
2104 12:28:19.939798 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2105 12:28:19.939890 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2106 12:28:19.940001 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2107 12:28:19.940094 # ok 377 Set SVE VL 1504
2108 12:28:19.940186 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2109 12:28:19.940278 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2110 12:28:19.940368 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2111 12:28:19.940464 # ok 381 Set SVE VL 1520
2112 12:28:19.940574 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2113 12:28:19.940668 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2114 12:28:19.940759 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2115 12:28:19.940850 # ok 385 Set SVE VL 1536
2116 12:28:19.940960 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2117 12:28:19.941053 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2118 12:28:19.941145 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2119 12:28:19.941255 # ok 389 Set SVE VL 1552
2120 12:28:19.941349 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2121 12:28:19.941445 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2122 12:28:19.941545 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2123 12:28:19.941667 # ok 393 Set SVE VL 1568
2124 12:28:19.941763 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2125 12:28:19.941855 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2126 12:28:19.949565 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2127 12:28:19.949832 # ok 397 Set SVE VL 1584
2128 12:28:19.950247 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2129 12:28:19.950442 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2130 12:28:19.950595 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2131 12:28:19.950779 # ok 401 Set SVE VL 1600
2132 12:28:19.950943 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2133 12:28:19.951095 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2134 12:28:19.951223 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2135 12:28:19.951351 # ok 405 Set SVE VL 1616
2136 12:28:19.951499 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2137 12:28:19.951634 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2138 12:28:19.951773 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2139 12:28:19.951925 # ok 409 Set SVE VL 1632
2140 12:28:19.952058 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2141 12:28:19.952189 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2142 12:28:19.952371 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2143 12:28:19.952552 # ok 413 Set SVE VL 1648
2144 12:28:19.952675 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2145 12:28:19.952787 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2146 12:28:19.952900 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2147 12:28:19.953022 # ok 417 Set SVE VL 1664
2148 12:28:19.953141 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2149 12:28:19.953255 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2150 12:28:19.953377 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2151 12:28:19.953493 # ok 421 Set SVE VL 1680
2152 12:28:19.953613 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2153 12:28:19.953743 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2154 12:28:19.953900 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2155 12:28:19.954032 # ok 425 Set SVE VL 1696
2156 12:28:19.954152 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2157 12:28:19.954270 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2158 12:28:19.954388 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2159 12:28:19.954502 # ok 429 Set SVE VL 1712
2160 12:28:19.954583 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2161 12:28:19.954661 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2162 12:28:19.958242 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2163 12:28:19.958762 # ok 433 Set SVE VL 1728
2164 12:28:19.958912 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2165 12:28:19.959084 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2166 12:28:19.959181 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2167 12:28:19.959270 # ok 437 Set SVE VL 1744
2168 12:28:19.959379 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2169 12:28:19.959472 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2170 12:28:19.959561 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2171 12:28:19.959649 # ok 441 Set SVE VL 1760
2172 12:28:19.959757 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2173 12:28:19.959848 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2174 12:28:19.959936 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2175 12:28:19.960024 # ok 445 Set SVE VL 1776
2176 12:28:19.960112 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2177 12:28:19.960205 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2178 12:28:19.960294 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2179 12:28:19.960400 # ok 449 Set SVE VL 1792
2180 12:28:19.960495 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2181 12:28:19.960583 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2182 12:28:19.960671 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2183 12:28:19.960758 # ok 453 Set SVE VL 1808
2184 12:28:19.960844 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2185 12:28:19.960957 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2186 12:28:19.961047 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2187 12:28:19.961135 # ok 457 Set SVE VL 1824
2188 12:28:19.961222 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2189 12:28:19.961326 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2190 12:28:19.961416 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2191 12:28:19.961504 # ok 461 Set SVE VL 1840
2192 12:28:19.961592 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2193 12:28:19.961705 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2194 12:28:19.967099 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2195 12:28:19.967430 # ok 465 Set SVE VL 1856
2196 12:28:19.967603 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2197 12:28:19.967824 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2198 12:28:19.968041 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2199 12:28:19.968212 # ok 469 Set SVE VL 1872
2200 12:28:19.968384 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2201 12:28:19.968763 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2202 12:28:19.968904 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2203 12:28:19.969055 # ok 473 Set SVE VL 1888
2204 12:28:19.969199 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2205 12:28:19.969342 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2206 12:28:19.969500 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2207 12:28:19.969672 # ok 477 Set SVE VL 1904
2208 12:28:19.969794 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2209 12:28:19.969910 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2210 12:28:19.978632 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2211 12:28:19.978874 # ok 481 Set SVE VL 1920
2212 12:28:19.978967 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2213 12:28:19.979073 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2214 12:28:19.979164 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2215 12:28:19.979271 # ok 485 Set SVE VL 1936
2216 12:28:19.979360 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2217 12:28:19.979656 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2218 12:28:19.979758 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2219 12:28:19.979847 # ok 489 Set SVE VL 1952
2220 12:28:19.979949 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2221 12:28:19.980049 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2222 12:28:19.980130 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2223 12:28:19.980288 # ok 493 Set SVE VL 1968
2224 12:28:19.980373 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2225 12:28:19.980464 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2226 12:28:19.980555 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2227 12:28:19.980847 # ok 497 Set SVE VL 1984
2228 12:28:19.980978 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2229 12:28:19.981080 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2230 12:28:19.981163 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2231 12:28:19.981251 # ok 501 Set SVE VL 2000
2232 12:28:19.981341 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2233 12:28:19.981619 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2234 12:28:19.981731 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2235 12:28:19.986441 # ok 505 Set SVE VL 2016
2236 12:28:19.986883 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2237 12:28:19.987000 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2238 12:28:19.987100 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2239 12:28:19.987198 # ok 509 Set SVE VL 2032
2240 12:28:19.987311 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2241 12:28:19.987411 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2242 12:28:19.987504 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2243 12:28:19.987612 # ok 513 Set SVE VL 2048
2244 12:28:19.987708 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2245 12:28:19.987800 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2246 12:28:19.987912 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2247 12:28:19.988006 # ok 517 Set SVE VL 2064
2248 12:28:19.988115 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2249 12:28:19.988211 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2250 12:28:19.988322 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2251 12:28:19.988417 # ok 521 Set SVE VL 2080
2252 12:28:19.988526 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2253 12:28:19.988636 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2254 12:28:19.988746 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2255 12:28:19.988857 # ok 525 Set SVE VL 2096
2256 12:28:19.988966 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2257 12:28:19.989447 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2258 12:28:19.989564 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2259 12:28:19.989669 # ok 529 Set SVE VL 2112
2260 12:28:19.989777 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2261 12:28:19.989870 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2262 12:28:19.994245 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2263 12:28:19.994657 # ok 533 Set SVE VL 2128
2264 12:28:19.994791 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2265 12:28:19.994893 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2266 12:28:19.995003 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2267 12:28:19.995100 # ok 537 Set SVE VL 2144
2268 12:28:19.995210 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2269 12:28:19.995304 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2270 12:28:19.995415 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2271 12:28:19.995511 # ok 541 Set SVE VL 2160
2272 12:28:19.995624 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2273 12:28:19.995720 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2274 12:28:19.995828 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2275 12:28:19.995924 # ok 545 Set SVE VL 2176
2276 12:28:19.996033 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2277 12:28:19.996143 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2278 12:28:19.996252 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2279 12:28:19.996362 # ok 549 Set SVE VL 2192
2280 12:28:19.996469 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2281 12:28:19.996579 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2282 12:28:19.997085 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2283 12:28:19.997195 # ok 553 Set SVE VL 2208
2284 12:28:19.997291 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2285 12:28:19.997384 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2286 12:28:19.997496 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2287 12:28:19.997598 # ok 557 Set SVE VL 2224
2288 12:28:19.997701 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2289 12:28:19.997794 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2290 12:28:20.002343 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2291 12:28:20.002938 # ok 561 Set SVE VL 2240
2292 12:28:20.003174 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2293 12:28:20.003355 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2294 12:28:20.003513 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2295 12:28:20.003676 # ok 565 Set SVE VL 2256
2296 12:28:20.003837 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2297 12:28:20.004044 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2298 12:28:20.004234 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2299 12:28:20.004422 # ok 569 Set SVE VL 2272
2300 12:28:20.004659 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2301 12:28:20.004836 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2302 12:28:20.005032 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2303 12:28:20.005205 # ok 573 Set SVE VL 2288
2304 12:28:20.005443 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2305 12:28:20.005639 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2306 12:28:20.005859 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2307 12:28:20.006055 # ok 577 Set SVE VL 2304
2308 12:28:20.006240 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2309 12:28:20.006394 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2310 12:28:20.006538 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2311 12:28:20.006681 # ok 581 Set SVE VL 2320
2312 12:28:20.006822 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2313 12:28:20.006964 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2314 12:28:20.007145 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2315 12:28:20.007283 # ok 585 Set SVE VL 2336
2316 12:28:20.010548 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2317 12:28:20.011069 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2318 12:28:20.011176 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2319 12:28:20.011266 # ok 589 Set SVE VL 2352
2320 12:28:20.011369 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2321 12:28:20.011460 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2322 12:28:20.011567 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2323 12:28:20.011657 # ok 593 Set SVE VL 2368
2324 12:28:20.011765 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2325 12:28:20.012066 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2326 12:28:20.012189 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2327 12:28:20.012491 # ok 597 Set SVE VL 2384
2328 12:28:20.012792 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2329 12:28:20.012889 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2330 12:28:20.012985 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2331 12:28:20.013077 # ok 601 Set SVE VL 2400
2332 12:28:20.013375 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2333 12:28:20.013483 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2334 12:28:20.013589 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2335 12:28:20.018106 # ok 605 Set SVE VL 2416
2336 12:28:20.018649 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2337 12:28:20.018840 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2338 12:28:20.019008 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2339 12:28:20.019164 # ok 609 Set SVE VL 2432
2340 12:28:20.019317 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2341 12:28:20.019555 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2342 12:28:20.019747 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2343 12:28:20.019957 # ok 613 Set SVE VL 2448
2344 12:28:20.020153 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2345 12:28:20.020327 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2346 12:28:20.020504 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2347 12:28:20.020671 # ok 617 Set SVE VL 2464
2348 12:28:20.020831 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2349 12:28:20.021062 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2350 12:28:20.021255 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2351 12:28:20.021429 # ok 621 Set SVE VL 2480
2352 12:28:20.021584 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2353 12:28:20.021803 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2354 12:28:20.022000 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2355 12:28:20.022185 # ok 625 Set SVE VL 2496
2356 12:28:20.022363 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2357 12:28:20.022507 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2358 12:28:20.022651 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2359 12:28:20.022794 # ok 629 Set SVE VL 2512
2360 12:28:20.022935 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2361 12:28:20.023077 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2362 12:28:20.023219 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2363 12:28:20.023362 # ok 633 Set SVE VL 2528
2364 12:28:20.023545 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2365 12:28:20.023679 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2366 12:28:20.023824 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2367 12:28:20.023967 # ok 637 Set SVE VL 2544
2368 12:28:20.024107 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2369 12:28:20.026321 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2370 12:28:20.026792 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2371 12:28:20.026987 # ok 641 Set SVE VL 2560
2372 12:28:20.027153 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2373 12:28:20.027313 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2374 12:28:20.027494 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2375 12:28:20.027649 # ok 645 Set SVE VL 2576
2376 12:28:20.027770 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2377 12:28:20.027883 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2378 12:28:20.027998 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2379 12:28:20.028113 # ok 649 Set SVE VL 2592
2380 12:28:20.028292 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2381 12:28:20.028437 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2382 12:28:20.028558 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2383 12:28:20.028676 # ok 653 Set SVE VL 2608
2384 12:28:20.028788 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2385 12:28:20.028902 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2386 12:28:20.029042 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2387 12:28:20.029162 # ok 657 Set SVE VL 2624
2388 12:28:20.029277 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2389 12:28:20.029391 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2390 12:28:20.029506 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2391 12:28:20.029619 # ok 661 Set SVE VL 2640
2392 12:28:20.029862 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2393 12:28:20.030060 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2394 12:28:20.030247 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2395 12:28:20.030433 # ok 665 Set SVE VL 2656
2396 12:28:20.033125 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2397 12:28:20.040275 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2398 12:28:20.040789 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2399 12:28:20.040981 # ok 669 Set SVE VL 2672
2400 12:28:20.041150 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2401 12:28:20.041335 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2402 12:28:20.041620 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2403 12:28:20.041843 # ok 673 Set SVE VL 2688
2404 12:28:20.041998 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2405 12:28:20.042193 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2406 12:28:20.042410 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2407 12:28:20.042612 # ok 677 Set SVE VL 2704
2408 12:28:20.042821 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2409 12:28:20.043026 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2410 12:28:20.043245 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2411 12:28:20.043469 # ok 681 Set SVE VL 2720
2412 12:28:20.043682 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2413 12:28:20.043902 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2414 12:28:20.044091 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2415 12:28:20.044324 # ok 685 Set SVE VL 2736
2416 12:28:20.044513 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2417 12:28:20.044695 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2418 12:28:20.044880 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2419 12:28:20.045057 # ok 689 Set SVE VL 2752
2420 12:28:20.045264 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2421 12:28:20.045472 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2422 12:28:20.046245 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2423 12:28:20.046434 # ok 693 Set SVE VL 2768
2424 12:28:20.046595 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2425 12:28:20.046756 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2426 12:28:20.046915 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2427 12:28:20.047076 # ok 697 Set SVE VL 2784
2428 12:28:20.047235 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2429 12:28:20.047388 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2430 12:28:20.047541 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2431 12:28:20.047696 # ok 701 Set SVE VL 2800
2432 12:28:20.047848 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2433 12:28:20.048004 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2434 12:28:20.048159 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2435 12:28:20.048316 # ok 705 Set SVE VL 2816
2436 12:28:20.048470 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2437 12:28:20.048631 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2438 12:28:20.048777 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2439 12:28:20.048909 # ok 709 Set SVE VL 2832
2440 12:28:20.049037 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2441 12:28:20.049161 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2442 12:28:20.049468 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2443 12:28:20.049572 # ok 713 Set SVE VL 2848
2444 12:28:20.049692 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2445 12:28:20.049802 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2446 12:28:20.049910 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2447 12:28:20.050015 # ok 717 Set SVE VL 2864
2448 12:28:20.050112 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2449 12:28:20.050197 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2450 12:28:20.050271 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2451 12:28:20.050354 # ok 721 Set SVE VL 2880
2452 12:28:20.050465 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2453 12:28:20.050573 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2454 12:28:20.050661 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2455 12:28:20.050741 # ok 725 Set SVE VL 2896
2456 12:28:20.050804 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2457 12:28:20.050872 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2458 12:28:20.050943 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2459 12:28:20.051018 # ok 729 Set SVE VL 2912
2460 12:28:20.051109 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2461 12:28:20.051212 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2462 12:28:20.051295 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2463 12:28:20.051377 # ok 733 Set SVE VL 2928
2464 12:28:20.051452 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2465 12:28:20.051548 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2466 12:28:20.051649 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2467 12:28:20.051752 # ok 737 Set SVE VL 2944
2468 12:28:20.051851 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2469 12:28:20.051954 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2470 12:28:20.052059 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2471 12:28:20.052163 # ok 741 Set SVE VL 2960
2472 12:28:20.052257 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2473 12:28:20.052364 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2474 12:28:20.052454 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2475 12:28:20.052563 # ok 745 Set SVE VL 2976
2476 12:28:20.052670 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2477 12:28:20.052773 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2478 12:28:20.052863 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2479 12:28:20.052942 # ok 749 Set SVE VL 2992
2480 12:28:20.053014 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2481 12:28:20.053094 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2482 12:28:20.053174 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2483 12:28:20.053251 # ok 753 Set SVE VL 3008
2484 12:28:20.053348 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2485 12:28:20.053429 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2486 12:28:20.054145 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2487 12:28:20.054232 # ok 757 Set SVE VL 3024
2488 12:28:20.054321 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2489 12:28:20.054397 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2490 12:28:20.054486 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2491 12:28:20.054586 # ok 761 Set SVE VL 3040
2492 12:28:20.054682 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2493 12:28:20.054788 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2494 12:28:20.054882 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2495 12:28:20.054957 # ok 765 Set SVE VL 3056
2496 12:28:20.055040 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2497 12:28:20.055127 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2498 12:28:20.055223 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2499 12:28:20.055326 # ok 769 Set SVE VL 3072
2500 12:28:20.055424 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2501 12:28:20.055522 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2502 12:28:20.055619 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2503 12:28:20.055724 # ok 773 Set SVE VL 3088
2504 12:28:20.055812 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2505 12:28:20.055889 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2506 12:28:20.055970 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2507 12:28:20.056055 # ok 777 Set SVE VL 3104
2508 12:28:20.056150 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2509 12:28:20.056240 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2510 12:28:20.056341 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2511 12:28:20.056444 # ok 781 Set SVE VL 3120
2512 12:28:20.056545 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2513 12:28:20.056643 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2514 12:28:20.056746 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2515 12:28:20.056845 # ok 785 Set SVE VL 3136
2516 12:28:20.056947 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2517 12:28:20.057048 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2518 12:28:20.057140 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2519 12:28:20.057254 # ok 789 Set SVE VL 3152
2520 12:28:20.057350 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2521 12:28:20.057448 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2522 12:28:20.057550 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2523 12:28:20.057719 # ok 793 Set SVE VL 3168
2524 12:28:20.057832 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2525 12:28:20.057928 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2526 12:28:20.058023 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2527 12:28:20.058119 # ok 797 Set SVE VL 3184
2528 12:28:20.058214 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2529 12:28:20.058313 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2530 12:28:20.058588 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2531 12:28:20.058707 # ok 801 Set SVE VL 3200
2532 12:28:20.058822 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2533 12:28:20.058942 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2534 12:28:20.059061 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2535 12:28:20.059163 # ok 805 Set SVE VL 3216
2536 12:28:20.059260 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2537 12:28:20.059357 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2538 12:28:20.059477 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2539 12:28:20.059572 # ok 809 Set SVE VL 3232
2540 12:28:20.059677 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2541 12:28:20.059769 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2542 12:28:20.059889 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2543 12:28:20.059989 # ok 813 Set SVE VL 3248
2544 12:28:20.060072 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2545 12:28:20.060158 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2546 12:28:20.060253 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2547 12:28:20.060334 # ok 817 Set SVE VL 3264
2548 12:28:20.060432 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2549 12:28:20.060516 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2550 12:28:20.060607 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2551 12:28:20.060693 # ok 821 Set SVE VL 3280
2552 12:28:20.060766 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2553 12:28:20.060835 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2554 12:28:20.060926 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2555 12:28:20.060996 # ok 825 Set SVE VL 3296
2556 12:28:20.061086 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2557 12:28:20.061178 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2558 12:28:20.061284 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2559 12:28:20.061385 # ok 829 Set SVE VL 3312
2560 12:28:20.061479 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2561 12:28:20.061584 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2562 12:28:20.062136 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2563 12:28:20.062224 # ok 833 Set SVE VL 3328
2564 12:28:20.062294 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2565 12:28:20.062355 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2566 12:28:20.062415 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2567 12:28:20.062474 # ok 837 Set SVE VL 3344
2568 12:28:20.062533 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2569 12:28:20.062592 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2570 12:28:20.062651 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2571 12:28:20.062710 # ok 841 Set SVE VL 3360
2572 12:28:20.062769 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2573 12:28:20.063023 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2574 12:28:20.063108 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2575 12:28:20.063197 # ok 845 Set SVE VL 3376
2576 12:28:20.063273 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2577 12:28:20.063347 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2578 12:28:20.063421 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2579 12:28:20.063494 # ok 849 Set SVE VL 3392
2580 12:28:20.063567 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2581 12:28:20.063640 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2582 12:28:20.063714 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2583 12:28:20.063788 # ok 853 Set SVE VL 3408
2584 12:28:20.063862 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2585 12:28:20.070620 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2586 12:28:20.070969 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2587 12:28:20.071159 # ok 857 Set SVE VL 3424
2588 12:28:20.071321 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2589 12:28:20.073774 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2590 12:28:20.073894 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2591 12:28:20.073963 # ok 861 Set SVE VL 3440
2592 12:28:20.074025 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2593 12:28:20.074085 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2594 12:28:20.074145 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2595 12:28:20.074205 # ok 865 Set SVE VL 3456
2596 12:28:20.074264 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2597 12:28:20.074323 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2598 12:28:20.074382 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2599 12:28:20.074441 # ok 869 Set SVE VL 3472
2600 12:28:20.074500 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2601 12:28:20.074559 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2602 12:28:20.074618 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2603 12:28:20.074677 # ok 873 Set SVE VL 3488
2604 12:28:20.074737 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2605 12:28:20.074795 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2606 12:28:20.074854 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2607 12:28:20.074912 # ok 877 Set SVE VL 3504
2608 12:28:20.076466 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2609 12:28:20.076747 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2610 12:28:20.077056 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2611 12:28:20.077163 # ok 881 Set SVE VL 3520
2612 12:28:20.077263 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2613 12:28:20.077380 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2614 12:28:20.077472 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2615 12:28:20.077576 # ok 885 Set SVE VL 3536
2616 12:28:20.077683 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2617 12:28:20.078256 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2618 12:28:20.078363 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2619 12:28:20.078466 # ok 889 Set SVE VL 3552
2620 12:28:20.078775 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2621 12:28:20.078881 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2622 12:28:20.078968 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2623 12:28:20.079061 # ok 893 Set SVE VL 3568
2624 12:28:20.079170 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2625 12:28:20.079287 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2626 12:28:20.079380 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2627 12:28:20.079477 # ok 897 Set SVE VL 3584
2628 12:28:20.079568 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2629 12:28:20.079686 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2630 12:28:20.079808 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2631 12:28:20.079922 # ok 901 Set SVE VL 3600
2632 12:28:20.080036 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2633 12:28:20.080149 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2634 12:28:20.080263 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2635 12:28:20.080383 # ok 905 Set SVE VL 3616
2636 12:28:20.080511 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2637 12:28:20.080605 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2638 12:28:20.080688 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2639 12:28:20.080778 # ok 909 Set SVE VL 3632
2640 12:28:20.080859 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2641 12:28:20.080956 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2642 12:28:20.081039 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2643 12:28:20.081122 # ok 913 Set SVE VL 3648
2644 12:28:20.081205 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2645 12:28:20.081294 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2646 12:28:20.081379 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2647 12:28:20.081466 # ok 917 Set SVE VL 3664
2648 12:28:20.081577 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2649 12:28:20.081906 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2650 12:28:20.082010 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2651 12:28:20.082126 # ok 921 Set SVE VL 3680
2652 12:28:20.082242 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2653 12:28:20.082326 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2654 12:28:20.082655 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2655 12:28:20.082752 # ok 925 Set SVE VL 3696
2656 12:28:20.082853 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2657 12:28:20.082958 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2658 12:28:20.083075 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2659 12:28:20.083178 # ok 929 Set SVE VL 3712
2660 12:28:20.083267 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2661 12:28:20.083372 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2662 12:28:20.083727 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2663 12:28:20.083840 # ok 933 Set SVE VL 3728
2664 12:28:20.083946 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2665 12:28:20.084052 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2666 12:28:20.084157 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2667 12:28:20.084274 # ok 937 Set SVE VL 3744
2668 12:28:20.084380 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2669 12:28:20.084483 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2670 12:28:20.084596 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2671 12:28:20.084682 # ok 941 Set SVE VL 3760
2672 12:28:20.084779 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2673 12:28:20.084877 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2674 12:28:20.084979 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2675 12:28:20.085108 # ok 945 Set SVE VL 3776
2676 12:28:20.085205 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2677 12:28:20.085292 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2678 12:28:20.085573 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2679 12:28:20.085676 # ok 949 Set SVE VL 3792
2680 12:28:20.085781 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2681 12:28:20.085863 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2682 12:28:20.085964 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2683 12:28:20.086064 # ok 953 Set SVE VL 3808
2684 12:28:20.086182 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2685 12:28:20.086307 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2686 12:28:20.086428 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2687 12:28:20.086550 # ok 957 Set SVE VL 3824
2688 12:28:20.086840 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2689 12:28:20.086923 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2690 12:28:20.087000 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2691 12:28:20.087077 # ok 961 Set SVE VL 3840
2692 12:28:20.087335 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2693 12:28:20.087428 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2694 12:28:20.087524 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2695 12:28:20.087604 # ok 965 Set SVE VL 3856
2696 12:28:20.087712 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2697 12:28:20.087979 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2698 12:28:20.088086 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2699 12:28:20.088183 # ok 969 Set SVE VL 3872
2700 12:28:20.088264 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2701 12:28:20.088359 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2702 12:28:20.088459 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2703 12:28:20.088557 # ok 973 Set SVE VL 3888
2704 12:28:20.088664 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2705 12:28:20.089036 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2706 12:28:20.089137 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2707 12:28:20.089220 # ok 977 Set SVE VL 3904
2708 12:28:20.089543 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2709 12:28:20.089628 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2710 12:28:20.089706 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2711 12:28:20.089780 # ok 981 Set SVE VL 3920
2712 12:28:20.089859 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2713 12:28:20.089943 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2714 12:28:20.090043 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2715 12:28:20.090131 # ok 985 Set SVE VL 3936
2716 12:28:20.090218 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2717 12:28:20.090302 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2718 12:28:20.090403 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2719 12:28:20.090495 # ok 989 Set SVE VL 3952
2720 12:28:20.090599 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2721 12:28:20.090719 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2722 12:28:20.090820 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2723 12:28:20.090908 # ok 993 Set SVE VL 3968
2724 12:28:20.090991 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2725 12:28:20.091089 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2726 12:28:20.091175 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2727 12:28:20.091257 # ok 997 Set SVE VL 3984
2728 12:28:20.091353 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2729 12:28:20.091435 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2730 12:28:20.091520 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2731 12:28:20.091614 # ok 1001 Set SVE VL 4000
2732 12:28:20.091740 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2733 12:28:20.091847 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2734 12:28:20.091933 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2735 12:28:20.092014 # ok 1005 Set SVE VL 4016
2736 12:28:20.092095 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2737 12:28:20.092194 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2738 12:28:20.092281 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2739 12:28:20.092367 # ok 1009 Set SVE VL 4032
2740 12:28:20.092453 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2741 12:28:20.092545 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2742 12:28:20.092629 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2743 12:28:20.092717 # ok 1013 Set SVE VL 4048
2744 12:28:20.092814 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2745 12:28:20.092938 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2746 12:28:20.093042 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2747 12:28:20.093141 # ok 1017 Set SVE VL 4064
2748 12:28:20.093242 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2749 12:28:20.093362 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2750 12:28:20.093463 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2751 12:28:20.093557 # ok 1021 Set SVE VL 4080
2752 12:28:20.093816 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2753 12:28:20.093941 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2754 12:28:20.094035 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2755 12:28:20.094121 # ok 1025 Set SVE VL 4096
2756 12:28:20.094218 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2757 12:28:20.094300 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2758 12:28:20.094386 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2759 12:28:20.094488 # ok 1029 Set SVE VL 4112
2760 12:28:20.094575 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2761 12:28:20.094661 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2762 12:28:20.094740 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2763 12:28:20.094854 # ok 1033 Set SVE VL 4128
2764 12:28:20.094983 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2765 12:28:20.095060 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2766 12:28:20.095123 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2767 12:28:20.095183 # ok 1037 Set SVE VL 4144
2768 12:28:20.095242 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2769 12:28:20.095301 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2770 12:28:20.095359 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2771 12:28:20.101621 # ok 1041 Set SVE VL 4160
2772 12:28:20.102367 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2773 12:28:20.102655 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2774 12:28:20.102755 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2775 12:28:20.102853 # ok 1045 Set SVE VL 4176
2776 12:28:20.102949 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2777 12:28:20.103062 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2778 12:28:20.103168 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2779 12:28:20.103252 # ok 1049 Set SVE VL 4192
2780 12:28:20.103349 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2781 12:28:20.103632 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2782 12:28:20.103739 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2783 12:28:20.103831 # ok 1053 Set SVE VL 4208
2784 12:28:20.104095 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2785 12:28:20.104208 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2786 12:28:20.104304 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2787 12:28:20.104380 # ok 1057 Set SVE VL 4224
2788 12:28:20.104470 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2789 12:28:20.104564 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2790 12:28:20.104672 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2791 12:28:20.104770 # ok 1061 Set SVE VL 4240
2792 12:28:20.105049 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2793 12:28:20.105147 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2794 12:28:20.105227 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2795 12:28:20.105302 # ok 1065 Set SVE VL 4256
2796 12:28:20.105382 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2797 12:28:20.105830 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2798 12:28:20.105929 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2799 12:28:20.106027 # ok 1069 Set SVE VL 4272
2800 12:28:20.106132 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2801 12:28:20.106247 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2802 12:28:20.106338 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2803 12:28:20.106438 # ok 1073 Set SVE VL 4288
2804 12:28:20.106513 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2805 12:28:20.106604 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2806 12:28:20.106700 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2807 12:28:20.106800 # ok 1077 Set SVE VL 4304
2808 12:28:20.107078 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2809 12:28:20.107184 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2810 12:28:20.107309 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2811 12:28:20.107415 # ok 1081 Set SVE VL 4320
2812 12:28:20.107530 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2813 12:28:20.107630 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2814 12:28:20.107752 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2815 12:28:20.107856 # ok 1085 Set SVE VL 4336
2816 12:28:20.107981 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2817 12:28:20.108075 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2818 12:28:20.108190 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2819 12:28:20.108284 # ok 1089 Set SVE VL 4352
2820 12:28:20.108386 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2821 12:28:20.108475 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2822 12:28:20.108559 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2823 12:28:20.108654 # ok 1093 Set SVE VL 4368
2824 12:28:20.108740 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2825 12:28:20.109042 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2826 12:28:20.109159 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2827 12:28:20.109260 # ok 1097 Set SVE VL 4384
2828 12:28:20.109376 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2829 12:28:20.109462 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2830 12:28:20.109542 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2831 12:28:20.109814 # ok 1101 Set SVE VL 4400
2832 12:28:20.109908 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2833 12:28:20.110019 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2834 12:28:20.110129 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2835 12:28:20.110247 # ok 1105 Set SVE VL 4416
2836 12:28:20.110359 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2837 12:28:20.110470 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2838 12:28:20.110597 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2839 12:28:20.110714 # ok 1109 Set SVE VL 4432
2840 12:28:20.111012 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2841 12:28:20.111114 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2842 12:28:20.111209 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2843 12:28:20.111287 # ok 1113 Set SVE VL 4448
2844 12:28:20.111366 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2845 12:28:20.111452 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2846 12:28:20.111720 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2847 12:28:20.111827 # ok 1117 Set SVE VL 4464
2848 12:28:20.111921 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2849 12:28:20.112001 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2850 12:28:20.112093 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2851 12:28:20.112169 # ok 1121 Set SVE VL 4480
2852 12:28:20.112268 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2853 12:28:20.112592 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2854 12:28:20.112691 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2855 12:28:20.112814 # ok 1125 Set SVE VL 4496
2856 12:28:20.112922 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2857 12:28:20.113033 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2858 12:28:20.113138 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2859 12:28:20.113224 # ok 1129 Set SVE VL 4512
2860 12:28:20.113346 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2861 12:28:20.113459 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2862 12:28:20.113569 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2863 12:28:20.113807 # ok 1133 Set SVE VL 4528
2864 12:28:20.113913 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2865 12:28:20.114199 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2866 12:28:20.114305 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2867 12:28:20.114428 # ok 1137 Set SVE VL 4544
2868 12:28:20.114522 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2869 12:28:20.114632 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2870 12:28:20.114717 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2871 12:28:20.114815 # ok 1141 Set SVE VL 4560
2872 12:28:20.114898 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2873 12:28:20.114989 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2874 12:28:20.115103 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2875 12:28:20.115209 # ok 1145 Set SVE VL 4576
2876 12:28:20.115324 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2877 12:28:20.115698 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2878 12:28:20.115816 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2879 12:28:20.115927 # ok 1149 Set SVE VL 4592
2880 12:28:20.116046 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2881 12:28:20.116152 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2882 12:28:20.116249 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2883 12:28:20.116353 # ok 1153 Set SVE VL 4608
2884 12:28:20.116479 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2885 12:28:20.116581 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2886 12:28:20.116690 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2887 12:28:20.116806 # ok 1157 Set SVE VL 4624
2888 12:28:20.116913 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2889 12:28:20.117011 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2890 12:28:20.117124 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2891 12:28:20.117233 # ok 1161 Set SVE VL 4640
2892 12:28:20.117337 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2893 12:28:20.117424 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2894 12:28:20.117556 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2895 12:28:20.117636 # ok 1165 Set SVE VL 4656
2896 12:28:20.117709 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2897 12:28:20.117947 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2898 12:28:20.118048 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2899 12:28:20.118159 # ok 1169 Set SVE VL 4672
2900 12:28:20.118288 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2901 12:28:20.118407 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2902 12:28:20.118526 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2903 12:28:20.118653 # ok 1173 Set SVE VL 4688
2904 12:28:20.118744 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2905 12:28:20.118865 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2906 12:28:20.118991 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2907 12:28:20.119100 # ok 1177 Set SVE VL 4704
2908 12:28:20.119396 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2909 12:28:20.119497 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2910 12:28:20.119613 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2911 12:28:20.119725 # ok 1181 Set SVE VL 4720
2912 12:28:20.119849 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2913 12:28:20.119947 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2914 12:28:20.120062 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2915 12:28:20.120163 # ok 1185 Set SVE VL 4736
2916 12:28:20.120283 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2917 12:28:20.120410 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2918 12:28:20.120504 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2919 12:28:20.120614 # ok 1189 Set SVE VL 4752
2920 12:28:20.120711 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2921 12:28:20.120828 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2922 12:28:20.121091 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2923 12:28:20.121184 # ok 1193 Set SVE VL 4768
2924 12:28:20.121310 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2925 12:28:20.121393 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2926 12:28:20.121496 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2927 12:28:20.121585 # ok 1197 Set SVE VL 4784
2928 12:28:20.121685 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2929 12:28:20.121984 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2930 12:28:20.122119 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2931 12:28:20.122254 # ok 1201 Set SVE VL 4800
2932 12:28:20.122348 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2933 12:28:20.122443 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2934 12:28:20.122540 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2935 12:28:20.122623 # ok 1205 Set SVE VL 4816
2936 12:28:20.122719 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2937 12:28:20.122820 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2938 12:28:20.122917 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2939 12:28:20.123014 # ok 1209 Set SVE VL 4832
2940 12:28:20.123266 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2941 12:28:20.123362 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2942 12:28:20.123458 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2943 12:28:20.123541 # ok 1213 Set SVE VL 4848
2944 12:28:20.123635 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2945 12:28:20.123949 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2946 12:28:20.124036 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2947 12:28:20.124113 # ok 1217 Set SVE VL 4864
2948 12:28:20.124202 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2949 12:28:20.124296 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2950 12:28:20.124381 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2951 12:28:20.124484 # ok 1221 Set SVE VL 4880
2952 12:28:20.124616 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2953 12:28:20.124717 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2954 12:28:20.141663 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2955 12:28:20.141855 # ok 1225 Set SVE VL 4896
2956 12:28:20.143892 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2957 12:28:20.144007 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2958 12:28:20.144299 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2959 12:28:20.144400 # ok 1229 Set SVE VL 4912
2960 12:28:20.144508 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2961 12:28:20.144635 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2962 12:28:20.144735 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2963 12:28:20.144841 # ok 1233 Set SVE VL 4928
2964 12:28:20.144936 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2965 12:28:20.145060 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2966 12:28:20.145163 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2967 12:28:20.145451 # ok 1237 Set SVE VL 4944
2968 12:28:20.145546 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2969 12:28:20.145637 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2970 12:28:20.146572 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2971 12:28:20.146867 # ok 1241 Set SVE VL 4960
2972 12:28:20.146963 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2973 12:28:20.147061 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2974 12:28:20.147141 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2975 12:28:20.147239 # ok 1245 Set SVE VL 4976
2976 12:28:20.147338 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2977 12:28:20.147433 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2978 12:28:20.147537 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2979 12:28:20.147641 # ok 1249 Set SVE VL 4992
2980 12:28:20.147932 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2981 12:28:20.148032 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2982 12:28:20.148111 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2983 12:28:20.148213 # ok 1253 Set SVE VL 5008
2984 12:28:20.148310 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2985 12:28:20.148557 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2986 12:28:20.148662 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2987 12:28:20.148752 # ok 1257 Set SVE VL 5024
2988 12:28:20.148840 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2989 12:28:20.148944 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2990 12:28:20.149233 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2991 12:28:20.149346 # ok 1261 Set SVE VL 5040
2992 12:28:20.149455 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2993 12:28:20.149565 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2994 12:28:20.152314 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2995 12:28:20.152636 # ok 1265 Set SVE VL 5056
2996 12:28:20.152736 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2997 12:28:20.152831 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2998 12:28:20.152906 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2999 12:28:20.153012 # ok 1269 Set SVE VL 5072
3000 12:28:20.153131 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
3001 12:28:20.153253 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
3002 12:28:20.153566 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3003 12:28:20.153665 # ok 1273 Set SVE VL 5088
3004 12:28:20.154836 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3005 12:28:20.155134 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3006 12:28:20.155226 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3007 12:28:20.155295 # ok 1277 Set SVE VL 5104
3008 12:28:20.155368 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3009 12:28:20.155635 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3010 12:28:20.155750 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3011 12:28:20.155885 # ok 1281 Set SVE VL 5120
3012 12:28:20.156005 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3013 12:28:20.156104 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3014 12:28:20.156248 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3015 12:28:20.156343 # ok 1285 Set SVE VL 5136
3016 12:28:20.156480 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3017 12:28:20.156577 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3018 12:28:20.156672 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3019 12:28:20.156763 # ok 1289 Set SVE VL 5152
3020 12:28:20.157052 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3021 12:28:20.157164 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3022 12:28:20.157278 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3023 12:28:20.157374 # ok 1293 Set SVE VL 5168
3024 12:28:20.157486 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3025 12:28:20.157929 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3026 12:28:20.158290 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3027 12:28:20.158460 # ok 1297 Set SVE VL 5184
3028 12:28:20.158598 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3029 12:28:20.158725 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3030 12:28:20.158902 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3031 12:28:20.159034 # ok 1301 Set SVE VL 5200
3032 12:28:20.159200 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3033 12:28:20.159412 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3034 12:28:20.159585 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3035 12:28:20.159741 # ok 1305 Set SVE VL 5216
3036 12:28:20.159902 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3037 12:28:20.160050 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3038 12:28:20.160247 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3039 12:28:20.160404 # ok 1309 Set SVE VL 5232
3040 12:28:20.160537 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3041 12:28:20.160679 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3042 12:28:20.160837 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3043 12:28:20.160993 # ok 1313 Set SVE VL 5248
3044 12:28:20.161167 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3045 12:28:20.161384 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3046 12:28:20.161539 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3047 12:28:20.161657 # ok 1317 Set SVE VL 5264
3048 12:28:20.161782 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3049 12:28:20.161932 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3050 12:28:20.162081 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3051 12:28:20.162248 # ok 1321 Set SVE VL 5280
3052 12:28:20.162396 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3053 12:28:20.162550 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3054 12:28:20.162672 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3055 12:28:20.162794 # ok 1325 Set SVE VL 5296
3056 12:28:20.162913 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3057 12:28:20.163030 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3058 12:28:20.163148 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3059 12:28:20.163263 # ok 1329 Set SVE VL 5312
3060 12:28:20.163431 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3061 12:28:20.163585 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3062 12:28:20.163732 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3063 12:28:20.163926 # ok 1333 Set SVE VL 5328
3064 12:28:20.164119 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3065 12:28:20.164278 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3066 12:28:20.164447 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3067 12:28:20.164601 # ok 1337 Set SVE VL 5344
3068 12:28:20.164735 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3069 12:28:20.165124 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3070 12:28:20.165280 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3071 12:28:20.165413 # ok 1341 Set SVE VL 5360
3072 12:28:20.165619 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3073 12:28:20.165724 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3074 12:28:20.165803 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3075 12:28:20.165888 # ok 1345 Set SVE VL 5376
3076 12:28:20.165965 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3077 12:28:20.166039 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3078 12:28:20.166115 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3079 12:28:20.166192 # ok 1349 Set SVE VL 5392
3080 12:28:20.166270 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3081 12:28:20.166348 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3082 12:28:20.166428 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3083 12:28:20.166504 # ok 1353 Set SVE VL 5408
3084 12:28:20.166582 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3085 12:28:20.166678 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3086 12:28:20.166759 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3087 12:28:20.166841 # ok 1357 Set SVE VL 5424
3088 12:28:20.166920 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3089 12:28:20.166999 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3090 12:28:20.167077 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3091 12:28:20.167156 # ok 1361 Set SVE VL 5440
3092 12:28:20.167239 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3093 12:28:20.167322 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3094 12:28:20.167400 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3095 12:28:20.167475 # ok 1365 Set SVE VL 5456
3096 12:28:20.167553 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3097 12:28:20.167632 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3098 12:28:20.167710 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3099 12:28:20.167806 # ok 1369 Set SVE VL 5472
3100 12:28:20.167886 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3101 12:28:20.167968 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3102 12:28:20.168045 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3103 12:28:20.168120 # ok 1373 Set SVE VL 5488
3104 12:28:20.168246 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3105 12:28:20.168338 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3106 12:28:20.168436 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3107 12:28:20.168518 # ok 1377 Set SVE VL 5504
3108 12:28:20.168595 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3109 12:28:20.168676 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3110 12:28:20.168758 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3111 12:28:20.168856 # ok 1381 Set SVE VL 5520
3112 12:28:20.169196 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3113 12:28:20.169379 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3114 12:28:20.169465 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3115 12:28:20.169546 # ok 1385 Set SVE VL 5536
3116 12:28:20.169625 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3117 12:28:20.169712 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3118 12:28:20.169788 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3119 12:28:20.169864 # ok 1389 Set SVE VL 5552
3120 12:28:20.169949 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3121 12:28:20.170023 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3122 12:28:20.170099 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3123 12:28:20.170177 # ok 1393 Set SVE VL 5568
3124 12:28:20.170252 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3125 12:28:20.170332 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3126 12:28:20.170424 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3127 12:28:20.170508 # ok 1397 Set SVE VL 5584
3128 12:28:20.170583 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3129 12:28:20.170655 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3130 12:28:20.170730 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3131 12:28:20.170803 # ok 1401 Set SVE VL 5600
3132 12:28:20.170874 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3133 12:28:20.170953 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3134 12:28:20.171039 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3135 12:28:20.171137 # ok 1405 Set SVE VL 5616
3136 12:28:20.171226 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3137 12:28:20.203936 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3138 12:28:20.204382 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3139 12:28:20.204490 # ok 1409 Set SVE VL 5632
3140 12:28:20.204601 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3141 12:28:20.204698 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3142 12:28:20.204817 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3143 12:28:20.204915 # ok 1413 Set SVE VL 5648
3144 12:28:20.205020 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3145 12:28:20.205139 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3146 12:28:20.205236 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3147 12:28:20.205373 # ok 1417 Set SVE VL 5664
3148 12:28:20.205475 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3149 12:28:20.205559 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3150 12:28:20.205638 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3151 12:28:20.205750 # ok 1421 Set SVE VL 5680
3152 12:28:20.206992 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3153 12:28:20.207349 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3154 12:28:20.207454 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3155 12:28:20.207539 # ok 1425 Set SVE VL 5696
3156 12:28:20.207626 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3157 12:28:20.207728 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3158 12:28:20.207813 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3159 12:28:20.207882 # ok 1429 Set SVE VL 5712
3160 12:28:20.207967 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3161 12:28:20.208070 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3162 12:28:20.208173 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3163 12:28:20.208268 # ok 1433 Set SVE VL 5728
3164 12:28:20.208351 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3165 12:28:20.208455 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3166 12:28:20.208774 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3167 12:28:20.208919 # ok 1437 Set SVE VL 5744
3168 12:28:20.209158 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3169 12:28:20.209475 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3170 12:28:20.209584 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3171 12:28:20.209674 # ok 1441 Set SVE VL 5760
3172 12:28:20.209755 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3173 12:28:20.209820 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3174 12:28:20.209902 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3175 12:28:20.210023 # ok 1445 Set SVE VL 5776
3176 12:28:20.210140 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3177 12:28:20.210255 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3178 12:28:20.210369 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3179 12:28:20.210484 # ok 1449 Set SVE VL 5792
3180 12:28:20.210596 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3181 12:28:20.210709 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3182 12:28:20.211795 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3183 12:28:20.211906 # ok 1453 Set SVE VL 5808
3184 12:28:20.211994 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3185 12:28:20.212072 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3186 12:28:20.212154 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3187 12:28:20.212232 # ok 1457 Set SVE VL 5824
3188 12:28:20.212307 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3189 12:28:20.212380 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3190 12:28:20.212453 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3191 12:28:20.212527 # ok 1461 Set SVE VL 5840
3192 12:28:20.212599 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3193 12:28:20.212896 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3194 12:28:20.212995 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3195 12:28:20.213079 # ok 1465 Set SVE VL 5856
3196 12:28:20.213164 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3197 12:28:20.213244 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3198 12:28:20.213318 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3199 12:28:20.213392 # ok 1469 Set SVE VL 5872
3200 12:28:20.213471 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3201 12:28:20.213554 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3202 12:28:20.213636 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3203 12:28:20.213730 # ok 1473 Set SVE VL 5888
3204 12:28:20.213814 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3205 12:28:20.213919 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3206 12:28:20.214007 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3207 12:28:20.214089 # ok 1477 Set SVE VL 5904
3208 12:28:20.214169 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3209 12:28:20.214250 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3210 12:28:20.214343 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3211 12:28:20.214425 # ok 1481 Set SVE VL 5920
3212 12:28:20.214517 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3213 12:28:20.214617 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3214 12:28:20.214716 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3215 12:28:20.215051 # ok 1485 Set SVE VL 5936
3216 12:28:20.215155 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3217 12:28:20.215243 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3218 12:28:20.215347 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3219 12:28:20.215436 # ok 1489 Set SVE VL 5952
3220 12:28:20.215524 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3221 12:28:20.215629 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3222 12:28:20.215717 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3223 12:28:20.215802 # ok 1493 Set SVE VL 5968
3224 12:28:20.215901 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3225 12:28:20.215988 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3226 12:28:20.216089 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3227 12:28:20.216173 # ok 1497 Set SVE VL 5984
3228 12:28:20.216266 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3229 12:28:20.216355 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3230 12:28:20.216445 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3231 12:28:20.216522 # ok 1501 Set SVE VL 6000
3232 12:28:20.216619 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3233 12:28:20.216927 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3234 12:28:20.217039 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3235 12:28:20.217127 # ok 1505 Set SVE VL 6016
3236 12:28:20.217229 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3237 12:28:20.217329 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3238 12:28:20.217412 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3239 12:28:20.217489 # ok 1509 Set SVE VL 6032
3240 12:28:20.217583 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3241 12:28:20.217675 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3242 12:28:20.217773 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3243 12:28:20.217857 # ok 1513 Set SVE VL 6048
3244 12:28:20.218469 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3245 12:28:20.218680 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3246 12:28:20.218889 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3247 12:28:20.219067 # ok 1517 Set SVE VL 6064
3248 12:28:20.219235 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3249 12:28:20.219435 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3250 12:28:20.219607 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3251 12:28:20.219781 # ok 1521 Set SVE VL 6080
3252 12:28:20.219982 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3253 12:28:20.220138 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3254 12:28:20.220343 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3255 12:28:20.220545 # ok 1525 Set SVE VL 6096
3256 12:28:20.220722 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3257 12:28:20.220971 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3258 12:28:20.221158 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3259 12:28:20.221344 # ok 1529 Set SVE VL 6112
3260 12:28:20.221530 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3261 12:28:20.221682 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3262 12:28:20.221806 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3263 12:28:20.221932 # ok 1533 Set SVE VL 6128
3264 12:28:20.222103 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3265 12:28:20.222249 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3266 12:28:20.222391 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3267 12:28:20.222559 # ok 1537 Set SVE VL 6144
3268 12:28:20.222803 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3269 12:28:20.222990 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3270 12:28:20.223152 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3271 12:28:20.223301 # ok 1541 Set SVE VL 6160
3272 12:28:20.223460 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3273 12:28:20.223625 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3274 12:28:20.223819 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3275 12:28:20.223981 # ok 1545 Set SVE VL 6176
3276 12:28:20.224134 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3277 12:28:20.224318 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3278 12:28:20.224514 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3279 12:28:20.224692 # ok 1549 Set SVE VL 6192
3280 12:28:20.224850 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3281 12:28:20.225007 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3282 12:28:20.225158 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3283 12:28:20.225324 # ok 1553 Set SVE VL 6208
3284 12:28:20.225486 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3285 12:28:20.225619 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3286 12:28:20.226179 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3287 12:28:20.226440 # ok 1557 Set SVE VL 6224
3288 12:28:20.226649 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3289 12:28:20.226833 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3290 12:28:20.226990 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3291 12:28:20.227149 # ok 1561 Set SVE VL 6240
3292 12:28:20.227294 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3293 12:28:20.227446 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3294 12:28:20.227596 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3295 12:28:20.227720 # ok 1565 Set SVE VL 6256
3296 12:28:20.227836 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3297 12:28:20.227950 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3298 12:28:20.228045 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3299 12:28:20.228130 # ok 1569 Set SVE VL 6272
3300 12:28:20.228253 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3301 12:28:20.228362 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3302 12:28:20.228452 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3303 12:28:20.228538 # ok 1573 Set SVE VL 6288
3304 12:28:20.228631 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3305 12:28:20.228746 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3306 12:28:20.228864 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3307 12:28:20.228956 # ok 1577 Set SVE VL 6304
3308 12:28:20.229046 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3309 12:28:20.229132 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3310 12:28:20.229219 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3311 12:28:20.229304 # ok 1581 Set SVE VL 6320
3312 12:28:20.229390 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3313 12:28:20.229476 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3314 12:28:20.229562 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3315 12:28:20.229663 # ok 1585 Set SVE VL 6336
3316 12:28:20.229822 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3317 12:28:20.229964 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3318 12:28:20.230071 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3319 12:28:20.230166 # ok 1589 Set SVE VL 6352
3320 12:28:20.230278 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3321 12:28:20.230606 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3322 12:28:20.230707 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3323 12:28:20.230797 # ok 1593 Set SVE VL 6368
3324 12:28:20.230877 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3325 12:28:20.230971 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3326 12:28:20.231258 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3327 12:28:20.231374 # ok 1597 Set SVE VL 6384
3328 12:28:20.231481 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3329 12:28:20.231618 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3330 12:28:20.231736 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3331 12:28:20.231843 # ok 1601 Set SVE VL 6400
3332 12:28:20.231948 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3333 12:28:20.232073 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3334 12:28:20.232168 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3335 12:28:20.232270 # ok 1605 Set SVE VL 6416
3336 12:28:20.232379 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3337 12:28:20.232474 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3338 12:28:20.232820 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3339 12:28:20.232926 # ok 1609 Set SVE VL 6432
3340 12:28:20.233042 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3341 12:28:20.233167 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3342 12:28:20.233276 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3343 12:28:20.233391 # ok 1613 Set SVE VL 6448
3344 12:28:20.233504 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3345 12:28:20.233619 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3346 12:28:20.233729 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3347 12:28:20.233827 # ok 1617 Set SVE VL 6464
3348 12:28:20.233933 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3349 12:28:20.234036 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3350 12:28:20.234137 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3351 12:28:20.234253 # ok 1621 Set SVE VL 6480
3352 12:28:20.234391 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3353 12:28:20.234508 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3354 12:28:20.234624 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3355 12:28:20.235037 # ok 1625 Set SVE VL 6496
3356 12:28:20.235140 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3357 12:28:20.235221 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3358 12:28:20.235302 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3359 12:28:20.235404 # ok 1629 Set SVE VL 6512
3360 12:28:20.235523 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3361 12:28:20.235639 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3362 12:28:20.235746 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3363 12:28:20.235852 # ok 1633 Set SVE VL 6528
3364 12:28:20.235966 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3365 12:28:20.236095 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3366 12:28:20.236219 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3367 12:28:20.236320 # ok 1637 Set SVE VL 6544
3368 12:28:20.236430 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3369 12:28:20.236563 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3370 12:28:20.236676 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3371 12:28:20.236778 # ok 1641 Set SVE VL 6560
3372 12:28:20.236864 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3373 12:28:20.236934 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3374 12:28:20.237015 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3375 12:28:20.237103 # ok 1645 Set SVE VL 6576
3376 12:28:20.237177 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3377 12:28:20.237274 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3378 12:28:20.237385 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3379 12:28:20.237477 # ok 1649 Set SVE VL 6592
3380 12:28:20.237580 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3381 12:28:20.237685 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3382 12:28:20.237780 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3383 12:28:20.237897 # ok 1653 Set SVE VL 6608
3384 12:28:20.238006 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3385 12:28:20.238113 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3386 12:28:20.238208 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3387 12:28:20.238311 # ok 1657 Set SVE VL 6624
3388 12:28:20.238395 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3389 12:28:20.238488 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3390 12:28:20.238845 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3391 12:28:20.239063 # ok 1661 Set SVE VL 6640
3392 12:28:20.239200 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3393 12:28:20.239343 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3394 12:28:20.239523 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3395 12:28:20.239701 # ok 1665 Set SVE VL 6656
3396 12:28:20.239795 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3397 12:28:20.239881 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3398 12:28:20.239967 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3399 12:28:20.240076 # ok 1669 Set SVE VL 6672
3400 12:28:20.240162 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3401 12:28:20.240247 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3402 12:28:20.240330 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3403 12:28:20.240419 # ok 1673 Set SVE VL 6688
3404 12:28:20.240509 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3405 12:28:20.240599 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3406 12:28:20.240690 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3407 12:28:20.240782 # ok 1677 Set SVE VL 6704
3408 12:28:20.240871 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3409 12:28:20.240962 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3410 12:28:20.241053 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3411 12:28:20.241136 # ok 1681 Set SVE VL 6720
3412 12:28:20.241219 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3413 12:28:20.241327 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3414 12:28:20.241416 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3415 12:28:20.241502 # ok 1685 Set SVE VL 6736
3416 12:28:20.241586 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3417 12:28:20.241684 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3418 12:28:20.241771 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3419 12:28:20.241859 # ok 1689 Set SVE VL 6752
3420 12:28:20.241945 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3421 12:28:20.242041 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3422 12:28:20.242135 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3423 12:28:20.242226 # ok 1693 Set SVE VL 6768
3424 12:28:20.242316 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3425 12:28:20.242429 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3426 12:28:20.242523 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3427 12:28:20.242615 # ok 1697 Set SVE VL 6784
3428 12:28:20.242704 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3429 12:28:20.242790 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3430 12:28:20.242870 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3431 12:28:20.242950 # ok 1701 Set SVE VL 6800
3432 12:28:20.243036 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3433 12:28:20.243406 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3434 12:28:20.243573 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3435 12:28:20.243708 # ok 1705 Set SVE VL 6816
3436 12:28:20.243844 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3437 12:28:20.243972 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3438 12:28:20.244102 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3439 12:28:20.244378 # ok 1709 Set SVE VL 6832
3440 12:28:20.244543 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3441 12:28:20.244669 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3442 12:28:20.244796 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3443 12:28:20.244922 # ok 1713 Set SVE VL 6848
3444 12:28:20.245087 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3445 12:28:20.245202 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3446 12:28:20.245317 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3447 12:28:20.245433 # ok 1717 Set SVE VL 6864
3448 12:28:20.245545 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3449 12:28:20.245640 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3450 12:28:20.245800 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3451 12:28:20.245948 # ok 1721 Set SVE VL 6880
3452 12:28:20.246071 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3453 12:28:20.246154 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3454 12:28:20.246231 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3455 12:28:20.246295 # ok 1725 Set SVE VL 6896
3456 12:28:20.246356 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3457 12:28:20.246417 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3458 12:28:20.246500 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3459 12:28:20.246569 # ok 1729 Set SVE VL 6912
3460 12:28:20.246635 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3461 12:28:20.246697 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3462 12:28:20.246760 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3463 12:28:20.246825 # ok 1733 Set SVE VL 6928
3464 12:28:20.246889 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3465 12:28:20.246954 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3466 12:28:20.247023 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3467 12:28:20.247086 # ok 1737 Set SVE VL 6944
3468 12:28:20.247151 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3469 12:28:20.247247 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3470 12:28:20.247366 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3471 12:28:20.247456 # ok 1741 Set SVE VL 6960
3472 12:28:20.247545 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3473 12:28:20.247621 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3474 12:28:20.247695 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3475 12:28:20.247769 # ok 1745 Set SVE VL 6976
3476 12:28:20.248048 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3477 12:28:20.248141 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3478 12:28:20.248243 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3479 12:28:20.248344 # ok 1749 Set SVE VL 6992
3480 12:28:20.248436 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3481 12:28:20.248529 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3482 12:28:20.248623 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3483 12:28:20.248705 # ok 1753 Set SVE VL 7008
3484 12:28:20.248787 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3485 12:28:20.248875 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3486 12:28:20.248954 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3487 12:28:20.249035 # ok 1757 Set SVE VL 7024
3488 12:28:20.249123 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3489 12:28:20.249216 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3490 12:28:20.249297 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3491 12:28:20.249374 # ok 1761 Set SVE VL 7040
3492 12:28:20.249453 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3493 12:28:20.249788 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3494 12:28:20.249897 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3495 12:28:20.249992 # ok 1765 Set SVE VL 7056
3496 12:28:20.250074 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3497 12:28:20.250537 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3498 12:28:20.250619 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3499 12:28:20.250682 # ok 1769 Set SVE VL 7072
3500 12:28:20.250742 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3501 12:28:20.250802 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3502 12:28:20.251042 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3503 12:28:20.253455 # ok 1773 Set SVE VL 7088
3504 12:28:20.253618 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3505 12:28:20.253727 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3506 12:28:20.253804 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3507 12:28:20.253879 # ok 1777 Set SVE VL 7104
3508 12:28:20.254142 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3509 12:28:20.254410 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3510 12:28:20.254518 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3511 12:28:20.254790 # ok 1781 Set SVE VL 7120
3512 12:28:20.255163 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3513 12:28:20.255263 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3514 12:28:20.255356 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3515 12:28:20.255433 # ok 1785 Set SVE VL 7136
3516 12:28:20.255550 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3517 12:28:20.255848 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3518 12:28:20.255965 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3519 12:28:20.256234 # ok 1789 Set SVE VL 7152
3520 12:28:20.256354 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3521 12:28:20.257806 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3522 12:28:20.257936 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3523 12:28:20.258032 # ok 1793 Set SVE VL 7168
3524 12:28:20.258108 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3525 12:28:20.258196 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3526 12:28:20.258282 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3527 12:28:20.258343 # ok 1797 Set SVE VL 7184
3528 12:28:20.258403 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3529 12:28:20.258461 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3530 12:28:20.258521 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3531 12:28:20.258580 # ok 1801 Set SVE VL 7200
3532 12:28:20.258854 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3533 12:28:20.258945 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3534 12:28:20.259024 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3535 12:28:20.259114 # ok 1805 Set SVE VL 7216
3536 12:28:20.259197 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3537 12:28:20.259278 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3538 12:28:20.259359 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3539 12:28:20.259439 # ok 1809 Set SVE VL 7232
3540 12:28:20.259542 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3541 12:28:20.259670 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3542 12:28:20.259774 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3543 12:28:20.259862 # ok 1813 Set SVE VL 7248
3544 12:28:20.259940 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3545 12:28:20.260039 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3546 12:28:20.260131 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3547 12:28:20.260215 # ok 1817 Set SVE VL 7264
3548 12:28:20.260318 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3549 12:28:20.260419 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3550 12:28:20.260520 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3551 12:28:20.260625 # ok 1821 Set SVE VL 7280
3552 12:28:20.260733 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3553 12:28:20.260834 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3554 12:28:20.260940 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3555 12:28:20.261027 # ok 1825 Set SVE VL 7296
3556 12:28:20.261116 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3557 12:28:20.261199 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3558 12:28:20.261281 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3559 12:28:20.261363 # ok 1829 Set SVE VL 7312
3560 12:28:20.261490 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3561 12:28:20.261599 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3562 12:28:20.261709 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3563 12:28:20.261792 # ok 1833 Set SVE VL 7328
3564 12:28:20.261872 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3565 12:28:20.261951 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3566 12:28:20.262047 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3567 12:28:20.262131 # ok 1837 Set SVE VL 7344
3568 12:28:20.262212 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3569 12:28:20.262308 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3570 12:28:20.262415 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3571 12:28:20.262548 # ok 1841 Set SVE VL 7360
3572 12:28:20.262683 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3573 12:28:20.262792 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3574 12:28:20.263104 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3575 12:28:20.263206 # ok 1845 Set SVE VL 7376
3576 12:28:20.263290 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3577 12:28:20.263372 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3578 12:28:20.263473 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3579 12:28:20.263560 # ok 1849 Set SVE VL 7392
3580 12:28:20.263638 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3581 12:28:20.263714 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3582 12:28:20.263811 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3583 12:28:20.263895 # ok 1853 Set SVE VL 7408
3584 12:28:20.263995 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3585 12:28:20.264094 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3586 12:28:20.264381 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3587 12:28:20.264466 # ok 1857 Set SVE VL 7424
3588 12:28:20.264556 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3589 12:28:20.264634 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3590 12:28:20.264723 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3591 12:28:20.264813 # ok 1861 Set SVE VL 7440
3592 12:28:20.265096 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3593 12:28:20.265182 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3594 12:28:20.265280 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3595 12:28:20.265369 # ok 1865 Set SVE VL 7456
3596 12:28:20.265643 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3597 12:28:20.265753 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3598 12:28:20.266026 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3599 12:28:20.266110 # ok 1869 Set SVE VL 7472
3600 12:28:20.266199 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3601 12:28:20.266293 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3602 12:28:20.266390 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3603 12:28:20.266490 # ok 1873 Set SVE VL 7488
3604 12:28:20.266591 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3605 12:28:20.266698 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3606 12:28:20.266987 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3607 12:28:20.267081 # ok 1877 Set SVE VL 7504
3608 12:28:20.267180 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3609 12:28:20.267276 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3610 12:28:20.267563 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3611 12:28:20.267656 # ok 1881 Set SVE VL 7520
3612 12:28:20.267755 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3613 12:28:20.267840 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3614 12:28:20.267938 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3615 12:28:20.268039 # ok 1885 Set SVE VL 7536
3616 12:28:20.268323 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3617 12:28:20.268407 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3618 12:28:20.272339 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3619 12:28:20.272527 # ok 1889 Set SVE VL 7552
3620 12:28:20.272607 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3621 12:28:20.272682 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3622 12:28:20.272757 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3623 12:28:20.272835 # ok 1893 Set SVE VL 7568
3624 12:28:20.272909 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3625 12:28:20.272983 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3626 12:28:20.273063 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3627 12:28:20.273148 # ok 1897 Set SVE VL 7584
3628 12:28:20.273232 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3629 12:28:20.273316 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3630 12:28:20.273400 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3631 12:28:20.273485 # ok 1901 Set SVE VL 7600
3632 12:28:20.273569 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3633 12:28:20.273660 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3634 12:28:20.273742 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3635 12:28:20.273823 # ok 1905 Set SVE VL 7616
3636 12:28:20.273903 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3637 12:28:20.273985 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3638 12:28:20.274069 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3639 12:28:20.274161 # ok 1909 Set SVE VL 7632
3640 12:28:20.274245 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3641 12:28:20.274330 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3642 12:28:20.274409 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3643 12:28:20.274493 # ok 1913 Set SVE VL 7648
3644 12:28:20.274576 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3645 12:28:20.274661 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3646 12:28:20.274747 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3647 12:28:20.274831 # ok 1917 Set SVE VL 7664
3648 12:28:20.275137 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3649 12:28:20.275233 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3650 12:28:20.275321 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3651 12:28:20.275409 # ok 1921 Set SVE VL 7680
3652 12:28:20.275498 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3653 12:28:20.275583 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3654 12:28:20.275667 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3655 12:28:20.275750 # ok 1925 Set SVE VL 7696
3656 12:28:20.275834 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3657 12:28:20.275917 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3658 12:28:20.276000 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3659 12:28:20.276085 # ok 1929 Set SVE VL 7712
3660 12:28:20.276171 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3661 12:28:20.276253 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3662 12:28:20.276332 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3663 12:28:20.276409 # ok 1933 Set SVE VL 7728
3664 12:28:20.276492 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3665 12:28:20.276575 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3666 12:28:20.276660 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3667 12:28:20.276744 # ok 1937 Set SVE VL 7744
3668 12:28:20.276852 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3669 12:28:20.276936 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3670 12:28:20.277020 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3671 12:28:20.277107 # ok 1941 Set SVE VL 7760
3672 12:28:20.277192 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3673 12:28:20.277276 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3674 12:28:20.277360 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3675 12:28:20.277443 # ok 1945 Set SVE VL 7776
3676 12:28:20.277526 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3677 12:28:20.277609 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3678 12:28:20.277704 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3679 12:28:20.277788 # ok 1949 Set SVE VL 7792
3680 12:28:20.277892 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3681 12:28:20.277979 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3682 12:28:20.278063 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3683 12:28:20.278150 # ok 1953 Set SVE VL 7808
3684 12:28:20.278232 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3685 12:28:20.278314 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3686 12:28:20.280198 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3687 12:28:20.280327 # ok 1957 Set SVE VL 7824
3688 12:28:20.280450 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3689 12:28:20.280556 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3690 12:28:20.280865 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3691 12:28:20.280982 # ok 1961 Set SVE VL 7840
3692 12:28:20.281100 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3693 12:28:20.281199 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3694 12:28:20.281334 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3695 12:28:20.281432 # ok 1965 Set SVE VL 7856
3696 12:28:20.281524 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3697 12:28:20.281813 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3698 12:28:20.281907 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3699 12:28:20.281981 # ok 1969 Set SVE VL 7872
3700 12:28:20.282387 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3701 12:28:20.282674 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3702 12:28:20.282758 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3703 12:28:20.282834 # ok 1973 Set SVE VL 7888
3704 12:28:20.282923 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3705 12:28:20.283212 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3706 12:28:20.283332 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3707 12:28:20.283421 # ok 1977 Set SVE VL 7904
3708 12:28:20.283520 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3709 12:28:20.283817 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3710 12:28:20.283922 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3711 12:28:20.284021 # ok 1981 Set SVE VL 7920
3712 12:28:20.284120 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3713 12:28:20.284218 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3714 12:28:20.284318 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3715 12:28:20.284416 # ok 1985 Set SVE VL 7936
3716 12:28:20.284518 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3717 12:28:20.284817 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3718 12:28:20.284935 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3719 12:28:20.285037 # ok 1989 Set SVE VL 7952
3720 12:28:20.285161 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3721 12:28:20.285276 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3722 12:28:20.285565 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3723 12:28:20.285659 # ok 1993 Set SVE VL 7968
3724 12:28:20.285951 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3725 12:28:20.286056 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3726 12:28:20.286158 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3727 12:28:20.286257 # ok 1997 Set SVE VL 7984
3728 12:28:20.286349 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3729 12:28:20.286440 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3730 12:28:20.286719 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3731 12:28:20.286820 # ok 2001 Set SVE VL 8000
3732 12:28:20.286915 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3733 12:28:20.287010 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3734 12:28:20.287309 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3735 12:28:20.287398 # ok 2005 Set SVE VL 8016
3736 12:28:20.287498 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3737 12:28:20.287587 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3738 12:28:20.287690 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3739 12:28:20.287792 # ok 2009 Set SVE VL 8032
3740 12:28:20.288074 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3741 12:28:20.288169 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3742 12:28:20.288272 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3743 12:28:20.288349 # ok 2013 Set SVE VL 8048
3744 12:28:20.288435 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3745 12:28:20.288707 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3746 12:28:20.288786 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3747 12:28:20.289057 # ok 2017 Set SVE VL 8064
3748 12:28:20.289146 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3749 12:28:20.289231 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3750 12:28:20.289331 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3751 12:28:20.289416 # ok 2021 Set SVE VL 8080
3752 12:28:20.289514 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3753 12:28:20.289599 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3754 12:28:20.289903 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3755 12:28:20.290189 # ok 2025 Set SVE VL 8096
3756 12:28:20.290281 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3757 12:28:20.290367 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3758 12:28:20.290465 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3759 12:28:20.290742 # ok 2029 Set SVE VL 8112
3760 12:28:20.290831 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3761 12:28:20.290911 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3762 12:28:20.291029 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3763 12:28:20.291112 # ok 2033 Set SVE VL 8128
3764 12:28:20.291207 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3765 12:28:20.291292 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3766 12:28:20.291393 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3767 12:28:20.291482 # ok 2037 Set SVE VL 8144
3768 12:28:20.291581 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3769 12:28:20.291667 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3770 12:28:20.291764 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3771 12:28:20.291864 # ok 2041 Set SVE VL 8160
3772 12:28:20.291963 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3773 12:28:20.292065 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3774 12:28:20.292167 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3775 12:28:20.292264 # ok 2045 Set SVE VL 8176
3776 12:28:20.292955 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3777 12:28:20.293058 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3778 12:28:20.293146 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3779 12:28:20.293229 # ok 2049 Set SVE VL 8192
3780 12:28:20.293312 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3781 12:28:20.293397 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3782 12:28:20.293684 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3783 12:28:20.293777 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3784 12:28:20.293863 # ok 2054 Streaming SVE get_fpsimd() gave same state
3785 12:28:20.293947 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3786 12:28:20.294029 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3787 12:28:20.294128 # ok 2057 Set Streaming SVE VL 16
3788 12:28:20.294210 # ok 2058 Set and get Streaming SVE data for VL 16
3789 12:28:20.294489 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3790 12:28:20.294582 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3791 12:28:20.294667 # ok 2061 Set Streaming SVE VL 32
3792 12:28:20.294749 # ok 2062 Set and get Streaming SVE data for VL 32
3793 12:28:20.295026 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3794 12:28:20.295117 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3795 12:28:20.295202 # ok 2065 Set Streaming SVE VL 48
3796 12:28:20.295286 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3797 12:28:20.295370 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3798 12:28:20.295470 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3799 12:28:20.295557 # ok 2069 Set Streaming SVE VL 64
3800 12:28:20.295641 # ok 2070 Set and get Streaming SVE data for VL 64
3801 12:28:20.295739 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3802 12:28:20.296019 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3803 12:28:20.296160 # ok 2073 Set Streaming SVE VL 80
3804 12:28:20.296250 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3805 12:28:20.296346 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3806 12:28:20.296442 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3807 12:28:20.296529 # ok 2077 Set Streaming SVE VL 96
3808 12:28:20.296612 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3809 12:28:20.296900 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3810 12:28:20.296989 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3811 12:28:20.297090 # ok 2081 Set Streaming SVE VL 112
3812 12:28:20.297175 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3813 12:28:20.297271 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3814 12:28:20.297371 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3815 12:28:20.297457 # ok 2085 Set Streaming SVE VL 128
3816 12:28:20.297555 # ok 2086 Set and get Streaming SVE data for VL 128
3817 12:28:20.297859 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3818 12:28:20.297977 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3819 12:28:20.298079 # ok 2089 Set Streaming SVE VL 144
3820 12:28:20.298179 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3821 12:28:20.298280 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3822 12:28:20.298580 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3823 12:28:20.298673 # ok 2093 Set Streaming SVE VL 160
3824 12:28:20.298775 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3825 12:28:20.298877 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3826 12:28:20.299168 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3827 12:28:20.299260 # ok 2097 Set Streaming SVE VL 176
3828 12:28:20.299345 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3829 12:28:20.299445 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3830 12:28:20.299532 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3831 12:28:20.299630 # ok 2101 Set Streaming SVE VL 192
3832 12:28:20.299730 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3833 12:28:20.300019 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3834 12:28:20.300113 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3835 12:28:20.300212 # ok 2105 Set Streaming SVE VL 208
3836 12:28:20.300291 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3837 12:28:20.300378 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3838 12:28:20.300640 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3839 12:28:20.300731 # ok 2109 Set Streaming SVE VL 224
3840 12:28:20.301070 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3841 12:28:20.301156 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3842 12:28:20.301231 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3843 12:28:20.301312 # ok 2113 Set Streaming SVE VL 240
3844 12:28:20.301580 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3845 12:28:20.301672 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3846 12:28:20.301747 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3847 12:28:20.301842 # ok 2117 Set Streaming SVE VL 256
3848 12:28:20.301924 # ok 2118 Set and get Streaming SVE data for VL 256
3849 12:28:20.302193 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3850 12:28:20.302281 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3851 12:28:20.302361 # ok 2121 Set Streaming SVE VL 272
3852 12:28:20.302457 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3853 12:28:20.302538 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3854 12:28:20.302638 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3855 12:28:20.302724 # ok 2125 Set Streaming SVE VL 288
3856 12:28:20.305501 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3857 12:28:20.306205 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3858 12:28:20.306500 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3859 12:28:20.306595 # ok 2129 Set Streaming SVE VL 304
3860 12:28:20.306695 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3861 12:28:20.306990 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3862 12:28:20.307133 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3863 12:28:20.307236 # ok 2133 Set Streaming SVE VL 320
3864 12:28:20.307351 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3865 12:28:20.307448 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3866 12:28:20.307560 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3867 12:28:20.307671 # ok 2137 Set Streaming SVE VL 336
3868 12:28:20.307783 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3869 12:28:20.307894 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3870 12:28:20.308006 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3871 12:28:20.308117 # ok 2141 Set Streaming SVE VL 352
3872 12:28:20.308325 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3873 12:28:20.308445 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3874 12:28:20.308760 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3875 12:28:20.308874 # ok 2145 Set Streaming SVE VL 368
3876 12:28:20.308987 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3877 12:28:20.309084 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3878 12:28:20.309199 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3879 12:28:20.309311 # ok 2149 Set Streaming SVE VL 384
3880 12:28:20.309443 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3881 12:28:20.309755 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3882 12:28:20.309872 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3883 12:28:20.310169 # ok 2153 Set Streaming SVE VL 400
3884 12:28:20.310269 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3885 12:28:20.310379 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3886 12:28:20.310490 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3887 12:28:20.310602 # ok 2157 Set Streaming SVE VL 416
3888 12:28:20.310713 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3889 12:28:20.311051 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3890 12:28:20.311152 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3891 12:28:20.311261 # ok 2161 Set Streaming SVE VL 432
3892 12:28:20.311349 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3893 12:28:20.311456 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3894 12:28:20.311747 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3895 12:28:20.311841 # ok 2165 Set Streaming SVE VL 448
3896 12:28:20.311941 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3897 12:28:20.312230 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3898 12:28:20.312330 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3899 12:28:20.312420 # ok 2169 Set Streaming SVE VL 464
3900 12:28:20.312691 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3901 12:28:20.312786 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3902 12:28:20.312876 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3903 12:28:20.313145 # ok 2173 Set Streaming SVE VL 480
3904 12:28:20.313247 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3905 12:28:20.313533 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3906 12:28:20.313629 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3907 12:28:20.313926 # ok 2177 Set Streaming SVE VL 496
3908 12:28:20.314016 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3909 12:28:20.314292 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3910 12:28:20.314384 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3911 12:28:20.314486 # ok 2181 Set Streaming SVE VL 512
3912 12:28:20.314763 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3913 12:28:20.314853 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3914 12:28:20.314940 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3915 12:28:20.315038 # ok 2185 Set Streaming SVE VL 528
3916 12:28:20.315139 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3917 12:28:20.315242 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3918 12:28:20.315342 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3919 12:28:20.315627 # ok 2189 Set Streaming SVE VL 544
3920 12:28:20.315719 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3921 12:28:20.315827 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3922 12:28:20.316109 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3923 12:28:20.316205 # ok 2193 Set Streaming SVE VL 560
3924 12:28:20.316297 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3925 12:28:20.317104 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3926 12:28:20.317200 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3927 12:28:20.317282 # ok 2197 Set Streaming SVE VL 576
3928 12:28:20.317361 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3929 12:28:20.317435 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3930 12:28:20.317510 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3931 12:28:20.317780 # ok 2201 Set Streaming SVE VL 592
3932 12:28:20.317870 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3933 12:28:20.317952 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3934 12:28:20.318049 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3935 12:28:20.318150 # ok 2205 Set Streaming SVE VL 608
3936 12:28:20.318250 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3937 12:28:20.318537 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3938 12:28:20.318624 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3939 12:28:20.318719 # ok 2209 Set Streaming SVE VL 624
3940 12:28:20.318818 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3941 12:28:20.319106 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3942 12:28:20.319198 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3943 12:28:20.319483 # ok 2213 Set Streaming SVE VL 640
3944 12:28:20.319573 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3945 12:28:20.319670 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3946 12:28:20.319947 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3947 12:28:20.320041 # ok 2217 Set Streaming SVE VL 656
3948 12:28:20.320134 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3949 12:28:20.320226 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3950 12:28:20.320516 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3951 12:28:20.320609 # ok 2221 Set Streaming SVE VL 672
3952 12:28:20.320697 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3953 12:28:20.320986 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3954 12:28:20.321080 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3955 12:28:20.321341 # ok 2225 Set Streaming SVE VL 688
3956 12:28:20.321422 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3957 12:28:20.321510 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3958 12:28:20.321787 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3959 12:28:20.321887 # ok 2229 Set Streaming SVE VL 704
3960 12:28:20.321977 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3961 12:28:20.322250 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3962 12:28:20.322344 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3963 12:28:20.322430 # ok 2233 Set Streaming SVE VL 720
3964 12:28:20.322709 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3965 12:28:20.322809 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3966 12:28:20.322905 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3967 12:28:20.323178 # ok 2237 Set Streaming SVE VL 736
3968 12:28:20.323264 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3969 12:28:20.323537 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3970 12:28:20.323643 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3971 12:28:20.323731 # ok 2241 Set Streaming SVE VL 752
3972 12:28:20.323829 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3973 12:28:20.324120 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3974 12:28:20.324228 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3975 12:28:20.324323 # ok 2245 Set Streaming SVE VL 768
3976 12:28:20.324400 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3977 12:28:20.324670 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3978 12:28:20.324764 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3979 12:28:20.324854 # ok 2249 Set Streaming SVE VL 784
3980 12:28:20.325125 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3981 12:28:20.325222 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3982 12:28:20.325312 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3983 12:28:20.325619 # ok 2253 Set Streaming SVE VL 800
3984 12:28:20.327905 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3985 12:28:20.328085 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3986 12:28:20.328176 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3987 12:28:20.328264 # ok 2257 Set Streaming SVE VL 816
3988 12:28:20.328342 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3989 12:28:20.328417 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3990 12:28:20.328491 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3991 12:28:20.328562 # ok 2261 Set Streaming SVE VL 832
3992 12:28:20.328635 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3993 12:28:20.328708 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3994 12:28:20.328781 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3995 12:28:20.328854 # ok 2265 Set Streaming SVE VL 848
3996 12:28:20.328927 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3997 12:28:20.329001 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3998 12:28:20.329074 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3999 12:28:20.329366 # ok 2269 Set Streaming SVE VL 864
4000 12:28:20.329461 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
4001 12:28:20.329539 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
4002 12:28:20.329616 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4003 12:28:20.329709 # ok 2273 Set Streaming SVE VL 880
4004 12:28:20.329782 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4005 12:28:20.329853 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4006 12:28:20.329924 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4007 12:28:20.329997 # ok 2277 Set Streaming SVE VL 896
4008 12:28:20.330069 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4009 12:28:20.331835 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4010 12:28:20.331978 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4011 12:28:20.332082 # ok 2281 Set Streaming SVE VL 912
4012 12:28:20.332184 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4013 12:28:20.332471 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4014 12:28:20.332596 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4015 12:28:20.332688 # ok 2285 Set Streaming SVE VL 928
4016 12:28:20.332790 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4017 12:28:20.333089 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4018 12:28:20.333200 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4019 12:28:20.333293 # ok 2289 Set Streaming SVE VL 944
4020 12:28:20.333413 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4021 12:28:20.334008 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4022 12:28:20.334328 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4023 12:28:20.334434 # ok 2293 Set Streaming SVE VL 960
4024 12:28:20.334542 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4025 12:28:20.334658 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4026 12:28:20.334767 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4027 12:28:20.334881 # ok 2297 Set Streaming SVE VL 976
4028 12:28:20.335197 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4029 12:28:20.335322 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4030 12:28:20.335432 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4031 12:28:20.335541 # ok 2301 Set Streaming SVE VL 992
4032 12:28:20.335844 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4033 12:28:20.335952 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4034 12:28:20.336058 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4035 12:28:20.336164 # ok 2305 Set Streaming SVE VL 1008
4036 12:28:20.336280 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4037 12:28:20.336589 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4038 12:28:20.336703 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4039 12:28:20.336822 # ok 2309 Set Streaming SVE VL 1024
4040 12:28:20.336916 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4041 12:28:20.337023 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4042 12:28:20.337129 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4043 12:28:20.337239 # ok 2313 Set Streaming SVE VL 1040
4044 12:28:20.337547 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4045 12:28:20.337872 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4046 12:28:20.338195 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4047 12:28:20.338305 # ok 2317 Set Streaming SVE VL 1056
4048 12:28:20.338413 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4049 12:28:20.338522 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4050 12:28:20.338627 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4051 12:28:20.338933 # ok 2321 Set Streaming SVE VL 1072
4052 12:28:20.339040 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4053 12:28:20.339147 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4054 12:28:20.339451 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4055 12:28:20.339554 # ok 2325 Set Streaming SVE VL 1088
4056 12:28:20.339659 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4057 12:28:20.339966 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4058 12:28:20.340089 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4059 12:28:20.340199 # ok 2329 Set Streaming SVE VL 1104
4060 12:28:20.340310 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4061 12:28:20.340614 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4062 12:28:20.340736 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4063 12:28:20.340844 # ok 2333 Set Streaming SVE VL 1120
4064 12:28:20.340958 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4065 12:28:20.341264 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4066 12:28:20.341379 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4067 12:28:20.341511 # ok 2337 Set Streaming SVE VL 1136
4068 12:28:20.341825 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4069 12:28:20.341959 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4070 12:28:20.342252 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4071 12:28:20.342347 # ok 2341 Set Streaming SVE VL 1152
4072 12:28:20.342440 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4073 12:28:20.342724 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4074 12:28:20.342824 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4075 12:28:20.342916 # ok 2345 Set Streaming SVE VL 1168
4076 12:28:20.343208 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4077 12:28:20.343328 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4078 12:28:20.343428 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4079 12:28:20.343530 # ok 2349 Set Streaming SVE VL 1184
4080 12:28:20.343826 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4081 12:28:20.343932 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4082 12:28:20.344040 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4083 12:28:20.344319 # ok 2353 Set Streaming SVE VL 1200
4084 12:28:20.344600 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4085 12:28:20.344683 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4086 12:28:20.344956 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4087 12:28:20.345037 # ok 2357 Set Streaming SVE VL 1216
4088 12:28:20.345306 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4089 12:28:20.345391 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4090 12:28:20.345871 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4091 12:28:20.345964 # ok 2361 Set Streaming SVE VL 1232
4092 12:28:20.346063 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4093 12:28:20.346340 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4094 12:28:20.346433 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4095 12:28:20.346524 # ok 2365 Set Streaming SVE VL 1248
4096 12:28:20.346812 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4097 12:28:20.346925 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4098 12:28:20.347026 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4099 12:28:20.347315 # ok 2369 Set Streaming SVE VL 1264
4100 12:28:20.347424 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4101 12:28:20.347529 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4102 12:28:20.347812 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4103 12:28:20.347899 # ok 2373 Set Streaming SVE VL 1280
4104 12:28:20.347990 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4105 12:28:20.348095 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4106 12:28:20.348366 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4107 12:28:20.348461 # ok 2377 Set Streaming SVE VL 1296
4108 12:28:20.348735 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4109 12:28:20.348833 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4110 12:28:20.349105 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4111 12:28:20.349192 # ok 2381 Set Streaming SVE VL 1312
4112 12:28:20.349283 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4113 12:28:20.349562 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4114 12:28:20.349861 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4115 12:28:20.349954 # ok 2385 Set Streaming SVE VL 1328
4116 12:28:20.350055 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4117 12:28:20.350175 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4118 12:28:20.350487 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4119 12:28:20.350597 # ok 2389 Set Streaming SVE VL 1344
4120 12:28:20.350699 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4121 12:28:20.350818 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4122 12:28:20.351103 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4123 12:28:20.351192 # ok 2393 Set Streaming SVE VL 1360
4124 12:28:20.351469 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4125 12:28:20.351556 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4126 12:28:20.351841 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4127 12:28:20.351931 # ok 2397 Set Streaming SVE VL 1376
4128 12:28:20.352022 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4129 12:28:20.352112 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4130 12:28:20.352395 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4131 12:28:20.352498 # ok 2401 Set Streaming SVE VL 1392
4132 12:28:20.352776 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4133 12:28:20.352862 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4134 12:28:20.352957 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4135 12:28:20.353058 # ok 2405 Set Streaming SVE VL 1408
4136 12:28:20.353161 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4137 12:28:20.353285 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4138 12:28:20.353574 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4139 12:28:20.353864 # ok 2409 Set Streaming SVE VL 1424
4140 12:28:20.353954 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4141 12:28:20.354234 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4142 12:28:20.354335 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4143 12:28:20.354433 # ok 2413 Set Streaming SVE VL 1440
4144 12:28:20.354727 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4145 12:28:20.354817 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4146 12:28:20.354909 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4147 12:28:20.355008 # ok 2417 Set Streaming SVE VL 1456
4148 12:28:20.355301 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4149 12:28:20.355409 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4150 12:28:20.355697 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4151 12:28:20.355787 # ok 2421 Set Streaming SVE VL 1472
4152 12:28:20.355882 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4153 12:28:20.356164 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4154 12:28:20.356262 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4155 12:28:20.356363 # ok 2425 Set Streaming SVE VL 1488
4156 12:28:20.356461 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4157 12:28:20.356747 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4158 12:28:20.356848 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4159 12:28:20.359475 # ok 2429 Set Streaming SVE VL 1504
4160 12:28:20.359649 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4161 12:28:20.359736 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4162 12:28:20.360016 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4163 12:28:20.360100 # ok 2433 Set Streaming SVE VL 1520
4164 12:28:20.360192 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4165 12:28:20.360282 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4166 12:28:20.360566 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4167 12:28:20.361754 # ok 2437 Set Streaming SVE VL 1536
4168 12:28:20.361866 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4169 12:28:20.361958 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4170 12:28:20.362048 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4171 12:28:20.362130 # ok 2441 Set Streaming SVE VL 1552
4172 12:28:20.362213 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4173 12:28:20.362306 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4174 12:28:20.362395 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4175 12:28:20.362482 # ok 2445 Set Streaming SVE VL 1568
4176 12:28:20.362569 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4177 12:28:20.362648 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4178 12:28:20.362920 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4179 12:28:20.363008 # ok 2449 Set Streaming SVE VL 1584
4180 12:28:20.363087 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4181 12:28:20.363170 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4182 12:28:20.363249 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4183 12:28:20.363345 # ok 2453 Set Streaming SVE VL 1600
4184 12:28:20.363425 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4185 12:28:20.363515 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4186 12:28:20.363611 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4187 12:28:20.363704 # ok 2457 Set Streaming SVE VL 1616
4188 12:28:20.363801 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4189 12:28:20.364102 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4190 12:28:20.364191 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4191 12:28:20.364295 # ok 2461 Set Streaming SVE VL 1632
4192 12:28:20.364388 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4193 12:28:20.364663 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4194 12:28:20.364759 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4195 12:28:20.364859 # ok 2465 Set Streaming SVE VL 1648
4196 12:28:20.365324 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4197 12:28:20.365417 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4198 12:28:20.365514 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4199 12:28:20.365599 # ok 2469 Set Streaming SVE VL 1664
4200 12:28:20.365905 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4201 12:28:20.366021 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4202 12:28:20.366305 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4203 12:28:20.366392 # ok 2473 Set Streaming SVE VL 1680
4204 12:28:20.366482 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4205 12:28:20.366581 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4206 12:28:20.366858 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4207 12:28:20.366958 # ok 2477 Set Streaming SVE VL 1696
4208 12:28:20.367226 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4209 12:28:20.367316 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4210 12:28:20.367414 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4211 12:28:20.367494 # ok 2481 Set Streaming SVE VL 1712
4212 12:28:20.367587 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4213 12:28:20.367705 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4214 12:28:20.367979 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4215 12:28:20.368083 # ok 2485 Set Streaming SVE VL 1728
4216 12:28:20.368369 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4217 12:28:20.368457 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4218 12:28:20.368547 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4219 12:28:20.368637 # ok 2489 Set Streaming SVE VL 1744
4220 12:28:20.368725 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4221 12:28:20.368833 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4222 12:28:20.369107 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4223 12:28:20.369204 # ok 2493 Set Streaming SVE VL 1760
4224 12:28:20.369300 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4225 12:28:20.369575 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4226 12:28:20.369901 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4227 12:28:20.369990 # ok 2497 Set Streaming SVE VL 1776
4228 12:28:20.370080 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4229 12:28:20.370364 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4230 12:28:20.370463 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4231 12:28:20.370553 # ok 2501 Set Streaming SVE VL 1792
4232 12:28:20.370838 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4233 12:28:20.370939 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4234 12:28:20.371231 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4235 12:28:20.371333 # ok 2505 Set Streaming SVE VL 1808
4236 12:28:20.371431 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4237 12:28:20.371712 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4238 12:28:20.371804 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4239 12:28:20.371903 # ok 2509 Set Streaming SVE VL 1824
4240 12:28:20.371999 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4241 12:28:20.372117 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4242 12:28:20.372408 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4243 12:28:20.372518 # ok 2513 Set Streaming SVE VL 1840
4244 12:28:20.372608 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4245 12:28:20.372892 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4246 12:28:20.372998 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4247 12:28:20.373088 # ok 2517 Set Streaming SVE VL 1856
4248 12:28:20.373359 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4249 12:28:20.373441 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4250 12:28:20.373697 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4251 12:28:20.373797 # ok 2521 Set Streaming SVE VL 1872
4252 12:28:20.374085 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4253 12:28:20.374180 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4254 12:28:20.374273 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4255 12:28:20.374364 # ok 2525 Set Streaming SVE VL 1888
4256 12:28:20.374642 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4257 12:28:20.374743 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4258 12:28:20.375030 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4259 12:28:20.375142 # ok 2529 Set Streaming SVE VL 1904
4260 12:28:20.375243 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4261 12:28:20.375535 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4262 12:28:20.375650 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4263 12:28:20.375750 # ok 2533 Set Streaming SVE VL 1920
4264 12:28:20.376047 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4265 12:28:20.376158 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4266 12:28:20.376328 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4267 12:28:20.376439 # ok 2537 Set Streaming SVE VL 1936
4268 12:28:20.376728 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4269 12:28:20.377018 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4270 12:28:20.377103 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4271 12:28:20.377194 # ok 2541 Set Streaming SVE VL 1952
4272 12:28:20.377487 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4273 12:28:20.377582 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4274 12:28:20.377908 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4275 12:28:20.378005 # ok 2545 Set Streaming SVE VL 1968
4276 12:28:20.378097 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4277 12:28:20.378387 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4278 12:28:20.378500 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4279 12:28:20.378596 # ok 2549 Set Streaming SVE VL 1984
4280 12:28:20.378886 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4281 12:28:20.378995 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4282 12:28:20.379085 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4283 12:28:20.379176 # ok 2553 Set Streaming SVE VL 2000
4284 12:28:20.379472 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4285 12:28:20.379578 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4286 12:28:20.379666 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4287 12:28:20.379949 # ok 2557 Set Streaming SVE VL 2016
4288 12:28:20.380046 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4289 12:28:20.380135 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4290 12:28:20.380416 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4291 12:28:20.380512 # ok 2561 Set Streaming SVE VL 2032
4292 12:28:20.380603 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4293 12:28:20.380888 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4294 12:28:20.381182 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4295 12:28:20.381275 # ok 2565 Set Streaming SVE VL 2048
4296 12:28:20.381367 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4297 12:28:20.381656 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4298 12:28:20.381952 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4299 12:28:20.382047 # ok 2569 Set Streaming SVE VL 2064
4300 12:28:20.382152 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4301 12:28:20.382438 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4302 12:28:20.382538 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4303 12:28:20.382628 # ok 2573 Set Streaming SVE VL 2080
4304 12:28:20.382926 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4305 12:28:20.383044 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4306 12:28:20.383329 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4307 12:28:20.383418 # ok 2577 Set Streaming SVE VL 2096
4308 12:28:20.383510 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4309 12:28:20.386535 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4310 12:28:20.386760 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4311 12:28:20.386853 # ok 2581 Set Streaming SVE VL 2112
4312 12:28:20.386958 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4313 12:28:20.387057 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4314 12:28:20.387347 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4315 12:28:20.387449 # ok 2585 Set Streaming SVE VL 2128
4316 12:28:20.387548 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4317 12:28:20.387834 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4318 12:28:20.387925 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4319 12:28:20.388025 # ok 2589 Set Streaming SVE VL 2144
4320 12:28:20.388318 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4321 12:28:20.388432 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4322 12:28:20.388531 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4323 12:28:20.388632 # ok 2593 Set Streaming SVE VL 2160
4324 12:28:20.388913 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4325 12:28:20.389003 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4326 12:28:20.389096 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4327 12:28:20.389190 # ok 2597 Set Streaming SVE VL 2176
4328 12:28:20.389296 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4329 12:28:20.389594 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4330 12:28:20.389903 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4331 12:28:20.390004 # ok 2601 Set Streaming SVE VL 2192
4332 12:28:20.390284 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4333 12:28:20.390392 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4334 12:28:20.390693 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4335 12:28:20.390787 # ok 2605 Set Streaming SVE VL 2208
4336 12:28:20.390890 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4337 12:28:20.391168 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4338 12:28:20.391254 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4339 12:28:20.391357 # ok 2609 Set Streaming SVE VL 2224
4340 12:28:20.391458 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4341 12:28:20.391568 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4342 12:28:20.391856 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4343 12:28:20.391953 # ok 2613 Set Streaming SVE VL 2240
4344 12:28:20.392057 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4345 12:28:20.392364 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4346 12:28:20.392466 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4347 12:28:20.392739 # ok 2617 Set Streaming SVE VL 2256
4348 12:28:20.392822 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4349 12:28:20.392912 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4350 12:28:20.393190 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4351 12:28:20.393293 # ok 2621 Set Streaming SVE VL 2272
4352 12:28:20.393582 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4353 12:28:20.393881 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4354 12:28:20.393980 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4355 12:28:20.394071 # ok 2625 Set Streaming SVE VL 2288
4356 12:28:20.394164 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4357 12:28:20.394452 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4358 12:28:20.394745 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4359 12:28:20.394852 # ok 2629 Set Streaming SVE VL 2304
4360 12:28:20.394939 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4361 12:28:20.395227 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4362 12:28:20.395318 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4363 12:28:20.395420 # ok 2633 Set Streaming SVE VL 2320
4364 12:28:20.395507 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4365 12:28:20.395610 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4366 12:28:20.395899 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4367 12:28:20.396007 # ok 2637 Set Streaming SVE VL 2336
4368 12:28:20.396116 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4369 12:28:20.396405 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4370 12:28:20.396677 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4371 12:28:20.396765 # ok 2641 Set Streaming SVE VL 2352
4372 12:28:20.396861 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4373 12:28:20.397140 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4374 12:28:20.397245 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4375 12:28:20.397337 # ok 2645 Set Streaming SVE VL 2368
4376 12:28:20.397446 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4377 12:28:20.397917 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4378 12:28:20.398007 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4379 12:28:20.398105 # ok 2649 Set Streaming SVE VL 2384
4380 12:28:20.398203 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4381 12:28:20.398500 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4382 12:28:20.398608 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4383 12:28:20.398726 # ok 2653 Set Streaming SVE VL 2400
4384 12:28:20.398831 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4385 12:28:20.399122 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4386 12:28:20.399407 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4387 12:28:20.399501 # ok 2657 Set Streaming SVE VL 2416
4388 12:28:20.399586 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4389 12:28:20.399683 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4390 12:28:20.399781 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4391 12:28:20.400070 # ok 2661 Set Streaming SVE VL 2432
4392 12:28:20.400165 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4393 12:28:20.400268 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4394 12:28:20.400368 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4395 12:28:20.400464 # ok 2665 Set Streaming SVE VL 2448
4396 12:28:20.400739 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4397 12:28:20.400835 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4398 12:28:20.401122 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4399 12:28:20.401214 # ok 2669 Set Streaming SVE VL 2464
4400 12:28:20.401500 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4401 12:28:20.401593 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4402 12:28:20.401703 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4403 12:28:20.401985 # ok 2673 Set Streaming SVE VL 2480
4404 12:28:20.402079 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4405 12:28:20.402184 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4406 12:28:20.402288 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4407 12:28:20.402392 # ok 2677 Set Streaming SVE VL 2496
4408 12:28:20.402684 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4409 12:28:20.402792 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4410 12:28:20.402896 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4411 12:28:20.402998 # ok 2681 Set Streaming SVE VL 2512
4412 12:28:20.403359 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4413 12:28:20.403448 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4414 12:28:20.403712 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4415 12:28:20.403803 # ok 2685 Set Streaming SVE VL 2528
4416 12:28:20.403903 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4417 12:28:20.404005 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4418 12:28:20.404107 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4419 12:28:20.404211 # ok 2689 Set Streaming SVE VL 2544
4420 12:28:20.404488 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4421 12:28:20.404586 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4422 12:28:20.404857 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4423 12:28:20.404950 # ok 2693 Set Streaming SVE VL 2560
4424 12:28:20.405215 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4425 12:28:20.405309 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4426 12:28:20.405416 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4427 12:28:20.405505 # ok 2697 Set Streaming SVE VL 2576
4428 12:28:20.405792 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4429 12:28:20.405900 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4430 12:28:20.406185 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4431 12:28:20.406271 # ok 2701 Set Streaming SVE VL 2592
4432 12:28:20.406557 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4433 12:28:20.406653 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4434 12:28:20.406746 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4435 12:28:20.406840 # ok 2705 Set Streaming SVE VL 2608
4436 12:28:20.407120 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4437 12:28:20.407224 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4438 12:28:20.407515 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4439 12:28:20.407611 # ok 2709 Set Streaming SVE VL 2624
4440 12:28:20.407710 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4441 12:28:20.407997 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4442 12:28:20.408102 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4443 12:28:20.408191 # ok 2713 Set Streaming SVE VL 2640
4444 12:28:20.408291 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4445 12:28:20.408571 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4446 12:28:20.408666 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4447 12:28:20.408755 # ok 2717 Set Streaming SVE VL 2656
4448 12:28:20.408845 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4449 12:28:20.409116 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4450 12:28:20.409413 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4451 12:28:20.409502 # ok 2721 Set Streaming SVE VL 2672
4452 12:28:20.409596 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4453 12:28:20.409895 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4454 12:28:20.410006 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4455 12:28:20.410110 # ok 2725 Set Streaming SVE VL 2688
4456 12:28:20.410400 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4457 12:28:20.410506 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4458 12:28:20.412802 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4459 12:28:20.412903 # ok 2729 Set Streaming SVE VL 2704
4460 12:28:20.413007 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4461 12:28:20.413111 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4462 12:28:20.413420 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4463 12:28:20.413513 # ok 2733 Set Streaming SVE VL 2720
4464 12:28:20.414132 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4465 12:28:20.414416 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4466 12:28:20.414509 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4467 12:28:20.414611 # ok 2737 Set Streaming SVE VL 2736
4468 12:28:20.414715 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4469 12:28:20.414819 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4470 12:28:20.415108 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4471 12:28:20.415202 # ok 2741 Set Streaming SVE VL 2752
4472 12:28:20.415304 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4473 12:28:20.415417 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4474 12:28:20.415707 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4475 12:28:20.415799 # ok 2745 Set Streaming SVE VL 2768
4476 12:28:20.415901 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4477 12:28:20.416004 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4478 12:28:20.417513 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4479 12:28:20.417608 # ok 2749 Set Streaming SVE VL 2784
4480 12:28:20.417696 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4481 12:28:20.417779 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4482 12:28:20.417864 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4483 12:28:20.417949 # ok 2753 Set Streaming SVE VL 2800
4484 12:28:20.418035 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4485 12:28:20.418121 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4486 12:28:20.418208 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4487 12:28:20.418294 # ok 2757 Set Streaming SVE VL 2816
4488 12:28:20.418381 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4489 12:28:20.418467 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4490 12:28:20.418552 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4491 12:28:20.418638 # ok 2761 Set Streaming SVE VL 2832
4492 12:28:20.418723 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4493 12:28:20.418998 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4494 12:28:20.419088 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4495 12:28:20.419167 # ok 2765 Set Streaming SVE VL 2848
4496 12:28:20.419249 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4497 12:28:20.419335 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4498 12:28:20.419420 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4499 12:28:20.419506 # ok 2769 Set Streaming SVE VL 2864
4500 12:28:20.419610 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4501 12:28:20.419700 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4502 12:28:20.419788 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4503 12:28:20.419876 # ok 2773 Set Streaming SVE VL 2880
4504 12:28:20.419978 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4505 12:28:20.420067 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4506 12:28:20.420155 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4507 12:28:20.420257 # ok 2777 Set Streaming SVE VL 2896
4508 12:28:20.420358 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4509 12:28:20.420454 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4510 12:28:20.420927 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4511 12:28:20.421025 # ok 2781 Set Streaming SVE VL 2912
4512 12:28:20.421124 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4513 12:28:20.421401 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4514 12:28:20.421499 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4515 12:28:20.421771 # ok 2785 Set Streaming SVE VL 2928
4516 12:28:20.422051 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4517 12:28:20.422151 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4518 12:28:20.422612 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4519 12:28:20.422705 # ok 2789 Set Streaming SVE VL 2944
4520 12:28:20.422788 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4521 12:28:20.422879 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4522 12:28:20.422959 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4523 12:28:20.423049 # ok 2793 Set Streaming SVE VL 2960
4524 12:28:20.423333 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4525 12:28:20.423430 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4526 12:28:20.423529 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4527 12:28:20.423627 # ok 2797 Set Streaming SVE VL 2976
4528 12:28:20.423731 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4529 12:28:20.424025 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4530 12:28:20.424125 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4531 12:28:20.424402 # ok 2801 Set Streaming SVE VL 2992
4532 12:28:20.424489 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4533 12:28:20.424763 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4534 12:28:20.424860 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4535 12:28:20.424957 # ok 2805 Set Streaming SVE VL 3008
4536 12:28:20.425051 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4537 12:28:20.425329 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4538 12:28:20.425607 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4539 12:28:20.425888 # ok 2809 Set Streaming SVE VL 3024
4540 12:28:20.425992 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4541 12:28:20.426280 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4542 12:28:20.426577 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4543 12:28:20.426668 # ok 2813 Set Streaming SVE VL 3040
4544 12:28:20.426955 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4545 12:28:20.427235 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4546 12:28:20.427337 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4547 12:28:20.427435 # ok 2817 Set Streaming SVE VL 3056
4548 12:28:20.427718 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4549 12:28:20.428004 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4550 12:28:20.428342 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4551 12:28:20.428433 # ok 2821 Set Streaming SVE VL 3072
4552 12:28:20.428510 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4553 12:28:20.428771 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4554 12:28:20.429278 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4555 12:28:20.429374 # ok 2825 Set Streaming SVE VL 3088
4556 12:28:20.429452 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4557 12:28:20.429532 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4558 12:28:20.429611 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4559 12:28:20.429890 # ok 2829 Set Streaming SVE VL 3104
4560 12:28:20.429977 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4561 12:28:20.430069 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4562 12:28:20.430348 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4563 12:28:20.430439 # ok 2833 Set Streaming SVE VL 3120
4564 12:28:20.430531 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4565 12:28:20.430809 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4566 12:28:20.431085 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4567 12:28:20.431186 # ok 2837 Set Streaming SVE VL 3136
4568 12:28:20.431453 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4569 12:28:20.431552 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4570 12:28:20.431662 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4571 12:28:20.431765 # ok 2841 Set Streaming SVE VL 3152
4572 12:28:20.432042 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4573 12:28:20.432143 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4574 12:28:20.432423 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4575 12:28:20.432510 # ok 2845 Set Streaming SVE VL 3168
4576 12:28:20.432599 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4577 12:28:20.432864 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4578 12:28:20.433142 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4579 12:28:20.433240 # ok 2849 Set Streaming SVE VL 3184
4580 12:28:20.433322 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4581 12:28:20.433597 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4582 12:28:20.433893 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4583 12:28:20.433993 # ok 2853 Set Streaming SVE VL 3200
4584 12:28:20.434087 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4585 12:28:20.434374 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4586 12:28:20.434473 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4587 12:28:20.434750 # ok 2857 Set Streaming SVE VL 3216
4588 12:28:20.434846 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4589 12:28:20.435128 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4590 12:28:20.435230 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4591 12:28:20.435321 # ok 2861 Set Streaming SVE VL 3232
4592 12:28:20.435594 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4593 12:28:20.435693 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4594 12:28:20.435789 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4595 12:28:20.435889 # ok 2865 Set Streaming SVE VL 3248
4596 12:28:20.436180 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4597 12:28:20.436289 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4598 12:28:20.436563 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4599 12:28:20.436657 # ok 2869 Set Streaming SVE VL 3264
4600 12:28:20.436927 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4601 12:28:20.437020 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4602 12:28:20.437289 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4603 12:28:20.437561 # ok 2873 Set Streaming SVE VL 3280
4604 12:28:20.437667 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4605 12:28:20.437942 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4606 12:28:20.438035 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4607 12:28:20.438126 # ok 2877 Set Streaming SVE VL 3296
4608 12:28:20.460526 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4609 12:28:20.460793 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4610 12:28:20.460894 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4611 12:28:20.461005 # ok 2881 Set Streaming SVE VL 3312
4612 12:28:20.461114 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4613 12:28:20.461416 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4614 12:28:20.461523 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4615 12:28:20.468663 # ok 2885 Set Streaming SVE VL 3328
4616 12:28:20.468894 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4617 12:28:20.468993 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4618 12:28:20.469322 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4619 12:28:20.469433 # ok 2889 Set Streaming SVE VL 3344
4620 12:28:20.469529 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4621 12:28:20.469622 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4622 12:28:20.469770 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4623 12:28:20.469863 # ok 2893 Set Streaming SVE VL 3360
4624 12:28:20.470996 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4625 12:28:20.471410 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4626 12:28:20.471513 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4627 12:28:20.471625 # ok 2897 Set Streaming SVE VL 3376
4628 12:28:20.471732 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4629 12:28:20.472378 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4630 12:28:20.472479 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4631 12:28:20.472594 # ok 2901 Set Streaming SVE VL 3392
4632 12:28:20.472709 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4633 12:28:20.472797 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4634 12:28:20.472881 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4635 12:28:20.472958 # ok 2905 Set Streaming SVE VL 3408
4636 12:28:20.473345 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4637 12:28:20.473548 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4638 12:28:20.473666 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4639 12:28:20.473764 # ok 2909 Set Streaming SVE VL 3424
4640 12:28:20.473860 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4641 12:28:20.473951 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4642 12:28:20.474045 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4643 12:28:20.474140 # ok 2913 Set Streaming SVE VL 3440
4644 12:28:20.474253 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4645 12:28:20.478964 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4646 12:28:20.479626 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4647 12:28:20.479742 # ok 2917 Set Streaming SVE VL 3456
4648 12:28:20.479839 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4649 12:28:20.479934 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4650 12:28:20.480030 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4651 12:28:20.480126 # ok 2921 Set Streaming SVE VL 3472
4652 12:28:20.480220 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4653 12:28:20.480336 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4654 12:28:20.480433 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4655 12:28:20.480527 # ok 2925 Set Streaming SVE VL 3488
4656 12:28:20.480622 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4657 12:28:20.480716 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4658 12:28:20.480826 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4659 12:28:20.481147 # ok 2929 Set Streaming SVE VL 3504
4660 12:28:20.481279 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4661 12:28:20.481387 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4662 12:28:20.481516 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4663 12:28:20.481617 # ok 2933 Set Streaming SVE VL 3520
4664 12:28:20.481722 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4665 12:28:20.481837 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4666 12:28:20.481934 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4667 12:28:20.482028 # ok 2937 Set Streaming SVE VL 3536
4668 12:28:20.487131 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4669 12:28:20.487662 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4670 12:28:20.487748 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4671 12:28:20.487817 # ok 2941 Set Streaming SVE VL 3552
4672 12:28:20.487879 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4673 12:28:20.487953 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4674 12:28:20.488015 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4675 12:28:20.488075 # ok 2945 Set Streaming SVE VL 3568
4676 12:28:20.488133 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4677 12:28:20.488400 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4678 12:28:20.488472 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4679 12:28:20.488554 # ok 2949 Set Streaming SVE VL 3584
4680 12:28:20.488623 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4681 12:28:20.488683 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4682 12:28:20.488759 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4683 12:28:20.488840 # ok 2953 Set Streaming SVE VL 3600
4684 12:28:20.488914 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4685 12:28:20.489479 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4686 12:28:20.489586 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4687 12:28:20.489669 # ok 2957 Set Streaming SVE VL 3616
4688 12:28:20.489741 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4689 12:28:20.489816 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4690 12:28:20.489875 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4691 12:28:20.489956 # ok 2961 Set Streaming SVE VL 3632
4692 12:28:20.495635 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4693 12:28:20.496281 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4694 12:28:20.496376 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4695 12:28:20.496451 # ok 2965 Set Streaming SVE VL 3648
4696 12:28:20.496536 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4697 12:28:20.496625 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4698 12:28:20.496708 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4699 12:28:20.496799 # ok 2969 Set Streaming SVE VL 3664
4700 12:28:20.496878 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4701 12:28:20.496975 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4702 12:28:20.497046 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4703 12:28:20.497148 # ok 2973 Set Streaming SVE VL 3680
4704 12:28:20.497258 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4705 12:28:20.497552 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4706 12:28:20.497638 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4707 12:28:20.503054 # ok 2977 Set Streaming SVE VL 3696
4708 12:28:20.503374 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4709 12:28:20.503689 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4710 12:28:20.503798 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4711 12:28:20.503888 # ok 2981 Set Streaming SVE VL 3712
4712 12:28:20.503971 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4713 12:28:20.504057 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4714 12:28:20.504160 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4715 12:28:20.504244 # ok 2985 Set Streaming SVE VL 3728
4716 12:28:20.504323 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4717 12:28:20.504424 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4718 12:28:20.504510 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4719 12:28:20.504608 # ok 2989 Set Streaming SVE VL 3744
4720 12:28:20.504901 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4721 12:28:20.505027 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4722 12:28:20.505344 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4723 12:28:20.505481 # ok 2993 Set Streaming SVE VL 3760
4724 12:28:20.505596 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4725 12:28:20.510582 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4726 12:28:20.510836 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4727 12:28:20.511138 # ok 2997 Set Streaming SVE VL 3776
4728 12:28:20.511239 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4729 12:28:20.511326 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4730 12:28:20.511407 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4731 12:28:20.511505 # ok 3001 Set Streaming SVE VL 3792
4732 12:28:20.511577 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4733 12:28:20.511683 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4734 12:28:20.511798 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4735 12:28:20.511876 # ok 3005 Set Streaming SVE VL 3808
4736 12:28:20.511954 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4737 12:28:20.512018 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4738 12:28:20.512321 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4739 12:28:20.512412 # ok 3009 Set Streaming SVE VL 3824
4740 12:28:20.512536 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4741 12:28:20.512869 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4742 12:28:20.512954 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4743 12:28:20.513039 # ok 3013 Set Streaming SVE VL 3840
4744 12:28:20.513108 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4745 12:28:20.513384 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4746 12:28:20.513493 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4747 12:28:20.513592 # ok 3017 Set Streaming SVE VL 3856
4748 12:28:20.513693 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4749 12:28:20.513782 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4750 12:28:20.515254 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4751 12:28:20.515588 # ok 3021 Set Streaming SVE VL 3872
4752 12:28:20.515695 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4753 12:28:20.515826 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4754 12:28:20.515918 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4755 12:28:20.516026 # ok 3025 Set Streaming SVE VL 3888
4756 12:28:20.516115 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4757 12:28:20.517112 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4758 12:28:20.517359 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4759 12:28:20.517476 # ok 3029 Set Streaming SVE VL 3904
4760 12:28:20.517566 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4761 12:28:20.523148 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4762 12:28:20.523630 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4763 12:28:20.523735 # ok 3033 Set Streaming SVE VL 3920
4764 12:28:20.523820 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4765 12:28:20.523921 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4766 12:28:20.524015 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4767 12:28:20.524154 # ok 3037 Set Streaming SVE VL 3936
4768 12:28:20.524263 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4769 12:28:20.524391 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4770 12:28:20.524496 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4771 12:28:20.524603 # ok 3041 Set Streaming SVE VL 3952
4772 12:28:20.524696 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4773 12:28:20.524817 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4774 12:28:20.524921 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4775 12:28:20.525002 # ok 3045 Set Streaming SVE VL 3968
4776 12:28:20.525248 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4777 12:28:20.525351 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4778 12:28:20.525468 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4779 12:28:20.525557 # ok 3049 Set Streaming SVE VL 3984
4780 12:28:20.530757 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4781 12:28:20.531181 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4782 12:28:20.531291 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4783 12:28:20.531381 # ok 3053 Set Streaming SVE VL 4000
4784 12:28:20.531471 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4785 12:28:20.531576 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4786 12:28:20.531669 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4787 12:28:20.531768 # ok 3057 Set Streaming SVE VL 4016
4788 12:28:20.531854 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4789 12:28:20.531956 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4790 12:28:20.532058 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4791 12:28:20.532162 # ok 3061 Set Streaming SVE VL 4032
4792 12:28:20.532553 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4793 12:28:20.532661 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4794 12:28:20.532764 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4795 12:28:20.532868 # ok 3065 Set Streaming SVE VL 4048
4796 12:28:20.533186 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4797 12:28:20.533291 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4798 12:28:20.533397 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4799 12:28:20.533485 # ok 3069 Set Streaming SVE VL 4064
4800 12:28:20.538713 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4801 12:28:20.539157 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4802 12:28:20.539258 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4803 12:28:20.539341 # ok 3073 Set Streaming SVE VL 4080
4804 12:28:20.539451 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4805 12:28:20.539581 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4806 12:28:20.539703 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4807 12:28:20.539822 # ok 3077 Set Streaming SVE VL 4096
4808 12:28:20.539957 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4809 12:28:20.540062 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4810 12:28:20.540160 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4811 12:28:20.540296 # ok 3081 Set Streaming SVE VL 4112
4812 12:28:20.540410 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4813 12:28:20.540544 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4814 12:28:20.540664 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4815 12:28:20.540795 # ok 3085 Set Streaming SVE VL 4128
4816 12:28:20.540905 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4817 12:28:20.541030 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4818 12:28:20.541156 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4819 12:28:20.541286 # ok 3089 Set Streaming SVE VL 4144
4820 12:28:20.541389 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4821 12:28:20.541516 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4822 12:28:20.547107 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4823 12:28:20.547574 # ok 3093 Set Streaming SVE VL 4160
4824 12:28:20.547682 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4825 12:28:20.547776 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4826 12:28:20.547882 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4827 12:28:20.548177 # ok 3097 Set Streaming SVE VL 4176
4828 12:28:20.548283 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4829 12:28:20.548375 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4830 12:28:20.548476 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4831 12:28:20.548566 # ok 3101 Set Streaming SVE VL 4192
4832 12:28:20.548668 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4833 12:28:20.549006 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4834 12:28:20.549220 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4835 12:28:20.549467 # ok 3105 Set Streaming SVE VL 4208
4836 12:28:20.549618 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4837 12:28:20.549784 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4838 12:28:20.550242 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4839 12:28:20.550630 # ok 3109 Set Streaming SVE VL 4224
4840 12:28:20.550824 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4841 12:28:20.550989 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4842 12:28:20.551180 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4843 12:28:20.551334 # ok 3113 Set Streaming SVE VL 4240
4844 12:28:20.551490 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4845 12:28:20.551643 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4846 12:28:20.551780 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4847 12:28:20.551940 # ok 3117 Set Streaming SVE VL 4256
4848 12:28:20.552098 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4849 12:28:20.552275 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4850 12:28:20.552440 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4851 12:28:20.552603 # ok 3121 Set Streaming SVE VL 4272
4852 12:28:20.552769 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4853 12:28:20.552930 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4854 12:28:20.553124 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4855 12:28:20.553292 # ok 3125 Set Streaming SVE VL 4288
4856 12:28:20.553452 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4857 12:28:20.553575 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4858 12:28:20.553742 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4859 12:28:20.553946 # ok 3129 Set Streaming SVE VL 4304
4860 12:28:20.554133 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4861 12:28:20.554356 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4862 12:28:20.554526 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4863 12:28:20.554672 # ok 3133 Set Streaming SVE VL 4320
4864 12:28:20.560638 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4865 12:28:20.560956 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4866 12:28:20.561221 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4867 12:28:20.561469 # ok 3137 Set Streaming SVE VL 4336
4868 12:28:20.561716 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4869 12:28:20.561872 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4870 12:28:20.562021 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4871 12:28:20.562143 # ok 3141 Set Streaming SVE VL 4352
4872 12:28:20.567396 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4873 12:28:20.567856 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4874 12:28:20.567963 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4875 12:28:20.568052 # ok 3145 Set Streaming SVE VL 4368
4876 12:28:20.568139 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4877 12:28:20.568239 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4878 12:28:20.568326 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4879 12:28:20.568425 # ok 3149 Set Streaming SVE VL 4384
4880 12:28:20.568714 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4881 12:28:20.568818 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4882 12:28:20.568920 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4883 12:28:20.569219 # ok 3153 Set Streaming SVE VL 4400
4884 12:28:20.569320 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4885 12:28:20.569422 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4886 12:28:20.569523 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4887 12:28:20.574708 # ok 3157 Set Streaming SVE VL 4416
4888 12:28:20.575169 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4889 12:28:20.575293 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4890 12:28:20.575381 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4891 12:28:20.575696 # ok 3161 Set Streaming SVE VL 4432
4892 12:28:20.575800 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4893 12:28:20.575889 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4894 12:28:20.575987 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4895 12:28:20.576077 # ok 3165 Set Streaming SVE VL 4448
4896 12:28:20.576177 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4897 12:28:20.577487 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4898 12:28:20.577798 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4899 12:28:20.577903 # ok 3169 Set Streaming SVE VL 4464
4900 12:28:20.577996 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4901 12:28:20.578088 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4902 12:28:20.578180 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4903 12:28:20.578271 # ok 3173 Set Streaming SVE VL 4480
4904 12:28:20.578360 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4905 12:28:20.578446 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4906 12:28:20.578533 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4907 12:28:20.591021 # ok 3177 Set Streaming SVE VL 4496
4908 12:28:20.591485 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4909 12:28:20.591599 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4910 12:28:20.591697 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4911 12:28:20.591805 # ok 3181 Set Streaming SVE VL 4512
4912 12:28:20.591914 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4913 12:28:20.592018 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4914 12:28:20.592109 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4915 12:28:20.592194 # ok 3185 Set Streaming SVE VL 4528
4916 12:28:20.592269 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4917 12:28:20.592345 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4918 12:28:20.592460 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4919 12:28:20.592571 # ok 3189 Set Streaming SVE VL 4544
4920 12:28:20.592670 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4921 12:28:20.592990 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4922 12:28:20.593117 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4923 12:28:20.593221 # ok 3193 Set Streaming SVE VL 4560
4924 12:28:20.593317 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4925 12:28:20.593445 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4926 12:28:20.593555 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4927 12:28:20.605770 # ok 3197 Set Streaming SVE VL 4576
4928 12:28:20.607818 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4929 12:28:20.609303 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4930 12:28:20.609474 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4931 12:28:20.609613 # ok 3201 Set Streaming SVE VL 4592
4932 12:28:20.609752 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4933 12:28:20.609873 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4934 12:28:20.609989 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4935 12:28:20.610317 # ok 3205 Set Streaming SVE VL 4608
4936 12:28:20.610445 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4937 12:28:20.610562 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4938 12:28:20.610676 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4939 12:28:20.610790 # ok 3209 Set Streaming SVE VL 4624
4940 12:28:20.610905 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4941 12:28:20.611018 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4942 12:28:20.611133 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4943 12:28:20.611247 # ok 3213 Set Streaming SVE VL 4640
4944 12:28:20.611361 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4945 12:28:20.611475 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4946 12:28:20.623586 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4947 12:28:20.623980 # ok 3217 Set Streaming SVE VL 4656
4948 12:28:20.624175 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4949 12:28:20.624392 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4950 12:28:20.624574 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4951 12:28:20.624715 # ok 3221 Set Streaming SVE VL 4672
4952 12:28:20.624892 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4953 12:28:20.625077 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4954 12:28:20.625214 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4955 12:28:20.625357 # ok 3225 Set Streaming SVE VL 4688
4956 12:28:20.625816 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4957 12:28:20.625917 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4958 12:28:20.625999 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4959 12:28:20.626075 # ok 3229 Set Streaming SVE VL 4704
4960 12:28:20.626150 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4961 12:28:20.626225 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4962 12:28:20.626301 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4963 12:28:20.626376 # ok 3233 Set Streaming SVE VL 4720
4964 12:28:20.626452 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4965 12:28:20.626528 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4966 12:28:20.626603 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4967 12:28:20.626678 # ok 3237 Set Streaming SVE VL 4736
4968 12:28:20.638889 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4969 12:28:20.639226 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4970 12:28:20.639663 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4971 12:28:20.639871 # ok 3241 Set Streaming SVE VL 4752
4972 12:28:20.640017 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4973 12:28:20.640219 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4974 12:28:20.640439 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4975 12:28:20.640645 # ok 3245 Set Streaming SVE VL 4768
4976 12:28:20.640863 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4977 12:28:20.641120 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4978 12:28:20.641302 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4979 12:28:20.641500 # ok 3249 Set Streaming SVE VL 4784
4980 12:28:20.641694 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4981 12:28:20.641827 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4982 12:28:20.641982 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4983 12:28:20.642156 # ok 3253 Set Streaming SVE VL 4800
4984 12:28:20.642281 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4985 12:28:20.642436 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4986 12:28:20.642586 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4987 12:28:20.642748 # ok 3257 Set Streaming SVE VL 4816
4988 12:28:20.642889 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4989 12:28:20.643008 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4990 12:28:20.643166 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4991 12:28:20.643289 # ok 3261 Set Streaming SVE VL 4832
4992 12:28:20.643420 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4993 12:28:20.648106 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4994 12:28:20.648321 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4995 12:28:20.648721 # ok 3265 Set Streaming SVE VL 4848
4996 12:28:20.648835 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4997 12:28:20.648930 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4998 12:28:20.649020 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4999 12:28:20.649112 # ok 3269 Set Streaming SVE VL 4864
5000 12:28:20.649203 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
5001 12:28:20.649310 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
5002 12:28:20.649402 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5003 12:28:20.649491 # ok 3273 Set Streaming SVE VL 4880
5004 12:28:20.649577 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5005 12:28:20.649678 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5006 12:28:20.649786 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5007 12:28:20.649880 # ok 3277 Set Streaming SVE VL 4896
5008 12:28:20.658892 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5009 12:28:20.659204 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5010 12:28:20.659619 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5011 12:28:20.659830 # ok 3281 Set Streaming SVE VL 4912
5012 12:28:20.660019 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5013 12:28:20.660207 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5014 12:28:20.660438 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5015 12:28:20.660619 # ok 3285 Set Streaming SVE VL 4928
5016 12:28:20.660747 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5017 12:28:20.660899 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5018 12:28:20.661092 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5019 12:28:20.661299 # ok 3289 Set Streaming SVE VL 4944
5020 12:28:20.661447 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5021 12:28:20.661629 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5022 12:28:20.661789 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5023 12:28:20.661943 # ok 3293 Set Streaming SVE VL 4960
5024 12:28:20.662092 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5025 12:28:20.666848 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5026 12:28:20.667197 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5027 12:28:20.667295 # ok 3297 Set Streaming SVE VL 4976
5028 12:28:20.667374 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5029 12:28:20.667467 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5030 12:28:20.667545 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5031 12:28:20.667819 # ok 3301 Set Streaming SVE VL 4992
5032 12:28:20.667913 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5033 12:28:20.667990 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5034 12:28:20.668082 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5035 12:28:20.668163 # ok 3305 Set Streaming SVE VL 5008
5036 12:28:20.668250 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5037 12:28:20.668549 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5038 12:28:20.668646 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5039 12:28:20.668736 # ok 3309 Set Streaming SVE VL 5024
5040 12:28:20.668815 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5041 12:28:20.668923 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5042 12:28:20.669012 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5043 12:28:20.669283 # ok 3313 Set Streaming SVE VL 5040
5044 12:28:20.669365 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5045 12:28:20.669454 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5046 12:28:20.675496 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5047 12:28:20.675924 # ok 3317 Set Streaming SVE VL 5056
5048 12:28:20.676290 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5049 12:28:20.676403 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5050 12:28:20.676490 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5051 12:28:20.676579 # ok 3321 Set Streaming SVE VL 5072
5052 12:28:20.676664 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5053 12:28:20.676751 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5054 12:28:20.676857 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5055 12:28:20.676952 # ok 3325 Set Streaming SVE VL 5088
5056 12:28:20.677031 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5057 12:28:20.684328 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5058 12:28:20.684722 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5059 12:28:20.684928 # ok 3329 Set Streaming SVE VL 5104
5060 12:28:20.685165 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5061 12:28:20.685374 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5062 12:28:20.685563 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5063 12:28:20.685769 # ok 3333 Set Streaming SVE VL 5120
5064 12:28:20.685978 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5065 12:28:20.686175 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5066 12:28:20.686337 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5067 12:28:20.686488 # ok 3337 Set Streaming SVE VL 5136
5068 12:28:20.695096 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5069 12:28:20.695617 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5070 12:28:20.695724 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5071 12:28:20.695805 # ok 3341 Set Streaming SVE VL 5152
5072 12:28:20.695879 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5073 12:28:20.695970 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5074 12:28:20.696050 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5075 12:28:20.696144 # ok 3345 Set Streaming SVE VL 5168
5076 12:28:20.696303 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5077 12:28:20.696399 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5078 12:28:20.696501 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5079 12:28:20.696617 # ok 3349 Set Streaming SVE VL 5184
5080 12:28:20.696902 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5081 12:28:20.697051 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5082 12:28:20.697728 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5083 12:28:20.697826 # ok 3353 Set Streaming SVE VL 5200
5084 12:28:20.697902 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5085 12:28:20.697984 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5086 12:28:20.703710 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5087 12:28:20.704012 # ok 3357 Set Streaming SVE VL 5216
5088 12:28:20.704361 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5089 12:28:20.704468 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5090 12:28:20.704555 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5091 12:28:20.704632 # ok 3361 Set Streaming SVE VL 5232
5092 12:28:20.704706 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5093 12:28:20.704794 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5094 12:28:20.704868 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5095 12:28:20.704940 # ok 3365 Set Streaming SVE VL 5248
5096 12:28:20.705023 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5097 12:28:20.705108 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5098 12:28:20.705194 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5099 12:28:20.705475 # ok 3369 Set Streaming SVE VL 5264
5100 12:28:20.705570 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5101 12:28:20.705656 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5102 12:28:20.711441 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5103 12:28:20.711642 # ok 3373 Set Streaming SVE VL 5280
5104 12:28:20.712593 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5105 12:28:20.712693 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5106 12:28:20.712772 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5107 12:28:20.712850 # ok 3377 Set Streaming SVE VL 5296
5108 12:28:20.712923 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5109 12:28:20.712998 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5110 12:28:20.713069 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5111 12:28:20.713140 # ok 3381 Set Streaming SVE VL 5312
5112 12:28:20.713429 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5113 12:28:20.713523 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5114 12:28:20.713600 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5115 12:28:20.713681 # ok 3385 Set Streaming SVE VL 5328
5116 12:28:20.713753 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5117 12:28:20.713826 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5118 12:28:20.713914 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5119 12:28:20.713989 # ok 3389 Set Streaming SVE VL 5344
5120 12:28:20.714068 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5121 12:28:20.714146 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5122 12:28:20.718861 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5123 12:28:20.719153 # ok 3393 Set Streaming SVE VL 5360
5124 12:28:20.719357 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5125 12:28:20.719755 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5126 12:28:20.719916 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5127 12:28:20.720092 # ok 3397 Set Streaming SVE VL 5376
5128 12:28:20.720239 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5129 12:28:20.720385 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5130 12:28:20.720529 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5131 12:28:20.720707 # ok 3401 Set Streaming SVE VL 5392
5132 12:28:20.720844 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5133 12:28:20.720992 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5134 12:28:20.721137 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5135 12:28:20.721317 # ok 3405 Set Streaming SVE VL 5408
5136 12:28:20.721491 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5137 12:28:20.721692 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5138 12:28:20.721862 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5139 12:28:20.722046 # ok 3409 Set Streaming SVE VL 5424
5140 12:28:20.722253 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5141 12:28:20.726943 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5142 12:28:20.727366 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5143 12:28:20.727525 # ok 3413 Set Streaming SVE VL 5440
5144 12:28:20.727718 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5145 12:28:20.727888 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5146 12:28:20.728049 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5147 12:28:20.728177 # ok 3417 Set Streaming SVE VL 5456
5148 12:28:20.728362 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5149 12:28:20.728556 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5150 12:28:20.728740 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5151 12:28:20.728890 # ok 3421 Set Streaming SVE VL 5472
5152 12:28:20.729038 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5153 12:28:20.729215 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5154 12:28:20.729367 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5155 12:28:20.729512 # ok 3425 Set Streaming SVE VL 5488
5156 12:28:20.729696 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5157 12:28:20.729851 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5158 12:28:20.729998 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5159 12:28:20.732377 # ok 3429 Set Streaming SVE VL 5504
5160 12:28:20.732662 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5161 12:28:20.733067 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5162 12:28:20.733252 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5163 12:28:20.733431 # ok 3433 Set Streaming SVE VL 5520
5164 12:28:20.733581 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5165 12:28:20.733744 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5166 12:28:20.733891 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5167 12:28:20.734041 # ok 3437 Set Streaming SVE VL 5536
5168 12:28:20.737057 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5169 12:28:20.737557 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5170 12:28:20.737679 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5171 12:28:20.737750 # ok 3441 Set Streaming SVE VL 5552
5172 12:28:20.742955 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5173 12:28:20.743201 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5174 12:28:20.743565 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5175 12:28:20.743674 # ok 3445 Set Streaming SVE VL 5568
5176 12:28:20.743769 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5177 12:28:20.743862 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5178 12:28:20.743969 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5179 12:28:20.744070 # ok 3449 Set Streaming SVE VL 5584
5180 12:28:20.744161 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5181 12:28:20.744276 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5182 12:28:20.744563 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5183 12:28:20.744675 # ok 3453 Set Streaming SVE VL 5600
5184 12:28:20.744776 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5185 12:28:20.744877 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5186 12:28:20.745225 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5187 12:28:20.745335 # ok 3457 Set Streaming SVE VL 5616
5188 12:28:20.745426 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5189 12:28:20.745516 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5190 12:28:20.745609 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5191 12:28:20.745708 # ok 3461 Set Streaming SVE VL 5632
5192 12:28:20.745992 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5193 12:28:20.746094 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5194 12:28:20.750773 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5195 12:28:20.751043 # ok 3465 Set Streaming SVE VL 5648
5196 12:28:20.753853 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5197 12:28:20.754079 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5198 12:28:20.754159 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5199 12:28:20.754238 # ok 3469 Set Streaming SVE VL 5664
5200 12:28:20.754316 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5201 12:28:20.754395 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5202 12:28:20.754472 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5203 12:28:20.754550 # ok 3473 Set Streaming SVE VL 5680
5204 12:28:20.754628 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5205 12:28:20.754705 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5206 12:28:20.754782 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5207 12:28:20.754859 # ok 3477 Set Streaming SVE VL 5696
5208 12:28:20.754937 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5209 12:28:20.755016 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5210 12:28:20.755094 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5211 12:28:20.760758 # ok 3481 Set Streaming SVE VL 5712
5212 12:28:20.761219 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5213 12:28:20.761309 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5214 12:28:20.761409 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5215 12:28:20.761500 # ok 3485 Set Streaming SVE VL 5728
5216 12:28:20.761596 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5217 12:28:20.761675 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5218 12:28:20.762126 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5219 12:28:20.762376 # ok 3489 Set Streaming SVE VL 5744
5220 12:28:20.762446 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5221 12:28:20.762537 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5222 12:28:20.762799 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5223 12:28:20.762883 # ok 3493 Set Streaming SVE VL 5760
5224 12:28:20.762956 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5225 12:28:20.763234 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5226 12:28:20.763305 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5227 12:28:20.763397 # ok 3497 Set Streaming SVE VL 5776
5228 12:28:20.763663 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5229 12:28:20.763747 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5230 12:28:20.763844 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5231 12:28:20.763937 # ok 3501 Set Streaming SVE VL 5792
5232 12:28:20.764207 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5233 12:28:20.764496 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5234 12:28:20.764589 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5235 12:28:20.764679 # ok 3505 Set Streaming SVE VL 5808
5236 12:28:20.764944 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5237 12:28:20.765030 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5238 12:28:20.765285 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5239 12:28:20.765356 # ok 3509 Set Streaming SVE VL 5824
5240 12:28:20.765445 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5241 12:28:20.773160 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5242 12:28:20.773671 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5243 12:28:20.773835 # ok 3513 Set Streaming SVE VL 5840
5244 12:28:20.774007 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5245 12:28:20.774406 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5246 12:28:20.774601 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5247 12:28:20.774848 # ok 3517 Set Streaming SVE VL 5856
5248 12:28:20.775030 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5249 12:28:20.775231 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5250 12:28:20.775444 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5251 12:28:20.775667 # ok 3521 Set Streaming SVE VL 5872
5252 12:28:20.775864 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5253 12:28:20.776074 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5254 12:28:20.776282 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5255 12:28:20.776453 # ok 3525 Set Streaming SVE VL 5888
5256 12:28:20.776615 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5257 12:28:20.776822 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5258 12:28:20.777035 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5259 12:28:20.777203 # ok 3529 Set Streaming SVE VL 5904
5260 12:28:20.777370 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5261 12:28:20.777509 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5262 12:28:20.777627 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5263 12:28:20.777876 # ok 3533 Set Streaming SVE VL 5920
5264 12:28:20.778084 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5265 12:28:20.778280 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5266 12:28:20.778432 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5267 12:28:20.778576 # ok 3537 Set Streaming SVE VL 5936
5268 12:28:20.778760 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5269 12:28:20.778895 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5270 12:28:20.779037 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5271 12:28:20.779179 # ok 3541 Set Streaming SVE VL 5952
5272 12:28:20.779320 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5273 12:28:20.790628 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5274 12:28:20.791162 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5275 12:28:20.791276 # ok 3545 Set Streaming SVE VL 5968
5276 12:28:20.791367 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5277 12:28:20.791454 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5278 12:28:20.791557 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5279 12:28:20.791646 # ok 3549 Set Streaming SVE VL 5984
5280 12:28:20.791731 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5281 12:28:20.792027 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5282 12:28:20.792174 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5283 12:28:20.792364 # ok 3553 Set Streaming SVE VL 6000
5284 12:28:20.792551 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5285 12:28:20.792643 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5286 12:28:20.792719 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5287 12:28:20.792793 # ok 3557 Set Streaming SVE VL 6016
5288 12:28:20.792866 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5289 12:28:20.792954 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5290 12:28:20.793030 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5291 12:28:20.793118 # ok 3561 Set Streaming SVE VL 6032
5292 12:28:20.793192 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5293 12:28:20.793263 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5294 12:28:20.793335 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5295 12:28:20.793406 # ok 3565 Set Streaming SVE VL 6048
5296 12:28:20.793491 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5297 12:28:20.793566 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5298 12:28:20.793878 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5299 12:28:20.794046 # ok 3569 Set Streaming SVE VL 6064
5300 12:28:20.794207 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5301 12:28:20.800497 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5302 12:28:20.800857 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5303 12:28:20.801311 # ok 3573 Set Streaming SVE VL 6080
5304 12:28:20.801510 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5305 12:28:20.801707 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5306 12:28:20.801866 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5307 12:28:20.801994 # ok 3577 Set Streaming SVE VL 6096
5308 12:28:20.802112 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5309 12:28:20.802229 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5310 12:28:20.802377 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5311 12:28:20.802499 # ok 3581 Set Streaming SVE VL 6112
5312 12:28:20.810767 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5313 12:28:20.811395 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5314 12:28:20.811503 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5315 12:28:20.811596 # ok 3585 Set Streaming SVE VL 6128
5316 12:28:20.811682 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5317 12:28:20.811767 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5318 12:28:20.811871 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5319 12:28:20.811958 # ok 3589 Set Streaming SVE VL 6144
5320 12:28:20.812057 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5321 12:28:20.812418 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5322 12:28:20.812757 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5323 12:28:20.812945 # ok 3593 Set Streaming SVE VL 6160
5324 12:28:20.813122 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5325 12:28:20.813300 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5326 12:28:20.813466 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5327 12:28:20.813615 # ok 3597 Set Streaming SVE VL 6176
5328 12:28:20.813821 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5329 12:28:20.814010 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5330 12:28:20.814154 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5331 12:28:20.814336 # ok 3601 Set Streaming SVE VL 6192
5332 12:28:20.814472 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5333 12:28:20.821711 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5334 12:28:20.822787 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5335 12:28:20.822990 # ok 3605 Set Streaming SVE VL 6208
5336 12:28:20.823196 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5337 12:28:20.823360 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5338 12:28:20.823506 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5339 12:28:20.823646 # ok 3609 Set Streaming SVE VL 6224
5340 12:28:20.823787 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5341 12:28:20.823906 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5342 12:28:20.824591 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5343 12:28:20.824846 # ok 3613 Set Streaming SVE VL 6240
5344 12:28:20.825066 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5345 12:28:20.825229 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5346 12:28:20.825373 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5347 12:28:20.825520 # ok 3617 Set Streaming SVE VL 6256
5348 12:28:20.825678 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5349 12:28:20.825826 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5350 12:28:20.825971 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5351 12:28:20.826113 # ok 3621 Set Streaming SVE VL 6272
5352 12:28:20.826258 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5353 12:28:20.826620 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5354 12:28:20.826759 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5355 12:28:20.826907 # ok 3625 Set Streaming SVE VL 6288
5356 12:28:20.835741 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5357 12:28:20.836084 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5358 12:28:20.836374 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5359 12:28:20.836609 # ok 3629 Set Streaming SVE VL 6304
5360 12:28:20.836830 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5361 12:28:20.836997 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5362 12:28:20.837163 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5363 12:28:20.837362 # ok 3633 Set Streaming SVE VL 6320
5364 12:28:20.837567 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5365 12:28:20.837774 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5366 12:28:20.837972 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5367 12:28:20.838118 # ok 3637 Set Streaming SVE VL 6336
5368 12:28:20.838261 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5369 12:28:20.838443 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5370 12:28:20.838580 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5371 12:28:20.838724 # ok 3641 Set Streaming SVE VL 6352
5372 12:28:20.838867 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5373 12:28:20.839011 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5374 12:28:20.846988 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5375 12:28:20.847191 # ok 3645 Set Streaming SVE VL 6368
5376 12:28:20.847541 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5377 12:28:20.847746 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5378 12:28:20.847927 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5379 12:28:20.848094 # ok 3649 Set Streaming SVE VL 6384
5380 12:28:20.848308 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5381 12:28:20.848467 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5382 12:28:20.848668 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5383 12:28:20.848892 # ok 3653 Set Streaming SVE VL 6400
5384 12:28:20.849118 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5385 12:28:20.849313 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5386 12:28:20.849539 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5387 12:28:20.849719 # ok 3657 Set Streaming SVE VL 6416
5388 12:28:20.849924 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5389 12:28:20.850110 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5390 12:28:20.850262 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5391 12:28:20.850406 # ok 3661 Set Streaming SVE VL 6432
5392 12:28:20.850547 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5393 12:28:20.850726 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5394 12:28:20.858766 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5395 12:28:20.859306 # ok 3665 Set Streaming SVE VL 6448
5396 12:28:20.859507 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5397 12:28:20.859736 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5398 12:28:20.860069 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5399 12:28:20.860279 # ok 3669 Set Streaming SVE VL 6464
5400 12:28:20.860479 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5401 12:28:20.860693 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5402 12:28:20.860832 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5403 12:28:20.860979 # ok 3673 Set Streaming SVE VL 6480
5404 12:28:20.861122 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5405 12:28:20.861266 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5406 12:28:20.861408 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5407 12:28:20.861551 # ok 3677 Set Streaming SVE VL 6496
5408 12:28:20.861706 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5409 12:28:20.861851 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5410 12:28:20.861994 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5411 12:28:20.862136 # ok 3681 Set Streaming SVE VL 6512
5412 12:28:20.862316 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5413 12:28:20.862452 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5414 12:28:20.862595 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5415 12:28:20.862737 # ok 3685 Set Streaming SVE VL 6528
5416 12:28:20.862879 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5417 12:28:20.863021 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5418 12:28:20.882717 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5419 12:28:20.883565 # ok 3689 Set Streaming SVE VL 6544
5420 12:28:20.883832 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5421 12:28:20.884032 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5422 12:28:20.884253 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5423 12:28:20.884480 # ok 3693 Set Streaming SVE VL 6560
5424 12:28:20.884681 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5425 12:28:20.884856 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5426 12:28:20.884995 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5427 12:28:20.885113 # ok 3697 Set Streaming SVE VL 6576
5428 12:28:20.885254 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5429 12:28:20.885377 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5430 12:28:20.891072 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5431 12:28:20.891458 # ok 3701 Set Streaming SVE VL 6592
5432 12:28:20.891568 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5433 12:28:20.891679 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5434 12:28:20.891772 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5435 12:28:20.892063 # ok 3705 Set Streaming SVE VL 6608
5436 12:28:20.892245 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5437 12:28:20.892391 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5438 12:28:20.892488 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5439 12:28:20.892592 # ok 3709 Set Streaming SVE VL 6624
5440 12:28:20.892702 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5441 12:28:20.892798 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5442 12:28:20.892886 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5443 12:28:20.892974 # ok 3713 Set Streaming SVE VL 6640
5444 12:28:20.893059 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5445 12:28:20.893364 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5446 12:28:20.893471 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5447 12:28:20.893562 # ok 3717 Set Streaming SVE VL 6656
5448 12:28:20.893659 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5449 12:28:20.893749 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5450 12:28:20.893856 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5451 12:28:20.893949 # ok 3721 Set Streaming SVE VL 6672
5452 12:28:20.903259 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5453 12:28:20.904036 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5454 12:28:20.904242 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5455 12:28:20.904347 # ok 3725 Set Streaming SVE VL 6688
5456 12:28:20.904454 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5457 12:28:20.904544 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5458 12:28:20.904650 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5459 12:28:20.905262 # ok 3729 Set Streaming SVE VL 6704
5460 12:28:20.905383 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5461 12:28:20.905473 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5462 12:28:20.905560 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5463 12:28:20.905861 # ok 3733 Set Streaming SVE VL 6720
5464 12:28:20.905967 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5465 12:28:20.906060 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5466 12:28:20.914755 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5467 12:28:20.915584 # ok 3737 Set Streaming SVE VL 6736
5468 12:28:20.916349 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5469 12:28:20.916722 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5470 12:28:20.917062 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5471 12:28:20.917261 # ok 3741 Set Streaming SVE VL 6752
5472 12:28:20.917428 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5473 12:28:20.917564 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5474 12:28:20.917766 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5475 12:28:20.917939 # ok 3745 Set Streaming SVE VL 6768
5476 12:28:20.918084 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5477 12:28:20.918508 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5478 12:28:20.918678 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5479 12:28:20.918929 # ok 3749 Set Streaming SVE VL 6784
5480 12:28:20.919073 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5481 12:28:20.919214 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5482 12:28:20.919673 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5483 12:28:20.919873 # ok 3753 Set Streaming SVE VL 6800
5484 12:28:20.920070 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5485 12:28:20.920257 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5486 12:28:20.920446 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5487 12:28:20.920658 # ok 3757 Set Streaming SVE VL 6816
5488 12:28:20.920866 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5489 12:28:20.921060 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5490 12:28:20.921261 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5491 12:28:20.921500 # ok 3761 Set Streaming SVE VL 6832
5492 12:28:20.921703 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5493 12:28:20.921854 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5494 12:28:20.921973 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5495 12:28:20.922091 # ok 3765 Set Streaming SVE VL 6848
5496 12:28:20.926315 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5497 12:28:20.926977 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5498 12:28:20.927180 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5499 12:28:20.927404 # ok 3769 Set Streaming SVE VL 6864
5500 12:28:20.927579 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5501 12:28:20.927775 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5502 12:28:20.927905 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5503 12:28:20.928023 # ok 3773 Set Streaming SVE VL 6880
5504 12:28:20.928139 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5505 12:28:20.950452 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5506 12:28:20.951111 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5507 12:28:20.951368 # ok 3777 Set Streaming SVE VL 6896
5508 12:28:20.951635 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5509 12:28:20.951872 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5510 12:28:20.952125 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5511 12:28:20.952333 # ok 3781 Set Streaming SVE VL 6912
5512 12:28:20.952601 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5513 12:28:20.952800 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5514 12:28:20.953011 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5515 12:28:20.953232 # ok 3785 Set Streaming SVE VL 6928
5516 12:28:20.953460 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5517 12:28:20.953665 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5518 12:28:20.953878 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5519 12:28:20.954040 # ok 3789 Set Streaming SVE VL 6944
5520 12:28:20.954184 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5521 12:28:20.954338 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5522 12:28:20.954485 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5523 12:28:20.954627 # ok 3793 Set Streaming SVE VL 6960
5524 12:28:20.954812 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5525 12:28:20.954946 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5526 12:28:20.955097 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5527 12:28:20.955241 # ok 3797 Set Streaming SVE VL 6976
5528 12:28:20.955389 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5529 12:28:20.955535 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5530 12:28:20.958133 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5531 12:28:20.958479 # ok 3801 Set Streaming SVE VL 6992
5532 12:28:20.958583 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5533 12:28:20.958675 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5534 12:28:20.958790 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5535 12:28:20.958894 # ok 3805 Set Streaming SVE VL 7008
5536 12:28:20.959019 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5537 12:28:20.959117 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5538 12:28:20.959225 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5539 12:28:20.959332 # ok 3809 Set Streaming SVE VL 7024
5540 12:28:20.959639 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5541 12:28:20.959760 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5542 12:28:20.959862 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5543 12:28:20.960387 # ok 3813 Set Streaming SVE VL 7040
5544 12:28:20.960730 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5545 12:28:20.961117 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5546 12:28:20.961510 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5547 12:28:20.961715 # ok 3817 Set Streaming SVE VL 7056
5548 12:28:20.961861 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5549 12:28:20.961984 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5550 12:28:20.962100 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5551 12:28:20.962214 # ok 3821 Set Streaming SVE VL 7072
5552 12:28:20.962331 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5553 12:28:20.962449 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5554 12:28:20.962562 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5555 12:28:20.962681 # ok 3825 Set Streaming SVE VL 7088
5556 12:28:20.962794 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5557 12:28:20.962909 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5558 12:28:20.965471 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5559 12:28:20.965724 # ok 3829 Set Streaming SVE VL 7104
5560 12:28:20.966904 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5561 12:28:20.967486 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5562 12:28:20.967719 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5563 12:28:20.967953 # ok 3833 Set Streaming SVE VL 7120
5564 12:28:20.968190 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5565 12:28:20.968436 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5566 12:28:20.968653 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5567 12:28:20.968878 # ok 3837 Set Streaming SVE VL 7136
5568 12:28:20.969066 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5569 12:28:20.969271 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5570 12:28:20.969486 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5571 12:28:20.969722 # ok 3841 Set Streaming SVE VL 7152
5572 12:28:20.969929 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5573 12:28:20.970135 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5574 12:28:20.970271 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5575 12:28:20.970415 # ok 3845 Set Streaming SVE VL 7168
5576 12:28:20.970560 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5577 12:28:20.970701 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5578 12:28:20.970844 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5579 12:28:20.970986 # ok 3849 Set Streaming SVE VL 7184
5580 12:28:20.971127 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5581 12:28:20.978092 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5582 12:28:20.978323 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5583 12:28:20.978631 # ok 3853 Set Streaming SVE VL 7200
5584 12:28:20.978744 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5585 12:28:20.978839 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5586 12:28:20.978928 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5587 12:28:20.979032 # ok 3857 Set Streaming SVE VL 7216
5588 12:28:20.979121 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5589 12:28:20.979219 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5590 12:28:20.979480 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5591 12:28:20.979586 # ok 3861 Set Streaming SVE VL 7232
5592 12:28:20.979675 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5593 12:28:20.979778 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5594 12:28:20.979866 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5595 12:28:20.979968 # ok 3865 Set Streaming SVE VL 7248
5596 12:28:20.980093 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5597 12:28:20.980196 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5598 12:28:20.980281 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5599 12:28:20.980377 # ok 3869 Set Streaming SVE VL 7264
5600 12:28:20.980476 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5601 12:28:20.980578 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5602 12:28:20.980885 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5603 12:28:20.980993 # ok 3873 Set Streaming SVE VL 7280
5604 12:28:20.981084 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5605 12:28:20.981584 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5606 12:28:20.981686 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5607 12:28:20.981767 # ok 3877 Set Streaming SVE VL 7296
5608 12:28:20.983391 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5609 12:28:20.983776 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5610 12:28:20.984028 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5611 12:28:20.984130 # ok 3881 Set Streaming SVE VL 7312
5612 12:28:20.984216 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5613 12:28:20.984320 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5614 12:28:20.984408 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5615 12:28:20.984494 # ok 3885 Set Streaming SVE VL 7328
5616 12:28:20.984594 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5617 12:28:20.984681 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5618 12:28:20.984777 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5619 12:28:20.985026 # ok 3889 Set Streaming SVE VL 7344
5620 12:28:20.985122 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5621 12:28:20.985212 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5622 12:28:20.985302 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5623 12:28:20.985381 # ok 3893 Set Streaming SVE VL 7360
5624 12:28:20.985472 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5625 12:28:20.996118 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5626 12:28:20.996603 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5627 12:28:20.997144 # ok 3897 Set Streaming SVE VL 7376
5628 12:28:20.997689 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5629 12:28:20.997914 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5630 12:28:20.998085 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5631 12:28:20.998248 # ok 3901 Set Streaming SVE VL 7392
5632 12:28:20.998388 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5633 12:28:20.998543 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5634 12:28:20.998709 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5635 12:28:20.998921 # ok 3905 Set Streaming SVE VL 7408
5636 12:28:20.999092 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5637 12:28:20.999259 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5638 12:28:21.013427 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5639 12:28:21.013983 # ok 3909 Set Streaming SVE VL 7424
5640 12:28:21.015677 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5641 12:28:21.016115 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5642 12:28:21.016346 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5643 12:28:21.016599 # ok 3913 Set Streaming SVE VL 7440
5644 12:28:21.016806 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5645 12:28:21.017552 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5646 12:28:21.017742 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5647 12:28:21.017874 # ok 3917 Set Streaming SVE VL 7456
5648 12:28:21.017991 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5649 12:28:21.018105 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5650 12:28:21.018220 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5651 12:28:21.018353 # ok 3921 Set Streaming SVE VL 7472
5652 12:28:21.018521 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5653 12:28:21.018661 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5654 12:28:21.029140 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5655 12:28:21.032040 # ok 3925 Set Streaming SVE VL 7488
5656 12:28:21.032362 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5657 12:28:21.032787 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5658 12:28:21.032980 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5659 12:28:21.033142 # ok 3929 Set Streaming SVE VL 7504
5660 12:28:21.033299 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5661 12:28:21.033458 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5662 12:28:21.033619 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5663 12:28:21.033796 # ok 3933 Set Streaming SVE VL 7520
5664 12:28:21.033917 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5665 12:28:21.034031 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5666 12:28:21.034144 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5667 12:28:21.034255 # ok 3937 Set Streaming SVE VL 7536
5668 12:28:21.034366 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5669 12:28:21.043064 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5670 12:28:21.043385 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5671 12:28:21.043556 # ok 3941 Set Streaming SVE VL 7552
5672 12:28:21.043715 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5673 12:28:21.043875 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5674 12:28:21.044393 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5675 12:28:21.044592 # ok 3945 Set Streaming SVE VL 7568
5676 12:28:21.044789 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5677 12:28:21.045004 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5678 12:28:21.045212 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5679 12:28:21.045414 # ok 3949 Set Streaming SVE VL 7584
5680 12:28:21.045619 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5681 12:28:21.045771 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5682 12:28:21.045886 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5683 12:28:21.045999 # ok 3953 Set Streaming SVE VL 7600
5684 12:28:21.046110 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5685 12:28:21.046221 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5686 12:28:21.046386 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5687 12:28:21.046505 # ok 3957 Set Streaming SVE VL 7616
5688 12:28:21.046617 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5689 12:28:21.046728 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5690 12:28:21.046839 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5691 12:28:21.046950 # ok 3961 Set Streaming SVE VL 7632
5692 12:28:21.047061 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5693 12:28:21.047172 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5694 12:28:21.047315 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5695 12:28:21.047503 # ok 3965 Set Streaming SVE VL 7648
5696 12:28:21.047680 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5697 12:28:21.047872 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5698 12:28:21.050464 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5699 12:28:21.051017 # ok 3969 Set Streaming SVE VL 7664
5700 12:28:21.051689 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5701 12:28:21.051896 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5702 12:28:21.052068 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5703 12:28:21.052236 # ok 3973 Set Streaming SVE VL 7680
5704 12:28:21.052407 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5705 12:28:21.052574 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5706 12:28:21.052741 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5707 12:28:21.052908 # ok 3977 Set Streaming SVE VL 7696
5708 12:28:21.053119 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5709 12:28:21.053284 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5710 12:28:21.053447 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5711 12:28:21.053590 # ok 3981 Set Streaming SVE VL 7712
5712 12:28:21.053727 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5713 12:28:21.053843 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5714 12:28:21.053956 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5715 12:28:21.054068 # ok 3985 Set Streaming SVE VL 7728
5716 12:28:21.054179 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5717 12:28:21.054291 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5718 12:28:21.054403 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5719 12:28:21.054554 # ok 3989 Set Streaming SVE VL 7744
5720 12:28:21.054672 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5721 12:28:21.054784 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5722 12:28:21.054895 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5723 12:28:21.058429 # ok 3993 Set Streaming SVE VL 7760
5724 12:28:21.058990 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5725 12:28:21.059154 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5726 12:28:21.059274 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5727 12:28:21.059410 # ok 3997 Set Streaming SVE VL 7776
5728 12:28:21.059561 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5729 12:28:21.059724 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5730 12:28:21.059909 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5731 12:28:21.060051 # ok 4001 Set Streaming SVE VL 7792
5732 12:28:21.060243 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5733 12:28:21.060550 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5734 12:28:21.060721 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5735 12:28:21.060850 # ok 4005 Set Streaming SVE VL 7808
5736 12:28:21.060960 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5737 12:28:21.061074 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5738 12:28:21.061201 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5739 12:28:21.061320 # ok 4009 Set Streaming SVE VL 7824
5740 12:28:21.061550 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5741 12:28:21.061663 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5742 12:28:21.061745 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5743 12:28:21.061831 # ok 4013 Set Streaming SVE VL 7840
5744 12:28:21.061911 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5745 12:28:21.061992 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5746 12:28:21.066251 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5747 12:28:21.066554 # ok 4017 Set Streaming SVE VL 7856
5748 12:28:21.066699 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5749 12:28:21.066834 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5750 12:28:21.067187 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5751 12:28:21.067336 # ok 4021 Set Streaming SVE VL 7872
5752 12:28:21.067427 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5753 12:28:21.067553 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5754 12:28:21.067659 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5755 12:28:21.067766 # ok 4025 Set Streaming SVE VL 7888
5756 12:28:21.067855 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5757 12:28:21.067941 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5758 12:28:21.068025 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5759 12:28:21.068103 # ok 4029 Set Streaming SVE VL 7904
5760 12:28:21.068211 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5761 12:28:21.068347 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5762 12:28:21.068437 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5763 12:28:21.068522 # ok 4033 Set Streaming SVE VL 7920
5764 12:28:21.068606 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5765 12:28:21.068712 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5766 12:28:21.068794 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5767 12:28:21.068872 # ok 4037 Set Streaming SVE VL 7936
5768 12:28:21.068945 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5769 12:28:21.069018 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5770 12:28:21.069108 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5771 12:28:21.069184 # ok 4041 Set Streaming SVE VL 7952
5772 12:28:21.069258 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5773 12:28:21.069346 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5774 12:28:21.069423 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5775 12:28:21.069497 # ok 4045 Set Streaming SVE VL 7968
5776 12:28:21.069582 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5777 12:28:21.074013 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5778 12:28:21.074488 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5779 12:28:21.074642 # ok 4049 Set Streaming SVE VL 7984
5780 12:28:21.074770 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5781 12:28:21.074908 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5782 12:28:21.075095 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5783 12:28:21.075223 # ok 4053 Set Streaming SVE VL 8000
5784 12:28:21.075355 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5785 12:28:21.075498 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5786 12:28:21.075626 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5787 12:28:21.075727 # ok 4057 Set Streaming SVE VL 8016
5788 12:28:21.075808 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5789 12:28:21.075915 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5790 12:28:21.076051 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5791 12:28:21.076140 # ok 4061 Set Streaming SVE VL 8032
5792 12:28:21.076241 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5793 12:28:21.076629 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5794 12:28:21.077302 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5795 12:28:21.077393 # ok 4065 Set Streaming SVE VL 8048
5796 12:28:21.077471 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5797 12:28:21.077547 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5798 12:28:21.077660 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5799 12:28:21.077747 # ok 4069 Set Streaming SVE VL 8064
5800 12:28:21.077825 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5801 12:28:21.077904 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5802 12:28:21.077983 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5803 12:28:21.078061 # ok 4073 Set Streaming SVE VL 8080
5804 12:28:21.078141 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5805 12:28:21.082990 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5806 12:28:21.083220 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5807 12:28:21.083529 # ok 4077 Set Streaming SVE VL 8096
5808 12:28:21.083680 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5809 12:28:21.083826 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5810 12:28:21.083979 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5811 12:28:21.084146 # ok 4081 Set Streaming SVE VL 8112
5812 12:28:21.084298 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5813 12:28:21.084448 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5814 12:28:21.084596 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5815 12:28:21.084693 # ok 4085 Set Streaming SVE VL 8128
5816 12:28:21.084785 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5817 12:28:21.084894 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5818 12:28:21.084975 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5819 12:28:21.085049 # ok 4089 Set Streaming SVE VL 8144
5820 12:28:21.085329 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5821 12:28:21.085425 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5822 12:28:21.085519 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5823 12:28:21.085601 # ok 4093 Set Streaming SVE VL 8160
5824 12:28:21.088163 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5825 12:28:21.088657 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5826 12:28:21.088761 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5827 12:28:21.088845 # ok 4097 Set Streaming SVE VL 8176
5828 12:28:21.089060 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5829 12:28:21.089257 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5830 12:28:21.089490 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5831 12:28:21.089569 # ok 4101 Set Streaming SVE VL 8192
5832 12:28:21.089661 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5833 12:28:21.089745 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5834 12:28:21.089828 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5835 12:28:21.089926 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5836 12:28:21.090004 ok 30 selftests: arm64: sve-ptrace
5837 12:28:21.090079 # selftests: arm64: sve-probe-vls
5838 12:28:21.090156 # TAP version 13
5839 12:28:21.090233 # 1..2
5840 12:28:21.090310 # ok 1 Enumerated 16 vector lengths
5841 12:28:21.090407 # ok 2 All vector lengths valid
5842 12:28:21.090490 # # 16
5843 12:28:21.090569 # # 32
5844 12:28:21.090651 # # 48
5845 12:28:21.090731 # # 64
5846 12:28:21.090810 # # 80
5847 12:28:21.090889 # # 96
5848 12:28:21.090965 # # 112
5849 12:28:21.091048 # # 128
5850 12:28:21.091127 # # 144
5851 12:28:21.091205 # # 160
5852 12:28:21.091288 # # 176
5853 12:28:21.091374 # # 192
5854 12:28:21.091475 # # 208
5855 12:28:21.091558 # # 224
5856 12:28:21.091638 # # 240
5857 12:28:21.091713 # # 256
5858 12:28:21.091788 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5859 12:28:21.091873 ok 31 selftests: arm64: sve-probe-vls
5860 12:28:21.227879 # selftests: arm64: vec-syscfg
5861 12:28:22.004092 # TAP version 13
5862 12:28:22.004636 # 1..20
5863 12:28:22.004794 # ok 1 SVE default vector length 64
5864 12:28:22.004930 # ok 2 SVE minimum vector length 16
5865 12:28:22.005067 # ok 3 SVE maximum vector length 256
5866 12:28:22.005204 # ok 4 SVE current VL is 64
5867 12:28:22.005371 # ok 5 SVE set VL 64 and have VL 64
5868 12:28:22.005519 # ok 6 SVE prctl() set min/max
5869 12:28:22.005632 # ok 7 SVE vector length used default
5870 12:28:22.005735 # ok 8 SVE vector length was inherited
5871 12:28:22.005827 # ok 9 SVE vector length set on exec
5872 12:28:22.005913 # ok 10 SVE prctl() set all VLs, 0 errors
5873 12:28:22.006000 # ok 11 SME default vector length 32
5874 12:28:22.006087 # ok 12 SME minimum vector length 16
5875 12:28:22.011682 # ok 13 SME maximum vector length 256
5876 12:28:22.011974 # ok 14 SME current VL is 32
5877 12:28:22.012344 # ok 15 SME set VL 32 and have VL 32
5878 12:28:22.012479 # ok 16 SME prctl() set min/max
5879 12:28:22.012621 # ok 17 SME vector length used default
5880 12:28:22.012728 # ok 18 SME vector length was inherited
5881 12:28:22.012839 # ok 19 SME vector length set on exec
5882 12:28:22.012931 # ok 20 SME prctl() set all VLs, 0 errors
5883 12:28:22.013020 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5884 12:28:22.031654 ok 32 selftests: arm64: vec-syscfg
5885 12:28:22.148207 # selftests: arm64: za-fork
5886 12:28:22.598596 # TAP version 13
5887 12:28:22.599175 # 1..1
5888 12:28:22.599339 # # PID: 1018
5889 12:28:22.599507 # ok 1 fork_test
5890 12:28:22.599634 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5891 12:28:22.619185 ok 33 selftests: arm64: za-fork
5892 12:28:22.732786 # selftests: arm64: za-ptrace
5893 12:28:22.869477 # TAP version 13
5894 12:28:22.869854 # 1..1536
5895 12:28:22.871115 # # Parent is 1036, child is 1037
5896 12:28:22.871308 # ok 1 Set VL 16
5897 12:28:22.871476 # ok 2 Disabled ZA for VL 16
5898 12:28:22.871734 # ok 3 Data match for VL 16
5899 12:28:22.871918 # ok 4 Set VL 32
5900 12:28:22.872083 # ok 5 Disabled ZA for VL 32
5901 12:28:22.872225 # ok 6 Data match for VL 32
5902 12:28:22.872364 # ok 7 Set VL 48
5903 12:28:22.872538 # ok 8 # SKIP Disabled ZA for VL 48
5904 12:28:22.872686 # ok 9 # SKIP Get and set data for VL 48
5905 12:28:22.872830 # ok 10 Set VL 64
5906 12:28:22.872973 # ok 11 Disabled ZA for VL 64
5907 12:28:22.873138 # ok 12 Data match for VL 64
5908 12:28:22.873313 # ok 13 Set VL 80
5909 12:28:22.873505 # ok 14 # SKIP Disabled ZA for VL 80
5910 12:28:22.873641 # ok 15 # SKIP Get and set data for VL 80
5911 12:28:22.873802 # ok 16 Set VL 96
5912 12:28:22.873946 # ok 17 # SKIP Disabled ZA for VL 96
5913 12:28:22.874094 # ok 18 # SKIP Get and set data for VL 96
5914 12:28:22.874236 # ok 19 Set VL 112
5915 12:28:22.874377 # ok 20 # SKIP Disabled ZA for VL 112
5916 12:28:22.874519 # ok 21 # SKIP Get and set data for VL 112
5917 12:28:22.874660 # ok 22 Set VL 128
5918 12:28:22.874802 # ok 23 Disabled ZA for VL 128
5919 12:28:22.874944 # ok 24 Data match for VL 128
5920 12:28:22.875088 # ok 25 Set VL 144
5921 12:28:22.875230 # ok 26 # SKIP Disabled ZA for VL 144
5922 12:28:22.875372 # ok 27 # SKIP Get and set data for VL 144
5923 12:28:22.875514 # ok 28 Set VL 160
5924 12:28:22.879085 # ok 29 # SKIP Disabled ZA for VL 160
5925 12:28:22.879304 # ok 30 # SKIP Get and set data for VL 160
5926 12:28:22.879492 # ok 31 Set VL 176
5927 12:28:22.879671 # ok 32 # SKIP Disabled ZA for VL 176
5928 12:28:22.880163 # ok 33 # SKIP Get and set data for VL 176
5929 12:28:22.880326 # ok 34 Set VL 192
5930 12:28:22.880489 # ok 35 # SKIP Disabled ZA for VL 192
5931 12:28:22.880576 # ok 36 # SKIP Get and set data for VL 192
5932 12:28:22.880653 # ok 37 Set VL 208
5933 12:28:22.880723 # ok 38 # SKIP Disabled ZA for VL 208
5934 12:28:22.880818 # ok 39 # SKIP Get and set data for VL 208
5935 12:28:22.880906 # ok 40 Set VL 224
5936 12:28:22.880973 # ok 41 # SKIP Disabled ZA for VL 224
5937 12:28:22.881038 # ok 42 # SKIP Get and set data for VL 224
5938 12:28:22.881103 # ok 43 Set VL 240
5939 12:28:22.881202 # ok 44 # SKIP Disabled ZA for VL 240
5940 12:28:22.881298 # ok 45 # SKIP Get and set data for VL 240
5941 12:28:22.881372 # ok 46 Set VL 256
5942 12:28:22.881433 # ok 47 Disabled ZA for VL 256
5943 12:28:22.881500 # ok 48 Data match for VL 256
5944 12:28:22.881597 # ok 49 Set VL 272
5945 12:28:22.881695 # ok 50 # SKIP Disabled ZA for VL 272
5946 12:28:22.881798 # ok 51 # SKIP Get and set data for VL 272
5947 12:28:22.881892 # ok 52 Set VL 288
5948 12:28:22.881989 # ok 53 # SKIP Disabled ZA for VL 288
5949 12:28:22.882071 # ok 54 # SKIP Get and set data for VL 288
5950 12:28:22.882145 # ok 55 Set VL 304
5951 12:28:22.882240 # ok 56 # SKIP Disabled ZA for VL 304
5952 12:28:22.885258 # ok 57 # SKIP Get and set data for VL 304
5953 12:28:22.885429 # ok 58 Set VL 320
5954 12:28:22.885911 # ok 59 # SKIP Disabled ZA for VL 320
5955 12:28:22.886012 # ok 60 # SKIP Get and set data for VL 320
5956 12:28:22.886137 # ok 61 Set VL 336
5957 12:28:22.886222 # ok 62 # SKIP Disabled ZA for VL 336
5958 12:28:22.886300 # ok 63 # SKIP Get and set data for VL 336
5959 12:28:22.886391 # ok 64 Set VL 352
5960 12:28:22.886487 # ok 65 # SKIP Disabled ZA for VL 352
5961 12:28:22.886571 # ok 66 # SKIP Get and set data for VL 352
5962 12:28:22.886658 # ok 67 Set VL 368
5963 12:28:22.886766 # ok 68 # SKIP Disabled ZA for VL 368
5964 12:28:22.886889 # ok 69 # SKIP Get and set data for VL 368
5965 12:28:22.886998 # ok 70 Set VL 384
5966 12:28:22.887094 # ok 71 # SKIP Disabled ZA for VL 384
5967 12:28:22.887216 # ok 72 # SKIP Get and set data for VL 384
5968 12:28:22.887290 # ok 73 Set VL 400
5969 12:28:22.887382 # ok 74 # SKIP Disabled ZA for VL 400
5970 12:28:22.887654 # ok 75 # SKIP Get and set data for VL 400
5971 12:28:22.887727 # ok 76 Set VL 416
5972 12:28:22.888003 # ok 77 # SKIP Disabled ZA for VL 416
5973 12:28:22.888111 # ok 78 # SKIP Get and set data for VL 416
5974 12:28:22.888209 # ok 79 Set VL 432
5975 12:28:22.888330 # ok 80 # SKIP Disabled ZA for VL 432
5976 12:28:22.888626 # ok 81 # SKIP Get and set data for VL 432
5977 12:28:22.888720 # ok 82 Set VL 448
5978 12:28:22.888809 # ok 83 # SKIP Disabled ZA for VL 448
5979 12:28:22.889086 # ok 84 # SKIP Get and set data for VL 448
5980 12:28:22.889178 # ok 85 Set VL 464
5981 12:28:22.895916 # ok 86 # SKIP Disabled ZA for VL 464
5982 12:28:22.896333 # ok 87 # SKIP Get and set data for VL 464
5983 12:28:22.896419 # ok 88 Set VL 480
5984 12:28:22.896486 # ok 89 # SKIP Disabled ZA for VL 480
5985 12:28:22.896564 # ok 90 # SKIP Get and set data for VL 480
5986 12:28:22.896631 # ok 91 Set VL 496
5987 12:28:22.896696 # ok 92 # SKIP Disabled ZA for VL 496
5988 12:28:22.896763 # ok 93 # SKIP Get and set data for VL 496
5989 12:28:22.896840 # ok 94 Set VL 512
5990 12:28:22.896906 # ok 95 # SKIP Disabled ZA for VL 512
5991 12:28:22.896971 # ok 96 # SKIP Get and set data for VL 512
5992 12:28:22.897055 # ok 97 Set VL 528
5993 12:28:22.897122 # ok 98 # SKIP Disabled ZA for VL 528
5994 12:28:22.897215 # ok 99 # SKIP Get and set data for VL 528
5995 12:28:22.897324 # ok 100 Set VL 544
5996 12:28:22.897400 # ok 101 # SKIP Disabled ZA for VL 544
5997 12:28:22.900982 # ok 102 # SKIP Get and set data for VL 544
5998 12:28:22.901357 # ok 103 Set VL 560
5999 12:28:22.901569 # ok 104 # SKIP Disabled ZA for VL 560
6000 12:28:22.901724 # ok 105 # SKIP Get and set data for VL 560
6001 12:28:22.901886 # ok 106 Set VL 576
6002 12:28:22.902055 # ok 107 # SKIP Disabled ZA for VL 576
6003 12:28:22.902196 # ok 108 # SKIP Get and set data for VL 576
6004 12:28:22.902385 # ok 109 Set VL 592
6005 12:28:22.902565 # ok 110 # SKIP Disabled ZA for VL 592
6006 12:28:22.902719 # ok 111 # SKIP Get and set data for VL 592
6007 12:28:22.902916 # ok 112 Set VL 608
6008 12:28:22.903055 # ok 113 # SKIP Disabled ZA for VL 608
6009 12:28:22.903218 # ok 114 # SKIP Get and set data for VL 608
6010 12:28:22.903443 # ok 115 Set VL 624
6011 12:28:22.903633 # ok 116 # SKIP Disabled ZA for VL 624
6012 12:28:22.903794 # ok 117 # SKIP Get and set data for VL 624
6013 12:28:22.903917 # ok 118 Set VL 640
6014 12:28:22.904035 # ok 119 # SKIP Disabled ZA for VL 640
6015 12:28:22.904155 # ok 120 # SKIP Get and set data for VL 640
6016 12:28:22.904320 # ok 121 Set VL 656
6017 12:28:22.904458 # ok 122 # SKIP Disabled ZA for VL 656
6018 12:28:22.904646 # ok 123 # SKIP Get and set data for VL 656
6019 12:28:22.904779 # ok 124 Set VL 672
6020 12:28:22.914939 # ok 125 # SKIP Disabled ZA for VL 672
6021 12:28:22.915250 # ok 126 # SKIP Get and set data for VL 672
6022 12:28:22.915633 # ok 127 Set VL 688
6023 12:28:22.915735 # ok 128 # SKIP Disabled ZA for VL 688
6024 12:28:22.915841 # ok 129 # SKIP Get and set data for VL 688
6025 12:28:22.915946 # ok 130 Set VL 704
6026 12:28:22.916037 # ok 131 # SKIP Disabled ZA for VL 704
6027 12:28:22.916123 # ok 132 # SKIP Get and set data for VL 704
6028 12:28:22.916195 # ok 133 Set VL 720
6029 12:28:22.916274 # ok 134 # SKIP Disabled ZA for VL 720
6030 12:28:22.916399 # ok 135 # SKIP Get and set data for VL 720
6031 12:28:22.916495 # ok 136 Set VL 736
6032 12:28:22.916596 # ok 137 # SKIP Disabled ZA for VL 736
6033 12:28:22.916687 # ok 138 # SKIP Get and set data for VL 736
6034 12:28:22.916767 # ok 139 Set VL 752
6035 12:28:22.916864 # ok 140 # SKIP Disabled ZA for VL 752
6036 12:28:22.916938 # ok 141 # SKIP Get and set data for VL 752
6037 12:28:22.917027 # ok 142 Set VL 768
6038 12:28:22.917106 # ok 143 # SKIP Disabled ZA for VL 768
6039 12:28:22.917209 # ok 144 # SKIP Get and set data for VL 768
6040 12:28:22.917289 # ok 145 Set VL 784
6041 12:28:22.917367 # ok 146 # SKIP Disabled ZA for VL 784
6042 12:28:22.917429 # ok 147 # SKIP Get and set data for VL 784
6043 12:28:22.917489 # ok 148 Set VL 800
6044 12:28:22.917547 # ok 149 # SKIP Disabled ZA for VL 800
6045 12:28:22.917620 # ok 150 # SKIP Get and set data for VL 800
6046 12:28:22.917718 # ok 151 Set VL 816
6047 12:28:22.917819 # ok 152 # SKIP Disabled ZA for VL 816
6048 12:28:22.924129 # ok 153 # SKIP Get and set data for VL 816
6049 12:28:22.924481 # ok 154 Set VL 832
6050 12:28:22.924578 # ok 155 # SKIP Disabled ZA for VL 832
6051 12:28:22.924674 # ok 156 # SKIP Get and set data for VL 832
6052 12:28:22.924780 # ok 157 Set VL 848
6053 12:28:22.924871 # ok 158 # SKIP Disabled ZA for VL 848
6054 12:28:22.924964 # ok 159 # SKIP Get and set data for VL 848
6055 12:28:22.925050 # ok 160 Set VL 864
6056 12:28:22.925141 # ok 161 # SKIP Disabled ZA for VL 864
6057 12:28:22.925245 # ok 162 # SKIP Get and set data for VL 864
6058 12:28:22.925352 # ok 163 Set VL 880
6059 12:28:22.925423 # ok 164 # SKIP Disabled ZA for VL 880
6060 12:28:22.925486 # ok 165 # SKIP Get and set data for VL 880
6061 12:28:22.925566 # ok 166 Set VL 896
6062 12:28:22.925635 # ok 167 # SKIP Disabled ZA for VL 896
6063 12:28:22.925743 # ok 168 # SKIP Get and set data for VL 896
6064 12:28:22.925844 # ok 169 Set VL 912
6065 12:28:22.925958 # ok 170 # SKIP Disabled ZA for VL 912
6066 12:28:22.926251 # ok 171 # SKIP Get and set data for VL 912
6067 12:28:22.926347 # ok 172 Set VL 928
6068 12:28:22.926446 # ok 173 # SKIP Disabled ZA for VL 928
6069 12:28:22.926537 # ok 174 # SKIP Get and set data for VL 928
6070 12:28:22.926646 # ok 175 Set VL 944
6071 12:28:22.926728 # ok 176 # SKIP Disabled ZA for VL 944
6072 12:28:22.926797 # ok 177 # SKIP Get and set data for VL 944
6073 12:28:22.926867 # ok 178 Set VL 960
6074 12:28:22.926956 # ok 179 # SKIP Disabled ZA for VL 960
6075 12:28:22.927023 # ok 180 # SKIP Get and set data for VL 960
6076 12:28:22.927126 # ok 181 Set VL 976
6077 12:28:22.927214 # ok 182 # SKIP Disabled ZA for VL 976
6078 12:28:22.927301 # ok 183 # SKIP Get and set data for VL 976
6079 12:28:22.927380 # ok 184 Set VL 992
6080 12:28:22.927529 # ok 185 # SKIP Disabled ZA for VL 992
6081 12:28:22.927979 # ok 186 # SKIP Get and set data for VL 992
6082 12:28:22.928079 # ok 187 Set VL 1008
6083 12:28:22.928158 # ok 188 # SKIP Disabled ZA for VL 1008
6084 12:28:22.928251 # ok 189 # SKIP Get and set data for VL 1008
6085 12:28:22.928351 # ok 190 Set VL 1024
6086 12:28:22.928444 # ok 191 # SKIP Disabled ZA for VL 1024
6087 12:28:22.928532 # ok 192 # SKIP Get and set data for VL 1024
6088 12:28:22.928618 # ok 193 Set VL 1040
6089 12:28:22.928697 # ok 194 # SKIP Disabled ZA for VL 1040
6090 12:28:22.928979 # ok 195 # SKIP Get and set data for VL 1040
6091 12:28:22.929067 # ok 196 Set VL 1056
6092 12:28:22.929180 # ok 197 # SKIP Disabled ZA for VL 1056
6093 12:28:22.929291 # ok 198 # SKIP Get and set data for VL 1056
6094 12:28:22.929391 # ok 199 Set VL 1072
6095 12:28:22.929479 # ok 200 # SKIP Disabled ZA for VL 1072
6096 12:28:22.929545 # ok 201 # SKIP Get and set data for VL 1072
6097 12:28:22.929605 # ok 202 Set VL 1088
6098 12:28:22.929687 # ok 203 # SKIP Disabled ZA for VL 1088
6099 12:28:22.929797 # ok 204 # SKIP Get and set data for VL 1088
6100 12:28:22.929876 # ok 205 Set VL 1104
6101 12:28:22.929938 # ok 206 # SKIP Disabled ZA for VL 1104
6102 12:28:22.929998 # ok 207 # SKIP Get and set data for VL 1104
6103 12:28:22.930058 # ok 208 Set VL 1120
6104 12:28:22.930134 # ok 209 # SKIP Disabled ZA for VL 1120
6105 12:28:22.930201 # ok 210 # SKIP Get and set data for VL 1120
6106 12:28:22.930267 # ok 211 Set VL 1136
6107 12:28:22.930329 # ok 212 # SKIP Disabled ZA for VL 1136
6108 12:28:22.939128 # ok 213 # SKIP Get and set data for VL 1136
6109 12:28:22.939420 # ok 214 Set VL 1152
6110 12:28:22.939524 # ok 215 # SKIP Disabled ZA for VL 1152
6111 12:28:22.939839 # ok 216 # SKIP Get and set data for VL 1152
6112 12:28:22.939942 # ok 217 Set VL 1168
6113 12:28:22.940045 # ok 218 # SKIP Disabled ZA for VL 1168
6114 12:28:22.940144 # ok 219 # SKIP Get and set data for VL 1168
6115 12:28:22.940246 # ok 220 Set VL 1184
6116 12:28:22.940342 # ok 221 # SKIP Disabled ZA for VL 1184
6117 12:28:22.940437 # ok 222 # SKIP Get and set data for VL 1184
6118 12:28:22.940533 # ok 223 Set VL 1200
6119 12:28:22.940621 # ok 224 # SKIP Disabled ZA for VL 1200
6120 12:28:22.940727 # ok 225 # SKIP Get and set data for VL 1200
6121 12:28:22.940848 # ok 226 Set VL 1216
6122 12:28:22.940948 # ok 227 # SKIP Disabled ZA for VL 1216
6123 12:28:22.941047 # ok 228 # SKIP Get and set data for VL 1216
6124 12:28:22.941159 # ok 229 Set VL 1232
6125 12:28:22.941461 # ok 230 # SKIP Disabled ZA for VL 1232
6126 12:28:22.941555 # ok 231 # SKIP Get and set data for VL 1232
6127 12:28:22.941643 # ok 232 Set VL 1248
6128 12:28:22.941728 # ok 233 # SKIP Disabled ZA for VL 1248
6129 12:28:22.941791 # ok 234 # SKIP Get and set data for VL 1248
6130 12:28:22.941856 # ok 235 Set VL 1264
6131 12:28:22.941916 # ok 236 # SKIP Disabled ZA for VL 1264
6132 12:28:22.941993 # ok 237 # SKIP Get and set data for VL 1264
6133 12:28:22.942067 # ok 238 Set VL 1280
6134 12:28:22.942135 # ok 239 # SKIP Disabled ZA for VL 1280
6135 12:28:22.942202 # ok 240 # SKIP Get and set data for VL 1280
6136 12:28:22.942262 # ok 241 Set VL 1296
6137 12:28:22.942321 # ok 242 # SKIP Disabled ZA for VL 1296
6138 12:28:22.945144 # ok 243 # SKIP Get and set data for VL 1296
6139 12:28:22.945328 # ok 244 Set VL 1312
6140 12:28:22.945424 # ok 245 # SKIP Disabled ZA for VL 1312
6141 12:28:22.945518 # ok 246 # SKIP Get and set data for VL 1312
6142 12:28:22.945610 # ok 247 Set VL 1328
6143 12:28:22.985329 # ok 248 # SKIP Disabled ZA for VL 1328
6144 12:28:22.985588 # ok 249 # SKIP Get and set data for VL 1328
6145 12:28:22.985904 # ok 250 Set VL 1344
6146 12:28:23.003474 # ok 251 # SKIP Disabled ZA for VL 1344
6147 12:28:23.003723 # ok 252 # SKIP Get and set data for VL 1344
6148 12:28:23.003820 # ok 253 Set VL 1360
6149 12:28:23.003929 # ok 254 # SKIP Disabled ZA for VL 1360
6150 12:28:23.004025 # ok 255 # SKIP Get and set data for VL 1360
6151 12:28:23.004116 # ok 256 Set VL 1376
6152 12:28:23.004203 # ok 257 # SKIP Disabled ZA for VL 1376
6153 12:28:23.004296 # ok 258 # SKIP Get and set data for VL 1376
6154 12:28:23.004383 # ok 259 Set VL 1392
6155 12:28:23.004489 # ok 260 # SKIP Disabled ZA for VL 1392
6156 12:28:23.004581 # ok 261 # SKIP Get and set data for VL 1392
6157 12:28:23.004670 # ok 262 Set VL 1408
6158 12:28:23.004757 # ok 263 # SKIP Disabled ZA for VL 1408
6159 12:28:23.004862 # ok 264 # SKIP Get and set data for VL 1408
6160 12:28:23.004952 # ok 265 Set VL 1424
6161 12:28:23.005042 # ok 266 # SKIP Disabled ZA for VL 1424
6162 12:28:23.005131 # ok 267 # SKIP Get and set data for VL 1424
6163 12:28:23.005217 # ok 268 Set VL 1440
6164 12:28:23.005328 # ok 269 # SKIP Disabled ZA for VL 1440
6165 12:28:23.005418 # ok 270 # SKIP Get and set data for VL 1440
6166 12:28:23.005508 # ok 271 Set VL 1456
6167 12:28:23.005597 # ok 272 # SKIP Disabled ZA for VL 1456
6168 12:28:23.005693 # ok 273 # SKIP Get and set data for VL 1456
6169 12:28:23.019771 # ok 274 Set VL 1472
6170 12:28:23.020382 # ok 275 # SKIP Disabled ZA for VL 1472
6171 12:28:23.020604 # ok 276 # SKIP Get and set data for VL 1472
6172 12:28:23.020791 # ok 277 Set VL 1488
6173 12:28:23.020976 # ok 278 # SKIP Disabled ZA for VL 1488
6174 12:28:23.021149 # ok 279 # SKIP Get and set data for VL 1488
6175 12:28:23.021308 # ok 280 Set VL 1504
6176 12:28:23.021478 # ok 281 # SKIP Disabled ZA for VL 1504
6177 12:28:23.021642 # ok 282 # SKIP Get and set data for VL 1504
6178 12:28:23.021811 # ok 283 Set VL 1520
6179 12:28:23.021931 # ok 284 # SKIP Disabled ZA for VL 1520
6180 12:28:23.022083 # ok 285 # SKIP Get and set data for VL 1520
6181 12:28:23.022227 # ok 286 Set VL 1536
6182 12:28:23.022343 # ok 287 # SKIP Disabled ZA for VL 1536
6183 12:28:23.022499 # ok 288 # SKIP Get and set data for VL 1536
6184 12:28:23.022622 # ok 289 Set VL 1552
6185 12:28:23.022758 # ok 290 # SKIP Disabled ZA for VL 1552
6186 12:28:23.022909 # ok 291 # SKIP Get and set data for VL 1552
6187 12:28:23.026363 # ok 292 Set VL 1568
6188 12:28:23.026835 # ok 293 # SKIP Disabled ZA for VL 1568
6189 12:28:23.026997 # ok 294 # SKIP Get and set data for VL 1568
6190 12:28:23.027120 # ok 295 Set VL 1584
6191 12:28:23.027244 # ok 296 # SKIP Disabled ZA for VL 1584
6192 12:28:23.027427 # ok 297 # SKIP Get and set data for VL 1584
6193 12:28:23.027553 # ok 298 Set VL 1600
6194 12:28:23.027670 # ok 299 # SKIP Disabled ZA for VL 1600
6195 12:28:23.027814 # ok 300 # SKIP Get and set data for VL 1600
6196 12:28:23.027950 # ok 301 Set VL 1616
6197 12:28:23.028097 # ok 302 # SKIP Disabled ZA for VL 1616
6198 12:28:23.028267 # ok 303 # SKIP Get and set data for VL 1616
6199 12:28:23.028395 # ok 304 Set VL 1632
6200 12:28:23.028513 # ok 305 # SKIP Disabled ZA for VL 1632
6201 12:28:23.028666 # ok 306 # SKIP Get and set data for VL 1632
6202 12:28:23.028788 # ok 307 Set VL 1648
6203 12:28:23.028918 # ok 308 # SKIP Disabled ZA for VL 1648
6204 12:28:23.029087 # ok 309 # SKIP Get and set data for VL 1648
6205 12:28:23.029215 # ok 310 Set VL 1664
6206 12:28:23.029365 # ok 311 # SKIP Disabled ZA for VL 1664
6207 12:28:23.029485 # ok 312 # SKIP Get and set data for VL 1664
6208 12:28:23.029612 # ok 313 Set VL 1680
6209 12:28:23.029816 # ok 314 # SKIP Disabled ZA for VL 1680
6210 12:28:23.029943 # ok 315 # SKIP Get and set data for VL 1680
6211 12:28:23.030098 # ok 316 Set VL 1696
6212 12:28:23.030221 # ok 317 # SKIP Disabled ZA for VL 1696
6213 12:28:23.030343 # ok 318 # SKIP Get and set data for VL 1696
6214 12:28:23.030494 # ok 319 Set VL 1712
6215 12:28:23.030613 # ok 320 # SKIP Disabled ZA for VL 1712
6216 12:28:23.030770 # ok 321 # SKIP Get and set data for VL 1712
6217 12:28:23.030907 # ok 322 Set VL 1728
6218 12:28:23.034638 # ok 323 # SKIP Disabled ZA for VL 1728
6219 12:28:23.035137 # ok 324 # SKIP Get and set data for VL 1728
6220 12:28:23.035241 # ok 325 Set VL 1744
6221 12:28:23.035316 # ok 326 # SKIP Disabled ZA for VL 1744
6222 12:28:23.035398 # ok 327 # SKIP Get and set data for VL 1744
6223 12:28:23.035470 # ok 328 Set VL 1760
6224 12:28:23.035558 # ok 329 # SKIP Disabled ZA for VL 1760
6225 12:28:23.035633 # ok 330 # SKIP Get and set data for VL 1760
6226 12:28:23.035703 # ok 331 Set VL 1776
6227 12:28:23.036074 # ok 332 # SKIP Disabled ZA for VL 1776
6228 12:28:23.036169 # ok 333 # SKIP Get and set data for VL 1776
6229 12:28:23.036252 # ok 334 Set VL 1792
6230 12:28:23.036328 # ok 335 # SKIP Disabled ZA for VL 1792
6231 12:28:23.036600 # ok 336 # SKIP Get and set data for VL 1792
6232 12:28:23.036698 # ok 337 Set VL 1808
6233 12:28:23.036779 # ok 338 # SKIP Disabled ZA for VL 1808
6234 12:28:23.036857 # ok 339 # SKIP Get and set data for VL 1808
6235 12:28:23.036932 # ok 340 Set VL 1824
6236 12:28:23.037010 # ok 341 # SKIP Disabled ZA for VL 1824
6237 12:28:23.037084 # ok 342 # SKIP Get and set data for VL 1824
6238 12:28:23.037155 # ok 343 Set VL 1840
6239 12:28:23.037243 # ok 344 # SKIP Disabled ZA for VL 1840
6240 12:28:23.037316 # ok 345 # SKIP Get and set data for VL 1840
6241 12:28:23.037389 # ok 346 Set VL 1856
6242 12:28:23.037461 # ok 347 # SKIP Disabled ZA for VL 1856
6243 12:28:23.037533 # ok 348 # SKIP Get and set data for VL 1856
6244 12:28:23.037610 # ok 349 Set VL 1872
6245 12:28:23.037711 # ok 350 # SKIP Disabled ZA for VL 1872
6246 12:28:23.043191 # ok 351 # SKIP Get and set data for VL 1872
6247 12:28:23.043428 # ok 352 Set VL 1888
6248 12:28:23.043524 # ok 353 # SKIP Disabled ZA for VL 1888
6249 12:28:23.043637 # ok 354 # SKIP Get and set data for VL 1888
6250 12:28:23.043731 # ok 355 Set VL 1904
6251 12:28:23.043821 # ok 356 # SKIP Disabled ZA for VL 1904
6252 12:28:23.043915 # ok 357 # SKIP Get and set data for VL 1904
6253 12:28:23.044023 # ok 358 Set VL 1920
6254 12:28:23.045180 # ok 359 # SKIP Disabled ZA for VL 1920
6255 12:28:23.045314 # ok 360 # SKIP Get and set data for VL 1920
6256 12:28:23.050911 # ok 361 Set VL 1936
6257 12:28:23.051492 # ok 362 # SKIP Disabled ZA for VL 1936
6258 12:28:23.051664 # ok 363 # SKIP Get and set data for VL 1936
6259 12:28:23.051843 # ok 364 Set VL 1952
6260 12:28:23.052003 # ok 365 # SKIP Disabled ZA for VL 1952
6261 12:28:23.052151 # ok 366 # SKIP Get and set data for VL 1952
6262 12:28:23.052309 # ok 367 Set VL 1968
6263 12:28:23.052507 # ok 368 # SKIP Disabled ZA for VL 1968
6264 12:28:23.052668 # ok 369 # SKIP Get and set data for VL 1968
6265 12:28:23.052824 # ok 370 Set VL 1984
6266 12:28:23.052978 # ok 371 # SKIP Disabled ZA for VL 1984
6267 12:28:23.053133 # ok 372 # SKIP Get and set data for VL 1984
6268 12:28:23.053291 # ok 373 Set VL 2000
6269 12:28:23.053443 # ok 374 # SKIP Disabled ZA for VL 2000
6270 12:28:23.053584 # ok 375 # SKIP Get and set data for VL 2000
6271 12:28:23.053756 # ok 376 Set VL 2016
6272 12:28:23.054002 # ok 377 # SKIP Disabled ZA for VL 2016
6273 12:28:23.054197 # ok 378 # SKIP Get and set data for VL 2016
6274 12:28:23.054343 # ok 379 Set VL 2032
6275 12:28:23.054490 # ok 380 # SKIP Disabled ZA for VL 2032
6276 12:28:23.054633 # ok 381 # SKIP Get and set data for VL 2032
6277 12:28:23.054775 # ok 382 Set VL 2048
6278 12:28:23.054916 # ok 383 # SKIP Disabled ZA for VL 2048
6279 12:28:23.055058 # ok 384 # SKIP Get and set data for VL 2048
6280 12:28:23.055200 # ok 385 Set VL 2064
6281 12:28:23.058759 # ok 386 # SKIP Disabled ZA for VL 2064
6282 12:28:23.059261 # ok 387 # SKIP Get and set data for VL 2064
6283 12:28:23.059464 # ok 388 Set VL 2080
6284 12:28:23.059665 # ok 389 # SKIP Disabled ZA for VL 2080
6285 12:28:23.059869 # ok 390 # SKIP Get and set data for VL 2080
6286 12:28:23.060080 # ok 391 Set VL 2096
6287 12:28:23.060335 # ok 392 # SKIP Disabled ZA for VL 2096
6288 12:28:23.060527 # ok 393 # SKIP Get and set data for VL 2096
6289 12:28:23.060709 # ok 394 Set VL 2112
6290 12:28:23.060927 # ok 395 # SKIP Disabled ZA for VL 2112
6291 12:28:23.061154 # ok 396 # SKIP Get and set data for VL 2112
6292 12:28:23.061372 # ok 397 Set VL 2128
6293 12:28:23.061515 # ok 398 # SKIP Disabled ZA for VL 2128
6294 12:28:23.061700 # ok 399 # SKIP Get and set data for VL 2128
6295 12:28:23.061868 # ok 400 Set VL 2144
6296 12:28:23.062045 # ok 401 # SKIP Disabled ZA for VL 2144
6297 12:28:23.062187 # ok 402 # SKIP Get and set data for VL 2144
6298 12:28:23.062347 # ok 403 Set VL 2160
6299 12:28:23.062476 # ok 404 # SKIP Disabled ZA for VL 2160
6300 12:28:23.062593 # ok 405 # SKIP Get and set data for VL 2160
6301 12:28:23.062721 # ok 406 Set VL 2176
6302 12:28:23.062837 # ok 407 # SKIP Disabled ZA for VL 2176
6303 12:28:23.062994 # ok 408 # SKIP Get and set data for VL 2176
6304 12:28:23.063129 # ok 409 Set VL 2192
6305 12:28:23.063294 # ok 410 # SKIP Disabled ZA for VL 2192
6306 12:28:23.063426 # ok 411 # SKIP Get and set data for VL 2192
6307 12:28:23.063543 # ok 412 Set VL 2208
6308 12:28:23.065157 # ok 413 # SKIP Disabled ZA for VL 2208
6309 12:28:23.065506 # ok 414 # SKIP Get and set data for VL 2208
6310 12:28:23.066540 # ok 415 Set VL 2224
6311 12:28:23.066859 # ok 416 # SKIP Disabled ZA for VL 2224
6312 12:28:23.066966 # ok 417 # SKIP Get and set data for VL 2224
6313 12:28:23.067059 # ok 418 Set VL 2240
6314 12:28:23.067166 # ok 419 # SKIP Disabled ZA for VL 2240
6315 12:28:23.067257 # ok 420 # SKIP Get and set data for VL 2240
6316 12:28:23.067349 # ok 421 Set VL 2256
6317 12:28:23.067457 # ok 422 # SKIP Disabled ZA for VL 2256
6318 12:28:23.067547 # ok 423 # SKIP Get and set data for VL 2256
6319 12:28:23.067651 # ok 424 Set VL 2272
6320 12:28:23.067740 # ok 425 # SKIP Disabled ZA for VL 2272
6321 12:28:23.067846 # ok 426 # SKIP Get and set data for VL 2272
6322 12:28:23.067937 # ok 427 Set VL 2288
6323 12:28:23.068041 # ok 428 # SKIP Disabled ZA for VL 2288
6324 12:28:23.068131 # ok 429 # SKIP Get and set data for VL 2288
6325 12:28:23.068556 # ok 430 Set VL 2304
6326 12:28:23.068675 # ok 431 # SKIP Disabled ZA for VL 2304
6327 12:28:23.068769 # ok 432 # SKIP Get and set data for VL 2304
6328 12:28:23.068860 # ok 433 Set VL 2320
6329 12:28:23.068948 # ok 434 # SKIP Disabled ZA for VL 2320
6330 12:28:23.069032 # ok 435 # SKIP Get and set data for VL 2320
6331 12:28:23.069120 # ok 436 Set VL 2336
6332 12:28:23.069227 # ok 437 # SKIP Disabled ZA for VL 2336
6333 12:28:23.069320 # ok 438 # SKIP Get and set data for VL 2336
6334 12:28:23.069409 # ok 439 Set VL 2352
6335 12:28:23.069497 # ok 440 # SKIP Disabled ZA for VL 2352
6336 12:28:23.069588 # ok 441 # SKIP Get and set data for VL 2352
6337 12:28:23.069707 # ok 442 Set VL 2368
6338 12:28:23.074721 # ok 443 # SKIP Disabled ZA for VL 2368
6339 12:28:23.075085 # ok 444 # SKIP Get and set data for VL 2368
6340 12:28:23.075287 # ok 445 Set VL 2384
6341 12:28:23.075498 # ok 446 # SKIP Disabled ZA for VL 2384
6342 12:28:23.075670 # ok 447 # SKIP Get and set data for VL 2384
6343 12:28:23.075843 # ok 448 Set VL 2400
6344 12:28:23.075987 # ok 449 # SKIP Disabled ZA for VL 2400
6345 12:28:23.076130 # ok 450 # SKIP Get and set data for VL 2400
6346 12:28:23.076289 # ok 451 Set VL 2416
6347 12:28:23.076482 # ok 452 # SKIP Disabled ZA for VL 2416
6348 12:28:23.076613 # ok 453 # SKIP Get and set data for VL 2416
6349 12:28:23.076733 # ok 454 Set VL 2432
6350 12:28:23.076850 # ok 455 # SKIP Disabled ZA for VL 2432
6351 12:28:23.076975 # ok 456 # SKIP Get and set data for VL 2432
6352 12:28:23.077097 # ok 457 Set VL 2448
6353 12:28:23.077220 # ok 458 # SKIP Disabled ZA for VL 2448
6354 12:28:23.077339 # ok 459 # SKIP Get and set data for VL 2448
6355 12:28:23.077458 # ok 460 Set VL 2464
6356 12:28:23.077599 # ok 461 # SKIP Disabled ZA for VL 2464
6357 12:28:23.077787 # ok 462 # SKIP Get and set data for VL 2464
6358 12:28:23.078076 # ok 463 Set VL 2480
6359 12:28:23.078263 # ok 464 # SKIP Disabled ZA for VL 2480
6360 12:28:23.078407 # ok 465 # SKIP Get and set data for VL 2480
6361 12:28:23.078551 # ok 466 Set VL 2496
6362 12:28:23.078691 # ok 467 # SKIP Disabled ZA for VL 2496
6363 12:28:23.078834 # ok 468 # SKIP Get and set data for VL 2496
6364 12:28:23.079043 # ok 469 Set VL 2512
6365 12:28:23.079203 # ok 470 # SKIP Disabled ZA for VL 2512
6366 12:28:23.079379 # ok 471 # SKIP Get and set data for VL 2512
6367 12:28:23.079547 # ok 472 Set VL 2528
6368 12:28:23.079720 # ok 473 # SKIP Disabled ZA for VL 2528
6369 12:28:23.079884 # ok 474 # SKIP Get and set data for VL 2528
6370 12:28:23.080049 # ok 475 Set VL 2544
6371 12:28:23.080413 # ok 476 # SKIP Disabled ZA for VL 2544
6372 12:28:23.081758 # ok 477 # SKIP Get and set data for VL 2544
6373 12:28:23.081944 # ok 478 Set VL 2560
6374 12:28:23.082090 # ok 479 # SKIP Disabled ZA for VL 2560
6375 12:28:23.082210 # ok 480 # SKIP Get and set data for VL 2560
6376 12:28:23.082368 # ok 481 Set VL 2576
6377 12:28:23.086621 # ok 482 # SKIP Disabled ZA for VL 2576
6378 12:28:23.087180 # ok 483 # SKIP Get and set data for VL 2576
6379 12:28:23.087371 # ok 484 Set VL 2592
6380 12:28:23.087540 # ok 485 # SKIP Disabled ZA for VL 2592
6381 12:28:23.087706 # ok 486 # SKIP Get and set data for VL 2592
6382 12:28:23.087874 # ok 487 Set VL 2608
6383 12:28:23.088075 # ok 488 # SKIP Disabled ZA for VL 2608
6384 12:28:23.088249 # ok 489 # SKIP Get and set data for VL 2608
6385 12:28:23.088418 # ok 490 Set VL 2624
6386 12:28:23.088589 # ok 491 # SKIP Disabled ZA for VL 2624
6387 12:28:23.088754 # ok 492 # SKIP Get and set data for VL 2624
6388 12:28:23.088918 # ok 493 Set VL 2640
6389 12:28:23.089076 # ok 494 # SKIP Disabled ZA for VL 2640
6390 12:28:23.089233 # ok 495 # SKIP Get and set data for VL 2640
6391 12:28:23.089394 # ok 496 Set VL 2656
6392 12:28:23.089588 # ok 497 # SKIP Disabled ZA for VL 2656
6393 12:28:23.089772 # ok 498 # SKIP Get and set data for VL 2656
6394 12:28:23.089936 # ok 499 Set VL 2672
6395 12:28:23.090101 # ok 500 # SKIP Disabled ZA for VL 2672
6396 12:28:23.090266 # ok 501 # SKIP Get and set data for VL 2672
6397 12:28:23.090426 # ok 502 Set VL 2688
6398 12:28:23.090551 # ok 503 # SKIP Disabled ZA for VL 2688
6399 12:28:23.090672 # ok 504 # SKIP Get and set data for VL 2688
6400 12:28:23.090793 # ok 505 Set VL 2704
6401 12:28:23.090914 # ok 506 # SKIP Disabled ZA for VL 2704
6402 12:28:23.091036 # ok 507 # SKIP Get and set data for VL 2704
6403 12:28:23.091160 # ok 508 Set VL 2720
6404 12:28:23.091278 # ok 509 # SKIP Disabled ZA for VL 2720
6405 12:28:23.094693 # ok 510 # SKIP Get and set data for VL 2720
6406 12:28:23.094902 # ok 511 Set VL 2736
6407 12:28:23.094990 # ok 512 # SKIP Disabled ZA for VL 2736
6408 12:28:23.095095 # ok 513 # SKIP Get and set data for VL 2736
6409 12:28:23.095180 # ok 514 Set VL 2752
6410 12:28:23.095264 # ok 515 # SKIP Disabled ZA for VL 2752
6411 12:28:23.095352 # ok 516 # SKIP Get and set data for VL 2752
6412 12:28:23.095457 # ok 517 Set VL 2768
6413 12:28:23.095547 # ok 518 # SKIP Disabled ZA for VL 2768
6414 12:28:23.095632 # ok 519 # SKIP Get and set data for VL 2768
6415 12:28:23.095711 # ok 520 Set VL 2784
6416 12:28:23.095807 # ok 521 # SKIP Disabled ZA for VL 2784
6417 12:28:23.095891 # ok 522 # SKIP Get and set data for VL 2784
6418 12:28:23.095976 # ok 523 Set VL 2800
6419 12:28:23.096074 # ok 524 # SKIP Disabled ZA for VL 2800
6420 12:28:23.096157 # ok 525 # SKIP Get and set data for VL 2800
6421 12:28:23.096238 # ok 526 Set VL 2816
6422 12:28:23.096331 # ok 527 # SKIP Disabled ZA for VL 2816
6423 12:28:23.096412 # ok 528 # SKIP Get and set data for VL 2816
6424 12:28:23.096499 # ok 529 Set VL 2832
6425 12:28:23.096595 # ok 530 # SKIP Disabled ZA for VL 2832
6426 12:28:23.096680 # ok 531 # SKIP Get and set data for VL 2832
6427 12:28:23.096761 # ok 532 Set VL 2848
6428 12:28:23.096856 # ok 533 # SKIP Disabled ZA for VL 2848
6429 12:28:23.096954 # ok 534 # SKIP Get and set data for VL 2848
6430 12:28:23.097039 # ok 535 Set VL 2864
6431 12:28:23.097138 # ok 536 # SKIP Disabled ZA for VL 2864
6432 12:28:23.097238 # ok 537 # SKIP Get and set data for VL 2864
6433 12:28:23.097323 # ok 538 Set VL 2880
6434 12:28:23.102639 # ok 539 # SKIP Disabled ZA for VL 2880
6435 12:28:23.102984 # ok 540 # SKIP Get and set data for VL 2880
6436 12:28:23.103162 # ok 541 Set VL 2896
6437 12:28:23.103376 # ok 542 # SKIP Disabled ZA for VL 2896
6438 12:28:23.103932 # ok 543 # SKIP Get and set data for VL 2896
6439 12:28:23.104137 # ok 544 Set VL 2912
6440 12:28:23.104326 # ok 545 # SKIP Disabled ZA for VL 2912
6441 12:28:23.104509 # ok 546 # SKIP Get and set data for VL 2912
6442 12:28:23.104682 # ok 547 Set VL 2928
6443 12:28:23.104856 # ok 548 # SKIP Disabled ZA for VL 2928
6444 12:28:23.105072 # ok 549 # SKIP Get and set data for VL 2928
6445 12:28:23.105262 # ok 550 Set VL 2944
6446 12:28:23.105425 # ok 551 # SKIP Disabled ZA for VL 2944
6447 12:28:23.105551 # ok 552 # SKIP Get and set data for VL 2944
6448 12:28:23.105697 # ok 553 Set VL 2960
6449 12:28:23.105903 # ok 554 # SKIP Disabled ZA for VL 2960
6450 12:28:23.106074 # ok 555 # SKIP Get and set data for VL 2960
6451 12:28:23.106218 # ok 556 Set VL 2976
6452 12:28:23.106360 # ok 557 # SKIP Disabled ZA for VL 2976
6453 12:28:23.106555 # ok 558 # SKIP Get and set data for VL 2976
6454 12:28:23.106690 # ok 559 Set VL 2992
6455 12:28:23.106831 # ok 560 # SKIP Disabled ZA for VL 2992
6456 12:28:23.106971 # ok 561 # SKIP Get and set data for VL 2992
6457 12:28:23.107112 # ok 562 Set VL 3008
6458 12:28:23.107253 # ok 563 # SKIP Disabled ZA for VL 3008
6459 12:28:23.107395 # ok 564 # SKIP Get and set data for VL 3008
6460 12:28:23.107536 # ok 565 Set VL 3024
6461 12:28:23.107677 # ok 566 # SKIP Disabled ZA for VL 3024
6462 12:28:23.107820 # ok 567 # SKIP Get and set data for VL 3024
6463 12:28:23.107961 # ok 568 Set VL 3040
6464 12:28:23.108102 # ok 569 # SKIP Disabled ZA for VL 3040
6465 12:28:23.108245 # ok 570 # SKIP Get and set data for VL 3040
6466 12:28:23.108386 # ok 571 Set VL 3056
6467 12:28:23.108531 # ok 572 # SKIP Disabled ZA for VL 3056
6468 12:28:23.110761 # ok 573 # SKIP Get and set data for VL 3056
6469 12:28:23.111008 # ok 574 Set VL 3072
6470 12:28:23.111106 # ok 575 # SKIP Disabled ZA for VL 3072
6471 12:28:23.111403 # ok 576 # SKIP Get and set data for VL 3072
6472 12:28:23.111502 # ok 577 Set VL 3088
6473 12:28:23.111594 # ok 578 # SKIP Disabled ZA for VL 3088
6474 12:28:23.111680 # ok 579 # SKIP Get and set data for VL 3088
6475 12:28:23.111767 # ok 580 Set VL 3104
6476 12:28:23.111853 # ok 581 # SKIP Disabled ZA for VL 3104
6477 12:28:23.111938 # ok 582 # SKIP Get and set data for VL 3104
6478 12:28:23.112044 # ok 583 Set VL 3120
6479 12:28:23.112130 # ok 584 # SKIP Disabled ZA for VL 3120
6480 12:28:23.112209 # ok 585 # SKIP Get and set data for VL 3120
6481 12:28:23.112283 # ok 586 Set VL 3136
6482 12:28:23.112359 # ok 587 # SKIP Disabled ZA for VL 3136
6483 12:28:23.112451 # ok 588 # SKIP Get and set data for VL 3136
6484 12:28:23.112531 # ok 589 Set VL 3152
6485 12:28:23.116588 # ok 590 # SKIP Disabled ZA for VL 3152
6486 12:28:23.116875 # ok 591 # SKIP Get and set data for VL 3152
6487 12:28:23.117027 # ok 592 Set VL 3168
6488 12:28:23.117394 # ok 593 # SKIP Disabled ZA for VL 3168
6489 12:28:23.117529 # ok 594 # SKIP Get and set data for VL 3168
6490 12:28:23.117666 # ok 595 Set VL 3184
6491 12:28:23.117787 # ok 596 # SKIP Disabled ZA for VL 3184
6492 12:28:23.117906 # ok 597 # SKIP Get and set data for VL 3184
6493 12:28:23.118023 # ok 598 Set VL 3200
6494 12:28:23.118141 # ok 599 # SKIP Disabled ZA for VL 3200
6495 12:28:23.118258 # ok 600 # SKIP Get and set data for VL 3200
6496 12:28:23.121463 # ok 601 Set VL 3216
6497 12:28:23.122373 # ok 602 # SKIP Disabled ZA for VL 3216
6498 12:28:23.122638 # ok 603 # SKIP Get and set data for VL 3216
6499 12:28:23.122862 # ok 604 Set VL 3232
6500 12:28:23.123006 # ok 605 # SKIP Disabled ZA for VL 3232
6501 12:28:23.123135 # ok 606 # SKIP Get and set data for VL 3232
6502 12:28:23.123262 # ok 607 Set VL 3248
6503 12:28:23.123438 # ok 608 # SKIP Disabled ZA for VL 3248
6504 12:28:23.123774 # ok 609 # SKIP Get and set data for VL 3248
6505 12:28:23.124005 # ok 610 Set VL 3264
6506 12:28:23.124211 # ok 611 # SKIP Disabled ZA for VL 3264
6507 12:28:23.124426 # ok 612 # SKIP Get and set data for VL 3264
6508 12:28:23.124633 # ok 613 Set VL 3280
6509 12:28:23.124833 # ok 614 # SKIP Disabled ZA for VL 3280
6510 12:28:23.125035 # ok 615 # SKIP Get and set data for VL 3280
6511 12:28:23.125210 # ok 616 Set VL 3296
6512 12:28:23.125359 # ok 617 # SKIP Disabled ZA for VL 3296
6513 12:28:23.125504 # ok 618 # SKIP Get and set data for VL 3296
6514 12:28:23.125663 # ok 619 Set VL 3312
6515 12:28:23.125808 # ok 620 # SKIP Disabled ZA for VL 3312
6516 12:28:23.125951 # ok 621 # SKIP Get and set data for VL 3312
6517 12:28:23.126141 # ok 622 Set VL 3328
6518 12:28:23.126275 # ok 623 # SKIP Disabled ZA for VL 3328
6519 12:28:23.126418 # ok 624 # SKIP Get and set data for VL 3328
6520 12:28:23.126563 # ok 625 Set VL 3344
6521 12:28:23.126705 # ok 626 # SKIP Disabled ZA for VL 3344
6522 12:28:23.126847 # ok 627 # SKIP Get and set data for VL 3344
6523 12:28:23.126989 # ok 628 Set VL 3360
6524 12:28:23.127130 # ok 629 # SKIP Disabled ZA for VL 3360
6525 12:28:23.127272 # ok 630 # SKIP Get and set data for VL 3360
6526 12:28:23.127413 # ok 631 Set VL 3376
6527 12:28:23.127556 # ok 632 # SKIP Disabled ZA for VL 3376
6528 12:28:23.127699 # ok 633 # SKIP Get and set data for VL 3376
6529 12:28:23.127840 # ok 634 Set VL 3392
6530 12:28:23.127981 # ok 635 # SKIP Disabled ZA for VL 3392
6531 12:28:23.128121 # ok 636 # SKIP Get and set data for VL 3392
6532 12:28:23.128262 # ok 637 Set VL 3408
6533 12:28:23.128403 # ok 638 # SKIP Disabled ZA for VL 3408
6534 12:28:23.128544 # ok 639 # SKIP Get and set data for VL 3408
6535 12:28:23.128688 # ok 640 Set VL 3424
6536 12:28:23.128828 # ok 641 # SKIP Disabled ZA for VL 3424
6537 12:28:23.128969 # ok 642 # SKIP Get and set data for VL 3424
6538 12:28:23.129111 # ok 643 Set VL 3440
6539 12:28:23.130756 # ok 644 # SKIP Disabled ZA for VL 3440
6540 12:28:23.130890 # ok 645 # SKIP Get and set data for VL 3440
6541 12:28:23.130982 # ok 646 Set VL 3456
6542 12:28:23.131087 # ok 647 # SKIP Disabled ZA for VL 3456
6543 12:28:23.131177 # ok 648 # SKIP Get and set data for VL 3456
6544 12:28:23.131266 # ok 649 Set VL 3472
6545 12:28:23.131368 # ok 650 # SKIP Disabled ZA for VL 3472
6546 12:28:23.131456 # ok 651 # SKIP Get and set data for VL 3472
6547 12:28:23.131544 # ok 652 Set VL 3488
6548 12:28:23.131646 # ok 653 # SKIP Disabled ZA for VL 3488
6549 12:28:23.131749 # ok 654 # SKIP Get and set data for VL 3488
6550 12:28:23.131838 # ok 655 Set VL 3504
6551 12:28:23.131939 # ok 656 # SKIP Disabled ZA for VL 3504
6552 12:28:23.132028 # ok 657 # SKIP Get and set data for VL 3504
6553 12:28:23.132129 # ok 658 Set VL 3520
6554 12:28:23.132232 # ok 659 # SKIP Disabled ZA for VL 3520
6555 12:28:23.132336 # ok 660 # SKIP Get and set data for VL 3520
6556 12:28:23.132424 # ok 661 Set VL 3536
6557 12:28:23.132525 # ok 662 # SKIP Disabled ZA for VL 3536
6558 12:28:23.132626 # ok 663 # SKIP Get and set data for VL 3536
6559 12:28:23.132714 # ok 664 Set VL 3552
6560 12:28:23.132817 # ok 665 # SKIP Disabled ZA for VL 3552
6561 12:28:23.132919 # ok 666 # SKIP Get and set data for VL 3552
6562 12:28:23.133021 # ok 667 Set VL 3568
6563 12:28:23.133109 # ok 668 # SKIP Disabled ZA for VL 3568
6564 12:28:23.133397 # ok 669 # SKIP Get and set data for VL 3568
6565 12:28:23.133483 # ok 670 Set VL 3584
6566 12:28:23.138436 # ok 671 # SKIP Disabled ZA for VL 3584
6567 12:28:23.138684 # ok 672 # SKIP Get and set data for VL 3584
6568 12:28:23.138989 # ok 673 Set VL 3600
6569 12:28:23.139097 # ok 674 # SKIP Disabled ZA for VL 3600
6570 12:28:23.139186 # ok 675 # SKIP Get and set data for VL 3600
6571 12:28:23.139273 # ok 676 Set VL 3616
6572 12:28:23.139358 # ok 677 # SKIP Disabled ZA for VL 3616
6573 12:28:23.139442 # ok 678 # SKIP Get and set data for VL 3616
6574 12:28:23.139528 # ok 679 Set VL 3632
6575 12:28:23.139631 # ok 680 # SKIP Disabled ZA for VL 3632
6576 12:28:23.139720 # ok 681 # SKIP Get and set data for VL 3632
6577 12:28:23.139807 # ok 682 Set VL 3648
6578 12:28:23.139891 # ok 683 # SKIP Disabled ZA for VL 3648
6579 12:28:23.139975 # ok 684 # SKIP Get and set data for VL 3648
6580 12:28:23.140075 # ok 685 Set VL 3664
6581 12:28:23.140162 # ok 686 # SKIP Disabled ZA for VL 3664
6582 12:28:23.140247 # ok 687 # SKIP Get and set data for VL 3664
6583 12:28:23.140330 # ok 688 Set VL 3680
6584 12:28:23.140429 # ok 689 # SKIP Disabled ZA for VL 3680
6585 12:28:23.140515 # ok 690 # SKIP Get and set data for VL 3680
6586 12:28:23.140601 # ok 691 Set VL 3696
6587 12:28:23.140687 # ok 692 # SKIP Disabled ZA for VL 3696
6588 12:28:23.140785 # ok 693 # SKIP Get and set data for VL 3696
6589 12:28:23.140871 # ok 694 Set VL 3712
6590 12:28:23.140955 # ok 695 # SKIP Disabled ZA for VL 3712
6591 12:28:23.141053 # ok 696 # SKIP Get and set data for VL 3712
6592 12:28:23.141138 # ok 697 Set VL 3728
6593 12:28:23.141234 # ok 698 # SKIP Disabled ZA for VL 3728
6594 12:28:23.141327 # ok 699 # SKIP Get and set data for VL 3728
6595 12:28:23.154619 # ok 700 Set VL 3744
6596 12:28:23.154961 # ok 701 # SKIP Disabled ZA for VL 3744
6597 12:28:23.155388 # ok 702 # SKIP Get and set data for VL 3744
6598 12:28:23.155585 # ok 703 Set VL 3760
6599 12:28:23.155743 # ok 704 # SKIP Disabled ZA for VL 3760
6600 12:28:23.155894 # ok 705 # SKIP Get and set data for VL 3760
6601 12:28:23.156043 # ok 706 Set VL 3776
6602 12:28:23.156200 # ok 707 # SKIP Disabled ZA for VL 3776
6603 12:28:23.156345 # ok 708 # SKIP Get and set data for VL 3776
6604 12:28:23.156505 # ok 709 Set VL 3792
6605 12:28:23.156690 # ok 710 # SKIP Disabled ZA for VL 3792
6606 12:28:23.156913 # ok 711 # SKIP Get and set data for VL 3792
6607 12:28:23.157082 # ok 712 Set VL 3808
6608 12:28:23.157245 # ok 713 # SKIP Disabled ZA for VL 3808
6609 12:28:23.157408 # ok 714 # SKIP Get and set data for VL 3808
6610 12:28:23.157569 # ok 715 Set VL 3824
6611 12:28:23.157754 # ok 716 # SKIP Disabled ZA for VL 3824
6612 12:28:23.157925 # ok 717 # SKIP Get and set data for VL 3824
6613 12:28:23.158095 # ok 718 Set VL 3840
6614 12:28:23.158262 # ok 719 # SKIP Disabled ZA for VL 3840
6615 12:28:23.158424 # ok 720 # SKIP Get and set data for VL 3840
6616 12:28:23.158596 # ok 721 Set VL 3856
6617 12:28:23.158765 # ok 722 # SKIP Disabled ZA for VL 3856
6618 12:28:23.158921 # ok 723 # SKIP Get and set data for VL 3856
6619 12:28:23.159060 # ok 724 Set VL 3872
6620 12:28:23.159217 # ok 725 # SKIP Disabled ZA for VL 3872
6621 12:28:23.159377 # ok 726 # SKIP Get and set data for VL 3872
6622 12:28:23.159528 # ok 727 Set VL 3888
6623 12:28:23.159690 # ok 728 # SKIP Disabled ZA for VL 3888
6624 12:28:23.159914 # ok 729 # SKIP Get and set data for VL 3888
6625 12:28:23.160093 # ok 730 Set VL 3904
6626 12:28:23.160261 # ok 731 # SKIP Disabled ZA for VL 3904
6627 12:28:23.160429 # ok 732 # SKIP Get and set data for VL 3904
6628 12:28:23.160602 # ok 733 Set VL 3920
6629 12:28:23.160780 # ok 734 # SKIP Disabled ZA for VL 3920
6630 12:28:23.160955 # ok 735 # SKIP Get and set data for VL 3920
6631 12:28:23.161125 # ok 736 Set VL 3936
6632 12:28:23.161296 # ok 737 # SKIP Disabled ZA for VL 3936
6633 12:28:23.168842 # ok 738 # SKIP Get and set data for VL 3936
6634 12:28:23.169196 # ok 739 Set VL 3952
6635 12:28:23.169579 # ok 740 # SKIP Disabled ZA for VL 3952
6636 12:28:23.169725 # ok 741 # SKIP Get and set data for VL 3952
6637 12:28:23.169844 # ok 742 Set VL 3968
6638 12:28:23.169960 # ok 743 # SKIP Disabled ZA for VL 3968
6639 12:28:23.170076 # ok 744 # SKIP Get and set data for VL 3968
6640 12:28:23.178817 # ok 745 Set VL 3984
6641 12:28:23.179319 # ok 746 # SKIP Disabled ZA for VL 3984
6642 12:28:23.179487 # ok 747 # SKIP Get and set data for VL 3984
6643 12:28:23.179620 # ok 748 Set VL 4000
6644 12:28:23.179770 # ok 749 # SKIP Disabled ZA for VL 4000
6645 12:28:23.179897 # ok 750 # SKIP Get and set data for VL 4000
6646 12:28:23.180022 # ok 751 Set VL 4016
6647 12:28:23.180145 # ok 752 # SKIP Disabled ZA for VL 4016
6648 12:28:23.180268 # ok 753 # SKIP Get and set data for VL 4016
6649 12:28:23.180390 # ok 754 Set VL 4032
6650 12:28:23.180517 # ok 755 # SKIP Disabled ZA for VL 4032
6651 12:28:23.180673 # ok 756 # SKIP Get and set data for VL 4032
6652 12:28:23.180801 # ok 757 Set VL 4048
6653 12:28:23.180931 # ok 758 # SKIP Disabled ZA for VL 4048
6654 12:28:23.181051 # ok 759 # SKIP Get and set data for VL 4048
6655 12:28:23.181176 # ok 760 Set VL 4064
6656 12:28:23.181298 # ok 761 # SKIP Disabled ZA for VL 4064
6657 12:28:23.181420 # ok 762 # SKIP Get and set data for VL 4064
6658 12:28:23.181541 # ok 763 Set VL 4080
6659 12:28:23.181699 # ok 764 # SKIP Disabled ZA for VL 4080
6660 12:28:23.181823 # ok 765 # SKIP Get and set data for VL 4080
6661 12:28:23.181938 # ok 766 Set VL 4096
6662 12:28:23.182053 # ok 767 # SKIP Disabled ZA for VL 4096
6663 12:28:23.182168 # ok 768 # SKIP Get and set data for VL 4096
6664 12:28:23.182283 # ok 769 Set VL 4112
6665 12:28:23.195017 # ok 770 # SKIP Disabled ZA for VL 4112
6666 12:28:23.195687 # ok 771 # SKIP Get and set data for VL 4112
6667 12:28:23.196041 # ok 772 Set VL 4128
6668 12:28:23.196333 # ok 773 # SKIP Disabled ZA for VL 4128
6669 12:28:23.196554 # ok 774 # SKIP Get and set data for VL 4128
6670 12:28:23.196771 # ok 775 Set VL 4144
6671 12:28:23.196996 # ok 776 # SKIP Disabled ZA for VL 4144
6672 12:28:23.197206 # ok 777 # SKIP Get and set data for VL 4144
6673 12:28:23.197460 # ok 778 Set VL 4160
6674 12:28:23.197610 # ok 779 # SKIP Disabled ZA for VL 4160
6675 12:28:23.197786 # ok 780 # SKIP Get and set data for VL 4160
6676 12:28:23.197915 # ok 781 Set VL 4176
6677 12:28:23.198044 # ok 782 # SKIP Disabled ZA for VL 4176
6678 12:28:23.198159 # ok 783 # SKIP Get and set data for VL 4176
6679 12:28:23.198276 # ok 784 Set VL 4192
6680 12:28:23.198409 # ok 785 # SKIP Disabled ZA for VL 4192
6681 12:28:23.198525 # ok 786 # SKIP Get and set data for VL 4192
6682 12:28:23.198645 # ok 787 Set VL 4208
6683 12:28:23.198770 # ok 788 # SKIP Disabled ZA for VL 4208
6684 12:28:23.198885 # ok 789 # SKIP Get and set data for VL 4208
6685 12:28:23.199001 # ok 790 Set VL 4224
6686 12:28:23.199127 # ok 791 # SKIP Disabled ZA for VL 4224
6687 12:28:23.199245 # ok 792 # SKIP Get and set data for VL 4224
6688 12:28:23.199362 # ok 793 Set VL 4240
6689 12:28:23.199485 # ok 794 # SKIP Disabled ZA for VL 4240
6690 12:28:23.211343 # ok 795 # SKIP Get and set data for VL 4240
6691 12:28:23.211607 # ok 796 Set VL 4256
6692 12:28:23.211698 # ok 797 # SKIP Disabled ZA for VL 4256
6693 12:28:23.212074 # ok 798 # SKIP Get and set data for VL 4256
6694 12:28:23.212187 # ok 799 Set VL 4272
6695 12:28:23.212273 # ok 800 # SKIP Disabled ZA for VL 4272
6696 12:28:23.212355 # ok 801 # SKIP Get and set data for VL 4272
6697 12:28:23.212434 # ok 802 Set VL 4288
6698 12:28:23.212516 # ok 803 # SKIP Disabled ZA for VL 4288
6699 12:28:23.212596 # ok 804 # SKIP Get and set data for VL 4288
6700 12:28:23.212677 # ok 805 Set VL 4304
6701 12:28:23.212966 # ok 806 # SKIP Disabled ZA for VL 4304
6702 12:28:23.213104 # ok 807 # SKIP Get and set data for VL 4304
6703 12:28:23.213231 # ok 808 Set VL 4320
6704 12:28:23.213321 # ok 809 # SKIP Disabled ZA for VL 4320
6705 12:28:23.213404 # ok 810 # SKIP Get and set data for VL 4320
6706 12:28:23.213485 # ok 811 Set VL 4336
6707 12:28:23.213567 # ok 812 # SKIP Disabled ZA for VL 4336
6708 12:28:23.213661 # ok 813 # SKIP Get and set data for VL 4336
6709 12:28:23.213744 # ok 814 Set VL 4352
6710 12:28:23.213827 # ok 815 # SKIP Disabled ZA for VL 4352
6711 12:28:23.213930 # ok 816 # SKIP Get and set data for VL 4352
6712 12:28:23.214018 # ok 817 Set VL 4368
6713 12:28:23.214101 # ok 818 # SKIP Disabled ZA for VL 4368
6714 12:28:23.226958 # ok 819 # SKIP Get and set data for VL 4368
6715 12:28:23.227227 # ok 820 Set VL 4384
6716 12:28:23.227532 # ok 821 # SKIP Disabled ZA for VL 4384
6717 12:28:23.228752 # ok 822 # SKIP Get and set data for VL 4384
6718 12:28:23.228931 # ok 823 Set VL 4400
6719 12:28:23.229055 # ok 824 # SKIP Disabled ZA for VL 4400
6720 12:28:23.229180 # ok 825 # SKIP Get and set data for VL 4400
6721 12:28:23.229329 # ok 826 Set VL 4416
6722 12:28:23.229459 # ok 827 # SKIP Disabled ZA for VL 4416
6723 12:28:23.229583 # ok 828 # SKIP Get and set data for VL 4416
6724 12:28:23.229722 # ok 829 Set VL 4432
6725 12:28:23.229848 # ok 830 # SKIP Disabled ZA for VL 4432
6726 12:28:23.230006 # ok 831 # SKIP Get and set data for VL 4432
6727 12:28:23.243404 # ok 832 Set VL 4448
6728 12:28:23.243711 # ok 833 # SKIP Disabled ZA for VL 4448
6729 12:28:23.243888 # ok 834 # SKIP Get and set data for VL 4448
6730 12:28:23.244039 # ok 835 Set VL 4464
6731 12:28:23.244201 # ok 836 # SKIP Disabled ZA for VL 4464
6732 12:28:23.244353 # ok 837 # SKIP Get and set data for VL 4464
6733 12:28:23.244511 # ok 838 Set VL 4480
6734 12:28:23.245812 # ok 839 # SKIP Disabled ZA for VL 4480
6735 12:28:23.245932 # ok 840 # SKIP Get and set data for VL 4480
6736 12:28:23.246024 # ok 841 Set VL 4496
6737 12:28:23.246114 # ok 842 # SKIP Disabled ZA for VL 4496
6738 12:28:23.246205 # ok 843 # SKIP Get and set data for VL 4496
6739 12:28:23.246295 # ok 844 Set VL 4512
6740 12:28:23.246382 # ok 845 # SKIP Disabled ZA for VL 4512
6741 12:28:23.246470 # ok 846 # SKIP Get and set data for VL 4512
6742 12:28:23.246557 # ok 847 Set VL 4528
6743 12:28:23.246645 # ok 848 # SKIP Disabled ZA for VL 4528
6744 12:28:23.246734 # ok 849 # SKIP Get and set data for VL 4528
6745 12:28:23.246822 # ok 850 Set VL 4544
6746 12:28:23.246911 # ok 851 # SKIP Disabled ZA for VL 4544
6747 12:28:23.247000 # ok 852 # SKIP Get and set data for VL 4544
6748 12:28:23.247089 # ok 853 Set VL 4560
6749 12:28:23.247177 # ok 854 # SKIP Disabled ZA for VL 4560
6750 12:28:23.247264 # ok 855 # SKIP Get and set data for VL 4560
6751 12:28:23.247348 # ok 856 Set VL 4576
6752 12:28:23.247430 # ok 857 # SKIP Disabled ZA for VL 4576
6753 12:28:23.247515 # ok 858 # SKIP Get and set data for VL 4576
6754 12:28:23.247597 # ok 859 Set VL 4592
6755 12:28:23.247679 # ok 860 # SKIP Disabled ZA for VL 4592
6756 12:28:23.247764 # ok 861 # SKIP Get and set data for VL 4592
6757 12:28:23.247848 # ok 862 Set VL 4608
6758 12:28:23.247929 # ok 863 # SKIP Disabled ZA for VL 4608
6759 12:28:23.262367 # ok 864 # SKIP Get and set data for VL 4608
6760 12:28:23.262706 # ok 865 Set VL 4624
6761 12:28:23.263092 # ok 866 # SKIP Disabled ZA for VL 4624
6762 12:28:23.263282 # ok 867 # SKIP Get and set data for VL 4624
6763 12:28:23.263462 # ok 868 Set VL 4640
6764 12:28:23.263634 # ok 869 # SKIP Disabled ZA for VL 4640
6765 12:28:23.263816 # ok 870 # SKIP Get and set data for VL 4640
6766 12:28:23.264002 # ok 871 Set VL 4656
6767 12:28:23.264179 # ok 872 # SKIP Disabled ZA for VL 4656
6768 12:28:23.264403 # ok 873 # SKIP Get and set data for VL 4656
6769 12:28:23.264585 # ok 874 Set VL 4672
6770 12:28:23.264767 # ok 875 # SKIP Disabled ZA for VL 4672
6771 12:28:23.264947 # ok 876 # SKIP Get and set data for VL 4672
6772 12:28:23.265134 # ok 877 Set VL 4688
6773 12:28:23.265324 # ok 878 # SKIP Disabled ZA for VL 4688
6774 12:28:23.265479 # ok 879 # SKIP Get and set data for VL 4688
6775 12:28:23.265639 # ok 880 Set VL 4704
6776 12:28:23.265786 # ok 881 # SKIP Disabled ZA for VL 4704
6777 12:28:23.265913 # ok 882 # SKIP Get and set data for VL 4704
6778 12:28:23.266035 # ok 883 Set VL 4720
6779 12:28:23.266156 # ok 884 # SKIP Disabled ZA for VL 4720
6780 12:28:23.266275 # ok 885 # SKIP Get and set data for VL 4720
6781 12:28:23.266560 # ok 886 Set VL 4736
6782 12:28:23.266733 # ok 887 # SKIP Disabled ZA for VL 4736
6783 12:28:23.266866 # ok 888 # SKIP Get and set data for VL 4736
6784 12:28:23.266981 # ok 889 Set VL 4752
6785 12:28:23.267095 # ok 890 # SKIP Disabled ZA for VL 4752
6786 12:28:23.278576 # ok 891 # SKIP Get and set data for VL 4752
6787 12:28:23.278818 # ok 892 Set VL 4768
6788 12:28:23.278919 # ok 893 # SKIP Disabled ZA for VL 4768
6789 12:28:23.279013 # ok 894 # SKIP Get and set data for VL 4768
6790 12:28:23.279300 # ok 895 Set VL 4784
6791 12:28:23.279409 # ok 896 # SKIP Disabled ZA for VL 4784
6792 12:28:23.279500 # ok 897 # SKIP Get and set data for VL 4784
6793 12:28:23.279590 # ok 898 Set VL 4800
6794 12:28:23.279678 # ok 899 # SKIP Disabled ZA for VL 4800
6795 12:28:23.279765 # ok 900 # SKIP Get and set data for VL 4800
6796 12:28:23.279848 # ok 901 Set VL 4816
6797 12:28:23.279960 # ok 902 # SKIP Disabled ZA for VL 4816
6798 12:28:23.280050 # ok 903 # SKIP Get and set data for VL 4816
6799 12:28:23.280136 # ok 904 Set VL 4832
6800 12:28:23.280221 # ok 905 # SKIP Disabled ZA for VL 4832
6801 12:28:23.280307 # ok 906 # SKIP Get and set data for VL 4832
6802 12:28:23.280411 # ok 907 Set VL 4848
6803 12:28:23.280504 # ok 908 # SKIP Disabled ZA for VL 4848
6804 12:28:23.280591 # ok 909 # SKIP Get and set data for VL 4848
6805 12:28:23.280693 # ok 910 Set VL 4864
6806 12:28:23.280780 # ok 911 # SKIP Disabled ZA for VL 4864
6807 12:28:23.280871 # ok 912 # SKIP Get and set data for VL 4864
6808 12:28:23.280955 # ok 913 Set VL 4880
6809 12:28:23.281040 # ok 914 # SKIP Disabled ZA for VL 4880
6810 12:28:23.281139 # ok 915 # SKIP Get and set data for VL 4880
6811 12:28:23.281238 # ok 916 Set VL 4896
6812 12:28:23.281323 # ok 917 # SKIP Disabled ZA for VL 4896
6813 12:28:23.281398 # ok 918 # SKIP Get and set data for VL 4896
6814 12:28:23.281472 # ok 919 Set VL 4912
6815 12:28:23.292050 # ok 920 # SKIP Disabled ZA for VL 4912
6816 12:28:23.292349 # ok 921 # SKIP Get and set data for VL 4912
6817 12:28:23.292480 # ok 922 Set VL 4928
6818 12:28:23.292604 # ok 923 # SKIP Disabled ZA for VL 4928
6819 12:28:23.293002 # ok 924 # SKIP Get and set data for VL 4928
6820 12:28:23.293109 # ok 925 Set VL 4944
6821 12:28:23.293199 # ok 926 # SKIP Disabled ZA for VL 4944
6822 12:28:23.293284 # ok 927 # SKIP Get and set data for VL 4944
6823 12:28:23.293361 # ok 928 Set VL 4960
6824 12:28:23.293434 # ok 929 # SKIP Disabled ZA for VL 4960
6825 12:28:23.293508 # ok 930 # SKIP Get and set data for VL 4960
6826 12:28:23.293581 # ok 931 Set VL 4976
6827 12:28:23.293666 # ok 932 # SKIP Disabled ZA for VL 4976
6828 12:28:23.293740 # ok 933 # SKIP Get and set data for VL 4976
6829 12:28:23.293813 # ok 934 Set VL 4992
6830 12:28:23.293892 # ok 935 # SKIP Disabled ZA for VL 4992
6831 12:28:23.293966 # ok 936 # SKIP Get and set data for VL 4992
6832 12:28:23.294039 # ok 937 Set VL 5008
6833 12:28:23.294130 # ok 938 # SKIP Disabled ZA for VL 5008
6834 12:28:23.296587 # ok 939 # SKIP Get and set data for VL 5008
6835 12:28:23.297228 # ok 940 Set VL 5024
6836 12:28:23.297337 # ok 941 # SKIP Disabled ZA for VL 5024
6837 12:28:23.297427 # ok 942 # SKIP Get and set data for VL 5024
6838 12:28:23.297511 # ok 943 Set VL 5040
6839 12:28:23.297597 # ok 944 # SKIP Disabled ZA for VL 5040
6840 12:28:23.297698 # ok 945 # SKIP Get and set data for VL 5040
6841 12:28:23.297784 # ok 946 Set VL 5056
6842 12:28:23.297872 # ok 947 # SKIP Disabled ZA for VL 5056
6843 12:28:23.297972 # ok 948 # SKIP Get and set data for VL 5056
6844 12:28:23.298060 # ok 949 Set VL 5072
6845 12:28:23.298141 # ok 950 # SKIP Disabled ZA for VL 5072
6846 12:28:23.303054 # ok 951 # SKIP Get and set data for VL 5072
6847 12:28:23.303278 # ok 952 Set VL 5088
6848 12:28:23.303375 # ok 953 # SKIP Disabled ZA for VL 5088
6849 12:28:23.303464 # ok 954 # SKIP Get and set data for VL 5088
6850 12:28:23.303572 # ok 955 Set VL 5104
6851 12:28:23.303664 # ok 956 # SKIP Disabled ZA for VL 5104
6852 12:28:23.303754 # ok 957 # SKIP Get and set data for VL 5104
6853 12:28:23.303847 # ok 958 Set VL 5120
6854 12:28:23.303938 # ok 959 # SKIP Disabled ZA for VL 5120
6855 12:28:23.304025 # ok 960 # SKIP Get and set data for VL 5120
6856 12:28:23.304116 # ok 961 Set VL 5136
6857 12:28:23.304225 # ok 962 # SKIP Disabled ZA for VL 5136
6858 12:28:23.304328 # ok 963 # SKIP Get and set data for VL 5136
6859 12:28:23.304417 # ok 964 Set VL 5152
6860 12:28:23.304506 # ok 965 # SKIP Disabled ZA for VL 5152
6861 12:28:23.304590 # ok 966 # SKIP Get and set data for VL 5152
6862 12:28:23.304671 # ok 967 Set VL 5168
6863 12:28:23.304752 # ok 968 # SKIP Disabled ZA for VL 5168
6864 12:28:23.304833 # ok 969 # SKIP Get and set data for VL 5168
6865 12:28:23.304936 # ok 970 Set VL 5184
6866 12:28:23.305022 # ok 971 # SKIP Disabled ZA for VL 5184
6867 12:28:23.305102 # ok 972 # SKIP Get and set data for VL 5184
6868 12:28:23.305182 # ok 973 Set VL 5200
6869 12:28:23.305265 # ok 974 # SKIP Disabled ZA for VL 5200
6870 12:28:23.305347 # ok 975 # SKIP Get and set data for VL 5200
6871 12:28:23.305429 # ok 976 Set VL 5216
6872 12:28:23.305509 # ok 977 # SKIP Disabled ZA for VL 5216
6873 12:28:23.305621 # ok 978 # SKIP Get and set data for VL 5216
6874 12:28:23.305740 # ok 979 Set VL 5232
6875 12:28:23.305823 # ok 980 # SKIP Disabled ZA for VL 5232
6876 12:28:23.305908 # ok 981 # SKIP Get and set data for VL 5232
6877 12:28:23.305992 # ok 982 Set VL 5248
6878 12:28:23.306076 # ok 983 # SKIP Disabled ZA for VL 5248
6879 12:28:23.306159 # ok 984 # SKIP Get and set data for VL 5248
6880 12:28:23.311628 # ok 985 Set VL 5264
6881 12:28:23.312114 # ok 986 # SKIP Disabled ZA for VL 5264
6882 12:28:23.312225 # ok 987 # SKIP Get and set data for VL 5264
6883 12:28:23.312317 # ok 988 Set VL 5280
6884 12:28:23.312402 # ok 989 # SKIP Disabled ZA for VL 5280
6885 12:28:23.312488 # ok 990 # SKIP Get and set data for VL 5280
6886 12:28:23.312575 # ok 991 Set VL 5296
6887 12:28:23.312682 # ok 992 # SKIP Disabled ZA for VL 5296
6888 12:28:23.312772 # ok 993 # SKIP Get and set data for VL 5296
6889 12:28:23.312856 # ok 994 Set VL 5312
6890 12:28:23.312945 # ok 995 # SKIP Disabled ZA for VL 5312
6891 12:28:23.313048 # ok 996 # SKIP Get and set data for VL 5312
6892 12:28:23.313135 # ok 997 Set VL 5328
6893 12:28:23.313220 # ok 998 # SKIP Disabled ZA for VL 5328
6894 12:28:23.313305 # ok 999 # SKIP Get and set data for VL 5328
6895 12:28:23.313389 # ok 1000 Set VL 5344
6896 12:28:23.313495 # ok 1001 # SKIP Disabled ZA for VL 5344
6897 12:28:23.313583 # ok 1002 # SKIP Get and set data for VL 5344
6898 12:28:23.313678 # ok 1003 Set VL 5360
6899 12:28:23.313761 # ok 1004 # SKIP Disabled ZA for VL 5360
6900 12:28:23.318544 # ok 1005 # SKIP Get and set data for VL 5360
6901 12:28:23.319010 # ok 1006 Set VL 5376
6902 12:28:23.319115 # ok 1007 # SKIP Disabled ZA for VL 5376
6903 12:28:23.319203 # ok 1008 # SKIP Get and set data for VL 5376
6904 12:28:23.319289 # ok 1009 Set VL 5392
6905 12:28:23.319373 # ok 1010 # SKIP Disabled ZA for VL 5392
6906 12:28:23.319456 # ok 1011 # SKIP Get and set data for VL 5392
6907 12:28:23.319558 # ok 1012 Set VL 5408
6908 12:28:23.319646 # ok 1013 # SKIP Disabled ZA for VL 5408
6909 12:28:23.319731 # ok 1014 # SKIP Get and set data for VL 5408
6910 12:28:23.319814 # ok 1015 Set VL 5424
6911 12:28:23.319898 # ok 1016 # SKIP Disabled ZA for VL 5424
6912 12:28:23.319997 # ok 1017 # SKIP Get and set data for VL 5424
6913 12:28:23.320084 # ok 1018 Set VL 5440
6914 12:28:23.320166 # ok 1019 # SKIP Disabled ZA for VL 5440
6915 12:28:23.320249 # ok 1020 # SKIP Get and set data for VL 5440
6916 12:28:23.320334 # ok 1021 Set VL 5456
6917 12:28:23.320421 # ok 1022 # SKIP Disabled ZA for VL 5456
6918 12:28:23.320508 # ok 1023 # SKIP Get and set data for VL 5456
6919 12:28:23.320615 # ok 1024 Set VL 5472
6920 12:28:23.320701 # ok 1025 # SKIP Disabled ZA for VL 5472
6921 12:28:23.320785 # ok 1026 # SKIP Get and set data for VL 5472
6922 12:28:23.320870 # ok 1027 Set VL 5488
6923 12:28:23.320956 # ok 1028 # SKIP Disabled ZA for VL 5488
6924 12:28:23.321039 # ok 1029 # SKIP Get and set data for VL 5488
6925 12:28:23.321125 # ok 1030 Set VL 5504
6926 12:28:23.321228 # ok 1031 # SKIP Disabled ZA for VL 5504
6927 12:28:23.321317 # ok 1032 # SKIP Get and set data for VL 5504
6928 12:28:23.321399 # ok 1033 Set VL 5520
6929 12:28:23.321480 # ok 1034 # SKIP Disabled ZA for VL 5520
6930 12:28:23.321562 # ok 1035 # SKIP Get and set data for VL 5520
6931 12:28:23.321657 # ok 1036 Set VL 5536
6932 12:28:23.321743 # ok 1037 # SKIP Disabled ZA for VL 5536
6933 12:28:23.321830 # ok 1038 # SKIP Get and set data for VL 5536
6934 12:28:23.321919 # ok 1039 Set VL 5552
6935 12:28:23.322026 # ok 1040 # SKIP Disabled ZA for VL 5552
6936 12:28:23.326651 # ok 1041 # SKIP Get and set data for VL 5552
6937 12:28:23.326881 # ok 1042 Set VL 5568
6938 12:28:23.327266 # ok 1043 # SKIP Disabled ZA for VL 5568
6939 12:28:23.327514 # ok 1044 # SKIP Get and set data for VL 5568
6940 12:28:23.327756 # ok 1045 Set VL 5584
6941 12:28:23.327958 # ok 1046 # SKIP Disabled ZA for VL 5584
6942 12:28:23.328165 # ok 1047 # SKIP Get and set data for VL 5584
6943 12:28:23.328357 # ok 1048 Set VL 5600
6944 12:28:23.328526 # ok 1049 # SKIP Disabled ZA for VL 5600
6945 12:28:23.328690 # ok 1050 # SKIP Get and set data for VL 5600
6946 12:28:23.328877 # ok 1051 Set VL 5616
6947 12:28:23.329019 # ok 1052 # SKIP Disabled ZA for VL 5616
6948 12:28:23.329138 # ok 1053 # SKIP Get and set data for VL 5616
6949 12:28:23.329279 # ok 1054 Set VL 5632
6950 12:28:23.329400 # ok 1055 # SKIP Disabled ZA for VL 5632
6951 12:28:23.329519 # ok 1056 # SKIP Get and set data for VL 5632
6952 12:28:23.329690 # ok 1057 Set VL 5648
6953 12:28:23.329886 # ok 1058 # SKIP Disabled ZA for VL 5648
6954 12:28:23.334761 # ok 1059 # SKIP Get and set data for VL 5648
6955 12:28:23.334984 # ok 1060 Set VL 5664
6956 12:28:23.335090 # ok 1061 # SKIP Disabled ZA for VL 5664
6957 12:28:23.335176 # ok 1062 # SKIP Get and set data for VL 5664
6958 12:28:23.335258 # ok 1063 Set VL 5680
6959 12:28:23.335338 # ok 1064 # SKIP Disabled ZA for VL 5680
6960 12:28:23.335419 # ok 1065 # SKIP Get and set data for VL 5680
6961 12:28:23.335517 # ok 1066 Set VL 5696
6962 12:28:23.335600 # ok 1067 # SKIP Disabled ZA for VL 5696
6963 12:28:23.335682 # ok 1068 # SKIP Get and set data for VL 5696
6964 12:28:23.335763 # ok 1069 Set VL 5712
6965 12:28:23.335841 # ok 1070 # SKIP Disabled ZA for VL 5712
6966 12:28:23.335922 # ok 1071 # SKIP Get and set data for VL 5712
6967 12:28:23.336003 # ok 1072 Set VL 5728
6968 12:28:23.336102 # ok 1073 # SKIP Disabled ZA for VL 5728
6969 12:28:23.336185 # ok 1074 # SKIP Get and set data for VL 5728
6970 12:28:23.336267 # ok 1075 Set VL 5744
6971 12:28:23.336350 # ok 1076 # SKIP Disabled ZA for VL 5744
6972 12:28:23.336433 # ok 1077 # SKIP Get and set data for VL 5744
6973 12:28:23.336516 # ok 1078 Set VL 5760
6974 12:28:23.336599 # ok 1079 # SKIP Disabled ZA for VL 5760
6975 12:28:23.336699 # ok 1080 # SKIP Get and set data for VL 5760
6976 12:28:23.336784 # ok 1081 Set VL 5776
6977 12:28:23.336868 # ok 1082 # SKIP Disabled ZA for VL 5776
6978 12:28:23.336951 # ok 1083 # SKIP Get and set data for VL 5776
6979 12:28:23.337034 # ok 1084 Set VL 5792
6980 12:28:23.337118 # ok 1085 # SKIP Disabled ZA for VL 5792
6981 12:28:23.337200 # ok 1086 # SKIP Get and set data for VL 5792
6982 12:28:23.337298 # ok 1087 Set VL 5808
6983 12:28:23.337385 # ok 1088 # SKIP Disabled ZA for VL 5808
6984 12:28:23.337468 # ok 1089 # SKIP Get and set data for VL 5808
6985 12:28:23.337552 # ok 1090 Set VL 5824
6986 12:28:23.337636 # ok 1091 # SKIP Disabled ZA for VL 5824
6987 12:28:23.337731 # ok 1092 # SKIP Get and set data for VL 5824
6988 12:28:23.337814 # ok 1093 Set VL 5840
6989 12:28:23.337914 # ok 1094 # SKIP Disabled ZA for VL 5840
6990 12:28:23.338003 # ok 1095 # SKIP Get and set data for VL 5840
6991 12:28:23.338107 # ok 1096 Set VL 5856
6992 12:28:23.338201 # ok 1097 # SKIP Disabled ZA for VL 5856
6993 12:28:23.338306 # ok 1098 # SKIP Get and set data for VL 5856
6994 12:28:23.338397 # ok 1099 Set VL 5872
6995 12:28:23.338498 # ok 1100 # SKIP Disabled ZA for VL 5872
6996 12:28:23.338588 # ok 1101 # SKIP Get and set data for VL 5872
6997 12:28:23.338691 # ok 1102 Set VL 5888
6998 12:28:23.338780 # ok 1103 # SKIP Disabled ZA for VL 5888
6999 12:28:23.338868 # ok 1104 # SKIP Get and set data for VL 5888
7000 12:28:23.338974 # ok 1105 Set VL 5904
7001 12:28:23.339070 # ok 1106 # SKIP Disabled ZA for VL 5904
7002 12:28:23.339158 # ok 1107 # SKIP Get and set data for VL 5904
7003 12:28:23.339260 # ok 1108 Set VL 5920
7004 12:28:23.339345 # ok 1109 # SKIP Disabled ZA for VL 5920
7005 12:28:23.339431 # ok 1110 # SKIP Get and set data for VL 5920
7006 12:28:23.339527 # ok 1111 Set VL 5936
7007 12:28:23.339888 # ok 1112 # SKIP Disabled ZA for VL 5936
7008 12:28:23.340000 # ok 1113 # SKIP Get and set data for VL 5936
7009 12:28:23.340088 # ok 1114 Set VL 5952
7010 12:28:23.340174 # ok 1115 # SKIP Disabled ZA for VL 5952
7011 12:28:23.340258 # ok 1116 # SKIP Get and set data for VL 5952
7012 12:28:23.340346 # ok 1117 Set VL 5968
7013 12:28:23.340453 # ok 1118 # SKIP Disabled ZA for VL 5968
7014 12:28:23.340543 # ok 1119 # SKIP Get and set data for VL 5968
7015 12:28:23.340631 # ok 1120 Set VL 5984
7016 12:28:23.340714 # ok 1121 # SKIP Disabled ZA for VL 5984
7017 12:28:23.341840 # ok 1122 # SKIP Get and set data for VL 5984
7018 12:28:23.342020 # ok 1123 Set VL 6000
7019 12:28:23.342145 # ok 1124 # SKIP Disabled ZA for VL 6000
7020 12:28:23.342264 # ok 1125 # SKIP Get and set data for VL 6000
7021 12:28:23.342382 # ok 1126 Set VL 6016
7022 12:28:23.342499 # ok 1127 # SKIP Disabled ZA for VL 6016
7023 12:28:23.342617 # ok 1128 # SKIP Get and set data for VL 6016
7024 12:28:23.342734 # ok 1129 Set VL 6032
7025 12:28:23.342851 # ok 1130 # SKIP Disabled ZA for VL 6032
7026 12:28:23.342968 # ok 1131 # SKIP Get and set data for VL 6032
7027 12:28:23.343085 # ok 1132 Set VL 6048
7028 12:28:23.345345 # ok 1133 # SKIP Disabled ZA for VL 6048
7029 12:28:23.349292 # ok 1134 # SKIP Get and set data for VL 6048
7030 12:28:23.349701 # ok 1135 Set VL 6064
7031 12:28:23.350282 # ok 1136 # SKIP Disabled ZA for VL 6064
7032 12:28:23.350590 # ok 1137 # SKIP Get and set data for VL 6064
7033 12:28:23.350697 # ok 1138 Set VL 6080
7034 12:28:23.350793 # ok 1139 # SKIP Disabled ZA for VL 6080
7035 12:28:23.350904 # ok 1140 # SKIP Get and set data for VL 6080
7036 12:28:23.351002 # ok 1141 Set VL 6096
7037 12:28:23.351093 # ok 1142 # SKIP Disabled ZA for VL 6096
7038 12:28:23.351200 # ok 1143 # SKIP Get and set data for VL 6096
7039 12:28:23.351294 # ok 1144 Set VL 6112
7040 12:28:23.351385 # ok 1145 # SKIP Disabled ZA for VL 6112
7041 12:28:23.351493 # ok 1146 # SKIP Get and set data for VL 6112
7042 12:28:23.351586 # ok 1147 Set VL 6128
7043 12:28:23.351677 # ok 1148 # SKIP Disabled ZA for VL 6128
7044 12:28:23.351768 # ok 1149 # SKIP Get and set data for VL 6128
7045 12:28:23.351856 # ok 1150 Set VL 6144
7046 12:28:23.351960 # ok 1151 # SKIP Disabled ZA for VL 6144
7047 12:28:23.352054 # ok 1152 # SKIP Get and set data for VL 6144
7048 12:28:23.352137 # ok 1153 Set VL 6160
7049 12:28:23.352238 # ok 1154 # SKIP Disabled ZA for VL 6160
7050 12:28:23.352323 # ok 1155 # SKIP Get and set data for VL 6160
7051 12:28:23.352406 # ok 1156 Set VL 6176
7052 12:28:23.352490 # ok 1157 # SKIP Disabled ZA for VL 6176
7053 12:28:23.352575 # ok 1158 # SKIP Get and set data for VL 6176
7054 12:28:23.352659 # ok 1159 Set VL 6192
7055 12:28:23.352760 # ok 1160 # SKIP Disabled ZA for VL 6192
7056 12:28:23.352848 # ok 1161 # SKIP Get and set data for VL 6192
7057 12:28:23.352931 # ok 1162 Set VL 6208
7058 12:28:23.353020 # ok 1163 # SKIP Disabled ZA for VL 6208
7059 12:28:23.353102 # ok 1164 # SKIP Get and set data for VL 6208
7060 12:28:23.353188 # ok 1165 Set VL 6224
7061 12:28:23.353288 # ok 1166 # SKIP Disabled ZA for VL 6224
7062 12:28:23.353375 # ok 1167 # SKIP Get and set data for VL 6224
7063 12:28:23.353461 # ok 1168 Set VL 6240
7064 12:28:23.353544 # ok 1169 # SKIP Disabled ZA for VL 6240
7065 12:28:23.353625 # ok 1170 # SKIP Get and set data for VL 6240
7066 12:28:23.354030 # ok 1171 Set VL 6256
7067 12:28:23.356968 # ok 1172 # SKIP Disabled ZA for VL 6256
7068 12:28:23.357359 # ok 1173 # SKIP Get and set data for VL 6256
7069 12:28:23.357520 # ok 1174 Set VL 6272
7070 12:28:23.357644 # ok 1175 # SKIP Disabled ZA for VL 6272
7071 12:28:23.358373 # ok 1176 # SKIP Get and set data for VL 6272
7072 12:28:23.358483 # ok 1177 Set VL 6288
7073 12:28:23.358771 # ok 1178 # SKIP Disabled ZA for VL 6288
7074 12:28:23.358875 # ok 1179 # SKIP Get and set data for VL 6288
7075 12:28:23.358966 # ok 1180 Set VL 6304
7076 12:28:23.359112 # ok 1181 # SKIP Disabled ZA for VL 6304
7077 12:28:23.359243 # ok 1182 # SKIP Get and set data for VL 6304
7078 12:28:23.359372 # ok 1183 Set VL 6320
7079 12:28:23.359522 # ok 1184 # SKIP Disabled ZA for VL 6320
7080 12:28:23.359656 # ok 1185 # SKIP Get and set data for VL 6320
7081 12:28:23.359779 # ok 1186 Set VL 6336
7082 12:28:23.359927 # ok 1187 # SKIP Disabled ZA for VL 6336
7083 12:28:23.360060 # ok 1188 # SKIP Get and set data for VL 6336
7084 12:28:23.360209 # ok 1189 Set VL 6352
7085 12:28:23.360339 # ok 1190 # SKIP Disabled ZA for VL 6352
7086 12:28:23.360489 # ok 1191 # SKIP Get and set data for VL 6352
7087 12:28:23.360642 # ok 1192 Set VL 6368
7088 12:28:23.360792 # ok 1193 # SKIP Disabled ZA for VL 6368
7089 12:28:23.361176 # ok 1194 # SKIP Get and set data for VL 6368
7090 12:28:23.361281 # ok 1195 Set VL 6384
7091 12:28:23.361380 # ok 1196 # SKIP Disabled ZA for VL 6384
7092 12:28:23.366168 # ok 1197 # SKIP Get and set data for VL 6384
7093 12:28:23.366415 # ok 1198 Set VL 6400
7094 12:28:23.366779 # ok 1199 # SKIP Disabled ZA for VL 6400
7095 12:28:23.367042 # ok 1200 # SKIP Get and set data for VL 6400
7096 12:28:23.367277 # ok 1201 Set VL 6416
7097 12:28:23.367555 # ok 1202 # SKIP Disabled ZA for VL 6416
7098 12:28:23.367817 # ok 1203 # SKIP Get and set data for VL 6416
7099 12:28:23.367998 # ok 1204 Set VL 6432
7100 12:28:23.368188 # ok 1205 # SKIP Disabled ZA for VL 6432
7101 12:28:23.368350 # ok 1206 # SKIP Get and set data for VL 6432
7102 12:28:23.368504 # ok 1207 Set VL 6448
7103 12:28:23.368653 # ok 1208 # SKIP Disabled ZA for VL 6448
7104 12:28:23.368821 # ok 1209 # SKIP Get and set data for VL 6448
7105 12:28:23.368989 # ok 1210 Set VL 6464
7106 12:28:23.369153 # ok 1211 # SKIP Disabled ZA for VL 6464
7107 12:28:23.369333 # ok 1212 # SKIP Get and set data for VL 6464
7108 12:28:23.369499 # ok 1213 Set VL 6480
7109 12:28:23.369658 # ok 1214 # SKIP Disabled ZA for VL 6480
7110 12:28:23.369808 # ok 1215 # SKIP Get and set data for VL 6480
7111 12:28:23.369956 # ok 1216 Set VL 6496
7112 12:28:23.370081 # ok 1217 # SKIP Disabled ZA for VL 6496
7113 12:28:23.370196 # ok 1218 # SKIP Get and set data for VL 6496
7114 12:28:23.370340 # ok 1219 Set VL 6512
7115 12:28:23.370459 # ok 1220 # SKIP Disabled ZA for VL 6512
7116 12:28:23.370573 # ok 1221 # SKIP Get and set data for VL 6512
7117 12:28:23.370684 # ok 1222 Set VL 6528
7118 12:28:23.370800 # ok 1223 # SKIP Disabled ZA for VL 6528
7119 12:28:23.370918 # ok 1224 # SKIP Get and set data for VL 6528
7120 12:28:23.371037 # ok 1225 Set VL 6544
7121 12:28:23.371152 # ok 1226 # SKIP Disabled ZA for VL 6544
7122 12:28:23.371271 # ok 1227 # SKIP Get and set data for VL 6544
7123 12:28:23.371390 # ok 1228 Set VL 6560
7124 12:28:23.371502 # ok 1229 # SKIP Disabled ZA for VL 6560
7125 12:28:23.379717 # ok 1230 # SKIP Get and set data for VL 6560
7126 12:28:23.379962 # ok 1231 Set VL 6576
7127 12:28:23.380270 # ok 1232 # SKIP Disabled ZA for VL 6576
7128 12:28:23.380377 # ok 1233 # SKIP Get and set data for VL 6576
7129 12:28:23.380467 # ok 1234 Set VL 6592
7130 12:28:23.380557 # ok 1235 # SKIP Disabled ZA for VL 6592
7131 12:28:23.380849 # ok 1236 # SKIP Get and set data for VL 6592
7132 12:28:23.380954 # ok 1237 Set VL 6608
7133 12:28:23.381088 # ok 1238 # SKIP Disabled ZA for VL 6608
7134 12:28:23.381190 # ok 1239 # SKIP Get and set data for VL 6608
7135 12:28:23.381281 # ok 1240 Set VL 6624
7136 12:28:23.381368 # ok 1241 # SKIP Disabled ZA for VL 6624
7137 12:28:23.381431 # ok 1242 # SKIP Get and set data for VL 6624
7138 12:28:23.381489 # ok 1243 Set VL 6640
7139 12:28:23.381548 # ok 1244 # SKIP Disabled ZA for VL 6640
7140 12:28:23.387886 # ok 1245 # SKIP Get and set data for VL 6640
7141 12:28:23.388185 # ok 1246 Set VL 6656
7142 12:28:23.388365 # ok 1247 # SKIP Disabled ZA for VL 6656
7143 12:28:23.388747 # ok 1248 # SKIP Get and set data for VL 6656
7144 12:28:23.388854 # ok 1249 Set VL 6672
7145 12:28:23.388942 # ok 1250 # SKIP Disabled ZA for VL 6672
7146 12:28:23.389025 # ok 1251 # SKIP Get and set data for VL 6672
7147 12:28:23.389108 # ok 1252 Set VL 6688
7148 12:28:23.389196 # ok 1253 # SKIP Disabled ZA for VL 6688
7149 12:28:23.389276 # ok 1254 # SKIP Get and set data for VL 6688
7150 12:28:23.389358 # ok 1255 Set VL 6704
7151 12:28:23.389441 # ok 1256 # SKIP Disabled ZA for VL 6704
7152 12:28:23.389545 # ok 1257 # SKIP Get and set data for VL 6704
7153 12:28:23.389633 # ok 1258 Set VL 6720
7154 12:28:23.389728 # ok 1259 # SKIP Disabled ZA for VL 6720
7155 12:28:23.389814 # ok 1260 # SKIP Get and set data for VL 6720
7156 12:28:23.389904 # ok 1261 Set VL 6736
7157 12:28:23.395252 # ok 1262 # SKIP Disabled ZA for VL 6736
7158 12:28:23.395495 # ok 1263 # SKIP Get and set data for VL 6736
7159 12:28:23.395610 # ok 1264 Set VL 6752
7160 12:28:23.395965 # ok 1265 # SKIP Disabled ZA for VL 6752
7161 12:28:23.396075 # ok 1266 # SKIP Get and set data for VL 6752
7162 12:28:23.396170 # ok 1267 Set VL 6768
7163 12:28:23.396257 # ok 1268 # SKIP Disabled ZA for VL 6768
7164 12:28:23.396340 # ok 1269 # SKIP Get and set data for VL 6768
7165 12:28:23.396432 # ok 1270 Set VL 6784
7166 12:28:23.396523 # ok 1271 # SKIP Disabled ZA for VL 6784
7167 12:28:23.396847 # ok 1272 # SKIP Get and set data for VL 6784
7168 12:28:23.397008 # ok 1273 Set VL 6800
7169 12:28:23.397135 # ok 1274 # SKIP Disabled ZA for VL 6800
7170 12:28:23.397255 # ok 1275 # SKIP Get and set data for VL 6800
7171 12:28:23.397372 # ok 1276 Set VL 6816
7172 12:28:23.397490 # ok 1277 # SKIP Disabled ZA for VL 6816
7173 12:28:23.404065 # ok 1278 # SKIP Get and set data for VL 6816
7174 12:28:23.404601 # ok 1279 Set VL 6832
7175 12:28:23.404757 # ok 1280 # SKIP Disabled ZA for VL 6832
7176 12:28:23.404865 # ok 1281 # SKIP Get and set data for VL 6832
7177 12:28:23.404954 # ok 1282 Set VL 6848
7178 12:28:23.405040 # ok 1283 # SKIP Disabled ZA for VL 6848
7179 12:28:23.405131 # ok 1284 # SKIP Get and set data for VL 6848
7180 12:28:23.405237 # ok 1285 Set VL 6864
7181 12:28:23.405321 # ok 1286 # SKIP Disabled ZA for VL 6864
7182 12:28:23.405406 # ok 1287 # SKIP Get and set data for VL 6864
7183 12:28:23.405490 # ok 1288 Set VL 6880
7184 12:28:23.405572 # ok 1289 # SKIP Disabled ZA for VL 6880
7185 12:28:23.405667 # ok 1290 # SKIP Get and set data for VL 6880
7186 12:28:23.405755 # ok 1291 Set VL 6896
7187 12:28:23.405858 # ok 1292 # SKIP Disabled ZA for VL 6896
7188 12:28:23.414509 # ok 1293 # SKIP Get and set data for VL 6896
7189 12:28:23.414748 # ok 1294 Set VL 6912
7190 12:28:23.414836 # ok 1295 # SKIP Disabled ZA for VL 6912
7191 12:28:23.414924 # ok 1296 # SKIP Get and set data for VL 6912
7192 12:28:23.415049 # ok 1297 Set VL 6928
7193 12:28:23.415160 # ok 1298 # SKIP Disabled ZA for VL 6928
7194 12:28:23.415267 # ok 1299 # SKIP Get and set data for VL 6928
7195 12:28:23.415371 # ok 1300 Set VL 6944
7196 12:28:23.415465 # ok 1301 # SKIP Disabled ZA for VL 6944
7197 12:28:23.415564 # ok 1302 # SKIP Get and set data for VL 6944
7198 12:28:23.415647 # ok 1303 Set VL 6960
7199 12:28:23.415732 # ok 1304 # SKIP Disabled ZA for VL 6960
7200 12:28:23.415821 # ok 1305 # SKIP Get and set data for VL 6960
7201 12:28:23.415932 # ok 1306 Set VL 6976
7202 12:28:23.416058 # ok 1307 # SKIP Disabled ZA for VL 6976
7203 12:28:23.416147 # ok 1308 # SKIP Get and set data for VL 6976
7204 12:28:23.416243 # ok 1309 Set VL 6992
7205 12:28:23.416353 # ok 1310 # SKIP Disabled ZA for VL 6992
7206 12:28:23.416459 # ok 1311 # SKIP Get and set data for VL 6992
7207 12:28:23.416558 # ok 1312 Set VL 7008
7208 12:28:23.416665 # ok 1313 # SKIP Disabled ZA for VL 7008
7209 12:28:23.416758 # ok 1314 # SKIP Get and set data for VL 7008
7210 12:28:23.416867 # ok 1315 Set VL 7024
7211 12:28:23.416970 # ok 1316 # SKIP Disabled ZA for VL 7024
7212 12:28:23.417068 # ok 1317 # SKIP Get and set data for VL 7024
7213 12:28:23.417165 # ok 1318 Set VL 7040
7214 12:28:23.417286 # ok 1319 # SKIP Disabled ZA for VL 7040
7215 12:28:23.417373 # ok 1320 # SKIP Get and set data for VL 7040
7216 12:28:23.417450 # ok 1321 Set VL 7056
7217 12:28:23.417522 # ok 1322 # SKIP Disabled ZA for VL 7056
7218 12:28:23.417594 # ok 1323 # SKIP Get and set data for VL 7056
7219 12:28:23.418096 # ok 1324 Set VL 7072
7220 12:28:23.426344 # ok 1325 # SKIP Disabled ZA for VL 7072
7221 12:28:23.426595 # ok 1326 # SKIP Get and set data for VL 7072
7222 12:28:23.426902 # ok 1327 Set VL 7088
7223 12:28:23.427000 # ok 1328 # SKIP Disabled ZA for VL 7088
7224 12:28:23.427160 # ok 1329 # SKIP Get and set data for VL 7088
7225 12:28:23.427346 # ok 1330 Set VL 7104
7226 12:28:23.427527 # ok 1331 # SKIP Disabled ZA for VL 7104
7227 12:28:23.427731 # ok 1332 # SKIP Get and set data for VL 7104
7228 12:28:23.427871 # ok 1333 Set VL 7120
7229 12:28:23.428013 # ok 1334 # SKIP Disabled ZA for VL 7120
7230 12:28:23.428193 # ok 1335 # SKIP Get and set data for VL 7120
7231 12:28:23.428328 # ok 1336 Set VL 7136
7232 12:28:23.428471 # ok 1337 # SKIP Disabled ZA for VL 7136
7233 12:28:23.428613 # ok 1338 # SKIP Get and set data for VL 7136
7234 12:28:23.428754 # ok 1339 Set VL 7152
7235 12:28:23.428943 # ok 1340 # SKIP Disabled ZA for VL 7152
7236 12:28:23.429108 # ok 1341 # SKIP Get and set data for VL 7152
7237 12:28:23.429270 # ok 1342 Set VL 7168
7238 12:28:23.429399 # ok 1343 # SKIP Disabled ZA for VL 7168
7239 12:28:23.429545 # ok 1344 # SKIP Get and set data for VL 7168
7240 12:28:23.429690 # ok 1345 Set VL 7184
7241 12:28:23.429890 # ok 1346 # SKIP Disabled ZA for VL 7184
7242 12:28:23.430035 # ok 1347 # SKIP Get and set data for VL 7184
7243 12:28:23.430181 # ok 1348 Set VL 7200
7244 12:28:23.430322 # ok 1349 # SKIP Disabled ZA for VL 7200
7245 12:28:23.430464 # ok 1350 # SKIP Get and set data for VL 7200
7246 12:28:23.430606 # ok 1351 Set VL 7216
7247 12:28:23.430746 # ok 1352 # SKIP Disabled ZA for VL 7216
7248 12:28:23.430887 # ok 1353 # SKIP Get and set data for VL 7216
7249 12:28:23.431028 # ok 1354 Set VL 7232
7250 12:28:23.442401 # ok 1355 # SKIP Disabled ZA for VL 7232
7251 12:28:23.443208 # ok 1356 # SKIP Get and set data for VL 7232
7252 12:28:23.443435 # ok 1357 Set VL 7248
7253 12:28:23.443656 # ok 1358 # SKIP Disabled ZA for VL 7248
7254 12:28:23.443871 # ok 1359 # SKIP Get and set data for VL 7248
7255 12:28:23.444092 # ok 1360 Set VL 7264
7256 12:28:23.444306 # ok 1361 # SKIP Disabled ZA for VL 7264
7257 12:28:23.444525 # ok 1362 # SKIP Get and set data for VL 7264
7258 12:28:23.444725 # ok 1363 Set VL 7280
7259 12:28:23.444913 # ok 1364 # SKIP Disabled ZA for VL 7280
7260 12:28:23.445094 # ok 1365 # SKIP Get and set data for VL 7280
7261 12:28:23.445349 # ok 1366 Set VL 7296
7262 12:28:23.445486 # ok 1367 # SKIP Disabled ZA for VL 7296
7263 12:28:23.445606 # ok 1368 # SKIP Get and set data for VL 7296
7264 12:28:23.445799 # ok 1369 Set VL 7312
7265 12:28:23.445996 # ok 1370 # SKIP Disabled ZA for VL 7312
7266 12:28:23.446174 # ok 1371 # SKIP Get and set data for VL 7312
7267 12:28:23.446319 # ok 1372 Set VL 7328
7268 12:28:23.446462 # ok 1373 # SKIP Disabled ZA for VL 7328
7269 12:28:23.446604 # ok 1374 # SKIP Get and set data for VL 7328
7270 12:28:23.446747 # ok 1375 Set VL 7344
7271 12:28:23.446887 # ok 1376 # SKIP Disabled ZA for VL 7344
7272 12:28:23.447028 # ok 1377 # SKIP Get and set data for VL 7344
7273 12:28:23.447170 # ok 1378 Set VL 7360
7274 12:28:23.447312 # ok 1379 # SKIP Disabled ZA for VL 7360
7275 12:28:23.447453 # ok 1380 # SKIP Get and set data for VL 7360
7276 12:28:23.447594 # ok 1381 Set VL 7376
7277 12:28:23.447735 # ok 1382 # SKIP Disabled ZA for VL 7376
7278 12:28:23.447877 # ok 1383 # SKIP Get and set data for VL 7376
7279 12:28:23.448017 # ok 1384 Set VL 7392
7280 12:28:23.454501 # ok 1385 # SKIP Disabled ZA for VL 7392
7281 12:28:23.454845 # ok 1386 # SKIP Get and set data for VL 7392
7282 12:28:23.455300 # ok 1387 Set VL 7408
7283 12:28:23.455406 # ok 1388 # SKIP Disabled ZA for VL 7408
7284 12:28:23.455500 # ok 1389 # SKIP Get and set data for VL 7408
7285 12:28:23.455587 # ok 1390 Set VL 7424
7286 12:28:23.455672 # ok 1391 # SKIP Disabled ZA for VL 7424
7287 12:28:23.455757 # ok 1392 # SKIP Get and set data for VL 7424
7288 12:28:23.455842 # ok 1393 Set VL 7440
7289 12:28:23.455943 # ok 1394 # SKIP Disabled ZA for VL 7440
7290 12:28:23.456032 # ok 1395 # SKIP Get and set data for VL 7440
7291 12:28:23.456119 # ok 1396 Set VL 7456
7292 12:28:23.456208 # ok 1397 # SKIP Disabled ZA for VL 7456
7293 12:28:23.456298 # ok 1398 # SKIP Get and set data for VL 7456
7294 12:28:23.456400 # ok 1399 Set VL 7472
7295 12:28:23.456490 # ok 1400 # SKIP Disabled ZA for VL 7472
7296 12:28:23.456592 # ok 1401 # SKIP Get and set data for VL 7472
7297 12:28:23.456679 # ok 1402 Set VL 7488
7298 12:28:23.457034 # ok 1403 # SKIP Disabled ZA for VL 7488
7299 12:28:23.457145 # ok 1404 # SKIP Get and set data for VL 7488
7300 12:28:23.457232 # ok 1405 Set VL 7504
7301 12:28:23.457325 # ok 1406 # SKIP Disabled ZA for VL 7504
7302 12:28:23.457400 # ok 1407 # SKIP Get and set data for VL 7504
7303 12:28:23.457472 # ok 1408 Set VL 7520
7304 12:28:23.457544 # ok 1409 # SKIP Disabled ZA for VL 7520
7305 12:28:23.462725 # ok 1410 # SKIP Get and set data for VL 7520
7306 12:28:23.463055 # ok 1411 Set VL 7536
7307 12:28:23.463445 # ok 1412 # SKIP Disabled ZA for VL 7536
7308 12:28:23.463550 # ok 1413 # SKIP Get and set data for VL 7536
7309 12:28:23.463638 # ok 1414 Set VL 7552
7310 12:28:23.463722 # ok 1415 # SKIP Disabled ZA for VL 7552
7311 12:28:23.463808 # ok 1416 # SKIP Get and set data for VL 7552
7312 12:28:23.463893 # ok 1417 Set VL 7568
7313 12:28:23.463996 # ok 1418 # SKIP Disabled ZA for VL 7568
7314 12:28:23.464081 # ok 1419 # SKIP Get and set data for VL 7568
7315 12:28:23.464170 # ok 1420 Set VL 7584
7316 12:28:23.464275 # ok 1421 # SKIP Disabled ZA for VL 7584
7317 12:28:23.464364 # ok 1422 # SKIP Get and set data for VL 7584
7318 12:28:23.464655 # ok 1423 Set VL 7600
7319 12:28:23.464757 # ok 1424 # SKIP Disabled ZA for VL 7600
7320 12:28:23.464844 # ok 1425 # SKIP Get and set data for VL 7600
7321 12:28:23.464931 # ok 1426 Set VL 7616
7322 12:28:23.465030 # ok 1427 # SKIP Disabled ZA for VL 7616
7323 12:28:23.465118 # ok 1428 # SKIP Get and set data for VL 7616
7324 12:28:23.465211 # ok 1429 Set VL 7632
7325 12:28:23.465297 # ok 1430 # SKIP Disabled ZA for VL 7632
7326 12:28:23.470333 # ok 1431 # SKIP Get and set data for VL 7632
7327 12:28:23.470810 # ok 1432 Set VL 7648
7328 12:28:23.470914 # ok 1433 # SKIP Disabled ZA for VL 7648
7329 12:28:23.471004 # ok 1434 # SKIP Get and set data for VL 7648
7330 12:28:23.471090 # ok 1435 Set VL 7664
7331 12:28:23.471176 # ok 1436 # SKIP Disabled ZA for VL 7664
7332 12:28:23.471269 # ok 1437 # SKIP Get and set data for VL 7664
7333 12:28:23.471371 # ok 1438 Set VL 7680
7334 12:28:23.471461 # ok 1439 # SKIP Disabled ZA for VL 7680
7335 12:28:23.471550 # ok 1440 # SKIP Get and set data for VL 7680
7336 12:28:23.471638 # ok 1441 Set VL 7696
7337 12:28:23.471740 # ok 1442 # SKIP Disabled ZA for VL 7696
7338 12:28:23.471824 # ok 1443 # SKIP Get and set data for VL 7696
7339 12:28:23.471910 # ok 1444 Set VL 7712
7340 12:28:23.472011 # ok 1445 # SKIP Disabled ZA for VL 7712
7341 12:28:23.472098 # ok 1446 # SKIP Get and set data for VL 7712
7342 12:28:23.472199 # ok 1447 Set VL 7728
7343 12:28:23.472289 # ok 1448 # SKIP Disabled ZA for VL 7728
7344 12:28:23.472388 # ok 1449 # SKIP Get and set data for VL 7728
7345 12:28:23.472473 # ok 1450 Set VL 7744
7346 12:28:23.472572 # ok 1451 # SKIP Disabled ZA for VL 7744
7347 12:28:23.472670 # ok 1452 # SKIP Get and set data for VL 7744
7348 12:28:23.472756 # ok 1453 Set VL 7760
7349 12:28:23.472853 # ok 1454 # SKIP Disabled ZA for VL 7760
7350 12:28:23.472961 # ok 1455 # SKIP Get and set data for VL 7760
7351 12:28:23.473061 # ok 1456 Set VL 7776
7352 12:28:23.473377 # ok 1457 # SKIP Disabled ZA for VL 7776
7353 12:28:23.492879 # ok 1458 # SKIP Get and set data for VL 7776
7354 12:28:23.493222 # ok 1459 Set VL 7792
7355 12:28:23.493363 # ok 1460 # SKIP Disabled ZA for VL 7792
7356 12:28:23.493715 # ok 1461 # SKIP Get and set data for VL 7792
7357 12:28:23.493822 # ok 1462 Set VL 7808
7358 12:28:23.493913 # ok 1463 # SKIP Disabled ZA for VL 7808
7359 12:28:23.493999 # ok 1464 # SKIP Get and set data for VL 7808
7360 12:28:23.494084 # ok 1465 Set VL 7824
7361 12:28:23.494185 # ok 1466 # SKIP Disabled ZA for VL 7824
7362 12:28:23.494275 # ok 1467 # SKIP Get and set data for VL 7824
7363 12:28:23.494366 # ok 1468 Set VL 7840
7364 12:28:23.494451 # ok 1469 # SKIP Disabled ZA for VL 7840
7365 12:28:23.494554 # ok 1470 # SKIP Get and set data for VL 7840
7366 12:28:23.494639 # ok 1471 Set VL 7856
7367 12:28:23.494727 # ok 1472 # SKIP Disabled ZA for VL 7856
7368 12:28:23.494814 # ok 1473 # SKIP Get and set data for VL 7856
7369 12:28:23.494917 # ok 1474 Set VL 7872
7370 12:28:23.495005 # ok 1475 # SKIP Disabled ZA for VL 7872
7371 12:28:23.495089 # ok 1476 # SKIP Get and set data for VL 7872
7372 12:28:23.495173 # ok 1477 Set VL 7888
7373 12:28:23.495257 # ok 1478 # SKIP Disabled ZA for VL 7888
7374 12:28:23.495360 # ok 1479 # SKIP Get and set data for VL 7888
7375 12:28:23.495454 # ok 1480 Set VL 7904
7376 12:28:23.495540 # ok 1481 # SKIP Disabled ZA for VL 7904
7377 12:28:23.495631 # ok 1482 # SKIP Get and set data for VL 7904
7378 12:28:23.495734 # ok 1483 Set VL 7920
7379 12:28:23.495821 # ok 1484 # SKIP Disabled ZA for VL 7920
7380 12:28:23.495905 # ok 1485 # SKIP Get and set data for VL 7920
7381 12:28:23.496005 # ok 1486 Set VL 7936
7382 12:28:23.496089 # ok 1487 # SKIP Disabled ZA for VL 7936
7383 12:28:23.496172 # ok 1488 # SKIP Get and set data for VL 7936
7384 12:28:23.496270 # ok 1489 Set VL 7952
7385 12:28:23.496372 # ok 1490 # SKIP Disabled ZA for VL 7952
7386 12:28:23.496471 # ok 1491 # SKIP Get and set data for VL 7952
7387 12:28:23.496574 # ok 1492 Set VL 7968
7388 12:28:23.496672 # ok 1493 # SKIP Disabled ZA for VL 7968
7389 12:28:23.497087 # ok 1494 # SKIP Get and set data for VL 7968
7390 12:28:23.497192 # ok 1495 Set VL 7984
7391 12:28:23.497275 # ok 1496 # SKIP Disabled ZA for VL 7984
7392 12:28:23.497352 # ok 1497 # SKIP Get and set data for VL 7984
7393 12:28:23.497444 # ok 1498 Set VL 8000
7394 12:28:23.497761 # ok 1499 # SKIP Disabled ZA for VL 8000
7395 12:28:23.497920 # ok 1500 # SKIP Get and set data for VL 8000
7396 12:28:23.498191 # ok 1501 Set VL 8016
7397 12:28:23.498278 # ok 1502 # SKIP Disabled ZA for VL 8016
7398 12:28:23.499030 # ok 1503 # SKIP Get and set data for VL 8016
7399 12:28:23.499567 # ok 1504 Set VL 8032
7400 12:28:23.499821 # ok 1505 # SKIP Disabled ZA for VL 8032
7401 12:28:23.500048 # ok 1506 # SKIP Get and set data for VL 8032
7402 12:28:23.500145 # ok 1507 Set VL 8048
7403 12:28:23.500255 # ok 1508 # SKIP Disabled ZA for VL 8048
7404 12:28:23.500353 # ok 1509 # SKIP Get and set data for VL 8048
7405 12:28:23.500440 # ok 1510 Set VL 8064
7406 12:28:23.500526 # ok 1511 # SKIP Disabled ZA for VL 8064
7407 12:28:23.500627 # ok 1512 # SKIP Get and set data for VL 8064
7408 12:28:23.500717 # ok 1513 Set VL 8080
7409 12:28:23.500819 # ok 1514 # SKIP Disabled ZA for VL 8080
7410 12:28:23.500923 # ok 1515 # SKIP Get and set data for VL 8080
7411 12:28:23.501011 # ok 1516 Set VL 8096
7412 12:28:23.501112 # ok 1517 # SKIP Disabled ZA for VL 8096
7413 12:28:23.501207 # ok 1518 # SKIP Get and set data for VL 8096
7414 12:28:23.501751 # ok 1519 Set VL 8112
7415 12:28:23.502191 # ok 1520 # SKIP Disabled ZA for VL 8112
7416 12:28:23.502385 # ok 1521 # SKIP Get and set data for VL 8112
7417 12:28:23.502563 # ok 1522 Set VL 8128
7418 12:28:23.502719 # ok 1523 # SKIP Disabled ZA for VL 8128
7419 12:28:23.502861 # ok 1524 # SKIP Get and set data for VL 8128
7420 12:28:23.503041 # ok 1525 Set VL 8144
7421 12:28:23.503191 # ok 1526 # SKIP Disabled ZA for VL 8144
7422 12:28:23.503332 # ok 1527 # SKIP Get and set data for VL 8144
7423 12:28:23.503487 # ok 1528 Set VL 8160
7424 12:28:23.503634 # ok 1529 # SKIP Disabled ZA for VL 8160
7425 12:28:23.503780 # ok 1530 # SKIP Get and set data for VL 8160
7426 12:28:23.503929 # ok 1531 Set VL 8176
7427 12:28:23.504082 # ok 1532 # SKIP Disabled ZA for VL 8176
7428 12:28:23.504203 # ok 1533 # SKIP Get and set data for VL 8176
7429 12:28:23.504318 # ok 1534 Set VL 8192
7430 12:28:23.504431 # ok 1535 # SKIP Disabled ZA for VL 8192
7431 12:28:23.504546 # ok 1536 # SKIP Get and set data for VL 8192
7432 12:28:23.504660 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7433 12:28:23.504776 ok 34 selftests: arm64: za-ptrace
7434 12:28:23.504892 # selftests: arm64: check_buffer_fill
7435 12:28:23.969351 # 1..20
7436 12:28:23.970875 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7437 12:28:23.971236 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7438 12:28:23.971571 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7439 12:28:23.971765 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7440 12:28:23.971876 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7441 12:28:23.972183 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7442 12:28:23.972289 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 12:28:23.972585 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7444 12:28:23.972690 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7445 12:28:23.972799 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7446 12:28:23.973104 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7447 12:28:23.973231 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7448 12:28:23.975307 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7449 12:28:23.975681 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7450 12:28:23.975793 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7451 12:28:23.975991 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7452 12:28:23.976315 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7453 12:28:23.976553 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7454 12:28:23.976799 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7455 12:28:23.976985 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7456 12:28:23.977147 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7457 12:28:23.992548 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7458 12:28:24.102420 # selftests: arm64: check_child_memory
7459 12:28:24.613345 # 1..12
7460 12:28:24.619156 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7461 12:28:24.619735 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7462 12:28:24.619852 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7463 12:28:24.619944 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7464 12:28:24.620048 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7465 12:28:24.620415 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7466 12:28:24.620526 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7467 12:28:24.620633 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7468 12:28:24.620987 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7469 12:28:24.621298 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7470 12:28:24.623141 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7471 12:28:24.623514 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7472 12:28:24.623620 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7473 12:28:24.637034 not ok 36 selftests: arm64: check_child_memory # exit=1
7474 12:28:24.747845 # selftests: arm64: check_gcr_el1_cswitch
7475 12:29:10.077343 <47>[ 99.432893] systemd-journald[109]: Sent WATCHDOG=1 notification.
7476 12:29:10.456982 <47>[ 99.814122] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3308 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
7477 12:29:10.457451 <47>[ 99.814713] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7478 12:29:10.457764 <47>[ 99.815099] systemd-journald[109]: Rotating...
7479 12:29:10.487414 <47>[ 99.844722] systemd-journald[109]: Reserving 333 entries in field hash table.
7480 12:29:10.538523 <47>[ 99.895861] systemd-journald[109]: Reserving 4408 entries in data hash table.
7481 12:29:10.542077 <47>[ 99.899474] systemd-journald[109]: Vacuuming...
7482 12:29:10.561676 <47>[ 99.918801] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7483 12:29:11.023171 # 1..1
7484 12:29:11.023523 # 1..1
7485 12:29:11.023701 # 1..1
7486 12:29:11.023860 # 1..1
7487 12:29:11.023989 # 1..1
7488 12:29:11.024107 # 1..1
7489 12:29:11.024222 # 1..1
7490 12:29:11.024336 # 1..1
7491 12:29:11.024452 # 1..1
7492 12:29:11.024568 # 1..1
7493 12:29:11.024683 # 1..1
7494 12:29:11.025029 # 1..1
7495 12:29:11.025158 # 1..1
7496 12:29:11.025276 # 1..1
7497 12:29:11.025391 # 1..1
7498 12:29:11.025506 # 1..1
7499 12:29:11.025620 # 1..1
7500 12:29:11.025792 # 1..1
7501 12:29:11.025925 # 1..1
7502 12:29:11.026042 # 1..1
7503 12:29:11.026157 # 1..1
7504 12:29:11.026270 # 1..1
7505 12:29:11.026399 # 1..1
7506 12:29:11.026516 # 1..1
7507 12:29:11.026631 # 1..1
7508 12:29:11.026746 # 1..1
7509 12:29:11.026860 # 1..1
7510 12:29:11.026974 # 1..1
7511 12:29:11.027089 # 1..1
7512 12:29:11.027203 # 1..1
7513 12:29:11.027318 # 1..1
7514 12:29:11.027431 # 1..1
7515 12:29:11.027546 # 1..1
7516 12:29:11.027660 # 1..1
7517 12:29:11.027774 # 1..1
7518 12:29:11.027888 # 1..1
7519 12:29:11.028003 # 1..1
7520 12:29:11.028116 # 1..1
7521 12:29:11.028231 # 1..1
7522 12:29:11.028344 # 1..1
7523 12:29:11.028458 # 1..1
7524 12:29:11.028571 # 1..1
7525 12:29:11.028685 # 1..1
7526 12:29:11.028799 # 1..1
7527 12:29:11.028912 # 1..1
7528 12:29:11.058358 # 1..1
7529 12:29:11.058685 # 1..1
7530 12:29:11.058863 # 1..1
7531 12:29:11.059036 # 1..1
7532 12:29:11.059206 # 1..1
7533 12:29:11.059346 # 1..1
7534 12:29:11.059489 # 1..1
7535 12:29:11.059847 # 1..1
7536 12:29:11.059987 # 1..1
7537 12:29:11.060121 # 1..1
7538 12:29:11.060240 # 1..1
7539 12:29:11.060354 # 1..1
7540 12:29:11.060469 # 1..1
7541 12:29:11.060583 # 1..1
7542 12:29:11.060697 # 1..1
7543 12:29:11.060812 # 1..1
7544 12:29:11.060926 # 1..1
7545 12:29:11.061040 # 1..1
7546 12:29:11.061154 # 1..1
7547 12:29:11.061268 # 1..1
7548 12:29:11.061382 # 1..1
7549 12:29:11.061496 # 1..1
7550 12:29:11.061610 # 1..1
7551 12:29:11.061739 # 1..1
7552 12:29:11.061853 # 1..1
7553 12:29:11.061967 # 1..1
7554 12:29:11.062079 # 1..1
7555 12:29:11.062191 # 1..1
7556 12:29:11.062304 # 1..1
7557 12:29:11.062416 # 1..1
7558 12:29:11.062531 # 1..1
7559 12:29:11.062644 # 1..1
7560 12:29:11.062756 # 1..1
7561 12:29:11.062869 # 1..1
7562 12:29:11.062980 # 1..1
7563 12:29:11.063092 # 1..1
7564 12:29:11.063203 # 1..1
7565 12:29:11.063315 # 1..1
7566 12:29:11.063426 # 1..1
7567 12:29:11.063541 # 1..1
7568 12:29:11.063652 # 1..1
7569 12:29:11.063764 # 1..1
7570 12:29:11.063877 # 1..1
7571 12:29:11.063989 # 1..1
7572 12:29:11.064102 # 1..1
7573 12:29:11.064214 # 1..1
7574 12:29:11.064327 # 1..1
7575 12:29:11.064440 # 1..1
7576 12:29:11.064553 # 1..1
7577 12:29:11.064664 # 1..1
7578 12:29:11.064775 # 1..1
7579 12:29:11.064886 # 1..1
7580 12:29:11.064999 # 1..1
7581 12:29:11.065110 # 1..1
7582 12:29:11.065222 # 1..1
7583 12:29:11.065334 # 1..1
7584 12:29:11.065445 # 1..1
7585 12:29:11.065558 # 1..1
7586 12:29:11.065683 # 1..1
7587 12:29:11.065798 # 1..1
7588 12:29:11.065910 # 1..1
7589 12:29:11.066022 # 1..1
7590 12:29:11.066133 # 1..1
7591 12:29:11.066244 # 1..1
7592 12:29:11.066356 # 1..1
7593 12:29:11.066508 # 1..1
7594 12:29:11.066626 # 1..1
7595 12:29:11.066739 # 1..1
7596 12:29:11.066851 # 1..1
7597 12:29:11.066962 # 1..1
7598 12:29:11.067074 # 1..1
7599 12:29:11.067185 # 1..1
7600 12:29:11.074949 # 1..1
7601 12:29:11.075293 # 1..1
7602 12:29:11.075495 # 1..1
7603 12:29:11.075666 # 1..1
7604 12:29:11.075799 # 1..1
7605 12:29:11.075955 # 1..1
7606 12:29:11.076084 # 1..1
7607 12:29:11.076198 # 1..1
7608 12:29:11.076308 # 1..1
7609 12:29:11.076419 # 1..1
7610 12:29:11.076531 # 1..1
7611 12:29:11.076883 # 1..1
7612 12:29:11.077048 # 1..1
7613 12:29:11.077177 # 1..1
7614 12:29:11.077295 # 1..1
7615 12:29:11.077409 # 1..1
7616 12:29:11.077524 # 1..1
7617 12:29:11.077642 # 1..1
7618 12:29:11.077816 # 1..1
7619 12:29:11.077938 # 1..1
7620 12:29:11.078052 # 1..1
7621 12:29:11.078165 # 1..1
7622 12:29:11.078276 # 1..1
7623 12:29:11.078388 # 1..1
7624 12:29:11.078500 # 1..1
7625 12:29:11.078628 # 1..1
7626 12:29:11.078745 # 1..1
7627 12:29:11.078860 # 1..1
7628 12:29:11.078974 # 1..1
7629 12:29:11.079087 # 1..1
7630 12:29:11.079202 # 1..1
7631 12:29:11.079316 # 1..1
7632 12:29:11.079430 # 1..1
7633 12:29:11.079546 # 1..1
7634 12:29:11.079662 # 1..1
7635 12:29:11.079777 # 1..1
7636 12:29:11.079891 # 1..1
7637 12:29:11.080006 # 1..1
7638 12:29:11.080121 # 1..1
7639 12:29:11.080235 # 1..1
7640 12:29:11.080350 # 1..1
7641 12:29:11.080464 # 1..1
7642 12:29:11.080580 # 1..1
7643 12:29:11.080696 # 1..1
7644 12:29:11.080810 # 1..1
7645 12:29:11.080923 # 1..1
7646 12:29:11.081038 # 1..1
7647 12:29:11.081155 # 1..1
7648 12:29:11.089184 # 1..1
7649 12:29:11.089474 # 1..1
7650 12:29:11.089621 # 1..1
7651 12:29:11.089761 # 1..1
7652 12:29:11.089879 # 1..1
7653 12:29:11.089996 # 1..1
7654 12:29:11.090114 # 1..1
7655 12:29:11.090496 # 1..1
7656 12:29:11.090678 # 1..1
7657 12:29:11.090844 # 1..1
7658 12:29:11.090999 # 1..1
7659 12:29:11.091175 # 1..1
7660 12:29:11.091322 # 1..1
7661 12:29:11.091507 # 1..1
7662 12:29:11.091690 # 1..1
7663 12:29:11.091838 # 1..1
7664 12:29:11.091973 # 1..1
7665 12:29:11.092105 # 1..1
7666 12:29:11.092223 # 1..1
7667 12:29:11.092339 # 1..1
7668 12:29:11.092453 # 1..1
7669 12:29:11.092567 # 1..1
7670 12:29:11.092681 # 1..1
7671 12:29:11.092796 # 1..1
7672 12:29:11.092911 # 1..1
7673 12:29:11.093025 # 1..1
7674 12:29:11.093140 # 1..1
7675 12:29:11.093256 # 1..1
7676 12:29:11.093371 # 1..1
7677 12:29:11.093486 # 1..1
7678 12:29:11.093600 # 1..1
7679 12:29:11.093731 # 1..1
7680 12:29:11.093848 # 1..1
7681 12:29:11.093965 # 1..1
7682 12:29:11.094080 # 1..1
7683 12:29:11.094196 # 1..1
7684 12:29:11.094310 # 1..1
7685 12:29:11.094425 # 1..1
7686 12:29:11.094538 # 1..1
7687 12:29:11.094656 # 1..1
7688 12:29:11.094771 # 1..1
7689 12:29:11.094887 # 1..1
7690 12:29:11.095003 # 1..1
7691 12:29:11.095118 # 1..1
7692 12:29:11.095232 # 1..1
7693 12:29:11.095347 # 1..1
7694 12:29:11.095462 # 1..1
7695 12:29:11.095579 # 1..1
7696 12:29:11.095694 # 1..1
7697 12:29:11.095809 # 1..1
7698 12:29:11.095925 # 1..1
7699 12:29:11.096042 # 1..1
7700 12:29:11.096157 # 1..1
7701 12:29:11.096272 # 1..1
7702 12:29:11.096388 # 1..1
7703 12:29:11.096502 # 1..1
7704 12:29:11.096618 # 1..1
7705 12:29:11.096732 # 1..1
7706 12:29:11.096894 # 1..1
7707 12:29:11.097019 # 1..1
7708 12:29:11.097136 # 1..1
7709 12:29:11.097252 # 1..1
7710 12:29:11.097368 # 1..1
7711 12:29:11.097483 # 1..1
7712 12:29:11.097599 # 1..1
7713 12:29:11.097728 # 1..1
7714 12:29:11.097845 # 1..1
7715 12:29:11.097959 # 1..1
7716 12:29:11.098076 # 1..1
7717 12:29:11.098195 # 1..1
7718 12:29:11.098311 # 1..1
7719 12:29:11.098426 # 1..1
7720 12:29:11.098542 # 1..1
7721 12:29:11.098659 # 1..1
7722 12:29:11.098775 # 1..1
7723 12:29:11.098891 # 1..1
7724 12:29:11.099007 # 1..1
7725 12:29:11.099123 # 1..1
7726 12:29:11.099238 # 1..1
7727 12:29:11.099355 # 1..1
7728 12:29:11.099472 # 1..1
7729 12:29:11.099588 # 1..1
7730 12:29:11.099703 # 1..1
7731 12:29:11.099820 # 1..1
7732 12:29:11.099934 # 1..1
7733 12:29:11.100049 # 1..1
7734 12:29:11.100165 # 1..1
7735 12:29:11.100281 # 1..1
7736 12:29:11.100396 # 1..1
7737 12:29:11.100511 # 1..1
7738 12:29:11.100630 # 1..1
7739 12:29:11.100745 # 1..1
7740 12:29:11.100861 # 1..1
7741 12:29:11.100976 # 1..1
7742 12:29:11.101092 # 1..1
7743 12:29:11.101207 # 1..1
7744 12:29:11.101323 # 1..1
7745 12:29:11.101439 # 1..1
7746 12:29:11.101553 # 1..1
7747 12:29:11.101685 # 1..1
7748 12:29:11.101804 # 1..1
7749 12:29:11.101919 # 1..1
7750 12:29:11.102031 # 1..1
7751 12:29:11.102143 # 1..1
7752 12:29:11.102255 # 1..1
7753 12:29:11.102367 # 1..1
7754 12:29:11.102480 # 1..1
7755 12:29:11.102593 # 1..1
7756 12:29:11.102705 # 1..1
7757 12:29:11.102818 # 1..1
7758 12:29:11.102930 # 1..1
7759 12:29:11.103041 # 1..1
7760 12:29:11.103152 # 1..1
7761 12:29:11.103265 # 1..1
7762 12:29:11.103377 # 1..1
7763 12:29:11.103489 # 1..1
7764 12:29:11.103602 # 1..1
7765 12:29:11.108881 # 1..1
7766 12:29:11.109102 # 1..1
7767 12:29:11.109235 # 1..1
7768 12:29:11.109398 # 1..1
7769 12:29:11.109573 # 1..1
7770 12:29:11.109775 # 1..1
7771 12:29:11.110178 # 1..1
7772 12:29:11.110363 # 1..1
7773 12:29:11.110548 # 1..1
7774 12:29:11.110733 # 1..1
7775 12:29:11.110882 # 1..1
7776 12:29:11.111053 # 1..1
7777 12:29:11.111263 # 1..1
7778 12:29:11.111439 # 1..1
7779 12:29:11.111643 # 1..1
7780 12:29:11.111844 # 1..1
7781 12:29:11.112002 # 1..1
7782 12:29:11.112130 # 1..1
7783 12:29:11.112246 # 1..1
7784 12:29:11.112359 # 1..1
7785 12:29:11.112471 # 1..1
7786 12:29:11.112584 # 1..1
7787 12:29:11.112696 # 1..1
7788 12:29:11.112809 # 1..1
7789 12:29:11.112922 # 1..1
7790 12:29:11.113034 # 1..1
7791 12:29:11.113147 # 1..1
7792 12:29:11.113260 # 1..1
7793 12:29:11.113372 # 1..1
7794 12:29:11.113484 # 1..1
7795 12:29:11.113599 # 1..1
7796 12:29:11.113826 # 1..1
7797 12:29:11.114023 # 1..1
7798 12:29:11.114207 # 1..1
7799 12:29:11.114390 # 1..1
7800 12:29:11.114572 # 1..1
7801 12:29:11.114737 # 1..1
7802 12:29:11.114879 # 1..1
7803 12:29:11.115020 # 1..1
7804 12:29:11.115161 # 1..1
7805 12:29:11.115302 # 1..1
7806 12:29:11.115445 # 1..1
7807 12:29:11.115586 # 1..1
7808 12:29:11.115727 # 1..1
7809 12:29:11.115868 # 1..1
7810 12:29:11.116009 # 1..1
7811 12:29:11.116150 # 1..1
7812 12:29:11.116292 # 1..1
7813 12:29:11.116433 # 1..1
7814 12:29:11.116616 # 1..1
7815 12:29:11.116789 # 1..1
7816 12:29:11.116933 # 1..1
7817 12:29:11.117073 # 1..1
7818 12:29:11.117215 # 1..1
7819 12:29:11.117356 # 1..1
7820 12:29:11.117552 # 1..1
7821 12:29:11.117700 # 1..1
7822 12:29:11.117846 # 1..1
7823 12:29:11.117988 # 1..1
7824 12:29:11.118128 # 1..1
7825 12:29:11.118269 # 1..1
7826 12:29:11.118410 # 1..1
7827 12:29:11.118551 # 1..1
7828 12:29:11.118693 # 1..1
7829 12:29:11.118832 # 1..1
7830 12:29:11.118975 # 1..1
7831 12:29:11.119115 # 1..1
7832 12:29:11.119256 # 1..1
7833 12:29:11.119398 # 1..1
7834 12:29:11.119539 # 1..1
7835 12:29:11.119682 # 1..1
7836 12:29:11.119822 # 1..1
7837 12:29:11.119962 # 1..1
7838 12:29:11.120103 # 1..1
7839 12:29:11.120243 # 1..1
7840 12:29:11.120382 # 1..1
7841 12:29:11.120521 # 1..1
7842 12:29:11.120666 # 1..1
7843 12:29:11.120808 # 1..1
7844 12:29:11.120949 # 1..1
7845 12:29:11.121089 # 1..1
7846 12:29:11.121230 # 1..1
7847 12:29:11.121370 # 1..1
7848 12:29:11.121511 # 1..1
7849 12:29:11.121659 # 1..1
7850 12:29:11.121805 # 1..1
7851 12:29:11.121946 # 1..1
7852 12:29:11.122087 # 1..1
7853 12:29:11.122228 # 1..1
7854 12:29:11.122367 # 1..1
7855 12:29:11.122509 # 1..1
7856 12:29:11.122651 # 1..1
7857 12:29:11.122791 # 1..1
7858 12:29:11.122932 # 1..1
7859 12:29:11.123072 # 1..1
7860 12:29:11.123212 # 1..1
7861 12:29:11.123355 # 1..1
7862 12:29:11.123497 # 1..1
7863 12:29:11.123639 # 1..1
7864 12:29:11.123779 # 1..1
7865 12:29:11.123919 # 1..1
7866 12:29:11.124060 # 1..1
7867 12:29:11.124201 # 1..1
7868 12:29:11.124343 # 1..1
7869 12:29:11.124484 # 1..1
7870 12:29:11.124626 # 1..1
7871 12:29:11.124766 # 1..1
7872 12:29:11.124906 # 1..1
7873 12:29:11.125047 # 1..1
7874 12:29:11.125188 # 1..1
7875 12:29:11.125328 # 1..1
7876 12:29:11.125468 # 1..1
7877 12:29:11.125610 # 1..1
7878 12:29:11.125763 # 1..1
7879 12:29:11.131058 # 1..1
7880 12:29:11.131391 # 1..1
7881 12:29:11.131545 # 1..1
7882 12:29:11.131675 # 1..1
7883 12:29:11.131802 # 1..1
7884 12:29:11.131928 # 1..1
7885 12:29:11.132267 # 1..1
7886 12:29:11.132394 # 1..1
7887 12:29:11.132519 # 1..1
7888 12:29:11.132696 # 1..1
7889 12:29:11.132841 # 1..1
7890 12:29:11.132983 # 1..1
7891 12:29:11.133151 # 1..1
7892 12:29:11.133323 # 1..1
7893 12:29:11.133479 # 1..1
7894 12:29:11.133606 # 1..1
7895 12:29:11.133814 # 1..1
7896 12:29:11.133987 # 1..1
7897 12:29:11.134168 # 1..1
7898 12:29:11.134318 # 1..1
7899 12:29:11.134489 # 1..1
7900 12:29:11.134683 # 1..1
7901 12:29:11.134858 # 1..1
7902 12:29:11.135028 # 1..1
7903 12:29:11.135169 # 1..1
7904 12:29:11.135325 # 1..1
7905 12:29:11.135491 # 1..1
7906 12:29:11.135659 # 1..1
7907 12:29:11.135822 # 1..1
7908 12:29:11.135972 # 1..1
7909 12:29:11.136092 # 1..1
7910 12:29:11.136205 # 1..1
7911 12:29:11.136317 # 1..1
7912 12:29:11.136431 # 1..1
7913 12:29:11.136544 # 1..1
7914 12:29:11.136657 # 1..1
7915 12:29:11.136769 # 1..1
7916 12:29:11.136882 # 1..1
7917 12:29:11.136993 # 1..1
7918 12:29:11.137108 # 1..1
7919 12:29:11.137220 # 1..1
7920 12:29:11.137334 # 1..1
7921 12:29:11.137447 # 1..1
7922 12:29:11.137560 # 1..1
7923 12:29:11.137731 # 1..1
7924 12:29:11.138004 # 1..1
7925 12:29:11.138193 # 1..1
7926 12:29:11.138376 # 1..1
7927 12:29:11.138558 # 1..1
7928 12:29:11.138743 # 1..1
7929 12:29:11.138886 # 1..1
7930 12:29:11.139028 # 1..1
7931 12:29:11.139169 # 1..1
7932 12:29:11.139311 # 1..1
7933 12:29:11.139451 # 1..1
7934 12:29:11.139592 # 1..1
7935 12:29:11.139737 # 1..1
7936 12:29:11.139877 # 1..1
7937 12:29:11.140017 # 1..1
7938 12:29:11.140160 # 1..1
7939 12:29:11.140301 # 1..1
7940 12:29:11.140442 # 1..1
7941 12:29:11.140582 # 1..1
7942 12:29:11.140727 # 1..1
7943 12:29:11.140867 # 1..1
7944 12:29:11.141008 # 1..1
7945 12:29:11.141149 # 1..1
7946 12:29:11.141290 # 1..1
7947 12:29:11.141431 # 1..1
7948 12:29:11.141572 # 1..1
7949 12:29:11.141729 # 1..1
7950 12:29:11.141873 # 1..1
7951 12:29:11.142014 # 1..1
7952 12:29:11.142155 # 1..1
7953 12:29:11.142297 # 1..1
7954 12:29:11.142437 # 1..1
7955 12:29:11.142578 # 1..1
7956 12:29:11.142720 # 1..1
7957 12:29:11.142860 # 1..1
7958 12:29:11.143000 # 1..1
7959 12:29:11.143142 # 1..1
7960 12:29:11.143282 # 1..1
7961 12:29:11.143422 # 1..1
7962 12:29:11.143562 # 1..1
7963 12:29:11.143702 # 1..1
7964 12:29:11.143842 # 1..1
7965 12:29:11.143983 # 1..1
7966 12:29:11.144122 # 1..1
7967 12:29:11.144262 # 1..1
7968 12:29:11.144402 # 1..1
7969 12:29:11.144542 # 1..1
7970 12:29:11.144682 # 1..1
7971 12:29:11.144821 # 1..1
7972 12:29:11.144960 # 1..1
7973 12:29:11.145101 # 1..1
7974 12:29:11.145242 # 1..1
7975 12:29:11.145382 # 1..1
7976 12:29:11.145524 # 1..1
7977 12:29:11.145678 # 1..1
7978 12:29:11.145821 # 1..1
7979 12:29:11.145961 # 1..1
7980 12:29:11.146101 # 1..1
7981 12:29:11.146240 # 1..1
7982 12:29:11.146381 # 1..1
7983 12:29:11.146522 # 1..1
7984 12:29:11.146663 # 1..1
7985 12:29:11.146805 # 1..1
7986 12:29:11.146945 # 1..1
7987 12:29:11.147085 # 1..1
7988 12:29:11.147225 # 1..1
7989 12:29:11.147367 # 1..1
7990 12:29:11.147508 # 1..1
7991 12:29:11.147649 # 1..1
7992 12:29:11.147789 # 1..1
7993 12:29:11.147931 # 1..1
7994 12:29:11.148072 # 1..1
7995 12:29:11.148212 # 1..1
7996 12:29:11.148352 # 1..1
7997 12:29:11.148490 # 1..1
7998 12:29:11.148631 # 1..1
7999 12:29:11.148772 # 1..1
8000 12:29:11.148911 # 1..1
8001 12:29:11.149051 # 1..1
8002 12:29:11.149192 # 1..1
8003 12:29:11.149331 # 1..1
8004 12:29:11.149471 # 1..1
8005 12:29:11.149611 # 1..1
8006 12:29:11.149761 # 1..1
8007 12:29:11.149903 # 1..1
8008 12:29:11.150042 # 1..1
8009 12:29:11.150183 # 1..1
8010 12:29:11.150324 # 1..1
8011 12:29:11.150464 # 1..1
8012 12:29:11.150603 # 1..1
8013 12:29:11.150744 # 1..1
8014 12:29:11.150884 # 1..1
8015 12:29:11.151024 # 1..1
8016 12:29:11.151164 # 1..1
8017 12:29:11.151303 # 1..1
8018 12:29:11.151444 # 1..1
8019 12:29:11.151584 # 1..1
8020 12:29:11.151726 # 1..1
8021 12:29:11.151866 # 1..1
8022 12:29:11.152008 # 1..1
8023 12:29:11.152149 # 1..1
8024 12:29:11.152289 # 1..1
8025 12:29:11.152429 # 1..1
8026 12:29:11.152569 # 1..1
8027 12:29:11.152712 # 1..1
8028 12:29:11.152852 # 1..1
8029 12:29:11.152992 # 1..1
8030 12:29:11.153133 # 1..1
8031 12:29:11.153272 # 1..1
8032 12:29:11.153412 # 1..1
8033 12:29:11.153551 # 1..1
8034 12:29:11.153705 # 1..1
8035 12:29:11.153849 # 1..1
8036 12:29:11.153989 # 1..1
8037 12:29:11.154130 # 1..1
8038 12:29:11.154271 # 1..1
8039 12:29:11.154412 # 1..1
8040 12:29:11.154552 # 1..1
8041 12:29:11.154692 # 1..1
8042 12:29:11.154833 # 1..1
8043 12:29:11.154974 # 1..1
8044 12:29:11.155114 # 1..1
8045 12:29:11.155255 # 1..1
8046 12:29:11.155395 # 1..1
8047 12:29:11.155535 # 1..1
8048 12:29:11.165764 # 1..1
8049 12:29:11.166033 # 1..1
8050 12:29:11.166217 # 1..1
8051 12:29:11.166363 # 1..1
8052 12:29:11.166557 # 1..1
8053 12:29:11.166694 # 1..1
8054 12:29:11.166811 # 1..1
8055 12:29:11.167156 #
8056 12:29:11.167309 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
8057 12:29:11.406709 # selftests: arm64: check_ksm_options
8058 12:29:11.755221 # 1..4
8059 12:29:11.755502 # # Invalid MTE synchronous exception caught!
8060 12:29:11.798386 not ok 38 selftests: arm64: check_ksm_options # exit=1
8061 12:29:12.053820 # selftests: arm64: check_mmap_options
8062 12:29:12.819518 # 1..22
8063 12:29:12.819961 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
8064 12:29:12.820054 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
8065 12:29:12.831413 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
8066 12:29:12.831997 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
8067 12:29:12.832161 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
8068 12:29:12.832330 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8069 12:29:12.875547 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
8070 12:29:12.876158 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8071 12:29:12.876336 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
8072 12:29:12.876513 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8073 12:29:12.892123 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8074 12:29:12.892911 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8075 12:29:12.893294 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8076 12:29:12.893489 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8077 12:29:12.893704 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8078 12:29:12.893898 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8079 12:29:12.894068 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8080 12:29:12.894219 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8081 12:29:12.894371 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8082 12:29:12.894738 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8083 12:29:12.894899 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8084 12:29:12.895046 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8085 12:29:12.895169 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8086 12:29:12.895848 not ok 39 selftests: arm64: check_mmap_options # exit=1
8087 12:29:13.167012 # selftests: arm64: check_prctl
8088 12:29:13.422039 # TAP version 13
8089 12:29:13.422369 # 1..5
8090 12:29:13.422508 # ok 1 check_basic_read
8091 12:29:13.422850 # ok 2 NONE
8092 12:29:13.422978 # ok 3 SYNC
8093 12:29:13.423098 # ok 4 ASYNC
8094 12:29:13.423213 # ok 5 SYNC+ASYNC
8095 12:29:13.423329 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8096 12:29:13.465328 ok 40 selftests: arm64: check_prctl
8097 12:29:13.814953 # selftests: arm64: check_tags_inclusion
8098 12:29:14.149200 # 1..4
8099 12:29:14.149842 # # Unexpected fault recorded for 0x800ffff8b3ed000-0x800ffff8b3ed050 in mode 1
8100 12:29:14.150053 # not ok 1 Check an included tag value with sync mode
8101 12:29:14.150248 # # Unexpected fault recorded for 0x200ffff8b3ed000-0x200ffff8b3ed050 in mode 1
8102 12:29:14.150436 # not ok 2 Check different included tags value with sync mode
8103 12:29:14.150593 # ok 3 Check none included tags value with sync mode
8104 12:29:14.150776 # # Unexpected fault recorded for 0x600ffff8b3ed000-0x600ffff8b3ed050 in mode 1
8105 12:29:14.150915 # not ok 4 Check all included tags value with sync mode
8106 12:29:14.151060 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8107 12:29:14.206151 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8108 12:29:14.486958 # selftests: arm64: check_user_mem
8109 12:29:24.011943 # 1..64
8110 12:29:24.012237 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8111 12:29:24.012646 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8112 12:29:24.013099 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8113 12:29:24.013367 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8114 12:29:24.013602 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8115 12:29:24.013969 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8116 12:29:24.014241 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8117 12:29:24.014436 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8118 12:29:24.014607 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8119 12:29:24.014779 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8120 12:29:24.014985 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8121 12:29:24.015161 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8122 12:29:24.015329 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8123 12:29:24.015493 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8124 12:29:24.015656 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8125 12:29:24.015813 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8126 12:29:24.015995 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8127 12:29:24.016124 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8128 12:29:24.016241 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8129 12:29:24.016358 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8130 12:29:24.016475 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8131 12:29:24.021800 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8132 12:29:24.022222 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8133 12:29:24.022343 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8134 12:29:24.022441 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8135 12:29:24.022559 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8136 12:29:24.022656 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8137 12:29:24.022770 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8138 12:29:24.022881 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8139 12:29:24.022992 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8140 12:29:24.023351 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8141 12:29:24.023469 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8142 12:29:24.023578 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8143 12:29:24.023893 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8144 12:29:24.024461 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8145 12:29:24.024798 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8146 12:29:24.024949 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8147 12:29:24.025067 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8148 12:29:24.025197 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8149 12:29:24.025530 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8150 12:29:24.025729 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8151 12:29:24.025885 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8152 12:29:24.026008 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8153 12:29:24.026322 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8154 12:29:24.026430 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8155 12:29:24.026544 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8156 12:29:24.026848 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8157 12:29:24.026974 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8158 12:29:24.027081 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8159 12:29:24.027380 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8160 12:29:24.027513 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8161 12:29:25.685431 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8162 12:29:25.686110 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8163 12:29:25.686326 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8164 12:29:25.686513 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8165 12:29:25.686695 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8166 12:29:25.686898 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8167 12:29:25.687065 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8168 12:29:25.687226 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8169 12:29:25.687384 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8170 12:29:25.687571 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8171 12:29:25.687725 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8172 12:29:25.687919 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8173 12:29:25.688103 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8174 12:29:25.688283 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8175 12:29:25.710014 ok 42 selftests: arm64: check_user_mem
8176 12:29:25.810144 # selftests: arm64: btitest
8177 12:29:25.907197 # TAP version 13
8178 12:29:25.907436 # 1..18
8179 12:29:25.907531 # # HWCAP_PACA present
8180 12:29:25.907840 # # HWCAP2_BTI present
8181 12:29:25.907944 # # Test binary built for BTI
8182 12:29:25.908032 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8183 12:29:25.908114 # ok 1 nohint_func/call_using_br_x0
8184 12:29:25.908208 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8185 12:29:25.910374 # ok 2 nohint_func/call_using_br_x16
8186 12:29:25.910683 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8187 12:29:25.910789 # ok 3 nohint_func/call_using_blr
8188 12:29:25.910888 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8189 12:29:25.911168 # ok 4 bti_none_func/call_using_br_x0
8190 12:29:25.911266 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8191 12:29:25.911351 # ok 5 bti_none_func/call_using_br_x16
8192 12:29:25.911445 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8193 12:29:25.911741 # ok 6 bti_none_func/call_using_blr
8194 12:29:25.911844 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8195 12:29:25.911925 # ok 7 bti_c_func/call_using_br_x0
8196 12:29:25.912004 # ok 8 bti_c_func/call_using_br_x16
8197 12:29:25.912097 # ok 9 bti_c_func/call_using_blr
8198 12:29:25.912176 # ok 10 bti_j_func/call_using_br_x0
8199 12:29:25.915725 # ok 11 bti_j_func/call_using_br_x16
8200 12:29:25.916028 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8201 12:29:25.917048 # ok 12 bti_j_func/call_using_blr
8202 12:29:25.917586 # ok 13 bti_jc_func/call_using_br_x0
8203 12:29:25.917802 # ok 14 bti_jc_func/call_using_br_x16
8204 12:29:25.917942 # ok 15 bti_jc_func/call_using_blr
8205 12:29:25.918062 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8206 12:29:25.918178 # ok 16 paciasp_func/call_using_br_x0
8207 12:29:25.918318 # ok 17 paciasp_func/call_using_br_x16
8208 12:29:25.918438 # ok 18 paciasp_func/call_using_blr
8209 12:29:25.918554 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8210 12:29:25.935763 ok 43 selftests: arm64: btitest
8211 12:29:26.038055 # selftests: arm64: nobtitest
8212 12:29:26.136075 # TAP version 13
8213 12:29:26.136348 # 1..18
8214 12:29:26.138236 # # HWCAP_PACA present
8215 12:29:26.138438 # # HWCAP2_BTI present
8216 12:29:26.138806 # # Test binary not built for BTI
8217 12:29:26.138920 # ok 1 nohint_func/call_using_br_x0
8218 12:29:26.139018 # ok 2 nohint_func/call_using_br_x16
8219 12:29:26.139113 # ok 3 nohint_func/call_using_blr
8220 12:29:26.139206 # ok 4 bti_none_func/call_using_br_x0
8221 12:29:26.139296 # ok 5 bti_none_func/call_using_br_x16
8222 12:29:26.139386 # ok 6 bti_none_func/call_using_blr
8223 12:29:26.139495 # ok 7 bti_c_func/call_using_br_x0
8224 12:29:26.139588 # ok 8 bti_c_func/call_using_br_x16
8225 12:29:26.139678 # ok 9 bti_c_func/call_using_blr
8226 12:29:26.139768 # ok 10 bti_j_func/call_using_br_x0
8227 12:29:26.139860 # ok 11 bti_j_func/call_using_br_x16
8228 12:29:26.139948 # ok 12 bti_j_func/call_using_blr
8229 12:29:26.140055 # ok 13 bti_jc_func/call_using_br_x0
8230 12:29:26.140150 # ok 14 bti_jc_func/call_using_br_x16
8231 12:29:26.140238 # ok 15 bti_jc_func/call_using_blr
8232 12:29:26.140325 # ok 16 paciasp_func/call_using_br_x0
8233 12:29:26.140411 # ok 17 paciasp_func/call_using_br_x16
8234 12:29:26.141429 # ok 18 paciasp_func/call_using_blr
8235 12:29:26.141685 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8236 12:29:26.158227 ok 44 selftests: arm64: nobtitest
8237 12:29:26.263391 # selftests: arm64: hwcap
8238 12:29:26.417454 # TAP version 13
8239 12:29:26.418036 # 1..28
8240 12:29:26.418237 # # RNG present
8241 12:29:26.418406 # ok 1 cpuinfo_match_RNG
8242 12:29:26.418577 # ok 2 sigill_RNG
8243 12:29:26.418722 # # SME present
8244 12:29:26.418845 # ok 3 cpuinfo_match_SME
8245 12:29:26.418985 # ok 4 sigill_SME
8246 12:29:26.419128 # # SVE present
8247 12:29:26.419274 # ok 5 cpuinfo_match_SVE
8248 12:29:26.419421 # ok 6 sigill_SVE
8249 12:29:26.419593 # # SVE 2 present
8250 12:29:26.419779 # ok 7 cpuinfo_match_SVE 2
8251 12:29:26.419938 # ok 8 sigill_SVE 2
8252 12:29:26.420068 # # SVE AES present
8253 12:29:26.420184 # ok 9 cpuinfo_match_SVE AES
8254 12:29:26.420300 # ok 10 sigill_SVE AES
8255 12:29:26.420415 # # SVE2 PMULL present
8256 12:29:26.420528 # ok 11 cpuinfo_match_SVE2 PMULL
8257 12:29:26.420641 # ok 12 sigill_SVE2 PMULL
8258 12:29:26.420755 # # SVE2 BITPERM present
8259 12:29:26.420868 # ok 13 cpuinfo_match_SVE2 BITPERM
8260 12:29:26.420983 # ok 14 sigill_SVE2 BITPERM
8261 12:29:26.421098 # # SVE2 SHA3 present
8262 12:29:26.421210 # ok 15 cpuinfo_match_SVE2 SHA3
8263 12:29:26.421323 # ok 16 sigill_SVE2 SHA3
8264 12:29:26.421438 # # SVE2 SM4 present
8265 12:29:26.421552 # ok 17 cpuinfo_match_SVE2 SM4
8266 12:29:26.421725 # ok 18 sigill_SVE2 SM4
8267 12:29:26.421935 # # SVE2 I8MM present
8268 12:29:26.422168 # ok 19 cpuinfo_match_SVE2 I8MM
8269 12:29:26.422357 # ok 20 sigill_SVE2 I8MM
8270 12:29:26.422543 # # SVE2 F32MM present
8271 12:29:26.422727 # ok 21 cpuinfo_match_SVE2 F32MM
8272 12:29:26.422917 # ok 22 sigill_SVE2 F32MM
8273 12:29:26.423111 # # SVE2 F64MM present
8274 12:29:26.423283 # ok 23 cpuinfo_match_SVE2 F64MM
8275 12:29:26.423429 # ok 24 sigill_SVE2 F64MM
8276 12:29:26.423609 # # SVE2 BF16 present
8277 12:29:26.423749 # ok 25 cpuinfo_match_SVE2 BF16
8278 12:29:26.423892 # ok 26 sigill_SVE2 BF16
8279 12:29:26.424035 # ok 27 cpuinfo_match_SVE2 EBF16
8280 12:29:26.424176 # ok 28 # SKIP sigill_SVE2 EBF16
8281 12:29:26.424319 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8282 12:29:26.445486 ok 45 selftests: arm64: hwcap
8283 12:29:26.629478 # selftests: arm64: ptrace
8284 12:29:26.797681 # TAP version 13
8285 12:29:26.798027 # 1..7
8286 12:29:26.798183 # # Parent is 4704, child is 4705
8287 12:29:26.798538 # ok 1 read_tpidr_one
8288 12:29:26.798687 # ok 2 write_tpidr_one
8289 12:29:26.798809 # ok 3 verify_tpidr_one
8290 12:29:26.798925 # ok 4 count_tpidrs
8291 12:29:26.799039 # ok 5 tpidr2_write
8292 12:29:26.799153 # ok 6 tpidr2_read
8293 12:29:26.799267 # ok 7 write_tpidr_only
8294 12:29:26.799381 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8295 12:29:26.821393 ok 46 selftests: arm64: ptrace
8296 12:29:26.951213 # selftests: arm64: syscall-abi
8297 12:29:29.576809 # TAP version 13
8298 12:29:29.577040 # 1..514
8299 12:29:29.577332 # # SME with FA64
8300 12:29:29.577437 # ok 1 getpid() FPSIMD
8301 12:29:29.577521 # ok 2 getpid() SVE VL 256
8302 12:29:29.577602 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8303 12:29:29.577692 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8304 12:29:29.577789 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8305 12:29:29.577876 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8306 12:29:29.578232 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8307 12:29:29.578337 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8308 12:29:29.578419 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8309 12:29:29.578498 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8310 12:29:29.578576 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8311 12:29:29.578662 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8312 12:29:29.578746 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8313 12:29:29.578827 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8314 12:29:29.579102 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8315 12:29:29.579205 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8316 12:29:29.579286 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8317 12:29:29.579367 # ok 18 getpid() SVE VL 240
8318 12:29:29.579445 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8319 12:29:29.579522 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8320 12:29:29.579598 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8321 12:29:29.579674 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8322 12:29:29.579751 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8323 12:29:29.579845 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8324 12:29:29.579925 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8325 12:29:29.580002 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8326 12:29:29.580078 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8327 12:29:29.580154 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8328 12:29:29.580231 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8329 12:29:29.580306 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8330 12:29:29.580382 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8331 12:29:29.580458 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8332 12:29:29.580550 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8333 12:29:29.580628 # ok 34 getpid() SVE VL 224
8334 12:29:29.584778 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8335 12:29:29.584999 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8336 12:29:29.585173 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8337 12:29:29.585516 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8338 12:29:29.585623 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8339 12:29:29.585717 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8340 12:29:29.585793 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8341 12:29:29.585864 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8342 12:29:29.585937 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8343 12:29:29.586015 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8344 12:29:29.586106 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8345 12:29:29.586183 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8346 12:29:29.586259 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8347 12:29:29.586333 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8348 12:29:29.586420 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8349 12:29:29.586510 # ok 50 getpid() SVE VL 208
8350 12:29:29.586848 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8351 12:29:29.587088 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8352 12:29:29.587338 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8353 12:29:29.587551 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8354 12:29:29.587784 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8355 12:29:29.588002 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8356 12:29:29.588159 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8357 12:29:29.588286 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8358 12:29:29.588435 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8359 12:29:29.588560 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8360 12:29:29.588681 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8361 12:29:29.588797 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8362 12:29:29.588913 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8363 12:29:29.589029 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8364 12:29:29.592674 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8365 12:29:29.593305 # ok 66 getpid() SVE VL 192
8366 12:29:29.593522 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8367 12:29:29.593743 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8368 12:29:29.593891 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8369 12:29:29.594013 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8370 12:29:29.594165 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8371 12:29:29.594333 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8372 12:29:29.594465 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8373 12:29:29.594594 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8374 12:29:29.594722 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8375 12:29:29.594923 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8376 12:29:29.595113 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8377 12:29:29.595339 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8378 12:29:29.595531 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8379 12:29:29.595717 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8380 12:29:29.595904 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8381 12:29:29.596060 # ok 82 getpid() SVE VL 176
8382 12:29:29.596182 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8383 12:29:29.596300 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8384 12:29:29.596416 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8385 12:29:29.596532 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8386 12:29:29.596651 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8387 12:29:29.596767 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8388 12:29:29.596912 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8389 12:29:29.597036 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8390 12:29:29.597154 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8391 12:29:29.597271 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8392 12:29:29.597386 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8393 12:29:29.600554 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8394 12:29:29.600954 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8395 12:29:29.601106 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8396 12:29:29.601255 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8397 12:29:29.601430 # ok 98 getpid() SVE VL 160
8398 12:29:32.127108 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8399 12:29:32.127571 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8400 12:29:32.127666 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8401 12:29:32.127751 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8402 12:29:32.128186 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8403 12:29:32.128291 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8404 12:29:32.128377 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8405 12:29:32.128458 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8406 12:29:32.128547 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8407 12:29:32.128628 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8408 12:29:32.128709 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8409 12:29:32.129019 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8410 12:29:32.129117 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8411 12:29:32.129201 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8412 12:29:32.129282 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8413 12:29:32.129364 # ok 114 getpid() SVE VL 144
8414 12:29:32.129445 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8415 12:29:32.129542 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8416 12:29:32.129625 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8417 12:29:32.129800 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8418 12:29:32.129892 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8419 12:29:32.129973 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8420 12:29:32.130072 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8421 12:29:32.130156 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8422 12:29:32.130236 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8423 12:29:32.130369 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8424 12:29:32.130458 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8425 12:29:32.130539 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8426 12:29:32.130638 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8427 12:29:32.130721 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8428 12:29:32.130801 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8429 12:29:32.130881 # ok 130 getpid() SVE VL 128
8430 12:29:32.130960 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8431 12:29:32.131057 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8432 12:29:32.131139 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8433 12:29:32.131218 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8434 12:29:32.131297 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8435 12:29:32.131664 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8436 12:29:32.131775 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8437 12:29:32.131861 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8438 12:29:32.131942 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8439 12:29:32.132021 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8440 12:29:32.132100 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8441 12:29:32.132195 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8442 12:29:32.132277 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8443 12:29:32.132357 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8444 12:29:32.136697 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8445 12:29:32.137033 # ok 146 getpid() SVE VL 112
8446 12:29:32.137173 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8447 12:29:32.137273 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8448 12:29:32.137372 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8449 12:29:32.137760 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8450 12:29:32.137864 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8451 12:29:32.137949 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8452 12:29:32.138029 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8453 12:29:32.138110 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8454 12:29:32.138189 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8455 12:29:32.138458 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8456 12:29:32.138547 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8457 12:29:32.138643 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8458 12:29:32.138725 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8459 12:29:32.138806 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8460 12:29:32.138885 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8461 12:29:32.138964 # ok 162 getpid() SVE VL 96
8462 12:29:32.139043 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8463 12:29:32.139139 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8464 12:29:32.139220 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8465 12:29:32.139300 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8466 12:29:32.139379 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8467 12:29:32.139458 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8468 12:29:32.139555 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8469 12:29:32.139636 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8470 12:29:32.139716 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8471 12:29:32.139795 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8472 12:29:32.139890 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8473 12:29:32.139972 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8474 12:29:32.140061 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8475 12:29:32.140155 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8476 12:29:32.144739 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8477 12:29:32.144844 # ok 178 getpid() SVE VL 80
8478 12:29:32.145241 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8479 12:29:32.145347 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8480 12:29:32.145432 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8481 12:29:32.145529 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8482 12:29:32.145612 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8483 12:29:32.145707 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8484 12:29:32.145788 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8485 12:29:32.145884 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8486 12:29:32.145966 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8487 12:29:32.146046 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8488 12:29:32.146139 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8489 12:29:32.146220 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8490 12:29:32.146300 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8491 12:29:32.146394 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8492 12:29:32.146677 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8493 12:29:32.146765 # ok 194 getpid() SVE VL 64
8494 12:29:32.146845 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8495 12:29:34.461295 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8496 12:29:34.462029 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8497 12:29:34.462221 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8498 12:29:34.462409 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8499 12:29:34.462575 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8500 12:29:34.462709 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8501 12:29:34.462856 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8502 12:29:34.463032 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8503 12:29:34.463161 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8504 12:29:34.463282 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8505 12:29:34.463402 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8506 12:29:34.463520 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8507 12:29:34.463637 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8508 12:29:34.463753 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8509 12:29:34.463872 # ok 210 getpid() SVE VL 48
8510 12:29:34.463989 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8511 12:29:34.464135 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8512 12:29:34.464257 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8513 12:29:34.464375 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8514 12:29:34.464491 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8515 12:29:34.464608 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8516 12:29:34.464725 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8517 12:29:34.464842 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8518 12:29:34.464959 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8519 12:29:34.472235 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8520 12:29:34.472574 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8521 12:29:34.472703 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8522 12:29:34.472823 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8523 12:29:34.472963 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8524 12:29:34.473083 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8525 12:29:34.473200 # ok 226 getpid() SVE VL 32
8526 12:29:34.473338 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8527 12:29:34.473458 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8528 12:29:34.473575 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8529 12:29:34.473704 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8530 12:29:34.473843 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8531 12:29:34.473968 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8532 12:29:34.474085 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8533 12:29:34.474202 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8534 12:29:34.474341 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8535 12:29:34.474461 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8536 12:29:34.474578 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8537 12:29:34.474694 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8538 12:29:34.474833 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8539 12:29:34.474955 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8540 12:29:34.475070 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8541 12:29:34.475185 # ok 242 getpid() SVE VL 16
8542 12:29:34.475321 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8543 12:29:34.475440 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8544 12:29:34.475556 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8545 12:29:34.475691 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8546 12:29:34.475829 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8547 12:29:34.475972 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8548 12:29:34.476804 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8549 12:29:34.476940 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8550 12:29:34.477314 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8551 12:29:34.477502 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8552 12:29:34.477684 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8553 12:29:34.477893 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8554 12:29:34.478093 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8555 12:29:34.478265 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8556 12:29:34.478459 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8557 12:29:34.478630 # ok 258 sched_yield() FPSIMD
8558 12:29:34.478867 # ok 259 sched_yield() SVE VL 256
8559 12:29:34.479040 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8560 12:29:34.479186 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8561 12:29:34.479329 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8562 12:29:34.479472 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8563 12:29:34.479615 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8564 12:29:34.479758 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8565 12:29:34.479901 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8566 12:29:34.480089 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8567 12:29:34.480224 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8568 12:29:34.480367 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8569 12:29:34.480510 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8570 12:29:34.480653 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8571 12:29:34.480795 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8572 12:29:34.480940 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8573 12:29:34.481085 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8574 12:29:34.481229 # ok 275 sched_yield() SVE VL 240
8575 12:29:34.481371 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8576 12:29:34.481515 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8577 12:29:34.481678 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8578 12:29:34.481845 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8579 12:29:34.481970 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8580 12:29:34.484653 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8581 12:29:34.485107 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8582 12:29:34.485212 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8583 12:29:34.485295 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8584 12:29:34.485371 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8585 12:29:34.485461 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8586 12:29:34.485538 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8587 12:29:34.485613 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8588 12:29:34.485696 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8589 12:29:36.571762 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8590 12:29:36.572199 # ok 291 sched_yield() SVE VL 224
8591 12:29:36.572305 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8592 12:29:36.580593 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8593 12:29:36.581086 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8594 12:29:36.581202 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8595 12:29:36.581299 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8596 12:29:36.581388 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8597 12:29:36.581476 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8598 12:29:36.581586 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8599 12:29:36.581686 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8600 12:29:36.581773 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8601 12:29:36.581859 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8602 12:29:36.581961 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8603 12:29:36.582050 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8604 12:29:36.582152 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8605 12:29:36.582239 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8606 12:29:36.582341 # ok 307 sched_yield() SVE VL 208
8607 12:29:36.582426 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8608 12:29:36.582503 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8609 12:29:36.582820 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8610 12:29:36.582931 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8611 12:29:36.583010 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8612 12:29:36.583102 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8613 12:29:36.583182 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8614 12:29:36.583258 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8615 12:29:36.583345 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8616 12:29:36.583420 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8617 12:29:36.583504 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8618 12:29:36.583835 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8619 12:29:36.584013 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8620 12:29:36.584378 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8621 12:29:36.585208 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8622 12:29:36.585672 # ok 323 sched_yield() SVE VL 192
8623 12:29:36.585884 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8624 12:29:36.586071 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8625 12:29:36.586286 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8626 12:29:36.586468 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8627 12:29:36.586647 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8628 12:29:36.586833 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8629 12:29:36.587001 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8630 12:29:36.587177 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8631 12:29:36.587363 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8632 12:29:36.587567 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8633 12:29:36.587748 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8634 12:29:36.587924 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8635 12:29:36.588071 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8636 12:29:36.588221 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8637 12:29:36.588346 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8638 12:29:36.593331 # ok 339 sched_yield() SVE VL 176
8639 12:29:36.594227 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8640 12:29:36.594468 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8641 12:29:36.594601 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8642 12:29:36.594725 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8643 12:29:36.594843 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8644 12:29:36.594961 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8645 12:29:36.595078 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8646 12:29:36.595194 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8647 12:29:36.595337 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8648 12:29:36.595747 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8649 12:29:36.595959 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8650 12:29:36.596174 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8651 12:29:36.596315 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8652 12:29:36.596435 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8653 12:29:36.596553 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8654 12:29:36.596670 # ok 355 sched_yield() SVE VL 160
8655 12:29:36.596787 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8656 12:29:36.596916 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8657 12:29:36.597076 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8658 12:29:36.597197 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8659 12:29:36.597315 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8660 12:29:36.597465 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8661 12:29:36.597589 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8662 12:29:36.597733 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8663 12:29:36.597853 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8664 12:29:36.604617 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8665 12:29:36.605158 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8666 12:29:36.605268 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8667 12:29:36.605361 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8668 12:29:36.605451 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8669 12:29:36.605557 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8670 12:29:36.605657 # ok 371 sched_yield() SVE VL 144
8671 12:29:36.605746 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8672 12:29:36.605849 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8673 12:29:36.605937 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8674 12:29:36.606041 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8675 12:29:36.606130 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8676 12:29:38.813819 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8677 12:29:38.814380 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8678 12:29:38.814573 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8679 12:29:38.814746 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8680 12:29:38.814911 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8681 12:29:38.815041 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8682 12:29:38.815170 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8683 12:29:38.815304 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8684 12:29:38.815474 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8685 12:29:38.815661 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8686 12:29:38.815895 # ok 387 sched_yield() SVE VL 128
8687 12:29:38.816064 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8688 12:29:38.816190 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8689 12:29:38.816310 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8690 12:29:38.816425 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8691 12:29:38.816542 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8692 12:29:38.816658 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8693 12:29:38.816774 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8694 12:29:38.816890 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8695 12:29:38.817036 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8696 12:29:38.817159 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8697 12:29:38.817279 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8698 12:29:38.817396 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8699 12:29:38.817512 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8700 12:29:38.824616 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8701 12:29:38.824839 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8702 12:29:38.825002 # ok 403 sched_yield() SVE VL 112
8703 12:29:38.825174 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8704 12:29:38.825299 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8705 12:29:38.825417 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8706 12:29:38.825541 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8707 12:29:38.825687 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8708 12:29:38.825865 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8709 12:29:38.825998 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8710 12:29:38.826142 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8711 12:29:38.826270 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8712 12:29:38.826388 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8713 12:29:38.826512 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8714 12:29:38.826667 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8715 12:29:38.826805 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8716 12:29:38.826936 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8717 12:29:38.827093 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8718 12:29:38.827259 # ok 419 sched_yield() SVE VL 96
8719 12:29:38.827420 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8720 12:29:38.827618 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8721 12:29:38.827786 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8722 12:29:38.827943 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8723 12:29:38.828064 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8724 12:29:38.828182 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8725 12:29:38.828301 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8726 12:29:38.828416 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8727 12:29:38.828531 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8728 12:29:38.828673 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8729 12:29:38.828853 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8730 12:29:38.828986 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8731 12:29:38.829131 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8732 12:29:38.829281 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8733 12:29:38.829421 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8734 12:29:38.829542 # ok 435 sched_yield() SVE VL 80
8735 12:29:38.829667 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8736 12:29:38.829814 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8737 12:29:38.829989 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8738 12:29:38.830123 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8739 12:29:38.830244 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8740 12:29:38.830362 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8741 12:29:38.830765 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8742 12:29:38.830982 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8743 12:29:38.831146 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8744 12:29:38.831308 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8745 12:29:38.831441 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8746 12:29:38.831608 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8747 12:29:38.831780 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8748 12:29:38.831930 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8749 12:29:38.832052 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8750 12:29:38.832169 # ok 451 sched_yield() SVE VL 64
8751 12:29:38.832288 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8752 12:29:38.832401 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8753 12:29:38.832550 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8754 12:29:38.832672 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8755 12:29:38.832789 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8756 12:29:38.832904 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8757 12:29:38.833018 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8758 12:29:38.833135 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8759 12:29:38.833251 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8760 12:29:38.833368 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8761 12:29:38.833482 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8762 12:29:38.833595 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8763 12:29:39.519368 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8764 12:29:39.520163 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8765 12:29:39.520381 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8766 12:29:39.520537 # ok 467 sched_yield() SVE VL 48
8767 12:29:39.520662 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8768 12:29:39.520782 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8769 12:29:39.520927 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8770 12:29:39.521051 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8771 12:29:39.522160 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8772 12:29:39.522605 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8773 12:29:39.522805 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8774 12:29:39.523026 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8775 12:29:39.523219 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8776 12:29:39.523457 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8777 12:29:39.523636 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8778 12:29:39.523782 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8779 12:29:39.523997 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8780 12:29:39.524171 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8781 12:29:39.524317 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8782 12:29:39.524460 # ok 483 sched_yield() SVE VL 32
8783 12:29:39.524609 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8784 12:29:39.524752 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8785 12:29:39.524935 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8786 12:29:39.525070 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8787 12:29:39.525215 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8788 12:29:39.525356 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8789 12:29:39.525498 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8790 12:29:39.525642 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8791 12:29:39.525800 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8792 12:29:39.530890 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8793 12:29:39.531111 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8794 12:29:39.531337 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8795 12:29:39.531533 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8796 12:29:39.531725 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8797 12:29:39.531935 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8798 12:29:39.532086 # ok 499 sched_yield() SVE VL 16
8799 12:29:39.532209 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8800 12:29:39.532343 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8801 12:29:39.532499 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8802 12:29:39.532663 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8803 12:29:39.532825 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8804 12:29:39.533010 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8805 12:29:39.533157 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8806 12:29:39.533300 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8807 12:29:39.533421 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8808 12:29:39.533537 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8809 12:29:39.533696 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8810 12:29:39.533847 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8811 12:29:39.533968 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8812 12:29:39.534085 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8813 12:29:39.534199 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8814 12:29:39.534314 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8815 12:29:39.534431 ok 47 selftests: arm64: syscall-abi
8816 12:29:39.586481 # selftests: arm64: tpidr2
8817 12:29:39.745545 # TAP version 13
8818 12:29:39.745861 # 1..5
8819 12:29:39.746007 # # PID: 4739
8820 12:29:39.746174 # ok 1 default_value
8821 12:29:39.746541 # ok 2 write_read
8822 12:29:39.746676 # ok 3 write_sleep_read
8823 12:29:39.746821 # ok 4 write_fork_read
8824 12:29:39.746954 # ok 5 write_clone_read
8825 12:29:39.747070 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8826 12:29:39.757452 ok 48 selftests: arm64: tpidr2
8827 12:29:40.287763 arm64_tags_test pass
8828 12:29:40.288320 arm64_run_tags_test_sh pass
8829 12:29:40.288427 arm64_fake_sigreturn_bad_magic pass
8830 12:29:40.288515 arm64_fake_sigreturn_bad_size pass
8831 12:29:40.288597 arm64_fake_sigreturn_bad_size_for_magic0 pass
8832 12:29:40.288678 arm64_fake_sigreturn_duplicated_fpsimd pass
8833 12:29:40.288758 arm64_fake_sigreturn_misaligned_sp pass
8834 12:29:40.288854 arm64_fake_sigreturn_missing_fpsimd pass
8835 12:29:40.288938 arm64_fake_sigreturn_sme_change_vl pass
8836 12:29:40.289019 arm64_fake_sigreturn_sve_change_vl pass
8837 12:29:40.289099 arm64_mangle_pstate_invalid_compat_toggle pass
8838 12:29:40.289179 arm64_mangle_pstate_invalid_daif_bits pass
8839 12:29:40.289277 arm64_mangle_pstate_invalid_mode_el1h pass
8840 12:29:40.289358 arm64_mangle_pstate_invalid_mode_el1t pass
8841 12:29:40.289440 arm64_mangle_pstate_invalid_mode_el2h pass
8842 12:29:40.289521 arm64_mangle_pstate_invalid_mode_el2t pass
8843 12:29:40.289602 arm64_mangle_pstate_invalid_mode_el3h pass
8844 12:29:40.289712 arm64_mangle_pstate_invalid_mode_el3t pass
8845 12:29:40.289798 arm64_sme_trap_no_sm pass
8846 12:29:40.289879 arm64_sme_trap_non_streaming skip
8847 12:29:40.289960 arm64_sme_trap_za pass
8848 12:29:40.290048 arm64_sme_vl pass
8849 12:29:40.290138 arm64_ssve_regs pass
8850 12:29:40.290225 arm64_sve_regs pass
8851 12:29:40.290332 arm64_sve_vl pass
8852 12:29:40.290421 arm64_za_no_regs pass
8853 12:29:40.290510 arm64_za_regs pass
8854 12:29:40.290597 arm64_pac_global_corrupt_pac pass
8855 12:29:40.290684 arm64_pac_global_pac_instructions_not_nop pass
8856 12:29:40.290771 arm64_pac_global_pac_instructions_not_nop_generic pass
8857 12:29:40.290858 arm64_pac_global_single_thread_different_keys pass
8858 12:29:40.290969 arm64_pac_global_exec_changed_keys pass
8859 12:29:40.291059 arm64_pac_global_context_switch_keep_keys pass
8860 12:29:40.291142 arm64_pac_global_context_switch_keep_keys_generic pass
8861 12:29:40.291226 arm64_pac pass
8862 12:29:40.291301 arm64_fp-stress_FPSIMD-0-0 pass
8863 12:29:40.291393 arm64_fp-stress_SVE-VL-256-0 pass
8864 12:29:40.291471 arm64_fp-stress_SVE-VL-240-0 pass
8865 12:29:40.291547 arm64_fp-stress_SVE-VL-224-0 pass
8866 12:29:40.291621 arm64_fp-stress_SVE-VL-208-0 pass
8867 12:29:40.291696 arm64_fp-stress_SVE-VL-192-0 pass
8868 12:29:40.291773 arm64_fp-stress_SVE-VL-176-0 pass
8869 12:29:40.292396 arm64_fp-stress_SVE-VL-160-0 pass
8870 12:29:40.292496 arm64_fp-stress_SVE-VL-144-0 pass
8871 12:29:40.292576 arm64_fp-stress_SVE-VL-128-0 pass
8872 12:29:40.292653 arm64_fp-stress_SVE-VL-112-0 pass
8873 12:29:40.292731 arm64_fp-stress_SVE-VL-96-0 pass
8874 12:29:40.292807 arm64_fp-stress_SVE-VL-80-0 pass
8875 12:29:40.296296 arm64_fp-stress_SVE-VL-64-0 pass
8876 12:29:40.296596 arm64_fp-stress_SVE-VL-48-0 pass
8877 12:29:40.296700 arm64_fp-stress_SVE-VL-32-0 pass
8878 12:29:40.296801 arm64_fp-stress_SVE-VL-16-0 pass
8879 12:29:40.296891 arm64_fp-stress_SSVE-VL-256-0 pass
8880 12:29:40.297001 arm64_fp-stress_ZA-VL-256-0 pass
8881 12:29:40.297091 arm64_fp-stress_SSVE-VL-128-0 pass
8882 12:29:40.297195 arm64_fp-stress_ZA-VL-128-0 pass
8883 12:29:40.297285 arm64_fp-stress_SSVE-VL-64-0 pass
8884 12:29:40.297389 arm64_fp-stress_ZA-VL-64-0 pass
8885 12:29:40.297479 arm64_fp-stress_SSVE-VL-32-0 pass
8886 12:29:40.297567 arm64_fp-stress_ZA-VL-32-0 pass
8887 12:29:40.297678 arm64_fp-stress_SSVE-VL-16-0 pass
8888 12:29:40.297768 arm64_fp-stress_ZA-VL-16-0 pass
8889 12:29:40.297852 arm64_fp-stress pass
8890 12:29:40.297943 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8891 12:29:40.298025 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8892 12:29:40.298114 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8893 12:29:40.301839 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8894 12:29:40.301958 arm64_sve-ptrace_Set_SVE_VL_16 pass
8895 12:29:40.302061 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8896 12:29:40.302155 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8897 12:29:40.302249 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8898 12:29:40.302341 arm64_sve-ptrace_Set_SVE_VL_32 pass
8899 12:29:40.302434 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8900 12:29:40.302527 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8901 12:29:40.302619 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8902 12:29:40.302712 arm64_sve-ptrace_Set_SVE_VL_48 pass
8903 12:29:40.302803 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8904 12:29:40.302895 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8905 12:29:40.302988 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8906 12:29:40.303084 arm64_sve-ptrace_Set_SVE_VL_64 pass
8907 12:29:40.303175 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8908 12:29:40.304226 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8909 12:29:40.304573 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8910 12:29:40.304784 arm64_sve-ptrace_Set_SVE_VL_80 pass
8911 12:29:40.305006 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8912 12:29:40.305323 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8913 12:29:40.305528 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8914 12:29:40.305730 arm64_sve-ptrace_Set_SVE_VL_96 pass
8915 12:29:40.305933 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8916 12:29:40.306152 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8917 12:29:40.306365 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8918 12:29:40.306604 arm64_sve-ptrace_Set_SVE_VL_112 pass
8919 12:29:40.306841 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8920 12:29:40.307066 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8921 12:29:40.307284 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8922 12:29:40.307508 arm64_sve-ptrace_Set_SVE_VL_128 pass
8923 12:29:40.307728 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8924 12:29:40.307921 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8925 12:29:40.308064 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8926 12:29:40.308192 arm64_sve-ptrace_Set_SVE_VL_144 pass
8927 12:29:40.308406 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8928 12:29:40.308557 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8929 12:29:40.308681 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8930 12:29:40.308798 arm64_sve-ptrace_Set_SVE_VL_160 pass
8931 12:29:40.308917 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8932 12:29:40.309034 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8933 12:29:40.309153 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8934 12:29:40.309270 arm64_sve-ptrace_Set_SVE_VL_176 pass
8935 12:29:40.309392 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8936 12:29:40.309526 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8937 12:29:40.312315 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8938 12:29:40.312537 arm64_sve-ptrace_Set_SVE_VL_192 pass
8939 12:29:40.312982 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8940 12:29:40.313194 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8941 12:29:40.313384 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8942 12:29:40.313587 arm64_sve-ptrace_Set_SVE_VL_208 pass
8943 12:29:40.313789 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8944 12:29:40.314076 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8945 12:29:40.314264 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8946 12:29:40.314439 arm64_sve-ptrace_Set_SVE_VL_224 pass
8947 12:29:40.314613 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8948 12:29:40.314843 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8949 12:29:40.315016 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8950 12:29:40.315161 arm64_sve-ptrace_Set_SVE_VL_240 pass
8951 12:29:40.315329 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8952 12:29:40.315549 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8953 12:29:40.315810 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8954 12:29:40.316049 arm64_sve-ptrace_Set_SVE_VL_256 pass
8955 12:29:40.316225 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8956 12:29:40.316401 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8957 12:29:40.316542 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8958 12:29:40.316667 arm64_sve-ptrace_Set_SVE_VL_272 pass
8959 12:29:40.316792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8960 12:29:40.316951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8961 12:29:40.317084 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8962 12:29:40.317200 arm64_sve-ptrace_Set_SVE_VL_288 pass
8963 12:29:40.317315 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8964 12:29:40.317430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8965 12:29:40.317544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8966 12:29:40.317787 arm64_sve-ptrace_Set_SVE_VL_304 pass
8967 12:29:40.317986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8968 12:29:40.318152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8969 12:29:40.320284 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8970 12:29:40.320495 arm64_sve-ptrace_Set_SVE_VL_320 pass
8971 12:29:40.320975 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8972 12:29:40.321180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8973 12:29:40.321346 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8974 12:29:40.321511 arm64_sve-ptrace_Set_SVE_VL_336 pass
8975 12:29:40.321684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8976 12:29:40.321942 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8977 12:29:40.322150 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8978 12:29:40.322397 arm64_sve-ptrace_Set_SVE_VL_352 pass
8979 12:29:40.322681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8980 12:29:40.322932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8981 12:29:40.323180 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8982 12:29:40.323418 arm64_sve-ptrace_Set_SVE_VL_368 pass
8983 12:29:40.323671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8984 12:29:40.323910 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8985 12:29:40.324118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8986 12:29:40.324293 arm64_sve-ptrace_Set_SVE_VL_384 pass
8987 12:29:40.324513 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8988 12:29:40.324653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8989 12:29:40.324796 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8990 12:29:40.324974 arm64_sve-ptrace_Set_SVE_VL_400 pass
8991 12:29:40.325144 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8992 12:29:40.325288 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8993 12:29:40.325431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8994 12:29:40.325572 arm64_sve-ptrace_Set_SVE_VL_416 pass
8995 12:29:40.325729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8996 12:29:40.325873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8997 12:29:40.326015 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8998 12:29:40.326179 arm64_sve-ptrace_Set_SVE_VL_432 pass
8999 12:29:40.326352 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
9000 12:29:40.328268 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
9001 12:29:40.328582 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
9002 12:29:40.328678 arm64_sve-ptrace_Set_SVE_VL_448 pass
9003 12:29:40.328766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
9004 12:29:40.328867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
9005 12:29:40.344669 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
9006 12:29:40.344925 arm64_sve-ptrace_Set_SVE_VL_464 pass
9007 12:29:40.345015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
9008 12:29:40.345314 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
9009 12:29:40.345415 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
9010 12:29:40.345496 arm64_sve-ptrace_Set_SVE_VL_480 pass
9011 12:29:40.345572 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
9012 12:29:40.345769 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
9013 12:29:40.345960 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
9014 12:29:40.346057 arm64_sve-ptrace_Set_SVE_VL_496 pass
9015 12:29:40.346139 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
9016 12:29:40.346218 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
9017 12:29:40.346295 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
9018 12:29:40.346370 arm64_sve-ptrace_Set_SVE_VL_512 pass
9019 12:29:40.346475 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
9020 12:29:40.346811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
9021 12:29:40.346920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
9022 12:29:40.347012 arm64_sve-ptrace_Set_SVE_VL_528 pass
9023 12:29:40.347106 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
9024 12:29:40.347194 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
9025 12:29:40.347281 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
9026 12:29:40.347368 arm64_sve-ptrace_Set_SVE_VL_544 pass
9027 12:29:40.347472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
9028 12:29:40.347564 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
9029 12:29:40.347652 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
9030 12:29:40.347736 arm64_sve-ptrace_Set_SVE_VL_560 pass
9031 12:29:40.347842 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
9032 12:29:40.347939 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
9033 12:29:40.348029 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
9034 12:29:40.348138 arm64_sve-ptrace_Set_SVE_VL_576 pass
9035 12:29:40.352281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
9036 12:29:40.352659 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
9037 12:29:40.352767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
9038 12:29:40.352861 arm64_sve-ptrace_Set_SVE_VL_592 pass
9039 12:29:40.352971 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
9040 12:29:40.353055 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
9041 12:29:40.353151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
9042 12:29:40.353230 arm64_sve-ptrace_Set_SVE_VL_608 pass
9043 12:29:40.353320 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
9044 12:29:40.353418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
9045 12:29:40.353509 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
9046 12:29:40.353834 arm64_sve-ptrace_Set_SVE_VL_624 pass
9047 12:29:40.354061 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
9048 12:29:40.354299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
9049 12:29:40.354461 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
9050 12:29:40.354609 arm64_sve-ptrace_Set_SVE_VL_640 pass
9051 12:29:40.354754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
9052 12:29:40.354976 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
9053 12:29:40.355140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
9054 12:29:40.355289 arm64_sve-ptrace_Set_SVE_VL_656 pass
9055 12:29:40.355433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
9056 12:29:40.355610 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
9057 12:29:40.355784 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
9058 12:29:40.355965 arm64_sve-ptrace_Set_SVE_VL_672 pass
9059 12:29:40.356141 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
9060 12:29:40.356364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
9061 12:29:40.356523 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
9062 12:29:40.356670 arm64_sve-ptrace_Set_SVE_VL_688 pass
9063 12:29:40.356814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
9064 12:29:40.356958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
9065 12:29:40.357103 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
9066 12:29:40.357251 arm64_sve-ptrace_Set_SVE_VL_704 pass
9067 12:29:40.357394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
9068 12:29:40.357535 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
9069 12:29:40.357719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
9070 12:29:40.357907 arm64_sve-ptrace_Set_SVE_VL_720 pass
9071 12:29:40.360485 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
9072 12:29:40.360708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
9073 12:29:40.361231 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9074 12:29:40.361408 arm64_sve-ptrace_Set_SVE_VL_736 pass
9075 12:29:40.361554 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9076 12:29:40.361717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9077 12:29:40.361925 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9078 12:29:40.362090 arm64_sve-ptrace_Set_SVE_VL_752 pass
9079 12:29:40.362240 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9080 12:29:40.362510 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9081 12:29:40.362703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9082 12:29:40.362875 arm64_sve-ptrace_Set_SVE_VL_768 pass
9083 12:29:40.363037 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9084 12:29:40.363187 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9085 12:29:40.363326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9086 12:29:40.363487 arm64_sve-ptrace_Set_SVE_VL_784 pass
9087 12:29:40.363651 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9088 12:29:40.363802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9089 12:29:40.363953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9090 12:29:40.364088 arm64_sve-ptrace_Set_SVE_VL_800 pass
9091 12:29:40.364241 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9092 12:29:40.364382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9093 12:29:40.364525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9094 12:29:40.364641 arm64_sve-ptrace_Set_SVE_VL_816 pass
9095 12:29:40.364754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9096 12:29:40.364865 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9097 12:29:40.364978 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9098 12:29:40.365093 arm64_sve-ptrace_Set_SVE_VL_832 pass
9099 12:29:40.365208 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9100 12:29:40.365322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9101 12:29:40.365437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9102 12:29:40.365550 arm64_sve-ptrace_Set_SVE_VL_848 pass
9103 12:29:40.366265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9104 12:29:40.366418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9105 12:29:40.366539 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9106 12:29:40.366656 arm64_sve-ptrace_Set_SVE_VL_864 pass
9107 12:29:40.368300 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9108 12:29:40.368619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9109 12:29:40.368725 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9110 12:29:40.368831 arm64_sve-ptrace_Set_SVE_VL_880 pass
9111 12:29:40.368919 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9112 12:29:40.369018 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9113 12:29:40.369375 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9114 12:29:40.369479 arm64_sve-ptrace_Set_SVE_VL_896 pass
9115 12:29:40.369581 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9116 12:29:40.369676 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9117 12:29:40.369777 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9118 12:29:40.370064 arm64_sve-ptrace_Set_SVE_VL_912 pass
9119 12:29:40.370384 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9120 12:29:40.370488 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9121 12:29:40.370579 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9122 12:29:40.370682 arm64_sve-ptrace_Set_SVE_VL_928 pass
9123 12:29:40.371176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9124 12:29:40.371456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9125 12:29:40.371556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9126 12:29:40.371642 arm64_sve-ptrace_Set_SVE_VL_944 pass
9127 12:29:40.371933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9128 12:29:40.372037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9129 12:29:40.372126 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9130 12:29:40.372236 arm64_sve-ptrace_Set_SVE_VL_960 pass
9131 12:29:40.372325 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9132 12:29:40.376418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9133 12:29:40.376538 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9134 12:29:40.376644 arm64_sve-ptrace_Set_SVE_VL_976 pass
9135 12:29:40.376747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9136 12:29:40.377079 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9137 12:29:40.377184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9138 12:29:40.377290 arm64_sve-ptrace_Set_SVE_VL_992 pass
9139 12:29:40.377376 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9140 12:29:40.377663 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9141 12:29:40.377967 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9142 12:29:40.378155 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9143 12:29:40.378280 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9144 12:29:40.378369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9145 12:29:40.378469 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9146 12:29:40.378556 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9147 12:29:40.378656 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9148 12:29:40.378945 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9149 12:29:40.379047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9150 12:29:40.379383 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9151 12:29:40.379487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9152 12:29:40.379590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9153 12:29:40.379901 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9154 12:29:40.380005 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9155 12:29:40.380110 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9156 12:29:40.384298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9157 12:29:40.384810 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9158 12:29:40.385040 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9159 12:29:40.385245 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9160 12:29:40.385430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9161 12:29:40.385570 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9162 12:29:40.385723 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9163 12:29:40.385897 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9164 12:29:40.386072 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9165 12:29:40.386208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9166 12:29:40.386325 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9167 12:29:40.399106 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9168 12:29:40.399609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9169 12:29:40.399715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9170 12:29:40.399804 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9171 12:29:40.399890 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9172 12:29:40.399976 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9173 12:29:40.400084 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9174 12:29:40.400177 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9175 12:29:40.400279 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9176 12:29:40.400570 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9177 12:29:40.400674 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9178 12:29:40.400780 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9179 12:29:40.400886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9180 12:29:40.400987 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9181 12:29:40.401291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9182 12:29:40.401396 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9183 12:29:40.401478 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9184 12:29:40.401568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9185 12:29:40.401654 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9186 12:29:40.401748 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9187 12:29:40.401839 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9188 12:29:40.402115 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9189 12:29:40.402216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9190 12:29:40.402312 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9191 12:29:40.402607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9192 12:29:40.402711 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9193 12:29:40.402791 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9194 12:29:40.402882 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9195 12:29:40.402959 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9196 12:29:40.403049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9197 12:29:40.403142 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9198 12:29:40.403235 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9199 12:29:40.403754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9200 12:29:40.404005 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9201 12:29:40.404160 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9202 12:29:40.404280 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9203 12:29:40.404424 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9204 12:29:40.408196 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9205 12:29:40.408638 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9206 12:29:40.408828 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9207 12:29:40.408999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9208 12:29:40.409203 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9209 12:29:40.409360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9210 12:29:40.409613 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9211 12:29:40.409795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9212 12:29:40.409988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9213 12:29:40.410154 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9214 12:29:40.410348 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9215 12:29:40.410520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9216 12:29:40.410718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9217 12:29:40.410905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9218 12:29:40.411062 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9219 12:29:40.411187 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9220 12:29:40.411303 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9221 12:29:40.411481 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9222 12:29:40.411696 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9223 12:29:40.411924 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9224 12:29:40.412132 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9225 12:29:40.412265 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9226 12:29:40.412391 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9227 12:29:40.412515 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9228 12:29:40.412635 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9229 12:29:40.412761 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9230 12:29:40.412879 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9231 12:29:40.413002 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9232 12:29:40.413126 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9233 12:29:40.413244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9234 12:29:40.413375 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9235 12:29:40.413494 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9236 12:29:40.413622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9237 12:29:40.413752 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9238 12:29:40.413869 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9239 12:29:40.414003 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9240 12:29:40.416163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9241 12:29:40.416594 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9242 12:29:40.416697 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9243 12:29:40.416829 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9244 12:29:40.416935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9245 12:29:40.417042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9246 12:29:40.417132 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9247 12:29:40.417566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9248 12:29:40.417676 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9249 12:29:40.417972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9250 12:29:40.418078 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9251 12:29:40.418159 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9252 12:29:40.418235 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9253 12:29:40.418312 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9254 12:29:40.418402 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9255 12:29:40.418481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9256 12:29:40.418572 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9257 12:29:40.418651 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9258 12:29:40.418739 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9259 12:29:40.418816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9260 12:29:40.418904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9261 12:29:40.419232 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9262 12:29:40.419423 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9263 12:29:40.419627 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9264 12:29:40.419799 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9265 12:29:40.420002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9266 12:29:40.420174 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9267 12:29:40.420305 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9268 12:29:40.420430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9269 12:29:40.424236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9270 12:29:40.424343 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9271 12:29:40.424634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9272 12:29:40.424737 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9273 12:29:40.424841 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9274 12:29:40.424928 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9275 12:29:40.425027 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9276 12:29:40.425126 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9277 12:29:40.425431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9278 12:29:40.425535 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9279 12:29:40.425854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9280 12:29:40.425955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9281 12:29:40.426052 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9282 12:29:40.426130 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9283 12:29:40.426219 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9284 12:29:40.426308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9285 12:29:40.426601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9286 12:29:40.426702 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9287 12:29:40.426792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9288 12:29:40.426967 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9289 12:29:40.427080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9290 12:29:40.427393 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9291 12:29:40.427492 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9292 12:29:40.427586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9293 12:29:40.427676 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9294 12:29:40.427765 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9295 12:29:40.427853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9296 12:29:40.432184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9297 12:29:40.432587 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9298 12:29:40.432694 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9299 12:29:40.432785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9300 12:29:40.432871 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9301 12:29:40.432970 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9302 12:29:40.433056 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9303 12:29:40.433155 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9304 12:29:40.433248 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9305 12:29:40.433349 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9306 12:29:40.433450 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9307 12:29:40.433785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9308 12:29:40.434016 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9309 12:29:40.434194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9310 12:29:40.434366 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9311 12:29:40.434574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9312 12:29:40.434746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9313 12:29:40.434917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9314 12:29:40.435077 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9315 12:29:40.435244 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9316 12:29:40.435458 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9317 12:29:40.435672 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9318 12:29:40.435804 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9319 12:29:40.435929 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9320 12:29:40.436045 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9321 12:29:40.436160 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9322 12:29:40.436278 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9323 12:29:40.436394 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9324 12:29:40.436508 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9325 12:29:40.436623 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9326 12:29:40.436738 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9327 12:29:40.451295 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9328 12:29:40.451584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9329 12:29:40.451798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9330 12:29:40.452265 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9331 12:29:40.452435 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9332 12:29:40.452586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9333 12:29:40.452726 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9334 12:29:40.452871 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9335 12:29:40.453040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9336 12:29:40.453207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9337 12:29:40.453412 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9338 12:29:40.453585 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9339 12:29:40.453800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9340 12:29:40.454030 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9341 12:29:40.454270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9342 12:29:40.454493 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9343 12:29:40.454733 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9344 12:29:40.454972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9345 12:29:40.455195 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9346 12:29:40.455415 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9347 12:29:40.455658 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9348 12:29:40.455921 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9349 12:29:40.456116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9350 12:29:40.456252 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9351 12:29:40.456369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9352 12:29:40.456484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9353 12:29:40.456598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9354 12:29:40.456712 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9355 12:29:40.456825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9356 12:29:40.456937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9357 12:29:40.457051 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9358 12:29:40.457164 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9359 12:29:40.457278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9360 12:29:40.457392 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9361 12:29:40.457504 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9362 12:29:40.457618 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9363 12:29:40.457794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9364 12:29:40.457926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9365 12:29:40.458046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9366 12:29:40.458163 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9367 12:29:40.458280 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9368 12:29:40.458607 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9369 12:29:40.458719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9370 12:29:40.458814 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9371 12:29:40.458905 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9372 12:29:40.460242 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9373 12:29:40.460372 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9374 12:29:40.460692 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9375 12:29:40.460895 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9376 12:29:40.461065 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9377 12:29:40.461270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9378 12:29:40.461448 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9379 12:29:40.461607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9380 12:29:40.461794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9381 12:29:40.461932 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9382 12:29:40.462109 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9383 12:29:40.462236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9384 12:29:40.462358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9385 12:29:40.462475 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9386 12:29:40.462592 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9387 12:29:40.462709 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9388 12:29:40.462825 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9389 12:29:40.462941 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9390 12:29:40.463087 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9391 12:29:40.463209 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9392 12:29:40.463326 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9393 12:29:40.463442 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9394 12:29:40.463558 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9395 12:29:40.463674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9396 12:29:40.463790 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9397 12:29:40.463904 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9398 12:29:40.464020 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9399 12:29:40.464135 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9400 12:29:40.464251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9401 12:29:40.464370 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9402 12:29:40.464513 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9403 12:29:40.464635 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9404 12:29:40.464753 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9405 12:29:40.464870 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9406 12:29:40.464987 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9407 12:29:40.465103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9408 12:29:40.465218 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9409 12:29:40.465334 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9410 12:29:40.465450 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9411 12:29:40.468585 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9412 12:29:40.468804 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9413 12:29:40.469044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9414 12:29:40.469502 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9415 12:29:40.469642 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9416 12:29:40.469776 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9417 12:29:40.469916 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9418 12:29:40.470206 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9419 12:29:40.470329 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9420 12:29:40.470415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9421 12:29:40.470491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9422 12:29:40.470566 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9423 12:29:40.470640 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9424 12:29:40.470733 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9425 12:29:40.470811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9426 12:29:40.470886 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9427 12:29:40.470960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9428 12:29:40.471033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9429 12:29:40.471108 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9430 12:29:40.471181 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9431 12:29:40.471257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9432 12:29:40.471333 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9433 12:29:40.471423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9434 12:29:40.471500 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9435 12:29:40.471574 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9436 12:29:40.473845 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9437 12:29:40.474013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9438 12:29:40.474138 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9439 12:29:40.474306 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9440 12:29:40.474462 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9441 12:29:40.474601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9442 12:29:40.474723 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9443 12:29:40.474840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9444 12:29:40.474957 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9445 12:29:40.476401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9446 12:29:40.476591 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9447 12:29:40.476816 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9448 12:29:40.476989 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9449 12:29:40.477152 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9450 12:29:40.477392 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9451 12:29:40.477598 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9452 12:29:40.478142 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9453 12:29:40.478311 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9454 12:29:40.478665 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9455 12:29:40.478884 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9456 12:29:40.479048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9457 12:29:40.479241 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9458 12:29:40.479457 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9459 12:29:40.479668 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9460 12:29:40.480222 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9461 12:29:40.480413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9462 12:29:40.480558 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9463 12:29:40.480686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9464 12:29:40.480811 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9465 12:29:40.480970 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9466 12:29:40.481103 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9467 12:29:40.481231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9468 12:29:40.481357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9469 12:29:40.481483 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9470 12:29:40.481610 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9471 12:29:40.481753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9472 12:29:40.481879 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9473 12:29:40.482005 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9474 12:29:40.484179 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9475 12:29:40.484481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9476 12:29:40.484581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9477 12:29:40.484678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9478 12:29:40.484758 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9479 12:29:40.484834 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9480 12:29:40.484923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9481 12:29:40.485013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9482 12:29:40.485300 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9483 12:29:40.485401 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9484 12:29:40.485493 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9485 12:29:40.485574 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9486 12:29:40.485676 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9487 12:29:40.502373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9488 12:29:40.502665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9489 12:29:40.503118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9490 12:29:40.503322 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9491 12:29:40.503491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9492 12:29:40.503649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9493 12:29:40.503814 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9494 12:29:40.503980 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9495 12:29:40.504131 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9496 12:29:40.504259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9497 12:29:40.504376 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9498 12:29:40.504490 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9499 12:29:40.504604 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9500 12:29:40.504718 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9501 12:29:40.504939 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9502 12:29:40.505113 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9503 12:29:40.505272 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9504 12:29:40.505419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9505 12:29:40.505558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9506 12:29:40.505733 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9507 12:29:40.505893 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9508 12:29:40.506080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9509 12:29:40.506309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9510 12:29:40.506645 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9511 12:29:40.506845 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9512 12:29:40.507023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9513 12:29:40.507226 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9514 12:29:40.507414 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9515 12:29:40.507597 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9516 12:29:40.507786 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9517 12:29:40.507976 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9518 12:29:40.508147 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9519 12:29:40.508280 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9520 12:29:40.508403 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9521 12:29:40.508520 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9522 12:29:40.508636 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9523 12:29:40.508753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9524 12:29:40.508919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9525 12:29:40.509043 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9526 12:29:40.509379 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9527 12:29:40.509508 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9528 12:29:40.509629 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9529 12:29:40.509801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9530 12:29:40.509946 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9531 12:29:40.510067 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9532 12:29:40.510184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9533 12:29:40.510350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9534 12:29:40.510482 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9535 12:29:40.510600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9536 12:29:40.510717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9537 12:29:40.510833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9538 12:29:40.510950 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9539 12:29:40.512221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9540 12:29:40.512656 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9541 12:29:40.513830 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9542 12:29:40.514030 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9543 12:29:40.514200 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9544 12:29:40.514413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9545 12:29:40.514602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9546 12:29:40.514778 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9547 12:29:40.514953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9548 12:29:40.515161 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9549 12:29:40.515372 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9550 12:29:40.515589 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9551 12:29:40.515794 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9552 12:29:40.516052 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9553 12:29:40.516468 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9554 12:29:40.516611 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9555 12:29:40.516734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9556 12:29:40.516855 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9557 12:29:40.516972 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9558 12:29:40.517089 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9559 12:29:40.517205 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9560 12:29:40.517322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9561 12:29:40.517440 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9562 12:29:40.517558 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9563 12:29:40.517716 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9564 12:29:40.517897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9565 12:29:40.518060 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9566 12:29:40.518210 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9567 12:29:40.518330 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9568 12:29:40.518465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9569 12:29:40.518621 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9570 12:29:40.518740 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9571 12:29:40.518854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9572 12:29:40.520253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9573 12:29:40.520357 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9574 12:29:40.520638 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9575 12:29:40.520725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9576 12:29:40.520802 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9577 12:29:40.520891 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9578 12:29:40.520968 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9579 12:29:40.521057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9580 12:29:40.521344 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9581 12:29:40.521459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9582 12:29:40.521539 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9583 12:29:40.521627 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9584 12:29:40.521717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9585 12:29:40.522181 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9586 12:29:40.522280 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9587 12:29:40.522359 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9588 12:29:40.522441 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9589 12:29:40.522518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9590 12:29:40.522592 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9591 12:29:40.522865 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9592 12:29:40.522964 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9593 12:29:40.523042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9594 12:29:40.523118 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9595 12:29:40.523192 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9596 12:29:40.523280 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9597 12:29:40.523357 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9598 12:29:40.523432 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9599 12:29:40.523520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9600 12:29:40.523596 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9601 12:29:40.523901 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9602 12:29:40.524001 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9603 12:29:40.524078 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9604 12:29:40.524166 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9605 12:29:40.528184 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9606 12:29:40.528530 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9607 12:29:40.528703 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9608 12:29:40.528843 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9609 12:29:40.528945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9610 12:29:40.529169 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9611 12:29:40.529282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9612 12:29:40.529362 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9613 12:29:40.529637 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9614 12:29:40.529744 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9615 12:29:40.529820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9616 12:29:40.529909 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9617 12:29:40.529989 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9618 12:29:40.530070 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9619 12:29:40.530160 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9620 12:29:40.530239 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9621 12:29:40.530504 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9622 12:29:40.530586 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9623 12:29:40.530664 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9624 12:29:40.530742 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9625 12:29:40.530830 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9626 12:29:40.530907 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9627 12:29:40.530980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9628 12:29:40.531066 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9629 12:29:40.531156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9630 12:29:40.531244 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9631 12:29:40.531519 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9632 12:29:40.531619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9633 12:29:40.531710 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9634 12:29:40.531787 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9635 12:29:40.531875 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9636 12:29:40.532160 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9637 12:29:40.540377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9638 12:29:40.540544 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9639 12:29:40.540617 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9640 12:29:40.540897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9641 12:29:40.541089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9642 12:29:40.541269 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9643 12:29:40.541417 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9644 12:29:40.541599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9645 12:29:40.541788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9646 12:29:40.541990 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9647 12:29:40.562405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9648 12:29:40.562642 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9649 12:29:40.563089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9650 12:29:40.563282 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9651 12:29:40.563448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9652 12:29:40.563616 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9653 12:29:40.563820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9654 12:29:40.564000 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9655 12:29:40.564180 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9656 12:29:40.564347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9657 12:29:40.564519 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9658 12:29:40.564692 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9659 12:29:40.564853 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9660 12:29:40.565059 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9661 12:29:40.565231 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9662 12:29:40.565395 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9663 12:29:40.565568 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9664 12:29:40.565749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9665 12:29:40.565910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9666 12:29:40.566074 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9667 12:29:40.566235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9668 12:29:40.566446 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9669 12:29:40.566624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9670 12:29:40.566792 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9671 12:29:40.566955 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9672 12:29:40.567120 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9673 12:29:40.567280 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9674 12:29:40.567413 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9675 12:29:40.567575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9676 12:29:40.567748 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9677 12:29:40.567920 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9678 12:29:40.568060 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9679 12:29:40.568208 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9680 12:29:40.568328 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9681 12:29:40.568448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9682 12:29:40.568564 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9683 12:29:40.568679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9684 12:29:40.568801 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9685 12:29:40.568917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9686 12:29:40.569230 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9687 12:29:40.569310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9688 12:29:40.569394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9689 12:29:40.569466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9690 12:29:40.572496 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9691 12:29:40.572602 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9692 12:29:40.572889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9693 12:29:40.572992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9694 12:29:40.573117 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9695 12:29:40.573221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9696 12:29:40.573317 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9697 12:29:40.573428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9698 12:29:40.573525 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9699 12:29:40.573638 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9700 12:29:40.573749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9701 12:29:40.573880 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9702 12:29:40.573984 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9703 12:29:40.574114 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9704 12:29:40.574476 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9705 12:29:40.574584 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9706 12:29:40.574690 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9707 12:29:40.574779 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9708 12:29:40.574855 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9709 12:29:40.574942 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9710 12:29:40.575032 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9711 12:29:40.575114 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9712 12:29:40.575399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9713 12:29:40.575504 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9714 12:29:40.575600 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9715 12:29:40.575681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9716 12:29:40.575762 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9717 12:29:40.576030 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9718 12:29:40.576126 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9719 12:29:40.580298 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9720 12:29:40.580404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9721 12:29:40.580686 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9722 12:29:40.580774 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9723 12:29:40.580847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9724 12:29:40.580926 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9725 12:29:40.581002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9726 12:29:40.581075 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9727 12:29:40.581348 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9728 12:29:40.581654 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9729 12:29:40.581766 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9730 12:29:40.581876 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9731 12:29:40.582007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9732 12:29:40.582105 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9733 12:29:40.582215 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9734 12:29:40.582325 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9735 12:29:40.582414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9736 12:29:40.582498 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9737 12:29:40.582613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9738 12:29:40.582721 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9739 12:29:40.582836 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9740 12:29:40.582923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9741 12:29:40.583221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9742 12:29:40.583308 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9743 12:29:40.583383 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9744 12:29:40.583472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9745 12:29:40.583559 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9746 12:29:40.583641 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9747 12:29:40.583935 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9748 12:29:40.584027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9749 12:29:40.588297 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9750 12:29:40.588760 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9751 12:29:40.588932 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9752 12:29:40.589094 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9753 12:29:40.589249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9754 12:29:40.589430 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9755 12:29:40.589573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9756 12:29:40.589761 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9757 12:29:40.589963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9758 12:29:40.590162 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9759 12:29:40.590375 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9760 12:29:40.590558 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9761 12:29:40.590756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9762 12:29:40.590914 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9763 12:29:40.591042 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9764 12:29:40.591160 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9765 12:29:40.591275 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9766 12:29:40.591388 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9767 12:29:40.591530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9768 12:29:40.591650 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9769 12:29:40.591775 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9770 12:29:40.591929 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9771 12:29:40.592145 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9772 12:29:40.592308 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9773 12:29:40.592437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9774 12:29:40.592553 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9775 12:29:40.592667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9776 12:29:40.592782 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9777 12:29:40.592897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9778 12:29:40.593009 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9779 12:29:40.593123 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9780 12:29:40.597034 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9781 12:29:40.597227 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9782 12:29:40.597377 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9783 12:29:40.597562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9784 12:29:40.597751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9785 12:29:40.597895 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9786 12:29:40.598013 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9787 12:29:40.598391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9788 12:29:40.598532 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9789 12:29:40.598688 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9790 12:29:40.598821 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9791 12:29:40.598943 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9792 12:29:40.599095 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9793 12:29:40.599226 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9794 12:29:40.599354 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9795 12:29:40.599539 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9796 12:29:40.599701 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9797 12:29:40.599830 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9798 12:29:40.599946 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9799 12:29:40.600092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9800 12:29:40.600214 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9801 12:29:40.600330 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9802 12:29:40.600445 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9803 12:29:40.600562 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9804 12:29:40.600677 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9805 12:29:40.600792 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9806 12:29:40.600907 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9807 12:29:40.629556 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9808 12:29:40.629695 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9809 12:29:40.630011 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9810 12:29:40.630106 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9811 12:29:40.630184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9812 12:29:40.630288 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9813 12:29:40.630379 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9814 12:29:40.631956 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9815 12:29:40.632060 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9816 12:29:40.632139 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9817 12:29:40.632202 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9818 12:29:40.632265 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9819 12:29:40.632380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9820 12:29:40.632492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9821 12:29:40.632613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9822 12:29:40.632717 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9823 12:29:40.632820 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9824 12:29:40.632936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9825 12:29:40.633279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9826 12:29:40.633370 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9827 12:29:40.633453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9828 12:29:40.633518 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9829 12:29:40.633577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9830 12:29:40.633640 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9831 12:29:40.633714 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9832 12:29:40.633773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9833 12:29:40.633851 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9834 12:29:40.633913 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9835 12:29:40.633991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9836 12:29:40.634064 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9837 12:29:40.634160 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9838 12:29:40.634255 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9839 12:29:40.634323 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9840 12:29:40.634387 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9841 12:29:40.634484 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9842 12:29:40.634550 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9843 12:29:40.634608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9844 12:29:40.634682 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9845 12:29:40.634771 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9846 12:29:40.634838 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9847 12:29:40.634918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9848 12:29:40.634995 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9849 12:29:40.635069 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9850 12:29:40.635131 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9851 12:29:40.635202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9852 12:29:40.635283 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9853 12:29:40.635362 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9854 12:29:40.635617 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9855 12:29:40.635701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9856 12:29:40.635778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9857 12:29:40.635892 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9858 12:29:40.636011 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9859 12:29:40.636116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9860 12:29:40.640207 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9861 12:29:40.640503 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9862 12:29:40.640779 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9863 12:29:40.640885 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9864 12:29:40.640985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9865 12:29:40.641062 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9866 12:29:40.641128 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9867 12:29:40.641211 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9868 12:29:40.641291 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9869 12:29:40.641550 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9870 12:29:40.641630 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9871 12:29:40.641706 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9872 12:29:40.641786 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9873 12:29:40.642072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9874 12:29:40.642156 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9875 12:29:40.642253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9876 12:29:40.642341 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9877 12:29:40.642413 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9878 12:29:40.642485 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9879 12:29:40.642589 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9880 12:29:40.642867 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9881 12:29:40.642964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9882 12:29:40.643051 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9883 12:29:40.643156 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9884 12:29:40.643264 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9885 12:29:40.643387 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9886 12:29:40.643473 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9887 12:29:40.643565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9888 12:29:40.643661 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9889 12:29:40.643973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9890 12:29:40.644134 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9891 12:29:40.644257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9892 12:29:40.648199 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9893 12:29:40.648624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9894 12:29:40.648814 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9895 12:29:40.648989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9896 12:29:40.649180 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9897 12:29:40.649343 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9898 12:29:40.649493 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9899 12:29:40.649628 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9900 12:29:40.649805 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9901 12:29:40.649971 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9902 12:29:40.650111 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9903 12:29:40.650278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9904 12:29:40.650448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9905 12:29:40.650588 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9906 12:29:40.650708 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9907 12:29:40.650945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9908 12:29:40.651135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9909 12:29:40.651305 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9910 12:29:40.651486 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9911 12:29:40.651663 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9912 12:29:40.651891 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9913 12:29:40.652080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9914 12:29:40.652254 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9915 12:29:40.652416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9916 12:29:40.652539 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9917 12:29:40.652657 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9918 12:29:40.652772 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9919 12:29:40.652886 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9920 12:29:40.653000 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9921 12:29:40.653115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9922 12:29:40.653230 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9923 12:29:40.653343 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9924 12:29:40.660213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9925 12:29:40.660660 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9926 12:29:40.660769 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9927 12:29:40.660864 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9928 12:29:40.660970 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9929 12:29:40.661077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9930 12:29:40.661167 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9931 12:29:40.661254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9932 12:29:40.661358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9933 12:29:40.661448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9934 12:29:40.661537 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9935 12:29:40.661654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9936 12:29:40.661757 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9937 12:29:40.661843 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9938 12:29:40.661945 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9939 12:29:40.662033 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9940 12:29:40.662343 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9941 12:29:40.662447 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9942 12:29:40.662537 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9943 12:29:40.662857 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9944 12:29:40.662960 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9945 12:29:40.663048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9946 12:29:40.663151 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9947 12:29:40.663236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9948 12:29:40.663332 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9949 12:29:40.663417 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9950 12:29:40.663521 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9951 12:29:40.663612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9952 12:29:40.663715 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9953 12:29:40.663820 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9954 12:29:40.663925 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9955 12:29:40.668734 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9956 12:29:40.670029 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9957 12:29:40.670196 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9958 12:29:40.670343 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9959 12:29:40.670479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9960 12:29:40.670611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9961 12:29:40.670708 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9962 12:29:40.670799 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9963 12:29:40.670890 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9964 12:29:40.670981 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9965 12:29:40.671071 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9966 12:29:40.671149 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9967 12:29:40.694958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9968 12:29:40.695389 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9969 12:29:40.695480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9970 12:29:40.695552 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9971 12:29:40.695621 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9972 12:29:40.695704 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9973 12:29:40.695783 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9974 12:29:40.695862 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9975 12:29:40.695940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9976 12:29:40.696388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9977 12:29:40.696485 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9978 12:29:40.696553 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9979 12:29:40.696800 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9980 12:29:40.696871 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9981 12:29:40.697116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9982 12:29:40.697198 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9983 12:29:40.697446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9984 12:29:40.697516 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9985 12:29:40.697592 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9986 12:29:40.697667 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9987 12:29:40.697744 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9988 12:29:40.697820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9989 12:29:40.698073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9990 12:29:40.698144 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9991 12:29:40.698221 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9992 12:29:40.698469 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9993 12:29:40.698551 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9994 12:29:40.698798 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9995 12:29:40.698874 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9996 12:29:40.698951 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9997 12:29:40.699204 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9998 12:29:40.699281 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9999 12:29:40.699523 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
10000 12:29:40.699590 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
10001 12:29:40.699837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
10002 12:29:40.699905 arm64_sve-ptrace_Set_SVE_VL_4448 pass
10003 12:29:40.699977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
10004 12:29:40.700040 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
10005 12:29:40.704236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
10006 12:29:40.704598 arm64_sve-ptrace_Set_SVE_VL_4464 pass
10007 12:29:40.704667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
10008 12:29:40.704732 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
10009 12:29:40.704806 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
10010 12:29:40.704882 arm64_sve-ptrace_Set_SVE_VL_4480 pass
10011 12:29:40.705128 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
10012 12:29:40.705197 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
10013 12:29:40.705440 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
10014 12:29:40.705506 arm64_sve-ptrace_Set_SVE_VL_4496 pass
10015 12:29:40.705766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
10016 12:29:40.705873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
10017 12:29:40.705943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
10018 12:29:40.706008 arm64_sve-ptrace_Set_SVE_VL_4512 pass
10019 12:29:40.706252 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
10020 12:29:40.706320 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
10021 12:29:40.706392 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
10022 12:29:40.706457 arm64_sve-ptrace_Set_SVE_VL_4528 pass
10023 12:29:40.706541 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
10024 12:29:40.706794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
10025 12:29:40.706871 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
10026 12:29:40.707113 arm64_sve-ptrace_Set_SVE_VL_4544 pass
10027 12:29:40.707180 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
10028 12:29:40.707253 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
10029 12:29:40.707534 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
10030 12:29:40.707603 arm64_sve-ptrace_Set_SVE_VL_4560 pass
10031 12:29:40.707843 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
10032 12:29:40.707937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
10033 12:29:40.708002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
10034 12:29:40.708074 arm64_sve-ptrace_Set_SVE_VL_4576 pass
10035 12:29:40.712433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
10036 12:29:40.712622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
10037 12:29:40.712882 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
10038 12:29:40.712950 arm64_sve-ptrace_Set_SVE_VL_4592 pass
10039 12:29:40.713013 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
10040 12:29:40.713075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
10041 12:29:40.713151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
10042 12:29:40.713214 arm64_sve-ptrace_Set_SVE_VL_4608 pass
10043 12:29:40.713479 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
10044 12:29:40.713582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
10045 12:29:40.713671 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
10046 12:29:40.713740 arm64_sve-ptrace_Set_SVE_VL_4624 pass
10047 12:29:40.713824 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
10048 12:29:40.713934 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
10049 12:29:40.714198 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
10050 12:29:40.714275 arm64_sve-ptrace_Set_SVE_VL_4640 pass
10051 12:29:40.714518 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
10052 12:29:40.714596 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
10053 12:29:40.714671 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
10054 12:29:40.714748 arm64_sve-ptrace_Set_SVE_VL_4656 pass
10055 12:29:40.714996 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
10056 12:29:40.715074 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
10057 12:29:40.715323 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
10058 12:29:40.715389 arm64_sve-ptrace_Set_SVE_VL_4672 pass
10059 12:29:40.715462 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
10060 12:29:40.715536 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
10061 12:29:40.715950 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
10062 12:29:40.716020 arm64_sve-ptrace_Set_SVE_VL_4688 pass
10063 12:29:40.716257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
10064 12:29:40.720340 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
10065 12:29:40.720722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
10066 12:29:40.720824 arm64_sve-ptrace_Set_SVE_VL_4704 pass
10067 12:29:40.720903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
10068 12:29:40.720996 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
10069 12:29:40.721084 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
10070 12:29:40.721170 arm64_sve-ptrace_Set_SVE_VL_4720 pass
10071 12:29:40.721260 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
10072 12:29:40.721547 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
10073 12:29:40.721816 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10074 12:29:40.721905 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10075 12:29:40.721994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10076 12:29:40.722065 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10077 12:29:40.722326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10078 12:29:40.722579 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10079 12:29:40.722648 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10080 12:29:40.722724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10081 12:29:40.722789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10082 12:29:40.722863 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10083 12:29:40.722972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10084 12:29:40.723294 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10085 12:29:40.723577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10086 12:29:40.723671 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10087 12:29:40.723774 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10088 12:29:40.723873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10089 12:29:40.723945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10090 12:29:40.724020 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10091 12:29:40.728211 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10092 12:29:40.728610 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10093 12:29:40.728713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10094 12:29:40.728797 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10095 12:29:40.728945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10096 12:29:40.729047 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10097 12:29:40.729138 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10098 12:29:40.729212 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10099 12:29:40.729289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10100 12:29:40.729381 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10101 12:29:40.729471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10102 12:29:40.729989 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10103 12:29:40.730090 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10104 12:29:40.730181 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10105 12:29:40.730258 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10106 12:29:40.730532 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10107 12:29:40.730652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10108 12:29:40.730745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10109 12:29:40.730828 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10110 12:29:40.730918 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10111 12:29:40.731031 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10112 12:29:40.731121 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10113 12:29:40.731192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10114 12:29:40.731254 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10115 12:29:40.731326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10116 12:29:40.731584 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10117 12:29:40.731681 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10118 12:29:40.731781 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10119 12:29:40.731863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10120 12:29:40.731935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10121 12:29:40.732013 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10122 12:29:40.736260 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10123 12:29:40.736674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10124 12:29:40.736756 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10125 12:29:40.736821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10126 12:29:40.736883 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10127 12:29:40.755536 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10128 12:29:40.756143 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10129 12:29:40.756351 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10130 12:29:40.756537 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10131 12:29:40.756755 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10132 12:29:40.756936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10133 12:29:40.757057 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10134 12:29:40.757173 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10135 12:29:40.757288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10136 12:29:40.757404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10137 12:29:40.757522 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10138 12:29:40.757643 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10139 12:29:40.757817 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10140 12:29:40.757898 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10141 12:29:40.757961 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10142 12:29:40.758027 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10143 12:29:40.758091 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10144 12:29:40.758157 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10145 12:29:40.758222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10146 12:29:40.758299 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10147 12:29:40.758375 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10148 12:29:40.758452 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10149 12:29:40.758543 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10150 12:29:40.758615 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10151 12:29:40.758679 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10152 12:29:40.758743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10153 12:29:40.758803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10154 12:29:40.758862 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10155 12:29:40.758965 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10156 12:29:40.759048 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10157 12:29:40.759115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10158 12:29:40.759192 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10159 12:29:40.759270 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10160 12:29:40.759347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10161 12:29:40.759421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10162 12:29:40.759500 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10163 12:29:40.759833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10164 12:29:40.759985 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10165 12:29:40.760087 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10166 12:29:40.764184 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10167 12:29:40.764608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10168 12:29:40.764709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10169 12:29:40.764789 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10170 12:29:40.764863 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10171 12:29:40.764945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10172 12:29:40.765011 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10173 12:29:40.765094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10174 12:29:40.765170 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10175 12:29:40.765261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10176 12:29:40.765561 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10177 12:29:40.765682 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10178 12:29:40.765766 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10179 12:29:40.765852 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10180 12:29:40.765943 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10181 12:29:40.766023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10182 12:29:40.766127 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10183 12:29:40.766218 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10184 12:29:40.767686 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10185 12:29:40.767863 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10186 12:29:40.767958 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10187 12:29:40.768048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10188 12:29:40.768137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10189 12:29:40.768219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10190 12:29:40.768296 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10191 12:29:40.768372 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10192 12:29:40.768448 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10193 12:29:40.768524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10194 12:29:40.768600 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10195 12:29:40.768903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10196 12:29:40.769015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10197 12:29:40.772322 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10198 12:29:40.772574 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10199 12:29:40.772887 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10200 12:29:40.772997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10201 12:29:40.773092 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10202 12:29:40.773182 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10203 12:29:40.773269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10204 12:29:40.773375 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10205 12:29:40.773463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10206 12:29:40.773553 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10207 12:29:40.773858 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10208 12:29:40.773969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10209 12:29:40.774056 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10210 12:29:40.774140 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10211 12:29:40.774226 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10212 12:29:40.774326 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10213 12:29:40.774412 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10214 12:29:40.774513 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10215 12:29:40.774803 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10216 12:29:40.774975 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10217 12:29:40.775068 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10218 12:29:40.775168 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10219 12:29:40.775254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10220 12:29:40.775349 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10221 12:29:40.775641 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10222 12:29:40.775749 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10223 12:29:40.775848 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10224 12:29:40.776215 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10225 12:29:40.780229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10226 12:29:40.780769 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10227 12:29:40.780882 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10228 12:29:40.780977 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10229 12:29:40.781063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10230 12:29:40.781164 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10231 12:29:40.781251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10232 12:29:40.781355 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10233 12:29:40.781443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10234 12:29:40.781544 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10235 12:29:40.781860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10236 12:29:40.781972 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10237 12:29:40.782073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10238 12:29:40.782353 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10239 12:29:40.782694 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10240 12:29:40.782800 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10241 12:29:40.783090 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10242 12:29:40.783195 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10243 12:29:40.783282 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10244 12:29:40.783368 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10245 12:29:40.783470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10246 12:29:40.783559 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10247 12:29:40.783661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10248 12:29:40.783749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10249 12:29:40.783842 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10250 12:29:40.783942 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10251 12:29:40.788445 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10252 12:29:40.788692 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10253 12:29:40.788992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10254 12:29:40.789087 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10255 12:29:40.789173 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10256 12:29:40.789262 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10257 12:29:40.789367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10258 12:29:40.789456 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10259 12:29:40.789557 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10260 12:29:40.789670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10261 12:29:40.789975 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10262 12:29:40.790095 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10263 12:29:40.790181 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10264 12:29:40.790473 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10265 12:29:40.790591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10266 12:29:40.790683 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10267 12:29:40.790771 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10268 12:29:40.790875 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10269 12:29:40.790970 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10270 12:29:40.791058 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10271 12:29:40.791159 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10272 12:29:40.791456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10273 12:29:40.791549 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10274 12:29:40.791655 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10275 12:29:40.791745 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10276 12:29:40.791834 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10277 12:29:40.791942 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10278 12:29:40.792047 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10279 12:29:40.796251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10280 12:29:40.796505 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10281 12:29:40.796824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10282 12:29:40.796935 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10283 12:29:40.797025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10284 12:29:40.797124 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10285 12:29:40.797206 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10286 12:29:40.797288 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10287 12:29:40.811234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10288 12:29:40.811489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10289 12:29:40.811799 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10290 12:29:40.811903 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10291 12:29:40.811994 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10292 12:29:40.812075 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10293 12:29:40.812159 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10294 12:29:40.812258 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10295 12:29:40.812361 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10296 12:29:40.812457 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10297 12:29:40.812572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10298 12:29:40.812706 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10299 12:29:40.812815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10300 12:29:40.812922 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10301 12:29:40.813047 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10302 12:29:40.813144 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10303 12:29:40.813239 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10304 12:29:40.813354 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10305 12:29:40.813441 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10306 12:29:40.813537 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10307 12:29:40.813656 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10308 12:29:40.813730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10309 12:29:40.813804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10310 12:29:40.813874 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10311 12:29:40.814425 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10312 12:29:40.814524 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10313 12:29:40.814813 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10314 12:29:40.814913 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10315 12:29:40.814980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10316 12:29:40.815041 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10317 12:29:40.815115 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10318 12:29:40.815191 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10319 12:29:40.815254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10320 12:29:40.815522 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10321 12:29:40.815610 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10322 12:29:40.815719 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10323 12:29:40.815795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10324 12:29:40.816073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10325 12:29:40.816175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10326 12:29:40.816272 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10327 12:29:40.820383 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10328 12:29:40.820621 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10329 12:29:40.820715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10330 12:29:40.820820 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10331 12:29:40.821103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10332 12:29:40.821187 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10333 12:29:40.821309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10334 12:29:40.821607 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10335 12:29:40.821900 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10336 12:29:40.821997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10337 12:29:40.822101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10338 12:29:40.822189 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10339 12:29:40.822294 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10340 12:29:40.822397 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10341 12:29:40.822685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10342 12:29:40.822788 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10343 12:29:40.822892 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10344 12:29:40.823005 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10345 12:29:40.823307 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10346 12:29:40.823408 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10347 12:29:40.823508 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10348 12:29:40.823587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10349 12:29:40.823832 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10350 12:29:40.823898 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10351 12:29:40.824161 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10352 12:29:40.824260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10353 12:29:40.828302 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10354 12:29:40.828549 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10355 12:29:40.828880 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10356 12:29:40.828997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10357 12:29:40.829090 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10358 12:29:40.829176 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10359 12:29:40.829265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10360 12:29:40.829375 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10361 12:29:40.829467 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10362 12:29:40.829557 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10363 12:29:40.829642 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10364 12:29:40.829754 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10365 12:29:40.829837 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10366 12:29:40.829939 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10367 12:29:40.830025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10368 12:29:40.830127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10369 12:29:40.830229 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10370 12:29:40.830334 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10371 12:29:40.830759 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10372 12:29:40.830963 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10373 12:29:40.831070 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10374 12:29:40.831176 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10375 12:29:40.831264 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10376 12:29:40.831347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10377 12:29:40.831431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10378 12:29:40.831534 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10379 12:29:40.831618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10380 12:29:40.831703 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10381 12:29:40.831801 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10382 12:29:40.831903 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10383 12:29:40.832011 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10384 12:29:40.836322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10385 12:29:40.836594 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10386 12:29:40.836682 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10387 12:29:40.836972 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10388 12:29:40.837072 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10389 12:29:40.837154 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10390 12:29:40.837232 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10391 12:29:40.837309 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10392 12:29:40.837404 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10393 12:29:40.837487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10394 12:29:40.837565 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10395 12:29:40.837667 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10396 12:29:40.837746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10397 12:29:40.837835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10398 12:29:40.838104 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10399 12:29:40.838188 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10400 12:29:40.838266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10401 12:29:40.838358 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10402 12:29:40.838453 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10403 12:29:40.838544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10404 12:29:40.838634 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10405 12:29:40.838729 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10406 12:29:40.838819 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10407 12:29:40.839111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10408 12:29:40.839220 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10409 12:29:40.839295 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10410 12:29:40.839380 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10411 12:29:40.839467 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10412 12:29:40.839663 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10413 12:29:40.839772 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10414 12:29:40.840056 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10415 12:29:40.844302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10416 12:29:40.844738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10417 12:29:40.844877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10418 12:29:40.844968 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10419 12:29:40.845059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10420 12:29:40.845163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10421 12:29:40.845251 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10422 12:29:40.845337 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10423 12:29:40.845555 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10424 12:29:40.845669 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10425 12:29:40.845758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10426 12:29:40.845860 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10427 12:29:40.845949 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10428 12:29:40.846034 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10429 12:29:40.846136 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10430 12:29:40.846224 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10431 12:29:40.846324 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10432 12:29:40.846426 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10433 12:29:40.846527 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10434 12:29:40.846967 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10435 12:29:40.847080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10436 12:29:40.847169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10437 12:29:40.847269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10438 12:29:40.847357 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10439 12:29:40.847443 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10440 12:29:40.847543 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10441 12:29:40.847626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10442 12:29:40.847892 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10443 12:29:40.847992 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10444 12:29:40.848089 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10445 12:29:40.852269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10446 12:29:40.852523 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10447 12:29:40.867092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10448 12:29:40.867447 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10449 12:29:40.867855 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10450 12:29:40.867962 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10451 12:29:40.868053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10452 12:29:40.868141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10453 12:29:40.868230 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10454 12:29:40.868315 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10455 12:29:40.868400 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10456 12:29:40.868502 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10457 12:29:40.868587 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10458 12:29:40.868669 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10459 12:29:40.868951 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10460 12:29:40.869052 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10461 12:29:40.869133 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10462 12:29:40.869216 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10463 12:29:40.869288 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10464 12:29:40.869362 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10465 12:29:40.869456 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10466 12:29:40.869550 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10467 12:29:40.869854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10468 12:29:40.869998 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10469 12:29:40.870111 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10470 12:29:40.870204 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10471 12:29:40.870308 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10472 12:29:40.870394 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10473 12:29:40.870687 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10474 12:29:40.870780 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10475 12:29:40.870881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10476 12:29:40.870982 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10477 12:29:40.871291 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10478 12:29:40.871399 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10479 12:29:40.871495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10480 12:29:40.871599 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10481 12:29:40.871703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10482 12:29:40.871807 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10483 12:29:40.871916 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10484 12:29:40.876310 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10485 12:29:40.876705 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10486 12:29:40.876819 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10487 12:29:40.876907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10488 12:29:40.876993 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10489 12:29:40.877091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10490 12:29:40.877164 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10491 12:29:40.877235 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10492 12:29:40.877310 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10493 12:29:40.877411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10494 12:29:40.877491 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10495 12:29:40.877588 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10496 12:29:40.877703 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10497 12:29:40.877805 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10498 12:29:40.877907 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10499 12:29:40.878201 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10500 12:29:40.878298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10501 12:29:40.878398 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10502 12:29:40.878499 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10503 12:29:40.878572 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10504 12:29:40.878654 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10505 12:29:40.878741 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10506 12:29:40.878842 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10507 12:29:40.879127 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10508 12:29:40.879224 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10509 12:29:40.879325 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10510 12:29:40.879602 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10511 12:29:40.879696 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10512 12:29:40.879798 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10513 12:29:40.879872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10514 12:29:40.879953 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10515 12:29:40.884373 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10516 12:29:40.884794 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10517 12:29:40.884969 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10518 12:29:40.885129 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10519 12:29:40.885301 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10520 12:29:40.885497 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10521 12:29:40.885710 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10522 12:29:40.885893 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10523 12:29:40.886089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10524 12:29:40.886240 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10525 12:29:40.886378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10526 12:29:40.886517 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10527 12:29:40.886692 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10528 12:29:40.886832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10529 12:29:40.886963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10530 12:29:40.887072 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10531 12:29:40.887164 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10532 12:29:40.887267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10533 12:29:40.887356 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10534 12:29:40.887441 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10535 12:29:40.887550 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10536 12:29:40.887670 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10537 12:29:40.887773 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10538 12:29:40.888081 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10539 12:29:40.888201 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10540 12:29:40.888282 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10541 12:29:40.893779 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10542 12:29:40.893979 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10543 12:29:40.894088 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10544 12:29:40.894183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10545 12:29:40.894283 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10546 12:29:40.894392 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10547 12:29:40.894500 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10548 12:29:40.894602 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10549 12:29:40.894705 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10550 12:29:40.894811 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10551 12:29:40.894903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10552 12:29:40.894976 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10553 12:29:40.895044 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10554 12:29:40.895138 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10555 12:29:40.895566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10556 12:29:40.895652 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10557 12:29:40.895721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10558 12:29:40.895785 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10559 12:29:40.895849 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10560 12:29:40.895912 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10561 12:29:40.895976 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10562 12:29:40.896038 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10563 12:29:40.896099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10564 12:29:40.896159 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10565 12:29:40.896221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10566 12:29:40.896281 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10567 12:29:40.896356 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10568 12:29:40.896419 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10569 12:29:40.896480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10570 12:29:40.896541 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10571 12:29:40.900232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10572 12:29:40.900333 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10573 12:29:40.900640 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10574 12:29:40.900750 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10575 12:29:40.900850 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10576 12:29:40.900956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10577 12:29:40.901058 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10578 12:29:40.901171 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10579 12:29:40.901275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10580 12:29:40.901573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10581 12:29:40.901703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10582 12:29:40.901843 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10583 12:29:40.901937 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10584 12:29:40.902033 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10585 12:29:40.902120 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10586 12:29:40.902217 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10587 12:29:40.902499 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10588 12:29:40.902611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10589 12:29:40.902717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10590 12:29:40.902806 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10591 12:29:40.902899 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10592 12:29:40.902998 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10593 12:29:40.903096 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10594 12:29:40.903482 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10595 12:29:40.903593 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10596 12:29:40.903667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10597 12:29:40.903748 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10598 12:29:40.903831 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10599 12:29:40.908132 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10600 12:29:40.908434 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10601 12:29:40.908560 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10602 12:29:40.908665 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10603 12:29:40.908766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10604 12:29:40.909060 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10605 12:29:40.909146 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10606 12:29:40.909222 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10607 12:29:40.924934 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10608 12:29:40.925295 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10609 12:29:40.925411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10610 12:29:40.925505 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10611 12:29:40.925608 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10612 12:29:40.925706 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10613 12:29:40.925811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10614 12:29:40.925901 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10615 12:29:40.926206 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10616 12:29:40.926312 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10617 12:29:40.926419 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10618 12:29:40.926512 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10619 12:29:40.926619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10620 12:29:40.926724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10621 12:29:40.926827 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10622 12:29:40.927127 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10623 12:29:40.927231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10624 12:29:40.927337 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10625 12:29:40.927684 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10626 12:29:40.927809 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10627 12:29:40.927919 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10628 12:29:40.928023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10629 12:29:40.932179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10630 12:29:40.932480 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10631 12:29:40.932592 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10632 12:29:40.932696 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10633 12:29:40.932785 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10634 12:29:40.932873 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10635 12:29:40.932973 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10636 12:29:40.933077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10637 12:29:40.933166 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10638 12:29:40.933266 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10639 12:29:40.933380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10640 12:29:40.933500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10641 12:29:40.933599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10642 12:29:40.933723 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10643 12:29:40.934032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10644 12:29:40.934148 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10645 12:29:40.934279 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10646 12:29:40.934381 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10647 12:29:40.934470 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10648 12:29:40.934768 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10649 12:29:40.934888 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10650 12:29:40.934978 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10651 12:29:40.935079 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10652 12:29:40.935184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10653 12:29:40.935487 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10654 12:29:40.935596 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10655 12:29:40.935683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10656 12:29:40.935781 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10657 12:29:40.936079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10658 12:29:40.940109 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10659 12:29:40.940495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10660 12:29:40.940596 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10661 12:29:40.940683 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10662 12:29:40.940770 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10663 12:29:40.940869 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10664 12:29:40.941176 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10665 12:29:40.941292 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10666 12:29:40.941394 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10667 12:29:40.941725 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10668 12:29:40.941838 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10669 12:29:40.941940 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10670 12:29:40.942023 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10671 12:29:40.942104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10672 12:29:40.942387 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10673 12:29:40.942496 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10674 12:29:40.942597 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10675 12:29:40.942686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10676 12:29:40.942864 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10677 12:29:40.942997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10678 12:29:40.945808 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10679 12:29:40.946057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10680 12:29:40.946184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10681 12:29:40.946303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10682 12:29:40.946416 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10683 12:29:40.946530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10684 12:29:40.946643 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10685 12:29:40.948213 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10686 12:29:40.948327 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10687 12:29:40.948604 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10688 12:29:40.948699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10689 12:29:40.948971 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10690 12:29:40.949067 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10691 12:29:40.949161 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10692 12:29:40.949480 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10693 12:29:40.949701 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10694 12:29:40.949897 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10695 12:29:40.950070 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10696 12:29:40.950234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10697 12:29:40.950421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10698 12:29:40.950589 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10699 12:29:40.950754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10700 12:29:40.950952 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10701 12:29:40.951104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10702 12:29:40.951262 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10703 12:29:40.951444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10704 12:29:40.951591 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10705 12:29:40.951764 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10706 12:29:40.951924 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10707 12:29:40.952054 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10708 12:29:40.952193 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10709 12:29:40.956690 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10710 12:29:40.957009 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10711 12:29:40.957182 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10712 12:29:40.957350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10713 12:29:40.957749 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10714 12:29:40.957939 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10715 12:29:40.958081 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10716 12:29:40.958243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10717 12:29:40.958393 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10718 12:29:40.958514 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10719 12:29:40.958700 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10720 12:29:40.958883 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10721 12:29:40.959088 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10722 12:29:40.959257 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10723 12:29:40.959422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10724 12:29:40.959582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10725 12:29:40.959743 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10726 12:29:40.959908 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10727 12:29:40.960077 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10728 12:29:40.960245 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10729 12:29:40.960410 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10730 12:29:40.960576 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10731 12:29:40.960792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10732 12:29:40.960958 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10733 12:29:40.961113 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10734 12:29:40.961273 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10735 12:29:40.961420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10736 12:29:40.964146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10737 12:29:40.964604 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10738 12:29:40.964753 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10739 12:29:40.964876 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10740 12:29:40.965015 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10741 12:29:40.965135 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10742 12:29:40.965254 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10743 12:29:40.965391 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10744 12:29:40.965531 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10745 12:29:40.965693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10746 12:29:40.965816 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10747 12:29:40.965953 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10748 12:29:40.966073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10749 12:29:40.966211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10750 12:29:40.966329 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10751 12:29:40.966466 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10752 12:29:40.966605 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10753 12:29:40.966744 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10754 12:29:40.966883 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10755 12:29:40.967038 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10756 12:29:40.967179 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10757 12:29:40.967317 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10758 12:29:40.967454 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10759 12:29:40.967613 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10760 12:29:40.967771 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10761 12:29:40.968169 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10762 12:29:40.972146 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10763 12:29:40.972607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10764 12:29:40.972735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10765 12:29:40.972852 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10766 12:29:40.972989 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10767 12:29:40.982565 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10768 12:29:40.983080 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10769 12:29:40.983276 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10770 12:29:40.983412 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10771 12:29:40.983530 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10772 12:29:40.983673 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10773 12:29:40.983817 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10774 12:29:40.983961 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10775 12:29:40.984080 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10776 12:29:40.984225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10777 12:29:40.984347 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10778 12:29:40.984464 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10779 12:29:40.984606 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10780 12:29:40.984726 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10781 12:29:40.984864 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10782 12:29:40.984983 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10783 12:29:40.985119 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10784 12:29:40.985262 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10785 12:29:40.985383 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10786 12:29:40.985518 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10787 12:29:40.985675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10788 12:29:40.985818 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10789 12:29:40.986171 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10790 12:29:40.986302 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10791 12:29:40.986440 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10792 12:29:40.986580 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10793 12:29:40.986699 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10794 12:29:40.986834 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10795 12:29:40.987023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10796 12:29:40.987209 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10797 12:29:40.987357 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10798 12:29:40.987476 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10799 12:29:40.987612 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10800 12:29:40.987751 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10801 12:29:40.988141 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10802 12:29:40.988287 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10803 12:29:40.992381 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10804 12:29:40.992656 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10805 12:29:40.992782 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10806 12:29:40.992919 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10807 12:29:40.993040 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10808 12:29:40.993177 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10809 12:29:40.993521 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10810 12:29:40.993668 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10811 12:29:40.993811 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10812 12:29:40.993953 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10813 12:29:40.994106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10814 12:29:40.994246 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10815 12:29:40.994386 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10816 12:29:40.994525 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10817 12:29:40.994881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10818 12:29:40.995026 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10819 12:29:40.995167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10820 12:29:40.995287 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10821 12:29:40.995424 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10822 12:29:40.995545 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10823 12:29:40.995683 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10824 12:29:40.995824 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10825 12:29:40.995964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10826 12:29:41.000170 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10827 12:29:41.000686 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10828 12:29:41.000842 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10829 12:29:41.000965 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10830 12:29:41.001106 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10831 12:29:41.001227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10832 12:29:41.001346 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10833 12:29:41.001484 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10834 12:29:41.001606 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10835 12:29:41.001742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10836 12:29:41.001882 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10837 12:29:41.002003 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10838 12:29:41.002141 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10839 12:29:41.002261 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10840 12:29:41.002399 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10841 12:29:41.002520 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10842 12:29:41.002658 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10843 12:29:41.002798 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10844 12:29:41.002955 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10845 12:29:41.003100 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10846 12:29:41.003221 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10847 12:29:41.003375 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10848 12:29:41.003520 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10849 12:29:41.003661 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10850 12:29:41.004018 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10851 12:29:41.004148 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10852 12:29:41.008123 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10853 12:29:41.008587 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10854 12:29:41.008715 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10855 12:29:41.008857 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10856 12:29:41.008978 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10857 12:29:41.009095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10858 12:29:41.009234 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10859 12:29:41.009354 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10860 12:29:41.009492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10861 12:29:41.009612 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10862 12:29:41.009769 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10863 12:29:41.009888 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10864 12:29:41.010027 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10865 12:29:41.010187 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10866 12:29:41.010338 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10867 12:29:41.010458 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10868 12:29:41.010597 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10869 12:29:41.010715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10870 12:29:41.010831 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10871 12:29:41.011023 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10872 12:29:41.011155 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10873 12:29:41.011272 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10874 12:29:41.011411 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10875 12:29:41.011531 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10876 12:29:41.011677 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10877 12:29:41.011803 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10878 12:29:41.011940 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10879 12:29:41.012059 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10880 12:29:41.016159 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10881 12:29:41.016973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10882 12:29:41.017205 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10883 12:29:41.017427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10884 12:29:41.017612 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10885 12:29:41.017815 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10886 12:29:41.017990 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10887 12:29:41.018195 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10888 12:29:41.018364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10889 12:29:41.018557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10890 12:29:41.018761 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10891 12:29:41.018922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10892 12:29:41.019073 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10893 12:29:41.019222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10894 12:29:41.019382 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10895 12:29:41.019545 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10896 12:29:41.019749 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10897 12:29:41.019914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10898 12:29:41.020048 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10899 12:29:41.020171 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10900 12:29:41.020287 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10901 12:29:41.020402 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10902 12:29:41.020516 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10903 12:29:41.020630 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10904 12:29:41.020745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10905 12:29:41.020858 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10906 12:29:41.020973 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10907 12:29:41.021116 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10908 12:29:41.021237 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10909 12:29:41.024211 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10910 12:29:41.024491 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10911 12:29:41.024891 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10912 12:29:41.025087 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10913 12:29:41.025243 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10914 12:29:41.025405 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10915 12:29:41.025550 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10916 12:29:41.026234 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10917 12:29:41.026397 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10918 12:29:41.026519 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10919 12:29:41.026701 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10920 12:29:41.026833 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10921 12:29:41.026950 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10922 12:29:41.027065 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10923 12:29:41.027179 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10924 12:29:41.027294 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10925 12:29:41.027414 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10926 12:29:41.027558 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10927 12:29:41.037408 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10928 12:29:41.038046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10929 12:29:41.038245 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10930 12:29:41.038417 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10931 12:29:41.038587 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10932 12:29:41.038759 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10933 12:29:41.038964 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10934 12:29:41.039136 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10935 12:29:41.039297 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10936 12:29:41.039437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10937 12:29:41.039594 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10938 12:29:41.039764 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10939 12:29:41.039932 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10940 12:29:41.040074 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10941 12:29:41.040294 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10942 12:29:41.040474 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10943 12:29:41.040684 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10944 12:29:41.040895 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10945 12:29:41.041082 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10946 12:29:41.041255 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10947 12:29:41.041432 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10948 12:29:41.041839 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10949 12:29:41.041964 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10950 12:29:41.042066 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10951 12:29:41.042162 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10952 12:29:41.042258 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10953 12:29:41.042355 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10954 12:29:41.042454 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10955 12:29:41.042549 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10956 12:29:41.042645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10957 12:29:41.042740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10958 12:29:41.042836 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10959 12:29:41.042987 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10960 12:29:41.043112 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10961 12:29:41.043210 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10962 12:29:41.043306 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10963 12:29:41.043402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10964 12:29:41.043496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10965 12:29:41.043632 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10966 12:29:41.043737 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10967 12:29:41.043858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10968 12:29:41.043957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10969 12:29:41.044053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10970 12:29:41.044147 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10971 12:29:41.044242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10972 12:29:41.044337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10973 12:29:41.044434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10974 12:29:41.044528 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10975 12:29:41.044641 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10976 12:29:41.044737 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10977 12:29:41.048391 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10978 12:29:41.050779 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10979 12:29:41.051002 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10980 12:29:41.051111 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10981 12:29:41.051208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10982 12:29:41.051304 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10983 12:29:41.051407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10984 12:29:41.051503 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10985 12:29:41.051582 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10986 12:29:41.051659 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10987 12:29:41.051737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10988 12:29:41.051815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10989 12:29:41.051892 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10990 12:29:41.051970 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10991 12:29:41.052048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10992 12:29:41.052125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10993 12:29:41.052201 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10994 12:29:41.052278 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10995 12:29:41.052354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10996 12:29:41.052433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10997 12:29:41.052510 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10998 12:29:41.052658 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10999 12:29:41.052743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
11000 12:29:41.053044 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
11001 12:29:41.053130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
11002 12:29:41.053205 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
11003 12:29:41.053278 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
11004 12:29:41.053354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
11005 12:29:41.053435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
11006 12:29:41.053526 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
11007 12:29:41.053617 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
11008 12:29:41.053723 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
11009 12:29:41.053814 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
11010 12:29:41.056251 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
11011 12:29:41.056421 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
11012 12:29:41.056996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
11013 12:29:41.057099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
11014 12:29:41.057192 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
11015 12:29:41.057402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
11016 12:29:41.057560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
11017 12:29:41.057666 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
11018 12:29:41.057759 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
11019 12:29:41.057851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
11020 12:29:41.058332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
11021 12:29:41.058819 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
11022 12:29:41.059243 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
11023 12:29:41.059693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
11024 12:29:41.059902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
11025 12:29:41.059988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
11026 12:29:41.060110 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
11027 12:29:41.060198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
11028 12:29:41.060269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
11029 12:29:41.060330 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
11030 12:29:41.060420 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
11031 12:29:41.060489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
11032 12:29:41.060550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
11033 12:29:41.060611 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
11034 12:29:41.060671 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
11035 12:29:41.060731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
11036 12:29:41.060791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
11037 12:29:41.060850 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
11038 12:29:41.060910 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
11039 12:29:41.063178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
11040 12:29:41.068195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
11041 12:29:41.068686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
11042 12:29:41.068799 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
11043 12:29:41.068894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
11044 12:29:41.069001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
11045 12:29:41.069094 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
11046 12:29:41.069200 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
11047 12:29:41.069513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
11048 12:29:41.069692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
11049 12:29:41.069864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
11050 12:29:41.070008 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
11051 12:29:41.070169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
11052 12:29:41.070300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
11053 12:29:41.070405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
11054 12:29:41.070518 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
11055 12:29:41.070649 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
11056 12:29:41.070776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
11057 12:29:41.070880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
11058 12:29:41.071013 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
11059 12:29:41.071117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
11060 12:29:41.071248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
11061 12:29:41.071657 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
11062 12:29:41.071781 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
11063 12:29:41.071916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
11064 12:29:41.086826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
11065 12:29:41.087145 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
11066 12:29:41.087254 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
11067 12:29:41.087346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
11068 12:29:41.087452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
11069 12:29:41.087559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
11070 12:29:41.087849 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
11071 12:29:41.087959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
11072 12:29:41.088050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
11073 12:29:41.088150 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11074 12:29:41.088488 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11075 12:29:41.088594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11076 12:29:41.088675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11077 12:29:41.088772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11078 12:29:41.088858 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11079 12:29:41.088959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11080 12:29:41.089256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11081 12:29:41.089375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11082 12:29:41.089702 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11083 12:29:41.089851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11084 12:29:41.090119 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11085 12:29:41.090252 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11086 12:29:41.090446 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11087 12:29:41.090539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11088 12:29:41.090828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11089 12:29:41.090981 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11090 12:29:41.091228 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11091 12:29:41.091395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11092 12:29:41.091562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11093 12:29:41.091760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11094 12:29:41.091973 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11095 12:29:41.092072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11096 12:29:41.092159 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11097 12:29:41.092244 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11098 12:29:41.096589 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11099 12:29:41.096781 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11100 12:29:41.096986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11101 12:29:41.097321 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11102 12:29:41.097464 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11103 12:29:41.097584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11104 12:29:41.097749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11105 12:29:41.097942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11106 12:29:41.098040 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11107 12:29:41.098127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11108 12:29:41.098211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11109 12:29:41.098310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11110 12:29:41.098409 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11111 12:29:41.098829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11112 12:29:41.098971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11113 12:29:41.099157 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11114 12:29:41.099345 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11115 12:29:41.099594 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11116 12:29:41.099813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11117 12:29:41.099978 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11118 12:29:41.100081 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11119 12:29:41.100188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11120 12:29:41.104150 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11121 12:29:41.104557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11122 12:29:41.104679 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11123 12:29:41.104991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11124 12:29:41.105098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11125 12:29:41.105500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11126 12:29:41.105608 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11127 12:29:41.105783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11128 12:29:41.105977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11129 12:29:41.106067 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11130 12:29:41.106151 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11131 12:29:41.106249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11132 12:29:41.106729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11133 12:29:41.106925 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11134 12:29:41.107378 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11135 12:29:41.107560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11136 12:29:41.107758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11137 12:29:41.107966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11138 12:29:41.108129 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11139 12:29:41.108208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11140 12:29:41.108295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11141 12:29:41.108380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11142 12:29:41.112186 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11143 12:29:41.112641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11144 12:29:41.112737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11145 12:29:41.113105 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11146 12:29:41.113230 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11147 12:29:41.113322 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11148 12:29:41.113407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11149 12:29:41.113780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11150 12:29:41.113961 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11151 12:29:41.114052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11152 12:29:41.114123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11153 12:29:41.114208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11154 12:29:41.114281 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11155 12:29:41.114363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11156 12:29:41.114462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11157 12:29:41.114771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11158 12:29:41.114881 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11159 12:29:41.115222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11160 12:29:41.115332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11161 12:29:41.115435 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11162 12:29:41.115510 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11163 12:29:41.115596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11164 12:29:41.115679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11165 12:29:41.115999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11166 12:29:41.120172 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11167 12:29:41.120721 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11168 12:29:41.121107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11169 12:29:41.121312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11170 12:29:41.121516 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11171 12:29:41.121609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11172 12:29:41.121839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11173 12:29:41.122042 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11174 12:29:41.122559 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11175 12:29:41.122661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11176 12:29:41.122904 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11177 12:29:41.123054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11178 12:29:41.123141 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11179 12:29:41.123226 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11180 12:29:41.123309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11181 12:29:41.123553 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11182 12:29:41.123769 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11183 12:29:41.123863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11184 12:29:41.123948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11185 12:29:41.124033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11186 12:29:41.124116 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11187 12:29:41.124196 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11188 12:29:41.124280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11189 12:29:41.124363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11190 12:29:41.124447 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11191 12:29:41.124519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11192 12:29:41.128422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11193 12:29:41.128629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11194 12:29:41.128834 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11195 12:29:41.129008 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11196 12:29:41.129169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11197 12:29:41.129321 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11198 12:29:41.129444 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11199 12:29:41.129580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11200 12:29:41.140455 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11201 12:29:41.140671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11202 12:29:41.141065 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11203 12:29:41.141220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11204 12:29:41.141318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11205 12:29:41.141487 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11206 12:29:41.141698 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11207 12:29:41.141996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11208 12:29:41.142127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11209 12:29:41.142325 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11210 12:29:41.142518 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11211 12:29:41.142704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11212 12:29:41.142915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11213 12:29:41.143081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11214 12:29:41.143273 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11215 12:29:41.143506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11216 12:29:41.143666 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11217 12:29:41.143946 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11218 12:29:41.144078 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11219 12:29:41.144172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11220 12:29:41.144256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11221 12:29:41.144335 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11222 12:29:41.144408 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11223 12:29:41.144494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11224 12:29:41.144566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11225 12:29:41.148663 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11226 12:29:41.149049 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11227 12:29:41.149153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11228 12:29:41.149429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11229 12:29:41.149964 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11230 12:29:41.150298 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11231 12:29:41.150614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11232 12:29:41.150936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11233 12:29:41.151399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11234 12:29:41.151515 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11235 12:29:41.151821 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11236 12:29:41.151963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11237 12:29:41.158027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11238 12:29:41.158350 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11239 12:29:41.158465 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11240 12:29:41.158784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11241 12:29:41.158900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11242 12:29:41.159000 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11243 12:29:41.159315 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11244 12:29:41.159475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11245 12:29:41.159728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11246 12:29:41.159923 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11247 12:29:41.160022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11248 12:29:41.160124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11249 12:29:41.160218 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11250 12:29:41.160318 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11251 12:29:41.160439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11252 12:29:41.160546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11253 12:29:41.160645 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11254 12:29:41.160743 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11255 12:29:41.161042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11256 12:29:41.161370 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11257 12:29:41.161532 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11258 12:29:41.161656 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11259 12:29:41.161810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11260 12:29:41.163151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11261 12:29:41.163550 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11262 12:29:41.163646 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11263 12:29:41.163717 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11264 12:29:41.163789 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11265 12:29:41.163870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11266 12:29:41.163953 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11267 12:29:41.164234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11268 12:29:41.164338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11269 12:29:41.164424 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11270 12:29:41.164511 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11271 12:29:41.164597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11272 12:29:41.164686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11273 12:29:41.164776 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11274 12:29:41.164876 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11275 12:29:41.164964 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11276 12:29:41.165050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11277 12:29:41.168290 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11278 12:29:41.168446 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11279 12:29:41.168801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11280 12:29:41.168897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11281 12:29:41.168994 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11282 12:29:41.169357 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11283 12:29:41.169490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11284 12:29:41.170020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11285 12:29:41.170204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11286 12:29:41.170327 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11287 12:29:41.170451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11288 12:29:41.170563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11289 12:29:41.171350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11290 12:29:41.171649 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11291 12:29:41.171751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11292 12:29:41.171837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11293 12:29:41.171920 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11294 12:29:41.172367 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11295 12:29:41.172563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11296 12:29:41.172874 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11297 12:29:41.172979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11298 12:29:41.173064 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11299 12:29:41.173147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11300 12:29:41.173237 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11301 12:29:41.173328 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11302 12:29:41.176264 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11303 12:29:41.176803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11304 12:29:41.177034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11305 12:29:41.177253 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11306 12:29:41.177478 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11307 12:29:41.177706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11308 12:29:41.177831 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11309 12:29:41.177950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11310 12:29:41.179033 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11311 12:29:41.179135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11312 12:29:41.179243 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11313 12:29:41.179330 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11314 12:29:41.179427 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11315 12:29:41.179513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11316 12:29:41.179608 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11317 12:29:41.179694 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11318 12:29:41.179772 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11319 12:29:41.180039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11320 12:29:41.180172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11321 12:29:41.180278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11322 12:29:41.180360 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11323 12:29:41.180440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11324 12:29:41.180519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11325 12:29:41.180598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11326 12:29:41.180676 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11327 12:29:41.184187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11328 12:29:41.184474 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11329 12:29:41.184593 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11330 12:29:41.184694 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11331 12:29:41.184811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11332 12:29:41.185360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11333 12:29:41.185445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11334 12:29:41.205427 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11335 12:29:41.205784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11336 12:29:41.205917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11337 12:29:41.206018 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11338 12:29:41.206107 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11339 12:29:41.206211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11340 12:29:41.206314 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11341 12:29:41.206622 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11342 12:29:41.206733 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11343 12:29:41.206837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11344 12:29:41.207206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11345 12:29:41.207923 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11346 12:29:41.208122 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11347 12:29:41.208215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11348 12:29:41.208301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11349 12:29:41.208386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11350 12:29:41.208470 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11351 12:29:41.212304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11352 12:29:41.213393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11353 12:29:41.213770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11354 12:29:41.213959 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11355 12:29:41.214062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11356 12:29:41.214153 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11357 12:29:41.214242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11358 12:29:41.214329 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11359 12:29:41.214413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11360 12:29:41.214703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11361 12:29:41.214812 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11362 12:29:41.214905 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11363 12:29:41.214995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11364 12:29:41.215084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11365 12:29:41.215173 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11366 12:29:41.215261 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11367 12:29:41.215350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11368 12:29:41.215458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11369 12:29:41.215550 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11370 12:29:41.215639 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11371 12:29:41.215723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11372 12:29:41.215810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11373 12:29:41.215917 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11374 12:29:41.216009 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11375 12:29:41.216114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11376 12:29:41.220340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11377 12:29:41.220497 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11378 12:29:41.220913 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11379 12:29:41.221003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11380 12:29:41.221125 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11381 12:29:41.221261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11382 12:29:41.221344 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11383 12:29:41.221429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11384 12:29:41.221529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11385 12:29:41.221626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11386 12:29:41.221969 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11387 12:29:41.222071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11388 12:29:41.222412 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11389 12:29:41.222718 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11390 12:29:41.222954 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11391 12:29:41.223106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11392 12:29:41.223321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11393 12:29:41.223463 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11394 12:29:41.223645 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11395 12:29:41.223957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11396 12:29:41.224121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11397 12:29:41.224291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11398 12:29:41.224459 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11399 12:29:41.224650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11400 12:29:41.228222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11401 12:29:41.228577 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11402 12:29:41.228716 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11403 12:29:41.228834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11404 12:29:41.229124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11405 12:29:41.229681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11406 12:29:41.230072 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11407 12:29:41.230286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11408 12:29:41.230779 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11409 12:29:41.230898 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11410 12:29:41.231012 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11411 12:29:41.231127 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11412 12:29:41.234861 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11413 12:29:41.234979 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11414 12:29:41.235072 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11415 12:29:41.235165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11416 12:29:41.235258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11417 12:29:41.235350 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11418 12:29:41.235444 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11419 12:29:41.235535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11420 12:29:41.235627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11421 12:29:41.235720 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11422 12:29:41.235816 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11423 12:29:41.235903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11424 12:29:41.235986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11425 12:29:41.236463 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11426 12:29:41.236584 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11427 12:29:41.236700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11428 12:29:41.237005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11429 12:29:41.237111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11430 12:29:41.237223 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11431 12:29:41.237333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11432 12:29:41.237611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11433 12:29:41.237717 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11434 12:29:41.238470 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11435 12:29:41.238588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11436 12:29:41.238698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11437 12:29:41.238803 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11438 12:29:41.238910 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11439 12:29:41.239195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11440 12:29:41.239305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11441 12:29:41.239420 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11442 12:29:41.239533 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11443 12:29:41.239651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11444 12:29:41.239788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11445 12:29:41.240110 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11446 12:29:41.240223 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11447 12:29:41.240320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11448 12:29:41.240444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11449 12:29:41.244235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11450 12:29:41.244612 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11451 12:29:41.244756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11452 12:29:41.245144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11453 12:29:41.245291 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11454 12:29:41.245531 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11455 12:29:41.245692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11456 12:29:41.245953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11457 12:29:41.246057 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11458 12:29:41.246524 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11459 12:29:41.246736 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11460 12:29:41.246879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11461 12:29:41.246988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11462 12:29:41.247090 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11463 12:29:41.247193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11464 12:29:41.247308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11465 12:29:41.247413 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11466 12:29:41.247522 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11467 12:29:41.247606 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11468 12:29:41.270266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11469 12:29:41.270916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11470 12:29:41.271015 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11471 12:29:41.271105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11472 12:29:41.271194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11473 12:29:41.271294 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11474 12:29:41.271381 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11475 12:29:41.271466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11476 12:29:41.271564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11477 12:29:41.271651 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11478 12:29:41.271928 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11479 12:29:41.272022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11480 12:29:41.272360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11481 12:29:41.272687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11482 12:29:41.272803 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11483 12:29:41.272908 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11484 12:29:41.273000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11485 12:29:41.273107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11486 12:29:41.273207 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11487 12:29:41.273509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11488 12:29:41.273813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11489 12:29:41.273952 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11490 12:29:41.274063 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11491 12:29:41.274399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11492 12:29:41.274520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11493 12:29:41.274610 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11494 12:29:41.274693 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11495 12:29:41.274777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11496 12:29:41.274875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11497 12:29:41.274966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11498 12:29:41.275071 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11499 12:29:41.275178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11500 12:29:41.275281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11501 12:29:41.275381 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11502 12:29:41.275673 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11503 12:29:41.275776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11504 12:29:41.275983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11505 12:29:41.276077 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11506 12:29:41.280560 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11507 12:29:41.282560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11508 12:29:41.282653 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11509 12:29:41.282744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11510 12:29:41.282823 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11511 12:29:41.282902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11512 12:29:41.282977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11513 12:29:41.283051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11514 12:29:41.283125 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11515 12:29:41.283199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11516 12:29:41.283273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11517 12:29:41.283347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11518 12:29:41.283452 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11519 12:29:41.283545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11520 12:29:41.283627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11521 12:29:41.283704 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11522 12:29:41.283983 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11523 12:29:41.284096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11524 12:29:41.284186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11525 12:29:41.284261 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11526 12:29:41.284335 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11527 12:29:41.284409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11528 12:29:41.284483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11529 12:29:41.284557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11530 12:29:41.284630 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11531 12:29:41.284704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11532 12:29:41.288328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11533 12:29:41.288681 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11534 12:29:41.288801 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11535 12:29:41.288991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11536 12:29:41.290023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11537 12:29:41.290156 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11538 12:29:41.290248 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11539 12:29:41.290323 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11540 12:29:41.290400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11541 12:29:41.290473 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11542 12:29:41.290550 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11543 12:29:41.290627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11544 12:29:41.290871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11545 12:29:41.291187 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11546 12:29:41.291336 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11547 12:29:41.291408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11548 12:29:41.291475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11549 12:29:41.291538 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11550 12:29:41.291772 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11551 12:29:41.291871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11552 12:29:41.291977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11553 12:29:41.292063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11554 12:29:41.292132 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11555 12:29:41.292192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11556 12:29:41.292251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11557 12:29:41.292310 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11558 12:29:41.296545 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11559 12:29:41.296669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11560 12:29:41.296755 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11561 12:29:41.297188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11562 12:29:41.297309 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11563 12:29:41.297438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11564 12:29:41.297887 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11565 12:29:41.297980 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11566 12:29:41.298091 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11567 12:29:41.298216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11568 12:29:41.298319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11569 12:29:41.298595 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11570 12:29:41.298702 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11571 12:29:41.298812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11572 12:29:41.298942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11573 12:29:41.299053 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11574 12:29:41.299137 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11575 12:29:41.299221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11576 12:29:41.299309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11577 12:29:41.299382 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11578 12:29:41.299467 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11579 12:29:41.299567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11580 12:29:41.299654 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11581 12:29:41.299754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11582 12:29:41.300051 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11583 12:29:41.304276 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11584 12:29:41.304933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11585 12:29:41.305032 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11586 12:29:41.305120 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11587 12:29:41.305207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11588 12:29:41.305311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11589 12:29:41.305403 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11590 12:29:41.305508 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11591 12:29:41.305597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11592 12:29:41.306083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11593 12:29:41.306405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11594 12:29:41.306584 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11595 12:29:41.306679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11596 12:29:41.306848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11597 12:29:41.306966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11598 12:29:41.307096 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11599 12:29:41.307190 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11600 12:29:41.307273 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11601 12:29:41.307337 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11602 12:29:41.327604 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11603 12:29:41.327838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11604 12:29:41.327926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11605 12:29:41.328219 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11606 12:29:41.328428 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11607 12:29:41.328926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11608 12:29:41.329034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11609 12:29:41.329125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11610 12:29:41.329211 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11611 12:29:41.329298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11612 12:29:41.329499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11613 12:29:41.329611 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11614 12:29:41.329712 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11615 12:29:41.329800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11616 12:29:41.330126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11617 12:29:41.330279 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11618 12:29:41.330658 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11619 12:29:41.330758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11620 12:29:41.331045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11621 12:29:41.331152 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11622 12:29:41.331241 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11623 12:29:41.331330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11624 12:29:41.331416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11625 12:29:41.331707 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11626 12:29:41.331813 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11627 12:29:41.331902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11628 12:29:41.332012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11629 12:29:41.332102 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11630 12:29:41.336463 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11631 12:29:41.336581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11632 12:29:41.336670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11633 12:29:41.337834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11634 12:29:41.337945 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11635 12:29:41.338035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11636 12:29:41.338123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11637 12:29:41.338208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11638 12:29:41.338294 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11639 12:29:41.338378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11640 12:29:41.338463 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11641 12:29:41.338542 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11642 12:29:41.338627 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11643 12:29:41.338714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11644 12:29:41.338799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11645 12:29:41.338883 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11646 12:29:41.339728 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11647 12:29:41.339846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11648 12:29:41.339930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11649 12:29:41.340017 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11650 12:29:41.340104 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11651 12:29:41.340187 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11652 12:29:41.340269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11653 12:29:41.340351 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11654 12:29:41.340426 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11655 12:29:41.340494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11656 12:29:41.340561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11657 12:29:41.340631 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11658 12:29:41.340711 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11659 12:29:41.340793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11660 12:29:41.340896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11661 12:29:41.340984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11662 12:29:41.345803 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11663 12:29:41.346184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11664 12:29:41.346301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11665 12:29:41.346399 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11666 12:29:41.346494 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11667 12:29:41.346588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11668 12:29:41.346683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11669 12:29:41.346775 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11670 12:29:41.346871 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11671 12:29:41.346968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11672 12:29:41.347353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11673 12:29:41.348009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11674 12:29:41.348120 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11675 12:29:41.348216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11676 12:29:41.348312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11677 12:29:41.348402 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11678 12:29:41.348493 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11679 12:29:41.348588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11680 12:29:41.348680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11681 12:29:41.348773 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11682 12:29:41.348864 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11683 12:29:41.348959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11684 12:29:41.349052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11685 12:29:41.349143 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11686 12:29:41.349256 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11687 12:29:41.349351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11688 12:29:41.349445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11689 12:29:41.352381 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11690 12:29:41.352729 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11691 12:29:41.352843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11692 12:29:41.352940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11693 12:29:41.353051 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11694 12:29:41.353145 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11695 12:29:41.353255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11696 12:29:41.353366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11697 12:29:41.353478 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11698 12:29:41.353572 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11699 12:29:41.353697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11700 12:29:41.353792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11701 12:29:41.353900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11702 12:29:41.354010 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11703 12:29:41.354318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11704 12:29:41.354419 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11705 12:29:41.354529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11706 12:29:41.354623 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11707 12:29:41.354716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11708 12:29:41.354826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11709 12:29:41.354943 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11710 12:29:41.355057 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11711 12:29:41.355149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11712 12:29:41.355256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11713 12:29:41.355347 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11714 12:29:41.355457 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11715 12:29:41.355751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11716 12:29:41.355858 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11717 12:29:41.355953 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11718 12:29:41.356063 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11719 12:29:41.356158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11720 12:29:41.360242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11721 12:29:41.361987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11722 12:29:41.362148 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11723 12:29:41.362247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11724 12:29:41.362340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11725 12:29:41.362434 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11726 12:29:41.362530 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11727 12:29:41.362622 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11728 12:29:41.362713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11729 12:29:41.362804 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11730 12:29:41.362897 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11731 12:29:41.362992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11732 12:29:41.363084 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11733 12:29:41.363379 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11734 12:29:41.363482 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11735 12:29:41.363578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11736 12:29:41.379532 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11737 12:29:41.379924 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11738 12:29:41.380033 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11739 12:29:41.380130 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11740 12:29:41.380482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11741 12:29:41.380763 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11742 12:29:41.381089 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11743 12:29:41.381195 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11744 12:29:41.381283 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11745 12:29:41.381381 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11746 12:29:41.381728 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11747 12:29:41.381825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11748 12:29:41.382112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11749 12:29:41.382211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11750 12:29:41.382295 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11751 12:29:41.382378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11752 12:29:41.382475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11753 12:29:41.382561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11754 12:29:41.382657 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11755 12:29:41.382941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11756 12:29:41.383034 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11757 12:29:41.383131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11758 12:29:41.383226 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11759 12:29:41.383530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11760 12:29:41.383629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11761 12:29:41.383728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11762 12:29:41.383935 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11763 12:29:41.384053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11764 12:29:41.388207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11765 12:29:41.388513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11766 12:29:41.388622 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11767 12:29:41.388953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11768 12:29:41.389055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11769 12:29:41.389142 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11770 12:29:41.389240 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11771 12:29:41.389328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11772 12:29:41.389425 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11773 12:29:41.389523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11774 12:29:41.389828 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11775 12:29:41.389943 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11776 12:29:41.390050 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11777 12:29:41.390148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11778 12:29:41.390247 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11779 12:29:41.390545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11780 12:29:41.390660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11781 12:29:41.390760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11782 12:29:41.391250 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11783 12:29:41.391354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11784 12:29:41.391456 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11785 12:29:41.391555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11786 12:29:41.391655 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11787 12:29:41.391739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11788 12:29:41.392032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11789 12:29:41.396158 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11790 12:29:41.396625 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11791 12:29:41.396724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11792 12:29:41.396822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11793 12:29:41.396905 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11794 12:29:41.397004 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11795 12:29:41.398019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11796 12:29:41.398121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11797 12:29:41.398203 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11798 12:29:41.398286 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11799 12:29:41.398524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11800 12:29:41.398618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11801 12:29:41.398699 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11802 12:29:41.399254 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11803 12:29:41.399977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11804 12:29:41.400080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11805 12:29:41.400343 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11806 12:29:41.400544 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11807 12:29:41.400833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11808 12:29:41.401194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11809 12:29:41.401281 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11810 12:29:41.401366 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11811 12:29:41.401471 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11812 12:29:41.401554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11813 12:29:41.401637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11814 12:29:41.401737 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11815 12:29:41.401817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11816 12:29:41.401902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11817 12:29:41.401986 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11818 12:29:41.402071 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11819 12:29:41.402152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11820 12:29:41.402231 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11821 12:29:41.402313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11822 12:29:41.402400 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11823 12:29:41.402484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11824 12:29:41.408238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11825 12:29:41.409203 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11826 12:29:41.409367 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11827 12:29:41.409517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11828 12:29:41.409823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11829 12:29:41.409915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11830 12:29:41.410000 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11831 12:29:41.410102 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11832 12:29:41.410188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11833 12:29:41.410273 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11834 12:29:41.410357 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11835 12:29:41.410440 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11836 12:29:41.410521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11837 12:29:41.410621 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11838 12:29:41.410707 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11839 12:29:41.410790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11840 12:29:41.410888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11841 12:29:41.410974 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11842 12:29:41.411264 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11843 12:29:41.411385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11844 12:29:41.411615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11845 12:29:41.411723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11846 12:29:41.411809 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11847 12:29:41.411907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11848 12:29:41.412005 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11849 12:29:41.416353 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11850 12:29:41.416448 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11851 12:29:41.416793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11852 12:29:41.416893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11853 12:29:41.417307 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11854 12:29:41.417392 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11855 12:29:41.417486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11856 12:29:41.417569 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11857 12:29:41.417882 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11858 12:29:41.418004 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11859 12:29:41.418118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11860 12:29:41.418317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11861 12:29:41.418408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11862 12:29:41.418479 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11863 12:29:41.418560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11864 12:29:41.418658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11865 12:29:41.418758 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11866 12:29:41.419036 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11867 12:29:41.419128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11868 12:29:41.419227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11869 12:29:41.419326 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11870 12:29:41.438960 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11871 12:29:41.439371 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11872 12:29:41.439484 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11873 12:29:41.439577 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11874 12:29:41.439879 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11875 12:29:41.439970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11876 12:29:41.440067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11877 12:29:41.440388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11878 12:29:41.440492 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11879 12:29:41.441051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11880 12:29:41.441892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11881 12:29:41.442537 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11882 12:29:41.442909 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11883 12:29:41.443017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11884 12:29:41.443091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11885 12:29:41.443155 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11886 12:29:41.443232 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11887 12:29:41.443298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11888 12:29:41.443378 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11889 12:29:41.443455 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11890 12:29:41.443534 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11891 12:29:41.443610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11892 12:29:41.443704 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11893 12:29:41.444125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11894 12:29:41.444238 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11895 12:29:41.444337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11896 12:29:41.444427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11897 12:29:41.444516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11898 12:29:41.444616 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11899 12:29:41.444724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11900 12:29:41.444838 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11901 12:29:41.444953 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11902 12:29:41.445058 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11903 12:29:41.445167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11904 12:29:41.445607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11905 12:29:41.445722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11906 12:29:41.445824 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11907 12:29:41.446086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11908 12:29:41.452286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11909 12:29:41.452742 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11910 12:29:41.452860 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11911 12:29:41.452959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11912 12:29:41.453053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11913 12:29:41.453170 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11914 12:29:41.453266 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11915 12:29:41.453360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11916 12:29:41.453470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11917 12:29:41.453567 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11918 12:29:41.453687 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11919 12:29:41.453980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11920 12:29:41.454092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11921 12:29:41.454190 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11922 12:29:41.454282 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11923 12:29:41.454393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11924 12:29:41.454488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11925 12:29:41.454600 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11926 12:29:41.454708 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11927 12:29:41.455017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11928 12:29:41.455134 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11929 12:29:41.455889 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11930 12:29:41.456004 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11931 12:29:41.456100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11932 12:29:41.456199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11933 12:29:41.456292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11934 12:29:41.456384 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11935 12:29:41.456476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11936 12:29:41.456567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11937 12:29:41.460099 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11938 12:29:41.460425 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11939 12:29:41.460519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11940 12:29:41.460629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11941 12:29:41.460739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11942 12:29:41.460853 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11943 12:29:41.461138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11944 12:29:41.461227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11945 12:29:41.461493 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11946 12:29:41.461578 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11947 12:29:41.461693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11948 12:29:41.461999 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11949 12:29:41.462288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11950 12:29:41.462370 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11951 12:29:41.462449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11952 12:29:41.462525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11953 12:29:41.462787 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11954 12:29:41.462875 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11955 12:29:41.462983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11956 12:29:41.463442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11957 12:29:41.463547 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11958 12:29:41.463664 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11959 12:29:41.463970 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11960 12:29:41.464082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11961 12:29:41.464200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11962 12:29:41.464297 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11963 12:29:41.468128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11964 12:29:41.468445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11965 12:29:41.468559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11966 12:29:41.468642 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11967 12:29:41.468733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11968 12:29:41.469020 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11969 12:29:41.469129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11970 12:29:41.469242 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11971 12:29:41.469542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11972 12:29:41.469853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11973 12:29:41.470216 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11974 12:29:41.470312 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11975 12:29:41.470761 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11976 12:29:41.470948 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11977 12:29:41.471137 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11978 12:29:41.471244 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11979 12:29:41.471524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11980 12:29:41.471616 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11981 12:29:41.471682 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11982 12:29:41.471747 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11983 12:29:41.471836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11984 12:29:41.471941 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11985 12:29:41.472687 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11986 12:29:41.472795 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11987 12:29:41.472907 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11988 12:29:41.476109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11989 12:29:41.476427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11990 12:29:41.476532 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11991 12:29:41.476812 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11992 12:29:41.476913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11993 12:29:41.477189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11994 12:29:41.477277 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11995 12:29:41.477374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11996 12:29:41.477458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11997 12:29:41.477554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11998 12:29:41.477642 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11999 12:29:41.477756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
12000 12:29:41.477853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
12001 12:29:41.478127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
12002 12:29:41.478227 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
12003 12:29:41.478311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
12004 12:29:41.497986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
12005 12:29:41.498212 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
12006 12:29:41.498306 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
12007 12:29:41.498395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
12008 12:29:41.498518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
12009 12:29:41.498615 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
12010 12:29:41.498704 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
12011 12:29:41.498792 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
12012 12:29:41.498879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
12013 12:29:41.498957 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
12014 12:29:41.499030 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
12015 12:29:41.499104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
12016 12:29:41.499175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
12017 12:29:41.499251 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
12018 12:29:41.499321 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
12019 12:29:41.499390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
12020 12:29:41.499460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
12021 12:29:41.499529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
12022 12:29:41.499598 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
12023 12:29:41.499668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
12024 12:29:41.499738 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
12025 12:29:41.499807 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
12026 12:29:41.499877 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
12027 12:29:41.499947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
12028 12:29:41.500233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
12029 12:29:41.500319 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
12030 12:29:41.500384 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
12031 12:29:41.500445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
12032 12:29:41.500506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
12033 12:29:41.500567 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
12034 12:29:41.500627 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
12035 12:29:41.500687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
12036 12:29:41.500748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
12037 12:29:41.500809 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
12038 12:29:41.500870 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
12039 12:29:41.500929 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
12040 12:29:41.500990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
12041 12:29:41.501050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
12042 12:29:41.501109 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
12043 12:29:41.501170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
12044 12:29:41.504400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
12045 12:29:41.504551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
12046 12:29:41.504817 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
12047 12:29:41.504911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
12048 12:29:41.505023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
12049 12:29:41.505123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
12050 12:29:41.505432 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
12051 12:29:41.505528 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
12052 12:29:41.505627 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
12053 12:29:41.505771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
12054 12:29:41.505898 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
12055 12:29:41.506011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
12056 12:29:41.506100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
12057 12:29:41.506188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
12058 12:29:41.506300 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
12059 12:29:41.506394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
12060 12:29:41.506501 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
12061 12:29:41.506591 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
12062 12:29:41.506670 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
12063 12:29:41.506758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
12064 12:29:41.506846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
12065 12:29:41.507128 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
12066 12:29:41.507215 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
12067 12:29:41.507312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
12068 12:29:41.507409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
12069 12:29:41.507526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
12070 12:29:41.507620 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
12071 12:29:41.507718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
12072 12:29:41.507836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
12073 12:29:41.507929 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12074 12:29:41.508025 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12075 12:29:41.508121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12076 12:29:41.508241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12077 12:29:41.512231 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12078 12:29:41.512634 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12079 12:29:41.512723 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12080 12:29:41.512809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12081 12:29:41.512914 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12082 12:29:41.513023 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12083 12:29:41.513144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12084 12:29:41.513436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12085 12:29:41.513561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12086 12:29:41.513681 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12087 12:29:41.513982 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12088 12:29:41.514104 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12089 12:29:41.514195 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12090 12:29:41.514303 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12091 12:29:41.514406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12092 12:29:41.514694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12093 12:29:41.515255 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12094 12:29:41.515341 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12095 12:29:41.515416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12096 12:29:41.515491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12097 12:29:41.515750 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12098 12:29:41.515835 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12099 12:29:41.515916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12100 12:29:41.516007 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12101 12:29:41.516087 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12102 12:29:41.520445 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12103 12:29:41.520815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12104 12:29:41.520905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12105 12:29:41.521026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12106 12:29:41.521128 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12107 12:29:41.521202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12108 12:29:41.521321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12109 12:29:41.521420 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12110 12:29:41.521696 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12111 12:29:41.521810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12112 12:29:41.521916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12113 12:29:41.522186 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12114 12:29:41.522276 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12115 12:29:41.522388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12116 12:29:41.522668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12117 12:29:41.522772 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12118 12:29:41.522885 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12119 12:29:41.523177 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12120 12:29:41.523277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12121 12:29:41.523394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12122 12:29:41.523499 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12123 12:29:41.523773 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12124 12:29:41.523881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12125 12:29:41.523972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12126 12:29:41.528358 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12127 12:29:41.528539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12128 12:29:41.528811 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12129 12:29:41.528900 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12130 12:29:41.529003 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12131 12:29:41.529109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12132 12:29:41.529396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12133 12:29:41.529699 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12134 12:29:41.529805 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12135 12:29:41.529911 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12136 12:29:41.530001 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12137 12:29:41.530104 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12138 12:29:41.555009 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12139 12:29:41.555293 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12140 12:29:41.555534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12141 12:29:41.556162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12142 12:29:41.556268 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12143 12:29:41.556346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12144 12:29:41.556422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12145 12:29:41.556496 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12146 12:29:41.556569 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12147 12:29:41.556642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12148 12:29:41.556730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12149 12:29:41.556805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12150 12:29:41.556877 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12151 12:29:41.556962 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12152 12:29:41.557047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12153 12:29:41.557866 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12154 12:29:41.557983 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12155 12:29:41.558074 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12156 12:29:41.558161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12157 12:29:41.558260 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12158 12:29:41.558346 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12159 12:29:41.558431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12160 12:29:41.558533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12161 12:29:41.558626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12162 12:29:41.558729 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12163 12:29:41.558836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12164 12:29:41.558947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12165 12:29:41.559066 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12166 12:29:41.559178 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12167 12:29:41.559494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12168 12:29:41.559619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12169 12:29:41.559730 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12170 12:29:41.559841 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12171 12:29:41.559958 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12172 12:29:41.564460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12173 12:29:41.564660 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12174 12:29:41.564952 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12175 12:29:41.565060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12176 12:29:41.565147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12177 12:29:41.565245 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12178 12:29:41.565333 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12179 12:29:41.565625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12180 12:29:41.565756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12181 12:29:41.565873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12182 12:29:41.566163 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12183 12:29:41.566248 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12184 12:29:41.566343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12185 12:29:41.566621 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12186 12:29:41.566719 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12187 12:29:41.566810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12188 12:29:41.567100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12189 12:29:41.567208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12190 12:29:41.567307 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12191 12:29:41.567586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12192 12:29:41.567683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12193 12:29:41.567962 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12194 12:29:41.568045 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12195 12:29:41.572680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12196 12:29:41.572871 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12197 12:29:41.573170 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12198 12:29:41.573306 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12199 12:29:41.573436 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12200 12:29:41.573521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12201 12:29:41.573615 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12202 12:29:41.573724 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12203 12:29:41.573803 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12204 12:29:41.573901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12205 12:29:41.573984 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12206 12:29:41.574082 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12207 12:29:41.574379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12208 12:29:41.574481 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12209 12:29:41.574583 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12210 12:29:41.574671 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12211 12:29:41.574767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12212 12:29:41.575060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12213 12:29:41.575173 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12214 12:29:41.575601 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12215 12:29:41.575725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12216 12:29:41.575815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12217 12:29:41.575988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12218 12:29:41.576067 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12219 12:29:41.580184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12220 12:29:41.580615 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12221 12:29:41.580743 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12222 12:29:41.580880 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12223 12:29:41.580989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12224 12:29:41.581284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12225 12:29:41.581392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12226 12:29:41.581474 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12227 12:29:41.581560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12228 12:29:41.581640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12229 12:29:41.581849 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12230 12:29:41.581958 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12231 12:29:41.582247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12232 12:29:41.582352 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12233 12:29:41.582456 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12234 12:29:41.582558 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12235 12:29:41.582839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12236 12:29:41.582923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12237 12:29:41.583011 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12238 12:29:41.583270 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12239 12:29:41.583383 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12240 12:29:41.583673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12241 12:29:41.583757 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12242 12:29:41.583852 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12243 12:29:41.584142 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12244 12:29:41.588170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12245 12:29:41.588513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12246 12:29:41.588602 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12247 12:29:41.588722 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12248 12:29:41.589027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12249 12:29:41.589133 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12250 12:29:41.589250 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12251 12:29:41.589346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12252 12:29:41.589429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12253 12:29:41.589707 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12254 12:29:41.589847 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12255 12:29:41.589961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12256 12:29:41.590073 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12257 12:29:41.590380 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12258 12:29:41.590477 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12259 12:29:41.590586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12260 12:29:41.590674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12261 12:29:41.590972 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12262 12:29:41.591067 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12263 12:29:41.591494 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12264 12:29:41.591624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12265 12:29:41.591723 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12266 12:29:41.591807 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12267 12:29:41.591893 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12268 12:29:41.591985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12269 12:29:41.596241 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12270 12:29:41.596637 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12271 12:29:41.596724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12272 12:29:41.618877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12273 12:29:41.619425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12274 12:29:41.619641 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12275 12:29:41.619742 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12276 12:29:41.619824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12277 12:29:41.619916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12278 12:29:41.619996 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12279 12:29:41.620078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12280 12:29:41.620147 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12281 12:29:41.620449 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12282 12:29:41.620547 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12283 12:29:41.620635 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12284 12:29:41.621063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12285 12:29:41.621153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12286 12:29:41.621244 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12287 12:29:41.621332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12288 12:29:41.621434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12289 12:29:41.621733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12290 12:29:41.622181 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12291 12:29:41.622840 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12292 12:29:41.623036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12293 12:29:41.623118 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12294 12:29:41.623211 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12295 12:29:41.623286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12296 12:29:41.623359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12297 12:29:41.623431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12298 12:29:41.623503 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12299 12:29:41.623576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12300 12:29:41.623862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12301 12:29:41.623967 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12302 12:29:41.624074 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12303 12:29:41.624165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12304 12:29:41.624259 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12305 12:29:41.628409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12306 12:29:41.628968 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12307 12:29:41.629822 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12308 12:29:41.629919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12309 12:29:41.630022 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12310 12:29:41.630118 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12311 12:29:41.630217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12312 12:29:41.630317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12313 12:29:41.630418 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12314 12:29:41.630525 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12315 12:29:41.630626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12316 12:29:41.630997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12317 12:29:41.631116 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12318 12:29:41.631212 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12319 12:29:41.631405 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12320 12:29:41.631507 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12321 12:29:41.631599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12322 12:29:41.631895 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12323 12:29:41.632006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12324 12:29:41.632099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12325 12:29:41.632194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12326 12:29:41.632287 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12327 12:29:41.632380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12328 12:29:41.632476 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12329 12:29:41.632570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12330 12:29:41.637856 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12331 12:29:41.637976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12332 12:29:41.638085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12333 12:29:41.638183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12334 12:29:41.638277 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12335 12:29:41.638374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12336 12:29:41.638470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12337 12:29:41.638571 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12338 12:29:41.638671 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12339 12:29:41.638759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12340 12:29:41.638835 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12341 12:29:41.638934 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12342 12:29:41.639005 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12343 12:29:41.639069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12344 12:29:41.639131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12345 12:29:41.639192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12346 12:29:41.639485 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12347 12:29:41.639570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12348 12:29:41.639645 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12349 12:29:41.639733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12350 12:29:41.639802 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12351 12:29:41.639868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12352 12:29:41.639940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12353 12:29:41.640027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12354 12:29:41.640093 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12355 12:29:41.640154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12356 12:29:41.640214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12357 12:29:41.640275 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12358 12:29:41.640335 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12359 12:29:41.640397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12360 12:29:41.640458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12361 12:29:41.640533 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12362 12:29:41.640598 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12363 12:29:41.640659 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12364 12:29:41.640720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12365 12:29:41.640780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12366 12:29:41.640841 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12367 12:29:41.644229 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12368 12:29:41.644613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12369 12:29:41.644722 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12370 12:29:41.644811 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12371 12:29:41.644891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12372 12:29:41.644983 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12373 12:29:41.645061 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12374 12:29:41.645140 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12375 12:29:41.645238 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12376 12:29:41.645319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12377 12:29:41.645410 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12378 12:29:41.645504 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12379 12:29:41.645600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12380 12:29:41.645875 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12381 12:29:41.645985 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12382 12:29:41.646078 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12383 12:29:41.646167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12384 12:29:41.646453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12385 12:29:41.646570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12386 12:29:41.646670 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12387 12:29:41.646778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12388 12:29:41.647053 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12389 12:29:41.647162 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12390 12:29:41.647446 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12391 12:29:41.647545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12392 12:29:41.647639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12393 12:29:41.647729 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12394 12:29:41.648000 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12395 12:29:41.648095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12396 12:29:41.648193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12397 12:29:41.648494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12398 12:29:41.652121 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12399 12:29:41.652428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12400 12:29:41.652550 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12401 12:29:41.652654 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12402 12:29:41.652747 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12403 12:29:41.652851 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12404 12:29:41.652939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12405 12:29:41.653041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12406 12:29:41.670811 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12407 12:29:41.671222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12408 12:29:41.671317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12409 12:29:41.671393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12410 12:29:41.671468 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12411 12:29:41.671553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12412 12:29:41.671630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12413 12:29:41.671715 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12414 12:29:41.671789 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12415 12:29:41.672067 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12416 12:29:41.672173 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12417 12:29:41.672444 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12418 12:29:41.672538 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12419 12:29:41.672626 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12420 12:29:41.672713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12421 12:29:41.672785 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12422 12:29:41.673068 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12423 12:29:41.673161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12424 12:29:41.673246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12425 12:29:41.673330 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12426 12:29:41.673413 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12427 12:29:41.673701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12428 12:29:41.673819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12429 12:29:41.673913 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12430 12:29:41.674002 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12431 12:29:41.674292 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12432 12:29:41.674398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12433 12:29:41.674503 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12434 12:29:41.674589 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12435 12:29:41.674673 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12436 12:29:41.674772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12437 12:29:41.674858 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12438 12:29:41.674948 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12439 12:29:41.675049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12440 12:29:41.675135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12441 12:29:41.675235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12442 12:29:41.675836 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12443 12:29:41.675953 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12444 12:29:41.676041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12445 12:29:41.676122 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12446 12:29:41.676207 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12447 12:29:41.676288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12448 12:29:41.676582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12449 12:29:41.676667 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12450 12:29:41.676749 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12451 12:29:41.676836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12452 12:29:41.676927 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12453 12:29:41.680153 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12454 12:29:41.680484 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12455 12:29:41.680588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12456 12:29:41.680709 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12457 12:29:41.680800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12458 12:29:41.680887 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12459 12:29:41.681161 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12460 12:29:41.681281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12461 12:29:41.681415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12462 12:29:41.681543 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12463 12:29:41.681671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12464 12:29:41.681793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12465 12:29:41.681903 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12466 12:29:41.682202 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12467 12:29:41.682317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12468 12:29:41.682422 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12469 12:29:41.682523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12470 12:29:41.682641 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12471 12:29:41.683012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12472 12:29:41.684168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12473 12:29:41.684288 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12474 12:29:41.684374 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12475 12:29:41.684468 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12476 12:29:41.684571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12477 12:29:41.684683 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12478 12:29:41.684780 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12479 12:29:41.688287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12480 12:29:41.688748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12481 12:29:41.688854 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12482 12:29:41.688933 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12483 12:29:41.689018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12484 12:29:41.689132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12485 12:29:41.689228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12486 12:29:41.689304 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12487 12:29:41.689399 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12488 12:29:41.689699 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12489 12:29:41.689799 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12490 12:29:41.689918 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12491 12:29:41.690042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12492 12:29:41.690446 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12493 12:29:41.690555 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12494 12:29:41.690657 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12495 12:29:41.690778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12496 12:29:41.691103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12497 12:29:41.691407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12498 12:29:41.691527 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12499 12:29:41.691642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12500 12:29:41.691766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12501 12:29:41.691876 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12502 12:29:41.691988 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12503 12:29:41.692121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12504 12:29:41.692247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12505 12:29:41.696360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12506 12:29:41.696556 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12507 12:29:41.696671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12508 12:29:41.696776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12509 12:29:41.697084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12510 12:29:41.697190 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12511 12:29:41.697297 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12512 12:29:41.697402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12513 12:29:41.697508 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12514 12:29:41.697614 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12515 12:29:41.697935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12516 12:29:41.698047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12517 12:29:41.700620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12518 12:29:41.700819 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12519 12:29:41.701006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12520 12:29:41.701115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12521 12:29:41.701225 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12522 12:29:41.701321 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12523 12:29:41.701407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12524 12:29:41.701502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12525 12:29:41.701606 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12526 12:29:41.701726 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12527 12:29:41.701827 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12528 12:29:41.701919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12529 12:29:41.702014 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12530 12:29:41.702097 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12531 12:29:41.704244 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12532 12:29:41.704416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12533 12:29:41.704754 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12534 12:29:41.704994 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12535 12:29:41.705167 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12536 12:29:41.705290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12537 12:29:41.705387 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12538 12:29:41.705481 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12539 12:29:41.705577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12540 12:29:41.728567 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12541 12:29:41.728840 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12542 12:29:41.729239 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12543 12:29:41.729516 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12544 12:29:41.730006 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12545 12:29:41.730549 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12546 12:29:41.731050 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12547 12:29:41.731828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12548 12:29:41.732227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12549 12:29:41.732322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12550 12:29:41.732413 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12551 12:29:41.732527 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12552 12:29:41.732617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12553 12:29:41.732708 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12554 12:29:41.732793 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12555 12:29:41.732878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12556 12:29:41.732963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12557 12:29:41.733048 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12558 12:29:41.733132 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12559 12:29:41.733216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12560 12:29:41.733301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12561 12:29:41.733386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12562 12:29:41.733471 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12563 12:29:41.733555 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12564 12:29:41.736233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12565 12:29:41.736608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12566 12:29:41.736717 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12567 12:29:41.736834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12568 12:29:41.736957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12569 12:29:41.737081 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12570 12:29:41.737192 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12571 12:29:41.737266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12572 12:29:41.737582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12573 12:29:41.737771 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12574 12:29:41.737893 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12575 12:29:41.737998 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12576 12:29:41.738083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12577 12:29:41.738644 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12578 12:29:41.738865 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12579 12:29:41.739188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12580 12:29:41.739388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12581 12:29:41.739849 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12582 12:29:41.740003 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12583 12:29:41.740115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12584 12:29:41.740251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12585 12:29:41.740354 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12586 12:29:41.740452 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12587 12:29:41.740546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12588 12:29:41.740641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12589 12:29:41.744398 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12590 12:29:41.744529 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12591 12:29:41.744879 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12592 12:29:41.744987 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12593 12:29:41.745314 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12594 12:29:41.745453 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12595 12:29:41.745568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12596 12:29:41.745689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12597 12:29:41.745788 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12598 12:29:41.745871 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12599 12:29:41.746596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12600 12:29:41.747683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12601 12:29:41.747873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12602 12:29:41.747987 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12603 12:29:41.748088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12604 12:29:41.748188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12605 12:29:41.748287 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12606 12:29:41.748557 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12607 12:29:41.748671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12608 12:29:41.748765 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12609 12:29:41.748853 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12610 12:29:41.748940 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12611 12:29:41.749026 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12612 12:29:41.752245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12613 12:29:41.752635 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12614 12:29:41.752862 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12615 12:29:41.753011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12616 12:29:41.753160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12617 12:29:41.753279 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12618 12:29:41.753395 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12619 12:29:41.753541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12620 12:29:41.753676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12621 12:29:41.753762 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12622 12:29:41.753858 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12623 12:29:41.753957 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12624 12:29:41.754060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12625 12:29:41.754388 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12626 12:29:41.754493 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12627 12:29:41.754611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12628 12:29:41.754744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12629 12:29:41.754878 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12630 12:29:41.755007 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12631 12:29:41.756096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12632 12:29:41.756345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12633 12:29:41.756470 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12634 12:29:41.756607 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12635 12:29:41.756724 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12636 12:29:41.756826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12637 12:29:41.760265 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12638 12:29:41.760632 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12639 12:29:41.760737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12640 12:29:41.760825 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12641 12:29:41.760948 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12642 12:29:41.761071 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12643 12:29:41.761203 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12644 12:29:41.761408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12645 12:29:41.761533 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12646 12:29:41.761676 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12647 12:29:41.762022 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12648 12:29:41.762208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12649 12:29:41.762523 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12650 12:29:41.762723 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12651 12:29:41.762883 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12652 12:29:41.763085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12653 12:29:41.763179 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12654 12:29:41.763267 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12655 12:29:41.763353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12656 12:29:41.763457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12657 12:29:41.763546 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12658 12:29:41.763626 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12659 12:29:41.763720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12660 12:29:41.763813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12661 12:29:41.763906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12662 12:29:41.768185 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12663 12:29:41.768617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12664 12:29:41.768757 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12665 12:29:41.768871 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12666 12:29:41.768961 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12667 12:29:41.769063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12668 12:29:41.769165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12669 12:29:41.769268 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12670 12:29:41.769369 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12671 12:29:41.769716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12672 12:29:41.769836 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12673 12:29:41.770086 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12674 12:29:41.787139 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12675 12:29:41.787595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12676 12:29:41.787685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12677 12:29:41.787762 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12678 12:29:41.787853 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12679 12:29:41.787928 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12680 12:29:41.788013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12681 12:29:41.788293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12682 12:29:41.788384 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12683 12:29:41.788472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12684 12:29:41.788559 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12685 12:29:41.788836 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12686 12:29:41.788942 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12687 12:29:41.789015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12688 12:29:41.789105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12689 12:29:41.789400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12690 12:29:41.789547 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12691 12:29:41.789688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12692 12:29:41.789839 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12693 12:29:41.789970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12694 12:29:41.790077 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12695 12:29:41.790165 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12696 12:29:41.790269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12697 12:29:41.790357 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12698 12:29:41.790443 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12699 12:29:41.790545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12700 12:29:41.790631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12701 12:29:41.790732 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12702 12:29:41.790841 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12703 12:29:41.790931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12704 12:29:41.791021 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12705 12:29:41.791098 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12706 12:29:41.791184 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12707 12:29:41.791271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12708 12:29:41.791359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12709 12:29:41.791665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12710 12:29:41.791750 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12711 12:29:41.792030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12712 12:29:41.792103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12713 12:29:41.792166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12714 12:29:41.796272 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12715 12:29:41.796697 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12716 12:29:41.796898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12717 12:29:41.796988 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12718 12:29:41.797095 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12719 12:29:41.797184 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12720 12:29:41.797266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12721 12:29:41.797360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12722 12:29:41.797468 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12723 12:29:41.797588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12724 12:29:41.797931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12725 12:29:41.798062 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12726 12:29:41.798197 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12727 12:29:41.798452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12728 12:29:41.798570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12729 12:29:41.798915 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12730 12:29:41.799034 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12731 12:29:41.799126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12732 12:29:41.799216 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12733 12:29:41.799315 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12734 12:29:41.799597 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12735 12:29:41.799703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12736 12:29:41.799995 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12737 12:29:41.800104 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12738 12:29:41.804367 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12739 12:29:41.804796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12740 12:29:41.804921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12741 12:29:41.805017 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12742 12:29:41.805115 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12743 12:29:41.805198 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12744 12:29:41.806124 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12745 12:29:41.806229 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12746 12:29:41.806307 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12747 12:29:41.806390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12748 12:29:41.806469 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12749 12:29:41.806559 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12750 12:29:41.806639 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12751 12:29:41.806745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12752 12:29:41.806877 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12753 12:29:41.806974 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12754 12:29:41.807271 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12755 12:29:41.807382 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12756 12:29:41.807499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12757 12:29:41.807805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12758 12:29:41.807893 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12759 12:29:41.812993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12760 12:29:41.813206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12761 12:29:41.813314 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12762 12:29:41.813620 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12763 12:29:41.813744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12764 12:29:41.813867 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12765 12:29:41.814005 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12766 12:29:41.814120 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12767 12:29:41.814236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12768 12:29:41.814353 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12769 12:29:41.814468 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12770 12:29:41.814577 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12771 12:29:41.814714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12772 12:29:41.814820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12773 12:29:41.814936 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12774 12:29:41.815049 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12775 12:29:41.815162 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12776 12:29:41.815261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12777 12:29:41.815372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12778 12:29:41.815657 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12779 12:29:41.815753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12780 12:29:41.815843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12781 12:29:41.815938 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12782 12:29:41.816217 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12783 12:29:41.820458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12784 12:29:41.820892 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12785 12:29:41.820983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12786 12:29:41.821078 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12787 12:29:41.821193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12788 12:29:41.821588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12789 12:29:41.821694 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12790 12:29:41.821789 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12791 12:29:41.821902 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12792 12:29:41.822202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12793 12:29:41.822312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12794 12:29:41.822414 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12795 12:29:41.822517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12796 12:29:41.822619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12797 12:29:41.822696 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12798 12:29:41.822759 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12799 12:29:41.822832 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12800 12:29:41.822918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12801 12:29:41.823004 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12802 12:29:41.823272 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12803 12:29:41.823340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12804 12:29:41.823591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12805 12:29:41.823838 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12806 12:29:41.823918 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12807 12:29:41.823980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12808 12:29:41.845733 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12809 12:29:41.845965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12810 12:29:41.846059 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12811 12:29:41.846144 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12812 12:29:41.846220 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12813 12:29:41.846296 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12814 12:29:41.846372 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12815 12:29:41.846438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12816 12:29:41.846510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12817 12:29:41.846579 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12818 12:29:41.846653 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12819 12:29:41.846720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12820 12:29:41.847099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12821 12:29:41.847200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12822 12:29:41.847281 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12823 12:29:41.847359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12824 12:29:41.847432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12825 12:29:41.847506 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12826 12:29:41.847569 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12827 12:29:41.847629 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12828 12:29:41.847713 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12829 12:29:41.847793 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12830 12:29:41.847867 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12831 12:29:41.847936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12832 12:29:41.848017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12833 12:29:41.848085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12834 12:29:41.852303 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12835 12:29:41.852570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12836 12:29:41.852946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12837 12:29:41.853054 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12838 12:29:41.853137 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12839 12:29:41.853215 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12840 12:29:41.853310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12841 12:29:41.853402 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12842 12:29:41.853493 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12843 12:29:41.853584 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12844 12:29:41.853681 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12845 12:29:41.853965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12846 12:29:41.854075 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12847 12:29:41.854365 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12848 12:29:41.854521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12849 12:29:41.854688 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12850 12:29:41.854837 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12851 12:29:41.855039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12852 12:29:41.855163 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12853 12:29:41.855292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12854 12:29:41.855425 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12855 12:29:41.855568 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12856 12:29:41.855692 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12857 12:29:41.855815 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12858 12:29:41.855977 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12859 12:29:41.860335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12860 12:29:41.861318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12861 12:29:41.861577 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12862 12:29:41.861762 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12863 12:29:41.861934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12864 12:29:41.862098 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12865 12:29:41.862259 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12866 12:29:41.862439 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12867 12:29:41.862621 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12868 12:29:41.862775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12869 12:29:41.862970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12870 12:29:41.863103 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12871 12:29:41.863233 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12872 12:29:41.863346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12873 12:29:41.863482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12874 12:29:41.863626 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12875 12:29:41.863753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12876 12:29:41.863912 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12877 12:29:41.864026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12878 12:29:41.864138 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12879 12:29:41.864218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12880 12:29:41.864308 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12881 12:29:41.864384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12882 12:29:41.864458 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12883 12:29:41.868139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12884 12:29:41.868539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12885 12:29:41.868705 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12886 12:29:41.868808 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12887 12:29:41.868890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12888 12:29:41.868991 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12889 12:29:41.869084 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12890 12:29:41.869194 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12891 12:29:41.869489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12892 12:29:41.869603 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12893 12:29:41.869968 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12894 12:29:41.870142 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12895 12:29:41.870319 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12896 12:29:41.870457 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12897 12:29:41.871322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12898 12:29:41.871564 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12899 12:29:41.871689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12900 12:29:41.871800 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12901 12:29:41.871942 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12902 12:29:41.872261 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12903 12:29:41.872350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12904 12:29:41.872424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12905 12:29:41.872495 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12906 12:29:41.872566 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12907 12:29:41.876624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12908 12:29:41.876881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12909 12:29:41.877210 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12910 12:29:41.877796 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12911 12:29:41.877938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12912 12:29:41.878068 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12913 12:29:41.878186 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12914 12:29:41.878317 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12915 12:29:41.878462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12916 12:29:41.878600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12917 12:29:41.878999 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12918 12:29:41.880175 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12919 12:29:41.880279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12920 12:29:41.880356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12921 12:29:41.880431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12922 12:29:41.880504 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12923 12:29:41.880580 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12924 12:29:41.880658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12925 12:29:41.880734 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12926 12:29:41.880808 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12927 12:29:41.880878 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12928 12:29:41.880949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12929 12:29:41.881023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12930 12:29:41.881097 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12931 12:29:41.881180 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12932 12:29:41.881264 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12933 12:29:41.881348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12934 12:29:41.881434 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12935 12:29:41.884514 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12936 12:29:41.884650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12937 12:29:41.886971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12938 12:29:41.887110 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12939 12:29:41.887186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12940 12:29:41.887258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12941 12:29:41.887330 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12942 12:29:41.909740 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12943 12:29:41.910193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12944 12:29:41.910295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12945 12:29:41.910384 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12946 12:29:41.910468 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12947 12:29:41.910551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12948 12:29:41.910640 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12949 12:29:41.910728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12950 12:29:41.910811 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12951 12:29:41.910899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12952 12:29:41.910989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12953 12:29:41.911080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12954 12:29:41.911170 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12955 12:29:41.911260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12956 12:29:41.911351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12957 12:29:41.911442 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12958 12:29:41.911532 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12959 12:29:41.911624 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12960 12:29:41.911715 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12961 12:29:41.911805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12962 12:29:41.911895 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12963 12:29:41.911986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12964 12:29:41.912075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12965 12:29:41.912166 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12966 12:29:41.912256 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12967 12:29:41.913787 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12968 12:29:41.913895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12969 12:29:41.913983 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12970 12:29:41.914183 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12971 12:29:41.914268 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12972 12:29:41.914351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12973 12:29:41.914438 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12974 12:29:41.914522 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12975 12:29:41.914610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12976 12:29:41.914695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12977 12:29:41.914781 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12978 12:29:41.915044 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12979 12:29:41.915136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12980 12:29:41.915221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12981 12:29:41.915301 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12982 12:29:41.915381 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12983 12:29:41.916905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12984 12:29:41.917032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12985 12:29:41.917131 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12986 12:29:41.917222 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12987 12:29:41.917313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12988 12:29:41.917404 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12989 12:29:41.917494 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12990 12:29:41.917905 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12991 12:29:41.918015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12992 12:29:41.918115 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12993 12:29:41.918206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12994 12:29:41.918299 arm64_sve-ptrace pass
12995 12:29:41.918390 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12996 12:29:41.918500 arm64_sve-probe-vls_All_vector_lengths_valid pass
12997 12:29:41.918593 arm64_sve-probe-vls pass
12998 12:29:41.918684 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12999 12:29:41.918775 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
13000 12:29:41.918865 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
13001 12:29:41.918973 arm64_vec-syscfg_SVE_current_VL_is_64 pass
13002 12:29:41.919068 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
13003 12:29:41.919177 arm64_vec-syscfg_SVE_prctl_set_min_max pass
13004 12:29:41.919269 arm64_vec-syscfg_SVE_vector_length_used_default pass
13005 12:29:41.919361 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
13006 12:29:41.919469 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
13007 12:29:41.919579 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
13008 12:29:41.919685 arm64_vec-syscfg_SME_default_vector_length_32 pass
13009 12:29:41.919793 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
13010 12:29:41.920093 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
13011 12:29:41.924348 arm64_vec-syscfg_SME_current_VL_is_32 pass
13012 12:29:41.924583 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
13013 12:29:41.924923 arm64_vec-syscfg_SME_prctl_set_min_max pass
13014 12:29:41.925035 arm64_vec-syscfg_SME_vector_length_used_default pass
13015 12:29:41.925126 arm64_vec-syscfg_SME_vector_length_was_inherited pass
13016 12:29:41.925208 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
13017 12:29:41.925311 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
13018 12:29:41.925400 arm64_vec-syscfg pass
13019 12:29:41.925507 arm64_za-fork_fork_test pass
13020 12:29:41.925594 arm64_za-fork pass
13021 12:29:41.925685 arm64_za-ptrace_Set_VL_16 pass
13022 12:29:41.925762 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
13023 12:29:41.925847 arm64_za-ptrace_Data_match_for_VL_16 pass
13024 12:29:41.925918 arm64_za-ptrace_Set_VL_32 pass
13025 12:29:41.925991 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
13026 12:29:41.926090 arm64_za-ptrace_Data_match_for_VL_32 pass
13027 12:29:41.926177 arm64_za-ptrace_Set_VL_48 pass
13028 12:29:41.926280 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
13029 12:29:41.926367 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
13030 12:29:41.926465 arm64_za-ptrace_Set_VL_64 pass
13031 12:29:41.926551 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
13032 12:29:41.926644 arm64_za-ptrace_Data_match_for_VL_64 pass
13033 12:29:41.926743 arm64_za-ptrace_Set_VL_80 pass
13034 12:29:41.926845 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
13035 12:29:41.926944 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
13036 12:29:41.927044 arm64_za-ptrace_Set_VL_96 pass
13037 12:29:41.927423 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
13038 12:29:41.927534 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
13039 12:29:41.927624 arm64_za-ptrace_Set_VL_112 pass
13040 12:29:41.927727 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
13041 12:29:41.927812 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
13042 12:29:41.927909 arm64_za-ptrace_Set_VL_128 pass
13043 12:29:41.928003 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
13044 12:29:41.932235 arm64_za-ptrace_Data_match_for_VL_128 pass
13045 12:29:41.932362 arm64_za-ptrace_Set_VL_144 pass
13046 12:29:41.932708 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
13047 12:29:41.932819 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
13048 12:29:41.932894 arm64_za-ptrace_Set_VL_160 pass
13049 12:29:41.932966 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
13050 12:29:41.933050 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
13051 12:29:41.933336 arm64_za-ptrace_Set_VL_176 pass
13052 12:29:41.933444 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
13053 12:29:41.933531 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
13054 12:29:41.933618 arm64_za-ptrace_Set_VL_192 pass
13055 12:29:41.933719 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
13056 12:29:41.933806 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
13057 12:29:41.933890 arm64_za-ptrace_Set_VL_208 pass
13058 12:29:41.933992 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
13059 12:29:41.934082 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
13060 12:29:41.934180 arm64_za-ptrace_Set_VL_224 pass
13061 12:29:41.934259 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
13062 12:29:41.934340 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
13063 12:29:41.934422 arm64_za-ptrace_Set_VL_240 pass
13064 12:29:41.934507 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
13065 12:29:41.934837 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
13066 12:29:41.934945 arm64_za-ptrace_Set_VL_256 pass
13067 12:29:41.935045 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
13068 12:29:41.935126 arm64_za-ptrace_Data_match_for_VL_256 pass
13069 12:29:41.935224 arm64_za-ptrace_Set_VL_272 pass
13070 12:29:41.935323 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
13071 12:29:41.935422 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
13072 12:29:41.935520 arm64_za-ptrace_Set_VL_288 pass
13073 12:29:41.935809 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13074 12:29:41.935919 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13075 12:29:41.936010 arm64_za-ptrace_Set_VL_304 pass
13076 12:29:41.944274 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13077 12:29:41.944423 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13078 12:29:41.944725 arm64_za-ptrace_Set_VL_320 pass
13079 12:29:41.944834 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13080 12:29:41.944921 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13081 12:29:41.945008 arm64_za-ptrace_Set_VL_336 pass
13082 12:29:41.945078 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13083 12:29:41.945147 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13084 12:29:41.945233 arm64_za-ptrace_Set_VL_352 pass
13085 12:29:41.945319 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13086 12:29:41.945417 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13087 12:29:41.945505 arm64_za-ptrace_Set_VL_368 pass
13088 12:29:41.945603 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13089 12:29:41.945708 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13090 12:29:41.945805 arm64_za-ptrace_Set_VL_384 pass
13091 12:29:41.945901 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13092 12:29:41.945998 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13093 12:29:41.946108 arm64_za-ptrace_Set_VL_400 pass
13094 12:29:41.947250 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13095 12:29:41.947362 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13096 12:29:41.947449 arm64_za-ptrace_Set_VL_416 pass
13097 12:29:41.947532 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13098 12:29:41.947607 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13099 12:29:41.947675 arm64_za-ptrace_Set_VL_432 pass
13100 12:29:41.947743 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13101 12:29:41.947815 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13102 12:29:41.947893 arm64_za-ptrace_Set_VL_448 pass
13103 12:29:41.947976 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13104 12:29:41.948058 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13105 12:29:41.948374 arm64_za-ptrace_Set_VL_464 pass
13106 12:29:41.948478 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13107 12:29:41.948566 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13108 12:29:41.948653 arm64_za-ptrace_Set_VL_480 pass
13109 12:29:41.948737 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13110 12:29:41.948820 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13111 12:29:41.948902 arm64_za-ptrace_Set_VL_496 pass
13112 12:29:41.948982 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13113 12:29:41.975219 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13114 12:29:41.975459 arm64_za-ptrace_Set_VL_512 pass
13115 12:29:41.975789 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13116 12:29:41.975902 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13117 12:29:41.976001 arm64_za-ptrace_Set_VL_528 pass
13118 12:29:41.976095 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13119 12:29:41.976194 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13120 12:29:41.976293 arm64_za-ptrace_Set_VL_544 pass
13121 12:29:41.976722 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13122 12:29:41.976834 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13123 12:29:41.976930 arm64_za-ptrace_Set_VL_560 pass
13124 12:29:41.977025 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13125 12:29:41.977120 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13126 12:29:41.977213 arm64_za-ptrace_Set_VL_576 pass
13127 12:29:41.977306 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13128 12:29:41.977399 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13129 12:29:41.977493 arm64_za-ptrace_Set_VL_592 pass
13130 12:29:41.977837 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13131 12:29:41.977948 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13132 12:29:41.978044 arm64_za-ptrace_Set_VL_608 pass
13133 12:29:41.978139 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13134 12:29:41.978235 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13135 12:29:41.978329 arm64_za-ptrace_Set_VL_624 pass
13136 12:29:41.978421 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13137 12:29:41.978515 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13138 12:29:41.978608 arm64_za-ptrace_Set_VL_640 pass
13139 12:29:41.978700 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13140 12:29:41.978795 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13141 12:29:41.978886 arm64_za-ptrace_Set_VL_656 pass
13142 12:29:41.979427 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13143 12:29:41.979567 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13144 12:29:41.979663 arm64_za-ptrace_Set_VL_672 pass
13145 12:29:41.979755 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13146 12:29:41.979843 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13147 12:29:41.979930 arm64_za-ptrace_Set_VL_688 pass
13148 12:29:41.980018 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13149 12:29:41.980105 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13150 12:29:41.980197 arm64_za-ptrace_Set_VL_704 pass
13151 12:29:41.980284 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13152 12:29:41.980373 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13153 12:29:41.980465 arm64_za-ptrace_Set_VL_720 pass
13154 12:29:41.980557 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13155 12:29:41.980649 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13156 12:29:41.980738 arm64_za-ptrace_Set_VL_736 pass
13157 12:29:41.980826 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13158 12:29:41.981436 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13159 12:29:41.981548 arm64_za-ptrace_Set_VL_752 pass
13160 12:29:41.981729 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13161 12:29:41.981916 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13162 12:29:41.982024 arm64_za-ptrace_Set_VL_768 pass
13163 12:29:41.982118 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13164 12:29:41.984286 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13165 12:29:41.984407 arm64_za-ptrace_Set_VL_784 pass
13166 12:29:41.984722 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13167 12:29:41.984828 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13168 12:29:41.984920 arm64_za-ptrace_Set_VL_800 pass
13169 12:29:41.985010 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13170 12:29:41.985531 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13171 12:29:41.985698 arm64_za-ptrace_Set_VL_816 pass
13172 12:29:41.986011 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13173 12:29:41.986420 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13174 12:29:41.986666 arm64_za-ptrace_Set_VL_832 pass
13175 12:29:41.986934 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13176 12:29:41.987402 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13177 12:29:41.987528 arm64_za-ptrace_Set_VL_848 pass
13178 12:29:41.987634 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13179 12:29:41.987723 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13180 12:29:41.988107 arm64_za-ptrace_Set_VL_864 pass
13181 12:29:41.988208 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13182 12:29:41.988301 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13183 12:29:41.988394 arm64_za-ptrace_Set_VL_880 pass
13184 12:29:41.988483 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13185 12:29:41.988573 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13186 12:29:41.988661 arm64_za-ptrace_Set_VL_896 pass
13187 12:29:41.988750 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13188 12:29:41.989008 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13189 12:29:41.989118 arm64_za-ptrace_Set_VL_912 pass
13190 12:29:41.989209 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13191 12:29:41.989299 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13192 12:29:41.989387 arm64_za-ptrace_Set_VL_928 pass
13193 12:29:41.989474 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13194 12:29:41.989563 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13195 12:29:41.989716 arm64_za-ptrace_Set_VL_944 pass
13196 12:29:41.989857 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13197 12:29:41.989954 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13198 12:29:41.990044 arm64_za-ptrace_Set_VL_960 pass
13199 12:29:41.992321 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13200 12:29:41.992533 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13201 12:29:41.992924 arm64_za-ptrace_Set_VL_976 pass
13202 12:29:41.993034 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13203 12:29:41.993132 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13204 12:29:41.993231 arm64_za-ptrace_Set_VL_992 pass
13205 12:29:41.993324 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13206 12:29:41.993416 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13207 12:29:41.997790 arm64_za-ptrace_Set_VL_1008 pass
13208 12:29:41.997956 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13209 12:29:41.998061 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13210 12:29:41.998157 arm64_za-ptrace_Set_VL_1024 pass
13211 12:29:41.998252 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13212 12:29:41.998351 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13213 12:29:41.998445 arm64_za-ptrace_Set_VL_1040 pass
13214 12:29:41.998539 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13215 12:29:41.998632 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13216 12:29:41.998727 arm64_za-ptrace_Set_VL_1056 pass
13217 12:29:41.998819 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13218 12:29:41.998911 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13219 12:29:41.999004 arm64_za-ptrace_Set_VL_1072 pass
13220 12:29:41.999097 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13221 12:29:41.999193 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13222 12:29:41.999285 arm64_za-ptrace_Set_VL_1088 pass
13223 12:29:41.999379 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13224 12:29:41.999469 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13225 12:29:41.999563 arm64_za-ptrace_Set_VL_1104 pass
13226 12:29:41.999653 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13227 12:29:41.999746 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13228 12:29:41.999838 arm64_za-ptrace_Set_VL_1120 pass
13229 12:29:41.999931 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13230 12:29:42.000023 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13231 12:29:42.000115 arm64_za-ptrace_Set_VL_1136 pass
13232 12:29:42.000207 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13233 12:29:42.000306 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13234 12:29:42.000400 arm64_za-ptrace_Set_VL_1152 pass
13235 12:29:42.001043 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13236 12:29:42.001157 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13237 12:29:42.001256 arm64_za-ptrace_Set_VL_1168 pass
13238 12:29:42.001348 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13239 12:29:42.001442 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13240 12:29:42.001535 arm64_za-ptrace_Set_VL_1184 pass
13241 12:29:42.001625 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13242 12:29:42.001933 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13243 12:29:42.002055 arm64_za-ptrace_Set_VL_1200 pass
13244 12:29:42.002151 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13245 12:29:42.002245 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13246 12:29:42.002337 arm64_za-ptrace_Set_VL_1216 pass
13247 12:29:42.002430 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13248 12:29:42.002522 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13249 12:29:42.002615 arm64_za-ptrace_Set_VL_1232 pass
13250 12:29:42.002706 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13251 12:29:42.002799 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13252 12:29:42.002891 arm64_za-ptrace_Set_VL_1248 pass
13253 12:29:42.002982 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13254 12:29:42.003076 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13255 12:29:42.003173 arm64_za-ptrace_Set_VL_1264 pass
13256 12:29:42.003267 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13257 12:29:42.003358 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13258 12:29:42.003451 arm64_za-ptrace_Set_VL_1280 pass
13259 12:29:42.003565 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13260 12:29:42.003660 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13261 12:29:42.003753 arm64_za-ptrace_Set_VL_1296 pass
13262 12:29:42.003845 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13263 12:29:42.003940 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13264 12:29:42.004031 arm64_za-ptrace_Set_VL_1312 pass
13265 12:29:42.004124 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13266 12:29:42.004217 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13267 12:29:42.004316 arm64_za-ptrace_Set_VL_1328 pass
13268 12:29:42.004409 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13269 12:29:42.004501 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13270 12:29:42.004596 arm64_za-ptrace_Set_VL_1344 pass
13271 12:29:42.004687 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13272 12:29:42.004801 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13273 12:29:42.004896 arm64_za-ptrace_Set_VL_1360 pass
13274 12:29:42.004988 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13275 12:29:42.005083 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13276 12:29:42.005176 arm64_za-ptrace_Set_VL_1376 pass
13277 12:29:42.008231 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13278 12:29:42.008359 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13279 12:29:42.008703 arm64_za-ptrace_Set_VL_1392 pass
13280 12:29:42.008813 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13281 12:29:42.008904 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13282 12:29:42.008992 arm64_za-ptrace_Set_VL_1408 pass
13283 12:29:42.009096 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13284 12:29:42.009186 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13285 12:29:42.009279 arm64_za-ptrace_Set_VL_1424 pass
13286 12:29:42.009390 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13287 12:29:42.009485 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13288 12:29:42.009579 arm64_za-ptrace_Set_VL_1440 pass
13289 12:29:42.009959 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13290 12:29:42.010095 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13291 12:29:42.010193 arm64_za-ptrace_Set_VL_1456 pass
13292 12:29:42.010293 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13293 12:29:42.010386 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13294 12:29:42.010478 arm64_za-ptrace_Set_VL_1472 pass
13295 12:29:42.010572 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13296 12:29:42.010664 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13297 12:29:42.011266 arm64_za-ptrace_Set_VL_1488 pass
13298 12:29:42.011367 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13299 12:29:42.011461 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13300 12:29:42.011555 arm64_za-ptrace_Set_VL_1504 pass
13301 12:29:42.011819 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13302 12:29:42.011918 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13303 12:29:42.012012 arm64_za-ptrace_Set_VL_1520 pass
13304 12:29:42.012103 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13305 12:29:42.012197 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13306 12:29:42.012290 arm64_za-ptrace_Set_VL_1536 pass
13307 12:29:42.012383 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13308 12:29:42.038280 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13309 12:29:42.038775 arm64_za-ptrace_Set_VL_1552 pass
13310 12:29:42.038938 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13311 12:29:42.039056 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13312 12:29:42.039155 arm64_za-ptrace_Set_VL_1568 pass
13313 12:29:42.039250 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13314 12:29:42.039366 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13315 12:29:42.039462 arm64_za-ptrace_Set_VL_1584 pass
13316 12:29:42.039560 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13317 12:29:42.039654 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13318 12:29:42.039748 arm64_za-ptrace_Set_VL_1600 pass
13319 12:29:42.039860 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13320 12:29:42.039954 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13321 12:29:42.040047 arm64_za-ptrace_Set_VL_1616 pass
13322 12:29:42.040137 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13323 12:29:42.040249 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13324 12:29:42.040344 arm64_za-ptrace_Set_VL_1632 pass
13325 12:29:42.040454 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13326 12:29:42.040552 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13327 12:29:42.040662 arm64_za-ptrace_Set_VL_1648 pass
13328 12:29:42.040759 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13329 12:29:42.040870 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13330 12:29:42.040965 arm64_za-ptrace_Set_VL_1664 pass
13331 12:29:42.041077 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13332 12:29:42.041171 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13333 12:29:42.041284 arm64_za-ptrace_Set_VL_1680 pass
13334 12:29:42.041398 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13335 12:29:42.041509 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13336 12:29:42.041621 arm64_za-ptrace_Set_VL_1696 pass
13337 12:29:42.042192 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13338 12:29:42.042293 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13339 12:29:42.042388 arm64_za-ptrace_Set_VL_1712 pass
13340 12:29:42.042482 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13341 12:29:42.042593 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13342 12:29:42.042689 arm64_za-ptrace_Set_VL_1728 pass
13343 12:29:42.042783 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13344 12:29:42.042876 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13345 12:29:42.042988 arm64_za-ptrace_Set_VL_1744 pass
13346 12:29:42.043083 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13347 12:29:42.043177 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13348 12:29:42.043285 arm64_za-ptrace_Set_VL_1760 pass
13349 12:29:42.043379 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13350 12:29:42.043490 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13351 12:29:42.043584 arm64_za-ptrace_Set_VL_1776 pass
13352 12:29:42.043678 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13353 12:29:42.043786 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13354 12:29:42.044075 arm64_za-ptrace_Set_VL_1792 pass
13355 12:29:42.044159 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13356 12:29:42.048233 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13357 12:29:42.048798 arm64_za-ptrace_Set_VL_1808 pass
13358 12:29:42.048911 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13359 12:29:42.049006 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13360 12:29:42.049097 arm64_za-ptrace_Set_VL_1824 pass
13361 12:29:42.049188 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13362 12:29:42.049297 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13363 12:29:42.049388 arm64_za-ptrace_Set_VL_1840 pass
13364 12:29:42.049477 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13365 12:29:42.049562 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13366 12:29:42.049677 arm64_za-ptrace_Set_VL_1856 pass
13367 12:29:42.049770 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13368 12:29:42.049877 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13369 12:29:42.049969 arm64_za-ptrace_Set_VL_1872 pass
13370 12:29:42.050073 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13371 12:29:42.050181 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13372 12:29:42.050307 arm64_za-ptrace_Set_VL_1888 pass
13373 12:29:42.050418 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13374 12:29:42.050542 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13375 12:29:42.050653 arm64_za-ptrace_Set_VL_1904 pass
13376 12:29:42.050756 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13377 12:29:42.051178 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13378 12:29:42.051287 arm64_za-ptrace_Set_VL_1920 pass
13379 12:29:42.051390 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13380 12:29:42.051475 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13381 12:29:42.051558 arm64_za-ptrace_Set_VL_1936 pass
13382 12:29:42.051663 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13383 12:29:42.051773 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13384 12:29:42.051908 arm64_za-ptrace_Set_VL_1952 pass
13385 12:29:42.052016 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13386 12:29:42.052148 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13387 12:29:42.052240 arm64_za-ptrace_Set_VL_1968 pass
13388 12:29:42.052327 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13389 12:29:42.052599 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13390 12:29:42.052705 arm64_za-ptrace_Set_VL_1984 pass
13391 12:29:42.052832 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13392 12:29:42.060217 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13393 12:29:42.060603 arm64_za-ptrace_Set_VL_2000 pass
13394 12:29:42.060708 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13395 12:29:42.060828 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13396 12:29:42.060924 arm64_za-ptrace_Set_VL_2016 pass
13397 12:29:42.061221 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13398 12:29:42.061326 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13399 12:29:42.061445 arm64_za-ptrace_Set_VL_2032 pass
13400 12:29:42.061553 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13401 12:29:42.061915 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13402 12:29:42.062019 arm64_za-ptrace_Set_VL_2048 pass
13403 12:29:42.062111 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13404 12:29:42.062228 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13405 12:29:42.062338 arm64_za-ptrace_Set_VL_2064 pass
13406 12:29:42.062464 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13407 12:29:42.062560 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13408 12:29:42.062968 arm64_za-ptrace_Set_VL_2080 pass
13409 12:29:42.063080 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13410 12:29:42.063177 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13411 12:29:42.063262 arm64_za-ptrace_Set_VL_2096 pass
13412 12:29:42.063344 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13413 12:29:42.063622 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13414 12:29:42.063722 arm64_za-ptrace_Set_VL_2112 pass
13415 12:29:42.063814 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13416 12:29:42.063901 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13417 12:29:42.064216 arm64_za-ptrace_Set_VL_2128 pass
13418 12:29:42.064328 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13419 12:29:42.064423 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13420 12:29:42.064522 arm64_za-ptrace_Set_VL_2144 pass
13421 12:29:42.064622 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13422 12:29:42.064714 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13423 12:29:42.064801 arm64_za-ptrace_Set_VL_2160 pass
13424 12:29:42.064883 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13425 12:29:42.064966 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13426 12:29:42.068479 arm64_za-ptrace_Set_VL_2176 pass
13427 12:29:42.068622 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13428 12:29:42.068947 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13429 12:29:42.069175 arm64_za-ptrace_Set_VL_2192 pass
13430 12:29:42.069285 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13431 12:29:42.069397 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13432 12:29:42.069516 arm64_za-ptrace_Set_VL_2208 pass
13433 12:29:42.069644 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13434 12:29:42.069747 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13435 12:29:42.069833 arm64_za-ptrace_Set_VL_2224 pass
13436 12:29:42.069917 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13437 12:29:42.070537 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13438 12:29:42.070692 arm64_za-ptrace_Set_VL_2240 pass
13439 12:29:42.070786 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13440 12:29:42.070949 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13441 12:29:42.071033 arm64_za-ptrace_Set_VL_2256 pass
13442 12:29:42.071112 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13443 12:29:42.071240 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13444 12:29:42.071339 arm64_za-ptrace_Set_VL_2272 pass
13445 12:29:42.071470 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13446 12:29:42.072016 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13447 12:29:42.072121 arm64_za-ptrace_Set_VL_2288 pass
13448 12:29:42.072411 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13449 12:29:42.072518 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13450 12:29:42.072609 arm64_za-ptrace_Set_VL_2304 pass
13451 12:29:42.072690 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13452 12:29:42.072764 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13453 12:29:42.072844 arm64_za-ptrace_Set_VL_2320 pass
13454 12:29:42.072922 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13455 12:29:42.073000 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13456 12:29:42.073079 arm64_za-ptrace_Set_VL_2336 pass
13457 12:29:42.073156 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13458 12:29:42.076292 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13459 12:29:42.076489 arm64_za-ptrace_Set_VL_2352 pass
13460 12:29:42.076771 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13461 12:29:42.076884 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13462 12:29:42.077044 arm64_za-ptrace_Set_VL_2368 pass
13463 12:29:42.077147 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13464 12:29:42.077237 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13465 12:29:42.077317 arm64_za-ptrace_Set_VL_2384 pass
13466 12:29:42.077422 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13467 12:29:42.077513 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13468 12:29:42.077603 arm64_za-ptrace_Set_VL_2400 pass
13469 12:29:42.077722 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13470 12:29:42.077803 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13471 12:29:42.077878 arm64_za-ptrace_Set_VL_2416 pass
13472 12:29:42.077968 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13473 12:29:42.078048 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13474 12:29:42.078124 arm64_za-ptrace_Set_VL_2432 pass
13475 12:29:42.078420 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13476 12:29:42.078520 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13477 12:29:42.078601 arm64_za-ptrace_Set_VL_2448 pass
13478 12:29:42.078991 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13479 12:29:42.079140 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13480 12:29:42.079241 arm64_za-ptrace_Set_VL_2464 pass
13481 12:29:42.079319 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13482 12:29:42.079393 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13483 12:29:42.079464 arm64_za-ptrace_Set_VL_2480 pass
13484 12:29:42.079537 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13485 12:29:42.079803 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13486 12:29:42.079897 arm64_za-ptrace_Set_VL_2496 pass
13487 12:29:42.079971 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13488 12:29:42.080047 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13489 12:29:42.080121 arm64_za-ptrace_Set_VL_2512 pass
13490 12:29:42.080193 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13491 12:29:42.080268 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13492 12:29:42.080345 arm64_za-ptrace_Set_VL_2528 pass
13493 12:29:42.080434 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13494 12:29:42.080513 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13495 12:29:42.084219 arm64_za-ptrace_Set_VL_2544 pass
13496 12:29:42.084642 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13497 12:29:42.084757 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13498 12:29:42.084854 arm64_za-ptrace_Set_VL_2560 pass
13499 12:29:42.084946 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13500 12:29:42.085305 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13501 12:29:42.111423 arm64_za-ptrace_Set_VL_2576 pass
13502 12:29:42.111663 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13503 12:29:42.111779 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13504 12:29:42.111877 arm64_za-ptrace_Set_VL_2592 pass
13505 12:29:42.111965 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13506 12:29:42.112063 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13507 12:29:42.112151 arm64_za-ptrace_Set_VL_2608 pass
13508 12:29:42.112248 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13509 12:29:42.112348 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13510 12:29:42.112450 arm64_za-ptrace_Set_VL_2624 pass
13511 12:29:42.112548 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13512 12:29:42.112646 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13513 12:29:42.112977 arm64_za-ptrace_Set_VL_2640 pass
13514 12:29:42.113081 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13515 12:29:42.113825 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13516 12:29:42.113963 arm64_za-ptrace_Set_VL_2656 pass
13517 12:29:42.114078 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13518 12:29:42.114217 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13519 12:29:42.114337 arm64_za-ptrace_Set_VL_2672 pass
13520 12:29:42.114423 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13521 12:29:42.114487 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13522 12:29:42.114765 arm64_za-ptrace_Set_VL_2688 pass
13523 12:29:42.114852 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13524 12:29:42.114952 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13525 12:29:42.115072 arm64_za-ptrace_Set_VL_2704 pass
13526 12:29:42.115187 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13527 12:29:42.115303 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13528 12:29:42.115417 arm64_za-ptrace_Set_VL_2720 pass
13529 12:29:42.115528 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13530 12:29:42.115620 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13531 12:29:42.115699 arm64_za-ptrace_Set_VL_2736 pass
13532 12:29:42.115763 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13533 12:29:42.115824 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13534 12:29:42.115916 arm64_za-ptrace_Set_VL_2752 pass
13535 12:29:42.115988 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13536 12:29:42.116074 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13537 12:29:42.116146 arm64_za-ptrace_Set_VL_2768 pass
13538 12:29:42.116212 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13539 12:29:42.116273 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13540 12:29:42.116338 arm64_za-ptrace_Set_VL_2784 pass
13541 12:29:42.116399 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13542 12:29:42.116475 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13543 12:29:42.116544 arm64_za-ptrace_Set_VL_2800 pass
13544 12:29:42.116621 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13545 12:29:42.116685 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13546 12:29:42.120155 arm64_za-ptrace_Set_VL_2816 pass
13547 12:29:42.120479 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13548 12:29:42.120556 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13549 12:29:42.120628 arm64_za-ptrace_Set_VL_2832 pass
13550 12:29:42.120723 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13551 12:29:42.120810 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13552 12:29:42.121065 arm64_za-ptrace_Set_VL_2848 pass
13553 12:29:42.121164 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13554 12:29:42.121233 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13555 12:29:42.121313 arm64_za-ptrace_Set_VL_2864 pass
13556 12:29:42.121398 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13557 12:29:42.121506 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13558 12:29:42.121789 arm64_za-ptrace_Set_VL_2880 pass
13559 12:29:42.122129 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13560 12:29:42.122230 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13561 12:29:42.122317 arm64_za-ptrace_Set_VL_2896 pass
13562 12:29:42.122404 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13563 12:29:42.122504 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13564 12:29:42.122741 arm64_za-ptrace_Set_VL_2912 pass
13565 12:29:42.122834 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13566 12:29:42.123027 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13567 12:29:42.123136 arm64_za-ptrace_Set_VL_2928 pass
13568 12:29:42.123555 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13569 12:29:42.123664 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13570 12:29:42.123754 arm64_za-ptrace_Set_VL_2944 pass
13571 12:29:42.123842 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13572 12:29:42.123928 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13573 12:29:42.124014 arm64_za-ptrace_Set_VL_2960 pass
13574 12:29:42.124100 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13575 12:29:42.124187 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13576 12:29:42.124490 arm64_za-ptrace_Set_VL_2976 pass
13577 12:29:42.124595 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13578 12:29:42.124685 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13579 12:29:42.124772 arm64_za-ptrace_Set_VL_2992 pass
13580 12:29:42.128212 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13581 12:29:42.128626 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13582 12:29:42.128732 arm64_za-ptrace_Set_VL_3008 pass
13583 12:29:42.128847 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13584 12:29:42.128954 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13585 12:29:42.129049 arm64_za-ptrace_Set_VL_3024 pass
13586 12:29:42.129119 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13587 12:29:42.129197 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13588 12:29:42.129271 arm64_za-ptrace_Set_VL_3040 pass
13589 12:29:42.129366 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13590 12:29:42.129449 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13591 12:29:42.129558 arm64_za-ptrace_Set_VL_3056 pass
13592 12:29:42.129663 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13593 12:29:42.129758 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13594 12:29:42.129854 arm64_za-ptrace_Set_VL_3072 pass
13595 12:29:42.129927 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13596 12:29:42.130018 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13597 12:29:42.130102 arm64_za-ptrace_Set_VL_3088 pass
13598 12:29:42.130198 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13599 12:29:42.130275 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13600 12:29:42.130345 arm64_za-ptrace_Set_VL_3104 pass
13601 12:29:42.130465 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13602 12:29:42.130794 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13603 12:29:42.131372 arm64_za-ptrace_Set_VL_3120 pass
13604 12:29:42.131470 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13605 12:29:42.131563 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13606 12:29:42.131638 arm64_za-ptrace_Set_VL_3136 pass
13607 12:29:42.131710 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13608 12:29:42.131781 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13609 12:29:42.131873 arm64_za-ptrace_Set_VL_3152 pass
13610 12:29:42.131993 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13611 12:29:42.132096 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13612 12:29:42.132219 arm64_za-ptrace_Set_VL_3168 pass
13613 12:29:42.132380 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13614 12:29:42.132583 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13615 12:29:42.132719 arm64_za-ptrace_Set_VL_3184 pass
13616 12:29:42.136207 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13617 12:29:42.136654 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13618 12:29:42.136756 arm64_za-ptrace_Set_VL_3200 pass
13619 12:29:42.136842 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13620 12:29:42.136927 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13621 12:29:42.137048 arm64_za-ptrace_Set_VL_3216 pass
13622 12:29:42.137144 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13623 12:29:42.137234 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13624 12:29:42.137319 arm64_za-ptrace_Set_VL_3232 pass
13625 12:29:42.137420 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13626 12:29:42.137522 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13627 12:29:42.137608 arm64_za-ptrace_Set_VL_3248 pass
13628 12:29:42.137709 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13629 12:29:42.137817 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13630 12:29:42.137905 arm64_za-ptrace_Set_VL_3264 pass
13631 12:29:42.138311 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13632 12:29:42.138410 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13633 12:29:42.138490 arm64_za-ptrace_Set_VL_3280 pass
13634 12:29:42.138566 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13635 12:29:42.138659 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13636 12:29:42.139405 arm64_za-ptrace_Set_VL_3296 pass
13637 12:29:42.141793 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13638 12:29:42.141959 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13639 12:29:42.142066 arm64_za-ptrace_Set_VL_3312 pass
13640 12:29:42.142157 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13641 12:29:42.142234 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13642 12:29:42.142309 arm64_za-ptrace_Set_VL_3328 pass
13643 12:29:42.142384 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13644 12:29:42.142461 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13645 12:29:42.142535 arm64_za-ptrace_Set_VL_3344 pass
13646 12:29:42.142609 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13647 12:29:42.142683 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13648 12:29:42.142757 arm64_za-ptrace_Set_VL_3360 pass
13649 12:29:42.142831 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13650 12:29:42.142926 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13651 12:29:42.146320 arm64_za-ptrace_Set_VL_3376 pass
13652 12:29:42.146618 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13653 12:29:42.146930 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13654 12:29:42.147070 arm64_za-ptrace_Set_VL_3392 pass
13655 12:29:42.147260 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13656 12:29:42.147464 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13657 12:29:42.147697 arm64_za-ptrace_Set_VL_3408 pass
13658 12:29:42.147850 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13659 12:29:42.148041 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13660 12:29:42.148258 arm64_za-ptrace_Set_VL_3424 pass
13661 12:29:42.148416 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13662 12:29:42.148499 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13663 12:29:42.148701 arm64_za-ptrace_Set_VL_3440 pass
13664 12:29:42.148902 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13665 12:29:42.149463 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13666 12:29:42.149709 arm64_za-ptrace_Set_VL_3456 pass
13667 12:29:42.149829 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13668 12:29:42.149908 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13669 12:29:42.150220 arm64_za-ptrace_Set_VL_3472 pass
13670 12:29:42.150307 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13671 12:29:42.150396 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13672 12:29:42.150473 arm64_za-ptrace_Set_VL_3488 pass
13673 12:29:42.150556 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13674 12:29:42.150631 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13675 12:29:42.150706 arm64_za-ptrace_Set_VL_3504 pass
13676 12:29:42.150781 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13677 12:29:42.150856 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13678 12:29:42.150961 arm64_za-ptrace_Set_VL_3520 pass
13679 12:29:42.151051 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13680 12:29:42.151132 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13681 12:29:42.151222 arm64_za-ptrace_Set_VL_3536 pass
13682 12:29:42.151308 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13683 12:29:42.151398 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13684 12:29:42.151489 arm64_za-ptrace_Set_VL_3552 pass
13685 12:29:42.151570 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13686 12:29:42.152483 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13687 12:29:42.152604 arm64_za-ptrace_Set_VL_3568 pass
13688 12:29:42.152707 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13689 12:29:42.153010 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13690 12:29:42.153104 arm64_za-ptrace_Set_VL_3584 pass
13691 12:29:42.153186 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13692 12:29:42.153267 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13693 12:29:42.181740 arm64_za-ptrace_Set_VL_3600 pass
13694 12:29:42.181972 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13695 12:29:42.182057 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13696 12:29:42.182137 arm64_za-ptrace_Set_VL_3616 pass
13697 12:29:42.182214 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13698 12:29:42.182294 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13699 12:29:42.182370 arm64_za-ptrace_Set_VL_3632 pass
13700 12:29:42.182445 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13701 12:29:42.182530 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13702 12:29:42.182605 arm64_za-ptrace_Set_VL_3648 pass
13703 12:29:42.183969 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13704 12:29:42.184116 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13705 12:29:42.184196 arm64_za-ptrace_Set_VL_3664 pass
13706 12:29:42.184269 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13707 12:29:42.184563 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13708 12:29:42.184674 arm64_za-ptrace_Set_VL_3680 pass
13709 12:29:42.184769 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13710 12:29:42.184862 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13711 12:29:42.184953 arm64_za-ptrace_Set_VL_3696 pass
13712 12:29:42.185042 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13713 12:29:42.185132 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13714 12:29:42.185223 arm64_za-ptrace_Set_VL_3712 pass
13715 12:29:42.185315 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13716 12:29:42.185404 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13717 12:29:42.185494 arm64_za-ptrace_Set_VL_3728 pass
13718 12:29:42.185589 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13719 12:29:42.185752 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13720 12:29:42.185843 arm64_za-ptrace_Set_VL_3744 pass
13721 12:29:42.185960 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13722 12:29:42.186064 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13723 12:29:42.187155 arm64_za-ptrace_Set_VL_3760 pass
13724 12:29:42.187282 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13725 12:29:42.188249 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13726 12:29:42.190608 arm64_za-ptrace_Set_VL_3776 pass
13727 12:29:42.190714 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13728 12:29:42.190801 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13729 12:29:42.190883 arm64_za-ptrace_Set_VL_3792 pass
13730 12:29:42.190963 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13731 12:29:42.191055 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13732 12:29:42.191144 arm64_za-ptrace_Set_VL_3808 pass
13733 12:29:42.191225 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13734 12:29:42.191306 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13735 12:29:42.191390 arm64_za-ptrace_Set_VL_3824 pass
13736 12:29:42.191478 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13737 12:29:42.191560 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13738 12:29:42.191633 arm64_za-ptrace_Set_VL_3840 pass
13739 12:29:42.191706 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13740 12:29:42.191784 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13741 12:29:42.191874 arm64_za-ptrace_Set_VL_3856 pass
13742 12:29:42.191972 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13743 12:29:42.192048 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13744 12:29:42.192127 arm64_za-ptrace_Set_VL_3872 pass
13745 12:29:42.192196 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13746 12:29:42.192256 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13747 12:29:42.192315 arm64_za-ptrace_Set_VL_3888 pass
13748 12:29:42.192565 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13749 12:29:42.192643 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13750 12:29:42.192706 arm64_za-ptrace_Set_VL_3904 pass
13751 12:29:42.192767 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13752 12:29:42.192828 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13753 12:29:42.192888 arm64_za-ptrace_Set_VL_3920 pass
13754 12:29:42.192948 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13755 12:29:42.193007 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13756 12:29:42.193066 arm64_za-ptrace_Set_VL_3936 pass
13757 12:29:42.193126 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13758 12:29:42.196221 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13759 12:29:42.196315 arm64_za-ptrace_Set_VL_3952 pass
13760 12:29:42.196594 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13761 12:29:42.196695 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13762 12:29:42.196780 arm64_za-ptrace_Set_VL_3968 pass
13763 12:29:42.196875 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13764 12:29:42.196957 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13765 12:29:42.197038 arm64_za-ptrace_Set_VL_3984 pass
13766 12:29:42.197127 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13767 12:29:42.197392 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13768 12:29:42.197474 arm64_za-ptrace_Set_VL_4000 pass
13769 12:29:42.197554 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13770 12:29:42.197627 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13771 12:29:42.197728 arm64_za-ptrace_Set_VL_4016 pass
13772 12:29:42.197806 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13773 12:29:42.197895 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13774 12:29:42.197976 arm64_za-ptrace_Set_VL_4032 pass
13775 12:29:42.198063 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13776 12:29:42.198341 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13777 12:29:42.198434 arm64_za-ptrace_Set_VL_4048 pass
13778 12:29:42.198524 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13779 12:29:42.198595 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13780 12:29:42.198667 arm64_za-ptrace_Set_VL_4064 pass
13781 12:29:42.198754 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13782 12:29:42.198835 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13783 12:29:42.199143 arm64_za-ptrace_Set_VL_4080 pass
13784 12:29:42.199269 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13785 12:29:42.199353 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13786 12:29:42.199448 arm64_za-ptrace_Set_VL_4096 pass
13787 12:29:42.199529 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13788 12:29:42.199622 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13789 12:29:42.200014 arm64_za-ptrace_Set_VL_4112 pass
13790 12:29:42.200141 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13791 12:29:42.200252 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13792 12:29:42.200355 arm64_za-ptrace_Set_VL_4128 pass
13793 12:29:42.200455 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13794 12:29:42.200530 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13795 12:29:42.200611 arm64_za-ptrace_Set_VL_4144 pass
13796 12:29:42.204956 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13797 12:29:42.205088 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13798 12:29:42.205169 arm64_za-ptrace_Set_VL_4160 pass
13799 12:29:42.205249 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13800 12:29:42.205326 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13801 12:29:42.205397 arm64_za-ptrace_Set_VL_4176 pass
13802 12:29:42.205641 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13803 12:29:42.205723 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13804 12:29:42.205827 arm64_za-ptrace_Set_VL_4192 pass
13805 12:29:42.207454 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13806 12:29:42.207552 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13807 12:29:42.207632 arm64_za-ptrace_Set_VL_4208 pass
13808 12:29:42.207711 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13809 12:29:42.207785 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13810 12:29:42.207869 arm64_za-ptrace_Set_VL_4224 pass
13811 12:29:42.207959 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13812 12:29:42.208043 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13813 12:29:42.208106 arm64_za-ptrace_Set_VL_4240 pass
13814 12:29:42.208166 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13815 12:29:42.208225 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13816 12:29:42.208285 arm64_za-ptrace_Set_VL_4256 pass
13817 12:29:42.208345 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13818 12:29:42.208404 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13819 12:29:42.208464 arm64_za-ptrace_Set_VL_4272 pass
13820 12:29:42.208523 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13821 12:29:42.208582 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13822 12:29:42.208646 arm64_za-ptrace_Set_VL_4288 pass
13823 12:29:42.208706 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13824 12:29:42.208765 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13825 12:29:42.208825 arm64_za-ptrace_Set_VL_4304 pass
13826 12:29:42.208885 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13827 12:29:42.208944 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13828 12:29:42.209003 arm64_za-ptrace_Set_VL_4320 pass
13829 12:29:42.209062 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13830 12:29:42.209304 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13831 12:29:42.209370 arm64_za-ptrace_Set_VL_4336 pass
13832 12:29:42.209431 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13833 12:29:42.209491 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13834 12:29:42.209550 arm64_za-ptrace_Set_VL_4352 pass
13835 12:29:42.209612 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13836 12:29:42.212303 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13837 12:29:42.212413 arm64_za-ptrace_Set_VL_4368 pass
13838 12:29:42.212953 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13839 12:29:42.213056 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13840 12:29:42.213139 arm64_za-ptrace_Set_VL_4384 pass
13841 12:29:42.213202 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13842 12:29:42.213616 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13843 12:29:42.213750 arm64_za-ptrace_Set_VL_4400 pass
13844 12:29:42.213885 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13845 12:29:42.213986 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13846 12:29:42.214246 arm64_za-ptrace_Set_VL_4416 pass
13847 12:29:42.214338 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13848 12:29:42.214424 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13849 12:29:42.214510 arm64_za-ptrace_Set_VL_4432 pass
13850 12:29:42.214612 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13851 12:29:42.214709 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13852 12:29:42.214796 arm64_za-ptrace_Set_VL_4448 pass
13853 12:29:42.214881 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13854 12:29:42.214965 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13855 12:29:42.215061 arm64_za-ptrace_Set_VL_4464 pass
13856 12:29:42.215164 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13857 12:29:42.215252 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13858 12:29:42.215344 arm64_za-ptrace_Set_VL_4480 pass
13859 12:29:42.215412 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13860 12:29:42.215476 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13861 12:29:42.215545 arm64_za-ptrace_Set_VL_4496 pass
13862 12:29:42.215625 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13863 12:29:42.215709 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13864 12:29:42.215793 arm64_za-ptrace_Set_VL_4512 pass
13865 12:29:42.215905 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13866 12:29:42.215988 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13867 12:29:42.216072 arm64_za-ptrace_Set_VL_4528 pass
13868 12:29:42.216139 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13869 12:29:42.216199 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13870 12:29:42.216258 arm64_za-ptrace_Set_VL_4544 pass
13871 12:29:42.216331 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13872 12:29:42.220384 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13873 12:29:42.220758 arm64_za-ptrace_Set_VL_4560 pass
13874 12:29:42.221052 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13875 12:29:42.221150 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13876 12:29:42.221231 arm64_za-ptrace_Set_VL_4576 pass
13877 12:29:42.221310 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13878 12:29:42.221388 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13879 12:29:42.221461 arm64_za-ptrace_Set_VL_4592 pass
13880 12:29:42.221684 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13881 12:29:42.221766 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13882 12:29:42.221839 arm64_za-ptrace_Set_VL_4608 pass
13883 12:29:42.221910 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13884 12:29:42.221984 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13885 12:29:42.222109 arm64_za-ptrace_Set_VL_4624 pass
13886 12:29:42.243589 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13887 12:29:42.243736 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13888 12:29:42.244044 arm64_za-ptrace_Set_VL_4640 pass
13889 12:29:42.244192 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13890 12:29:42.244284 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13891 12:29:42.244364 arm64_za-ptrace_Set_VL_4656 pass
13892 12:29:42.244459 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13893 12:29:42.244751 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13894 12:29:42.244856 arm64_za-ptrace_Set_VL_4672 pass
13895 12:29:42.244944 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13896 12:29:42.245029 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13897 12:29:42.245128 arm64_za-ptrace_Set_VL_4688 pass
13898 12:29:42.245398 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13899 12:29:42.245500 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13900 12:29:42.245585 arm64_za-ptrace_Set_VL_4704 pass
13901 12:29:42.245681 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13902 12:29:42.246074 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13903 12:29:42.246179 arm64_za-ptrace_Set_VL_4720 pass
13904 12:29:42.246266 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13905 12:29:42.246350 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13906 12:29:42.246435 arm64_za-ptrace_Set_VL_4736 pass
13907 12:29:42.246717 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13908 12:29:42.246817 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13909 12:29:42.246902 arm64_za-ptrace_Set_VL_4752 pass
13910 12:29:42.246983 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13911 12:29:42.247065 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13912 12:29:42.247146 arm64_za-ptrace_Set_VL_4768 pass
13913 12:29:42.247243 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13914 12:29:42.247670 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13915 12:29:42.247804 arm64_za-ptrace_Set_VL_4784 pass
13916 12:29:42.247902 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13917 12:29:42.247997 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13918 12:29:42.248072 arm64_za-ptrace_Set_VL_4800 pass
13919 12:29:42.248133 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13920 12:29:42.248193 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13921 12:29:42.248440 arm64_za-ptrace_Set_VL_4816 pass
13922 12:29:42.248534 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13923 12:29:42.252131 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13924 12:29:42.252453 arm64_za-ptrace_Set_VL_4832 pass
13925 12:29:42.252563 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13926 12:29:42.252665 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13927 12:29:42.252767 arm64_za-ptrace_Set_VL_4848 pass
13928 12:29:42.252853 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13929 12:29:42.252952 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13930 12:29:42.253056 arm64_za-ptrace_Set_VL_4864 pass
13931 12:29:42.253197 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13932 12:29:42.253314 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13933 12:29:42.253441 arm64_za-ptrace_Set_VL_4880 pass
13934 12:29:42.253556 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13935 12:29:42.253679 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13936 12:29:42.253768 arm64_za-ptrace_Set_VL_4896 pass
13937 12:29:42.254112 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13938 12:29:42.254217 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13939 12:29:42.254308 arm64_za-ptrace_Set_VL_4912 pass
13940 12:29:42.254395 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13941 12:29:42.254748 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13942 12:29:42.254854 arm64_za-ptrace_Set_VL_4928 pass
13943 12:29:42.255011 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13944 12:29:42.255119 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13945 12:29:42.255223 arm64_za-ptrace_Set_VL_4944 pass
13946 12:29:42.255324 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13947 12:29:42.255432 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13948 12:29:42.255536 arm64_za-ptrace_Set_VL_4960 pass
13949 12:29:42.255634 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13950 12:29:42.255716 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13951 12:29:42.255805 arm64_za-ptrace_Set_VL_4976 pass
13952 12:29:42.255898 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13953 12:29:42.256020 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13954 12:29:42.256127 arm64_za-ptrace_Set_VL_4992 pass
13955 12:29:42.256219 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13956 12:29:42.256296 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13957 12:29:42.256372 arm64_za-ptrace_Set_VL_5008 pass
13958 12:29:42.260193 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13959 12:29:42.260327 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13960 12:29:42.260618 arm64_za-ptrace_Set_VL_5024 pass
13961 12:29:42.260728 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13962 12:29:42.260815 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13963 12:29:42.260900 arm64_za-ptrace_Set_VL_5040 pass
13964 12:29:42.260999 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13965 12:29:42.261201 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13966 12:29:42.261379 arm64_za-ptrace_Set_VL_5056 pass
13967 12:29:42.261476 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13968 12:29:42.261565 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13969 12:29:42.261676 arm64_za-ptrace_Set_VL_5072 pass
13970 12:29:42.261771 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13971 12:29:42.261876 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13972 12:29:42.261962 arm64_za-ptrace_Set_VL_5088 pass
13973 12:29:42.262063 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13974 12:29:42.262166 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13975 12:29:42.262430 arm64_za-ptrace_Set_VL_5104 pass
13976 12:29:42.262525 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13977 12:29:42.262629 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13978 12:29:42.262719 arm64_za-ptrace_Set_VL_5120 pass
13979 12:29:42.262817 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13980 12:29:42.262917 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13981 12:29:42.263019 arm64_za-ptrace_Set_VL_5136 pass
13982 12:29:42.263316 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13983 12:29:42.263435 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13984 12:29:42.263527 arm64_za-ptrace_Set_VL_5152 pass
13985 12:29:42.263627 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13986 12:29:42.263729 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13987 12:29:42.263837 arm64_za-ptrace_Set_VL_5168 pass
13988 12:29:42.263944 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13989 12:29:42.268193 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13990 12:29:42.268517 arm64_za-ptrace_Set_VL_5184 pass
13991 12:29:42.268624 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13992 12:29:42.268733 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13993 12:29:42.268824 arm64_za-ptrace_Set_VL_5200 pass
13994 12:29:42.268925 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13995 12:29:42.269028 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13996 12:29:42.269127 arm64_za-ptrace_Set_VL_5216 pass
13997 12:29:42.269850 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13998 12:29:42.269949 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13999 12:29:42.270029 arm64_za-ptrace_Set_VL_5232 pass
14000 12:29:42.270094 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
14001 12:29:42.270157 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
14002 12:29:42.270230 arm64_za-ptrace_Set_VL_5248 pass
14003 12:29:42.270499 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
14004 12:29:42.270606 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
14005 12:29:42.270718 arm64_za-ptrace_Set_VL_5264 pass
14006 12:29:42.270827 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
14007 12:29:42.270932 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
14008 12:29:42.271046 arm64_za-ptrace_Set_VL_5280 pass
14009 12:29:42.271144 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
14010 12:29:42.271232 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
14011 12:29:42.271314 arm64_za-ptrace_Set_VL_5296 pass
14012 12:29:42.271394 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
14013 12:29:42.271482 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
14014 12:29:42.271562 arm64_za-ptrace_Set_VL_5312 pass
14015 12:29:42.271644 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
14016 12:29:42.271747 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
14017 12:29:42.271836 arm64_za-ptrace_Set_VL_5328 pass
14018 12:29:42.271944 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
14019 12:29:42.272051 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
14020 12:29:42.272129 arm64_za-ptrace_Set_VL_5344 pass
14021 12:29:42.272190 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
14022 12:29:42.276121 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
14023 12:29:42.276688 arm64_za-ptrace_Set_VL_5360 pass
14024 12:29:42.276870 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
14025 12:29:42.276962 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
14026 12:29:42.277048 arm64_za-ptrace_Set_VL_5376 pass
14027 12:29:42.277141 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
14028 12:29:42.277214 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
14029 12:29:42.277285 arm64_za-ptrace_Set_VL_5392 pass
14030 12:29:42.277728 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
14031 12:29:42.277836 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
14032 12:29:42.277923 arm64_za-ptrace_Set_VL_5408 pass
14033 12:29:42.278007 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
14034 12:29:42.278107 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
14035 12:29:42.278196 arm64_za-ptrace_Set_VL_5424 pass
14036 12:29:42.278281 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
14037 12:29:42.278363 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
14038 12:29:42.278445 arm64_za-ptrace_Set_VL_5440 pass
14039 12:29:42.278732 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
14040 12:29:42.278841 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
14041 12:29:42.278917 arm64_za-ptrace_Set_VL_5456 pass
14042 12:29:42.278990 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
14043 12:29:42.279060 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
14044 12:29:42.279135 arm64_za-ptrace_Set_VL_5472 pass
14045 12:29:42.279238 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
14046 12:29:42.279323 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
14047 12:29:42.279406 arm64_za-ptrace_Set_VL_5488 pass
14048 12:29:42.279488 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
14049 12:29:42.279569 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
14050 12:29:42.279645 arm64_za-ptrace_Set_VL_5504 pass
14051 12:29:42.279725 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
14052 12:29:42.279824 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
14053 12:29:42.279909 arm64_za-ptrace_Set_VL_5520 pass
14054 12:29:42.279995 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
14055 12:29:42.280078 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
14056 12:29:42.280160 arm64_za-ptrace_Set_VL_5536 pass
14057 12:29:42.280258 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
14058 12:29:42.284200 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
14059 12:29:42.284512 arm64_za-ptrace_Set_VL_5552 pass
14060 12:29:42.284616 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
14061 12:29:42.284698 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
14062 12:29:42.284982 arm64_za-ptrace_Set_VL_5568 pass
14063 12:29:42.285081 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
14064 12:29:42.285176 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
14065 12:29:42.285251 arm64_za-ptrace_Set_VL_5584 pass
14066 12:29:42.285327 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
14067 12:29:42.285419 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
14068 12:29:42.285499 arm64_za-ptrace_Set_VL_5600 pass
14069 12:29:42.285582 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
14070 12:29:42.285672 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
14071 12:29:42.285774 arm64_za-ptrace_Set_VL_5616 pass
14072 12:29:42.285862 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
14073 12:29:42.285974 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14074 12:29:42.286042 arm64_za-ptrace_Set_VL_5632 pass
14075 12:29:42.286104 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14076 12:29:42.286177 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14077 12:29:42.286241 arm64_za-ptrace_Set_VL_5648 pass
14078 12:29:42.307600 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14079 12:29:42.307773 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14080 12:29:42.307861 arm64_za-ptrace_Set_VL_5664 pass
14081 12:29:42.308163 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14082 12:29:42.308272 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14083 12:29:42.308367 arm64_za-ptrace_Set_VL_5680 pass
14084 12:29:42.308456 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14085 12:29:42.308548 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14086 12:29:42.308637 arm64_za-ptrace_Set_VL_5696 pass
14087 12:29:42.308728 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14088 12:29:42.308836 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14089 12:29:42.309036 arm64_za-ptrace_Set_VL_5712 pass
14090 12:29:42.309131 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14091 12:29:42.309217 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14092 12:29:42.309304 arm64_za-ptrace_Set_VL_5728 pass
14093 12:29:42.309407 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14094 12:29:42.309497 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14095 12:29:42.309583 arm64_za-ptrace_Set_VL_5744 pass
14096 12:29:42.309940 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14097 12:29:42.310050 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14098 12:29:42.310140 arm64_za-ptrace_Set_VL_5760 pass
14099 12:29:42.310225 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14100 12:29:42.310311 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14101 12:29:42.310395 arm64_za-ptrace_Set_VL_5776 pass
14102 12:29:42.310690 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14103 12:29:42.310852 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14104 12:29:42.310961 arm64_za-ptrace_Set_VL_5792 pass
14105 12:29:42.311043 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14106 12:29:42.312142 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14107 12:29:42.312245 arm64_za-ptrace_Set_VL_5808 pass
14108 12:29:42.312332 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14109 12:29:42.312414 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14110 12:29:42.312494 arm64_za-ptrace_Set_VL_5824 pass
14111 12:29:42.312574 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14112 12:29:42.312660 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14113 12:29:42.312743 arm64_za-ptrace_Set_VL_5840 pass
14114 12:29:42.312829 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14115 12:29:42.312909 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14116 12:29:42.312991 arm64_za-ptrace_Set_VL_5856 pass
14117 12:29:42.313072 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14118 12:29:42.313152 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14119 12:29:42.313231 arm64_za-ptrace_Set_VL_5872 pass
14120 12:29:42.313309 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14121 12:29:42.313389 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14122 12:29:42.313469 arm64_za-ptrace_Set_VL_5888 pass
14123 12:29:42.313866 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14124 12:29:42.313966 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14125 12:29:42.316274 arm64_za-ptrace_Set_VL_5904 pass
14126 12:29:42.316592 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14127 12:29:42.316704 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14128 12:29:42.316789 arm64_za-ptrace_Set_VL_5920 pass
14129 12:29:42.316878 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14130 12:29:42.316952 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14131 12:29:42.317022 arm64_za-ptrace_Set_VL_5936 pass
14132 12:29:42.317117 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14133 12:29:42.317200 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14134 12:29:42.317278 arm64_za-ptrace_Set_VL_5952 pass
14135 12:29:42.317356 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14136 12:29:42.317436 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14137 12:29:42.317536 arm64_za-ptrace_Set_VL_5968 pass
14138 12:29:42.317619 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14139 12:29:42.317725 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14140 12:29:42.317815 arm64_za-ptrace_Set_VL_5984 pass
14141 12:29:42.317913 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14142 12:29:42.317996 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14143 12:29:42.318090 arm64_za-ptrace_Set_VL_6000 pass
14144 12:29:42.318172 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14145 12:29:42.318265 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14146 12:29:42.318550 arm64_za-ptrace_Set_VL_6016 pass
14147 12:29:42.318650 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14148 12:29:42.319430 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14149 12:29:42.319556 arm64_za-ptrace_Set_VL_6032 pass
14150 12:29:42.319635 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14151 12:29:42.319713 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14152 12:29:42.319785 arm64_za-ptrace_Set_VL_6048 pass
14153 12:29:42.319864 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14154 12:29:42.319939 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14155 12:29:42.320011 arm64_za-ptrace_Set_VL_6064 pass
14156 12:29:42.320106 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14157 12:29:42.320389 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14158 12:29:42.320483 arm64_za-ptrace_Set_VL_6080 pass
14159 12:29:42.320562 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14160 12:29:42.320636 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14161 12:29:42.320707 arm64_za-ptrace_Set_VL_6096 pass
14162 12:29:42.320783 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14163 12:29:42.324148 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14164 12:29:42.324431 arm64_za-ptrace_Set_VL_6112 pass
14165 12:29:42.324531 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14166 12:29:42.324607 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14167 12:29:42.324725 arm64_za-ptrace_Set_VL_6128 pass
14168 12:29:42.324823 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14169 12:29:42.324927 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14170 12:29:42.325048 arm64_za-ptrace_Set_VL_6144 pass
14171 12:29:42.325143 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14172 12:29:42.325230 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14173 12:29:42.325335 arm64_za-ptrace_Set_VL_6160 pass
14174 12:29:42.325430 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14175 12:29:42.325519 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14176 12:29:42.325612 arm64_za-ptrace_Set_VL_6176 pass
14177 12:29:42.325735 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14178 12:29:42.325843 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14179 12:29:42.325947 arm64_za-ptrace_Set_VL_6192 pass
14180 12:29:42.326038 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14181 12:29:42.326139 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14182 12:29:42.326219 arm64_za-ptrace_Set_VL_6208 pass
14183 12:29:42.326527 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14184 12:29:42.326633 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14185 12:29:42.326719 arm64_za-ptrace_Set_VL_6224 pass
14186 12:29:42.326804 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14187 12:29:42.326888 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14188 12:29:42.326969 arm64_za-ptrace_Set_VL_6240 pass
14189 12:29:42.327068 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14190 12:29:42.327159 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14191 12:29:42.327243 arm64_za-ptrace_Set_VL_6256 pass
14192 12:29:42.327324 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14193 12:29:42.327972 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14194 12:29:42.328075 arm64_za-ptrace_Set_VL_6272 pass
14195 12:29:42.328158 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14196 12:29:42.328264 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14197 12:29:42.328373 arm64_za-ptrace_Set_VL_6288 pass
14198 12:29:42.328465 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14199 12:29:42.328740 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14200 12:29:42.328894 arm64_za-ptrace_Set_VL_6304 pass
14201 12:29:42.332330 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14202 12:29:42.332442 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14203 12:29:42.332528 arm64_za-ptrace_Set_VL_6320 pass
14204 12:29:42.332610 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14205 12:29:42.333021 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14206 12:29:42.333357 arm64_za-ptrace_Set_VL_6336 pass
14207 12:29:42.333555 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14208 12:29:42.333644 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14209 12:29:42.333735 arm64_za-ptrace_Set_VL_6352 pass
14210 12:29:42.333817 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14211 12:29:42.333915 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14212 12:29:42.333989 arm64_za-ptrace_Set_VL_6368 pass
14213 12:29:42.334059 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14214 12:29:42.334142 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14215 12:29:42.334219 arm64_za-ptrace_Set_VL_6384 pass
14216 12:29:42.334295 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14217 12:29:42.334371 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14218 12:29:42.334449 arm64_za-ptrace_Set_VL_6400 pass
14219 12:29:42.335039 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14220 12:29:42.335148 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14221 12:29:42.335232 arm64_za-ptrace_Set_VL_6416 pass
14222 12:29:42.335312 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14223 12:29:42.335393 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14224 12:29:42.335470 arm64_za-ptrace_Set_VL_6432 pass
14225 12:29:42.335545 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14226 12:29:42.335621 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14227 12:29:42.335700 arm64_za-ptrace_Set_VL_6448 pass
14228 12:29:42.335782 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14229 12:29:42.335865 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14230 12:29:42.336145 arm64_za-ptrace_Set_VL_6464 pass
14231 12:29:42.336271 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14232 12:29:42.336402 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14233 12:29:42.336504 arm64_za-ptrace_Set_VL_6480 pass
14234 12:29:42.336594 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14235 12:29:42.336684 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14236 12:29:42.336765 arm64_za-ptrace_Set_VL_6496 pass
14237 12:29:42.336848 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14238 12:29:42.340209 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14239 12:29:42.340512 arm64_za-ptrace_Set_VL_6512 pass
14240 12:29:42.340617 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14241 12:29:42.340705 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14242 12:29:42.340804 arm64_za-ptrace_Set_VL_6528 pass
14243 12:29:42.340890 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14244 12:29:42.340988 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14245 12:29:42.341073 arm64_za-ptrace_Set_VL_6544 pass
14246 12:29:42.341173 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14247 12:29:42.341471 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14248 12:29:42.341577 arm64_za-ptrace_Set_VL_6560 pass
14249 12:29:42.341690 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14250 12:29:42.341781 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14251 12:29:42.341888 arm64_za-ptrace_Set_VL_6576 pass
14252 12:29:42.341979 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14253 12:29:42.342465 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14254 12:29:42.342572 arm64_za-ptrace_Set_VL_6592 pass
14255 12:29:42.342662 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14256 12:29:42.342949 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14257 12:29:42.343047 arm64_za-ptrace_Set_VL_6608 pass
14258 12:29:42.343137 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14259 12:29:42.343226 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14260 12:29:42.343316 arm64_za-ptrace_Set_VL_6624 pass
14261 12:29:42.343420 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14262 12:29:42.343510 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14263 12:29:42.343602 arm64_za-ptrace_Set_VL_6640 pass
14264 12:29:42.343688 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14265 12:29:42.343774 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14266 12:29:42.343861 arm64_za-ptrace_Set_VL_6656 pass
14267 12:29:42.343969 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14268 12:29:42.344060 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14269 12:29:42.344148 arm64_za-ptrace_Set_VL_6672 pass
14270 12:29:42.349773 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14271 12:29:42.369900 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14272 12:29:42.370158 arm64_za-ptrace_Set_VL_6688 pass
14273 12:29:42.370468 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14274 12:29:42.370579 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14275 12:29:42.370668 arm64_za-ptrace_Set_VL_6704 pass
14276 12:29:42.370771 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14277 12:29:42.370858 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14278 12:29:42.370946 arm64_za-ptrace_Set_VL_6720 pass
14279 12:29:42.371030 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14280 12:29:42.371114 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14281 12:29:42.371197 arm64_za-ptrace_Set_VL_6736 pass
14282 12:29:42.371297 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14283 12:29:42.371384 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14284 12:29:42.371468 arm64_za-ptrace_Set_VL_6752 pass
14285 12:29:42.371551 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14286 12:29:42.371651 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14287 12:29:42.371743 arm64_za-ptrace_Set_VL_6768 pass
14288 12:29:42.371823 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14289 12:29:42.371902 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14290 12:29:42.372004 arm64_za-ptrace_Set_VL_6784 pass
14291 12:29:42.372086 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14292 12:29:42.372165 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14293 12:29:42.372274 arm64_za-ptrace_Set_VL_6800 pass
14294 12:29:42.372742 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14295 12:29:42.372854 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14296 12:29:42.372951 arm64_za-ptrace_Set_VL_6816 pass
14297 12:29:42.373042 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14298 12:29:42.373144 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14299 12:29:42.373240 arm64_za-ptrace_Set_VL_6832 pass
14300 12:29:42.373333 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14301 12:29:42.373426 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14302 12:29:42.373512 arm64_za-ptrace_Set_VL_6848 pass
14303 12:29:42.373622 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14304 12:29:42.373730 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14305 12:29:42.373822 arm64_za-ptrace_Set_VL_6864 pass
14306 12:29:42.373931 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14307 12:29:42.374021 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14308 12:29:42.374112 arm64_za-ptrace_Set_VL_6880 pass
14309 12:29:42.374204 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14310 12:29:42.374312 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14311 12:29:42.374406 arm64_za-ptrace_Set_VL_6896 pass
14312 12:29:42.374495 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14313 12:29:42.374816 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14314 12:29:42.374918 arm64_za-ptrace_Set_VL_6912 pass
14315 12:29:42.375019 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14316 12:29:42.375114 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14317 12:29:42.375206 arm64_za-ptrace_Set_VL_6928 pass
14318 12:29:42.375296 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14319 12:29:42.375387 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14320 12:29:42.375479 arm64_za-ptrace_Set_VL_6944 pass
14321 12:29:42.375771 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14322 12:29:42.375885 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14323 12:29:42.375986 arm64_za-ptrace_Set_VL_6960 pass
14324 12:29:42.376078 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14325 12:29:42.376168 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14326 12:29:42.376260 arm64_za-ptrace_Set_VL_6976 pass
14327 12:29:42.376353 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14328 12:29:42.376463 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14329 12:29:42.376558 arm64_za-ptrace_Set_VL_6992 pass
14330 12:29:42.376649 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14331 12:29:42.376742 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14332 12:29:42.376834 arm64_za-ptrace_Set_VL_7008 pass
14333 12:29:42.376930 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14334 12:29:42.377022 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14335 12:29:42.380584 arm64_za-ptrace_Set_VL_7024 pass
14336 12:29:42.380747 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14337 12:29:42.380897 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14338 12:29:42.381045 arm64_za-ptrace_Set_VL_7040 pass
14339 12:29:42.382672 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14340 12:29:42.383853 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14341 12:29:42.384097 arm64_za-ptrace_Set_VL_7056 pass
14342 12:29:42.384183 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14343 12:29:42.384298 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14344 12:29:42.384382 arm64_za-ptrace_Set_VL_7072 pass
14345 12:29:42.384458 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14346 12:29:42.384532 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14347 12:29:42.384606 arm64_za-ptrace_Set_VL_7088 pass
14348 12:29:42.384680 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14349 12:29:42.384754 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14350 12:29:42.384835 arm64_za-ptrace_Set_VL_7104 pass
14351 12:29:42.384912 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14352 12:29:42.384986 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14353 12:29:42.385060 arm64_za-ptrace_Set_VL_7120 pass
14354 12:29:42.385134 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14355 12:29:42.385207 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14356 12:29:42.385281 arm64_za-ptrace_Set_VL_7136 pass
14357 12:29:42.385355 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14358 12:29:42.385428 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14359 12:29:42.385502 arm64_za-ptrace_Set_VL_7152 pass
14360 12:29:42.385576 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14361 12:29:42.385682 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14362 12:29:42.385761 arm64_za-ptrace_Set_VL_7168 pass
14363 12:29:42.385836 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14364 12:29:42.385910 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14365 12:29:42.385985 arm64_za-ptrace_Set_VL_7184 pass
14366 12:29:42.386074 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14367 12:29:42.386678 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14368 12:29:42.386871 arm64_za-ptrace_Set_VL_7200 pass
14369 12:29:42.386956 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14370 12:29:42.387031 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14371 12:29:42.387105 arm64_za-ptrace_Set_VL_7216 pass
14372 12:29:42.387177 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14373 12:29:42.387249 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14374 12:29:42.387321 arm64_za-ptrace_Set_VL_7232 pass
14375 12:29:42.387393 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14376 12:29:42.387465 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14377 12:29:42.387537 arm64_za-ptrace_Set_VL_7248 pass
14378 12:29:42.387609 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14379 12:29:42.387681 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14380 12:29:42.388396 arm64_za-ptrace_Set_VL_7264 pass
14381 12:29:42.388818 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14382 12:29:42.389578 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14383 12:29:42.389896 arm64_za-ptrace_Set_VL_7280 pass
14384 12:29:42.389985 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14385 12:29:42.390060 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14386 12:29:42.390133 arm64_za-ptrace_Set_VL_7296 pass
14387 12:29:42.390205 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14388 12:29:42.390278 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14389 12:29:42.390350 arm64_za-ptrace_Set_VL_7312 pass
14390 12:29:42.390443 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14391 12:29:42.390520 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14392 12:29:42.390597 arm64_za-ptrace_Set_VL_7328 pass
14393 12:29:42.390672 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14394 12:29:42.390747 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14395 12:29:42.390822 arm64_za-ptrace_Set_VL_7344 pass
14396 12:29:42.390897 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14397 12:29:42.390972 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14398 12:29:42.391046 arm64_za-ptrace_Set_VL_7360 pass
14399 12:29:42.391137 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14400 12:29:42.391214 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14401 12:29:42.391287 arm64_za-ptrace_Set_VL_7376 pass
14402 12:29:42.391361 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14403 12:29:42.391434 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14404 12:29:42.391507 arm64_za-ptrace_Set_VL_7392 pass
14405 12:29:42.391579 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14406 12:29:42.391652 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14407 12:29:42.391742 arm64_za-ptrace_Set_VL_7408 pass
14408 12:29:42.391816 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14409 12:29:42.391890 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14410 12:29:42.391962 arm64_za-ptrace_Set_VL_7424 pass
14411 12:29:42.392034 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14412 12:29:42.392106 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14413 12:29:42.392183 arm64_za-ptrace_Set_VL_7440 pass
14414 12:29:42.392256 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14415 12:29:42.392343 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14416 12:29:42.392419 arm64_za-ptrace_Set_VL_7456 pass
14417 12:29:42.397835 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14418 12:29:42.398042 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14419 12:29:42.398311 arm64_za-ptrace_Set_VL_7472 pass
14420 12:29:42.398414 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14421 12:29:42.398500 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14422 12:29:42.398581 arm64_za-ptrace_Set_VL_7488 pass
14423 12:29:42.398659 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14424 12:29:42.398738 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14425 12:29:42.398816 arm64_za-ptrace_Set_VL_7504 pass
14426 12:29:42.400073 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14427 12:29:42.400164 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14428 12:29:42.400248 arm64_za-ptrace_Set_VL_7520 pass
14429 12:29:42.400327 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14430 12:29:42.400405 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14431 12:29:42.400483 arm64_za-ptrace_Set_VL_7536 pass
14432 12:29:42.400560 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14433 12:29:42.400638 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14434 12:29:42.400715 arm64_za-ptrace_Set_VL_7552 pass
14435 12:29:42.400815 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14436 12:29:42.400897 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14437 12:29:42.400977 arm64_za-ptrace_Set_VL_7568 pass
14438 12:29:42.401055 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14439 12:29:42.401133 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14440 12:29:42.401213 arm64_za-ptrace_Set_VL_7584 pass
14441 12:29:42.401286 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14442 12:29:42.401360 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14443 12:29:42.401434 arm64_za-ptrace_Set_VL_7600 pass
14444 12:29:42.401509 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14445 12:29:42.401587 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14446 12:29:42.401672 arm64_za-ptrace_Set_VL_7616 pass
14447 12:29:42.401746 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14448 12:29:42.401815 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14449 12:29:42.401887 arm64_za-ptrace_Set_VL_7632 pass
14450 12:29:42.401965 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14451 12:29:42.402676 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14452 12:29:42.402766 arm64_za-ptrace_Set_VL_7648 pass
14453 12:29:42.404773 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14454 12:29:42.404880 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14455 12:29:42.404960 arm64_za-ptrace_Set_VL_7664 pass
14456 12:29:42.405045 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14457 12:29:42.405126 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14458 12:29:42.405362 arm64_za-ptrace_Set_VL_7680 pass
14459 12:29:42.405455 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14460 12:29:42.405696 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14461 12:29:42.405856 arm64_za-ptrace_Set_VL_7696 pass
14462 12:29:42.405947 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14463 12:29:42.437750 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14464 12:29:42.437967 arm64_za-ptrace_Set_VL_7712 pass
14465 12:29:42.438273 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14466 12:29:42.438378 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14467 12:29:42.438478 arm64_za-ptrace_Set_VL_7728 pass
14468 12:29:42.438567 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14469 12:29:42.438642 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14470 12:29:42.438758 arm64_za-ptrace_Set_VL_7744 pass
14471 12:29:42.438864 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14472 12:29:42.438957 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14473 12:29:42.439034 arm64_za-ptrace_Set_VL_7760 pass
14474 12:29:42.439103 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14475 12:29:42.439168 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14476 12:29:42.439231 arm64_za-ptrace_Set_VL_7776 pass
14477 12:29:42.439309 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14478 12:29:42.439376 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14479 12:29:42.439440 arm64_za-ptrace_Set_VL_7792 pass
14480 12:29:42.439503 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14481 12:29:42.439582 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14482 12:29:42.439647 arm64_za-ptrace_Set_VL_7808 pass
14483 12:29:42.439709 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14484 12:29:42.439786 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14485 12:29:42.440062 arm64_za-ptrace_Set_VL_7824 pass
14486 12:29:42.440170 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14487 12:29:42.440264 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14488 12:29:42.440355 arm64_za-ptrace_Set_VL_7840 pass
14489 12:29:42.440459 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14490 12:29:42.440549 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14491 12:29:42.440639 arm64_za-ptrace_Set_VL_7856 pass
14492 12:29:42.440741 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14493 12:29:42.440828 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14494 12:29:42.440915 arm64_za-ptrace_Set_VL_7872 pass
14495 12:29:42.441278 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14496 12:29:42.441374 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14497 12:29:42.441462 arm64_za-ptrace_Set_VL_7888 pass
14498 12:29:42.441747 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14499 12:29:42.441853 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14500 12:29:42.441945 arm64_za-ptrace_Set_VL_7904 pass
14501 12:29:42.442033 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14502 12:29:42.442611 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14503 12:29:42.442708 arm64_za-ptrace_Set_VL_7920 pass
14504 12:29:42.442797 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14505 12:29:42.442883 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14506 12:29:42.442972 arm64_za-ptrace_Set_VL_7936 pass
14507 12:29:42.443061 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14508 12:29:42.443150 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14509 12:29:42.443239 arm64_za-ptrace_Set_VL_7952 pass
14510 12:29:42.443327 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14511 12:29:42.443669 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14512 12:29:42.443770 arm64_za-ptrace_Set_VL_7968 pass
14513 12:29:42.443868 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14514 12:29:42.443976 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14515 12:29:42.444081 arm64_za-ptrace_Set_VL_7984 pass
14516 12:29:42.444189 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14517 12:29:42.444287 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14518 12:29:42.444405 arm64_za-ptrace_Set_VL_8000 pass
14519 12:29:42.444505 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14520 12:29:42.444604 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14521 12:29:42.444711 arm64_za-ptrace_Set_VL_8016 pass
14522 12:29:42.444810 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14523 12:29:42.444915 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14524 12:29:42.445013 arm64_za-ptrace_Set_VL_8032 pass
14525 12:29:42.445116 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14526 12:29:42.448741 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14527 12:29:42.448839 arm64_za-ptrace_Set_VL_8048 pass
14528 12:29:42.448923 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14529 12:29:42.449014 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14530 12:29:42.449113 arm64_za-ptrace_Set_VL_8064 pass
14531 12:29:42.450727 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14532 12:29:42.450858 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14533 12:29:42.450945 arm64_za-ptrace_Set_VL_8080 pass
14534 12:29:42.451051 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14535 12:29:42.451426 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14536 12:29:42.451537 arm64_za-ptrace_Set_VL_8096 pass
14537 12:29:42.451645 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14538 12:29:42.451743 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14539 12:29:42.451842 arm64_za-ptrace_Set_VL_8112 pass
14540 12:29:42.451945 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14541 12:29:42.452016 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14542 12:29:42.452081 arm64_za-ptrace_Set_VL_8128 pass
14543 12:29:42.452140 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14544 12:29:42.452200 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14545 12:29:42.452259 arm64_za-ptrace_Set_VL_8144 pass
14546 12:29:42.452319 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14547 12:29:42.452378 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14548 12:29:42.452438 arm64_za-ptrace_Set_VL_8160 pass
14549 12:29:42.452498 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14550 12:29:42.452557 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14551 12:29:42.452616 arm64_za-ptrace_Set_VL_8176 pass
14552 12:29:42.452675 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14553 12:29:42.452735 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14554 12:29:42.452793 arm64_za-ptrace_Set_VL_8192 pass
14555 12:29:42.452853 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14556 12:29:42.452912 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14557 12:29:42.452972 arm64_za-ptrace pass
14558 12:29:42.453032 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14559 12:29:42.453108 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14560 12:29:42.453172 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14561 12:29:42.453233 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14562 12:29:42.456425 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14563 12:29:42.457260 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14564 12:29:42.457365 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14565 12:29:42.457455 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14566 12:29:42.458568 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14567 12:29:42.458698 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14568 12:29:42.458796 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14569 12:29:42.458887 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14570 12:29:42.458994 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14571 12:29:42.459313 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14572 12:29:42.459434 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14573 12:29:42.459753 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14574 12:29:42.464460 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14575 12:29:42.464922 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14576 12:29:42.465058 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14577 12:29:42.465170 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14578 12:29:42.465442 arm64_check_buffer_fill fail
14579 12:29:42.465836 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14580 12:29:42.465948 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14581 12:29:42.466340 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14582 12:29:42.466463 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14583 12:29:42.466770 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14584 12:29:42.467098 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14585 12:29:42.467220 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14586 12:29:42.467571 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14587 12:29:42.467909 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14588 12:29:42.468029 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14589 12:29:42.476344 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14590 12:29:42.476703 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14591 12:29:42.476812 arm64_check_child_memory fail
14592 12:29:42.476989 arm64_check_gcr_el1_cswitch fail
14593 12:29:42.477094 arm64_check_ksm_options fail
14594 12:29:42.477196 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14595 12:29:42.477635 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14596 12:29:42.477982 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14597 12:29:42.481756 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14598 12:29:42.481879 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14599 12:29:42.485888 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14600 12:29:42.486215 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14601 12:29:42.486682 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14602 12:29:42.487004 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14603 12:29:42.487440 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14604 12:29:42.487768 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14605 12:29:42.488131 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14606 12:29:42.488419 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14607 12:29:42.488554 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14608 12:29:42.488866 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14609 12:29:42.489192 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14610 12:29:42.489526 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14611 12:29:42.489871 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14612 12:29:42.489999 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14613 12:29:42.490381 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14614 12:29:42.490695 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14615 12:29:42.491003 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14616 12:29:42.491108 arm64_check_mmap_options fail
14617 12:29:42.491211 arm64_check_prctl_check_basic_read pass
14618 12:29:42.491295 arm64_check_prctl_NONE pass
14619 12:29:42.491375 arm64_check_prctl_SYNC pass
14620 12:29:42.491467 arm64_check_prctl_ASYNC pass
14621 12:29:42.491546 arm64_check_prctl_SYNC_ASYNC pass
14622 12:29:42.491624 arm64_check_prctl pass
14623 12:29:42.491715 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14624 12:29:42.491994 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14625 12:29:42.496434 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14626 12:29:42.496973 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14627 12:29:42.497079 arm64_check_tags_inclusion fail
14628 12:29:42.497162 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14629 12:29:42.497254 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14630 12:29:42.497327 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14631 12:29:42.497417 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14632 12:29:42.497690 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14633 12:29:42.498000 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14634 12:29:42.498104 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14635 12:29:42.498199 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14636 12:29:42.498492 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14637 12:29:42.498612 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14638 12:29:42.498943 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14639 12:29:42.499064 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14640 12:29:42.499394 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14641 12:29:42.499702 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14642 12:29:42.499822 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14643 12:29:42.505131 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14644 12:29:42.505245 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14645 12:29:42.505336 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14646 12:29:42.505423 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14647 12:29:42.506319 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14648 12:29:42.506432 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14649 12:29:42.506522 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14650 12:29:42.506610 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14651 12:29:42.506695 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14652 12:29:42.506800 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14653 12:29:42.506888 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14654 12:29:42.506974 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14655 12:29:42.507072 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14656 12:29:42.510202 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14657 12:29:42.510317 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14658 12:29:42.510414 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14659 12:29:42.512497 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14660 12:29:42.512603 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14661 12:29:42.512889 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14662 12:29:42.512992 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14663 12:29:42.513097 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14664 12:29:42.513201 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14665 12:29:42.513701 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14666 12:29:42.513810 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14667 12:29:42.514310 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14668 12:29:42.514689 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14669 12:29:42.514824 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14670 12:29:42.514957 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14671 12:29:42.515119 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14672 12:29:42.515415 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14673 12:29:42.515839 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14674 12:29:42.515954 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14675 12:29:42.516362 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14676 12:29:42.524329 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14677 12:29:42.525712 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14678 12:29:42.525824 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14679 12:29:42.525911 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14680 12:29:42.525996 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14681 12:29:42.526082 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14682 12:29:42.526184 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14683 12:29:42.526269 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14684 12:29:42.526354 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14685 12:29:42.526489 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14686 12:29:42.526819 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14687 12:29:42.527124 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14688 12:29:42.527494 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14689 12:29:42.527782 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14690 12:29:42.545898 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14691 12:29:42.546112 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14692 12:29:42.546200 arm64_check_user_mem pass
14693 12:29:42.546283 arm64_btitest_nohint_func_call_using_br_x0 pass
14694 12:29:42.546371 arm64_btitest_nohint_func_call_using_br_x16 pass
14695 12:29:42.546450 arm64_btitest_nohint_func_call_using_blr pass
14696 12:29:42.546528 arm64_btitest_bti_none_func_call_using_br_x0 pass
14697 12:29:42.546787 arm64_btitest_bti_none_func_call_using_br_x16 pass
14698 12:29:42.546893 arm64_btitest_bti_none_func_call_using_blr pass
14699 12:29:42.546975 arm64_btitest_bti_c_func_call_using_br_x0 pass
14700 12:29:42.547054 arm64_btitest_bti_c_func_call_using_br_x16 pass
14701 12:29:42.547133 arm64_btitest_bti_c_func_call_using_blr pass
14702 12:29:42.547212 arm64_btitest_bti_j_func_call_using_br_x0 pass
14703 12:29:42.547307 arm64_btitest_bti_j_func_call_using_br_x16 pass
14704 12:29:42.547388 arm64_btitest_bti_j_func_call_using_blr pass
14705 12:29:42.547460 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14706 12:29:42.547544 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14707 12:29:42.547623 arm64_btitest_bti_jc_func_call_using_blr pass
14708 12:29:42.547704 arm64_btitest_paciasp_func_call_using_br_x0 pass
14709 12:29:42.547796 arm64_btitest_paciasp_func_call_using_br_x16 pass
14710 12:29:42.547880 arm64_btitest_paciasp_func_call_using_blr pass
14711 12:29:42.547960 arm64_btitest pass
14712 12:29:42.548056 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14713 12:29:42.548136 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14714 12:29:42.548213 arm64_nobtitest_nohint_func_call_using_blr pass
14715 12:29:42.552287 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14716 12:29:42.552635 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14717 12:29:42.552736 arm64_nobtitest_bti_none_func_call_using_blr pass
14718 12:29:42.552819 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14719 12:29:42.552899 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14720 12:29:42.552992 arm64_nobtitest_bti_c_func_call_using_blr pass
14721 12:29:42.553072 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14722 12:29:42.553155 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14723 12:29:42.553231 arm64_nobtitest_bti_j_func_call_using_blr pass
14724 12:29:42.553328 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14725 12:29:42.553610 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14726 12:29:42.553898 arm64_nobtitest_bti_jc_func_call_using_blr pass
14727 12:29:42.554169 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14728 12:29:42.554253 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14729 12:29:42.554335 arm64_nobtitest_paciasp_func_call_using_blr pass
14730 12:29:42.554426 arm64_nobtitest pass
14731 12:29:42.554518 arm64_hwcap_cpuinfo_match_RNG pass
14732 12:29:42.554599 arm64_hwcap_sigill_RNG pass
14733 12:29:42.554689 arm64_hwcap_cpuinfo_match_SME pass
14734 12:29:42.554958 arm64_hwcap_sigill_SME pass
14735 12:29:42.555038 arm64_hwcap_cpuinfo_match_SVE pass
14736 12:29:42.555113 arm64_hwcap_sigill_SVE pass
14737 12:29:42.555205 arm64_hwcap_cpuinfo_match_SVE_2 pass
14738 12:29:42.555285 arm64_hwcap_sigill_SVE_2 pass
14739 12:29:42.555376 arm64_hwcap_cpuinfo_match_SVE_AES pass
14740 12:29:42.555471 arm64_hwcap_sigill_SVE_AES pass
14741 12:29:42.555551 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14742 12:29:42.555629 arm64_hwcap_sigill_SVE2_PMULL pass
14743 12:29:42.555720 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14744 12:29:42.555799 arm64_hwcap_sigill_SVE2_BITPERM pass
14745 12:29:42.555892 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14746 12:29:42.555972 arm64_hwcap_sigill_SVE2_SHA3 pass
14747 12:29:42.556063 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14748 12:29:42.560355 arm64_hwcap_sigill_SVE2_SM4 pass
14749 12:29:42.560760 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14750 12:29:42.560860 arm64_hwcap_sigill_SVE2_I8MM pass
14751 12:29:42.560944 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14752 12:29:42.561037 arm64_hwcap_sigill_SVE2_F32MM pass
14753 12:29:42.561117 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14754 12:29:42.561196 arm64_hwcap_sigill_SVE2_F64MM pass
14755 12:29:42.561273 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14756 12:29:42.561368 arm64_hwcap_sigill_SVE2_BF16 pass
14757 12:29:42.561445 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14758 12:29:42.561522 arm64_hwcap_sigill_SVE2_EBF16 skip
14759 12:29:42.561613 arm64_hwcap pass
14760 12:29:42.561766 arm64_ptrace_read_tpidr_one pass
14761 12:29:42.561919 arm64_ptrace_write_tpidr_one pass
14762 12:29:42.562008 arm64_ptrace_verify_tpidr_one pass
14763 12:29:42.562086 arm64_ptrace_count_tpidrs pass
14764 12:29:42.562161 arm64_ptrace_tpidr2_write pass
14765 12:29:42.562252 arm64_ptrace_tpidr2_read pass
14766 12:29:42.562333 arm64_ptrace_write_tpidr_only pass
14767 12:29:42.562429 arm64_ptrace pass
14768 12:29:42.562509 arm64_syscall-abi_getpid_FPSIMD pass
14769 12:29:42.562586 arm64_syscall-abi_getpid_SVE_VL_256 pass
14770 12:29:42.563011 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14771 12:29:42.563099 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14772 12:29:42.563177 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14773 12:29:42.563254 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14774 12:29:42.563333 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14775 12:29:42.563596 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14776 12:29:42.563865 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14777 12:29:42.563949 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14778 12:29:42.564027 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14779 12:29:42.564103 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14780 12:29:42.564196 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14781 12:29:42.564277 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14782 12:29:42.564359 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14783 12:29:42.564436 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14784 12:29:42.569874 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14785 12:29:42.570091 arm64_syscall-abi_getpid_SVE_VL_240 pass
14786 12:29:42.570175 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14787 12:29:42.570254 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14788 12:29:42.570331 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14789 12:29:42.570407 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14790 12:29:42.570484 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14791 12:29:42.570559 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14792 12:29:42.570635 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14793 12:29:42.570713 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14794 12:29:42.571004 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14795 12:29:42.571102 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14796 12:29:42.571181 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14797 12:29:42.571258 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14798 12:29:42.571334 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14799 12:29:42.571408 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14800 12:29:42.571482 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14801 12:29:42.571556 arm64_syscall-abi_getpid_SVE_VL_224 pass
14802 12:29:42.571630 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14803 12:29:42.571720 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14804 12:29:42.571798 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14805 12:29:42.571888 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14806 12:29:42.571966 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14807 12:29:42.572041 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14808 12:29:42.572115 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14809 12:29:42.572189 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14810 12:29:42.572280 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14811 12:29:42.576610 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14812 12:29:42.577755 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14813 12:29:42.577864 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14814 12:29:42.577944 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14815 12:29:42.578026 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14816 12:29:42.578102 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14817 12:29:42.578178 arm64_syscall-abi_getpid_SVE_VL_208 pass
14818 12:29:42.578253 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14819 12:29:42.578329 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14820 12:29:42.578406 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14821 12:29:42.578482 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14822 12:29:42.578755 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14823 12:29:42.578838 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14824 12:29:42.578914 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14825 12:29:42.578990 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14826 12:29:42.579065 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14827 12:29:42.579141 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14828 12:29:42.579217 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14829 12:29:42.579309 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14830 12:29:42.579395 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14831 12:29:42.579473 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14832 12:29:42.579566 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14833 12:29:42.579644 arm64_syscall-abi_getpid_SVE_VL_192 pass
14834 12:29:42.579725 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14835 12:29:42.579804 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14836 12:29:42.579899 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14837 12:29:42.579976 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14838 12:29:42.580065 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14839 12:29:42.584866 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14840 12:29:42.585303 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14841 12:29:42.585444 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14842 12:29:42.585719 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14843 12:29:42.586048 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14844 12:29:42.586155 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14845 12:29:42.586245 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14846 12:29:42.586325 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14847 12:29:42.586490 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14848 12:29:42.586733 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14849 12:29:42.586816 arm64_syscall-abi_getpid_SVE_VL_176 pass
14850 12:29:42.586915 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14851 12:29:42.586996 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14852 12:29:42.587073 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14853 12:29:42.587151 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14854 12:29:42.587230 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14855 12:29:42.587326 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14856 12:29:42.587411 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14857 12:29:42.587505 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14858 12:29:42.587585 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14859 12:29:42.592806 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14860 12:29:42.607599 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14861 12:29:42.607821 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14862 12:29:42.607938 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14863 12:29:42.608034 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14864 12:29:42.608798 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14865 12:29:42.608933 arm64_syscall-abi_getpid_SVE_VL_160 pass
14866 12:29:42.609031 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14867 12:29:42.609142 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14868 12:29:42.609236 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14869 12:29:42.609610 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14870 12:29:42.609763 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14871 12:29:42.609910 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14872 12:29:42.610082 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14873 12:29:42.610227 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14874 12:29:42.610367 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14875 12:29:42.610490 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14876 12:29:42.610583 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14877 12:29:42.610675 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14878 12:29:42.610782 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14879 12:29:42.610892 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14880 12:29:42.610999 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14881 12:29:42.611109 arm64_syscall-abi_getpid_SVE_VL_144 pass
14882 12:29:42.611454 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14883 12:29:42.611565 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14884 12:29:42.611673 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14885 12:29:42.611771 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14886 12:29:42.612065 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14887 12:29:42.616188 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14888 12:29:42.616530 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14889 12:29:42.616641 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14890 12:29:42.616752 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14891 12:29:42.616860 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14892 12:29:42.616968 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14893 12:29:42.617276 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14894 12:29:42.617389 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14895 12:29:42.617497 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14896 12:29:42.617603 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14897 12:29:42.617734 arm64_syscall-abi_getpid_SVE_VL_128 pass
14898 12:29:42.618164 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14899 12:29:42.618275 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14900 12:29:42.618380 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14901 12:29:42.618485 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14902 12:29:42.618589 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14903 12:29:42.618692 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14904 12:29:42.618996 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14905 12:29:42.619118 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14906 12:29:42.619208 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14907 12:29:42.619318 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14908 12:29:42.619428 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14909 12:29:42.619538 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14910 12:29:42.619648 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14911 12:29:42.619960 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14912 12:29:42.620071 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14913 12:29:42.624365 arm64_syscall-abi_getpid_SVE_VL_112 pass
14914 12:29:42.624719 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14915 12:29:42.624831 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14916 12:29:42.624928 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14917 12:29:42.625214 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14918 12:29:42.625314 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14919 12:29:42.625410 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14920 12:29:42.625505 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14921 12:29:42.625599 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14922 12:29:42.625702 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14923 12:29:42.625816 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14924 12:29:42.625913 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14925 12:29:42.626008 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14926 12:29:42.626102 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14927 12:29:42.626196 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14928 12:29:42.626291 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14929 12:29:42.626388 arm64_syscall-abi_getpid_SVE_VL_96 pass
14930 12:29:42.626504 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14931 12:29:42.626601 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14932 12:29:42.626695 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14933 12:29:42.626790 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14934 12:29:42.626884 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14935 12:29:42.626996 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14936 12:29:42.627093 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14937 12:29:42.627203 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14938 12:29:42.627299 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14939 12:29:42.627397 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14940 12:29:42.627508 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14941 12:29:42.627606 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14942 12:29:42.628068 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14943 12:29:42.628171 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14944 12:29:42.628267 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14945 12:29:42.628367 arm64_syscall-abi_getpid_SVE_VL_80 pass
14946 12:29:42.633237 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14947 12:29:42.633392 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14948 12:29:42.633488 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14949 12:29:42.633580 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14950 12:29:42.633681 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14951 12:29:42.633774 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14952 12:29:42.633865 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14953 12:29:42.633956 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14954 12:29:42.634363 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14955 12:29:42.634561 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14956 12:29:42.634653 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14957 12:29:42.634739 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14958 12:29:42.634848 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14959 12:29:42.634952 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14960 12:29:42.635037 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14961 12:29:42.635139 arm64_syscall-abi_getpid_SVE_VL_64 pass
14962 12:29:42.635226 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14963 12:29:42.635309 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14964 12:29:42.635398 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14965 12:29:42.635480 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14966 12:29:42.637792 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14967 12:29:42.637992 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14968 12:29:42.638092 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14969 12:29:42.638183 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14970 12:29:42.638273 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14971 12:29:42.638362 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14972 12:29:42.638452 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14973 12:29:42.641958 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14974 12:29:42.642114 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14975 12:29:42.642215 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14976 12:29:42.642313 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14977 12:29:42.642415 arm64_syscall-abi_getpid_SVE_VL_48 pass
14978 12:29:42.642510 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14979 12:29:42.642606 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14980 12:29:42.642701 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14981 12:29:42.642796 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14982 12:29:42.642892 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14983 12:29:42.642987 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14984 12:29:42.643082 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14985 12:29:42.643178 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14986 12:29:42.643273 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14987 12:29:42.643367 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14988 12:29:42.643679 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14989 12:29:42.643794 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14990 12:29:42.643891 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14991 12:29:42.643987 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14992 12:29:42.644083 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14993 12:29:42.644178 arm64_syscall-abi_getpid_SVE_VL_32 pass
14994 12:29:42.644272 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14995 12:29:42.644369 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14996 12:29:42.644466 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14997 12:29:42.644561 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14998 12:29:42.644661 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14999 12:29:42.644758 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
15000 12:29:42.644854 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
15001 12:29:42.644967 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
15002 12:29:42.645064 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
15003 12:29:42.645159 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
15004 12:29:42.648323 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
15005 12:29:42.648448 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
15006 12:29:42.648767 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
15007 12:29:42.648885 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
15008 12:29:42.649013 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
15009 12:29:42.649110 arm64_syscall-abi_getpid_SVE_VL_16 pass
15010 12:29:42.649237 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
15011 12:29:42.649367 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
15012 12:29:42.662097 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
15013 12:29:42.662482 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
15014 12:29:42.662770 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
15015 12:29:42.662854 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
15016 12:29:42.662953 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
15017 12:29:42.663043 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
15018 12:29:42.663137 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
15019 12:29:42.663209 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
15020 12:29:42.663492 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
15021 12:29:42.663681 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
15022 12:29:42.663896 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
15023 12:29:42.664003 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
15024 12:29:42.664125 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
15025 12:29:42.664264 arm64_syscall-abi_sched_yield_FPSIMD pass
15026 12:29:42.664384 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
15027 12:29:42.664498 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
15028 12:29:42.664599 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
15029 12:29:42.664699 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
15030 12:29:42.664815 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
15031 12:29:42.664912 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
15032 12:29:42.665010 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
15033 12:29:42.665107 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
15034 12:29:42.665223 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
15035 12:29:42.665338 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
15036 12:29:42.665441 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
15037 12:29:42.665569 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
15038 12:29:42.665710 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
15039 12:29:42.665829 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
15040 12:29:42.665927 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
15041 12:29:42.666039 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
15042 12:29:42.666138 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
15043 12:29:42.666252 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
15044 12:29:42.666378 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
15045 12:29:42.666497 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
15046 12:29:42.666784 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
15047 12:29:42.666883 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
15048 12:29:42.666974 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
15049 12:29:42.667249 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
15050 12:29:42.667344 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
15051 12:29:42.667436 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
15052 12:29:42.667516 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
15053 12:29:42.667784 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
15054 12:29:42.667864 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
15055 12:29:42.667954 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
15056 12:29:42.673743 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
15057 12:29:42.673857 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
15058 12:29:42.673941 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
15059 12:29:42.674021 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
15060 12:29:42.674099 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
15061 12:29:42.674177 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
15062 12:29:42.674254 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
15063 12:29:42.674330 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
15064 12:29:42.674406 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
15065 12:29:42.674486 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
15066 12:29:42.674564 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
15067 12:29:42.674836 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
15068 12:29:42.674944 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
15069 12:29:42.675037 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
15070 12:29:42.675127 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
15071 12:29:42.675214 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
15072 12:29:42.675299 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
15073 12:29:42.675385 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15074 12:29:42.675473 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15075 12:29:42.675578 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15076 12:29:42.675667 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15077 12:29:42.675752 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15078 12:29:42.675839 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15079 12:29:42.675946 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15080 12:29:42.676038 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15081 12:29:42.676129 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15082 12:29:42.680133 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15083 12:29:42.680474 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15084 12:29:42.680636 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15085 12:29:42.680730 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15086 12:29:42.680824 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15087 12:29:42.681113 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15088 12:29:42.681231 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15089 12:29:42.681328 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15090 12:29:42.681424 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15091 12:29:42.681697 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15092 12:29:42.681813 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15093 12:29:42.681910 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15094 12:29:42.682000 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15095 12:29:42.682284 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15096 12:29:42.682387 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15097 12:29:42.682482 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15098 12:29:42.682577 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15099 12:29:42.682872 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15100 12:29:42.683163 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15101 12:29:42.683250 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15102 12:29:42.683344 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15103 12:29:42.683426 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15104 12:29:42.683521 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15105 12:29:42.683807 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15106 12:29:42.683913 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15107 12:29:42.683996 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15108 12:29:42.684092 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15109 12:29:42.688188 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15110 12:29:42.688552 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15111 12:29:42.688663 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15112 12:29:42.688748 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15113 12:29:42.688850 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15114 12:29:42.688985 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15115 12:29:42.689102 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15116 12:29:42.689200 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15117 12:29:42.689294 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15118 12:29:42.689694 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15119 12:29:42.689800 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15120 12:29:42.689958 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15121 12:29:42.690077 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15122 12:29:42.690176 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15123 12:29:42.690303 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15124 12:29:42.690441 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15125 12:29:42.690740 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15126 12:29:42.690836 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15127 12:29:42.690944 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15128 12:29:42.691047 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15129 12:29:42.691152 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15130 12:29:42.691226 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15131 12:29:42.691561 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15132 12:29:42.691673 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15133 12:29:42.691794 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15134 12:29:42.692080 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15135 12:29:42.692153 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15136 12:29:42.696648 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15137 12:29:42.696773 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15138 12:29:42.696904 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15139 12:29:42.697490 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15140 12:29:42.697678 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15141 12:29:42.697788 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15142 12:29:42.697894 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15143 12:29:42.698019 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15144 12:29:42.698120 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15145 12:29:42.698222 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15146 12:29:42.698308 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15147 12:29:42.698415 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15148 12:29:42.698502 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15149 12:29:42.698586 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15150 12:29:42.698682 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15151 12:29:42.698748 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15152 12:29:42.714976 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15153 12:29:42.715314 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15154 12:29:42.715403 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15155 12:29:42.715512 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15156 12:29:42.715587 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15157 12:29:42.715979 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15158 12:29:42.716084 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15159 12:29:42.716162 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15160 12:29:42.716262 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15161 12:29:42.716541 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15162 12:29:42.716628 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15163 12:29:42.716697 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15164 12:29:42.716963 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15165 12:29:42.717078 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15166 12:29:42.717190 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15167 12:29:42.717298 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15168 12:29:42.717386 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15169 12:29:42.717467 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15170 12:29:42.717539 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15171 12:29:42.717643 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15172 12:29:42.717799 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15173 12:29:42.717936 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15174 12:29:42.718244 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15175 12:29:42.718549 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15176 12:29:42.718642 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15177 12:29:42.718735 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15178 12:29:42.719557 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15179 12:29:42.719655 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15180 12:29:42.719745 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15181 12:29:42.719821 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15182 12:29:42.719904 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15183 12:29:42.719994 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15184 12:29:42.720069 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15185 12:29:42.720335 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15186 12:29:42.720422 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15187 12:29:42.720494 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15188 12:29:42.724516 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15189 12:29:42.724631 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15190 12:29:42.724737 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15191 12:29:42.724829 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15192 12:29:42.724915 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15193 12:29:42.725202 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15194 12:29:42.725483 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15195 12:29:42.725565 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15196 12:29:42.725664 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15197 12:29:42.725757 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15198 12:29:42.725852 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15199 12:29:42.726139 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15200 12:29:42.726212 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15201 12:29:42.726277 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15202 12:29:42.726346 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15203 12:29:42.726410 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15204 12:29:42.726515 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15205 12:29:42.726618 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15206 12:29:42.727395 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15207 12:29:42.727493 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15208 12:29:42.727567 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15209 12:29:42.727680 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15210 12:29:42.727780 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15211 12:29:42.727879 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15212 12:29:42.727982 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15213 12:29:42.728069 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15214 12:29:42.728175 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15215 12:29:42.728278 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15216 12:29:42.728575 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15217 12:29:42.728695 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15218 12:29:42.728796 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15219 12:29:42.728897 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15220 12:29:42.728999 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15221 12:29:42.732161 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15222 12:29:42.732464 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15223 12:29:42.732558 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15224 12:29:42.732665 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15225 12:29:42.732772 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15226 12:29:42.733080 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15227 12:29:42.733170 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15228 12:29:42.733269 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15229 12:29:42.733366 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15230 12:29:42.733662 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15231 12:29:42.733780 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15232 12:29:42.733864 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15233 12:29:42.734031 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15234 12:29:42.734147 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15235 12:29:42.734733 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15236 12:29:42.734838 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15237 12:29:42.734917 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15238 12:29:42.735006 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15239 12:29:42.735083 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15240 12:29:42.735373 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15241 12:29:42.735482 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15242 12:29:42.735804 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15243 12:29:42.736140 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15244 12:29:42.736359 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15245 12:29:42.740180 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15246 12:29:42.740465 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15247 12:29:42.740556 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15248 12:29:42.740676 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15249 12:29:42.740770 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15250 12:29:42.740895 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15251 12:29:42.741341 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15252 12:29:42.741442 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15253 12:29:42.741523 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15254 12:29:42.741812 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15255 12:29:42.741914 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15256 12:29:42.742007 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15257 12:29:42.742200 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15258 12:29:42.742280 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15259 12:29:42.742545 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15260 12:29:42.742642 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15261 12:29:42.742741 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15262 12:29:42.743021 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15263 12:29:42.743156 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15264 12:29:42.743252 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15265 12:29:42.743341 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15266 12:29:42.743614 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15267 12:29:42.743736 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15268 12:29:42.743823 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15269 12:29:42.743918 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15270 12:29:42.749789 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15271 12:29:42.749896 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15272 12:29:42.749964 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15273 12:29:42.750025 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15274 12:29:42.750089 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15275 12:29:42.750150 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15276 12:29:42.750212 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15277 12:29:42.750273 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15278 12:29:42.750333 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15279 12:29:42.750393 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15280 12:29:42.750454 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15281 12:29:42.750515 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15282 12:29:42.750575 arm64_syscall-abi pass
15283 12:29:42.750635 arm64_tpidr2_default_value pass
15284 12:29:42.750700 arm64_tpidr2_write_read pass
15285 12:29:42.750764 arm64_tpidr2_write_sleep_read pass
15286 12:29:42.751009 arm64_tpidr2_write_fork_read pass
15287 12:29:42.751077 arm64_tpidr2_write_clone_read pass
15288 12:29:42.751139 arm64_tpidr2 pass
15289 12:29:42.769092 + ../../utils/send-to-lava.sh ./output/result.txt
15290 12:29:42.827463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15291 12:29:42.828708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15293 12:29:42.874926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15295 12:29:42.875547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15296 12:29:42.923246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15298 12:29:42.923852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15299 12:29:42.966626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15300 12:29:42.967297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15302 12:29:43.011230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15304 12:29:43.011749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15305 12:29:43.055408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15306 12:29:43.055990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15308 12:29:43.102294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15309 12:29:43.102766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15311 12:29:43.146266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15312 12:29:43.146741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15314 12:29:43.189858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15315 12:29:43.190367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15317 12:29:43.229442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15318 12:29:43.229960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15320 12:29:43.281945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15322 12:29:43.282416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15323 12:29:43.313837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15324 12:29:43.314264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15326 12:29:43.350346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15327 12:29:43.350768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15329 12:29:43.385392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15331 12:29:43.386022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15332 12:29:43.423297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15334 12:29:43.423975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15335 12:29:43.463160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15336 12:29:43.463566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15338 12:29:43.500795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15339 12:29:43.501220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15341 12:29:43.532907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15342 12:29:43.533334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15344 12:29:43.573305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15345 12:29:43.573690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15347 12:29:43.611899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15348 12:29:43.612351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15350 12:29:43.655229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15352 12:29:43.657909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15353 12:29:43.706547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15354 12:29:43.707010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15356 12:29:43.758962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15357 12:29:43.759415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15359 12:29:43.793754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15360 12:29:43.797741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15362 12:29:43.830244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15363 12:29:43.830679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15365 12:29:43.866247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15366 12:29:43.866733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15368 12:29:43.898788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15369 12:29:43.899287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15371 12:29:43.930389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15372 12:29:43.930877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15374 12:29:43.962899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15375 12:29:43.963319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15377 12:29:43.994945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15378 12:29:43.995383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15380 12:29:44.027776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15382 12:29:44.028260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15383 12:29:44.059687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15385 12:29:44.060148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15386 12:29:44.091877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15388 12:29:44.092341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15389 12:29:44.123527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15390 12:29:44.123909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15392 12:29:44.155507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15393 12:29:44.156019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15395 12:29:44.187763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15396 12:29:44.188242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15398 12:29:44.219868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15399 12:29:44.220360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15401 12:29:44.252588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15402 12:29:44.253011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15404 12:29:44.285153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15406 12:29:44.285596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15407 12:29:44.317193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15408 12:29:44.317591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15410 12:29:44.349485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15411 12:29:44.349932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15413 12:29:44.381450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15414 12:29:44.381942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15416 12:29:44.413881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15417 12:29:44.414326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15419 12:29:44.446765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15421 12:29:44.447216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15422 12:29:44.479000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15424 12:29:44.479573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15425 12:29:44.512655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15426 12:29:44.513082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15428 12:29:44.546331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15430 12:29:44.547041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15431 12:29:44.578339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15433 12:29:44.578961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15434 12:29:44.611361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15435 12:29:44.611883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15437 12:29:44.645237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15438 12:29:44.645691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15440 12:29:44.678536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15441 12:29:44.678945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15443 12:29:44.717053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15444 12:29:44.717549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15446 12:29:44.749570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15447 12:29:44.750075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15449 12:29:44.782016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15450 12:29:44.782504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15452 12:29:44.815026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15453 12:29:44.815484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15455 12:29:44.847943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15457 12:29:44.848423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15458 12:29:44.880804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15459 12:29:44.881234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15461 12:29:44.913078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15462 12:29:44.913524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15464 12:29:44.948760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15465 12:29:44.949218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15467 12:29:44.983639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15468 12:29:44.984070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15470 12:29:45.016374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15472 12:29:45.016860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15473 12:29:45.049426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15474 12:29:45.049884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15476 12:29:45.082868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15477 12:29:45.083309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15479 12:29:45.117719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15480 12:29:45.118221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15482 12:29:45.158128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15483 12:29:45.158569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15485 12:29:45.191653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15486 12:29:45.192108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15488 12:29:45.226110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15489 12:29:45.226542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15491 12:29:45.258743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15493 12:29:45.259179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15494 12:29:45.291289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15495 12:29:45.291709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15497 12:29:45.326963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15498 12:29:45.327367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15500 12:29:45.361602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15501 12:29:45.362033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15503 12:29:45.393920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15504 12:29:45.394368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15506 12:29:45.427311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15508 12:29:45.427959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15509 12:29:45.460229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15511 12:29:45.460882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15512 12:29:45.494450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15513 12:29:45.494976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15515 12:29:45.528040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15517 12:29:45.528649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15518 12:29:45.561248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15519 12:29:45.561690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15521 12:29:45.597407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15522 12:29:45.597820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15524 12:29:45.631214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15526 12:29:45.631845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15527 12:29:45.664999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15528 12:29:45.665430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15530 12:29:45.697966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15532 12:29:45.698444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15533 12:29:45.731003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15534 12:29:45.731447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15536 12:29:45.765062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15537 12:29:45.765497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15539 12:29:45.798083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15540 12:29:45.798518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15542 12:29:45.831468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15543 12:29:45.831880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15545 12:29:45.863839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15547 12:29:45.864274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15548 12:29:45.896409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15550 12:29:45.896820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15551 12:29:45.929124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15552 12:29:45.929548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15554 12:29:45.961711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15555 12:29:45.962145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15557 12:29:45.994618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15558 12:29:45.995064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15560 12:29:46.030696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15561 12:29:46.031121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15563 12:29:46.065412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15564 12:29:46.065865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15566 12:29:46.101595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15567 12:29:46.102034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15569 12:29:46.135164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15571 12:29:46.135541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15572 12:29:46.169763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15573 12:29:46.170262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15575 12:29:46.198778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15576 12:29:46.199230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15578 12:29:46.231662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15580 12:29:46.232041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15581 12:29:46.264839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15583 12:29:46.265322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15584 12:29:46.297630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15586 12:29:46.298277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15587 12:29:46.330599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15589 12:29:46.331052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15590 12:29:46.367823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15592 12:29:46.368447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15593 12:29:46.405744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15594 12:29:46.406240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15596 12:29:46.439018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15597 12:29:46.439438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15599 12:29:46.473215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15600 12:29:46.473643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15602 12:29:46.504772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15603 12:29:46.505153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15605 12:29:46.537323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15607 12:29:46.537994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15608 12:29:46.569706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15610 12:29:46.570176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15611 12:29:46.601673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15612 12:29:46.602171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15614 12:29:46.634059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15616 12:29:46.634680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15617 12:29:46.666218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15618 12:29:46.666633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15620 12:29:46.699072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15622 12:29:46.699508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15623 12:29:46.730511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15625 12:29:46.730964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15626 12:29:46.761484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15628 12:29:46.761938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15629 12:29:46.793749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15630 12:29:46.794180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15632 12:29:46.826349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15633 12:29:46.826781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15635 12:29:46.858832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15636 12:29:46.859252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15638 12:29:46.890726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15639 12:29:46.891191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15641 12:29:46.922802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15642 12:29:46.923275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15644 12:29:46.955634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15646 12:29:46.956214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15647 12:29:46.987731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15648 12:29:46.988182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15650 12:29:47.021989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15651 12:29:47.022326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15653 12:29:47.054463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15655 12:29:47.055036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15656 12:29:47.087139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15658 12:29:47.087731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15659 12:29:47.118530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15660 12:29:47.119016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15662 12:29:47.151176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15664 12:29:47.151751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15665 12:29:47.183174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15666 12:29:47.183637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15668 12:29:47.215126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15669 12:29:47.215536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15671 12:29:47.247283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15673 12:29:47.247720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15674 12:29:47.278809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15675 12:29:47.279198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15677 12:29:47.316361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15679 12:29:47.316821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15680 12:29:47.353076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15682 12:29:47.353523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15683 12:29:47.386211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15684 12:29:47.386650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15686 12:29:47.421450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15688 12:29:47.421918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15689 12:29:47.458027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15690 12:29:47.458433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15692 12:29:47.498528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15693 12:29:47.498938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15695 12:29:47.530943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15696 12:29:47.531416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15698 12:29:47.563157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15699 12:29:47.563609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15701 12:29:47.595028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15702 12:29:47.595493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15704 12:29:47.627200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15705 12:29:47.627615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15707 12:29:47.659514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15708 12:29:47.659927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15710 12:29:47.692749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15711 12:29:47.693140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15713 12:29:47.725458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15714 12:29:47.725862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15716 12:29:47.757287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15717 12:29:47.757776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15719 12:29:47.789086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15720 12:29:47.789592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15722 12:29:47.822123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15723 12:29:47.822597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15725 12:29:47.854848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15726 12:29:47.855279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15728 12:29:47.889937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15730 12:29:47.890438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15731 12:29:47.921583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15732 12:29:47.922055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15734 12:29:47.953803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15736 12:29:47.954251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15737 12:29:47.985562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15738 12:29:47.985979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15740 12:29:48.018478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15742 12:29:48.018942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15743 12:29:48.051354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15745 12:29:48.051959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15746 12:29:48.085234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15747 12:29:48.085702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15749 12:29:48.117254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15750 12:29:48.117710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15752 12:29:48.149780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15754 12:29:48.150340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15755 12:29:48.181149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15756 12:29:48.181607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15758 12:29:48.212915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15759 12:29:48.213360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15761 12:29:48.245452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15762 12:29:48.245905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15764 12:29:48.277193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15766 12:29:48.277809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15767 12:29:48.308082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15769 12:29:48.308740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15770 12:29:48.339381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15771 12:29:48.339822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15773 12:29:48.370388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15775 12:29:48.370867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15776 12:29:48.403238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15777 12:29:48.403693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15779 12:29:48.434397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15780 12:29:48.434846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15782 12:29:48.465721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15783 12:29:48.466205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15785 12:29:48.497463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15786 12:29:48.497950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15788 12:29:48.528966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15790 12:29:48.529528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15791 12:29:48.560825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15793 12:29:48.561397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15794 12:29:48.594930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15796 12:29:48.595486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15797 12:29:48.626094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15798 12:29:48.626564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15800 12:29:48.658965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15801 12:29:48.659404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15803 12:29:48.693096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15804 12:29:48.693528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15806 12:29:48.725853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15807 12:29:48.726304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15809 12:29:48.763328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15810 12:29:48.763760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15812 12:29:48.801182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15813 12:29:48.801622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15815 12:29:48.839006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15816 12:29:48.839420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15818 12:29:48.878634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15820 12:29:48.879008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15821 12:29:48.914988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15822 12:29:48.915384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15824 12:29:48.947617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15825 12:29:48.948063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15827 12:29:48.978991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15828 12:29:48.979488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15830 12:29:49.010755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15832 12:29:49.011328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15833 12:29:49.041696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15834 12:29:49.042119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15836 12:29:49.073598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15837 12:29:49.074025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15839 12:29:49.105199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15840 12:29:49.105689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15842 12:29:49.143512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15843 12:29:49.143979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15845 12:29:49.174759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15846 12:29:49.175184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15848 12:29:49.206563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15850 12:29:49.207011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15851 12:29:49.237928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15853 12:29:49.238398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15854 12:29:49.269504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15856 12:29:49.270074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15857 12:29:49.305600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15859 12:29:49.306176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15860 12:29:49.338049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15862 12:29:49.338616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15863 12:29:49.369626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15864 12:29:49.370120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15866 12:29:49.401481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15867 12:29:49.401936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15869 12:29:49.435546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15870 12:29:49.435994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15872 12:29:49.467884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15873 12:29:49.468313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15875 12:29:49.504966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15876 12:29:49.505440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15878 12:29:49.537619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15879 12:29:49.538068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15881 12:29:49.569021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15883 12:29:49.569487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15884 12:29:49.599810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15885 12:29:49.600292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15887 12:29:49.632215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15889 12:29:49.632981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15890 12:29:49.670639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15891 12:29:49.671079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15893 12:29:49.703113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15894 12:29:49.703529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15896 12:29:49.737307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15897 12:29:49.737673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15899 12:29:49.769188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15900 12:29:49.769691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15902 12:29:49.801713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15904 12:29:49.802406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15905 12:29:49.838798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15906 12:29:49.839161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15908 12:29:49.874253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15909 12:29:49.874649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15911 12:29:49.905766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15912 12:29:49.906142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15914 12:29:49.937320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15915 12:29:49.937693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15917 12:29:49.972451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15919 12:29:49.972850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15920 12:29:50.007055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15922 12:29:50.007519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15923 12:29:50.043282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15925 12:29:50.045798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15926 12:29:50.075965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15927 12:29:50.076384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15929 12:29:50.108843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15930 12:29:50.109233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15932 12:29:50.141132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15934 12:29:50.141505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15935 12:29:50.173538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15936 12:29:50.174025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15938 12:29:50.206759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15939 12:29:50.207167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15941 12:29:50.239293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15942 12:29:50.239707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15944 12:29:50.272999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15945 12:29:50.273388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15947 12:29:50.304537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15948 12:29:50.304962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15950 12:29:50.337149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15951 12:29:50.337561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15953 12:29:50.369419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15954 12:29:50.369861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15956 12:29:50.402573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15958 12:29:50.403039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15959 12:29:50.434525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15960 12:29:50.434956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15962 12:29:50.467007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15963 12:29:50.467494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15965 12:29:50.499176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15966 12:29:50.499589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15968 12:29:50.531612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15969 12:29:50.532031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15971 12:29:50.563790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15973 12:29:50.564400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15974 12:29:50.597113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15975 12:29:50.597550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15977 12:29:50.629106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15978 12:29:50.629542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15980 12:29:50.661632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15981 12:29:50.662056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15983 12:29:50.693435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15985 12:29:50.693888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15986 12:29:50.725255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15988 12:29:50.725707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15989 12:29:50.761363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15991 12:29:50.761797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15992 12:29:50.795077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15993 12:29:50.795562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15995 12:29:50.830181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15996 12:29:50.830624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15998 12:29:50.865662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15999 12:29:50.866080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
16001 12:29:50.901422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
16002 12:29:50.901841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
16004 12:29:50.934004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
16006 12:29:50.934454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
16007 12:29:50.966123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
16009 12:29:50.966570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
16010 12:29:50.997672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
16011 12:29:50.998204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
16013 12:29:51.029535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
16015 12:29:51.030115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
16016 12:29:51.061491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
16017 12:29:51.061983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
16019 12:29:51.093429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
16021 12:29:51.094037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
16022 12:29:51.125542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
16024 12:29:51.126143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
16025 12:29:51.157217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
16026 12:29:51.157702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
16028 12:29:51.188373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
16030 12:29:51.188953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
16031 12:29:51.219705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
16033 12:29:51.220257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
16034 12:29:51.251454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
16036 12:29:51.252051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
16037 12:29:51.283090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
16038 12:29:51.283545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
16040 12:29:51.317561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
16042 12:29:51.318185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
16043 12:29:51.349316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
16044 12:29:51.349747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
16046 12:29:51.381612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
16047 12:29:51.382038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
16049 12:29:51.413560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
16051 12:29:51.414042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
16052 12:29:51.446037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
16054 12:29:51.446495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
16055 12:29:51.479133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
16056 12:29:51.479579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
16058 12:29:51.511255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
16059 12:29:51.511707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
16061 12:29:51.543289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
16063 12:29:51.543769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
16064 12:29:51.574749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
16065 12:29:51.575155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
16067 12:29:51.605831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
16068 12:29:51.606326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
16070 12:29:51.637607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
16071 12:29:51.638130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
16073 12:29:51.670129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16075 12:29:51.670783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16076 12:29:51.701551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16078 12:29:51.702207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16079 12:29:51.733124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16080 12:29:51.733609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16082 12:29:51.764734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16083 12:29:51.765144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16085 12:29:51.796035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16086 12:29:51.796450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16088 12:29:51.829719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16089 12:29:51.830178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16091 12:29:51.862212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16093 12:29:51.862804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16094 12:29:51.894055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16095 12:29:51.894495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16097 12:29:51.926156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16098 12:29:51.926589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16100 12:29:51.957520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16101 12:29:51.957971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16103 12:29:51.988342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16105 12:29:51.989027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16106 12:29:52.021405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16107 12:29:52.021823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16109 12:29:52.052751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16110 12:29:52.053199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16112 12:29:52.085356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16114 12:29:52.085810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16115 12:29:52.117176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16117 12:29:52.117659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16118 12:29:52.148013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16119 12:29:52.148499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16121 12:29:52.179752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16122 12:29:52.180194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16124 12:29:52.212889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16125 12:29:52.213385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16127 12:29:52.244745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16128 12:29:52.245298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16130 12:29:52.275523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16131 12:29:52.275957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16133 12:29:52.307778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16135 12:29:52.308481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16136 12:29:52.340291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16138 12:29:52.340762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16139 12:29:52.373425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16140 12:29:52.374021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16142 12:29:52.405823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16143 12:29:52.406332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16145 12:29:52.438695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16146 12:29:52.439135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16148 12:29:52.470739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16149 12:29:52.471198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16151 12:29:52.502751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16153 12:29:52.503318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16154 12:29:52.541184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16156 12:29:52.541980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16157 12:29:52.577274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16158 12:29:52.577764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16160 12:29:52.609904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16162 12:29:52.610386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16163 12:29:52.641618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16165 12:29:52.642088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16166 12:29:52.674148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16168 12:29:52.674740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16169 12:29:52.707520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16170 12:29:52.708022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16172 12:29:52.741220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16173 12:29:52.741708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16175 12:29:52.772959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16176 12:29:52.773444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16178 12:29:52.804776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16179 12:29:52.805262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16181 12:29:52.836599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16182 12:29:52.837078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16184 12:29:52.869072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16185 12:29:52.869488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16187 12:29:52.901270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16189 12:29:52.901889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16190 12:29:52.933613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16192 12:29:52.934196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16193 12:29:52.965034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16195 12:29:52.965663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16196 12:29:52.996101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16198 12:29:52.996540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16199 12:29:53.033399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16201 12:29:53.034061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16202 12:29:53.078344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16204 12:29:53.078935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16205 12:29:53.123383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16206 12:29:53.123842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16208 12:29:53.165418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16209 12:29:53.165855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16211 12:29:53.199055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16212 12:29:53.199453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16214 12:29:53.231841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16216 12:29:53.232329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16217 12:29:53.268037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16218 12:29:53.268541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16220 12:29:53.313408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16222 12:29:53.314204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16223 12:29:53.357968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16225 12:29:53.358339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16226 12:29:53.406042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16227 12:29:53.406459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16229 12:29:53.438690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16230 12:29:53.439238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16232 12:29:53.472593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16234 12:29:53.473175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16235 12:29:53.507420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16236 12:29:53.507861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16238 12:29:53.540917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16239 12:29:53.541301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16241 12:29:53.574203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16242 12:29:53.574642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16244 12:29:53.606887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16246 12:29:53.607313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16247 12:29:53.640030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16248 12:29:53.640480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16250 12:29:53.675528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16251 12:29:53.676019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16253 12:29:53.712356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16255 12:29:53.712826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16256 12:29:53.758817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16258 12:29:53.759305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16259 12:29:53.793749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16260 12:29:53.794187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16262 12:29:53.829790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16263 12:29:53.830280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16265 12:29:53.861562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16267 12:29:53.862253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16268 12:29:53.893663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16270 12:29:53.894065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16271 12:29:53.925796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16272 12:29:53.926182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16274 12:29:53.958101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16275 12:29:53.958516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16277 12:29:53.994482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16279 12:29:53.994919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16280 12:29:54.027534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16281 12:29:54.027883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16283 12:29:54.060815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16285 12:29:54.061288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16286 12:29:54.092078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16287 12:29:54.092510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16289 12:29:54.123382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16290 12:29:54.123899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16292 12:29:54.155448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16294 12:29:54.156022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16295 12:29:54.190013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16296 12:29:54.190450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16298 12:29:54.224265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16300 12:29:54.224711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16301 12:29:54.258295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16302 12:29:54.258717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16304 12:29:54.292358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16306 12:29:54.292785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16307 12:29:54.326466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16308 12:29:54.326884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16310 12:29:54.361744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16311 12:29:54.362169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16313 12:29:54.396873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16315 12:29:54.397365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16316 12:29:54.430062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16317 12:29:54.430492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16319 12:29:54.463832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16320 12:29:54.464284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16322 12:29:54.499140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16323 12:29:54.499573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16325 12:29:54.537571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16327 12:29:54.538052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16328 12:29:54.572781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16329 12:29:54.573213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16331 12:29:54.609705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16333 12:29:54.610156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16334 12:29:54.646158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16336 12:29:54.646633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16337 12:29:54.685758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16338 12:29:54.686187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16340 12:29:54.721183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16342 12:29:54.721783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16343 12:29:54.755400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16344 12:29:54.755886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16346 12:29:54.787740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16347 12:29:54.788249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16349 12:29:54.820621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16350 12:29:54.821076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16352 12:29:54.852257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16354 12:29:54.852911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16355 12:29:54.885120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16356 12:29:54.885603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16358 12:29:54.918271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16359 12:29:54.918720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16361 12:29:54.953266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16362 12:29:54.953781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16364 12:29:54.987469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16366 12:29:54.988214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16367 12:29:55.022441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16368 12:29:55.022888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16370 12:29:55.057552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16371 12:29:55.057992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16373 12:29:55.092161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16375 12:29:55.092648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16376 12:29:55.129743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16377 12:29:55.130160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16379 12:29:55.161830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16380 12:29:55.162236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16382 12:29:55.193063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16383 12:29:55.193499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16385 12:29:55.227774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16386 12:29:55.228217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16388 12:29:55.266446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16389 12:29:55.266957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16391 12:29:55.303591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16392 12:29:55.304074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16394 12:29:55.341584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16396 12:29:55.342244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16397 12:29:55.379875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16398 12:29:55.380467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16400 12:29:55.419945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16401 12:29:55.420420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16403 12:29:55.459007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16404 12:29:55.459506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16406 12:29:55.495595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16408 12:29:55.496173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16409 12:29:55.531519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16410 12:29:55.531995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16412 12:29:55.567678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16413 12:29:55.568139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16415 12:29:55.609139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16417 12:29:55.609735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16418 12:29:55.648484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16420 12:29:55.648948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16421 12:29:55.685714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16423 12:29:55.686186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16424 12:29:55.722023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16425 12:29:55.722450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16427 12:29:55.759022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16428 12:29:55.759479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16430 12:29:55.802304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16431 12:29:55.802758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16433 12:29:55.838874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16435 12:29:55.839352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16436 12:29:55.875767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16438 12:29:55.876244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16439 12:29:55.913860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16440 12:29:55.914306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16442 12:29:55.953074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16444 12:29:55.953539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16445 12:29:55.991389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16446 12:29:55.991829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16448 12:29:56.027326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16449 12:29:56.027775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16451 12:29:56.062710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16452 12:29:56.063158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16454 12:29:56.098598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16455 12:29:56.099042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16457 12:29:56.134860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16458 12:29:56.135303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16460 12:29:56.175661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16462 12:29:56.176122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16463 12:29:56.213710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16465 12:29:56.214170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16466 12:29:56.249899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16468 12:29:56.250358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16469 12:29:56.286470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16470 12:29:56.286916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16472 12:29:56.325871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16473 12:29:56.326287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16475 12:29:56.364328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16477 12:29:56.364816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16478 12:29:56.405865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16479 12:29:56.406320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16481 12:29:56.442485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16482 12:29:56.442937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16484 12:29:56.481708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16485 12:29:56.482152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16487 12:29:56.521160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16488 12:29:56.521595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16490 12:29:56.559553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16491 12:29:56.559999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16493 12:29:56.598259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16494 12:29:56.598726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16496 12:29:56.637036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16498 12:29:56.637607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16499 12:29:56.675887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16501 12:29:56.676426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16502 12:29:56.717702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16503 12:29:56.718137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16505 12:29:56.757630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16506 12:29:56.758029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16508 12:29:56.796115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16509 12:29:56.796655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16511 12:29:56.834837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16513 12:29:56.835447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16514 12:29:56.874279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16515 12:29:56.874752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16517 12:29:56.913713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16518 12:29:56.914090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16520 12:29:56.952107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16522 12:29:56.952649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16523 12:29:56.991518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16524 12:29:56.991940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16526 12:29:57.031322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16528 12:29:57.031876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16529 12:29:57.071073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16530 12:29:57.071476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16532 12:29:57.109806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16533 12:29:57.110169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16535 12:29:57.146976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16537 12:29:57.147479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16538 12:29:57.184711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16539 12:29:57.185069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16541 12:29:57.223806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16543 12:29:57.224338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16544 12:29:57.261784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16545 12:29:57.262198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16547 12:29:57.299371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16548 12:29:57.299819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16550 12:29:57.338155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16551 12:29:57.338590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16553 12:29:57.377875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16555 12:29:57.378333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16556 12:29:57.417730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16558 12:29:57.418274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16559 12:29:57.457070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16560 12:29:57.457630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16562 12:29:57.496419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16564 12:29:57.497188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16565 12:29:57.535227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16566 12:29:57.535663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16568 12:29:57.575320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16569 12:29:57.575697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16571 12:29:57.614923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16573 12:29:57.615472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16574 12:29:57.653641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16575 12:29:57.654042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16577 12:29:57.693152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16578 12:29:57.693600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16580 12:29:57.731570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16581 12:29:57.731946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16583 12:29:57.771740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16584 12:29:57.772196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16586 12:29:57.810987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16587 12:29:57.811343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16589 12:29:57.850500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16591 12:29:57.851033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16592 12:29:57.889930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16593 12:29:57.890310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16595 12:29:57.931119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16596 12:29:57.931614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16598 12:29:57.981094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16599 12:29:57.981473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16601 12:29:58.033528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16602 12:29:58.034019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16604 12:29:58.077070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16605 12:29:58.077520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16607 12:29:58.112974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16609 12:29:58.113442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16610 12:29:58.148906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16612 12:29:58.149359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16613 12:29:58.184000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16614 12:29:58.184425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16616 12:29:58.219424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16617 12:29:58.219842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16619 12:29:58.255262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16621 12:29:58.255856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16622 12:29:58.290808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16624 12:29:58.291336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16625 12:29:58.325978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16626 12:29:58.326428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16628 12:29:58.360914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16629 12:29:58.361274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16631 12:29:58.395687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16633 12:29:58.396182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16634 12:29:58.429935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16635 12:29:58.430341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16637 12:29:58.466176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16639 12:29:58.466787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16640 12:29:58.502874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16641 12:29:58.503175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16643 12:29:58.539086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16644 12:29:58.539459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16646 12:29:58.574940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16648 12:29:58.575567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16649 12:29:58.610744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16651 12:29:58.611209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16652 12:29:58.649438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16654 12:29:58.650005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16655 12:29:58.685986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16657 12:29:58.686466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16658 12:29:58.725234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16660 12:29:58.725896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16661 12:29:58.762584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16662 12:29:58.763036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16664 12:29:58.798291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16665 12:29:58.798798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16667 12:29:58.837492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16669 12:29:58.837945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16670 12:29:58.873101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16671 12:29:58.873486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16673 12:29:58.907530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16674 12:29:58.907908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16676 12:29:58.942428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16677 12:29:58.942842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16679 12:29:58.978001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16681 12:29:58.978482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16682 12:29:59.020878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16683 12:29:59.021368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16685 12:29:59.057247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16686 12:29:59.057679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16688 12:29:59.092596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16689 12:29:59.093043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16691 12:29:59.129343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16693 12:29:59.129949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16694 12:29:59.165945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16695 12:29:59.166418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16697 12:29:59.207991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16699 12:29:59.208470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16700 12:29:59.243937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16701 12:29:59.244375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16703 12:29:59.279437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16704 12:29:59.279888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16706 12:29:59.314608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16707 12:29:59.315056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16709 12:29:59.350896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16711 12:29:59.351378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16712 12:29:59.389498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16714 12:29:59.389984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16715 12:29:59.424984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16716 12:29:59.425374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16718 12:29:59.459730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16720 12:29:59.460310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16721 12:29:59.495838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16722 12:29:59.496320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16724 12:29:59.531742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16725 12:29:59.532201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16727 12:29:59.568144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16729 12:29:59.568744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16730 12:29:59.602987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16732 12:29:59.603467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16733 12:29:59.638672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16735 12:29:59.639244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16736 12:29:59.674305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16737 12:29:59.674771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16739 12:29:59.710453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16740 12:29:59.710960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16742 12:29:59.749752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16743 12:29:59.750227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16745 12:29:59.785794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16747 12:29:59.786285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16748 12:29:59.821158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16750 12:29:59.821632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16751 12:29:59.856868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16752 12:29:59.857313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16754 12:29:59.893424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16755 12:29:59.893882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16757 12:29:59.929714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16759 12:29:59.930187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16760 12:29:59.964449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16762 12:29:59.965027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16763 12:30:00.000097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16765 12:30:00.000717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16766 12:30:00.034900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16768 12:30:00.035383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16769 12:30:00.069586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16770 12:30:00.070038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16772 12:30:00.105878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16773 12:30:00.106376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16775 12:30:00.141773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16777 12:30:00.142261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16778 12:30:00.177107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16780 12:30:00.177583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16781 12:30:00.212072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16783 12:30:00.212705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16784 12:30:00.248173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16786 12:30:00.248742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16787 12:30:00.284998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16789 12:30:00.285462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16790 12:30:00.320443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16792 12:30:00.320910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16793 12:30:00.357169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16794 12:30:00.357593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16796 12:30:00.394520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16797 12:30:00.394850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16799 12:30:00.430637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16801 12:30:00.431135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16802 12:30:00.469245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16803 12:30:00.469660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16805 12:30:00.505149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16806 12:30:00.505583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16808 12:30:00.540567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16809 12:30:00.540905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16811 12:30:00.575860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16813 12:30:00.576252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16814 12:30:00.612434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16816 12:30:00.612815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16817 12:30:00.651301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16818 12:30:00.651716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16820 12:30:00.687366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16821 12:30:00.687785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16823 12:30:00.726063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16824 12:30:00.726491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16826 12:30:00.762289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16827 12:30:00.762680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16829 12:30:00.803254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16830 12:30:00.803659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16832 12:30:00.841569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16833 12:30:00.842058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16835 12:30:00.876891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16836 12:30:00.877374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16838 12:30:00.912360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16840 12:30:00.912921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16841 12:30:00.946929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16842 12:30:00.947395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16844 12:30:00.985261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16845 12:30:00.985711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16847 12:30:01.022405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16849 12:30:01.023145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16850 12:30:01.057583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16851 12:30:01.058146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16853 12:30:01.093862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16854 12:30:01.094231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16856 12:30:01.129539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16858 12:30:01.130000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16859 12:30:01.165899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16861 12:30:01.166326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16862 12:30:01.201884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16863 12:30:01.202286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16865 12:30:01.238969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16866 12:30:01.239379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16868 12:30:01.274886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16869 12:30:01.275360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16871 12:30:01.310560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16872 12:30:01.310992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16874 12:30:01.350774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16875 12:30:01.351191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16877 12:30:01.388929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16878 12:30:01.389333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16880 12:30:01.425518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16881 12:30:01.425988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16883 12:30:01.462681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16885 12:30:01.463301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16886 12:30:01.500874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16888 12:30:01.501402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16889 12:30:01.541420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16890 12:30:01.541799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16892 12:30:01.578373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16893 12:30:01.578843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16895 12:30:01.613938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16896 12:30:01.614366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16898 12:30:01.668496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16900 12:30:01.668998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16901 12:30:01.709615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16902 12:30:01.709992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16904 12:30:01.746436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16906 12:30:01.746813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16907 12:30:01.783210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16908 12:30:01.783602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16910 12:30:01.819543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16911 12:30:01.819977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16913 12:30:01.858485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16914 12:30:01.858922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16916 12:30:01.896488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16918 12:30:01.897018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16919 12:30:01.934396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16920 12:30:01.934913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16922 12:30:01.972317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16924 12:30:01.972908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16925 12:30:02.015016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16926 12:30:02.015475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16928 12:30:02.054134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16929 12:30:02.054586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16931 12:30:02.089098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16933 12:30:02.089509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16934 12:30:02.123534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16936 12:30:02.124013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16937 12:30:02.157615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16938 12:30:02.158100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16940 12:30:02.192959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16942 12:30:02.193445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16943 12:30:02.229082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16945 12:30:02.229600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16946 12:30:02.276422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16948 12:30:02.276907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16949 12:30:02.316367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16951 12:30:02.316835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16952 12:30:02.359023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16954 12:30:02.359556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16955 12:30:02.404155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16956 12:30:02.404688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16958 12:30:02.451286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16959 12:30:02.451706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16961 12:30:02.507510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16962 12:30:02.507906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16964 12:30:02.546058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16965 12:30:02.546468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16967 12:30:02.580013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16968 12:30:02.580411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16970 12:30:02.615436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16971 12:30:02.615815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16973 12:30:02.648930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16974 12:30:02.649370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16976 12:30:02.681859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16977 12:30:02.682283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16979 12:30:02.716011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16981 12:30:02.716476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16982 12:30:02.749559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16983 12:30:02.750013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16985 12:30:02.786573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16987 12:30:02.787230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16988 12:30:02.820686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16989 12:30:02.821119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16991 12:30:02.857571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16992 12:30:02.858027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16994 12:30:02.902989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16995 12:30:02.903521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16997 12:30:02.938213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16998 12:30:02.938623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
17000 12:30:02.972908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
17001 12:30:02.973366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
17003 12:30:03.007527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
17005 12:30:03.008040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
17006 12:30:03.044204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
17008 12:30:03.044689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
17009 12:30:03.079811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
17011 12:30:03.080303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
17012 12:30:03.115321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
17014 12:30:03.115808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
17015 12:30:03.151762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
17016 12:30:03.152258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
17018 12:30:03.189044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
17019 12:30:03.189567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
17021 12:30:03.225440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
17022 12:30:03.225944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
17024 12:30:03.260570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
17026 12:30:03.261061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
17027 12:30:03.297723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
17028 12:30:03.298228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
17030 12:30:03.333989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
17032 12:30:03.334647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
17033 12:30:03.373565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
17034 12:30:03.374034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
17036 12:30:03.409443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
17038 12:30:03.409915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
17039 12:30:03.445115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
17041 12:30:03.445577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
17042 12:30:03.490931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
17044 12:30:03.491394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
17045 12:30:03.526033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
17046 12:30:03.526452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
17048 12:30:03.561695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
17049 12:30:03.562116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
17051 12:30:03.598557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
17052 12:30:03.599268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
17054 12:30:03.637552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
17055 12:30:03.638003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
17057 12:30:03.690554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
17058 12:30:03.691027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
17060 12:30:03.750544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
17061 12:30:03.751045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
17063 12:30:03.799250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
17064 12:30:03.799713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
17066 12:30:03.833886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
17067 12:30:03.834347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
17069 12:30:03.871319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
17070 12:30:03.871764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
17072 12:30:03.905918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17073 12:30:03.906347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17075 12:30:03.942994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17076 12:30:03.943376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17078 12:30:03.978433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17079 12:30:03.978806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17081 12:30:04.018250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17082 12:30:04.018626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17084 12:30:04.055162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17085 12:30:04.055598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17087 12:30:04.091889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17089 12:30:04.092397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17090 12:30:04.127571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17092 12:30:04.128040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17093 12:30:04.161781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17094 12:30:04.162210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17096 12:30:04.201044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17097 12:30:04.201491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17099 12:30:04.255195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17101 12:30:04.255678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17102 12:30:04.289999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17104 12:30:04.290501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17105 12:30:04.325312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17107 12:30:04.325820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17108 12:30:04.360152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17110 12:30:04.360632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17111 12:30:04.401560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17112 12:30:04.402092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17114 12:30:04.439073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17116 12:30:04.439470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17117 12:30:04.478884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17119 12:30:04.479358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17120 12:30:04.515505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17121 12:30:04.515973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17123 12:30:04.554477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17124 12:30:04.554925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17126 12:30:04.590692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17127 12:30:04.591125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17129 12:30:04.626310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17131 12:30:04.626789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17132 12:30:04.662485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17133 12:30:04.662924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17135 12:30:04.699313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17136 12:30:04.699781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17138 12:30:04.737921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17140 12:30:04.738409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17141 12:30:04.773787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17142 12:30:04.774178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17144 12:30:04.813560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17146 12:30:04.814071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17147 12:30:04.850819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17149 12:30:04.851287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17150 12:30:04.885653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17151 12:30:04.886078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17153 12:30:04.923283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17154 12:30:04.923712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17156 12:30:04.979502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17157 12:30:04.980019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17159 12:30:05.040300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17161 12:30:05.040985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17162 12:30:05.086903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17164 12:30:05.087371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17165 12:30:05.134168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17166 12:30:05.134601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17168 12:30:05.165926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17170 12:30:05.166403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17171 12:30:05.198124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17172 12:30:05.198578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17174 12:30:05.231200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17175 12:30:05.231647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17177 12:30:05.265188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17178 12:30:05.265595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17180 12:30:05.298604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17181 12:30:05.299037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17183 12:30:05.330949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17184 12:30:05.331369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17186 12:30:05.365324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17187 12:30:05.365805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17189 12:30:05.403151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17190 12:30:05.403574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17192 12:30:05.437211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17193 12:30:05.437629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17195 12:30:05.473315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17197 12:30:05.473916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17198 12:30:05.507730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17199 12:30:05.508209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17201 12:30:05.541955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17202 12:30:05.542421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17204 12:30:05.574765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17205 12:30:05.575288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17207 12:30:05.612901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17208 12:30:05.613395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17210 12:30:05.650053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17211 12:30:05.650519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17213 12:30:05.688878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17214 12:30:05.689326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17216 12:30:05.726114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17218 12:30:05.726612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17219 12:30:05.766079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17220 12:30:05.766441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17222 12:30:05.801530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17223 12:30:05.802125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17225 12:30:05.838302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17227 12:30:05.838760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17228 12:30:05.877860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17229 12:30:05.878513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17231 12:30:05.914967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17233 12:30:05.915424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17234 12:30:05.950287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17235 12:30:05.950703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17237 12:30:05.988323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17239 12:30:05.988734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17240 12:30:06.026147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17242 12:30:06.026558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17243 12:30:06.062253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17244 12:30:06.062648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17246 12:30:06.096042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17248 12:30:06.096517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17249 12:30:06.128838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17250 12:30:06.129279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17252 12:30:06.161011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17253 12:30:06.161510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17255 12:30:06.193657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17257 12:30:06.194133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17258 12:30:06.227056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17259 12:30:06.227494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17261 12:30:06.263124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17262 12:30:06.263554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17264 12:30:06.297444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17265 12:30:06.297866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17267 12:30:06.332097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17269 12:30:06.332582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17270 12:30:06.365927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17271 12:30:06.366340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17273 12:30:06.399554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17274 12:30:06.400148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17276 12:30:06.433510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17277 12:30:06.434015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17279 12:30:06.465954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17280 12:30:06.466387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17282 12:30:06.502906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17283 12:30:06.503346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17285 12:30:06.536138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17287 12:30:06.536627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17288 12:30:06.573015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17289 12:30:06.573440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17291 12:30:06.606926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17292 12:30:06.607382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17294 12:30:06.639226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17295 12:30:06.639695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17297 12:30:06.672936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17299 12:30:06.673418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17300 12:30:06.707048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17301 12:30:06.707554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17303 12:30:06.741154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17304 12:30:06.741678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17306 12:30:06.775195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17307 12:30:06.775667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17309 12:30:06.827761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17310 12:30:06.828245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17312 12:30:06.878930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17314 12:30:06.879582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17315 12:30:06.929918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17317 12:30:06.930510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17318 12:30:06.978532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17319 12:30:06.978932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17321 12:30:07.026098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17323 12:30:07.026483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17324 12:30:07.058922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17325 12:30:07.059329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17327 12:30:07.093425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17329 12:30:07.093898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17330 12:30:07.128929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17331 12:30:07.129355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17333 12:30:07.165197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17335 12:30:07.165710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17336 12:30:07.202743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17337 12:30:07.203278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17339 12:30:07.241183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17340 12:30:07.241665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17342 12:30:07.279163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17343 12:30:07.279629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17345 12:30:07.314805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17347 12:30:07.315203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17348 12:30:07.347804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17349 12:30:07.348262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17351 12:30:07.383065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17352 12:30:07.383465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17354 12:30:07.418615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17355 12:30:07.419336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17357 12:30:07.455906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17358 12:30:07.456422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17360 12:30:07.495786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17361 12:30:07.496242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17363 12:30:07.531008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17364 12:30:07.531441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17366 12:30:07.562290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17367 12:30:07.562743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17369 12:30:07.594242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17371 12:30:07.594711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17372 12:30:07.631889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17373 12:30:07.632296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17375 12:30:07.666943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17377 12:30:07.667386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17378 12:30:07.700256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17380 12:30:07.701034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17381 12:30:07.738566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17382 12:30:07.738953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17384 12:30:07.773590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17385 12:30:07.774129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17387 12:30:07.808091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17389 12:30:07.808671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17390 12:30:07.844334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17392 12:30:07.844893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17393 12:30:07.876082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17394 12:30:07.876471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17396 12:30:07.909374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17397 12:30:07.909887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17399 12:30:07.943306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17400 12:30:07.943790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17402 12:30:07.977520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17403 12:30:07.977959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17405 12:30:08.015484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17406 12:30:08.015945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17408 12:30:08.052345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17410 12:30:08.052856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17411 12:30:08.086646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17412 12:30:08.087097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17414 12:30:08.136954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17415 12:30:08.137444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17417 12:30:08.185526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17418 12:30:08.185907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17420 12:30:08.219276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17422 12:30:08.219728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17423 12:30:08.252935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17424 12:30:08.253377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17426 12:30:08.287980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17428 12:30:08.288367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17429 12:30:08.322181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17431 12:30:08.322653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17432 12:30:08.359082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17434 12:30:08.359488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17435 12:30:08.393311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17436 12:30:08.393686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17438 12:30:08.425526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17439 12:30:08.426017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17441 12:30:08.463197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17443 12:30:08.463779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17444 12:30:08.501254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17446 12:30:08.501875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17447 12:30:08.538650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17448 12:30:08.539079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17450 12:30:08.577366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17451 12:30:08.577786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17453 12:30:08.616518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17455 12:30:08.616983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17456 12:30:08.654901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17458 12:30:08.655598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17459 12:30:08.693109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17460 12:30:08.693614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17462 12:30:08.729324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17463 12:30:08.729937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17465 12:30:08.764345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17467 12:30:08.764817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17468 12:30:08.796070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17470 12:30:08.796546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17471 12:30:08.829248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17472 12:30:08.829628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17474 12:30:08.861594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17475 12:30:08.862024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17477 12:30:08.894964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17479 12:30:08.895434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17480 12:30:08.929431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17481 12:30:08.929858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17483 12:30:08.962970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17485 12:30:08.963353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17486 12:30:08.995203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17487 12:30:08.995589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17489 12:30:09.028610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17490 12:30:09.029050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17492 12:30:09.061146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17494 12:30:09.061631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17495 12:30:09.093701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17496 12:30:09.094148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17498 12:30:09.125479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17499 12:30:09.125959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17501 12:30:09.161082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17502 12:30:09.161530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17504 12:30:09.195097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17505 12:30:09.195542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17507 12:30:09.227252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17508 12:30:09.227681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17510 12:30:09.259843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17511 12:30:09.260350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17513 12:30:09.293728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17514 12:30:09.294237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17516 12:30:09.327323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17518 12:30:09.327777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17519 12:30:09.360875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17520 12:30:09.361354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17522 12:30:09.394358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17523 12:30:09.394785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17525 12:30:09.427030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17526 12:30:09.427414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17528 12:30:09.461712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17530 12:30:09.462126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17531 12:30:09.496779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17532 12:30:09.497271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17534 12:30:09.530894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17536 12:30:09.531316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17537 12:30:09.566236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17538 12:30:09.566671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17540 12:30:09.602228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17541 12:30:09.602640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17543 12:30:09.640665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17544 12:30:09.641080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17546 12:30:09.675588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17547 12:30:09.675994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17549 12:30:09.710895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17550 12:30:09.711363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17552 12:30:09.742718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17553 12:30:09.743175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17555 12:30:09.775212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17557 12:30:09.775824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17558 12:30:09.807278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17559 12:30:09.807732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17561 12:30:09.842131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17562 12:30:09.842704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17564 12:30:09.877313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17565 12:30:09.877786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17567 12:30:09.909314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17569 12:30:09.909767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17570 12:30:09.941987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17571 12:30:09.942448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17573 12:30:09.979067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17574 12:30:09.979554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17576 12:30:10.012896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17578 12:30:10.013538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17579 12:30:10.045938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17580 12:30:10.046362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17582 12:30:10.078536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17584 12:30:10.079183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17585 12:30:10.110458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17587 12:30:10.111099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17588 12:30:10.145161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17590 12:30:10.145850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17591 12:30:10.177692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17592 12:30:10.178433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17594 12:30:10.209724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17595 12:30:10.210239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17597 12:30:10.244312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17599 12:30:10.244791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17600 12:30:10.281661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17601 12:30:10.282103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17603 12:30:10.314370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17604 12:30:10.314799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17606 12:30:10.347661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17607 12:30:10.348160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17609 12:30:10.380150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17610 12:30:10.380617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17612 12:30:10.414848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17614 12:30:10.415309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17615 12:30:10.448512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17617 12:30:10.448976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17618 12:30:10.481598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17620 12:30:10.482055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17621 12:30:10.513338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17622 12:30:10.513762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17624 12:30:10.545463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17625 12:30:10.545961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17627 12:30:10.580112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17629 12:30:10.580685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17630 12:30:10.613838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17631 12:30:10.614262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17633 12:30:10.648911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17635 12:30:10.649543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17636 12:30:10.681550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17637 12:30:10.681985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17639 12:30:10.714613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17641 12:30:10.715098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17642 12:30:10.746761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17643 12:30:10.747278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17645 12:30:10.783781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17647 12:30:10.784533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17648 12:30:10.826375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17649 12:30:10.826754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17651 12:30:10.861306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17652 12:30:10.861740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17654 12:30:10.899566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17655 12:30:10.900014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17657 12:30:10.934406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17659 12:30:10.935016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17660 12:30:10.972135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17662 12:30:10.972716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17663 12:30:11.007534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17664 12:30:11.008018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17666 12:30:11.043534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17668 12:30:11.044118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17669 12:30:11.083994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17670 12:30:11.084461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17672 12:30:11.119494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17673 12:30:11.119915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17675 12:30:11.158290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17676 12:30:11.158776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17678 12:30:11.193255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17679 12:30:11.193701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17681 12:30:11.224734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17682 12:30:11.225235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17684 12:30:11.263549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17685 12:30:11.264028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17687 12:30:11.297926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17688 12:30:11.298419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17690 12:30:11.333864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17691 12:30:11.334280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17693 12:30:11.372328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17695 12:30:11.372898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17696 12:30:11.413309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17697 12:30:11.413773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17699 12:30:11.451666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17701 12:30:11.452162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17702 12:30:11.486063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17703 12:30:11.486554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17705 12:30:11.520744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17706 12:30:11.521161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17708 12:30:11.555605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17709 12:30:11.556064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17711 12:30:11.590384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17713 12:30:11.590848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17714 12:30:11.629153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17716 12:30:11.629612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17717 12:30:11.661101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17718 12:30:11.661569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17720 12:30:11.693211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17721 12:30:11.693685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17723 12:30:11.742201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17724 12:30:11.742647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17726 12:30:11.775224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17727 12:30:11.775712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17729 12:30:11.809526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17730 12:30:11.810022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17732 12:30:11.841735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17733 12:30:11.842221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17735 12:30:11.873823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17737 12:30:11.874457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17738 12:30:11.905231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17739 12:30:11.905701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17741 12:30:11.938363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17743 12:30:11.938825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17744 12:30:11.974665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17745 12:30:11.975196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17747 12:30:12.009971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17748 12:30:12.010502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17750 12:30:12.046643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17752 12:30:12.047154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17753 12:30:12.089786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17755 12:30:12.090239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17756 12:30:12.126864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17758 12:30:12.127327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17759 12:30:12.166020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17760 12:30:12.166439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17762 12:30:12.202320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17763 12:30:12.202742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17765 12:30:12.237976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17767 12:30:12.238438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17768 12:30:12.273412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17769 12:30:12.273836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17771 12:30:12.308151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17773 12:30:12.308820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17774 12:30:12.345608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17775 12:30:12.346116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17777 12:30:12.378246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17778 12:30:12.378745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17780 12:30:12.413491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17782 12:30:12.414230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17783 12:30:12.449980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17784 12:30:12.450489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17786 12:30:12.482655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17787 12:30:12.483163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17789 12:30:12.518678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17790 12:30:12.519185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17792 12:30:12.553803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17794 12:30:12.554633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17795 12:30:12.589276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17796 12:30:12.589692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17798 12:30:12.625213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17799 12:30:12.625639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17801 12:30:12.657546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17802 12:30:12.658005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17804 12:30:12.698302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17805 12:30:12.698743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17807 12:30:12.732798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17809 12:30:12.733247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17810 12:30:12.766448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17812 12:30:12.766892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17813 12:30:12.800166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17815 12:30:12.800611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17816 12:30:12.835870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17817 12:30:12.836328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17819 12:30:12.872809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17821 12:30:12.873251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17822 12:30:12.904921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17823 12:30:12.905320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17825 12:30:12.936244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17827 12:30:12.936687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17828 12:30:12.967691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17829 12:30:12.968125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17831 12:30:12.999822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17832 12:30:13.000354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17834 12:30:13.032581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17835 12:30:13.033040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17837 12:30:13.067169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17838 12:30:13.067618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17840 12:30:13.098233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17841 12:30:13.098673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17843 12:30:13.129697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17844 12:30:13.130186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17846 12:30:13.160943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17848 12:30:13.161428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17849 12:30:13.193051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17850 12:30:13.193531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17852 12:30:13.227714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17853 12:30:13.228215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17855 12:30:13.261400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17856 12:30:13.261859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17858 12:30:13.292785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17859 12:30:13.293288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17861 12:30:13.323797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17863 12:30:13.324287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17864 12:30:13.355323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17865 12:30:13.355782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17867 12:30:13.389903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17869 12:30:13.390348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17870 12:30:13.422592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17871 12:30:13.422995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17873 12:30:13.456132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17874 12:30:13.456636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17876 12:30:13.490918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17877 12:30:13.491390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17879 12:30:13.524459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17881 12:30:13.525295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17882 12:30:13.561264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17883 12:30:13.561682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17885 12:30:13.597151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17887 12:30:13.597520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17888 12:30:13.629331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17889 12:30:13.629785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17891 12:30:13.661593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17893 12:30:13.662157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17894 12:30:13.696254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17896 12:30:13.696876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17897 12:30:13.733498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17898 12:30:13.733973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17900 12:30:13.771777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17901 12:30:13.772187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17903 12:30:13.806786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17905 12:30:13.807277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17906 12:30:13.842788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17907 12:30:13.843303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17909 12:30:13.878145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17911 12:30:13.878752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17912 12:30:13.913537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17913 12:30:13.914032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17915 12:30:13.948363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17917 12:30:13.948751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17918 12:30:13.981426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17920 12:30:13.981847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17921 12:30:14.015151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17923 12:30:14.015638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17924 12:30:14.054706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17925 12:30:14.055147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17927 12:30:14.089489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17928 12:30:14.089953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17930 12:30:14.125239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17931 12:30:14.125693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17933 12:30:14.159972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17934 12:30:14.160424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17936 12:30:14.196859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17937 12:30:14.197297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17939 12:30:14.231728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17940 12:30:14.232173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17942 12:30:14.269387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17944 12:30:14.269885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17945 12:30:14.307243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17947 12:30:14.307735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17948 12:30:14.346368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17950 12:30:14.346888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17951 12:30:14.393601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17952 12:30:14.394067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17954 12:30:14.441068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17956 12:30:14.441534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17957 12:30:14.479295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17958 12:30:14.479712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17960 12:30:14.533051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17961 12:30:14.533494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17963 12:30:14.583400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17964 12:30:14.583824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17966 12:30:14.631410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17968 12:30:14.631882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17969 12:30:14.680868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17970 12:30:14.681273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17972 12:30:14.719700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17973 12:30:14.720099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17975 12:30:14.764942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17977 12:30:14.765480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17978 12:30:14.809122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17979 12:30:14.809535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17981 12:30:14.843572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17982 12:30:14.843960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17984 12:30:14.879382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17985 12:30:14.879809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17987 12:30:14.917693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17988 12:30:14.918124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17990 12:30:14.962518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17991 12:30:14.962929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17993 12:30:15.014470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17995 12:30:15.014929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17996 12:30:15.058066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17997 12:30:15.058453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17999 12:30:15.099900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
18001 12:30:15.100317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
18002 12:30:15.137931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
18004 12:30:15.138489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
18005 12:30:15.178151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
18006 12:30:15.178526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
18008 12:30:15.220055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
18009 12:30:15.220493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
18011 12:30:15.261241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
18013 12:30:15.261703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
18014 12:30:15.297789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
18015 12:30:15.298181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
18017 12:30:15.338213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
18019 12:30:15.338601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
18020 12:30:15.379715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
18021 12:30:15.380121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
18023 12:30:15.415558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
18024 12:30:15.415978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
18026 12:30:15.450367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
18027 12:30:15.450765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
18029 12:30:15.483644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
18030 12:30:15.484137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
18032 12:30:15.517712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
18034 12:30:15.518176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
18035 12:30:15.555236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
18036 12:30:15.555679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
18038 12:30:15.588399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
18040 12:30:15.588861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
18041 12:30:15.621714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
18042 12:30:15.622136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
18044 12:30:15.655225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
18045 12:30:15.655650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
18047 12:30:15.688749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
18048 12:30:15.689181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
18050 12:30:15.725053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
18051 12:30:15.725468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
18053 12:30:15.758023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
18055 12:30:15.758478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
18056 12:30:15.791489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
18057 12:30:15.791916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
18059 12:30:15.824974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
18060 12:30:15.825409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
18062 12:30:15.858597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
18063 12:30:15.859107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
18065 12:30:15.895013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
18067 12:30:15.895743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
18068 12:30:15.928862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
18069 12:30:15.929339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
18071 12:30:15.961628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18073 12:30:15.962296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
18074 12:30:15.995991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18075 12:30:15.996482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18077 12:30:16.030878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18078 12:30:16.031340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18080 12:30:16.066527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18081 12:30:16.067001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18083 12:30:16.100562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18084 12:30:16.101049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18086 12:30:16.134888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18087 12:30:16.135353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18089 12:30:16.169700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18091 12:30:16.170349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18092 12:30:16.204978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18094 12:30:16.205620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18095 12:30:16.239802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18097 12:30:16.240280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18098 12:30:16.274453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18100 12:30:16.275108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18101 12:30:16.307667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18102 12:30:16.308114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18104 12:30:16.341287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18105 12:30:16.341684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18107 12:30:16.374362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18108 12:30:16.374811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18110 12:30:16.407873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18112 12:30:16.408301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18113 12:30:16.443248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18114 12:30:16.443768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18116 12:30:16.477429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18118 12:30:16.478010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18119 12:30:16.511151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18120 12:30:16.511602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18122 12:30:16.544304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18124 12:30:16.544772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18125 12:30:16.582030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18126 12:30:16.582429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18128 12:30:16.622595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18129 12:30:16.623013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18131 12:30:16.657058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18132 12:30:16.657442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18134 12:30:16.690607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18135 12:30:16.690999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18137 12:30:16.723287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18138 12:30:16.723696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18140 12:30:16.757580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18141 12:30:16.758111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18143 12:30:16.792914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18144 12:30:16.793408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18146 12:30:16.825957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18147 12:30:16.826434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18149 12:30:16.858320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18150 12:30:16.858784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18152 12:30:16.891503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18154 12:30:16.892123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18155 12:30:16.925434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18157 12:30:16.926090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18158 12:30:16.961083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18159 12:30:16.961548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18161 12:30:16.995174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18163 12:30:16.995745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18164 12:30:17.028712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18165 12:30:17.029147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18167 12:30:17.062127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18169 12:30:17.062590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18170 12:30:17.096878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18171 12:30:17.097288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18173 12:30:17.133621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18175 12:30:17.134092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18176 12:30:17.168217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18178 12:30:17.168692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18179 12:30:17.202548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18180 12:30:17.202993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18182 12:30:17.237042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18184 12:30:17.237517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18185 12:30:17.271739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18187 12:30:17.272391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18188 12:30:17.306509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18190 12:30:17.307241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18191 12:30:17.341508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18193 12:30:17.341977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18194 12:30:17.375425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18195 12:30:17.375866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18197 12:30:17.408406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18199 12:30:17.408877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18200 12:30:17.441949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18201 12:30:17.442389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18203 12:30:17.482071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18205 12:30:17.482854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18206 12:30:17.521334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18207 12:30:17.521921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18209 12:30:17.557743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18210 12:30:17.558188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18212 12:30:17.595315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18214 12:30:17.596131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18215 12:30:17.631569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18217 12:30:17.632034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18218 12:30:17.668403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18220 12:30:17.668813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18221 12:30:17.702758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18223 12:30:17.703437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18224 12:30:17.736143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18225 12:30:17.736642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18227 12:30:17.770366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18228 12:30:17.770876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18230 12:30:17.804997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18232 12:30:17.805444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18233 12:30:17.869946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18235 12:30:17.870400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18236 12:30:17.903707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18237 12:30:17.904111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18239 12:30:17.937048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18240 12:30:17.937463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18242 12:30:17.970471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18244 12:30:17.970916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18245 12:30:18.003944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18246 12:30:18.004364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18248 12:30:18.041942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18249 12:30:18.042371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18251 12:30:18.076419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18253 12:30:18.076879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18254 12:30:18.110109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18255 12:30:18.110579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18257 12:30:18.144774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18258 12:30:18.145236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18260 12:30:18.179238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18261 12:30:18.179693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18263 12:30:18.215182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18264 12:30:18.215626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18266 12:30:18.249255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18267 12:30:18.249689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18269 12:30:18.283541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18270 12:30:18.284015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18272 12:30:18.317369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18273 12:30:18.317787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18275 12:30:18.350903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18276 12:30:18.351323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18278 12:30:18.388902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18279 12:30:18.389343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18281 12:30:18.422238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18282 12:30:18.422676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18284 12:30:18.455898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18285 12:30:18.456346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18287 12:30:18.489388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18288 12:30:18.489825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18290 12:30:18.523463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18292 12:30:18.523948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18293 12:30:18.557414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18294 12:30:18.557864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18296 12:30:18.592751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18297 12:30:18.593161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18299 12:30:18.626709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18301 12:30:18.627165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18302 12:30:18.660518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18303 12:30:18.660946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18305 12:30:18.698118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18306 12:30:18.698501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18308 12:30:18.734457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18309 12:30:18.734867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18311 12:30:18.771276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18313 12:30:18.771741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18314 12:30:18.809268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18315 12:30:18.809693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18317 12:30:18.846629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18318 12:30:18.847046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18320 12:30:18.882044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18321 12:30:18.882478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18323 12:30:18.916911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18324 12:30:18.917344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18326 12:30:18.950219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18328 12:30:18.950688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18329 12:30:18.982818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18330 12:30:18.983305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18332 12:30:19.015259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18333 12:30:19.015682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18335 12:30:19.047954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18336 12:30:19.048364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18338 12:30:19.081396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18340 12:30:19.081852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18341 12:30:19.116617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18342 12:30:19.117100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18344 12:30:19.153629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18345 12:30:19.154070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18347 12:30:19.187935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18348 12:30:19.188357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18350 12:30:19.221342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18352 12:30:19.222005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18353 12:30:19.254640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18355 12:30:19.255221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18356 12:30:19.289391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18357 12:30:19.289856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18359 12:30:19.322814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18361 12:30:19.323403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18362 12:30:19.355859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18363 12:30:19.356330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18365 12:30:19.390595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18367 12:30:19.391015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18368 12:30:19.424162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18370 12:30:19.424574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18371 12:30:19.458886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18372 12:30:19.459292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18374 12:30:19.493975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18375 12:30:19.494379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18377 12:30:19.529251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18379 12:30:19.529676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18380 12:30:19.562588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18381 12:30:19.563047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18383 12:30:19.595847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18384 12:30:19.596344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18386 12:30:19.630239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18387 12:30:19.630720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18389 12:30:19.665261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18390 12:30:19.665694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18392 12:30:19.699238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18393 12:30:19.699679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18395 12:30:19.734042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18396 12:30:19.734524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18398 12:30:19.768022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18400 12:30:19.768578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18401 12:30:19.801831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18402 12:30:19.802270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18404 12:30:19.837275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18405 12:30:19.837681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18407 12:30:19.871637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18409 12:30:19.872288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18410 12:30:19.905478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18411 12:30:19.905921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18413 12:30:19.939407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18414 12:30:19.939846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18416 12:30:19.973374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18417 12:30:19.973784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18419 12:30:20.009028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18420 12:30:20.009446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18422 12:30:20.042666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18424 12:30:20.043118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18425 12:30:20.077073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18426 12:30:20.077557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18428 12:30:20.110125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18430 12:30:20.110684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18431 12:30:20.143490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18432 12:30:20.143973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18434 12:30:20.178353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18436 12:30:20.178918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18437 12:30:20.211328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18438 12:30:20.211803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18440 12:30:20.245460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18441 12:30:20.245888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18443 12:30:20.280355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18445 12:30:20.280775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18446 12:30:20.313801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18447 12:30:20.314199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18449 12:30:20.348492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18451 12:30:20.349026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18452 12:30:20.382175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18453 12:30:20.382591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18455 12:30:20.417338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18456 12:30:20.417769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18458 12:30:20.451664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18459 12:30:20.452057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18461 12:30:20.485452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18462 12:30:20.485848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18464 12:30:20.519393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18465 12:30:20.519874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18467 12:30:20.553060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18468 12:30:20.553502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18470 12:30:20.586465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18471 12:30:20.586892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18473 12:30:20.620135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18474 12:30:20.620647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18476 12:30:20.653238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18477 12:30:20.653693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18479 12:30:20.686230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18480 12:30:20.686626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18482 12:30:20.721229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18483 12:30:20.721628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18485 12:30:20.754692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18486 12:30:20.755157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18488 12:30:20.789115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18490 12:30:20.789841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18491 12:30:20.823857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18493 12:30:20.824488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18494 12:30:20.857496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18496 12:30:20.858114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18497 12:30:20.893953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18499 12:30:20.894523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18500 12:30:20.933400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18501 12:30:20.933897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18503 12:30:20.966728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18505 12:30:20.967300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18506 12:30:21.000735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18507 12:30:21.001141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18509 12:30:21.035538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18510 12:30:21.035952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18512 12:30:21.071414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18513 12:30:21.071916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18515 12:30:21.106477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18517 12:30:21.107116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18518 12:30:21.141074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18520 12:30:21.141666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18521 12:30:21.175534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18522 12:30:21.176008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18524 12:30:21.209164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18525 12:30:21.209602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18527 12:30:21.244996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18528 12:30:21.245409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18530 12:30:21.279193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18532 12:30:21.279648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18533 12:30:21.313459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18535 12:30:21.313936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18536 12:30:21.349285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18538 12:30:21.349883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18539 12:30:21.385203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18541 12:30:21.385839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18542 12:30:21.426015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18543 12:30:21.426547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18545 12:30:21.475772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18547 12:30:21.476298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18548 12:30:21.510643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18549 12:30:21.511027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18551 12:30:21.544835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18552 12:30:21.545251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18554 12:30:21.581128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18555 12:30:21.581640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18557 12:30:21.618241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18558 12:30:21.618651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18560 12:30:21.659158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18561 12:30:21.659656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18563 12:30:21.715984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18564 12:30:21.716413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18566 12:30:21.754586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18567 12:30:21.755030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18569 12:30:21.793070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18570 12:30:21.793487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18572 12:30:21.829108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18573 12:30:21.829527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18575 12:30:21.865349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18576 12:30:21.865761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18578 12:30:21.903271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18579 12:30:21.903684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18581 12:30:21.941694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18582 12:30:21.942125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18584 12:30:21.979367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18586 12:30:21.979818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18587 12:30:22.017318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18588 12:30:22.017757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18590 12:30:22.053786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18591 12:30:22.054231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18593 12:30:22.091220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18594 12:30:22.091665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18596 12:30:22.129710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18597 12:30:22.130154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18599 12:30:22.167955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18600 12:30:22.168406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18602 12:30:22.206910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18603 12:30:22.207379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18605 12:30:22.245690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18607 12:30:22.246147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18608 12:30:22.282497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18609 12:30:22.282918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18611 12:30:22.321366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18612 12:30:22.321799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18614 12:30:22.359097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18615 12:30:22.359525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18617 12:30:22.397424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18618 12:30:22.397863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18620 12:30:22.434061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18622 12:30:22.434543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18623 12:30:22.472369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18625 12:30:22.472889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18626 12:30:22.526694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18628 12:30:22.527173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18629 12:30:22.575536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18630 12:30:22.575973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18632 12:30:22.618522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18633 12:30:22.618919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18635 12:30:22.662177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18637 12:30:22.662907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18638 12:30:22.703057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18640 12:30:22.703694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18641 12:30:22.741596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18643 12:30:22.742131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18644 12:30:22.781227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18645 12:30:22.781660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18647 12:30:22.832533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18649 12:30:22.833119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18650 12:30:22.883164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18651 12:30:22.883636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18653 12:30:22.926246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18654 12:30:22.926652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18656 12:30:22.991368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18657 12:30:22.991751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18659 12:30:23.030255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18660 12:30:23.030839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18662 12:30:23.067114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18663 12:30:23.067592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18665 12:30:23.105296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18667 12:30:23.106100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18668 12:30:23.142186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18669 12:30:23.142633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18671 12:30:23.184122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18673 12:30:23.184646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18674 12:30:23.232893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18675 12:30:23.233304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18677 12:30:23.270928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18678 12:30:23.271328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18680 12:30:23.309200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18681 12:30:23.309588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18683 12:30:23.346678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18684 12:30:23.347095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18686 12:30:23.384320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18688 12:30:23.384697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18689 12:30:23.422049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18691 12:30:23.422445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18692 12:30:23.458064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18694 12:30:23.458614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18695 12:30:23.496930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18697 12:30:23.497476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18698 12:30:23.531271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18699 12:30:23.531709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18701 12:30:23.573595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18702 12:30:23.573997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18704 12:30:23.612231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18706 12:30:23.612948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18707 12:30:23.651095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18708 12:30:23.651512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18710 12:30:23.690941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18711 12:30:23.691533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18713 12:30:23.735428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18714 12:30:23.735939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18716 12:30:23.786668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18717 12:30:23.787049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18719 12:30:23.825187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18721 12:30:23.825600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18722 12:30:23.866955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18723 12:30:23.867321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18725 12:30:23.907420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18726 12:30:23.907823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18728 12:30:23.962262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18729 12:30:23.962704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18731 12:30:24.017607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18733 12:30:24.018059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18734 12:30:24.077733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18735 12:30:24.078175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18737 12:30:24.123633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18738 12:30:24.124049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18740 12:30:24.166492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18742 12:30:24.166940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18743 12:30:24.207809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18744 12:30:24.208304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18746 12:30:24.250943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18747 12:30:24.251362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18749 12:30:24.303379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18750 12:30:24.303862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18752 12:30:24.350083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18753 12:30:24.350516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18755 12:30:24.388287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18757 12:30:24.388868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18758 12:30:24.434788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18759 12:30:24.435161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18761 12:30:24.493282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18762 12:30:24.493688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18764 12:30:24.537717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18765 12:30:24.538193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18767 12:30:24.579390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18768 12:30:24.579897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18770 12:30:24.622669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18771 12:30:24.623336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18773 12:30:24.668148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18774 12:30:24.668585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18776 12:30:24.706917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18777 12:30:24.707271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18779 12:30:24.746496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18780 12:30:24.746845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18782 12:30:24.787553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18783 12:30:24.788000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18785 12:30:24.845749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18786 12:30:24.846148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18788 12:30:24.897327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18789 12:30:24.897775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18791 12:30:24.938109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18792 12:30:24.938644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18794 12:30:24.979608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18795 12:30:24.980051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18797 12:30:25.016010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18798 12:30:25.016480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18800 12:30:25.053340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18801 12:30:25.053832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18803 12:30:25.090447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18804 12:30:25.090940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18806 12:30:25.127347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18807 12:30:25.127840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18809 12:30:25.165376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18811 12:30:25.166027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18812 12:30:25.201767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18813 12:30:25.202269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18815 12:30:25.238120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18817 12:30:25.238668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18818 12:30:25.274399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18819 12:30:25.274836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18821 12:30:25.310860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18822 12:30:25.311260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18824 12:30:25.348136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18825 12:30:25.348552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18827 12:30:25.386117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18829 12:30:25.386567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18830 12:30:25.422636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18832 12:30:25.423113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18833 12:30:25.468003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18834 12:30:25.468463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18836 12:30:25.507752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18838 12:30:25.508319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18839 12:30:25.547245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18840 12:30:25.547791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18842 12:30:25.586457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18843 12:30:25.586961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18845 12:30:25.624027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18847 12:30:25.624513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18848 12:30:25.662942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18850 12:30:25.663717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18851 12:30:25.701279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18852 12:30:25.701706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18854 12:30:25.743443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18855 12:30:25.743844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18857 12:30:25.799170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18858 12:30:25.799598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18860 12:30:25.839298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18861 12:30:25.839715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18863 12:30:25.895144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18864 12:30:25.895596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18866 12:30:25.941505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18867 12:30:25.941957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18869 12:30:25.985384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18871 12:30:25.985903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18872 12:30:26.039404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18873 12:30:26.039823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18875 12:30:26.099178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18876 12:30:26.099597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18878 12:30:26.157643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18879 12:30:26.158055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18881 12:30:26.198590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18883 12:30:26.199056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18884 12:30:26.243055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18885 12:30:26.243429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18887 12:30:26.281850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18889 12:30:26.282271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18890 12:30:26.319471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18892 12:30:26.319916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18893 12:30:26.375224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18895 12:30:26.375633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18896 12:30:26.431057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18898 12:30:26.431526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18899 12:30:26.481828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18900 12:30:26.482230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18902 12:30:26.540383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18904 12:30:26.541017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18905 12:30:26.598470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18907 12:30:26.598863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18908 12:30:26.655472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18909 12:30:26.655961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18911 12:30:26.693784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18912 12:30:26.694282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18914 12:30:26.732873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18916 12:30:26.733367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18917 12:30:26.773259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18918 12:30:26.773614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18920 12:30:26.811419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18922 12:30:26.812035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18923 12:30:26.859074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18924 12:30:26.859552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18926 12:30:26.905798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18927 12:30:26.906242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18929 12:30:26.961861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18930 12:30:26.962259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18932 12:30:27.007394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18933 12:30:27.007830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18935 12:30:27.054625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18936 12:30:27.055014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18938 12:30:27.094995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18939 12:30:27.095489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18941 12:30:27.134552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18942 12:30:27.134961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18944 12:30:27.171707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18945 12:30:27.172148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18947 12:30:27.223951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18948 12:30:27.224371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18950 12:30:27.269821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18951 12:30:27.270341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18953 12:30:27.315360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18954 12:30:27.315817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18956 12:30:27.353709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18957 12:30:27.354146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18959 12:30:27.391669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18960 12:30:27.392137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18962 12:30:27.430613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18963 12:30:27.431055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18965 12:30:27.473146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18967 12:30:27.473616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18968 12:30:27.530975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18970 12:30:27.531459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18971 12:30:27.594355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18973 12:30:27.594841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18974 12:30:27.637964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18975 12:30:27.638409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18977 12:30:27.677338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18979 12:30:27.677813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18980 12:30:27.715350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18982 12:30:27.715813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18983 12:30:27.756259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18984 12:30:27.756616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18986 12:30:27.797562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18988 12:30:27.798059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18989 12:30:27.846016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18990 12:30:27.846446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18992 12:30:27.900479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18994 12:30:27.900951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18995 12:30:27.942099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18996 12:30:27.942505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18998 12:30:27.998459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18999 12:30:27.998854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
19001 12:30:28.038582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
19003 12:30:28.039003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
19004 12:30:28.095805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
19005 12:30:28.096248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
19007 12:30:28.134409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
19008 12:30:28.134889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
19010 12:30:28.171806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
19011 12:30:28.172267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
19013 12:30:28.210052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
19014 12:30:28.210528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
19016 12:30:28.247485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
19018 12:30:28.247951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
19019 12:30:28.285798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
19020 12:30:28.286250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
19022 12:30:28.334721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
19023 12:30:28.335149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
19025 12:30:28.381712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
19026 12:30:28.382263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
19028 12:30:28.419241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
19029 12:30:28.419679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
19031 12:30:28.458936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
19033 12:30:28.459415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
19034 12:30:28.498143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
19036 12:30:28.498627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
19037 12:30:28.539001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
19039 12:30:28.539401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
19040 12:30:28.578117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
19041 12:30:28.578552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
19043 12:30:28.615863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
19044 12:30:28.616283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
19046 12:30:28.653984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
19047 12:30:28.654413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
19049 12:30:28.699810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
19050 12:30:28.700253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
19052 12:30:28.745630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
19053 12:30:28.746130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
19055 12:30:28.789290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
19056 12:30:28.789753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
19058 12:30:28.835271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
19060 12:30:28.835885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
19061 12:30:28.878432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
19063 12:30:28.878824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
19064 12:30:28.918858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
19065 12:30:28.919291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
19067 12:30:28.954750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
19068 12:30:28.955152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
19070 12:30:28.989873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
19072 12:30:28.990362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
19073 12:30:29.025242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19075 12:30:29.025732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19076 12:30:29.060389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19078 12:30:29.060962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19079 12:30:29.095158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19080 12:30:29.095613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19082 12:30:29.129961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19084 12:30:29.130595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19085 12:30:29.164802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19087 12:30:29.165422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19088 12:30:29.199064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19089 12:30:29.199523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19091 12:30:29.234446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19092 12:30:29.234860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19094 12:30:29.269904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19095 12:30:29.270363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19097 12:30:29.305278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19098 12:30:29.305694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19100 12:30:29.339734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19101 12:30:29.340131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19103 12:30:29.375176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19104 12:30:29.375574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19106 12:30:29.410396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19107 12:30:29.410788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19109 12:30:29.446026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19111 12:30:29.446807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19112 12:30:29.481972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19113 12:30:29.482432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19115 12:30:29.518266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19116 12:30:29.518725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19118 12:30:29.553887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19119 12:30:29.554340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19121 12:30:29.589844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19122 12:30:29.590259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19124 12:30:29.625956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19125 12:30:29.626421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19127 12:30:29.666016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19128 12:30:29.666413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19130 12:30:29.702604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19132 12:30:29.703066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19133 12:30:29.738583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19134 12:30:29.738942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19136 12:30:29.773927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19137 12:30:29.774361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19139 12:30:29.814328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19140 12:30:29.814794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19142 12:30:29.853653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19143 12:30:29.854103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19145 12:30:29.891006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19147 12:30:29.891692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19148 12:30:29.928679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19149 12:30:29.929126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19151 12:30:29.967501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19153 12:30:29.967966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19154 12:30:30.009922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19155 12:30:30.010367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19157 12:30:30.055142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19158 12:30:30.055578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19160 12:30:30.103219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19161 12:30:30.103663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19163 12:30:30.154266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19165 12:30:30.154770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19166 12:30:30.207710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19167 12:30:30.208135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19169 12:30:30.265183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19170 12:30:30.265618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19172 12:30:30.306712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19174 12:30:30.307159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19175 12:30:30.347086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19177 12:30:30.347550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19178 12:30:30.391259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19180 12:30:30.391850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19181 12:30:30.436304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19183 12:30:30.436801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19184 12:30:30.490077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19185 12:30:30.490547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19187 12:30:30.542860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19189 12:30:30.543318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19190 12:30:30.581852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19191 12:30:30.582259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19193 12:30:30.620374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19195 12:30:30.620805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19196 12:30:30.663544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19198 12:30:30.664044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19199 12:30:30.707838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19200 12:30:30.708299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19202 12:30:30.752559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19204 12:30:30.753208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19205 12:30:30.810589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19206 12:30:30.811115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19208 12:30:30.859438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19210 12:30:30.859871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19211 12:30:30.899171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19212 12:30:30.899752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19214 12:30:30.941294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19215 12:30:30.941685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19217 12:30:30.978939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19218 12:30:30.979348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19220 12:30:31.016091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19221 12:30:31.016584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19223 12:30:31.053344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19225 12:30:31.053942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19226 12:30:31.089795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19227 12:30:31.090277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19229 12:30:31.127384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19230 12:30:31.127848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19232 12:30:31.165383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19234 12:30:31.165876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19235 12:30:31.201811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19236 12:30:31.202222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19238 12:30:31.238973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19239 12:30:31.239402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19241 12:30:31.286723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19242 12:30:31.287109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19244 12:30:31.331358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19245 12:30:31.331830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19247 12:30:31.372290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19249 12:30:31.372934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19250 12:30:31.416952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19251 12:30:31.417383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19253 12:30:31.461505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19254 12:30:31.461967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19256 12:30:31.510101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19257 12:30:31.510536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19259 12:30:31.560053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19261 12:30:31.560536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19262 12:30:31.603500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19263 12:30:31.603940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19265 12:30:31.663809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19266 12:30:31.664401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19268 12:30:31.703786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19269 12:30:31.704207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19271 12:30:31.741726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19272 12:30:31.742123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19274 12:30:31.778459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19276 12:30:31.778853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19277 12:30:31.818676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19278 12:30:31.819104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19280 12:30:31.858526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19282 12:30:31.858986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19283 12:30:31.903667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19285 12:30:31.904154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19286 12:30:31.952717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19288 12:30:31.953178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19289 12:30:31.993581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19290 12:30:31.997759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19292 12:30:32.033598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19293 12:30:32.033997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19295 12:30:32.071837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19296 12:30:32.072235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19298 12:30:32.114961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19299 12:30:32.115385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19301 12:30:32.157049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19303 12:30:32.157552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19304 12:30:32.194494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19305 12:30:32.194948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19307 12:30:32.233934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19309 12:30:32.234410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19310 12:30:32.273440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19311 12:30:32.273857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19313 12:30:32.311036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19314 12:30:32.311444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19316 12:30:32.350581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19317 12:30:32.351020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19319 12:30:32.395354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19321 12:30:32.395820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19322 12:30:32.434096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19323 12:30:32.434477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19325 12:30:32.485228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19326 12:30:32.487705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19328 12:30:32.529681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19330 12:30:32.530111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19331 12:30:32.579649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19333 12:30:32.580309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19334 12:30:32.631699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19335 12:30:32.632147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19337 12:30:32.671276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19338 12:30:32.671659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19340 12:30:32.708438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19342 12:30:32.708825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19343 12:30:32.745445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19345 12:30:32.745844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19346 12:30:32.782549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19347 12:30:32.782974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19349 12:30:32.825198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19350 12:30:32.825628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19352 12:30:32.870753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19353 12:30:32.871184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19355 12:30:32.912966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19356 12:30:32.913419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19358 12:30:32.951870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19359 12:30:32.952320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19361 12:30:32.993962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19362 12:30:32.994350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19364 12:30:33.038273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19365 12:30:33.038688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19367 12:30:33.091176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19368 12:30:33.091647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19370 12:30:33.150393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19371 12:30:33.150801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19373 12:30:33.240441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19375 12:30:33.241206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19376 12:30:33.299795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19378 12:30:33.300420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19379 12:30:33.361376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19380 12:30:33.361778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19382 12:30:33.419550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19383 12:30:33.420048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19385 12:30:33.473424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19386 12:30:33.473914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19388 12:30:33.514304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19389 12:30:33.514794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19391 12:30:33.562528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19392 12:30:33.563101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19394 12:30:33.609040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19395 12:30:33.609538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19397 12:30:33.653512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19399 12:30:33.654125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19400 12:30:33.694109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19401 12:30:33.694585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19403 12:30:33.741538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19405 12:30:33.742011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19406 12:30:33.786840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19408 12:30:33.787224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19409 12:30:33.829538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19410 12:30:33.830006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19412 12:30:33.871274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19413 12:30:33.871718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19415 12:30:33.919630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19416 12:30:33.920017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19418 12:30:33.977177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19420 12:30:33.977747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19421 12:30:34.038156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19422 12:30:34.038603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19424 12:30:34.094432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19425 12:30:34.094900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19427 12:30:34.149231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19428 12:30:34.149671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19430 12:30:34.202852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19431 12:30:34.203288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19433 12:30:34.255821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19435 12:30:34.256266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19436 12:30:34.310678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19437 12:30:34.311103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19439 12:30:34.367322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19440 12:30:34.367748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19442 12:30:34.419756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19443 12:30:34.420156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19445 12:30:34.471467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19446 12:30:34.471877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19448 12:30:34.524032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19449 12:30:34.524435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19451 12:30:34.571167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19452 12:30:34.571577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19454 12:30:34.622784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19455 12:30:34.623230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19457 12:30:34.681703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19458 12:30:34.682136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19460 12:30:34.739465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19461 12:30:34.739866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19463 12:30:34.799418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19464 12:30:34.799874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19466 12:30:34.855880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19467 12:30:34.856303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19469 12:30:34.911357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19471 12:30:34.911822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19472 12:30:34.963449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19474 12:30:34.963906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19475 12:30:35.011172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19477 12:30:35.011562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19478 12:30:35.055079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19479 12:30:35.055521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19481 12:30:35.097263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19482 12:30:35.097700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19484 12:30:35.141672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19485 12:30:35.142107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19487 12:30:35.181740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19489 12:30:35.182415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19490 12:30:35.223672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19492 12:30:35.224159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19493 12:30:35.265069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19494 12:30:35.265484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19496 12:30:35.307686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19497 12:30:35.308144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19499 12:30:35.350885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19500 12:30:35.351337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19502 12:30:35.393918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19503 12:30:35.394348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19505 12:30:35.435437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19506 12:30:35.435891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19508 12:30:35.478645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19510 12:30:35.479123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19511 12:30:35.522958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19512 12:30:35.523418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19514 12:30:35.570905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19515 12:30:35.571327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19517 12:30:35.613577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19518 12:30:35.614041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19520 12:30:35.654403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19521 12:30:35.654853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19523 12:30:35.699985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19525 12:30:35.700474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19526 12:30:35.741665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19527 12:30:35.742221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19529 12:30:35.793397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19530 12:30:35.793874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19532 12:30:35.851068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19533 12:30:35.851545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19535 12:30:35.900780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19536 12:30:35.901231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19538 12:30:35.941810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19539 12:30:35.942266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19541 12:30:35.981207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19543 12:30:35.981767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19544 12:30:36.022001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19546 12:30:36.022493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19547 12:30:36.065384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19549 12:30:36.065885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19550 12:30:36.109369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19552 12:30:36.109872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19553 12:30:36.155522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19554 12:30:36.155968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19556 12:30:36.215437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19558 12:30:36.215927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19559 12:30:36.274078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19561 12:30:36.274554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19562 12:30:36.328959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19563 12:30:36.329553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19565 12:30:36.370961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19566 12:30:36.371543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19568 12:30:36.430744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19569 12:30:36.431264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19571 12:30:36.483957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19572 12:30:36.484341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19574 12:30:36.526985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19576 12:30:36.527754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19577 12:30:36.570571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19578 12:30:36.571071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19580 12:30:36.614312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19581 12:30:36.614675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19583 12:30:36.669755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19584 12:30:36.670198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19586 12:30:36.711592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19588 12:30:36.712094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19589 12:30:36.754833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19590 12:30:36.755295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19592 12:30:36.795880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19594 12:30:36.796652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19595 12:30:36.839463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19597 12:30:36.839898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19598 12:30:36.891232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19599 12:30:36.891653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19601 12:30:36.937515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19602 12:30:36.938097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19604 12:30:36.977725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19606 12:30:36.978215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19607 12:30:37.017735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19608 12:30:37.018198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19610 12:30:37.057041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19611 12:30:37.057434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19613 12:30:37.097563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19614 12:30:37.098013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19616 12:30:37.138956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19617 12:30:37.139390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19619 12:30:37.188425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19621 12:30:37.189192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19622 12:30:37.230982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19623 12:30:37.231480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19625 12:30:37.281288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19627 12:30:37.281796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19628 12:30:37.326444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19629 12:30:37.326908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19631 12:30:37.383465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19632 12:30:37.383902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19634 12:30:37.439901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19635 12:30:37.440342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19637 12:30:37.486229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19638 12:30:37.486632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19640 12:30:37.529726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19641 12:30:37.530129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19643 12:30:37.578861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19644 12:30:37.579303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19646 12:30:37.629688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19648 12:30:37.630166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19649 12:30:37.677052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19650 12:30:37.677468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19652 12:30:37.721675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19653 12:30:37.722129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19655 12:30:37.769340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19657 12:30:37.769831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19658 12:30:37.811397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19659 12:30:37.811821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19661 12:30:37.856946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19662 12:30:37.857378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19664 12:30:37.906175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19665 12:30:37.906613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19667 12:30:37.959572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19669 12:30:37.960059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19670 12:30:38.002307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19672 12:30:38.002773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19673 12:30:38.043721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19675 12:30:38.044186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19676 12:30:38.093871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19677 12:30:38.094384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19679 12:30:38.138586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19681 12:30:38.139057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19682 12:30:38.183380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19684 12:30:38.183856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19685 12:30:38.223827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19687 12:30:38.224322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19688 12:30:38.263643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19689 12:30:38.264072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19691 12:30:38.330844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19693 12:30:38.331323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19694 12:30:38.371499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19696 12:30:38.371975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19697 12:30:38.423269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19698 12:30:38.423694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19700 12:30:38.461563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19701 12:30:38.462010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19703 12:30:38.504947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19705 12:30:38.505428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19706 12:30:38.546409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19708 12:30:38.546874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19709 12:30:38.595074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19710 12:30:38.595503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19712 12:30:38.640076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19713 12:30:38.640499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19715 12:30:38.699610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19717 12:30:38.700103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19718 12:30:38.756050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19719 12:30:38.756469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19721 12:30:38.794644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19722 12:30:38.795071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19724 12:30:38.850441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19725 12:30:38.850878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19727 12:30:38.907093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19728 12:30:38.907526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19730 12:30:38.958601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19731 12:30:38.959010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19733 12:30:39.001951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19734 12:30:39.002400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19736 12:30:39.059630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19738 12:30:39.060119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19739 12:30:39.120034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19740 12:30:39.120488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19742 12:30:39.166117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19743 12:30:39.166545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19745 12:30:39.205992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19747 12:30:39.206480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19748 12:30:39.254877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19750 12:30:39.255352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19751 12:30:39.307324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19752 12:30:39.307738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19754 12:30:39.345136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19756 12:30:39.345615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19757 12:30:39.382694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19758 12:30:39.383119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19760 12:30:39.421032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19761 12:30:39.421464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19763 12:30:39.459891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19764 12:30:39.460329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19766 12:30:39.503051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19768 12:30:39.503526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19769 12:30:39.548526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19771 12:30:39.549027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19772 12:30:39.593534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19774 12:30:39.594011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19775 12:30:39.633602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19777 12:30:39.634083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19778 12:30:39.679578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19779 12:30:39.680024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19781 12:30:39.720475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19783 12:30:39.720948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19784 12:30:39.759054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19786 12:30:39.759512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19787 12:30:39.799199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19788 12:30:39.799604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19790 12:30:39.843062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19791 12:30:39.843519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19793 12:30:39.884577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19795 12:30:39.885047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19796 12:30:39.923361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19797 12:30:39.923796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19799 12:30:39.964937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19800 12:30:39.965392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19802 12:30:40.006848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19803 12:30:40.007283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19805 12:30:40.050852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19806 12:30:40.051241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19808 12:30:40.092140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19809 12:30:40.092532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19811 12:30:40.136904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19812 12:30:40.137271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19814 12:30:40.175129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19816 12:30:40.175516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19817 12:30:40.214365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19818 12:30:40.214804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19820 12:30:40.253644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19821 12:30:40.254162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19823 12:30:40.292323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19825 12:30:40.292803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19826 12:30:40.335334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19827 12:30:40.335863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19829 12:30:40.380036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19830 12:30:40.380419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19832 12:30:40.426470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19833 12:30:40.426957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19835 12:30:40.473323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19836 12:30:40.473781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19838 12:30:40.515276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19839 12:30:40.515737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19841 12:30:40.562684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19842 12:30:40.563079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19844 12:30:40.603181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19846 12:30:40.603661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19847 12:30:40.645720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19849 12:30:40.646219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19850 12:30:40.701953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19851 12:30:40.702344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19853 12:30:40.762172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19855 12:30:40.762765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19856 12:30:40.822916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19857 12:30:40.823404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19859 12:30:40.882291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19860 12:30:40.882752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19862 12:30:40.923448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19863 12:30:40.923906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19865 12:30:40.969441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19867 12:30:40.969946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19868 12:30:41.009274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19869 12:30:41.009689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19871 12:30:41.049160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19873 12:30:41.049658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19874 12:30:41.087507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19875 12:30:41.087963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19877 12:30:41.127051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19878 12:30:41.127511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19880 12:30:41.174053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19882 12:30:41.174522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19883 12:30:41.225491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19884 12:30:41.225952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19886 12:30:41.274422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19887 12:30:41.274879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19889 12:30:41.323657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19890 12:30:41.324104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19892 12:30:41.361133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19894 12:30:41.361618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19895 12:30:41.397588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19896 12:30:41.398055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19898 12:30:41.437998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19900 12:30:41.438488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19901 12:30:41.478519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19902 12:30:41.478949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19904 12:30:41.519399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19905 12:30:41.519846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19907 12:30:41.563834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19909 12:30:41.564318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19910 12:30:41.608810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19911 12:30:41.609253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19913 12:30:41.648494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19915 12:30:41.648947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19916 12:30:41.694041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19918 12:30:41.694521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19919 12:30:41.735991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19920 12:30:41.736445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19922 12:30:41.781756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19923 12:30:41.782192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19925 12:30:41.820837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19926 12:30:41.821420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19928 12:30:41.862964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19929 12:30:41.863421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19931 12:30:41.909280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19932 12:30:41.909683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19934 12:30:41.959256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19935 12:30:41.959699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19937 12:30:42.010074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19938 12:30:42.010589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19940 12:30:42.059549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19941 12:30:42.060193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19943 12:30:42.117581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19944 12:30:42.118051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19946 12:30:42.166771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19947 12:30:42.167271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19949 12:30:42.215954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19951 12:30:42.216726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19952 12:30:42.259355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19953 12:30:42.259854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19955 12:30:42.302575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19956 12:30:42.303022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19958 12:30:42.351290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19960 12:30:42.351772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19961 12:30:42.395179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19962 12:30:42.395619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19964 12:30:42.439017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19966 12:30:42.439498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19967 12:30:42.477376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19969 12:30:42.478022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19970 12:30:42.515814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19971 12:30:42.516213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19973 12:30:42.560499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19975 12:30:42.560904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19976 12:30:42.608284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19977 12:30:42.608751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19979 12:30:42.653299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19981 12:30:42.653746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19982 12:30:42.697281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19983 12:30:42.697688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19985 12:30:42.739225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19986 12:30:42.739620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19988 12:30:42.796429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19990 12:30:42.796862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19991 12:30:42.846812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19992 12:30:42.847222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19994 12:30:42.888388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19996 12:30:42.888778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19997 12:30:42.929091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19998 12:30:42.929462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
20000 12:30:42.970357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
20001 12:30:42.970685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
20003 12:30:43.011163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
20004 12:30:43.011597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
20006 12:30:43.049833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
20007 12:30:43.050330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
20009 12:30:43.092627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
20011 12:30:43.093357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
20012 12:30:43.131418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
20013 12:30:43.131849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
20015 12:30:43.175115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
20016 12:30:43.175547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
20018 12:30:43.215192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
20019 12:30:43.215633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
20021 12:30:43.261630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
20022 12:30:43.262078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
20024 12:30:43.302962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
20025 12:30:43.303409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
20027 12:30:43.342366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
20028 12:30:43.342878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
20030 12:30:43.385518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
20031 12:30:43.386059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
20033 12:30:43.466533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
20034 12:30:43.467034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
20036 12:30:43.526663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
20037 12:30:43.527051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
20039 12:30:43.586195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
20040 12:30:43.586615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
20042 12:30:43.646976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
20044 12:30:43.647451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
20045 12:30:43.707502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
20046 12:30:43.708077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
20048 12:30:43.758323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
20050 12:30:43.758933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
20051 12:30:43.803025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
20052 12:30:43.803447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
20054 12:30:43.855781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
20056 12:30:43.856270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
20057 12:30:43.910275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
20059 12:30:43.910753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
20060 12:30:43.965535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
20062 12:30:43.966039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
20063 12:30:44.006878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
20064 12:30:44.007268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
20066 12:30:44.050110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
20068 12:30:44.050532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
20069 12:30:44.102006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
20070 12:30:44.102486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
20072 12:30:44.151021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20074 12:30:44.151658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
20075 12:30:44.197445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20076 12:30:44.197876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20078 12:30:44.242600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20079 12:30:44.242990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20081 12:30:44.293711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20082 12:30:44.294093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20084 12:30:44.339916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20085 12:30:44.340306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20087 12:30:44.385518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20088 12:30:44.385979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20090 12:30:44.447161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20092 12:30:44.447859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20093 12:30:44.509817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20094 12:30:44.510218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20096 12:30:44.571041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20097 12:30:44.571492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20099 12:30:44.632332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20101 12:30:44.632841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20102 12:30:44.694487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20103 12:30:44.694863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20105 12:30:44.757003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20106 12:30:44.757468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20108 12:30:44.817453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20109 12:30:44.817887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20111 12:30:44.874450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20112 12:30:44.874864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20114 12:30:44.936580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20116 12:30:44.937134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20117 12:30:45.001443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20118 12:30:45.001866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20120 12:30:45.063386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20121 12:30:45.063879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20123 12:30:45.124478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20125 12:30:45.124931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20126 12:30:45.182705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20127 12:30:45.183119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20129 12:30:45.239526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20130 12:30:45.239934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20132 12:30:45.298191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20134 12:30:45.298609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20135 12:30:45.355270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20136 12:30:45.355756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20138 12:30:45.413501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20139 12:30:45.414022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20141 12:30:45.473036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20142 12:30:45.473518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20144 12:30:45.532039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20146 12:30:45.532620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20147 12:30:45.593351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20149 12:30:45.594045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20150 12:30:45.643941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20152 12:30:45.644529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20153 12:30:45.685262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20155 12:30:45.685850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20156 12:30:45.725634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20157 12:30:45.726064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20159 12:30:45.767411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20160 12:30:45.767905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20162 12:30:45.810002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20163 12:30:45.810447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20165 12:30:45.849706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20166 12:30:45.850152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20168 12:30:45.890015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20169 12:30:45.890468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20171 12:30:45.930668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20173 12:30:45.931131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20174 12:30:45.970323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20175 12:30:45.970766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20177 12:30:46.030090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20179 12:30:46.030541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20180 12:30:46.090630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20181 12:30:46.091066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20183 12:30:46.150067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20184 12:30:46.150520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20186 12:30:46.208222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20188 12:30:46.208715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20189 12:30:46.268091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20190 12:30:46.268528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20192 12:30:46.324470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20194 12:30:46.324916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20195 12:30:46.365990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20196 12:30:46.366433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20198 12:30:46.407902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20200 12:30:46.408378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20201 12:30:46.447722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20202 12:30:46.448119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20204 12:30:46.486445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20205 12:30:46.486875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20207 12:30:46.526739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20208 12:30:46.527168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20210 12:30:46.571309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20211 12:30:46.571739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20213 12:30:46.611741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20214 12:30:46.612198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20216 12:30:46.652330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20218 12:30:46.652807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20219 12:30:46.693415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20220 12:30:46.693851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20222 12:30:46.735581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20223 12:30:46.736476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20225 12:30:46.791421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20226 12:30:46.792005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20228 12:30:46.846994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20230 12:30:46.847499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20231 12:30:46.901835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20233 12:30:46.902316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20234 12:30:46.958575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20235 12:30:46.958992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20237 12:30:47.001170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20239 12:30:47.001694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20240 12:30:47.053808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20241 12:30:47.054214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20243 12:30:47.114356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20244 12:30:47.114738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20246 12:30:47.174204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20247 12:30:47.174638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20249 12:30:47.234000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20251 12:30:47.234504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20252 12:30:47.294811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20254 12:30:47.295519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20255 12:30:47.345246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20256 12:30:47.345838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20258 12:30:47.401780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20260 12:30:47.402272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20261 12:30:47.442677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20262 12:30:47.443121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20264 12:30:47.491851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20265 12:30:47.492306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20267 12:30:47.546506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20269 12:30:47.546922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20270 12:30:47.598071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20271 12:30:47.598485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20273 12:30:47.657392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20274 12:30:47.657873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20276 12:30:47.710241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20278 12:30:47.710627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20279 12:30:47.772008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20281 12:30:47.772407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20282 12:30:47.818460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20284 12:30:47.818864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20285 12:30:47.861437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20287 12:30:47.861940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20288 12:30:47.906227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20290 12:30:47.906718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20291 12:30:47.958301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20292 12:30:47.958748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20294 12:30:48.015625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20295 12:30:48.016049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20297 12:30:48.070112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20299 12:30:48.070567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20300 12:30:48.131395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20301 12:30:48.131825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20303 12:30:48.190100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20304 12:30:48.190555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20306 12:30:48.248439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20308 12:30:48.248880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20309 12:30:48.307754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20310 12:30:48.308156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20312 12:30:48.366584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20313 12:30:48.367135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20315 12:30:48.426683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20316 12:30:48.427144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20318 12:30:48.487871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20319 12:30:48.488316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20321 12:30:48.582169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20322 12:30:48.582615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20324 12:30:48.642756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20325 12:30:48.643195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20327 12:30:48.702381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20328 12:30:48.703615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20330 12:30:48.762438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20331 12:30:48.762831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20333 12:30:48.821900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20334 12:30:48.822343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20336 12:30:48.882457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20337 12:30:48.882918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20339 12:30:48.943511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20340 12:30:48.943954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20342 12:30:49.005088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20343 12:30:49.005529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20345 12:30:49.064961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20347 12:30:49.065419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20348 12:30:49.126750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20349 12:30:49.127214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20351 12:30:49.188103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20352 12:30:49.188545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20354 12:30:49.248265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20355 12:30:49.248697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20357 12:30:49.309438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20358 12:30:49.309883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20360 12:30:49.367850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20362 12:30:49.368344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20363 12:30:49.428096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20365 12:30:49.428581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20366 12:30:49.486920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20367 12:30:49.487321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20369 12:30:49.543302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20370 12:30:49.543723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20372 12:30:49.591920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20373 12:30:49.592371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20375 12:30:49.638087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20376 12:30:49.638544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20378 12:30:49.681718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20379 12:30:49.682165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20381 12:30:49.740327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20382 12:30:49.740758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20384 12:30:49.799298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20385 12:30:49.799707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20387 12:30:49.862202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20388 12:30:49.862640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20390 12:30:49.922315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20392 12:30:49.922806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20393 12:30:49.983353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20394 12:30:49.983760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20396 12:30:50.044699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20398 12:30:50.045203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20399 12:30:50.104017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20401 12:30:50.104561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20402 12:30:50.166377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20403 12:30:50.166795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20405 12:30:50.226193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20406 12:30:50.226598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20408 12:30:50.278804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20410 12:30:50.279290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20411 12:30:50.314162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20413 12:30:50.314631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20414 12:30:50.348440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20416 12:30:50.348902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20417 12:30:50.383136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20419 12:30:50.383521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20420 12:30:50.422739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20421 12:30:50.423233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20423 12:30:50.461568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20424 12:30:50.462098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20426 12:30:50.495126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20427 12:30:50.495643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20429 12:30:50.532481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20431 12:30:50.533064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20432 12:30:50.571784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20433 12:30:50.572246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20435 12:30:50.609876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20436 12:30:50.610298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20438 12:30:50.647204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20439 12:30:50.647626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20441 12:30:50.685266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20442 12:30:50.685686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20444 12:30:50.723192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20445 12:30:50.723621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20447 12:30:50.759473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20448 12:30:50.759927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20450 12:30:50.797644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20452 12:30:50.798128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20453 12:30:50.834798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20454 12:30:50.835229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20456 12:30:50.871917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20457 12:30:50.872353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20459 12:30:50.909711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20460 12:30:50.910164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20462 12:30:50.947504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20464 12:30:50.947969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20465 12:30:50.985138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20466 12:30:50.985576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20468 12:30:51.021458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20469 12:30:51.021915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20471 12:30:51.057503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20472 12:30:51.058091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20474 12:30:51.117130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20475 12:30:51.117578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20477 12:30:51.170404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20478 12:30:51.170851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20480 12:30:51.223137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20481 12:30:51.223533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20483 12:30:51.283970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20485 12:30:51.284488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20486 12:30:51.340054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20487 12:30:51.340506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20489 12:30:51.389473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20491 12:30:51.389981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20492 12:30:51.431481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20493 12:30:51.431900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20495 12:30:51.472034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20496 12:30:51.472469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20498 12:30:51.514605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20499 12:30:51.515031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20501 12:30:51.566129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20502 12:30:51.566571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20504 12:30:51.616040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20505 12:30:51.616496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20507 12:30:51.663848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20508 12:30:51.664290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20510 12:30:51.721433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20511 12:30:51.721956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20513 12:30:51.782067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20514 12:30:51.782446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20516 12:30:51.841033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20517 12:30:51.841533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20519 12:30:51.898683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20520 12:30:51.899252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20522 12:30:51.954040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20524 12:30:51.954525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20525 12:30:51.997224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20526 12:30:51.997684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20528 12:30:52.037661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20529 12:30:52.038119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20531 12:30:52.079592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20533 12:30:52.080074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20534 12:30:52.121129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20535 12:30:52.121549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20537 12:30:52.177394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20539 12:30:52.177881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20540 12:30:52.235177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20541 12:30:52.235578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20543 12:30:52.277665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20544 12:30:52.278233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20546 12:30:52.318099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20547 12:30:52.318546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20549 12:30:52.365983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20550 12:30:52.366390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20552 12:30:52.412490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20554 12:30:52.412967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20555 12:30:52.462451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20556 12:30:52.462827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20558 12:30:52.509432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20559 12:30:52.509887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20561 12:30:52.558181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20562 12:30:52.558606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20564 12:30:52.606344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20566 12:30:52.606937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20567 12:30:52.654694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20568 12:30:52.655142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20570 12:30:52.702569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20571 12:30:52.702982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20573 12:30:52.759502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20574 12:30:52.759947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20576 12:30:52.806701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20577 12:30:52.807187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20579 12:30:52.850949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20580 12:30:52.851346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20582 12:30:52.893397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20583 12:30:52.893817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20585 12:30:52.938586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20586 12:30:52.939021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20588 12:30:52.983476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20589 12:30:52.983879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20591 12:30:53.038719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20592 12:30:53.039151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20594 12:30:53.086038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20595 12:30:53.086480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20597 12:30:53.123915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20599 12:30:53.124523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20600 12:30:53.162377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20601 12:30:53.162887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20603 12:30:53.202631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20604 12:30:53.203136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20606 12:30:53.242555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20607 12:30:53.242962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20609 12:30:53.290533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20611 12:30:53.290988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20612 12:30:53.329500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20614 12:30:53.330002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20615 12:30:53.374104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20616 12:30:53.374503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20618 12:30:53.425467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20620 12:30:53.425931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20621 12:30:53.471675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20622 12:30:53.472120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20624 12:30:53.514926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20625 12:30:53.515334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20627 12:30:53.555514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20628 12:30:53.555877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20630 12:30:53.601587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20632 12:30:53.602128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20633 12:30:53.645441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20634 12:30:53.645844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20636 12:30:53.719336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20637 12:30:53.719830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20639 12:30:53.766525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20640 12:30:53.766975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20642 12:30:53.805128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20643 12:30:53.805567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20645 12:30:53.851024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20646 12:30:53.851456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20648 12:30:53.911008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20649 12:30:53.911420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20651 12:30:53.950933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20652 12:30:53.951363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20654 12:30:53.992178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20655 12:30:53.992581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20657 12:30:54.036060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20658 12:30:54.036441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20660 12:30:54.089569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20661 12:30:54.090038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20663 12:30:54.146886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20664 12:30:54.147395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20666 12:30:54.198037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20668 12:30:54.198548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20669 12:30:54.238677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20670 12:30:54.239088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20672 12:30:54.277052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20673 12:30:54.277638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20675 12:30:54.321542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20676 12:30:54.322012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20678 12:30:54.359128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20679 12:30:54.359559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20681 12:30:54.398029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20682 12:30:54.398463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20684 12:30:54.435568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20685 12:30:54.436052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20687 12:30:54.477562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20689 12:30:54.478059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20690 12:30:54.522865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20691 12:30:54.523286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20693 12:30:54.566184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20694 12:30:54.566624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20696 12:30:54.614740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20697 12:30:54.615193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20699 12:30:54.653218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20700 12:30:54.653686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20702 12:30:54.691689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20703 12:30:54.692244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20705 12:30:54.730023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20706 12:30:54.730445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20708 12:30:54.769578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20709 12:30:54.770079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20711 12:30:54.811021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20712 12:30:54.811483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20714 12:30:54.851348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20716 12:30:54.851846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20717 12:30:54.893377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20718 12:30:54.893856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20720 12:30:54.931857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20721 12:30:54.932305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20723 12:30:54.982593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20724 12:30:54.982980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20726 12:30:55.029260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20727 12:30:55.029656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20729 12:30:55.069261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20731 12:30:55.069914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20732 12:30:55.108432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20734 12:30:55.108839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20735 12:30:55.146353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20736 12:30:55.146862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20738 12:30:55.187109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20740 12:30:55.187589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20741 12:30:55.237795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20742 12:30:55.238236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20744 12:30:55.295779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20745 12:30:55.296272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20747 12:30:55.355264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20748 12:30:55.355647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20750 12:30:55.413525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20751 12:30:55.414018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20753 12:30:55.458257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20755 12:30:55.458650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20756 12:30:55.499242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20757 12:30:55.499625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20759 12:30:55.543103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20760 12:30:55.543509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20762 12:30:55.581630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20764 12:30:55.582034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20765 12:30:55.619244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20767 12:30:55.619657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20768 12:30:55.655163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20770 12:30:55.655865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20771 12:30:55.694141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20773 12:30:55.694701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20774 12:30:55.734629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20776 12:30:55.735106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20777 12:30:55.779512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20778 12:30:55.779933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20780 12:30:55.826652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20781 12:30:55.827057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20783 12:30:55.885359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20784 12:30:55.885811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20786 12:30:55.931080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20787 12:30:55.931547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20789 12:30:55.970625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20791 12:30:55.971329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20792 12:30:56.011234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20793 12:30:56.011648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20795 12:30:56.068285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20797 12:30:56.068941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20798 12:30:56.110220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20800 12:30:56.110596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20801 12:30:56.152970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20803 12:30:56.153462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20804 12:30:56.191271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20805 12:30:56.191756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20807 12:30:56.233561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20809 12:30:56.233986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20810 12:30:56.274364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20811 12:30:56.274803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20813 12:30:56.312927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20815 12:30:56.313422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20816 12:30:56.357886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20817 12:30:56.358315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20819 12:30:56.398428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20820 12:30:56.398944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20822 12:30:56.435757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20824 12:30:56.436444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20825 12:30:56.492612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20827 12:30:56.493346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20828 12:30:56.534892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20829 12:30:56.535364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20831 12:30:56.575329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20832 12:30:56.575900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20834 12:30:56.617761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20835 12:30:56.618344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20837 12:30:56.672084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20838 12:30:56.672601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20840 12:30:56.710722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20842 12:30:56.711192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20843 12:30:56.753282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20844 12:30:56.753801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20846 12:30:56.810653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20848 12:30:56.811243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20849 12:30:56.850792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20850 12:30:56.851349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20852 12:30:56.891387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20854 12:30:56.891855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20855 12:30:56.941826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20856 12:30:56.942257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20858 12:30:56.986150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20860 12:30:56.986690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20861 12:30:57.024938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20863 12:30:57.025674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20864 12:30:57.061635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20865 12:30:57.062093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20867 12:30:57.103675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20869 12:30:57.104075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20870 12:30:57.141827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20871 12:30:57.142254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20873 12:30:57.182651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20874 12:30:57.183044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20876 12:30:57.223212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20877 12:30:57.223648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20879 12:30:57.266010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20880 12:30:57.266443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20882 12:30:57.309140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20883 12:30:57.309565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20885 12:30:57.361798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20886 12:30:57.362188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20888 12:30:57.403744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20889 12:30:57.404140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20891 12:30:57.454526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20892 12:30:57.454931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20894 12:30:57.513162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20895 12:30:57.513573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20897 12:30:57.571143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20898 12:30:57.571578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20900 12:30:57.617574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20901 12:30:57.617996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20903 12:30:57.659526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20904 12:30:57.659944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20906 12:30:57.705815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20907 12:30:57.706249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20909 12:30:57.748940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20910 12:30:57.749405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20912 12:30:57.792546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20914 12:30:57.793034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20915 12:30:57.844939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20916 12:30:57.845345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20918 12:30:57.888144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20919 12:30:57.888586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20921 12:30:57.929869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20922 12:30:57.930259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20924 12:30:57.967778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20926 12:30:57.968234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20927 12:30:58.006741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20928 12:30:58.007133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20930 12:30:58.046000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20931 12:30:58.046552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20933 12:30:58.087643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20935 12:30:58.088132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20936 12:30:58.141465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20937 12:30:58.141916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20939 12:30:58.187791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20941 12:30:58.188275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20942 12:30:58.225773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20944 12:30:58.226255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20945 12:30:58.266121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20946 12:30:58.266577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20948 12:30:58.314335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20950 12:30:58.314814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20951 12:30:58.353689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20953 12:30:58.354167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20954 12:30:58.397521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20955 12:30:58.397969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20957 12:30:58.443414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20959 12:30:58.443896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20960 12:30:58.485641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20962 12:30:58.486048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20963 12:30:58.528402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20965 12:30:58.529184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20966 12:30:58.576428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20968 12:30:58.576908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20969 12:30:58.626746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20971 12:30:58.627240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20972 12:30:58.671168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20974 12:30:58.671653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20975 12:30:58.713727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20977 12:30:58.714495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20978 12:30:58.766753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20979 12:30:58.767326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20981 12:30:58.834865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20982 12:30:58.835318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20984 12:30:58.878128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20985 12:30:58.878572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20987 12:30:58.921940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20988 12:30:58.922399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20990 12:30:58.967716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20991 12:30:58.968167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20993 12:30:59.015697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20994 12:30:59.016094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20996 12:30:59.062239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20997 12:30:59.062736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20999 12:30:59.108643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
21000 12:30:59.109140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
21002 12:30:59.158085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
21004 12:30:59.158575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
21005 12:30:59.199665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
21006 12:30:59.200132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
21008 12:30:59.241716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
21009 12:30:59.242182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
21011 12:30:59.286015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
21012 12:30:59.286506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
21014 12:30:59.339835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
21015 12:30:59.340260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
21017 12:30:59.383710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
21018 12:30:59.384106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
21020 12:30:59.430605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
21021 12:30:59.430984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
21023 12:30:59.474564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
21024 12:30:59.475035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
21026 12:30:59.515745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
21027 12:30:59.516131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
21029 12:30:59.558577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
21030 12:30:59.559049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
21032 12:30:59.607331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
21033 12:30:59.607810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
21035 12:30:59.666233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
21037 12:30:59.666807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
21038 12:30:59.723102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
21039 12:30:59.723540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
21041 12:30:59.775762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
21043 12:30:59.776425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
21044 12:30:59.816595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
21046 12:30:59.817368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
21047 12:30:59.859737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
21048 12:30:59.860205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
21050 12:30:59.902688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
21051 12:30:59.903133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
21053 12:30:59.951042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
21054 12:30:59.951488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
21056 12:30:59.994186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
21058 12:30:59.994669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
21059 12:31:00.046324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
21060 12:31:00.046777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
21062 12:31:00.087444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
21063 12:31:00.087942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
21065 12:31:00.130752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
21066 12:31:00.131196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
21068 12:31:00.176054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
21070 12:31:00.176515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
21071 12:31:00.219972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
21072 12:31:00.220413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21074 12:31:00.258674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21075 12:31:00.259138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21077 12:31:00.298900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21078 12:31:00.299343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21080 12:31:00.342420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21082 12:31:00.343509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21083 12:31:00.381774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21085 12:31:00.382258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21086 12:31:00.418913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21087 12:31:00.419358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21089 12:31:00.459502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21090 12:31:00.459903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21092 12:31:00.499048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21094 12:31:00.499553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21095 12:31:00.536585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21097 12:31:00.537199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21098 12:31:00.583500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21099 12:31:00.583992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21101 12:31:00.630109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21102 12:31:00.630493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21104 12:31:00.675098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21105 12:31:00.675538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21107 12:31:00.721317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21108 12:31:00.721681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21110 12:31:00.766415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21112 12:31:00.766792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21113 12:31:00.806808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21114 12:31:00.807212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21116 12:31:00.849497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21118 12:31:00.849993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21119 12:31:00.897710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21121 12:31:00.898135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21122 12:31:00.950398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21123 12:31:00.950782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21125 12:31:00.998844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21126 12:31:00.999256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21128 12:31:01.051690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21129 12:31:01.052169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21131 12:31:01.095501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21132 12:31:01.095969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21134 12:31:01.140495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21136 12:31:01.140888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21137 12:31:01.182802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21138 12:31:01.183252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21140 12:31:01.225389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21141 12:31:01.225798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21143 12:31:01.271083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21145 12:31:01.271498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21146 12:31:01.313467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21147 12:31:01.314001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21149 12:31:01.355812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21150 12:31:01.356306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21152 12:31:01.398707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21153 12:31:01.399181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21155 12:31:01.439589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21156 12:31:01.440041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21158 12:31:01.479424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21160 12:31:01.479883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21161 12:31:01.519670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21162 12:31:01.520153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21164 12:31:01.563168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21166 12:31:01.563731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21167 12:31:01.607717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21168 12:31:01.608201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21170 12:31:01.660950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21171 12:31:01.661480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21173 12:31:01.701997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21174 12:31:01.702379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21176 12:31:01.745727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21178 12:31:01.746391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21179 12:31:01.788733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21180 12:31:01.789289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21182 12:31:01.827992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21184 12:31:01.828470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21185 12:31:01.866740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21186 12:31:01.867203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21188 12:31:01.905107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21189 12:31:01.905696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21191 12:31:01.939197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21192 12:31:01.939704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21194 12:31:01.977620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21195 12:31:01.978138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21197 12:31:02.015864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21199 12:31:02.016620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21200 12:31:02.053198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21201 12:31:02.053575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21203 12:31:02.090402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21204 12:31:02.090942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21206 12:31:02.130169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21208 12:31:02.130722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21209 12:31:02.184334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21211 12:31:02.184999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21212 12:31:02.221733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21213 12:31:02.222233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21215 12:31:02.256754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21216 12:31:02.257231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21218 12:31:02.293128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21220 12:31:02.293617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21221 12:31:02.329672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21222 12:31:02.330097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21224 12:31:02.371238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21225 12:31:02.371722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21227 12:31:02.409075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21229 12:31:02.409797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21230 12:31:02.446344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21231 12:31:02.446777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21233 12:31:02.481931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21235 12:31:02.482416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21236 12:31:02.518477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21237 12:31:02.518891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21239 12:31:02.555265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21240 12:31:02.555715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21242 12:31:02.591716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21243 12:31:02.592236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21245 12:31:02.635501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21247 12:31:02.635975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21248 12:31:02.686766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21249 12:31:02.687245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21251 12:31:02.745425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21253 12:31:02.746017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21254 12:31:02.794390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21255 12:31:02.794827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21257 12:31:02.836301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21259 12:31:02.836779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21260 12:31:02.876381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21262 12:31:02.876868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21263 12:31:02.917362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21264 12:31:02.917763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21266 12:31:02.967878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21267 12:31:02.968375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21269 12:31:03.013764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21271 12:31:03.014317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21272 12:31:03.059231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21273 12:31:03.059668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21275 12:31:03.103412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21277 12:31:03.104093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21278 12:31:03.149927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21279 12:31:03.150369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21281 12:31:03.189118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21282 12:31:03.189578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21284 12:31:03.232019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21285 12:31:03.232462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21287 12:31:03.273160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21288 12:31:03.273717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21290 12:31:03.318797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21292 12:31:03.319235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21293 12:31:03.368448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21295 12:31:03.369064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21296 12:31:03.410177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21297 12:31:03.410619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21299 12:31:03.458361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21300 12:31:03.458821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21302 12:31:03.503114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21303 12:31:03.503548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21305 12:31:03.545146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21307 12:31:03.545659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21308 12:31:03.587112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21309 12:31:03.587564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21311 12:31:03.626694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21312 12:31:03.627277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21314 12:31:03.671668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21315 12:31:03.672135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21317 12:31:03.719755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21318 12:31:03.720211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21320 12:31:03.774506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21321 12:31:03.774960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21323 12:31:03.822977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21324 12:31:03.823415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21326 12:31:03.874226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21328 12:31:03.874711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21329 12:31:03.959408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21331 12:31:03.959873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21332 12:31:04.020528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21333 12:31:04.021036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21335 12:31:04.071447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21336 12:31:04.071923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21338 12:31:04.122750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21339 12:31:04.123215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21341 12:31:04.178216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21342 12:31:04.178677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21344 12:31:04.229858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21345 12:31:04.230304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21347 12:31:04.273374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21348 12:31:04.273811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21350 12:31:04.327083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21351 12:31:04.327523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21353 12:31:04.380590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21355 12:31:04.381089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21356 12:31:04.437167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21358 12:31:04.437679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21359 12:31:04.490622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21360 12:31:04.491086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21362 12:31:04.543870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21363 12:31:04.544302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21365 12:31:04.591544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21366 12:31:04.591986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21368 12:31:04.637884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21369 12:31:04.638349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21371 12:31:04.685692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21372 12:31:04.686153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21374 12:31:04.733163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21375 12:31:04.733620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21377 12:31:04.786487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21379 12:31:04.786967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21380 12:31:04.845549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21381 12:31:04.846009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21383 12:31:04.902542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21384 12:31:04.903012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21386 12:31:04.962516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21388 12:31:04.962979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21389 12:31:05.019591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21390 12:31:05.019991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21392 12:31:05.071286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21393 12:31:05.071733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21395 12:31:05.120963 <47>[ 214.478351] systemd-journald[109]: Sent WATCHDOG=1 notification.
21396 12:31:05.127419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21397 12:31:05.127874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21399 12:31:05.174273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21400 12:31:05.174723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21402 12:31:05.226782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21403 12:31:05.227229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21405 12:31:05.279349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21407 12:31:05.279840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21408 12:31:05.327908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21410 12:31:05.328402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21411 12:31:05.380655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21413 12:31:05.381153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21414 12:31:05.431345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21415 12:31:05.431804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21417 12:31:05.481934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21418 12:31:05.482378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21420 12:31:05.534046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21421 12:31:05.534489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21423 12:31:05.586252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21424 12:31:05.586674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21426 12:31:05.637946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21427 12:31:05.638389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21429 12:31:05.685480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21430 12:31:05.685932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21432 12:31:05.734463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21433 12:31:05.734876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21435 12:31:05.782081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21436 12:31:05.782506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21438 12:31:05.833898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21440 12:31:05.834382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21441 12:31:05.892150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21443 12:31:05.892649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21444 12:31:05.949436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21445 12:31:05.949917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21447 12:31:06.003068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21448 12:31:06.003535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21450 12:31:06.055126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21452 12:31:06.055615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21453 12:31:06.110914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21454 12:31:06.111356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21456 12:31:06.164012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21458 12:31:06.164501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21459 12:31:06.218576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21460 12:31:06.218999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21462 12:31:06.266335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21463 12:31:06.266776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21465 12:31:06.324261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21466 12:31:06.324720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21468 12:31:06.379363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21469 12:31:06.379819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21471 12:31:06.438182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21472 12:31:06.438624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21474 12:31:06.488464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21476 12:31:06.488968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21477 12:31:06.543681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21479 12:31:06.544184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21480 12:31:06.594207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21481 12:31:06.594647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21483 12:31:06.647666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21484 12:31:06.648115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21486 12:31:06.700447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21488 12:31:06.700922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21489 12:31:06.755324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21490 12:31:06.755762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21492 12:31:06.809804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21493 12:31:06.810243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21495 12:31:06.853889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21496 12:31:06.854350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21498 12:31:06.895000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21500 12:31:06.895484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21501 12:31:06.947825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21503 12:31:06.948260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21504 12:31:06.999843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21505 12:31:07.000301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21507 12:31:07.057954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21508 12:31:07.058394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21510 12:31:07.110510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21511 12:31:07.110951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21513 12:31:07.162722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21514 12:31:07.163192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21516 12:31:07.208434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21518 12:31:07.208944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21519 12:31:07.262373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21521 12:31:07.262799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21522 12:31:07.315382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21523 12:31:07.315808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21525 12:31:07.368448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21527 12:31:07.368924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21528 12:31:07.418648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21529 12:31:07.419111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21531 12:31:07.470619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21532 12:31:07.471053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21534 12:31:07.525167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21535 12:31:07.525628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21537 12:31:07.577881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21539 12:31:07.578367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21540 12:31:07.628451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21542 12:31:07.628938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21543 12:31:07.679660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21545 12:31:07.680101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21546 12:31:07.731267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21548 12:31:07.731696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21549 12:31:07.785177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21551 12:31:07.785671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21552 12:31:07.835304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21554 12:31:07.835765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21555 12:31:07.886420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21556 12:31:07.886911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21558 12:31:07.939373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21559 12:31:07.939768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21561 12:31:07.991270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21562 12:31:07.991722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21564 12:31:08.042396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21565 12:31:08.042833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21567 12:31:08.092007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21568 12:31:08.092396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21570 12:31:08.143775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21571 12:31:08.144328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21573 12:31:08.195322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21575 12:31:08.196057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21576 12:31:08.246255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21577 12:31:08.246689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21579 12:31:08.297631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21580 12:31:08.298084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21582 12:31:08.349685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21583 12:31:08.350145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21585 12:31:08.394604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21586 12:31:08.395010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21588 12:31:08.438681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21589 12:31:08.439255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21591 12:31:08.486122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21592 12:31:08.486604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21594 12:31:08.537481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21596 12:31:08.537920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21597 12:31:08.590228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21599 12:31:08.590683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21600 12:31:08.634324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21601 12:31:08.634765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21603 12:31:08.683301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21604 12:31:08.683737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21606 12:31:08.738935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21607 12:31:08.739381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21609 12:31:08.790786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21610 12:31:08.791258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21612 12:31:08.839162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21613 12:31:08.839604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21615 12:31:08.883529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21616 12:31:08.883960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21618 12:31:08.927683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21619 12:31:08.928141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21621 12:31:08.981869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21622 12:31:08.982330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21624 12:31:09.051383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21625 12:31:09.051822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21627 12:31:09.106195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21628 12:31:09.106615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21630 12:31:09.156495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21632 12:31:09.157151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21633 12:31:09.207443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21634 12:31:09.207802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21636 12:31:09.269156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21637 12:31:09.269521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21639 12:31:09.326120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21640 12:31:09.326523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21642 12:31:09.378936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21644 12:31:09.379716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21645 12:31:09.433782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21647 12:31:09.434266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21648 12:31:09.479680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21650 12:31:09.480084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21651 12:31:09.534412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21652 12:31:09.534801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21654 12:31:09.583928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21655 12:31:09.584318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21657 12:31:09.641218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21659 12:31:09.641678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21660 12:31:09.696934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21662 12:31:09.697424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21663 12:31:09.754497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21665 12:31:09.754973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21666 12:31:09.818618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21667 12:31:09.819056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21669 12:31:09.871389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21670 12:31:09.871834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21672 12:31:09.922240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21674 12:31:09.922723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21675 12:31:09.967304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21677 12:31:09.967785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21678 12:31:10.024241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21680 12:31:10.024818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21681 12:31:10.080602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21683 12:31:10.081078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21684 12:31:10.134783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21686 12:31:10.135271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21687 12:31:10.182105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21688 12:31:10.182479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21690 12:31:10.227282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21691 12:31:10.227724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21693 12:31:10.266170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21694 12:31:10.266604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21696 12:31:10.310646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21697 12:31:10.311093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21699 12:31:10.351043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21700 12:31:10.351556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21702 12:31:10.393174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21703 12:31:10.393629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21705 12:31:10.434814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21706 12:31:10.435272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21708 12:31:10.486251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21709 12:31:10.486712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21711 12:31:10.547542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21712 12:31:10.547983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21714 12:31:10.591224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21715 12:31:10.591664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21717 12:31:10.632368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21719 12:31:10.633775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21720 12:31:10.691318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21722 12:31:10.691984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21723 12:31:10.747733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21724 12:31:10.748161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21726 12:31:10.807885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21727 12:31:10.808293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21729 12:31:10.866759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21731 12:31:10.867193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21732 12:31:10.926022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21734 12:31:10.926501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21735 12:31:10.983546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21737 12:31:10.984013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21738 12:31:11.041747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21740 12:31:11.042159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21741 12:31:11.100426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21743 12:31:11.100903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21744 12:31:11.159302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21745 12:31:11.159699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21747 12:31:11.215684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21748 12:31:11.216107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21750 12:31:11.266257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21751 12:31:11.266689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21753 12:31:11.308229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21755 12:31:11.308974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21756 12:31:11.354314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21757 12:31:11.354715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21759 12:31:11.405474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21761 12:31:11.405904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21762 12:31:11.450470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21763 12:31:11.450903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21765 12:31:11.495833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21766 12:31:11.496394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21768 12:31:11.543144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21770 12:31:11.543629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21771 12:31:11.597984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21773 12:31:11.598468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21774 12:31:11.645186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21776 12:31:11.645690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21777 12:31:11.691218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21778 12:31:11.691601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21780 12:31:11.742081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21782 12:31:11.742465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21783 12:31:11.788553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21785 12:31:11.789197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21786 12:31:11.835408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21787 12:31:11.835874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21789 12:31:11.884219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21791 12:31:11.884645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21792 12:31:11.923280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21793 12:31:11.923721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21795 12:31:11.966573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21796 12:31:11.966973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21798 12:31:12.015188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21799 12:31:12.015618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21801 12:31:12.066986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21802 12:31:12.067538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21804 12:31:12.114865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21805 12:31:12.115338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21807 12:31:12.156810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21808 12:31:12.157258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21810 12:31:12.205196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21811 12:31:12.205674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21813 12:31:12.259772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21814 12:31:12.260236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21816 12:31:12.309346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21818 12:31:12.309779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21819 12:31:12.353659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21821 12:31:12.354248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21822 12:31:12.394148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21823 12:31:12.394657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21825 12:31:12.438226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21826 12:31:12.438675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21828 12:31:12.487412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21829 12:31:12.487930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21831 12:31:12.544542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21833 12:31:12.545061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21834 12:31:12.602190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21835 12:31:12.602679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21837 12:31:12.660503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21839 12:31:12.661845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21840 12:31:12.719401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21841 12:31:12.719855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21843 12:31:12.778501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21844 12:31:12.778891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21846 12:31:12.837025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21847 12:31:12.837459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21849 12:31:12.895180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21851 12:31:12.895664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21852 12:31:12.951380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21853 12:31:12.951946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21855 12:31:13.011063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21856 12:31:13.011526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21858 12:31:13.067606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21859 12:31:13.068080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21861 12:31:13.125775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21862 12:31:13.126151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21864 12:31:13.169811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21865 12:31:13.170195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21867 12:31:13.227811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21868 12:31:13.228262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21870 12:31:13.283808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21871 12:31:13.284273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21873 12:31:13.329785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21874 12:31:13.330221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21876 12:31:13.387290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21877 12:31:13.387697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21879 12:31:13.437963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21880 12:31:13.438402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21882 12:31:13.482996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21884 12:31:13.483417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21885 12:31:13.537594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21886 12:31:13.538053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21888 12:31:13.583735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21889 12:31:13.584259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21891 12:31:13.633565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21892 12:31:13.634013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21894 12:31:13.681164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21895 12:31:13.681614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21897 12:31:13.730330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21899 12:31:13.730915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21900 12:31:13.774693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21901 12:31:13.775282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21903 12:31:13.823218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21904 12:31:13.823594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21906 12:31:13.875364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21907 12:31:13.875764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21909 12:31:13.928312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21911 12:31:13.928762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21912 12:31:13.976024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21914 12:31:13.976519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21915 12:31:14.028588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21917 12:31:14.029070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21918 12:31:14.077414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21919 12:31:14.077879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21921 12:31:14.127905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21922 12:31:14.128353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21924 12:31:14.198864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21926 12:31:14.199344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21927 12:31:14.247836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21928 12:31:14.248279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21930 12:31:14.292385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21931 12:31:14.292828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21933 12:31:14.334688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21934 12:31:14.335075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21936 12:31:14.385023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21938 12:31:14.385498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21939 12:31:14.434701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21940 12:31:14.435128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21942 12:31:14.486585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21943 12:31:14.486954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21945 12:31:14.530591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21946 12:31:14.531010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21948 12:31:14.577062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21949 12:31:14.577515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21951 12:31:14.618421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21952 12:31:14.618843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21954 12:31:14.661806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21955 12:31:14.662358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21957 12:31:14.708464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21959 12:31:14.708897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21960 12:31:14.757975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21961 12:31:14.758415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21963 12:31:14.803078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21964 12:31:14.803519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21966 12:31:14.843021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21967 12:31:14.843536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21969 12:31:14.882838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21970 12:31:14.883283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21972 12:31:14.923361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21974 12:31:14.923855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21975 12:31:14.979532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21976 12:31:14.980122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21978 12:31:15.030475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21979 12:31:15.030916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21981 12:31:15.073117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21982 12:31:15.073585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21984 12:31:15.115825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21986 12:31:15.116234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21987 12:31:15.155533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21988 12:31:15.156107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21990 12:31:15.196482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21992 12:31:15.196950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21993 12:31:15.235582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21994 12:31:15.236020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21996 12:31:15.274054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21997 12:31:15.274447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21999 12:31:15.313547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
22000 12:31:15.314001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
22002 12:31:15.354060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
22003 12:31:15.354467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
22005 12:31:15.392202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
22007 12:31:15.392804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
22008 12:31:15.433788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
22010 12:31:15.434276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
22011 12:31:15.472387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
22013 12:31:15.472870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
22014 12:31:15.511831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
22015 12:31:15.512230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
22017 12:31:15.551750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
22018 12:31:15.552192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
22020 12:31:15.593155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
22021 12:31:15.593556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
22023 12:31:15.633491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
22025 12:31:15.633996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
22026 12:31:15.683498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
22027 12:31:15.683938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
22029 12:31:15.726147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
22031 12:31:15.726629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
22032 12:31:15.765322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
22034 12:31:15.765812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
22035 12:31:15.804455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
22037 12:31:15.804913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
22038 12:31:15.852466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
22040 12:31:15.853042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
22041 12:31:15.891387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
22042 12:31:15.891810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
22044 12:31:15.937249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
22045 12:31:15.937675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
22047 12:31:15.996875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
22049 12:31:15.997366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
22050 12:31:16.060028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
22051 12:31:16.060476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
22053 12:31:16.121373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
22054 12:31:16.121767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
22056 12:31:16.181461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
22057 12:31:16.181899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
22059 12:31:16.239463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
22060 12:31:16.239882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
22062 12:31:16.298142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
22063 12:31:16.298622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
22065 12:31:16.347582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
22066 12:31:16.348007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
22068 12:31:16.387741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
22070 12:31:16.388241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
22071 12:31:16.427201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22072 12:31:16.427638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
22074 12:31:16.466771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22075 12:31:16.467207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22077 12:31:16.511877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22078 12:31:16.512324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22080 12:31:16.561233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22082 12:31:16.561719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22083 12:31:16.619876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22084 12:31:16.620282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22086 12:31:16.672000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22088 12:31:16.672446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22089 12:31:16.718974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22090 12:31:16.719397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22092 12:31:16.773288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22093 12:31:16.773727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22095 12:31:16.826585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22096 12:31:16.826981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22098 12:31:16.886442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22099 12:31:16.886858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22101 12:31:16.947511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22102 12:31:16.947938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22104 12:31:16.995001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22105 12:31:16.995516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22107 12:31:17.040796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22109 12:31:17.041305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22110 12:31:17.090912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22111 12:31:17.091444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22113 12:31:17.134448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22114 12:31:17.134869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22116 12:31:17.175812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22118 12:31:17.176304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22119 12:31:17.217846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22120 12:31:17.218269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22122 12:31:17.256438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22124 12:31:17.256914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22125 12:31:17.300929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22126 12:31:17.301357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22128 12:31:17.346397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22129 12:31:17.346821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22131 12:31:17.383696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22133 12:31:17.384291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22134 12:31:17.425725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22135 12:31:17.426161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22137 12:31:17.466213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22139 12:31:17.466616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22140 12:31:17.506968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22141 12:31:17.507413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22143 12:31:17.547708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22144 12:31:17.548110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22146 12:31:17.587233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22148 12:31:17.587707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22149 12:31:17.643607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22150 12:31:17.644047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22152 12:31:17.683589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22154 12:31:17.684058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22155 12:31:17.741886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22156 12:31:17.742324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22158 12:31:17.787411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22159 12:31:17.787849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22161 12:31:17.835385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22162 12:31:17.835779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22164 12:31:17.880074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22166 12:31:17.880550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22167 12:31:17.923092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22169 12:31:17.923569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22170 12:31:17.970693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22171 12:31:17.971105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22173 12:31:18.013516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22174 12:31:18.013963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22176 12:31:18.057031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22178 12:31:18.057501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22179 12:31:18.102253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22180 12:31:18.102647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22182 12:31:18.151581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22183 12:31:18.152095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22185 12:31:18.206390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22186 12:31:18.206817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22188 12:31:18.255333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22189 12:31:18.255784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22191 12:31:18.299070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22193 12:31:18.299558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22194 12:31:18.347190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22195 12:31:18.347633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22197 12:31:18.391171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22198 12:31:18.391665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22200 12:31:18.434742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22201 12:31:18.435153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22203 12:31:18.472087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22204 12:31:18.472527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22206 12:31:18.515480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22207 12:31:18.515895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22209 12:31:18.560462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22211 12:31:18.560943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22212 12:31:18.603852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22214 12:31:18.604243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22215 12:31:18.654906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22216 12:31:18.655390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22218 12:31:18.706859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22220 12:31:18.707489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22221 12:31:18.755092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22222 12:31:18.755508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22224 12:31:18.793124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22225 12:31:18.793574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22227 12:31:18.836420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22229 12:31:18.836955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22230 12:31:18.888278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22232 12:31:18.888764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22233 12:31:18.929929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22234 12:31:18.930359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22236 12:31:18.990591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22237 12:31:18.991042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22239 12:31:19.045440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22240 12:31:19.045885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22242 12:31:19.093344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22243 12:31:19.093798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22245 12:31:19.137440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22246 12:31:19.137852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22248 12:31:19.182042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22250 12:31:19.182511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22251 12:31:19.225692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22252 12:31:19.226268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22254 12:31:19.299694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22255 12:31:19.300129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22257 12:31:19.352272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22259 12:31:19.352764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22260 12:31:19.410877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22261 12:31:19.411296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22263 12:31:19.453499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22264 12:31:19.454178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22266 12:31:19.498495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22267 12:31:19.498906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22269 12:31:19.539106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22270 12:31:19.539538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22272 12:31:19.586109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22273 12:31:19.586520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22275 12:31:19.634302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22277 12:31:19.634828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22278 12:31:19.678311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22279 12:31:19.678768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22281 12:31:19.719771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22282 12:31:19.720332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22284 12:31:19.761849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22286 12:31:19.762332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22287 12:31:19.805751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22288 12:31:19.806201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22290 12:31:19.851419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22292 12:31:19.851915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22293 12:31:19.899791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22294 12:31:19.900279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22296 12:31:19.947283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22297 12:31:19.947684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22299 12:31:19.995535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22301 12:31:19.995960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22302 12:31:20.040058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22303 12:31:20.040507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22305 12:31:20.083355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22306 12:31:20.083804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22308 12:31:20.123175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22309 12:31:20.123554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22311 12:31:20.162970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22312 12:31:20.163414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22314 12:31:20.204464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22316 12:31:20.205044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22317 12:31:20.247816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22319 12:31:20.248271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22320 12:31:20.288990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22321 12:31:20.289424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22323 12:31:20.333291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22325 12:31:20.333796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22326 12:31:20.386083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22327 12:31:20.386575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22329 12:31:20.437788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22331 12:31:20.438182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22332 12:31:20.478978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22333 12:31:20.479439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22335 12:31:20.522830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22336 12:31:20.523332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22338 12:31:20.564114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22340 12:31:20.564821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22341 12:31:20.618080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22342 12:31:20.618508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22344 12:31:20.663301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22346 12:31:20.663784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22347 12:31:20.707105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22348 12:31:20.707568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22350 12:31:20.746345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22351 12:31:20.746790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22353 12:31:20.783047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22354 12:31:20.783473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22356 12:31:20.827173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22357 12:31:20.827595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22359 12:31:20.877789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22360 12:31:20.878233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22362 12:31:20.933801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22363 12:31:20.934238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22365 12:31:20.978097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22366 12:31:20.978520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22368 12:31:21.027588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22369 12:31:21.028024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22371 12:31:21.073159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22373 12:31:21.073629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22374 12:31:21.115124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22375 12:31:21.115547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22377 12:31:21.157939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22379 12:31:21.158374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22380 12:31:21.206100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22382 12:31:21.206585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22383 12:31:21.257973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22385 12:31:21.258396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22386 12:31:21.303552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22387 12:31:21.304009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22389 12:31:21.351099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22390 12:31:21.351668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22392 12:31:21.390638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22393 12:31:21.391042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22395 12:31:21.429794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22396 12:31:21.430234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22398 12:31:21.470105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22399 12:31:21.470637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22401 12:31:21.507902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22403 12:31:21.508385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22404 12:31:21.550884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22406 12:31:21.551357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22407 12:31:21.591411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22408 12:31:21.591837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22410 12:31:21.642288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22411 12:31:21.642670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22413 12:31:21.691683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22414 12:31:21.692308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22416 12:31:21.750253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22417 12:31:21.750694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22419 12:31:21.809185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22420 12:31:21.809605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22422 12:31:21.851488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22423 12:31:21.851925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22425 12:31:21.894070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22426 12:31:21.894537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22428 12:31:21.930926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22429 12:31:21.931403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22431 12:31:21.973761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22432 12:31:21.974320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22434 12:31:22.017790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22435 12:31:22.018190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22437 12:31:22.062556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22438 12:31:22.062987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22440 12:31:22.110956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22441 12:31:22.111358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22443 12:31:22.158765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22445 12:31:22.159258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22446 12:31:22.212481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22448 12:31:22.213295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22449 12:31:22.262884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22450 12:31:22.263316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22452 12:31:22.315675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22453 12:31:22.316070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22455 12:31:22.370453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22457 12:31:22.370907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22458 12:31:22.423745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22459 12:31:22.424182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22461 12:31:22.485467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22462 12:31:22.485910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22464 12:31:22.542658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22465 12:31:22.543060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22467 12:31:22.597377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22468 12:31:22.597802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22470 12:31:22.649434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22471 12:31:22.649888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22473 12:31:22.693093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22475 12:31:22.693575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22476 12:31:22.743006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22477 12:31:22.743443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22479 12:31:22.794200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22481 12:31:22.794581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22482 12:31:22.852033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22483 12:31:22.852408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22485 12:31:22.911840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22486 12:31:22.912225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22488 12:31:22.967853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22489 12:31:22.968269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22491 12:31:23.015859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22492 12:31:23.016314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22494 12:31:23.074514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22495 12:31:23.074976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22497 12:31:23.127655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22499 12:31:23.128106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22500 12:31:23.178045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22501 12:31:23.178500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22503 12:31:23.226978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22504 12:31:23.227420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22506 12:31:23.271048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22507 12:31:23.271481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22509 12:31:23.319521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22510 12:31:23.319967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22512 12:31:23.367882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22513 12:31:23.368339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22515 12:31:23.422483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22516 12:31:23.422918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22518 12:31:23.475127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22519 12:31:23.475543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22521 12:31:23.529455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22523 12:31:23.529919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22524 12:31:23.583149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22525 12:31:23.583607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22527 12:31:23.636335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22529 12:31:23.636926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22530 12:31:23.689335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22532 12:31:23.689790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22533 12:31:23.742462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22535 12:31:23.742935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22536 12:31:23.790958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22537 12:31:23.791400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22539 12:31:23.834304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22541 12:31:23.834765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22542 12:31:23.883233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22543 12:31:23.883645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22545 12:31:23.933006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22546 12:31:23.933397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22548 12:31:23.975986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22549 12:31:23.976383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22551 12:31:24.035185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22553 12:31:24.035577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22554 12:31:24.095510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22555 12:31:24.095909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22557 12:31:24.151794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22558 12:31:24.152197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22560 12:31:24.206819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22561 12:31:24.207211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22563 12:31:24.262408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22564 12:31:24.262814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22566 12:31:24.319536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22567 12:31:24.320022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22569 12:31:24.390464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22570 12:31:24.390897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22572 12:31:24.458668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22574 12:31:24.459123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22575 12:31:24.508635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22577 12:31:24.509206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22578 12:31:24.557145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22579 12:31:24.557692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22581 12:31:24.610893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22583 12:31:24.611319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22584 12:31:24.659666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22585 12:31:24.660113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22587 12:31:24.707725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22588 12:31:24.708167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22590 12:31:24.752069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22592 12:31:24.752549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22593 12:31:24.799288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22594 12:31:24.799722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22596 12:31:24.845717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22597 12:31:24.846140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22599 12:31:24.891405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22600 12:31:24.891818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22602 12:31:24.939355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22603 12:31:24.939719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22605 12:31:24.986825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22607 12:31:24.987306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22608 12:31:25.033705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22609 12:31:25.034158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22611 12:31:25.081722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22613 12:31:25.082193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22614 12:31:25.130904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22616 12:31:25.131287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22617 12:31:25.175632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22618 12:31:25.176075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22620 12:31:25.222444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22621 12:31:25.222883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22623 12:31:25.267387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22624 12:31:25.267836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22626 12:31:25.327228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22628 12:31:25.327611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22629 12:31:25.382026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22630 12:31:25.382474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22632 12:31:25.427094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22633 12:31:25.427508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22635 12:31:25.470948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22636 12:31:25.471401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22638 12:31:25.514421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22639 12:31:25.514857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22641 12:31:25.571105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22642 12:31:25.571543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22644 12:31:25.630251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22646 12:31:25.630733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22647 12:31:25.689234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22648 12:31:25.689777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22650 12:31:25.745937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22651 12:31:25.746376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22653 12:31:25.803474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22654 12:31:25.804027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22656 12:31:25.862241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22657 12:31:25.862633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22659 12:31:25.920962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22660 12:31:25.921360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22662 12:31:25.978826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22663 12:31:25.979224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22665 12:31:26.037227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22666 12:31:26.037665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22668 12:31:26.095571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22669 12:31:26.096053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22671 12:31:26.154788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22672 12:31:26.155333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22674 12:31:26.214017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22675 12:31:26.214416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22677 12:31:26.271089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22679 12:31:26.271519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22680 12:31:26.318221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22681 12:31:26.318660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22683 12:31:26.365036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22684 12:31:26.365448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22686 12:31:26.417751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22687 12:31:26.418228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22689 12:31:26.470569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22690 12:31:26.471006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22692 12:31:26.523674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22693 12:31:26.524118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22695 12:31:26.575685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22696 12:31:26.576131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22698 12:31:26.627354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22700 12:31:26.627842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22701 12:31:26.678462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22702 12:31:26.678932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22704 12:31:26.735976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22705 12:31:26.736381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22707 12:31:26.791663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22708 12:31:26.792130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22710 12:31:26.835256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22712 12:31:26.835712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22713 12:31:26.890140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22714 12:31:26.890521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22716 12:31:26.937045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22717 12:31:26.937521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22719 12:31:26.985686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22720 12:31:26.986100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22722 12:31:27.041505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22723 12:31:27.041978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22725 12:31:27.096127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22726 12:31:27.096536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22728 12:31:27.137675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22729 12:31:27.138113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22731 12:31:27.186899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22732 12:31:27.187343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22734 12:31:27.235516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22735 12:31:27.235964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22737 12:31:27.282300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22738 12:31:27.282743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22740 12:31:27.330853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22741 12:31:27.331279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22743 12:31:27.386631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22745 12:31:27.387013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22746 12:31:27.435446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22748 12:31:27.436230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22749 12:31:27.484346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22751 12:31:27.484829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22752 12:31:27.533585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22753 12:31:27.534031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22755 12:31:27.581146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22757 12:31:27.581600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22758 12:31:27.624614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22760 12:31:27.625055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22761 12:31:27.670500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22762 12:31:27.670896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22764 12:31:27.722087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22765 12:31:27.722558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22767 12:31:27.769677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22768 12:31:27.770123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22770 12:31:27.828438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22771 12:31:27.828912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22773 12:31:27.877467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22775 12:31:27.877956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22776 12:31:27.926493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22777 12:31:27.926932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22779 12:31:27.982054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22780 12:31:27.982539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22782 12:31:28.035331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22784 12:31:28.035775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22785 12:31:28.082288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22786 12:31:28.082710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22788 12:31:28.127600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22789 12:31:28.128001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22791 12:31:28.174763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22792 12:31:28.175212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22794 12:31:28.219426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22796 12:31:28.219874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22797 12:31:28.267416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22798 12:31:28.267836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22800 12:31:28.311369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22801 12:31:28.311816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22803 12:31:28.357449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22805 12:31:28.357849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22806 12:31:28.407134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22807 12:31:28.407565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22809 12:31:28.453328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22810 12:31:28.453762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22812 12:31:28.500557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22814 12:31:28.501034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22815 12:31:28.542554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22816 12:31:28.542966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22818 12:31:28.587320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22820 12:31:28.587760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22821 12:31:28.637807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22822 12:31:28.638301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22824 12:31:28.693687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22826 12:31:28.694141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22827 12:31:28.753217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22828 12:31:28.753636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22830 12:31:28.811474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22831 12:31:28.811929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22833 12:31:28.858504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22834 12:31:28.858960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22836 12:31:28.899002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22837 12:31:28.899446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22839 12:31:28.949977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22840 12:31:28.950413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22842 12:31:29.004521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22844 12:31:29.004983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22845 12:31:29.062968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22846 12:31:29.063415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22848 12:31:29.121861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22850 12:31:29.122273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22851 12:31:29.181204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22852 12:31:29.181677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22854 12:31:29.238619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22855 12:31:29.239070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22857 12:31:29.297356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22858 12:31:29.297762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22860 12:31:29.355929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22862 12:31:29.356342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22863 12:31:29.414897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22865 12:31:29.415386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22866 12:31:29.473726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22867 12:31:29.474197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22869 12:31:29.553954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22870 12:31:29.554354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22872 12:31:29.595300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22874 12:31:29.595744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22875 12:31:29.649000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22876 12:31:29.649452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22878 12:31:29.698170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22879 12:31:29.698598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22881 12:31:29.750381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22882 12:31:29.750810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22884 12:31:29.798716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22885 12:31:29.799126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22887 12:31:29.843504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22888 12:31:29.843967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22890 12:31:29.890334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22891 12:31:29.890796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22893 12:31:29.932922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22894 12:31:29.933365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22896 12:31:29.988016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22898 12:31:29.988520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22899 12:31:30.037627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22900 12:31:30.038101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22902 12:31:30.090020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22903 12:31:30.090460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22905 12:31:30.151632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22906 12:31:30.152080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22908 12:31:30.206519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22909 12:31:30.206946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22911 12:31:30.254458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22912 12:31:30.254896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22914 12:31:30.305687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22915 12:31:30.306151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22917 12:31:30.355948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22918 12:31:30.356346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22920 12:31:30.409851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22922 12:31:30.410288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22923 12:31:30.459511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22924 12:31:30.459944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22926 12:31:30.511632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22927 12:31:30.512034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22929 12:31:30.562460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22930 12:31:30.562896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22932 12:31:30.618602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22933 12:31:30.619043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22935 12:31:30.668572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22937 12:31:30.669043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22938 12:31:30.721234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22939 12:31:30.721642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22941 12:31:30.773692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22942 12:31:30.774159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22944 12:31:30.825119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22946 12:31:30.825616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22947 12:31:30.873548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22948 12:31:30.874029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22950 12:31:30.915573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22951 12:31:30.916014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22953 12:31:30.956138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22954 12:31:30.956577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22956 12:31:30.998283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22957 12:31:30.998730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22959 12:31:31.042987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22960 12:31:31.043424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22962 12:31:31.085726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22963 12:31:31.086156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22965 12:31:31.125873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22966 12:31:31.126326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22968 12:31:31.165607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22969 12:31:31.166108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22971 12:31:31.206091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22972 12:31:31.206523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22974 12:31:31.249257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22975 12:31:31.249624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22977 12:31:31.302071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22978 12:31:31.302508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22980 12:31:31.348385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22982 12:31:31.348863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22983 12:31:31.391332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22985 12:31:31.391812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22986 12:31:31.438216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22988 12:31:31.438657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22989 12:31:31.487443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22990 12:31:31.487905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22992 12:31:31.533724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22993 12:31:31.534182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22995 12:31:31.586673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22996 12:31:31.587071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22998 12:31:31.637379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22999 12:31:31.637834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
23001 12:31:31.679434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
23002 12:31:31.679901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
23004 12:31:31.718746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
23005 12:31:31.719201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
23007 12:31:31.766327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
23008 12:31:31.766747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
23010 12:31:31.823321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
23011 12:31:31.823714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
23013 12:31:31.875394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
23014 12:31:31.875850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
23016 12:31:31.922753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
23017 12:31:31.923193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
23019 12:31:31.970789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
23020 12:31:31.971233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
23022 12:31:32.022827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
23023 12:31:32.023294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
23025 12:31:32.074157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
23026 12:31:32.074584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
23028 12:31:32.123046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
23030 12:31:32.123479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
23031 12:31:32.177439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
23032 12:31:32.177839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
23034 12:31:32.235284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
23036 12:31:32.236013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
23037 12:31:32.294741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
23039 12:31:32.295467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
23040 12:31:32.353370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
23042 12:31:32.353825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
23043 12:31:32.408530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
23045 12:31:32.409011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
23046 12:31:32.457944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
23047 12:31:32.458401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
23049 12:31:32.507257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
23050 12:31:32.507744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
23052 12:31:32.555396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
23053 12:31:32.555832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
23055 12:31:32.597468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
23056 12:31:32.597905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
23058 12:31:32.639419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
23059 12:31:32.639870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
23061 12:31:32.682010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
23062 12:31:32.682441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
23064 12:31:32.726262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
23065 12:31:32.726676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
23067 12:31:32.782256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
23069 12:31:32.782751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
23070 12:31:32.836429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
23072 12:31:32.836939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
23073 12:31:32.894967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23074 12:31:32.895410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23076 12:31:32.954583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23077 12:31:32.954996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23079 12:31:33.004397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23081 12:31:33.005092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23082 12:31:33.055648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23084 12:31:33.056059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23085 12:31:33.101990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23086 12:31:33.102488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23088 12:31:33.147034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23090 12:31:33.147517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23091 12:31:33.193515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23093 12:31:33.194020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23094 12:31:33.242942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23096 12:31:33.243440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23097 12:31:33.290528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23098 12:31:33.290953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23100 12:31:33.329958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23101 12:31:33.330393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23103 12:31:33.378052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23104 12:31:33.378451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23106 12:31:33.423512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23108 12:31:33.423971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23109 12:31:33.470914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23111 12:31:33.471517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23112 12:31:33.521145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23113 12:31:33.521582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23115 12:31:33.563908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23117 12:31:33.564302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23118 12:31:33.618629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23119 12:31:33.619019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23121 12:31:33.671585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23122 12:31:33.672015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23124 12:31:33.726031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23125 12:31:33.726486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23127 12:31:33.769448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23128 12:31:33.769903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23130 12:31:33.810111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23131 12:31:33.810498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23133 12:31:33.854573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23134 12:31:33.854998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23136 12:31:33.893394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23137 12:31:33.893811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23139 12:31:33.938103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23140 12:31:33.938544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23142 12:31:33.980436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23144 12:31:33.980911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23145 12:31:34.031298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23146 12:31:34.031742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23148 12:31:34.089526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23150 12:31:34.090027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23151 12:31:34.144226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23153 12:31:34.144750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23154 12:31:34.198165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23156 12:31:34.198606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23157 12:31:34.245686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23159 12:31:34.246177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23160 12:31:34.304255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23162 12:31:34.304656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23163 12:31:34.355675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23164 12:31:34.356101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23166 12:31:34.401898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23168 12:31:34.402371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23169 12:31:34.448033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23170 12:31:34.448478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23172 12:31:34.500417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23174 12:31:34.501021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23175 12:31:34.550326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23176 12:31:34.550770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23178 12:31:34.606906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23179 12:31:34.607345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23181 12:31:34.682890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23182 12:31:34.683340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23184 12:31:34.742209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23185 12:31:34.742654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23187 12:31:34.803098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23188 12:31:34.803536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23190 12:31:34.863921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23191 12:31:34.864372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23193 12:31:34.923632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23194 12:31:34.924069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23196 12:31:34.984437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23198 12:31:34.984845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23199 12:31:35.046735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23200 12:31:35.047131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23202 12:31:35.107754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23203 12:31:35.108209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23205 12:31:35.168345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23207 12:31:35.168824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23208 12:31:35.228090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23209 12:31:35.228494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23211 12:31:35.288110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23213 12:31:35.288594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23214 12:31:35.341865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23215 12:31:35.342437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23217 12:31:35.389216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23218 12:31:35.389712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23220 12:31:35.443459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23221 12:31:35.443853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23223 12:31:35.493557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23224 12:31:35.493982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23226 12:31:35.553155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23227 12:31:35.553709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23229 12:31:35.611948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23230 12:31:35.612358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23232 12:31:35.655596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23233 12:31:35.656059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23235 12:31:35.702346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23236 12:31:35.702809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23238 12:31:35.743335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23239 12:31:35.743710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23241 12:31:35.797116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23243 12:31:35.797914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23244 12:31:35.847289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23246 12:31:35.847965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23247 12:31:35.899082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23248 12:31:35.899603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23250 12:31:35.946547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23251 12:31:35.946954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23253 12:31:35.990859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23254 12:31:35.991313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23256 12:31:36.039625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23258 12:31:36.040099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23259 12:31:36.085687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23260 12:31:36.086141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23262 12:31:36.132613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23264 12:31:36.133047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23265 12:31:36.180549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23267 12:31:36.181165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23268 12:31:36.225430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23269 12:31:36.225973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23271 12:31:36.270044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23272 12:31:36.270557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23274 12:31:36.317740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23275 12:31:36.318241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23277 12:31:36.366333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23279 12:31:36.367104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23280 12:31:36.415678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23281 12:31:36.416123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23283 12:31:36.466033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23285 12:31:36.466515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23286 12:31:36.509695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23287 12:31:36.510249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23289 12:31:36.562037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23290 12:31:36.562483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23292 12:31:36.601029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23293 12:31:36.601466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23295 12:31:36.653816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23296 12:31:36.654277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23298 12:31:36.700024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23299 12:31:36.700587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23301 12:31:36.745193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23302 12:31:36.745590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23304 12:31:36.795425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23305 12:31:36.795847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23307 12:31:36.838386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23308 12:31:36.838775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23310 12:31:36.888068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23311 12:31:36.888492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23313 12:31:36.930502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23314 12:31:36.930928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23316 12:31:36.970920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23318 12:31:36.971383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23319 12:31:37.009731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23321 12:31:37.010314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23322 12:31:37.049431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23323 12:31:37.049953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23325 12:31:37.090839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23326 12:31:37.091222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23328 12:31:37.127015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23329 12:31:37.127403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23331 12:31:37.164953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23332 12:31:37.165387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23334 12:31:37.203443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23336 12:31:37.203919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23337 12:31:37.243846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23338 12:31:37.244306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23340 12:31:37.284040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23342 12:31:37.284429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23343 12:31:37.323131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23345 12:31:37.323776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23346 12:31:37.362572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23347 12:31:37.363061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23349 12:31:37.401151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23350 12:31:37.401632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23352 12:31:37.441820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23353 12:31:37.442231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23355 12:31:37.487013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23357 12:31:37.487495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23358 12:31:37.533428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23359 12:31:37.533851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23361 12:31:37.578035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23362 12:31:37.578472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23364 12:31:37.621934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23366 12:31:37.622424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23367 12:31:37.661360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23368 12:31:37.661801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23370 12:31:37.706025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23371 12:31:37.706458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23373 12:31:37.752938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23374 12:31:37.757783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23376 12:31:37.799069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23377 12:31:37.799489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23379 12:31:37.852285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23380 12:31:37.852730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23382 12:31:37.898403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23383 12:31:37.898830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23385 12:31:37.936804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23386 12:31:37.937230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23388 12:31:37.978031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23389 12:31:37.978451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23391 12:31:38.020301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23393 12:31:38.020767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23394 12:31:38.070259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23395 12:31:38.070705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23397 12:31:38.116861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23398 12:31:38.117277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23400 12:31:38.158231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23401 12:31:38.158663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23403 12:31:38.202309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23404 12:31:38.202748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23406 12:31:38.245892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23407 12:31:38.246305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23409 12:31:38.290507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23410 12:31:38.290904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23412 12:31:38.339370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23413 12:31:38.339809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23415 12:31:38.384012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23416 12:31:38.384456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23418 12:31:38.427258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23419 12:31:38.427641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23421 12:31:38.471620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23422 12:31:38.472145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23424 12:31:38.515998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23425 12:31:38.516405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23427 12:31:38.561502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23428 12:31:38.561947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23430 12:31:38.604485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23432 12:31:38.604914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23433 12:31:38.647653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23434 12:31:38.648102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23436 12:31:38.689778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23437 12:31:38.690270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23439 12:31:38.728469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23441 12:31:38.728958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23442 12:31:38.771574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23444 12:31:38.772072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23445 12:31:38.823666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23446 12:31:38.824216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23448 12:31:38.873724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23450 12:31:38.874309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23451 12:31:38.915422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23453 12:31:38.916096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23454 12:31:38.962240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23455 12:31:38.962665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23457 12:31:39.003114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23458 12:31:39.003520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23460 12:31:39.043773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23461 12:31:39.044298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23463 12:31:39.086727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23464 12:31:39.087165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23466 12:31:39.127490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23468 12:31:39.127913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23469 12:31:39.178907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23470 12:31:39.179292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23472 12:31:39.229940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23474 12:31:39.230426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23475 12:31:39.276404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23477 12:31:39.276873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23478 12:31:39.320512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23480 12:31:39.320933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23481 12:31:39.361714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23482 12:31:39.362160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23484 12:31:39.402513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23485 12:31:39.402964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23487 12:31:39.445235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23489 12:31:39.445716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23490 12:31:39.491370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23491 12:31:39.491804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23493 12:31:39.539335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23495 12:31:39.539798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23496 12:31:39.585723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23497 12:31:39.586145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23499 12:31:39.643512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23501 12:31:39.644109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23502 12:31:39.691798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23503 12:31:39.692249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23505 12:31:39.761883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23506 12:31:39.762271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23508 12:31:39.805704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23510 12:31:39.806186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23511 12:31:39.854574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23512 12:31:39.855013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23514 12:31:39.906993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23515 12:31:39.907417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23517 12:31:39.965190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23518 12:31:39.965625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23520 12:31:40.022420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23521 12:31:40.022858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23523 12:31:40.079621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23524 12:31:40.080088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23526 12:31:40.138489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23527 12:31:40.138904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23529 12:31:40.198748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23530 12:31:40.199206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23532 12:31:40.258913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23533 12:31:40.259361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23535 12:31:40.318211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23536 12:31:40.318617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23538 12:31:40.371860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23539 12:31:40.372373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23541 12:31:40.417747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23543 12:31:40.418240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23544 12:31:40.459429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23545 12:31:40.459860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23547 12:31:40.508068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23549 12:31:40.508451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23550 12:31:40.554609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23551 12:31:40.555053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23553 12:31:40.603518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23554 12:31:40.603961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23556 12:31:40.651927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23557 12:31:40.652338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23559 12:31:40.701309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23560 12:31:40.701744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23562 12:31:40.749201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23564 12:31:40.749663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23565 12:31:40.799738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23567 12:31:40.800187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23568 12:31:40.846315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23569 12:31:40.846798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23571 12:31:40.890134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23573 12:31:40.890600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23574 12:31:40.928967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23576 12:31:40.929439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23577 12:31:40.970000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23578 12:31:40.970428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23580 12:31:41.018334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23581 12:31:41.018781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23583 12:31:41.069903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23584 12:31:41.070346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23586 12:31:41.112990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23587 12:31:41.113431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23589 12:31:41.150622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23590 12:31:41.151053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23592 12:31:41.190251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23593 12:31:41.190697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23595 12:31:41.230088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23596 12:31:41.230646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23598 12:31:41.273137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23599 12:31:41.273564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23601 12:31:41.315124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23602 12:31:41.315569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23604 12:31:41.358301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23605 12:31:41.358743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23607 12:31:41.399639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23608 12:31:41.400042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23610 12:31:41.438918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23611 12:31:41.439374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23613 12:31:41.479820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23614 12:31:41.480270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23616 12:31:41.518168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23618 12:31:41.518660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23619 12:31:41.555219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23620 12:31:41.555657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23622 12:31:41.595919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23624 12:31:41.596403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23625 12:31:41.638209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23626 12:31:41.638663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23628 12:31:41.681931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23629 12:31:41.682389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23631 12:31:41.722182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23632 12:31:41.722566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23634 12:31:41.758591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23635 12:31:41.758997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23637 12:31:41.799089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23638 12:31:41.799475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23640 12:31:41.837706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23642 12:31:41.838149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23643 12:31:41.879586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23644 12:31:41.880095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23646 12:31:41.925100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23647 12:31:41.925506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23649 12:31:41.967967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23650 12:31:41.968428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23652 12:31:42.013746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23653 12:31:42.014204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23655 12:31:42.058056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23656 12:31:42.058521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23658 12:31:42.100523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23660 12:31:42.100996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23661 12:31:42.144379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23663 12:31:42.145249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23664 12:31:42.187282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23665 12:31:42.187709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23667 12:31:42.233591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23668 12:31:42.234006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23670 12:31:42.290298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23671 12:31:42.290739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23673 12:31:42.333778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23674 12:31:42.334189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23676 12:31:42.383290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23678 12:31:42.383690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23679 12:31:42.431880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23680 12:31:42.432334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23682 12:31:42.470540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23683 12:31:42.470984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23685 12:31:42.512352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23687 12:31:42.512825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23688 12:31:42.548778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23690 12:31:42.549212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23691 12:31:42.585500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23692 12:31:42.585958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23694 12:31:42.631180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23695 12:31:42.631681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23697 12:31:42.679058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23698 12:31:42.679552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23700 12:31:42.719285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23701 12:31:42.719856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23703 12:31:42.763866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23704 12:31:42.764382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23706 12:31:42.819756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23707 12:31:42.820194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23709 12:31:42.879435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23710 12:31:42.879865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23712 12:31:42.929726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23713 12:31:42.930157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23715 12:31:42.978263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23716 12:31:42.978701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23718 12:31:43.019321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23719 12:31:43.019776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23721 12:31:43.066428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23722 12:31:43.066890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23724 12:31:43.107205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23726 12:31:43.107690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23727 12:31:43.145908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23729 12:31:43.146382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23730 12:31:43.184518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23732 12:31:43.185216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23733 12:31:43.232422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23735 12:31:43.232819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23736 12:31:43.269689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23738 12:31:43.270124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23739 12:31:43.318068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23740 12:31:43.318614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23742 12:31:43.369592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23743 12:31:43.370015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23745 12:31:43.411461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23746 12:31:43.411880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23748 12:31:43.450944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23749 12:31:43.451367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23751 12:31:43.490619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23752 12:31:43.491019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23754 12:31:43.528486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23756 12:31:43.528999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23757 12:31:43.574300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23759 12:31:43.574722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23760 12:31:43.617672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23762 12:31:43.618146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23763 12:31:43.665843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23764 12:31:43.666282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23766 12:31:43.709929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23767 12:31:43.710349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23769 12:31:43.751476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23770 12:31:43.751933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23772 12:31:43.794646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23774 12:31:43.795115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23775 12:31:43.833798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23776 12:31:43.834247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23778 12:31:43.877724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23779 12:31:43.878165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23781 12:31:43.919750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23782 12:31:43.920189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23784 12:31:43.961913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23785 12:31:43.962372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23787 12:31:44.001194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23788 12:31:44.001704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23790 12:31:44.045976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23791 12:31:44.046479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23793 12:31:44.090560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23794 12:31:44.090976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23796 12:31:44.151676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23798 12:31:44.152120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23799 12:31:44.211429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23800 12:31:44.211802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23802 12:31:44.267074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23803 12:31:44.267479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23805 12:31:44.317791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23806 12:31:44.318184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23808 12:31:44.361889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23809 12:31:44.362302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23811 12:31:44.402449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23812 12:31:44.402820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23814 12:31:44.450544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23816 12:31:44.451024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23817 12:31:44.488383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23819 12:31:44.488825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23820 12:31:44.530244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23821 12:31:44.530650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23823 12:31:44.571574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23825 12:31:44.572045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23826 12:31:44.613731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23827 12:31:44.614295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23829 12:31:44.653870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23830 12:31:44.654286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23832 12:31:44.699818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23833 12:31:44.700250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23835 12:31:44.749327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23836 12:31:44.749858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23838 12:31:44.795702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23839 12:31:44.796157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23841 12:31:44.837661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23842 12:31:44.838087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23844 12:31:44.920375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23846 12:31:44.920853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23847 12:31:44.973221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23848 12:31:44.973721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23850 12:31:45.021661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23852 12:31:45.022139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23853 12:31:45.074122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23854 12:31:45.074495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23856 12:31:45.116042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23857 12:31:45.116441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23859 12:31:45.170005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23860 12:31:45.170414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23862 12:31:45.223286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23863 12:31:45.223689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23865 12:31:45.273120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23866 12:31:45.273524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23868 12:31:45.313020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23870 12:31:45.313510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23871 12:31:45.355572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23872 12:31:45.356010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23874 12:31:45.400036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23875 12:31:45.400463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23877 12:31:45.437864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23878 12:31:45.438301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23880 12:31:45.475718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23882 12:31:45.476178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23883 12:31:45.520226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23885 12:31:45.520928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23886 12:31:45.563003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23887 12:31:45.563494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23889 12:31:45.608399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23891 12:31:45.609092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23892 12:31:45.655459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23893 12:31:45.656039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23895 12:31:45.698459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23896 12:31:45.698891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23898 12:31:45.747372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23899 12:31:45.747976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23901 12:31:45.789642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23902 12:31:45.790143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23904 12:31:45.842994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23906 12:31:45.843666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23907 12:31:45.893425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23908 12:31:45.893930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23910 12:31:45.936474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23912 12:31:45.936920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23913 12:31:45.977896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23915 12:31:45.978368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23916 12:31:46.019371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23917 12:31:46.019827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23919 12:31:46.062055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23920 12:31:46.062510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23922 12:31:46.101554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23923 12:31:46.102103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23925 12:31:46.141815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23927 12:31:46.142267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23928 12:31:46.181261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23930 12:31:46.181881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23931 12:31:46.219913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23932 12:31:46.220348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23934 12:31:46.262658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23935 12:31:46.263181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23937 12:31:46.308455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23939 12:31:46.308942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23940 12:31:46.350038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23942 12:31:46.350509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23943 12:31:46.393665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23944 12:31:46.394184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23946 12:31:46.435275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23947 12:31:46.435745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23949 12:31:46.478323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23950 12:31:46.478753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23952 12:31:46.516930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23953 12:31:46.517414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23955 12:31:46.556288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23957 12:31:46.556777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23958 12:31:46.597372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23959 12:31:46.597768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23961 12:31:46.638187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23962 12:31:46.638571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23964 12:31:46.676225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23966 12:31:46.676639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23967 12:31:46.733271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23968 12:31:46.733739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23970 12:31:46.790531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23971 12:31:46.791018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23973 12:31:46.847992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23975 12:31:46.848426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23976 12:31:46.904410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23978 12:31:46.904815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23979 12:31:46.962236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23980 12:31:46.962669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23982 12:31:47.019732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23983 12:31:47.020122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23985 12:31:47.079609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23987 12:31:47.080061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23988 12:31:47.138114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23989 12:31:47.138493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23991 12:31:47.194739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23992 12:31:47.195222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23994 12:31:47.252480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23996 12:31:47.252888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23997 12:31:47.303408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23998 12:31:47.303798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
24000 12:31:47.359181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
24001 12:31:47.359562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
24003 12:31:47.417446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
24004 12:31:47.417926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
24006 12:31:47.472591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
24008 12:31:47.472992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
24009 12:31:47.516371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
24011 12:31:47.516765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
24012 12:31:47.558443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
24013 12:31:47.558839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
24015 12:31:47.611103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
24016 12:31:47.611532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
24018 12:31:47.661711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
24020 12:31:47.662154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
24021 12:31:47.711437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
24022 12:31:47.711847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
24024 12:31:47.762617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
24025 12:31:47.763056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
24027 12:31:47.806833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
24028 12:31:47.807313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
24030 12:31:47.854573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
24031 12:31:47.854995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
24033 12:31:47.905574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
24034 12:31:47.905992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
24036 12:31:47.949678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
24037 12:31:47.950110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
24039 12:31:48.003675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
24040 12:31:48.004123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
24042 12:31:48.056314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
24044 12:31:48.056819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
24045 12:31:48.109951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
24047 12:31:48.110419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
24048 12:31:48.162914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
24050 12:31:48.163354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
24051 12:31:48.203370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
24052 12:31:48.203789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
24054 12:31:48.251073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
24055 12:31:48.251511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
24057 12:31:48.293731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
24058 12:31:48.294248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
24060 12:31:48.341274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
24061 12:31:48.341788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
24063 12:31:48.390126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
24064 12:31:48.390565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
24066 12:31:48.440013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
24067 12:31:48.440405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
24069 12:31:48.485844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
24070 12:31:48.486280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
24072 12:31:48.533563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24073 12:31:48.533976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24075 12:31:48.578753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24077 12:31:48.579233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24078 12:31:48.632087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24080 12:31:48.632577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24081 12:31:48.693387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24082 12:31:48.693851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24084 12:31:48.754268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24085 12:31:48.754680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24087 12:31:48.806422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24089 12:31:48.806899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24090 12:31:48.859899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24091 12:31:48.860367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24093 12:31:48.911885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24094 12:31:48.912343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24096 12:31:48.963013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24097 12:31:48.963427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24099 12:31:49.021552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24100 12:31:49.021999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24102 12:31:49.075524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24104 12:31:49.076012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24105 12:31:49.130741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24106 12:31:49.131187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24108 12:31:49.183885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24109 12:31:49.184297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24111 12:31:49.236595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24113 12:31:49.237074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24114 12:31:49.296024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24115 12:31:49.296622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24117 12:31:49.356091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24119 12:31:49.356474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24120 12:31:49.409713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24121 12:31:49.410104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24123 12:31:49.460260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24125 12:31:49.460798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24126 12:31:49.502997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24128 12:31:49.503486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24129 12:31:49.548048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24130 12:31:49.548479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24132 12:31:49.587682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24134 12:31:49.588280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24135 12:31:49.630213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24136 12:31:49.630651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24138 12:31:49.671050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24139 12:31:49.671500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24141 12:31:49.720026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24142 12:31:49.720435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24144 12:31:49.758818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24145 12:31:49.759249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24147 12:31:49.800267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24148 12:31:49.800695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24150 12:31:49.851717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24151 12:31:49.852167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24153 12:31:49.889223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24154 12:31:49.889667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24156 12:31:49.938209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24157 12:31:49.938658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24159 12:31:50.009718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24160 12:31:50.010160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24162 12:31:50.053204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24163 12:31:50.053667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24165 12:31:50.091350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24166 12:31:50.091791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24168 12:31:50.134700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24169 12:31:50.135092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24171 12:31:50.179919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24172 12:31:50.180362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24174 12:31:50.223049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24175 12:31:50.223498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24177 12:31:50.275102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24178 12:31:50.275523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24180 12:31:50.327039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24181 12:31:50.327491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24183 12:31:50.378334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24185 12:31:50.378700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24186 12:31:50.429297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24188 12:31:50.429757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24189 12:31:50.474968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24190 12:31:50.475408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24192 12:31:50.522374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24193 12:31:50.522807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24195 12:31:50.570459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24196 12:31:50.570861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24198 12:31:50.619401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24199 12:31:50.619809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24201 12:31:50.664397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24203 12:31:50.664831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24204 12:31:50.710292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24205 12:31:50.710804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24207 12:31:50.759598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24208 12:31:50.760020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24210 12:31:50.803999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24212 12:31:50.804776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24213 12:31:50.855667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24215 12:31:50.856299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24216 12:31:50.900356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24218 12:31:50.900792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24219 12:31:50.940483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24221 12:31:50.940974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24222 12:31:50.979569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24223 12:31:50.980011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24225 12:31:51.018763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24226 12:31:51.019160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24228 12:31:51.058262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24229 12:31:51.058675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24231 12:31:51.102301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24232 12:31:51.102756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24234 12:31:51.158265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24236 12:31:51.158653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24237 12:31:51.217817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24238 12:31:51.218392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24240 12:31:51.259098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24242 12:31:51.259581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24243 12:31:51.301633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24244 12:31:51.302078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24246 12:31:51.351292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24248 12:31:51.351765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24249 12:31:51.399001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24250 12:31:51.399382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24252 12:31:51.454302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24253 12:31:51.454755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24255 12:31:51.499134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24256 12:31:51.499570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24258 12:31:51.539601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24260 12:31:51.540080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24261 12:31:51.585379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24263 12:31:51.585858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24264 12:31:51.623868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24265 12:31:51.624272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24267 12:31:51.674930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24268 12:31:51.675417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24270 12:31:51.717015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24272 12:31:51.717500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24273 12:31:51.755760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24274 12:31:51.756164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24276 12:31:51.805518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24277 12:31:51.806089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24279 12:31:51.853240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24280 12:31:51.853663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24282 12:31:51.897172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24283 12:31:51.897685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24285 12:31:51.945768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24286 12:31:51.946217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24288 12:31:51.994487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24289 12:31:51.994922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24291 12:31:52.051831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24292 12:31:52.052295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24294 12:31:52.098637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24296 12:31:52.099082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24297 12:31:52.146984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24298 12:31:52.147458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24300 12:31:52.198007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24301 12:31:52.198386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24303 12:31:52.247593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24304 12:31:52.248026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24306 12:31:52.290632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24307 12:31:52.291061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24309 12:31:52.331700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24310 12:31:52.332193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24312 12:31:52.381394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24314 12:31:52.381837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24315 12:31:52.427431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24317 12:31:52.427914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24318 12:31:52.481715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24319 12:31:52.482146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24321 12:31:52.534975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24322 12:31:52.535444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24324 12:31:52.582889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24325 12:31:52.583366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24327 12:31:52.625814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24328 12:31:52.626174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24330 12:31:52.670068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24331 12:31:52.670515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24333 12:31:52.713675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24334 12:31:52.714104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24336 12:31:52.757872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24337 12:31:52.758219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24339 12:31:52.799708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24340 12:31:52.800183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24342 12:31:52.846710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24343 12:31:52.847095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24345 12:31:52.894892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24346 12:31:52.895328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24348 12:31:52.956507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24350 12:31:52.956985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24351 12:31:53.009060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24352 12:31:53.009492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24354 12:31:53.059920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24355 12:31:53.060364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24357 12:31:53.097952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24358 12:31:53.098446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24360 12:31:53.135956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24361 12:31:53.136390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24363 12:31:53.177400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24364 12:31:53.177844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24366 12:31:53.218916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24367 12:31:53.219352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24369 12:31:53.259625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24370 12:31:53.260058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24372 12:31:53.308284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24374 12:31:53.308715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24375 12:31:53.358293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24376 12:31:53.358740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24378 12:31:53.411269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24379 12:31:53.411734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24381 12:31:53.458175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24382 12:31:53.460644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24384 12:31:53.507042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24385 12:31:53.507460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24387 12:31:53.552414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24389 12:31:53.552852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24390 12:31:53.607464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24391 12:31:53.607906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24393 12:31:53.657497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24394 12:31:53.657952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24396 12:31:53.712994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24398 12:31:53.713445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24399 12:31:53.766443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24400 12:31:53.766853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24402 12:31:53.819889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24403 12:31:53.820307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24405 12:31:53.878672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24406 12:31:53.879196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24408 12:31:53.937079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24410 12:31:53.937885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24411 12:31:53.985041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24412 12:31:53.985478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24414 12:31:54.039315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24415 12:31:54.039761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24417 12:31:54.086831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24418 12:31:54.087285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24420 12:31:54.133803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24421 12:31:54.134255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24423 12:31:54.178130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24424 12:31:54.178539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24426 12:31:54.230592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24427 12:31:54.230990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24429 12:31:54.290886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24431 12:31:54.291368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24432 12:31:54.349121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24433 12:31:54.349541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24435 12:31:54.406789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24436 12:31:54.407184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24438 12:31:54.465779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24439 12:31:54.466222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24441 12:31:54.523148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24442 12:31:54.523540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24444 12:31:54.580306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24446 12:31:54.580767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24447 12:31:54.638367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24448 12:31:54.638761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24450 12:31:54.697523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24451 12:31:54.698013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24453 12:31:54.755270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24454 12:31:54.755667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24456 12:31:54.812395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24458 12:31:54.812887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24459 12:31:54.870268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24461 12:31:54.870743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24462 12:31:54.928506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24464 12:31:54.928966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24465 12:31:54.986471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24466 12:31:54.986866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24468 12:31:55.043717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24470 12:31:55.044173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24471 12:31:55.106196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24472 12:31:55.106585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24474 12:31:55.159094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24476 12:31:55.159577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24477 12:31:55.205430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24478 12:31:55.205884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24480 12:31:55.257919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24481 12:31:55.258360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24483 12:31:55.307690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24485 12:31:55.308173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24486 12:31:55.354477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24487 12:31:55.354905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24489 12:31:55.399083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24490 12:31:55.399520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24492 12:31:55.458274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24493 12:31:55.458714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24495 12:31:55.518691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24496 12:31:55.519171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24498 12:31:55.577230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24500 12:31:55.577716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24501 12:31:55.619360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24502 12:31:55.619753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24504 12:31:55.671907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24505 12:31:55.672385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24507 12:31:55.720901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24508 12:31:55.721338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24510 12:31:55.765906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24512 12:31:55.766385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24513 12:31:55.810995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24514 12:31:55.811374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24516 12:31:55.855059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24517 12:31:55.855473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24519 12:31:55.906063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24521 12:31:55.906555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24522 12:31:55.951484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24523 12:31:55.952032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24525 12:31:55.999043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24527 12:31:55.999487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24528 12:31:56.043754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24529 12:31:56.044193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24531 12:31:56.089538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24533 12:31:56.090000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24534 12:31:56.135437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24536 12:31:56.135917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24537 12:31:56.179724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24539 12:31:56.180212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24540 12:31:56.229053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24541 12:31:56.229510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24543 12:31:56.280306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24545 12:31:56.280752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24546 12:31:56.324341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24548 12:31:56.324803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24549 12:31:56.369489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24550 12:31:56.369947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24552 12:31:56.423871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24553 12:31:56.424305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24555 12:31:56.472499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24557 12:31:56.472975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24558 12:31:56.519169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24559 12:31:56.519571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24561 12:31:56.566850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24562 12:31:56.567261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24564 12:31:56.610256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24565 12:31:56.610764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24567 12:31:56.656980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24569 12:31:56.657488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24570 12:31:56.703770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24571 12:31:56.704233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24573 12:31:56.751518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24574 12:31:56.751935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24576 12:31:56.791265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24578 12:31:56.791753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24579 12:31:56.829876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24580 12:31:56.830280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24582 12:31:56.877104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24583 12:31:56.877568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24585 12:31:56.923351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24586 12:31:56.923769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24588 12:31:56.965257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24589 12:31:56.965721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24591 12:31:57.003513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24592 12:31:57.004073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24594 12:31:57.050421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24596 12:31:57.050894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24597 12:31:57.090890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24598 12:31:57.091227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24600 12:31:57.130735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24602 12:31:57.131150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24603 12:31:57.172963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24604 12:31:57.173385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24606 12:31:57.218232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24607 12:31:57.218670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24609 12:31:57.256387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24610 12:31:57.256802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24612 12:31:57.294727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24613 12:31:57.295266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24615 12:31:57.334002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24616 12:31:57.334473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24618 12:31:57.377572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24619 12:31:57.378009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24621 12:31:57.418282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24622 12:31:57.418715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24624 12:31:57.461166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24625 12:31:57.461657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24627 12:31:57.507628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24628 12:31:57.508038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24630 12:31:57.557320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24631 12:31:57.557744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24633 12:31:57.603118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24635 12:31:57.603593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24636 12:31:57.647990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24638 12:31:57.648390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24639 12:31:57.697026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24640 12:31:57.697595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24642 12:31:57.742010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24643 12:31:57.742475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24645 12:31:57.785063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24646 12:31:57.785506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24648 12:31:57.831167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24649 12:31:57.831631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24651 12:31:57.886740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24653 12:31:57.887465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24654 12:31:57.941555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24655 12:31:57.942025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24657 12:31:57.990490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24658 12:31:57.990915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24660 12:31:58.035382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24662 12:31:58.035771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24663 12:31:58.083400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24664 12:31:58.083846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24666 12:31:58.130109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24667 12:31:58.130542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24669 12:31:58.177598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24670 12:31:58.178040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24672 12:31:58.216912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24674 12:31:58.217395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24675 12:31:58.258600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24676 12:31:58.259118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24678 12:31:58.305471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24680 12:31:58.305948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24681 12:31:58.346461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24682 12:31:58.346910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24684 12:31:58.391717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24686 12:31:58.392199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24687 12:31:58.438516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24688 12:31:58.438934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24690 12:31:58.486009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24691 12:31:58.486417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24693 12:31:58.527973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24694 12:31:58.528422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24696 12:31:58.569129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24697 12:31:58.569583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24699 12:31:58.610328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24700 12:31:58.610801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24702 12:31:58.656942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24703 12:31:58.657412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24705 12:31:58.703254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24706 12:31:58.703689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24708 12:31:58.743480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24710 12:31:58.743971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24711 12:31:58.786915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24713 12:31:58.787354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24714 12:31:58.845230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24715 12:31:58.845679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24717 12:31:58.899327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24718 12:31:58.899750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24720 12:31:58.950658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24722 12:31:58.951308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24723 12:31:59.001865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24724 12:31:59.002318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24726 12:31:59.061343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24727 12:31:59.061800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24729 12:31:59.113484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24730 12:31:59.114003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24732 12:31:59.166128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24733 12:31:59.166588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24735 12:31:59.217427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24736 12:31:59.217840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24738 12:31:59.270181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24740 12:31:59.270639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24741 12:31:59.322519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24742 12:31:59.323057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24744 12:31:59.367028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24745 12:31:59.367421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24747 12:31:59.418525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24748 12:31:59.418925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24750 12:31:59.468008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24752 12:31:59.468472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24753 12:31:59.522738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24754 12:31:59.523176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24756 12:31:59.571260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24757 12:31:59.571675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24759 12:31:59.623717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24761 12:31:59.624391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24762 12:31:59.671172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24763 12:31:59.671595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24765 12:31:59.717610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24766 12:31:59.718020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24768 12:31:59.765942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24770 12:31:59.766402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24771 12:31:59.811267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24773 12:31:59.811735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24774 12:31:59.856889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24775 12:31:59.857333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24777 12:31:59.906231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24778 12:31:59.906701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24780 12:31:59.951887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24781 12:31:59.952413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24783 12:31:59.994500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24784 12:31:59.994955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24786 12:32:00.044321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24788 12:32:00.044817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24789 12:32:00.088107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24790 12:32:00.088519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24792 12:32:00.133800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24794 12:32:00.134382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24795 12:32:00.179363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24797 12:32:00.179823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24798 12:32:00.257433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24799 12:32:00.257849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24801 12:32:00.307642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24802 12:32:00.308070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24804 12:32:00.354084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24805 12:32:00.354517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24807 12:32:00.403880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24808 12:32:00.404324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24810 12:32:00.448498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24812 12:32:00.449144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24813 12:32:00.502425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24814 12:32:00.502817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24816 12:32:00.550491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24817 12:32:00.550893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24819 12:32:00.595095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24820 12:32:00.595503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24822 12:32:00.637994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24824 12:32:00.638467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24825 12:32:00.681349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24826 12:32:00.681747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24828 12:32:00.726529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24829 12:32:00.726992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24831 12:32:00.767841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24832 12:32:00.768255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24834 12:32:00.813754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24835 12:32:00.814207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24837 12:32:00.868216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24839 12:32:00.868709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24840 12:32:00.927887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24841 12:32:00.928320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24843 12:32:00.988220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24845 12:32:00.988850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24846 12:32:01.049593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24847 12:32:01.050039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24849 12:32:01.109788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24851 12:32:01.110185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24852 12:32:01.170067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24853 12:32:01.170523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24855 12:32:01.230875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24856 12:32:01.231287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24858 12:32:01.290788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24859 12:32:01.291185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24861 12:32:01.353720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24862 12:32:01.354150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24864 12:32:01.416006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24866 12:32:01.416480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24867 12:32:01.477977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24868 12:32:01.478377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24870 12:32:01.537955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24872 12:32:01.538391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24873 12:32:01.597928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24874 12:32:01.598399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24876 12:32:01.658677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24878 12:32:01.659188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24879 12:32:01.719261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24880 12:32:01.719698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24882 12:32:01.767975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24883 12:32:01.768420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24885 12:32:01.815498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24886 12:32:01.815875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24888 12:32:01.870069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24889 12:32:01.870509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24891 12:32:01.931439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24892 12:32:01.931862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24894 12:32:01.992366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24896 12:32:01.992818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24897 12:32:02.058604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24898 12:32:02.059036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24900 12:32:02.117891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24901 12:32:02.118288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24903 12:32:02.177679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24904 12:32:02.178093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24906 12:32:02.238071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24907 12:32:02.238492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24909 12:32:02.299572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24910 12:32:02.300004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24912 12:32:02.354811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24913 12:32:02.355375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24915 12:32:02.402729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24916 12:32:02.403159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24918 12:32:02.446471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24919 12:32:02.446902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24921 12:32:02.487402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24922 12:32:02.487805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24924 12:32:02.530135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24925 12:32:02.530547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24927 12:32:02.572842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24928 12:32:02.573394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24930 12:32:02.612988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24931 12:32:02.613478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24933 12:32:02.658589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24935 12:32:02.659029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24936 12:32:02.698218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24937 12:32:02.698738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24939 12:32:02.742688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24941 12:32:02.743164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24942 12:32:02.790628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24943 12:32:02.791040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24945 12:32:02.846737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24947 12:32:02.847221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24948 12:32:02.899131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24949 12:32:02.899527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24951 12:32:02.946122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24952 12:32:02.946476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24954 12:32:02.991329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24955 12:32:02.991767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24957 12:32:03.040352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24959 12:32:03.040804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24960 12:32:03.093939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24961 12:32:03.094372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24963 12:32:03.141474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24964 12:32:03.141943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24966 12:32:03.182850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24967 12:32:03.183280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24969 12:32:03.225394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24970 12:32:03.225826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24972 12:32:03.273584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24974 12:32:03.274063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24975 12:32:03.323529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24976 12:32:03.323989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24978 12:32:03.375337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24980 12:32:03.375836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24981 12:32:03.423197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24983 12:32:03.423919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24984 12:32:03.473190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24985 12:32:03.473592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24987 12:32:03.522899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24988 12:32:03.523353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24990 12:32:03.574499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24991 12:32:03.574938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24993 12:32:03.615930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24995 12:32:03.616375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24996 12:32:03.664449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24998 12:32:03.664942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24999 12:32:03.711339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
25000 12:32:03.711788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
25002 12:32:03.758583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
25004 12:32:03.759061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
25005 12:32:03.799595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
25006 12:32:03.800009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
25008 12:32:03.853147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
25009 12:32:03.853675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
25011 12:32:03.898644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
25012 12:32:03.899101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
25014 12:32:03.938297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
25015 12:32:03.938724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
25017 12:32:03.978697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
25018 12:32:03.979095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
25020 12:32:04.019414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
25021 12:32:04.019831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
25023 12:32:04.067920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
25024 12:32:04.068339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
25026 12:32:04.117159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
25027 12:32:04.117607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
25029 12:32:04.169811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
25030 12:32:04.170217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
25032 12:32:04.215824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
25034 12:32:04.216322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
25035 12:32:04.265107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
25036 12:32:04.265571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
25038 12:32:04.320119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
25040 12:32:04.320508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
25041 12:32:04.375266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
25042 12:32:04.375684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
25044 12:32:04.421717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
25045 12:32:04.422334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
25047 12:32:04.465038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
25048 12:32:04.465463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
25050 12:32:04.518232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
25051 12:32:04.518714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
25053 12:32:04.559874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
25055 12:32:04.560369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
25056 12:32:04.606535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
25057 12:32:04.609756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
25059 12:32:04.658209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
25060 12:32:04.658641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
25062 12:32:04.705337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
25063 12:32:04.705798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
25065 12:32:04.753869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
25066 12:32:04.754473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
25068 12:32:04.802755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
25070 12:32:04.803246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
25071 12:32:04.854903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
25072 12:32:04.855348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25074 12:32:04.909159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25075 12:32:04.909548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25077 12:32:04.962956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25078 12:32:04.963416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25080 12:32:05.014631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25081 12:32:05.015088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25083 12:32:05.065638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25084 12:32:05.066066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25086 12:32:05.134809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25087 12:32:05.135299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25089 12:32:05.197847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25090 12:32:05.198295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25092 12:32:05.258601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25093 12:32:05.259016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25095 12:32:05.315439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25097 12:32:05.315936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25098 12:32:05.389251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25099 12:32:05.389697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25101 12:32:05.445280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25102 12:32:05.445678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25104 12:32:05.493319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25106 12:32:05.493772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25107 12:32:05.537550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25108 12:32:05.538090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25110 12:32:05.579114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25111 12:32:05.579543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25113 12:32:05.626108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25114 12:32:05.626534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25116 12:32:05.676027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25117 12:32:05.676467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25119 12:32:05.721530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25120 12:32:05.721979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25122 12:32:05.766678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25123 12:32:05.767140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25125 12:32:05.816315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25127 12:32:05.816724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25128 12:32:05.865252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25129 12:32:05.865707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25131 12:32:05.918003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25132 12:32:05.918439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25134 12:32:05.972336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25136 12:32:05.972816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25137 12:32:06.031831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25138 12:32:06.032291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25140 12:32:06.092029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25141 12:32:06.092416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25143 12:32:06.150776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25144 12:32:06.151197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25146 12:32:06.210822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25147 12:32:06.211235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25149 12:32:06.269858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25150 12:32:06.270280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25152 12:32:06.327089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25153 12:32:06.327503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25155 12:32:06.382928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25157 12:32:06.383423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25158 12:32:06.441804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25159 12:32:06.442250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25161 12:32:06.487378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25162 12:32:06.487821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25164 12:32:06.539148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25166 12:32:06.539594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25167 12:32:06.594558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25168 12:32:06.595000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25170 12:32:06.647476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25171 12:32:06.647923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25173 12:32:06.698304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25174 12:32:06.698739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25176 12:32:06.753353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25178 12:32:06.753810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25179 12:32:06.807960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25180 12:32:06.808398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25182 12:32:06.862309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25183 12:32:06.862747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25185 12:32:06.923863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25186 12:32:06.924302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25188 12:32:06.975376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25189 12:32:06.975804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25191 12:32:07.031067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25193 12:32:07.031490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25194 12:32:07.078446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25196 12:32:07.078940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25197 12:32:07.126919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25198 12:32:07.127340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25200 12:32:07.174696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25202 12:32:07.175270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25203 12:32:07.225982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25205 12:32:07.226445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25206 12:32:07.276085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25208 12:32:07.276480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25209 12:32:07.335238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25210 12:32:07.335671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25212 12:32:07.383908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25213 12:32:07.384463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25215 12:32:07.443858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25216 12:32:07.444254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25218 12:32:07.493719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25220 12:32:07.494326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25221 12:32:07.541088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25222 12:32:07.541556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25224 12:32:07.582390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25226 12:32:07.582879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25227 12:32:07.625726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25228 12:32:07.626167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25230 12:32:07.675860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25231 12:32:07.676296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25233 12:32:07.726637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25234 12:32:07.727074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25236 12:32:07.783514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25237 12:32:07.783951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25239 12:32:07.838098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25241 12:32:07.838568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25242 12:32:07.887762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25243 12:32:07.888175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25245 12:32:07.937981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25246 12:32:07.938423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25248 12:32:07.989062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25249 12:32:07.989502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25251 12:32:08.033788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25252 12:32:08.034226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25254 12:32:08.090302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25255 12:32:08.090711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25257 12:32:08.131427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25258 12:32:08.131900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25260 12:32:08.183682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25261 12:32:08.184057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25263 12:32:08.236512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25265 12:32:08.236956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25266 12:32:08.287739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25267 12:32:08.288203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25269 12:32:08.333159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25270 12:32:08.333588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25272 12:32:08.375975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25274 12:32:08.376462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25275 12:32:08.422710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25277 12:32:08.423183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25278 12:32:08.473838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25280 12:32:08.474447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25281 12:32:08.518464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25282 12:32:08.518895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25284 12:32:08.554814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25286 12:32:08.555603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25287 12:32:08.591735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25288 12:32:08.592241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25290 12:32:08.629762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25291 12:32:08.630312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25293 12:32:08.675188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25294 12:32:08.675771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25296 12:32:08.713719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25298 12:32:08.714195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25299 12:32:08.754455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25300 12:32:08.754890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25302 12:32:08.794813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25303 12:32:08.795271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25305 12:32:08.832620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25307 12:32:08.833210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25308 12:32:08.870435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25310 12:32:08.870875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25311 12:32:08.912136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25312 12:32:08.912544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25314 12:32:08.962341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25315 12:32:08.962705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25317 12:32:09.015621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25318 12:32:09.016065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25320 12:32:09.066393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25322 12:32:09.066834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25323 12:32:09.119519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25324 12:32:09.119982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25326 12:32:09.177533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25327 12:32:09.177976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25329 12:32:09.234066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25331 12:32:09.234554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25332 12:32:09.275331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25333 12:32:09.275807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25335 12:32:09.319859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25336 12:32:09.320249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25338 12:32:09.358933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25340 12:32:09.359421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25341 12:32:09.397004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25342 12:32:09.397456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25344 12:32:09.434794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25345 12:32:09.435233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25347 12:32:09.474249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25348 12:32:09.474682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25350 12:32:09.513678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25351 12:32:09.514133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25353 12:32:09.556036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25354 12:32:09.556471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25356 12:32:09.596051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25357 12:32:09.596477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25359 12:32:09.638553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25361 12:32:09.639010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25362 12:32:09.676404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25364 12:32:09.676997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25365 12:32:09.716927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25366 12:32:09.717484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25368 12:32:09.759085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25369 12:32:09.759502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25371 12:32:09.799085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25372 12:32:09.799540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25374 12:32:09.845854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25375 12:32:09.846310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25377 12:32:09.898595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25378 12:32:09.899033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25380 12:32:09.953052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25381 12:32:09.953488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25383 12:32:09.995367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25384 12:32:09.995738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25386 12:32:10.042325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25387 12:32:10.042738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25389 12:32:10.093985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25390 12:32:10.094410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25392 12:32:10.134380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25394 12:32:10.135133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25395 12:32:10.175912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25396 12:32:10.176452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25398 12:32:10.227928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25399 12:32:10.228348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25401 12:32:10.283614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25402 12:32:10.284056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25404 12:32:10.343718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25405 12:32:10.344141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25407 12:32:10.397189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25408 12:32:10.397558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25410 12:32:10.442867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25411 12:32:10.443257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25413 12:32:10.509394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25414 12:32:10.509832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25416 12:32:10.548857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25417 12:32:10.549310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25419 12:32:10.586330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25420 12:32:10.586715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25422 12:32:10.622008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25424 12:32:10.622630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25425 12:32:10.669594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25426 12:32:10.670005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25428 12:32:10.715532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25430 12:32:10.716021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25431 12:32:10.758924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25432 12:32:10.759371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25434 12:32:10.803290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25435 12:32:10.803686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25437 12:32:10.858555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25438 12:32:10.858981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25440 12:32:10.904035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25441 12:32:10.904485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25443 12:32:10.945606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25445 12:32:10.946089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25446 12:32:10.989666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25447 12:32:10.990105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25449 12:32:11.046370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25451 12:32:11.046871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25452 12:32:11.102258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25453 12:32:11.102692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25455 12:32:11.149732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25456 12:32:11.150171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25458 12:32:11.196089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25459 12:32:11.196535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25461 12:32:11.241904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25462 12:32:11.242290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25464 12:32:11.279039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25465 12:32:11.279547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25467 12:32:11.316188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25468 12:32:11.316672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25470 12:32:11.357697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25472 12:32:11.358171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25473 12:32:11.401281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25474 12:32:11.401694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25476 12:32:11.451727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25477 12:32:11.452140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25479 12:32:11.498504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25481 12:32:11.498980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25482 12:32:11.537228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25483 12:32:11.537622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25485 12:32:11.578280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25486 12:32:11.578754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25488 12:32:11.617709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25490 12:32:11.618263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25491 12:32:11.669634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25493 12:32:11.670132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25494 12:32:11.711680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25496 12:32:11.712153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25497 12:32:11.755124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25498 12:32:11.755560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25500 12:32:11.795134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25502 12:32:11.795828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25503 12:32:11.836306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25505 12:32:11.836711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25506 12:32:11.875540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25508 12:32:11.875968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25509 12:32:11.917005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25510 12:32:11.917598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25512 12:32:11.952988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25513 12:32:11.953447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25515 12:32:11.998758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25516 12:32:11.999193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25518 12:32:12.046228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25519 12:32:12.046668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25521 12:32:12.093046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25522 12:32:12.093485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25524 12:32:12.135946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25525 12:32:12.136339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25527 12:32:12.181597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25528 12:32:12.182032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25530 12:32:12.226062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25531 12:32:12.226431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25533 12:32:12.263604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25534 12:32:12.264058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25536 12:32:12.302632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25537 12:32:12.303084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25539 12:32:12.342539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25540 12:32:12.342980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25542 12:32:12.383781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25543 12:32:12.384238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25545 12:32:12.430388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25546 12:32:12.430821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25548 12:32:12.475403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25550 12:32:12.475896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25551 12:32:12.518484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25552 12:32:12.518981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25554 12:32:12.566689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25556 12:32:12.567420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25557 12:32:12.610798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25558 12:32:12.611353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25560 12:32:12.655603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25561 12:32:12.656047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25563 12:32:12.701721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25564 12:32:12.702127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25566 12:32:12.742516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25568 12:32:12.743122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25569 12:32:12.785478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25570 12:32:12.785874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25572 12:32:12.821465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25574 12:32:12.821902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25575 12:32:12.861106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25576 12:32:12.861541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25578 12:32:12.898207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25580 12:32:12.898948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25581 12:32:12.935298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25582 12:32:12.935720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25584 12:32:12.972025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25586 12:32:12.972511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25587 12:32:13.021844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25588 12:32:13.022241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25590 12:32:13.063469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25592 12:32:13.063911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25593 12:32:13.105054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25594 12:32:13.105489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25596 12:32:13.146800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25597 12:32:13.147230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25599 12:32:13.187997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25600 12:32:13.188433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25602 12:32:13.229581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25603 12:32:13.229979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25605 12:32:13.279787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25606 12:32:13.280211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25608 12:32:13.329561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25610 12:32:13.330019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25611 12:32:13.374585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25612 12:32:13.375006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25614 12:32:13.418447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25615 12:32:13.418875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25617 12:32:13.466846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25618 12:32:13.467332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25620 12:32:13.521299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25621 12:32:13.521739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25623 12:32:13.577542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25624 12:32:13.577981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25626 12:32:13.626445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25628 12:32:13.626888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25629 12:32:13.668994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25630 12:32:13.669430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25632 12:32:13.715870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25634 12:32:13.716305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25635 12:32:13.763730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25637 12:32:13.764305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25638 12:32:13.802350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25639 12:32:13.802814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25641 12:32:13.839809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25642 12:32:13.840197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25644 12:32:13.880062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25646 12:32:13.880480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25647 12:32:13.925413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25648 12:32:13.925852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25650 12:32:13.965330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25652 12:32:13.965824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25653 12:32:14.009748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25654 12:32:14.010151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25656 12:32:14.061194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25657 12:32:14.061585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25659 12:32:14.118692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25660 12:32:14.119087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25662 12:32:14.176906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25663 12:32:14.177368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25665 12:32:14.219681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25666 12:32:14.220126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25668 12:32:14.271793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25669 12:32:14.272274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25671 12:32:14.324101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25672 12:32:14.324545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25674 12:32:14.377470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25676 12:32:14.377932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25677 12:32:14.429803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25678 12:32:14.430248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25680 12:32:14.478198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25681 12:32:14.478633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25683 12:32:14.530042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25684 12:32:14.530490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25686 12:32:14.574908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25687 12:32:14.575310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25689 12:32:14.625174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25690 12:32:14.625610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25692 12:32:14.679219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25693 12:32:14.679623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25695 12:32:14.735399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25696 12:32:14.735828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25698 12:32:14.786942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25699 12:32:14.787393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25701 12:32:14.831621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25702 12:32:14.832080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25704 12:32:14.877491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25705 12:32:14.877940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25707 12:32:14.924610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25709 12:32:14.925091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25710 12:32:14.970459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25711 12:32:14.970887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25713 12:32:15.017362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25714 12:32:15.017785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25716 12:32:15.062222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25717 12:32:15.062656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25719 12:32:15.102788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25720 12:32:15.103223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25722 12:32:15.145973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25723 12:32:15.146408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25725 12:32:15.186216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25726 12:32:15.186677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25728 12:32:15.229107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25729 12:32:15.229500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25731 12:32:15.271063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25732 12:32:15.271442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25734 12:32:15.322690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25735 12:32:15.323178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25737 12:32:15.368808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25739 12:32:15.369223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25740 12:32:15.415185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25742 12:32:15.415653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25743 12:32:15.459016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25744 12:32:15.459461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25746 12:32:15.506147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25748 12:32:15.506635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25749 12:32:15.547326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25750 12:32:15.547766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25752 12:32:15.615869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25754 12:32:15.616486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25755 12:32:15.664974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25756 12:32:15.665405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25758 12:32:15.711286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25759 12:32:15.711726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25761 12:32:15.771027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25762 12:32:15.771584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25764 12:32:15.818147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25766 12:32:15.818622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25767 12:32:15.867022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25769 12:32:15.867517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25770 12:32:15.922276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25771 12:32:15.922705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25773 12:32:15.963397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25774 12:32:15.963829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25776 12:32:16.003628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25777 12:32:16.004058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25779 12:32:16.043246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25780 12:32:16.043641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25782 12:32:16.083340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25783 12:32:16.083799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25785 12:32:16.125683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25787 12:32:16.126152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25788 12:32:16.166342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25789 12:32:16.166796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25791 12:32:16.209940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25792 12:32:16.210293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25794 12:32:16.262628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25795 12:32:16.263039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25797 12:32:16.301720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25798 12:32:16.302183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25800 12:32:16.341217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25801 12:32:16.341655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25803 12:32:16.392008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25804 12:32:16.392427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25806 12:32:16.445244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25807 12:32:16.445687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25809 12:32:16.485744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25810 12:32:16.486193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25812 12:32:16.545465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25813 12:32:16.545919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25815 12:32:16.605888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25816 12:32:16.606327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25818 12:32:16.659786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25819 12:32:16.660207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25821 12:32:16.706681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25822 12:32:16.707089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25824 12:32:16.757052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25825 12:32:16.757485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25827 12:32:16.797132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25828 12:32:16.797565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25830 12:32:16.838891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25831 12:32:16.839329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25833 12:32:16.885372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25834 12:32:16.885799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25836 12:32:16.926441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25837 12:32:16.927199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25839 12:32:16.966016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25840 12:32:16.966437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25842 12:32:17.009729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25843 12:32:17.010132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25845 12:32:17.051252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25846 12:32:17.052022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25848 12:32:17.107406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25850 12:32:17.108007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25851 12:32:17.150549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25852 12:32:17.150973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25854 12:32:17.196709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25856 12:32:17.197374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25857 12:32:17.242780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25858 12:32:17.243189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25860 12:32:17.288122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25861 12:32:17.288556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25863 12:32:17.350160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25864 12:32:17.350604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25866 12:32:17.414449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25867 12:32:17.414889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25869 12:32:17.478021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25870 12:32:17.478467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25872 12:32:17.527783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25873 12:32:17.528215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25875 12:32:17.574004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25877 12:32:17.574445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25878 12:32:17.624518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25880 12:32:17.624992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25881 12:32:17.674598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25882 12:32:17.675037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25884 12:32:17.725675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25885 12:32:17.726106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25887 12:32:17.768410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25889 12:32:17.768929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25890 12:32:17.818962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25891 12:32:17.819403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25893 12:32:17.870145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25894 12:32:17.870584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25896 12:32:17.928589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25898 12:32:17.929074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25899 12:32:17.986677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25900 12:32:17.987120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25902 12:32:18.043729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25904 12:32:18.044225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25905 12:32:18.094371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25906 12:32:18.094823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25908 12:32:18.145728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25909 12:32:18.146169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25911 12:32:18.195652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25913 12:32:18.196139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25914 12:32:18.243939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25916 12:32:18.244434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25917 12:32:18.287946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25918 12:32:18.288384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25920 12:32:18.336512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25922 12:32:18.337011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25923 12:32:18.389179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25924 12:32:18.389675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25926 12:32:18.431017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25927 12:32:18.431445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25929 12:32:18.486456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25930 12:32:18.486879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25932 12:32:18.545857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25933 12:32:18.546325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25935 12:32:18.600029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25936 12:32:18.600469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25938 12:32:18.659572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25939 12:32:18.660000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25941 12:32:18.710515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25943 12:32:18.710981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25944 12:32:18.758415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25945 12:32:18.758847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25947 12:32:18.799969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25948 12:32:18.800402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25950 12:32:18.853785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25951 12:32:18.854229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25953 12:32:18.898589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25955 12:32:18.899078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25956 12:32:18.940186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25957 12:32:18.940636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25959 12:32:18.991336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25960 12:32:18.991749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25962 12:32:19.048135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25964 12:32:19.048620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25965 12:32:19.101914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25967 12:32:19.102405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25968 12:32:19.148061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25969 12:32:19.148495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25971 12:32:19.190591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25972 12:32:19.191030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25974 12:32:19.235500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25975 12:32:19.235931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25977 12:32:19.284255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25979 12:32:19.284757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25980 12:32:19.344585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25982 12:32:19.345319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25983 12:32:19.404352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25985 12:32:19.405154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25986 12:32:19.446439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25987 12:32:19.446868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25989 12:32:19.498119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25990 12:32:19.498559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25992 12:32:19.545641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25993 12:32:19.546098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25995 12:32:19.598906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25996 12:32:19.599308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25998 12:32:19.653045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25999 12:32:19.653436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
26001 12:32:19.705051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
26003 12:32:19.705424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
26004 12:32:19.753931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
26005 12:32:19.754454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
26007 12:32:19.795802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
26008 12:32:19.796222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
26010 12:32:19.856102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
26011 12:32:19.856531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
26013 12:32:19.913076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
26014 12:32:19.913505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
26016 12:32:19.964386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
26018 12:32:19.964822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
26019 12:32:20.018739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
26021 12:32:20.019225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
26022 12:32:20.072225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
26024 12:32:20.072706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
26025 12:32:20.118949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
26026 12:32:20.119379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
26028 12:32:20.174107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
26029 12:32:20.174550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
26031 12:32:20.226186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
26032 12:32:20.226624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
26034 12:32:20.275688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
26035 12:32:20.276133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
26037 12:32:20.325538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
26038 12:32:20.326005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
26040 12:32:20.378519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
26041 12:32:20.378958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
26043 12:32:20.437368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
26045 12:32:20.437852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
26046 12:32:20.492316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
26048 12:32:20.492809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
26049 12:32:20.538402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
26050 12:32:20.538838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
26052 12:32:20.591998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
26053 12:32:20.592448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
26055 12:32:20.635970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
26056 12:32:20.636389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
26058 12:32:20.701769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
26059 12:32:20.702164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
26061 12:32:20.769299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
26063 12:32:20.769743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
26064 12:32:20.817820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
26065 12:32:20.818232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
26067 12:32:20.868493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
26069 12:32:20.868995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
26070 12:32:20.918198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
26071 12:32:20.918613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
26073 12:32:20.962222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26074 12:32:20.962643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26076 12:32:21.007711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26077 12:32:21.008186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26079 12:32:21.070349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26080 12:32:21.070760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26082 12:32:21.133105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26083 12:32:21.133499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26085 12:32:21.194256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26086 12:32:21.194726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26088 12:32:21.241380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26090 12:32:21.241870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26091 12:32:21.292339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26093 12:32:21.292824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26094 12:32:21.339505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26095 12:32:21.339977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26097 12:32:21.390930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26099 12:32:21.391414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26100 12:32:21.441433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26101 12:32:21.441879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26103 12:32:21.490957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26104 12:32:21.491392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26106 12:32:21.545236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26107 12:32:21.545679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26109 12:32:21.596869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26110 12:32:21.597322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26112 12:32:21.648040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26113 12:32:21.648471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26115 12:32:21.699207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26116 12:32:21.699707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26118 12:32:21.741714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26119 12:32:21.742143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26121 12:32:21.793772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26122 12:32:21.794263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26124 12:32:21.837235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26125 12:32:21.837720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26127 12:32:21.891406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26129 12:32:21.892059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26130 12:32:21.944495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26132 12:32:21.945154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26133 12:32:21.995538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26134 12:32:21.995995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26136 12:32:22.044531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26138 12:32:22.045300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26139 12:32:22.083212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26141 12:32:22.083667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26142 12:32:22.130788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26143 12:32:22.131207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26145 12:32:22.175845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26146 12:32:22.176364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26148 12:32:22.214329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26149 12:32:22.214815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26151 12:32:22.265163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26153 12:32:22.265884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26154 12:32:22.317326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26155 12:32:22.317821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26157 12:32:22.356546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26159 12:32:22.357329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26160 12:32:22.405121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26162 12:32:22.405593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26163 12:32:22.457837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26164 12:32:22.458269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26166 12:32:22.509973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26167 12:32:22.510395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26169 12:32:22.550955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26170 12:32:22.551359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26172 12:32:22.592139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26174 12:32:22.592591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26175 12:32:22.644072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26176 12:32:22.644516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26178 12:32:22.687888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26179 12:32:22.688415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26181 12:32:22.727981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26182 12:32:22.728412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26184 12:32:22.775963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26185 12:32:22.776397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26187 12:32:22.833278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26188 12:32:22.833698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26190 12:32:22.886341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26191 12:32:22.886900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26193 12:32:22.930685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26194 12:32:22.931105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26196 12:32:22.973296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26197 12:32:22.973683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26199 12:32:23.014340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26201 12:32:23.014787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26202 12:32:23.065604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26203 12:32:23.066061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26205 12:32:23.121926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26206 12:32:23.122382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26208 12:32:23.166861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26209 12:32:23.167294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26211 12:32:23.219581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26212 12:32:23.220045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26214 12:32:23.272452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26216 12:32:23.272932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26217 12:32:23.325477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26218 12:32:23.325929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26220 12:32:23.379020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26222 12:32:23.379450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26223 12:32:23.427534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26224 12:32:23.427969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26226 12:32:23.477995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26228 12:32:23.478492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26229 12:32:23.537713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26230 12:32:23.538153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26232 12:32:23.579728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26233 12:32:23.580200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26235 12:32:23.626622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26237 12:32:23.627043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26238 12:32:23.670607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26239 12:32:23.670999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26241 12:32:23.721150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26242 12:32:23.721589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26244 12:32:23.771056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26245 12:32:23.771461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26247 12:32:23.819132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26248 12:32:23.819588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26250 12:32:23.867998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26251 12:32:23.868442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26253 12:32:23.917667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26254 12:32:23.918103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26256 12:32:23.971277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26257 12:32:23.971717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26259 12:32:24.028417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26261 12:32:24.028906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26262 12:32:24.078131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26264 12:32:24.078618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26265 12:32:24.126537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26266 12:32:24.126979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26268 12:32:24.172381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26270 12:32:24.172864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26271 12:32:24.215916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26273 12:32:24.216366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26274 12:32:24.266903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26275 12:32:24.267274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26277 12:32:24.314874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26278 12:32:24.315429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26280 12:32:24.371710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26282 12:32:24.372204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26283 12:32:24.426076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26284 12:32:24.426527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26286 12:32:24.479720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26287 12:32:24.480162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26289 12:32:24.532327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26291 12:32:24.532809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26292 12:32:24.577080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26294 12:32:24.577513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26295 12:32:24.617211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26296 12:32:24.617597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26298 12:32:24.662400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26299 12:32:24.662910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26301 12:32:24.713538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26302 12:32:24.714111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26304 12:32:24.761540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26305 12:32:24.762034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26307 12:32:24.815268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26308 12:32:24.815767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26310 12:32:24.869845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26312 12:32:24.870578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26313 12:32:24.923637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26314 12:32:24.924117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26316 12:32:24.975875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26317 12:32:24.976318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26319 12:32:25.022131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26320 12:32:25.022559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26322 12:32:25.071865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26323 12:32:25.072358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26325 12:32:25.122047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26326 12:32:25.122552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26328 12:32:25.168032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26329 12:32:25.168514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26331 12:32:25.219710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26332 12:32:25.220127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26334 12:32:25.274144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26335 12:32:25.274568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26337 12:32:25.328088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26338 12:32:25.328525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26340 12:32:25.381451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26341 12:32:25.381901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26343 12:32:25.431303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26344 12:32:25.431709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26346 12:32:25.488080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26348 12:32:25.488524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26349 12:32:25.538737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26350 12:32:25.539301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26352 12:32:25.587195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26353 12:32:25.587604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26355 12:32:25.634668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26357 12:32:25.635130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26358 12:32:25.677804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26360 12:32:25.678316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26361 12:32:25.722707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26362 12:32:25.723172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26364 12:32:25.770825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26366 12:32:25.771273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26367 12:32:25.830309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26368 12:32:25.830859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26370 12:32:25.877174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26371 12:32:25.877696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26373 12:32:25.925152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26374 12:32:25.925566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26376 12:32:25.973995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26378 12:32:25.974463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26379 12:32:26.031688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26380 12:32:26.032131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26382 12:32:26.091933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26383 12:32:26.092379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26385 12:32:26.131494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26386 12:32:26.131945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26388 12:32:26.179699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26389 12:32:26.180169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26391 12:32:26.233151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26392 12:32:26.233568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26394 12:32:26.286054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26396 12:32:26.286520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26397 12:32:26.325896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26398 12:32:26.326411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26400 12:32:26.365843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26401 12:32:26.366293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26403 12:32:26.407340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26405 12:32:26.407815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26406 12:32:26.450515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26407 12:32:26.450999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26409 12:32:26.497713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26410 12:32:26.498115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26412 12:32:26.543678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26413 12:32:26.544113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26415 12:32:26.584561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26417 12:32:26.585317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26418 12:32:26.624096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26420 12:32:26.624574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26421 12:32:26.667875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26422 12:32:26.668278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26424 12:32:26.709776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26425 12:32:26.710213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26427 12:32:26.751210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26429 12:32:26.751687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26430 12:32:26.797334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26431 12:32:26.797763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26433 12:32:26.846166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26434 12:32:26.846558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26436 12:32:26.900959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26438 12:32:26.901388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26439 12:32:26.951959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26440 12:32:26.952352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26442 12:32:27.007037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26444 12:32:27.007466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26445 12:32:27.069608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26447 12:32:27.070376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26448 12:32:27.128308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26450 12:32:27.128755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26451 12:32:27.176015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26453 12:32:27.176434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26454 12:32:27.217398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26455 12:32:27.217786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26457 12:32:27.259630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26458 12:32:27.260080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26460 12:32:27.310980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26462 12:32:27.311461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26463 12:32:27.357352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26464 12:32:27.357784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26466 12:32:27.410230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26467 12:32:27.410660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26469 12:32:27.464340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26471 12:32:27.464751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26472 12:32:27.507552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26473 12:32:27.507954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26475 12:32:27.557813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26476 12:32:27.558270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26478 12:32:27.605194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26480 12:32:27.605631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26481 12:32:27.655116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26482 12:32:27.655587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26484 12:32:27.714043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26485 12:32:27.714490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26487 12:32:27.766756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26488 12:32:27.767207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26490 12:32:27.816033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26492 12:32:27.816463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26493 12:32:27.862421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26494 12:32:27.862848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26496 12:32:27.902580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26498 12:32:27.903049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26499 12:32:27.942435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26500 12:32:27.942947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26502 12:32:27.986409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26503 12:32:27.986853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26505 12:32:28.030123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26506 12:32:28.030638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26508 12:32:28.086395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26509 12:32:28.086842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26511 12:32:28.141394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26512 12:32:28.141825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26514 12:32:28.195768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26515 12:32:28.196202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26517 12:32:28.249935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26518 12:32:28.250429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26520 12:32:28.301950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26521 12:32:28.302380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26523 12:32:28.353802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26524 12:32:28.354190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26526 12:32:28.399899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26527 12:32:28.400439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26529 12:32:28.444135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26530 12:32:28.444544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26532 12:32:28.490072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26533 12:32:28.490508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26535 12:32:28.537599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26537 12:32:28.538097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26538 12:32:28.590607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26539 12:32:28.591047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26541 12:32:28.645287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26542 12:32:28.645692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26544 12:32:28.695615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26545 12:32:28.696060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26547 12:32:28.736522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26549 12:32:28.737092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26550 12:32:28.781552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26551 12:32:28.781993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26553 12:32:28.832395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26555 12:32:28.832908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26556 12:32:28.891361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26557 12:32:28.891943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26559 12:32:28.950557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26560 12:32:28.950966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26562 12:32:29.008407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26564 12:32:29.009011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26565 12:32:29.065816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26566 12:32:29.066380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26568 12:32:29.122381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26569 12:32:29.122952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26571 12:32:29.179516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26572 12:32:29.180061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26574 12:32:29.237754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26575 12:32:29.238284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26577 12:32:29.295136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26579 12:32:29.295889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26580 12:32:29.351648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26581 12:32:29.352142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26583 12:32:29.409792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26584 12:32:29.410274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26586 12:32:29.471007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26587 12:32:29.471416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26589 12:32:29.530076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26590 12:32:29.530475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26592 12:32:29.586097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26593 12:32:29.586484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26595 12:32:29.642584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26596 12:32:29.643141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26598 12:32:29.687571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26599 12:32:29.688148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26601 12:32:29.734447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26602 12:32:29.734873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26604 12:32:29.782835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26605 12:32:29.783281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26607 12:32:29.826754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26608 12:32:29.827151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26610 12:32:29.869974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26611 12:32:29.870410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26613 12:32:29.910228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26615 12:32:29.910672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26616 12:32:29.954392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26617 12:32:29.954777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26619 12:32:30.005001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26620 12:32:30.005412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26622 12:32:30.051548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26623 12:32:30.052008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26625 12:32:30.097246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26626 12:32:30.097696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26628 12:32:30.138909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26629 12:32:30.139402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26631 12:32:30.183013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26633 12:32:30.183439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26634 12:32:30.223129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26636 12:32:30.223569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26637 12:32:30.279760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26638 12:32:30.280302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26640 12:32:30.329720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26641 12:32:30.330286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26643 12:32:30.378281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26644 12:32:30.378757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26646 12:32:30.431703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26647 12:32:30.432149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26649 12:32:30.480908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26651 12:32:30.481338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26652 12:32:30.531001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26653 12:32:30.531404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26655 12:32:30.581410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26656 12:32:30.581771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26658 12:32:30.632259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26660 12:32:30.632667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26661 12:32:30.681196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26663 12:32:30.681687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26664 12:32:30.730416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26665 12:32:30.730995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26667 12:32:30.782231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26668 12:32:30.782635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26670 12:32:30.835504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26671 12:32:30.835931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26673 12:32:30.885792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26674 12:32:30.886218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26676 12:32:30.946026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26677 12:32:30.946462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26679 12:32:30.996219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26681 12:32:30.996641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26682 12:32:31.045681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26684 12:32:31.046159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26685 12:32:31.090931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26686 12:32:31.091384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26688 12:32:31.141744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26689 12:32:31.142256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26691 12:32:31.187697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26692 12:32:31.188241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26694 12:32:31.237294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26695 12:32:31.237881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26697 12:32:31.290051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26698 12:32:31.290488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26700 12:32:31.346788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26701 12:32:31.347242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26703 12:32:31.407391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26704 12:32:31.407782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26706 12:32:31.462009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26707 12:32:31.462428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26709 12:32:31.510590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26710 12:32:31.511112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26712 12:32:31.554030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26714 12:32:31.554509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26715 12:32:31.595862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26717 12:32:31.596350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26718 12:32:31.638020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26719 12:32:31.638459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26721 12:32:31.677997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26722 12:32:31.678419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26724 12:32:31.718552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26725 12:32:31.718990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26727 12:32:31.771188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26728 12:32:31.771625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26730 12:32:31.819265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26731 12:32:31.819670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26733 12:32:31.872356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26735 12:32:31.872752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26736 12:32:31.915288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26738 12:32:31.915761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26739 12:32:31.962868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26740 12:32:31.963303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26742 12:32:32.013233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26743 12:32:32.013678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26745 12:32:32.060269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26747 12:32:32.060735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26748 12:32:32.109733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26749 12:32:32.110159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26751 12:32:32.153960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26753 12:32:32.154374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26754 12:32:32.201789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26755 12:32:32.202303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26757 12:32:32.246256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26758 12:32:32.246700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26760 12:32:32.289540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26761 12:32:32.289948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26763 12:32:32.334596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26764 12:32:32.335138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26766 12:32:32.377758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26767 12:32:32.378243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26769 12:32:32.419496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26770 12:32:32.419905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26772 12:32:32.463802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26773 12:32:32.464247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26775 12:32:32.507865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26776 12:32:32.508266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26778 12:32:32.554660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26779 12:32:32.555098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26781 12:32:32.609889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26782 12:32:32.610321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26784 12:32:32.650294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26785 12:32:32.650720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26787 12:32:32.700337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26788 12:32:32.700774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26790 12:32:32.753966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26791 12:32:32.754442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26793 12:32:32.801751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26794 12:32:32.802210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26796 12:32:32.841219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26798 12:32:32.841679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26799 12:32:32.884891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26800 12:32:32.885275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26802 12:32:32.927161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26803 12:32:32.927548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26805 12:32:32.971732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26806 12:32:32.972153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26808 12:32:33.015345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26809 12:32:33.015742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26811 12:32:33.054856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26813 12:32:33.055621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26814 12:32:33.102949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26815 12:32:33.103400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26817 12:32:33.157604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26818 12:32:33.158058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26820 12:32:33.206559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26821 12:32:33.206998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26823 12:32:33.253303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26824 12:32:33.253664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26826 12:32:33.293531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26827 12:32:33.293983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26829 12:32:33.337479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26830 12:32:33.337893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26832 12:32:33.384492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26834 12:32:33.384977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26835 12:32:33.430314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26837 12:32:33.430784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26838 12:32:33.481267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26839 12:32:33.481728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26841 12:32:33.526289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26842 12:32:33.526841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26844 12:32:33.567828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26846 12:32:33.568251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26847 12:32:33.615745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26848 12:32:33.616179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26850 12:32:33.661704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26852 12:32:33.662168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26853 12:32:33.708150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26854 12:32:33.708548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26856 12:32:33.746299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26857 12:32:33.746703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26859 12:32:33.787597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26861 12:32:33.788059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26862 12:32:33.827387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26863 12:32:33.827805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26865 12:32:33.866046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26866 12:32:33.866479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26868 12:32:33.913109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26870 12:32:33.913503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26871 12:32:33.951319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26872 12:32:33.951754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26874 12:32:34.003146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26876 12:32:34.003647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26877 12:32:34.058737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26878 12:32:34.059181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26880 12:32:34.108152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26882 12:32:34.108643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26883 12:32:34.151734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26884 12:32:34.152137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26886 12:32:34.197492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26887 12:32:34.198054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26889 12:32:34.243171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26890 12:32:34.243707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26892 12:32:34.292146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26894 12:32:34.292645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26895 12:32:34.339175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26897 12:32:34.339556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26898 12:32:34.383630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26899 12:32:34.384077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26901 12:32:34.435186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26902 12:32:34.435638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26904 12:32:34.486564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26905 12:32:34.487007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26907 12:32:34.539313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26908 12:32:34.539756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26910 12:32:34.580411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26912 12:32:34.580898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26913 12:32:34.624455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26915 12:32:34.625050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26916 12:32:34.663922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26917 12:32:34.664359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26919 12:32:34.707502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26920 12:32:34.707946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26922 12:32:34.749328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26924 12:32:34.749823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26925 12:32:34.788791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26926 12:32:34.789217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26928 12:32:34.831567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26930 12:32:34.832018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26931 12:32:34.879584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26932 12:32:34.880022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26934 12:32:34.927874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26935 12:32:34.928319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26937 12:32:34.967492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26938 12:32:34.967942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26940 12:32:35.006331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26942 12:32:35.006825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26943 12:32:35.049116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26944 12:32:35.049616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26946 12:32:35.091619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26947 12:32:35.092050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26949 12:32:35.121297 <47>[ 304.478511] systemd-journald[109]: Sent WATCHDOG=1 notification.
26950 12:32:35.137275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26951 12:32:35.137700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26953 12:32:35.179419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26955 12:32:35.179872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26956 12:32:35.219550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26957 12:32:35.219992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26959 12:32:35.259044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26960 12:32:35.259452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26962 12:32:35.298363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26963 12:32:35.298814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26965 12:32:35.335889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26966 12:32:35.336338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26968 12:32:35.378893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26970 12:32:35.379379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26971 12:32:35.427261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26972 12:32:35.427712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26974 12:32:35.469334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26975 12:32:35.469785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26977 12:32:35.515104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26978 12:32:35.515546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26980 12:32:35.552166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26981 12:32:35.552606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26983 12:32:35.589637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26984 12:32:35.590084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26986 12:32:35.626671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26987 12:32:35.627117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26989 12:32:35.666041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26991 12:32:35.666521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26992 12:32:35.707296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26993 12:32:35.707871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26995 12:32:35.750427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26996 12:32:35.750781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26998 12:32:35.795413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26999 12:32:35.795827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
27001 12:32:35.831880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
27002 12:32:35.832286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
27004 12:32:35.869412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
27005 12:32:35.869890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
27007 12:32:35.909499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
27009 12:32:35.910000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
27010 12:32:35.950304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
27012 12:32:35.951124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
27013 12:32:35.995422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
27014 12:32:35.995831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
27016 12:32:36.034675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
27018 12:32:36.035136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
27019 12:32:36.092836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
27020 12:32:36.093231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
27022 12:32:36.135901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
27023 12:32:36.136518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
27025 12:32:36.175673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
27026 12:32:36.176135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
27028 12:32:36.213152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
27029 12:32:36.213590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
27031 12:32:36.251751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
27032 12:32:36.252263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
27034 12:32:36.291957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
27035 12:32:36.292444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
27037 12:32:36.333986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
27038 12:32:36.334489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
27040 12:32:36.381071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
27041 12:32:36.381591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
27043 12:32:36.426715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
27044 12:32:36.427143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
27046 12:32:36.466910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
27047 12:32:36.467361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
27049 12:32:36.508056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
27051 12:32:36.508554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
27052 12:32:36.553369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
27054 12:32:36.553859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
27055 12:32:36.596099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
27057 12:32:36.596554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
27058 12:32:36.633960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
27059 12:32:36.634381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
27061 12:32:36.673663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
27062 12:32:36.674094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
27064 12:32:36.721548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
27065 12:32:36.721960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
27067 12:32:36.774239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
27068 12:32:36.774669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
27070 12:32:36.825655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
27071 12:32:36.826058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
27073 12:32:36.867580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27075 12:32:36.868081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27076 12:32:36.907923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27077 12:32:36.908487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27079 12:32:36.946658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27080 12:32:36.947071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27082 12:32:36.984053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27083 12:32:36.984518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27085 12:32:37.029255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27086 12:32:37.029816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27088 12:32:37.069694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27090 12:32:37.070167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27091 12:32:37.109708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27093 12:32:37.110431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27094 12:32:37.148545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27096 12:32:37.149023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27097 12:32:37.191217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27098 12:32:37.191671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27100 12:32:37.231139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27101 12:32:37.231570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27103 12:32:37.274769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27105 12:32:37.275255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27106 12:32:37.317164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27107 12:32:37.317593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27109 12:32:37.359538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27111 12:32:37.360021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27112 12:32:37.403024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27113 12:32:37.403457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27115 12:32:37.447525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27116 12:32:37.447957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27118 12:32:37.496113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27119 12:32:37.496547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27121 12:32:37.542874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27122 12:32:37.543323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27124 12:32:37.591555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27125 12:32:37.592125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27127 12:32:37.645623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27129 12:32:37.646358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27130 12:32:37.694851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27131 12:32:37.695282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27133 12:32:37.750809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27134 12:32:37.751251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27136 12:32:37.807773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27137 12:32:37.808223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27139 12:32:37.867711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27140 12:32:37.868286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27142 12:32:37.927211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27143 12:32:37.927603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27145 12:32:37.985610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27146 12:32:37.986053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27148 12:32:38.042826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27150 12:32:38.043312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27151 12:32:38.101663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27152 12:32:38.102163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27154 12:32:38.159578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27156 12:32:38.160059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27157 12:32:38.218221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27158 12:32:38.218614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27160 12:32:38.275815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27161 12:32:38.276266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27163 12:32:38.332322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27165 12:32:38.332800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27166 12:32:38.390563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27167 12:32:38.390990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27169 12:32:38.447086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27170 12:32:38.447536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27172 12:32:38.497718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27174 12:32:38.498199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27175 12:32:38.555296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27176 12:32:38.555816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27178 12:32:38.593793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27180 12:32:38.594232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27181 12:32:38.635995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27182 12:32:38.636439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27184 12:32:38.676331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27185 12:32:38.676849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27187 12:32:38.717241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27188 12:32:38.717683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27190 12:32:38.760098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27191 12:32:38.760491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27193 12:32:38.800111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27194 12:32:38.800554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27196 12:32:38.841713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27197 12:32:38.842118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27199 12:32:38.893674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27201 12:32:38.894132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27202 12:32:38.944391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27204 12:32:38.944842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27205 12:32:38.982504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27207 12:32:38.983040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27208 12:32:39.033809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27209 12:32:39.034220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27211 12:32:39.093937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27212 12:32:39.094376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27214 12:32:39.154776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27215 12:32:39.155204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27217 12:32:39.215107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27218 12:32:39.215493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27220 12:32:39.276047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27221 12:32:39.276452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27223 12:32:39.334130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27224 12:32:39.334677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27226 12:32:39.385902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27228 12:32:39.386360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27229 12:32:39.436244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27231 12:32:39.436727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27232 12:32:39.495778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27233 12:32:39.496194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27235 12:32:39.554645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27236 12:32:39.555083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27238 12:32:39.611539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27239 12:32:39.611965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27241 12:32:39.668593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27243 12:32:39.669393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27244 12:32:39.718064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27245 12:32:39.718452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27247 12:32:39.757632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27248 12:32:39.758026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27250 12:32:39.805402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27251 12:32:39.805786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27253 12:32:39.855100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27254 12:32:39.855546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27256 12:32:39.899940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27257 12:32:39.900375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27259 12:32:39.945897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27261 12:32:39.946345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27262 12:32:39.989940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27263 12:32:39.990402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27265 12:32:40.031586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27266 12:32:40.032072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27268 12:32:40.083418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27270 12:32:40.084170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27271 12:32:40.135547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27272 12:32:40.136021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27274 12:32:40.194763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27275 12:32:40.195199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27277 12:32:40.235092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27278 12:32:40.235532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27280 12:32:40.274768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27282 12:32:40.275220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27283 12:32:40.319966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27284 12:32:40.320384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27286 12:32:40.360300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27288 12:32:40.360794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27289 12:32:40.406879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27290 12:32:40.407348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27292 12:32:40.459478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27293 12:32:40.459922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27295 12:32:40.509600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27297 12:32:40.510064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27298 12:32:40.554200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27300 12:32:40.554677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27301 12:32:40.609787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27302 12:32:40.610832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27304 12:32:40.667416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27305 12:32:40.667849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27307 12:32:40.717163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27308 12:32:40.717752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27310 12:32:40.756469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27312 12:32:40.757204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27313 12:32:40.815219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27314 12:32:40.815755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27316 12:32:40.874608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27317 12:32:40.875072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27319 12:32:40.934355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27321 12:32:40.934838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27322 12:32:40.982514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27323 12:32:40.982961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27325 12:32:41.031844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27326 12:32:41.032297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27328 12:32:41.070027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27329 12:32:41.070411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27331 12:32:41.111440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27332 12:32:41.111839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27334 12:32:41.159050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27335 12:32:41.159480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27337 12:32:41.215306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27339 12:32:41.215779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27340 12:32:41.259733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27341 12:32:41.260176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27343 12:32:41.310664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27345 12:32:41.311117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27346 12:32:41.359837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27347 12:32:41.360310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27349 12:32:41.413737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27350 12:32:41.414173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27352 12:32:41.459108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27353 12:32:41.459542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27355 12:32:41.503206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27356 12:32:41.503650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27358 12:32:41.550738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27359 12:32:41.551170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27361 12:32:41.594803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27362 12:32:41.595265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27364 12:32:41.645525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27365 12:32:41.646042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27367 12:32:41.689236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27369 12:32:41.689580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27370 12:32:41.734896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27372 12:32:41.735387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27373 12:32:41.782492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27374 12:32:41.782945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27376 12:32:41.826948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27377 12:32:41.827393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27379 12:32:41.884533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27381 12:32:41.885220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27382 12:32:41.942797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27384 12:32:41.943283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27385 12:32:41.999973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27387 12:32:42.000466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27388 12:32:42.059128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27389 12:32:42.059540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27391 12:32:42.118016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27393 12:32:42.118632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27394 12:32:42.175484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27395 12:32:42.175956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27397 12:32:42.233358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27398 12:32:42.233851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27400 12:32:42.290499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27401 12:32:42.290936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27403 12:32:42.349585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27404 12:32:42.350056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27406 12:32:42.408081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27407 12:32:42.408525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27409 12:32:42.464761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27410 12:32:42.465215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27412 12:32:42.509377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27413 12:32:42.509895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27415 12:32:42.548911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27416 12:32:42.549470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27418 12:32:42.592842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27419 12:32:42.593267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27421 12:32:42.637840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27422 12:32:42.638198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27424 12:32:42.678905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27425 12:32:42.679346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27427 12:32:42.726844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27428 12:32:42.727279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27430 12:32:42.766235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27431 12:32:42.766689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27433 12:32:42.806058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27434 12:32:42.806480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27436 12:32:42.855111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27437 12:32:42.855539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27439 12:32:42.902481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27441 12:32:42.902982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27442 12:32:42.955447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27444 12:32:42.955954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27445 12:32:43.005627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27447 12:32:43.006017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27448 12:32:43.057248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27449 12:32:43.057658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27451 12:32:43.101374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27452 12:32:43.101802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27454 12:32:43.158517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27455 12:32:43.158921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27457 12:32:43.214856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27459 12:32:43.215384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27460 12:32:43.266500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27461 12:32:43.266923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27463 12:32:43.314556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27464 12:32:43.314997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27466 12:32:43.358228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27467 12:32:43.358658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27469 12:32:43.409289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27471 12:32:43.409773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27472 12:32:43.458451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27473 12:32:43.458872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27475 12:32:43.499822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27477 12:32:43.500276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27478 12:32:43.555366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27479 12:32:43.555777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27481 12:32:43.614336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27483 12:32:43.614807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27484 12:32:43.659917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27485 12:32:43.660406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27487 12:32:43.718997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27488 12:32:43.719431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27490 12:32:43.775653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27491 12:32:43.776145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27493 12:32:43.832452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27495 12:32:43.832875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27496 12:32:43.889411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27497 12:32:43.889925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27499 12:32:43.946567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27501 12:32:43.947033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27502 12:32:44.005829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27503 12:32:44.006326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27505 12:32:44.062874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27506 12:32:44.063283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27508 12:32:44.119940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27509 12:32:44.120417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27511 12:32:44.178382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27512 12:32:44.178792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27514 12:32:44.238091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27515 12:32:44.238509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27517 12:32:44.297440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27518 12:32:44.297871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27520 12:32:44.355258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27521 12:32:44.355657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27523 12:32:44.413818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27524 12:32:44.414249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27526 12:32:44.473495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27527 12:32:44.473946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27529 12:32:44.531338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27530 12:32:44.531752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27532 12:32:44.590280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27533 12:32:44.590690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27535 12:32:44.642753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27537 12:32:44.643236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27538 12:32:44.686582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27539 12:32:44.687004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27541 12:32:44.731592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27542 12:32:44.732118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27544 12:32:44.777457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27545 12:32:44.777978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27547 12:32:44.821319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27548 12:32:44.821823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27550 12:32:44.859577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27551 12:32:44.860013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27553 12:32:44.906653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27554 12:32:44.907096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27556 12:32:44.956394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27558 12:32:44.956881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27559 12:32:45.005427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27560 12:32:45.005845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27562 12:32:45.051033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27563 12:32:45.051468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27565 12:32:45.096604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27567 12:32:45.097237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27568 12:32:45.139562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27569 12:32:45.140013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27571 12:32:45.186928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27573 12:32:45.187413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27574 12:32:45.229637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27575 12:32:45.230083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27577 12:32:45.269399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27579 12:32:45.269858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27580 12:32:45.309975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27581 12:32:45.310428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27583 12:32:45.354326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27584 12:32:45.354785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27586 12:32:45.410562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27588 12:32:45.411039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27589 12:32:45.472503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27591 12:32:45.473014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27592 12:32:45.528968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27593 12:32:45.529368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27595 12:32:45.571775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27597 12:32:45.572205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27598 12:32:45.616277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27600 12:32:45.616787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27601 12:32:45.658780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27602 12:32:45.659232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27604 12:32:45.703840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27605 12:32:45.704306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27607 12:32:45.754206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27608 12:32:45.754607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27610 12:32:45.802366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27612 12:32:45.802887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27613 12:32:45.852144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27615 12:32:45.852523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27616 12:32:45.904069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27617 12:32:45.904537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27619 12:32:45.956870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27621 12:32:45.957596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27622 12:32:46.010007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27623 12:32:46.010405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27625 12:32:46.061717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27626 12:32:46.062111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27628 12:32:46.103184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27629 12:32:46.103735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27631 12:32:46.142721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27632 12:32:46.143157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27634 12:32:46.181909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27635 12:32:46.182342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27637 12:32:46.224305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27639 12:32:46.224750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27640 12:32:46.263756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27641 12:32:46.264209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27643 12:32:46.326850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27644 12:32:46.327266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27646 12:32:46.367836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27647 12:32:46.368282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27649 12:32:46.414286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27650 12:32:46.414701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27652 12:32:46.456501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27654 12:32:46.456972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27655 12:32:46.503516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27657 12:32:46.503980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27658 12:32:46.551618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27660 12:32:46.552108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27661 12:32:46.597701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27662 12:32:46.598223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27664 12:32:46.646007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27666 12:32:46.646687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27667 12:32:46.697170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27668 12:32:46.697724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27670 12:32:46.747180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27671 12:32:46.747716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27673 12:32:46.793401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27675 12:32:46.793885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27676 12:32:46.835659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27677 12:32:46.836109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27679 12:32:46.880455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27681 12:32:46.880941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27682 12:32:46.930432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27683 12:32:46.930861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27685 12:32:46.983165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27687 12:32:46.983632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27688 12:32:47.026015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27689 12:32:47.026456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27691 12:32:47.068454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27693 12:32:47.068836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27694 12:32:47.118697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27696 12:32:47.119183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27697 12:32:47.159922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27698 12:32:47.160362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27700 12:32:47.218063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27701 12:32:47.218493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27703 12:32:47.259592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27704 12:32:47.260007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27706 12:32:47.299372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27708 12:32:47.299853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27709 12:32:47.338490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27710 12:32:47.338983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27712 12:32:47.381238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27713 12:32:47.381668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27715 12:32:47.430496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27716 12:32:47.430945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27718 12:32:47.481227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27719 12:32:47.481670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27721 12:32:47.534867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27722 12:32:47.535301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27724 12:32:47.594857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27725 12:32:47.595256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27727 12:32:47.654672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27728 12:32:47.655056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27730 12:32:47.714531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27731 12:32:47.715082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27733 12:32:47.776996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27734 12:32:47.777422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27736 12:32:47.837250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27737 12:32:47.837698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27739 12:32:47.896299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27741 12:32:47.896881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27742 12:32:47.955828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27743 12:32:47.956271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27745 12:32:48.015413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27746 12:32:48.015843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27748 12:32:48.075145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27750 12:32:48.075608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27751 12:32:48.129618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27752 12:32:48.133731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27754 12:32:48.190662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27756 12:32:48.191046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27757 12:32:48.255742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27758 12:32:48.256176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27760 12:32:48.303383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27761 12:32:48.303815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27763 12:32:48.366434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27764 12:32:48.366816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27766 12:32:48.414894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27767 12:32:48.415344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27769 12:32:48.462006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27770 12:32:48.462455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27772 12:32:48.510902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27774 12:32:48.511579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27775 12:32:48.553739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27776 12:32:48.554236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27778 12:32:48.605751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27779 12:32:48.606238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27781 12:32:48.657545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27783 12:32:48.658029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27784 12:32:48.707169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27785 12:32:48.707677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27787 12:32:48.751457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27788 12:32:48.751931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27790 12:32:48.797031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27791 12:32:48.797492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27793 12:32:48.841720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27794 12:32:48.842140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27796 12:32:48.898954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27797 12:32:48.899442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27799 12:32:48.954724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27800 12:32:48.955165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27802 12:32:49.010424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27803 12:32:49.010981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27805 12:32:49.066772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27806 12:32:49.067193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27808 12:32:49.123956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27809 12:32:49.124383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27811 12:32:49.182972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27813 12:32:49.183457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27814 12:32:49.240454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27816 12:32:49.240937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27817 12:32:49.296911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27818 12:32:49.297318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27820 12:32:49.351856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27822 12:32:49.352348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27823 12:32:49.410775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27824 12:32:49.411206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27826 12:32:49.467059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27827 12:32:49.467510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27829 12:32:49.523054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27830 12:32:49.523464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27832 12:32:49.578028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27834 12:32:49.578526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27835 12:32:49.630060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27836 12:32:49.630508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27838 12:32:49.682598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27839 12:32:49.683053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27841 12:32:49.730264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27842 12:32:49.730728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27844 12:32:49.780906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27846 12:32:49.781316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27847 12:32:49.830545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27848 12:32:49.830914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27850 12:32:49.870464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27851 12:32:49.870970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27853 12:32:49.915029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27854 12:32:49.915468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27856 12:32:49.967191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27857 12:32:49.967653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27859 12:32:50.020975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27860 12:32:50.021469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27862 12:32:50.065762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27863 12:32:50.066182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27865 12:32:50.115802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27866 12:32:50.116261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27868 12:32:50.175494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27869 12:32:50.175945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27871 12:32:50.235928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27872 12:32:50.236389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27874 12:32:50.294815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27875 12:32:50.295243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27877 12:32:50.352800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27878 12:32:50.353208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27880 12:32:50.409578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27881 12:32:50.410156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27883 12:32:50.467999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27884 12:32:50.468423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27886 12:32:50.530909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27888 12:32:50.531368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27889 12:32:50.590453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27890 12:32:50.590855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27892 12:32:50.650442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27893 12:32:50.650879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27895 12:32:50.710208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27896 12:32:50.710655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27898 12:32:50.770181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27899 12:32:50.770541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27901 12:32:50.829787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27902 12:32:50.830231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27904 12:32:50.890651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27905 12:32:50.891040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27907 12:32:50.949715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27908 12:32:50.950106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27910 12:32:51.007929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27912 12:32:51.008421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27913 12:32:51.067349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27915 12:32:51.068004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27916 12:32:51.127453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27917 12:32:51.127851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27919 12:32:51.187161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27921 12:32:51.187656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27922 12:32:51.246831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27924 12:32:51.247324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27925 12:32:51.307434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27926 12:32:51.307889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27928 12:32:51.365697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27929 12:32:51.366134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27931 12:32:51.418812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27932 12:32:51.419241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27934 12:32:51.479888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27936 12:32:51.480383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27937 12:32:51.527222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27939 12:32:51.527685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27940 12:32:51.574664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27941 12:32:51.575130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27943 12:32:51.622662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27944 12:32:51.623104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27946 12:32:51.671370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27948 12:32:51.671850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27949 12:32:51.722566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27950 12:32:51.722971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27952 12:32:51.775886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27953 12:32:51.776335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27955 12:32:51.824120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27956 12:32:51.824567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27958 12:32:51.874398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27959 12:32:51.874833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27961 12:32:51.927242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27962 12:32:51.927716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27964 12:32:51.975525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27966 12:32:51.976009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27967 12:32:52.026119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27969 12:32:52.026598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27970 12:32:52.070106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27971 12:32:52.070563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27973 12:32:52.115360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27975 12:32:52.115820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27976 12:32:52.163237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27978 12:32:52.163726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27979 12:32:52.212342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27981 12:32:52.212781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27982 12:32:52.256467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27984 12:32:52.257058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27985 12:32:52.303289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27986 12:32:52.303744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27988 12:32:52.347238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27989 12:32:52.347670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27991 12:32:52.392076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27992 12:32:52.392534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27994 12:32:52.435837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27995 12:32:52.436258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27997 12:32:52.480741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27998 12:32:52.481187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
28000 12:32:52.527718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
28001 12:32:52.528110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
28003 12:32:52.571854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
28004 12:32:52.572270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
28006 12:32:52.609993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
28008 12:32:52.610465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
28009 12:32:52.652008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
28011 12:32:52.652457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
28012 12:32:52.699293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
28013 12:32:52.699748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
28015 12:32:52.745394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
28017 12:32:52.746143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
28018 12:32:52.796913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
28020 12:32:52.797390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
28021 12:32:52.834759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
28022 12:32:52.835221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
28024 12:32:52.874408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
28025 12:32:52.874844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
28027 12:32:52.921725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
28028 12:32:52.922164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
28030 12:32:52.960096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
28031 12:32:52.960538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
28033 12:32:53.005618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
28034 12:32:53.006077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
28036 12:32:53.042418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
28037 12:32:53.042850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
28039 12:32:53.078752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
28041 12:32:53.079528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
28042 12:32:53.115532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
28043 12:32:53.115976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
28045 12:32:53.153737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
28046 12:32:53.154151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
28048 12:32:53.195186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
28050 12:32:53.195654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
28051 12:32:53.238744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
28053 12:32:53.239330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
28054 12:32:53.289478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
28055 12:32:53.290223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
28057 12:32:53.334052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
28059 12:32:53.334527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
28060 12:32:53.372025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
28061 12:32:53.372433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
28063 12:32:53.413805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
28065 12:32:53.414241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
28066 12:32:53.455365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
28067 12:32:53.455753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
28069 12:32:53.502391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
28070 12:32:53.502759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
28072 12:32:53.551944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
28073 12:32:53.552448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28075 12:32:53.588586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28077 12:32:53.589179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28078 12:32:53.627487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28079 12:32:53.628051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28081 12:32:53.670442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28082 12:32:53.670856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28084 12:32:53.718895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28086 12:32:53.719356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28087 12:32:53.766434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28089 12:32:53.766858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28090 12:32:53.815171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28091 12:32:53.815627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28093 12:32:53.864400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28095 12:32:53.864884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28096 12:32:53.910147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28097 12:32:53.910639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28099 12:32:53.963005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28100 12:32:53.963567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28102 12:32:54.011398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28104 12:32:54.011863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28105 12:32:54.057640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28106 12:32:54.058096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28108 12:32:54.106217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28110 12:32:54.106702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28111 12:32:54.146507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28112 12:32:54.146937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28114 12:32:54.198563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28115 12:32:54.199039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28117 12:32:54.245255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28119 12:32:54.245806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28120 12:32:54.295914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28121 12:32:54.296377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28123 12:32:54.348908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28124 12:32:54.349327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28126 12:32:54.401344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28127 12:32:54.401755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28129 12:32:54.448051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28131 12:32:54.448825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28132 12:32:54.488810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28133 12:32:54.489295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28135 12:32:54.532462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28137 12:32:54.532919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28138 12:32:54.574652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28140 12:32:54.575279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28141 12:32:54.619758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28142 12:32:54.620207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28144 12:32:54.677220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28145 12:32:54.677678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28147 12:32:54.727232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28149 12:32:54.727736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28150 12:32:54.777797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28152 12:32:54.778281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28153 12:32:54.827240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28154 12:32:54.827648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28156 12:32:54.875614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28157 12:32:54.876072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28159 12:32:54.936558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28161 12:32:54.937044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28162 12:32:54.995209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28163 12:32:54.995659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28165 12:32:55.051458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28167 12:32:55.051960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28168 12:32:55.102914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28170 12:32:55.103380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28171 12:32:55.150404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28172 12:32:55.150807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28174 12:32:55.201581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28175 12:32:55.202055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28177 12:32:55.249904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28178 12:32:55.250495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28180 12:32:55.289352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28182 12:32:55.289796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28183 12:32:55.333996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28184 12:32:55.334387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28186 12:32:55.378726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28187 12:32:55.379152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28189 12:32:55.426444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28190 12:32:55.426895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28192 12:32:55.473498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28194 12:32:55.473986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28195 12:32:55.531543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28196 12:32:55.531982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28198 12:32:55.591214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28199 12:32:55.591673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28201 12:32:55.650549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28202 12:32:55.651050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28204 12:32:55.711348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28205 12:32:55.711788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28207 12:32:55.761686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28208 12:32:55.762198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28210 12:32:55.810240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28211 12:32:55.810737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28213 12:32:55.863199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28214 12:32:55.863795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28216 12:32:55.905865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28217 12:32:55.906329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28219 12:32:55.950766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28220 12:32:55.951205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28222 12:32:55.995017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28224 12:32:55.995469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28225 12:32:56.042625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28226 12:32:56.043043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28228 12:32:56.090046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28230 12:32:56.090444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28231 12:32:56.141376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28232 12:32:56.141961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28234 12:32:56.192317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28236 12:32:56.192797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28237 12:32:56.238622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28238 12:32:56.239085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28240 12:32:56.287290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28241 12:32:56.287707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28243 12:32:56.337426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28244 12:32:56.337960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28246 12:32:56.387327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28248 12:32:56.387781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28249 12:32:56.434917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28251 12:32:56.435376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28252 12:32:56.482416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28254 12:32:56.482851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28255 12:32:56.554655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28256 12:32:56.555061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28258 12:32:56.608195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28259 12:32:56.608627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28261 12:32:56.652022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28263 12:32:56.652515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28264 12:32:56.699298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28265 12:32:56.699771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28267 12:32:56.749859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28269 12:32:56.750351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28270 12:32:56.798446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28271 12:32:56.798883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28273 12:32:56.846088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28275 12:32:56.846487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28276 12:32:56.896425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28277 12:32:56.896940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28279 12:32:56.942024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28281 12:32:56.942438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28282 12:32:56.994264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28284 12:32:56.994905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28285 12:32:57.041173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28286 12:32:57.041625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28288 12:32:57.087308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28289 12:32:57.087750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28291 12:32:57.129155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28292 12:32:57.129586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28294 12:32:57.167891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28295 12:32:57.168328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28297 12:32:57.214856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28298 12:32:57.215321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28300 12:32:57.255568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28301 12:32:57.256032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28303 12:32:57.294194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28305 12:32:57.294647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28306 12:32:57.341569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28308 12:32:57.342060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28309 12:32:57.381710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28310 12:32:57.382136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28312 12:32:57.424984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28314 12:32:57.425383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28315 12:32:57.467135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28316 12:32:57.467521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28318 12:32:57.514650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28319 12:32:57.515089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28321 12:32:57.561185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28322 12:32:57.561681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28324 12:32:57.600688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28325 12:32:57.601148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28327 12:32:57.638856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28328 12:32:57.639361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28330 12:32:57.681268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28332 12:32:57.681911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28333 12:32:57.721933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28334 12:32:57.722495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28336 12:32:57.764920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28337 12:32:57.765317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28339 12:32:57.807115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28340 12:32:57.807672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28342 12:32:57.849835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28344 12:32:57.850240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28345 12:32:57.890382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28346 12:32:57.890787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28348 12:32:57.930901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28349 12:32:57.931368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28351 12:32:57.969856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28352 12:32:57.970303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28354 12:32:58.016273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28356 12:32:58.016744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28357 12:32:58.065996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28358 12:32:58.066429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28360 12:32:58.115537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28361 12:32:58.115966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28363 12:32:58.162877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28364 12:32:58.163315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28366 12:32:58.217422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28367 12:32:58.217818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28369 12:32:58.266896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28371 12:32:58.267370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28372 12:32:58.313941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28374 12:32:58.314411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28375 12:32:58.363142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28376 12:32:58.363576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28378 12:32:58.409991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28380 12:32:58.410460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28381 12:32:58.453046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28382 12:32:58.453628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28384 12:32:58.495090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28385 12:32:58.495602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28387 12:32:58.537761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28388 12:32:58.538221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28390 12:32:58.578487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28391 12:32:58.578950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28393 12:32:58.619512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28394 12:32:58.619966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28396 12:32:58.665117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28397 12:32:58.665536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28399 12:32:58.704224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28401 12:32:58.704634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28402 12:32:58.749670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28404 12:32:58.750099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28405 12:32:58.794010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28407 12:32:58.794448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28408 12:32:58.835802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28409 12:32:58.836215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28411 12:32:58.879008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28412 12:32:58.879459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28414 12:32:58.921167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28415 12:32:58.921628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28417 12:32:58.965332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28419 12:32:58.965796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28420 12:32:59.007076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28421 12:32:59.007506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28423 12:32:59.054728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28424 12:32:59.055156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28426 12:32:59.105012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28427 12:32:59.105462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28429 12:32:59.152277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28431 12:32:59.152750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28432 12:32:59.199189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28433 12:32:59.199602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28435 12:32:59.237971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28436 12:32:59.238382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28438 12:32:59.282094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28439 12:32:59.282534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28441 12:32:59.325234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28442 12:32:59.325715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28444 12:32:59.373103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28445 12:32:59.373547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28447 12:32:59.425236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28448 12:32:59.425669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28450 12:32:59.469234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28452 12:32:59.469718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28453 12:32:59.507727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28454 12:32:59.508171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28456 12:32:59.547403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28457 12:32:59.549755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28459 12:32:59.593353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28460 12:32:59.593760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28462 12:32:59.641940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28464 12:32:59.642379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28465 12:32:59.686751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28466 12:32:59.687207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28468 12:32:59.731977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28469 12:32:59.732447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28471 12:32:59.785209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28472 12:32:59.785643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28474 12:32:59.833679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28475 12:32:59.834136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28477 12:32:59.877894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28478 12:32:59.878303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28480 12:32:59.918724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28482 12:32:59.919235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28483 12:32:59.962229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28484 12:32:59.962661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28486 12:33:00.005842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28487 12:33:00.006272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28489 12:33:00.047179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28491 12:33:00.047654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28492 12:33:00.092492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28494 12:33:00.092984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28495 12:33:00.139942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28497 12:33:00.140396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28498 12:33:00.183690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28500 12:33:00.184178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28501 12:33:00.226378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28502 12:33:00.226787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28504 12:33:00.269988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28505 12:33:00.270402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28507 12:33:00.314392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28509 12:33:00.315062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28510 12:33:00.354000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28511 12:33:00.354498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28513 12:33:00.403283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28514 12:33:00.403659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28516 12:33:00.446016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28517 12:33:00.446466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28519 12:33:00.486325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28520 12:33:00.486779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28522 12:33:00.541777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28524 12:33:00.542239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28525 12:33:00.590714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28527 12:33:00.591188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28528 12:33:00.630792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28529 12:33:00.631180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28531 12:33:00.674006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28533 12:33:00.674490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28534 12:33:00.711939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28536 12:33:00.712373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28537 12:33:00.762602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28539 12:33:00.763031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28540 12:33:00.810150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28541 12:33:00.810663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28543 12:33:00.859522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28544 12:33:00.859984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28546 12:33:00.905908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28547 12:33:00.906310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28549 12:33:00.954415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28551 12:33:00.954890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28552 12:33:00.993376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28553 12:33:00.993774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28555 12:33:01.031281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28556 12:33:01.031721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28558 12:33:01.071595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28559 12:33:01.072054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28561 12:33:01.112283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28563 12:33:01.112703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28564 12:33:01.151152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28566 12:33:01.151911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28567 12:33:01.194222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28568 12:33:01.194803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28570 12:33:01.233434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28571 12:33:01.233994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28573 12:33:01.281843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28575 12:33:01.282321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28576 12:33:01.329428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28578 12:33:01.329936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28579 12:33:01.375803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28581 12:33:01.376265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28582 12:33:01.425606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28583 12:33:01.426070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28585 12:33:01.467521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28586 12:33:01.467956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28588 12:33:01.512179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28590 12:33:01.512673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28591 12:33:01.559022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28592 12:33:01.559459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28594 12:33:01.607113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28596 12:33:01.607602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28597 12:33:01.662434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28599 12:33:01.662912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28600 12:33:01.718230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28601 12:33:01.718676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28603 12:33:01.762798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28605 12:33:01.763260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28606 12:33:01.801926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28607 12:33:01.802368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28609 12:33:01.844130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28610 12:33:01.844563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28612 12:33:01.887582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28614 12:33:01.888056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28615 12:33:01.935355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28616 12:33:01.935794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28618 12:33:01.982709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28620 12:33:01.983181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28621 12:33:02.029854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28622 12:33:02.030283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28624 12:33:02.073678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28625 12:33:02.074138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28627 12:33:02.119547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28629 12:33:02.120038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28630 12:33:02.161950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28631 12:33:02.162392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28633 12:33:02.205255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28634 12:33:02.205686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28636 12:33:02.254166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28637 12:33:02.254630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28639 12:33:02.299599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28641 12:33:02.300030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28642 12:33:02.342761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28643 12:33:02.343220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28645 12:33:02.385818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28646 12:33:02.386254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28648 12:33:02.427412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28649 12:33:02.427876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28651 12:33:02.470954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28652 12:33:02.471420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28654 12:33:02.513818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28655 12:33:02.514249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28657 12:33:02.554093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28658 12:33:02.554529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28660 12:33:02.591057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28661 12:33:02.591475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28663 12:33:02.626715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28665 12:33:02.627202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28666 12:33:02.672507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28668 12:33:02.672990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28669 12:33:02.723436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28670 12:33:02.723889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28672 12:33:02.774483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28673 12:33:02.774874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28675 12:33:02.821128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28676 12:33:02.821516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28678 12:33:02.865675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28679 12:33:02.866230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28681 12:33:02.903619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28682 12:33:02.904028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28684 12:33:02.949565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28685 12:33:02.949990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28687 12:33:02.994695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28688 12:33:02.995224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28690 12:33:03.039770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28692 12:33:03.040180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28693 12:33:03.080249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28694 12:33:03.080638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28696 12:33:03.117645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28697 12:33:03.118132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28699 12:33:03.159356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28700 12:33:03.159773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28702 12:33:03.201338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28703 12:33:03.201792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28705 12:33:03.245470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28706 12:33:03.245886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28708 12:33:03.293776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28709 12:33:03.294223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28711 12:33:03.335796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28712 12:33:03.336204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28714 12:33:03.382021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28716 12:33:03.382513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28717 12:33:03.423816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28719 12:33:03.424297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28720 12:33:03.469730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28721 12:33:03.470213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28723 12:33:03.512347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28724 12:33:03.512764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28726 12:33:03.550502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28727 12:33:03.550889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28729 12:33:03.596151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28730 12:33:03.596579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28732 12:33:03.637765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28733 12:33:03.638313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28735 12:33:03.675835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28736 12:33:03.676311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28738 12:33:03.723223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28739 12:33:03.723657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28741 12:33:03.761660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28743 12:33:03.762136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28744 12:33:03.810858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28745 12:33:03.811253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28747 12:33:03.862555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28749 12:33:03.863028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28750 12:33:03.911428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28751 12:33:03.911860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28753 12:33:03.960268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28755 12:33:03.960745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28756 12:33:04.015201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28757 12:33:04.015643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28759 12:33:04.056036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28760 12:33:04.056560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28762 12:33:04.095050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28764 12:33:04.095691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28765 12:33:04.140491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28767 12:33:04.140895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28768 12:33:04.188783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28769 12:33:04.189195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28771 12:33:04.227845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28772 12:33:04.228275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28774 12:33:04.271365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28775 12:33:04.271808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28777 12:33:04.320135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28778 12:33:04.320509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28780 12:33:04.358036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28781 12:33:04.358428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28783 12:33:04.399560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28785 12:33:04.400242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28786 12:33:04.438978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28787 12:33:04.439453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28789 12:33:04.491188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28790 12:33:04.491619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28792 12:33:04.546716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28794 12:33:04.547268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28795 12:33:04.597590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28796 12:33:04.598024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28798 12:33:04.645985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28800 12:33:04.646501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28801 12:33:04.693548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28803 12:33:04.694034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28804 12:33:04.734211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28805 12:33:04.734658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28807 12:33:04.774437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28808 12:33:04.774933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28810 12:33:04.812892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28811 12:33:04.813324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28813 12:33:04.853291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28815 12:33:04.854055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28816 12:33:04.897021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28818 12:33:04.897595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28819 12:33:04.939292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28820 12:33:04.939860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28822 12:33:04.983339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28823 12:33:04.983805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28825 12:33:05.026068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28826 12:33:05.026526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28828 12:33:05.072054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28829 12:33:05.072539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28831 12:33:05.121366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28832 12:33:05.121890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28834 12:33:05.169809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28835 12:33:05.170194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28837 12:33:05.221258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28839 12:33:05.221754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28840 12:33:05.266773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28841 12:33:05.267190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28843 12:33:05.311167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28844 12:33:05.311585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28846 12:33:05.351151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28847 12:33:05.351604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28849 12:33:05.400390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28851 12:33:05.400868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28852 12:33:05.440448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28854 12:33:05.441127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28855 12:33:05.483110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28856 12:33:05.483542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28858 12:33:05.526411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28860 12:33:05.526801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28861 12:33:05.570980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28862 12:33:05.571405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28864 12:33:05.620949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28865 12:33:05.621317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28867 12:33:05.675923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28868 12:33:05.676450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28870 12:33:05.725158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28871 12:33:05.725616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28873 12:33:05.763127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28874 12:33:05.763588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28876 12:33:05.803400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28877 12:33:05.803940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28879 12:33:05.849992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28881 12:33:05.850477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28882 12:33:05.891927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28883 12:33:05.892423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28885 12:33:05.941566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28886 12:33:05.942003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28888 12:33:05.990118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28889 12:33:05.990579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28891 12:33:06.026480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28892 12:33:06.026921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28894 12:33:06.063827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28895 12:33:06.064279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28897 12:33:06.104319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28899 12:33:06.105089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28900 12:33:06.142259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28901 12:33:06.142735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28903 12:33:06.180890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28904 12:33:06.181378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28906 12:33:06.222853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28908 12:33:06.223330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28909 12:33:06.266011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28910 12:33:06.266461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28912 12:33:06.306275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28913 12:33:06.306706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28915 12:33:06.353981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28917 12:33:06.354438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28918 12:33:06.402104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28920 12:33:06.402573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28921 12:33:06.441270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28923 12:33:06.441746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28924 12:33:06.480511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28926 12:33:06.481300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28927 12:33:06.526820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28929 12:33:06.527569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28930 12:33:06.566691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28931 12:33:06.567112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28933 12:33:06.619034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28934 12:33:06.619486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28936 12:33:06.667579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28938 12:33:06.668034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28939 12:33:06.716836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28940 12:33:06.717286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28942 12:33:06.761822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28943 12:33:06.762219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28945 12:33:06.824366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28947 12:33:06.824852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28948 12:33:06.872002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28950 12:33:06.872597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28951 12:33:06.924595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28953 12:33:06.925037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28954 12:33:06.968103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28956 12:33:06.968586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28957 12:33:07.007826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28959 12:33:07.008210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28960 12:33:07.063222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28961 12:33:07.063585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28963 12:33:07.115724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28964 12:33:07.116134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28966 12:33:07.167273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28967 12:33:07.167775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28969 12:33:07.218518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28970 12:33:07.218916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28972 12:33:07.271609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28973 12:33:07.272196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28975 12:33:07.323845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28976 12:33:07.324235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28978 12:33:07.374815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28979 12:33:07.375307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28981 12:33:07.421282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28982 12:33:07.421730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28984 12:33:07.464689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28985 12:33:07.465144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28987 12:33:07.514359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28988 12:33:07.514798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28990 12:33:07.556209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28991 12:33:07.556609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28993 12:33:07.602566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28994 12:33:07.603149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28996 12:33:07.648439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28998 12:33:07.648904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28999 12:33:07.690597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
29001 12:33:07.691081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
29002 12:33:07.730895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
29004 12:33:07.731380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
29005 12:33:07.775268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
29006 12:33:07.775725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
29008 12:33:07.818492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
29009 12:33:07.818928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
29011 12:33:07.865116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
29012 12:33:07.865514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
29014 12:33:07.906615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
29016 12:33:07.907011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
29017 12:33:07.947779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
29018 12:33:07.948324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
29020 12:33:08.001552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
29021 12:33:08.002000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
29023 12:33:08.049250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
29024 12:33:08.049769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
29026 12:33:08.091011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
29027 12:33:08.091550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
29029 12:33:08.131791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
29031 12:33:08.132278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
29032 12:33:08.175237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
29033 12:33:08.175755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
29035 12:33:08.215636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
29036 12:33:08.216213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
29038 12:33:08.267445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
29039 12:33:08.267891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
29041 12:33:08.321961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
29042 12:33:08.322400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
29044 12:33:08.375243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
29046 12:33:08.375730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
29047 12:33:08.426740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
29048 12:33:08.427190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
29050 12:33:08.481136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
29052 12:33:08.481525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
29053 12:33:08.529639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
29054 12:33:08.530085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
29056 12:33:08.578038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
29057 12:33:08.578492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
29059 12:33:08.617729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
29060 12:33:08.618225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
29062 12:33:08.668948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
29063 12:33:08.669370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
29065 12:33:08.717954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
29066 12:33:08.718413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
29068 12:33:08.766549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
29069 12:33:08.766988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
29071 12:33:08.810800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
29072 12:33:08.811291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29074 12:33:08.861535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29075 12:33:08.862120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29077 12:33:08.903905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29078 12:33:08.904433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29080 12:33:08.960146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29082 12:33:08.960886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29083 12:33:09.005575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29084 12:33:09.006001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29086 12:33:09.053681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29088 12:33:09.054286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29089 12:33:09.098913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29090 12:33:09.099413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29092 12:33:09.146007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29093 12:33:09.146409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29095 12:33:09.190273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29096 12:33:09.190847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29098 12:33:09.230097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29100 12:33:09.230682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29101 12:33:09.270483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29102 12:33:09.270997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29104 12:33:09.317520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29106 12:33:09.317968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29107 12:33:09.359809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29108 12:33:09.360245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29110 12:33:09.398083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29112 12:33:09.400040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29113 12:33:09.437877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29115 12:33:09.438345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29116 12:33:09.475184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29117 12:33:09.475587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29119 12:33:09.516846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29120 12:33:09.517393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29122 12:33:09.554712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29124 12:33:09.555385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29125 12:33:09.592487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29127 12:33:09.592965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29128 12:33:09.645774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29130 12:33:09.646252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29131 12:33:09.693014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29132 12:33:09.693409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29134 12:33:09.739448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29135 12:33:09.739859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29137 12:33:09.789494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29138 12:33:09.789890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29140 12:33:09.828033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29141 12:33:09.828395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29143 12:33:09.877433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29145 12:33:09.877939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29146 12:33:09.917693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29147 12:33:09.918149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29149 12:33:09.954302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29151 12:33:09.954771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29152 12:33:09.990454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29153 12:33:09.990882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29155 12:33:10.025472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29157 12:33:10.025889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29158 12:33:10.062219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29159 12:33:10.062698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29161 12:33:10.098278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29163 12:33:10.098750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29164 12:33:10.136413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29166 12:33:10.136871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29167 12:33:10.178021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29168 12:33:10.178373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29170 12:33:10.218043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29171 12:33:10.218492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29173 12:33:10.259623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29174 12:33:10.260175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29176 12:33:10.306836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29178 12:33:10.307305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29179 12:33:10.353440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29181 12:33:10.353911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29182 12:33:10.397487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29184 12:33:10.397990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29185 12:33:10.445470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29186 12:33:10.445899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29188 12:33:10.494422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29189 12:33:10.494847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29191 12:33:10.539988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29192 12:33:10.540454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29194 12:33:10.596054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29195 12:33:10.596455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29197 12:33:10.635225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29198 12:33:10.635623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29200 12:33:10.674056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29201 12:33:10.674505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29203 12:33:10.712340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29205 12:33:10.712825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29206 12:33:10.754340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29207 12:33:10.754798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29209 12:33:10.797518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29210 12:33:10.797978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29212 12:33:10.836500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29214 12:33:10.836986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29215 12:33:10.884490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29217 12:33:10.884964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29218 12:33:10.929436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29220 12:33:10.930109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29221 12:33:10.966065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29222 12:33:10.966614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29224 12:33:11.012933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29225 12:33:11.013346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29227 12:33:11.059861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29228 12:33:11.060297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29230 12:33:11.106337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29232 12:33:11.106802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29233 12:33:11.144205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29235 12:33:11.144718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29236 12:33:11.191934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29237 12:33:11.192319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29239 12:33:11.227007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29240 12:33:11.227504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29242 12:33:11.266262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29244 12:33:11.266854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29245 12:33:11.305679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29247 12:33:11.306280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29248 12:33:11.345717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29249 12:33:11.346205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29251 12:33:11.385322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29252 12:33:11.385721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29254 12:33:11.423624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29256 12:33:11.424059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29257 12:33:11.465771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29258 12:33:11.466193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29260 12:33:11.508322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29262 12:33:11.508811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29263 12:33:11.550831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29264 12:33:11.551361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29266 12:33:11.593336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29268 12:33:11.594034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29269 12:33:11.638050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29271 12:33:11.638537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29272 12:33:11.689271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29273 12:33:11.689702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29275 12:33:11.733156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29277 12:33:11.733672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29278 12:33:11.781168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29279 12:33:11.781584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29281 12:33:11.821677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29282 12:33:11.822119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29284 12:33:11.862419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29285 12:33:11.862937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29287 12:33:11.925466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29288 12:33:11.925932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29290 12:33:11.973594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29292 12:33:11.974050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29293 12:33:12.017781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29295 12:33:12.018253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29296 12:33:12.057526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29297 12:33:12.057993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29299 12:33:12.099138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29300 12:33:12.099596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29302 12:33:12.137787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29303 12:33:12.138231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29305 12:33:12.182369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29306 12:33:12.182821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29308 12:33:12.222893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29309 12:33:12.223279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29311 12:33:12.273926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29313 12:33:12.274708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29314 12:33:12.325259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29315 12:33:12.325690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29317 12:33:12.373754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29318 12:33:12.374211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29320 12:33:12.417280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29321 12:33:12.417692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29323 12:33:12.462023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29325 12:33:12.462504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29326 12:33:12.510598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29327 12:33:12.510987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29329 12:33:12.550669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29330 12:33:12.551153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29332 12:33:12.586596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29333 12:33:12.587144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29335 12:33:12.624657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29336 12:33:12.625150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29338 12:33:12.667551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29339 12:33:12.667944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29341 12:33:12.709316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29343 12:33:12.709793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29344 12:33:12.746951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29345 12:33:12.747388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29347 12:33:12.796497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29349 12:33:12.797029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29350 12:33:12.841527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29351 12:33:12.841967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29353 12:33:12.885573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29354 12:33:12.885982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29356 12:33:12.931952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29357 12:33:12.932389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29359 12:33:12.979682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29360 12:33:12.980108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29362 12:33:13.018264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29363 12:33:13.018667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29365 12:33:13.066774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29366 12:33:13.067207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29368 12:33:13.113688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29370 12:33:13.114450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29371 12:33:13.161677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29373 12:33:13.162174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29374 12:33:13.205673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29375 12:33:13.206132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29377 12:33:13.246893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29378 12:33:13.247353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29380 12:33:13.294893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29382 12:33:13.295334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29383 12:33:13.345791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29384 12:33:13.346199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29386 12:33:13.390173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29387 12:33:13.390637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29389 12:33:13.429518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29390 12:33:13.429984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29392 12:33:13.471295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29394 12:33:13.471780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29395 12:33:13.527548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29396 12:33:13.528055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29398 12:33:13.586862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29399 12:33:13.587301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29401 12:33:13.648005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29402 12:33:13.648421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29404 12:33:13.707986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29405 12:33:13.708412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29407 12:33:13.767497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29409 12:33:13.767979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29410 12:33:13.826987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29411 12:33:13.827402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29413 12:33:13.885272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29415 12:33:13.885736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29416 12:33:13.930455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29417 12:33:13.930866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29419 12:33:13.969015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29420 12:33:13.969424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29422 12:33:14.013390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29423 12:33:14.013828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29425 12:33:14.054898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29426 12:33:14.055309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29428 12:33:14.095822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29429 12:33:14.096286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29431 12:33:14.141514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29432 12:33:14.141984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29434 12:33:14.182568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29435 12:33:14.182969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29437 12:33:14.225345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29438 12:33:14.225751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29440 12:33:14.266073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29442 12:33:14.266486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29443 12:33:14.307582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29445 12:33:14.308065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29446 12:33:14.351241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29447 12:33:14.351680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29449 12:33:14.394874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29451 12:33:14.395353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29452 12:33:14.438070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29453 12:33:14.438490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29455 12:33:14.478298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29456 12:33:14.478721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29458 12:33:14.518583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29459 12:33:14.519090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29461 12:33:14.564333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29463 12:33:14.564724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29464 12:33:14.617137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29466 12:33:14.617555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29467 12:33:14.665539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29468 12:33:14.665978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29470 12:33:14.727016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29471 12:33:14.727454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29473 12:33:14.786009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29475 12:33:14.786399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29476 12:33:14.834909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29477 12:33:14.835333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29479 12:33:14.878772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29480 12:33:14.879195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29482 12:33:14.921185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29484 12:33:14.921984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29485 12:33:14.972332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29487 12:33:14.972758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29488 12:33:15.026601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29489 12:33:15.026989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29491 12:33:15.085110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29492 12:33:15.085470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29494 12:33:15.141397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29495 12:33:15.141817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29497 12:33:15.197942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29499 12:33:15.198379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29500 12:33:15.251175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29501 12:33:15.251597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29503 12:33:15.293323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29505 12:33:15.293779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29506 12:33:15.333065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29507 12:33:15.333487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29509 12:33:15.375339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29510 12:33:15.375790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29512 12:33:15.414873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29513 12:33:15.415285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29515 12:33:15.456469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29517 12:33:15.457179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29518 12:33:15.499436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29519 12:33:15.499869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29521 12:33:15.540109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29522 12:33:15.540692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29524 12:33:15.586596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29525 12:33:15.587047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29527 12:33:15.635328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29528 12:33:15.635752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29530 12:33:15.688229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29532 12:33:15.688707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29533 12:33:15.735384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29534 12:33:15.735812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29536 12:33:15.782817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29537 12:33:15.783270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29539 12:33:15.829176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29540 12:33:15.829582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29542 12:33:15.875712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29543 12:33:15.876295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29545 12:33:15.919829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29546 12:33:15.920291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29548 12:33:15.960803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29549 12:33:15.961251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29551 12:33:16.003701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29552 12:33:16.004099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29554 12:33:16.053839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29555 12:33:16.054220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29557 12:33:16.102305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29558 12:33:16.102757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29560 12:33:16.150393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29561 12:33:16.150816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29563 12:33:16.194936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29564 12:33:16.195373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29566 12:33:16.238416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29567 12:33:16.238872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29569 12:33:16.280702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29570 12:33:16.281163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29572 12:33:16.322418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29573 12:33:16.322868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29575 12:33:16.370019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29576 12:33:16.370424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29578 12:33:16.410295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29579 12:33:16.410839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29581 12:33:16.448078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29582 12:33:16.448593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29584 12:33:16.491273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29585 12:33:16.491722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29587 12:33:16.535851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29588 12:33:16.536278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29590 12:33:16.579654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29592 12:33:16.580089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29593 12:33:16.624099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29594 12:33:16.624529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29596 12:33:16.670454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29597 12:33:16.670889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29599 12:33:16.717967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29600 12:33:16.718353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29602 12:33:16.755009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29603 12:33:16.755504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29605 12:33:16.793794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29607 12:33:16.794267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29608 12:33:16.838569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29609 12:33:16.838976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29611 12:33:16.877230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29612 12:33:16.877680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29614 12:33:16.925166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29616 12:33:16.925627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29617 12:33:16.969722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29618 12:33:16.970145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29620 12:33:17.026355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29622 12:33:17.026826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29623 12:33:17.078918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29624 12:33:17.079478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29626 12:33:17.122996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29627 12:33:17.123401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29629 12:33:17.167540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29630 12:33:17.168042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29632 12:33:17.209051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29634 12:33:17.209582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29635 12:33:17.251708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29637 12:33:17.252188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29638 12:33:17.295553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29639 12:33:17.295955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29641 12:33:17.333982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29642 12:33:17.334554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29644 12:33:17.377928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29645 12:33:17.378329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29647 12:33:17.418947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29649 12:33:17.419583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29650 12:33:17.461061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29652 12:33:17.461845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29653 12:33:17.505203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29654 12:33:17.505612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29656 12:33:17.547352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29657 12:33:17.547774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29659 12:33:17.593031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29660 12:33:17.593539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29662 12:33:17.642243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29664 12:33:17.642732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29665 12:33:17.694156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29667 12:33:17.694611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29668 12:33:17.735506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29669 12:33:17.735920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29671 12:33:17.781429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29672 12:33:17.781844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29674 12:33:17.828342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29675 12:33:17.828817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29677 12:33:17.872108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29678 12:33:17.872523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29680 12:33:17.921713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29681 12:33:17.922175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29683 12:33:17.970397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29684 12:33:17.970818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29686 12:33:18.022328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29687 12:33:18.022760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29689 12:33:18.071213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29690 12:33:18.071651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29692 12:33:18.108080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29694 12:33:18.108568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29695 12:33:18.160445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29697 12:33:18.160939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29698 12:33:18.209846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29700 12:33:18.210470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29701 12:33:18.251356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29702 12:33:18.251849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29704 12:33:18.299128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29706 12:33:18.299609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29707 12:33:18.346641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29708 12:33:18.347076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29710 12:33:18.399152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29711 12:33:18.399576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29713 12:33:18.445873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29714 12:33:18.446306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29716 12:33:18.486952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29717 12:33:18.487408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29719 12:33:18.529495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29720 12:33:18.529955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29722 12:33:18.571281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29723 12:33:18.571802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29725 12:33:18.614965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29726 12:33:18.615525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29728 12:33:18.662448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29730 12:33:18.663147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29731 12:33:18.708633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29732 12:33:18.709182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29734 12:33:18.756261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29736 12:33:18.756713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29737 12:33:18.798905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29739 12:33:18.799286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29740 12:33:18.836119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29741 12:33:18.836613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29743 12:33:18.880384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29745 12:33:18.880975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29746 12:33:18.923301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29747 12:33:18.923732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29749 12:33:18.969400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29750 12:33:18.969867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29752 12:33:19.019121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29753 12:33:19.019495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29755 12:33:19.067413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29756 12:33:19.067834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29758 12:33:19.105718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29760 12:33:19.106197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29761 12:33:19.143291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29762 12:33:19.143719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29764 12:33:19.187841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29766 12:33:19.188291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29767 12:33:19.238638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29768 12:33:19.239086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29770 12:33:19.279191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29771 12:33:19.279626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29773 12:33:19.324999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29774 12:33:19.325432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29776 12:33:19.373115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29778 12:33:19.373580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29779 12:33:19.415331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29780 12:33:19.415765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29782 12:33:19.459613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29783 12:33:19.460084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29785 12:33:19.506780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29787 12:33:19.507260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29788 12:33:19.555659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29789 12:33:19.556091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29791 12:33:19.605194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29792 12:33:19.605644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29794 12:33:19.649958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29795 12:33:19.650378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29797 12:33:19.697513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29798 12:33:19.697992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29800 12:33:19.746083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29802 12:33:19.746519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29803 12:33:19.796020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29804 12:33:19.796440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29806 12:33:19.845936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29807 12:33:19.846355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29809 12:33:19.894643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29811 12:33:19.895129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29812 12:33:19.942353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29814 12:33:19.942951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29815 12:33:19.997692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29817 12:33:19.998466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29818 12:33:20.052191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29820 12:33:20.052656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29821 12:33:20.095747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29822 12:33:20.096147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29824 12:33:20.133625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29825 12:33:20.134089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29827 12:33:20.170910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29828 12:33:20.171362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29830 12:33:20.207464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29831 12:33:20.207890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29833 12:33:20.246268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29834 12:33:20.246719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29836 12:33:20.290144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29838 12:33:20.290626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29839 12:33:20.337616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29840 12:33:20.338034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29842 12:33:20.391715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29843 12:33:20.392144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29845 12:33:20.447217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29847 12:33:20.447615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29848 12:33:20.502609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29849 12:33:20.503040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29851 12:33:20.560581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29853 12:33:20.561241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29854 12:33:20.607100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29855 12:33:20.607500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29857 12:33:20.660823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29858 12:33:20.661240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29860 12:33:20.713011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29861 12:33:20.713450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29863 12:33:20.773150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29864 12:33:20.773590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29866 12:33:20.834071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29868 12:33:20.834557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29869 12:33:20.895478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29871 12:33:20.895967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29872 12:33:20.953661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29874 12:33:20.954099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29875 12:33:21.004874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29876 12:33:21.005269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29878 12:33:21.055191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29879 12:33:21.055646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29881 12:33:21.097296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29882 12:33:21.097693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29884 12:33:21.139619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29886 12:33:21.140107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29887 12:33:21.181036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29888 12:33:21.181464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29890 12:33:21.231384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29892 12:33:21.232084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29893 12:33:21.284509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29895 12:33:21.285077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29896 12:33:21.337316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29898 12:33:21.337811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29899 12:33:21.386313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29901 12:33:21.386753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29902 12:33:21.445561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29903 12:33:21.446017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29905 12:33:21.494401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29907 12:33:21.494889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29908 12:33:21.539895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29909 12:33:21.540371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29911 12:33:21.587911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29912 12:33:21.588327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29914 12:33:21.639957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29915 12:33:21.640364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29917 12:33:21.689415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29918 12:33:21.689892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29920 12:33:21.739707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29922 12:33:21.740166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29923 12:33:21.785405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29925 12:33:21.786098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29926 12:33:21.843921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29927 12:33:21.844353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29929 12:33:21.890242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29930 12:33:21.890808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29932 12:33:21.938771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29933 12:33:21.939225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29935 12:33:21.990681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29936 12:33:21.991123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29938 12:33:22.038270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29940 12:33:22.038759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29941 12:33:22.079972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29942 12:33:22.080408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29944 12:33:22.123152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29945 12:33:22.123606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29947 12:33:22.189788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29949 12:33:22.190260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29950 12:33:22.233182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29951 12:33:22.233662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29953 12:33:22.283131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29955 12:33:22.283593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29956 12:33:22.339932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29957 12:33:22.340378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29959 12:33:22.390131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29961 12:33:22.390612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29962 12:33:22.442836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29963 12:33:22.443267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29965 12:33:22.493881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29966 12:33:22.494336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29968 12:33:22.548493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29970 12:33:22.548967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29971 12:33:22.599384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29973 12:33:22.599857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29974 12:33:22.649297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29975 12:33:22.649686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29977 12:33:22.699130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29978 12:33:22.699556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29980 12:33:22.745618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29981 12:33:22.746068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29983 12:33:22.790103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29985 12:33:22.790545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29986 12:33:22.832032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29988 12:33:22.832532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29989 12:33:22.882441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29990 12:33:22.882876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29992 12:33:22.926894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29994 12:33:22.927326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29995 12:33:22.967606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29997 12:33:22.968095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29998 12:33:23.010332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29999 12:33:23.010786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
30001 12:33:23.058497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
30002 12:33:23.058930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
30004 12:33:23.101260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
30005 12:33:23.101697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
30007 12:33:23.149938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
30008 12:33:23.150391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
30010 12:33:23.199841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
30011 12:33:23.200408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
30013 12:33:23.247669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
30015 12:33:23.248156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
30016 12:33:23.295183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
30017 12:33:23.295656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
30019 12:33:23.353027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
30020 12:33:23.353486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
30022 12:33:23.412541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
30024 12:33:23.412998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
30025 12:33:23.457662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
30026 12:33:23.458128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
30028 12:33:23.497472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
30030 12:33:23.498165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
30031 12:33:23.539596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
30033 12:33:23.540057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
30034 12:33:23.587107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
30035 12:33:23.587548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
30037 12:33:23.630588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
30038 12:33:23.631001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
30040 12:33:23.675693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
30042 12:33:23.676134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
30043 12:33:23.729003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
30044 12:33:23.729411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
30046 12:33:23.779098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
30047 12:33:23.779587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
30049 12:33:23.824317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
30051 12:33:23.825062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
30052 12:33:23.875584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
30053 12:33:23.876169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
30055 12:33:23.927144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
30057 12:33:23.927643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
30058 12:33:23.972299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
30060 12:33:23.972796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
30061 12:33:24.020819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
30062 12:33:24.021285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
30064 12:33:24.069663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
30065 12:33:24.070149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
30067 12:33:24.121003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
30068 12:33:24.121462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
30070 12:33:24.162304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
30071 12:33:24.162763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
30073 12:33:24.213887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30074 12:33:24.214345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30076 12:33:24.267616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30077 12:33:24.268062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30079 12:33:24.329059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30081 12:33:24.329465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30082 12:33:24.377491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30083 12:33:24.378060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30085 12:33:24.425405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30086 12:33:24.425982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30088 12:33:24.470603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30089 12:33:24.471186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30091 12:33:24.519112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30092 12:33:24.519533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30094 12:33:24.567915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30096 12:33:24.568609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30097 12:33:24.619965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30099 12:33:24.620359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30100 12:33:24.673043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30101 12:33:24.673506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30103 12:33:24.727460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30104 12:33:24.727920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30106 12:33:24.777788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30107 12:33:24.778235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30109 12:33:24.830004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30111 12:33:24.830449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30112 12:33:24.878674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30113 12:33:24.879088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30115 12:33:24.921667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30117 12:33:24.922111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30118 12:33:24.967992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30119 12:33:24.968424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30121 12:33:25.014826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30122 12:33:25.015310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30124 12:33:25.059012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30125 12:33:25.059717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30127 12:33:25.104424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30129 12:33:25.104916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30130 12:33:25.148255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30132 12:33:25.148717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30133 12:33:25.195414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30135 12:33:25.195862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30136 12:33:25.243228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30137 12:33:25.243714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30139 12:33:25.290158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30140 12:33:25.290666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30142 12:33:25.339256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30143 12:33:25.339708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30145 12:33:25.381970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30146 12:33:25.382532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30148 12:33:25.425977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30150 12:33:25.426490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30151 12:33:25.469808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30152 12:33:25.470383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30154 12:33:25.511525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30155 12:33:25.512095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30157 12:33:25.559162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30158 12:33:25.559721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30160 12:33:25.618386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30161 12:33:25.618827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30163 12:33:25.665393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30164 12:33:25.665782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30166 12:33:25.707702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30167 12:33:25.708141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30169 12:33:25.753077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30170 12:33:25.753441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30172 12:33:25.805046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30173 12:33:25.805502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30175 12:33:25.855140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30176 12:33:25.855564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30178 12:33:25.912452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30180 12:33:25.912978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30181 12:33:25.965267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30182 12:33:25.965676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30184 12:33:26.023249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30185 12:33:26.023700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30187 12:33:26.083244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30188 12:33:26.083712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30190 12:33:26.127740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30191 12:33:26.128178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30193 12:33:26.175598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30195 12:33:26.176070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30196 12:33:26.227126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30197 12:33:26.227534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30199 12:33:26.279925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30200 12:33:26.280346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30202 12:33:26.326542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30203 12:33:26.326944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30205 12:33:26.370359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30207 12:33:26.370813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30208 12:33:26.410926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30209 12:33:26.411360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30211 12:33:26.470377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30212 12:33:26.470806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30214 12:33:26.528621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30216 12:33:26.529352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30217 12:33:26.586731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30218 12:33:26.587155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30220 12:33:26.644228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30221 12:33:26.644640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30223 12:33:26.702441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30224 12:33:26.702881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30226 12:33:26.759811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30228 12:33:26.760300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30229 12:33:26.820399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30231 12:33:26.821068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30232 12:33:26.869821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30233 12:33:26.870335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30235 12:33:26.915386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30236 12:33:26.915814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30238 12:33:26.962769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30240 12:33:26.963356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30241 12:33:27.005224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30243 12:33:27.005709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30244 12:33:27.050889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30245 12:33:27.051310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30247 12:33:27.102138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30248 12:33:27.102579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30250 12:33:27.143231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30251 12:33:27.143668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30253 12:33:27.195156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30254 12:33:27.195597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30256 12:33:27.266842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30257 12:33:27.267355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30259 12:33:27.338886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30260 12:33:27.339324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30262 12:33:27.397823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30263 12:33:27.398235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30265 12:33:27.455073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30267 12:33:27.455529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30268 12:33:27.507697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30269 12:33:27.508153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30271 12:33:27.556560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30273 12:33:27.557344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30274 12:33:27.599370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30276 12:33:27.600075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30277 12:33:27.647810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30278 12:33:27.648222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30280 12:33:27.700334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30282 12:33:27.700743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30283 12:33:27.745916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30285 12:33:27.746403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30286 12:33:27.797528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30288 12:33:27.798197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30289 12:33:27.844498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30291 12:33:27.844931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30292 12:33:27.903130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30294 12:33:27.903565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30295 12:33:27.953876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30297 12:33:27.954362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30298 12:33:27.997997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30300 12:33:27.998485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30301 12:33:28.042417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30302 12:33:28.042897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30304 12:33:28.102979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30306 12:33:28.103484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30307 12:33:28.152930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30309 12:33:28.153409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30310 12:33:28.197068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30311 12:33:28.197531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30313 12:33:28.247979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30315 12:33:28.248480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30316 12:33:28.293830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30317 12:33:28.294275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30319 12:33:28.333493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30320 12:33:28.334969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30322 12:33:28.387450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30323 12:33:28.387891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30325 12:33:28.438226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30326 12:33:28.438655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30328 12:33:28.487604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30329 12:33:28.488036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30331 12:33:28.538597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30332 12:33:28.539019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30334 12:33:28.582116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30336 12:33:28.582636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30337 12:33:28.629932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30338 12:33:28.630348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30340 12:33:28.675187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30341 12:33:28.675618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30343 12:33:28.719558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30345 12:33:28.720052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30346 12:33:28.778645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30347 12:33:28.779138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30349 12:33:28.838301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30351 12:33:28.838745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30352 12:33:28.895924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30353 12:33:28.896460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30355 12:33:28.955569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30357 12:33:28.956068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30358 12:33:29.007648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30360 12:33:29.008123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30361 12:33:29.049677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30363 12:33:29.050151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30364 12:33:29.095549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30366 12:33:29.096048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30367 12:33:29.143607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30368 12:33:29.144057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30370 12:33:29.196404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30372 12:33:29.196893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30373 12:33:29.249670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30374 12:33:29.250057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30376 12:33:29.306434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30377 12:33:29.306900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30379 12:33:29.355931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30380 12:33:29.356388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30382 12:33:29.415424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30383 12:33:29.415867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30385 12:33:29.471280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30387 12:33:29.471759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30388 12:33:29.527628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30389 12:33:29.528068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30391 12:33:29.579072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30392 12:33:29.579536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30394 12:33:29.627156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30396 12:33:29.627629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30397 12:33:29.675960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30398 12:33:29.676408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30400 12:33:29.726871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30401 12:33:29.727295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30403 12:33:29.770639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30405 12:33:29.771115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30406 12:33:29.823649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30407 12:33:29.824078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30409 12:33:29.873826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30410 12:33:29.874258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30412 12:33:29.922012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30414 12:33:29.922496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30415 12:33:29.960223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30417 12:33:29.960705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30418 12:33:30.015735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30419 12:33:30.016146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30421 12:33:30.063502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30422 12:33:30.063915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30424 12:33:30.110289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30425 12:33:30.110678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30427 12:33:30.156096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30428 12:33:30.156542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30430 12:33:30.195005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30431 12:33:30.195468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30433 12:33:30.234031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30434 12:33:30.234414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30436 12:33:30.283883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30437 12:33:30.284323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30439 12:33:30.325341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30440 12:33:30.325795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30442 12:33:30.368360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30444 12:33:30.369422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30445 12:33:30.411381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30446 12:33:30.411824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30448 12:33:30.450003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30449 12:33:30.450450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30451 12:33:30.489768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30452 12:33:30.490223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30454 12:33:30.529842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30455 12:33:30.530305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30457 12:33:30.573405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30459 12:33:30.573901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30460 12:33:30.617908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30461 12:33:30.618334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30463 12:33:30.673774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30465 12:33:30.674242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30466 12:33:30.721487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30468 12:33:30.721963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30469 12:33:30.767277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30471 12:33:30.767765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30472 12:33:30.818711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30474 12:33:30.819196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30475 12:33:30.861040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30477 12:33:30.861516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30478 12:33:30.900005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30480 12:33:30.900402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30481 12:33:30.937594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30482 12:33:30.938048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30484 12:33:30.983743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30485 12:33:30.984168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30487 12:33:31.022855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30488 12:33:31.023280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30490 12:33:31.074702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30491 12:33:31.075099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30493 12:33:31.113391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30495 12:33:31.113864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30496 12:33:31.156427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30498 12:33:31.156895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30499 12:33:31.215329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30500 12:33:31.215877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30502 12:33:31.274801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30503 12:33:31.275320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30505 12:33:31.334901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30506 12:33:31.335321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30508 12:33:31.394346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30509 12:33:31.394802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30511 12:33:31.443523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30512 12:33:31.443975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30514 12:33:31.497033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30515 12:33:31.497494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30517 12:33:31.547460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30518 12:33:31.547916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30520 12:33:31.602862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30521 12:33:31.603317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30523 12:33:31.654690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30524 12:33:31.655135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30526 12:33:31.706341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30527 12:33:31.706777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30529 12:33:31.758060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30530 12:33:31.758515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30532 12:33:31.811335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30534 12:33:31.811822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30535 12:33:31.865370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30536 12:33:31.865959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30538 12:33:31.917039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30539 12:33:31.917445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30541 12:33:31.971269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30542 12:33:31.971695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30544 12:33:32.026591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30545 12:33:32.026988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30547 12:33:32.073963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30549 12:33:32.074441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30550 12:33:32.125785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30551 12:33:32.126221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30553 12:33:32.171850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30555 12:33:32.172327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30556 12:33:32.217913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30557 12:33:32.218412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30559 12:33:32.270088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30561 12:33:32.270516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30562 12:33:32.320011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30563 12:33:32.320452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30565 12:33:32.382755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30567 12:33:32.383239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30568 12:33:32.446053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30569 12:33:32.446558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30571 12:33:32.491239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30572 12:33:32.491699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30574 12:33:32.538420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30575 12:33:32.538828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30577 12:33:32.583700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30578 12:33:32.584127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30580 12:33:32.626039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30581 12:33:32.626441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30583 12:33:32.668173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30584 12:33:32.668610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30586 12:33:32.711974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30587 12:33:32.712420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30589 12:33:32.761863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30590 12:33:32.762317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30592 12:33:32.812337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30593 12:33:32.812771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30595 12:33:32.865396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30596 12:33:32.865969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30598 12:33:32.922998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30600 12:33:32.923360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30601 12:33:32.980958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30603 12:33:32.981440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30604 12:33:33.029724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30606 12:33:33.030213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30607 12:33:33.075515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30608 12:33:33.075932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30610 12:33:33.117886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30611 12:33:33.118348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30613 12:33:33.159059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30614 12:33:33.159488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30616 12:33:33.206970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30617 12:33:33.207387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30619 12:33:33.258310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30621 12:33:33.258743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30622 12:33:33.309716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30623 12:33:33.310160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30625 12:33:33.365219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30627 12:33:33.365606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30628 12:33:33.424245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30630 12:33:33.424731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30631 12:33:33.478287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30633 12:33:33.478758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30634 12:33:33.531297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30635 12:33:33.531866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30637 12:33:33.586391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30638 12:33:33.586818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30640 12:33:33.636070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30641 12:33:33.636494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30643 12:33:33.673447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30645 12:33:33.673941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30646 12:33:33.717887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30648 12:33:33.718372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30649 12:33:33.767163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30650 12:33:33.767616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30652 12:33:33.818789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30654 12:33:33.819490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30655 12:33:33.877463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30656 12:33:33.877988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30658 12:33:33.935219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30660 12:33:33.935697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30661 12:33:33.995037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30663 12:33:33.995514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30664 12:33:34.054291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30666 12:33:34.054674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30667 12:33:34.099829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30668 12:33:34.100224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30670 12:33:34.155933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30671 12:33:34.156357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30673 12:33:34.200342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30675 12:33:34.200922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30676 12:33:34.239612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30677 12:33:34.240046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30679 12:33:34.280416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30681 12:33:34.281215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30682 12:33:34.325601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30683 12:33:34.326065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30685 12:33:34.382521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30687 12:33:34.382963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30688 12:33:34.442241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30689 12:33:34.442657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30691 12:33:34.491410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30693 12:33:34.491818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30694 12:33:34.539790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30696 12:33:34.540257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30697 12:33:34.591332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30698 12:33:34.591707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30700 12:33:34.635848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30701 12:33:34.636283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30703 12:33:34.683858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30705 12:33:34.684338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30706 12:33:34.730763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30707 12:33:34.731322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30709 12:33:34.785171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30711 12:33:34.785682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30712 12:33:34.846879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30713 12:33:34.847318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30715 12:33:34.910835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30716 12:33:34.911270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30718 12:33:34.969535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30719 12:33:34.969966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30721 12:33:35.026758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30722 12:33:35.027207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30724 12:33:35.083994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30725 12:33:35.084394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30727 12:33:35.142136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30729 12:33:35.142643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30730 12:33:35.200596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30732 12:33:35.201410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30733 12:33:35.259069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30734 12:33:35.259504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30736 12:33:35.313794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30737 12:33:35.314246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30739 12:33:35.369521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30741 12:33:35.369986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30742 12:33:35.425717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30743 12:33:35.426145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30745 12:33:35.482404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30746 12:33:35.482799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30748 12:33:35.538416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30749 12:33:35.538848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30751 12:33:35.582353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30753 12:33:35.582822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30754 12:33:35.626858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30755 12:33:35.627321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30757 12:33:35.674222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30758 12:33:35.674672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30760 12:33:35.719164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30761 12:33:35.719575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30763 12:33:35.763644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30764 12:33:35.764076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30766 12:33:35.803940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30768 12:33:35.804434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30769 12:33:35.845899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30771 12:33:35.846370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30772 12:33:35.888092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30774 12:33:35.888534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30775 12:33:35.931098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30777 12:33:35.931489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30778 12:33:35.970577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30780 12:33:35.971317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30781 12:33:36.013780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30782 12:33:36.014156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30784 12:33:36.055786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30785 12:33:36.056197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30787 12:33:36.099868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30788 12:33:36.100312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30790 12:33:36.154250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30791 12:33:36.155124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30793 12:33:36.198966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30794 12:33:36.199516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30796 12:33:36.258999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30797 12:33:36.259398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30799 12:33:36.311329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30800 12:33:36.311735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30802 12:33:36.370400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30803 12:33:36.370803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30805 12:33:36.432545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30807 12:33:36.433016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30808 12:33:36.491179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30809 12:33:36.491633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30811 12:33:36.534766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30813 12:33:36.535239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30814 12:33:36.581379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30816 12:33:36.581861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30817 12:33:36.638971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30818 12:33:36.639402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30820 12:33:36.691512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30821 12:33:36.691946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30823 12:33:36.735689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30824 12:33:36.736124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30826 12:33:36.775852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30827 12:33:36.776291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30829 12:33:36.822770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30831 12:33:36.823534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30832 12:33:36.867874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30834 12:33:36.868303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30835 12:33:36.914628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30837 12:33:36.915307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30838 12:33:36.958586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30839 12:33:36.959072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30841 12:33:36.998156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30842 12:33:36.998754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30844 12:33:37.043320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30846 12:33:37.043816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30847 12:33:37.085412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30849 12:33:37.085917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30850 12:33:37.131509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30851 12:33:37.131921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30853 12:33:37.171118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30854 12:33:37.171656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30856 12:33:37.218299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30857 12:33:37.218701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30859 12:33:37.268401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30861 12:33:37.268884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30862 12:33:37.323010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30864 12:33:37.323451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30865 12:33:37.366071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30866 12:33:37.366543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30868 12:33:37.416073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30869 12:33:37.416476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30871 12:33:37.462298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30872 12:33:37.462876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30874 12:33:37.515576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30875 12:33:37.516085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30877 12:33:37.554763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30878 12:33:37.555201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30880 12:33:37.605782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30881 12:33:37.606228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30883 12:33:37.662639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30885 12:33:37.663027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30886 12:33:37.721160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30887 12:33:37.721590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30889 12:33:37.779620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30891 12:33:37.780116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30892 12:33:37.838571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30894 12:33:37.839058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30895 12:33:37.895880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30897 12:33:37.896316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30898 12:33:37.937417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30899 12:33:37.937889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30901 12:33:37.984363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30903 12:33:37.984832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30904 12:33:38.029807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30905 12:33:38.030222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30907 12:33:38.078782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30908 12:33:38.079159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30910 12:33:38.119530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30911 12:33:38.119956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30913 12:33:38.162604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30914 12:33:38.163033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30916 12:33:38.203893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30917 12:33:38.204480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30919 12:33:38.243769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30921 12:33:38.244268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30922 12:33:38.283332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30924 12:33:38.283722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30925 12:33:38.326345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30926 12:33:38.326797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30928 12:33:38.365392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30929 12:33:38.365836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30931 12:33:38.405244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30932 12:33:38.405653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30934 12:33:38.447664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30935 12:33:38.448241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30937 12:33:38.489132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30939 12:33:38.489931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30940 12:33:38.527017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30942 12:33:38.527565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30943 12:33:38.569689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30944 12:33:38.570105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30946 12:33:38.615578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30947 12:33:38.616141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30949 12:33:38.655049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30951 12:33:38.655479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30952 12:33:38.694636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30953 12:33:38.695103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30955 12:33:38.730896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30957 12:33:38.731386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30958 12:33:38.767444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30960 12:33:38.767835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30961 12:33:38.804058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30962 12:33:38.804493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30964 12:33:38.845626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30965 12:33:38.846029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30967 12:33:38.887766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30969 12:33:38.888349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30970 12:33:38.925291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30972 12:33:38.925945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30973 12:33:38.970357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30974 12:33:38.970879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30976 12:33:39.011106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30977 12:33:39.011483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30979 12:33:39.048389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30981 12:33:39.049075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30982 12:33:39.085850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30983 12:33:39.086326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30985 12:33:39.125516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30986 12:33:39.125995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30988 12:33:39.167862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30990 12:33:39.168623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30991 12:33:39.209112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30992 12:33:39.209576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30994 12:33:39.247126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30996 12:33:39.247600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30997 12:33:39.297811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30999 12:33:39.298246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
31000 12:33:39.343082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
31001 12:33:39.343498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
31003 12:33:39.386977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
31005 12:33:39.387444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
31006 12:33:39.427640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
31008 12:33:39.428115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
31009 12:33:39.469484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
31010 12:33:39.469922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
31012 12:33:39.519160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
31013 12:33:39.519545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
31015 12:33:39.559571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
31016 12:33:39.560028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
31018 12:33:39.605786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
31019 12:33:39.606227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
31021 12:33:39.664176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
31022 12:33:39.664607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
31024 12:33:39.722661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
31025 12:33:39.723053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
31027 12:33:39.782954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
31028 12:33:39.783368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
31030 12:33:39.845693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
31031 12:33:39.846078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
31033 12:33:39.905676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
31034 12:33:39.906115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
31036 12:33:39.953242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
31037 12:33:39.953712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
31039 12:33:40.001448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
31040 12:33:40.001889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
31042 12:33:40.041285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
31043 12:33:40.041700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
31045 12:33:40.085593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
31047 12:33:40.086067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
31048 12:33:40.131511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
31050 12:33:40.132000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
31051 12:33:40.171119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
31053 12:33:40.171583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
31054 12:33:40.210343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
31056 12:33:40.210804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
31057 12:33:40.248280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
31059 12:33:40.248958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
31060 12:33:40.292889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
31061 12:33:40.293379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
31063 12:33:40.331326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
31064 12:33:40.331757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
31066 12:33:40.371585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
31068 12:33:40.372056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
31069 12:33:40.414902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
31070 12:33:40.415389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
31072 12:33:40.454573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
31073 12:33:40.454996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31075 12:33:40.497012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31076 12:33:40.497437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31078 12:33:40.539690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31079 12:33:40.540259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31081 12:33:40.580768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31082 12:33:40.581222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31084 12:33:40.626544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31085 12:33:40.626966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31087 12:33:40.674766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31088 12:33:40.675225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31090 12:33:40.716530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31092 12:33:40.717004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31093 12:33:40.757756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31094 12:33:40.758198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31096 12:33:40.811962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31097 12:33:40.812373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31099 12:33:40.857705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31101 12:33:40.858128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31102 12:33:40.897223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31103 12:33:40.897711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31105 12:33:40.942210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31107 12:33:40.942599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31108 12:33:40.990528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31109 12:33:40.990965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31111 12:33:41.038869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31113 12:33:41.039301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31114 12:33:41.085432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31115 12:33:41.085901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31117 12:33:41.128399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31119 12:33:41.128899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31120 12:33:41.186643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31121 12:33:41.187033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31123 12:33:41.245718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31124 12:33:41.246111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31126 12:33:41.304165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31127 12:33:41.304610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31129 12:33:41.366420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31130 12:33:41.366879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31132 12:33:41.427816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31134 12:33:41.428308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31135 12:33:41.490519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31136 12:33:41.490960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31138 12:33:41.547215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31140 12:33:41.547911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31141 12:33:41.595091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31142 12:33:41.595543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31144 12:33:41.638496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31145 12:33:41.638991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31147 12:33:41.686210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31148 12:33:41.686716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31150 12:33:41.732674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31151 12:33:41.733102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31153 12:33:41.777296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31155 12:33:41.777731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31156 12:33:41.829752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31157 12:33:41.830318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31159 12:33:41.874254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31161 12:33:41.874731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31162 12:33:41.912180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31164 12:33:41.912734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31165 12:33:41.959887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31166 12:33:41.960306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31168 12:33:41.998805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31169 12:33:41.999239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31171 12:33:42.041348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31173 12:33:42.041825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31174 12:33:42.081485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31175 12:33:42.081919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31177 12:33:42.137684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31178 12:33:42.138129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31180 12:33:42.176509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31182 12:33:42.176993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31183 12:33:42.225899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31184 12:33:42.226294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31186 12:33:42.264316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31188 12:33:42.264798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31189 12:33:42.310195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31191 12:33:42.310664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31192 12:33:42.352781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31193 12:33:42.353189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31195 12:33:42.398026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31196 12:33:42.398539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31198 12:33:42.442483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31199 12:33:42.442909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31201 12:33:42.477687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31202 12:33:42.478140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31204 12:33:42.513586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31205 12:33:42.514054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31207 12:33:42.549856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31208 12:33:42.550286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31210 12:33:42.586642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31212 12:33:42.587328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31213 12:33:42.643211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31214 12:33:42.643577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31216 12:33:42.679283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31217 12:33:42.679724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31219 12:33:42.717849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31220 12:33:42.718234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31222 12:33:42.758449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31223 12:33:42.758840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31225 12:33:42.795892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31226 12:33:42.796356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31228 12:33:42.834389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31229 12:33:42.834845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31231 12:33:42.877425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31233 12:33:42.877829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31234 12:33:42.916925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31235 12:33:42.917352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31237 12:33:42.955928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31238 12:33:42.956491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31240 12:33:42.993074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31241 12:33:42.993467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31243 12:33:43.035432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31244 12:33:43.035830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31246 12:33:43.078610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31248 12:33:43.079075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31249 12:33:43.113819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31251 12:33:43.114204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31252 12:33:43.150556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31253 12:33:43.151096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31255 12:33:43.189570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31256 12:33:43.190010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31258 12:33:43.225387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31259 12:33:43.225859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31261 12:33:43.276994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31262 12:33:43.277407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31264 12:33:43.311529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31266 12:33:43.312312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31267 12:33:43.346569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31268 12:33:43.347096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31270 12:33:43.383142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31272 12:33:43.383766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31273 12:33:43.429832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31274 12:33:43.430283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31276 12:33:43.466180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31278 12:33:43.466654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31279 12:33:43.505272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31280 12:33:43.505707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31282 12:33:43.544880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31283 12:33:43.545312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31285 12:33:43.590332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31286 12:33:43.590788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31288 12:33:43.627726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31289 12:33:43.628194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31291 12:33:43.680059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31293 12:33:43.680543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31294 12:33:43.735759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31295 12:33:43.736187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31297 12:33:43.781721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31298 12:33:43.782154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31300 12:33:43.820183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31301 12:33:43.820641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31303 12:33:43.855910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31304 12:33:43.856369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31306 12:33:43.898030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31308 12:33:43.898542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31309 12:33:43.938071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31311 12:33:43.938522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31312 12:33:43.986349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31313 12:33:43.986774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31315 12:33:44.034909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31317 12:33:44.035586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31318 12:33:44.081260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31319 12:33:44.081683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31321 12:33:44.124130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31322 12:33:44.124587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31324 12:33:44.175350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31325 12:33:44.175760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31327 12:33:44.232055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31328 12:33:44.232454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31330 12:33:44.285505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31332 12:33:44.286015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31333 12:33:44.332877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31334 12:33:44.333321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31336 12:33:44.368945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31337 12:33:44.369399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31339 12:33:44.405371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31340 12:33:44.405829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31342 12:33:44.444898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31343 12:33:44.445500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31345 12:33:44.481466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31346 12:33:44.481931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31348 12:33:44.525328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31349 12:33:44.525776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31351 12:33:44.571195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31353 12:33:44.571680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31354 12:33:44.616018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31355 12:33:44.616451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31357 12:33:44.651782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31358 12:33:44.652236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31360 12:33:44.699862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31362 12:33:44.700346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31363 12:33:44.756586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31365 12:33:44.757376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31366 12:33:44.807400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31367 12:33:44.807853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31369 12:33:44.846252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31370 12:33:44.846693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31372 12:33:44.893891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31373 12:33:44.894338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31375 12:33:44.933002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31377 12:33:44.933491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31378 12:33:44.974815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31380 12:33:44.975247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31381 12:33:45.017838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31383 12:33:45.018320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31384 12:33:45.059931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31385 12:33:45.060385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31387 12:33:45.103593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31389 12:33:45.104126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31390 12:33:45.145983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31392 12:33:45.146601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31393 12:33:45.186275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31394 12:33:45.186732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31396 12:33:45.237077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31397 12:33:45.237518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31399 12:33:45.277557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31401 12:33:45.278153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31402 12:33:45.313748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31403 12:33:45.314206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31405 12:33:45.351072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31407 12:33:45.351783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31408 12:33:45.391633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31409 12:33:45.392030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31411 12:33:45.431180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31413 12:33:45.431645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31414 12:33:45.467212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31415 12:33:45.467665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31417 12:33:45.504866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31418 12:33:45.505291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31420 12:33:45.547603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31421 12:33:45.548002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31423 12:33:45.586534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31424 12:33:45.586931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31426 12:33:45.625372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31427 12:33:45.625771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31429 12:33:45.664981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31430 12:33:45.665491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31432 12:33:45.703195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31434 12:33:45.703627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31435 12:33:45.756944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31436 12:33:45.757320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31438 12:33:45.810264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31439 12:33:45.810703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31441 12:33:45.850899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31442 12:33:45.851342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31444 12:33:45.895810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31445 12:33:45.896253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31447 12:33:45.946022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31448 12:33:45.946452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31450 12:33:45.991933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31451 12:33:45.992387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31453 12:33:46.041677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31454 12:33:46.042082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31456 12:33:46.095251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31457 12:33:46.095627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31459 12:33:46.150163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31460 12:33:46.150757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31462 12:33:46.199233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31463 12:33:46.199756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31465 12:33:46.237097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31466 12:33:46.237553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31468 12:33:46.274145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31469 12:33:46.274569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31471 12:33:46.317398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31472 12:33:46.317982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31474 12:33:46.357233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31475 12:33:46.357694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31477 12:33:46.413987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31478 12:33:46.414411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31480 12:33:46.466123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31482 12:33:46.466741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31483 12:33:46.503146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31485 12:33:46.503555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31486 12:33:46.540782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31488 12:33:46.541200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31489 12:33:46.589378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31490 12:33:46.589815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31492 12:33:46.626102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31494 12:33:46.626572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31495 12:33:46.663352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31496 12:33:46.663761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31498 12:33:46.701373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31499 12:33:46.701738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31501 12:33:46.746732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31503 12:33:46.747163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31504 12:33:46.793976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31505 12:33:46.794408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31507 12:33:46.839658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31508 12:33:46.840098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31510 12:33:46.885775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31511 12:33:46.886219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31513 12:33:46.934369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31515 12:33:46.934753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31516 12:33:46.985538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31517 12:33:46.985935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31519 12:33:47.036588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31521 12:33:47.037331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31522 12:33:47.072873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31523 12:33:47.073313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31525 12:33:47.125662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31526 12:33:47.126107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31528 12:33:47.168921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31529 12:33:47.169405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31531 12:33:47.215083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31532 12:33:47.215572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31534 12:33:47.269588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31535 12:33:47.270112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31537 12:33:47.321799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31538 12:33:47.322221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31540 12:33:47.367900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31541 12:33:47.368289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31543 12:33:47.422004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31544 12:33:47.422426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31546 12:33:47.466384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31547 12:33:47.466783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31549 12:33:47.503251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31550 12:33:47.503742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31552 12:33:47.549670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31554 12:33:47.550087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31555 12:33:47.585708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31556 12:33:47.586096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31558 12:33:47.641436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31560 12:33:47.642026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31561 12:33:47.685202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31562 12:33:47.685668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31564 12:33:47.722199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31566 12:33:47.722647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31567 12:33:47.785522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31568 12:33:47.786019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31570 12:33:47.822983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31572 12:33:47.823462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31573 12:33:47.866693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31574 12:33:47.867166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31576 12:33:47.909048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31577 12:33:47.909615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31579 12:33:47.945027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31580 12:33:47.945488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31582 12:33:47.980405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31584 12:33:47.980855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31585 12:33:48.017348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31587 12:33:48.017885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31588 12:33:48.066396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31590 12:33:48.066877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31591 12:33:48.100693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31592 12:33:48.101124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31594 12:33:48.145775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31595 12:33:48.146165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31597 12:33:48.180367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31599 12:33:48.180869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31600 12:33:48.219480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31601 12:33:48.219875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31603 12:33:48.262272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31604 12:33:48.262697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31606 12:33:48.313680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31608 12:33:48.314294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31609 12:33:48.361926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31610 12:33:48.362293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31612 12:33:48.398677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31614 12:33:48.399062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31615 12:33:48.441962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31617 12:33:48.442481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31618 12:33:48.482992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31620 12:33:48.483486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31621 12:33:48.519985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31622 12:33:48.520467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31624 12:33:48.567814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31625 12:33:48.568238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31627 12:33:48.607387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31628 12:33:48.607959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31630 12:33:48.647439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31632 12:33:48.648153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31633 12:33:48.690134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31634 12:33:48.690613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31636 12:33:48.729269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31637 12:33:48.729796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31639 12:33:48.765111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31640 12:33:48.765563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31642 12:33:48.810202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31643 12:33:48.810558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31645 12:33:48.846593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31646 12:33:48.847132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31648 12:33:48.896057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31649 12:33:48.896585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31651 12:33:48.931294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31653 12:33:48.931762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31654 12:33:48.966062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31655 12:33:48.966477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31657 12:33:49.001712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31658 12:33:49.002129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31660 12:33:49.045170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31661 12:33:49.045595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31663 12:33:49.093968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31665 12:33:49.094418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31666 12:33:49.126476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31667 12:33:49.126880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31669 12:33:49.162974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31670 12:33:49.163400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31672 12:33:49.200354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31674 12:33:49.201124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31675 12:33:49.243132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31677 12:33:49.243626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31678 12:33:49.281536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31680 12:33:49.282160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31681 12:33:49.315943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31683 12:33:49.316372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31684 12:33:49.353823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31685 12:33:49.354247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31687 12:33:49.389348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31689 12:33:49.389843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31690 12:33:49.426369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31691 12:33:49.426800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31693 12:33:49.463620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31694 12:33:49.464051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31696 12:33:49.498783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31698 12:33:49.499224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31699 12:33:49.534315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31701 12:33:49.534779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31702 12:33:49.579863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31704 12:33:49.580626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31705 12:33:49.630067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31706 12:33:49.630449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31708 12:33:49.679468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31709 12:33:49.680024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31711 12:33:49.731213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31712 12:33:49.731660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31714 12:33:49.778439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31715 12:33:49.778895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31717 12:33:49.824907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31718 12:33:49.825335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31720 12:33:49.862334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31721 12:33:49.862762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31723 12:33:49.914607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31724 12:33:49.915114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31726 12:33:49.956737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31727 12:33:49.957157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31729 12:33:50.004847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31730 12:33:50.005237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31732 12:33:50.041232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31733 12:33:50.041676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31735 12:33:50.086231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31736 12:33:50.086626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31738 12:33:50.133006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31740 12:33:50.133488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31741 12:33:50.171179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31742 12:33:50.171579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31744 12:33:50.208232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31746 12:33:50.208831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31747 12:33:50.245130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31748 12:33:50.245711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31750 12:33:50.294260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31751 12:33:50.294692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31753 12:33:50.329606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31754 12:33:50.330073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31756 12:33:50.366508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31757 12:33:50.367015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31759 12:33:50.403460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31761 12:33:50.403904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31762 12:33:50.438538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31763 12:33:50.439039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31765 12:33:50.475495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31766 12:33:50.475899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31768 12:33:50.511014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31770 12:33:50.511412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31771 12:33:50.554179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31772 12:33:50.554583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31774 12:33:50.597574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31775 12:33:50.597993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31777 12:33:50.645356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31778 12:33:50.645822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31780 12:33:50.698131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31781 12:33:50.698580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31783 12:33:50.739307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31784 12:33:50.739765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31786 12:33:50.787551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31787 12:33:50.787989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31789 12:33:50.824525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31791 12:33:50.824995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31792 12:33:50.870962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31793 12:33:50.871386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31795 12:33:50.913766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31796 12:33:50.914214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31798 12:33:50.950903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31799 12:33:50.951470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31801 12:33:50.997330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31802 12:33:50.997771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31804 12:33:51.050191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31806 12:33:51.050671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31807 12:33:51.095233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31809 12:33:51.095623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31810 12:33:51.142040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31812 12:33:51.142799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31813 12:33:51.177543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31814 12:33:51.178022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31816 12:33:51.210364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31817 12:33:51.210959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31819 12:33:51.243801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31820 12:33:51.244203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31822 12:33:51.285539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31823 12:33:51.285956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31825 12:33:51.322451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31826 12:33:51.322897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31828 12:33:51.369434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31829 12:33:51.369819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31831 12:33:51.414313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31832 12:33:51.414743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31834 12:33:51.453414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31835 12:33:51.453898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31837 12:33:51.493895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31838 12:33:51.494289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31840 12:33:51.536464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31842 12:33:51.536915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31843 12:33:51.572077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31844 12:33:51.572465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31846 12:33:51.615243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31847 12:33:51.615634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31849 12:33:51.651640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31851 12:33:51.652063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31852 12:33:51.686429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31854 12:33:51.686809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31855 12:33:51.721437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31856 12:33:51.721865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31858 12:33:51.767414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31859 12:33:51.767938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31861 12:33:51.809348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31863 12:33:51.809977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31864 12:33:51.857722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31866 12:33:51.858217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31867 12:33:51.901955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31868 12:33:51.902385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31870 12:33:51.947328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31872 12:33:51.947823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31873 12:33:51.990971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31874 12:33:51.991419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31876 12:33:52.026309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31877 12:33:52.026730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31879 12:33:52.067820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31880 12:33:52.068252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31882 12:33:52.125135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31883 12:33:52.125559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31885 12:33:52.183041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31886 12:33:52.183435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31888 12:33:52.223442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31890 12:33:52.223886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31891 12:33:52.265981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31892 12:33:52.266433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31894 12:33:52.306150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31896 12:33:52.306925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31897 12:33:52.341794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31898 12:33:52.342295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31900 12:33:52.385217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31902 12:33:52.385667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31903 12:33:52.434735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31905 12:33:52.435199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31906 12:33:52.476736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31907 12:33:52.477169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31909 12:33:52.515785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31910 12:33:52.516247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31912 12:33:52.561658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31913 12:33:52.562041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31915 12:33:52.604972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31917 12:33:52.605417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31918 12:33:52.643038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31919 12:33:52.643492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31921 12:33:52.687883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31923 12:33:52.688359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31924 12:33:52.728193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31926 12:33:52.728779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31927 12:33:52.767361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31928 12:33:52.767796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31930 12:33:52.803680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31932 12:33:52.804169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31933 12:33:52.838743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31934 12:33:52.839196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31936 12:33:52.897311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31938 12:33:52.897805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31939 12:33:52.939286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31940 12:33:52.939738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31942 12:33:52.979374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31943 12:33:52.979805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31945 12:33:53.033138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31946 12:33:53.033574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31948 12:33:53.082377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31949 12:33:53.082940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31951 12:33:53.118506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31952 12:33:53.119006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31954 12:33:53.166969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31955 12:33:53.167544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31957 12:33:53.206323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31958 12:33:53.206874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31960 12:33:53.244777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31961 12:33:53.245162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31963 12:33:53.291437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31965 12:33:53.291920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31966 12:33:53.337837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31968 12:33:53.338223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31969 12:33:53.373316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31970 12:33:53.373763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31972 12:33:53.410807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31973 12:33:53.411237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31975 12:33:53.449498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31977 12:33:53.449910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31978 12:33:53.486657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31979 12:33:53.487093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31981 12:33:53.526242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31983 12:33:53.526712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31984 12:33:53.561476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31985 12:33:53.561878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31987 12:33:53.597845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31989 12:33:53.598312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31990 12:33:53.637106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31991 12:33:53.637539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31993 12:33:53.675785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31994 12:33:53.676237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31996 12:33:53.711708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31997 12:33:53.712163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31999 12:33:53.751267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
32000 12:33:53.751697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
32002 12:33:53.788114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
32003 12:33:53.788503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
32005 12:33:53.835281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
32006 12:33:53.835678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
32008 12:33:53.873778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
32009 12:33:53.874179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
32011 12:33:53.908614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
32012 12:33:53.909020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
32014 12:33:53.944960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
32016 12:33:53.945442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
32017 12:33:53.991616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
32018 12:33:53.992049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
32020 12:33:54.037232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
32022 12:33:54.037707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
32023 12:33:54.079699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
32024 12:33:54.080153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
32026 12:33:54.115671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
32027 12:33:54.116167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
32029 12:33:54.159165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
32030 12:33:54.159569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
32032 12:33:54.197100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
32033 12:33:54.197550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
32035 12:33:54.233433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
32037 12:33:54.233935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
32038 12:33:54.281701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
32039 12:33:54.282067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
32041 12:33:54.339556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
32043 12:33:54.340042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
32044 12:33:54.373639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
32045 12:33:54.374085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
32047 12:33:54.412334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
32049 12:33:54.412774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
32050 12:33:54.449803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
32051 12:33:54.450283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
32053 12:33:54.500015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
32055 12:33:54.500502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
32056 12:33:54.543674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
32057 12:33:54.544109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
32059 12:33:54.582091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
32060 12:33:54.582536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
32062 12:33:54.620949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
32064 12:33:54.621697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
32065 12:33:54.658568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
32066 12:33:54.659028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
32068 12:33:54.695961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
32069 12:33:54.696395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
32071 12:33:54.741040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
32072 12:33:54.741457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32074 12:33:54.781085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32075 12:33:54.781537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32077 12:33:54.830041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32078 12:33:54.830429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32080 12:33:54.882261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32081 12:33:54.882657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32083 12:33:54.939036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32085 12:33:54.939521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32086 12:33:54.985174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32087 12:33:54.985616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32089 12:33:55.024992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32091 12:33:55.025461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32092 12:33:55.062479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32093 12:33:55.062862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32095 12:33:55.102728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32096 12:33:55.103158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32098 12:33:55.155783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32099 12:33:55.156259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32101 12:33:55.197983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32102 12:33:55.198386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32104 12:33:55.237699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32105 12:33:55.238147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32107 12:33:55.284979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32108 12:33:55.285409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32110 12:33:55.339001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32111 12:33:55.339523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32113 12:33:55.378929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32114 12:33:55.379325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32116 12:33:55.415426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32117 12:33:55.415926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32119 12:33:55.451683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32121 12:33:55.452412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32122 12:33:55.490825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32123 12:33:55.491288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32125 12:33:55.538505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32126 12:33:55.538861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32128 12:33:55.585665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32129 12:33:55.586136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32131 12:33:55.622618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32132 12:33:55.623074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32134 12:33:55.659837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32135 12:33:55.660292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32137 12:33:55.696833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32138 12:33:55.697272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32140 12:33:55.734997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32141 12:33:55.735447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32143 12:33:55.778470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32144 12:33:55.778931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32146 12:33:55.818689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32147 12:33:55.819134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32149 12:33:55.856966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32150 12:33:55.857330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32152 12:33:55.890257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32153 12:33:55.890728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32155 12:33:55.924958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32156 12:33:55.925394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32158 12:33:55.961953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32159 12:33:55.962330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32161 12:33:55.997329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32162 12:33:55.997680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32164 12:33:56.033613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32165 12:33:56.034032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32167 12:33:56.076422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32169 12:33:56.076850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32170 12:33:56.118181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32172 12:33:56.118656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32173 12:33:56.159527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32174 12:33:56.159955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32176 12:33:56.195033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32177 12:33:56.195487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32179 12:33:56.237006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32180 12:33:56.237460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32182 12:33:56.288169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32183 12:33:56.288557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32185 12:33:56.338223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32186 12:33:56.338671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32188 12:33:56.379804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32190 12:33:56.380289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32191 12:33:56.437434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32192 12:33:56.437881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32194 12:33:56.491866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32195 12:33:56.492364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32197 12:33:56.547733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32199 12:33:56.548431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32200 12:33:56.601468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32202 12:33:56.601916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32203 12:33:56.655875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32205 12:33:56.656523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32206 12:33:56.702554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32207 12:33:56.703133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32209 12:33:56.747502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32211 12:33:56.748184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32212 12:33:56.802396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32213 12:33:56.802805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32215 12:33:56.852980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32216 12:33:56.853439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32218 12:33:56.891792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32219 12:33:56.892245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32221 12:33:56.943986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32223 12:33:56.944447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32224 12:33:56.981963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32225 12:33:56.982372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32227 12:33:57.020931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32228 12:33:57.021324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32230 12:33:57.065961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32232 12:33:57.066486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32233 12:33:57.103507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32234 12:33:57.103993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32236 12:33:57.142193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32237 12:33:57.142747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32239 12:33:57.181884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32240 12:33:57.182429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32242 12:33:57.225699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32243 12:33:57.226161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32245 12:33:57.273316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32246 12:33:57.273790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32248 12:33:57.313860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32250 12:33:57.314336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32251 12:33:57.356932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32253 12:33:57.357418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32254 12:33:57.397760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32255 12:33:57.398238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32257 12:33:57.446247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32259 12:33:57.446654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32260 12:33:57.485239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32262 12:33:57.485956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32263 12:33:57.528468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32265 12:33:57.528960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32266 12:33:57.566245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32267 12:33:57.566687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32269 12:33:57.608359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32271 12:33:57.608838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32272 12:33:57.643626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32273 12:33:57.644034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32275 12:33:57.686680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32277 12:33:57.687155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32278 12:33:57.725223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32279 12:33:57.725694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32281 12:33:57.766365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32282 12:33:57.766797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32284 12:33:57.807634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32285 12:33:57.808049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32287 12:33:57.851254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32289 12:33:57.851709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32290 12:33:57.893242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32291 12:33:57.893642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32293 12:33:57.931442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32294 12:33:57.931862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32296 12:33:57.998615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32297 12:33:57.999046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32299 12:33:58.046579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32300 12:33:58.047071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32302 12:33:58.092819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32303 12:33:58.093349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32305 12:33:58.142928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32306 12:33:58.143414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32308 12:33:58.180938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32310 12:33:58.181707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32311 12:33:58.217815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32312 12:33:58.218319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32314 12:33:58.261370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32315 12:33:58.261783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32317 12:33:58.316131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32319 12:33:58.316552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32320 12:33:58.356792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32321 12:33:58.357369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32323 12:33:58.399551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32324 12:33:58.399955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32326 12:33:58.444077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32327 12:33:58.444535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32329 12:33:58.489624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32330 12:33:58.490052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32332 12:33:58.545820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32334 12:33:58.546310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32335 12:33:58.595431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32336 12:33:58.595870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32338 12:33:58.636599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32340 12:33:58.637073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32341 12:33:58.671785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32342 12:33:58.672242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32344 12:33:58.713690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32345 12:33:58.714086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32347 12:33:58.754540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32348 12:33:58.754933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32350 12:33:58.790819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32351 12:33:58.791238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32353 12:33:58.834301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32354 12:33:58.834695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32356 12:33:58.876100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32358 12:33:58.876580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32359 12:33:58.930293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32360 12:33:58.930746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32362 12:33:58.974711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32363 12:33:58.975133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32365 12:33:59.017118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32367 12:33:59.017576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32368 12:33:59.055987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32370 12:33:59.056486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32371 12:33:59.109264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32372 12:33:59.109752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32374 12:33:59.149582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32375 12:33:59.150032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32377 12:33:59.195449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32378 12:33:59.195899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32380 12:33:59.233666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32382 12:33:59.234154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32383 12:33:59.271569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32384 12:33:59.272016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32386 12:33:59.313463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32387 12:33:59.313939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32389 12:33:59.351495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32390 12:33:59.351960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32392 12:33:59.386695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32393 12:33:59.387109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32395 12:33:59.433452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32396 12:33:59.434001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32398 12:33:59.473272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32400 12:33:59.473773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32401 12:33:59.507665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32402 12:33:59.508092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32404 12:33:59.542553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32405 12:33:59.542955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32407 12:33:59.579260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32408 12:33:59.579665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32410 12:33:59.617772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32411 12:33:59.618229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32413 12:33:59.656249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32414 12:33:59.656669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32416 12:33:59.702158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32417 12:33:59.702588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32419 12:33:59.743836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32421 12:33:59.744312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32422 12:33:59.778618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32423 12:33:59.779045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32425 12:33:59.814441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32426 12:33:59.814867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32428 12:33:59.853742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32429 12:33:59.854180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32431 12:33:59.901234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32432 12:33:59.901752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32434 12:33:59.959004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32435 12:33:59.959400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32437 12:34:00.001041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32438 12:34:00.001509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32440 12:34:00.053324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32441 12:34:00.053755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32443 12:34:00.110537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32444 12:34:00.111005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32446 12:34:00.150685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32448 12:34:00.151134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32449 12:34:00.192922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32450 12:34:00.193379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32452 12:34:00.227967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32453 12:34:00.228379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32455 12:34:00.270979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32457 12:34:00.271468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32458 12:34:00.318039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32459 12:34:00.318472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32461 12:34:00.364981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32462 12:34:00.365416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32464 12:34:00.417196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32465 12:34:00.417618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32467 12:34:00.464882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32468 12:34:00.465319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32470 12:34:00.507989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32471 12:34:00.508421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32473 12:34:00.544672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32475 12:34:00.545095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32476 12:34:00.585403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32477 12:34:00.585801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32479 12:34:00.623150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32480 12:34:00.623558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32482 12:34:00.662000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32484 12:34:00.662394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32485 12:34:00.701661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32487 12:34:00.702433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32488 12:34:00.741815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32489 12:34:00.742209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32491 12:34:00.788087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32493 12:34:00.788608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32494 12:34:00.838693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32496 12:34:00.839072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32497 12:34:00.877899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32498 12:34:00.878280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32500 12:34:00.917977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32502 12:34:00.918446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32503 12:34:00.963248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32504 12:34:00.963652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32506 12:34:01.001257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32507 12:34:01.001715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32509 12:34:01.046199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32510 12:34:01.046653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32512 12:34:01.085418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32514 12:34:01.086194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32515 12:34:01.140258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32517 12:34:01.140682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32518 12:34:01.177999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32519 12:34:01.178431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32521 12:34:01.218157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32522 12:34:01.218566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32524 12:34:01.256605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32526 12:34:01.257082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32527 12:34:01.299439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32528 12:34:01.299876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32530 12:34:01.354145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32531 12:34:01.354574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32533 12:34:01.400407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32535 12:34:01.400883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32536 12:34:01.458614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32538 12:34:01.459101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32539 12:34:01.505384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32540 12:34:01.505791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32542 12:34:01.559311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32543 12:34:01.559809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32545 12:34:01.607177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32547 12:34:01.607619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32548 12:34:01.658438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32550 12:34:01.658950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32551 12:34:01.710499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32552 12:34:01.710935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32554 12:34:01.750409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32555 12:34:01.750850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32557 12:34:01.789399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32558 12:34:01.789862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32560 12:34:01.829180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32561 12:34:01.829637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32563 12:34:01.870607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32564 12:34:01.871051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32566 12:34:01.909388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32567 12:34:01.909923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32569 12:34:01.947734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32570 12:34:01.948262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32572 12:34:01.989897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32573 12:34:01.990273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32575 12:34:02.027399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32576 12:34:02.027872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32578 12:34:02.065976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32579 12:34:02.066397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32581 12:34:02.105000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32582 12:34:02.105433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32584 12:34:02.145203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32585 12:34:02.145637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32587 12:34:02.186970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32588 12:34:02.187399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32590 12:34:02.233374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32591 12:34:02.233817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32593 12:34:02.277007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32594 12:34:02.277422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32596 12:34:02.321727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32597 12:34:02.322160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32599 12:34:02.361531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32600 12:34:02.361970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32602 12:34:02.401041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32603 12:34:02.401462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32605 12:34:02.440452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32607 12:34:02.440995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32608 12:34:02.486411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32609 12:34:02.486863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32611 12:34:02.532519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32613 12:34:02.533002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32614 12:34:02.576549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32616 12:34:02.577042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32617 12:34:02.633944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32618 12:34:02.634376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32620 12:34:02.673802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32621 12:34:02.674235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32623 12:34:02.713961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32624 12:34:02.714398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32626 12:34:02.757342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32627 12:34:02.757785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32629 12:34:02.802066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32630 12:34:02.802502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32632 12:34:02.863646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32634 12:34:02.864089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32635 12:34:02.922485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32636 12:34:02.922921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32638 12:34:02.981297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32639 12:34:02.981785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32641 12:34:03.026594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32642 12:34:03.027047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32644 12:34:03.065944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32645 12:34:03.066513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32647 12:34:03.130739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32648 12:34:03.131244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32650 12:34:03.185645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32651 12:34:03.186076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32653 12:34:03.231510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32654 12:34:03.231930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32656 12:34:03.269770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32657 12:34:03.270173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32659 12:34:03.309599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32660 12:34:03.309998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32662 12:34:03.346779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32663 12:34:03.347168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32665 12:34:03.392986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32667 12:34:03.393447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32668 12:34:03.432003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32670 12:34:03.432486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32671 12:34:03.475295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32672 12:34:03.475727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32674 12:34:03.517126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32676 12:34:03.517602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32677 12:34:03.571552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32679 12:34:03.572033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32680 12:34:03.629207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32681 12:34:03.629588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32683 12:34:03.679387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32684 12:34:03.679815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32686 12:34:03.722107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32687 12:34:03.722558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32689 12:34:03.759461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32690 12:34:03.759887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32692 12:34:03.796550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32694 12:34:03.796949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32695 12:34:03.835162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32697 12:34:03.835619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32698 12:34:03.875059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32700 12:34:03.875542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32701 12:34:03.914153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32702 12:34:03.914553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32704 12:34:03.955153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32705 12:34:03.955545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32707 12:34:03.991765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32708 12:34:03.992137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32710 12:34:04.029850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32711 12:34:04.030255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32713 12:34:04.072343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32715 12:34:04.072752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32716 12:34:04.115036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32717 12:34:04.115425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32719 12:34:04.158770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32720 12:34:04.159192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32722 12:34:04.198567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32723 12:34:04.198987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32725 12:34:04.236514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32727 12:34:04.236929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32728 12:34:04.276405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32730 12:34:04.276830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32731 12:34:04.317406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32732 12:34:04.317855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32734 12:34:04.355687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32735 12:34:04.356132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32737 12:34:04.399560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32738 12:34:04.400018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32740 12:34:04.441642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32741 12:34:04.442089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32743 12:34:04.480372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32745 12:34:04.480863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32746 12:34:04.518157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32747 12:34:04.518588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32749 12:34:04.565951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32750 12:34:04.566381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32752 12:34:04.607456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32753 12:34:04.608000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32755 12:34:04.650281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32756 12:34:04.650711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32758 12:34:04.705260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32760 12:34:04.705760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32761 12:34:04.746588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32762 12:34:04.746953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32764 12:34:04.786368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32765 12:34:04.786833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32767 12:34:04.825850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32768 12:34:04.826276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32770 12:34:04.867223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32771 12:34:04.867662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32773 12:34:04.908276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32775 12:34:04.908753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32776 12:34:04.952646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32778 12:34:04.953128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32779 12:34:04.998941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32780 12:34:04.999368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32782 12:34:05.039437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32783 12:34:05.039876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32785 12:34:05.084445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32787 12:34:05.084919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32788 12:34:05.123989 <47>[ 394.481132] systemd-journald[109]: Sent WATCHDOG=1 notification.
32789 12:34:05.146153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32790 12:34:05.146639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32792 12:34:05.197551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32793 12:34:05.198113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32795 12:34:05.235849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32796 12:34:05.236295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32798 12:34:05.280612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32800 12:34:05.281399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32801 12:34:05.332149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32802 12:34:05.332600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32804 12:34:05.379986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32805 12:34:05.380552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32807 12:34:05.419993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32809 12:34:05.420663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32810 12:34:05.467483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32811 12:34:05.467981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32813 12:34:05.506714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32814 12:34:05.507259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32816 12:34:05.551769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32817 12:34:05.552321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32819 12:34:05.591986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32820 12:34:05.592490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32822 12:34:05.636644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32824 12:34:05.637322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32825 12:34:05.688538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32827 12:34:05.688966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32828 12:34:05.734897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32829 12:34:05.735315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32831 12:34:05.776932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32832 12:34:05.777313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32834 12:34:05.830065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32835 12:34:05.830643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32837 12:34:05.877851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32838 12:34:05.878371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32840 12:34:05.918585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32841 12:34:05.918988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32843 12:34:05.967634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32844 12:34:05.968070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32846 12:34:06.016489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32848 12:34:06.016935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32849 12:34:06.059825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32850 12:34:06.060394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32852 12:34:06.117207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32854 12:34:06.117842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32855 12:34:06.176434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32857 12:34:06.177095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32858 12:34:06.219489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32859 12:34:06.220007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32861 12:34:06.274482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32862 12:34:06.274995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32864 12:34:06.323005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32866 12:34:06.323775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32867 12:34:06.363650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32869 12:34:06.364110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32870 12:34:06.410032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32871 12:34:06.410418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32873 12:34:06.450106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32874 12:34:06.450514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32876 12:34:06.490153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32877 12:34:06.490577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32879 12:34:06.530358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32880 12:34:06.530777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32882 12:34:06.570646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32883 12:34:06.571068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32885 12:34:06.610765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32886 12:34:06.611249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32888 12:34:06.652407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32890 12:34:06.653088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32891 12:34:06.693041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32893 12:34:06.693422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32894 12:34:06.736023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32895 12:34:06.736449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32897 12:34:06.774601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32898 12:34:06.775116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32900 12:34:06.814381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32901 12:34:06.814893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32903 12:34:06.853149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32905 12:34:06.853675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32906 12:34:06.907273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32907 12:34:06.907768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32909 12:34:06.945433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32910 12:34:06.945846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32912 12:34:06.983968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32913 12:34:06.984377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32915 12:34:07.021025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32916 12:34:07.021470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32918 12:34:07.062297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32920 12:34:07.062756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32921 12:34:07.100486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32923 12:34:07.100965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32924 12:34:07.138990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32926 12:34:07.139455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32927 12:34:07.175556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32928 12:34:07.176008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32930 12:34:07.213452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32931 12:34:07.213880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32933 12:34:07.250206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32934 12:34:07.250596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32936 12:34:07.287292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32937 12:34:07.287722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32939 12:34:07.336886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32940 12:34:07.337312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32942 12:34:07.373330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32943 12:34:07.373755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32945 12:34:07.412079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32947 12:34:07.412560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32948 12:34:07.454400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32949 12:34:07.454789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32951 12:34:07.506515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32952 12:34:07.507008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32954 12:34:07.559659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32955 12:34:07.560134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32957 12:34:07.602659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32958 12:34:07.603110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32960 12:34:07.643230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32961 12:34:07.643661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32963 12:34:07.688559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32965 12:34:07.689128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32966 12:34:07.728866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32967 12:34:07.729254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32969 12:34:07.769068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32970 12:34:07.769498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32972 12:34:07.813231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32974 12:34:07.813894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32975 12:34:07.861474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32976 12:34:07.862022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32978 12:34:07.901199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32979 12:34:07.901638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32981 12:34:07.949789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32983 12:34:07.950268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32984 12:34:07.989425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32985 12:34:07.989842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32987 12:34:08.034771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32988 12:34:08.035204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32990 12:34:08.091529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32991 12:34:08.091970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32993 12:34:08.149052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32994 12:34:08.149462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32996 12:34:08.193102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32998 12:34:08.193819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32999 12:34:08.247904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
33000 12:34:08.248300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
33002 12:34:08.290720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
33003 12:34:08.291130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
33005 12:34:08.334662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
33006 12:34:08.335145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
33008 12:34:08.373437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
33009 12:34:08.373866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
33011 12:34:08.423840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
33013 12:34:08.424339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
33014 12:34:08.467071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
33016 12:34:08.467553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
33017 12:34:08.509818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
33018 12:34:08.510234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
33020 12:34:08.565991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
33021 12:34:08.566410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
33023 12:34:08.605690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
33025 12:34:08.606329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
33026 12:34:08.646636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
33028 12:34:08.647397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
33029 12:34:08.685795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
33030 12:34:08.686365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
33032 12:34:08.727540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
33033 12:34:08.728077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
33035 12:34:08.778543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
33037 12:34:08.778973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
33038 12:34:08.815980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
33040 12:34:08.816630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
33041 12:34:08.854969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
33042 12:34:08.855461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
33044 12:34:08.901129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
33045 12:34:08.901549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
33047 12:34:08.941001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
33048 12:34:08.941429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
33050 12:34:08.978037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
33051 12:34:08.978454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
33053 12:34:09.017036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
33055 12:34:09.017489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
33056 12:34:09.059148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
33057 12:34:09.059565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
33059 12:34:09.102252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
33061 12:34:09.102712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
33062 12:34:09.144259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
33064 12:34:09.144740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
33065 12:34:09.194937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
33066 12:34:09.195366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
33068 12:34:09.236516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
33070 12:34:09.237142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
33071 12:34:09.275612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33072 12:34:09.276101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
33074 12:34:09.314011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33075 12:34:09.314468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33077 12:34:09.351401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33078 12:34:09.351856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33080 12:34:09.390020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33081 12:34:09.390423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33083 12:34:09.444080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33084 12:34:09.444511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33086 12:34:09.501705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33087 12:34:09.502082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33089 12:34:09.558119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33090 12:34:09.558522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33092 12:34:09.614362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33093 12:34:09.614877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33095 12:34:09.669717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33097 12:34:09.670158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33098 12:34:09.722394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33100 12:34:09.723003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33101 12:34:09.765132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33102 12:34:09.765592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33104 12:34:09.806693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33105 12:34:09.807195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33107 12:34:09.854240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33108 12:34:09.854644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33110 12:34:09.905179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33111 12:34:09.905599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33113 12:34:09.952642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33114 12:34:09.953052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33116 12:34:10.010601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33117 12:34:10.011169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33119 12:34:10.052472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33121 12:34:10.053231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33122 12:34:10.099757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33123 12:34:10.100113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33125 12:34:10.145596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33127 12:34:10.146086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33128 12:34:10.183834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33129 12:34:10.184273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33131 12:34:10.223378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33132 12:34:10.223795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33134 12:34:10.265918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33135 12:34:10.266344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33137 12:34:10.311767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33139 12:34:10.312240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33140 12:34:10.365994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33141 12:34:10.366413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33143 12:34:10.403444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33144 12:34:10.403847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33146 12:34:10.449428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33147 12:34:10.449826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33149 12:34:10.487671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33150 12:34:10.488091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33152 12:34:10.525933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33153 12:34:10.526308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33155 12:34:10.582730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33157 12:34:10.583422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33158 12:34:10.621855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33159 12:34:10.622276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33161 12:34:10.661420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33162 12:34:10.661882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33164 12:34:10.701289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33165 12:34:10.701693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33167 12:34:10.745482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33169 12:34:10.745956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33170 12:34:10.787980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33171 12:34:10.788388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33173 12:34:10.828093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33175 12:34:10.828582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33176 12:34:10.881644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33177 12:34:10.882042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33179 12:34:10.932496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33181 12:34:10.932898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33182 12:34:10.981516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33183 12:34:10.981931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33185 12:34:11.018486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33187 12:34:11.018930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33188 12:34:11.065848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33190 12:34:11.066327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33191 12:34:11.101755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33192 12:34:11.102202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33194 12:34:11.139345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33195 12:34:11.139795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33197 12:34:11.181879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33199 12:34:11.182324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33200 12:34:11.221390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33201 12:34:11.221884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33203 12:34:11.258286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33205 12:34:11.259001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33206 12:34:11.295823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33208 12:34:11.296440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33209 12:34:11.334640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33211 12:34:11.335384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33212 12:34:11.376460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33214 12:34:11.377002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33215 12:34:11.425899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33217 12:34:11.426538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33218 12:34:11.462786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33219 12:34:11.463282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33221 12:34:11.511237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33222 12:34:11.511636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33224 12:34:11.560011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33226 12:34:11.560494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33227 12:34:11.606757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33228 12:34:11.607175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33230 12:34:11.667413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33231 12:34:11.667863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33233 12:34:11.709675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33235 12:34:11.710116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33236 12:34:11.759472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33237 12:34:11.759882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33239 12:34:11.798350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33240 12:34:11.798759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33242 12:34:11.835732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33243 12:34:11.836140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33245 12:34:11.872898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33246 12:34:11.873486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33248 12:34:11.914869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33250 12:34:11.915332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33251 12:34:11.955797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33253 12:34:11.956278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33254 12:34:11.993085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33255 12:34:11.993532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33257 12:34:12.039372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33259 12:34:12.040139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33260 12:34:12.094175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33261 12:34:12.094537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33263 12:34:12.149286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33264 12:34:12.149888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33266 12:34:12.202774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33267 12:34:12.203246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33269 12:34:12.257080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33270 12:34:12.257555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33272 12:34:12.314323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33274 12:34:12.315123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33275 12:34:12.367964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33277 12:34:12.368576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33278 12:34:12.404032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33279 12:34:12.404583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33281 12:34:12.441224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33282 12:34:12.441636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33284 12:34:12.479427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33286 12:34:12.479995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33287 12:34:12.518058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33289 12:34:12.518709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33290 12:34:12.555862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33291 12:34:12.556270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33293 12:34:12.593468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33294 12:34:12.593922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33296 12:34:12.634107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33298 12:34:12.634488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33299 12:34:12.690378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33301 12:34:12.690868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33302 12:34:12.745503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33303 12:34:12.746061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33305 12:34:12.802108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33306 12:34:12.802534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33308 12:34:12.857269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33309 12:34:12.857667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33311 12:34:12.911219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33312 12:34:12.911653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33314 12:34:12.964052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33315 12:34:12.964448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33317 12:34:13.007750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33319 12:34:13.008228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33320 12:34:13.046760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33321 12:34:13.047199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33323 12:34:13.099539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33324 12:34:13.099955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33326 12:34:13.142663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33327 12:34:13.143051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33329 12:34:13.198258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33330 12:34:13.198790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33332 12:34:13.254823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33333 12:34:13.255338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33335 12:34:13.310300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33336 12:34:13.310807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33338 12:34:13.383629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33339 12:34:13.384035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33341 12:34:13.427091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33342 12:34:13.427525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33344 12:34:13.485940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33345 12:34:13.486423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33347 12:34:13.534670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33349 12:34:13.535122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33350 12:34:13.586755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33352 12:34:13.587308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33353 12:34:13.633971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33354 12:34:13.634398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33356 12:34:13.674857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33357 12:34:13.675262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33359 12:34:13.719904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33361 12:34:13.720421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33362 12:34:13.765226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33363 12:34:13.765635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33365 12:34:13.817017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33366 12:34:13.817443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33368 12:34:13.856340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33370 12:34:13.857020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33371 12:34:13.894823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33372 12:34:13.895369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33374 12:34:13.934209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33376 12:34:13.934876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33377 12:34:13.973432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33379 12:34:13.973922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33380 12:34:14.030844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33381 12:34:14.031288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33383 12:34:14.090224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33384 12:34:14.090592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33386 12:34:14.149643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33387 12:34:14.150087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33389 12:34:14.191509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33390 12:34:14.192021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33392 12:34:14.239985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33393 12:34:14.240444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33395 12:34:14.293022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33396 12:34:14.293407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33398 12:34:14.345973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33399 12:34:14.346484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33401 12:34:14.398939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33402 12:34:14.399370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33404 12:34:14.444986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33406 12:34:14.445368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33407 12:34:14.485936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33408 12:34:14.486240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33410 12:34:14.527582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33411 12:34:14.527930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33413 12:34:14.576432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33415 12:34:14.576816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33416 12:34:14.618409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33417 12:34:14.618788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33419 12:34:14.657525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33420 12:34:14.657989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33422 12:34:14.698988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33423 12:34:14.699379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33425 12:34:14.739040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33426 12:34:14.739464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33428 12:34:14.779219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33429 12:34:14.779666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33431 12:34:14.821829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33433 12:34:14.822293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33434 12:34:14.863666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33435 12:34:14.864101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33437 12:34:14.907480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33438 12:34:14.907873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33440 12:34:14.951420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33441 12:34:14.951836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33443 12:34:14.992108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33444 12:34:14.992495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33446 12:34:15.047391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33448 12:34:15.047879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33449 12:34:15.087802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33450 12:34:15.088183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33452 12:34:15.129799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33453 12:34:15.130249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33455 12:34:15.169038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33457 12:34:15.169498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33458 12:34:15.207994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33459 12:34:15.208422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33461 12:34:15.248319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33463 12:34:15.248787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33464 12:34:15.288285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33466 12:34:15.288849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33467 12:34:15.327867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33469 12:34:15.328341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33470 12:34:15.366872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33471 12:34:15.367323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33473 12:34:15.405720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33475 12:34:15.406190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33476 12:34:15.443399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33477 12:34:15.443844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33479 12:34:15.483314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33480 12:34:15.483706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33482 12:34:15.522266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33483 12:34:15.522708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33485 12:34:15.561781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33486 12:34:15.562221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33488 12:34:15.601469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33489 12:34:15.601931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33491 12:34:15.639875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33492 12:34:15.640325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33494 12:34:15.679042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33495 12:34:15.679479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33497 12:34:15.718514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33498 12:34:15.718980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33500 12:34:15.757738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33501 12:34:15.758171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33503 12:34:15.797801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33504 12:34:15.798229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33506 12:34:15.841725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33507 12:34:15.842157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33509 12:34:15.892185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33511 12:34:15.892671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33512 12:34:15.937728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33513 12:34:15.938152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33515 12:34:15.982551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33516 12:34:15.982978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33518 12:34:16.021863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33519 12:34:16.022305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33521 12:34:16.062371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33522 12:34:16.062809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33524 12:34:16.103415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33525 12:34:16.103868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33527 12:34:16.149118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33528 12:34:16.149562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33530 12:34:16.210161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33531 12:34:16.210533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33533 12:34:16.257845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33534 12:34:16.258304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33536 12:34:16.309838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33537 12:34:16.310402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33539 12:34:16.362339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33540 12:34:16.362780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33542 12:34:16.401681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33544 12:34:16.402169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33545 12:34:16.441715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33547 12:34:16.442190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33548 12:34:16.479901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33549 12:34:16.480368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33551 12:34:16.519455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33553 12:34:16.519940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33554 12:34:16.558469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33555 12:34:16.558896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33557 12:34:16.599162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33558 12:34:16.599597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33560 12:34:16.658384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33561 12:34:16.658847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33563 12:34:16.718021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33565 12:34:16.718667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33566 12:34:16.777690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33567 12:34:16.778142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33569 12:34:16.835894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33570 12:34:16.836324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33572 12:34:16.894965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33574 12:34:16.895450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33575 12:34:16.954352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33576 12:34:16.954786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33578 12:34:17.013057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33579 12:34:17.013441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33581 12:34:17.071496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33582 12:34:17.071883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33584 12:34:17.131399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33585 12:34:17.131786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33587 12:34:17.190856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33588 12:34:17.191248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33590 12:34:17.251599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33592 12:34:17.252082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33593 12:34:17.312501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33595 12:34:17.313327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33596 12:34:17.372154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33597 12:34:17.372618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33599 12:34:17.424072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33600 12:34:17.424502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33602 12:34:17.464908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33603 12:34:17.465340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33605 12:34:17.503316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33606 12:34:17.503776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33608 12:34:17.543438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33609 12:34:17.543863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33611 12:34:17.583253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33612 12:34:17.583678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33614 12:34:17.622931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33615 12:34:17.623364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33617 12:34:17.661900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33618 12:34:17.662325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33620 12:34:17.702021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33622 12:34:17.702494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33623 12:34:17.741783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33625 12:34:17.742260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33626 12:34:17.780374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33628 12:34:17.780834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33629 12:34:17.819178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33630 12:34:17.819642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33632 12:34:17.859242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33633 12:34:17.859698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33635 12:34:17.904395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33637 12:34:17.904813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33638 12:34:17.953641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33639 12:34:17.954065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33641 12:34:17.997153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33643 12:34:17.997631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33644 12:34:18.037617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33646 12:34:18.038106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33647 12:34:18.076754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33648 12:34:18.077207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33650 12:34:18.115306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33652 12:34:18.115783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33653 12:34:18.170527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33654 12:34:18.170938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33656 12:34:18.215135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33658 12:34:18.215621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33659 12:34:18.254464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33660 12:34:18.254892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33662 12:34:18.303755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33663 12:34:18.304192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33665 12:34:18.349884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33666 12:34:18.350323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33668 12:34:18.389393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33670 12:34:18.389869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33671 12:34:18.430942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33672 12:34:18.431370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33674 12:34:18.506568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33675 12:34:18.507137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33677 12:34:18.557359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33678 12:34:18.557734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33680 12:34:18.602245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33681 12:34:18.602817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33683 12:34:18.645802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33684 12:34:18.646257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33686 12:34:18.687873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33688 12:34:18.688275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33689 12:34:18.733805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33690 12:34:18.734241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33692 12:34:18.778551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33693 12:34:18.778933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33695 12:34:18.825589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33697 12:34:18.826195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33698 12:34:18.865665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33699 12:34:18.866145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33701 12:34:18.910359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33702 12:34:18.910853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33704 12:34:18.956122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33706 12:34:18.956564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33707 12:34:18.995917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33709 12:34:18.996355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33710 12:34:19.045374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33712 12:34:19.045736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33713 12:34:19.095908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33714 12:34:19.096309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33716 12:34:19.139226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33718 12:34:19.139646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33719 12:34:19.178666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33720 12:34:19.179121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33722 12:34:19.215874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33723 12:34:19.216331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33725 12:34:19.259885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33726 12:34:19.260301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33728 12:34:19.307122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33729 12:34:19.307517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33731 12:34:19.359450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33732 12:34:19.359896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33734 12:34:19.410555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33736 12:34:19.411186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33737 12:34:19.449751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33738 12:34:19.450240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33740 12:34:19.486480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33741 12:34:19.486963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33743 12:34:19.530897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33745 12:34:19.531390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33746 12:34:19.576456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33748 12:34:19.576934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33749 12:34:19.613731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33750 12:34:19.614156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33752 12:34:19.651892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33753 12:34:19.652296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33755 12:34:19.702191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33756 12:34:19.702618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33758 12:34:19.744294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33760 12:34:19.744773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33761 12:34:19.793807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33763 12:34:19.794240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33764 12:34:19.837811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33765 12:34:19.838265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33767 12:34:19.877268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33768 12:34:19.877679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33770 12:34:19.926541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33771 12:34:19.926989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33773 12:34:19.978751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33774 12:34:19.979197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33776 12:34:20.021592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33777 12:34:20.022052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33779 12:34:20.076334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33781 12:34:20.076730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33782 12:34:20.113917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33784 12:34:20.114315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33785 12:34:20.163505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33787 12:34:20.163952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33788 12:34:20.210108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33789 12:34:20.210585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33791 12:34:20.248211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33793 12:34:20.248857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33794 12:34:20.287999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33795 12:34:20.288406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33797 12:34:20.333412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33799 12:34:20.333847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33800 12:34:20.370820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33802 12:34:20.371251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33803 12:34:20.409839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33804 12:34:20.410235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33806 12:34:20.459412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33807 12:34:20.459792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33809 12:34:20.501945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33810 12:34:20.502390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33812 12:34:20.547348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33813 12:34:20.547785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33815 12:34:20.586944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33816 12:34:20.587384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33818 12:34:20.625847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33819 12:34:20.626283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33821 12:34:20.665446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33822 12:34:20.665893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33824 12:34:20.703568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33826 12:34:20.704058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33827 12:34:20.759392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33829 12:34:20.759869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33830 12:34:20.819277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33831 12:34:20.819715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33833 12:34:20.867803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33834 12:34:20.868266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33836 12:34:20.914510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33837 12:34:20.914941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33839 12:34:20.956805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33840 12:34:20.957260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33842 12:34:21.003353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33843 12:34:21.003774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33845 12:34:21.044368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33847 12:34:21.044981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33848 12:34:21.086344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33850 12:34:21.086809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33851 12:34:21.125343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33853 12:34:21.125821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33854 12:34:21.175462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33855 12:34:21.175901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33857 12:34:21.215500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33859 12:34:21.215966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33860 12:34:21.255332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33862 12:34:21.255762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33863 12:34:21.294112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33865 12:34:21.294582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33866 12:34:21.345710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33867 12:34:21.346154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33869 12:34:21.404542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33871 12:34:21.405252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33872 12:34:21.457537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33873 12:34:21.457999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33875 12:34:21.504351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33877 12:34:21.504854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33878 12:34:21.559858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33879 12:34:21.560295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33881 12:34:21.600927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33883 12:34:21.601381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33884 12:34:21.639216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33885 12:34:21.639671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33887 12:34:21.680389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33889 12:34:21.680898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33890 12:34:21.718895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33892 12:34:21.719303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33893 12:34:21.758052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33895 12:34:21.758443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33896 12:34:21.801778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33897 12:34:21.802207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33899 12:34:21.847530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33900 12:34:21.847956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33902 12:34:21.886528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33903 12:34:21.886964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33905 12:34:21.925249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33907 12:34:21.925629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33908 12:34:21.972856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33909 12:34:21.973361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33911 12:34:22.010381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33912 12:34:22.010955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33914 12:34:22.048000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33915 12:34:22.048394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33917 12:34:22.095210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33919 12:34:22.095700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33920 12:34:22.135852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33922 12:34:22.136443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33923 12:34:22.174370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33924 12:34:22.174855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33926 12:34:22.213804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33927 12:34:22.214240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33929 12:34:22.251468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33930 12:34:22.251889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33932 12:34:22.290348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33933 12:34:22.290770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33935 12:34:22.335660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33936 12:34:22.336123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33938 12:34:22.381329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33939 12:34:22.381820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33941 12:34:22.430651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33942 12:34:22.431204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33944 12:34:22.479591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33945 12:34:22.480152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33947 12:34:22.517892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33949 12:34:22.518350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33950 12:34:22.569562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33951 12:34:22.570121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33953 12:34:22.626648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33955 12:34:22.627142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33956 12:34:22.673551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33957 12:34:22.673996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33959 12:34:22.712487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33961 12:34:22.712954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33962 12:34:22.767239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33963 12:34:22.767675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33965 12:34:22.822077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33967 12:34:22.822535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33968 12:34:22.859188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33969 12:34:22.859694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33971 12:34:22.897094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33972 12:34:22.897508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33974 12:34:22.939334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33975 12:34:22.939750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33977 12:34:22.982724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33978 12:34:22.983108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33980 12:34:23.018538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33981 12:34:23.018993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33983 12:34:23.067443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33984 12:34:23.067885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33986 12:34:23.111493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33988 12:34:23.111967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33989 12:34:23.150584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33990 12:34:23.151002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33992 12:34:23.189664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33993 12:34:23.190097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33995 12:34:23.229281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33996 12:34:23.229690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33998 12:34:23.268938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
34000 12:34:23.269409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
34001 12:34:23.307625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
34002 12:34:23.308079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
34004 12:34:23.348134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
34005 12:34:23.348569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
34007 12:34:23.408414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
34009 12:34:23.408971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
34010 12:34:23.467500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
34012 12:34:23.467984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
34013 12:34:23.510467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
34015 12:34:23.510948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
34016 12:34:23.550933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
34018 12:34:23.551419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
34019 12:34:23.623955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
34020 12:34:23.624386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
34022 12:34:23.671709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
34023 12:34:23.672168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
34025 12:34:23.722537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
34027 12:34:23.723033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
34028 12:34:23.763445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
34029 12:34:23.763883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
34031 12:34:23.804366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
34033 12:34:23.804842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
34034 12:34:23.851454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
34036 12:34:23.852116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
34037 12:34:23.898228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
34039 12:34:23.898975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
34040 12:34:23.942016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
34041 12:34:23.942399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
34043 12:34:23.982135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
34044 12:34:23.982562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
34046 12:34:24.023949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
34048 12:34:24.024452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
34049 12:34:24.061806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
34050 12:34:24.062249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
34052 12:34:24.101161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
34053 12:34:24.101583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
34055 12:34:24.142105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
34057 12:34:24.142552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
34058 12:34:24.177715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
34059 12:34:24.178124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
34061 12:34:24.214864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
34062 12:34:24.215275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
34064 12:34:24.260430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
34066 12:34:24.260910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
34067 12:34:24.298853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
34069 12:34:24.299236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
34070 12:34:24.338470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
34071 12:34:24.338936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
34073 12:34:24.379915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34075 12:34:24.380403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34076 12:34:24.423344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34077 12:34:24.423773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34079 12:34:24.462406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34081 12:34:24.462885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34082 12:34:24.501693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34083 12:34:24.502118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34085 12:34:24.553791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34086 12:34:24.554223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34088 12:34:24.593359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34090 12:34:24.593854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34091 12:34:24.633229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34093 12:34:24.633725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34094 12:34:24.690126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34095 12:34:24.690553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34097 12:34:24.727875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34098 12:34:24.728289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34100 12:34:24.776789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34101 12:34:24.777226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34103 12:34:24.833093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34105 12:34:24.833598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34106 12:34:24.879089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34107 12:34:24.879618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34109 12:34:24.930791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34111 12:34:24.931293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34112 12:34:24.969816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34113 12:34:24.970211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34115 12:34:25.011743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34117 12:34:25.012213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34118 12:34:25.051393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34119 12:34:25.051822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34121 12:34:25.111040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34122 12:34:25.111411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34124 12:34:25.156055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34126 12:34:25.156527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34127 12:34:25.194578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34129 12:34:25.195082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34130 12:34:25.241916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34132 12:34:25.242331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34133 12:34:25.292446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34135 12:34:25.292929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34136 12:34:25.333537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34137 12:34:25.333990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34139 12:34:25.373374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34140 12:34:25.373815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34142 12:34:25.423987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34143 12:34:25.424436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34145 12:34:25.477071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34146 12:34:25.477513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34148 12:34:25.520065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34149 12:34:25.520522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34151 12:34:25.561498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34153 12:34:25.561988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34154 12:34:25.604979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34156 12:34:25.605410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34157 12:34:25.657679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34159 12:34:25.658145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34160 12:34:25.697927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34162 12:34:25.698424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34163 12:34:25.736341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34165 12:34:25.736813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34166 12:34:25.773698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34167 12:34:25.774127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34169 12:34:25.821241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34170 12:34:25.821689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34172 12:34:25.871946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34173 12:34:25.872380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34175 12:34:25.917810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34176 12:34:25.918274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34178 12:34:25.973267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34179 12:34:25.973686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34181 12:34:26.030571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34182 12:34:26.030961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34184 12:34:26.087892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34186 12:34:26.088378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34187 12:34:26.142821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34188 12:34:26.143317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34190 12:34:26.189810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34192 12:34:26.190238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34193 12:34:26.233190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34194 12:34:26.233645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34196 12:34:26.286403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34197 12:34:26.286962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34199 12:34:26.346560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34200 12:34:26.347072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34202 12:34:26.397810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34204 12:34:26.398285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34205 12:34:26.434888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34206 12:34:26.435346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34208 12:34:26.491622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34209 12:34:26.492161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34211 12:34:26.543726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34212 12:34:26.544189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34214 12:34:26.591182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34215 12:34:26.591693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34217 12:34:26.640405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34219 12:34:26.640840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34220 12:34:26.698235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34222 12:34:26.698838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34223 12:34:26.754912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34224 12:34:26.755351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34226 12:34:26.801193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34227 12:34:26.801764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34229 12:34:26.838735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34230 12:34:26.839174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34232 12:34:26.875825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34234 12:34:26.876298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34235 12:34:26.917990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34236 12:34:26.918383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34238 12:34:26.958505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34240 12:34:26.959211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34241 12:34:27.006706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34242 12:34:27.007184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34244 12:34:27.059224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34245 12:34:27.059765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34247 12:34:27.105765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34248 12:34:27.106220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34250 12:34:27.159378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34251 12:34:27.159817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34253 12:34:27.198426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34255 12:34:27.198897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34256 12:34:27.238549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34257 12:34:27.238995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34259 12:34:27.276992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34261 12:34:27.277378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34262 12:34:27.315725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34263 12:34:27.316162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34265 12:34:27.358674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34266 12:34:27.359111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34268 12:34:27.395674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34269 12:34:27.396111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34271 12:34:27.434656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34272 12:34:27.435247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34274 12:34:27.487859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34275 12:34:27.488352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34277 12:34:27.544194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34279 12:34:27.544769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34280 12:34:27.583636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34281 12:34:27.584197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34283 12:34:27.621522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34284 12:34:27.622090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34286 12:34:27.667076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34288 12:34:27.667573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34289 12:34:27.712609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34291 12:34:27.713202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34292 12:34:27.754851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34294 12:34:27.755505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34295 12:34:27.792121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34296 12:34:27.792558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34298 12:34:27.830124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34299 12:34:27.830513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34301 12:34:27.866688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34302 12:34:27.867149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34304 12:34:27.908399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34306 12:34:27.909088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34307 12:34:27.951415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34308 12:34:27.951828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34310 12:34:27.998752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34311 12:34:27.999187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34313 12:34:28.036457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34315 12:34:28.036928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34316 12:34:28.075018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34317 12:34:28.075406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34319 12:34:28.120001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34320 12:34:28.120392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34322 12:34:28.164891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34323 12:34:28.165332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34325 12:34:28.203628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34327 12:34:28.204381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34328 12:34:28.247564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34329 12:34:28.248081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34331 12:34:28.291954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34332 12:34:28.292514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34334 12:34:28.337616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34335 12:34:28.338066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34337 12:34:28.378297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34338 12:34:28.378691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34340 12:34:28.415295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34341 12:34:28.415690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34343 12:34:28.452402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34345 12:34:28.452870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34346 12:34:28.490951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34347 12:34:28.491444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34349 12:34:28.527543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34351 12:34:28.527933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34352 12:34:28.566667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34354 12:34:28.567455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34355 12:34:28.604606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34357 12:34:28.605088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34358 12:34:28.646731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34359 12:34:28.647164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34361 12:34:28.718770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34362 12:34:28.719236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34364 12:34:28.775301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34365 12:34:28.775811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34367 12:34:28.827130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34368 12:34:28.827527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34370 12:34:28.878781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34371 12:34:28.879221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34373 12:34:28.929579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34375 12:34:28.929973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34376 12:34:28.979791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34377 12:34:28.980367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34379 12:34:29.030656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34380 12:34:29.031063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34382 12:34:29.086473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34383 12:34:29.086907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34385 12:34:29.137587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34387 12:34:29.138032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34388 12:34:29.180414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34390 12:34:29.180852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34391 12:34:29.223407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34393 12:34:29.223882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34394 12:34:29.267118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34396 12:34:29.267572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34397 12:34:29.315663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34398 12:34:29.316092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34400 12:34:29.354997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34401 12:34:29.355448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34403 12:34:29.394245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34404 12:34:29.394684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34406 12:34:29.451892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34407 12:34:29.452327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34409 12:34:29.502344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34411 12:34:29.502833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34412 12:34:29.545412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34414 12:34:29.545907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34415 12:34:29.595031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34416 12:34:29.595611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34418 12:34:29.646849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34419 12:34:29.647381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34421 12:34:29.685543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34423 12:34:29.686005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34424 12:34:29.725796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34425 12:34:29.726311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34427 12:34:29.773061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34428 12:34:29.773541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34430 12:34:29.817375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34431 12:34:29.817959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34433 12:34:29.855253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34435 12:34:29.855965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34436 12:34:29.893963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34437 12:34:29.894418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34439 12:34:29.932010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34440 12:34:29.932413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34442 12:34:29.971043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34443 12:34:29.971469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34445 12:34:30.019223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34446 12:34:30.019594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34448 12:34:30.059481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34449 12:34:30.059918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34451 12:34:30.112986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34452 12:34:30.113439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34454 12:34:30.161631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34455 12:34:30.162134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34457 12:34:30.203168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34458 12:34:30.203716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34460 12:34:30.242241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34461 12:34:30.242712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34463 12:34:30.281138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34465 12:34:30.281740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34466 12:34:30.326486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34468 12:34:30.327079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34469 12:34:30.370568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34470 12:34:30.371014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34472 12:34:30.409838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34473 12:34:30.410316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34475 12:34:30.448073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34476 12:34:30.448539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34478 12:34:30.488441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34480 12:34:30.489065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34481 12:34:30.530097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34482 12:34:30.530490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34484 12:34:30.579511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34485 12:34:30.580070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34487 12:34:30.620145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34488 12:34:30.620537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34490 12:34:30.662627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34491 12:34:30.662994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34493 12:34:30.701941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34494 12:34:30.702429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34496 12:34:30.742352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34497 12:34:30.742838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34499 12:34:30.779872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34500 12:34:30.780303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34502 12:34:30.818829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34503 12:34:30.819219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34505 12:34:30.865803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34506 12:34:30.866254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34508 12:34:30.916209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34509 12:34:30.916671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34511 12:34:30.962204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34512 12:34:30.962673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34514 12:34:31.002330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34515 12:34:31.002790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34517 12:34:31.042174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34518 12:34:31.042587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34520 12:34:31.081910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34521 12:34:31.082345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34523 12:34:31.138814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34524 12:34:31.139256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34526 12:34:31.178594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34527 12:34:31.179034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34529 12:34:31.217256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34530 12:34:31.217719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34532 12:34:31.267584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34534 12:34:31.268018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34535 12:34:31.317370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34536 12:34:31.317976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34538 12:34:31.353751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34539 12:34:31.354204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34541 12:34:31.394836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34542 12:34:31.395337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34544 12:34:31.445062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34545 12:34:31.445516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34547 12:34:31.490137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34548 12:34:31.490575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34550 12:34:31.533364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34551 12:34:31.533765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34553 12:34:31.577933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34554 12:34:31.578368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34556 12:34:31.622905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34557 12:34:31.623313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34559 12:34:31.662495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34561 12:34:31.662942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34562 12:34:31.703024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34563 12:34:31.703447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34565 12:34:31.742586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34566 12:34:31.743021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34568 12:34:31.784166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34570 12:34:31.784652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34571 12:34:31.823667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34573 12:34:31.824137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34574 12:34:31.860493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34576 12:34:31.861237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34577 12:34:31.898308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34578 12:34:31.898727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34580 12:34:31.947273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34582 12:34:31.947742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34583 12:34:32.001789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34584 12:34:32.002233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34586 12:34:32.059810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34587 12:34:32.060363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34589 12:34:32.102549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34591 12:34:32.102957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34592 12:34:32.141053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34593 12:34:32.141480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34595 12:34:32.179569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34596 12:34:32.179996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34598 12:34:32.218326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34599 12:34:32.218770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34601 12:34:32.257102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34602 12:34:32.257512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34604 12:34:32.295293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34606 12:34:32.295760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34607 12:34:32.337818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34609 12:34:32.338279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34610 12:34:32.381902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34611 12:34:32.382346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34613 12:34:32.421728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34614 12:34:32.422146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34616 12:34:32.473072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34617 12:34:32.473664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34619 12:34:32.526741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34620 12:34:32.527154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34622 12:34:32.573458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34623 12:34:32.573912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34625 12:34:32.618898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34627 12:34:32.619564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34628 12:34:32.667887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34630 12:34:32.668365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34631 12:34:32.724493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34633 12:34:32.724960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34634 12:34:32.761567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34635 12:34:32.762039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34637 12:34:32.808838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34638 12:34:32.809289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34640 12:34:32.847588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34641 12:34:32.848022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34643 12:34:32.886881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34644 12:34:32.887330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34646 12:34:32.936006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34648 12:34:32.936585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34649 12:34:32.982723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34651 12:34:32.983195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34652 12:34:33.023024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34653 12:34:33.023421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34655 12:34:33.070195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34656 12:34:33.070605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34658 12:34:33.123966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34659 12:34:33.124544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34661 12:34:33.162374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34662 12:34:33.162886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34664 12:34:33.198847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34665 12:34:33.199338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34667 12:34:33.235281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34668 12:34:33.235778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34670 12:34:33.277620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34671 12:34:33.278158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34673 12:34:33.322372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34674 12:34:33.322882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34676 12:34:33.364729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34678 12:34:33.365185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34679 12:34:33.369116 + set +x
34680 12:34:33.369515 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 568844_1.1.3.5>
34681 12:34:33.369820 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 568844_1.1.3.5
34682 12:34:33.369936 Ending use of test pattern.
34683 12:34:33.370035 Ending test lava.1_kselftest-arm64_qemu (568844_1.1.3.5), duration 399.69
34685 12:34:33.374736 <LAVA_TEST_RUNNER EXIT>
34686 12:34:33.375169 ok: lava_test_shell seems to have completed
34687 12:34:33.449386 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34688 12:34:33.452763 end: 3.1 lava-test-shell (duration 00:06:41) [common]
34689 12:34:33.452920 end: 3 lava-test-retry (duration 00:06:41) [common]
34690 12:34:33.453034 start: 4 finalize (timeout 00:02:06) [common]
34691 12:34:33.453141 start: 4.1 power-off (timeout 00:00:30) [common]
34692 12:34:33.453242 end: 4.1 power-off (duration 00:00:00) [common]
34693 12:34:33.453340 start: 4.2 read-feedback (timeout 00:02:06) [common]
34694 12:34:33.453542 Listened to connection for namespace 'common' for up to 1s
34695 12:34:33.453851 Listened to connection for namespace 'common' for up to 1s
34696 12:34:34.457781 Finalising connection for namespace 'common'
34698 12:34:34.558792 / # poweroff
34699 12:34:34.559339 Already disconnected
34700 12:34:34.559465 poweroff
34701 12:34:34.961657 end: 4.2 read-feedback (duration 00:00:02) [common]
34702 12:34:34.961907 Already disconnected
34703 12:34:34.962029 end: 4 finalize (duration 00:00:02) [common]
34704 12:34:34.962173 Cleaning after the job
34705 12:34:34.962337 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/568844/deployimages-r4n_h3ap/kernel
34706 12:34:34.970195 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/568844/deployimages-r4n_h3ap/ramdisk
34707 12:34:34.986079 Stopping the qemu container lava-docker-qemu-568844-2.1.1-huisqkbmbp
34708 12:34:35.646114 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/568844
34709 12:34:35.731128 Job finished correctly