Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 12:13:41.477774 lava-dispatcher, installed at version: 2023.05.1
2 12:13:41.478039 start: 0 validate
3 12:13:41.478220 Start time: 2023-06-06 12:13:41.478211+00:00 (UTC)
4 12:13:41.478397 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:13:41.478584 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:13:41.775705 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:13:41.775893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:13:42.063888 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:13:42.064081 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:13:42.355408 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:13:42.355592 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:13:42.643400 validate duration: 1.17
14 12:13:42.643685 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:13:42.643815 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:13:42.643922 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:13:42.644043 Not decompressing ramdisk as can be used compressed.
18 12:13:42.644132 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 12:13:42.644200 saving as /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/ramdisk/rootfs.cpio.gz
20 12:13:42.644289 total size: 43394293 (41MB)
21 12:13:42.645428 progress 0% (0MB)
22 12:13:42.657114 progress 5% (2MB)
23 12:13:42.668461 progress 10% (4MB)
24 12:13:42.680558 progress 15% (6MB)
25 12:13:42.693282 progress 20% (8MB)
26 12:13:42.705732 progress 25% (10MB)
27 12:13:42.717215 progress 30% (12MB)
28 12:13:42.728345 progress 35% (14MB)
29 12:13:42.739506 progress 40% (16MB)
30 12:13:42.750616 progress 45% (18MB)
31 12:13:42.762122 progress 50% (20MB)
32 12:13:42.773285 progress 55% (22MB)
33 12:13:42.784563 progress 60% (24MB)
34 12:13:42.795899 progress 65% (26MB)
35 12:13:42.807251 progress 70% (29MB)
36 12:13:42.818544 progress 75% (31MB)
37 12:13:42.829654 progress 80% (33MB)
38 12:13:42.840675 progress 85% (35MB)
39 12:13:42.851715 progress 90% (37MB)
40 12:13:42.862837 progress 95% (39MB)
41 12:13:42.873858 progress 100% (41MB)
42 12:13:42.874021 41MB downloaded in 0.23s (180.14MB/s)
43 12:13:42.874185 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:13:42.874435 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:13:42.874529 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:13:42.874616 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:13:42.874751 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:13:42.874827 saving as /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/kernel/Image
50 12:13:42.874892 total size: 45746688 (43MB)
51 12:13:42.874955 No compression specified
52 12:13:42.876065 progress 0% (0MB)
53 12:13:42.887794 progress 5% (2MB)
54 12:13:42.899557 progress 10% (4MB)
55 12:13:42.911304 progress 15% (6MB)
56 12:13:42.924199 progress 20% (8MB)
57 12:13:42.936497 progress 25% (10MB)
58 12:13:42.948295 progress 30% (13MB)
59 12:13:42.960606 progress 35% (15MB)
60 12:13:42.972784 progress 40% (17MB)
61 12:13:42.985566 progress 45% (19MB)
62 12:13:42.998174 progress 50% (21MB)
63 12:13:43.010208 progress 55% (24MB)
64 12:13:43.022007 progress 60% (26MB)
65 12:13:43.033773 progress 65% (28MB)
66 12:13:43.045546 progress 70% (30MB)
67 12:13:43.057279 progress 75% (32MB)
68 12:13:43.068949 progress 80% (34MB)
69 12:13:43.080698 progress 85% (37MB)
70 12:13:43.092648 progress 90% (39MB)
71 12:13:43.104346 progress 95% (41MB)
72 12:13:43.115977 progress 100% (43MB)
73 12:13:43.116141 43MB downloaded in 0.24s (180.84MB/s)
74 12:13:43.116303 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:13:43.116543 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:13:43.116633 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:13:43.116721 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:13:43.116856 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:13:43.116936 saving as /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/dtb/mt8192-asurada-spherion-r0.dtb
81 12:13:43.117001 total size: 46924 (0MB)
82 12:13:43.117063 No compression specified
83 12:13:43.118256 progress 69% (0MB)
84 12:13:43.118534 progress 100% (0MB)
85 12:13:43.118690 0MB downloaded in 0.00s (26.53MB/s)
86 12:13:43.118816 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:13:43.119043 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:13:43.119132 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:13:43.119220 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:13:43.119334 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:13:43.119417 saving as /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/modules/modules.tar
93 12:13:43.119481 total size: 8553528 (8MB)
94 12:13:43.119544 Using unxz to decompress xz
95 12:13:43.123037 progress 0% (0MB)
96 12:13:43.144390 progress 5% (0MB)
97 12:13:43.169110 progress 10% (0MB)
98 12:13:43.200107 progress 15% (1MB)
99 12:13:43.226133 progress 20% (1MB)
100 12:13:43.251024 progress 25% (2MB)
101 12:13:43.275815 progress 30% (2MB)
102 12:13:43.301711 progress 35% (2MB)
103 12:13:43.326492 progress 40% (3MB)
104 12:13:43.351850 progress 45% (3MB)
105 12:13:43.376667 progress 50% (4MB)
106 12:13:43.401024 progress 55% (4MB)
107 12:13:43.426244 progress 60% (4MB)
108 12:13:43.450977 progress 65% (5MB)
109 12:13:43.478529 progress 70% (5MB)
110 12:13:43.503336 progress 75% (6MB)
111 12:13:43.530792 progress 80% (6MB)
112 12:13:43.555739 progress 85% (6MB)
113 12:13:43.580296 progress 90% (7MB)
114 12:13:43.603634 progress 95% (7MB)
115 12:13:43.629714 progress 100% (8MB)
116 12:13:43.634368 8MB downloaded in 0.51s (15.84MB/s)
117 12:13:43.634718 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:13:43.635130 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:13:43.635244 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:13:43.635393 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:13:43.635496 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:13:43.635629 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:13:43.635874 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv
125 12:13:43.636054 makedir: /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin
126 12:13:43.636201 makedir: /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/tests
127 12:13:43.636342 makedir: /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/results
128 12:13:43.636473 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-add-keys
129 12:13:43.636639 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-add-sources
130 12:13:43.636788 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-background-process-start
131 12:13:43.636942 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-background-process-stop
132 12:13:43.637090 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-common-functions
133 12:13:43.637263 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-echo-ipv4
134 12:13:43.637436 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-install-packages
135 12:13:43.637612 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-installed-packages
136 12:13:43.637758 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-os-build
137 12:13:43.637903 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-probe-channel
138 12:13:43.638048 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-probe-ip
139 12:13:43.638192 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-target-ip
140 12:13:43.638340 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-target-mac
141 12:13:43.638487 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-target-storage
142 12:13:43.638664 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-case
143 12:13:43.638837 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-event
144 12:13:43.639006 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-feedback
145 12:13:43.639150 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-raise
146 12:13:43.639300 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-reference
147 12:13:43.639485 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-runner
148 12:13:43.639631 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-set
149 12:13:43.639776 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-test-shell
150 12:13:43.639927 Updating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-install-packages (oe)
151 12:13:43.640725 Updating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/bin/lava-installed-packages (oe)
152 12:13:43.640893 Creating /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/environment
153 12:13:43.641011 LAVA metadata
154 12:13:43.641101 - LAVA_JOB_ID=10605408
155 12:13:43.641211 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:13:43.641374 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:13:43.641478 skipped lava-vland-overlay
158 12:13:43.641588 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:13:43.641693 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:13:43.641774 skipped lava-multinode-overlay
161 12:13:43.641880 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:13:43.641994 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:13:43.642111 Loading test definitions
164 12:13:43.642251 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:13:43.642365 Using /lava-10605408 at stage 0
166 12:13:43.642804 uuid=10605408_1.5.2.3.1 testdef=None
167 12:13:43.642932 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:13:43.643061 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:13:43.643811 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:13:43.644096 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:13:43.644881 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:13:43.645150 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:13:43.646359 runner path: /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/0/tests/0_igt-gpu-panfrost test_uuid 10605408_1.5.2.3.1
176 12:13:43.646531 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:13:43.646770 Creating lava-test-runner.conf files
179 12:13:43.646879 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605408/lava-overlay-a5mo40xv/lava-10605408/0 for stage 0
180 12:13:43.647019 - 0_igt-gpu-panfrost
181 12:13:43.647159 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:13:43.647294 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:13:43.654013 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:13:43.654143 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:13:43.654253 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:13:43.654386 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:13:43.654523 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:13:45.020219 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:13:45.020638 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:13:45.020786 extracting modules file /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605408/extract-overlay-ramdisk-i7rv8l3m/ramdisk
191 12:13:45.248287 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:13:45.248471 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:13:45.248583 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605408/compress-overlay-i37qh9vs/overlay-1.5.2.4.tar.gz to ramdisk
194 12:13:45.248661 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605408/compress-overlay-i37qh9vs/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605408/extract-overlay-ramdisk-i7rv8l3m/ramdisk
195 12:13:45.255538 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:13:45.255669 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:13:45.255778 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:13:45.255876 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:13:45.255968 Building ramdisk /var/lib/lava/dispatcher/tmp/10605408/extract-overlay-ramdisk-i7rv8l3m/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605408/extract-overlay-ramdisk-i7rv8l3m/ramdisk
200 12:13:46.177204 >> 369045 blocks
201 12:13:52.220947 rename /var/lib/lava/dispatcher/tmp/10605408/extract-overlay-ramdisk-i7rv8l3m/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/ramdisk/ramdisk.cpio.gz
202 12:13:52.221374 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:13:52.221500 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 12:13:52.221607 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 12:13:52.221719 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/kernel/Image'
206 12:14:04.732585 Returned 0 in 12 seconds
207 12:14:04.833202 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/kernel/image.itb
208 12:14:05.584977 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:14:05.585347 output: Created: Tue Jun 6 13:14:05 2023
210 12:14:05.585430 output: Image 0 (kernel-1)
211 12:14:05.585503 output: Description:
212 12:14:05.585571 output: Created: Tue Jun 6 13:14:05 2023
213 12:14:05.585640 output: Type: Kernel Image
214 12:14:05.585710 output: Compression: lzma compressed
215 12:14:05.585772 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
216 12:14:05.585834 output: Architecture: AArch64
217 12:14:05.585897 output: OS: Linux
218 12:14:05.585961 output: Load Address: 0x00000000
219 12:14:05.586023 output: Entry Point: 0x00000000
220 12:14:05.586086 output: Hash algo: crc32
221 12:14:05.586148 output: Hash value: fd97082e
222 12:14:05.586205 output: Image 1 (fdt-1)
223 12:14:05.586265 output: Description: mt8192-asurada-spherion-r0
224 12:14:05.586323 output: Created: Tue Jun 6 13:14:05 2023
225 12:14:05.586379 output: Type: Flat Device Tree
226 12:14:05.586437 output: Compression: uncompressed
227 12:14:05.586496 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:14:05.586555 output: Architecture: AArch64
229 12:14:05.586612 output: Hash algo: crc32
230 12:14:05.586666 output: Hash value: 1df858fa
231 12:14:05.586721 output: Image 2 (ramdisk-1)
232 12:14:05.586778 output: Description: unavailable
233 12:14:05.586846 output: Created: Tue Jun 6 13:14:05 2023
234 12:14:05.586906 output: Type: RAMDisk Image
235 12:14:05.586965 output: Compression: Unknown Compression
236 12:14:05.587023 output: Data Size: 56379964 Bytes = 55058.56 KiB = 53.77 MiB
237 12:14:05.587082 output: Architecture: AArch64
238 12:14:05.587140 output: OS: Linux
239 12:14:05.587197 output: Load Address: unavailable
240 12:14:05.587253 output: Entry Point: unavailable
241 12:14:05.587308 output: Hash algo: crc32
242 12:14:05.587371 output: Hash value: c46df310
243 12:14:05.587432 output: Default Configuration: 'conf-1'
244 12:14:05.587497 output: Configuration 0 (conf-1)
245 12:14:05.587554 output: Description: mt8192-asurada-spherion-r0
246 12:14:05.587623 output: Kernel: kernel-1
247 12:14:05.587678 output: Init Ramdisk: ramdisk-1
248 12:14:05.587732 output: FDT: fdt-1
249 12:14:05.587796 output: Loadables: kernel-1
250 12:14:05.587852 output:
251 12:14:05.588059 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:14:05.588170 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:14:05.588283 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:14:05.588391 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 12:14:05.588477 No LXC device requested
256 12:14:05.588586 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:14:05.588731 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 12:14:05.588853 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:14:05.588962 Checking files for TFTP limit of 4294967296 bytes.
260 12:14:05.589495 end: 1 tftp-deploy (duration 00:00:23) [common]
261 12:14:05.589615 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:14:05.589714 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:14:05.589849 substitutions:
264 12:14:05.589922 - {DTB}: 10605408/tftp-deploy-wio5u1tq/dtb/mt8192-asurada-spherion-r0.dtb
265 12:14:05.589992 - {INITRD}: 10605408/tftp-deploy-wio5u1tq/ramdisk/ramdisk.cpio.gz
266 12:14:05.590060 - {KERNEL}: 10605408/tftp-deploy-wio5u1tq/kernel/Image
267 12:14:05.590124 - {LAVA_MAC}: None
268 12:14:05.590184 - {PRESEED_CONFIG}: None
269 12:14:05.590242 - {PRESEED_LOCAL}: None
270 12:14:05.590299 - {RAMDISK}: 10605408/tftp-deploy-wio5u1tq/ramdisk/ramdisk.cpio.gz
271 12:14:05.590359 - {ROOT_PART}: None
272 12:14:05.590420 - {ROOT}: None
273 12:14:05.590481 - {SERVER_IP}: 192.168.201.1
274 12:14:05.590539 - {TEE}: None
275 12:14:05.590599 Parsed boot commands:
276 12:14:05.590660 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:14:05.590838 Parsed boot commands: tftpboot 192.168.201.1 10605408/tftp-deploy-wio5u1tq/kernel/image.itb 10605408/tftp-deploy-wio5u1tq/kernel/cmdline
278 12:14:05.590933 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:14:05.591027 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:14:05.591132 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:14:05.591226 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:14:05.591303 Not connected, no need to disconnect.
283 12:14:05.591415 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:14:05.591505 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:14:05.591579 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 12:14:05.594823 Setting prompt string to ['lava-test: # ']
287 12:14:05.595178 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:14:05.595295 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:14:05.595412 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:14:05.595515 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:14:05.595725 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 12:14:10.732355 >> Command sent successfully.
293 12:14:10.734654 Returned 0 in 5 seconds
294 12:14:10.835062 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:14:10.835763 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:14:10.835878 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:14:10.835977 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:14:10.836058 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:14:10.836150 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:14:10.836419 [Enter `^Ec?' for help]
302 12:14:11.010304
303 12:14:11.010494
304 12:14:11.010574 F0: 102B 0000
305 12:14:11.010642
306 12:14:11.010733 F3: 1001 0000 [0200]
307 12:14:11.010852
308 12:14:11.013600 F3: 1001 0000
309 12:14:11.013717
310 12:14:11.013816 F7: 102D 0000
311 12:14:11.013937
312 12:14:11.016857 F1: 0000 0000
313 12:14:11.016986
314 12:14:11.017089 V0: 0000 0000 [0001]
315 12:14:11.017183
316 12:14:11.020282 00: 0007 8000
317 12:14:11.020384
318 12:14:11.020454 01: 0000 0000
319 12:14:11.020523
320 12:14:11.023512 BP: 0C00 0209 [0000]
321 12:14:11.023591
322 12:14:11.023656 G0: 1182 0000
323 12:14:11.023717
324 12:14:11.023791 EC: 0000 0021 [4000]
325 12:14:11.027433
326 12:14:11.027544 S7: 0000 0000 [0000]
327 12:14:11.027639
328 12:14:11.030693 CC: 0000 0000 [0001]
329 12:14:11.030804
330 12:14:11.030876 T0: 0000 0040 [010F]
331 12:14:11.030941
332 12:14:11.031010 Jump to BL
333 12:14:11.031078
334 12:14:11.056819
335 12:14:11.056948
336 12:14:11.057019
337 12:14:11.064042 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:14:11.067265 ARM64: Exception handlers installed.
339 12:14:11.071213 ARM64: Testing exception
340 12:14:11.074261 ARM64: Done test exception
341 12:14:11.080849 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:14:11.091801 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:14:11.098158 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:14:11.108120 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:14:11.114588 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:14:11.124623 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:14:11.135205 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:14:11.141924 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:14:11.160357 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:14:11.163604 WDT: Last reset was cold boot
351 12:14:11.166834 SPI1(PAD0) initialized at 2873684 Hz
352 12:14:11.170098 SPI5(PAD0) initialized at 992727 Hz
353 12:14:11.173413 VBOOT: Loading verstage.
354 12:14:11.179864 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:14:11.183135 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:14:11.186964 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:14:11.189981 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:14:11.197820 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:14:11.204207 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:14:11.214716 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:14:11.214799
362 12:14:11.214868
363 12:14:11.225171 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:14:11.228499 ARM64: Exception handlers installed.
365 12:14:11.231860 ARM64: Testing exception
366 12:14:11.231946 ARM64: Done test exception
367 12:14:11.238306 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:14:11.241488 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:14:11.257305 Probing TPM: . done!
370 12:14:11.257435 TPM ready after 0 ms
371 12:14:11.263987 Connected to device vid:did:rid of 1ae0:0028:00
372 12:14:11.270641 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:14:11.329278 Initialized TPM device CR50 revision 0
374 12:14:11.340620 tlcl_send_startup: Startup return code is 0
375 12:14:11.340738 TPM: setup succeeded
376 12:14:11.352631 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:14:11.360869 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:14:11.373576 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:14:11.383266 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:14:11.386605 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:14:11.390455 in-header: 03 07 00 00 08 00 00 00
382 12:14:11.394100 in-data: aa e4 47 04 13 02 00 00
383 12:14:11.397899 Chrome EC: UHEPI supported
384 12:14:11.405005 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:14:11.408810 in-header: 03 ad 00 00 08 00 00 00
386 12:14:11.412656 in-data: 00 20 20 08 00 00 00 00
387 12:14:11.412762 Phase 1
388 12:14:11.415842 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:14:11.423871 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:14:11.427232 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:14:11.431251 Recovery requested (1009000e)
392 12:14:11.439781 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:14:11.445694 tlcl_extend: response is 0
394 12:14:11.455676 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:14:11.461519 tlcl_extend: response is 0
396 12:14:11.468828 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:14:11.488796 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:14:11.495223 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:14:11.495343
400 12:14:11.495455
401 12:14:11.505330 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:14:11.509172 ARM64: Exception handlers installed.
403 12:14:11.509294 ARM64: Testing exception
404 12:14:11.513075 ARM64: Done test exception
405 12:14:11.534690 pmic_efuse_setting: Set efuses in 11 msecs
406 12:14:11.537915 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:14:11.544505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:14:11.547788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:14:11.554486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:14:11.557883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:14:11.561943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:14:11.569389 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:14:11.572753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:14:11.576775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:14:11.580676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:14:11.587946 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:14:11.591290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:14:11.595290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:14:11.598613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:14:11.605972 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:14:11.613875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:14:11.617135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:14:11.624237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:14:11.628192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:14:11.634928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:14:11.638911 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:14:11.646376 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:14:11.649668 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:14:11.657133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:14:11.660997 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:14:11.668340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:14:11.672274 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:14:11.679567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:14:11.682887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:14:11.686811 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:14:11.694161 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:14:11.696860 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:14:11.704307 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:14:11.708263 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:14:11.711707 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:14:11.719107 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:14:11.722891 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:14:11.726812 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:14:11.733970 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:14:11.737384 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:14:11.741274 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:14:11.745171 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:14:11.752504 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:14:11.756513 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:14:11.759951 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:14:11.763918 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:14:11.767323 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:14:11.771333 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:14:11.778041 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:14:11.781513 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:14:11.785436 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:14:11.789424 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:14:11.796788 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:14:11.804018 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:14:11.811301 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:14:11.818581 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:14:11.825545 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:14:11.829455 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:14:11.836690 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:14:11.840178 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:14:11.847415 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
467 12:14:11.851317 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:14:11.858618 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:14:11.861989 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:14:11.871270 [RTC]rtc_get_frequency_meter,154: input=15, output=791
471 12:14:11.880621 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 12:14:11.890040 [RTC]rtc_get_frequency_meter,154: input=19, output=883
473 12:14:11.900029 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 12:14:11.909876 [RTC]rtc_get_frequency_meter,154: input=16, output=812
475 12:14:11.919120 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 12:14:11.929382 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 12:14:11.933013 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 12:14:11.936883 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 12:14:11.940708 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:14:11.947980 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:14:11.952000 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:14:11.955154 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:14:11.958901 ADC[4]: Raw value=900959 ID=7
484 12:14:11.958990 ADC[3]: Raw value=213336 ID=1
485 12:14:11.962931 RAM Code: 0x71
486 12:14:11.966193 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:14:11.970183 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:14:11.981328 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:14:11.985265 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:14:11.989154 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:14:11.992337 in-header: 03 07 00 00 08 00 00 00
492 12:14:11.996456 in-data: aa e4 47 04 13 02 00 00
493 12:14:11.999644 Chrome EC: UHEPI supported
494 12:14:12.006920 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:14:12.010800 in-header: 03 ed 00 00 08 00 00 00
496 12:14:12.010885 in-data: 80 20 60 08 00 00 00 00
497 12:14:12.014797 MRC: failed to locate region type 0.
498 12:14:12.022109 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:14:12.025930 DRAM-K: Running full calibration
500 12:14:12.032852 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:14:12.032942 header.status = 0x0
502 12:14:12.036701 header.version = 0x6 (expected: 0x6)
503 12:14:12.040476 header.size = 0xd00 (expected: 0xd00)
504 12:14:12.040560 header.flags = 0x0
505 12:14:12.048071 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:14:12.065157 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 12:14:12.072625 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:14:12.075908 dram_init: ddr_geometry: 2
509 12:14:12.076013 [EMI] MDL number = 2
510 12:14:12.079847 [EMI] Get MDL freq = 0
511 12:14:12.079949 dram_init: ddr_type: 0
512 12:14:12.083767 is_discrete_lpddr4: 1
513 12:14:12.087069 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:14:12.087176
515 12:14:12.087273
516 12:14:12.091015 [Bian_co] ETT version 0.0.0.1
517 12:14:12.094991 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:14:12.095095
519 12:14:12.098288 dramc_set_vcore_voltage set vcore to 650000
520 12:14:12.101684 Read voltage for 800, 4
521 12:14:12.101793 Vio18 = 0
522 12:14:12.101889 Vcore = 650000
523 12:14:12.101981 Vdram = 0
524 12:14:12.105608 Vddq = 0
525 12:14:12.105711 Vmddr = 0
526 12:14:12.108869 dram_init: config_dvfs: 1
527 12:14:12.112774 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:14:12.119558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:14:12.122725 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 12:14:12.125990 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 12:14:12.129324 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 12:14:12.133240 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 12:14:12.135785 MEM_TYPE=3, freq_sel=18
534 12:14:12.139594 sv_algorithm_assistance_LP4_1600
535 12:14:12.142675 ============ PULL DRAM RESETB DOWN ============
536 12:14:12.146046 ========== PULL DRAM RESETB DOWN end =========
537 12:14:12.152946 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:14:12.156255 ===================================
539 12:14:12.156344 LPDDR4 DRAM CONFIGURATION
540 12:14:12.159285 ===================================
541 12:14:12.162513 EX_ROW_EN[0] = 0x0
542 12:14:12.162600 EX_ROW_EN[1] = 0x0
543 12:14:12.165866 LP4Y_EN = 0x0
544 12:14:12.169062 WORK_FSP = 0x0
545 12:14:12.169149 WL = 0x2
546 12:14:12.172366 RL = 0x2
547 12:14:12.172452 BL = 0x2
548 12:14:12.175709 RPST = 0x0
549 12:14:12.175796 RD_PRE = 0x0
550 12:14:12.179102 WR_PRE = 0x1
551 12:14:12.179188 WR_PST = 0x0
552 12:14:12.182945 DBI_WR = 0x0
553 12:14:12.183031 DBI_RD = 0x0
554 12:14:12.185666 OTF = 0x1
555 12:14:12.189681 ===================================
556 12:14:12.192957 ===================================
557 12:14:12.193043 ANA top config
558 12:14:12.196238 ===================================
559 12:14:12.199584 DLL_ASYNC_EN = 0
560 12:14:12.202875 ALL_SLAVE_EN = 1
561 12:14:12.202974 NEW_RANK_MODE = 1
562 12:14:12.206219 DLL_IDLE_MODE = 1
563 12:14:12.209488 LP45_APHY_COMB_EN = 1
564 12:14:12.212694 TX_ODT_DIS = 1
565 12:14:12.212825 NEW_8X_MODE = 1
566 12:14:12.216035 ===================================
567 12:14:12.219244 ===================================
568 12:14:12.222561 data_rate = 1600
569 12:14:12.225808 CKR = 1
570 12:14:12.229131 DQ_P2S_RATIO = 8
571 12:14:12.232552 ===================================
572 12:14:12.235903 CA_P2S_RATIO = 8
573 12:14:12.239752 DQ_CA_OPEN = 0
574 12:14:12.239832 DQ_SEMI_OPEN = 0
575 12:14:12.242946 CA_SEMI_OPEN = 0
576 12:14:12.246192 CA_FULL_RATE = 0
577 12:14:12.249430 DQ_CKDIV4_EN = 1
578 12:14:12.252803 CA_CKDIV4_EN = 1
579 12:14:12.255939 CA_PREDIV_EN = 0
580 12:14:12.256030 PH8_DLY = 0
581 12:14:12.259841 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:14:12.263084 DQ_AAMCK_DIV = 4
583 12:14:12.266432 CA_AAMCK_DIV = 4
584 12:14:12.269511 CA_ADMCK_DIV = 4
585 12:14:12.269630 DQ_TRACK_CA_EN = 0
586 12:14:12.272912 CA_PICK = 800
587 12:14:12.276256 CA_MCKIO = 800
588 12:14:12.279716 MCKIO_SEMI = 0
589 12:14:12.282911 PLL_FREQ = 3068
590 12:14:12.286889 DQ_UI_PI_RATIO = 32
591 12:14:12.286966 CA_UI_PI_RATIO = 0
592 12:14:12.290327 ===================================
593 12:14:12.294265 ===================================
594 12:14:12.298321 memory_type:LPDDR4
595 12:14:12.298449 GP_NUM : 10
596 12:14:12.301628 SRAM_EN : 1
597 12:14:12.304987 MD32_EN : 0
598 12:14:12.305109 ===================================
599 12:14:12.308957 [ANA_INIT] >>>>>>>>>>>>>>
600 12:14:12.312283 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:14:12.316312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:14:12.319649 ===================================
603 12:14:12.323015 data_rate = 1600,PCW = 0X7600
604 12:14:12.326284 ===================================
605 12:14:12.329711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:14:12.333144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:14:12.339665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:14:12.342946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:14:12.346272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:14:12.349553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:14:12.352857 [ANA_INIT] flow start
612 12:14:12.356030 [ANA_INIT] PLL >>>>>>>>
613 12:14:12.356113 [ANA_INIT] PLL <<<<<<<<
614 12:14:12.359328 [ANA_INIT] MIDPI >>>>>>>>
615 12:14:12.363108 [ANA_INIT] MIDPI <<<<<<<<
616 12:14:12.363211 [ANA_INIT] DLL >>>>>>>>
617 12:14:12.366413 [ANA_INIT] flow end
618 12:14:12.369715 ============ LP4 DIFF to SE enter ============
619 12:14:12.372947 ============ LP4 DIFF to SE exit ============
620 12:14:12.376568 [ANA_INIT] <<<<<<<<<<<<<
621 12:14:12.379658 [Flow] Enable top DCM control >>>>>
622 12:14:12.383056 [Flow] Enable top DCM control <<<<<
623 12:14:12.386276 Enable DLL master slave shuffle
624 12:14:12.392961 ==============================================================
625 12:14:12.393066 Gating Mode config
626 12:14:12.399787 ==============================================================
627 12:14:12.399890 Config description:
628 12:14:12.409700 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:14:12.416509 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:14:12.423147 SELPH_MODE 0: By rank 1: By Phase
631 12:14:12.426537 ==============================================================
632 12:14:12.429819 GAT_TRACK_EN = 1
633 12:14:12.433072 RX_GATING_MODE = 2
634 12:14:12.436434 RX_GATING_TRACK_MODE = 2
635 12:14:12.439752 SELPH_MODE = 1
636 12:14:12.443055 PICG_EARLY_EN = 1
637 12:14:12.446260 VALID_LAT_VALUE = 1
638 12:14:12.449433 ==============================================================
639 12:14:12.453347 Enter into Gating configuration >>>>
640 12:14:12.456560 Exit from Gating configuration <<<<
641 12:14:12.459812 Enter into DVFS_PRE_config >>>>>
642 12:14:12.473213 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:14:12.476657 Exit from DVFS_PRE_config <<<<<
644 12:14:12.479974 Enter into PICG configuration >>>>
645 12:14:12.480096 Exit from PICG configuration <<<<
646 12:14:12.483291 [RX_INPUT] configuration >>>>>
647 12:14:12.486730 [RX_INPUT] configuration <<<<<
648 12:14:12.493172 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:14:12.496530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:14:12.503998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:14:12.510674 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:14:12.517336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:14:12.523934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:14:12.527215 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:14:12.530478 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:14:12.533829 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:14:12.537067 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:14:12.543690 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:14:12.547657 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:14:12.551019 ===================================
661 12:14:12.554249 LPDDR4 DRAM CONFIGURATION
662 12:14:12.557367 ===================================
663 12:14:12.557489 EX_ROW_EN[0] = 0x0
664 12:14:12.560703 EX_ROW_EN[1] = 0x0
665 12:14:12.560786 LP4Y_EN = 0x0
666 12:14:12.563981 WORK_FSP = 0x0
667 12:14:12.564066 WL = 0x2
668 12:14:12.567859 RL = 0x2
669 12:14:12.567954 BL = 0x2
670 12:14:12.570506 RPST = 0x0
671 12:14:12.570607 RD_PRE = 0x0
672 12:14:12.574336 WR_PRE = 0x1
673 12:14:12.574449 WR_PST = 0x0
674 12:14:12.577613 DBI_WR = 0x0
675 12:14:12.577717 DBI_RD = 0x0
676 12:14:12.581004 OTF = 0x1
677 12:14:12.584280 ===================================
678 12:14:12.587671 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:14:12.590885 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:14:12.597677 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:14:12.600963 ===================================
682 12:14:12.601042 LPDDR4 DRAM CONFIGURATION
683 12:14:12.604294 ===================================
684 12:14:12.607662 EX_ROW_EN[0] = 0x10
685 12:14:12.611001 EX_ROW_EN[1] = 0x0
686 12:14:12.611113 LP4Y_EN = 0x0
687 12:14:12.614182 WORK_FSP = 0x0
688 12:14:12.614286 WL = 0x2
689 12:14:12.617464 RL = 0x2
690 12:14:12.617579 BL = 0x2
691 12:14:12.620614 RPST = 0x0
692 12:14:12.620689 RD_PRE = 0x0
693 12:14:12.623999 WR_PRE = 0x1
694 12:14:12.624083 WR_PST = 0x0
695 12:14:12.627249 DBI_WR = 0x0
696 12:14:12.627328 DBI_RD = 0x0
697 12:14:12.630651 OTF = 0x1
698 12:14:12.633896 ===================================
699 12:14:12.640477 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:14:12.644430 nWR fixed to 40
701 12:14:12.647032 [ModeRegInit_LP4] CH0 RK0
702 12:14:12.647143 [ModeRegInit_LP4] CH0 RK1
703 12:14:12.651011 [ModeRegInit_LP4] CH1 RK0
704 12:14:12.654344 [ModeRegInit_LP4] CH1 RK1
705 12:14:12.654424 match AC timing 13
706 12:14:12.661004 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:14:12.664171 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:14:12.667216 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:14:12.674171 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:14:12.677322 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:14:12.677403 [EMI DOE] emi_dcm 0
712 12:14:12.683758 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:14:12.683869 ==
714 12:14:12.687712 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:14:12.690931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:14:12.691024 ==
717 12:14:12.697584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:14:12.700811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:14:12.710935 [CA 0] Center 37 (7~68) winsize 62
720 12:14:12.714154 [CA 1] Center 37 (6~68) winsize 63
721 12:14:12.717639 [CA 2] Center 35 (5~66) winsize 62
722 12:14:12.720908 [CA 3] Center 34 (4~65) winsize 62
723 12:14:12.724250 [CA 4] Center 34 (3~65) winsize 63
724 12:14:12.727655 [CA 5] Center 33 (3~64) winsize 62
725 12:14:12.727772
726 12:14:12.731513 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:14:12.731629
728 12:14:12.734828 [CATrainingPosCal] consider 1 rank data
729 12:14:12.738184 u2DelayCellTimex100 = 270/100 ps
730 12:14:12.741510 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:14:12.744733 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 12:14:12.751501 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 12:14:12.754748 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:14:12.758056 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 12:14:12.761257 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:14:12.761362
737 12:14:12.764589 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:14:12.764690
739 12:14:12.767985 [CBTSetCACLKResult] CA Dly = 33
740 12:14:12.768078 CS Dly: 5 (0~36)
741 12:14:12.768172 ==
742 12:14:12.771164 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:14:12.777983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:14:12.778066 ==
745 12:14:12.781115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:14:12.788102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:14:12.797059 [CA 0] Center 37 (6~68) winsize 63
748 12:14:12.800387 [CA 1] Center 37 (6~68) winsize 63
749 12:14:12.803688 [CA 2] Center 35 (4~66) winsize 63
750 12:14:12.806943 [CA 3] Center 35 (4~66) winsize 63
751 12:14:12.810321 [CA 4] Center 34 (3~65) winsize 63
752 12:14:12.813756 [CA 5] Center 33 (3~64) winsize 62
753 12:14:12.813833
754 12:14:12.816887 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:14:12.816959
756 12:14:12.820889 [CATrainingPosCal] consider 2 rank data
757 12:14:12.824066 u2DelayCellTimex100 = 270/100 ps
758 12:14:12.827448 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:14:12.830878 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
760 12:14:12.836876 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 12:14:12.840195 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:14:12.844084 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 12:14:12.847303 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:14:12.847402
765 12:14:12.850764 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:14:12.850854
767 12:14:12.853986 [CBTSetCACLKResult] CA Dly = 33
768 12:14:12.854072 CS Dly: 6 (0~38)
769 12:14:12.854141
770 12:14:12.857195 ----->DramcWriteLeveling(PI) begin...
771 12:14:12.860650 ==
772 12:14:12.864082 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:14:12.867435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:14:12.867520 ==
775 12:14:12.871397 Write leveling (Byte 0): 29 => 29
776 12:14:12.871484 Write leveling (Byte 1): 29 => 29
777 12:14:12.874686 DramcWriteLeveling(PI) end<-----
778 12:14:12.874763
779 12:14:12.874837 ==
780 12:14:12.878755 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:14:12.884825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:14:12.884915 ==
783 12:14:12.884985 [Gating] SW mode calibration
784 12:14:12.895539 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:14:12.898708 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:14:12.902519 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:14:12.909082 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 12:14:12.912421 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 12:14:12.915693 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:14:12.922337 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:14:12.925559 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:14:12.928942 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:14:12.932180 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:14:12.938683 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:14:12.942559 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:14:12.945867 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:14:12.952589 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:14:12.955890 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:14:12.959049 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:14:12.965812 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:14:12.969071 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:14:12.972587 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:14:12.979219 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:14:12.982586 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
805 12:14:12.985793 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 12:14:12.992620 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:14:12.995824 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:14:12.999508 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:14:13.002382 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:14:13.009164 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:14:13.012547 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:14:13.015850 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:14:13.023083 0 9 12 | B1->B0 | 2c2c 3131 | 0 1 | (0 0) (1 1)
814 12:14:13.026303 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:14:13.029578 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:14:13.036215 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:14:13.039559 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:14:13.042831 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:14:13.049278 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
820 12:14:13.052606 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
821 12:14:13.055845 0 10 12 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
822 12:14:13.062429 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:14:13.066303 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:14:13.069543 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:14:13.076276 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:14:13.079467 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:14:13.082740 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:14:13.089291 0 11 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
829 12:14:13.092664 0 11 12 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
830 12:14:13.095982 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:14:13.102809 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:14:13.105886 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:14:13.108918 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:14:13.115732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:14:13.119472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:14:13.122659 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 12:14:13.125892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
838 12:14:13.132488 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:14:13.135664 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:14:13.139100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:14:13.145785 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:14:13.149023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:14:13.152231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:14:13.159546 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:14:13.162814 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:14:13.165527 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:14:13.172112 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:14:13.176081 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:14:13.179298 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:14:13.185866 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:14:13.189185 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:14:13.192515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:14:13.195828 Total UI for P1: 0, mck2ui 16
854 12:14:13.199122 best dqsien dly found for B0: ( 0, 14, 6)
855 12:14:13.205497 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:14:13.205581 Total UI for P1: 0, mck2ui 16
857 12:14:13.208741 best dqsien dly found for B1: ( 0, 14, 8)
858 12:14:13.215594 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 12:14:13.218708 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:14:13.218808
861 12:14:13.222437 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 12:14:13.225572 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:14:13.228891 [Gating] SW calibration Done
864 12:14:13.228990 ==
865 12:14:13.232120 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:14:13.235305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:14:13.235438 ==
868 12:14:13.235541 RX Vref Scan: 0
869 12:14:13.239253
870 12:14:13.239385 RX Vref 0 -> 0, step: 1
871 12:14:13.239496
872 12:14:13.242608 RX Delay -130 -> 252, step: 16
873 12:14:13.245908 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 12:14:13.249207 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 12:14:13.255713 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 12:14:13.258910 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 12:14:13.262281 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 12:14:13.265591 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 12:14:13.268929 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 12:14:13.275609 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 12:14:13.278911 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 12:14:13.282136 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 12:14:13.285621 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 12:14:13.288845 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 12:14:13.296028 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 12:14:13.298692 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 12:14:13.302747 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 12:14:13.305481 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 12:14:13.305565 ==
890 12:14:13.308823 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:14:13.315486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:14:13.315570 ==
893 12:14:13.315636 DQS Delay:
894 12:14:13.319135 DQS0 = 0, DQS1 = 0
895 12:14:13.319219 DQM Delay:
896 12:14:13.319299 DQM0 = 87, DQM1 = 81
897 12:14:13.322154 DQ Delay:
898 12:14:13.325887 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 12:14:13.329076 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
900 12:14:13.332248 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
901 12:14:13.335604 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
902 12:14:13.335730
903 12:14:13.335826
904 12:14:13.335920 ==
905 12:14:13.339183 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:14:13.342257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:14:13.342342 ==
908 12:14:13.342408
909 12:14:13.342468
910 12:14:13.345625 TX Vref Scan disable
911 12:14:13.345709 == TX Byte 0 ==
912 12:14:13.352040 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 12:14:13.355869 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 12:14:13.355952 == TX Byte 1 ==
915 12:14:13.362343 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 12:14:13.365621 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 12:14:13.365705 ==
918 12:14:13.368949 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:14:13.372379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:14:13.372463 ==
921 12:14:13.386063 TX Vref=22, minBit 0, minWin=27, winSum=439
922 12:14:13.389926 TX Vref=24, minBit 5, minWin=27, winSum=445
923 12:14:13.393262 TX Vref=26, minBit 8, minWin=27, winSum=448
924 12:14:13.396406 TX Vref=28, minBit 1, minWin=28, winSum=453
925 12:14:13.399723 TX Vref=30, minBit 12, minWin=27, winSum=454
926 12:14:13.406357 TX Vref=32, minBit 2, minWin=28, winSum=451
927 12:14:13.409634 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 28
928 12:14:13.409719
929 12:14:13.412939 Final TX Range 1 Vref 28
930 12:14:13.413023
931 12:14:13.413089 ==
932 12:14:13.416189 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:14:13.419630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:14:13.419715 ==
935 12:14:13.419781
936 12:14:13.422809
937 12:14:13.422892 TX Vref Scan disable
938 12:14:13.426521 == TX Byte 0 ==
939 12:14:13.429611 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 12:14:13.436009 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 12:14:13.436096 == TX Byte 1 ==
942 12:14:13.439775 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 12:14:13.446047 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 12:14:13.446179
945 12:14:13.446277 [DATLAT]
946 12:14:13.446385 Freq=800, CH0 RK0
947 12:14:13.446476
948 12:14:13.449168 DATLAT Default: 0xa
949 12:14:13.449271 0, 0xFFFF, sum = 0
950 12:14:13.453054 1, 0xFFFF, sum = 0
951 12:14:13.453161 2, 0xFFFF, sum = 0
952 12:14:13.456294 3, 0xFFFF, sum = 0
953 12:14:13.456405 4, 0xFFFF, sum = 0
954 12:14:13.459499 5, 0xFFFF, sum = 0
955 12:14:13.462735 6, 0xFFFF, sum = 0
956 12:14:13.462845 7, 0xFFFF, sum = 0
957 12:14:13.466027 8, 0xFFFF, sum = 0
958 12:14:13.466148 9, 0x0, sum = 1
959 12:14:13.469306 10, 0x0, sum = 2
960 12:14:13.469410 11, 0x0, sum = 3
961 12:14:13.469511 12, 0x0, sum = 4
962 12:14:13.472636 best_step = 10
963 12:14:13.472740
964 12:14:13.472834 ==
965 12:14:13.475962 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:14:13.479261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:14:13.479404 ==
968 12:14:13.482695 RX Vref Scan: 1
969 12:14:13.482798
970 12:14:13.486042 Set Vref Range= 32 -> 127
971 12:14:13.486143
972 12:14:13.486243 RX Vref 32 -> 127, step: 1
973 12:14:13.486337
974 12:14:13.489359 RX Delay -95 -> 252, step: 8
975 12:14:13.489463
976 12:14:13.492668 Set Vref, RX VrefLevel [Byte0]: 32
977 12:14:13.495934 [Byte1]: 32
978 12:14:13.496051
979 12:14:13.499134 Set Vref, RX VrefLevel [Byte0]: 33
980 12:14:13.503226 [Byte1]: 33
981 12:14:13.507269
982 12:14:13.507397 Set Vref, RX VrefLevel [Byte0]: 34
983 12:14:13.510422 [Byte1]: 34
984 12:14:13.514312
985 12:14:13.514437 Set Vref, RX VrefLevel [Byte0]: 35
986 12:14:13.517644 [Byte1]: 35
987 12:14:13.521678
988 12:14:13.521798 Set Vref, RX VrefLevel [Byte0]: 36
989 12:14:13.525098 [Byte1]: 36
990 12:14:13.529027
991 12:14:13.529136 Set Vref, RX VrefLevel [Byte0]: 37
992 12:14:13.532284 [Byte1]: 37
993 12:14:13.536879
994 12:14:13.536992 Set Vref, RX VrefLevel [Byte0]: 38
995 12:14:13.540561 [Byte1]: 38
996 12:14:13.544980
997 12:14:13.545103 Set Vref, RX VrefLevel [Byte0]: 39
998 12:14:13.548056 [Byte1]: 39
999 12:14:13.552474
1000 12:14:13.552603 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:14:13.555747 [Byte1]: 40
1002 12:14:13.559594
1003 12:14:13.559680 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:14:13.562804 [Byte1]: 41
1005 12:14:13.567511
1006 12:14:13.570864 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:14:13.570972 [Byte1]: 42
1008 12:14:13.574741
1009 12:14:13.574847 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:14:13.578021 [Byte1]: 43
1011 12:14:13.582672
1012 12:14:13.582779 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:14:13.585962 [Byte1]: 44
1014 12:14:13.589901
1015 12:14:13.590019 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:14:13.593694 [Byte1]: 45
1017 12:14:13.597595
1018 12:14:13.597699 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:14:13.600888 [Byte1]: 46
1020 12:14:13.605525
1021 12:14:13.605633 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:14:13.608788 [Byte1]: 47
1023 12:14:13.612623
1024 12:14:13.612704 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:14:13.615975 [Byte1]: 48
1026 12:14:13.620569
1027 12:14:13.620678 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:14:13.623867 [Byte1]: 49
1029 12:14:13.627826
1030 12:14:13.627934 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:14:13.631123 [Byte1]: 50
1032 12:14:13.635694
1033 12:14:13.635805 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:14:13.639093 [Byte1]: 51
1035 12:14:13.642957
1036 12:14:13.643063 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:14:13.646673 [Byte1]: 52
1038 12:14:13.651134
1039 12:14:13.651242 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:14:13.654303 [Byte1]: 53
1041 12:14:13.658078
1042 12:14:13.658189 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:14:13.661979 [Byte1]: 54
1044 12:14:13.666242
1045 12:14:13.666346 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:14:13.669377 [Byte1]: 55
1047 12:14:13.673991
1048 12:14:13.674096 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:14:13.677255 [Byte1]: 56
1050 12:14:13.681188
1051 12:14:13.681292 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:14:13.684488 [Byte1]: 57
1053 12:14:13.689102
1054 12:14:13.689209 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:14:13.692335 [Byte1]: 58
1056 12:14:13.696396
1057 12:14:13.696502 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:14:13.699736 [Byte1]: 59
1059 12:14:13.704281
1060 12:14:13.704384 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:14:13.707639 [Byte1]: 60
1062 12:14:13.711605
1063 12:14:13.711685 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:14:13.714732 [Byte1]: 61
1065 12:14:13.719286
1066 12:14:13.719411 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:14:13.722599 [Byte1]: 62
1068 12:14:13.726700
1069 12:14:13.726804 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:14:13.729994 [Byte1]: 63
1071 12:14:13.734536
1072 12:14:13.734643 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:14:13.737925 [Byte1]: 64
1074 12:14:13.741895
1075 12:14:13.742014 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:14:13.745138 [Byte1]: 65
1077 12:14:13.749845
1078 12:14:13.749951 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:14:13.752967 [Byte1]: 66
1080 12:14:13.757267
1081 12:14:13.757385 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:14:13.760597 [Byte1]: 67
1083 12:14:13.764473
1084 12:14:13.767668 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:14:13.771394 [Byte1]: 68
1086 12:14:13.771490
1087 12:14:13.774623 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:14:13.777964 [Byte1]: 69
1089 12:14:13.778070
1090 12:14:13.781225 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:14:13.784518 [Byte1]: 70
1092 12:14:13.784621
1093 12:14:13.787823 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:14:13.791161 [Byte1]: 71
1095 12:14:13.795189
1096 12:14:13.795292 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:14:13.801741 [Byte1]: 72
1098 12:14:13.801847
1099 12:14:13.804992 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:14:13.808192 [Byte1]: 73
1101 12:14:13.808292
1102 12:14:13.811533 Set Vref, RX VrefLevel [Byte0]: 74
1103 12:14:13.814724 [Byte1]: 74
1104 12:14:13.814827
1105 12:14:13.818078 Set Vref, RX VrefLevel [Byte0]: 75
1106 12:14:13.821366 [Byte1]: 75
1107 12:14:13.825368
1108 12:14:13.825471 Set Vref, RX VrefLevel [Byte0]: 76
1109 12:14:13.828775 [Byte1]: 76
1110 12:14:13.833369
1111 12:14:13.833485 Set Vref, RX VrefLevel [Byte0]: 77
1112 12:14:13.836682 [Byte1]: 77
1113 12:14:13.840654
1114 12:14:13.840773 Final RX Vref Byte 0 = 62 to rank0
1115 12:14:13.843853 Final RX Vref Byte 1 = 60 to rank0
1116 12:14:13.847060 Final RX Vref Byte 0 = 62 to rank1
1117 12:14:13.850436 Final RX Vref Byte 1 = 60 to rank1==
1118 12:14:13.854252 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 12:14:13.860719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 12:14:13.860824 ==
1121 12:14:13.860895 DQS Delay:
1122 12:14:13.860961 DQS0 = 0, DQS1 = 0
1123 12:14:13.863964 DQM Delay:
1124 12:14:13.864041 DQM0 = 88, DQM1 = 79
1125 12:14:13.867148 DQ Delay:
1126 12:14:13.870966 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1127 12:14:13.871070 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1128 12:14:13.874171 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1129 12:14:13.877284 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1130 12:14:13.880634
1131 12:14:13.880732
1132 12:14:13.887247 [DQSOSCAuto] RK0, (LSB)MR18= 0x250c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1133 12:14:13.890614 CH0 RK0: MR19=606, MR18=250C
1134 12:14:13.897724 CH0_RK0: MR19=0x606, MR18=0x250C, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 12:14:13.897827
1136 12:14:13.900978 ----->DramcWriteLeveling(PI) begin...
1137 12:14:13.901080 ==
1138 12:14:13.904204 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 12:14:13.907401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 12:14:13.907479 ==
1141 12:14:13.910634 Write leveling (Byte 0): 31 => 31
1142 12:14:13.913988 Write leveling (Byte 1): 27 => 27
1143 12:14:13.917212 DramcWriteLeveling(PI) end<-----
1144 12:14:13.917316
1145 12:14:13.917408 ==
1146 12:14:13.921054 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 12:14:13.924206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 12:14:13.924307 ==
1149 12:14:13.927309 [Gating] SW mode calibration
1150 12:14:13.934120 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 12:14:13.940687 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 12:14:13.944113 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 12:14:13.987688 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 12:14:13.987988 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 12:14:13.988102 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 12:14:13.988212 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:14:13.988316 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:14:13.988442 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:14:13.988537 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:14:13.988632 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:14:13.988766 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:14:13.988855 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:14:14.032156 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:14:14.032481 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:14:14.032567 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:14:14.032633 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:14:14.032696 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:14:14.032766 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 12:14:14.032861 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 12:14:14.032948 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1171 12:14:14.033008 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1172 12:14:14.033075 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:14:14.076260 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:14:14.076621 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:14:14.076709 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:14:14.076775 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:14:14.076885 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:14:14.076969 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1179 12:14:14.077031 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1180 12:14:14.077527 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:14:14.077611 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:14:14.077867 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:14:14.080714 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:14:14.083953 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:14:14.090221 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1186 12:14:14.094192 0 10 8 | B1->B0 | 3232 2626 | 1 0 | (1 0) (0 0)
1187 12:14:14.097513 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
1188 12:14:14.100781 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:14:14.107261 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:14:14.110503 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:14:14.114500 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:14:14.121735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:14:14.125741 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1194 12:14:14.129658 0 11 8 | B1->B0 | 2c2c 4141 | 0 0 | (0 0) (0 0)
1195 12:14:14.132912 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1196 12:14:14.136223 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:14:14.142921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:14:14.146843 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:14:14.150173 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:14:14.153470 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:14:14.159988 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 12:14:14.163422 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 12:14:14.166491 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1204 12:14:14.173537 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:14:14.177144 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:14:14.180430 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:14:14.187031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:14:14.190274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:14:14.193431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:14:14.200624 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:14:14.203814 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:14:14.207071 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:14:14.213713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:14:14.217006 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:14:14.220441 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:14:14.223627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:14:14.230268 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1218 12:14:14.233605 Total UI for P1: 0, mck2ui 16
1219 12:14:14.236871 best dqsien dly found for B0: ( 0, 14, 2)
1220 12:14:14.240208 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 12:14:14.244235 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 12:14:14.247459 Total UI for P1: 0, mck2ui 16
1223 12:14:14.250865 best dqsien dly found for B1: ( 0, 14, 10)
1224 12:14:14.254102 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1225 12:14:14.257526 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1226 12:14:14.257633
1227 12:14:14.263950 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1228 12:14:14.267294 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1229 12:14:14.267440 [Gating] SW calibration Done
1230 12:14:14.270641 ==
1231 12:14:14.274026 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 12:14:14.277314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 12:14:14.277432 ==
1234 12:14:14.277624 RX Vref Scan: 0
1235 12:14:14.277819
1236 12:14:14.280456 RX Vref 0 -> 0, step: 1
1237 12:14:14.280558
1238 12:14:14.283725 RX Delay -130 -> 252, step: 16
1239 12:14:14.287301 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1240 12:14:14.290420 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 12:14:14.294120 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1242 12:14:14.300697 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1243 12:14:14.304036 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1244 12:14:14.307255 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1245 12:14:14.310630 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1246 12:14:14.313717 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1247 12:14:14.320232 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1248 12:14:14.323631 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1249 12:14:14.326867 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 12:14:14.330669 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1251 12:14:14.334015 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1252 12:14:14.340528 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1253 12:14:14.343825 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1254 12:14:14.347108 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1255 12:14:14.347215 ==
1256 12:14:14.350405 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 12:14:14.353662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 12:14:14.353769 ==
1259 12:14:14.357542 DQS Delay:
1260 12:14:14.357644 DQS0 = 0, DQS1 = 0
1261 12:14:14.360825 DQM Delay:
1262 12:14:14.360925 DQM0 = 85, DQM1 = 76
1263 12:14:14.361020 DQ Delay:
1264 12:14:14.364044 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1265 12:14:14.367270 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1266 12:14:14.370688 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1267 12:14:14.373988 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1268 12:14:14.374067
1269 12:14:14.374135
1270 12:14:14.377222 ==
1271 12:14:14.380599 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 12:14:14.383937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 12:14:14.384042 ==
1274 12:14:14.384139
1275 12:14:14.384232
1276 12:14:14.387096 TX Vref Scan disable
1277 12:14:14.387183 == TX Byte 0 ==
1278 12:14:14.390828 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 12:14:14.397159 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 12:14:14.397245 == TX Byte 1 ==
1281 12:14:14.400234 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1282 12:14:14.407149 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1283 12:14:14.407233 ==
1284 12:14:14.410508 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:14:14.413807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:14:14.413900 ==
1287 12:14:14.427459 TX Vref=22, minBit 3, minWin=27, winSum=441
1288 12:14:14.430650 TX Vref=24, minBit 8, minWin=27, winSum=447
1289 12:14:14.434682 TX Vref=26, minBit 9, minWin=27, winSum=450
1290 12:14:14.437852 TX Vref=28, minBit 9, minWin=27, winSum=450
1291 12:14:14.441236 TX Vref=30, minBit 12, minWin=27, winSum=455
1292 12:14:14.447223 TX Vref=32, minBit 4, minWin=28, winSum=456
1293 12:14:14.451151 [TxChooseVref] Worse bit 4, Min win 28, Win sum 456, Final Vref 32
1294 12:14:14.451244
1295 12:14:14.454478 Final TX Range 1 Vref 32
1296 12:14:14.454582
1297 12:14:14.454689 ==
1298 12:14:14.457658 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 12:14:14.460936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 12:14:14.461018 ==
1301 12:14:14.464170
1302 12:14:14.464270
1303 12:14:14.464371 TX Vref Scan disable
1304 12:14:14.467537 == TX Byte 0 ==
1305 12:14:14.470734 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1306 12:14:14.477306 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1307 12:14:14.477385 == TX Byte 1 ==
1308 12:14:14.480665 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1309 12:14:14.487210 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1310 12:14:14.487319
1311 12:14:14.487503 [DATLAT]
1312 12:14:14.487576 Freq=800, CH0 RK1
1313 12:14:14.487643
1314 12:14:14.490434 DATLAT Default: 0xa
1315 12:14:14.490508 0, 0xFFFF, sum = 0
1316 12:14:14.494381 1, 0xFFFF, sum = 0
1317 12:14:14.497423 2, 0xFFFF, sum = 0
1318 12:14:14.497516 3, 0xFFFF, sum = 0
1319 12:14:14.500352 4, 0xFFFF, sum = 0
1320 12:14:14.500458 5, 0xFFFF, sum = 0
1321 12:14:14.504134 6, 0xFFFF, sum = 0
1322 12:14:14.504222 7, 0xFFFF, sum = 0
1323 12:14:14.507268 8, 0xFFFF, sum = 0
1324 12:14:14.507344 9, 0x0, sum = 1
1325 12:14:14.510330 10, 0x0, sum = 2
1326 12:14:14.510415 11, 0x0, sum = 3
1327 12:14:14.514133 12, 0x0, sum = 4
1328 12:14:14.514211 best_step = 10
1329 12:14:14.514279
1330 12:14:14.514349 ==
1331 12:14:14.517361 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 12:14:14.520615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 12:14:14.520693 ==
1334 12:14:14.523996 RX Vref Scan: 0
1335 12:14:14.524114
1336 12:14:14.527229 RX Vref 0 -> 0, step: 1
1337 12:14:14.527307
1338 12:14:14.527379 RX Delay -95 -> 252, step: 8
1339 12:14:14.534457 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 12:14:14.537885 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1341 12:14:14.541158 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1342 12:14:14.544478 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1343 12:14:14.547775 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1344 12:14:14.554547 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1345 12:14:14.557769 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1346 12:14:14.561069 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1347 12:14:14.564345 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1348 12:14:14.567593 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1349 12:14:14.574235 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1350 12:14:14.577467 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1351 12:14:14.580651 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1352 12:14:14.583997 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1353 12:14:14.587314 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1354 12:14:14.593997 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 12:14:14.594074 ==
1356 12:14:14.597178 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 12:14:14.601121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 12:14:14.601232 ==
1359 12:14:14.601326 DQS Delay:
1360 12:14:14.604357 DQS0 = 0, DQS1 = 0
1361 12:14:14.604431 DQM Delay:
1362 12:14:14.607583 DQM0 = 87, DQM1 = 78
1363 12:14:14.607663 DQ Delay:
1364 12:14:14.610771 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1365 12:14:14.613895 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1366 12:14:14.617152 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1367 12:14:14.620363 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1368 12:14:14.620470
1369 12:14:14.620581
1370 12:14:14.630870 [DQSOSCAuto] RK1, (LSB)MR18= 0x321b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1371 12:14:14.630958 CH0 RK1: MR19=606, MR18=321B
1372 12:14:14.637463 CH0_RK1: MR19=0x606, MR18=0x321B, DQSOSC=397, MR23=63, INC=93, DEC=62
1373 12:14:14.640783 [RxdqsGatingPostProcess] freq 800
1374 12:14:14.647271 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 12:14:14.650637 Pre-setting of DQS Precalculation
1376 12:14:14.653946 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 12:14:14.654046 ==
1378 12:14:14.657213 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 12:14:14.660482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 12:14:14.663757 ==
1381 12:14:14.667035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 12:14:14.673996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 12:14:14.682676 [CA 0] Center 36 (6~66) winsize 61
1384 12:14:14.686054 [CA 1] Center 36 (6~66) winsize 61
1385 12:14:14.689264 [CA 2] Center 34 (4~65) winsize 62
1386 12:14:14.692602 [CA 3] Center 34 (3~65) winsize 63
1387 12:14:14.695817 [CA 4] Center 34 (4~65) winsize 62
1388 12:14:14.699138 [CA 5] Center 33 (3~64) winsize 62
1389 12:14:14.699233
1390 12:14:14.702429 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 12:14:14.702514
1392 12:14:14.705719 [CATrainingPosCal] consider 1 rank data
1393 12:14:14.708933 u2DelayCellTimex100 = 270/100 ps
1394 12:14:14.712641 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1395 12:14:14.715837 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 12:14:14.722197 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 12:14:14.725408 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1398 12:14:14.729282 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 12:14:14.732021 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 12:14:14.732105
1401 12:14:14.735945 CA PerBit enable=1, Macro0, CA PI delay=33
1402 12:14:14.736029
1403 12:14:14.738661 [CBTSetCACLKResult] CA Dly = 33
1404 12:14:14.738746 CS Dly: 5 (0~36)
1405 12:14:14.742036 ==
1406 12:14:14.742120 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 12:14:14.749114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 12:14:14.749224 ==
1409 12:14:14.752364 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 12:14:14.758850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 12:14:14.768636 [CA 0] Center 36 (6~66) winsize 61
1412 12:14:14.771942 [CA 1] Center 36 (6~66) winsize 61
1413 12:14:14.775345 [CA 2] Center 34 (4~64) winsize 61
1414 12:14:14.778621 [CA 3] Center 33 (3~64) winsize 62
1415 12:14:14.781838 [CA 4] Center 34 (4~65) winsize 62
1416 12:14:14.785805 [CA 5] Center 33 (3~64) winsize 62
1417 12:14:14.785909
1418 12:14:14.789678 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1419 12:14:14.789781
1420 12:14:14.793645 [CATrainingPosCal] consider 2 rank data
1421 12:14:14.796910 u2DelayCellTimex100 = 270/100 ps
1422 12:14:14.800921 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1423 12:14:14.804229 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 12:14:14.808107 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1425 12:14:14.812085 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1426 12:14:14.815357 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1427 12:14:14.819146 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 12:14:14.819251
1429 12:14:14.822244 CA PerBit enable=1, Macro0, CA PI delay=33
1430 12:14:14.822350
1431 12:14:14.825521 [CBTSetCACLKResult] CA Dly = 33
1432 12:14:14.825600 CS Dly: 5 (0~36)
1433 12:14:14.825666
1434 12:14:14.829197 ----->DramcWriteLeveling(PI) begin...
1435 12:14:14.829308 ==
1436 12:14:14.832514 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:14:14.839080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:14:14.839190 ==
1439 12:14:14.842393 Write leveling (Byte 0): 27 => 27
1440 12:14:14.842499 Write leveling (Byte 1): 28 => 28
1441 12:14:14.845684 DramcWriteLeveling(PI) end<-----
1442 12:14:14.845760
1443 12:14:14.848832 ==
1444 12:14:14.848905 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 12:14:14.855420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 12:14:14.855524 ==
1447 12:14:14.858723 [Gating] SW mode calibration
1448 12:14:14.865795 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 12:14:14.869122 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 12:14:14.875725 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 12:14:14.878908 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 12:14:14.882099 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 12:14:14.888676 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:14:14.891967 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:14:14.895973 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:14:14.899293 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:14:14.905673 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:14:14.909025 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:14:14.912251 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:14:14.918745 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:14:14.922605 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:14:14.925770 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:14:14.932712 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:14:14.935953 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:14:14.939178 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1466 12:14:14.945672 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:14:14.948959 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 12:14:14.952268 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1469 12:14:14.958940 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:14:14.962203 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:14:14.965321 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:14:14.972009 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:14:14.975272 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:14:14.979251 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:14:14.985281 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:14:14.988624 0 9 8 | B1->B0 | 2525 2626 | 1 1 | (1 1) (0 0)
1477 12:14:14.991901 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:14:14.998594 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:14:15.001881 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:14:15.005176 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:14:15.009153 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:14:15.015696 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:14:15.018922 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1484 12:14:15.022152 0 10 8 | B1->B0 | 2929 2a2a | 0 0 | (0 0) (0 0)
1485 12:14:15.028981 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:14:15.032300 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:14:15.035553 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:14:15.042439 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:14:15.045634 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:14:15.048895 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:14:15.055535 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1492 12:14:15.058833 0 11 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1493 12:14:15.062097 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:14:15.068649 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:14:15.071923 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:14:15.075199 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:14:15.082279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:14:15.085622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:14:15.089069 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:14:15.095616 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 12:14:15.098809 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:14:15.102235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:14:15.108642 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:14:15.111860 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:14:15.115209 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:14:15.118463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:14:15.125047 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:14:15.128947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:14:15.132122 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:14:15.138452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:14:15.142187 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:14:15.145441 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:14:15.151990 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:14:15.155258 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:14:15.158701 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:14:15.165236 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 12:14:15.168494 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 12:14:15.172295 Total UI for P1: 0, mck2ui 16
1519 12:14:15.175049 best dqsien dly found for B0: ( 0, 14, 8)
1520 12:14:15.178429 Total UI for P1: 0, mck2ui 16
1521 12:14:15.182290 best dqsien dly found for B1: ( 0, 14, 8)
1522 12:14:15.185019 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1523 12:14:15.188344 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1524 12:14:15.188457
1525 12:14:15.192245 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1526 12:14:15.195550 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 12:14:15.198942 [Gating] SW calibration Done
1528 12:14:15.199025 ==
1529 12:14:15.202198 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 12:14:15.205490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 12:14:15.205607 ==
1532 12:14:15.208688 RX Vref Scan: 0
1533 12:14:15.208771
1534 12:14:15.212014 RX Vref 0 -> 0, step: 1
1535 12:14:15.212129
1536 12:14:15.212209 RX Delay -130 -> 252, step: 16
1537 12:14:15.218624 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1538 12:14:15.221942 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1539 12:14:15.225123 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1540 12:14:15.228681 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1541 12:14:15.231904 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1542 12:14:15.238406 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1543 12:14:15.242193 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1544 12:14:15.245428 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1545 12:14:15.248517 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1546 12:14:15.251684 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1547 12:14:15.258776 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1548 12:14:15.262145 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1549 12:14:15.265401 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1550 12:14:15.268813 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1551 12:14:15.272099 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1552 12:14:15.278625 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1553 12:14:15.278742 ==
1554 12:14:15.282019 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 12:14:15.285277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 12:14:15.285358 ==
1557 12:14:15.285440 DQS Delay:
1558 12:14:15.288571 DQS0 = 0, DQS1 = 0
1559 12:14:15.288646 DQM Delay:
1560 12:14:15.291933 DQM0 = 84, DQM1 = 76
1561 12:14:15.292007 DQ Delay:
1562 12:14:15.295150 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1563 12:14:15.298467 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1564 12:14:15.301746 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1565 12:14:15.305120 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 12:14:15.305245
1567 12:14:15.305359
1568 12:14:15.305464 ==
1569 12:14:15.308430 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 12:14:15.311763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 12:14:15.314878 ==
1572 12:14:15.314960
1573 12:14:15.315061
1574 12:14:15.315162 TX Vref Scan disable
1575 12:14:15.318224 == TX Byte 0 ==
1576 12:14:15.322136 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 12:14:15.325560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 12:14:15.328861 == TX Byte 1 ==
1579 12:14:15.332055 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1580 12:14:15.335263 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1581 12:14:15.335382 ==
1582 12:14:15.338597 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 12:14:15.344903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 12:14:15.344992 ==
1585 12:14:15.356904 TX Vref=22, minBit 0, minWin=27, winSum=438
1586 12:14:15.360701 TX Vref=24, minBit 4, minWin=27, winSum=442
1587 12:14:15.364082 TX Vref=26, minBit 3, minWin=27, winSum=446
1588 12:14:15.368124 TX Vref=28, minBit 11, minWin=27, winSum=449
1589 12:14:15.371328 TX Vref=30, minBit 4, minWin=27, winSum=449
1590 12:14:15.374616 TX Vref=32, minBit 1, minWin=28, winSum=456
1591 12:14:15.381299 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 32
1592 12:14:15.381384
1593 12:14:15.384486 Final TX Range 1 Vref 32
1594 12:14:15.384576
1595 12:14:15.384642 ==
1596 12:14:15.387720 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 12:14:15.391004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 12:14:15.391088 ==
1599 12:14:15.391154
1600 12:14:15.391215
1601 12:14:15.394949 TX Vref Scan disable
1602 12:14:15.398166 == TX Byte 0 ==
1603 12:14:15.401554 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 12:14:15.404805 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 12:14:15.408311 == TX Byte 1 ==
1606 12:14:15.411440 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 12:14:15.414841 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 12:14:15.414925
1609 12:14:15.418071 [DATLAT]
1610 12:14:15.418154 Freq=800, CH1 RK0
1611 12:14:15.418222
1612 12:14:15.421440 DATLAT Default: 0xa
1613 12:14:15.421551 0, 0xFFFF, sum = 0
1614 12:14:15.424678 1, 0xFFFF, sum = 0
1615 12:14:15.424795 2, 0xFFFF, sum = 0
1616 12:14:15.427873 3, 0xFFFF, sum = 0
1617 12:14:15.427953 4, 0xFFFF, sum = 0
1618 12:14:15.431184 5, 0xFFFF, sum = 0
1619 12:14:15.431270 6, 0xFFFF, sum = 0
1620 12:14:15.434459 7, 0xFFFF, sum = 0
1621 12:14:15.434575 8, 0xFFFF, sum = 0
1622 12:14:15.437682 9, 0x0, sum = 1
1623 12:14:15.437763 10, 0x0, sum = 2
1624 12:14:15.441041 11, 0x0, sum = 3
1625 12:14:15.441154 12, 0x0, sum = 4
1626 12:14:15.441257 best_step = 10
1627 12:14:15.444865
1628 12:14:15.444965 ==
1629 12:14:15.448117 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 12:14:15.451261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 12:14:15.451377 ==
1632 12:14:15.451480 RX Vref Scan: 1
1633 12:14:15.451574
1634 12:14:15.454460 Set Vref Range= 32 -> 127
1635 12:14:15.454547
1636 12:14:15.457633 RX Vref 32 -> 127, step: 1
1637 12:14:15.457752
1638 12:14:15.461382 RX Delay -95 -> 252, step: 8
1639 12:14:15.461486
1640 12:14:15.464526 Set Vref, RX VrefLevel [Byte0]: 32
1641 12:14:15.467638 [Byte1]: 32
1642 12:14:15.467749
1643 12:14:15.471342 Set Vref, RX VrefLevel [Byte0]: 33
1644 12:14:15.474932 [Byte1]: 33
1645 12:14:15.475047
1646 12:14:15.478240 Set Vref, RX VrefLevel [Byte0]: 34
1647 12:14:15.481295 [Byte1]: 34
1648 12:14:15.484629
1649 12:14:15.484742 Set Vref, RX VrefLevel [Byte0]: 35
1650 12:14:15.488572 [Byte1]: 35
1651 12:14:15.492590
1652 12:14:15.492696 Set Vref, RX VrefLevel [Byte0]: 36
1653 12:14:15.495926 [Byte1]: 36
1654 12:14:15.499962
1655 12:14:15.500041 Set Vref, RX VrefLevel [Byte0]: 37
1656 12:14:15.503257 [Byte1]: 37
1657 12:14:15.507868
1658 12:14:15.507973 Set Vref, RX VrefLevel [Byte0]: 38
1659 12:14:15.511119 [Byte1]: 38
1660 12:14:15.514981
1661 12:14:15.515086 Set Vref, RX VrefLevel [Byte0]: 39
1662 12:14:15.518227 [Byte1]: 39
1663 12:14:15.522790
1664 12:14:15.522911 Set Vref, RX VrefLevel [Byte0]: 40
1665 12:14:15.526186 [Byte1]: 40
1666 12:14:15.530103
1667 12:14:15.530225 Set Vref, RX VrefLevel [Byte0]: 41
1668 12:14:15.534109 [Byte1]: 41
1669 12:14:15.538118
1670 12:14:15.538232 Set Vref, RX VrefLevel [Byte0]: 42
1671 12:14:15.544757 [Byte1]: 42
1672 12:14:15.544869
1673 12:14:15.548016 Set Vref, RX VrefLevel [Byte0]: 43
1674 12:14:15.550847 [Byte1]: 43
1675 12:14:15.550962
1676 12:14:15.554616 Set Vref, RX VrefLevel [Byte0]: 44
1677 12:14:15.557706 [Byte1]: 44
1678 12:14:15.557820
1679 12:14:15.560917 Set Vref, RX VrefLevel [Byte0]: 45
1680 12:14:15.564182 [Byte1]: 45
1681 12:14:15.568639
1682 12:14:15.568748 Set Vref, RX VrefLevel [Byte0]: 46
1683 12:14:15.571843 [Byte1]: 46
1684 12:14:15.575787
1685 12:14:15.575905 Set Vref, RX VrefLevel [Byte0]: 47
1686 12:14:15.579601 [Byte1]: 47
1687 12:14:15.583562
1688 12:14:15.583666 Set Vref, RX VrefLevel [Byte0]: 48
1689 12:14:15.586840 [Byte1]: 48
1690 12:14:15.591295
1691 12:14:15.591402 Set Vref, RX VrefLevel [Byte0]: 49
1692 12:14:15.594659 [Byte1]: 49
1693 12:14:15.598651
1694 12:14:15.598761 Set Vref, RX VrefLevel [Byte0]: 50
1695 12:14:15.601836 [Byte1]: 50
1696 12:14:15.606522
1697 12:14:15.606603 Set Vref, RX VrefLevel [Byte0]: 51
1698 12:14:15.609834 [Byte1]: 51
1699 12:14:15.613808
1700 12:14:15.613895 Set Vref, RX VrefLevel [Byte0]: 52
1701 12:14:15.617133 [Byte1]: 52
1702 12:14:15.621776
1703 12:14:15.621884 Set Vref, RX VrefLevel [Byte0]: 53
1704 12:14:15.625112 [Byte1]: 53
1705 12:14:15.629067
1706 12:14:15.629175 Set Vref, RX VrefLevel [Byte0]: 54
1707 12:14:15.632246 [Byte1]: 54
1708 12:14:15.636879
1709 12:14:15.636998 Set Vref, RX VrefLevel [Byte0]: 55
1710 12:14:15.640206 [Byte1]: 55
1711 12:14:15.644803
1712 12:14:15.644947 Set Vref, RX VrefLevel [Byte0]: 56
1713 12:14:15.648059 [Byte1]: 56
1714 12:14:15.652049
1715 12:14:15.652160 Set Vref, RX VrefLevel [Byte0]: 57
1716 12:14:15.655272 [Byte1]: 57
1717 12:14:15.659813
1718 12:14:15.659921 Set Vref, RX VrefLevel [Byte0]: 58
1719 12:14:15.662878 [Byte1]: 58
1720 12:14:15.667266
1721 12:14:15.667390 Set Vref, RX VrefLevel [Byte0]: 59
1722 12:14:15.670376 [Byte1]: 59
1723 12:14:15.674776
1724 12:14:15.674885 Set Vref, RX VrefLevel [Byte0]: 60
1725 12:14:15.677994 [Byte1]: 60
1726 12:14:15.682395
1727 12:14:15.682501 Set Vref, RX VrefLevel [Byte0]: 61
1728 12:14:15.686098 [Byte1]: 61
1729 12:14:15.689902
1730 12:14:15.690012 Set Vref, RX VrefLevel [Byte0]: 62
1731 12:14:15.693136 [Byte1]: 62
1732 12:14:15.697876
1733 12:14:15.697982 Set Vref, RX VrefLevel [Byte0]: 63
1734 12:14:15.701142 [Byte1]: 63
1735 12:14:15.705125
1736 12:14:15.705239 Set Vref, RX VrefLevel [Byte0]: 64
1737 12:14:15.708461 [Byte1]: 64
1738 12:14:15.713039
1739 12:14:15.713131 Set Vref, RX VrefLevel [Byte0]: 65
1740 12:14:15.716425 [Byte1]: 65
1741 12:14:15.720302
1742 12:14:15.720386 Set Vref, RX VrefLevel [Byte0]: 66
1743 12:14:15.723499 [Byte1]: 66
1744 12:14:15.728058
1745 12:14:15.728138 Set Vref, RX VrefLevel [Byte0]: 67
1746 12:14:15.731331 [Byte1]: 67
1747 12:14:15.735272
1748 12:14:15.735388 Set Vref, RX VrefLevel [Byte0]: 68
1749 12:14:15.738662 [Byte1]: 68
1750 12:14:15.743257
1751 12:14:15.743371 Set Vref, RX VrefLevel [Byte0]: 69
1752 12:14:15.746622 [Byte1]: 69
1753 12:14:15.751034
1754 12:14:15.751143 Set Vref, RX VrefLevel [Byte0]: 70
1755 12:14:15.754317 [Byte1]: 70
1756 12:14:15.758246
1757 12:14:15.758359 Set Vref, RX VrefLevel [Byte0]: 71
1758 12:14:15.761447 [Byte1]: 71
1759 12:14:15.766118
1760 12:14:15.766241 Set Vref, RX VrefLevel [Byte0]: 72
1761 12:14:15.769404 [Byte1]: 72
1762 12:14:15.773149
1763 12:14:15.776858 Set Vref, RX VrefLevel [Byte0]: 73
1764 12:14:15.776976 [Byte1]: 73
1765 12:14:15.780998
1766 12:14:15.781107 Set Vref, RX VrefLevel [Byte0]: 74
1767 12:14:15.784619 [Byte1]: 74
1768 12:14:15.788874
1769 12:14:15.788983 Set Vref, RX VrefLevel [Byte0]: 75
1770 12:14:15.792001 [Byte1]: 75
1771 12:14:15.796292
1772 12:14:15.796399 Set Vref, RX VrefLevel [Byte0]: 76
1773 12:14:15.799470 [Byte1]: 76
1774 12:14:15.804096
1775 12:14:15.804202 Set Vref, RX VrefLevel [Byte0]: 77
1776 12:14:15.810122 [Byte1]: 77
1777 12:14:15.810235
1778 12:14:15.813482 Set Vref, RX VrefLevel [Byte0]: 78
1779 12:14:15.817364 [Byte1]: 78
1780 12:14:15.817495
1781 12:14:15.820729 Set Vref, RX VrefLevel [Byte0]: 79
1782 12:14:15.823978 [Byte1]: 79
1783 12:14:15.824096
1784 12:14:15.827191 Final RX Vref Byte 0 = 60 to rank0
1785 12:14:15.830421 Final RX Vref Byte 1 = 59 to rank0
1786 12:14:15.833750 Final RX Vref Byte 0 = 60 to rank1
1787 12:14:15.836950 Final RX Vref Byte 1 = 59 to rank1==
1788 12:14:15.840323 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 12:14:15.843659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 12:14:15.846952 ==
1791 12:14:15.847062 DQS Delay:
1792 12:14:15.847162 DQS0 = 0, DQS1 = 0
1793 12:14:15.850225 DQM Delay:
1794 12:14:15.850337 DQM0 = 85, DQM1 = 75
1795 12:14:15.853591 DQ Delay:
1796 12:14:15.853698 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1797 12:14:15.856966 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1798 12:14:15.860293 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1799 12:14:15.863583 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1800 12:14:15.863727
1801 12:14:15.866790
1802 12:14:15.873571 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 400 ps
1803 12:14:15.876836 CH1 RK0: MR19=605, MR18=27FD
1804 12:14:15.883999 CH1_RK0: MR19=0x605, MR18=0x27FD, DQSOSC=400, MR23=63, INC=92, DEC=61
1805 12:14:15.884113
1806 12:14:15.887113 ----->DramcWriteLeveling(PI) begin...
1807 12:14:15.887229 ==
1808 12:14:15.890364 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 12:14:15.893562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 12:14:15.893679 ==
1811 12:14:15.896610 Write leveling (Byte 0): 26 => 26
1812 12:14:15.900413 Write leveling (Byte 1): 27 => 27
1813 12:14:15.903626 DramcWriteLeveling(PI) end<-----
1814 12:14:15.903755
1815 12:14:15.903848 ==
1816 12:14:15.906795 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 12:14:15.909719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 12:14:15.909843 ==
1819 12:14:15.913523 [Gating] SW mode calibration
1820 12:14:15.919950 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 12:14:15.926468 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 12:14:15.929720 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 12:14:15.933726 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1824 12:14:15.940239 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:14:15.943527 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:14:15.946856 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:14:15.952873 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:14:15.956777 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:14:15.960138 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:14:15.966752 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:14:15.969953 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:14:15.973249 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:14:15.979918 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:14:15.983202 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:14:15.986469 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:14:15.993038 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 12:14:15.996898 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1838 12:14:16.000018 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1839 12:14:16.003131 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1840 12:14:16.010057 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1841 12:14:16.013345 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:14:16.016407 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:14:16.022934 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:14:16.026263 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:14:16.030162 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:14:16.036700 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:14:16.039956 0 9 4 | B1->B0 | 2323 2929 | 1 1 | (0 0) (1 1)
1848 12:14:16.043253 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1849 12:14:16.049872 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1850 12:14:16.053111 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:14:16.056353 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 12:14:16.062923 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 12:14:16.066087 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 12:14:16.069990 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1855 12:14:16.075967 0 10 4 | B1->B0 | 3030 3030 | 1 0 | (1 0) (0 1)
1856 12:14:16.079953 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
1857 12:14:16.082591 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:14:16.089737 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:14:16.092809 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:14:16.096094 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:14:16.102707 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:14:16.105944 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:14:16.109932 0 11 4 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
1864 12:14:16.116252 0 11 8 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
1865 12:14:16.119503 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:14:16.122860 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:14:16.125907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:14:16.133084 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:14:16.136283 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:14:16.142898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:14:16.146115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1872 12:14:16.149500 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1873 12:14:16.152711 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:14:16.159257 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:14:16.162566 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:14:16.165906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:14:16.172580 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:14:16.175863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:14:16.179136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:14:16.185808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:14:16.189042 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:14:16.192900 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:14:16.199250 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:14:16.202548 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:14:16.205690 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 12:14:16.212375 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 12:14:16.215944 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1888 12:14:16.219037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 12:14:16.222061 Total UI for P1: 0, mck2ui 16
1890 12:14:16.225844 best dqsien dly found for B0: ( 0, 14, 4)
1891 12:14:16.229018 Total UI for P1: 0, mck2ui 16
1892 12:14:16.232167 best dqsien dly found for B1: ( 0, 14, 6)
1893 12:14:16.235803 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1894 12:14:16.238911 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1895 12:14:16.239021
1896 12:14:16.242218 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 12:14:16.248807 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1898 12:14:16.248917 [Gating] SW calibration Done
1899 12:14:16.249024 ==
1900 12:14:16.252089 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 12:14:16.259388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 12:14:16.259506 ==
1903 12:14:16.259607 RX Vref Scan: 0
1904 12:14:16.259701
1905 12:14:16.262609 RX Vref 0 -> 0, step: 1
1906 12:14:16.262717
1907 12:14:16.265878 RX Delay -130 -> 252, step: 16
1908 12:14:16.269175 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 12:14:16.272624 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1910 12:14:16.275962 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 12:14:16.282601 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1912 12:14:16.285934 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1913 12:14:16.289128 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1914 12:14:16.292482 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1915 12:14:16.295805 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1916 12:14:16.299655 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1917 12:14:16.306050 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1918 12:14:16.309248 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1919 12:14:16.312584 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1920 12:14:16.315813 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1921 12:14:16.319776 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1922 12:14:16.326212 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1923 12:14:16.329464 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1924 12:14:16.329578 ==
1925 12:14:16.332589 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 12:14:16.336185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 12:14:16.336307 ==
1928 12:14:16.339426 DQS Delay:
1929 12:14:16.339530 DQS0 = 0, DQS1 = 0
1930 12:14:16.339628 DQM Delay:
1931 12:14:16.343047 DQM0 = 81, DQM1 = 77
1932 12:14:16.343157 DQ Delay:
1933 12:14:16.346050 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1934 12:14:16.350019 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1935 12:14:16.353241 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1936 12:14:16.356575 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 12:14:16.356679
1938 12:14:16.356786
1939 12:14:16.356885 ==
1940 12:14:16.359812 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 12:14:16.363061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 12:14:16.366432 ==
1943 12:14:16.366541
1944 12:14:16.366638
1945 12:14:16.366731 TX Vref Scan disable
1946 12:14:16.369587 == TX Byte 0 ==
1947 12:14:16.372867 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1948 12:14:16.376155 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1949 12:14:16.380134 == TX Byte 1 ==
1950 12:14:16.382871 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1951 12:14:16.386787 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1952 12:14:16.386889 ==
1953 12:14:16.390176 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:14:16.396753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:14:16.396861 ==
1956 12:14:16.408440 TX Vref=22, minBit 0, minWin=27, winSum=440
1957 12:14:16.411610 TX Vref=24, minBit 1, minWin=27, winSum=444
1958 12:14:16.414902 TX Vref=26, minBit 1, minWin=27, winSum=448
1959 12:14:16.418739 TX Vref=28, minBit 0, minWin=28, winSum=450
1960 12:14:16.421943 TX Vref=30, minBit 12, minWin=27, winSum=452
1961 12:14:16.425255 TX Vref=32, minBit 9, minWin=27, winSum=450
1962 12:14:16.431792 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 28
1963 12:14:16.431900
1964 12:14:16.434976 Final TX Range 1 Vref 28
1965 12:14:16.435082
1966 12:14:16.435179 ==
1967 12:14:16.438356 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 12:14:16.442026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 12:14:16.442153 ==
1970 12:14:16.442256
1971 12:14:16.445008
1972 12:14:16.445122 TX Vref Scan disable
1973 12:14:16.448193 == TX Byte 0 ==
1974 12:14:16.451526 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1975 12:14:16.458569 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1976 12:14:16.458654 == TX Byte 1 ==
1977 12:14:16.461911 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1978 12:14:16.468679 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1979 12:14:16.468765
1980 12:14:16.468832 [DATLAT]
1981 12:14:16.468894 Freq=800, CH1 RK1
1982 12:14:16.468960
1983 12:14:16.471887 DATLAT Default: 0xa
1984 12:14:16.471972 0, 0xFFFF, sum = 0
1985 12:14:16.475085 1, 0xFFFF, sum = 0
1986 12:14:16.475170 2, 0xFFFF, sum = 0
1987 12:14:16.478272 3, 0xFFFF, sum = 0
1988 12:14:16.478385 4, 0xFFFF, sum = 0
1989 12:14:16.481542 5, 0xFFFF, sum = 0
1990 12:14:16.484946 6, 0xFFFF, sum = 0
1991 12:14:16.485055 7, 0xFFFF, sum = 0
1992 12:14:16.488267 8, 0xFFFF, sum = 0
1993 12:14:16.488353 9, 0x0, sum = 1
1994 12:14:16.488427 10, 0x0, sum = 2
1995 12:14:16.491582 11, 0x0, sum = 3
1996 12:14:16.491663 12, 0x0, sum = 4
1997 12:14:16.494758 best_step = 10
1998 12:14:16.494835
1999 12:14:16.494943 ==
2000 12:14:16.498249 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 12:14:16.501456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 12:14:16.501536 ==
2003 12:14:16.504826 RX Vref Scan: 0
2004 12:14:16.504906
2005 12:14:16.504977 RX Vref 0 -> 0, step: 1
2006 12:14:16.505041
2007 12:14:16.508156 RX Delay -95 -> 252, step: 8
2008 12:14:16.515186 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2009 12:14:16.518502 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2010 12:14:16.521551 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2011 12:14:16.524864 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2012 12:14:16.528164 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2013 12:14:16.534699 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2014 12:14:16.538627 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2015 12:14:16.541983 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2016 12:14:16.545263 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2017 12:14:16.548583 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2018 12:14:16.555412 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2019 12:14:16.558662 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2020 12:14:16.561852 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2021 12:14:16.565075 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2022 12:14:16.568248 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2023 12:14:16.574905 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2024 12:14:16.575039 ==
2025 12:14:16.578123 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 12:14:16.581538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 12:14:16.581646 ==
2028 12:14:16.581761 DQS Delay:
2029 12:14:16.585443 DQS0 = 0, DQS1 = 0
2030 12:14:16.585547 DQM Delay:
2031 12:14:16.588838 DQM0 = 80, DQM1 = 75
2032 12:14:16.588943 DQ Delay:
2033 12:14:16.592052 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2034 12:14:16.595283 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2035 12:14:16.598593 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2036 12:14:16.601868 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2037 12:14:16.601954
2038 12:14:16.602041
2039 12:14:16.608490 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2040 12:14:16.611867 CH1 RK1: MR19=606, MR18=1E29
2041 12:14:16.618989 CH1_RK1: MR19=0x606, MR18=0x1E29, DQSOSC=399, MR23=63, INC=92, DEC=61
2042 12:14:16.622156 [RxdqsGatingPostProcess] freq 800
2043 12:14:16.628585 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 12:14:16.628676 Pre-setting of DQS Precalculation
2045 12:14:16.635086 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 12:14:16.642256 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 12:14:16.648958 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 12:14:16.649072
2049 12:14:16.649174
2050 12:14:16.652284 [Calibration Summary] 1600 Mbps
2051 12:14:16.655764 CH 0, Rank 0
2052 12:14:16.655847 SW Impedance : PASS
2053 12:14:16.658649 DUTY Scan : NO K
2054 12:14:16.658735 ZQ Calibration : PASS
2055 12:14:16.662408 Jitter Meter : NO K
2056 12:14:16.665466 CBT Training : PASS
2057 12:14:16.665550 Write leveling : PASS
2058 12:14:16.668557 RX DQS gating : PASS
2059 12:14:16.672483 RX DQ/DQS(RDDQC) : PASS
2060 12:14:16.672578 TX DQ/DQS : PASS
2061 12:14:16.675685 RX DATLAT : PASS
2062 12:14:16.678908 RX DQ/DQS(Engine): PASS
2063 12:14:16.679020 TX OE : NO K
2064 12:14:16.682208 All Pass.
2065 12:14:16.682296
2066 12:14:16.682393 CH 0, Rank 1
2067 12:14:16.685597 SW Impedance : PASS
2068 12:14:16.685678 DUTY Scan : NO K
2069 12:14:16.688855 ZQ Calibration : PASS
2070 12:14:16.692108 Jitter Meter : NO K
2071 12:14:16.692216 CBT Training : PASS
2072 12:14:16.695386 Write leveling : PASS
2073 12:14:16.695463 RX DQS gating : PASS
2074 12:14:16.698750 RX DQ/DQS(RDDQC) : PASS
2075 12:14:16.702043 TX DQ/DQS : PASS
2076 12:14:16.702124 RX DATLAT : PASS
2077 12:14:16.705296 RX DQ/DQS(Engine): PASS
2078 12:14:16.708678 TX OE : NO K
2079 12:14:16.708762 All Pass.
2080 12:14:16.708828
2081 12:14:16.708888 CH 1, Rank 0
2082 12:14:16.712616 SW Impedance : PASS
2083 12:14:16.715933 DUTY Scan : NO K
2084 12:14:16.716016 ZQ Calibration : PASS
2085 12:14:16.719224 Jitter Meter : NO K
2086 12:14:16.722017 CBT Training : PASS
2087 12:14:16.722100 Write leveling : PASS
2088 12:14:16.725778 RX DQS gating : PASS
2089 12:14:16.729001 RX DQ/DQS(RDDQC) : PASS
2090 12:14:16.729116 TX DQ/DQS : PASS
2091 12:14:16.731920 RX DATLAT : PASS
2092 12:14:16.735708 RX DQ/DQS(Engine): PASS
2093 12:14:16.735792 TX OE : NO K
2094 12:14:16.735859 All Pass.
2095 12:14:16.739064
2096 12:14:16.739146 CH 1, Rank 1
2097 12:14:16.742243 SW Impedance : PASS
2098 12:14:16.742328 DUTY Scan : NO K
2099 12:14:16.745471 ZQ Calibration : PASS
2100 12:14:16.745555 Jitter Meter : NO K
2101 12:14:16.748681 CBT Training : PASS
2102 12:14:16.751986 Write leveling : PASS
2103 12:14:16.752070 RX DQS gating : PASS
2104 12:14:16.755235 RX DQ/DQS(RDDQC) : PASS
2105 12:14:16.758607 TX DQ/DQS : PASS
2106 12:14:16.758691 RX DATLAT : PASS
2107 12:14:16.761835 RX DQ/DQS(Engine): PASS
2108 12:14:16.765682 TX OE : NO K
2109 12:14:16.765767 All Pass.
2110 12:14:16.765833
2111 12:14:16.768716 DramC Write-DBI off
2112 12:14:16.768831 PER_BANK_REFRESH: Hybrid Mode
2113 12:14:16.772373 TX_TRACKING: ON
2114 12:14:16.775518 [GetDramInforAfterCalByMRR] Vendor 6.
2115 12:14:16.778722 [GetDramInforAfterCalByMRR] Revision 606.
2116 12:14:16.782027 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 12:14:16.782136 MR0 0x3b3b
2118 12:14:16.785305 MR8 0x5151
2119 12:14:16.788611 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 12:14:16.788713
2121 12:14:16.788805 MR0 0x3b3b
2122 12:14:16.788899 MR8 0x5151
2123 12:14:16.795239 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 12:14:16.795354
2125 12:14:16.801802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 12:14:16.805123 [FAST_K] Save calibration result to emmc
2127 12:14:16.808964 [FAST_K] Save calibration result to emmc
2128 12:14:16.812257 dram_init: config_dvfs: 1
2129 12:14:16.815578 dramc_set_vcore_voltage set vcore to 662500
2130 12:14:16.819070 Read voltage for 1200, 2
2131 12:14:16.819174 Vio18 = 0
2132 12:14:16.822253 Vcore = 662500
2133 12:14:16.822356 Vdram = 0
2134 12:14:16.822448 Vddq = 0
2135 12:14:16.822537 Vmddr = 0
2136 12:14:16.828944 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 12:14:16.835121 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 12:14:16.835208 MEM_TYPE=3, freq_sel=15
2139 12:14:16.838654 sv_algorithm_assistance_LP4_1600
2140 12:14:16.842047 ============ PULL DRAM RESETB DOWN ============
2141 12:14:16.848558 ========== PULL DRAM RESETB DOWN end =========
2142 12:14:16.851772 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 12:14:16.855044 ===================================
2144 12:14:16.858300 LPDDR4 DRAM CONFIGURATION
2145 12:14:16.861705 ===================================
2146 12:14:16.861783 EX_ROW_EN[0] = 0x0
2147 12:14:16.864933 EX_ROW_EN[1] = 0x0
2148 12:14:16.865013 LP4Y_EN = 0x0
2149 12:14:16.868239 WORK_FSP = 0x0
2150 12:14:16.872136 WL = 0x4
2151 12:14:16.872219 RL = 0x4
2152 12:14:16.875275 BL = 0x2
2153 12:14:16.875355 RPST = 0x0
2154 12:14:16.878575 RD_PRE = 0x0
2155 12:14:16.878656 WR_PRE = 0x1
2156 12:14:16.881706 WR_PST = 0x0
2157 12:14:16.881780 DBI_WR = 0x0
2158 12:14:16.885209 DBI_RD = 0x0
2159 12:14:16.885286 OTF = 0x1
2160 12:14:16.888271 ===================================
2161 12:14:16.891587 ===================================
2162 12:14:16.895000 ANA top config
2163 12:14:16.898251 ===================================
2164 12:14:16.898336 DLL_ASYNC_EN = 0
2165 12:14:16.902132 ALL_SLAVE_EN = 0
2166 12:14:16.905468 NEW_RANK_MODE = 1
2167 12:14:16.908148 DLL_IDLE_MODE = 1
2168 12:14:16.908223 LP45_APHY_COMB_EN = 1
2169 12:14:16.912145 TX_ODT_DIS = 1
2170 12:14:16.914847 NEW_8X_MODE = 1
2171 12:14:16.918197 ===================================
2172 12:14:16.921744 ===================================
2173 12:14:16.925020 data_rate = 2400
2174 12:14:16.928341 CKR = 1
2175 12:14:16.931580 DQ_P2S_RATIO = 8
2176 12:14:16.931657 ===================================
2177 12:14:16.935443 CA_P2S_RATIO = 8
2178 12:14:16.938576 DQ_CA_OPEN = 0
2179 12:14:16.941743 DQ_SEMI_OPEN = 0
2180 12:14:16.945103 CA_SEMI_OPEN = 0
2181 12:14:16.948957 CA_FULL_RATE = 0
2182 12:14:16.949038 DQ_CKDIV4_EN = 0
2183 12:14:16.952116 CA_CKDIV4_EN = 0
2184 12:14:16.955261 CA_PREDIV_EN = 0
2185 12:14:16.958458 PH8_DLY = 17
2186 12:14:16.961701 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 12:14:16.964938 DQ_AAMCK_DIV = 4
2188 12:14:16.965017 CA_AAMCK_DIV = 4
2189 12:14:16.968209 CA_ADMCK_DIV = 4
2190 12:14:16.971615 DQ_TRACK_CA_EN = 0
2191 12:14:16.975513 CA_PICK = 1200
2192 12:14:16.978656 CA_MCKIO = 1200
2193 12:14:16.981839 MCKIO_SEMI = 0
2194 12:14:16.985051 PLL_FREQ = 2366
2195 12:14:16.985167 DQ_UI_PI_RATIO = 32
2196 12:14:16.988940 CA_UI_PI_RATIO = 0
2197 12:14:16.992006 ===================================
2198 12:14:16.995090 ===================================
2199 12:14:16.998384 memory_type:LPDDR4
2200 12:14:17.002372 GP_NUM : 10
2201 12:14:17.002452 SRAM_EN : 1
2202 12:14:17.005040 MD32_EN : 0
2203 12:14:17.009071 ===================================
2204 12:14:17.009151 [ANA_INIT] >>>>>>>>>>>>>>
2205 12:14:17.012267 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 12:14:17.015588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 12:14:17.019014 ===================================
2208 12:14:17.022389 data_rate = 2400,PCW = 0X5b00
2209 12:14:17.025584 ===================================
2210 12:14:17.028950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 12:14:17.035611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 12:14:17.041830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 12:14:17.045581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 12:14:17.048891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 12:14:17.052072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 12:14:17.055292 [ANA_INIT] flow start
2217 12:14:17.055397 [ANA_INIT] PLL >>>>>>>>
2218 12:14:17.058694 [ANA_INIT] PLL <<<<<<<<
2219 12:14:17.061937 [ANA_INIT] MIDPI >>>>>>>>
2220 12:14:17.062021 [ANA_INIT] MIDPI <<<<<<<<
2221 12:14:17.065183 [ANA_INIT] DLL >>>>>>>>
2222 12:14:17.068537 [ANA_INIT] DLL <<<<<<<<
2223 12:14:17.068621 [ANA_INIT] flow end
2224 12:14:17.075110 ============ LP4 DIFF to SE enter ============
2225 12:14:17.078499 ============ LP4 DIFF to SE exit ============
2226 12:14:17.078583 [ANA_INIT] <<<<<<<<<<<<<
2227 12:14:17.081831 [Flow] Enable top DCM control >>>>>
2228 12:14:17.085109 [Flow] Enable top DCM control <<<<<
2229 12:14:17.088890 Enable DLL master slave shuffle
2230 12:14:17.095154 ==============================================================
2231 12:14:17.095241 Gating Mode config
2232 12:14:17.102320 ==============================================================
2233 12:14:17.105635 Config description:
2234 12:14:17.115042 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 12:14:17.122202 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 12:14:17.125543 SELPH_MODE 0: By rank 1: By Phase
2237 12:14:17.132031 ==============================================================
2238 12:14:17.135283 GAT_TRACK_EN = 1
2239 12:14:17.138569 RX_GATING_MODE = 2
2240 12:14:17.138681 RX_GATING_TRACK_MODE = 2
2241 12:14:17.141926 SELPH_MODE = 1
2242 12:14:17.145158 PICG_EARLY_EN = 1
2243 12:14:17.148385 VALID_LAT_VALUE = 1
2244 12:14:17.155265 ==============================================================
2245 12:14:17.158287 Enter into Gating configuration >>>>
2246 12:14:17.161594 Exit from Gating configuration <<<<
2247 12:14:17.165031 Enter into DVFS_PRE_config >>>>>
2248 12:14:17.175405 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 12:14:17.178625 Exit from DVFS_PRE_config <<<<<
2250 12:14:17.181903 Enter into PICG configuration >>>>
2251 12:14:17.185250 Exit from PICG configuration <<<<
2252 12:14:17.188633 [RX_INPUT] configuration >>>>>
2253 12:14:17.191998 [RX_INPUT] configuration <<<<<
2254 12:14:17.195267 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 12:14:17.201668 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 12:14:17.208698 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 12:14:17.211841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 12:14:17.218449 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 12:14:17.224952 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 12:14:17.228270 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 12:14:17.231660 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 12:14:17.238836 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 12:14:17.242044 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 12:14:17.245260 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 12:14:17.252005 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 12:14:17.255165 ===================================
2267 12:14:17.255276 LPDDR4 DRAM CONFIGURATION
2268 12:14:17.258467 ===================================
2269 12:14:17.262238 EX_ROW_EN[0] = 0x0
2270 12:14:17.262345 EX_ROW_EN[1] = 0x0
2271 12:14:17.265487 LP4Y_EN = 0x0
2272 12:14:17.265591 WORK_FSP = 0x0
2273 12:14:17.268759 WL = 0x4
2274 12:14:17.272097 RL = 0x4
2275 12:14:17.272179 BL = 0x2
2276 12:14:17.275504 RPST = 0x0
2277 12:14:17.275584 RD_PRE = 0x0
2278 12:14:17.278899 WR_PRE = 0x1
2279 12:14:17.279000 WR_PST = 0x0
2280 12:14:17.282182 DBI_WR = 0x0
2281 12:14:17.282257 DBI_RD = 0x0
2282 12:14:17.285426 OTF = 0x1
2283 12:14:17.288705 ===================================
2284 12:14:17.292010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 12:14:17.295271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 12:14:17.299031 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 12:14:17.302404 ===================================
2288 12:14:17.305580 LPDDR4 DRAM CONFIGURATION
2289 12:14:17.308700 ===================================
2290 12:14:17.312376 EX_ROW_EN[0] = 0x10
2291 12:14:17.312485 EX_ROW_EN[1] = 0x0
2292 12:14:17.315513 LP4Y_EN = 0x0
2293 12:14:17.315614 WORK_FSP = 0x0
2294 12:14:17.318890 WL = 0x4
2295 12:14:17.318995 RL = 0x4
2296 12:14:17.322153 BL = 0x2
2297 12:14:17.322255 RPST = 0x0
2298 12:14:17.325485 RD_PRE = 0x0
2299 12:14:17.325589 WR_PRE = 0x1
2300 12:14:17.328733 WR_PST = 0x0
2301 12:14:17.328835 DBI_WR = 0x0
2302 12:14:17.332583 DBI_RD = 0x0
2303 12:14:17.332689 OTF = 0x1
2304 12:14:17.335915 ===================================
2305 12:14:17.342569 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 12:14:17.342675 ==
2307 12:14:17.345956 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 12:14:17.352552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 12:14:17.352662 ==
2310 12:14:17.352758 [Duty_Offset_Calibration]
2311 12:14:17.355890 B0:2 B1:-1 CA:1
2312 12:14:17.355995
2313 12:14:17.359123 [DutyScan_Calibration_Flow] k_type=0
2314 12:14:17.366670
2315 12:14:17.366781 ==CLK 0==
2316 12:14:17.370047 Final CLK duty delay cell = -4
2317 12:14:17.373238 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2318 12:14:17.376601 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2319 12:14:17.379888 [-4] AVG Duty = 4953%(X100)
2320 12:14:17.379988
2321 12:14:17.383166 CH0 CLK Duty spec in!! Max-Min= 156%
2322 12:14:17.386571 [DutyScan_Calibration_Flow] ====Done====
2323 12:14:17.386680
2324 12:14:17.389925 [DutyScan_Calibration_Flow] k_type=1
2325 12:14:17.406123
2326 12:14:17.406237 ==DQS 0 ==
2327 12:14:17.409394 Final DQS duty delay cell = 0
2328 12:14:17.412648 [0] MAX Duty = 5125%(X100), DQS PI = 48
2329 12:14:17.415896 [0] MIN Duty = 5000%(X100), DQS PI = 14
2330 12:14:17.415998 [0] AVG Duty = 5062%(X100)
2331 12:14:17.419146
2332 12:14:17.419244 ==DQS 1 ==
2333 12:14:17.422818 Final DQS duty delay cell = -4
2334 12:14:17.426094 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2335 12:14:17.429505 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2336 12:14:17.432852 [-4] AVG Duty = 5062%(X100)
2337 12:14:17.432957
2338 12:14:17.436151 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2339 12:14:17.436252
2340 12:14:17.439474 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2341 12:14:17.442886 [DutyScan_Calibration_Flow] ====Done====
2342 12:14:17.442993
2343 12:14:17.445539 [DutyScan_Calibration_Flow] k_type=3
2344 12:14:17.462533
2345 12:14:17.462643 ==DQM 0 ==
2346 12:14:17.465674 Final DQM duty delay cell = 0
2347 12:14:17.469485 [0] MAX Duty = 5031%(X100), DQS PI = 54
2348 12:14:17.472580 [0] MIN Duty = 4907%(X100), DQS PI = 2
2349 12:14:17.472685 [0] AVG Duty = 4969%(X100)
2350 12:14:17.475879
2351 12:14:17.475977 ==DQM 1 ==
2352 12:14:17.479157 Final DQM duty delay cell = 0
2353 12:14:17.482394 [0] MAX Duty = 5156%(X100), DQS PI = 62
2354 12:14:17.485745 [0] MIN Duty = 4969%(X100), DQS PI = 10
2355 12:14:17.489029 [0] AVG Duty = 5062%(X100)
2356 12:14:17.489132
2357 12:14:17.492375 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2358 12:14:17.492476
2359 12:14:17.495651 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2360 12:14:17.498926 [DutyScan_Calibration_Flow] ====Done====
2361 12:14:17.499030
2362 12:14:17.502125 [DutyScan_Calibration_Flow] k_type=2
2363 12:14:17.518087
2364 12:14:17.518190 ==DQ 0 ==
2365 12:14:17.521495 Final DQ duty delay cell = -4
2366 12:14:17.525298 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2367 12:14:17.528411 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2368 12:14:17.531947 [-4] AVG Duty = 4969%(X100)
2369 12:14:17.532049
2370 12:14:17.532145 ==DQ 1 ==
2371 12:14:17.534983 Final DQ duty delay cell = 0
2372 12:14:17.538167 [0] MAX Duty = 5031%(X100), DQS PI = 18
2373 12:14:17.541542 [0] MIN Duty = 4907%(X100), DQS PI = 46
2374 12:14:17.544986 [0] AVG Duty = 4969%(X100)
2375 12:14:17.545099
2376 12:14:17.548118 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2377 12:14:17.548215
2378 12:14:17.551440 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2379 12:14:17.554841 [DutyScan_Calibration_Flow] ====Done====
2380 12:14:17.554942 ==
2381 12:14:17.558123 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 12:14:17.561474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 12:14:17.561581 ==
2384 12:14:17.564845 [Duty_Offset_Calibration]
2385 12:14:17.564951 B0:1 B1:1 CA:2
2386 12:14:17.565046
2387 12:14:17.568058 [DutyScan_Calibration_Flow] k_type=0
2388 12:14:17.578598
2389 12:14:17.578709 ==CLK 0==
2390 12:14:17.581996 Final CLK duty delay cell = 0
2391 12:14:17.585292 [0] MAX Duty = 5094%(X100), DQS PI = 56
2392 12:14:17.588591 [0] MIN Duty = 4969%(X100), DQS PI = 8
2393 12:14:17.588697 [0] AVG Duty = 5031%(X100)
2394 12:14:17.591782
2395 12:14:17.595124 CH1 CLK Duty spec in!! Max-Min= 125%
2396 12:14:17.598413 [DutyScan_Calibration_Flow] ====Done====
2397 12:14:17.598522
2398 12:14:17.601710 [DutyScan_Calibration_Flow] k_type=1
2399 12:14:17.618122
2400 12:14:17.618244 ==DQS 0 ==
2401 12:14:17.621407 Final DQS duty delay cell = 0
2402 12:14:17.624746 [0] MAX Duty = 5031%(X100), DQS PI = 50
2403 12:14:17.628127 [0] MIN Duty = 4875%(X100), DQS PI = 18
2404 12:14:17.631451 [0] AVG Duty = 4953%(X100)
2405 12:14:17.631620
2406 12:14:17.631730 ==DQS 1 ==
2407 12:14:17.634696 Final DQS duty delay cell = 0
2408 12:14:17.637740 [0] MAX Duty = 5062%(X100), DQS PI = 26
2409 12:14:17.640912 [0] MIN Duty = 4907%(X100), DQS PI = 0
2410 12:14:17.644811 [0] AVG Duty = 4984%(X100)
2411 12:14:17.644934
2412 12:14:17.648136 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2413 12:14:17.648237
2414 12:14:17.651521 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2415 12:14:17.654159 [DutyScan_Calibration_Flow] ====Done====
2416 12:14:17.654278
2417 12:14:17.657948 [DutyScan_Calibration_Flow] k_type=3
2418 12:14:17.674259
2419 12:14:17.674361 ==DQM 0 ==
2420 12:14:17.678259 Final DQM duty delay cell = 0
2421 12:14:17.681215 [0] MAX Duty = 5093%(X100), DQS PI = 6
2422 12:14:17.684529 [0] MIN Duty = 4907%(X100), DQS PI = 16
2423 12:14:17.684640 [0] AVG Duty = 5000%(X100)
2424 12:14:17.687773
2425 12:14:17.687843 ==DQM 1 ==
2426 12:14:17.691063 Final DQM duty delay cell = 0
2427 12:14:17.694418 [0] MAX Duty = 5156%(X100), DQS PI = 30
2428 12:14:17.697661 [0] MIN Duty = 4938%(X100), DQS PI = 54
2429 12:14:17.697755 [0] AVG Duty = 5047%(X100)
2430 12:14:17.701015
2431 12:14:17.704239 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2432 12:14:17.704323
2433 12:14:17.707604 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2434 12:14:17.710834 [DutyScan_Calibration_Flow] ====Done====
2435 12:14:17.710917
2436 12:14:17.714124 [DutyScan_Calibration_Flow] k_type=2
2437 12:14:17.730139
2438 12:14:17.730224 ==DQ 0 ==
2439 12:14:17.733413 Final DQ duty delay cell = 0
2440 12:14:17.736651 [0] MAX Duty = 5124%(X100), DQS PI = 50
2441 12:14:17.739882 [0] MIN Duty = 4938%(X100), DQS PI = 62
2442 12:14:17.739966 [0] AVG Duty = 5031%(X100)
2443 12:14:17.743685
2444 12:14:17.743771 ==DQ 1 ==
2445 12:14:17.746898 Final DQ duty delay cell = -4
2446 12:14:17.750121 [-4] MAX Duty = 4969%(X100), DQS PI = 10
2447 12:14:17.753766 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2448 12:14:17.753850 [-4] AVG Duty = 4938%(X100)
2449 12:14:17.756717
2450 12:14:17.759955 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2451 12:14:17.760040
2452 12:14:17.763255 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2453 12:14:17.766531 [DutyScan_Calibration_Flow] ====Done====
2454 12:14:17.770407 nWR fixed to 30
2455 12:14:17.770491 [ModeRegInit_LP4] CH0 RK0
2456 12:14:17.773667 [ModeRegInit_LP4] CH0 RK1
2457 12:14:17.777011 [ModeRegInit_LP4] CH1 RK0
2458 12:14:17.777095 [ModeRegInit_LP4] CH1 RK1
2459 12:14:17.780211 match AC timing 7
2460 12:14:17.783396 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 12:14:17.787045 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 12:14:17.793635 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 12:14:17.797039 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 12:14:17.803577 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 12:14:17.803658 ==
2466 12:14:17.806896 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 12:14:17.810105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 12:14:17.810217 ==
2469 12:14:17.816754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 12:14:17.819984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 12:14:17.830506 [CA 0] Center 40 (10~71) winsize 62
2472 12:14:17.833784 [CA 1] Center 39 (9~70) winsize 62
2473 12:14:17.837131 [CA 2] Center 36 (6~67) winsize 62
2474 12:14:17.840445 [CA 3] Center 36 (5~67) winsize 63
2475 12:14:17.843706 [CA 4] Center 35 (5~65) winsize 61
2476 12:14:17.846892 [CA 5] Center 34 (4~64) winsize 61
2477 12:14:17.846995
2478 12:14:17.850201 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2479 12:14:17.850304
2480 12:14:17.853492 [CATrainingPosCal] consider 1 rank data
2481 12:14:17.856780 u2DelayCellTimex100 = 270/100 ps
2482 12:14:17.860491 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2483 12:14:17.867102 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2484 12:14:17.870409 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2485 12:14:17.873619 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2486 12:14:17.876830 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2487 12:14:17.880098 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2488 12:14:17.880202
2489 12:14:17.883893 CA PerBit enable=1, Macro0, CA PI delay=34
2490 12:14:17.883967
2491 12:14:17.886982 [CBTSetCACLKResult] CA Dly = 34
2492 12:14:17.887082 CS Dly: 7 (0~38)
2493 12:14:17.887176 ==
2494 12:14:17.890152 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 12:14:17.897186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 12:14:17.897291 ==
2497 12:14:17.900564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 12:14:17.906913 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2499 12:14:17.916180 [CA 0] Center 39 (9~70) winsize 62
2500 12:14:17.919460 [CA 1] Center 40 (10~70) winsize 61
2501 12:14:17.922806 [CA 2] Center 36 (6~67) winsize 62
2502 12:14:17.926085 [CA 3] Center 36 (5~67) winsize 63
2503 12:14:17.929331 [CA 4] Center 34 (4~65) winsize 62
2504 12:14:17.932627 [CA 5] Center 34 (4~64) winsize 61
2505 12:14:17.932729
2506 12:14:17.935935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 12:14:17.936015
2508 12:14:17.939326 [CATrainingPosCal] consider 2 rank data
2509 12:14:17.942640 u2DelayCellTimex100 = 270/100 ps
2510 12:14:17.945950 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 12:14:17.953025 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2512 12:14:17.956326 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2513 12:14:17.959727 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2514 12:14:17.962874 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2515 12:14:17.966099 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2516 12:14:17.966201
2517 12:14:17.969929 CA PerBit enable=1, Macro0, CA PI delay=34
2518 12:14:17.970033
2519 12:14:17.973129 [CBTSetCACLKResult] CA Dly = 34
2520 12:14:17.973231 CS Dly: 8 (0~41)
2521 12:14:17.973325
2522 12:14:17.976076 ----->DramcWriteLeveling(PI) begin...
2523 12:14:17.979960 ==
2524 12:14:17.983257 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 12:14:17.986529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 12:14:17.986635 ==
2527 12:14:17.989748 Write leveling (Byte 0): 31 => 31
2528 12:14:17.992870 Write leveling (Byte 1): 29 => 29
2529 12:14:17.996511 DramcWriteLeveling(PI) end<-----
2530 12:14:17.996626
2531 12:14:17.996727 ==
2532 12:14:17.999752 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 12:14:18.003101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 12:14:18.003208 ==
2535 12:14:18.006420 [Gating] SW mode calibration
2536 12:14:18.012953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 12:14:18.016255 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 12:14:18.022775 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:14:18.026147 0 15 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2540 12:14:18.029411 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2541 12:14:18.036595 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 12:14:18.039808 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 12:14:18.043104 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 12:14:18.049665 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 12:14:18.053001 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 12:14:18.056110 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
2547 12:14:18.063128 1 0 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2548 12:14:18.066303 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:14:18.069723 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:14:18.076209 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:14:18.079470 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 12:14:18.083022 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 12:14:18.089375 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 12:14:18.092619 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2555 12:14:18.096426 1 1 4 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2556 12:14:18.102672 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:14:18.105926 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:14:18.109917 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:14:18.116223 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 12:14:18.119455 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 12:14:18.122777 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:14:18.126030 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 12:14:18.132749 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 12:14:18.136097 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:14:18.139488 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:14:18.146069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:14:18.149372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:14:18.152740 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:14:18.159365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:14:18.162597 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:14:18.165795 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:14:18.173098 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:14:18.176385 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:14:18.179708 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:14:18.186038 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:14:18.189114 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:14:18.192962 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:14:18.199561 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2579 12:14:18.202660 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2580 12:14:18.205810 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 12:14:18.209614 Total UI for P1: 0, mck2ui 16
2582 12:14:18.212943 best dqsien dly found for B0: ( 1, 4, 2)
2583 12:14:18.216263 Total UI for P1: 0, mck2ui 16
2584 12:14:18.219481 best dqsien dly found for B1: ( 1, 4, 2)
2585 12:14:18.222775 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2586 12:14:18.226148 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2587 12:14:18.226249
2588 12:14:18.229533 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2589 12:14:18.232821 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 12:14:18.236109 [Gating] SW calibration Done
2591 12:14:18.236193 ==
2592 12:14:18.239475 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 12:14:18.245910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 12:14:18.246023 ==
2595 12:14:18.246098 RX Vref Scan: 0
2596 12:14:18.246170
2597 12:14:18.249260 RX Vref 0 -> 0, step: 1
2598 12:14:18.249340
2599 12:14:18.252577 RX Delay -40 -> 252, step: 8
2600 12:14:18.255868 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2601 12:14:18.259217 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2602 12:14:18.262513 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2603 12:14:18.265766 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2604 12:14:18.272766 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2605 12:14:18.275880 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2606 12:14:18.279222 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2607 12:14:18.282639 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2608 12:14:18.286019 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2609 12:14:18.292567 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2610 12:14:18.295727 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2611 12:14:18.299492 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2612 12:14:18.302748 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2613 12:14:18.306010 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2614 12:14:18.312243 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2615 12:14:18.315591 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2616 12:14:18.315707 ==
2617 12:14:18.318865 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 12:14:18.322313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 12:14:18.322414 ==
2620 12:14:18.325559 DQS Delay:
2621 12:14:18.325656 DQS0 = 0, DQS1 = 0
2622 12:14:18.325751 DQM Delay:
2623 12:14:18.328856 DQM0 = 116, DQM1 = 107
2624 12:14:18.328939 DQ Delay:
2625 12:14:18.332061 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2626 12:14:18.336029 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2627 12:14:18.338693 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2628 12:14:18.345970 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2629 12:14:18.346073
2630 12:14:18.346171
2631 12:14:18.346263 ==
2632 12:14:18.349250 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 12:14:18.352525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 12:14:18.352622 ==
2635 12:14:18.352719
2636 12:14:18.352811
2637 12:14:18.355880 TX Vref Scan disable
2638 12:14:18.355978 == TX Byte 0 ==
2639 12:14:18.362282 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2640 12:14:18.365685 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2641 12:14:18.365767 == TX Byte 1 ==
2642 12:14:18.372239 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2643 12:14:18.375610 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2644 12:14:18.375692 ==
2645 12:14:18.378769 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:14:18.381912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:14:18.382015 ==
2648 12:14:18.394808 TX Vref=22, minBit 0, minWin=25, winSum=418
2649 12:14:18.398075 TX Vref=24, minBit 7, minWin=25, winSum=423
2650 12:14:18.401353 TX Vref=26, minBit 5, minWin=25, winSum=427
2651 12:14:18.405133 TX Vref=28, minBit 1, minWin=26, winSum=432
2652 12:14:18.408254 TX Vref=30, minBit 4, minWin=26, winSum=437
2653 12:14:18.414645 TX Vref=32, minBit 0, minWin=26, winSum=433
2654 12:14:18.418271 [TxChooseVref] Worse bit 4, Min win 26, Win sum 437, Final Vref 30
2655 12:14:18.418358
2656 12:14:18.421541 Final TX Range 1 Vref 30
2657 12:14:18.421623
2658 12:14:18.421726 ==
2659 12:14:18.424820 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 12:14:18.428159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 12:14:18.428246 ==
2662 12:14:18.431544
2663 12:14:18.431630
2664 12:14:18.431717 TX Vref Scan disable
2665 12:14:18.434812 == TX Byte 0 ==
2666 12:14:18.438129 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2667 12:14:18.441408 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2668 12:14:18.444691 == TX Byte 1 ==
2669 12:14:18.447940 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2670 12:14:18.451219 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2671 12:14:18.454561
2672 12:14:18.454660 [DATLAT]
2673 12:14:18.454739 Freq=1200, CH0 RK0
2674 12:14:18.454810
2675 12:14:18.457890 DATLAT Default: 0xd
2676 12:14:18.457998 0, 0xFFFF, sum = 0
2677 12:14:18.461705 1, 0xFFFF, sum = 0
2678 12:14:18.461819 2, 0xFFFF, sum = 0
2679 12:14:18.464962 3, 0xFFFF, sum = 0
2680 12:14:18.465046 4, 0xFFFF, sum = 0
2681 12:14:18.468303 5, 0xFFFF, sum = 0
2682 12:14:18.471557 6, 0xFFFF, sum = 0
2683 12:14:18.471638 7, 0xFFFF, sum = 0
2684 12:14:18.474738 8, 0xFFFF, sum = 0
2685 12:14:18.474821 9, 0xFFFF, sum = 0
2686 12:14:18.478077 10, 0xFFFF, sum = 0
2687 12:14:18.478190 11, 0xFFFF, sum = 0
2688 12:14:18.481436 12, 0x0, sum = 1
2689 12:14:18.481545 13, 0x0, sum = 2
2690 12:14:18.484559 14, 0x0, sum = 3
2691 12:14:18.484643 15, 0x0, sum = 4
2692 12:14:18.484712 best_step = 13
2693 12:14:18.484776
2694 12:14:18.488419 ==
2695 12:14:18.491542 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 12:14:18.494877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 12:14:18.494969 ==
2698 12:14:18.495071 RX Vref Scan: 1
2699 12:14:18.495164
2700 12:14:18.498057 Set Vref Range= 32 -> 127
2701 12:14:18.498163
2702 12:14:18.501334 RX Vref 32 -> 127, step: 1
2703 12:14:18.501426
2704 12:14:18.504702 RX Delay -21 -> 252, step: 4
2705 12:14:18.504781
2706 12:14:18.507953 Set Vref, RX VrefLevel [Byte0]: 32
2707 12:14:18.511262 [Byte1]: 32
2708 12:14:18.511384
2709 12:14:18.514801 Set Vref, RX VrefLevel [Byte0]: 33
2710 12:14:18.517781 [Byte1]: 33
2711 12:14:18.517863
2712 12:14:18.521472 Set Vref, RX VrefLevel [Byte0]: 34
2713 12:14:18.524602 [Byte1]: 34
2714 12:14:18.529008
2715 12:14:18.529132 Set Vref, RX VrefLevel [Byte0]: 35
2716 12:14:18.532217 [Byte1]: 35
2717 12:14:18.536821
2718 12:14:18.536928 Set Vref, RX VrefLevel [Byte0]: 36
2719 12:14:18.540251 [Byte1]: 36
2720 12:14:18.545031
2721 12:14:18.545119 Set Vref, RX VrefLevel [Byte0]: 37
2722 12:14:18.548329 [Byte1]: 37
2723 12:14:18.552903
2724 12:14:18.552987 Set Vref, RX VrefLevel [Byte0]: 38
2725 12:14:18.556173 [Byte1]: 38
2726 12:14:18.560829
2727 12:14:18.560913 Set Vref, RX VrefLevel [Byte0]: 39
2728 12:14:18.564091 [Byte1]: 39
2729 12:14:18.568739
2730 12:14:18.568812 Set Vref, RX VrefLevel [Byte0]: 40
2731 12:14:18.572007 [Byte1]: 40
2732 12:14:18.576462
2733 12:14:18.576566 Set Vref, RX VrefLevel [Byte0]: 41
2734 12:14:18.579776 [Byte1]: 41
2735 12:14:18.584311
2736 12:14:18.584386 Set Vref, RX VrefLevel [Byte0]: 42
2737 12:14:18.587790 [Byte1]: 42
2738 12:14:18.592096
2739 12:14:18.592169 Set Vref, RX VrefLevel [Byte0]: 43
2740 12:14:18.596043 [Byte1]: 43
2741 12:14:18.600637
2742 12:14:18.600710 Set Vref, RX VrefLevel [Byte0]: 44
2743 12:14:18.603838 [Byte1]: 44
2744 12:14:18.608458
2745 12:14:18.608553 Set Vref, RX VrefLevel [Byte0]: 45
2746 12:14:18.611826 [Byte1]: 45
2747 12:14:18.616410
2748 12:14:18.616492 Set Vref, RX VrefLevel [Byte0]: 46
2749 12:14:18.619521 [Byte1]: 46
2750 12:14:18.624059
2751 12:14:18.624136 Set Vref, RX VrefLevel [Byte0]: 47
2752 12:14:18.627200 [Byte1]: 47
2753 12:14:18.632187
2754 12:14:18.632294 Set Vref, RX VrefLevel [Byte0]: 48
2755 12:14:18.635137 [Byte1]: 48
2756 12:14:18.639842
2757 12:14:18.639952 Set Vref, RX VrefLevel [Byte0]: 49
2758 12:14:18.643053 [Byte1]: 49
2759 12:14:18.648222
2760 12:14:18.648305 Set Vref, RX VrefLevel [Byte0]: 50
2761 12:14:18.651483 [Byte1]: 50
2762 12:14:18.656036
2763 12:14:18.656109 Set Vref, RX VrefLevel [Byte0]: 51
2764 12:14:18.659233 [Byte1]: 51
2765 12:14:18.663873
2766 12:14:18.663956 Set Vref, RX VrefLevel [Byte0]: 52
2767 12:14:18.667136 [Byte1]: 52
2768 12:14:18.671823
2769 12:14:18.671907 Set Vref, RX VrefLevel [Byte0]: 53
2770 12:14:18.675020 [Byte1]: 53
2771 12:14:18.679494
2772 12:14:18.679577 Set Vref, RX VrefLevel [Byte0]: 54
2773 12:14:18.682798 [Byte1]: 54
2774 12:14:18.687445
2775 12:14:18.687528 Set Vref, RX VrefLevel [Byte0]: 55
2776 12:14:18.690667 [Byte1]: 55
2777 12:14:18.695261
2778 12:14:18.695345 Set Vref, RX VrefLevel [Byte0]: 56
2779 12:14:18.698448 [Byte1]: 56
2780 12:14:18.703136
2781 12:14:18.703219 Set Vref, RX VrefLevel [Byte0]: 57
2782 12:14:18.706420 [Byte1]: 57
2783 12:14:18.711627
2784 12:14:18.711710 Set Vref, RX VrefLevel [Byte0]: 58
2785 12:14:18.714992 [Byte1]: 58
2786 12:14:18.719571
2787 12:14:18.719655 Set Vref, RX VrefLevel [Byte0]: 59
2788 12:14:18.722856 [Byte1]: 59
2789 12:14:18.727164
2790 12:14:18.730484 Set Vref, RX VrefLevel [Byte0]: 60
2791 12:14:18.730574 [Byte1]: 60
2792 12:14:18.734810
2793 12:14:18.734894 Set Vref, RX VrefLevel [Byte0]: 61
2794 12:14:18.738630 [Byte1]: 61
2795 12:14:18.743099
2796 12:14:18.743182 Set Vref, RX VrefLevel [Byte0]: 62
2797 12:14:18.746392 [Byte1]: 62
2798 12:14:18.751122
2799 12:14:18.751206 Set Vref, RX VrefLevel [Byte0]: 63
2800 12:14:18.754469 [Byte1]: 63
2801 12:14:18.758995
2802 12:14:18.759079 Set Vref, RX VrefLevel [Byte0]: 64
2803 12:14:18.762258 [Byte1]: 64
2804 12:14:18.766897
2805 12:14:18.766981 Set Vref, RX VrefLevel [Byte0]: 65
2806 12:14:18.770138 [Byte1]: 65
2807 12:14:18.774830
2808 12:14:18.774914 Set Vref, RX VrefLevel [Byte0]: 66
2809 12:14:18.778104 [Byte1]: 66
2810 12:14:18.782686
2811 12:14:18.782764 Set Vref, RX VrefLevel [Byte0]: 67
2812 12:14:18.786034 [Byte1]: 67
2813 12:14:18.790759
2814 12:14:18.790843 Set Vref, RX VrefLevel [Byte0]: 68
2815 12:14:18.793922 [Byte1]: 68
2816 12:14:18.798435
2817 12:14:18.798519 Set Vref, RX VrefLevel [Byte0]: 69
2818 12:14:18.801580 [Byte1]: 69
2819 12:14:18.806652
2820 12:14:18.806736 Final RX Vref Byte 0 = 55 to rank0
2821 12:14:18.809900 Final RX Vref Byte 1 = 50 to rank0
2822 12:14:18.813253 Final RX Vref Byte 0 = 55 to rank1
2823 12:14:18.816622 Final RX Vref Byte 1 = 50 to rank1==
2824 12:14:18.819940 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 12:14:18.823399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 12:14:18.826695 ==
2827 12:14:18.826779 DQS Delay:
2828 12:14:18.826847 DQS0 = 0, DQS1 = 0
2829 12:14:18.829715 DQM Delay:
2830 12:14:18.829828 DQM0 = 115, DQM1 = 105
2831 12:14:18.832840 DQ Delay:
2832 12:14:18.836709 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2833 12:14:18.839915 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2834 12:14:18.843015 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2835 12:14:18.846372 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2836 12:14:18.846483
2837 12:14:18.846578
2838 12:14:18.853086 [DQSOSCAuto] RK0, (LSB)MR18= 0xfae9, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2839 12:14:18.856295 CH0 RK0: MR19=303, MR18=FAE9
2840 12:14:18.863025 CH0_RK0: MR19=0x303, MR18=0xFAE9, DQSOSC=412, MR23=63, INC=38, DEC=25
2841 12:14:18.863138
2842 12:14:18.866306 ----->DramcWriteLeveling(PI) begin...
2843 12:14:18.866416 ==
2844 12:14:18.869521 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 12:14:18.873549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 12:14:18.873665 ==
2847 12:14:18.876153 Write leveling (Byte 0): 32 => 32
2848 12:14:18.879478 Write leveling (Byte 1): 28 => 28
2849 12:14:18.882820 DramcWriteLeveling(PI) end<-----
2850 12:14:18.882938
2851 12:14:18.883044 ==
2852 12:14:18.886772 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 12:14:18.893326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 12:14:18.893455 ==
2855 12:14:18.893562 [Gating] SW mode calibration
2856 12:14:18.903113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 12:14:18.906202 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 12:14:18.909455 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
2859 12:14:18.916027 0 15 4 | B1->B0 | 2828 3434 | 1 0 | (0 0) (0 0)
2860 12:14:18.920070 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:14:18.923223 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:14:18.929677 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:14:18.932819 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:14:18.936646 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2865 12:14:18.942981 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
2866 12:14:18.946223 1 0 0 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (1 1)
2867 12:14:18.949908 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 12:14:18.956667 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:14:18.959852 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:14:18.963123 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:14:18.969737 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:14:18.973042 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2873 12:14:18.976292 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2874 12:14:18.982875 1 1 0 | B1->B0 | 3231 4040 | 1 0 | (0 0) (0 0)
2875 12:14:18.986130 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2876 12:14:18.989391 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:14:18.995986 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:14:18.999872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:14:19.003137 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:14:19.006298 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:14:19.012573 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2882 12:14:19.016421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2883 12:14:19.019767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 12:14:19.026216 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:14:19.029553 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:14:19.032903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:14:19.039345 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:14:19.043106 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:14:19.046342 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:14:19.052755 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:14:19.055940 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:14:19.059219 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:14:19.065965 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:14:19.069259 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:14:19.072587 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:14:19.079882 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:14:19.083141 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 12:14:19.086328 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 12:14:19.089599 Total UI for P1: 0, mck2ui 16
2900 12:14:19.092863 best dqsien dly found for B0: ( 1, 3, 28)
2901 12:14:19.096183 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 12:14:19.099497 Total UI for P1: 0, mck2ui 16
2903 12:14:19.102831 best dqsien dly found for B1: ( 1, 4, 0)
2904 12:14:19.106099 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2905 12:14:19.112609 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2906 12:14:19.112693
2907 12:14:19.116470 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2908 12:14:19.119629 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2909 12:14:19.123112 [Gating] SW calibration Done
2910 12:14:19.123220 ==
2911 12:14:19.126269 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:14:19.129513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:14:19.129599 ==
2914 12:14:19.129672 RX Vref Scan: 0
2915 12:14:19.129738
2916 12:14:19.132992 RX Vref 0 -> 0, step: 1
2917 12:14:19.133071
2918 12:14:19.136197 RX Delay -40 -> 252, step: 8
2919 12:14:19.139514 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2920 12:14:19.142830 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2921 12:14:19.149564 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2922 12:14:19.152770 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2923 12:14:19.155947 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2924 12:14:19.159118 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2925 12:14:19.162977 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2926 12:14:19.169608 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 12:14:19.172896 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2928 12:14:19.176070 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2929 12:14:19.179472 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2930 12:14:19.182721 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2931 12:14:19.189275 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2932 12:14:19.192576 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2933 12:14:19.195894 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2934 12:14:19.199090 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2935 12:14:19.199176 ==
2936 12:14:19.202490 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 12:14:19.205791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 12:14:19.209114 ==
2939 12:14:19.209198 DQS Delay:
2940 12:14:19.209266 DQS0 = 0, DQS1 = 0
2941 12:14:19.213015 DQM Delay:
2942 12:14:19.213126 DQM0 = 116, DQM1 = 106
2943 12:14:19.216194 DQ Delay:
2944 12:14:19.219502 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2945 12:14:19.222638 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2946 12:14:19.225896 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2947 12:14:19.229254 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2948 12:14:19.229339
2949 12:14:19.229406
2950 12:14:19.229481 ==
2951 12:14:19.232484 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 12:14:19.235752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 12:14:19.235838 ==
2954 12:14:19.235905
2955 12:14:19.235967
2956 12:14:19.239043 TX Vref Scan disable
2957 12:14:19.242428 == TX Byte 0 ==
2958 12:14:19.245718 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2959 12:14:19.249442 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2960 12:14:19.252529 == TX Byte 1 ==
2961 12:14:19.256166 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2962 12:14:19.259234 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2963 12:14:19.259341 ==
2964 12:14:19.262442 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 12:14:19.266325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 12:14:19.269567 ==
2967 12:14:19.279464 TX Vref=22, minBit 0, minWin=25, winSum=420
2968 12:14:19.282867 TX Vref=24, minBit 1, minWin=26, winSum=426
2969 12:14:19.286047 TX Vref=26, minBit 0, minWin=26, winSum=429
2970 12:14:19.289372 TX Vref=28, minBit 6, minWin=26, winSum=434
2971 12:14:19.292546 TX Vref=30, minBit 3, minWin=26, winSum=431
2972 12:14:19.299791 TX Vref=32, minBit 1, minWin=26, winSum=436
2973 12:14:19.303093 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 32
2974 12:14:19.303176
2975 12:14:19.306205 Final TX Range 1 Vref 32
2976 12:14:19.306318
2977 12:14:19.306416 ==
2978 12:14:19.309445 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 12:14:19.312645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 12:14:19.312752 ==
2981 12:14:19.315934
2982 12:14:19.316039
2983 12:14:19.316145 TX Vref Scan disable
2984 12:14:19.319375 == TX Byte 0 ==
2985 12:14:19.322713 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 12:14:19.329215 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 12:14:19.329327 == TX Byte 1 ==
2988 12:14:19.332453 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2989 12:14:19.339092 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2990 12:14:19.339204
2991 12:14:19.339303 [DATLAT]
2992 12:14:19.339415 Freq=1200, CH0 RK1
2993 12:14:19.339507
2994 12:14:19.342472 DATLAT Default: 0xd
2995 12:14:19.345632 0, 0xFFFF, sum = 0
2996 12:14:19.345749 1, 0xFFFF, sum = 0
2997 12:14:19.349646 2, 0xFFFF, sum = 0
2998 12:14:19.349731 3, 0xFFFF, sum = 0
2999 12:14:19.352762 4, 0xFFFF, sum = 0
3000 12:14:19.352868 5, 0xFFFF, sum = 0
3001 12:14:19.355924 6, 0xFFFF, sum = 0
3002 12:14:19.356002 7, 0xFFFF, sum = 0
3003 12:14:19.359086 8, 0xFFFF, sum = 0
3004 12:14:19.359172 9, 0xFFFF, sum = 0
3005 12:14:19.362306 10, 0xFFFF, sum = 0
3006 12:14:19.362387 11, 0xFFFF, sum = 0
3007 12:14:19.365555 12, 0x0, sum = 1
3008 12:14:19.365670 13, 0x0, sum = 2
3009 12:14:19.368833 14, 0x0, sum = 3
3010 12:14:19.368946 15, 0x0, sum = 4
3011 12:14:19.372489 best_step = 13
3012 12:14:19.372610
3013 12:14:19.372708 ==
3014 12:14:19.375781 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 12:14:19.379053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 12:14:19.379165 ==
3017 12:14:19.379270 RX Vref Scan: 0
3018 12:14:19.379370
3019 12:14:19.382403 RX Vref 0 -> 0, step: 1
3020 12:14:19.382488
3021 12:14:19.385638 RX Delay -21 -> 252, step: 4
3022 12:14:19.389005 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3023 12:14:19.395592 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3024 12:14:19.398988 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3025 12:14:19.402105 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3026 12:14:19.405400 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3027 12:14:19.408797 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
3028 12:14:19.416001 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3029 12:14:19.419402 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3030 12:14:19.422530 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3031 12:14:19.425729 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3032 12:14:19.428974 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3033 12:14:19.435488 iDelay=195, Bit 11, Center 92 (27 ~ 158) 132
3034 12:14:19.438744 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3035 12:14:19.442035 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3036 12:14:19.445190 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3037 12:14:19.448543 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3038 12:14:19.451920 ==
3039 12:14:19.455222 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 12:14:19.458386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 12:14:19.458465 ==
3042 12:14:19.458535 DQS Delay:
3043 12:14:19.461633 DQS0 = 0, DQS1 = 0
3044 12:14:19.461718 DQM Delay:
3045 12:14:19.465406 DQM0 = 114, DQM1 = 104
3046 12:14:19.465483 DQ Delay:
3047 12:14:19.468857 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3048 12:14:19.472041 DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122
3049 12:14:19.475257 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =92
3050 12:14:19.478504 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3051 12:14:19.478583
3052 12:14:19.478667
3053 12:14:19.488949 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3054 12:14:19.489036 CH0 RK1: MR19=403, MR18=2F3
3055 12:14:19.494908 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3056 12:14:19.498308 [RxdqsGatingPostProcess] freq 1200
3057 12:14:19.504900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 12:14:19.508760 best DQS0 dly(2T, 0.5T) = (0, 12)
3059 12:14:19.512011 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 12:14:19.515396 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3061 12:14:19.518648 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 12:14:19.521921 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 12:14:19.522034 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 12:14:19.525273 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 12:14:19.528649 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 12:14:19.531454 Pre-setting of DQS Precalculation
3067 12:14:19.537956 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 12:14:19.538070 ==
3069 12:14:19.541837 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 12:14:19.545074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 12:14:19.545179 ==
3072 12:14:19.551695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 12:14:19.558147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 12:14:19.565192 [CA 0] Center 38 (9~68) winsize 60
3075 12:14:19.568333 [CA 1] Center 38 (9~68) winsize 60
3076 12:14:19.572149 [CA 2] Center 35 (6~65) winsize 60
3077 12:14:19.575475 [CA 3] Center 34 (4~65) winsize 62
3078 12:14:19.578678 [CA 4] Center 34 (4~65) winsize 62
3079 12:14:19.581688 [CA 5] Center 34 (4~64) winsize 61
3080 12:14:19.581788
3081 12:14:19.585600 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3082 12:14:19.585699
3083 12:14:19.588944 [CATrainingPosCal] consider 1 rank data
3084 12:14:19.592185 u2DelayCellTimex100 = 270/100 ps
3085 12:14:19.595364 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3086 12:14:19.598658 CA1 delay=38 (9~68),Diff = 4 PI (19 cell)
3087 12:14:19.601966 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3088 12:14:19.608560 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3089 12:14:19.611849 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3090 12:14:19.615251 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3091 12:14:19.615357
3092 12:14:19.619093 CA PerBit enable=1, Macro0, CA PI delay=34
3093 12:14:19.619191
3094 12:14:19.622426 [CBTSetCACLKResult] CA Dly = 34
3095 12:14:19.622530 CS Dly: 6 (0~37)
3096 12:14:19.622628 ==
3097 12:14:19.625656 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 12:14:19.632242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 12:14:19.632347 ==
3100 12:14:19.635598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 12:14:19.642114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3102 12:14:19.650563 [CA 0] Center 38 (8~68) winsize 61
3103 12:14:19.653943 [CA 1] Center 38 (9~68) winsize 60
3104 12:14:19.657122 [CA 2] Center 34 (4~65) winsize 62
3105 12:14:19.660379 [CA 3] Center 34 (4~65) winsize 62
3106 12:14:19.664222 [CA 4] Center 34 (4~65) winsize 62
3107 12:14:19.667598 [CA 5] Center 33 (4~63) winsize 60
3108 12:14:19.667713
3109 12:14:19.670902 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3110 12:14:19.670991
3111 12:14:19.673876 [CATrainingPosCal] consider 2 rank data
3112 12:14:19.677206 u2DelayCellTimex100 = 270/100 ps
3113 12:14:19.680549 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3114 12:14:19.687514 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3115 12:14:19.690733 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3116 12:14:19.694051 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3117 12:14:19.697266 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3118 12:14:19.700582 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3119 12:14:19.700701
3120 12:14:19.703836 CA PerBit enable=1, Macro0, CA PI delay=33
3121 12:14:19.703959
3122 12:14:19.707139 [CBTSetCACLKResult] CA Dly = 33
3123 12:14:19.707245 CS Dly: 8 (0~41)
3124 12:14:19.707367
3125 12:14:19.710407 ----->DramcWriteLeveling(PI) begin...
3126 12:14:19.713714 ==
3127 12:14:19.717749 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 12:14:19.721008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 12:14:19.721130 ==
3130 12:14:19.724228 Write leveling (Byte 0): 26 => 26
3131 12:14:19.727466 Write leveling (Byte 1): 31 => 31
3132 12:14:19.730728 DramcWriteLeveling(PI) end<-----
3133 12:14:19.730834
3134 12:14:19.730930 ==
3135 12:14:19.734038 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 12:14:19.737232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 12:14:19.737336 ==
3138 12:14:19.740630 [Gating] SW mode calibration
3139 12:14:19.747149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 12:14:19.753510 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 12:14:19.757380 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
3142 12:14:19.760682 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3143 12:14:19.763995 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3144 12:14:19.770584 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3145 12:14:19.773835 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:14:19.777133 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 12:14:19.783566 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 12:14:19.787495 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3149 12:14:19.790437 1 0 0 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
3150 12:14:19.796985 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3151 12:14:19.800207 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:14:19.803456 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:14:19.810814 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:14:19.814094 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 12:14:19.817436 1 0 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
3156 12:14:19.823960 1 0 28 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
3157 12:14:19.827218 1 1 0 | B1->B0 | 3d3d 3131 | 0 0 | (0 0) (1 1)
3158 12:14:19.830555 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:14:19.837222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:14:19.840652 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:14:19.843869 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:14:19.850524 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:14:19.853668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 12:14:19.856877 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:14:19.863586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3166 12:14:19.866811 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:14:19.870794 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:14:19.874176 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:14:19.880657 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:14:19.883928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:14:19.887029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:14:19.893570 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:14:19.897170 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:14:19.900371 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:14:19.906944 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:14:19.910136 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:14:19.913503 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:14:19.920278 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:14:19.923486 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:14:19.927409 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3181 12:14:19.933873 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 12:14:19.933959 Total UI for P1: 0, mck2ui 16
3183 12:14:19.940498 best dqsien dly found for B0: ( 1, 3, 28)
3184 12:14:19.940582 Total UI for P1: 0, mck2ui 16
3185 12:14:19.946940 best dqsien dly found for B1: ( 1, 3, 30)
3186 12:14:19.950191 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3187 12:14:19.953496 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3188 12:14:19.953601
3189 12:14:19.956825 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3190 12:14:19.960012 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3191 12:14:19.963876 [Gating] SW calibration Done
3192 12:14:19.963952 ==
3193 12:14:19.967112 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 12:14:19.970391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 12:14:19.970507 ==
3196 12:14:19.973650 RX Vref Scan: 0
3197 12:14:19.973735
3198 12:14:19.973802 RX Vref 0 -> 0, step: 1
3199 12:14:19.973865
3200 12:14:19.976866 RX Delay -40 -> 252, step: 8
3201 12:14:19.980127 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3202 12:14:19.986934 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3203 12:14:19.990128 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3204 12:14:19.993313 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3205 12:14:19.996505 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3206 12:14:19.999842 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3207 12:14:20.006898 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3208 12:14:20.010085 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3209 12:14:20.013281 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3210 12:14:20.016584 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3211 12:14:20.019925 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3212 12:14:20.023178 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3213 12:14:20.030453 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3214 12:14:20.033713 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3215 12:14:20.036959 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3216 12:14:20.040293 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3217 12:14:20.040378 ==
3218 12:14:20.043680 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 12:14:20.050124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 12:14:20.050240 ==
3221 12:14:20.050339 DQS Delay:
3222 12:14:20.053427 DQS0 = 0, DQS1 = 0
3223 12:14:20.053537 DQM Delay:
3224 12:14:20.053637 DQM0 = 116, DQM1 = 109
3225 12:14:20.056603 DQ Delay:
3226 12:14:20.059954 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3227 12:14:20.063227 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3228 12:14:20.067130 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3229 12:14:20.070362 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3230 12:14:20.070465
3231 12:14:20.070564
3232 12:14:20.070657 ==
3233 12:14:20.073675 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 12:14:20.077080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 12:14:20.080199 ==
3236 12:14:20.080300
3237 12:14:20.080398
3238 12:14:20.080494 TX Vref Scan disable
3239 12:14:20.083620 == TX Byte 0 ==
3240 12:14:20.086860 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3241 12:14:20.090296 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3242 12:14:20.093521 == TX Byte 1 ==
3243 12:14:20.096713 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3244 12:14:20.099945 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3245 12:14:20.100044 ==
3246 12:14:20.103232 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 12:14:20.110263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 12:14:20.110373 ==
3249 12:14:20.121309 TX Vref=22, minBit 0, minWin=25, winSum=404
3250 12:14:20.124765 TX Vref=24, minBit 1, minWin=25, winSum=415
3251 12:14:20.127972 TX Vref=26, minBit 1, minWin=25, winSum=418
3252 12:14:20.131119 TX Vref=28, minBit 0, minWin=26, winSum=423
3253 12:14:20.134453 TX Vref=30, minBit 3, minWin=25, winSum=424
3254 12:14:20.137725 TX Vref=32, minBit 0, minWin=26, winSum=424
3255 12:14:20.144269 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
3256 12:14:20.144395
3257 12:14:20.147530 Final TX Range 1 Vref 32
3258 12:14:20.147618
3259 12:14:20.147686 ==
3260 12:14:20.151450 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 12:14:20.154770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 12:14:20.154855 ==
3263 12:14:20.154922
3264 12:14:20.158127
3265 12:14:20.158211 TX Vref Scan disable
3266 12:14:20.161498 == TX Byte 0 ==
3267 12:14:20.164720 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 12:14:20.168025 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 12:14:20.171262 == TX Byte 1 ==
3270 12:14:20.174549 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3271 12:14:20.177849 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3272 12:14:20.177964
3273 12:14:20.181029 [DATLAT]
3274 12:14:20.181132 Freq=1200, CH1 RK0
3275 12:14:20.181233
3276 12:14:20.184314 DATLAT Default: 0xd
3277 12:14:20.184395 0, 0xFFFF, sum = 0
3278 12:14:20.187723 1, 0xFFFF, sum = 0
3279 12:14:20.187825 2, 0xFFFF, sum = 0
3280 12:14:20.190967 3, 0xFFFF, sum = 0
3281 12:14:20.191047 4, 0xFFFF, sum = 0
3282 12:14:20.194210 5, 0xFFFF, sum = 0
3283 12:14:20.197413 6, 0xFFFF, sum = 0
3284 12:14:20.197501 7, 0xFFFF, sum = 0
3285 12:14:20.201246 8, 0xFFFF, sum = 0
3286 12:14:20.201329 9, 0xFFFF, sum = 0
3287 12:14:20.204471 10, 0xFFFF, sum = 0
3288 12:14:20.204555 11, 0xFFFF, sum = 0
3289 12:14:20.207662 12, 0x0, sum = 1
3290 12:14:20.207772 13, 0x0, sum = 2
3291 12:14:20.210892 14, 0x0, sum = 3
3292 12:14:20.211002 15, 0x0, sum = 4
3293 12:14:20.211098 best_step = 13
3294 12:14:20.211187
3295 12:14:20.214041 ==
3296 12:14:20.217585 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 12:14:20.220914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 12:14:20.221059 ==
3299 12:14:20.221159 RX Vref Scan: 1
3300 12:14:20.221249
3301 12:14:20.224072 Set Vref Range= 32 -> 127
3302 12:14:20.224171
3303 12:14:20.227416 RX Vref 32 -> 127, step: 1
3304 12:14:20.227540
3305 12:14:20.230709 RX Delay -21 -> 252, step: 4
3306 12:14:20.230816
3307 12:14:20.234025 Set Vref, RX VrefLevel [Byte0]: 32
3308 12:14:20.237216 [Byte1]: 32
3309 12:14:20.237315
3310 12:14:20.241205 Set Vref, RX VrefLevel [Byte0]: 33
3311 12:14:20.244471 [Byte1]: 33
3312 12:14:20.244582
3313 12:14:20.247781 Set Vref, RX VrefLevel [Byte0]: 34
3314 12:14:20.250996 [Byte1]: 34
3315 12:14:20.255472
3316 12:14:20.255612 Set Vref, RX VrefLevel [Byte0]: 35
3317 12:14:20.258719 [Byte1]: 35
3318 12:14:20.263227
3319 12:14:20.263339 Set Vref, RX VrefLevel [Byte0]: 36
3320 12:14:20.266468 [Byte1]: 36
3321 12:14:20.271145
3322 12:14:20.271260 Set Vref, RX VrefLevel [Byte0]: 37
3323 12:14:20.274508 [Byte1]: 37
3324 12:14:20.278848
3325 12:14:20.278950 Set Vref, RX VrefLevel [Byte0]: 38
3326 12:14:20.282152 [Byte1]: 38
3327 12:14:20.286868
3328 12:14:20.286991 Set Vref, RX VrefLevel [Byte0]: 39
3329 12:14:20.290389 [Byte1]: 39
3330 12:14:20.294889
3331 12:14:20.295031 Set Vref, RX VrefLevel [Byte0]: 40
3332 12:14:20.298143 [Byte1]: 40
3333 12:14:20.302629
3334 12:14:20.302714 Set Vref, RX VrefLevel [Byte0]: 41
3335 12:14:20.306481 [Byte1]: 41
3336 12:14:20.310972
3337 12:14:20.311055 Set Vref, RX VrefLevel [Byte0]: 42
3338 12:14:20.314174 [Byte1]: 42
3339 12:14:20.318618
3340 12:14:20.318699 Set Vref, RX VrefLevel [Byte0]: 43
3341 12:14:20.321814 [Byte1]: 43
3342 12:14:20.326236
3343 12:14:20.326350 Set Vref, RX VrefLevel [Byte0]: 44
3344 12:14:20.329583 [Byte1]: 44
3345 12:14:20.334809
3346 12:14:20.334893 Set Vref, RX VrefLevel [Byte0]: 45
3347 12:14:20.337420 [Byte1]: 45
3348 12:14:20.342666
3349 12:14:20.342751 Set Vref, RX VrefLevel [Byte0]: 46
3350 12:14:20.345925 [Byte1]: 46
3351 12:14:20.350579
3352 12:14:20.350690 Set Vref, RX VrefLevel [Byte0]: 47
3353 12:14:20.353884 [Byte1]: 47
3354 12:14:20.358457
3355 12:14:20.358533 Set Vref, RX VrefLevel [Byte0]: 48
3356 12:14:20.361803 [Byte1]: 48
3357 12:14:20.366311
3358 12:14:20.366425 Set Vref, RX VrefLevel [Byte0]: 49
3359 12:14:20.369613 [Byte1]: 49
3360 12:14:20.374137
3361 12:14:20.374240 Set Vref, RX VrefLevel [Byte0]: 50
3362 12:14:20.377326 [Byte1]: 50
3363 12:14:20.381946
3364 12:14:20.382052 Set Vref, RX VrefLevel [Byte0]: 51
3365 12:14:20.385062 [Byte1]: 51
3366 12:14:20.389750
3367 12:14:20.389852 Set Vref, RX VrefLevel [Byte0]: 52
3368 12:14:20.393085 [Byte1]: 52
3369 12:14:20.397712
3370 12:14:20.397813 Set Vref, RX VrefLevel [Byte0]: 53
3371 12:14:20.400936 [Byte1]: 53
3372 12:14:20.405563
3373 12:14:20.405664 Set Vref, RX VrefLevel [Byte0]: 54
3374 12:14:20.408972 [Byte1]: 54
3375 12:14:20.413438
3376 12:14:20.413515 Set Vref, RX VrefLevel [Byte0]: 55
3377 12:14:20.416710 [Byte1]: 55
3378 12:14:20.421271
3379 12:14:20.421355 Set Vref, RX VrefLevel [Byte0]: 56
3380 12:14:20.424627 [Byte1]: 56
3381 12:14:20.429866
3382 12:14:20.429950 Set Vref, RX VrefLevel [Byte0]: 57
3383 12:14:20.433109 [Byte1]: 57
3384 12:14:20.437756
3385 12:14:20.437866 Set Vref, RX VrefLevel [Byte0]: 58
3386 12:14:20.441140 [Byte1]: 58
3387 12:14:20.445630
3388 12:14:20.445714 Set Vref, RX VrefLevel [Byte0]: 59
3389 12:14:20.448890 [Byte1]: 59
3390 12:14:20.452954
3391 12:14:20.453067 Set Vref, RX VrefLevel [Byte0]: 60
3392 12:14:20.456873 [Byte1]: 60
3393 12:14:20.460909
3394 12:14:20.461010 Set Vref, RX VrefLevel [Byte0]: 61
3395 12:14:20.464201 [Byte1]: 61
3396 12:14:20.468865
3397 12:14:20.468945 Set Vref, RX VrefLevel [Byte0]: 62
3398 12:14:20.472624 [Byte1]: 62
3399 12:14:20.477133
3400 12:14:20.477219 Set Vref, RX VrefLevel [Byte0]: 63
3401 12:14:20.480443 [Byte1]: 63
3402 12:14:20.485047
3403 12:14:20.485169 Set Vref, RX VrefLevel [Byte0]: 64
3404 12:14:20.491499 [Byte1]: 64
3405 12:14:20.491596
3406 12:14:20.494830 Set Vref, RX VrefLevel [Byte0]: 65
3407 12:14:20.498058 [Byte1]: 65
3408 12:14:20.498146
3409 12:14:20.501465 Set Vref, RX VrefLevel [Byte0]: 66
3410 12:14:20.504818 [Byte1]: 66
3411 12:14:20.508696
3412 12:14:20.508824 Set Vref, RX VrefLevel [Byte0]: 67
3413 12:14:20.511936 [Byte1]: 67
3414 12:14:20.516562
3415 12:14:20.516650 Set Vref, RX VrefLevel [Byte0]: 68
3416 12:14:20.519653 [Byte1]: 68
3417 12:14:20.524668
3418 12:14:20.524748 Set Vref, RX VrefLevel [Byte0]: 69
3419 12:14:20.528012 [Byte1]: 69
3420 12:14:20.532534
3421 12:14:20.532616 Set Vref, RX VrefLevel [Byte0]: 70
3422 12:14:20.535905 [Byte1]: 70
3423 12:14:20.540547
3424 12:14:20.540667 Set Vref, RX VrefLevel [Byte0]: 71
3425 12:14:20.543841 [Byte1]: 71
3426 12:14:20.548425
3427 12:14:20.548551 Final RX Vref Byte 0 = 61 to rank0
3428 12:14:20.551784 Final RX Vref Byte 1 = 54 to rank0
3429 12:14:20.555108 Final RX Vref Byte 0 = 61 to rank1
3430 12:14:20.558209 Final RX Vref Byte 1 = 54 to rank1==
3431 12:14:20.561614 Dram Type= 6, Freq= 0, CH_1, rank 0
3432 12:14:20.568167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 12:14:20.568286 ==
3434 12:14:20.568389 DQS Delay:
3435 12:14:20.568489 DQS0 = 0, DQS1 = 0
3436 12:14:20.571466 DQM Delay:
3437 12:14:20.571553 DQM0 = 116, DQM1 = 110
3438 12:14:20.574783 DQ Delay:
3439 12:14:20.578023 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3440 12:14:20.581294 DQ4 =116, DQ5 =122, DQ6 =128, DQ7 =114
3441 12:14:20.585161 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3442 12:14:20.587857 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =114
3443 12:14:20.587941
3444 12:14:20.588007
3445 12:14:20.594802 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3446 12:14:20.598121 CH1 RK0: MR19=303, MR18=FDE2
3447 12:14:20.604707 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3448 12:14:20.604800
3449 12:14:20.607862 ----->DramcWriteLeveling(PI) begin...
3450 12:14:20.607970 ==
3451 12:14:20.611838 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 12:14:20.614581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 12:14:20.618533 ==
3454 12:14:20.618641 Write leveling (Byte 0): 26 => 26
3455 12:14:20.621807 Write leveling (Byte 1): 30 => 30
3456 12:14:20.624823 DramcWriteLeveling(PI) end<-----
3457 12:14:20.624929
3458 12:14:20.625023 ==
3459 12:14:20.627911 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 12:14:20.634563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 12:14:20.634671 ==
3462 12:14:20.634765 [Gating] SW mode calibration
3463 12:14:20.644525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3464 12:14:20.648435 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3465 12:14:20.651752 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
3466 12:14:20.658256 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 12:14:20.661600 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 12:14:20.664933 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 12:14:20.671490 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 12:14:20.674801 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 12:14:20.678035 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
3472 12:14:20.684557 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3473 12:14:20.687933 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 12:14:20.691257 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 12:14:20.697779 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 12:14:20.701543 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 12:14:20.704720 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 12:14:20.711230 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 12:14:20.714612 1 0 24 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
3480 12:14:20.717972 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 12:14:20.724527 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 12:14:20.727724 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 12:14:20.730964 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 12:14:20.737462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 12:14:20.741369 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 12:14:20.744450 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 12:14:20.751308 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3488 12:14:20.753970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3489 12:14:20.757388 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:14:20.763943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:14:20.767899 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:14:20.771206 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:14:20.777659 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:14:20.780978 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:14:20.784237 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:14:20.790759 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:14:20.794065 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:14:20.797456 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:14:20.803978 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:14:20.807132 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:14:20.810391 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 12:14:20.817100 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:14:20.820284 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 12:14:20.823545 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3505 12:14:20.827521 Total UI for P1: 0, mck2ui 16
3506 12:14:20.830714 best dqsien dly found for B0: ( 1, 3, 24)
3507 12:14:20.833918 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 12:14:20.837169 Total UI for P1: 0, mck2ui 16
3509 12:14:20.840246 best dqsien dly found for B1: ( 1, 3, 28)
3510 12:14:20.843562 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3511 12:14:20.850269 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3512 12:14:20.850383
3513 12:14:20.853422 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3514 12:14:20.856630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3515 12:14:20.859998 [Gating] SW calibration Done
3516 12:14:20.860104 ==
3517 12:14:20.863267 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 12:14:20.866536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 12:14:20.866659 ==
3520 12:14:20.869853 RX Vref Scan: 0
3521 12:14:20.869957
3522 12:14:20.870061 RX Vref 0 -> 0, step: 1
3523 12:14:20.870156
3524 12:14:20.873110 RX Delay -40 -> 252, step: 8
3525 12:14:20.876429 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3526 12:14:20.883688 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3527 12:14:20.886997 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3528 12:14:20.890170 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3529 12:14:20.893435 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3530 12:14:20.896740 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3531 12:14:20.903379 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3532 12:14:20.906683 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3533 12:14:20.909861 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3534 12:14:20.913210 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3535 12:14:20.916548 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3536 12:14:20.922504 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3537 12:14:20.926414 iDelay=192, Bit 12, Center 119 (48 ~ 191) 144
3538 12:14:20.929733 iDelay=192, Bit 13, Center 123 (56 ~ 191) 136
3539 12:14:20.932954 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3540 12:14:20.939438 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3541 12:14:20.939567 ==
3542 12:14:20.942578 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 12:14:20.945672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 12:14:20.945784 ==
3545 12:14:20.945892 DQS Delay:
3546 12:14:20.949643 DQS0 = 0, DQS1 = 0
3547 12:14:20.949761 DQM Delay:
3548 12:14:20.952958 DQM0 = 112, DQM1 = 111
3549 12:14:20.953066 DQ Delay:
3550 12:14:20.956015 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3551 12:14:20.959258 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3552 12:14:20.962562 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3553 12:14:20.965804 DQ12 =119, DQ13 =123, DQ14 =119, DQ15 =119
3554 12:14:20.965913
3555 12:14:20.966026
3556 12:14:20.966124 ==
3557 12:14:20.969153 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 12:14:20.975706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 12:14:20.975817 ==
3560 12:14:20.975919
3561 12:14:20.976016
3562 12:14:20.978949 TX Vref Scan disable
3563 12:14:20.979070 == TX Byte 0 ==
3564 12:14:20.982285 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3565 12:14:20.988826 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3566 12:14:20.988947 == TX Byte 1 ==
3567 12:14:20.992105 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3568 12:14:20.999168 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3569 12:14:20.999274 ==
3570 12:14:21.002477 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 12:14:21.005803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 12:14:21.005919 ==
3573 12:14:21.017769 TX Vref=22, minBit 0, minWin=25, winSum=415
3574 12:14:21.021074 TX Vref=24, minBit 0, minWin=25, winSum=420
3575 12:14:21.024222 TX Vref=26, minBit 0, minWin=25, winSum=423
3576 12:14:21.027611 TX Vref=28, minBit 0, minWin=25, winSum=426
3577 12:14:21.030874 TX Vref=30, minBit 3, minWin=25, winSum=432
3578 12:14:21.037477 TX Vref=32, minBit 0, minWin=26, winSum=432
3579 12:14:21.040773 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 32
3580 12:14:21.040878
3581 12:14:21.044149 Final TX Range 1 Vref 32
3582 12:14:21.044240
3583 12:14:21.044311 ==
3584 12:14:21.047423 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 12:14:21.051030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 12:14:21.051176 ==
3587 12:14:21.054281
3588 12:14:21.054406
3589 12:14:21.054503 TX Vref Scan disable
3590 12:14:21.057458 == TX Byte 0 ==
3591 12:14:21.060612 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 12:14:21.064363 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 12:14:21.067659 == TX Byte 1 ==
3594 12:14:21.070893 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3595 12:14:21.077554 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3596 12:14:21.077649
3597 12:14:21.077716 [DATLAT]
3598 12:14:21.077778 Freq=1200, CH1 RK1
3599 12:14:21.077839
3600 12:14:21.080890 DATLAT Default: 0xd
3601 12:14:21.080975 0, 0xFFFF, sum = 0
3602 12:14:21.084180 1, 0xFFFF, sum = 0
3603 12:14:21.084266 2, 0xFFFF, sum = 0
3604 12:14:21.087516 3, 0xFFFF, sum = 0
3605 12:14:21.090756 4, 0xFFFF, sum = 0
3606 12:14:21.090843 5, 0xFFFF, sum = 0
3607 12:14:21.094180 6, 0xFFFF, sum = 0
3608 12:14:21.094267 7, 0xFFFF, sum = 0
3609 12:14:21.097395 8, 0xFFFF, sum = 0
3610 12:14:21.097481 9, 0xFFFF, sum = 0
3611 12:14:21.100704 10, 0xFFFF, sum = 0
3612 12:14:21.100791 11, 0xFFFF, sum = 0
3613 12:14:21.103964 12, 0x0, sum = 1
3614 12:14:21.104050 13, 0x0, sum = 2
3615 12:14:21.107281 14, 0x0, sum = 3
3616 12:14:21.107402 15, 0x0, sum = 4
3617 12:14:21.110696 best_step = 13
3618 12:14:21.110807
3619 12:14:21.110904 ==
3620 12:14:21.113910 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 12:14:21.117241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 12:14:21.117349 ==
3623 12:14:21.117445 RX Vref Scan: 0
3624 12:14:21.117546
3625 12:14:21.120546 RX Vref 0 -> 0, step: 1
3626 12:14:21.120661
3627 12:14:21.123787 RX Delay -21 -> 252, step: 4
3628 12:14:21.127024 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3629 12:14:21.133637 iDelay=191, Bit 1, Center 110 (47 ~ 174) 128
3630 12:14:21.136930 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3631 12:14:21.140227 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3632 12:14:21.143542 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3633 12:14:21.146829 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3634 12:14:21.153393 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3635 12:14:21.156547 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3636 12:14:21.160322 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3637 12:14:21.163424 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3638 12:14:21.166570 iDelay=191, Bit 10, Center 112 (47 ~ 178) 132
3639 12:14:21.172872 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3640 12:14:21.176801 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3641 12:14:21.180042 iDelay=191, Bit 13, Center 120 (59 ~ 182) 124
3642 12:14:21.183471 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3643 12:14:21.190015 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3644 12:14:21.190137 ==
3645 12:14:21.193365 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 12:14:21.196648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 12:14:21.196728 ==
3648 12:14:21.196803 DQS Delay:
3649 12:14:21.199873 DQS0 = 0, DQS1 = 0
3650 12:14:21.199945 DQM Delay:
3651 12:14:21.203148 DQM0 = 113, DQM1 = 110
3652 12:14:21.203259 DQ Delay:
3653 12:14:21.206475 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3654 12:14:21.209796 DQ4 =112, DQ5 =124, DQ6 =120, DQ7 =110
3655 12:14:21.213047 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =102
3656 12:14:21.216353 DQ12 =116, DQ13 =120, DQ14 =118, DQ15 =120
3657 12:14:21.216454
3658 12:14:21.216562
3659 12:14:21.226130 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb03, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 412 ps
3660 12:14:21.229934 CH1 RK1: MR19=304, MR18=FB03
3661 12:14:21.232677 CH1_RK1: MR19=0x304, MR18=0xFB03, DQSOSC=408, MR23=63, INC=39, DEC=26
3662 12:14:21.236029 [RxdqsGatingPostProcess] freq 1200
3663 12:14:21.243147 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3664 12:14:21.246499 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 12:14:21.249737 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 12:14:21.253125 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 12:14:21.256468 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 12:14:21.259751 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 12:14:21.262935 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 12:14:21.266047 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 12:14:21.269224 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 12:14:21.272932 Pre-setting of DQS Precalculation
3673 12:14:21.275947 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3674 12:14:21.282396 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3675 12:14:21.289476 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3676 12:14:21.289586
3677 12:14:21.292841
3678 12:14:21.292944 [Calibration Summary] 2400 Mbps
3679 12:14:21.296199 CH 0, Rank 0
3680 12:14:21.296307 SW Impedance : PASS
3681 12:14:21.299494 DUTY Scan : NO K
3682 12:14:21.302878 ZQ Calibration : PASS
3683 12:14:21.302987 Jitter Meter : NO K
3684 12:14:21.306200 CBT Training : PASS
3685 12:14:21.309579 Write leveling : PASS
3686 12:14:21.309682 RX DQS gating : PASS
3687 12:14:21.312884 RX DQ/DQS(RDDQC) : PASS
3688 12:14:21.315627 TX DQ/DQS : PASS
3689 12:14:21.315709 RX DATLAT : PASS
3690 12:14:21.318878 RX DQ/DQS(Engine): PASS
3691 12:14:21.322788 TX OE : NO K
3692 12:14:21.322896 All Pass.
3693 12:14:21.322997
3694 12:14:21.323097 CH 0, Rank 1
3695 12:14:21.326113 SW Impedance : PASS
3696 12:14:21.329348 DUTY Scan : NO K
3697 12:14:21.329439 ZQ Calibration : PASS
3698 12:14:21.332500 Jitter Meter : NO K
3699 12:14:21.335764 CBT Training : PASS
3700 12:14:21.335870 Write leveling : PASS
3701 12:14:21.339099 RX DQS gating : PASS
3702 12:14:21.339212 RX DQ/DQS(RDDQC) : PASS
3703 12:14:21.342340 TX DQ/DQS : PASS
3704 12:14:21.345577 RX DATLAT : PASS
3705 12:14:21.345688 RX DQ/DQS(Engine): PASS
3706 12:14:21.348821 TX OE : NO K
3707 12:14:21.348934 All Pass.
3708 12:14:21.349032
3709 12:14:21.352246 CH 1, Rank 0
3710 12:14:21.352358 SW Impedance : PASS
3711 12:14:21.355680 DUTY Scan : NO K
3712 12:14:21.359053 ZQ Calibration : PASS
3713 12:14:21.359160 Jitter Meter : NO K
3714 12:14:21.362182 CBT Training : PASS
3715 12:14:21.365558 Write leveling : PASS
3716 12:14:21.365671 RX DQS gating : PASS
3717 12:14:21.368762 RX DQ/DQS(RDDQC) : PASS
3718 12:14:21.371991 TX DQ/DQS : PASS
3719 12:14:21.372099 RX DATLAT : PASS
3720 12:14:21.375815 RX DQ/DQS(Engine): PASS
3721 12:14:21.378935 TX OE : NO K
3722 12:14:21.379050 All Pass.
3723 12:14:21.379150
3724 12:14:21.379246 CH 1, Rank 1
3725 12:14:21.381977 SW Impedance : PASS
3726 12:14:21.385709 DUTY Scan : NO K
3727 12:14:21.385823 ZQ Calibration : PASS
3728 12:14:21.389056 Jitter Meter : NO K
3729 12:14:21.392245 CBT Training : PASS
3730 12:14:21.392350 Write leveling : PASS
3731 12:14:21.395639 RX DQS gating : PASS
3732 12:14:21.395743 RX DQ/DQS(RDDQC) : PASS
3733 12:14:21.398953 TX DQ/DQS : PASS
3734 12:14:21.402150 RX DATLAT : PASS
3735 12:14:21.402257 RX DQ/DQS(Engine): PASS
3736 12:14:21.405507 TX OE : NO K
3737 12:14:21.405618 All Pass.
3738 12:14:21.405715
3739 12:14:21.408700 DramC Write-DBI off
3740 12:14:21.411891 PER_BANK_REFRESH: Hybrid Mode
3741 12:14:21.411980 TX_TRACKING: ON
3742 12:14:21.421790 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3743 12:14:21.425157 [FAST_K] Save calibration result to emmc
3744 12:14:21.428409 dramc_set_vcore_voltage set vcore to 650000
3745 12:14:21.431776 Read voltage for 600, 5
3746 12:14:21.431888 Vio18 = 0
3747 12:14:21.431987 Vcore = 650000
3748 12:14:21.435043 Vdram = 0
3749 12:14:21.435154 Vddq = 0
3750 12:14:21.435247 Vmddr = 0
3751 12:14:21.442029 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3752 12:14:21.445245 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3753 12:14:21.448549 MEM_TYPE=3, freq_sel=19
3754 12:14:21.451828 sv_algorithm_assistance_LP4_1600
3755 12:14:21.455034 ============ PULL DRAM RESETB DOWN ============
3756 12:14:21.458420 ========== PULL DRAM RESETB DOWN end =========
3757 12:14:21.465028 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 12:14:21.468340 ===================================
3759 12:14:21.471683 LPDDR4 DRAM CONFIGURATION
3760 12:14:21.474942 ===================================
3761 12:14:21.475053 EX_ROW_EN[0] = 0x0
3762 12:14:21.478094 EX_ROW_EN[1] = 0x0
3763 12:14:21.478178 LP4Y_EN = 0x0
3764 12:14:21.481958 WORK_FSP = 0x0
3765 12:14:21.482042 WL = 0x2
3766 12:14:21.485054 RL = 0x2
3767 12:14:21.485139 BL = 0x2
3768 12:14:21.488229 RPST = 0x0
3769 12:14:21.488314 RD_PRE = 0x0
3770 12:14:21.491898 WR_PRE = 0x1
3771 12:14:21.491983 WR_PST = 0x0
3772 12:14:21.495118 DBI_WR = 0x0
3773 12:14:21.495202 DBI_RD = 0x0
3774 12:14:21.498211 OTF = 0x1
3775 12:14:21.501576 ===================================
3776 12:14:21.504924 ===================================
3777 12:14:21.505004 ANA top config
3778 12:14:21.508193 ===================================
3779 12:14:21.511520 DLL_ASYNC_EN = 0
3780 12:14:21.514759 ALL_SLAVE_EN = 1
3781 12:14:21.518614 NEW_RANK_MODE = 1
3782 12:14:21.518699 DLL_IDLE_MODE = 1
3783 12:14:21.521953 LP45_APHY_COMB_EN = 1
3784 12:14:21.525251 TX_ODT_DIS = 1
3785 12:14:21.528583 NEW_8X_MODE = 1
3786 12:14:21.531905 ===================================
3787 12:14:21.534611 ===================================
3788 12:14:21.538449 data_rate = 1200
3789 12:14:21.541641 CKR = 1
3790 12:14:21.541756 DQ_P2S_RATIO = 8
3791 12:14:21.544931 ===================================
3792 12:14:21.547940 CA_P2S_RATIO = 8
3793 12:14:21.551199 DQ_CA_OPEN = 0
3794 12:14:21.554508 DQ_SEMI_OPEN = 0
3795 12:14:21.557814 CA_SEMI_OPEN = 0
3796 12:14:21.561118 CA_FULL_RATE = 0
3797 12:14:21.561226 DQ_CKDIV4_EN = 1
3798 12:14:21.564507 CA_CKDIV4_EN = 1
3799 12:14:21.568192 CA_PREDIV_EN = 0
3800 12:14:21.571628 PH8_DLY = 0
3801 12:14:21.574882 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3802 12:14:21.574993 DQ_AAMCK_DIV = 4
3803 12:14:21.578111 CA_AAMCK_DIV = 4
3804 12:14:21.581405 CA_ADMCK_DIV = 4
3805 12:14:21.584708 DQ_TRACK_CA_EN = 0
3806 12:14:21.588072 CA_PICK = 600
3807 12:14:21.591506 CA_MCKIO = 600
3808 12:14:21.594443 MCKIO_SEMI = 0
3809 12:14:21.594549 PLL_FREQ = 2288
3810 12:14:21.597676 DQ_UI_PI_RATIO = 32
3811 12:14:21.600887 CA_UI_PI_RATIO = 0
3812 12:14:21.604875 ===================================
3813 12:14:21.608118 ===================================
3814 12:14:21.611452 memory_type:LPDDR4
3815 12:14:21.614704 GP_NUM : 10
3816 12:14:21.614816 SRAM_EN : 1
3817 12:14:21.617960 MD32_EN : 0
3818 12:14:21.621217 ===================================
3819 12:14:21.621332 [ANA_INIT] >>>>>>>>>>>>>>
3820 12:14:21.624435 <<<<<< [CONFIGURE PHASE]: ANA_TX
3821 12:14:21.627827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3822 12:14:21.631136 ===================================
3823 12:14:21.634455 data_rate = 1200,PCW = 0X5800
3824 12:14:21.637703 ===================================
3825 12:14:21.640936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3826 12:14:21.647390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 12:14:21.654463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 12:14:21.657671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3829 12:14:21.661025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3830 12:14:21.664281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3831 12:14:21.667500 [ANA_INIT] flow start
3832 12:14:21.667609 [ANA_INIT] PLL >>>>>>>>
3833 12:14:21.670758 [ANA_INIT] PLL <<<<<<<<
3834 12:14:21.674100 [ANA_INIT] MIDPI >>>>>>>>
3835 12:14:21.674208 [ANA_INIT] MIDPI <<<<<<<<
3836 12:14:21.677902 [ANA_INIT] DLL >>>>>>>>
3837 12:14:21.681148 [ANA_INIT] flow end
3838 12:14:21.684422 ============ LP4 DIFF to SE enter ============
3839 12:14:21.687779 ============ LP4 DIFF to SE exit ============
3840 12:14:21.690939 [ANA_INIT] <<<<<<<<<<<<<
3841 12:14:21.694202 [Flow] Enable top DCM control >>>>>
3842 12:14:21.697435 [Flow] Enable top DCM control <<<<<
3843 12:14:21.700617 Enable DLL master slave shuffle
3844 12:14:21.703827 ==============================================================
3845 12:14:21.707689 Gating Mode config
3846 12:14:21.714224 ==============================================================
3847 12:14:21.714334 Config description:
3848 12:14:21.723595 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3849 12:14:21.730248 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3850 12:14:21.733505 SELPH_MODE 0: By rank 1: By Phase
3851 12:14:21.740777 ==============================================================
3852 12:14:21.743415 GAT_TRACK_EN = 1
3853 12:14:21.746796 RX_GATING_MODE = 2
3854 12:14:21.750060 RX_GATING_TRACK_MODE = 2
3855 12:14:21.753869 SELPH_MODE = 1
3856 12:14:21.757081 PICG_EARLY_EN = 1
3857 12:14:21.760339 VALID_LAT_VALUE = 1
3858 12:14:21.763520 ==============================================================
3859 12:14:21.766850 Enter into Gating configuration >>>>
3860 12:14:21.770096 Exit from Gating configuration <<<<
3861 12:14:21.773427 Enter into DVFS_PRE_config >>>>>
3862 12:14:21.786624 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3863 12:14:21.786724 Exit from DVFS_PRE_config <<<<<
3864 12:14:21.789947 Enter into PICG configuration >>>>
3865 12:14:21.793168 Exit from PICG configuration <<<<
3866 12:14:21.796529 [RX_INPUT] configuration >>>>>
3867 12:14:21.799860 [RX_INPUT] configuration <<<<<
3868 12:14:21.806856 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3869 12:14:21.810118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3870 12:14:21.816552 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 12:14:21.823213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 12:14:21.829926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 12:14:21.836584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 12:14:21.839839 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3875 12:14:21.842970 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3876 12:14:21.846235 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3877 12:14:21.852896 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3878 12:14:21.856235 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3879 12:14:21.859930 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 12:14:21.863123 ===================================
3881 12:14:21.866352 LPDDR4 DRAM CONFIGURATION
3882 12:14:21.869603 ===================================
3883 12:14:21.872908 EX_ROW_EN[0] = 0x0
3884 12:14:21.873029 EX_ROW_EN[1] = 0x0
3885 12:14:21.876205 LP4Y_EN = 0x0
3886 12:14:21.876321 WORK_FSP = 0x0
3887 12:14:21.879545 WL = 0x2
3888 12:14:21.879656 RL = 0x2
3889 12:14:21.882722 BL = 0x2
3890 12:14:21.882831 RPST = 0x0
3891 12:14:21.886047 RD_PRE = 0x0
3892 12:14:21.886153 WR_PRE = 0x1
3893 12:14:21.889932 WR_PST = 0x0
3894 12:14:21.890040 DBI_WR = 0x0
3895 12:14:21.893348 DBI_RD = 0x0
3896 12:14:21.893452 OTF = 0x1
3897 12:14:21.896606 ===================================
3898 12:14:21.899935 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3899 12:14:21.906438 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3900 12:14:21.909567 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 12:14:21.912748 ===================================
3902 12:14:21.915853 LPDDR4 DRAM CONFIGURATION
3903 12:14:21.919489 ===================================
3904 12:14:21.919599 EX_ROW_EN[0] = 0x10
3905 12:14:21.922733 EX_ROW_EN[1] = 0x0
3906 12:14:21.926075 LP4Y_EN = 0x0
3907 12:14:21.926167 WORK_FSP = 0x0
3908 12:14:21.929223 WL = 0x2
3909 12:14:21.929322 RL = 0x2
3910 12:14:21.932567 BL = 0x2
3911 12:14:21.932644 RPST = 0x0
3912 12:14:21.935891 RD_PRE = 0x0
3913 12:14:21.935977 WR_PRE = 0x1
3914 12:14:21.939271 WR_PST = 0x0
3915 12:14:21.939394 DBI_WR = 0x0
3916 12:14:21.942557 DBI_RD = 0x0
3917 12:14:21.942654 OTF = 0x1
3918 12:14:21.945819 ===================================
3919 12:14:21.952512 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3920 12:14:21.957117 nWR fixed to 30
3921 12:14:21.960371 [ModeRegInit_LP4] CH0 RK0
3922 12:14:21.960488 [ModeRegInit_LP4] CH0 RK1
3923 12:14:21.963521 [ModeRegInit_LP4] CH1 RK0
3924 12:14:21.966768 [ModeRegInit_LP4] CH1 RK1
3925 12:14:21.966880 match AC timing 17
3926 12:14:21.973240 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3927 12:14:21.977147 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3928 12:14:21.980398 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3929 12:14:21.986900 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3930 12:14:21.990217 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3931 12:14:21.990300 ==
3932 12:14:21.993465 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 12:14:21.996714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 12:14:21.996837 ==
3935 12:14:22.003215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 12:14:22.009695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3937 12:14:22.013580 [CA 0] Center 36 (6~66) winsize 61
3938 12:14:22.016775 [CA 1] Center 36 (6~66) winsize 61
3939 12:14:22.020000 [CA 2] Center 34 (4~65) winsize 62
3940 12:14:22.023673 [CA 3] Center 34 (4~65) winsize 62
3941 12:14:22.026968 [CA 4] Center 34 (4~64) winsize 61
3942 12:14:22.030188 [CA 5] Center 33 (3~64) winsize 62
3943 12:14:22.030306
3944 12:14:22.033564 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3945 12:14:22.033663
3946 12:14:22.036377 [CATrainingPosCal] consider 1 rank data
3947 12:14:22.039541 u2DelayCellTimex100 = 270/100 ps
3948 12:14:22.042841 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 12:14:22.046735 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3950 12:14:22.049457 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 12:14:22.052830 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 12:14:22.059359 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3953 12:14:22.063260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 12:14:22.063381
3955 12:14:22.065946 CA PerBit enable=1, Macro0, CA PI delay=33
3956 12:14:22.066032
3957 12:14:22.069854 [CBTSetCACLKResult] CA Dly = 33
3958 12:14:22.069968 CS Dly: 5 (0~36)
3959 12:14:22.070065 ==
3960 12:14:22.073166 Dram Type= 6, Freq= 0, CH_0, rank 1
3961 12:14:22.079439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 12:14:22.079528 ==
3963 12:14:22.082738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 12:14:22.089344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3965 12:14:22.092582 [CA 0] Center 36 (6~66) winsize 61
3966 12:14:22.095785 [CA 1] Center 36 (6~66) winsize 61
3967 12:14:22.099015 [CA 2] Center 35 (5~65) winsize 61
3968 12:14:22.102914 [CA 3] Center 34 (4~65) winsize 62
3969 12:14:22.106101 [CA 4] Center 33 (3~64) winsize 62
3970 12:14:22.109346 [CA 5] Center 33 (3~64) winsize 62
3971 12:14:22.109452
3972 12:14:22.112616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3973 12:14:22.112723
3974 12:14:22.115893 [CATrainingPosCal] consider 2 rank data
3975 12:14:22.119070 u2DelayCellTimex100 = 270/100 ps
3976 12:14:22.122341 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3977 12:14:22.125517 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3978 12:14:22.132086 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3979 12:14:22.135426 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 12:14:22.139311 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3981 12:14:22.142662 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 12:14:22.142766
3983 12:14:22.145912 CA PerBit enable=1, Macro0, CA PI delay=33
3984 12:14:22.146017
3985 12:14:22.149144 [CBTSetCACLKResult] CA Dly = 33
3986 12:14:22.149245 CS Dly: 5 (0~36)
3987 12:14:22.149341
3988 12:14:22.152558 ----->DramcWriteLeveling(PI) begin...
3989 12:14:22.155856 ==
3990 12:14:22.159103 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 12:14:22.162375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 12:14:22.162462 ==
3993 12:14:22.165636 Write leveling (Byte 0): 31 => 31
3994 12:14:22.168913 Write leveling (Byte 1): 30 => 30
3995 12:14:22.172291 DramcWriteLeveling(PI) end<-----
3996 12:14:22.172402
3997 12:14:22.172502 ==
3998 12:14:22.175532 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 12:14:22.178849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 12:14:22.178955 ==
4001 12:14:22.182648 [Gating] SW mode calibration
4002 12:14:22.189198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4003 12:14:22.192542 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4004 12:14:22.199109 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 12:14:22.202351 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 12:14:22.205613 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 12:14:22.212238 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 12:14:22.215583 0 9 16 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (1 1)
4009 12:14:22.218826 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 12:14:22.225341 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 12:14:22.228556 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 12:14:22.232180 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 12:14:22.238817 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 12:14:22.241970 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 12:14:22.245317 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 12:14:22.251963 0 10 16 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (0 0)
4017 12:14:22.255212 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 12:14:22.258505 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 12:14:22.265143 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:14:22.268397 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 12:14:22.271716 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 12:14:22.278339 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 12:14:22.281567 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 12:14:22.285348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4025 12:14:22.291975 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4026 12:14:22.295220 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:14:22.298499 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:14:22.305175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:14:22.308570 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:14:22.311968 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:14:22.318522 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:14:22.321872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:14:22.325102 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:14:22.331545 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:14:22.335453 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:14:22.338579 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:14:22.341765 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:14:22.348426 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:14:22.351665 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:14:22.355069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4041 12:14:22.358351 Total UI for P1: 0, mck2ui 16
4042 12:14:22.361655 best dqsien dly found for B0: ( 0, 13, 14)
4043 12:14:22.368139 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 12:14:22.371429 Total UI for P1: 0, mck2ui 16
4045 12:14:22.374830 best dqsien dly found for B1: ( 0, 13, 16)
4046 12:14:22.378075 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4047 12:14:22.381374 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4048 12:14:22.381462
4049 12:14:22.384536 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4050 12:14:22.388283 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4051 12:14:22.391597 [Gating] SW calibration Done
4052 12:14:22.391674 ==
4053 12:14:22.394736 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 12:14:22.397985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 12:14:22.398072 ==
4056 12:14:22.401182 RX Vref Scan: 0
4057 12:14:22.401263
4058 12:14:22.404556 RX Vref 0 -> 0, step: 1
4059 12:14:22.404643
4060 12:14:22.404726 RX Delay -230 -> 252, step: 16
4061 12:14:22.411111 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4062 12:14:22.414983 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4063 12:14:22.418344 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4064 12:14:22.421585 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4065 12:14:22.428104 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4066 12:14:22.431433 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4067 12:14:22.434773 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4068 12:14:22.437971 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4069 12:14:22.441127 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4070 12:14:22.448246 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4071 12:14:22.451434 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4072 12:14:22.454680 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4073 12:14:22.458091 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4074 12:14:22.464764 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4075 12:14:22.468154 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4076 12:14:22.471388 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4077 12:14:22.471495 ==
4078 12:14:22.474747 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 12:14:22.477469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 12:14:22.481451 ==
4081 12:14:22.481554 DQS Delay:
4082 12:14:22.481691 DQS0 = 0, DQS1 = 0
4083 12:14:22.484188 DQM Delay:
4084 12:14:22.484285 DQM0 = 40, DQM1 = 32
4085 12:14:22.487429 DQ Delay:
4086 12:14:22.487506 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4087 12:14:22.491401 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4088 12:14:22.494471 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4089 12:14:22.497572 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4090 12:14:22.497715
4091 12:14:22.500910
4092 12:14:22.501038 ==
4093 12:14:22.504166 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 12:14:22.507837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 12:14:22.507953 ==
4096 12:14:22.508060
4097 12:14:22.508162
4098 12:14:22.511053 TX Vref Scan disable
4099 12:14:22.511159 == TX Byte 0 ==
4100 12:14:22.517631 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4101 12:14:22.521006 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4102 12:14:22.521115 == TX Byte 1 ==
4103 12:14:22.527731 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4104 12:14:22.531249 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4105 12:14:22.531385 ==
4106 12:14:22.534494 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 12:14:22.537190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 12:14:22.537277 ==
4109 12:14:22.537343
4110 12:14:22.537404
4111 12:14:22.540531 TX Vref Scan disable
4112 12:14:22.544405 == TX Byte 0 ==
4113 12:14:22.547597 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4114 12:14:22.550844 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4115 12:14:22.554102 == TX Byte 1 ==
4116 12:14:22.557492 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4117 12:14:22.560831 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4118 12:14:22.560915
4119 12:14:22.564096 [DATLAT]
4120 12:14:22.564179 Freq=600, CH0 RK0
4121 12:14:22.564246
4122 12:14:22.567400 DATLAT Default: 0x9
4123 12:14:22.567487 0, 0xFFFF, sum = 0
4124 12:14:22.570570 1, 0xFFFF, sum = 0
4125 12:14:22.570656 2, 0xFFFF, sum = 0
4126 12:14:22.573864 3, 0xFFFF, sum = 0
4127 12:14:22.573950 4, 0xFFFF, sum = 0
4128 12:14:22.577197 5, 0xFFFF, sum = 0
4129 12:14:22.577283 6, 0xFFFF, sum = 0
4130 12:14:22.580523 7, 0xFFFF, sum = 0
4131 12:14:22.580608 8, 0x0, sum = 1
4132 12:14:22.583791 9, 0x0, sum = 2
4133 12:14:22.583877 10, 0x0, sum = 3
4134 12:14:22.587065 11, 0x0, sum = 4
4135 12:14:22.587149 best_step = 9
4136 12:14:22.587216
4137 12:14:22.587278 ==
4138 12:14:22.590363 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 12:14:22.596850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 12:14:22.596935 ==
4141 12:14:22.597001 RX Vref Scan: 1
4142 12:14:22.597062
4143 12:14:22.600724 RX Vref 0 -> 0, step: 1
4144 12:14:22.600807
4145 12:14:22.603990 RX Delay -195 -> 252, step: 8
4146 12:14:22.604078
4147 12:14:22.607289 Set Vref, RX VrefLevel [Byte0]: 55
4148 12:14:22.610582 [Byte1]: 50
4149 12:14:22.610665
4150 12:14:22.613901 Final RX Vref Byte 0 = 55 to rank0
4151 12:14:22.617194 Final RX Vref Byte 1 = 50 to rank0
4152 12:14:22.620501 Final RX Vref Byte 0 = 55 to rank1
4153 12:14:22.623754 Final RX Vref Byte 1 = 50 to rank1==
4154 12:14:22.627028 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 12:14:22.630444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 12:14:22.630528 ==
4157 12:14:22.633737 DQS Delay:
4158 12:14:22.633821 DQS0 = 0, DQS1 = 0
4159 12:14:22.633887 DQM Delay:
4160 12:14:22.637031 DQM0 = 43, DQM1 = 33
4161 12:14:22.637115 DQ Delay:
4162 12:14:22.640443 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4163 12:14:22.643736 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4164 12:14:22.647091 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4165 12:14:22.650101 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4166 12:14:22.650214
4167 12:14:22.650312
4168 12:14:22.660482 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b19, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4169 12:14:22.663903 CH0 RK0: MR19=808, MR18=3B19
4170 12:14:22.667233 CH0_RK0: MR19=0x808, MR18=0x3B19, DQSOSC=398, MR23=63, INC=165, DEC=110
4171 12:14:22.667318
4172 12:14:22.670428 ----->DramcWriteLeveling(PI) begin...
4173 12:14:22.673611 ==
4174 12:14:22.676961 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 12:14:22.680177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 12:14:22.680265 ==
4177 12:14:22.683427 Write leveling (Byte 0): 33 => 33
4178 12:14:22.686662 Write leveling (Byte 1): 31 => 31
4179 12:14:22.689928 DramcWriteLeveling(PI) end<-----
4180 12:14:22.690020
4181 12:14:22.690088 ==
4182 12:14:22.693209 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 12:14:22.696521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 12:14:22.696596 ==
4185 12:14:22.699806 [Gating] SW mode calibration
4186 12:14:22.706990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4187 12:14:22.713522 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4188 12:14:22.716737 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 12:14:22.719989 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 12:14:22.726412 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 12:14:22.729693 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4192 12:14:22.733053 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4193 12:14:22.736167 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 12:14:22.743341 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 12:14:22.746639 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 12:14:22.749866 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 12:14:22.756463 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 12:14:22.759670 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 12:14:22.763087 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4200 12:14:22.769793 0 10 16 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
4201 12:14:22.773108 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 12:14:22.776496 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 12:14:22.782913 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 12:14:22.786286 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 12:14:22.789544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 12:14:22.796126 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4207 12:14:22.800087 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 12:14:22.803366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4209 12:14:22.809861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:14:22.813119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:14:22.816340 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:14:22.822956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:14:22.826290 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:14:22.829584 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:14:22.836132 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:14:22.839338 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:14:22.842710 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:14:22.849235 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:14:22.852608 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:14:22.856448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:14:22.859735 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 12:14:22.866081 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:14:22.869350 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4224 12:14:22.872602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 12:14:22.875761 Total UI for P1: 0, mck2ui 16
4226 12:14:22.878986 best dqsien dly found for B0: ( 0, 13, 12)
4227 12:14:22.882369 Total UI for P1: 0, mck2ui 16
4228 12:14:22.885600 best dqsien dly found for B1: ( 0, 13, 14)
4229 12:14:22.888996 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4230 12:14:22.895535 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4231 12:14:22.895629
4232 12:14:22.899419 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4233 12:14:22.902685 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4234 12:14:22.905960 [Gating] SW calibration Done
4235 12:14:22.906058 ==
4236 12:14:22.909247 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 12:14:22.912540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 12:14:22.912625 ==
4239 12:14:22.915760 RX Vref Scan: 0
4240 12:14:22.915833
4241 12:14:22.915918 RX Vref 0 -> 0, step: 1
4242 12:14:22.916016
4243 12:14:22.918895 RX Delay -230 -> 252, step: 16
4244 12:14:22.922198 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4245 12:14:22.928864 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4246 12:14:22.932160 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4247 12:14:22.935460 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4248 12:14:22.939187 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4249 12:14:22.945715 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4250 12:14:22.949038 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4251 12:14:22.952247 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4252 12:14:22.955540 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4253 12:14:22.958829 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4254 12:14:22.965239 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4255 12:14:22.969034 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4256 12:14:22.972341 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4257 12:14:22.975597 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4258 12:14:22.982093 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4259 12:14:22.985392 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4260 12:14:22.985492 ==
4261 12:14:22.988625 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 12:14:22.991918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 12:14:22.991995 ==
4264 12:14:22.995193 DQS Delay:
4265 12:14:22.995293 DQS0 = 0, DQS1 = 0
4266 12:14:22.995421 DQM Delay:
4267 12:14:22.998453 DQM0 = 40, DQM1 = 34
4268 12:14:22.998525 DQ Delay:
4269 12:14:23.001652 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4270 12:14:23.005486 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4271 12:14:23.008686 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4272 12:14:23.011939 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4273 12:14:23.012025
4274 12:14:23.012137
4275 12:14:23.012198 ==
4276 12:14:23.015227 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 12:14:23.021781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 12:14:23.021858 ==
4279 12:14:23.021922
4280 12:14:23.021989
4281 12:14:23.022047 TX Vref Scan disable
4282 12:14:23.025753 == TX Byte 0 ==
4283 12:14:23.028978 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4284 12:14:23.035574 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4285 12:14:23.035654 == TX Byte 1 ==
4286 12:14:23.038962 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 12:14:23.045498 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 12:14:23.045600 ==
4289 12:14:23.048687 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 12:14:23.051967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 12:14:23.052096 ==
4292 12:14:23.052208
4293 12:14:23.052327
4294 12:14:23.055201 TX Vref Scan disable
4295 12:14:23.058551 == TX Byte 0 ==
4296 12:14:23.062464 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4297 12:14:23.065617 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4298 12:14:23.068866 == TX Byte 1 ==
4299 12:14:23.072046 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4300 12:14:23.075287 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4301 12:14:23.075426
4302 12:14:23.075490 [DATLAT]
4303 12:14:23.078673 Freq=600, CH0 RK1
4304 12:14:23.078744
4305 12:14:23.078803 DATLAT Default: 0x9
4306 12:14:23.081812 0, 0xFFFF, sum = 0
4307 12:14:23.085095 1, 0xFFFF, sum = 0
4308 12:14:23.085167 2, 0xFFFF, sum = 0
4309 12:14:23.088939 3, 0xFFFF, sum = 0
4310 12:14:23.089013 4, 0xFFFF, sum = 0
4311 12:14:23.092265 5, 0xFFFF, sum = 0
4312 12:14:23.092344 6, 0xFFFF, sum = 0
4313 12:14:23.095561 7, 0xFFFF, sum = 0
4314 12:14:23.095632 8, 0x0, sum = 1
4315 12:14:23.098885 9, 0x0, sum = 2
4316 12:14:23.098963 10, 0x0, sum = 3
4317 12:14:23.099023 11, 0x0, sum = 4
4318 12:14:23.102113 best_step = 9
4319 12:14:23.102219
4320 12:14:23.102279 ==
4321 12:14:23.105354 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 12:14:23.108692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 12:14:23.108771 ==
4324 12:14:23.112061 RX Vref Scan: 0
4325 12:14:23.112134
4326 12:14:23.112195 RX Vref 0 -> 0, step: 1
4327 12:14:23.115268
4328 12:14:23.115399 RX Delay -179 -> 252, step: 8
4329 12:14:23.122581 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4330 12:14:23.125851 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4331 12:14:23.129131 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4332 12:14:23.132553 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4333 12:14:23.139178 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4334 12:14:23.142533 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4335 12:14:23.145752 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4336 12:14:23.149045 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4337 12:14:23.152483 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4338 12:14:23.158963 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4339 12:14:23.162328 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4340 12:14:23.165581 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4341 12:14:23.168936 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4342 12:14:23.176048 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4343 12:14:23.179200 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4344 12:14:23.182417 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4345 12:14:23.182492 ==
4346 12:14:23.185566 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 12:14:23.192160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 12:14:23.192241 ==
4349 12:14:23.192305 DQS Delay:
4350 12:14:23.192364 DQS0 = 0, DQS1 = 0
4351 12:14:23.195457 DQM Delay:
4352 12:14:23.195527 DQM0 = 39, DQM1 = 33
4353 12:14:23.198757 DQ Delay:
4354 12:14:23.201985 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4355 12:14:23.202090 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4356 12:14:23.205252 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4357 12:14:23.212477 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4358 12:14:23.212558
4359 12:14:23.212656
4360 12:14:23.219022 [DQSOSCAuto] RK1, (LSB)MR18= 0x492b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4361 12:14:23.222360 CH0 RK1: MR19=808, MR18=492B
4362 12:14:23.228874 CH0_RK1: MR19=0x808, MR18=0x492B, DQSOSC=396, MR23=63, INC=167, DEC=111
4363 12:14:23.232133 [RxdqsGatingPostProcess] freq 600
4364 12:14:23.235258 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4365 12:14:23.238536 Pre-setting of DQS Precalculation
4366 12:14:23.245827 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4367 12:14:23.245947 ==
4368 12:14:23.249135 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 12:14:23.252373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 12:14:23.252476 ==
4371 12:14:23.259011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 12:14:23.262388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 12:14:23.266395 [CA 0] Center 35 (5~65) winsize 61
4374 12:14:23.269514 [CA 1] Center 35 (5~66) winsize 62
4375 12:14:23.272830 [CA 2] Center 34 (4~64) winsize 61
4376 12:14:23.276018 [CA 3] Center 33 (3~64) winsize 62
4377 12:14:23.279281 [CA 4] Center 34 (3~65) winsize 63
4378 12:14:23.283071 [CA 5] Center 33 (3~64) winsize 62
4379 12:14:23.283175
4380 12:14:23.286232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 12:14:23.286348
4382 12:14:23.289507 [CATrainingPosCal] consider 1 rank data
4383 12:14:23.292809 u2DelayCellTimex100 = 270/100 ps
4384 12:14:23.296167 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4385 12:14:23.302837 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 12:14:23.306184 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4387 12:14:23.309439 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 12:14:23.312607 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4389 12:14:23.315874 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 12:14:23.315975
4391 12:14:23.319040 CA PerBit enable=1, Macro0, CA PI delay=33
4392 12:14:23.319140
4393 12:14:23.322414 [CBTSetCACLKResult] CA Dly = 33
4394 12:14:23.322483 CS Dly: 3 (0~34)
4395 12:14:23.325824 ==
4396 12:14:23.329094 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 12:14:23.332411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 12:14:23.332484 ==
4399 12:14:23.335650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 12:14:23.342810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4401 12:14:23.346639 [CA 0] Center 35 (5~66) winsize 62
4402 12:14:23.349859 [CA 1] Center 35 (5~66) winsize 62
4403 12:14:23.353172 [CA 2] Center 34 (4~65) winsize 62
4404 12:14:23.356438 [CA 3] Center 34 (3~65) winsize 63
4405 12:14:23.359796 [CA 4] Center 34 (3~65) winsize 63
4406 12:14:23.363103 [CA 5] Center 33 (3~64) winsize 62
4407 12:14:23.363199
4408 12:14:23.366459 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4409 12:14:23.366537
4410 12:14:23.369705 [CATrainingPosCal] consider 2 rank data
4411 12:14:23.373104 u2DelayCellTimex100 = 270/100 ps
4412 12:14:23.376445 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4413 12:14:23.382761 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4414 12:14:23.385940 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4415 12:14:23.389851 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 12:14:23.393041 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4417 12:14:23.396282 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 12:14:23.396383
4419 12:14:23.399745 CA PerBit enable=1, Macro0, CA PI delay=33
4420 12:14:23.399848
4421 12:14:23.402924 [CBTSetCACLKResult] CA Dly = 33
4422 12:14:23.402996 CS Dly: 4 (0~37)
4423 12:14:23.406203
4424 12:14:23.409550 ----->DramcWriteLeveling(PI) begin...
4425 12:14:23.409621 ==
4426 12:14:23.412758 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 12:14:23.416040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 12:14:23.416141 ==
4429 12:14:23.419407 Write leveling (Byte 0): 28 => 28
4430 12:14:23.422724 Write leveling (Byte 1): 33 => 33
4431 12:14:23.426022 DramcWriteLeveling(PI) end<-----
4432 12:14:23.426134
4433 12:14:23.426224 ==
4434 12:14:23.429418 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 12:14:23.432671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 12:14:23.432744 ==
4437 12:14:23.435951 [Gating] SW mode calibration
4438 12:14:23.443000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4439 12:14:23.446032 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4440 12:14:23.452571 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 12:14:23.456486 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 12:14:23.459908 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4443 12:14:23.466319 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4444 12:14:23.469625 0 9 16 | B1->B0 | 2c2c 2424 | 1 1 | (1 0) (1 0)
4445 12:14:23.472860 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 12:14:23.479260 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 12:14:23.482622 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 12:14:23.485703 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 12:14:23.492660 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4450 12:14:23.495836 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 12:14:23.498980 0 10 12 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (1 1)
4452 12:14:23.505748 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4453 12:14:23.508920 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 12:14:23.512193 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 12:14:23.518659 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 12:14:23.522606 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 12:14:23.525926 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 12:14:23.531999 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 12:14:23.535276 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4460 12:14:23.538698 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:14:23.545728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:14:23.548969 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:14:23.552226 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:14:23.558768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:14:23.562072 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:14:23.565340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:14:23.572010 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:14:23.575202 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:14:23.578549 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:14:23.585751 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:14:23.588892 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:14:23.592145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:14:23.598853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:14:23.602037 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:14:23.605197 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4476 12:14:23.612284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 12:14:23.612363 Total UI for P1: 0, mck2ui 16
4478 12:14:23.615713 best dqsien dly found for B0: ( 0, 13, 12)
4479 12:14:23.618295 Total UI for P1: 0, mck2ui 16
4480 12:14:23.622194 best dqsien dly found for B1: ( 0, 13, 12)
4481 12:14:23.625421 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4482 12:14:23.631704 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4483 12:14:23.631780
4484 12:14:23.635079 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4485 12:14:23.638963 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4486 12:14:23.641640 [Gating] SW calibration Done
4487 12:14:23.641714 ==
4488 12:14:23.645521 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 12:14:23.648766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 12:14:23.648847 ==
4491 12:14:23.651994 RX Vref Scan: 0
4492 12:14:23.652091
4493 12:14:23.652185 RX Vref 0 -> 0, step: 1
4494 12:14:23.652272
4495 12:14:23.655067 RX Delay -230 -> 252, step: 16
4496 12:14:23.658345 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4497 12:14:23.664959 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4498 12:14:23.668333 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4499 12:14:23.671583 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4500 12:14:23.674946 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4501 12:14:23.678837 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4502 12:14:23.684849 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4503 12:14:23.688180 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4504 12:14:23.691499 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4505 12:14:23.695243 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4506 12:14:23.701559 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4507 12:14:23.704662 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4508 12:14:23.708453 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4509 12:14:23.711679 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4510 12:14:23.718094 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4511 12:14:23.721460 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4512 12:14:23.721564 ==
4513 12:14:23.724738 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 12:14:23.727918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 12:14:23.728071 ==
4516 12:14:23.731288 DQS Delay:
4517 12:14:23.731427 DQS0 = 0, DQS1 = 0
4518 12:14:23.731493 DQM Delay:
4519 12:14:23.734566 DQM0 = 43, DQM1 = 35
4520 12:14:23.734641 DQ Delay:
4521 12:14:23.737818 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4522 12:14:23.741097 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4523 12:14:23.744468 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4524 12:14:23.748343 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4525 12:14:23.748444
4526 12:14:23.748534
4527 12:14:23.748627 ==
4528 12:14:23.751633 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 12:14:23.758276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 12:14:23.758383 ==
4531 12:14:23.758456
4532 12:14:23.758518
4533 12:14:23.758578 TX Vref Scan disable
4534 12:14:23.761443 == TX Byte 0 ==
4535 12:14:23.764795 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 12:14:23.771290 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 12:14:23.771413 == TX Byte 1 ==
4538 12:14:23.775297 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4539 12:14:23.781361 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4540 12:14:23.781436 ==
4541 12:14:23.785337 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 12:14:23.788605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 12:14:23.788716 ==
4544 12:14:23.788810
4545 12:14:23.788899
4546 12:14:23.791941 TX Vref Scan disable
4547 12:14:23.794567 == TX Byte 0 ==
4548 12:14:23.798492 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4549 12:14:23.801652 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4550 12:14:23.804737 == TX Byte 1 ==
4551 12:14:23.807735 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4552 12:14:23.811731 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4553 12:14:23.811839
4554 12:14:23.811932 [DATLAT]
4555 12:14:23.814922 Freq=600, CH1 RK0
4556 12:14:23.815023
4557 12:14:23.818152 DATLAT Default: 0x9
4558 12:14:23.818256 0, 0xFFFF, sum = 0
4559 12:14:23.821405 1, 0xFFFF, sum = 0
4560 12:14:23.821507 2, 0xFFFF, sum = 0
4561 12:14:23.824838 3, 0xFFFF, sum = 0
4562 12:14:23.824938 4, 0xFFFF, sum = 0
4563 12:14:23.828085 5, 0xFFFF, sum = 0
4564 12:14:23.828157 6, 0xFFFF, sum = 0
4565 12:14:23.831304 7, 0xFFFF, sum = 0
4566 12:14:23.831440 8, 0x0, sum = 1
4567 12:14:23.834623 9, 0x0, sum = 2
4568 12:14:23.834697 10, 0x0, sum = 3
4569 12:14:23.834767 11, 0x0, sum = 4
4570 12:14:23.837871 best_step = 9
4571 12:14:23.837972
4572 12:14:23.838060 ==
4573 12:14:23.841204 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 12:14:23.844419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:14:23.844526 ==
4576 12:14:23.847750 RX Vref Scan: 1
4577 12:14:23.847820
4578 12:14:23.847881 RX Vref 0 -> 0, step: 1
4579 12:14:23.851065
4580 12:14:23.851162 RX Delay -195 -> 252, step: 8
4581 12:14:23.851253
4582 12:14:23.854384 Set Vref, RX VrefLevel [Byte0]: 61
4583 12:14:23.857673 [Byte1]: 54
4584 12:14:23.862262
4585 12:14:23.862377 Final RX Vref Byte 0 = 61 to rank0
4586 12:14:23.865505 Final RX Vref Byte 1 = 54 to rank0
4587 12:14:23.868845 Final RX Vref Byte 0 = 61 to rank1
4588 12:14:23.872103 Final RX Vref Byte 1 = 54 to rank1==
4589 12:14:23.875471 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 12:14:23.881999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 12:14:23.882108 ==
4592 12:14:23.882205 DQS Delay:
4593 12:14:23.882301 DQS0 = 0, DQS1 = 0
4594 12:14:23.885319 DQM Delay:
4595 12:14:23.885426 DQM0 = 40, DQM1 = 33
4596 12:14:23.888712 DQ Delay:
4597 12:14:23.892055 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4598 12:14:23.895451 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4599 12:14:23.895536 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4600 12:14:23.901970 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4601 12:14:23.902086
4602 12:14:23.902188
4603 12:14:23.908879 [DQSOSCAuto] RK0, (LSB)MR18= 0x470d, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4604 12:14:23.912015 CH1 RK0: MR19=808, MR18=470D
4605 12:14:23.918642 CH1_RK0: MR19=0x808, MR18=0x470D, DQSOSC=396, MR23=63, INC=167, DEC=111
4606 12:14:23.918757
4607 12:14:23.921863 ----->DramcWriteLeveling(PI) begin...
4608 12:14:23.921967 ==
4609 12:14:23.925542 Dram Type= 6, Freq= 0, CH_1, rank 1
4610 12:14:23.928795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 12:14:23.928897 ==
4612 12:14:23.932047 Write leveling (Byte 0): 30 => 30
4613 12:14:23.935343 Write leveling (Byte 1): 30 => 30
4614 12:14:23.938621 DramcWriteLeveling(PI) end<-----
4615 12:14:23.938727
4616 12:14:23.938824 ==
4617 12:14:23.941878 Dram Type= 6, Freq= 0, CH_1, rank 1
4618 12:14:23.945248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4619 12:14:23.945352 ==
4620 12:14:23.948497 [Gating] SW mode calibration
4621 12:14:23.955162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4622 12:14:23.961705 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4623 12:14:23.964868 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 12:14:23.972137 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4625 12:14:23.975248 0 9 8 | B1->B0 | 3535 3333 | 0 1 | (0 0) (0 1)
4626 12:14:23.978675 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (0 0) (1 0)
4627 12:14:23.982060 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4628 12:14:23.988683 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4629 12:14:23.992012 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 12:14:23.995400 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 12:14:24.002002 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 12:14:24.004695 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 12:14:24.008014 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4634 12:14:24.014904 0 10 12 | B1->B0 | 3232 3f3f | 0 0 | (0 0) (0 0)
4635 12:14:24.018066 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4636 12:14:24.021779 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 12:14:24.028157 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 12:14:24.031275 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 12:14:24.034492 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 12:14:24.041604 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 12:14:24.044934 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4642 12:14:24.048209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4643 12:14:24.054955 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:14:24.058155 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:14:24.061444 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:14:24.068126 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:14:24.071464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:14:24.074634 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:14:24.081251 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:14:24.084578 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:14:24.087802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:14:24.094505 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:14:24.097877 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:14:24.101149 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:14:24.107796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:14:24.111122 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:14:24.114819 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4658 12:14:24.117910 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4659 12:14:24.121240 Total UI for P1: 0, mck2ui 16
4660 12:14:24.124480 best dqsien dly found for B0: ( 0, 13, 8)
4661 12:14:24.131613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 12:14:24.134590 Total UI for P1: 0, mck2ui 16
4663 12:14:24.137772 best dqsien dly found for B1: ( 0, 13, 14)
4664 12:14:24.141084 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4665 12:14:24.144433 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4666 12:14:24.144529
4667 12:14:24.148371 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4668 12:14:24.151059 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4669 12:14:24.154907 [Gating] SW calibration Done
4670 12:14:24.154987 ==
4671 12:14:24.158177 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 12:14:24.161455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 12:14:24.161539 ==
4674 12:14:24.164769 RX Vref Scan: 0
4675 12:14:24.164856
4676 12:14:24.164922 RX Vref 0 -> 0, step: 1
4677 12:14:24.164987
4678 12:14:24.168016 RX Delay -230 -> 252, step: 16
4679 12:14:24.174474 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4680 12:14:24.178374 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4681 12:14:24.181590 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4682 12:14:24.184882 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4683 12:14:24.188083 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4684 12:14:24.194644 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4685 12:14:24.198125 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4686 12:14:24.201479 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4687 12:14:24.204644 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4688 12:14:24.211172 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4689 12:14:24.214446 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4690 12:14:24.217704 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4691 12:14:24.221596 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4692 12:14:24.228116 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4693 12:14:24.231294 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4694 12:14:24.234491 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4695 12:14:24.234570 ==
4696 12:14:24.237754 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:14:24.241425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:14:24.241541 ==
4699 12:14:24.244666 DQS Delay:
4700 12:14:24.244765 DQS0 = 0, DQS1 = 0
4701 12:14:24.247984 DQM Delay:
4702 12:14:24.248066 DQM0 = 39, DQM1 = 35
4703 12:14:24.248132 DQ Delay:
4704 12:14:24.251332 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4705 12:14:24.254609 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4706 12:14:24.257534 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4707 12:14:24.260963 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4708 12:14:24.261065
4709 12:14:24.261159
4710 12:14:24.264261 ==
4711 12:14:24.264339 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 12:14:24.271497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 12:14:24.271580 ==
4714 12:14:24.271646
4715 12:14:24.271707
4716 12:14:24.271765 TX Vref Scan disable
4717 12:14:24.274806 == TX Byte 0 ==
4718 12:14:24.278741 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 12:14:24.285131 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 12:14:24.285241 == TX Byte 1 ==
4721 12:14:24.288428 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4722 12:14:24.295026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4723 12:14:24.295121 ==
4724 12:14:24.298355 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 12:14:24.301636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 12:14:24.301748 ==
4727 12:14:24.301842
4728 12:14:24.301932
4729 12:14:24.305023 TX Vref Scan disable
4730 12:14:24.308265 == TX Byte 0 ==
4731 12:14:24.311650 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4732 12:14:24.314936 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4733 12:14:24.318222 == TX Byte 1 ==
4734 12:14:24.321576 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 12:14:24.324682 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 12:14:24.324804
4737 12:14:24.324916 [DATLAT]
4738 12:14:24.327981 Freq=600, CH1 RK1
4739 12:14:24.328058
4740 12:14:24.331198 DATLAT Default: 0x9
4741 12:14:24.331306 0, 0xFFFF, sum = 0
4742 12:14:24.334661 1, 0xFFFF, sum = 0
4743 12:14:24.334777 2, 0xFFFF, sum = 0
4744 12:14:24.337740 3, 0xFFFF, sum = 0
4745 12:14:24.337824 4, 0xFFFF, sum = 0
4746 12:14:24.340915 5, 0xFFFF, sum = 0
4747 12:14:24.341014 6, 0xFFFF, sum = 0
4748 12:14:24.344195 7, 0xFFFF, sum = 0
4749 12:14:24.344279 8, 0x0, sum = 1
4750 12:14:24.347609 9, 0x0, sum = 2
4751 12:14:24.347693 10, 0x0, sum = 3
4752 12:14:24.351246 11, 0x0, sum = 4
4753 12:14:24.351328 best_step = 9
4754 12:14:24.351416
4755 12:14:24.351485 ==
4756 12:14:24.354621 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 12:14:24.357945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 12:14:24.358025 ==
4759 12:14:24.361217 RX Vref Scan: 0
4760 12:14:24.361307
4761 12:14:24.364214 RX Vref 0 -> 0, step: 1
4762 12:14:24.364298
4763 12:14:24.364429 RX Delay -195 -> 252, step: 8
4764 12:14:24.372152 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4765 12:14:24.375552 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4766 12:14:24.378865 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4767 12:14:24.382104 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4768 12:14:24.388611 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4769 12:14:24.391794 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4770 12:14:24.395058 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4771 12:14:24.398302 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4772 12:14:24.404901 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4773 12:14:24.408229 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4774 12:14:24.411509 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4775 12:14:24.415501 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4776 12:14:24.418727 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4777 12:14:24.425008 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4778 12:14:24.428168 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4779 12:14:24.431469 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4780 12:14:24.431563 ==
4781 12:14:24.435287 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 12:14:24.441699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 12:14:24.441813 ==
4784 12:14:24.441909 DQS Delay:
4785 12:14:24.442008 DQS0 = 0, DQS1 = 0
4786 12:14:24.444861 DQM Delay:
4787 12:14:24.444940 DQM0 = 39, DQM1 = 34
4788 12:14:24.447985 DQ Delay:
4789 12:14:24.451183 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4790 12:14:24.455061 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4791 12:14:24.455172 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4792 12:14:24.461121 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4793 12:14:24.461201
4794 12:14:24.461267
4795 12:14:24.467660 [DQSOSCAuto] RK1, (LSB)MR18= 0x3342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4796 12:14:24.470886 CH1 RK1: MR19=808, MR18=3342
4797 12:14:24.477606 CH1_RK1: MR19=0x808, MR18=0x3342, DQSOSC=397, MR23=63, INC=166, DEC=110
4798 12:14:24.481021 [RxdqsGatingPostProcess] freq 600
4799 12:14:24.484358 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4800 12:14:24.487599 Pre-setting of DQS Precalculation
4801 12:14:24.494598 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4802 12:14:24.501068 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4803 12:14:24.507849 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4804 12:14:24.507973
4805 12:14:24.508069
4806 12:14:24.511169 [Calibration Summary] 1200 Mbps
4807 12:14:24.511251 CH 0, Rank 0
4808 12:14:24.514515 SW Impedance : PASS
4809 12:14:24.517812 DUTY Scan : NO K
4810 12:14:24.517908 ZQ Calibration : PASS
4811 12:14:24.521008 Jitter Meter : NO K
4812 12:14:24.524275 CBT Training : PASS
4813 12:14:24.524359 Write leveling : PASS
4814 12:14:24.527744 RX DQS gating : PASS
4815 12:14:24.531018 RX DQ/DQS(RDDQC) : PASS
4816 12:14:24.531112 TX DQ/DQS : PASS
4817 12:14:24.533790 RX DATLAT : PASS
4818 12:14:24.537471 RX DQ/DQS(Engine): PASS
4819 12:14:24.537556 TX OE : NO K
4820 12:14:24.540660 All Pass.
4821 12:14:24.540737
4822 12:14:24.540801 CH 0, Rank 1
4823 12:14:24.543809 SW Impedance : PASS
4824 12:14:24.543908 DUTY Scan : NO K
4825 12:14:24.547117 ZQ Calibration : PASS
4826 12:14:24.550788 Jitter Meter : NO K
4827 12:14:24.550864 CBT Training : PASS
4828 12:14:24.554010 Write leveling : PASS
4829 12:14:24.554131 RX DQS gating : PASS
4830 12:14:24.557166 RX DQ/DQS(RDDQC) : PASS
4831 12:14:24.560519 TX DQ/DQS : PASS
4832 12:14:24.560602 RX DATLAT : PASS
4833 12:14:24.563793 RX DQ/DQS(Engine): PASS
4834 12:14:24.567022 TX OE : NO K
4835 12:14:24.567122 All Pass.
4836 12:14:24.567188
4837 12:14:24.567250 CH 1, Rank 0
4838 12:14:24.570307 SW Impedance : PASS
4839 12:14:24.573550 DUTY Scan : NO K
4840 12:14:24.573648 ZQ Calibration : PASS
4841 12:14:24.576924 Jitter Meter : NO K
4842 12:14:24.580199 CBT Training : PASS
4843 12:14:24.580298 Write leveling : PASS
4844 12:14:24.583709 RX DQS gating : PASS
4845 12:14:24.586983 RX DQ/DQS(RDDQC) : PASS
4846 12:14:24.587082 TX DQ/DQS : PASS
4847 12:14:24.590310 RX DATLAT : PASS
4848 12:14:24.593688 RX DQ/DQS(Engine): PASS
4849 12:14:24.593770 TX OE : NO K
4850 12:14:24.596805 All Pass.
4851 12:14:24.596904
4852 12:14:24.597001 CH 1, Rank 1
4853 12:14:24.599977 SW Impedance : PASS
4854 12:14:24.600076 DUTY Scan : NO K
4855 12:14:24.603771 ZQ Calibration : PASS
4856 12:14:24.607134 Jitter Meter : NO K
4857 12:14:24.607222 CBT Training : PASS
4858 12:14:24.610624 Write leveling : PASS
4859 12:14:24.613818 RX DQS gating : PASS
4860 12:14:24.613933 RX DQ/DQS(RDDQC) : PASS
4861 12:14:24.616508 TX DQ/DQS : PASS
4862 12:14:24.616593 RX DATLAT : PASS
4863 12:14:24.619811 RX DQ/DQS(Engine): PASS
4864 12:14:24.623670 TX OE : NO K
4865 12:14:24.623786 All Pass.
4866 12:14:24.623878
4867 12:14:24.626972 DramC Write-DBI off
4868 12:14:24.627078 PER_BANK_REFRESH: Hybrid Mode
4869 12:14:24.630297 TX_TRACKING: ON
4870 12:14:24.639997 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4871 12:14:24.643185 [FAST_K] Save calibration result to emmc
4872 12:14:24.646539 dramc_set_vcore_voltage set vcore to 662500
4873 12:14:24.646623 Read voltage for 933, 3
4874 12:14:24.650307 Vio18 = 0
4875 12:14:24.650392 Vcore = 662500
4876 12:14:24.650459 Vdram = 0
4877 12:14:24.653512 Vddq = 0
4878 12:14:24.653598 Vmddr = 0
4879 12:14:24.656721 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4880 12:14:24.663069 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4881 12:14:24.666401 MEM_TYPE=3, freq_sel=17
4882 12:14:24.669689 sv_algorithm_assistance_LP4_1600
4883 12:14:24.673027 ============ PULL DRAM RESETB DOWN ============
4884 12:14:24.676397 ========== PULL DRAM RESETB DOWN end =========
4885 12:14:24.682929 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4886 12:14:24.686303 ===================================
4887 12:14:24.686389 LPDDR4 DRAM CONFIGURATION
4888 12:14:24.689641 ===================================
4889 12:14:24.692866 EX_ROW_EN[0] = 0x0
4890 12:14:24.696192 EX_ROW_EN[1] = 0x0
4891 12:14:24.696293 LP4Y_EN = 0x0
4892 12:14:24.699521 WORK_FSP = 0x0
4893 12:14:24.699607 WL = 0x3
4894 12:14:24.702998 RL = 0x3
4895 12:14:24.703082 BL = 0x2
4896 12:14:24.706047 RPST = 0x0
4897 12:14:24.706130 RD_PRE = 0x0
4898 12:14:24.709451 WR_PRE = 0x1
4899 12:14:24.709534 WR_PST = 0x0
4900 12:14:24.712719 DBI_WR = 0x0
4901 12:14:24.712802 DBI_RD = 0x0
4902 12:14:24.716052 OTF = 0x1
4903 12:14:24.719425 ===================================
4904 12:14:24.722600 ===================================
4905 12:14:24.722674 ANA top config
4906 12:14:24.725847 ===================================
4907 12:14:24.729109 DLL_ASYNC_EN = 0
4908 12:14:24.732473 ALL_SLAVE_EN = 1
4909 12:14:24.735746 NEW_RANK_MODE = 1
4910 12:14:24.735821 DLL_IDLE_MODE = 1
4911 12:14:24.739124 LP45_APHY_COMB_EN = 1
4912 12:14:24.742394 TX_ODT_DIS = 1
4913 12:14:24.745612 NEW_8X_MODE = 1
4914 12:14:24.748973 ===================================
4915 12:14:24.752645 ===================================
4916 12:14:24.755898 data_rate = 1866
4917 12:14:24.755985 CKR = 1
4918 12:14:24.759067 DQ_P2S_RATIO = 8
4919 12:14:24.762151 ===================================
4920 12:14:24.765888 CA_P2S_RATIO = 8
4921 12:14:24.769159 DQ_CA_OPEN = 0
4922 12:14:24.772442 DQ_SEMI_OPEN = 0
4923 12:14:24.775732 CA_SEMI_OPEN = 0
4924 12:14:24.775841 CA_FULL_RATE = 0
4925 12:14:24.779075 DQ_CKDIV4_EN = 1
4926 12:14:24.782444 CA_CKDIV4_EN = 1
4927 12:14:24.785832 CA_PREDIV_EN = 0
4928 12:14:24.789189 PH8_DLY = 0
4929 12:14:24.791932 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4930 12:14:24.792004 DQ_AAMCK_DIV = 4
4931 12:14:24.795895 CA_AAMCK_DIV = 4
4932 12:14:24.799128 CA_ADMCK_DIV = 4
4933 12:14:24.802441 DQ_TRACK_CA_EN = 0
4934 12:14:24.805625 CA_PICK = 933
4935 12:14:24.808860 CA_MCKIO = 933
4936 12:14:24.808938 MCKIO_SEMI = 0
4937 12:14:24.811994 PLL_FREQ = 3732
4938 12:14:24.815375 DQ_UI_PI_RATIO = 32
4939 12:14:24.818555 CA_UI_PI_RATIO = 0
4940 12:14:24.821909 ===================================
4941 12:14:24.825199 ===================================
4942 12:14:24.828541 memory_type:LPDDR4
4943 12:14:24.828622 GP_NUM : 10
4944 12:14:24.831891 SRAM_EN : 1
4945 12:14:24.835191 MD32_EN : 0
4946 12:14:24.838426 ===================================
4947 12:14:24.838506 [ANA_INIT] >>>>>>>>>>>>>>
4948 12:14:24.842307 <<<<<< [CONFIGURE PHASE]: ANA_TX
4949 12:14:24.844862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4950 12:14:24.848845 ===================================
4951 12:14:24.852109 data_rate = 1866,PCW = 0X8f00
4952 12:14:24.855179 ===================================
4953 12:14:24.858328 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4954 12:14:24.864954 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 12:14:24.868170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 12:14:24.875202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4957 12:14:24.878418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4958 12:14:24.881705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4959 12:14:24.881788 [ANA_INIT] flow start
4960 12:14:24.884984 [ANA_INIT] PLL >>>>>>>>
4961 12:14:24.888213 [ANA_INIT] PLL <<<<<<<<
4962 12:14:24.891613 [ANA_INIT] MIDPI >>>>>>>>
4963 12:14:24.891696 [ANA_INIT] MIDPI <<<<<<<<
4964 12:14:24.895106 [ANA_INIT] DLL >>>>>>>>
4965 12:14:24.898537 [ANA_INIT] flow end
4966 12:14:24.901868 ============ LP4 DIFF to SE enter ============
4967 12:14:24.905100 ============ LP4 DIFF to SE exit ============
4968 12:14:24.908411 [ANA_INIT] <<<<<<<<<<<<<
4969 12:14:24.911702 [Flow] Enable top DCM control >>>>>
4970 12:14:24.914972 [Flow] Enable top DCM control <<<<<
4971 12:14:24.918237 Enable DLL master slave shuffle
4972 12:14:24.921601 ==============================================================
4973 12:14:24.924953 Gating Mode config
4974 12:14:24.928297 ==============================================================
4975 12:14:24.931574 Config description:
4976 12:14:24.941394 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4977 12:14:24.948030 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4978 12:14:24.951440 SELPH_MODE 0: By rank 1: By Phase
4979 12:14:24.957899 ==============================================================
4980 12:14:24.960830 GAT_TRACK_EN = 1
4981 12:14:24.964743 RX_GATING_MODE = 2
4982 12:14:24.967971 RX_GATING_TRACK_MODE = 2
4983 12:14:24.970980 SELPH_MODE = 1
4984 12:14:24.974077 PICG_EARLY_EN = 1
4985 12:14:24.977845 VALID_LAT_VALUE = 1
4986 12:14:24.981060 ==============================================================
4987 12:14:24.984424 Enter into Gating configuration >>>>
4988 12:14:24.987745 Exit from Gating configuration <<<<
4989 12:14:24.991046 Enter into DVFS_PRE_config >>>>>
4990 12:14:25.004320 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4991 12:14:25.004411 Exit from DVFS_PRE_config <<<<<
4992 12:14:25.007048 Enter into PICG configuration >>>>
4993 12:14:25.011011 Exit from PICG configuration <<<<
4994 12:14:25.014271 [RX_INPUT] configuration >>>>>
4995 12:14:25.017548 [RX_INPUT] configuration <<<<<
4996 12:14:25.024277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4997 12:14:25.027709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4998 12:14:25.034290 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 12:14:25.040963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 12:14:25.047576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5001 12:14:25.054177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5002 12:14:25.057515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5003 12:14:25.060758 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5004 12:14:25.063874 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5005 12:14:25.070829 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5006 12:14:25.073948 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5007 12:14:25.077602 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 12:14:25.080785 ===================================
5009 12:14:25.083918 LPDDR4 DRAM CONFIGURATION
5010 12:14:25.087688 ===================================
5011 12:14:25.087774 EX_ROW_EN[0] = 0x0
5012 12:14:25.090394 EX_ROW_EN[1] = 0x0
5013 12:14:25.090477 LP4Y_EN = 0x0
5014 12:14:25.093801 WORK_FSP = 0x0
5015 12:14:25.097265 WL = 0x3
5016 12:14:25.097390 RL = 0x3
5017 12:14:25.100636 BL = 0x2
5018 12:14:25.100737 RPST = 0x0
5019 12:14:25.103970 RD_PRE = 0x0
5020 12:14:25.104076 WR_PRE = 0x1
5021 12:14:25.107217 WR_PST = 0x0
5022 12:14:25.107327 DBI_WR = 0x0
5023 12:14:25.110665 DBI_RD = 0x0
5024 12:14:25.110773 OTF = 0x1
5025 12:14:25.113918 ===================================
5026 12:14:25.117206 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5027 12:14:25.123711 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5028 12:14:25.127004 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 12:14:25.130200 ===================================
5030 12:14:25.133610 LPDDR4 DRAM CONFIGURATION
5031 12:14:25.136845 ===================================
5032 12:14:25.136952 EX_ROW_EN[0] = 0x10
5033 12:14:25.140222 EX_ROW_EN[1] = 0x0
5034 12:14:25.140307 LP4Y_EN = 0x0
5035 12:14:25.143633 WORK_FSP = 0x0
5036 12:14:25.143708 WL = 0x3
5037 12:14:25.147019 RL = 0x3
5038 12:14:25.147093 BL = 0x2
5039 12:14:25.150314 RPST = 0x0
5040 12:14:25.153619 RD_PRE = 0x0
5041 12:14:25.153690 WR_PRE = 0x1
5042 12:14:25.156876 WR_PST = 0x0
5043 12:14:25.156967 DBI_WR = 0x0
5044 12:14:25.160147 DBI_RD = 0x0
5045 12:14:25.160231 OTF = 0x1
5046 12:14:25.163476 ===================================
5047 12:14:25.170430 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5048 12:14:25.174235 nWR fixed to 30
5049 12:14:25.177475 [ModeRegInit_LP4] CH0 RK0
5050 12:14:25.177553 [ModeRegInit_LP4] CH0 RK1
5051 12:14:25.180613 [ModeRegInit_LP4] CH1 RK0
5052 12:14:25.183771 [ModeRegInit_LP4] CH1 RK1
5053 12:14:25.183848 match AC timing 9
5054 12:14:25.190758 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5055 12:14:25.193949 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5056 12:14:25.197243 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5057 12:14:25.203895 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5058 12:14:25.207247 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5059 12:14:25.207372 ==
5060 12:14:25.210589 Dram Type= 6, Freq= 0, CH_0, rank 0
5061 12:14:25.213878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 12:14:25.213971 ==
5063 12:14:25.220737 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 12:14:25.226690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5065 12:14:25.229850 [CA 0] Center 38 (8~69) winsize 62
5066 12:14:25.233187 [CA 1] Center 37 (7~68) winsize 62
5067 12:14:25.236510 [CA 2] Center 35 (5~66) winsize 62
5068 12:14:25.239830 [CA 3] Center 34 (4~65) winsize 62
5069 12:14:25.243136 [CA 4] Center 34 (4~65) winsize 62
5070 12:14:25.246496 [CA 5] Center 34 (4~64) winsize 61
5071 12:14:25.246568
5072 12:14:25.249813 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5073 12:14:25.249886
5074 12:14:25.253187 [CATrainingPosCal] consider 1 rank data
5075 12:14:25.256526 u2DelayCellTimex100 = 270/100 ps
5076 12:14:25.259872 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5077 12:14:25.263194 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5078 12:14:25.266482 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5079 12:14:25.269868 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5080 12:14:25.276285 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5081 12:14:25.279998 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5082 12:14:25.280081
5083 12:14:25.283219 CA PerBit enable=1, Macro0, CA PI delay=34
5084 12:14:25.283331
5085 12:14:25.286434 [CBTSetCACLKResult] CA Dly = 34
5086 12:14:25.286546 CS Dly: 6 (0~37)
5087 12:14:25.286611 ==
5088 12:14:25.289544 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 12:14:25.293493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 12:14:25.296617 ==
5091 12:14:25.299984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5092 12:14:25.306529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5093 12:14:25.309694 [CA 0] Center 38 (7~69) winsize 63
5094 12:14:25.312931 [CA 1] Center 38 (7~69) winsize 63
5095 12:14:25.316192 [CA 2] Center 35 (5~66) winsize 62
5096 12:14:25.319564 [CA 3] Center 35 (5~66) winsize 62
5097 12:14:25.322822 [CA 4] Center 34 (3~65) winsize 63
5098 12:14:25.326095 [CA 5] Center 33 (3~64) winsize 62
5099 12:14:25.326180
5100 12:14:25.329485 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5101 12:14:25.329570
5102 12:14:25.332794 [CATrainingPosCal] consider 2 rank data
5103 12:14:25.336059 u2DelayCellTimex100 = 270/100 ps
5104 12:14:25.339282 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5105 12:14:25.342636 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5106 12:14:25.345921 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5107 12:14:25.353180 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5108 12:14:25.356485 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5109 12:14:25.359153 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5110 12:14:25.359264
5111 12:14:25.363045 CA PerBit enable=1, Macro0, CA PI delay=34
5112 12:14:25.363130
5113 12:14:25.366285 [CBTSetCACLKResult] CA Dly = 34
5114 12:14:25.366372 CS Dly: 7 (0~39)
5115 12:14:25.366440
5116 12:14:25.369482 ----->DramcWriteLeveling(PI) begin...
5117 12:14:25.369569 ==
5118 12:14:25.372796 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 12:14:25.379246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 12:14:25.379364 ==
5121 12:14:25.382384 Write leveling (Byte 0): 33 => 33
5122 12:14:25.385657 Write leveling (Byte 1): 27 => 27
5123 12:14:25.385742 DramcWriteLeveling(PI) end<-----
5124 12:14:25.389495
5125 12:14:25.389581 ==
5126 12:14:25.392710 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 12:14:25.395936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5128 12:14:25.396022 ==
5129 12:14:25.399133 [Gating] SW mode calibration
5130 12:14:25.405585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5131 12:14:25.408758 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5132 12:14:25.415491 0 14 0 | B1->B0 | 2323 2f2f | 1 0 | (1 1) (0 0)
5133 12:14:25.418791 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5134 12:14:25.422232 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 12:14:25.428796 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 12:14:25.432177 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 12:14:25.435457 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 12:14:25.442014 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 12:14:25.445449 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5140 12:14:25.448553 0 15 0 | B1->B0 | 3030 2d2d | 0 1 | (0 0) (1 0)
5141 12:14:25.455234 0 15 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
5142 12:14:25.458612 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 12:14:25.461917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 12:14:25.469036 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 12:14:25.472250 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 12:14:25.475511 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 12:14:25.482037 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5148 12:14:25.485310 1 0 0 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
5149 12:14:25.488505 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 12:14:25.495660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 12:14:25.498854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 12:14:25.502017 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 12:14:25.508527 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 12:14:25.511827 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 12:14:25.515172 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5156 12:14:25.521789 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5157 12:14:25.525096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:14:25.528321 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:14:25.535495 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:14:25.538734 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:14:25.542010 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:14:25.548452 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:14:25.551856 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:14:25.555217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:14:25.558448 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:14:25.565214 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:14:25.568585 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:14:25.571932 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:14:25.578451 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:14:25.581810 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:14:25.585128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5172 12:14:25.591681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5173 12:14:25.594909 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 12:14:25.598639 Total UI for P1: 0, mck2ui 16
5175 12:14:25.601893 best dqsien dly found for B0: ( 1, 2, 30)
5176 12:14:25.605166 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 12:14:25.608422 Total UI for P1: 0, mck2ui 16
5178 12:14:25.611738 best dqsien dly found for B1: ( 1, 3, 0)
5179 12:14:25.615041 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5180 12:14:25.618236 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5181 12:14:25.618313
5182 12:14:25.624857 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5183 12:14:25.628009 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5184 12:14:25.628114 [Gating] SW calibration Done
5185 12:14:25.631925 ==
5186 12:14:25.632028 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 12:14:25.637954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 12:14:25.638061 ==
5189 12:14:25.638158 RX Vref Scan: 0
5190 12:14:25.638259
5191 12:14:25.641199 RX Vref 0 -> 0, step: 1
5192 12:14:25.641300
5193 12:14:25.644572 RX Delay -80 -> 252, step: 8
5194 12:14:25.648387 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5195 12:14:25.651638 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5196 12:14:25.654947 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5197 12:14:25.661502 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5198 12:14:25.664842 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5199 12:14:25.668055 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5200 12:14:25.671380 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5201 12:14:25.674643 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5202 12:14:25.677910 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5203 12:14:25.684481 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5204 12:14:25.687856 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5205 12:14:25.691174 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5206 12:14:25.695080 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5207 12:14:25.698180 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5208 12:14:25.704378 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5209 12:14:25.708216 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5210 12:14:25.708299 ==
5211 12:14:25.711412 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 12:14:25.714782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 12:14:25.714866 ==
5214 12:14:25.714932 DQS Delay:
5215 12:14:25.717925 DQS0 = 0, DQS1 = 0
5216 12:14:25.718040 DQM Delay:
5217 12:14:25.721198 DQM0 = 97, DQM1 = 86
5218 12:14:25.721282 DQ Delay:
5219 12:14:25.724476 DQ0 =95, DQ1 =103, DQ2 =91, DQ3 =91
5220 12:14:25.727620 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5221 12:14:25.730890 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5222 12:14:25.734222 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5223 12:14:25.734306
5224 12:14:25.734372
5225 12:14:25.734434 ==
5226 12:14:25.737609 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 12:14:25.744151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 12:14:25.744234 ==
5229 12:14:25.744301
5230 12:14:25.744364
5231 12:14:25.744423 TX Vref Scan disable
5232 12:14:25.748153 == TX Byte 0 ==
5233 12:14:25.751466 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5234 12:14:25.757947 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5235 12:14:25.758030 == TX Byte 1 ==
5236 12:14:25.761226 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5237 12:14:25.767824 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5238 12:14:25.767910 ==
5239 12:14:25.771158 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 12:14:25.774531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 12:14:25.774617 ==
5242 12:14:25.774682
5243 12:14:25.774742
5244 12:14:25.777857 TX Vref Scan disable
5245 12:14:25.777956 == TX Byte 0 ==
5246 12:14:25.784280 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5247 12:14:25.787621 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5248 12:14:25.790943 == TX Byte 1 ==
5249 12:14:25.794231 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5250 12:14:25.797551 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5251 12:14:25.797652
5252 12:14:25.797747 [DATLAT]
5253 12:14:25.800649 Freq=933, CH0 RK0
5254 12:14:25.800742
5255 12:14:25.800818 DATLAT Default: 0xd
5256 12:14:25.804418 0, 0xFFFF, sum = 0
5257 12:14:25.804494 1, 0xFFFF, sum = 0
5258 12:14:25.807545 2, 0xFFFF, sum = 0
5259 12:14:25.810689 3, 0xFFFF, sum = 0
5260 12:14:25.810792 4, 0xFFFF, sum = 0
5261 12:14:25.813919 5, 0xFFFF, sum = 0
5262 12:14:25.814034 6, 0xFFFF, sum = 0
5263 12:14:25.817688 7, 0xFFFF, sum = 0
5264 12:14:25.817787 8, 0xFFFF, sum = 0
5265 12:14:25.820956 9, 0xFFFF, sum = 0
5266 12:14:25.821060 10, 0x0, sum = 1
5267 12:14:25.824283 11, 0x0, sum = 2
5268 12:14:25.824383 12, 0x0, sum = 3
5269 12:14:25.824475 13, 0x0, sum = 4
5270 12:14:25.827451 best_step = 11
5271 12:14:25.827548
5272 12:14:25.827636 ==
5273 12:14:25.830816 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 12:14:25.834101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 12:14:25.834178 ==
5276 12:14:25.837449 RX Vref Scan: 1
5277 12:14:25.837546
5278 12:14:25.840713 RX Vref 0 -> 0, step: 1
5279 12:14:25.840784
5280 12:14:25.840845 RX Delay -69 -> 252, step: 4
5281 12:14:25.840911
5282 12:14:25.844033 Set Vref, RX VrefLevel [Byte0]: 55
5283 12:14:25.847223 [Byte1]: 50
5284 12:14:25.852004
5285 12:14:25.852127 Final RX Vref Byte 0 = 55 to rank0
5286 12:14:25.855285 Final RX Vref Byte 1 = 50 to rank0
5287 12:14:25.858844 Final RX Vref Byte 0 = 55 to rank1
5288 12:14:25.862034 Final RX Vref Byte 1 = 50 to rank1==
5289 12:14:25.865457 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 12:14:25.871954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 12:14:25.872066 ==
5292 12:14:25.872135 DQS Delay:
5293 12:14:25.872196 DQS0 = 0, DQS1 = 0
5294 12:14:25.875372 DQM Delay:
5295 12:14:25.875459 DQM0 = 97, DQM1 = 87
5296 12:14:25.878641 DQ Delay:
5297 12:14:25.881940 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5298 12:14:25.885221 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5299 12:14:25.888574 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =82
5300 12:14:25.891959 DQ12 =94, DQ13 =90, DQ14 =102, DQ15 =96
5301 12:14:25.892059
5302 12:14:25.892150
5303 12:14:25.898056 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5304 12:14:25.901389 CH0 RK0: MR19=504, MR18=11FC
5305 12:14:25.908250 CH0_RK0: MR19=0x504, MR18=0x11FC, DQSOSC=416, MR23=63, INC=62, DEC=41
5306 12:14:25.908353
5307 12:14:25.911512 ----->DramcWriteLeveling(PI) begin...
5308 12:14:25.911587 ==
5309 12:14:25.914613 Dram Type= 6, Freq= 0, CH_0, rank 1
5310 12:14:25.918509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 12:14:25.918583 ==
5312 12:14:25.921697 Write leveling (Byte 0): 30 => 30
5313 12:14:25.924908 Write leveling (Byte 1): 28 => 28
5314 12:14:25.928239 DramcWriteLeveling(PI) end<-----
5315 12:14:25.928388
5316 12:14:25.928500 ==
5317 12:14:25.931403 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 12:14:25.934759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 12:14:25.934875 ==
5320 12:14:25.938054 [Gating] SW mode calibration
5321 12:14:25.944730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5322 12:14:25.951432 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5323 12:14:25.954650 0 14 0 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
5324 12:14:25.961345 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5325 12:14:25.964446 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 12:14:25.968336 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 12:14:25.974961 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 12:14:25.978160 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 12:14:25.981429 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5330 12:14:25.987939 0 14 28 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (0 0)
5331 12:14:25.991296 0 15 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
5332 12:14:25.994658 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5333 12:14:26.001261 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 12:14:26.004404 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 12:14:26.007679 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 12:14:26.011423 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 12:14:26.017822 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 12:14:26.021032 0 15 28 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
5339 12:14:26.024295 1 0 0 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
5340 12:14:26.031199 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 12:14:26.034542 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 12:14:26.037820 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 12:14:26.044449 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 12:14:26.047704 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 12:14:26.050966 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:14:26.057554 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5347 12:14:26.060736 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 12:14:26.064065 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:14:26.070717 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:14:26.073962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 12:14:26.077382 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:14:26.083827 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:14:26.087167 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:14:26.090429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:14:26.096967 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:14:26.100350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:14:26.104253 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:14:26.110236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:14:26.114071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:14:26.117070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:14:26.124099 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:14:26.127282 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5363 12:14:26.130667 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5364 12:14:26.133663 Total UI for P1: 0, mck2ui 16
5365 12:14:26.137496 best dqsien dly found for B0: ( 1, 2, 28)
5366 12:14:26.144076 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 12:14:26.144173 Total UI for P1: 0, mck2ui 16
5368 12:14:26.147323 best dqsien dly found for B1: ( 1, 3, 0)
5369 12:14:26.153839 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5370 12:14:26.157105 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5371 12:14:26.157211
5372 12:14:26.160349 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5373 12:14:26.163577 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5374 12:14:26.166906 [Gating] SW calibration Done
5375 12:14:26.167012 ==
5376 12:14:26.170207 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 12:14:26.173386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 12:14:26.173488 ==
5379 12:14:26.176584 RX Vref Scan: 0
5380 12:14:26.176689
5381 12:14:26.176785 RX Vref 0 -> 0, step: 1
5382 12:14:26.176877
5383 12:14:26.180539 RX Delay -80 -> 252, step: 8
5384 12:14:26.183167 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5385 12:14:26.186483 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5386 12:14:26.193626 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5387 12:14:26.196830 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5388 12:14:26.200097 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5389 12:14:26.203485 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5390 12:14:26.206638 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5391 12:14:26.210035 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5392 12:14:26.216576 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5393 12:14:26.219872 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5394 12:14:26.223582 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5395 12:14:26.226699 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5396 12:14:26.229833 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5397 12:14:26.236430 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5398 12:14:26.240180 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5399 12:14:26.243534 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5400 12:14:26.243619 ==
5401 12:14:26.246787 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 12:14:26.250012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 12:14:26.250124 ==
5404 12:14:26.253204 DQS Delay:
5405 12:14:26.253288 DQS0 = 0, DQS1 = 0
5406 12:14:26.253354 DQM Delay:
5407 12:14:26.256500 DQM0 = 97, DQM1 = 87
5408 12:14:26.256597 DQ Delay:
5409 12:14:26.259844 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5410 12:14:26.263101 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5411 12:14:26.267025 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =75
5412 12:14:26.270277 DQ12 =87, DQ13 =95, DQ14 =99, DQ15 =95
5413 12:14:26.270369
5414 12:14:26.270464
5415 12:14:26.270539 ==
5416 12:14:26.273562 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 12:14:26.279990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 12:14:26.280080 ==
5419 12:14:26.280197
5420 12:14:26.280292
5421 12:14:26.280389 TX Vref Scan disable
5422 12:14:26.283252 == TX Byte 0 ==
5423 12:14:26.287144 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5424 12:14:26.293661 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5425 12:14:26.293763 == TX Byte 1 ==
5426 12:14:26.296892 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5427 12:14:26.303535 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5428 12:14:26.303619 ==
5429 12:14:26.306730 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 12:14:26.309968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 12:14:26.310053 ==
5432 12:14:26.310120
5433 12:14:26.310183
5434 12:14:26.313119 TX Vref Scan disable
5435 12:14:26.313220 == TX Byte 0 ==
5436 12:14:26.319761 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5437 12:14:26.323077 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5438 12:14:26.323191 == TX Byte 1 ==
5439 12:14:26.329825 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5440 12:14:26.332991 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5441 12:14:26.333072
5442 12:14:26.333138 [DATLAT]
5443 12:14:26.336856 Freq=933, CH0 RK1
5444 12:14:26.336937
5445 12:14:26.337003 DATLAT Default: 0xb
5446 12:14:26.340155 0, 0xFFFF, sum = 0
5447 12:14:26.340246 1, 0xFFFF, sum = 0
5448 12:14:26.343259 2, 0xFFFF, sum = 0
5449 12:14:26.343368 3, 0xFFFF, sum = 0
5450 12:14:26.346463 4, 0xFFFF, sum = 0
5451 12:14:26.346549 5, 0xFFFF, sum = 0
5452 12:14:26.349696 6, 0xFFFF, sum = 0
5453 12:14:26.353001 7, 0xFFFF, sum = 0
5454 12:14:26.353090 8, 0xFFFF, sum = 0
5455 12:14:26.356872 9, 0xFFFF, sum = 0
5456 12:14:26.356983 10, 0x0, sum = 1
5457 12:14:26.357100 11, 0x0, sum = 2
5458 12:14:26.360172 12, 0x0, sum = 3
5459 12:14:26.360271 13, 0x0, sum = 4
5460 12:14:26.363550 best_step = 11
5461 12:14:26.363639
5462 12:14:26.363709 ==
5463 12:14:26.366749 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 12:14:26.369953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 12:14:26.370041 ==
5466 12:14:26.373206 RX Vref Scan: 0
5467 12:14:26.373294
5468 12:14:26.373367 RX Vref 0 -> 0, step: 1
5469 12:14:26.373428
5470 12:14:26.376539 RX Delay -61 -> 252, step: 4
5471 12:14:26.383715 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5472 12:14:26.386909 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5473 12:14:26.390838 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5474 12:14:26.393979 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5475 12:14:26.397209 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5476 12:14:26.400525 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5477 12:14:26.407197 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5478 12:14:26.410597 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5479 12:14:26.413861 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5480 12:14:26.417113 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5481 12:14:26.420469 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5482 12:14:26.426916 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5483 12:14:26.430146 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5484 12:14:26.433401 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5485 12:14:26.437152 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5486 12:14:26.440311 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5487 12:14:26.440396 ==
5488 12:14:26.443359 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 12:14:26.449796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 12:14:26.449910 ==
5491 12:14:26.450006 DQS Delay:
5492 12:14:26.453751 DQS0 = 0, DQS1 = 0
5493 12:14:26.453834 DQM Delay:
5494 12:14:26.453902 DQM0 = 95, DQM1 = 87
5495 12:14:26.456940 DQ Delay:
5496 12:14:26.460283 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5497 12:14:26.463548 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =104
5498 12:14:26.466828 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5499 12:14:26.470092 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5500 12:14:26.470176
5501 12:14:26.470243
5502 12:14:26.476849 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5503 12:14:26.479578 CH0 RK1: MR19=505, MR18=1805
5504 12:14:26.486774 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5505 12:14:26.490034 [RxdqsGatingPostProcess] freq 933
5506 12:14:26.493102 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 12:14:26.496417 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 12:14:26.499604 best DQS1 dly(2T, 0.5T) = (0, 11)
5509 12:14:26.502874 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 12:14:26.506172 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5511 12:14:26.509481 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 12:14:26.513307 best DQS1 dly(2T, 0.5T) = (0, 11)
5513 12:14:26.516598 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 12:14:26.519897 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5515 12:14:26.523211 Pre-setting of DQS Precalculation
5516 12:14:26.526478 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 12:14:26.529793 ==
5518 12:14:26.529878 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 12:14:26.536125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 12:14:26.536209 ==
5521 12:14:26.539932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 12:14:26.546325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 12:14:26.549537 [CA 0] Center 36 (6~67) winsize 62
5524 12:14:26.553279 [CA 1] Center 36 (6~67) winsize 62
5525 12:14:26.556632 [CA 2] Center 34 (4~65) winsize 62
5526 12:14:26.559924 [CA 3] Center 33 (3~64) winsize 62
5527 12:14:26.563107 [CA 4] Center 34 (4~65) winsize 62
5528 12:14:26.566473 [CA 5] Center 33 (3~64) winsize 62
5529 12:14:26.566558
5530 12:14:26.569560 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 12:14:26.569645
5532 12:14:26.572845 [CATrainingPosCal] consider 1 rank data
5533 12:14:26.576193 u2DelayCellTimex100 = 270/100 ps
5534 12:14:26.579647 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 12:14:26.586338 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 12:14:26.589672 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5537 12:14:26.592843 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 12:14:26.596097 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 12:14:26.599952 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5540 12:14:26.600035
5541 12:14:26.603197 CA PerBit enable=1, Macro0, CA PI delay=33
5542 12:14:26.603279
5543 12:14:26.606560 [CBTSetCACLKResult] CA Dly = 33
5544 12:14:26.606642 CS Dly: 4 (0~35)
5545 12:14:26.609944 ==
5546 12:14:26.610027 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 12:14:26.616439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 12:14:26.616521 ==
5549 12:14:26.619626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 12:14:26.626070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5551 12:14:26.629397 [CA 0] Center 36 (6~67) winsize 62
5552 12:14:26.633256 [CA 1] Center 36 (6~67) winsize 62
5553 12:14:26.636450 [CA 2] Center 34 (4~64) winsize 61
5554 12:14:26.639730 [CA 3] Center 33 (3~64) winsize 62
5555 12:14:26.642926 [CA 4] Center 34 (4~65) winsize 62
5556 12:14:26.645976 [CA 5] Center 33 (2~64) winsize 63
5557 12:14:26.646067
5558 12:14:26.649362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5559 12:14:26.649487
5560 12:14:26.653174 [CATrainingPosCal] consider 2 rank data
5561 12:14:26.656444 u2DelayCellTimex100 = 270/100 ps
5562 12:14:26.659602 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 12:14:26.666186 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 12:14:26.669532 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5565 12:14:26.672766 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5566 12:14:26.676123 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5567 12:14:26.679251 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5568 12:14:26.679346
5569 12:14:26.682551 CA PerBit enable=1, Macro0, CA PI delay=33
5570 12:14:26.682646
5571 12:14:26.685888 [CBTSetCACLKResult] CA Dly = 33
5572 12:14:26.686045 CS Dly: 5 (0~37)
5573 12:14:26.689246
5574 12:14:26.692476 ----->DramcWriteLeveling(PI) begin...
5575 12:14:26.692578 ==
5576 12:14:26.695870 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 12:14:26.699148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 12:14:26.699246 ==
5579 12:14:26.702903 Write leveling (Byte 0): 27 => 27
5580 12:14:26.706098 Write leveling (Byte 1): 27 => 27
5581 12:14:26.709458 DramcWriteLeveling(PI) end<-----
5582 12:14:26.709617
5583 12:14:26.709705 ==
5584 12:14:26.712664 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 12:14:26.715933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 12:14:26.716004 ==
5587 12:14:26.719162 [Gating] SW mode calibration
5588 12:14:26.725759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 12:14:26.732880 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 12:14:26.736195 0 14 0 | B1->B0 | 2f2f 3333 | 1 0 | (1 1) (0 0)
5591 12:14:26.739527 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 12:14:26.742934 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 12:14:26.749379 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 12:14:26.752611 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 12:14:26.759138 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 12:14:26.762272 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5597 12:14:26.765626 0 14 28 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 1)
5598 12:14:26.768977 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5599 12:14:26.775574 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 12:14:26.778897 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 12:14:26.782213 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5602 12:14:26.788911 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5603 12:14:26.792251 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 12:14:26.795634 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 12:14:26.802158 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 0)
5606 12:14:26.805900 1 0 0 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
5607 12:14:26.808955 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 12:14:26.815501 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 12:14:26.818936 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 12:14:26.822145 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 12:14:26.829235 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:14:26.832294 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:14:26.835602 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 12:14:26.842182 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 12:14:26.846042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:14:26.849409 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:14:26.855721 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:14:26.858906 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:14:26.862228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:14:26.868863 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:14:26.872081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:14:26.875326 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:14:26.881907 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:14:26.885182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:14:26.888399 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:14:26.894964 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:14:26.898460 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:14:26.901796 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5629 12:14:26.908210 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5630 12:14:26.911905 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 12:14:26.915166 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 12:14:26.918538 Total UI for P1: 0, mck2ui 16
5633 12:14:26.921914 best dqsien dly found for B0: ( 1, 2, 28)
5634 12:14:26.925193 Total UI for P1: 0, mck2ui 16
5635 12:14:26.928443 best dqsien dly found for B1: ( 1, 2, 30)
5636 12:14:26.931821 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5637 12:14:26.935037 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5638 12:14:26.935138
5639 12:14:26.938317 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5640 12:14:26.944928 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5641 12:14:26.945005 [Gating] SW calibration Done
5642 12:14:26.945071 ==
5643 12:14:26.948221 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 12:14:26.954762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 12:14:26.954889 ==
5646 12:14:26.954988 RX Vref Scan: 0
5647 12:14:26.955083
5648 12:14:26.958566 RX Vref 0 -> 0, step: 1
5649 12:14:26.958709
5650 12:14:26.961788 RX Delay -80 -> 252, step: 8
5651 12:14:26.965101 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5652 12:14:26.968537 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5653 12:14:26.971779 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5654 12:14:26.974496 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5655 12:14:26.981708 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5656 12:14:26.984944 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5657 12:14:26.988222 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5658 12:14:26.991547 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5659 12:14:26.994946 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5660 12:14:26.998256 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5661 12:14:27.004843 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5662 12:14:27.008103 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5663 12:14:27.011235 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5664 12:14:27.014404 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5665 12:14:27.018141 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5666 12:14:27.024657 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5667 12:14:27.024737 ==
5668 12:14:27.027909 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 12:14:27.031284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 12:14:27.031425 ==
5671 12:14:27.031493 DQS Delay:
5672 12:14:27.034616 DQS0 = 0, DQS1 = 0
5673 12:14:27.034716 DQM Delay:
5674 12:14:27.037960 DQM0 = 96, DQM1 = 88
5675 12:14:27.038059 DQ Delay:
5676 12:14:27.041344 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5677 12:14:27.044752 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5678 12:14:27.048178 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5679 12:14:27.051514 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5680 12:14:27.051600
5681 12:14:27.051667
5682 12:14:27.051728 ==
5683 12:14:27.054653 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 12:14:27.057922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 12:14:27.058006 ==
5686 12:14:27.058097
5687 12:14:27.061235
5688 12:14:27.061319 TX Vref Scan disable
5689 12:14:27.064370 == TX Byte 0 ==
5690 12:14:27.067697 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5691 12:14:27.071260 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5692 12:14:27.074594 == TX Byte 1 ==
5693 12:14:27.077917 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5694 12:14:27.081144 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5695 12:14:27.081228 ==
5696 12:14:27.084434 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 12:14:27.091071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 12:14:27.091159 ==
5699 12:14:27.091225
5700 12:14:27.091285
5701 12:14:27.091344 TX Vref Scan disable
5702 12:14:27.095001 == TX Byte 0 ==
5703 12:14:27.098243 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5704 12:14:27.104872 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5705 12:14:27.104955 == TX Byte 1 ==
5706 12:14:27.108160 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5707 12:14:27.114835 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5708 12:14:27.114919
5709 12:14:27.114984 [DATLAT]
5710 12:14:27.115045 Freq=933, CH1 RK0
5711 12:14:27.115105
5712 12:14:27.118071 DATLAT Default: 0xd
5713 12:14:27.118153 0, 0xFFFF, sum = 0
5714 12:14:27.121268 1, 0xFFFF, sum = 0
5715 12:14:27.124651 2, 0xFFFF, sum = 0
5716 12:14:27.124734 3, 0xFFFF, sum = 0
5717 12:14:27.127959 4, 0xFFFF, sum = 0
5718 12:14:27.128042 5, 0xFFFF, sum = 0
5719 12:14:27.131282 6, 0xFFFF, sum = 0
5720 12:14:27.131392 7, 0xFFFF, sum = 0
5721 12:14:27.134549 8, 0xFFFF, sum = 0
5722 12:14:27.134632 9, 0xFFFF, sum = 0
5723 12:14:27.137922 10, 0x0, sum = 1
5724 12:14:27.138029 11, 0x0, sum = 2
5725 12:14:27.141281 12, 0x0, sum = 3
5726 12:14:27.141360 13, 0x0, sum = 4
5727 12:14:27.141444 best_step = 11
5728 12:14:27.141511
5729 12:14:27.144523 ==
5730 12:14:27.147812 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 12:14:27.151060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 12:14:27.151165 ==
5733 12:14:27.151259 RX Vref Scan: 1
5734 12:14:27.151354
5735 12:14:27.154399 RX Vref 0 -> 0, step: 1
5736 12:14:27.154473
5737 12:14:27.157695 RX Delay -69 -> 252, step: 4
5738 12:14:27.157770
5739 12:14:27.160920 Set Vref, RX VrefLevel [Byte0]: 61
5740 12:14:27.164244 [Byte1]: 54
5741 12:14:27.167660
5742 12:14:27.167748 Final RX Vref Byte 0 = 61 to rank0
5743 12:14:27.170832 Final RX Vref Byte 1 = 54 to rank0
5744 12:14:27.173959 Final RX Vref Byte 0 = 61 to rank1
5745 12:14:27.177222 Final RX Vref Byte 1 = 54 to rank1==
5746 12:14:27.180971 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 12:14:27.187272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 12:14:27.187420 ==
5749 12:14:27.187516 DQS Delay:
5750 12:14:27.190523 DQS0 = 0, DQS1 = 0
5751 12:14:27.190628 DQM Delay:
5752 12:14:27.190721 DQM0 = 98, DQM1 = 91
5753 12:14:27.193934 DQ Delay:
5754 12:14:27.197224 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =100
5755 12:14:27.200641 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5756 12:14:27.203935 DQ8 =82, DQ9 =82, DQ10 =90, DQ11 =86
5757 12:14:27.207289 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =94
5758 12:14:27.207443
5759 12:14:27.207543
5760 12:14:27.213876 [DQSOSCAuto] RK0, (LSB)MR18= 0x15f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 415 ps
5761 12:14:27.217240 CH1 RK0: MR19=504, MR18=15F2
5762 12:14:27.223891 CH1_RK0: MR19=0x504, MR18=0x15F2, DQSOSC=415, MR23=63, INC=62, DEC=41
5763 12:14:27.224004
5764 12:14:27.227097 ----->DramcWriteLeveling(PI) begin...
5765 12:14:27.227207 ==
5766 12:14:27.230396 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 12:14:27.233693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 12:14:27.233799 ==
5769 12:14:27.236834 Write leveling (Byte 0): 28 => 28
5770 12:14:27.240746 Write leveling (Byte 1): 28 => 28
5771 12:14:27.243993 DramcWriteLeveling(PI) end<-----
5772 12:14:27.244092
5773 12:14:27.244177 ==
5774 12:14:27.247243 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 12:14:27.250423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 12:14:27.253742 ==
5777 12:14:27.253813 [Gating] SW mode calibration
5778 12:14:27.263703 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 12:14:27.266894 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 12:14:27.270347 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 12:14:27.276861 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 12:14:27.280064 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5783 12:14:27.283337 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5784 12:14:27.289727 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5785 12:14:27.292969 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 12:14:27.296322 0 14 24 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
5787 12:14:27.303092 0 14 28 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
5788 12:14:27.306374 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 12:14:27.309751 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 12:14:27.316324 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 12:14:27.319655 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 12:14:27.322946 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 12:14:27.329385 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 12:14:27.332606 0 15 24 | B1->B0 | 2827 3737 | 1 1 | (0 0) (0 0)
5795 12:14:27.336544 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5796 12:14:27.342897 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 12:14:27.346322 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 12:14:27.349526 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 12:14:27.356529 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 12:14:27.359831 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 12:14:27.363070 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 12:14:27.369603 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5803 12:14:27.373002 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5804 12:14:27.376239 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:14:27.382776 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:14:27.385919 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:14:27.389720 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:14:27.395903 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:14:27.399259 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:14:27.402673 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:14:27.405913 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:14:27.412685 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:14:27.415977 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:14:27.419279 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:14:27.425996 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:14:27.429032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:14:27.432652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5818 12:14:27.439198 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5819 12:14:27.442447 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5820 12:14:27.445718 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 12:14:27.449082 Total UI for P1: 0, mck2ui 16
5822 12:14:27.452481 best dqsien dly found for B0: ( 1, 2, 24)
5823 12:14:27.455892 Total UI for P1: 0, mck2ui 16
5824 12:14:27.459222 best dqsien dly found for B1: ( 1, 2, 28)
5825 12:14:27.462550 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5826 12:14:27.465759 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5827 12:14:27.465841
5828 12:14:27.472296 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5829 12:14:27.475541 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5830 12:14:27.478944 [Gating] SW calibration Done
5831 12:14:27.479027 ==
5832 12:14:27.482118 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 12:14:27.485452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 12:14:27.485583 ==
5835 12:14:27.485649 RX Vref Scan: 0
5836 12:14:27.485715
5837 12:14:27.489289 RX Vref 0 -> 0, step: 1
5838 12:14:27.489383
5839 12:14:27.492541 RX Delay -80 -> 252, step: 8
5840 12:14:27.495529 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5841 12:14:27.499134 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5842 12:14:27.502313 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5843 12:14:27.508863 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5844 12:14:27.512245 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5845 12:14:27.515572 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5846 12:14:27.518978 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5847 12:14:27.522226 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5848 12:14:27.525601 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5849 12:14:27.532097 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5850 12:14:27.535327 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5851 12:14:27.538501 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5852 12:14:27.542250 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5853 12:14:27.545414 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5854 12:14:27.551932 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5855 12:14:27.555258 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5856 12:14:27.555369 ==
5857 12:14:27.558550 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 12:14:27.561916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 12:14:27.562048 ==
5860 12:14:27.562140 DQS Delay:
5861 12:14:27.565158 DQS0 = 0, DQS1 = 0
5862 12:14:27.565240 DQM Delay:
5863 12:14:27.569027 DQM0 = 94, DQM1 = 89
5864 12:14:27.569109 DQ Delay:
5865 12:14:27.571725 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5866 12:14:27.575011 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5867 12:14:27.578799 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5868 12:14:27.582071 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5869 12:14:27.582167
5870 12:14:27.582233
5871 12:14:27.582293 ==
5872 12:14:27.585312 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 12:14:27.588642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 12:14:27.591927 ==
5875 12:14:27.592010
5876 12:14:27.592075
5877 12:14:27.592136 TX Vref Scan disable
5878 12:14:27.594976 == TX Byte 0 ==
5879 12:14:27.598172 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5880 12:14:27.601871 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5881 12:14:27.605219 == TX Byte 1 ==
5882 12:14:27.608512 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5883 12:14:27.611728 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5884 12:14:27.614962 ==
5885 12:14:27.618242 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 12:14:27.621561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 12:14:27.621647 ==
5888 12:14:27.621714
5889 12:14:27.621776
5890 12:14:27.624839 TX Vref Scan disable
5891 12:14:27.624923 == TX Byte 0 ==
5892 12:14:27.631516 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5893 12:14:27.634759 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5894 12:14:27.634860 == TX Byte 1 ==
5895 12:14:27.641856 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5896 12:14:27.644990 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5897 12:14:27.645068
5898 12:14:27.645134 [DATLAT]
5899 12:14:27.648112 Freq=933, CH1 RK1
5900 12:14:27.648231
5901 12:14:27.648326 DATLAT Default: 0xb
5902 12:14:27.651327 0, 0xFFFF, sum = 0
5903 12:14:27.651447 1, 0xFFFF, sum = 0
5904 12:14:27.654716 2, 0xFFFF, sum = 0
5905 12:14:27.654836 3, 0xFFFF, sum = 0
5906 12:14:27.658117 4, 0xFFFF, sum = 0
5907 12:14:27.658221 5, 0xFFFF, sum = 0
5908 12:14:27.661463 6, 0xFFFF, sum = 0
5909 12:14:27.661545 7, 0xFFFF, sum = 0
5910 12:14:27.664715 8, 0xFFFF, sum = 0
5911 12:14:27.664791 9, 0xFFFF, sum = 0
5912 12:14:27.667975 10, 0x0, sum = 1
5913 12:14:27.668049 11, 0x0, sum = 2
5914 12:14:27.671267 12, 0x0, sum = 3
5915 12:14:27.671373 13, 0x0, sum = 4
5916 12:14:27.674606 best_step = 11
5917 12:14:27.674709
5918 12:14:27.674799 ==
5919 12:14:27.678009 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 12:14:27.681239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 12:14:27.681340 ==
5922 12:14:27.684571 RX Vref Scan: 0
5923 12:14:27.684644
5924 12:14:27.684706 RX Vref 0 -> 0, step: 1
5925 12:14:27.684803
5926 12:14:27.687869 RX Delay -61 -> 252, step: 4
5927 12:14:27.695240 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5928 12:14:27.698468 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5929 12:14:27.701629 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5930 12:14:27.704930 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5931 12:14:27.708766 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5932 12:14:27.711991 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5933 12:14:27.718522 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5934 12:14:27.721886 iDelay=195, Bit 7, Center 92 (7 ~ 178) 172
5935 12:14:27.725076 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5936 12:14:27.728465 iDelay=195, Bit 9, Center 82 (-5 ~ 170) 176
5937 12:14:27.731776 iDelay=195, Bit 10, Center 94 (3 ~ 186) 184
5938 12:14:27.738437 iDelay=195, Bit 11, Center 86 (-1 ~ 174) 176
5939 12:14:27.741667 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5940 12:14:27.744972 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5941 12:14:27.748133 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5942 12:14:27.751415 iDelay=195, Bit 15, Center 100 (11 ~ 190) 180
5943 12:14:27.751530 ==
5944 12:14:27.754679 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 12:14:27.761327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 12:14:27.761455 ==
5947 12:14:27.761549 DQS Delay:
5948 12:14:27.764681 DQS0 = 0, DQS1 = 0
5949 12:14:27.764798 DQM Delay:
5950 12:14:27.764889 DQM0 = 95, DQM1 = 91
5951 12:14:27.768083 DQ Delay:
5952 12:14:27.771385 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5953 12:14:27.774592 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
5954 12:14:27.777903 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =86
5955 12:14:27.781113 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =100
5956 12:14:27.781224
5957 12:14:27.781318
5958 12:14:27.787719 [DQSOSCAuto] RK1, (LSB)MR18= 0x913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 419 ps
5959 12:14:27.791706 CH1 RK1: MR19=505, MR18=913
5960 12:14:27.798210 CH1_RK1: MR19=0x505, MR18=0x913, DQSOSC=415, MR23=63, INC=62, DEC=41
5961 12:14:27.801426 [RxdqsGatingPostProcess] freq 933
5962 12:14:27.804502 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 12:14:27.807756 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 12:14:27.811083 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 12:14:27.814218 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 12:14:27.817627 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 12:14:27.821009 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 12:14:27.824147 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 12:14:27.827373 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 12:14:27.830700 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 12:14:27.833990 Pre-setting of DQS Precalculation
5972 12:14:27.837864 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 12:14:27.847749 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 12:14:27.854245 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 12:14:27.854331
5976 12:14:27.854397
5977 12:14:27.857389 [Calibration Summary] 1866 Mbps
5978 12:14:27.857474 CH 0, Rank 0
5979 12:14:27.860562 SW Impedance : PASS
5980 12:14:27.860647 DUTY Scan : NO K
5981 12:14:27.864510 ZQ Calibration : PASS
5982 12:14:27.867866 Jitter Meter : NO K
5983 12:14:27.867951 CBT Training : PASS
5984 12:14:27.871132 Write leveling : PASS
5985 12:14:27.874481 RX DQS gating : PASS
5986 12:14:27.874565 RX DQ/DQS(RDDQC) : PASS
5987 12:14:27.877838 TX DQ/DQS : PASS
5988 12:14:27.881105 RX DATLAT : PASS
5989 12:14:27.881190 RX DQ/DQS(Engine): PASS
5990 12:14:27.883760 TX OE : NO K
5991 12:14:27.883845 All Pass.
5992 12:14:27.883912
5993 12:14:27.887085 CH 0, Rank 1
5994 12:14:27.887169 SW Impedance : PASS
5995 12:14:27.890455 DUTY Scan : NO K
5996 12:14:27.893767 ZQ Calibration : PASS
5997 12:14:27.893851 Jitter Meter : NO K
5998 12:14:27.897026 CBT Training : PASS
5999 12:14:27.897110 Write leveling : PASS
6000 12:14:27.900400 RX DQS gating : PASS
6001 12:14:27.904267 RX DQ/DQS(RDDQC) : PASS
6002 12:14:27.904349 TX DQ/DQS : PASS
6003 12:14:27.907250 RX DATLAT : PASS
6004 12:14:27.910463 RX DQ/DQS(Engine): PASS
6005 12:14:27.910546 TX OE : NO K
6006 12:14:27.914331 All Pass.
6007 12:14:27.914414
6008 12:14:27.914556 CH 1, Rank 0
6009 12:14:27.917538 SW Impedance : PASS
6010 12:14:27.917620 DUTY Scan : NO K
6011 12:14:27.920878 ZQ Calibration : PASS
6012 12:14:27.924092 Jitter Meter : NO K
6013 12:14:27.924174 CBT Training : PASS
6014 12:14:27.927358 Write leveling : PASS
6015 12:14:27.930554 RX DQS gating : PASS
6016 12:14:27.930629 RX DQ/DQS(RDDQC) : PASS
6017 12:14:27.933943 TX DQ/DQS : PASS
6018 12:14:27.937250 RX DATLAT : PASS
6019 12:14:27.937349 RX DQ/DQS(Engine): PASS
6020 12:14:27.940625 TX OE : NO K
6021 12:14:27.940724 All Pass.
6022 12:14:27.940822
6023 12:14:27.943860 CH 1, Rank 1
6024 12:14:27.943946 SW Impedance : PASS
6025 12:14:27.947270 DUTY Scan : NO K
6026 12:14:27.950629 ZQ Calibration : PASS
6027 12:14:27.950733 Jitter Meter : NO K
6028 12:14:27.953271 CBT Training : PASS
6029 12:14:27.956560 Write leveling : PASS
6030 12:14:27.956636 RX DQS gating : PASS
6031 12:14:27.960255 RX DQ/DQS(RDDQC) : PASS
6032 12:14:27.960378 TX DQ/DQS : PASS
6033 12:14:27.963613 RX DATLAT : PASS
6034 12:14:27.966705 RX DQ/DQS(Engine): PASS
6035 12:14:27.966787 TX OE : NO K
6036 12:14:27.970089 All Pass.
6037 12:14:27.970198
6038 12:14:27.970265 DramC Write-DBI off
6039 12:14:27.973418 PER_BANK_REFRESH: Hybrid Mode
6040 12:14:27.976734 TX_TRACKING: ON
6041 12:14:27.983361 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 12:14:27.986663 [FAST_K] Save calibration result to emmc
6043 12:14:27.989979 dramc_set_vcore_voltage set vcore to 650000
6044 12:14:27.993322 Read voltage for 400, 6
6045 12:14:27.993401 Vio18 = 0
6046 12:14:27.996524 Vcore = 650000
6047 12:14:27.996627 Vdram = 0
6048 12:14:27.996696 Vddq = 0
6049 12:14:27.999914 Vmddr = 0
6050 12:14:28.003188 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 12:14:28.009724 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 12:14:28.009809 MEM_TYPE=3, freq_sel=20
6053 12:14:28.012971 sv_algorithm_assistance_LP4_800
6054 12:14:28.019501 ============ PULL DRAM RESETB DOWN ============
6055 12:14:28.023342 ========== PULL DRAM RESETB DOWN end =========
6056 12:14:28.026516 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 12:14:28.029817 ===================================
6058 12:14:28.033059 LPDDR4 DRAM CONFIGURATION
6059 12:14:28.036414 ===================================
6060 12:14:28.039713 EX_ROW_EN[0] = 0x0
6061 12:14:28.039790 EX_ROW_EN[1] = 0x0
6062 12:14:28.043009 LP4Y_EN = 0x0
6063 12:14:28.043084 WORK_FSP = 0x0
6064 12:14:28.046237 WL = 0x2
6065 12:14:28.046311 RL = 0x2
6066 12:14:28.049567 BL = 0x2
6067 12:14:28.049641 RPST = 0x0
6068 12:14:28.052805 RD_PRE = 0x0
6069 12:14:28.052904 WR_PRE = 0x1
6070 12:14:28.056146 WR_PST = 0x0
6071 12:14:28.056238 DBI_WR = 0x0
6072 12:14:28.059466 DBI_RD = 0x0
6073 12:14:28.059549 OTF = 0x1
6074 12:14:28.062717 ===================================
6075 12:14:28.066505 ===================================
6076 12:14:28.069672 ANA top config
6077 12:14:28.072955 ===================================
6078 12:14:28.076198 DLL_ASYNC_EN = 0
6079 12:14:28.076290 ALL_SLAVE_EN = 1
6080 12:14:28.079544 NEW_RANK_MODE = 1
6081 12:14:28.082843 DLL_IDLE_MODE = 1
6082 12:14:28.086014 LP45_APHY_COMB_EN = 1
6083 12:14:28.086127 TX_ODT_DIS = 1
6084 12:14:28.089314 NEW_8X_MODE = 1
6085 12:14:28.092651 ===================================
6086 12:14:28.095979 ===================================
6087 12:14:28.099345 data_rate = 800
6088 12:14:28.102646 CKR = 1
6089 12:14:28.105924 DQ_P2S_RATIO = 4
6090 12:14:28.109735 ===================================
6091 12:14:28.113033 CA_P2S_RATIO = 4
6092 12:14:28.113114 DQ_CA_OPEN = 0
6093 12:14:28.115728 DQ_SEMI_OPEN = 1
6094 12:14:28.119601 CA_SEMI_OPEN = 1
6095 12:14:28.122309 CA_FULL_RATE = 0
6096 12:14:28.126108 DQ_CKDIV4_EN = 0
6097 12:14:28.129350 CA_CKDIV4_EN = 1
6098 12:14:28.129438 CA_PREDIV_EN = 0
6099 12:14:28.132581 PH8_DLY = 0
6100 12:14:28.135641 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 12:14:28.138985 DQ_AAMCK_DIV = 0
6102 12:14:28.142393 CA_AAMCK_DIV = 0
6103 12:14:28.145593 CA_ADMCK_DIV = 4
6104 12:14:28.145676 DQ_TRACK_CA_EN = 0
6105 12:14:28.148861 CA_PICK = 800
6106 12:14:28.152163 CA_MCKIO = 400
6107 12:14:28.155439 MCKIO_SEMI = 400
6108 12:14:28.158713 PLL_FREQ = 3016
6109 12:14:28.162033 DQ_UI_PI_RATIO = 32
6110 12:14:28.165891 CA_UI_PI_RATIO = 32
6111 12:14:28.169210 ===================================
6112 12:14:28.172455 ===================================
6113 12:14:28.172544 memory_type:LPDDR4
6114 12:14:28.175622 GP_NUM : 10
6115 12:14:28.178887 SRAM_EN : 1
6116 12:14:28.178963 MD32_EN : 0
6117 12:14:28.182198 ===================================
6118 12:14:28.185543 [ANA_INIT] >>>>>>>>>>>>>>
6119 12:14:28.188900 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 12:14:28.192083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 12:14:28.195414 ===================================
6122 12:14:28.198797 data_rate = 800,PCW = 0X7400
6123 12:14:28.202108 ===================================
6124 12:14:28.205416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 12:14:28.208678 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 12:14:28.221780 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 12:14:28.224938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 12:14:28.228931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 12:14:28.231493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 12:14:28.235322 [ANA_INIT] flow start
6131 12:14:28.238542 [ANA_INIT] PLL >>>>>>>>
6132 12:14:28.238636 [ANA_INIT] PLL <<<<<<<<
6133 12:14:28.241812 [ANA_INIT] MIDPI >>>>>>>>
6134 12:14:28.245074 [ANA_INIT] MIDPI <<<<<<<<
6135 12:14:28.245158 [ANA_INIT] DLL >>>>>>>>
6136 12:14:28.248385 [ANA_INIT] flow end
6137 12:14:28.251673 ============ LP4 DIFF to SE enter ============
6138 12:14:28.255021 ============ LP4 DIFF to SE exit ============
6139 12:14:28.258234 [ANA_INIT] <<<<<<<<<<<<<
6140 12:14:28.261578 [Flow] Enable top DCM control >>>>>
6141 12:14:28.264925 [Flow] Enable top DCM control <<<<<
6142 12:14:28.268031 Enable DLL master slave shuffle
6143 12:14:28.275093 ==============================================================
6144 12:14:28.275179 Gating Mode config
6145 12:14:28.281574 ==============================================================
6146 12:14:28.281660 Config description:
6147 12:14:28.291623 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 12:14:28.298120 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 12:14:28.305361 SELPH_MODE 0: By rank 1: By Phase
6150 12:14:28.308622 ==============================================================
6151 12:14:28.311918 GAT_TRACK_EN = 0
6152 12:14:28.315185 RX_GATING_MODE = 2
6153 12:14:28.318497 RX_GATING_TRACK_MODE = 2
6154 12:14:28.321858 SELPH_MODE = 1
6155 12:14:28.325076 PICG_EARLY_EN = 1
6156 12:14:28.328453 VALID_LAT_VALUE = 1
6157 12:14:28.334854 ==============================================================
6158 12:14:28.338090 Enter into Gating configuration >>>>
6159 12:14:28.341225 Exit from Gating configuration <<<<
6160 12:14:28.341308 Enter into DVFS_PRE_config >>>>>
6161 12:14:28.355011 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 12:14:28.358456 Exit from DVFS_PRE_config <<<<<
6163 12:14:28.361656 Enter into PICG configuration >>>>
6164 12:14:28.364956 Exit from PICG configuration <<<<
6165 12:14:28.365061 [RX_INPUT] configuration >>>>>
6166 12:14:28.368166 [RX_INPUT] configuration <<<<<
6167 12:14:28.374692 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 12:14:28.377941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 12:14:28.384915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 12:14:28.391486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 12:14:28.398122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 12:14:28.404528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 12:14:28.407855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 12:14:28.411177 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 12:14:28.417897 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 12:14:28.421327 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 12:14:28.424576 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 12:14:28.427885 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 12:14:28.431275 ===================================
6180 12:14:28.434594 LPDDR4 DRAM CONFIGURATION
6181 12:14:28.437761 ===================================
6182 12:14:28.441040 EX_ROW_EN[0] = 0x0
6183 12:14:28.441184 EX_ROW_EN[1] = 0x0
6184 12:14:28.444394 LP4Y_EN = 0x0
6185 12:14:28.444499 WORK_FSP = 0x0
6186 12:14:28.447883 WL = 0x2
6187 12:14:28.448004 RL = 0x2
6188 12:14:28.451536 BL = 0x2
6189 12:14:28.451644 RPST = 0x0
6190 12:14:28.454139 RD_PRE = 0x0
6191 12:14:28.457463 WR_PRE = 0x1
6192 12:14:28.457546 WR_PST = 0x0
6193 12:14:28.460747 DBI_WR = 0x0
6194 12:14:28.460844 DBI_RD = 0x0
6195 12:14:28.464159 OTF = 0x1
6196 12:14:28.467470 ===================================
6197 12:14:28.470762 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 12:14:28.473977 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 12:14:28.477340 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 12:14:28.480366 ===================================
6201 12:14:28.483633 LPDDR4 DRAM CONFIGURATION
6202 12:14:28.486957 ===================================
6203 12:14:28.490200 EX_ROW_EN[0] = 0x10
6204 12:14:28.490320 EX_ROW_EN[1] = 0x0
6205 12:14:28.494088 LP4Y_EN = 0x0
6206 12:14:28.494198 WORK_FSP = 0x0
6207 12:14:28.497386 WL = 0x2
6208 12:14:28.497493 RL = 0x2
6209 12:14:28.500731 BL = 0x2
6210 12:14:28.500841 RPST = 0x0
6211 12:14:28.504019 RD_PRE = 0x0
6212 12:14:28.504122 WR_PRE = 0x1
6213 12:14:28.507456 WR_PST = 0x0
6214 12:14:28.510788 DBI_WR = 0x0
6215 12:14:28.510896 DBI_RD = 0x0
6216 12:14:28.514085 OTF = 0x1
6217 12:14:28.517464 ===================================
6218 12:14:28.520673 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 12:14:28.526004 nWR fixed to 30
6220 12:14:28.529182 [ModeRegInit_LP4] CH0 RK0
6221 12:14:28.529290 [ModeRegInit_LP4] CH0 RK1
6222 12:14:28.532614 [ModeRegInit_LP4] CH1 RK0
6223 12:14:28.535253 [ModeRegInit_LP4] CH1 RK1
6224 12:14:28.535382 match AC timing 19
6225 12:14:28.542455 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 12:14:28.545582 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 12:14:28.548919 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 12:14:28.555409 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 12:14:28.558714 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 12:14:28.558817 ==
6231 12:14:28.562007 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 12:14:28.565241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 12:14:28.565342 ==
6234 12:14:28.571876 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 12:14:28.578361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6236 12:14:28.581641 [CA 0] Center 36 (8~64) winsize 57
6237 12:14:28.584856 [CA 1] Center 36 (8~64) winsize 57
6238 12:14:28.588215 [CA 2] Center 36 (8~64) winsize 57
6239 12:14:28.591578 [CA 3] Center 36 (8~64) winsize 57
6240 12:14:28.594818 [CA 4] Center 36 (8~64) winsize 57
6241 12:14:28.594892 [CA 5] Center 36 (8~64) winsize 57
6242 12:14:28.598678
6243 12:14:28.601951 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6244 12:14:28.602034
6245 12:14:28.604616 [CATrainingPosCal] consider 1 rank data
6246 12:14:28.607881 u2DelayCellTimex100 = 270/100 ps
6247 12:14:28.611234 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:14:28.614585 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:14:28.618531 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:14:28.621674 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:14:28.624955 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:14:28.628122 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:14:28.628205
6254 12:14:28.631431 CA PerBit enable=1, Macro0, CA PI delay=36
6255 12:14:28.631530
6256 12:14:28.634703 [CBTSetCACLKResult] CA Dly = 36
6257 12:14:28.637935 CS Dly: 1 (0~32)
6258 12:14:28.638070 ==
6259 12:14:28.641254 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 12:14:28.644592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 12:14:28.644690 ==
6262 12:14:28.651484 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 12:14:28.657794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6264 12:14:28.661085 [CA 0] Center 36 (8~64) winsize 57
6265 12:14:28.661185 [CA 1] Center 36 (8~64) winsize 57
6266 12:14:28.664982 [CA 2] Center 36 (8~64) winsize 57
6267 12:14:28.668278 [CA 3] Center 36 (8~64) winsize 57
6268 12:14:28.671562 [CA 4] Center 36 (8~64) winsize 57
6269 12:14:28.674856 [CA 5] Center 36 (8~64) winsize 57
6270 12:14:28.674962
6271 12:14:28.678013 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6272 12:14:28.678098
6273 12:14:28.681402 [CATrainingPosCal] consider 2 rank data
6274 12:14:28.684580 u2DelayCellTimex100 = 270/100 ps
6275 12:14:28.687954 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 12:14:28.694534 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:14:28.697752 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:14:28.701054 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:14:28.704193 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:14:28.708088 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:14:28.708191
6282 12:14:28.711500 CA PerBit enable=1, Macro0, CA PI delay=36
6283 12:14:28.711585
6284 12:14:28.714232 [CBTSetCACLKResult] CA Dly = 36
6285 12:14:28.714316 CS Dly: 1 (0~32)
6286 12:14:28.717639
6287 12:14:28.720905 ----->DramcWriteLeveling(PI) begin...
6288 12:14:28.721036 ==
6289 12:14:28.724716 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 12:14:28.727955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 12:14:28.728054 ==
6292 12:14:28.731230 Write leveling (Byte 0): 40 => 8
6293 12:14:28.734561 Write leveling (Byte 1): 32 => 0
6294 12:14:28.737318 DramcWriteLeveling(PI) end<-----
6295 12:14:28.737452
6296 12:14:28.737576 ==
6297 12:14:28.740619 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 12:14:28.744071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 12:14:28.744167 ==
6300 12:14:28.747247 [Gating] SW mode calibration
6301 12:14:28.754518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 12:14:28.761063 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 12:14:28.764076 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 12:14:28.767287 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 12:14:28.773894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 12:14:28.777726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 12:14:28.780919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 12:14:28.787341 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 12:14:28.790571 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 12:14:28.793914 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 12:14:28.800375 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 12:14:28.800459 Total UI for P1: 0, mck2ui 16
6313 12:14:28.804221 best dqsien dly found for B0: ( 0, 14, 24)
6314 12:14:28.807451 Total UI for P1: 0, mck2ui 16
6315 12:14:28.810562 best dqsien dly found for B1: ( 0, 14, 24)
6316 12:14:28.813829 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 12:14:28.820361 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 12:14:28.820466
6319 12:14:28.824162 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 12:14:28.827393 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 12:14:28.830657 [Gating] SW calibration Done
6322 12:14:28.830742 ==
6323 12:14:28.834027 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 12:14:28.837343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 12:14:28.837445 ==
6326 12:14:28.840603 RX Vref Scan: 0
6327 12:14:28.840703
6328 12:14:28.840809 RX Vref 0 -> 0, step: 1
6329 12:14:28.840902
6330 12:14:28.844013 RX Delay -410 -> 252, step: 16
6331 12:14:28.847358 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6332 12:14:28.853902 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6333 12:14:28.856971 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6334 12:14:28.860195 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6335 12:14:28.863408 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6336 12:14:28.870534 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6337 12:14:28.873753 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6338 12:14:28.876964 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6339 12:14:28.880213 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6340 12:14:28.886818 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6341 12:14:28.890034 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6342 12:14:28.893294 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6343 12:14:28.899812 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6344 12:14:28.903054 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6345 12:14:28.906386 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6346 12:14:28.909710 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6347 12:14:28.909821 ==
6348 12:14:28.913461 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 12:14:28.920013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 12:14:28.920126 ==
6351 12:14:28.920231 DQS Delay:
6352 12:14:28.923205 DQS0 = 43, DQS1 = 51
6353 12:14:28.923315 DQM Delay:
6354 12:14:28.926429 DQM0 = 14, DQM1 = 10
6355 12:14:28.926540 DQ Delay:
6356 12:14:28.929747 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6357 12:14:28.933053 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6358 12:14:28.936463 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6359 12:14:28.939720 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6360 12:14:28.939826
6361 12:14:28.939921
6362 12:14:28.940020 ==
6363 12:14:28.943020 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 12:14:28.946239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 12:14:28.946352 ==
6366 12:14:28.946448
6367 12:14:28.946537
6368 12:14:28.949543 TX Vref Scan disable
6369 12:14:28.949647 == TX Byte 0 ==
6370 12:14:28.956262 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 12:14:28.959412 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 12:14:28.959517 == TX Byte 1 ==
6373 12:14:28.966415 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6374 12:14:28.969704 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6375 12:14:28.969816 ==
6376 12:14:28.972911 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 12:14:28.976079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 12:14:28.976184 ==
6379 12:14:28.976282
6380 12:14:28.976372
6381 12:14:28.979415 TX Vref Scan disable
6382 12:14:28.979542 == TX Byte 0 ==
6383 12:14:28.986014 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 12:14:28.989909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 12:14:28.990025 == TX Byte 1 ==
6386 12:14:28.996445 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6387 12:14:28.999814 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6388 12:14:28.999898
6389 12:14:28.999964 [DATLAT]
6390 12:14:29.003137 Freq=400, CH0 RK0
6391 12:14:29.003221
6392 12:14:29.003287 DATLAT Default: 0xf
6393 12:14:29.006389 0, 0xFFFF, sum = 0
6394 12:14:29.006474 1, 0xFFFF, sum = 0
6395 12:14:29.009829 2, 0xFFFF, sum = 0
6396 12:14:29.009945 3, 0xFFFF, sum = 0
6397 12:14:29.013078 4, 0xFFFF, sum = 0
6398 12:14:29.013162 5, 0xFFFF, sum = 0
6399 12:14:29.016234 6, 0xFFFF, sum = 0
6400 12:14:29.016318 7, 0xFFFF, sum = 0
6401 12:14:29.019432 8, 0xFFFF, sum = 0
6402 12:14:29.022705 9, 0xFFFF, sum = 0
6403 12:14:29.022790 10, 0xFFFF, sum = 0
6404 12:14:29.025961 11, 0xFFFF, sum = 0
6405 12:14:29.026046 12, 0xFFFF, sum = 0
6406 12:14:29.029193 13, 0x0, sum = 1
6407 12:14:29.029268 14, 0x0, sum = 2
6408 12:14:29.032588 15, 0x0, sum = 3
6409 12:14:29.032670 16, 0x0, sum = 4
6410 12:14:29.032738 best_step = 14
6411 12:14:29.032798
6412 12:14:29.035965 ==
6413 12:14:29.039443 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 12:14:29.042762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 12:14:29.042837 ==
6416 12:14:29.042900 RX Vref Scan: 1
6417 12:14:29.042960
6418 12:14:29.045988 RX Vref 0 -> 0, step: 1
6419 12:14:29.046061
6420 12:14:29.049220 RX Delay -343 -> 252, step: 8
6421 12:14:29.049294
6422 12:14:29.052620 Set Vref, RX VrefLevel [Byte0]: 55
6423 12:14:29.055964 [Byte1]: 50
6424 12:14:29.059982
6425 12:14:29.060084 Final RX Vref Byte 0 = 55 to rank0
6426 12:14:29.063242 Final RX Vref Byte 1 = 50 to rank0
6427 12:14:29.066435 Final RX Vref Byte 0 = 55 to rank1
6428 12:14:29.069649 Final RX Vref Byte 1 = 50 to rank1==
6429 12:14:29.072851 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 12:14:29.079843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 12:14:29.079920 ==
6432 12:14:29.079984 DQS Delay:
6433 12:14:29.083051 DQS0 = 44, DQS1 = 60
6434 12:14:29.083147 DQM Delay:
6435 12:14:29.083237 DQM0 = 11, DQM1 = 15
6436 12:14:29.086342 DQ Delay:
6437 12:14:29.089608 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6438 12:14:29.089717 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6439 12:14:29.092812 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6440 12:14:29.096036 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6441 12:14:29.099415
6442 12:14:29.099487
6443 12:14:29.106530 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a58, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6444 12:14:29.109852 CH0 RK0: MR19=C0C, MR18=8A58
6445 12:14:29.116459 CH0_RK0: MR19=0xC0C, MR18=0x8A58, DQSOSC=392, MR23=63, INC=384, DEC=256
6446 12:14:29.116540 ==
6447 12:14:29.119572 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 12:14:29.122739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 12:14:29.122841 ==
6450 12:14:29.126075 [Gating] SW mode calibration
6451 12:14:29.132476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 12:14:29.139019 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 12:14:29.142424 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 12:14:29.145742 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 12:14:29.152416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 12:14:29.155653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 12:14:29.158973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 12:14:29.166188 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 12:14:29.169440 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 12:14:29.172663 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 12:14:29.175850 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 12:14:29.179160 Total UI for P1: 0, mck2ui 16
6463 12:14:29.182359 best dqsien dly found for B0: ( 0, 14, 24)
6464 12:14:29.185503 Total UI for P1: 0, mck2ui 16
6465 12:14:29.189440 best dqsien dly found for B1: ( 0, 14, 24)
6466 12:14:29.192632 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 12:14:29.199220 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 12:14:29.199326
6469 12:14:29.202611 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 12:14:29.205964 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 12:14:29.209175 [Gating] SW calibration Done
6472 12:14:29.209286 ==
6473 12:14:29.212480 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 12:14:29.215758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 12:14:29.215883 ==
6476 12:14:29.219111 RX Vref Scan: 0
6477 12:14:29.219271
6478 12:14:29.219384 RX Vref 0 -> 0, step: 1
6479 12:14:29.219466
6480 12:14:29.222344 RX Delay -410 -> 252, step: 16
6481 12:14:29.225499 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6482 12:14:29.232046 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6483 12:14:29.235879 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6484 12:14:29.239117 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6485 12:14:29.242414 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6486 12:14:29.249078 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6487 12:14:29.252413 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6488 12:14:29.255691 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6489 12:14:29.258940 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6490 12:14:29.265573 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6491 12:14:29.268866 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6492 12:14:29.272000 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6493 12:14:29.275264 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6494 12:14:29.282356 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6495 12:14:29.285612 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6496 12:14:29.288851 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6497 12:14:29.288981 ==
6498 12:14:29.292081 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 12:14:29.298378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 12:14:29.298465 ==
6501 12:14:29.298534 DQS Delay:
6502 12:14:29.301728 DQS0 = 35, DQS1 = 51
6503 12:14:29.301833 DQM Delay:
6504 12:14:29.301929 DQM0 = 4, DQM1 = 10
6505 12:14:29.305072 DQ Delay:
6506 12:14:29.308401 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6507 12:14:29.308506 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6508 12:14:29.311601 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6509 12:14:29.314782 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6510 12:14:29.314890
6511 12:14:29.318806
6512 12:14:29.318909 ==
6513 12:14:29.322046 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 12:14:29.325301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 12:14:29.325405 ==
6516 12:14:29.325505
6517 12:14:29.325599
6518 12:14:29.328554 TX Vref Scan disable
6519 12:14:29.328661 == TX Byte 0 ==
6520 12:14:29.331881 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6521 12:14:29.338205 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6522 12:14:29.338319 == TX Byte 1 ==
6523 12:14:29.341924 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6524 12:14:29.348624 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6525 12:14:29.348707 ==
6526 12:14:29.351979 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 12:14:29.354685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 12:14:29.354789 ==
6529 12:14:29.354883
6530 12:14:29.354974
6531 12:14:29.358572 TX Vref Scan disable
6532 12:14:29.358672 == TX Byte 0 ==
6533 12:14:29.361794 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6534 12:14:29.368307 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6535 12:14:29.368398 == TX Byte 1 ==
6536 12:14:29.371699 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6537 12:14:29.378208 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6538 12:14:29.378318
6539 12:14:29.378413 [DATLAT]
6540 12:14:29.378501 Freq=400, CH0 RK1
6541 12:14:29.378589
6542 12:14:29.381472 DATLAT Default: 0xe
6543 12:14:29.384640 0, 0xFFFF, sum = 0
6544 12:14:29.384746 1, 0xFFFF, sum = 0
6545 12:14:29.387828 2, 0xFFFF, sum = 0
6546 12:14:29.387933 3, 0xFFFF, sum = 0
6547 12:14:29.391107 4, 0xFFFF, sum = 0
6548 12:14:29.391210 5, 0xFFFF, sum = 0
6549 12:14:29.394342 6, 0xFFFF, sum = 0
6550 12:14:29.394446 7, 0xFFFF, sum = 0
6551 12:14:29.398248 8, 0xFFFF, sum = 0
6552 12:14:29.398350 9, 0xFFFF, sum = 0
6553 12:14:29.401483 10, 0xFFFF, sum = 0
6554 12:14:29.401589 11, 0xFFFF, sum = 0
6555 12:14:29.404761 12, 0xFFFF, sum = 0
6556 12:14:29.404868 13, 0x0, sum = 1
6557 12:14:29.408058 14, 0x0, sum = 2
6558 12:14:29.408165 15, 0x0, sum = 3
6559 12:14:29.411389 16, 0x0, sum = 4
6560 12:14:29.411500 best_step = 14
6561 12:14:29.411594
6562 12:14:29.411692 ==
6563 12:14:29.414760 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 12:14:29.421361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 12:14:29.421468 ==
6566 12:14:29.421565 RX Vref Scan: 0
6567 12:14:29.421661
6568 12:14:29.424604 RX Vref 0 -> 0, step: 1
6569 12:14:29.424705
6570 12:14:29.427921 RX Delay -343 -> 252, step: 8
6571 12:14:29.434688 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6572 12:14:29.438016 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6573 12:14:29.441212 iDelay=217, Bit 2, Center -36 (-279 ~ 208) 488
6574 12:14:29.444527 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6575 12:14:29.451050 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6576 12:14:29.454200 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6577 12:14:29.457515 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6578 12:14:29.460837 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6579 12:14:29.467322 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6580 12:14:29.470606 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6581 12:14:29.474555 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6582 12:14:29.477698 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6583 12:14:29.484381 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6584 12:14:29.487612 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6585 12:14:29.490655 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6586 12:14:29.494382 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6587 12:14:29.497653 ==
6588 12:14:29.500988 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 12:14:29.504128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 12:14:29.504232 ==
6591 12:14:29.504327 DQS Delay:
6592 12:14:29.507457 DQS0 = 48, DQS1 = 56
6593 12:14:29.507569 DQM Delay:
6594 12:14:29.510741 DQM0 = 13, DQM1 = 10
6595 12:14:29.510856 DQ Delay:
6596 12:14:29.514064 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =12
6597 12:14:29.517441 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6598 12:14:29.520756 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6599 12:14:29.524048 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6600 12:14:29.524154
6601 12:14:29.524251
6602 12:14:29.530734 [DQSOSCAuto] RK1, (LSB)MR18= 0x9264, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6603 12:14:29.533969 CH0 RK1: MR19=C0C, MR18=9264
6604 12:14:29.540414 CH0_RK1: MR19=0xC0C, MR18=0x9264, DQSOSC=391, MR23=63, INC=386, DEC=257
6605 12:14:29.544177 [RxdqsGatingPostProcess] freq 400
6606 12:14:29.547333 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 12:14:29.550604 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 12:14:29.553861 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 12:14:29.557128 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 12:14:29.560507 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 12:14:29.563840 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 12:14:29.567096 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 12:14:29.570411 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 12:14:29.573763 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 12:14:29.577004 Pre-setting of DQS Precalculation
6616 12:14:29.580329 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 12:14:29.584081 ==
6618 12:14:29.587442 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 12:14:29.590633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 12:14:29.590736 ==
6621 12:14:29.593793 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 12:14:29.600880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 12:14:29.603620 [CA 0] Center 36 (8~64) winsize 57
6624 12:14:29.606824 [CA 1] Center 36 (8~64) winsize 57
6625 12:14:29.610576 [CA 2] Center 36 (8~64) winsize 57
6626 12:14:29.613633 [CA 3] Center 36 (8~64) winsize 57
6627 12:14:29.616997 [CA 4] Center 36 (8~64) winsize 57
6628 12:14:29.620092 [CA 5] Center 36 (8~64) winsize 57
6629 12:14:29.620196
6630 12:14:29.623410 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 12:14:29.623515
6632 12:14:29.627448 [CATrainingPosCal] consider 1 rank data
6633 12:14:29.630761 u2DelayCellTimex100 = 270/100 ps
6634 12:14:29.633443 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:14:29.636799 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:14:29.640710 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:14:29.643407 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:14:29.647179 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:14:29.653504 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:14:29.653612
6641 12:14:29.656840 CA PerBit enable=1, Macro0, CA PI delay=36
6642 12:14:29.656940
6643 12:14:29.660162 [CBTSetCACLKResult] CA Dly = 36
6644 12:14:29.660236 CS Dly: 1 (0~32)
6645 12:14:29.660303 ==
6646 12:14:29.663596 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 12:14:29.666860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 12:14:29.670130 ==
6649 12:14:29.673383 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 12:14:29.679938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6651 12:14:29.683141 [CA 0] Center 36 (8~64) winsize 57
6652 12:14:29.686583 [CA 1] Center 36 (8~64) winsize 57
6653 12:14:29.689872 [CA 2] Center 36 (8~64) winsize 57
6654 12:14:29.693163 [CA 3] Center 36 (8~64) winsize 57
6655 12:14:29.696469 [CA 4] Center 36 (8~64) winsize 57
6656 12:14:29.699753 [CA 5] Center 36 (8~64) winsize 57
6657 12:14:29.699875
6658 12:14:29.702814 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6659 12:14:29.702933
6660 12:14:29.706692 [CATrainingPosCal] consider 2 rank data
6661 12:14:29.709987 u2DelayCellTimex100 = 270/100 ps
6662 12:14:29.713113 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 12:14:29.716451 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:14:29.719583 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:14:29.722848 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:14:29.726626 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:14:29.729937 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:14:29.730057
6669 12:14:29.736590 CA PerBit enable=1, Macro0, CA PI delay=36
6670 12:14:29.736674
6671 12:14:29.736742 [CBTSetCACLKResult] CA Dly = 36
6672 12:14:29.739977 CS Dly: 1 (0~32)
6673 12:14:29.740054
6674 12:14:29.743222 ----->DramcWriteLeveling(PI) begin...
6675 12:14:29.743307 ==
6676 12:14:29.745899 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 12:14:29.749739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 12:14:29.749824 ==
6679 12:14:29.752813 Write leveling (Byte 0): 40 => 8
6680 12:14:29.756156 Write leveling (Byte 1): 40 => 8
6681 12:14:29.759429 DramcWriteLeveling(PI) end<-----
6682 12:14:29.759513
6683 12:14:29.759578 ==
6684 12:14:29.762699 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 12:14:29.765947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 12:14:29.769150 ==
6687 12:14:29.769235 [Gating] SW mode calibration
6688 12:14:29.779011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 12:14:29.782346 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 12:14:29.786276 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 12:14:29.792286 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 12:14:29.796180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 12:14:29.799636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 12:14:29.806047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 12:14:29.809223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 12:14:29.812362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 12:14:29.819358 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 12:14:29.822472 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 12:14:29.825545 Total UI for P1: 0, mck2ui 16
6700 12:14:29.829403 best dqsien dly found for B0: ( 0, 14, 24)
6701 12:14:29.832633 Total UI for P1: 0, mck2ui 16
6702 12:14:29.835959 best dqsien dly found for B1: ( 0, 14, 24)
6703 12:14:29.839188 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 12:14:29.842384 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 12:14:29.842467
6706 12:14:29.845667 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 12:14:29.849056 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 12:14:29.852396 [Gating] SW calibration Done
6709 12:14:29.852479 ==
6710 12:14:29.855595 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 12:14:29.858896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 12:14:29.862131 ==
6713 12:14:29.862215 RX Vref Scan: 0
6714 12:14:29.862282
6715 12:14:29.865597 RX Vref 0 -> 0, step: 1
6716 12:14:29.865681
6717 12:14:29.868774 RX Delay -410 -> 252, step: 16
6718 12:14:29.872078 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6719 12:14:29.875406 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6720 12:14:29.878649 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6721 12:14:29.885329 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6722 12:14:29.888622 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6723 12:14:29.891962 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6724 12:14:29.895815 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6725 12:14:29.901859 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6726 12:14:29.905777 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6727 12:14:29.909098 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6728 12:14:29.912219 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6729 12:14:29.918611 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6730 12:14:29.921931 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6731 12:14:29.925138 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6732 12:14:29.931882 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6733 12:14:29.935159 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6734 12:14:29.935264 ==
6735 12:14:29.938401 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 12:14:29.941709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 12:14:29.941793 ==
6738 12:14:29.945652 DQS Delay:
6739 12:14:29.945750 DQS0 = 51, DQS1 = 59
6740 12:14:29.945816 DQM Delay:
6741 12:14:29.948909 DQM0 = 19, DQM1 = 15
6742 12:14:29.948991 DQ Delay:
6743 12:14:29.952293 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6744 12:14:29.955546 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6745 12:14:29.958904 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6746 12:14:29.962091 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6747 12:14:29.962174
6748 12:14:29.962240
6749 12:14:29.962300 ==
6750 12:14:29.965302 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 12:14:29.968550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 12:14:29.972005 ==
6753 12:14:29.972081
6754 12:14:29.972145
6755 12:14:29.972214 TX Vref Scan disable
6756 12:14:29.975212 == TX Byte 0 ==
6757 12:14:29.978588 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 12:14:29.981885 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 12:14:29.985266 == TX Byte 1 ==
6760 12:14:29.988578 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 12:14:29.991980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 12:14:29.992063 ==
6763 12:14:29.995314 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 12:14:30.001850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 12:14:30.001950 ==
6766 12:14:30.002049
6767 12:14:30.002142
6768 12:14:30.002214 TX Vref Scan disable
6769 12:14:30.005102 == TX Byte 0 ==
6770 12:14:30.008517 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 12:14:30.011808 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 12:14:30.015023 == TX Byte 1 ==
6773 12:14:30.018244 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 12:14:30.021574 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 12:14:30.021688
6776 12:14:30.024805 [DATLAT]
6777 12:14:30.024922 Freq=400, CH1 RK0
6778 12:14:30.024990
6779 12:14:30.028269 DATLAT Default: 0xf
6780 12:14:30.028364 0, 0xFFFF, sum = 0
6781 12:14:30.031550 1, 0xFFFF, sum = 0
6782 12:14:30.031647 2, 0xFFFF, sum = 0
6783 12:14:30.034773 3, 0xFFFF, sum = 0
6784 12:14:30.034856 4, 0xFFFF, sum = 0
6785 12:14:30.038047 5, 0xFFFF, sum = 0
6786 12:14:30.038164 6, 0xFFFF, sum = 0
6787 12:14:30.041213 7, 0xFFFF, sum = 0
6788 12:14:30.041336 8, 0xFFFF, sum = 0
6789 12:14:30.045153 9, 0xFFFF, sum = 0
6790 12:14:30.045235 10, 0xFFFF, sum = 0
6791 12:14:30.047926 11, 0xFFFF, sum = 0
6792 12:14:30.051277 12, 0xFFFF, sum = 0
6793 12:14:30.051438 13, 0x0, sum = 1
6794 12:14:30.051552 14, 0x0, sum = 2
6795 12:14:30.055157 15, 0x0, sum = 3
6796 12:14:30.055239 16, 0x0, sum = 4
6797 12:14:30.058532 best_step = 14
6798 12:14:30.058613
6799 12:14:30.058680 ==
6800 12:14:30.061841 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 12:14:30.065222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 12:14:30.065307 ==
6803 12:14:30.068521 RX Vref Scan: 1
6804 12:14:30.068604
6805 12:14:30.068670 RX Vref 0 -> 0, step: 1
6806 12:14:30.068730
6807 12:14:30.071668 RX Delay -359 -> 252, step: 8
6808 12:14:30.071751
6809 12:14:30.075044 Set Vref, RX VrefLevel [Byte0]: 61
6810 12:14:30.078224 [Byte1]: 54
6811 12:14:30.082800
6812 12:14:30.082882 Final RX Vref Byte 0 = 61 to rank0
6813 12:14:30.086663 Final RX Vref Byte 1 = 54 to rank0
6814 12:14:30.089995 Final RX Vref Byte 0 = 61 to rank1
6815 12:14:30.093229 Final RX Vref Byte 1 = 54 to rank1==
6816 12:14:30.096560 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 12:14:30.103080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 12:14:30.103182 ==
6819 12:14:30.103278 DQS Delay:
6820 12:14:30.106409 DQS0 = 52, DQS1 = 60
6821 12:14:30.106494 DQM Delay:
6822 12:14:30.106560 DQM0 = 15, DQM1 = 13
6823 12:14:30.109563 DQ Delay:
6824 12:14:30.112767 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
6825 12:14:30.116051 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
6826 12:14:30.119323 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6827 12:14:30.122592 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6828 12:14:30.122677
6829 12:14:30.122762
6830 12:14:30.129056 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c35, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6831 12:14:30.133021 CH1 RK0: MR19=C0C, MR18=8C35
6832 12:14:30.139506 CH1_RK0: MR19=0xC0C, MR18=0x8C35, DQSOSC=392, MR23=63, INC=384, DEC=256
6833 12:14:30.139613 ==
6834 12:14:30.142624 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 12:14:30.145898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 12:14:30.145983 ==
6837 12:14:30.149188 [Gating] SW mode calibration
6838 12:14:30.155812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 12:14:30.162402 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 12:14:30.165707 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6841 12:14:30.169115 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6842 12:14:30.175527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 12:14:30.178816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 12:14:30.182713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 12:14:30.189248 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 12:14:30.192526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 12:14:30.195873 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 12:14:30.202433 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 12:14:30.202516 Total UI for P1: 0, mck2ui 16
6850 12:14:30.208870 best dqsien dly found for B0: ( 0, 14, 24)
6851 12:14:30.208954 Total UI for P1: 0, mck2ui 16
6852 12:14:30.215515 best dqsien dly found for B1: ( 0, 14, 24)
6853 12:14:30.218797 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 12:14:30.222003 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 12:14:30.222087
6856 12:14:30.225329 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 12:14:30.228496 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 12:14:30.231634 [Gating] SW calibration Done
6859 12:14:30.231717 ==
6860 12:14:30.234870 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 12:14:30.238204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 12:14:30.238304 ==
6863 12:14:30.241526 RX Vref Scan: 0
6864 12:14:30.241627
6865 12:14:30.244741 RX Vref 0 -> 0, step: 1
6866 12:14:30.244826
6867 12:14:30.244893 RX Delay -410 -> 252, step: 16
6868 12:14:30.251202 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6869 12:14:30.255048 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6870 12:14:30.258411 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6871 12:14:30.261543 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6872 12:14:30.268194 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6873 12:14:30.271604 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6874 12:14:30.274923 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6875 12:14:30.281273 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6876 12:14:30.284561 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6877 12:14:30.287809 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6878 12:14:30.291139 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6879 12:14:30.297650 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6880 12:14:30.300895 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6881 12:14:30.304133 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6882 12:14:30.307459 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6883 12:14:30.314274 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6884 12:14:30.314357 ==
6885 12:14:30.317459 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 12:14:30.320737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 12:14:30.320820 ==
6888 12:14:30.320889 DQS Delay:
6889 12:14:30.324027 DQS0 = 51, DQS1 = 59
6890 12:14:30.324143 DQM Delay:
6891 12:14:30.327829 DQM0 = 18, DQM1 = 20
6892 12:14:30.327903 DQ Delay:
6893 12:14:30.331036 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6894 12:14:30.334321 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6895 12:14:30.337514 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6896 12:14:30.340925 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6897 12:14:30.341008
6898 12:14:30.341073
6899 12:14:30.341134 ==
6900 12:14:30.344215 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 12:14:30.347488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 12:14:30.347571 ==
6903 12:14:30.350840
6904 12:14:30.350922
6905 12:14:30.350987 TX Vref Scan disable
6906 12:14:30.354068 == TX Byte 0 ==
6907 12:14:30.357455 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6908 12:14:30.360757 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6909 12:14:30.363963 == TX Byte 1 ==
6910 12:14:30.367203 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6911 12:14:30.370491 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6912 12:14:30.370588 ==
6913 12:14:30.373810 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 12:14:30.377117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 12:14:30.380337 ==
6916 12:14:30.380419
6917 12:14:30.380484
6918 12:14:30.380545 TX Vref Scan disable
6919 12:14:30.383542 == TX Byte 0 ==
6920 12:14:30.386856 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6921 12:14:30.389991 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6922 12:14:30.393876 == TX Byte 1 ==
6923 12:14:30.397123 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6924 12:14:30.400286 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6925 12:14:30.400370
6926 12:14:30.403574 [DATLAT]
6927 12:14:30.403656 Freq=400, CH1 RK1
6928 12:14:30.403722
6929 12:14:30.406801 DATLAT Default: 0xe
6930 12:14:30.406883 0, 0xFFFF, sum = 0
6931 12:14:30.410066 1, 0xFFFF, sum = 0
6932 12:14:30.410149 2, 0xFFFF, sum = 0
6933 12:14:30.413457 3, 0xFFFF, sum = 0
6934 12:14:30.413540 4, 0xFFFF, sum = 0
6935 12:14:30.416738 5, 0xFFFF, sum = 0
6936 12:14:30.416822 6, 0xFFFF, sum = 0
6937 12:14:30.419871 7, 0xFFFF, sum = 0
6938 12:14:30.419955 8, 0xFFFF, sum = 0
6939 12:14:30.423209 9, 0xFFFF, sum = 0
6940 12:14:30.423292 10, 0xFFFF, sum = 0
6941 12:14:30.426441 11, 0xFFFF, sum = 0
6942 12:14:30.429729 12, 0xFFFF, sum = 0
6943 12:14:30.429813 13, 0x0, sum = 1
6944 12:14:30.429880 14, 0x0, sum = 2
6945 12:14:30.433028 15, 0x0, sum = 3
6946 12:14:30.433111 16, 0x0, sum = 4
6947 12:14:30.436398 best_step = 14
6948 12:14:30.436480
6949 12:14:30.436545 ==
6950 12:14:30.439690 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 12:14:30.443372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 12:14:30.443469 ==
6953 12:14:30.446718 RX Vref Scan: 0
6954 12:14:30.446832
6955 12:14:30.446898 RX Vref 0 -> 0, step: 1
6956 12:14:30.447012
6957 12:14:30.449968 RX Delay -359 -> 252, step: 8
6958 12:14:30.458266 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6959 12:14:30.461508 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6960 12:14:30.464709 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6961 12:14:30.471209 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6962 12:14:30.474690 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6963 12:14:30.477901 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6964 12:14:30.481163 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6965 12:14:30.487690 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6966 12:14:30.490844 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6967 12:14:30.494218 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6968 12:14:30.497479 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6969 12:14:30.504702 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6970 12:14:30.507903 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6971 12:14:30.511311 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6972 12:14:30.514639 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6973 12:14:30.520989 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6974 12:14:30.521072 ==
6975 12:14:30.524314 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 12:14:30.527623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 12:14:30.527706 ==
6978 12:14:30.527802 DQS Delay:
6979 12:14:30.530865 DQS0 = 52, DQS1 = 56
6980 12:14:30.530947 DQM Delay:
6981 12:14:30.534206 DQM0 = 14, DQM1 = 9
6982 12:14:30.534289 DQ Delay:
6983 12:14:30.537509 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6984 12:14:30.540969 DQ4 =16, DQ5 =28, DQ6 =24, DQ7 =8
6985 12:14:30.544269 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6986 12:14:30.547526 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6987 12:14:30.547609
6988 12:14:30.547674
6989 12:14:30.553930 [DQSOSCAuto] RK1, (LSB)MR18= 0x7186, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 395 ps
6990 12:14:30.557131 CH1 RK1: MR19=C0C, MR18=7186
6991 12:14:30.564267 CH1_RK1: MR19=0xC0C, MR18=0x7186, DQSOSC=393, MR23=63, INC=382, DEC=254
6992 12:14:30.567384 [RxdqsGatingPostProcess] freq 400
6993 12:14:30.573887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 12:14:30.577283 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 12:14:30.577366 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 12:14:30.580543 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 12:14:30.583683 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 12:14:30.587051 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 12:14:30.590954 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 12:14:30.594180 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 12:14:30.597507 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 12:14:30.600630 Pre-setting of DQS Precalculation
7003 12:14:30.607252 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 12:14:30.613838 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 12:14:30.620281 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 12:14:30.620364
7007 12:14:30.620474
7008 12:14:30.623532 [Calibration Summary] 800 Mbps
7009 12:14:30.623634 CH 0, Rank 0
7010 12:14:30.626845 SW Impedance : PASS
7011 12:14:30.630110 DUTY Scan : NO K
7012 12:14:30.630191 ZQ Calibration : PASS
7013 12:14:30.633460 Jitter Meter : NO K
7014 12:14:30.633544 CBT Training : PASS
7015 12:14:30.637333 Write leveling : PASS
7016 12:14:30.640638 RX DQS gating : PASS
7017 12:14:30.640740 RX DQ/DQS(RDDQC) : PASS
7018 12:14:30.643919 TX DQ/DQS : PASS
7019 12:14:30.647120 RX DATLAT : PASS
7020 12:14:30.647260 RX DQ/DQS(Engine): PASS
7021 12:14:30.650246 TX OE : NO K
7022 12:14:30.650345 All Pass.
7023 12:14:30.650419
7024 12:14:30.653434 CH 0, Rank 1
7025 12:14:30.653533 SW Impedance : PASS
7026 12:14:30.656671 DUTY Scan : NO K
7027 12:14:30.659913 ZQ Calibration : PASS
7028 12:14:30.659989 Jitter Meter : NO K
7029 12:14:30.663228 CBT Training : PASS
7030 12:14:30.666666 Write leveling : NO K
7031 12:14:30.666763 RX DQS gating : PASS
7032 12:14:30.670103 RX DQ/DQS(RDDQC) : PASS
7033 12:14:30.673368 TX DQ/DQS : PASS
7034 12:14:30.673451 RX DATLAT : PASS
7035 12:14:30.676606 RX DQ/DQS(Engine): PASS
7036 12:14:30.679983 TX OE : NO K
7037 12:14:30.680065 All Pass.
7038 12:14:30.680131
7039 12:14:30.680191 CH 1, Rank 0
7040 12:14:30.683344 SW Impedance : PASS
7041 12:14:30.686662 DUTY Scan : NO K
7042 12:14:30.686745 ZQ Calibration : PASS
7043 12:14:30.690026 Jitter Meter : NO K
7044 12:14:30.690108 CBT Training : PASS
7045 12:14:30.693153 Write leveling : PASS
7046 12:14:30.696358 RX DQS gating : PASS
7047 12:14:30.696440 RX DQ/DQS(RDDQC) : PASS
7048 12:14:30.700111 TX DQ/DQS : PASS
7049 12:14:30.703269 RX DATLAT : PASS
7050 12:14:30.703359 RX DQ/DQS(Engine): PASS
7051 12:14:30.706528 TX OE : NO K
7052 12:14:30.706611 All Pass.
7053 12:14:30.706677
7054 12:14:30.710432 CH 1, Rank 1
7055 12:14:30.710515 SW Impedance : PASS
7056 12:14:30.713595 DUTY Scan : NO K
7057 12:14:30.716983 ZQ Calibration : PASS
7058 12:14:30.717066 Jitter Meter : NO K
7059 12:14:30.720212 CBT Training : PASS
7060 12:14:30.723555 Write leveling : NO K
7061 12:14:30.723638 RX DQS gating : PASS
7062 12:14:30.726283 RX DQ/DQS(RDDQC) : PASS
7063 12:14:30.730177 TX DQ/DQS : PASS
7064 12:14:30.730260 RX DATLAT : PASS
7065 12:14:30.733441 RX DQ/DQS(Engine): PASS
7066 12:14:30.736672 TX OE : NO K
7067 12:14:30.736756 All Pass.
7068 12:14:30.736823
7069 12:14:30.736886 DramC Write-DBI off
7070 12:14:30.739936 PER_BANK_REFRESH: Hybrid Mode
7071 12:14:30.743240 TX_TRACKING: ON
7072 12:14:30.749879 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 12:14:30.752951 [FAST_K] Save calibration result to emmc
7074 12:14:30.759853 dramc_set_vcore_voltage set vcore to 725000
7075 12:14:30.759936 Read voltage for 1600, 0
7076 12:14:30.763068 Vio18 = 0
7077 12:14:30.763179 Vcore = 725000
7078 12:14:30.763273 Vdram = 0
7079 12:14:30.766356 Vddq = 0
7080 12:14:30.766458 Vmddr = 0
7081 12:14:30.769663 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 12:14:30.776045 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 12:14:30.779942 MEM_TYPE=3, freq_sel=13
7084 12:14:30.782644 sv_algorithm_assistance_LP4_3733
7085 12:14:30.786443 ============ PULL DRAM RESETB DOWN ============
7086 12:14:30.789786 ========== PULL DRAM RESETB DOWN end =========
7087 12:14:30.792542 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 12:14:30.796458 ===================================
7089 12:14:30.799696 LPDDR4 DRAM CONFIGURATION
7090 12:14:30.802839 ===================================
7091 12:14:30.805953 EX_ROW_EN[0] = 0x0
7092 12:14:30.806038 EX_ROW_EN[1] = 0x0
7093 12:14:30.809386 LP4Y_EN = 0x0
7094 12:14:30.809470 WORK_FSP = 0x1
7095 12:14:30.812667 WL = 0x5
7096 12:14:30.812751 RL = 0x5
7097 12:14:30.815939 BL = 0x2
7098 12:14:30.816024 RPST = 0x0
7099 12:14:30.819127 RD_PRE = 0x0
7100 12:14:30.819211 WR_PRE = 0x1
7101 12:14:30.823014 WR_PST = 0x1
7102 12:14:30.826307 DBI_WR = 0x0
7103 12:14:30.826395 DBI_RD = 0x0
7104 12:14:30.829632 OTF = 0x1
7105 12:14:30.832914 ===================================
7106 12:14:30.832998 ===================================
7107 12:14:30.836229 ANA top config
7108 12:14:30.839565 ===================================
7109 12:14:30.842883 DLL_ASYNC_EN = 0
7110 12:14:30.842967 ALL_SLAVE_EN = 0
7111 12:14:30.846157 NEW_RANK_MODE = 1
7112 12:14:30.849479 DLL_IDLE_MODE = 1
7113 12:14:30.852792 LP45_APHY_COMB_EN = 1
7114 12:14:30.856063 TX_ODT_DIS = 0
7115 12:14:30.856148 NEW_8X_MODE = 1
7116 12:14:30.859207 ===================================
7117 12:14:30.862349 ===================================
7118 12:14:30.865510 data_rate = 3200
7119 12:14:30.869383 CKR = 1
7120 12:14:30.872675 DQ_P2S_RATIO = 8
7121 12:14:30.875851 ===================================
7122 12:14:30.879130 CA_P2S_RATIO = 8
7123 12:14:30.882303 DQ_CA_OPEN = 0
7124 12:14:30.882407 DQ_SEMI_OPEN = 0
7125 12:14:30.885633 CA_SEMI_OPEN = 0
7126 12:14:30.888898 CA_FULL_RATE = 0
7127 12:14:30.892097 DQ_CKDIV4_EN = 0
7128 12:14:30.895528 CA_CKDIV4_EN = 0
7129 12:14:30.898823 CA_PREDIV_EN = 0
7130 12:14:30.898908 PH8_DLY = 12
7131 12:14:30.901965 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 12:14:30.905307 DQ_AAMCK_DIV = 4
7133 12:14:30.908504 CA_AAMCK_DIV = 4
7134 12:14:30.912264 CA_ADMCK_DIV = 4
7135 12:14:30.915481 DQ_TRACK_CA_EN = 0
7136 12:14:30.918729 CA_PICK = 1600
7137 12:14:30.918812 CA_MCKIO = 1600
7138 12:14:30.922023 MCKIO_SEMI = 0
7139 12:14:30.925183 PLL_FREQ = 3068
7140 12:14:30.928502 DQ_UI_PI_RATIO = 32
7141 12:14:30.931898 CA_UI_PI_RATIO = 0
7142 12:14:30.935080 ===================================
7143 12:14:30.938441 ===================================
7144 12:14:30.941700 memory_type:LPDDR4
7145 12:14:30.941786 GP_NUM : 10
7146 12:14:30.945630 SRAM_EN : 1
7147 12:14:30.945713 MD32_EN : 0
7148 12:14:30.948287 ===================================
7149 12:14:30.951630 [ANA_INIT] >>>>>>>>>>>>>>
7150 12:14:30.954939 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 12:14:30.958931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 12:14:30.962060 ===================================
7153 12:14:30.965479 data_rate = 3200,PCW = 0X7600
7154 12:14:30.968539 ===================================
7155 12:14:30.971852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 12:14:30.978304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 12:14:30.981490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 12:14:30.988025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 12:14:30.991215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 12:14:30.994583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 12:14:30.994682 [ANA_INIT] flow start
7162 12:14:30.998565 [ANA_INIT] PLL >>>>>>>>
7163 12:14:31.001159 [ANA_INIT] PLL <<<<<<<<
7164 12:14:31.001244 [ANA_INIT] MIDPI >>>>>>>>
7165 12:14:31.005033 [ANA_INIT] MIDPI <<<<<<<<
7166 12:14:31.008367 [ANA_INIT] DLL >>>>>>>>
7167 12:14:31.008451 [ANA_INIT] DLL <<<<<<<<
7168 12:14:31.011537 [ANA_INIT] flow end
7169 12:14:31.014755 ============ LP4 DIFF to SE enter ============
7170 12:14:31.021452 ============ LP4 DIFF to SE exit ============
7171 12:14:31.021535 [ANA_INIT] <<<<<<<<<<<<<
7172 12:14:31.024556 [Flow] Enable top DCM control >>>>>
7173 12:14:31.027873 [Flow] Enable top DCM control <<<<<
7174 12:14:31.031055 Enable DLL master slave shuffle
7175 12:14:31.038217 ==============================================================
7176 12:14:31.038306 Gating Mode config
7177 12:14:31.044884 ==============================================================
7178 12:14:31.048142 Config description:
7179 12:14:31.054196 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 12:14:31.060865 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 12:14:31.068033 SELPH_MODE 0: By rank 1: By Phase
7182 12:14:31.074485 ==============================================================
7183 12:14:31.077781 GAT_TRACK_EN = 1
7184 12:14:31.077855 RX_GATING_MODE = 2
7185 12:14:31.081031 RX_GATING_TRACK_MODE = 2
7186 12:14:31.084368 SELPH_MODE = 1
7187 12:14:31.087809 PICG_EARLY_EN = 1
7188 12:14:31.090989 VALID_LAT_VALUE = 1
7189 12:14:31.097506 ==============================================================
7190 12:14:31.100867 Enter into Gating configuration >>>>
7191 12:14:31.104140 Exit from Gating configuration <<<<
7192 12:14:31.107405 Enter into DVFS_PRE_config >>>>>
7193 12:14:31.117859 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 12:14:31.120965 Exit from DVFS_PRE_config <<<<<
7195 12:14:31.124269 Enter into PICG configuration >>>>
7196 12:14:31.127548 Exit from PICG configuration <<<<
7197 12:14:31.130754 [RX_INPUT] configuration >>>>>
7198 12:14:31.130839 [RX_INPUT] configuration <<<<<
7199 12:14:31.137220 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 12:14:31.144423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 12:14:31.151050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 12:14:31.154310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 12:14:31.160862 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 12:14:31.167313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 12:14:31.170753 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 12:14:31.173992 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 12:14:31.180878 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 12:14:31.183970 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 12:14:31.187154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 12:14:31.193752 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 12:14:31.197026 ===================================
7212 12:14:31.197111 LPDDR4 DRAM CONFIGURATION
7213 12:14:31.200342 ===================================
7214 12:14:31.203677 EX_ROW_EN[0] = 0x0
7215 12:14:31.203762 EX_ROW_EN[1] = 0x0
7216 12:14:31.207051 LP4Y_EN = 0x0
7217 12:14:31.210324 WORK_FSP = 0x1
7218 12:14:31.210412 WL = 0x5
7219 12:14:31.213678 RL = 0x5
7220 12:14:31.213763 BL = 0x2
7221 12:14:31.216910 RPST = 0x0
7222 12:14:31.216994 RD_PRE = 0x0
7223 12:14:31.220211 WR_PRE = 0x1
7224 12:14:31.220295 WR_PST = 0x1
7225 12:14:31.223396 DBI_WR = 0x0
7226 12:14:31.223480 DBI_RD = 0x0
7227 12:14:31.227137 OTF = 0x1
7228 12:14:31.230338 ===================================
7229 12:14:31.233577 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 12:14:31.236735 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 12:14:31.243866 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 12:14:31.247105 ===================================
7233 12:14:31.247189 LPDDR4 DRAM CONFIGURATION
7234 12:14:31.250434 ===================================
7235 12:14:31.253823 EX_ROW_EN[0] = 0x10
7236 12:14:31.253907 EX_ROW_EN[1] = 0x0
7237 12:14:31.257144 LP4Y_EN = 0x0
7238 12:14:31.257229 WORK_FSP = 0x1
7239 12:14:31.260357 WL = 0x5
7240 12:14:31.263638 RL = 0x5
7241 12:14:31.263726 BL = 0x2
7242 12:14:31.266900 RPST = 0x0
7243 12:14:31.266985 RD_PRE = 0x0
7244 12:14:31.270144 WR_PRE = 0x1
7245 12:14:31.270228 WR_PST = 0x1
7246 12:14:31.273402 DBI_WR = 0x0
7247 12:14:31.273476 DBI_RD = 0x0
7248 12:14:31.276687 OTF = 0x1
7249 12:14:31.280361 ===================================
7250 12:14:31.286587 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 12:14:31.286701 ==
7252 12:14:31.289649 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 12:14:31.292914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 12:14:31.293015 ==
7255 12:14:31.296182 [Duty_Offset_Calibration]
7256 12:14:31.296282 B0:2 B1:-1 CA:1
7257 12:14:31.296376
7258 12:14:31.299507 [DutyScan_Calibration_Flow] k_type=0
7259 12:14:31.309169
7260 12:14:31.309251 ==CLK 0==
7261 12:14:31.312389 Final CLK duty delay cell = -4
7262 12:14:31.316303 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7263 12:14:31.319635 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7264 12:14:31.322939 [-4] AVG Duty = 4937%(X100)
7265 12:14:31.323038
7266 12:14:31.326089 CH0 CLK Duty spec in!! Max-Min= 187%
7267 12:14:31.329295 [DutyScan_Calibration_Flow] ====Done====
7268 12:14:31.329394
7269 12:14:31.332407 [DutyScan_Calibration_Flow] k_type=1
7270 12:14:31.349024
7271 12:14:31.349133 ==DQS 0 ==
7272 12:14:31.352302 Final DQS duty delay cell = 0
7273 12:14:31.355537 [0] MAX Duty = 5125%(X100), DQS PI = 54
7274 12:14:31.358750 [0] MIN Duty = 5031%(X100), DQS PI = 4
7275 12:14:31.362013 [0] AVG Duty = 5078%(X100)
7276 12:14:31.362115
7277 12:14:31.362190 ==DQS 1 ==
7278 12:14:31.365321 Final DQS duty delay cell = -4
7279 12:14:31.368542 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7280 12:14:31.372028 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7281 12:14:31.375381 [-4] AVG Duty = 5046%(X100)
7282 12:14:31.375488
7283 12:14:31.378654 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7284 12:14:31.378758
7285 12:14:31.381941 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7286 12:14:31.385323 [DutyScan_Calibration_Flow] ====Done====
7287 12:14:31.385424
7288 12:14:31.388464 [DutyScan_Calibration_Flow] k_type=3
7289 12:14:31.405847
7290 12:14:31.405963 ==DQM 0 ==
7291 12:14:31.409137 Final DQM duty delay cell = 0
7292 12:14:31.412406 [0] MAX Duty = 5000%(X100), DQS PI = 16
7293 12:14:31.416370 [0] MIN Duty = 4875%(X100), DQS PI = 6
7294 12:14:31.419613 [0] AVG Duty = 4937%(X100)
7295 12:14:31.419692
7296 12:14:31.419757 ==DQM 1 ==
7297 12:14:31.422923 Final DQM duty delay cell = 0
7298 12:14:31.426239 [0] MAX Duty = 5218%(X100), DQS PI = 58
7299 12:14:31.429566 [0] MIN Duty = 4969%(X100), DQS PI = 18
7300 12:14:31.432881 [0] AVG Duty = 5093%(X100)
7301 12:14:31.432963
7302 12:14:31.435901 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7303 12:14:31.435983
7304 12:14:31.439132 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7305 12:14:31.442430 [DutyScan_Calibration_Flow] ====Done====
7306 12:14:31.442528
7307 12:14:31.445585 [DutyScan_Calibration_Flow] k_type=2
7308 12:14:31.463441
7309 12:14:31.463561 ==DQ 0 ==
7310 12:14:31.466748 Final DQ duty delay cell = 0
7311 12:14:31.470059 [0] MAX Duty = 5156%(X100), DQS PI = 0
7312 12:14:31.473543 [0] MIN Duty = 5031%(X100), DQS PI = 12
7313 12:14:31.473622 [0] AVG Duty = 5093%(X100)
7314 12:14:31.473687
7315 12:14:31.476846 ==DQ 1 ==
7316 12:14:31.480157 Final DQ duty delay cell = 0
7317 12:14:31.483469 [0] MAX Duty = 5000%(X100), DQS PI = 0
7318 12:14:31.486695 [0] MIN Duty = 4907%(X100), DQS PI = 18
7319 12:14:31.486776 [0] AVG Duty = 4953%(X100)
7320 12:14:31.486841
7321 12:14:31.489891 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7322 12:14:31.493153
7323 12:14:31.493234 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7324 12:14:31.499607 [DutyScan_Calibration_Flow] ====Done====
7325 12:14:31.499697 ==
7326 12:14:31.502872 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 12:14:31.506183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 12:14:31.506265 ==
7329 12:14:31.509517 [Duty_Offset_Calibration]
7330 12:14:31.509596 B0:1 B1:1 CA:2
7331 12:14:31.509661
7332 12:14:31.512670 [DutyScan_Calibration_Flow] k_type=0
7333 12:14:31.523045
7334 12:14:31.523126 ==CLK 0==
7335 12:14:31.526369 Final CLK duty delay cell = 0
7336 12:14:31.529620 [0] MAX Duty = 5187%(X100), DQS PI = 24
7337 12:14:31.532867 [0] MIN Duty = 4938%(X100), DQS PI = 50
7338 12:14:31.536713 [0] AVG Duty = 5062%(X100)
7339 12:14:31.536785
7340 12:14:31.540015 CH1 CLK Duty spec in!! Max-Min= 249%
7341 12:14:31.543140 [DutyScan_Calibration_Flow] ====Done====
7342 12:14:31.543216
7343 12:14:31.546372 [DutyScan_Calibration_Flow] k_type=1
7344 12:14:31.562637
7345 12:14:31.562723 ==DQS 0 ==
7346 12:14:31.566020 Final DQS duty delay cell = 0
7347 12:14:31.569396 [0] MAX Duty = 5062%(X100), DQS PI = 20
7348 12:14:31.572630 [0] MIN Duty = 4813%(X100), DQS PI = 52
7349 12:14:31.576038 [0] AVG Duty = 4937%(X100)
7350 12:14:31.576116
7351 12:14:31.576183 ==DQS 1 ==
7352 12:14:31.579301 Final DQS duty delay cell = 0
7353 12:14:31.582607 [0] MAX Duty = 5062%(X100), DQS PI = 34
7354 12:14:31.585960 [0] MIN Duty = 4938%(X100), DQS PI = 12
7355 12:14:31.589200 [0] AVG Duty = 5000%(X100)
7356 12:14:31.589292
7357 12:14:31.592575 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7358 12:14:31.592650
7359 12:14:31.595978 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7360 12:14:31.599885 [DutyScan_Calibration_Flow] ====Done====
7361 12:14:31.599976
7362 12:14:31.602800 [DutyScan_Calibration_Flow] k_type=3
7363 12:14:31.620197
7364 12:14:31.620301 ==DQM 0 ==
7365 12:14:31.623502 Final DQM duty delay cell = 0
7366 12:14:31.626807 [0] MAX Duty = 5156%(X100), DQS PI = 20
7367 12:14:31.629483 [0] MIN Duty = 4844%(X100), DQS PI = 50
7368 12:14:31.632739 [0] AVG Duty = 5000%(X100)
7369 12:14:31.632820
7370 12:14:31.632902 ==DQM 1 ==
7371 12:14:31.636695 Final DQM duty delay cell = 0
7372 12:14:31.639389 [0] MAX Duty = 5125%(X100), DQS PI = 8
7373 12:14:31.643312 [0] MIN Duty = 4875%(X100), DQS PI = 20
7374 12:14:31.646584 [0] AVG Duty = 5000%(X100)
7375 12:14:31.646660
7376 12:14:31.649627 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7377 12:14:31.649709
7378 12:14:31.652843 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7379 12:14:31.656590 [DutyScan_Calibration_Flow] ====Done====
7380 12:14:31.656669
7381 12:14:31.659277 [DutyScan_Calibration_Flow] k_type=2
7382 12:14:31.677032
7383 12:14:31.677172 ==DQ 0 ==
7384 12:14:31.680339 Final DQ duty delay cell = 0
7385 12:14:31.683517 [0] MAX Duty = 5156%(X100), DQS PI = 20
7386 12:14:31.686784 [0] MIN Duty = 4907%(X100), DQS PI = 52
7387 12:14:31.686909 [0] AVG Duty = 5031%(X100)
7388 12:14:31.690213
7389 12:14:31.690336 ==DQ 1 ==
7390 12:14:31.693230 Final DQ duty delay cell = 0
7391 12:14:31.696565 [0] MAX Duty = 5093%(X100), DQS PI = 6
7392 12:14:31.699898 [0] MIN Duty = 5031%(X100), DQS PI = 0
7393 12:14:31.700016 [0] AVG Duty = 5062%(X100)
7394 12:14:31.700131
7395 12:14:31.703027 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7396 12:14:31.706830
7397 12:14:31.710088 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7398 12:14:31.713395 [DutyScan_Calibration_Flow] ====Done====
7399 12:14:31.716635 nWR fixed to 30
7400 12:14:31.716719 [ModeRegInit_LP4] CH0 RK0
7401 12:14:31.719762 [ModeRegInit_LP4] CH0 RK1
7402 12:14:31.723529 [ModeRegInit_LP4] CH1 RK0
7403 12:14:31.723674 [ModeRegInit_LP4] CH1 RK1
7404 12:14:31.726763 match AC timing 5
7405 12:14:31.729419 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 12:14:31.736097 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 12:14:31.739309 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 12:14:31.745920 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 12:14:31.749265 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 12:14:31.749396 [MiockJmeterHQA]
7411 12:14:31.749530
7412 12:14:31.752611 [DramcMiockJmeter] u1RxGatingPI = 0
7413 12:14:31.755911 0 : 4252, 4027
7414 12:14:31.756130 4 : 4255, 4029
7415 12:14:31.759650 8 : 4363, 4137
7416 12:14:31.759780 12 : 4252, 4027
7417 12:14:31.759916 16 : 4363, 4137
7418 12:14:31.762827 20 : 4252, 4027
7419 12:14:31.763030 24 : 4252, 4027
7420 12:14:31.766153 28 : 4252, 4027
7421 12:14:31.766318 32 : 4253, 4027
7422 12:14:31.769553 36 : 4252, 4027
7423 12:14:31.769697 40 : 4361, 4137
7424 12:14:31.772997 44 : 4365, 4140
7425 12:14:31.773175 48 : 4249, 4027
7426 12:14:31.773290 52 : 4253, 4026
7427 12:14:31.776234 56 : 4252, 4027
7428 12:14:31.776368 60 : 4250, 4027
7429 12:14:31.779395 64 : 4250, 4027
7430 12:14:31.779509 68 : 4361, 4138
7431 12:14:31.782807 72 : 4250, 4026
7432 12:14:31.782900 76 : 4250, 4027
7433 12:14:31.785946 80 : 4250, 4027
7434 12:14:31.786037 84 : 4250, 4027
7435 12:14:31.786109 88 : 4250, 4027
7436 12:14:31.789221 92 : 4360, 4137
7437 12:14:31.789312 96 : 4361, 3435
7438 12:14:31.792656 100 : 4249, 0
7439 12:14:31.792747 104 : 4361, 0
7440 12:14:31.792819 108 : 4250, 0
7441 12:14:31.795959 112 : 4250, 0
7442 12:14:31.796055 116 : 4250, 0
7443 12:14:31.799178 120 : 4250, 0
7444 12:14:31.799304 124 : 4250, 0
7445 12:14:31.799411 128 : 4250, 0
7446 12:14:31.802553 132 : 4250, 0
7447 12:14:31.802639 136 : 4360, 0
7448 12:14:31.805717 140 : 4250, 0
7449 12:14:31.805803 144 : 4361, 0
7450 12:14:31.805871 148 : 4252, 0
7451 12:14:31.809375 152 : 4360, 0
7452 12:14:31.809460 156 : 4250, 0
7453 12:14:31.809533 160 : 4250, 0
7454 12:14:31.812529 164 : 4250, 0
7455 12:14:31.812616 168 : 4250, 0
7456 12:14:31.815868 172 : 4250, 0
7457 12:14:31.815955 176 : 4250, 0
7458 12:14:31.816024 180 : 4250, 0
7459 12:14:31.819104 184 : 4250, 0
7460 12:14:31.819190 188 : 4361, 0
7461 12:14:31.822391 192 : 4250, 0
7462 12:14:31.822477 196 : 4361, 0
7463 12:14:31.822545 200 : 4250, 0
7464 12:14:31.825488 204 : 4249, 0
7465 12:14:31.825574 208 : 4250, 0
7466 12:14:31.829336 212 : 4250, 198
7467 12:14:31.829423 216 : 4250, 3843
7468 12:14:31.832590 220 : 4249, 4027
7469 12:14:31.832676 224 : 4360, 4137
7470 12:14:31.832744 228 : 4250, 4027
7471 12:14:31.835829 232 : 4250, 4027
7472 12:14:31.835914 236 : 4361, 4138
7473 12:14:31.839105 240 : 4249, 4027
7474 12:14:31.839190 244 : 4250, 4026
7475 12:14:31.842447 248 : 4361, 4137
7476 12:14:31.842525 252 : 4250, 4027
7477 12:14:31.845661 256 : 4249, 4027
7478 12:14:31.845735 260 : 4250, 4026
7479 12:14:31.848975 264 : 4250, 4027
7480 12:14:31.849046 268 : 4250, 4026
7481 12:14:31.852262 272 : 4249, 4027
7482 12:14:31.852368 276 : 4360, 4137
7483 12:14:31.855577 280 : 4250, 4027
7484 12:14:31.855686 284 : 4250, 4027
7485 12:14:31.858711 288 : 4361, 4138
7486 12:14:31.858829 292 : 4250, 4027
7487 12:14:31.858928 296 : 4253, 4026
7488 12:14:31.861891 300 : 4361, 4137
7489 12:14:31.861996 304 : 4250, 4027
7490 12:14:31.865113 308 : 4250, 4027
7491 12:14:31.865230 312 : 4250, 4026
7492 12:14:31.868895 316 : 4250, 4027
7493 12:14:31.868981 320 : 4250, 4027
7494 12:14:31.872190 324 : 4249, 4027
7495 12:14:31.872276 328 : 4360, 4137
7496 12:14:31.875596 332 : 4250, 2786
7497 12:14:31.875682 336 : 4250, 43
7498 12:14:31.875751
7499 12:14:31.878848 MIOCK jitter meter ch=0
7500 12:14:31.878932
7501 12:14:31.882166 1T = (336-100) = 236 dly cells
7502 12:14:31.885451 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7503 12:14:31.885537 ==
7504 12:14:31.888866 Dram Type= 6, Freq= 0, CH_0, rank 0
7505 12:14:31.895065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7506 12:14:31.895155 ==
7507 12:14:31.898351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7508 12:14:31.905197 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7509 12:14:31.908504 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7510 12:14:31.915048 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7511 12:14:31.923526 [CA 0] Center 44 (14~74) winsize 61
7512 12:14:31.926786 [CA 1] Center 44 (14~74) winsize 61
7513 12:14:31.929999 [CA 2] Center 39 (10~68) winsize 59
7514 12:14:31.933159 [CA 3] Center 39 (10~68) winsize 59
7515 12:14:31.936583 [CA 4] Center 37 (7~67) winsize 61
7516 12:14:31.939969 [CA 5] Center 37 (7~67) winsize 61
7517 12:14:31.940079
7518 12:14:31.943159 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7519 12:14:31.943272
7520 12:14:31.949535 [CATrainingPosCal] consider 1 rank data
7521 12:14:31.949641 u2DelayCellTimex100 = 275/100 ps
7522 12:14:31.956263 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7523 12:14:31.959497 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7524 12:14:31.962802 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7525 12:14:31.965985 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 12:14:31.969267 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7527 12:14:31.973288 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 12:14:31.973396
7529 12:14:31.976623 CA PerBit enable=1, Macro0, CA PI delay=37
7530 12:14:31.976727
7531 12:14:31.979312 [CBTSetCACLKResult] CA Dly = 37
7532 12:14:31.982584 CS Dly: 10 (0~41)
7533 12:14:31.985861 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7534 12:14:31.989135 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7535 12:14:31.989239 ==
7536 12:14:31.992508 Dram Type= 6, Freq= 0, CH_0, rank 1
7537 12:14:31.999078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 12:14:31.999189 ==
7539 12:14:32.002518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7540 12:14:32.009403 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7541 12:14:32.012675 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7542 12:14:32.019075 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7543 12:14:32.026694 [CA 0] Center 44 (14~75) winsize 62
7544 12:14:32.030605 [CA 1] Center 44 (14~75) winsize 62
7545 12:14:32.033842 [CA 2] Center 39 (10~69) winsize 60
7546 12:14:32.036990 [CA 3] Center 39 (10~69) winsize 60
7547 12:14:32.040358 [CA 4] Center 38 (8~68) winsize 61
7548 12:14:32.043750 [CA 5] Center 37 (7~67) winsize 61
7549 12:14:32.043857
7550 12:14:32.047086 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7551 12:14:32.047189
7552 12:14:32.050305 [CATrainingPosCal] consider 2 rank data
7553 12:14:32.053678 u2DelayCellTimex100 = 275/100 ps
7554 12:14:32.060327 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7555 12:14:32.063634 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7556 12:14:32.066905 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7557 12:14:32.070184 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 12:14:32.073399 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7559 12:14:32.076738 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 12:14:32.076846
7561 12:14:32.080039 CA PerBit enable=1, Macro0, CA PI delay=37
7562 12:14:32.080142
7563 12:14:32.083282 [CBTSetCACLKResult] CA Dly = 37
7564 12:14:32.086579 CS Dly: 11 (0~44)
7565 12:14:32.089882 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7566 12:14:32.093166 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7567 12:14:32.093267
7568 12:14:32.096619 ----->DramcWriteLeveling(PI) begin...
7569 12:14:32.096721 ==
7570 12:14:32.100001 Dram Type= 6, Freq= 0, CH_0, rank 0
7571 12:14:32.106482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 12:14:32.106591 ==
7573 12:14:32.109878 Write leveling (Byte 0): 34 => 34
7574 12:14:32.113116 Write leveling (Byte 1): 27 => 27
7575 12:14:32.113218 DramcWriteLeveling(PI) end<-----
7576 12:14:32.116551
7577 12:14:32.116625 ==
7578 12:14:32.119826 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 12:14:32.122986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7580 12:14:32.123087 ==
7581 12:14:32.126302 [Gating] SW mode calibration
7582 12:14:32.132792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7583 12:14:32.135996 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7584 12:14:32.143154 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 12:14:32.146404 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 12:14:32.149915 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 12:14:32.156502 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 12:14:32.159965 1 4 16 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7589 12:14:32.162665 1 4 20 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
7590 12:14:32.169863 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7591 12:14:32.173126 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 12:14:32.176321 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 12:14:32.182803 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 12:14:32.186071 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 12:14:32.189386 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7596 12:14:32.195777 1 5 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7597 12:14:32.199037 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7598 12:14:32.202906 1 5 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7599 12:14:32.209449 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 12:14:32.212786 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 12:14:32.216052 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 12:14:32.222646 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:14:32.226277 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:14:32.229480 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7605 12:14:32.232683 1 6 20 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
7606 12:14:32.239573 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7607 12:14:32.242773 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 12:14:32.245909 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 12:14:32.252467 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 12:14:32.255629 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:14:32.258990 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:14:32.265653 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 12:14:32.268926 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7614 12:14:32.272322 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 12:14:32.278893 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 12:14:32.282050 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 12:14:32.285400 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 12:14:32.291827 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:14:32.295738 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:14:32.298995 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:14:32.305550 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:14:32.308852 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:14:32.312174 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:14:32.318853 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:14:32.322152 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:14:32.325486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:14:32.331897 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:14:32.335648 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7629 12:14:32.338839 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7630 12:14:32.345164 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7631 12:14:32.345256 Total UI for P1: 0, mck2ui 16
7632 12:14:32.352042 best dqsien dly found for B0: ( 1, 9, 18)
7633 12:14:32.355287 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 12:14:32.358573 Total UI for P1: 0, mck2ui 16
7635 12:14:32.361997 best dqsien dly found for B1: ( 1, 9, 22)
7636 12:14:32.365308 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7637 12:14:32.368655 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7638 12:14:32.368764
7639 12:14:32.371893 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7640 12:14:32.375179 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7641 12:14:32.378436 [Gating] SW calibration Done
7642 12:14:32.378545 ==
7643 12:14:32.381764 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 12:14:32.388194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 12:14:32.388325 ==
7646 12:14:32.388428 RX Vref Scan: 0
7647 12:14:32.388533
7648 12:14:32.391377 RX Vref 0 -> 0, step: 1
7649 12:14:32.391464
7650 12:14:32.394823 RX Delay 0 -> 252, step: 8
7651 12:14:32.397976 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7652 12:14:32.401392 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7653 12:14:32.404737 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7654 12:14:32.408024 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7655 12:14:32.414622 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7656 12:14:32.417933 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7657 12:14:32.421311 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7658 12:14:32.424621 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7659 12:14:32.427823 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7660 12:14:32.434508 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7661 12:14:32.438583 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7662 12:14:32.441643 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7663 12:14:32.444799 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7664 12:14:32.447995 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7665 12:14:32.454473 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7666 12:14:32.457831 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7667 12:14:32.457911 ==
7668 12:14:32.461783 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 12:14:32.465128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 12:14:32.465206 ==
7671 12:14:32.468387 DQS Delay:
7672 12:14:32.468474 DQS0 = 0, DQS1 = 0
7673 12:14:32.468543 DQM Delay:
7674 12:14:32.471758 DQM0 = 132, DQM1 = 123
7675 12:14:32.471848 DQ Delay:
7676 12:14:32.475023 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7677 12:14:32.477705 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7678 12:14:32.481135 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7679 12:14:32.487911 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7680 12:14:32.488003
7681 12:14:32.488091
7682 12:14:32.488174 ==
7683 12:14:32.491138 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 12:14:32.494442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 12:14:32.494528 ==
7686 12:14:32.494595
7687 12:14:32.494658
7688 12:14:32.497616 TX Vref Scan disable
7689 12:14:32.497701 == TX Byte 0 ==
7690 12:14:32.504283 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7691 12:14:32.507713 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7692 12:14:32.507825 == TX Byte 1 ==
7693 12:14:32.514176 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7694 12:14:32.517594 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7695 12:14:32.517679 ==
7696 12:14:32.520912 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 12:14:32.524141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 12:14:32.524226 ==
7699 12:14:32.540354
7700 12:14:32.543774 TX Vref early break, caculate TX vref
7701 12:14:32.547452 TX Vref=16, minBit 7, minWin=21, winSum=363
7702 12:14:32.550632 TX Vref=18, minBit 7, minWin=22, winSum=373
7703 12:14:32.553778 TX Vref=20, minBit 7, minWin=23, winSum=383
7704 12:14:32.556980 TX Vref=22, minBit 4, minWin=24, winSum=396
7705 12:14:32.560386 TX Vref=24, minBit 7, minWin=24, winSum=404
7706 12:14:32.567343 TX Vref=26, minBit 2, minWin=25, winSum=414
7707 12:14:32.570696 TX Vref=28, minBit 4, minWin=25, winSum=424
7708 12:14:32.573450 TX Vref=30, minBit 0, minWin=26, winSum=422
7709 12:14:32.576747 TX Vref=32, minBit 4, minWin=24, winSum=412
7710 12:14:32.579987 TX Vref=34, minBit 4, minWin=24, winSum=405
7711 12:14:32.583342 TX Vref=36, minBit 4, minWin=23, winSum=390
7712 12:14:32.590571 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
7713 12:14:32.590685
7714 12:14:32.593830 Final TX Range 0 Vref 30
7715 12:14:32.593937
7716 12:14:32.594043 ==
7717 12:14:32.597128 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 12:14:32.600303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 12:14:32.600414 ==
7720 12:14:32.600520
7721 12:14:32.603537
7722 12:14:32.603647 TX Vref Scan disable
7723 12:14:32.610222 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 12:14:32.610346 == TX Byte 0 ==
7725 12:14:32.613538 u2DelayCellOfst[0]=14 cells (4 PI)
7726 12:14:32.616988 u2DelayCellOfst[1]=21 cells (6 PI)
7727 12:14:32.620294 u2DelayCellOfst[2]=14 cells (4 PI)
7728 12:14:32.623653 u2DelayCellOfst[3]=17 cells (5 PI)
7729 12:14:32.626368 u2DelayCellOfst[4]=10 cells (3 PI)
7730 12:14:32.629659 u2DelayCellOfst[5]=0 cells (0 PI)
7731 12:14:32.632971 u2DelayCellOfst[6]=21 cells (6 PI)
7732 12:14:32.636939 u2DelayCellOfst[7]=21 cells (6 PI)
7733 12:14:32.639635 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7734 12:14:32.643570 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7735 12:14:32.646844 == TX Byte 1 ==
7736 12:14:32.649996 u2DelayCellOfst[8]=0 cells (0 PI)
7737 12:14:32.653401 u2DelayCellOfst[9]=0 cells (0 PI)
7738 12:14:32.656655 u2DelayCellOfst[10]=7 cells (2 PI)
7739 12:14:32.659881 u2DelayCellOfst[11]=0 cells (0 PI)
7740 12:14:32.660006 u2DelayCellOfst[12]=14 cells (4 PI)
7741 12:14:32.663143 u2DelayCellOfst[13]=10 cells (3 PI)
7742 12:14:32.666426 u2DelayCellOfst[14]=17 cells (5 PI)
7743 12:14:32.669712 u2DelayCellOfst[15]=10 cells (3 PI)
7744 12:14:32.676385 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7745 12:14:32.679639 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7746 12:14:32.679722 DramC Write-DBI on
7747 12:14:32.679818 ==
7748 12:14:32.682943 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 12:14:32.689483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 12:14:32.689592 ==
7751 12:14:32.689690
7752 12:14:32.689784
7753 12:14:32.689874 TX Vref Scan disable
7754 12:14:32.694100 == TX Byte 0 ==
7755 12:14:32.697396 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7756 12:14:32.700648 == TX Byte 1 ==
7757 12:14:32.703857 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7758 12:14:32.707047 DramC Write-DBI off
7759 12:14:32.707146
7760 12:14:32.707218 [DATLAT]
7761 12:14:32.707282 Freq=1600, CH0 RK0
7762 12:14:32.707370
7763 12:14:32.710272 DATLAT Default: 0xf
7764 12:14:32.710350 0, 0xFFFF, sum = 0
7765 12:14:32.713585 1, 0xFFFF, sum = 0
7766 12:14:32.716853 2, 0xFFFF, sum = 0
7767 12:14:32.716946 3, 0xFFFF, sum = 0
7768 12:14:32.720787 4, 0xFFFF, sum = 0
7769 12:14:32.720863 5, 0xFFFF, sum = 0
7770 12:14:32.723529 6, 0xFFFF, sum = 0
7771 12:14:32.723616 7, 0xFFFF, sum = 0
7772 12:14:32.726886 8, 0xFFFF, sum = 0
7773 12:14:32.726966 9, 0xFFFF, sum = 0
7774 12:14:32.730181 10, 0xFFFF, sum = 0
7775 12:14:32.730264 11, 0xFFFF, sum = 0
7776 12:14:32.733626 12, 0xFFFF, sum = 0
7777 12:14:32.733700 13, 0xFFFF, sum = 0
7778 12:14:32.736839 14, 0x0, sum = 1
7779 12:14:32.736916 15, 0x0, sum = 2
7780 12:14:32.740336 16, 0x0, sum = 3
7781 12:14:32.740411 17, 0x0, sum = 4
7782 12:14:32.743499 best_step = 15
7783 12:14:32.743571
7784 12:14:32.743645 ==
7785 12:14:32.746917 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 12:14:32.750152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 12:14:32.750229 ==
7788 12:14:32.753471 RX Vref Scan: 1
7789 12:14:32.753558
7790 12:14:32.753624 Set Vref Range= 24 -> 127
7791 12:14:32.753695
7792 12:14:32.756765 RX Vref 24 -> 127, step: 1
7793 12:14:32.756842
7794 12:14:32.760053 RX Delay 11 -> 252, step: 4
7795 12:14:32.760133
7796 12:14:32.763412 Set Vref, RX VrefLevel [Byte0]: 24
7797 12:14:32.766511 [Byte1]: 24
7798 12:14:32.766587
7799 12:14:32.770308 Set Vref, RX VrefLevel [Byte0]: 25
7800 12:14:32.773514 [Byte1]: 25
7801 12:14:32.776672
7802 12:14:32.776747 Set Vref, RX VrefLevel [Byte0]: 26
7803 12:14:32.779903 [Byte1]: 26
7804 12:14:32.784360
7805 12:14:32.784462 Set Vref, RX VrefLevel [Byte0]: 27
7806 12:14:32.787607 [Byte1]: 27
7807 12:14:32.792290
7808 12:14:32.792375 Set Vref, RX VrefLevel [Byte0]: 28
7809 12:14:32.795508 [Byte1]: 28
7810 12:14:32.799456
7811 12:14:32.799534 Set Vref, RX VrefLevel [Byte0]: 29
7812 12:14:32.802775 [Byte1]: 29
7813 12:14:32.807572
7814 12:14:32.807663 Set Vref, RX VrefLevel [Byte0]: 30
7815 12:14:32.810764 [Byte1]: 30
7816 12:14:32.814656
7817 12:14:32.814743 Set Vref, RX VrefLevel [Byte0]: 31
7818 12:14:32.817867 [Byte1]: 31
7819 12:14:32.822488
7820 12:14:32.822569 Set Vref, RX VrefLevel [Byte0]: 32
7821 12:14:32.825773 [Byte1]: 32
7822 12:14:32.829804
7823 12:14:32.829880 Set Vref, RX VrefLevel [Byte0]: 33
7824 12:14:32.833125 [Byte1]: 33
7825 12:14:32.837926
7826 12:14:32.838011 Set Vref, RX VrefLevel [Byte0]: 34
7827 12:14:32.841189 [Byte1]: 34
7828 12:14:32.845165
7829 12:14:32.845241 Set Vref, RX VrefLevel [Byte0]: 35
7830 12:14:32.848576 [Byte1]: 35
7831 12:14:32.853129
7832 12:14:32.853213 Set Vref, RX VrefLevel [Byte0]: 36
7833 12:14:32.859650 [Byte1]: 36
7834 12:14:32.859732
7835 12:14:32.862268 Set Vref, RX VrefLevel [Byte0]: 37
7836 12:14:32.866201 [Byte1]: 37
7837 12:14:32.866276
7838 12:14:32.869404 Set Vref, RX VrefLevel [Byte0]: 38
7839 12:14:32.872573 [Byte1]: 38
7840 12:14:32.875947
7841 12:14:32.876025 Set Vref, RX VrefLevel [Byte0]: 39
7842 12:14:32.879192 [Byte1]: 39
7843 12:14:32.883104
7844 12:14:32.883209 Set Vref, RX VrefLevel [Byte0]: 40
7845 12:14:32.886382 [Byte1]: 40
7846 12:14:32.891056
7847 12:14:32.891133 Set Vref, RX VrefLevel [Byte0]: 41
7848 12:14:32.894311 [Byte1]: 41
7849 12:14:32.898270
7850 12:14:32.898357 Set Vref, RX VrefLevel [Byte0]: 42
7851 12:14:32.902222 [Byte1]: 42
7852 12:14:32.906256
7853 12:14:32.906339 Set Vref, RX VrefLevel [Byte0]: 43
7854 12:14:32.909630 [Byte1]: 43
7855 12:14:32.913564
7856 12:14:32.913648 Set Vref, RX VrefLevel [Byte0]: 44
7857 12:14:32.916867 [Byte1]: 44
7858 12:14:32.921456
7859 12:14:32.921567 Set Vref, RX VrefLevel [Byte0]: 45
7860 12:14:32.924730 [Byte1]: 45
7861 12:14:32.928760
7862 12:14:32.928865 Set Vref, RX VrefLevel [Byte0]: 46
7863 12:14:32.932097 [Byte1]: 46
7864 12:14:32.936832
7865 12:14:32.936945 Set Vref, RX VrefLevel [Byte0]: 47
7866 12:14:32.940103 [Byte1]: 47
7867 12:14:32.944110
7868 12:14:32.944219 Set Vref, RX VrefLevel [Byte0]: 48
7869 12:14:32.947535 [Byte1]: 48
7870 12:14:32.951565
7871 12:14:32.951669 Set Vref, RX VrefLevel [Byte0]: 49
7872 12:14:32.954807 [Byte1]: 49
7873 12:14:32.959495
7874 12:14:32.959618 Set Vref, RX VrefLevel [Byte0]: 50
7875 12:14:32.962650 [Byte1]: 50
7876 12:14:32.967315
7877 12:14:32.967459 Set Vref, RX VrefLevel [Byte0]: 51
7878 12:14:32.970600 [Byte1]: 51
7879 12:14:32.974523
7880 12:14:32.974629 Set Vref, RX VrefLevel [Byte0]: 52
7881 12:14:32.977817 [Byte1]: 52
7882 12:14:32.982345
7883 12:14:32.982442 Set Vref, RX VrefLevel [Byte0]: 53
7884 12:14:32.985539 [Byte1]: 53
7885 12:14:32.990119
7886 12:14:32.990275 Set Vref, RX VrefLevel [Byte0]: 54
7887 12:14:32.993401 [Byte1]: 54
7888 12:14:32.997476
7889 12:14:32.997632 Set Vref, RX VrefLevel [Byte0]: 55
7890 12:14:33.000707 [Byte1]: 55
7891 12:14:33.005437
7892 12:14:33.005600 Set Vref, RX VrefLevel [Byte0]: 56
7893 12:14:33.008533 [Byte1]: 56
7894 12:14:33.012545
7895 12:14:33.012704 Set Vref, RX VrefLevel [Byte0]: 57
7896 12:14:33.015772 [Byte1]: 57
7897 12:14:33.020300
7898 12:14:33.020459 Set Vref, RX VrefLevel [Byte0]: 58
7899 12:14:33.023563 [Byte1]: 58
7900 12:14:33.028088
7901 12:14:33.028249 Set Vref, RX VrefLevel [Byte0]: 59
7902 12:14:33.031342 [Byte1]: 59
7903 12:14:33.035441
7904 12:14:33.035651 Set Vref, RX VrefLevel [Byte0]: 60
7905 12:14:33.038826 [Byte1]: 60
7906 12:14:33.043490
7907 12:14:33.043671 Set Vref, RX VrefLevel [Byte0]: 61
7908 12:14:33.046763 [Byte1]: 61
7909 12:14:33.050695
7910 12:14:33.050859 Set Vref, RX VrefLevel [Byte0]: 62
7911 12:14:33.053905 [Byte1]: 62
7912 12:14:33.058600
7913 12:14:33.058742 Set Vref, RX VrefLevel [Byte0]: 63
7914 12:14:33.061885 [Byte1]: 63
7915 12:14:33.065866
7916 12:14:33.065978 Set Vref, RX VrefLevel [Byte0]: 64
7917 12:14:33.069111 [Byte1]: 64
7918 12:14:33.073728
7919 12:14:33.073846 Set Vref, RX VrefLevel [Byte0]: 65
7920 12:14:33.076962 [Byte1]: 65
7921 12:14:33.081396
7922 12:14:33.081512 Set Vref, RX VrefLevel [Byte0]: 66
7923 12:14:33.084814 [Byte1]: 66
7924 12:14:33.089264
7925 12:14:33.089361 Set Vref, RX VrefLevel [Byte0]: 67
7926 12:14:33.092524 [Byte1]: 67
7927 12:14:33.096243
7928 12:14:33.096344 Set Vref, RX VrefLevel [Byte0]: 68
7929 12:14:33.099548 [Byte1]: 68
7930 12:14:33.104167
7931 12:14:33.104294 Set Vref, RX VrefLevel [Byte0]: 69
7932 12:14:33.107453 [Byte1]: 69
7933 12:14:33.111483
7934 12:14:33.111583 Set Vref, RX VrefLevel [Byte0]: 70
7935 12:14:33.114835 [Byte1]: 70
7936 12:14:33.119507
7937 12:14:33.119620 Set Vref, RX VrefLevel [Byte0]: 71
7938 12:14:33.122881 [Byte1]: 71
7939 12:14:33.126789
7940 12:14:33.126894 Set Vref, RX VrefLevel [Byte0]: 72
7941 12:14:33.130103 [Byte1]: 72
7942 12:14:33.134828
7943 12:14:33.134938 Set Vref, RX VrefLevel [Byte0]: 73
7944 12:14:33.137586 [Byte1]: 73
7945 12:14:33.142078
7946 12:14:33.142167 Set Vref, RX VrefLevel [Byte0]: 74
7947 12:14:33.145615 [Byte1]: 74
7948 12:14:33.149652
7949 12:14:33.149751 Set Vref, RX VrefLevel [Byte0]: 75
7950 12:14:33.153164 [Byte1]: 75
7951 12:14:33.157734
7952 12:14:33.157816 Set Vref, RX VrefLevel [Byte0]: 76
7953 12:14:33.160881 [Byte1]: 76
7954 12:14:33.164881
7955 12:14:33.164968 Set Vref, RX VrefLevel [Byte0]: 77
7956 12:14:33.168234 [Byte1]: 77
7957 12:14:33.172903
7958 12:14:33.173005 Final RX Vref Byte 0 = 60 to rank0
7959 12:14:33.176227 Final RX Vref Byte 1 = 60 to rank0
7960 12:14:33.179552 Final RX Vref Byte 0 = 60 to rank1
7961 12:14:33.182301 Final RX Vref Byte 1 = 60 to rank1==
7962 12:14:33.186160 Dram Type= 6, Freq= 0, CH_0, rank 0
7963 12:14:33.192834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 12:14:33.192920 ==
7965 12:14:33.193019 DQS Delay:
7966 12:14:33.193102 DQS0 = 0, DQS1 = 0
7967 12:14:33.196052 DQM Delay:
7968 12:14:33.196131 DQM0 = 129, DQM1 = 121
7969 12:14:33.199184 DQ Delay:
7970 12:14:33.202459 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7971 12:14:33.205829 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7972 12:14:33.209109 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7973 12:14:33.212490 DQ12 =126, DQ13 =126, DQ14 =130, DQ15 =132
7974 12:14:33.212570
7975 12:14:33.212666
7976 12:14:33.212746
7977 12:14:33.215734 [DramC_TX_OE_Calibration] TA2
7978 12:14:33.218934 Original DQ_B0 (3 6) =30, OEN = 27
7979 12:14:33.222825 Original DQ_B1 (3 6) =30, OEN = 27
7980 12:14:33.225874 24, 0x0, End_B0=24 End_B1=24
7981 12:14:33.225963 25, 0x0, End_B0=25 End_B1=25
7982 12:14:33.229185 26, 0x0, End_B0=26 End_B1=26
7983 12:14:33.232531 27, 0x0, End_B0=27 End_B1=27
7984 12:14:33.236312 28, 0x0, End_B0=28 End_B1=28
7985 12:14:33.236405 29, 0x0, End_B0=29 End_B1=29
7986 12:14:33.239569 30, 0x0, End_B0=30 End_B1=30
7987 12:14:33.242334 31, 0x4545, End_B0=30 End_B1=30
7988 12:14:33.245583 Byte0 end_step=30 best_step=27
7989 12:14:33.248913 Byte1 end_step=30 best_step=27
7990 12:14:33.252311 Byte0 TX OE(2T, 0.5T) = (3, 3)
7991 12:14:33.252417 Byte1 TX OE(2T, 0.5T) = (3, 3)
7992 12:14:33.255576
7993 12:14:33.255656
7994 12:14:33.262083 [DQSOSCAuto] RK0, (LSB)MR18= 0x1105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
7995 12:14:33.265534 CH0 RK0: MR19=303, MR18=1105
7996 12:14:33.272250 CH0_RK0: MR19=0x303, MR18=0x1105, DQSOSC=401, MR23=63, INC=22, DEC=15
7997 12:14:33.272341
7998 12:14:33.275480 ----->DramcWriteLeveling(PI) begin...
7999 12:14:33.275558 ==
8000 12:14:33.279337 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 12:14:33.282718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 12:14:33.282795 ==
8003 12:14:33.286059 Write leveling (Byte 0): 35 => 35
8004 12:14:33.289134 Write leveling (Byte 1): 24 => 24
8005 12:14:33.292406 DramcWriteLeveling(PI) end<-----
8006 12:14:33.292490
8007 12:14:33.292556 ==
8008 12:14:33.295705 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 12:14:33.298773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 12:14:33.298857 ==
8011 12:14:33.302677 [Gating] SW mode calibration
8012 12:14:33.309299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8013 12:14:33.315889 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8014 12:14:33.319134 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 12:14:33.322448 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 12:14:33.328989 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 12:14:33.332419 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8018 12:14:33.335674 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8019 12:14:33.342127 1 4 20 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
8020 12:14:33.345386 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8021 12:14:33.348854 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 12:14:33.355371 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 12:14:33.358713 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 12:14:33.362024 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8025 12:14:33.368600 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8026 12:14:33.371812 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8027 12:14:33.375705 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8028 12:14:33.382303 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 12:14:33.385658 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 12:14:33.388318 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 12:14:33.395359 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 12:14:33.398651 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8033 12:14:33.401912 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8034 12:14:33.408445 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8035 12:14:33.411565 1 6 20 | B1->B0 | 3433 4646 | 1 0 | (0 0) (0 0)
8036 12:14:33.414960 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 12:14:33.421616 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 12:14:33.425029 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 12:14:33.428578 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 12:14:33.435126 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8041 12:14:33.438429 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8042 12:14:33.441562 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8043 12:14:33.447904 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 12:14:33.451316 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8045 12:14:33.455121 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 12:14:33.457889 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 12:14:33.465017 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:14:33.468341 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:14:33.471634 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:14:33.478421 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:14:33.481747 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:14:33.485020 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:14:33.491604 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:14:33.494809 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:14:33.498035 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:14:33.504881 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 12:14:33.508348 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8058 12:14:33.511969 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8059 12:14:33.514963 Total UI for P1: 0, mck2ui 16
8060 12:14:33.518182 best dqsien dly found for B0: ( 1, 9, 10)
8061 12:14:33.524813 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8062 12:14:33.528614 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8063 12:14:33.531346 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 12:14:33.534716 Total UI for P1: 0, mck2ui 16
8065 12:14:33.537922 best dqsien dly found for B1: ( 1, 9, 22)
8066 12:14:33.541842 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8067 12:14:33.544971 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8068 12:14:33.545493
8069 12:14:33.551413 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8070 12:14:33.554491 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8071 12:14:33.557890 [Gating] SW calibration Done
8072 12:14:33.558465 ==
8073 12:14:33.561169 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:14:33.564511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:14:33.564970 ==
8076 12:14:33.565323 RX Vref Scan: 0
8077 12:14:33.565642
8078 12:14:33.567756 RX Vref 0 -> 0, step: 1
8079 12:14:33.568240
8080 12:14:33.571619 RX Delay 0 -> 252, step: 8
8081 12:14:33.574644 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8082 12:14:33.578055 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8083 12:14:33.584649 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8084 12:14:33.587835 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8085 12:14:33.591218 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8086 12:14:33.594394 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8087 12:14:33.597695 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8088 12:14:33.604137 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8089 12:14:33.607253 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8090 12:14:33.610920 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8091 12:14:33.614021 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8092 12:14:33.617364 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8093 12:14:33.624293 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8094 12:14:33.627494 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8095 12:14:33.630887 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8096 12:14:33.634245 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8097 12:14:33.634920 ==
8098 12:14:33.637587 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 12:14:33.644001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 12:14:33.644432 ==
8101 12:14:33.644778 DQS Delay:
8102 12:14:33.647397 DQS0 = 0, DQS1 = 0
8103 12:14:33.647906 DQM Delay:
8104 12:14:33.648294 DQM0 = 131, DQM1 = 125
8105 12:14:33.650658 DQ Delay:
8106 12:14:33.653904 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8107 12:14:33.657081 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8108 12:14:33.660351 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8109 12:14:33.663639 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8110 12:14:33.664151
8111 12:14:33.664574
8112 12:14:33.664960 ==
8113 12:14:33.666976 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 12:14:33.670853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 12:14:33.674310 ==
8116 12:14:33.674779
8117 12:14:33.675236
8118 12:14:33.675655 TX Vref Scan disable
8119 12:14:33.677388 == TX Byte 0 ==
8120 12:14:33.680685 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8121 12:14:33.683953 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8122 12:14:33.687195 == TX Byte 1 ==
8123 12:14:33.690587 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8124 12:14:33.696695 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8125 12:14:33.697313 ==
8126 12:14:33.700668 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 12:14:33.703229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 12:14:33.703715 ==
8129 12:14:33.718731
8130 12:14:33.721946 TX Vref early break, caculate TX vref
8131 12:14:33.725167 TX Vref=16, minBit 8, minWin=22, winSum=375
8132 12:14:33.728246 TX Vref=18, minBit 9, minWin=23, winSum=389
8133 12:14:33.732119 TX Vref=20, minBit 1, minWin=24, winSum=395
8134 12:14:33.735267 TX Vref=22, minBit 8, minWin=24, winSum=403
8135 12:14:33.738700 TX Vref=24, minBit 9, minWin=24, winSum=410
8136 12:14:33.745190 TX Vref=26, minBit 4, minWin=25, winSum=419
8137 12:14:33.747919 TX Vref=28, minBit 4, minWin=25, winSum=421
8138 12:14:33.751727 TX Vref=30, minBit 0, minWin=26, winSum=427
8139 12:14:33.755174 TX Vref=32, minBit 8, minWin=25, winSum=417
8140 12:14:33.758321 TX Vref=34, minBit 1, minWin=25, winSum=409
8141 12:14:33.761587 TX Vref=36, minBit 4, minWin=24, winSum=399
8142 12:14:33.768330 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
8143 12:14:33.768586
8144 12:14:33.771658 Final TX Range 0 Vref 30
8145 12:14:33.771892
8146 12:14:33.772074 ==
8147 12:14:33.774887 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 12:14:33.778294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 12:14:33.778518 ==
8150 12:14:33.778694
8151 12:14:33.781596
8152 12:14:33.781856 TX Vref Scan disable
8153 12:14:33.788214 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8154 12:14:33.788521 == TX Byte 0 ==
8155 12:14:33.791345 u2DelayCellOfst[0]=14 cells (4 PI)
8156 12:14:33.794676 u2DelayCellOfst[1]=21 cells (6 PI)
8157 12:14:33.798012 u2DelayCellOfst[2]=14 cells (4 PI)
8158 12:14:33.801396 u2DelayCellOfst[3]=14 cells (4 PI)
8159 12:14:33.804791 u2DelayCellOfst[4]=10 cells (3 PI)
8160 12:14:33.808097 u2DelayCellOfst[5]=0 cells (0 PI)
8161 12:14:33.811379 u2DelayCellOfst[6]=21 cells (6 PI)
8162 12:14:33.814102 u2DelayCellOfst[7]=21 cells (6 PI)
8163 12:14:33.817997 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8164 12:14:33.820636 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8165 12:14:33.824627 == TX Byte 1 ==
8166 12:14:33.827731 u2DelayCellOfst[8]=0 cells (0 PI)
8167 12:14:33.830918 u2DelayCellOfst[9]=0 cells (0 PI)
8168 12:14:33.834227 u2DelayCellOfst[10]=3 cells (1 PI)
8169 12:14:33.837350 u2DelayCellOfst[11]=0 cells (0 PI)
8170 12:14:33.837670 u2DelayCellOfst[12]=10 cells (3 PI)
8171 12:14:33.840670 u2DelayCellOfst[13]=10 cells (3 PI)
8172 12:14:33.844198 u2DelayCellOfst[14]=14 cells (4 PI)
8173 12:14:33.847402 u2DelayCellOfst[15]=10 cells (3 PI)
8174 12:14:33.854094 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8175 12:14:33.857385 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8176 12:14:33.857712 DramC Write-DBI on
8177 12:14:33.860912 ==
8178 12:14:33.863979 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 12:14:33.866981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 12:14:33.867064 ==
8181 12:14:33.867130
8182 12:14:33.867190
8183 12:14:33.870803 TX Vref Scan disable
8184 12:14:33.870885 == TX Byte 0 ==
8185 12:14:33.877272 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8186 12:14:33.877366 == TX Byte 1 ==
8187 12:14:33.880542 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8188 12:14:33.883783 DramC Write-DBI off
8189 12:14:33.883866
8190 12:14:33.883939 [DATLAT]
8191 12:14:33.887068 Freq=1600, CH0 RK1
8192 12:14:33.887150
8193 12:14:33.887215 DATLAT Default: 0xf
8194 12:14:33.890391 0, 0xFFFF, sum = 0
8195 12:14:33.890474 1, 0xFFFF, sum = 0
8196 12:14:33.893826 2, 0xFFFF, sum = 0
8197 12:14:33.893915 3, 0xFFFF, sum = 0
8198 12:14:33.897181 4, 0xFFFF, sum = 0
8199 12:14:33.897277 5, 0xFFFF, sum = 0
8200 12:14:33.900397 6, 0xFFFF, sum = 0
8201 12:14:33.900504 7, 0xFFFF, sum = 0
8202 12:14:33.903604 8, 0xFFFF, sum = 0
8203 12:14:33.906989 9, 0xFFFF, sum = 0
8204 12:14:33.907454 10, 0xFFFF, sum = 0
8205 12:14:33.911030 11, 0xFFFF, sum = 0
8206 12:14:33.911598 12, 0xFFFF, sum = 0
8207 12:14:33.914202 13, 0xFFFF, sum = 0
8208 12:14:33.914733 14, 0x0, sum = 1
8209 12:14:33.917178 15, 0x0, sum = 2
8210 12:14:33.917261 16, 0x0, sum = 3
8211 12:14:33.920445 17, 0x0, sum = 4
8212 12:14:33.920529 best_step = 15
8213 12:14:33.920594
8214 12:14:33.920655 ==
8215 12:14:33.923833 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 12:14:33.927139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 12:14:33.927228 ==
8218 12:14:33.930230 RX Vref Scan: 0
8219 12:14:33.930329
8220 12:14:33.933579 RX Vref 0 -> 0, step: 1
8221 12:14:33.933654
8222 12:14:33.933724 RX Delay 11 -> 252, step: 4
8223 12:14:33.941125 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8224 12:14:33.944138 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8225 12:14:33.947569 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8226 12:14:33.950772 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8227 12:14:33.954080 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8228 12:14:33.960673 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8229 12:14:33.963971 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8230 12:14:33.967196 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8231 12:14:33.970474 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8232 12:14:33.974458 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8233 12:14:33.980379 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8234 12:14:33.983877 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8235 12:14:33.987141 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8236 12:14:33.990402 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8237 12:14:33.997088 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8238 12:14:34.000411 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8239 12:14:34.000499 ==
8240 12:14:34.003730 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 12:14:34.007100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 12:14:34.007202 ==
8243 12:14:34.007295 DQS Delay:
8244 12:14:34.010406 DQS0 = 0, DQS1 = 0
8245 12:14:34.010511 DQM Delay:
8246 12:14:34.013576 DQM0 = 127, DQM1 = 122
8247 12:14:34.013656 DQ Delay:
8248 12:14:34.016920 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8249 12:14:34.020291 DQ4 =126, DQ5 =116, DQ6 =138, DQ7 =134
8250 12:14:34.024150 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8251 12:14:34.027439 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8252 12:14:34.030762
8253 12:14:34.030844
8254 12:14:34.030909
8255 12:14:34.030971 [DramC_TX_OE_Calibration] TA2
8256 12:14:34.033966 Original DQ_B0 (3 6) =30, OEN = 27
8257 12:14:34.037196 Original DQ_B1 (3 6) =30, OEN = 27
8258 12:14:34.040581 24, 0x0, End_B0=24 End_B1=24
8259 12:14:34.043784 25, 0x0, End_B0=25 End_B1=25
8260 12:14:34.046960 26, 0x0, End_B0=26 End_B1=26
8261 12:14:34.047045 27, 0x0, End_B0=27 End_B1=27
8262 12:14:34.050132 28, 0x0, End_B0=28 End_B1=28
8263 12:14:34.053466 29, 0x0, End_B0=29 End_B1=29
8264 12:14:34.056783 30, 0x0, End_B0=30 End_B1=30
8265 12:14:34.060119 31, 0x4141, End_B0=30 End_B1=30
8266 12:14:34.063469 Byte0 end_step=30 best_step=27
8267 12:14:34.063552 Byte1 end_step=30 best_step=27
8268 12:14:34.066759 Byte0 TX OE(2T, 0.5T) = (3, 3)
8269 12:14:34.070347 Byte1 TX OE(2T, 0.5T) = (3, 3)
8270 12:14:34.070434
8271 12:14:34.070501
8272 12:14:34.080152 [DQSOSCAuto] RK1, (LSB)MR18= 0x160b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8273 12:14:34.080247 CH0 RK1: MR19=303, MR18=160B
8274 12:14:34.086622 CH0_RK1: MR19=0x303, MR18=0x160B, DQSOSC=398, MR23=63, INC=23, DEC=15
8275 12:14:34.089912 [RxdqsGatingPostProcess] freq 1600
8276 12:14:34.096540 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8277 12:14:34.100021 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 12:14:34.103319 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 12:14:34.106650 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 12:14:34.106726 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 12:14:34.110433 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 12:14:34.113756 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 12:14:34.116496 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 12:14:34.119902 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 12:14:34.123204 Pre-setting of DQS Precalculation
8286 12:14:34.129875 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8287 12:14:34.129960 ==
8288 12:14:34.133775 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 12:14:34.136570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 12:14:34.136654 ==
8291 12:14:34.143663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 12:14:34.146844 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 12:14:34.150110 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 12:14:34.156765 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 12:14:34.165087 [CA 0] Center 42 (13~71) winsize 59
8296 12:14:34.168266 [CA 1] Center 42 (13~71) winsize 59
8297 12:14:34.171666 [CA 2] Center 37 (8~66) winsize 59
8298 12:14:34.175026 [CA 3] Center 36 (7~65) winsize 59
8299 12:14:34.178525 [CA 4] Center 37 (8~67) winsize 60
8300 12:14:34.181687 [CA 5] Center 36 (7~66) winsize 60
8301 12:14:34.181864
8302 12:14:34.184675 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8303 12:14:34.184854
8304 12:14:34.188526 [CATrainingPosCal] consider 1 rank data
8305 12:14:34.191753 u2DelayCellTimex100 = 275/100 ps
8306 12:14:34.195036 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8307 12:14:34.201562 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8308 12:14:34.204918 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8309 12:14:34.208269 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8310 12:14:34.211515 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8311 12:14:34.214781 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8312 12:14:34.215027
8313 12:14:34.218074 CA PerBit enable=1, Macro0, CA PI delay=36
8314 12:14:34.218319
8315 12:14:34.221375 [CBTSetCACLKResult] CA Dly = 36
8316 12:14:34.224856 CS Dly: 9 (0~40)
8317 12:14:34.228142 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 12:14:34.231535 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 12:14:34.231795 ==
8320 12:14:34.234736 Dram Type= 6, Freq= 0, CH_1, rank 1
8321 12:14:34.238148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 12:14:34.238407 ==
8323 12:14:34.244741 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 12:14:34.248159 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 12:14:34.254654 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 12:14:34.257759 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 12:14:34.268060 [CA 0] Center 43 (14~72) winsize 59
8328 12:14:34.271527 [CA 1] Center 43 (14~72) winsize 59
8329 12:14:34.274880 [CA 2] Center 37 (9~66) winsize 58
8330 12:14:34.278043 [CA 3] Center 37 (8~66) winsize 59
8331 12:14:34.281581 [CA 4] Center 37 (8~67) winsize 60
8332 12:14:34.284832 [CA 5] Center 36 (7~66) winsize 60
8333 12:14:34.285079
8334 12:14:34.288106 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8335 12:14:34.288282
8336 12:14:34.291196 [CATrainingPosCal] consider 2 rank data
8337 12:14:34.294442 u2DelayCellTimex100 = 275/100 ps
8338 12:14:34.301087 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8339 12:14:34.305140 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8340 12:14:34.308426 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8341 12:14:34.311791 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8342 12:14:34.314962 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8343 12:14:34.318150 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8344 12:14:34.318534
8345 12:14:34.321426 CA PerBit enable=1, Macro0, CA PI delay=36
8346 12:14:34.321821
8347 12:14:34.324650 [CBTSetCACLKResult] CA Dly = 36
8348 12:14:34.327919 CS Dly: 11 (0~44)
8349 12:14:34.331321 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 12:14:34.334476 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 12:14:34.335018
8352 12:14:34.337739 ----->DramcWriteLeveling(PI) begin...
8353 12:14:34.338444 ==
8354 12:14:34.341063 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 12:14:34.347477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 12:14:34.348106 ==
8357 12:14:34.350843 Write leveling (Byte 0): 25 => 25
8358 12:14:34.351470 Write leveling (Byte 1): 28 => 28
8359 12:14:34.354794 DramcWriteLeveling(PI) end<-----
8360 12:14:34.355223
8361 12:14:34.358075 ==
8362 12:14:34.358580 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 12:14:34.364592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 12:14:34.365079 ==
8365 12:14:34.367551 [Gating] SW mode calibration
8366 12:14:34.374081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8367 12:14:34.377454 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8368 12:14:34.384019 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 12:14:34.387889 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 12:14:34.390926 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:14:34.397389 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:14:34.400716 1 4 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
8373 12:14:34.403626 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
8374 12:14:34.410402 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 12:14:34.413751 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:14:34.416953 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:14:34.423543 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:14:34.426795 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:14:34.430126 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8380 12:14:34.436747 1 5 16 | B1->B0 | 2e2e 3333 | 1 0 | (1 0) (0 1)
8381 12:14:34.440038 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 12:14:34.443475 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 12:14:34.449962 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:14:34.453131 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:14:34.456569 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:14:34.463223 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:14:34.466481 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:14:34.470157 1 6 16 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (0 0)
8389 12:14:34.476708 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 12:14:34.479888 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 12:14:34.483086 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:14:34.489544 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:14:34.492786 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:14:34.496797 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:14:34.502776 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8396 12:14:34.506564 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8397 12:14:34.509344 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8398 12:14:34.516620 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8399 12:14:34.519872 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:14:34.523262 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:14:34.525907 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:14:34.532497 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:14:34.536532 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:14:34.539260 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:14:34.545738 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:14:34.549651 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:14:34.552835 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:14:34.559329 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:14:34.562621 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:14:34.565870 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:14:34.572832 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:14:34.575974 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8413 12:14:34.579171 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 12:14:34.582622 Total UI for P1: 0, mck2ui 16
8415 12:14:34.585935 best dqsien dly found for B0: ( 1, 9, 16)
8416 12:14:34.589252 Total UI for P1: 0, mck2ui 16
8417 12:14:34.592528 best dqsien dly found for B1: ( 1, 9, 16)
8418 12:14:34.595822 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8419 12:14:34.599222 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8420 12:14:34.599305
8421 12:14:34.605830 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8422 12:14:34.609011 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8423 12:14:34.612127 [Gating] SW calibration Done
8424 12:14:34.612209 ==
8425 12:14:34.615606 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:14:34.618894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:14:34.618977 ==
8428 12:14:34.619042 RX Vref Scan: 0
8429 12:14:34.622190
8430 12:14:34.622272 RX Vref 0 -> 0, step: 1
8431 12:14:34.622352
8432 12:14:34.625428 RX Delay 0 -> 252, step: 8
8433 12:14:34.628615 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8434 12:14:34.631925 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8435 12:14:34.638628 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8436 12:14:34.641926 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8437 12:14:34.645211 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8438 12:14:34.648559 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8439 12:14:34.651869 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8440 12:14:34.658392 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8441 12:14:34.662363 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8442 12:14:34.665650 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8443 12:14:34.668858 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8444 12:14:34.672226 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8445 12:14:34.678763 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8446 12:14:34.681975 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8447 12:14:34.685214 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8448 12:14:34.688562 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8449 12:14:34.688678 ==
8450 12:14:34.692091 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 12:14:34.698498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 12:14:34.698583 ==
8453 12:14:34.698670 DQS Delay:
8454 12:14:34.701744 DQS0 = 0, DQS1 = 0
8455 12:14:34.701821 DQM Delay:
8456 12:14:34.701890 DQM0 = 134, DQM1 = 127
8457 12:14:34.704986 DQ Delay:
8458 12:14:34.708316 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8459 12:14:34.711546 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8460 12:14:34.714844 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8461 12:14:34.718086 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8462 12:14:34.718169
8463 12:14:34.718255
8464 12:14:34.718337 ==
8465 12:14:34.721462 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 12:14:34.724671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 12:14:34.728041 ==
8468 12:14:34.728128
8469 12:14:34.728232
8470 12:14:34.728320 TX Vref Scan disable
8471 12:14:34.731345 == TX Byte 0 ==
8472 12:14:34.734792 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8473 12:14:34.738229 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 12:14:34.741421 == TX Byte 1 ==
8475 12:14:34.744807 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8476 12:14:34.748087 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8477 12:14:34.751462 ==
8478 12:14:34.754778 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 12:14:34.758062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 12:14:34.758155 ==
8481 12:14:34.770032
8482 12:14:34.773256 TX Vref early break, caculate TX vref
8483 12:14:34.776516 TX Vref=16, minBit 8, minWin=20, winSum=359
8484 12:14:34.779957 TX Vref=18, minBit 8, minWin=21, winSum=369
8485 12:14:34.783896 TX Vref=20, minBit 5, minWin=22, winSum=383
8486 12:14:34.787088 TX Vref=22, minBit 8, minWin=23, winSum=394
8487 12:14:34.790366 TX Vref=24, minBit 8, minWin=23, winSum=403
8488 12:14:34.796969 TX Vref=26, minBit 5, minWin=24, winSum=409
8489 12:14:34.800376 TX Vref=28, minBit 5, minWin=25, winSum=414
8490 12:14:34.803639 TX Vref=30, minBit 9, minWin=25, winSum=420
8491 12:14:34.806898 TX Vref=32, minBit 0, minWin=25, winSum=408
8492 12:14:34.810119 TX Vref=34, minBit 11, minWin=23, winSum=398
8493 12:14:34.816581 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 30
8494 12:14:34.816663
8495 12:14:34.819845 Final TX Range 0 Vref 30
8496 12:14:34.819923
8497 12:14:34.819984 ==
8498 12:14:34.823167 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 12:14:34.826687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 12:14:34.826825 ==
8501 12:14:34.826888
8502 12:14:34.826947
8503 12:14:34.829921 TX Vref Scan disable
8504 12:14:34.836525 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8505 12:14:34.836639 == TX Byte 0 ==
8506 12:14:34.839839 u2DelayCellOfst[0]=17 cells (5 PI)
8507 12:14:34.843237 u2DelayCellOfst[1]=14 cells (4 PI)
8508 12:14:34.846666 u2DelayCellOfst[2]=0 cells (0 PI)
8509 12:14:34.849935 u2DelayCellOfst[3]=7 cells (2 PI)
8510 12:14:34.853243 u2DelayCellOfst[4]=7 cells (2 PI)
8511 12:14:34.856529 u2DelayCellOfst[5]=17 cells (5 PI)
8512 12:14:34.859983 u2DelayCellOfst[6]=17 cells (5 PI)
8513 12:14:34.863269 u2DelayCellOfst[7]=7 cells (2 PI)
8514 12:14:34.866481 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8515 12:14:34.869952 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 12:14:34.873184 == TX Byte 1 ==
8517 12:14:34.873304 u2DelayCellOfst[8]=0 cells (0 PI)
8518 12:14:34.876526 u2DelayCellOfst[9]=7 cells (2 PI)
8519 12:14:34.879854 u2DelayCellOfst[10]=10 cells (3 PI)
8520 12:14:34.883074 u2DelayCellOfst[11]=7 cells (2 PI)
8521 12:14:34.886448 u2DelayCellOfst[12]=14 cells (4 PI)
8522 12:14:34.889681 u2DelayCellOfst[13]=17 cells (5 PI)
8523 12:14:34.892901 u2DelayCellOfst[14]=17 cells (5 PI)
8524 12:14:34.896149 u2DelayCellOfst[15]=17 cells (5 PI)
8525 12:14:34.899334 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8526 12:14:34.905884 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8527 12:14:34.905968 DramC Write-DBI on
8528 12:14:34.906035 ==
8529 12:14:34.909141 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 12:14:34.912977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 12:14:34.916278 ==
8532 12:14:34.916353
8533 12:14:34.916417
8534 12:14:34.916477 TX Vref Scan disable
8535 12:14:34.919383 == TX Byte 0 ==
8536 12:14:34.923212 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8537 12:14:34.926494 == TX Byte 1 ==
8538 12:14:34.929555 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8539 12:14:34.932869 DramC Write-DBI off
8540 12:14:34.932952
8541 12:14:34.933017 [DATLAT]
8542 12:14:34.933078 Freq=1600, CH1 RK0
8543 12:14:34.933137
8544 12:14:34.936088 DATLAT Default: 0xf
8545 12:14:34.936170 0, 0xFFFF, sum = 0
8546 12:14:34.939300 1, 0xFFFF, sum = 0
8547 12:14:34.939410 2, 0xFFFF, sum = 0
8548 12:14:34.942684 3, 0xFFFF, sum = 0
8549 12:14:34.946001 4, 0xFFFF, sum = 0
8550 12:14:34.946085 5, 0xFFFF, sum = 0
8551 12:14:34.949273 6, 0xFFFF, sum = 0
8552 12:14:34.949357 7, 0xFFFF, sum = 0
8553 12:14:34.952536 8, 0xFFFF, sum = 0
8554 12:14:34.952619 9, 0xFFFF, sum = 0
8555 12:14:34.955899 10, 0xFFFF, sum = 0
8556 12:14:34.955982 11, 0xFFFF, sum = 0
8557 12:14:34.959108 12, 0xFFFF, sum = 0
8558 12:14:34.959192 13, 0xFFFF, sum = 0
8559 12:14:34.963033 14, 0x0, sum = 1
8560 12:14:34.963116 15, 0x0, sum = 2
8561 12:14:34.966366 16, 0x0, sum = 3
8562 12:14:34.966449 17, 0x0, sum = 4
8563 12:14:34.969817 best_step = 15
8564 12:14:34.969898
8565 12:14:34.969964 ==
8566 12:14:34.972462 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 12:14:34.976016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 12:14:34.976102 ==
8569 12:14:34.976169 RX Vref Scan: 1
8570 12:14:34.979891
8571 12:14:34.979976 Set Vref Range= 24 -> 127
8572 12:14:34.980043
8573 12:14:34.983068 RX Vref 24 -> 127, step: 1
8574 12:14:34.983222
8575 12:14:34.985822 RX Delay 11 -> 252, step: 4
8576 12:14:34.985947
8577 12:14:34.989163 Set Vref, RX VrefLevel [Byte0]: 24
8578 12:14:34.992415 [Byte1]: 24
8579 12:14:34.992515
8580 12:14:34.996190 Set Vref, RX VrefLevel [Byte0]: 25
8581 12:14:34.999477 [Byte1]: 25
8582 12:14:34.999613
8583 12:14:35.002488 Set Vref, RX VrefLevel [Byte0]: 26
8584 12:14:35.005615 [Byte1]: 26
8585 12:14:35.010215
8586 12:14:35.010333 Set Vref, RX VrefLevel [Byte0]: 27
8587 12:14:35.013510 [Byte1]: 27
8588 12:14:35.017577
8589 12:14:35.017683 Set Vref, RX VrefLevel [Byte0]: 28
8590 12:14:35.020767 [Byte1]: 28
8591 12:14:35.025231
8592 12:14:35.025350 Set Vref, RX VrefLevel [Byte0]: 29
8593 12:14:35.028436 [Byte1]: 29
8594 12:14:35.032743
8595 12:14:35.032842 Set Vref, RX VrefLevel [Byte0]: 30
8596 12:14:35.035928 [Byte1]: 30
8597 12:14:35.040530
8598 12:14:35.040619 Set Vref, RX VrefLevel [Byte0]: 31
8599 12:14:35.046424 [Byte1]: 31
8600 12:14:35.046568
8601 12:14:35.049817 Set Vref, RX VrefLevel [Byte0]: 32
8602 12:14:35.053104 [Byte1]: 32
8603 12:14:35.053204
8604 12:14:35.056498 Set Vref, RX VrefLevel [Byte0]: 33
8605 12:14:35.059838 [Byte1]: 33
8606 12:14:35.063178
8607 12:14:35.063276 Set Vref, RX VrefLevel [Byte0]: 34
8608 12:14:35.066661 [Byte1]: 34
8609 12:14:35.070549
8610 12:14:35.070664 Set Vref, RX VrefLevel [Byte0]: 35
8611 12:14:35.073869 [Byte1]: 35
8612 12:14:35.078589
8613 12:14:35.078702 Set Vref, RX VrefLevel [Byte0]: 36
8614 12:14:35.081832 [Byte1]: 36
8615 12:14:35.085915
8616 12:14:35.086035 Set Vref, RX VrefLevel [Byte0]: 37
8617 12:14:35.089176 [Byte1]: 37
8618 12:14:35.093819
8619 12:14:35.093924 Set Vref, RX VrefLevel [Byte0]: 38
8620 12:14:35.097071 [Byte1]: 38
8621 12:14:35.101475
8622 12:14:35.101578 Set Vref, RX VrefLevel [Byte0]: 39
8623 12:14:35.104884 [Byte1]: 39
8624 12:14:35.108500
8625 12:14:35.108607 Set Vref, RX VrefLevel [Byte0]: 40
8626 12:14:35.112421 [Byte1]: 40
8627 12:14:35.116450
8628 12:14:35.116556 Set Vref, RX VrefLevel [Byte0]: 41
8629 12:14:35.119841 [Byte1]: 41
8630 12:14:35.123841
8631 12:14:35.123918 Set Vref, RX VrefLevel [Byte0]: 42
8632 12:14:35.127779 [Byte1]: 42
8633 12:14:35.131627
8634 12:14:35.131713 Set Vref, RX VrefLevel [Byte0]: 43
8635 12:14:35.134911 [Byte1]: 43
8636 12:14:35.139571
8637 12:14:35.139690 Set Vref, RX VrefLevel [Byte0]: 44
8638 12:14:35.145441 [Byte1]: 44
8639 12:14:35.145550
8640 12:14:35.148879 Set Vref, RX VrefLevel [Byte0]: 45
8641 12:14:35.152214 [Byte1]: 45
8642 12:14:35.152325
8643 12:14:35.155522 Set Vref, RX VrefLevel [Byte0]: 46
8644 12:14:35.158923 [Byte1]: 46
8645 12:14:35.162250
8646 12:14:35.162365 Set Vref, RX VrefLevel [Byte0]: 47
8647 12:14:35.165737 [Byte1]: 47
8648 12:14:35.169704
8649 12:14:35.169816 Set Vref, RX VrefLevel [Byte0]: 48
8650 12:14:35.173021 [Byte1]: 48
8651 12:14:35.177654
8652 12:14:35.177740 Set Vref, RX VrefLevel [Byte0]: 49
8653 12:14:35.180804 [Byte1]: 49
8654 12:14:35.184722
8655 12:14:35.184835 Set Vref, RX VrefLevel [Byte0]: 50
8656 12:14:35.187986 [Byte1]: 50
8657 12:14:35.192717
8658 12:14:35.192825 Set Vref, RX VrefLevel [Byte0]: 51
8659 12:14:35.195975 [Byte1]: 51
8660 12:14:35.199922
8661 12:14:35.199999 Set Vref, RX VrefLevel [Byte0]: 52
8662 12:14:35.203745 [Byte1]: 52
8663 12:14:35.207488
8664 12:14:35.207588 Set Vref, RX VrefLevel [Byte0]: 53
8665 12:14:35.211151 [Byte1]: 53
8666 12:14:35.215793
8667 12:14:35.215904 Set Vref, RX VrefLevel [Byte0]: 54
8668 12:14:35.218409 [Byte1]: 54
8669 12:14:35.223077
8670 12:14:35.223177 Set Vref, RX VrefLevel [Byte0]: 55
8671 12:14:35.226393 [Byte1]: 55
8672 12:14:35.230925
8673 12:14:35.231035 Set Vref, RX VrefLevel [Byte0]: 56
8674 12:14:35.234239 [Byte1]: 56
8675 12:14:35.238585
8676 12:14:35.238687 Set Vref, RX VrefLevel [Byte0]: 57
8677 12:14:35.241848 [Byte1]: 57
8678 12:14:35.245658
8679 12:14:35.245760 Set Vref, RX VrefLevel [Byte0]: 58
8680 12:14:35.249409 [Byte1]: 58
8681 12:14:35.253334
8682 12:14:35.253434 Set Vref, RX VrefLevel [Byte0]: 59
8683 12:14:35.256559 [Byte1]: 59
8684 12:14:35.261303
8685 12:14:35.261403 Set Vref, RX VrefLevel [Byte0]: 60
8686 12:14:35.264615 [Byte1]: 60
8687 12:14:35.268566
8688 12:14:35.268672 Set Vref, RX VrefLevel [Byte0]: 61
8689 12:14:35.271923 [Byte1]: 61
8690 12:14:35.276591
8691 12:14:35.276672 Set Vref, RX VrefLevel [Byte0]: 62
8692 12:14:35.279789 [Byte1]: 62
8693 12:14:35.283664
8694 12:14:35.283742 Set Vref, RX VrefLevel [Byte0]: 63
8695 12:14:35.286963 [Byte1]: 63
8696 12:14:35.291540
8697 12:14:35.291613 Set Vref, RX VrefLevel [Byte0]: 64
8698 12:14:35.294880 [Byte1]: 64
8699 12:14:35.298934
8700 12:14:35.299017 Set Vref, RX VrefLevel [Byte0]: 65
8701 12:14:35.302225 [Byte1]: 65
8702 12:14:35.306830
8703 12:14:35.306913 Set Vref, RX VrefLevel [Byte0]: 66
8704 12:14:35.309875 [Byte1]: 66
8705 12:14:35.314440
8706 12:14:35.314523 Set Vref, RX VrefLevel [Byte0]: 67
8707 12:14:35.317581 [Byte1]: 67
8708 12:14:35.322201
8709 12:14:35.322284 Set Vref, RX VrefLevel [Byte0]: 68
8710 12:14:35.325487 [Byte1]: 68
8711 12:14:35.329413
8712 12:14:35.329497 Set Vref, RX VrefLevel [Byte0]: 69
8713 12:14:35.332722 [Byte1]: 69
8714 12:14:35.337204
8715 12:14:35.337288 Set Vref, RX VrefLevel [Byte0]: 70
8716 12:14:35.340371 [Byte1]: 70
8717 12:14:35.344886
8718 12:14:35.344969 Set Vref, RX VrefLevel [Byte0]: 71
8719 12:14:35.348113 [Byte1]: 71
8720 12:14:35.352627
8721 12:14:35.352710 Set Vref, RX VrefLevel [Byte0]: 72
8722 12:14:35.355947 [Byte1]: 72
8723 12:14:35.359776
8724 12:14:35.359859 Set Vref, RX VrefLevel [Byte0]: 73
8725 12:14:35.363154 [Byte1]: 73
8726 12:14:35.367714
8727 12:14:35.367803 Final RX Vref Byte 0 = 57 to rank0
8728 12:14:35.371021 Final RX Vref Byte 1 = 54 to rank0
8729 12:14:35.374423 Final RX Vref Byte 0 = 57 to rank1
8730 12:14:35.377795 Final RX Vref Byte 1 = 54 to rank1==
8731 12:14:35.381093 Dram Type= 6, Freq= 0, CH_1, rank 0
8732 12:14:35.387774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8733 12:14:35.387936 ==
8734 12:14:35.388075 DQS Delay:
8735 12:14:35.390938 DQS0 = 0, DQS1 = 0
8736 12:14:35.391081 DQM Delay:
8737 12:14:35.391231 DQM0 = 131, DQM1 = 124
8738 12:14:35.394263 DQ Delay:
8739 12:14:35.397731 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8740 12:14:35.401020 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8741 12:14:35.404304 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =118
8742 12:14:35.407868 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8743 12:14:35.408293
8744 12:14:35.408627
8745 12:14:35.408945
8746 12:14:35.411151 [DramC_TX_OE_Calibration] TA2
8747 12:14:35.414195 Original DQ_B0 (3 6) =30, OEN = 27
8748 12:14:35.417937 Original DQ_B1 (3 6) =30, OEN = 27
8749 12:14:35.421075 24, 0x0, End_B0=24 End_B1=24
8750 12:14:35.421664 25, 0x0, End_B0=25 End_B1=25
8751 12:14:35.424153 26, 0x0, End_B0=26 End_B1=26
8752 12:14:35.427433 27, 0x0, End_B0=27 End_B1=27
8753 12:14:35.430873 28, 0x0, End_B0=28 End_B1=28
8754 12:14:35.434045 29, 0x0, End_B0=29 End_B1=29
8755 12:14:35.434668 30, 0x0, End_B0=30 End_B1=30
8756 12:14:35.437993 31, 0x4545, End_B0=30 End_B1=30
8757 12:14:35.441043 Byte0 end_step=30 best_step=27
8758 12:14:35.444348 Byte1 end_step=30 best_step=27
8759 12:14:35.447491 Byte0 TX OE(2T, 0.5T) = (3, 3)
8760 12:14:35.450844 Byte1 TX OE(2T, 0.5T) = (3, 3)
8761 12:14:35.451493
8762 12:14:35.451847
8763 12:14:35.457664 [DQSOSCAuto] RK0, (LSB)MR18= 0x15ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8764 12:14:35.460955 CH1 RK0: MR19=302, MR18=15FF
8765 12:14:35.467751 CH1_RK0: MR19=0x302, MR18=0x15FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8766 12:14:35.468175
8767 12:14:35.470872 ----->DramcWriteLeveling(PI) begin...
8768 12:14:35.471460 ==
8769 12:14:35.474019 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 12:14:35.477370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 12:14:35.477817 ==
8772 12:14:35.480580 Write leveling (Byte 0): 27 => 27
8773 12:14:35.483864 Write leveling (Byte 1): 28 => 28
8774 12:14:35.487152 DramcWriteLeveling(PI) end<-----
8775 12:14:35.487685
8776 12:14:35.488021 ==
8777 12:14:35.490348 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 12:14:35.493774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 12:14:35.494203 ==
8780 12:14:35.497087 [Gating] SW mode calibration
8781 12:14:35.503768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8782 12:14:35.510521 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8783 12:14:35.513841 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 12:14:35.520291 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 12:14:35.523464 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8786 12:14:35.526767 1 4 12 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
8787 12:14:35.533352 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 12:14:35.536550 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 12:14:35.540016 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 12:14:35.546490 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 12:14:35.549805 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 12:14:35.553496 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8793 12:14:35.559741 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
8794 12:14:35.563337 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8795 12:14:35.566574 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8796 12:14:35.573252 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 12:14:35.576663 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 12:14:35.579882 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 12:14:35.583205 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 12:14:35.589649 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8801 12:14:35.593573 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8802 12:14:35.596215 1 6 12 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
8803 12:14:35.602744 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 12:14:35.606580 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:14:35.609977 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 12:14:35.616659 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 12:14:35.619808 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:14:35.622910 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:14:35.629300 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8810 12:14:35.633007 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8811 12:14:35.636284 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8812 12:14:35.642844 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:14:35.646148 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:14:35.649487 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:14:35.655803 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:14:35.659191 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:14:35.663013 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:14:35.669464 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:14:35.672095 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:14:35.676122 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:14:35.682182 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:14:35.685354 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:14:35.688668 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:14:35.695810 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:14:35.699010 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8826 12:14:35.702326 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8827 12:14:35.705756 Total UI for P1: 0, mck2ui 16
8828 12:14:35.708976 best dqsien dly found for B0: ( 1, 9, 8)
8829 12:14:35.715570 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8830 12:14:35.718778 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 12:14:35.722061 Total UI for P1: 0, mck2ui 16
8832 12:14:35.725245 best dqsien dly found for B1: ( 1, 9, 14)
8833 12:14:35.728814 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8834 12:14:35.731947 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8835 12:14:35.732461
8836 12:14:35.735146 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8837 12:14:35.738150 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8838 12:14:35.742008 [Gating] SW calibration Done
8839 12:14:35.742456 ==
8840 12:14:35.745346 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 12:14:35.752045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 12:14:35.752572 ==
8843 12:14:35.752939 RX Vref Scan: 0
8844 12:14:35.753277
8845 12:14:35.755307 RX Vref 0 -> 0, step: 1
8846 12:14:35.755794
8847 12:14:35.758456 RX Delay 0 -> 252, step: 8
8848 12:14:35.761831 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8849 12:14:35.765003 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8850 12:14:35.768246 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8851 12:14:35.771315 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8852 12:14:35.778470 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8853 12:14:35.781643 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8854 12:14:35.784940 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8855 12:14:35.788208 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8856 12:14:35.791462 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8857 12:14:35.798491 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8858 12:14:35.801843 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8859 12:14:35.805034 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8860 12:14:35.808269 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8861 12:14:35.811482 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8862 12:14:35.818097 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8863 12:14:35.821380 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8864 12:14:35.821855 ==
8865 12:14:35.824706 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 12:14:35.828643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 12:14:35.829104 ==
8868 12:14:35.831892 DQS Delay:
8869 12:14:35.832352 DQS0 = 0, DQS1 = 0
8870 12:14:35.832709 DQM Delay:
8871 12:14:35.834962 DQM0 = 132, DQM1 = 128
8872 12:14:35.835462 DQ Delay:
8873 12:14:35.838097 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8874 12:14:35.841339 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8875 12:14:35.845188 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8876 12:14:35.851842 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8877 12:14:35.852318
8878 12:14:35.852774
8879 12:14:35.853116 ==
8880 12:14:35.854856 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 12:14:35.858137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 12:14:35.858213 ==
8883 12:14:35.858295
8884 12:14:35.858364
8885 12:14:35.861506 TX Vref Scan disable
8886 12:14:35.861588 == TX Byte 0 ==
8887 12:14:35.867904 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8888 12:14:35.871214 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8889 12:14:35.871322 == TX Byte 1 ==
8890 12:14:35.877626 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8891 12:14:35.880989 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8892 12:14:35.881071 ==
8893 12:14:35.884161 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 12:14:35.887596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 12:14:35.887682 ==
8896 12:14:35.902114
8897 12:14:35.905412 TX Vref early break, caculate TX vref
8898 12:14:35.909492 TX Vref=16, minBit 8, minWin=22, winSum=376
8899 12:14:35.912094 TX Vref=18, minBit 8, minWin=22, winSum=379
8900 12:14:35.915360 TX Vref=20, minBit 8, minWin=23, winSum=393
8901 12:14:35.918587 TX Vref=22, minBit 0, minWin=24, winSum=400
8902 12:14:35.921943 TX Vref=24, minBit 5, minWin=24, winSum=407
8903 12:14:35.929073 TX Vref=26, minBit 0, minWin=25, winSum=418
8904 12:14:35.932464 TX Vref=28, minBit 4, minWin=25, winSum=417
8905 12:14:35.935594 TX Vref=30, minBit 0, minWin=25, winSum=418
8906 12:14:35.938844 TX Vref=32, minBit 0, minWin=25, winSum=413
8907 12:14:35.942048 TX Vref=34, minBit 0, minWin=24, winSum=399
8908 12:14:35.945264 TX Vref=36, minBit 0, minWin=22, winSum=393
8909 12:14:35.952439 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8910 12:14:35.952551
8911 12:14:35.955738 Final TX Range 0 Vref 26
8912 12:14:35.955811
8913 12:14:35.955876 ==
8914 12:14:35.959080 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 12:14:35.962342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 12:14:35.962417 ==
8917 12:14:35.962480
8918 12:14:35.962538
8919 12:14:35.965677 TX Vref Scan disable
8920 12:14:35.971756 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8921 12:14:35.971830 == TX Byte 0 ==
8922 12:14:35.975590 u2DelayCellOfst[0]=17 cells (5 PI)
8923 12:14:35.978847 u2DelayCellOfst[1]=10 cells (3 PI)
8924 12:14:35.981942 u2DelayCellOfst[2]=0 cells (0 PI)
8925 12:14:35.985103 u2DelayCellOfst[3]=7 cells (2 PI)
8926 12:14:35.988884 u2DelayCellOfst[4]=7 cells (2 PI)
8927 12:14:35.992126 u2DelayCellOfst[5]=17 cells (5 PI)
8928 12:14:35.995444 u2DelayCellOfst[6]=17 cells (5 PI)
8929 12:14:35.998712 u2DelayCellOfst[7]=7 cells (2 PI)
8930 12:14:36.002019 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8931 12:14:36.005345 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8932 12:14:36.008608 == TX Byte 1 ==
8933 12:14:36.011925 u2DelayCellOfst[8]=0 cells (0 PI)
8934 12:14:36.011994 u2DelayCellOfst[9]=3 cells (1 PI)
8935 12:14:36.015122 u2DelayCellOfst[10]=10 cells (3 PI)
8936 12:14:36.018444 u2DelayCellOfst[11]=7 cells (2 PI)
8937 12:14:36.021784 u2DelayCellOfst[12]=14 cells (4 PI)
8938 12:14:36.024920 u2DelayCellOfst[13]=17 cells (5 PI)
8939 12:14:36.028841 u2DelayCellOfst[14]=17 cells (5 PI)
8940 12:14:36.032069 u2DelayCellOfst[15]=17 cells (5 PI)
8941 12:14:36.035318 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8942 12:14:36.041795 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8943 12:14:36.041870 DramC Write-DBI on
8944 12:14:36.041932 ==
8945 12:14:36.045036 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 12:14:36.051455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 12:14:36.051529 ==
8948 12:14:36.051592
8949 12:14:36.051649
8950 12:14:36.051709 TX Vref Scan disable
8951 12:14:36.055259 == TX Byte 0 ==
8952 12:14:36.058571 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8953 12:14:36.061983 == TX Byte 1 ==
8954 12:14:36.065247 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8955 12:14:36.068437 DramC Write-DBI off
8956 12:14:36.068505
8957 12:14:36.068566 [DATLAT]
8958 12:14:36.068623 Freq=1600, CH1 RK1
8959 12:14:36.068684
8960 12:14:36.072407 DATLAT Default: 0xf
8961 12:14:36.072473 0, 0xFFFF, sum = 0
8962 12:14:36.075737 1, 0xFFFF, sum = 0
8963 12:14:36.075803 2, 0xFFFF, sum = 0
8964 12:14:36.078989 3, 0xFFFF, sum = 0
8965 12:14:36.082063 4, 0xFFFF, sum = 0
8966 12:14:36.082141 5, 0xFFFF, sum = 0
8967 12:14:36.085296 6, 0xFFFF, sum = 0
8968 12:14:36.085372 7, 0xFFFF, sum = 0
8969 12:14:36.088500 8, 0xFFFF, sum = 0
8970 12:14:36.088579 9, 0xFFFF, sum = 0
8971 12:14:36.092289 10, 0xFFFF, sum = 0
8972 12:14:36.092360 11, 0xFFFF, sum = 0
8973 12:14:36.095579 12, 0xFFFF, sum = 0
8974 12:14:36.095650 13, 0xFFFF, sum = 0
8975 12:14:36.098922 14, 0x0, sum = 1
8976 12:14:36.099019 15, 0x0, sum = 2
8977 12:14:36.102171 16, 0x0, sum = 3
8978 12:14:36.102245 17, 0x0, sum = 4
8979 12:14:36.105462 best_step = 15
8980 12:14:36.105532
8981 12:14:36.105596 ==
8982 12:14:36.108759 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 12:14:36.112108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 12:14:36.112186 ==
8985 12:14:36.115337 RX Vref Scan: 0
8986 12:14:36.115449
8987 12:14:36.115512 RX Vref 0 -> 0, step: 1
8988 12:14:36.115570
8989 12:14:36.118670 RX Delay 11 -> 252, step: 4
8990 12:14:36.121948 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8991 12:14:36.128385 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8992 12:14:36.131563 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8993 12:14:36.135496 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8994 12:14:36.138863 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8995 12:14:36.141565 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8996 12:14:36.148816 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8997 12:14:36.151926 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8998 12:14:36.155172 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8999 12:14:36.158197 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9000 12:14:36.161565 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9001 12:14:36.168180 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9002 12:14:36.171529 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9003 12:14:36.174796 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9004 12:14:36.178089 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9005 12:14:36.182069 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9006 12:14:36.185153 ==
9007 12:14:36.188341 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 12:14:36.191966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 12:14:36.192056 ==
9010 12:14:36.192122 DQS Delay:
9011 12:14:36.195096 DQS0 = 0, DQS1 = 0
9012 12:14:36.195178 DQM Delay:
9013 12:14:36.198244 DQM0 = 129, DQM1 = 126
9014 12:14:36.198326 DQ Delay:
9015 12:14:36.201440 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9016 12:14:36.205331 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9017 12:14:36.208687 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9018 12:14:36.212048 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9019 12:14:36.212131
9020 12:14:36.212196
9021 12:14:36.212284
9022 12:14:36.215097 [DramC_TX_OE_Calibration] TA2
9023 12:14:36.218478 Original DQ_B0 (3 6) =30, OEN = 27
9024 12:14:36.221851 Original DQ_B1 (3 6) =30, OEN = 27
9025 12:14:36.225134 24, 0x0, End_B0=24 End_B1=24
9026 12:14:36.228518 25, 0x0, End_B0=25 End_B1=25
9027 12:14:36.228601 26, 0x0, End_B0=26 End_B1=26
9028 12:14:36.231201 27, 0x0, End_B0=27 End_B1=27
9029 12:14:36.235138 28, 0x0, End_B0=28 End_B1=28
9030 12:14:36.238344 29, 0x0, End_B0=29 End_B1=29
9031 12:14:36.241622 30, 0x0, End_B0=30 End_B1=30
9032 12:14:36.241707 31, 0x4545, End_B0=30 End_B1=30
9033 12:14:36.244891 Byte0 end_step=30 best_step=27
9034 12:14:36.248125 Byte1 end_step=30 best_step=27
9035 12:14:36.251520 Byte0 TX OE(2T, 0.5T) = (3, 3)
9036 12:14:36.254682 Byte1 TX OE(2T, 0.5T) = (3, 3)
9037 12:14:36.254764
9038 12:14:36.254829
9039 12:14:36.261136 [DQSOSCAuto] RK1, (LSB)MR18= 0x1218, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9040 12:14:36.265064 CH1 RK1: MR19=303, MR18=1218
9041 12:14:36.271566 CH1_RK1: MR19=0x303, MR18=0x1218, DQSOSC=397, MR23=63, INC=23, DEC=15
9042 12:14:36.274779 [RxdqsGatingPostProcess] freq 1600
9043 12:14:36.281267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9044 12:14:36.281365 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 12:14:36.284449 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 12:14:36.287719 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 12:14:36.291549 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 12:14:36.294769 best DQS0 dly(2T, 0.5T) = (1, 1)
9049 12:14:36.297928 best DQS1 dly(2T, 0.5T) = (1, 1)
9050 12:14:36.301213 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9051 12:14:36.304423 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9052 12:14:36.307629 Pre-setting of DQS Precalculation
9053 12:14:36.310906 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9054 12:14:36.321361 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9055 12:14:36.327985 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9056 12:14:36.328072
9057 12:14:36.328138
9058 12:14:36.331484 [Calibration Summary] 3200 Mbps
9059 12:14:36.331612 CH 0, Rank 0
9060 12:14:36.334057 SW Impedance : PASS
9061 12:14:36.334175 DUTY Scan : NO K
9062 12:14:36.337403 ZQ Calibration : PASS
9063 12:14:36.341247 Jitter Meter : NO K
9064 12:14:36.341374 CBT Training : PASS
9065 12:14:36.344485 Write leveling : PASS
9066 12:14:36.347928 RX DQS gating : PASS
9067 12:14:36.348043 RX DQ/DQS(RDDQC) : PASS
9068 12:14:36.350591 TX DQ/DQS : PASS
9069 12:14:36.353893 RX DATLAT : PASS
9070 12:14:36.353977 RX DQ/DQS(Engine): PASS
9071 12:14:36.357707 TX OE : PASS
9072 12:14:36.357791 All Pass.
9073 12:14:36.357887
9074 12:14:36.360836 CH 0, Rank 1
9075 12:14:36.360918 SW Impedance : PASS
9076 12:14:36.364084 DUTY Scan : NO K
9077 12:14:36.364166 ZQ Calibration : PASS
9078 12:14:36.367357 Jitter Meter : NO K
9079 12:14:36.370558 CBT Training : PASS
9080 12:14:36.370686 Write leveling : PASS
9081 12:14:36.373818 RX DQS gating : PASS
9082 12:14:36.377137 RX DQ/DQS(RDDQC) : PASS
9083 12:14:36.377258 TX DQ/DQS : PASS
9084 12:14:36.380367 RX DATLAT : PASS
9085 12:14:36.384265 RX DQ/DQS(Engine): PASS
9086 12:14:36.384340 TX OE : PASS
9087 12:14:36.387694 All Pass.
9088 12:14:36.387787
9089 12:14:36.387853 CH 1, Rank 0
9090 12:14:36.390293 SW Impedance : PASS
9091 12:14:36.390361 DUTY Scan : NO K
9092 12:14:36.394273 ZQ Calibration : PASS
9093 12:14:36.397424 Jitter Meter : NO K
9094 12:14:36.397508 CBT Training : PASS
9095 12:14:36.400765 Write leveling : PASS
9096 12:14:36.404026 RX DQS gating : PASS
9097 12:14:36.404111 RX DQ/DQS(RDDQC) : PASS
9098 12:14:36.407251 TX DQ/DQS : PASS
9099 12:14:36.410416 RX DATLAT : PASS
9100 12:14:36.410501 RX DQ/DQS(Engine): PASS
9101 12:14:36.413681 TX OE : PASS
9102 12:14:36.413757 All Pass.
9103 12:14:36.413824
9104 12:14:36.416922 CH 1, Rank 1
9105 12:14:36.416994 SW Impedance : PASS
9106 12:14:36.420186 DUTY Scan : NO K
9107 12:14:36.420270 ZQ Calibration : PASS
9108 12:14:36.423525 Jitter Meter : NO K
9109 12:14:36.426783 CBT Training : PASS
9110 12:14:36.426854 Write leveling : PASS
9111 12:14:36.430115 RX DQS gating : PASS
9112 12:14:36.433465 RX DQ/DQS(RDDQC) : PASS
9113 12:14:36.433548 TX DQ/DQS : PASS
9114 12:14:36.436795 RX DATLAT : PASS
9115 12:14:36.440555 RX DQ/DQS(Engine): PASS
9116 12:14:36.440631 TX OE : PASS
9117 12:14:36.443862 All Pass.
9118 12:14:36.443946
9119 12:14:36.444013 DramC Write-DBI on
9120 12:14:36.447181 PER_BANK_REFRESH: Hybrid Mode
9121 12:14:36.447266 TX_TRACKING: ON
9122 12:14:36.457097 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9123 12:14:36.466778 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9124 12:14:36.473205 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9125 12:14:36.476895 [FAST_K] Save calibration result to emmc
9126 12:14:36.480164 sync common calibartion params.
9127 12:14:36.480249 sync cbt_mode0:1, 1:1
9128 12:14:36.483540 dram_init: ddr_geometry: 2
9129 12:14:36.486730 dram_init: ddr_geometry: 2
9130 12:14:36.486814 dram_init: ddr_geometry: 2
9131 12:14:36.489908 0:dram_rank_size:100000000
9132 12:14:36.493373 1:dram_rank_size:100000000
9133 12:14:36.499983 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9134 12:14:36.500072 DFS_SHUFFLE_HW_MODE: ON
9135 12:14:36.503400 dramc_set_vcore_voltage set vcore to 725000
9136 12:14:36.506612 Read voltage for 1600, 0
9137 12:14:36.506696 Vio18 = 0
9138 12:14:36.509815 Vcore = 725000
9139 12:14:36.509899 Vdram = 0
9140 12:14:36.509965 Vddq = 0
9141 12:14:36.513181 Vmddr = 0
9142 12:14:36.513305 switch to 3200 Mbps bootup
9143 12:14:36.516371 [DramcRunTimeConfig]
9144 12:14:36.516488 PHYPLL
9145 12:14:36.519752 DPM_CONTROL_AFTERK: ON
9146 12:14:36.519835 PER_BANK_REFRESH: ON
9147 12:14:36.522971 REFRESH_OVERHEAD_REDUCTION: ON
9148 12:14:36.526832 CMD_PICG_NEW_MODE: OFF
9149 12:14:36.526933 XRTWTW_NEW_MODE: ON
9150 12:14:36.530091 XRTRTR_NEW_MODE: ON
9151 12:14:36.530174 TX_TRACKING: ON
9152 12:14:36.533454 RDSEL_TRACKING: OFF
9153 12:14:36.536186 DQS Precalculation for DVFS: ON
9154 12:14:36.536269 RX_TRACKING: OFF
9155 12:14:36.539427 HW_GATING DBG: ON
9156 12:14:36.539510 ZQCS_ENABLE_LP4: ON
9157 12:14:36.543382 RX_PICG_NEW_MODE: ON
9158 12:14:36.543466 TX_PICG_NEW_MODE: ON
9159 12:14:36.546528 ENABLE_RX_DCM_DPHY: ON
9160 12:14:36.549838 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9161 12:14:36.553113 DUMMY_READ_FOR_TRACKING: OFF
9162 12:14:36.553197 !!! SPM_CONTROL_AFTERK: OFF
9163 12:14:36.556517 !!! SPM could not control APHY
9164 12:14:36.559789 IMPEDANCE_TRACKING: ON
9165 12:14:36.559872 TEMP_SENSOR: ON
9166 12:14:36.563123 HW_SAVE_FOR_SR: OFF
9167 12:14:36.566451 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9168 12:14:36.569510 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9169 12:14:36.572678 Read ODT Tracking: ON
9170 12:14:36.572761 Refresh Rate DeBounce: ON
9171 12:14:36.576501 DFS_NO_QUEUE_FLUSH: ON
9172 12:14:36.579641 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9173 12:14:36.582851 ENABLE_DFS_RUNTIME_MRW: OFF
9174 12:14:36.582934 DDR_RESERVE_NEW_MODE: ON
9175 12:14:36.586161 MR_CBT_SWITCH_FREQ: ON
9176 12:14:36.589402 =========================
9177 12:14:36.606907 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9178 12:14:36.610081 dram_init: ddr_geometry: 2
9179 12:14:36.628334 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9180 12:14:36.632207 dram_init: dram init end (result: 0)
9181 12:14:36.638897 DRAM-K: Full calibration passed in 24601 msecs
9182 12:14:36.641638 MRC: failed to locate region type 0.
9183 12:14:36.641722 DRAM rank0 size:0x100000000,
9184 12:14:36.644853 DRAM rank1 size=0x100000000
9185 12:14:36.655245 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9186 12:14:36.661933 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9187 12:14:36.668525 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9188 12:14:36.674889 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9189 12:14:36.678176 DRAM rank0 size:0x100000000,
9190 12:14:36.681368 DRAM rank1 size=0x100000000
9191 12:14:36.681473 CBMEM:
9192 12:14:36.685246 IMD: root @ 0xfffff000 254 entries.
9193 12:14:36.688539 IMD: root @ 0xffffec00 62 entries.
9194 12:14:36.691794 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9195 12:14:36.695084 WARNING: RO_VPD is uninitialized or empty.
9196 12:14:36.701603 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9197 12:14:36.708774 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9198 12:14:36.720974 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9199 12:14:36.732625 BS: romstage times (exec / console): total (unknown) / 24101 ms
9200 12:14:36.732710
9201 12:14:36.732776
9202 12:14:36.742412 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9203 12:14:36.745770 ARM64: Exception handlers installed.
9204 12:14:36.749312 ARM64: Testing exception
9205 12:14:36.752515 ARM64: Done test exception
9206 12:14:36.752629 Enumerating buses...
9207 12:14:36.755794 Show all devs... Before device enumeration.
9208 12:14:36.759088 Root Device: enabled 1
9209 12:14:36.762436 CPU_CLUSTER: 0: enabled 1
9210 12:14:36.762520 CPU: 00: enabled 1
9211 12:14:36.765809 Compare with tree...
9212 12:14:36.765893 Root Device: enabled 1
9213 12:14:36.769063 CPU_CLUSTER: 0: enabled 1
9214 12:14:36.772572 CPU: 00: enabled 1
9215 12:14:36.772655 Root Device scanning...
9216 12:14:36.775704 scan_static_bus for Root Device
9217 12:14:36.779421 CPU_CLUSTER: 0 enabled
9218 12:14:36.782517 scan_static_bus for Root Device done
9219 12:14:36.785683 scan_bus: bus Root Device finished in 8 msecs
9220 12:14:36.785786 done
9221 12:14:36.792603 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9222 12:14:36.795879 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9223 12:14:36.802562 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9224 12:14:36.805765 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9225 12:14:36.809059 Allocating resources...
9226 12:14:36.812395 Reading resources...
9227 12:14:36.815620 Root Device read_resources bus 0 link: 0
9228 12:14:36.815693 DRAM rank0 size:0x100000000,
9229 12:14:36.818924 DRAM rank1 size=0x100000000
9230 12:14:36.822229 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9231 12:14:36.825491 CPU: 00 missing read_resources
9232 12:14:36.831789 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9233 12:14:36.835056 Root Device read_resources bus 0 link: 0 done
9234 12:14:36.835170 Done reading resources.
9235 12:14:36.841768 Show resources in subtree (Root Device)...After reading.
9236 12:14:36.845070 Root Device child on link 0 CPU_CLUSTER: 0
9237 12:14:36.848346 CPU_CLUSTER: 0 child on link 0 CPU: 00
9238 12:14:36.858116 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9239 12:14:36.858228 CPU: 00
9240 12:14:36.861432 Root Device assign_resources, bus 0 link: 0
9241 12:14:36.864833 CPU_CLUSTER: 0 missing set_resources
9242 12:14:36.871470 Root Device assign_resources, bus 0 link: 0 done
9243 12:14:36.871584 Done setting resources.
9244 12:14:36.878080 Show resources in subtree (Root Device)...After assigning values.
9245 12:14:36.881258 Root Device child on link 0 CPU_CLUSTER: 0
9246 12:14:36.885064 CPU_CLUSTER: 0 child on link 0 CPU: 00
9247 12:14:36.894571 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9248 12:14:36.894654 CPU: 00
9249 12:14:36.897793 Done allocating resources.
9250 12:14:36.905034 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9251 12:14:36.905118 Enabling resources...
9252 12:14:36.905183 done.
9253 12:14:36.911544 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9254 12:14:36.911630 Initializing devices...
9255 12:14:36.914950 Root Device init
9256 12:14:36.917597 init hardware done!
9257 12:14:36.917694 0x00000018: ctrlr->caps
9258 12:14:36.920931 52.000 MHz: ctrlr->f_max
9259 12:14:36.924888 0.400 MHz: ctrlr->f_min
9260 12:14:36.924971 0x40ff8080: ctrlr->voltages
9261 12:14:36.928085 sclk: 390625
9262 12:14:36.928181 Bus Width = 1
9263 12:14:36.928264 sclk: 390625
9264 12:14:36.931298 Bus Width = 1
9265 12:14:36.931399 Early init status = 3
9266 12:14:36.937741 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9267 12:14:36.941094 in-header: 03 fc 00 00 01 00 00 00
9268 12:14:36.944474 in-data: 00
9269 12:14:36.947702 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9270 12:14:36.951641 in-header: 03 fd 00 00 00 00 00 00
9271 12:14:36.954851 in-data:
9272 12:14:36.958030 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9273 12:14:36.961444 in-header: 03 fc 00 00 01 00 00 00
9274 12:14:36.964765 in-data: 00
9275 12:14:36.967936 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9276 12:14:36.973147 in-header: 03 fd 00 00 00 00 00 00
9277 12:14:36.976522 in-data:
9278 12:14:36.979842 [SSUSB] Setting up USB HOST controller...
9279 12:14:36.983122 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9280 12:14:36.986421 [SSUSB] phy power-on done.
9281 12:14:36.989563 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9282 12:14:36.995977 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9283 12:14:36.999727 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9284 12:14:37.006195 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9285 12:14:37.012657 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9286 12:14:37.019132 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9287 12:14:37.025710 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9288 12:14:37.032713 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9289 12:14:37.035767 SPM: binary array size = 0x9dc
9290 12:14:37.039367 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9291 12:14:37.045887 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9292 12:14:37.052551 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9293 12:14:37.059056 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9294 12:14:37.062340 configure_display: Starting display init
9295 12:14:37.096659 anx7625_power_on_init: Init interface.
9296 12:14:37.099806 anx7625_disable_pd_protocol: Disabled PD feature.
9297 12:14:37.102873 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9298 12:14:37.130969 anx7625_start_dp_work: Secure OCM version=00
9299 12:14:37.133693 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9300 12:14:37.149027 sp_tx_get_edid_block: EDID Block = 1
9301 12:14:37.251611 Extracted contents:
9302 12:14:37.254602 header: 00 ff ff ff ff ff ff 00
9303 12:14:37.257932 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9304 12:14:37.261134 version: 01 04
9305 12:14:37.264444 basic params: 95 1f 11 78 0a
9306 12:14:37.267923 chroma info: 76 90 94 55 54 90 27 21 50 54
9307 12:14:37.271240 established: 00 00 00
9308 12:14:37.277798 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9309 12:14:37.281138 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9310 12:14:37.287869 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9311 12:14:37.294422 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9312 12:14:37.301024 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9313 12:14:37.304275 extensions: 00
9314 12:14:37.304417 checksum: fb
9315 12:14:37.304543
9316 12:14:37.307449 Manufacturer: IVO Model 57d Serial Number 0
9317 12:14:37.310694 Made week 0 of 2020
9318 12:14:37.310801 EDID version: 1.4
9319 12:14:37.314513 Digital display
9320 12:14:37.317879 6 bits per primary color channel
9321 12:14:37.318009 DisplayPort interface
9322 12:14:37.321134 Maximum image size: 31 cm x 17 cm
9323 12:14:37.324438 Gamma: 220%
9324 12:14:37.324522 Check DPMS levels
9325 12:14:37.327645 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9326 12:14:37.334084 First detailed timing is preferred timing
9327 12:14:37.334169 Established timings supported:
9328 12:14:37.337464 Standard timings supported:
9329 12:14:37.340693 Detailed timings
9330 12:14:37.343862 Hex of detail: 383680a07038204018303c0035ae10000019
9331 12:14:37.347732 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9332 12:14:37.353958 0780 0798 07c8 0820 hborder 0
9333 12:14:37.357183 0438 043b 0447 0458 vborder 0
9334 12:14:37.361038 -hsync -vsync
9335 12:14:37.361122 Did detailed timing
9336 12:14:37.367529 Hex of detail: 000000000000000000000000000000000000
9337 12:14:37.367614 Manufacturer-specified data, tag 0
9338 12:14:37.374205 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9339 12:14:37.377556 ASCII string: InfoVision
9340 12:14:37.380902 Hex of detail: 000000fe00523134304e574635205248200a
9341 12:14:37.384131 ASCII string: R140NWF5 RH
9342 12:14:37.384215 Checksum
9343 12:14:37.387299 Checksum: 0xfb (valid)
9344 12:14:37.390589 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9345 12:14:37.393791 DSI data_rate: 832800000 bps
9346 12:14:37.400879 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9347 12:14:37.404067 anx7625_parse_edid: pixelclock(138800).
9348 12:14:37.407301 hactive(1920), hsync(48), hfp(24), hbp(88)
9349 12:14:37.410454 vactive(1080), vsync(12), vfp(3), vbp(17)
9350 12:14:37.413647 anx7625_dsi_config: config dsi.
9351 12:14:37.420860 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9352 12:14:37.433469 anx7625_dsi_config: success to config DSI
9353 12:14:37.436811 anx7625_dp_start: MIPI phy setup OK.
9354 12:14:37.440178 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9355 12:14:37.443390 mtk_ddp_mode_set invalid vrefresh 60
9356 12:14:37.446570 main_disp_path_setup
9357 12:14:37.446650 ovl_layer_smi_id_en
9358 12:14:37.449833 ovl_layer_smi_id_en
9359 12:14:37.449919 ccorr_config
9360 12:14:37.450003 aal_config
9361 12:14:37.453088 gamma_config
9362 12:14:37.453165 postmask_config
9363 12:14:37.456417 dither_config
9364 12:14:37.460324 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9365 12:14:37.466575 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9366 12:14:37.469900 Root Device init finished in 551 msecs
9367 12:14:37.469981 CPU_CLUSTER: 0 init
9368 12:14:37.479769 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9369 12:14:37.483074 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9370 12:14:37.486352 APU_MBOX 0x190000b0 = 0x10001
9371 12:14:37.489558 APU_MBOX 0x190001b0 = 0x10001
9372 12:14:37.492923 APU_MBOX 0x190005b0 = 0x10001
9373 12:14:37.496308 APU_MBOX 0x190006b0 = 0x10001
9374 12:14:37.499680 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9375 12:14:37.512662 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9376 12:14:37.524833 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9377 12:14:37.531230 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9378 12:14:37.543047 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9379 12:14:37.551966 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9380 12:14:37.555331 CPU_CLUSTER: 0 init finished in 81 msecs
9381 12:14:37.558673 Devices initialized
9382 12:14:37.561953 Show all devs... After init.
9383 12:14:37.562065 Root Device: enabled 1
9384 12:14:37.565037 CPU_CLUSTER: 0: enabled 1
9385 12:14:37.568828 CPU: 00: enabled 1
9386 12:14:37.572021 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9387 12:14:37.575411 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9388 12:14:37.578660 ELOG: NV offset 0x57f000 size 0x1000
9389 12:14:37.585312 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9390 12:14:37.591831 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9391 12:14:37.595120 ELOG: Event(17) added with size 13 at 2023-06-06 12:14:48 UTC
9392 12:14:37.601774 out: cmd=0x121: 03 db 21 01 00 00 00 00
9393 12:14:37.604992 in-header: 03 bc 00 00 2c 00 00 00
9394 12:14:37.614940 in-data: a3 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9395 12:14:37.621974 ELOG: Event(A1) added with size 10 at 2023-06-06 12:14:48 UTC
9396 12:14:37.628305 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9397 12:14:37.634578 ELOG: Event(A0) added with size 9 at 2023-06-06 12:14:48 UTC
9398 12:14:37.637892 elog_add_boot_reason: Logged dev mode boot
9399 12:14:37.645034 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9400 12:14:37.645120 Finalize devices...
9401 12:14:37.648354 Devices finalized
9402 12:14:37.651639 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9403 12:14:37.654899 Writing coreboot table at 0xffe64000
9404 12:14:37.658329 0. 000000000010a000-0000000000113fff: RAMSTAGE
9405 12:14:37.664878 1. 0000000040000000-00000000400fffff: RAM
9406 12:14:37.668118 2. 0000000040100000-000000004032afff: RAMSTAGE
9407 12:14:37.671131 3. 000000004032b000-00000000545fffff: RAM
9408 12:14:37.674423 4. 0000000054600000-000000005465ffff: BL31
9409 12:14:37.677634 5. 0000000054660000-00000000ffe63fff: RAM
9410 12:14:37.684910 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9411 12:14:37.688100 7. 0000000100000000-000000023fffffff: RAM
9412 12:14:37.691346 Passing 5 GPIOs to payload:
9413 12:14:37.694673 NAME | PORT | POLARITY | VALUE
9414 12:14:37.701253 EC in RW | 0x000000aa | low | undefined
9415 12:14:37.704575 EC interrupt | 0x00000005 | low | undefined
9416 12:14:37.707647 TPM interrupt | 0x000000ab | high | undefined
9417 12:14:37.714188 SD card detect | 0x00000011 | high | undefined
9418 12:14:37.718051 speaker enable | 0x00000093 | high | undefined
9419 12:14:37.721332 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9420 12:14:37.724587 in-header: 03 f9 00 00 02 00 00 00
9421 12:14:37.727821 in-data: 02 00
9422 12:14:37.730998 ADC[4]: Raw value=900221 ID=7
9423 12:14:37.731077 ADC[3]: Raw value=213336 ID=1
9424 12:14:37.734357 RAM Code: 0x71
9425 12:14:37.737387 ADC[6]: Raw value=74557 ID=0
9426 12:14:37.737472 ADC[5]: Raw value=212229 ID=1
9427 12:14:37.740688 SKU Code: 0x1
9428 12:14:37.747203 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9429 12:14:37.747316 coreboot table: 964 bytes.
9430 12:14:37.750563 IMD ROOT 0. 0xfffff000 0x00001000
9431 12:14:37.754488 IMD SMALL 1. 0xffffe000 0x00001000
9432 12:14:37.757802 RO MCACHE 2. 0xffffc000 0x00001104
9433 12:14:37.760506 CONSOLE 3. 0xfff7c000 0x00080000
9434 12:14:37.763855 FMAP 4. 0xfff7b000 0x00000452
9435 12:14:37.767652 TIME STAMP 5. 0xfff7a000 0x00000910
9436 12:14:37.771044 VBOOT WORK 6. 0xfff66000 0x00014000
9437 12:14:37.774135 RAMOOPS 7. 0xffe66000 0x00100000
9438 12:14:37.777438 COREBOOT 8. 0xffe64000 0x00002000
9439 12:14:37.780553 IMD small region:
9440 12:14:37.783983 IMD ROOT 0. 0xffffec00 0x00000400
9441 12:14:37.787248 VPD 1. 0xffffeba0 0x0000004c
9442 12:14:37.790540 MMC STATUS 2. 0xffffeb80 0x00000004
9443 12:14:37.793736 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9444 12:14:37.797095 Probing TPM: done!
9445 12:14:37.801005 Connected to device vid:did:rid of 1ae0:0028:00
9446 12:14:37.811510 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9447 12:14:37.814841 Initialized TPM device CR50 revision 0
9448 12:14:37.818183 Checking cr50 for pending updates
9449 12:14:37.822086 Reading cr50 TPM mode
9450 12:14:37.830706 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9451 12:14:37.837142 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9452 12:14:37.877639 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9453 12:14:37.880747 Checking segment from ROM address 0x40100000
9454 12:14:37.883969 Checking segment from ROM address 0x4010001c
9455 12:14:37.890684 Loading segment from ROM address 0x40100000
9456 12:14:37.890769 code (compression=0)
9457 12:14:37.900510 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9458 12:14:37.907736 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9459 12:14:37.907846 it's not compressed!
9460 12:14:37.914140 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9461 12:14:37.917427 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9462 12:14:37.938101 Loading segment from ROM address 0x4010001c
9463 12:14:37.938219 Entry Point 0x80000000
9464 12:14:37.941334 Loaded segments
9465 12:14:37.944605 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9466 12:14:37.951009 Jumping to boot code at 0x80000000(0xffe64000)
9467 12:14:37.958188 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9468 12:14:37.964645 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9469 12:14:37.972629 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9470 12:14:37.975871 Checking segment from ROM address 0x40100000
9471 12:14:37.979112 Checking segment from ROM address 0x4010001c
9472 12:14:37.985726 Loading segment from ROM address 0x40100000
9473 12:14:37.985812 code (compression=1)
9474 12:14:37.992871 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9475 12:14:38.002746 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9476 12:14:38.002828 using LZMA
9477 12:14:38.010573 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9478 12:14:38.017774 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9479 12:14:38.021064 Loading segment from ROM address 0x4010001c
9480 12:14:38.021147 Entry Point 0x54601000
9481 12:14:38.024320 Loaded segments
9482 12:14:38.027543 NOTICE: MT8192 bl31_setup
9483 12:14:38.034599 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9484 12:14:38.037850 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9485 12:14:38.041012 WARNING: region 0:
9486 12:14:38.044750 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 12:14:38.044855 WARNING: region 1:
9488 12:14:38.051081 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9489 12:14:38.054373 WARNING: region 2:
9490 12:14:38.057614 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9491 12:14:38.060842 WARNING: region 3:
9492 12:14:38.064082 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 12:14:38.068104 WARNING: region 4:
9494 12:14:38.074546 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 12:14:38.074629 WARNING: region 5:
9496 12:14:38.077772 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 12:14:38.081042 WARNING: region 6:
9498 12:14:38.084352 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 12:14:38.084435 WARNING: region 7:
9500 12:14:38.091373 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 12:14:38.097717 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9502 12:14:38.101052 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9503 12:14:38.104372 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9504 12:14:38.111488 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9505 12:14:38.114702 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9506 12:14:38.118039 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9507 12:14:38.124581 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9508 12:14:38.127731 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9509 12:14:38.130936 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9510 12:14:38.137600 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9511 12:14:38.141551 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9512 12:14:38.147732 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9513 12:14:38.150820 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9514 12:14:38.154591 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9515 12:14:38.161000 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9516 12:14:38.164360 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9517 12:14:38.168343 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9518 12:14:38.174435 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9519 12:14:38.178321 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9520 12:14:38.181525 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9521 12:14:38.187956 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9522 12:14:38.191143 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9523 12:14:38.197709 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9524 12:14:38.201032 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9525 12:14:38.204918 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9526 12:14:38.211325 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9527 12:14:38.214590 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9528 12:14:38.221123 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9529 12:14:38.224432 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9530 12:14:38.227805 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9531 12:14:38.234423 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9532 12:14:38.238247 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9533 12:14:38.241614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9534 12:14:38.248165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9535 12:14:38.251500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9536 12:14:38.254599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9537 12:14:38.257832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9538 12:14:38.264696 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9539 12:14:38.267849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9540 12:14:38.271077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9541 12:14:38.274440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9542 12:14:38.281104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9543 12:14:38.284396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9544 12:14:38.287615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9545 12:14:38.290912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9546 12:14:38.297553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9547 12:14:38.301468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9548 12:14:38.304668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9549 12:14:38.311244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9550 12:14:38.314442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9551 12:14:38.321088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9552 12:14:38.324378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9553 12:14:38.327745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9554 12:14:38.334384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9555 12:14:38.337584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9556 12:14:38.344123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9557 12:14:38.347444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9558 12:14:38.354021 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9559 12:14:38.357866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9560 12:14:38.361094 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9561 12:14:38.367564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9562 12:14:38.371396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9563 12:14:38.377896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9564 12:14:38.381175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9565 12:14:38.387766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9566 12:14:38.390938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9567 12:14:38.394197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9568 12:14:38.400900 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9569 12:14:38.404037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9570 12:14:38.411111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9571 12:14:38.414393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9572 12:14:38.420912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9573 12:14:38.424088 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9574 12:14:38.427518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9575 12:14:38.434123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9576 12:14:38.437354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9577 12:14:38.443946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9578 12:14:38.447245 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9579 12:14:38.454410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9580 12:14:38.457712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9581 12:14:38.464379 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9582 12:14:38.467669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9583 12:14:38.470849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9584 12:14:38.477841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9585 12:14:38.481066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9586 12:14:38.487490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9587 12:14:38.490944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9588 12:14:38.497628 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9589 12:14:38.500950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9590 12:14:38.504276 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9591 12:14:38.510735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9592 12:14:38.514074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9593 12:14:38.520586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9594 12:14:38.523866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9595 12:14:38.530978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9596 12:14:38.534279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9597 12:14:38.537459 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9598 12:14:38.543980 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9599 12:14:38.547342 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9600 12:14:38.550771 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9601 12:14:38.554004 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9602 12:14:38.560495 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9603 12:14:38.564421 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9604 12:14:38.570878 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9605 12:14:38.574101 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9606 12:14:38.577842 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9607 12:14:38.584144 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9608 12:14:38.587404 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9609 12:14:38.593830 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9610 12:14:38.597537 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9611 12:14:38.600791 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9612 12:14:38.607510 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9613 12:14:38.610888 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9614 12:14:38.614146 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9615 12:14:38.620583 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9616 12:14:38.623892 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9617 12:14:38.627123 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9618 12:14:38.634360 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9619 12:14:38.637622 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9620 12:14:38.641027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9621 12:14:38.647620 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9622 12:14:38.650831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9623 12:14:38.654076 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9624 12:14:38.657441 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9625 12:14:38.663999 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9626 12:14:38.667272 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9627 12:14:38.674393 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9628 12:14:38.677697 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9629 12:14:38.680729 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9630 12:14:38.687721 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9631 12:14:38.690269 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9632 12:14:38.694182 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9633 12:14:38.700560 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9634 12:14:38.703890 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9635 12:14:38.710554 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9636 12:14:38.713768 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9637 12:14:38.717049 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9638 12:14:38.724089 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9639 12:14:38.727368 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9640 12:14:38.733832 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9641 12:14:38.737058 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9642 12:14:38.740374 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9643 12:14:38.747119 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9644 12:14:38.750396 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9645 12:14:38.753733 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9646 12:14:38.760373 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9647 12:14:38.764165 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9648 12:14:38.770823 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9649 12:14:38.774149 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9650 12:14:38.777413 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9651 12:14:38.783793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9652 12:14:38.786886 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9653 12:14:38.793645 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9654 12:14:38.797505 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9655 12:14:38.800600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9656 12:14:38.806997 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9657 12:14:38.810280 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9658 12:14:38.816885 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9659 12:14:38.820103 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9660 12:14:38.823438 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9661 12:14:38.830441 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9662 12:14:38.833703 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9663 12:14:38.840278 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9664 12:14:38.843509 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9665 12:14:38.846773 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9666 12:14:38.853373 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9667 12:14:38.856659 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9668 12:14:38.860507 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9669 12:14:38.867273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9670 12:14:38.869985 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9671 12:14:38.876644 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9672 12:14:38.879965 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9673 12:14:38.883185 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9674 12:14:38.889735 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9675 12:14:38.893538 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9676 12:14:38.899979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9677 12:14:38.903291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9678 12:14:38.906465 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9679 12:14:38.913013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9680 12:14:38.916357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9681 12:14:38.923545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9682 12:14:38.926759 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9683 12:14:38.930034 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9684 12:14:38.936393 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9685 12:14:38.939656 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9686 12:14:38.946280 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9687 12:14:38.949523 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9688 12:14:38.952768 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9689 12:14:38.959500 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9690 12:14:38.962702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9691 12:14:38.969262 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9692 12:14:38.972532 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9693 12:14:38.976434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9694 12:14:38.982479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9695 12:14:38.985824 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9696 12:14:38.992859 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9697 12:14:38.995766 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9698 12:14:39.002636 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9699 12:14:39.005835 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9700 12:14:39.009018 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9701 12:14:39.015598 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9702 12:14:39.019539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9703 12:14:39.025941 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9704 12:14:39.029394 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9705 12:14:39.032744 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9706 12:14:39.039177 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9707 12:14:39.042479 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9708 12:14:39.049090 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9709 12:14:39.052429 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9710 12:14:39.058859 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9711 12:14:39.062218 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9712 12:14:39.065515 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9713 12:14:39.072019 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9714 12:14:39.075285 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9715 12:14:39.081966 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9716 12:14:39.085275 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9717 12:14:39.092276 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9718 12:14:39.095486 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9719 12:14:39.098798 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9720 12:14:39.105112 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9721 12:14:39.108849 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9722 12:14:39.115156 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9723 12:14:39.118466 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9724 12:14:39.121690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9725 12:14:39.128312 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9726 12:14:39.131632 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9727 12:14:39.138733 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9728 12:14:39.142022 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9729 12:14:39.145312 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9730 12:14:39.151826 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9731 12:14:39.155133 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9732 12:14:39.158485 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9733 12:14:39.161807 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9734 12:14:39.168506 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9735 12:14:39.171697 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9736 12:14:39.174912 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9737 12:14:39.181389 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9738 12:14:39.184748 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9739 12:14:39.188138 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9740 12:14:39.194628 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9741 12:14:39.198460 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9742 12:14:39.204847 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9743 12:14:39.208141 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9744 12:14:39.211334 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9745 12:14:39.218189 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9746 12:14:39.221432 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9747 12:14:39.224780 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9748 12:14:39.231336 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9749 12:14:39.234527 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9750 12:14:39.241094 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9751 12:14:39.244444 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9752 12:14:39.247762 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9753 12:14:39.254872 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9754 12:14:39.258197 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9755 12:14:39.261161 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9756 12:14:39.267694 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9757 12:14:39.271168 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9758 12:14:39.277560 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9759 12:14:39.280816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9760 12:14:39.284097 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9761 12:14:39.290810 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9762 12:14:39.294810 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9763 12:14:39.298072 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9764 12:14:39.304694 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9765 12:14:39.307851 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9766 12:14:39.311123 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9767 12:14:39.317848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9768 12:14:39.321029 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9769 12:14:39.324866 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9770 12:14:39.330812 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9771 12:14:39.334796 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9772 12:14:39.337917 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9773 12:14:39.341286 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9774 12:14:39.347939 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9775 12:14:39.351191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9776 12:14:39.354180 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9777 12:14:39.357478 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9778 12:14:39.364058 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9779 12:14:39.367550 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9780 12:14:39.370679 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9781 12:14:39.374030 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9782 12:14:39.380182 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9783 12:14:39.384074 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9784 12:14:39.390746 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9785 12:14:39.393991 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9786 12:14:39.397395 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9787 12:14:39.404115 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9788 12:14:39.407335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9789 12:14:39.413596 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9790 12:14:39.417471 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9791 12:14:39.420590 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9792 12:14:39.427210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9793 12:14:39.430461 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9794 12:14:39.437279 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9795 12:14:39.440592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9796 12:14:39.443572 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9797 12:14:39.450240 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9798 12:14:39.453585 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9799 12:14:39.460570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9800 12:14:39.463850 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9801 12:14:39.470539 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9802 12:14:39.473893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9803 12:14:39.477275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9804 12:14:39.483989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9805 12:14:39.487228 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9806 12:14:39.490485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9807 12:14:39.497197 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9808 12:14:39.500438 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9809 12:14:39.507041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9810 12:14:39.510601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9811 12:14:39.517079 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9812 12:14:39.520232 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9813 12:14:39.523435 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9814 12:14:39.530203 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9815 12:14:39.533999 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9816 12:14:39.539953 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9817 12:14:39.543845 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9818 12:14:39.547154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9819 12:14:39.553733 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9820 12:14:39.556904 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9821 12:14:39.563546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9822 12:14:39.566685 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9823 12:14:39.569926 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9824 12:14:39.576517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9825 12:14:39.579876 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9826 12:14:39.586287 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9827 12:14:39.590174 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9828 12:14:39.596462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9829 12:14:39.600238 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9830 12:14:39.603520 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9831 12:14:39.610123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9832 12:14:39.613301 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9833 12:14:39.619820 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9834 12:14:39.622995 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9835 12:14:39.626577 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9836 12:14:39.633071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9837 12:14:39.636276 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9838 12:14:39.643122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9839 12:14:39.646347 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9840 12:14:39.649522 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9841 12:14:39.656186 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9842 12:14:39.659472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9843 12:14:39.666102 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9844 12:14:39.669972 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9845 12:14:39.676576 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9846 12:14:39.679244 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9847 12:14:39.682585 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9848 12:14:39.689721 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9849 12:14:39.692963 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9850 12:14:39.699624 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9851 12:14:39.702942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9852 12:14:39.706050 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9853 12:14:39.712717 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9854 12:14:39.715938 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9855 12:14:39.722456 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9856 12:14:39.725718 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9857 12:14:39.729363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9858 12:14:39.735687 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9859 12:14:39.739028 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9860 12:14:39.745926 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9861 12:14:39.748963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9862 12:14:39.755451 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9863 12:14:39.758652 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9864 12:14:39.765171 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9865 12:14:39.768579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9866 12:14:39.771795 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9867 12:14:39.778338 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9868 12:14:39.781665 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9869 12:14:39.788666 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9870 12:14:39.791878 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9871 12:14:39.798345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9872 12:14:39.801676 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9873 12:14:39.804957 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9874 12:14:39.811624 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9875 12:14:39.814893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9876 12:14:39.821458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9877 12:14:39.825375 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9878 12:14:39.831896 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9879 12:14:39.834903 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9880 12:14:39.838585 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9881 12:14:39.844964 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9882 12:14:39.848571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9883 12:14:39.855083 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9884 12:14:39.858371 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9885 12:14:39.865168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9886 12:14:39.868530 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9887 12:14:39.871896 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9888 12:14:39.878427 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9889 12:14:39.881538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9890 12:14:39.888064 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9891 12:14:39.891278 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9892 12:14:39.897898 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9893 12:14:39.901145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9894 12:14:39.908345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9895 12:14:39.911486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9896 12:14:39.914818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9897 12:14:39.921526 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9898 12:14:39.924759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9899 12:14:39.931519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9900 12:14:39.934680 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9901 12:14:39.941438 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9902 12:14:39.944545 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9903 12:14:39.947898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9904 12:14:39.954350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9905 12:14:39.957491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9906 12:14:39.964623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9907 12:14:39.968049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9908 12:14:39.974683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9909 12:14:39.977803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9910 12:14:39.984391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9911 12:14:39.987472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9912 12:14:39.994080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9913 12:14:39.997494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9914 12:14:40.004539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9915 12:14:40.007895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9916 12:14:40.014493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9917 12:14:40.017671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9918 12:14:40.020892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9919 12:14:40.027545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9920 12:14:40.030999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9921 12:14:40.037406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9922 12:14:40.040652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9923 12:14:40.047506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9924 12:14:40.051214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9925 12:14:40.057785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9926 12:14:40.060955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9927 12:14:40.067379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9928 12:14:40.070848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9929 12:14:40.078039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9930 12:14:40.081410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9931 12:14:40.087418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9932 12:14:40.091385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9933 12:14:40.097685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9934 12:14:40.100924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9935 12:14:40.107502 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9936 12:14:40.107928 INFO: [APUAPC] vio 0
9937 12:14:40.114786 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9938 12:14:40.117981 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9939 12:14:40.121241 INFO: [APUAPC] D0_APC_0: 0x400510
9940 12:14:40.124409 INFO: [APUAPC] D0_APC_1: 0x0
9941 12:14:40.127813 INFO: [APUAPC] D0_APC_2: 0x1540
9942 12:14:40.131046 INFO: [APUAPC] D0_APC_3: 0x0
9943 12:14:40.133949 INFO: [APUAPC] D1_APC_0: 0xffffffff
9944 12:14:40.137125 INFO: [APUAPC] D1_APC_1: 0xffffffff
9945 12:14:40.140457 INFO: [APUAPC] D1_APC_2: 0x3fffff
9946 12:14:40.143684 INFO: [APUAPC] D1_APC_3: 0x0
9947 12:14:40.147548 INFO: [APUAPC] D2_APC_0: 0xffffffff
9948 12:14:40.150644 INFO: [APUAPC] D2_APC_1: 0xffffffff
9949 12:14:40.153905 INFO: [APUAPC] D2_APC_2: 0x3fffff
9950 12:14:40.157171 INFO: [APUAPC] D2_APC_3: 0x0
9951 12:14:40.160497 INFO: [APUAPC] D3_APC_0: 0xffffffff
9952 12:14:40.163629 INFO: [APUAPC] D3_APC_1: 0xffffffff
9953 12:14:40.166898 INFO: [APUAPC] D3_APC_2: 0x3fffff
9954 12:14:40.170136 INFO: [APUAPC] D3_APC_3: 0x0
9955 12:14:40.173369 INFO: [APUAPC] D4_APC_0: 0xffffffff
9956 12:14:40.177142 INFO: [APUAPC] D4_APC_1: 0xffffffff
9957 12:14:40.180513 INFO: [APUAPC] D4_APC_2: 0x3fffff
9958 12:14:40.183773 INFO: [APUAPC] D4_APC_3: 0x0
9959 12:14:40.187041 INFO: [APUAPC] D5_APC_0: 0xffffffff
9960 12:14:40.190408 INFO: [APUAPC] D5_APC_1: 0xffffffff
9961 12:14:40.193742 INFO: [APUAPC] D5_APC_2: 0x3fffff
9962 12:14:40.193825 INFO: [APUAPC] D5_APC_3: 0x0
9963 12:14:40.200040 INFO: [APUAPC] D6_APC_0: 0xffffffff
9964 12:14:40.203291 INFO: [APUAPC] D6_APC_1: 0xffffffff
9965 12:14:40.206663 INFO: [APUAPC] D6_APC_2: 0x3fffff
9966 12:14:40.206746 INFO: [APUAPC] D6_APC_3: 0x0
9967 12:14:40.209804 INFO: [APUAPC] D7_APC_0: 0xffffffff
9968 12:14:40.213144 INFO: [APUAPC] D7_APC_1: 0xffffffff
9969 12:14:40.216288 INFO: [APUAPC] D7_APC_2: 0x3fffff
9970 12:14:40.219685 INFO: [APUAPC] D7_APC_3: 0x0
9971 12:14:40.222913 INFO: [APUAPC] D8_APC_0: 0xffffffff
9972 12:14:40.226157 INFO: [APUAPC] D8_APC_1: 0xffffffff
9973 12:14:40.230108 INFO: [APUAPC] D8_APC_2: 0x3fffff
9974 12:14:40.232840 INFO: [APUAPC] D8_APC_3: 0x0
9975 12:14:40.236822 INFO: [APUAPC] D9_APC_0: 0xffffffff
9976 12:14:40.239488 INFO: [APUAPC] D9_APC_1: 0xffffffff
9977 12:14:40.243396 INFO: [APUAPC] D9_APC_2: 0x3fffff
9978 12:14:40.245990 INFO: [APUAPC] D9_APC_3: 0x0
9979 12:14:40.249991 INFO: [APUAPC] D10_APC_0: 0xffffffff
9980 12:14:40.253170 INFO: [APUAPC] D10_APC_1: 0xffffffff
9981 12:14:40.256264 INFO: [APUAPC] D10_APC_2: 0x3fffff
9982 12:14:40.259396 INFO: [APUAPC] D10_APC_3: 0x0
9983 12:14:40.262657 INFO: [APUAPC] D11_APC_0: 0xffffffff
9984 12:14:40.266525 INFO: [APUAPC] D11_APC_1: 0xffffffff
9985 12:14:40.269767 INFO: [APUAPC] D11_APC_2: 0x3fffff
9986 12:14:40.272933 INFO: [APUAPC] D11_APC_3: 0x0
9987 12:14:40.276113 INFO: [APUAPC] D12_APC_0: 0xffffffff
9988 12:14:40.279498 INFO: [APUAPC] D12_APC_1: 0xffffffff
9989 12:14:40.282744 INFO: [APUAPC] D12_APC_2: 0x3fffff
9990 12:14:40.286001 INFO: [APUAPC] D12_APC_3: 0x0
9991 12:14:40.289389 INFO: [APUAPC] D13_APC_0: 0xffffffff
9992 12:14:40.292731 INFO: [APUAPC] D13_APC_1: 0xffffffff
9993 12:14:40.295958 INFO: [APUAPC] D13_APC_2: 0x3fffff
9994 12:14:40.299238 INFO: [APUAPC] D13_APC_3: 0x0
9995 12:14:40.303039 INFO: [APUAPC] D14_APC_0: 0xffffffff
9996 12:14:40.306400 INFO: [APUAPC] D14_APC_1: 0xffffffff
9997 12:14:40.309582 INFO: [APUAPC] D14_APC_2: 0x3fffff
9998 12:14:40.312923 INFO: [APUAPC] D14_APC_3: 0x0
9999 12:14:40.316192 INFO: [APUAPC] D15_APC_0: 0xffffffff
10000 12:14:40.319525 INFO: [APUAPC] D15_APC_1: 0xffffffff
10001 12:14:40.322664 INFO: [APUAPC] D15_APC_2: 0x3fffff
10002 12:14:40.325964 INFO: [APUAPC] D15_APC_3: 0x0
10003 12:14:40.329319 INFO: [APUAPC] APC_CON: 0x4
10004 12:14:40.332614 INFO: [NOCDAPC] D0_APC_0: 0x0
10005 12:14:40.336529 INFO: [NOCDAPC] D0_APC_1: 0x0
10006 12:14:40.339702 INFO: [NOCDAPC] D1_APC_0: 0x0
10007 12:14:40.343048 INFO: [NOCDAPC] D1_APC_1: 0xfff
10008 12:14:40.346437 INFO: [NOCDAPC] D2_APC_0: 0x0
10009 12:14:40.349002 INFO: [NOCDAPC] D2_APC_1: 0xfff
10010 12:14:40.349084 INFO: [NOCDAPC] D3_APC_0: 0x0
10011 12:14:40.352960 INFO: [NOCDAPC] D3_APC_1: 0xfff
10012 12:14:40.356041 INFO: [NOCDAPC] D4_APC_0: 0x0
10013 12:14:40.359162 INFO: [NOCDAPC] D4_APC_1: 0xfff
10014 12:14:40.362201 INFO: [NOCDAPC] D5_APC_0: 0x0
10015 12:14:40.366148 INFO: [NOCDAPC] D5_APC_1: 0xfff
10016 12:14:40.368813 INFO: [NOCDAPC] D6_APC_0: 0x0
10017 12:14:40.372544 INFO: [NOCDAPC] D6_APC_1: 0xfff
10018 12:14:40.375753 INFO: [NOCDAPC] D7_APC_0: 0x0
10019 12:14:40.379000 INFO: [NOCDAPC] D7_APC_1: 0xfff
10020 12:14:40.382193 INFO: [NOCDAPC] D8_APC_0: 0x0
10021 12:14:40.385522 INFO: [NOCDAPC] D8_APC_1: 0xfff
10022 12:14:40.385606 INFO: [NOCDAPC] D9_APC_0: 0x0
10023 12:14:40.388775 INFO: [NOCDAPC] D9_APC_1: 0xfff
10024 12:14:40.392659 INFO: [NOCDAPC] D10_APC_0: 0x0
10025 12:14:40.395925 INFO: [NOCDAPC] D10_APC_1: 0xfff
10026 12:14:40.399304 INFO: [NOCDAPC] D11_APC_0: 0x0
10027 12:14:40.402087 INFO: [NOCDAPC] D11_APC_1: 0xfff
10028 12:14:40.405322 INFO: [NOCDAPC] D12_APC_0: 0x0
10029 12:14:40.409173 INFO: [NOCDAPC] D12_APC_1: 0xfff
10030 12:14:40.412551 INFO: [NOCDAPC] D13_APC_0: 0x0
10031 12:14:40.415842 INFO: [NOCDAPC] D13_APC_1: 0xfff
10032 12:14:40.418976 INFO: [NOCDAPC] D14_APC_0: 0x0
10033 12:14:40.422304 INFO: [NOCDAPC] D14_APC_1: 0xfff
10034 12:14:40.425642 INFO: [NOCDAPC] D15_APC_0: 0x0
10035 12:14:40.428898 INFO: [NOCDAPC] D15_APC_1: 0xfff
10036 12:14:40.428980 INFO: [NOCDAPC] APC_CON: 0x4
10037 12:14:40.432198 INFO: [APUAPC] set_apusys_apc done
10038 12:14:40.435513 INFO: [DEVAPC] devapc_init done
10039 12:14:40.442058 INFO: GICv3 without legacy support detected.
10040 12:14:40.445411 INFO: ARM GICv3 driver initialized in EL3
10041 12:14:40.448707 INFO: Maximum SPI INTID supported: 639
10042 12:14:40.452449 INFO: BL31: Initializing runtime services
10043 12:14:40.459028 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10044 12:14:40.462214 INFO: SPM: enable CPC mode
10045 12:14:40.465356 INFO: mcdi ready for mcusys-off-idle and system suspend
10046 12:14:40.471720 INFO: BL31: Preparing for EL3 exit to normal world
10047 12:14:40.474949 INFO: Entry point address = 0x80000000
10048 12:14:40.475031 INFO: SPSR = 0x8
10049 12:14:40.482094
10050 12:14:40.482177
10051 12:14:40.482252
10052 12:14:40.485244 Starting depthcharge on Spherion...
10053 12:14:40.485369
10054 12:14:40.485483 Wipe memory regions:
10055 12:14:40.485643
10056 12:14:40.486498 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10057 12:14:40.486631 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10058 12:14:40.486744 Setting prompt string to ['asurada:']
10059 12:14:40.486852 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10060 12:14:40.488563 [0x00000040000000, 0x00000054600000)
10061 12:14:40.611159
10062 12:14:40.611302 [0x00000054660000, 0x00000080000000)
10063 12:14:40.872026
10064 12:14:40.872545 [0x000000821a7280, 0x000000ffe64000)
10065 12:14:41.616632
10066 12:14:41.616835 [0x00000100000000, 0x00000240000000)
10067 12:14:43.507084
10068 12:14:43.510406 Initializing XHCI USB controller at 0x11200000.
10069 12:14:44.549732
10070 12:14:44.553027 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10071 12:14:44.553577
10072 12:14:44.553982
10073 12:14:44.554343
10074 12:14:44.555078 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 12:14:44.656278 asurada: tftpboot 192.168.201.1 10605408/tftp-deploy-wio5u1tq/kernel/image.itb 10605408/tftp-deploy-wio5u1tq/kernel/cmdline
10077 12:14:44.656846 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 12:14:44.657326 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10079 12:14:44.661599 tftpboot 192.168.201.1 10605408/tftp-deploy-wio5u1tq/kernel/image.itp-deploy-wio5u1tq/kernel/cmdline
10080 12:14:44.662041
10081 12:14:44.662383 Waiting for link
10082 12:14:44.822283
10083 12:14:44.822774 R8152: Initializing
10084 12:14:44.823126
10085 12:14:44.824939 Version 6 (ocp_data = 5c30)
10086 12:14:44.825372
10087 12:14:44.828134 R8152: Done initializing
10088 12:14:44.828568
10089 12:14:44.828918 Adding net device
10090 12:14:46.696641
10091 12:14:46.696815 done.
10092 12:14:46.696913
10093 12:14:46.697013 MAC: 00:24:32:30:78:52
10094 12:14:46.697103
10095 12:14:46.699612 Sending DHCP discover... done.
10096 12:14:46.699689
10097 12:14:46.702920 Waiting for reply... done.
10098 12:14:46.702992
10099 12:14:46.706549 Sending DHCP request... done.
10100 12:14:46.706637
10101 12:14:46.706710 Waiting for reply... done.
10102 12:14:46.706776
10103 12:14:46.709809 My ip is 192.168.201.14
10104 12:14:46.709890
10105 12:14:46.712535 The DHCP server ip is 192.168.201.1
10106 12:14:46.712610
10107 12:14:46.716513 TFTP server IP predefined by user: 192.168.201.1
10108 12:14:46.716602
10109 12:14:46.722488 Bootfile predefined by user: 10605408/tftp-deploy-wio5u1tq/kernel/image.itb
10110 12:14:46.722574
10111 12:14:46.725776 Sending tftp read request... done.
10112 12:14:46.725854
10113 12:14:46.729115 Waiting for the transfer...
10114 12:14:46.729193
10115 12:14:47.354545 00000000 ################################################################
10116 12:14:47.355089
10117 12:14:48.009283 00080000 ################################################################
10118 12:14:48.009672
10119 12:14:48.585526 00100000 ################################################################
10120 12:14:48.585703
10121 12:14:49.142021 00180000 ################################################################
10122 12:14:49.142165
10123 12:14:49.678999 00200000 ################################################################
10124 12:14:49.679146
10125 12:14:50.280098 00280000 ################################################################
10126 12:14:50.280250
10127 12:14:50.843593 00300000 ################################################################
10128 12:14:50.843754
10129 12:14:51.394883 00380000 ################################################################
10130 12:14:51.395097
10131 12:14:51.938368 00400000 ################################################################
10132 12:14:51.938544
10133 12:14:52.485990 00480000 ################################################################
10134 12:14:52.486171
10135 12:14:53.025983 00500000 ################################################################
10136 12:14:53.026124
10137 12:14:53.564337 00580000 ################################################################
10138 12:14:53.564511
10139 12:14:54.114801 00600000 ################################################################
10140 12:14:54.114941
10141 12:14:54.675094 00680000 ################################################################
10142 12:14:54.675227
10143 12:14:55.257482 00700000 ################################################################
10144 12:14:55.257634
10145 12:14:55.800365 00780000 ################################################################
10146 12:14:55.800542
10147 12:14:56.359034 00800000 ################################################################
10148 12:14:56.359193
10149 12:14:56.909453 00880000 ################################################################
10150 12:14:56.909587
10151 12:14:57.444298 00900000 ################################################################
10152 12:14:57.444470
10153 12:14:58.001414 00980000 ################################################################
10154 12:14:58.001553
10155 12:14:58.565894 00a00000 ################################################################
10156 12:14:58.566039
10157 12:14:59.172834 00a80000 ################################################################
10158 12:14:59.173410
10159 12:14:59.766508 00b00000 ################################################################
10160 12:14:59.766964
10161 12:15:00.374132 00b80000 ################################################################
10162 12:15:00.374271
10163 12:15:00.922525 00c00000 ################################################################
10164 12:15:00.922665
10165 12:15:01.461098 00c80000 ################################################################
10166 12:15:01.461262
10167 12:15:01.996626 00d00000 ################################################################
10168 12:15:01.996765
10169 12:15:02.526212 00d80000 ################################################################
10170 12:15:02.526349
10171 12:15:03.059663 00e00000 ################################################################
10172 12:15:03.059855
10173 12:15:03.604863 00e80000 ################################################################
10174 12:15:03.605007
10175 12:15:04.133894 00f00000 ################################################################
10176 12:15:04.134041
10177 12:15:04.670492 00f80000 ################################################################
10178 12:15:04.670631
10179 12:15:05.224810 01000000 ################################################################
10180 12:15:05.224949
10181 12:15:05.770360 01080000 ################################################################
10182 12:15:05.770551
10183 12:15:06.304857 01100000 ################################################################
10184 12:15:06.305007
10185 12:15:06.850434 01180000 ################################################################
10186 12:15:06.850596
10187 12:15:07.393917 01200000 ################################################################
10188 12:15:07.394066
10189 12:15:07.923099 01280000 ################################################################
10190 12:15:07.923251
10191 12:15:08.474049 01300000 ################################################################
10192 12:15:08.474225
10193 12:15:09.002110 01380000 ################################################################
10194 12:15:09.002283
10195 12:15:09.531764 01400000 ################################################################
10196 12:15:09.531911
10197 12:15:10.061489 01480000 ################################################################
10198 12:15:10.061638
10199 12:15:10.587820 01500000 ################################################################
10200 12:15:10.587976
10201 12:15:11.128882 01580000 ################################################################
10202 12:15:11.129032
10203 12:15:11.668358 01600000 ################################################################
10204 12:15:11.668520
10205 12:15:12.205171 01680000 ################################################################
10206 12:15:12.205384
10207 12:15:12.743908 01700000 ################################################################
10208 12:15:12.744065
10209 12:15:13.270122 01780000 ################################################################
10210 12:15:13.270316
10211 12:15:13.837659 01800000 ################################################################
10212 12:15:13.837810
10213 12:15:14.375067 01880000 ################################################################
10214 12:15:14.375230
10215 12:15:14.917165 01900000 ################################################################
10216 12:15:14.917314
10217 12:15:15.456688 01980000 ################################################################
10218 12:15:15.456890
10219 12:15:15.986818 01a00000 ################################################################
10220 12:15:15.986991
10221 12:15:16.517167 01a80000 ################################################################
10222 12:15:16.517333
10223 12:15:17.050825 01b00000 ################################################################
10224 12:15:17.050994
10225 12:15:17.564054 01b80000 ################################################################
10226 12:15:17.564210
10227 12:15:18.079532 01c00000 ################################################################
10228 12:15:18.079685
10229 12:15:18.648034 01c80000 ################################################################
10230 12:15:18.648189
10231 12:15:19.171636 01d00000 ################################################################
10232 12:15:19.171791
10233 12:15:19.712620 01d80000 ################################################################
10234 12:15:19.712797
10235 12:15:20.270229 01e00000 ################################################################
10236 12:15:20.270404
10237 12:15:20.852201 01e80000 ################################################################
10238 12:15:20.852340
10239 12:15:21.379513 01f00000 ################################################################
10240 12:15:21.379663
10241 12:15:21.918799 01f80000 ################################################################
10242 12:15:21.918939
10243 12:15:22.461662 02000000 ################################################################
10244 12:15:22.461801
10245 12:15:22.993549 02080000 ################################################################
10246 12:15:22.993701
10247 12:15:23.522191 02100000 ################################################################
10248 12:15:23.522362
10249 12:15:24.054447 02180000 ################################################################
10250 12:15:24.054585
10251 12:15:24.595242 02200000 ################################################################
10252 12:15:24.595407
10253 12:15:25.147040 02280000 ################################################################
10254 12:15:25.147208
10255 12:15:25.687843 02300000 ################################################################
10256 12:15:25.687987
10257 12:15:26.277498 02380000 ################################################################
10258 12:15:26.277662
10259 12:15:26.813702 02400000 ################################################################
10260 12:15:26.813839
10261 12:15:27.358882 02480000 ################################################################
10262 12:15:27.359047
10263 12:15:27.930383 02500000 ################################################################
10264 12:15:27.930530
10265 12:15:28.474407 02580000 ################################################################
10266 12:15:28.474554
10267 12:15:28.997413 02600000 ################################################################
10268 12:15:28.997584
10269 12:15:29.522205 02680000 ################################################################
10270 12:15:29.522346
10271 12:15:30.060204 02700000 ################################################################
10272 12:15:30.060347
10273 12:15:30.626038 02780000 ################################################################
10274 12:15:30.626215
10275 12:15:31.223744 02800000 ################################################################
10276 12:15:31.223897
10277 12:15:31.765103 02880000 ################################################################
10278 12:15:31.765255
10279 12:15:32.303215 02900000 ################################################################
10280 12:15:32.303405
10281 12:15:32.828913 02980000 ################################################################
10282 12:15:32.829052
10283 12:15:33.371266 02a00000 ################################################################
10284 12:15:33.371425
10285 12:15:33.900386 02a80000 ################################################################
10286 12:15:33.900526
10287 12:15:34.443600 02b00000 ################################################################
10288 12:15:34.443769
10289 12:15:34.986852 02b80000 ################################################################
10290 12:15:34.987025
10291 12:15:35.529483 02c00000 ################################################################
10292 12:15:35.529632
10293 12:15:36.078870 02c80000 ################################################################
10294 12:15:36.079044
10295 12:15:36.620906 02d00000 ################################################################
10296 12:15:36.621055
10297 12:15:37.180573 02d80000 ################################################################
10298 12:15:37.180739
10299 12:15:37.730414 02e00000 ################################################################
10300 12:15:37.730570
10301 12:15:38.259094 02e80000 ################################################################
10302 12:15:38.259291
10303 12:15:38.794437 02f00000 ################################################################
10304 12:15:38.794623
10305 12:15:39.351246 02f80000 ################################################################
10306 12:15:39.351446
10307 12:15:39.892824 03000000 ################################################################
10308 12:15:39.892992
10309 12:15:40.428739 03080000 ################################################################
10310 12:15:40.428893
10311 12:15:40.983017 03100000 ################################################################
10312 12:15:40.983195
10313 12:15:41.514787 03180000 ################################################################
10314 12:15:41.514926
10315 12:15:42.028853 03200000 ################################################################
10316 12:15:42.029032
10317 12:15:42.552702 03280000 ################################################################
10318 12:15:42.552843
10319 12:15:43.068424 03300000 ################################################################
10320 12:15:43.068612
10321 12:15:43.605617 03380000 ################################################################
10322 12:15:43.605777
10323 12:15:44.126867 03400000 ################################################################
10324 12:15:44.127057
10325 12:15:44.647979 03480000 ################################################################
10326 12:15:44.648117
10327 12:15:45.179540 03500000 ################################################################
10328 12:15:45.179703
10329 12:15:45.707725 03580000 ################################################################
10330 12:15:45.707925
10331 12:15:46.250869 03600000 ################################################################
10332 12:15:46.251073
10333 12:15:46.807296 03680000 ################################################################
10334 12:15:46.807490
10335 12:15:47.346137 03700000 ################################################################
10336 12:15:47.346313
10337 12:15:47.887109 03780000 ################################################################
10338 12:15:47.887291
10339 12:15:48.427147 03800000 ################################################################
10340 12:15:48.427328
10341 12:15:49.006576 03880000 ################################################################
10342 12:15:49.006753
10343 12:15:49.558848 03900000 ################################################################
10344 12:15:49.559018
10345 12:15:50.104048 03980000 ################################################################
10346 12:15:50.104200
10347 12:15:50.649214 03a00000 ################################################################
10348 12:15:50.649417
10349 12:15:51.198333 03a80000 ################################################################
10350 12:15:51.198480
10351 12:15:51.779395 03b00000 ################################################################
10352 12:15:51.779548
10353 12:15:52.303157 03b80000 ################################################################
10354 12:15:52.303331
10355 12:15:52.846090 03c00000 ################################################################
10356 12:15:52.846236
10357 12:15:53.390357 03c80000 ################################################################
10358 12:15:53.390491
10359 12:15:53.931078 03d00000 ################################################################
10360 12:15:53.931240
10361 12:15:54.463187 03d80000 ################################################################
10362 12:15:54.463320
10363 12:15:54.988412 03e00000 ################################################################
10364 12:15:54.988581
10365 12:15:55.541700 03e80000 ################################################################
10366 12:15:55.541844
10367 12:15:56.036292 03f00000 ######################################################### done.
10368 12:15:56.036439
10369 12:15:56.039682 The bootfile was 66523542 bytes long.
10370 12:15:56.039792
10371 12:15:56.043048 Sending tftp read request... done.
10372 12:15:56.043150
10373 12:15:56.043220 Waiting for the transfer...
10374 12:15:56.043283
10375 12:15:56.046344 00000000 # done.
10376 12:15:56.046464
10377 12:15:56.053422 Command line loaded dynamically from TFTP file: 10605408/tftp-deploy-wio5u1tq/kernel/cmdline
10378 12:15:56.053555
10379 12:15:56.066108 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10380 12:15:56.066244
10381 12:15:56.066315 Loading FIT.
10382 12:15:56.066378
10383 12:15:56.069828 Image ramdisk-1 has 56379964 bytes.
10384 12:15:56.069917
10385 12:15:56.072895 Image fdt-1 has 46924 bytes.
10386 12:15:56.073030
10387 12:15:56.076502 Image kernel-1 has 10094623 bytes.
10388 12:15:56.076627
10389 12:15:56.083125 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10390 12:15:56.083256
10391 12:15:56.103161 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10392 12:15:56.103329
10393 12:15:56.106235 Choosing best match conf-1 for compat google,spherion-rev2.
10394 12:15:56.111256
10395 12:15:56.115963 Connected to device vid:did:rid of 1ae0:0028:00
10396 12:15:56.123235
10397 12:15:56.126164 tpm_get_response: command 0x17b, return code 0x0
10398 12:15:56.126266
10399 12:15:56.129469 ec_init: CrosEC protocol v3 supported (256, 248)
10400 12:15:56.133565
10401 12:15:56.136918 tpm_cleanup: add release locality here.
10402 12:15:56.137002
10403 12:15:56.140279 Shutting down all USB controllers.
10404 12:15:56.140363
10405 12:15:56.140430 Removing current net device
10406 12:15:56.140492
10407 12:15:56.146907 Exiting depthcharge with code 4 at timestamp: 105086359
10408 12:15:56.147017
10409 12:15:56.150302 LZMA decompressing kernel-1 to 0x821a6718
10410 12:15:56.150413
10411 12:15:56.153066 LZMA decompressing kernel-1 to 0x40000000
10412 12:15:57.421655
10413 12:15:57.421795 jumping to kernel
10414 12:15:57.422230 end: 2.2.4 bootloader-commands (duration 00:01:17) [common]
10415 12:15:57.422330 start: 2.2.5 auto-login-action (timeout 00:03:08) [common]
10416 12:15:57.422408 Setting prompt string to ['Linux version [0-9]']
10417 12:15:57.422477 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10418 12:15:57.422545 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10419 12:15:57.504784
10420 12:15:57.507464 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10421 12:15:57.511037 start: 2.2.5.1 login-action (timeout 00:03:08) [common]
10422 12:15:57.511178 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10423 12:15:57.511271 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10424 12:15:57.511358 Using line separator: #'\n'#
10425 12:15:57.511426 No login prompt set.
10426 12:15:57.511490 Parsing kernel messages
10427 12:15:57.511548 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10428 12:15:57.511651 [login-action] Waiting for messages, (timeout 00:03:08)
10429 12:15:57.530682 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10430 12:15:57.534226 [ 0.000000] random: crng init done
10431 12:15:57.537809 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10432 12:15:57.540943 [ 0.000000] efi: UEFI not found.
10433 12:15:57.550868 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10434 12:15:57.557536 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10435 12:15:57.567588 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10436 12:15:57.577617 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10437 12:15:57.583705 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10438 12:15:57.587569 [ 0.000000] printk: bootconsole [mtk8250] enabled
10439 12:15:57.595802 [ 0.000000] NUMA: No NUMA configuration found
10440 12:15:57.602707 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10441 12:15:57.609050 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10442 12:15:57.609142 [ 0.000000] Zone ranges:
10443 12:15:57.615703 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10444 12:15:57.619007 [ 0.000000] DMA32 empty
10445 12:15:57.625339 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10446 12:15:57.628662 [ 0.000000] Movable zone start for each node
10447 12:15:57.632013 [ 0.000000] Early memory node ranges
10448 12:15:57.638530 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10449 12:15:57.645571 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10450 12:15:57.652250 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10451 12:15:57.658976 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10452 12:15:57.665714 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10453 12:15:57.672351 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10454 12:15:57.728682 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10455 12:15:57.735310 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10456 12:15:57.741436 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10457 12:15:57.745301 [ 0.000000] psci: probing for conduit method from DT.
10458 12:15:57.751575 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10459 12:15:57.754867 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10460 12:15:57.761476 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10461 12:15:57.764782 [ 0.000000] psci: SMC Calling Convention v1.2
10462 12:15:57.771306 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10463 12:15:57.774522 [ 0.000000] Detected VIPT I-cache on CPU0
10464 12:15:57.781213 [ 0.000000] CPU features: detected: GIC system register CPU interface
10465 12:15:57.787890 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10466 12:15:57.794430 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10467 12:15:57.801072 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10468 12:15:57.811153 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10469 12:15:57.817525 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10470 12:15:57.820800 [ 0.000000] alternatives: applying boot alternatives
10471 12:15:57.828017 [ 0.000000] Fallback order for Node 0: 0
10472 12:15:57.834573 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10473 12:15:57.838000 [ 0.000000] Policy zone: Normal
10474 12:15:57.847948 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10475 12:15:57.860979 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10476 12:15:57.870860 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10477 12:15:57.877601 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10478 12:15:57.884083 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10479 12:15:57.890761 <6>[ 0.000000] software IO TLB: area num 8.
10480 12:15:57.945975 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10481 12:15:58.095469 <6>[ 0.000000] Memory: 7917884K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434884K reserved, 32768K cma-reserved)
10482 12:15:58.102151 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10483 12:15:58.108922 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10484 12:15:58.112262 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10485 12:15:58.118818 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10486 12:15:58.125048 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10487 12:15:58.128620 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10488 12:15:58.138083 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10489 12:15:58.145180 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10490 12:15:58.151344 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10491 12:15:58.158070 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10492 12:15:58.161238 <6>[ 0.000000] GICv3: 608 SPIs implemented
10493 12:15:58.164532 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10494 12:15:58.171580 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10495 12:15:58.174752 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10496 12:15:58.181354 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10497 12:15:58.194556 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10498 12:15:58.204568 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10499 12:15:58.214404 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10500 12:15:58.221865 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10501 12:15:58.235176 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10502 12:15:58.241518 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10503 12:15:58.248474 <6>[ 0.009174] Console: colour dummy device 80x25
10504 12:15:58.258500 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10505 12:15:58.264592 <6>[ 0.024411] pid_max: default: 32768 minimum: 301
10506 12:15:58.267860 <6>[ 0.029314] LSM: Security Framework initializing
10507 12:15:58.274518 <6>[ 0.034253] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10508 12:15:58.284901 <6>[ 0.042067] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10509 12:15:58.291401 <6>[ 0.051496] cblist_init_generic: Setting adjustable number of callback queues.
10510 12:15:58.298172 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10511 12:15:58.304891 <6>[ 0.065289] cblist_init_generic: Setting shift to 3 and lim to 1.
10512 12:15:58.311175 <6>[ 0.071697] rcu: Hierarchical SRCU implementation.
10513 12:15:58.317787 <6>[ 0.076710] rcu: Max phase no-delay instances is 1000.
10514 12:15:58.321138 <6>[ 0.083731] EFI services will not be available.
10515 12:15:58.327650 <6>[ 0.088702] smp: Bringing up secondary CPUs ...
10516 12:15:58.335110 <6>[ 0.093756] Detected VIPT I-cache on CPU1
10517 12:15:58.341601 <6>[ 0.093830] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10518 12:15:58.348559 <6>[ 0.093862] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10519 12:15:58.351861 <6>[ 0.094196] Detected VIPT I-cache on CPU2
10520 12:15:58.358578 <6>[ 0.094245] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10521 12:15:58.364883 <6>[ 0.094260] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10522 12:15:58.371541 <6>[ 0.094518] Detected VIPT I-cache on CPU3
10523 12:15:58.378280 <6>[ 0.094564] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10524 12:15:58.384541 <6>[ 0.094577] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10525 12:15:58.387887 <6>[ 0.094881] CPU features: detected: Spectre-v4
10526 12:15:58.394401 <6>[ 0.094886] CPU features: detected: Spectre-BHB
10527 12:15:58.397685 <6>[ 0.094891] Detected PIPT I-cache on CPU4
10528 12:15:58.404385 <6>[ 0.094942] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10529 12:15:58.411222 <6>[ 0.094957] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10530 12:15:58.418065 <6>[ 0.095234] Detected PIPT I-cache on CPU5
10531 12:15:58.424483 <6>[ 0.095289] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10532 12:15:58.431022 <6>[ 0.095305] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10533 12:15:58.434295 <6>[ 0.095588] Detected PIPT I-cache on CPU6
10534 12:15:58.441010 <6>[ 0.095653] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10535 12:15:58.447437 <6>[ 0.095669] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10536 12:15:58.454329 <6>[ 0.095966] Detected PIPT I-cache on CPU7
10537 12:15:58.461159 <6>[ 0.096030] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10538 12:15:58.467522 <6>[ 0.096046] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10539 12:15:58.470719 <6>[ 0.096093] smp: Brought up 1 node, 8 CPUs
10540 12:15:58.477831 <6>[ 0.237425] SMP: Total of 8 processors activated.
10541 12:15:58.480457 <6>[ 0.242346] CPU features: detected: 32-bit EL0 Support
10542 12:15:58.490721 <6>[ 0.247709] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10543 12:15:58.497341 <6>[ 0.256563] CPU features: detected: Common not Private translations
10544 12:15:58.503460 <6>[ 0.263039] CPU features: detected: CRC32 instructions
10545 12:15:58.507377 <6>[ 0.268390] CPU features: detected: RCpc load-acquire (LDAPR)
10546 12:15:58.513445 <6>[ 0.274349] CPU features: detected: LSE atomic instructions
10547 12:15:58.520182 <6>[ 0.280131] CPU features: detected: Privileged Access Never
10548 12:15:58.526910 <6>[ 0.285910] CPU features: detected: RAS Extension Support
10549 12:15:58.533409 <6>[ 0.291553] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10550 12:15:58.536849 <6>[ 0.298774] CPU: All CPU(s) started at EL2
10551 12:15:58.543421 <6>[ 0.303117] alternatives: applying system-wide alternatives
10552 12:15:58.552581 <6>[ 0.313869] devtmpfs: initialized
10553 12:15:58.564882 <6>[ 0.322722] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10554 12:15:58.574933 <6>[ 0.332683] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10555 12:15:58.581346 <6>[ 0.340698] pinctrl core: initialized pinctrl subsystem
10556 12:15:58.585141 <6>[ 0.347354] DMI not present or invalid.
10557 12:15:58.591852 <6>[ 0.351759] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10558 12:15:58.601396 <6>[ 0.358627] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10559 12:15:58.607950 <6>[ 0.366209] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10560 12:15:58.618123 <6>[ 0.374426] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10561 12:15:58.621322 <6>[ 0.382669] audit: initializing netlink subsys (disabled)
10562 12:15:58.630626 <5>[ 0.388363] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10563 12:15:58.637265 <6>[ 0.389076] thermal_sys: Registered thermal governor 'step_wise'
10564 12:15:58.644034 <6>[ 0.396327] thermal_sys: Registered thermal governor 'power_allocator'
10565 12:15:58.647226 <6>[ 0.402580] cpuidle: using governor menu
10566 12:15:58.653886 <6>[ 0.413535] NET: Registered PF_QIPCRTR protocol family
10567 12:15:58.660437 <6>[ 0.419010] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10568 12:15:58.667287 <6>[ 0.426115] ASID allocator initialised with 32768 entries
10569 12:15:58.670272 <6>[ 0.432700] Serial: AMBA PL011 UART driver
10570 12:15:58.680381 <4>[ 0.441380] Trying to register duplicate clock ID: 134
10571 12:15:58.734099 <6>[ 0.498562] KASLR enabled
10572 12:15:58.748453 <6>[ 0.506249] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10573 12:15:58.755454 <6>[ 0.513264] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10574 12:15:58.762168 <6>[ 0.519752] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10575 12:15:58.768886 <6>[ 0.526759] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10576 12:15:58.775005 <6>[ 0.533247] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10577 12:15:58.781644 <6>[ 0.540253] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10578 12:15:58.788156 <6>[ 0.546741] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10579 12:15:58.795242 <6>[ 0.553742] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10580 12:15:58.798496 <6>[ 0.561229] ACPI: Interpreter disabled.
10581 12:15:58.806874 <6>[ 0.567654] iommu: Default domain type: Translated
10582 12:15:58.813429 <6>[ 0.572769] iommu: DMA domain TLB invalidation policy: strict mode
10583 12:15:58.816700 <5>[ 0.579427] SCSI subsystem initialized
10584 12:15:58.823362 <6>[ 0.583665] usbcore: registered new interface driver usbfs
10585 12:15:58.830083 <6>[ 0.589393] usbcore: registered new interface driver hub
10586 12:15:58.833348 <6>[ 0.594943] usbcore: registered new device driver usb
10587 12:15:58.839998 <6>[ 0.601050] pps_core: LinuxPPS API ver. 1 registered
10588 12:15:58.850015 <6>[ 0.606246] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10589 12:15:58.853476 <6>[ 0.615585] PTP clock support registered
10590 12:15:58.856846 <6>[ 0.619825] EDAC MC: Ver: 3.0.0
10591 12:15:58.864082 <6>[ 0.625018] FPGA manager framework
10592 12:15:58.870627 <6>[ 0.628693] Advanced Linux Sound Architecture Driver Initialized.
10593 12:15:58.873933 <6>[ 0.635463] vgaarb: loaded
10594 12:15:58.880444 <6>[ 0.638624] clocksource: Switched to clocksource arch_sys_counter
10595 12:15:58.883700 <5>[ 0.645073] VFS: Disk quotas dquot_6.6.0
10596 12:15:58.890559 <6>[ 0.649258] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10597 12:15:58.893676 <6>[ 0.656451] pnp: PnP ACPI: disabled
10598 12:15:58.901949 <6>[ 0.663185] NET: Registered PF_INET protocol family
10599 12:15:58.912087 <6>[ 0.668789] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10600 12:15:58.923097 <6>[ 0.681090] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10601 12:15:58.933303 <6>[ 0.689906] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10602 12:15:58.939853 <6>[ 0.697878] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10603 12:15:58.949839 <6>[ 0.706575] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10604 12:15:58.956476 <6>[ 0.716286] TCP: Hash tables configured (established 65536 bind 65536)
10605 12:15:58.963152 <6>[ 0.723144] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10606 12:15:58.972975 <6>[ 0.730343] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10607 12:15:58.979534 <6>[ 0.738047] NET: Registered PF_UNIX/PF_LOCAL protocol family
10608 12:15:58.982872 <6>[ 0.744215] RPC: Registered named UNIX socket transport module.
10609 12:15:58.989288 <6>[ 0.750369] RPC: Registered udp transport module.
10610 12:15:58.992392 <6>[ 0.755302] RPC: Registered tcp transport module.
10611 12:15:58.999501 <6>[ 0.760236] RPC: Registered tcp NFSv4.1 backchannel transport module.
10612 12:15:59.005563 <6>[ 0.766904] PCI: CLS 0 bytes, default 64
10613 12:15:59.009325 <6>[ 0.771280] Unpacking initramfs...
10614 12:15:59.025439 <6>[ 0.783157] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10615 12:15:59.035375 <6>[ 0.791817] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10616 12:15:59.038834 <6>[ 0.800666] kvm [1]: IPA Size Limit: 40 bits
10617 12:15:59.045354 <6>[ 0.805195] kvm [1]: GICv3: no GICV resource entry
10618 12:15:59.048641 <6>[ 0.810217] kvm [1]: disabling GICv2 emulation
10619 12:15:59.055280 <6>[ 0.814903] kvm [1]: GIC system register CPU interface enabled
10620 12:15:59.058625 <6>[ 0.821069] kvm [1]: vgic interrupt IRQ18
10621 12:15:59.065208 <6>[ 0.825432] kvm [1]: VHE mode initialized successfully
10622 12:15:59.071811 <5>[ 0.831878] Initialise system trusted keyrings
10623 12:15:59.078443 <6>[ 0.836707] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10624 12:15:59.085877 <6>[ 0.846865] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10625 12:15:59.092530 <5>[ 0.853255] NFS: Registering the id_resolver key type
10626 12:15:59.096172 <5>[ 0.858557] Key type id_resolver registered
10627 12:15:59.102143 <5>[ 0.862972] Key type id_legacy registered
10628 12:15:59.108777 <6>[ 0.867270] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10629 12:15:59.115545 <6>[ 0.874193] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10630 12:15:59.122493 <6>[ 0.881929] 9p: Installing v9fs 9p2000 file system support
10631 12:15:59.158372 <5>[ 0.919641] Key type asymmetric registered
10632 12:15:59.161772 <5>[ 0.923974] Asymmetric key parser 'x509' registered
10633 12:15:59.171892 <6>[ 0.929123] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10634 12:15:59.175088 <6>[ 0.936739] io scheduler mq-deadline registered
10635 12:15:59.178510 <6>[ 0.941513] io scheduler kyber registered
10636 12:15:59.197053 <6>[ 0.958429] EINJ: ACPI disabled.
10637 12:15:59.229380 <4>[ 0.983788] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 12:15:59.239337 <4>[ 0.994434] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 12:15:59.253679 <6>[ 1.015018] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10640 12:15:59.261626 <6>[ 1.022981] printk: console [ttyS0] disabled
10641 12:15:59.289844 <6>[ 1.047630] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10642 12:15:59.296491 <6>[ 1.057110] printk: console [ttyS0] enabled
10643 12:15:59.299800 <6>[ 1.057110] printk: console [ttyS0] enabled
10644 12:15:59.306419 <6>[ 1.066008] printk: bootconsole [mtk8250] disabled
10645 12:15:59.309847 <6>[ 1.066008] printk: bootconsole [mtk8250] disabled
10646 12:15:59.316668 <6>[ 1.077186] SuperH (H)SCI(F) driver initialized
10647 12:15:59.319920 <6>[ 1.082455] msm_serial: driver initialized
10648 12:15:59.333973 <6>[ 1.091371] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10649 12:15:59.343219 <6>[ 1.099918] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10650 12:15:59.350021 <6>[ 1.108460] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10651 12:15:59.360374 <6>[ 1.117091] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10652 12:15:59.369800 <6>[ 1.125797] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10653 12:15:59.376998 <6>[ 1.134509] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10654 12:15:59.386640 <6>[ 1.143051] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10655 12:15:59.393142 <6>[ 1.151863] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10656 12:15:59.403250 <6>[ 1.160406] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10657 12:15:59.415085 <6>[ 1.176147] loop: module loaded
10658 12:15:59.421571 <6>[ 1.182234] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10659 12:15:59.444490 <4>[ 1.205783] mtk-pmic-keys: Failed to locate of_node [id: -1]
10660 12:15:59.451943 <6>[ 1.212742] megasas: 07.719.03.00-rc1
10661 12:15:59.461235 <6>[ 1.222478] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10662 12:15:59.469116 <6>[ 1.230043] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10663 12:15:59.485641 <6>[ 1.246729] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10664 12:15:59.546422 <6>[ 1.300842] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10665 12:16:01.413155 <6>[ 3.174616] Freeing initrd memory: 55052K
10666 12:16:01.423225 <6>[ 3.184792] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10667 12:16:01.434598 <6>[ 3.195827] tun: Universal TUN/TAP device driver, 1.6
10668 12:16:01.437993 <6>[ 3.201869] thunder_xcv, ver 1.0
10669 12:16:01.441231 <6>[ 3.205375] thunder_bgx, ver 1.0
10670 12:16:01.444595 <6>[ 3.208871] nicpf, ver 1.0
10671 12:16:01.454681 <6>[ 3.212869] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10672 12:16:01.458458 <6>[ 3.220346] hns3: Copyright (c) 2017 Huawei Corporation.
10673 12:16:01.465123 <6>[ 3.225932] hclge is initializing
10674 12:16:01.467843 <6>[ 3.229512] e1000: Intel(R) PRO/1000 Network Driver
10675 12:16:01.474605 <6>[ 3.234642] e1000: Copyright (c) 1999-2006 Intel Corporation.
10676 12:16:01.478012 <6>[ 3.240654] e1000e: Intel(R) PRO/1000 Network Driver
10677 12:16:01.484622 <6>[ 3.245870] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10678 12:16:01.491192 <6>[ 3.252056] igb: Intel(R) Gigabit Ethernet Network Driver
10679 12:16:01.498253 <6>[ 3.257706] igb: Copyright (c) 2007-2014 Intel Corporation.
10680 12:16:01.504689 <6>[ 3.263545] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10681 12:16:01.510923 <6>[ 3.270064] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10682 12:16:01.514524 <6>[ 3.276520] sky2: driver version 1.30
10683 12:16:01.520885 <6>[ 3.281502] VFIO - User Level meta-driver version: 0.3
10684 12:16:01.528439 <6>[ 3.289704] usbcore: registered new interface driver usb-storage
10685 12:16:01.535065 <6>[ 3.296148] usbcore: registered new device driver onboard-usb-hub
10686 12:16:01.543738 <6>[ 3.305216] mt6397-rtc mt6359-rtc: registered as rtc0
10687 12:16:01.553502 <6>[ 3.310681] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:16:12 UTC (1686053772)
10688 12:16:01.556887 <6>[ 3.320246] i2c_dev: i2c /dev entries driver
10689 12:16:01.574209 <6>[ 3.332012] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10690 12:16:01.580769 <6>[ 3.342196] sdhci: Secure Digital Host Controller Interface driver
10691 12:16:01.587368 <6>[ 3.348636] sdhci: Copyright(c) Pierre Ossman
10692 12:16:01.593955 <6>[ 3.354036] Synopsys Designware Multimedia Card Interface Driver
10693 12:16:01.597314 <6>[ 3.360631] mmc0: CQHCI version 5.10
10694 12:16:01.604195 <6>[ 3.361181] sdhci-pltfm: SDHCI platform and OF driver helper
10695 12:16:01.611283 <6>[ 3.372505] ledtrig-cpu: registered to indicate activity on CPUs
10696 12:16:01.621811 <6>[ 3.379810] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10697 12:16:01.624962 <6>[ 3.387204] usbcore: registered new interface driver usbhid
10698 12:16:01.631517 <6>[ 3.393037] usbhid: USB HID core driver
10699 12:16:01.638359 <6>[ 3.397288] spi_master spi0: will run message pump with realtime priority
10700 12:16:01.684355 <6>[ 3.438770] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10701 12:16:01.703266 <6>[ 3.454292] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10702 12:16:01.706547 <6>[ 3.467872] mmc0: Command Queue Engine enabled
10703 12:16:01.713590 <6>[ 3.469371] cros-ec-spi spi0.0: Chrome EC device registered
10704 12:16:01.720160 <6>[ 3.472614] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10705 12:16:01.723367 <6>[ 3.485957] mmcblk0: mmc0:0001 DA4128 116 GiB
10706 12:16:01.738084 <6>[ 3.496347] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10707 12:16:01.744613 <6>[ 3.499455] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10708 12:16:01.751359 <6>[ 3.507787] NET: Registered PF_PACKET protocol family
10709 12:16:01.754703 <6>[ 3.512921] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10710 12:16:01.761822 <6>[ 3.517029] 9pnet: Installing 9P2000 support
10711 12:16:01.765227 <6>[ 3.522776] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10712 12:16:01.771206 <5>[ 3.526693] Key type dns_resolver registered
10713 12:16:01.777884 <6>[ 3.532545] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10714 12:16:01.781193 <6>[ 3.536978] registered taskstats version 1
10715 12:16:01.784588 <5>[ 3.547288] Loading compiled-in X.509 certificates
10716 12:16:01.819431 <4>[ 3.574447] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10717 12:16:01.829309 <4>[ 3.585146] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10718 12:16:01.839889 <3>[ 3.597864] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10719 12:16:01.852062 <6>[ 3.613353] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10720 12:16:01.858807 <6>[ 3.620110] xhci-mtk 11200000.usb: xHCI Host Controller
10721 12:16:01.865228 <6>[ 3.625610] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10722 12:16:01.875234 <6>[ 3.633469] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10723 12:16:01.881843 <6>[ 3.642937] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10724 12:16:01.888565 <6>[ 3.649144] xhci-mtk 11200000.usb: xHCI Host Controller
10725 12:16:01.895308 <6>[ 3.654644] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10726 12:16:01.901921 <6>[ 3.662309] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10727 12:16:01.908626 <6>[ 3.670214] hub 1-0:1.0: USB hub found
10728 12:16:01.911867 <6>[ 3.674249] hub 1-0:1.0: 1 port detected
10729 12:16:01.922130 <6>[ 3.678600] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10730 12:16:01.925351 <6>[ 3.687417] hub 2-0:1.0: USB hub found
10731 12:16:01.928618 <6>[ 3.691459] hub 2-0:1.0: 1 port detected
10732 12:16:01.936907 <6>[ 3.698446] mtk-msdc 11f70000.mmc: Got CD GPIO
10733 12:16:01.954554 <6>[ 3.712744] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10734 12:16:01.961753 <6>[ 3.720769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10735 12:16:01.971560 <4>[ 3.728739] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10736 12:16:01.980918 <6>[ 3.738391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10737 12:16:01.987660 <6>[ 3.746473] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10738 12:16:01.994309 <6>[ 3.754501] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10739 12:16:02.004305 <6>[ 3.762416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10740 12:16:02.011070 <6>[ 3.770237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10741 12:16:02.020986 <6>[ 3.778064] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10742 12:16:02.030574 <6>[ 3.788775] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10743 12:16:02.040662 <6>[ 3.797163] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10744 12:16:02.047345 <6>[ 3.805520] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10745 12:16:02.057290 <6>[ 3.813868] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10746 12:16:02.063635 <6>[ 3.822211] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10747 12:16:02.073539 <6>[ 3.830554] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10748 12:16:02.080801 <6>[ 3.838898] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10749 12:16:02.090312 <6>[ 3.847242] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10750 12:16:02.097081 <6>[ 3.855585] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10751 12:16:02.106883 <6>[ 3.863930] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10752 12:16:02.113485 <6>[ 3.872273] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10753 12:16:02.123469 <6>[ 3.880616] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10754 12:16:02.129868 <6>[ 3.888960] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10755 12:16:02.140231 <6>[ 3.897302] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10756 12:16:02.146957 <6>[ 3.905646] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10757 12:16:02.153439 <6>[ 3.914522] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10758 12:16:02.160550 <6>[ 3.921957] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10759 12:16:02.167540 <6>[ 3.928996] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10760 12:16:02.174511 <6>[ 3.936089] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10761 12:16:02.185260 <6>[ 3.943382] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10762 12:16:02.192141 <6>[ 3.950307] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10763 12:16:02.201957 <6>[ 3.959446] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10764 12:16:02.211950 <6>[ 3.968574] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10765 12:16:02.221924 <6>[ 3.977876] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10766 12:16:02.231886 <6>[ 3.987352] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10767 12:16:02.238021 <6>[ 3.996826] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10768 12:16:02.248084 <6>[ 4.005953] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10769 12:16:02.257813 <6>[ 4.015429] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10770 12:16:02.268259 <6>[ 4.024559] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10771 12:16:02.277859 <6>[ 4.033866] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10772 12:16:02.287791 <6>[ 4.044034] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10773 12:16:02.297700 <6>[ 4.055899] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10774 12:16:02.336585 <6>[ 4.094910] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10775 12:16:02.491060 <6>[ 4.252251] hub 1-1:1.0: USB hub found
10776 12:16:02.494184 <6>[ 4.256721] hub 1-1:1.0: 4 ports detected
10777 12:16:02.616584 <6>[ 4.375096] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10778 12:16:02.641604 <6>[ 4.403366] hub 2-1:1.0: USB hub found
10779 12:16:02.645071 <6>[ 4.407783] hub 2-1:1.0: 3 ports detected
10780 12:16:02.816732 <6>[ 4.574897] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10781 12:16:02.949738 <6>[ 4.710851] hub 1-1.4:1.0: USB hub found
10782 12:16:02.953017 <6>[ 4.715522] hub 1-1.4:1.0: 2 ports detected
10783 12:16:03.028862 <6>[ 4.787138] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10784 12:16:03.248435 <6>[ 5.006895] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10785 12:16:03.440427 <6>[ 5.198895] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10786 12:16:14.597010 <6>[ 16.363465] ALSA device list:
10787 12:16:14.604151 <6>[ 16.366721] No soundcards found.
10788 12:16:14.616356 <6>[ 16.379182] Freeing unused kernel memory: 8384K
10789 12:16:14.619653 <6>[ 16.384112] Run /init as init process
10790 12:16:14.649946 <6>[ 16.413123] NET: Registered PF_INET6 protocol family
10791 12:16:14.657148 <6>[ 16.419920] Segment Routing with IPv6
10792 12:16:14.660550 <6>[ 16.423878] In-situ OAM (IOAM) with IPv6
10793 12:16:14.695228 <30>[ 16.438567] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10794 12:16:14.698647 <30>[ 16.462328] systemd[1]: Detected architecture arm64.
10795 12:16:14.698764
10796 12:16:14.705342 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10797 12:16:14.705461
10798 12:16:14.720212 <30>[ 16.483030] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10799 12:16:14.861847 <30>[ 16.621819] systemd[1]: Queued start job for default target Graphical Interface.
10800 12:16:14.909173 <30>[ 16.672176] systemd[1]: Created slice system-getty.slice.
10801 12:16:14.915939 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10802 12:16:14.932213 <30>[ 16.695467] systemd[1]: Created slice system-modprobe.slice.
10803 12:16:14.939034 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10804 12:16:14.956258 <30>[ 16.719382] systemd[1]: Created slice system-serial\x2dgetty.slice.
10805 12:16:14.966604 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10806 12:16:14.981011 <30>[ 16.743930] systemd[1]: Created slice User and Session Slice.
10807 12:16:14.987611 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10808 12:16:15.007889 <30>[ 16.767431] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10809 12:16:15.017742 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10810 12:16:15.035803 <30>[ 16.795417] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10811 12:16:15.042107 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10812 12:16:15.062933 <30>[ 16.818994] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10813 12:16:15.069315 <30>[ 16.831027] systemd[1]: Reached target Local Encrypted Volumes.
10814 12:16:15.076089 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10815 12:16:15.092380 <30>[ 16.855240] systemd[1]: Reached target Paths.
10816 12:16:15.095459 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10817 12:16:15.112263 <30>[ 16.874929] systemd[1]: Reached target Remote File Systems.
10818 12:16:15.118658 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10819 12:16:15.131779 <30>[ 16.894924] systemd[1]: Reached target Slices.
10820 12:16:15.138263 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10821 12:16:15.152015 <30>[ 16.914889] systemd[1]: Reached target Swap.
10822 12:16:15.155090 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10823 12:16:15.175954 <30>[ 16.935276] systemd[1]: Listening on initctl Compatibility Named Pipe.
10824 12:16:15.182081 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10825 12:16:15.189145 <30>[ 16.949964] systemd[1]: Listening on Journal Audit Socket.
10826 12:16:15.195657 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10827 12:16:15.208587 <30>[ 16.971135] systemd[1]: Listening on Journal Socket (/dev/log).
10828 12:16:15.215013 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10829 12:16:15.232484 <30>[ 16.995207] systemd[1]: Listening on Journal Socket.
10830 12:16:15.239127 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10831 12:16:15.252095 <30>[ 17.015198] systemd[1]: Listening on udev Control Socket.
10832 12:16:15.258746 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10833 12:16:15.272024 <30>[ 17.035070] systemd[1]: Listening on udev Kernel Socket.
10834 12:16:15.278660 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10835 12:16:20.099870 <30>[ 21.863320] systemd[1]: Mounting Huge Pages File System...
10836 12:16:20.106232 Mounting [0;1;39mHuge Pages File System[0m...
10837 12:16:20.121642 <30>[ 21.884929] systemd[1]: Mounting POSIX Message Queue File System...
10838 12:16:20.128084 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10839 12:16:20.149293 <30>[ 21.912950] systemd[1]: Mounting Kernel Debug File System...
10840 12:16:20.156207 Mounting [0;1;39mKernel Debug File System[0m...
10841 12:16:20.174763 <30>[ 21.935213] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10842 12:16:20.185886 <30>[ 21.946255] systemd[1]: Starting Create list of static device nodes for the current kernel...
10843 12:16:20.192845 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10844 12:16:20.219715 <30>[ 21.983415] systemd[1]: Starting Load Kernel Module configfs...
10845 12:16:20.226223 Starting [0;1;39mLoad Kernel Module configfs[0m...
10846 12:16:20.241764 <30>[ 22.005228] systemd[1]: Starting Load Kernel Module drm...
10847 12:16:20.248106 Starting [0;1;39mLoad Kernel Module drm[0m...
10848 12:16:20.267000 <30>[ 22.027115] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10849 12:16:20.316169 <30>[ 22.079500] systemd[1]: Starting Journal Service...
10850 12:16:20.319302 Starting [0;1;39mJournal Service[0m...
10851 12:16:20.338328 <30>[ 22.101486] systemd[1]: Starting Load Kernel Modules...
10852 12:16:20.344369 Starting [0;1;39mLoad Kernel Modules[0m...
10853 12:16:20.365015 <30>[ 22.125627] systemd[1]: Starting Remount Root and Kernel File Systems...
10854 12:16:20.371751 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10855 12:16:20.389741 <30>[ 22.153405] systemd[1]: Starting Coldplug All udev Devices...
10856 12:16:20.396269 Starting [0;1;39mColdplug All udev Devices[0m...
10857 12:16:20.414017 <30>[ 22.177743] systemd[1]: Mounted Huge Pages File System.
10858 12:16:20.421060 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10859 12:16:20.436041 <30>[ 22.199458] systemd[1]: Started Journal Service.
10860 12:16:20.442378 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10861 12:16:20.457589 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10862 12:16:20.476817 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10863 12:16:20.496301 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10864 12:16:20.513395 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10865 12:16:20.529331 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10866 12:16:20.544858 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10867 12:16:20.565087 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10868 12:16:20.579773 See 'systemctl status systemd-remount-fs.service' for details.
10869 12:16:20.616013 Mounting [0;1;39mKernel Configuration File System[0m...
10870 12:16:20.634306 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10871 12:16:20.651683 <46>[ 22.411775] systemd-journald[176]: Received client request to flush runtime journal.
10872 12:16:20.660713 Starting [0;1;39mLoad/Save Random Seed[0m...
10873 12:16:20.679025 Starting [0;1;39mApply Kernel Variables[0m...
10874 12:16:20.698223 Starting [0;1;39mCreate System Users[0m...
10875 12:16:20.717183 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10876 12:16:20.736027 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10877 12:16:20.748745 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10878 12:16:20.764738 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10879 12:16:20.781099 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10880 12:16:20.796586 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10881 12:16:20.847976 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10882 12:16:20.872104 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10883 12:16:20.887454 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10884 12:16:20.907153 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10885 12:16:20.944141 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10886 12:16:20.967494 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10887 12:16:20.984983 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10888 12:16:21.004440 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10889 12:16:21.044902 Starting [0;1;39mNetwork Time Synchronization[0m...
10890 12:16:21.062249 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10891 12:16:21.092656 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10892 12:16:21.149503 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10893 12:16:21.169164 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10894 12:16:21.186695 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10895 12:16:21.207049 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 22.967702] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10896 12:16:21.207218 em Time Set[0m.
10897 12:16:21.217272 <6>[ 22.980770] remoteproc remoteproc0: scp is available
10898 12:16:21.226807 <4>[ 22.986233] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10899 12:16:21.233442 <6>[ 22.987501] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10900 12:16:21.240180 <6>[ 22.997385] remoteproc remoteproc0: powering up scp
10901 12:16:21.246849 <3>[ 22.999525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 12:16:21.257091 <3>[ 22.999543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 12:16:21.263534 <3>[ 22.999551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 12:16:21.273170 <6>[ 23.003955] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10905 12:16:21.282999 <4>[ 23.009040] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10906 12:16:21.292932 <6>[ 23.017054] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10907 12:16:21.299698 <3>[ 23.024829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 12:16:21.309378 <3>[ 23.024851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10909 12:16:21.316145 <3>[ 23.024860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10910 12:16:21.322577 <3>[ 23.024872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 12:16:21.333043 <3>[ 23.024882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 12:16:21.339515 <3>[ 23.024974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 12:16:21.349000 <3>[ 23.025045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 12:16:21.356135 <3>[ 23.025055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 12:16:21.365741 <3>[ 23.025062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 12:16:21.372852 <3>[ 23.025094] remoteproc remoteproc0: request_firmware failed: -2
10917 12:16:21.379330 <3>[ 23.025144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 12:16:21.385918 <6>[ 23.062969] usbcore: registered new interface driver r8152
10919 12:16:21.392110 <3>[ 23.068751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 12:16:21.398983 <6>[ 23.112209] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10921 12:16:21.408998 <3>[ 23.117275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 12:16:21.412295 <6>[ 23.149429] mc: Linux media interface: v0.10
10923 12:16:21.422114 <3>[ 23.153547] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 12:16:21.429141 <4>[ 23.163056] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10925 12:16:21.435515 <3>[ 23.169271] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 12:16:21.442386 <6>[ 23.171261] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10927 12:16:21.448988 <6>[ 23.171271] pci_bus 0000:00: root bus resource [bus 00-ff]
10928 12:16:21.455236 <6>[ 23.171279] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10929 12:16:21.465470 <6>[ 23.171286] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10930 12:16:21.472514 <6>[ 23.171326] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10931 12:16:21.479148 <6>[ 23.171350] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10932 12:16:21.485840 <6>[ 23.171435] pci 0000:00:00.0: supports D1 D2
10933 12:16:21.492210 <6>[ 23.171439] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10934 12:16:21.499003 <4>[ 23.177393] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10935 12:16:21.505837 <4>[ 23.177393] Fallback method does not support PEC.
10936 12:16:21.515982 <3>[ 23.190575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10937 12:16:21.522442 <4>[ 23.190596] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10938 12:16:21.532122 <6>[ 23.191252] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10939 12:16:21.538476 <6>[ 23.199803] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10940 12:16:21.548785 <6>[ 23.224048] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10941 12:16:21.555312 <6>[ 23.226356] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10942 12:16:21.562341 <6>[ 23.228070] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10943 12:16:21.571809 <6>[ 23.228108] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10944 12:16:21.578283 <6>[ 23.228129] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10945 12:16:21.585393 <6>[ 23.228148] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10946 12:16:21.588603 <6>[ 23.228281] pci 0000:01:00.0: supports D1 D2
10947 12:16:21.598707 <6>[ 23.228284] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10948 12:16:21.601979 <6>[ 23.233729] videodev: Linux video capture interface: v2.00
10949 12:16:21.612102 <3>[ 23.236812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 12:16:21.618570 <6>[ 23.257615] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10951 12:16:21.628211 <6>[ 23.366089] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10952 12:16:21.635282 <6>[ 23.371721] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10953 12:16:21.644954 <6>[ 23.404810] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10954 12:16:21.651366 <4>[ 23.408772] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10955 12:16:21.661617 <6>[ 23.413046] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10956 12:16:21.671759 [[0;32m OK [<4>[ 23.421899] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10957 12:16:21.678554 <6>[ 23.422997] usbcore: registered new interface driver cdc_ether
10958 12:16:21.684871 0m] Reached targ<6>[ 23.429881] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10959 12:16:21.691319 <6>[ 23.440335] Bluetooth: Core ver 2.22
10960 12:16:21.694711 <6>[ 23.440373] usbcore: registered new interface driver r8153_ecm
10961 12:16:21.704975 et [0;1;39mSyst<6>[ 23.446518] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10962 12:16:21.711222 em Time Synchron<6>[ 23.455065] NET: Registered PF_BLUETOOTH protocol family
10963 12:16:21.717801 <6>[ 23.458674] pci 0000:00:00.0: PCI bridge to [bus 01]
10964 12:16:21.717887 ized[0m.
10965 12:16:21.724242 <6>[ 23.459957] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10966 12:16:21.738159 <6>[ 23.461722] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10967 12:16:21.744765 <6>[ 23.461869] usbcore: registered new interface driver uvcvideo
10968 12:16:21.751273 <6>[ 23.464945] Bluetooth: HCI device and connection manager initialized
10969 12:16:21.757805 <6>[ 23.474134] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10970 12:16:21.764395 <6>[ 23.481108] Bluetooth: HCI socket layer initialized
10971 12:16:21.771292 <6>[ 23.482004] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10972 12:16:21.774461 <6>[ 23.486233] remoteproc remoteproc0: powering up scp
10973 12:16:21.784998 <4>[ 23.486281] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10974 12:16:21.791992 <3>[ 23.486290] remoteproc remoteproc0: request_firmware failed: -2
10975 12:16:21.798866 <6>[ 23.486466] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10976 12:16:21.802845 <6>[ 23.487377] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10977 12:16:21.809149 <6>[ 23.487887] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10978 12:16:21.815853 <6>[ 23.494370] Bluetooth: L2CAP socket layer initialized
10979 12:16:21.819661 <6>[ 23.494432] Bluetooth: SCO socket layer initialized
10980 12:16:21.829834 <5>[ 23.515996] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10981 12:16:21.836363 <3>[ 23.519770] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10982 12:16:21.839711 <6>[ 23.527745] r8152 2-1.3:1.0 eth0: v1.12.13
10983 12:16:21.846089 <6>[ 23.533941] usbcore: registered new interface driver btusb
10984 12:16:21.856395 <4>[ 23.534468] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10985 12:16:21.862842 <3>[ 23.534477] Bluetooth: hci0: Failed to load firmware file (-2)
10986 12:16:21.870002 <3>[ 23.534480] Bluetooth: hci0: Failed to set up firmware (-2)
10987 12:16:21.880011 <4>[ 23.534484] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10988 12:16:21.886238 <5>[ 23.549679] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10989 12:16:21.892850 <6>[ 23.552049] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10990 12:16:21.899207 <3>[ 23.578279] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10991 12:16:21.910270 [[0;32m OK [<3>[ 23.670808] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 12:16:21.919786 0m] Started [0;<4>[ 23.675258] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10993 12:16:21.933039 1;39mDiscard unu<3>[ 23.678299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10994 12:16:21.942763 sed blocks once <3>[ 23.680515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10995 12:16:21.942851 a week[0m.
10996 12:16:21.946504 <6>[ 23.690242] cfg80211: failed to load regulatory.db
10997 12:16:21.953640 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10998 12:16:21.979302 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message B<3>[ 23.737212] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 12:16:21.985856 <6>[ 23.745958] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11000 12:16:21.985955 us Socket[0m.
11001 12:16:21.992270 <6>[ 23.754784] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11002 12:16:22.007321 <3>[ 23.767781] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 12:16:22.013927 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11004 12:16:22.020676 <6>[ 23.782694] mt7921e 0000:01:00.0: ASIC revision: 79610010
11005 12:16:22.027316 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11006 12:16:22.040727 <3>[ 23.800985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 12:16:22.071134 <3>[ 23.831173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 12:16:22.077429 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11009 12:16:22.103917 <3>[ 23.864432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 12:16:22.110552 Starting [0;1;39mUser Login Management[0m...
11011 12:16:22.127212 <4>[ 23.884132] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11012 12:16:22.144292 Starting [0;1;39mPermit User Sessions[0m...
11013 12:16:22.165882 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11014 12:16:22.191863 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11015 12:16:22.248456 <4>[ 24.006021] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11016 12:16:22.368092 <4>[ 24.125174] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11017 12:16:22.377872 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11018 12:16:22.391748 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11019 12:16:22.407817 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11020 12:16:22.427299 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11021 12:16:22.488524 [[0;32m OK [0m] Started [0;1;39mGetty on tt<4>[ 24.246118] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11022 12:16:22.488678 y1[0m.
11023 12:16:22.528526 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11024 12:16:22.534715 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11025 12:16:22.551298 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11026 12:16:22.567513 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11027 12:16:22.608204 <4>[ 24.365516] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11028 12:16:22.631111 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11029 12:16:22.650448 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11030 12:16:22.669749 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11031 12:16:22.728269 <4>[ 24.485395] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11032 12:16:22.734877 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11033 12:16:22.755063 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11034 12:16:22.768013 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11035 12:16:22.785932
11036 12:16:22.786091
11037 12:16:22.789110 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11038 12:16:22.789189
11039 12:16:22.792328 debian-bullseye-arm64 login: root (automatic login)
11040 12:16:22.792403
11041 12:16:22.792466
11042 12:16:22.809124 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
11043 12:16:22.809274
11044 12:16:22.815556 The programs included with the Debian GNU/Linux system are free software;
11045 12:16:22.822403 the exact distribution terms for each program are described in the
11046 12:16:22.825566 individual files in /usr/share/doc/*/copyright.
11047 12:16:22.825727
11048 12:16:22.831976 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11049 12:16:22.832167 permitted by applicable law.
11050 12:16:22.836191 Matched prompt #10: / #
11052 12:16:22.836497 Setting prompt string to ['/ #']
11053 12:16:22.836658 end: 2.2.5.1 login-action (duration 00:00:25) [common]
11055 12:16:22.836871 end: 2.2.5 auto-login-action (duration 00:00:25) [common]
11056 12:16:22.836983 start: 2.2.6 expect-shell-connection (timeout 00:02:43) [common]
11057 12:16:22.837062 Setting prompt string to ['/ #']
11058 12:16:22.837126 Forcing a shell prompt, looking for ['/ #']
11060 12:16:22.887338 / #
11061 12:16:22.887599 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11062 12:16:22.887704 Waiting using forced prompt support (timeout 00:02:30)
11063 12:16:22.887878 <4>[ 24.609596] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11064 12:16:22.892509
11065 12:16:22.892811 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11066 12:16:22.892915 start: 2.2.7 export-device-env (timeout 00:02:43) [common]
11067 12:16:22.893024 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11068 12:16:22.893112 end: 2.2 depthcharge-retry (duration 00:02:17) [common]
11069 12:16:22.893227 end: 2 depthcharge-action (duration 00:02:17) [common]
11070 12:16:22.893334 start: 3 lava-test-retry (timeout 00:07:20) [common]
11071 12:16:22.893497 start: 3.1 lava-test-shell (timeout 00:07:20) [common]
11072 12:16:22.893573 Using namespace: common
11074 12:16:22.993912 / # #
11075 12:16:22.994107 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11076 12:16:22.994235 #<4>[ 24.729169] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11077 12:16:22.999155
11078 12:16:22.999399 Using /lava-10605408
11080 12:16:23.099720 / # export SHELL=/bin/sh
11081 12:16:23.100039 export SHELL=/bin/sh<4>[ 24.848944] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11082 12:16:23.105120
11084 12:16:23.205684 / # . /lava-10605408/environment
11085 12:16:23.251559 . /lava-10605408/environment<4>[ 24.969260] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11086 12:16:23.251726
11088 12:16:23.352290 / # /lava-10605408/bin/lava-test-runner /lava-10605408/0
11089 12:16:23.352467 Test shell timeout: 10s (minimum of the action and connection timeout)
11090 12:16:23.352817 /lava-10605408/bin/lava-test-runner /lava-10605408/0<3>[ 25.087497] mt7921e 0000:01:00.0: hardware init failed
11091 12:16:23.357393
11092 12:16:23.403472 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 25.144520] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10605408_1.5.2.3.1>
11093 12:16:23.403633 rost
11094 12:16:23.403886 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10605408_1.5.2.3.1
11095 12:16:23.403968 Starting test lava.0_igt-gpu-panfrost (10605408_1.5.2.3.1)
11096 12:16:23.404055 Skipping test definition patterns.
11097 12:16:23.404163 + cd /lava-10605408/0/tests/0_igt-gpu-panfrost
11098 12:16:23.404231 + cat uuid
11099 12:16:23.404292 + UUID=10605408_1.5.2.3.1
11100 12:16:23.404350 + set +x
11101 12:16:23.404407 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11102 12:16:23.411505 <8>[ 25.175471] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11103 12:16:23.411788 Received signal: <TESTSET> START panfrost_gem_new
11104 12:16:23.411890 Starting test_set panfrost_gem_new
11105 12:16:23.435345 <14>[ 25.199276] [IGT] panfrost_gem_new: executing
11106 12:16:23.445165 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.207810] [IGT] panfrost_gem_new: exiting, ret=77
11107 12:16:23.445279 .1.31 aarch64)
11108 12:16:23.458431 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.219894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11109 12:16:23.458717 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11111 12:16:23.462239 b/drmtest.c:621:
11112 12:16:23.462332 Test requirement: !(fd<0)
11113 12:16:23.468804 No known gpu found for chipset flags 0x32 (panfrost)
11114 12:16:23.471988 Last errno: 2, No such file or directory
11115 12:16:23.475186 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11116 12:16:23.482287 <14>[ 25.246283] [IGT] panfrost_gem_new: executing
11117 12:16:23.492681 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.254415] [IGT] panfrost_gem_new: exiting, ret=77
11118 12:16:23.492877 .1.31 aarch64)
11119 12:16:23.505646 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.266553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11120 12:16:23.505801 b/drmtest.c:621:
11121 12:16:23.506088 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11123 12:16:23.508673 Test requirement: !(fd<0)
11124 12:16:23.515364 No known gpu found for chipset flags 0x32 (panfrost)
11125 12:16:23.518614 Last errno: 2, No such file or directory
11126 12:16:23.522253 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11127 12:16:23.528476 <14>[ 25.291396] [IGT] panfrost_gem_new: executing
11128 12:16:23.535023 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.299514] [IGT] panfrost_gem_new: exiting, ret=77
11129 12:16:23.538826 .1.31 aarch64)
11130 12:16:23.551847 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.311678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11131 12:16:23.551992 b/drmtest.c:621:
11132 12:16:23.552267 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11134 12:16:23.558757 Test requireme<8>[ 25.321496] <LAVA_SIGNAL_TESTSET STOP>
11135 12:16:23.558874 nt: !(fd<0)
11136 12:16:23.559145 Received signal: <TESTSET> STOP
11137 12:16:23.559247 Closing test_set panfrost_gem_new
11138 12:16:23.565075 No known gpu found for chipset flags 0x32 (panfrost)
11139 12:16:23.568252 Last errno: 2, No such file or directory
11140 12:16:23.571554 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11141 12:16:23.584199 <8>[ 25.347975] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11142 12:16:23.584512 Received signal: <TESTSET> START panfrost_get_param
11143 12:16:23.584591 Starting test_set panfrost_get_param
11144 12:16:23.607759 <14>[ 25.371685] [IGT] panfrost_get_param: executing
11145 12:16:23.617960 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.380146] [IGT] panfrost_get_param: exiting, ret=77
11146 12:16:23.618087 .1.31 aarch64)
11147 12:16:23.630998 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.392790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11148 12:16:23.631296 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11150 12:16:23.634048 b/drmtest.c:621:
11151 12:16:23.634137 Test requirement: !(fd<0)
11152 12:16:23.641080 No known gpu found for chipset flags 0x32 (panfrost)
11153 12:16:23.644285 Last errno: 2, No such file or directory
11154 12:16:23.647513 [1mSubtest base-params: SKIP (0.000s)[0m
11155 12:16:23.654018 <14>[ 25.417485] [IGT] panfrost_get_param: executing
11156 12:16:23.664106 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.425689] [IGT] panfrost_get_param: exiting, ret=77
11157 12:16:23.664240 .1.31 aarch64)
11158 12:16:23.677077 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.438067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11159 12:16:23.677196 b/drmtest.c:621:
11160 12:16:23.677443 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11162 12:16:23.680295 Test requirement: !(fd<0)
11163 12:16:23.687298 No known gpu found for chipset flags 0x32 (panfrost)
11164 12:16:23.690673 Last errno: 2, No such file or directory
11165 12:16:23.693790 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11166 12:16:23.700364 <14>[ 25.463012] [IGT] panfrost_get_param: executing
11167 12:16:23.709904 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.471320] [IGT] panfrost_get_param: exiting, ret=77
11168 12:16:23.710033 .1.31 aarch64)
11169 12:16:23.723439 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.483731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11170 12:16:23.723567 b/drmtest.c:621:
11171 12:16:23.723859 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11173 12:16:23.730308 Test requireme<8>[ 25.493594] <LAVA_SIGNAL_TESTSET STOP>
11174 12:16:23.730420 nt: !(fd<0)
11175 12:16:23.730688 Received signal: <TESTSET> STOP
11176 12:16:23.730785 Closing test_set panfrost_get_param
11177 12:16:23.736560 No known gpu found for chipset flags 0x32 (panfrost)
11178 12:16:23.740478 Last errno: 2, No such file or directory
11179 12:16:23.743381 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11180 12:16:23.755119 <8>[ 25.519366] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11181 12:16:23.755424 Received signal: <TESTSET> START panfrost_prime
11182 12:16:23.755500 Starting test_set panfrost_prime
11183 12:16:23.779120 <14>[ 25.542877] [IGT] panfrost_prime: executing
11184 12:16:23.788617 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.551077] [IGT] panfrost_prime: exiting, ret=77
11185 12:16:23.788784 .1.31 aarch64)
11186 12:16:23.802197 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.563020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11187 12:16:23.802330 b/drmtest.c:621:
11188 12:16:23.802603 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11190 12:16:23.808711 Test requireme<8>[ 25.572750] <LAVA_SIGNAL_TESTSET STOP>
11191 12:16:23.808825 nt: !(fd<0)
11192 12:16:23.809094 Received signal: <TESTSET> STOP
11193 12:16:23.809192 Closing test_set panfrost_prime
11194 12:16:23.815101 No known gpu found for chipset flags 0x32 (panfrost)
11195 12:16:23.818795 Last errno: 2, No such file or directory
11196 12:16:23.822120 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11197 12:16:23.835238 <8>[ 25.599362] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11198 12:16:23.835547 Received signal: <TESTSET> START panfrost_submit
11199 12:16:23.835632 Starting test_set panfrost_submit
11200 12:16:23.857794 <14>[ 25.621819] [IGT] panfrost_submit: executing
11201 12:16:23.867931 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.629951] [IGT] panfrost_submit: exiting, ret=77
11202 12:16:23.868040 .1.31 aarch64)
11203 12:16:23.881031 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.641807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11204 12:16:23.881149 b/drmtest.c:621:
11205 12:16:23.881394 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11207 12:16:23.884293 Test requirement: !(fd<0)
11208 12:16:23.890336 No known gpu found for chipset flags 0x32 (panfrost)
11209 12:16:23.894172 Last errno: 2, No such file or directory
11210 12:16:23.897375 [1mSubtest pan-submit: SKIP (0.000s)[0m
11211 12:16:23.903978 <14>[ 25.667960] [IGT] panfrost_submit: executing
11212 12:16:23.913664 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.676121] [IGT] panfrost_submit: exiting, ret=77
11213 12:16:23.913753 .1.31 aarch64)
11214 12:16:23.927196 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.688083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11215 12:16:23.927470 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11217 12:16:23.930423 b/drmtest.c:621:
11218 12:16:23.930506 Test requirement: !(fd<0)
11219 12:16:23.936900 No known gpu found for chipset flags 0x32 (panfrost)
11220 12:16:23.940118 Last errno: 2, No such file or directory
11221 12:16:23.943785 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11222 12:16:23.951266 <14>[ 25.715402] [IGT] panfrost_submit: executing
11223 12:16:23.961223 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.723714] [IGT] panfrost_submit: exiting, ret=77
11224 12:16:23.961318 .1.31 aarch64)
11225 12:16:23.974716 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.735628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11226 12:16:23.975009 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11228 12:16:23.977921 b/drmtest.c:621:
11229 12:16:23.980883 Test requirement: !(fd<0)
11230 12:16:23.984694 No known gpu found for chipset flags 0x32 (panfrost)
11231 12:16:23.987949 Last errno: 2, No such file or directory
11232 12:16:23.994348 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11233 12:16:23.997461 <14>[ 25.761908] [IGT] panfrost_submit: executing
11234 12:16:24.008021 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.770558] [IGT] panfrost_submit: exiting, ret=77
11235 12:16:24.008115 .1.31 aarch64)
11236 12:16:24.024157 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.782520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11237 12:16:24.024261 b/drmtest.c:621:
11238 12:16:24.024500 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11240 12:16:24.027929 Test requirement: !(fd<0)
11241 12:16:24.031301 No known gpu found for chipset flags 0x32 (panfrost)
11242 12:16:24.034486 Last errno: 2, No such file or directory
11243 12:16:24.040999 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11244 12:16:24.047443 <14>[ 25.810589] [IGT] panfrost_submit: executing
11245 12:16:24.054055 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.818520] [IGT] panfrost_submit: exiting, ret=77
11246 12:16:24.057131 .1.31 aarch64)
11247 12:16:24.070911 Test requirement not met in function drm_open_driver, file ../li<8>[ 25.830437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11248 12:16:24.071185 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11250 12:16:24.074056 b/drmtest.c:621:
11251 12:16:24.074146 Test requirement: !(fd<0)
11252 12:16:24.080291 No known gpu found for chipset flags 0x32 (panfrost)
11253 12:16:24.084080 Last errno: 2, No such file or directory
11254 12:16:24.090697 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11255 12:16:24.093904 <14>[ 25.857439] [IGT] panfrost_submit: executing
11256 12:16:24.103650 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.866211] [IGT] panfrost_submit: exiting, ret=77
11257 12:16:24.103758 .1.31 aarch64)
11258 12:16:24.117208 Test requirement not met in function drm_open_dr<8>[ 25.877834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11259 12:16:24.117500 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11261 12:16:24.120410 iver, file ../lib/drmtest.c:621:
11262 12:16:24.123571 Test requirement: !(fd<0)
11263 12:16:24.126751 No known gpu found for chipset flags 0x32 (panfrost)
11264 12:16:24.130034 Last errno: 2, No such file or directory
11265 12:16:24.140327 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.<14>[ 25.903901] [IGT] panfrost_submit: executing
11266 12:16:24.140412 000s)[0m
11267 12:16:24.149950 IGT-Version: 1.27.1-g766edf9 (aa<14>[ 25.912512] [IGT] panfrost_submit: exiting, ret=77
11268 12:16:24.154003 rch64) (Linux: 6.1.31 aarch64)
11269 12:16:24.163746 Test requirement not met in function drm_open_dr<8>[ 25.923680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11270 12:16:24.164006 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11272 12:16:24.166703 iver, file ../lib/drmtest.c:621:
11273 12:16:24.166785 Test requirement: !(fd<0)
11274 12:16:24.173481 No known gpu found for chipset flags 0x32 (panfrost)
11275 12:16:24.176521 Last errno: 2, No such file or directory
11276 12:16:24.179740 [1mSubtest pan-reset: SKIP (0.000s)[0m
11277 12:16:24.186556 <14>[ 25.949763] [IGT] panfrost_submit: executing
11278 12:16:24.196530 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 25.958107] [IGT] panfrost_submit: exiting, ret=77
11279 12:16:24.196621 .1.31 aarch64)
11280 12:16:24.206764 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11282 12:16:24.209729 Test requirement not met in function drm_open_dr<8>[ 25.969509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11283 12:16:24.209816 iver, file ../lib/drmtest.c:621:
11284 12:16:24.212980 Test requirement: !(fd<0)
11285 12:16:24.220168 No known gpu found for chipset flags 0x32 (panfrost)
11286 12:16:24.223307 Last errno: 2, No such file or directory
11287 12:16:24.229795 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m<14>[ 25.994497] [IGT] panfrost_submit: executing
11288 12:16:24.229890
11289 12:16:24.239527 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 26.003357] [IGT] panfrost_submit: exiting, ret=77
11290 12:16:24.242787 .1.31 aarch64)
11291 12:16:24.256230 Test requirement not met in function drm_open_driver, file ../li<8>[ 26.015060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11292 12:16:24.256521 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11294 12:16:24.259563 b/drmtest.c:621:<8>[ 26.025742] <LAVA_SIGNAL_TESTSET STOP>
11295 12:16:24.259648
11296 12:16:24.259885 Received signal: <TESTSET> STOP
11297 12:16:24.259954 Closing test_set panfrost_submit
11298 12:16:24.269297 Test requireme<8>[ 26.030486] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10605408_1.5.2.3.1>
11299 12:16:24.269384 nt: !(fd<0)
11300 12:16:24.269620 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10605408_1.5.2.3.1
11301 12:16:24.269709 Ending use of test pattern.
11302 12:16:24.269771 Ending test lava.0_igt-gpu-panfrost (10605408_1.5.2.3.1), duration 0.87
11304 12:16:24.276185 No known gpu found for chipset flags 0x32 (panfrost)
11305 12:16:24.279200 Last errno: 2, No such file or directory
11306 12:16:24.282903 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11307 12:16:24.282988 + set +x
11308 12:16:24.285843 <LAVA_TEST_RUNNER EXIT>
11309 12:16:24.286100 ok: lava_test_shell seems to have completed
11310 12:16:24.286412 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11311 12:16:24.286555 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11312 12:16:24.286645 end: 3 lava-test-retry (duration 00:00:01) [common]
11313 12:16:24.286735 start: 4 finalize (timeout 00:07:18) [common]
11314 12:16:24.286823 start: 4.1 power-off (timeout 00:00:30) [common]
11315 12:16:24.286979 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11316 12:16:24.361729 >> Command sent successfully.
11317 12:16:24.364107 Returned 0 in 0 seconds
11318 12:16:24.464502 end: 4.1 power-off (duration 00:00:00) [common]
11320 12:16:24.464943 start: 4.2 read-feedback (timeout 00:07:18) [common]
11321 12:16:24.465239 Listened to connection for namespace 'common' for up to 1s
11322 12:16:25.466245 Finalising connection for namespace 'common'
11323 12:16:25.466575 Disconnecting from shell: Finalise
11324 12:16:25.466745 / #
11325 12:16:25.567406 end: 4.2 read-feedback (duration 00:00:01) [common]
11326 12:16:25.568043 end: 4 finalize (duration 00:00:01) [common]
11327 12:16:25.568679 Cleaning after the job
11328 12:16:25.569135 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/ramdisk
11329 12:16:25.593209 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/kernel
11330 12:16:25.606104 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/dtb
11331 12:16:25.606442 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605408/tftp-deploy-wio5u1tq/modules
11332 12:16:25.614382 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605408
11333 12:16:25.711967 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605408
11334 12:16:25.712151 Job finished correctly