Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 27
1 12:10:21.705147 lava-dispatcher, installed at version: 2023.05.1
2 12:10:21.705362 start: 0 validate
3 12:10:21.705507 Start time: 2023-06-06 12:10:21.705499+00:00 (UTC)
4 12:10:21.705643 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:10:21.705779 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:10:22.004877 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:10:22.005131 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:10:39.310045 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:10:39.310234 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:10:39.595451 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:10:39.595683 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:10:43.379332 validate duration: 21.67
14 12:10:43.379679 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:10:43.379814 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:10:43.379927 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:10:43.380059 Not decompressing ramdisk as can be used compressed.
18 12:10:43.380146 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 12:10:43.380216 saving as /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/ramdisk/rootfs.cpio.gz
20 12:10:43.380279 total size: 43394293 (41MB)
21 12:10:43.678485 progress 0% (0MB)
22 12:10:43.695375 progress 5% (2MB)
23 12:10:43.710442 progress 10% (4MB)
24 12:10:43.725405 progress 15% (6MB)
25 12:10:43.743703 progress 20% (8MB)
26 12:10:43.757911 progress 25% (10MB)
27 12:10:43.773160 progress 30% (12MB)
28 12:10:43.788351 progress 35% (14MB)
29 12:10:43.807129 progress 40% (16MB)
30 12:10:43.822330 progress 45% (18MB)
31 12:10:43.838892 progress 50% (20MB)
32 12:10:43.854634 progress 55% (22MB)
33 12:10:43.869051 progress 60% (24MB)
34 12:10:43.883803 progress 65% (26MB)
35 12:10:43.900856 progress 70% (29MB)
36 12:10:43.917612 progress 75% (31MB)
37 12:10:43.933328 progress 80% (33MB)
38 12:10:43.948686 progress 85% (35MB)
39 12:10:43.965402 progress 90% (37MB)
40 12:10:43.980096 progress 95% (39MB)
41 12:10:43.993616 progress 100% (41MB)
42 12:10:43.993809 41MB downloaded in 0.61s (67.45MB/s)
43 12:10:43.993976 end: 1.1.1 http-download (duration 00:00:01) [common]
45 12:10:43.994224 end: 1.1 download-retry (duration 00:00:01) [common]
46 12:10:43.994313 start: 1.2 download-retry (timeout 00:09:59) [common]
47 12:10:43.994399 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 12:10:43.994534 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:10:43.994609 saving as /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/kernel/Image
50 12:10:43.994673 total size: 45746688 (43MB)
51 12:10:43.994734 No compression specified
52 12:10:43.995930 progress 0% (0MB)
53 12:10:44.007472 progress 5% (2MB)
54 12:10:44.019057 progress 10% (4MB)
55 12:10:44.030603 progress 15% (6MB)
56 12:10:44.042083 progress 20% (8MB)
57 12:10:44.053561 progress 25% (10MB)
58 12:10:44.064951 progress 30% (13MB)
59 12:10:44.076451 progress 35% (15MB)
60 12:10:44.088010 progress 40% (17MB)
61 12:10:44.099577 progress 45% (19MB)
62 12:10:44.111590 progress 50% (21MB)
63 12:10:44.123264 progress 55% (24MB)
64 12:10:44.135445 progress 60% (26MB)
65 12:10:44.147244 progress 65% (28MB)
66 12:10:44.158808 progress 70% (30MB)
67 12:10:44.170337 progress 75% (32MB)
68 12:10:44.181856 progress 80% (34MB)
69 12:10:44.193419 progress 85% (37MB)
70 12:10:44.204952 progress 90% (39MB)
71 12:10:44.216466 progress 95% (41MB)
72 12:10:44.228010 progress 100% (43MB)
73 12:10:44.228171 43MB downloaded in 0.23s (186.85MB/s)
74 12:10:44.228324 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:10:44.228560 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:10:44.228651 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:10:44.228737 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:10:44.228892 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:10:44.228968 saving as /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/dtb/mt8192-asurada-spherion-r0.dtb
81 12:10:44.229032 total size: 46924 (0MB)
82 12:10:44.229094 No compression specified
83 12:10:44.230216 progress 69% (0MB)
84 12:10:44.230491 progress 100% (0MB)
85 12:10:44.230644 0MB downloaded in 0.00s (27.80MB/s)
86 12:10:44.230766 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:10:44.230991 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:10:44.231078 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:10:44.231162 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:10:44.231272 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:10:44.231342 saving as /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/modules/modules.tar
93 12:10:44.231404 total size: 8553528 (8MB)
94 12:10:44.231465 Using unxz to decompress xz
95 12:10:44.234780 progress 0% (0MB)
96 12:10:44.255848 progress 5% (0MB)
97 12:10:44.280307 progress 10% (0MB)
98 12:10:44.312473 progress 15% (1MB)
99 12:10:44.339225 progress 20% (1MB)
100 12:10:44.365732 progress 25% (2MB)
101 12:10:44.391797 progress 30% (2MB)
102 12:10:44.419152 progress 35% (2MB)
103 12:10:44.445740 progress 40% (3MB)
104 12:10:44.473487 progress 45% (3MB)
105 12:10:44.499751 progress 50% (4MB)
106 12:10:44.525533 progress 55% (4MB)
107 12:10:44.550480 progress 60% (4MB)
108 12:10:44.575952 progress 65% (5MB)
109 12:10:44.602036 progress 70% (5MB)
110 12:10:44.627652 progress 75% (6MB)
111 12:10:44.655603 progress 80% (6MB)
112 12:10:44.682136 progress 85% (6MB)
113 12:10:44.708240 progress 90% (7MB)
114 12:10:44.732597 progress 95% (7MB)
115 12:10:44.759782 progress 100% (8MB)
116 12:10:44.764533 8MB downloaded in 0.53s (15.30MB/s)
117 12:10:44.764878 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:10:44.765144 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:10:44.765238 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:10:44.765333 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:10:44.765417 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:10:44.765503 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:10:44.765719 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd
125 12:10:44.765852 makedir: /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin
126 12:10:44.765957 makedir: /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/tests
127 12:10:44.766056 makedir: /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/results
128 12:10:44.766171 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-add-keys
129 12:10:44.766317 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-add-sources
130 12:10:44.766444 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-background-process-start
131 12:10:44.766571 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-background-process-stop
132 12:10:44.766694 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-common-functions
133 12:10:44.766818 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-echo-ipv4
134 12:10:44.766944 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-install-packages
135 12:10:44.767066 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-installed-packages
136 12:10:44.767189 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-os-build
137 12:10:44.767311 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-probe-channel
138 12:10:44.767433 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-probe-ip
139 12:10:44.767554 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-target-ip
140 12:10:44.767674 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-target-mac
141 12:10:44.767795 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-target-storage
142 12:10:44.767920 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-case
143 12:10:44.768043 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-event
144 12:10:44.768165 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-feedback
145 12:10:44.768286 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-raise
146 12:10:44.768410 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-reference
147 12:10:44.768532 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-runner
148 12:10:44.768654 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-set
149 12:10:44.768785 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-test-shell
150 12:10:44.768913 Updating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-install-packages (oe)
151 12:10:44.769067 Updating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/bin/lava-installed-packages (oe)
152 12:10:44.769201 Creating /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/environment
153 12:10:44.769316 LAVA metadata
154 12:10:44.769394 - LAVA_JOB_ID=10605395
155 12:10:44.769463 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:10:44.769570 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:10:44.769640 skipped lava-vland-overlay
158 12:10:44.769719 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:10:44.769803 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:10:44.769868 skipped lava-multinode-overlay
161 12:10:44.769943 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:10:44.770045 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:10:44.770123 Loading test definitions
164 12:10:44.770233 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:10:44.770312 Using /lava-10605395 at stage 0
166 12:10:44.770625 uuid=10605395_1.5.2.3.1 testdef=None
167 12:10:44.770735 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:10:44.770825 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:10:44.771335 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:10:44.771566 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:10:44.772253 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:10:44.772631 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:10:44.773284 runner path: /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/0/tests/0_igt-kms-mediatek test_uuid 10605395_1.5.2.3.1
176 12:10:44.773443 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:10:44.773657 Creating lava-test-runner.conf files
179 12:10:44.773722 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605395/lava-overlay-0d6grisd/lava-10605395/0 for stage 0
180 12:10:44.773810 - 0_igt-kms-mediatek
181 12:10:44.773909 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:10:44.773997 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:10:44.781038 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:10:44.781148 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:10:44.781237 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:10:44.781325 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:10:44.781418 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:10:46.163349 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:10:46.163741 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 12:10:46.163886 extracting modules file /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605395/extract-overlay-ramdisk-gsjka4_m/ramdisk
191 12:10:46.402075 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:10:46.402251 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:10:46.402352 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605395/compress-overlay-refhymm9/overlay-1.5.2.4.tar.gz to ramdisk
194 12:10:46.402425 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605395/compress-overlay-refhymm9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605395/extract-overlay-ramdisk-gsjka4_m/ramdisk
195 12:10:46.408897 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:10:46.409016 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:10:46.409111 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:10:46.409204 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:10:46.409288 Building ramdisk /var/lib/lava/dispatcher/tmp/10605395/extract-overlay-ramdisk-gsjka4_m/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605395/extract-overlay-ramdisk-gsjka4_m/ramdisk
200 12:10:47.268884 >> 369045 blocks
201 12:10:53.399536 rename /var/lib/lava/dispatcher/tmp/10605395/extract-overlay-ramdisk-gsjka4_m/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/ramdisk/ramdisk.cpio.gz
202 12:10:53.399961 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:10:53.400090 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 12:10:53.400199 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 12:10:53.400311 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/kernel/Image'
206 12:11:06.725683 Returned 0 in 13 seconds
207 12:11:06.826309 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/kernel/image.itb
208 12:11:07.543216 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:11:07.543553 output: Created: Tue Jun 6 13:11:07 2023
210 12:11:07.543633 output: Image 0 (kernel-1)
211 12:11:07.543704 output: Description:
212 12:11:07.543769 output: Created: Tue Jun 6 13:11:07 2023
213 12:11:07.543832 output: Type: Kernel Image
214 12:11:07.543895 output: Compression: lzma compressed
215 12:11:07.543961 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
216 12:11:07.544027 output: Architecture: AArch64
217 12:11:07.544090 output: OS: Linux
218 12:11:07.544148 output: Load Address: 0x00000000
219 12:11:07.544210 output: Entry Point: 0x00000000
220 12:11:07.544266 output: Hash algo: crc32
221 12:11:07.544321 output: Hash value: fd97082e
222 12:11:07.544383 output: Image 1 (fdt-1)
223 12:11:07.544442 output: Description: mt8192-asurada-spherion-r0
224 12:11:07.544498 output: Created: Tue Jun 6 13:11:07 2023
225 12:11:07.544553 output: Type: Flat Device Tree
226 12:11:07.544609 output: Compression: uncompressed
227 12:11:07.544664 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:11:07.544720 output: Architecture: AArch64
229 12:11:07.544790 output: Hash algo: crc32
230 12:11:07.544847 output: Hash value: 1df858fa
231 12:11:07.544906 output: Image 2 (ramdisk-1)
232 12:11:07.544964 output: Description: unavailable
233 12:11:07.545019 output: Created: Tue Jun 6 13:11:07 2023
234 12:11:07.545078 output: Type: RAMDisk Image
235 12:11:07.545136 output: Compression: Unknown Compression
236 12:11:07.545195 output: Data Size: 56395188 Bytes = 55073.43 KiB = 53.78 MiB
237 12:11:07.545254 output: Architecture: AArch64
238 12:11:07.545311 output: OS: Linux
239 12:11:07.545367 output: Load Address: unavailable
240 12:11:07.545423 output: Entry Point: unavailable
241 12:11:07.545479 output: Hash algo: crc32
242 12:11:07.545534 output: Hash value: 69519553
243 12:11:07.545589 output: Default Configuration: 'conf-1'
244 12:11:07.545644 output: Configuration 0 (conf-1)
245 12:11:07.545700 output: Description: mt8192-asurada-spherion-r0
246 12:11:07.545756 output: Kernel: kernel-1
247 12:11:07.545811 output: Init Ramdisk: ramdisk-1
248 12:11:07.545867 output: FDT: fdt-1
249 12:11:07.545922 output: Loadables: kernel-1
250 12:11:07.545977 output:
251 12:11:07.546166 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:11:07.546267 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:11:07.546373 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 12:11:07.546472 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 12:11:07.546552 No LXC device requested
256 12:11:07.546634 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:11:07.546723 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 12:11:07.546808 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:11:07.546884 Checking files for TFTP limit of 4294967296 bytes.
260 12:11:07.547378 end: 1 tftp-deploy (duration 00:00:24) [common]
261 12:11:07.547488 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:11:07.547584 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:11:07.547711 substitutions:
264 12:11:07.547783 - {DTB}: 10605395/tftp-deploy-6cskc8xc/dtb/mt8192-asurada-spherion-r0.dtb
265 12:11:07.547852 - {INITRD}: 10605395/tftp-deploy-6cskc8xc/ramdisk/ramdisk.cpio.gz
266 12:11:07.547915 - {KERNEL}: 10605395/tftp-deploy-6cskc8xc/kernel/Image
267 12:11:07.547979 - {LAVA_MAC}: None
268 12:11:07.548041 - {PRESEED_CONFIG}: None
269 12:11:07.548105 - {PRESEED_LOCAL}: None
270 12:11:07.548166 - {RAMDISK}: 10605395/tftp-deploy-6cskc8xc/ramdisk/ramdisk.cpio.gz
271 12:11:07.548225 - {ROOT_PART}: None
272 12:11:07.548287 - {ROOT}: None
273 12:11:07.548349 - {SERVER_IP}: 192.168.201.1
274 12:11:07.548420 - {TEE}: None
275 12:11:07.548482 Parsed boot commands:
276 12:11:07.548541 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:11:07.548733 Parsed boot commands: tftpboot 192.168.201.1 10605395/tftp-deploy-6cskc8xc/kernel/image.itb 10605395/tftp-deploy-6cskc8xc/kernel/cmdline
278 12:11:07.548843 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:11:07.548931 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:11:07.549038 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:11:07.549145 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:11:07.549223 Not connected, no need to disconnect.
283 12:11:07.549304 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:11:07.549392 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:11:07.549466 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 12:11:07.552569 Setting prompt string to ['lava-test: # ']
287 12:11:07.552929 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:11:07.553046 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:11:07.553149 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:11:07.553245 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:11:07.553452 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 12:11:12.687363 >> Command sent successfully.
293 12:11:12.689684 Returned 0 in 5 seconds
294 12:11:12.790068 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:11:12.790771 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:11:12.790913 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:11:12.791044 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:11:12.791159 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:11:12.791269 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:11:12.791635 [Enter `^Ec?' for help]
302 12:11:12.964830
303 12:11:12.964994
304 12:11:12.965069 F0: 102B 0000
305 12:11:12.965136
306 12:11:12.965199 F3: 1001 0000 [0200]
307 12:11:12.967944
308 12:11:12.968029 F3: 1001 0000
309 12:11:12.968113
310 12:11:12.968180 F7: 102D 0000
311 12:11:12.968241
312 12:11:12.971555 F1: 0000 0000
313 12:11:12.971644
314 12:11:12.971714 V0: 0000 0000 [0001]
315 12:11:12.971782
316 12:11:12.971845 00: 0007 8000
317 12:11:12.971910
318 12:11:12.975552 01: 0000 0000
319 12:11:12.975672
320 12:11:12.975777 BP: 0C00 0209 [0000]
321 12:11:12.975840
322 12:11:12.979294 G0: 1182 0000
323 12:11:12.979413
324 12:11:12.979484 EC: 0000 0021 [4000]
325 12:11:12.979566
326 12:11:12.982824 S7: 0000 0000 [0000]
327 12:11:12.982916
328 12:11:12.983006 CC: 0000 0000 [0001]
329 12:11:12.983100
330 12:11:12.986025 T0: 0000 0040 [010F]
331 12:11:12.986101
332 12:11:12.986171 Jump to BL
333 12:11:12.986233
334 12:11:13.011902
335 12:11:13.011990
336 12:11:13.012066
337 12:11:13.018876 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:11:13.022799 ARM64: Exception handlers installed.
339 12:11:13.026379 ARM64: Testing exception
340 12:11:13.029517 ARM64: Done test exception
341 12:11:13.036711 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:11:13.044054 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:11:13.051723 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:11:13.061993 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:11:13.068919 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:11:13.079255 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:11:13.089472 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:11:13.095913 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:11:13.114555 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:11:13.117769 WDT: Last reset was cold boot
351 12:11:13.120917 SPI1(PAD0) initialized at 2873684 Hz
352 12:11:13.124444 SPI5(PAD0) initialized at 992727 Hz
353 12:11:13.127704 VBOOT: Loading verstage.
354 12:11:13.134283 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:11:13.137353 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:11:13.141017 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:11:13.144067 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:11:13.151871 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:11:13.158654 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:11:13.169295 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:11:13.169379
362 12:11:13.169446
363 12:11:13.179116 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:11:13.182818 ARM64: Exception handlers installed.
365 12:11:13.185810 ARM64: Testing exception
366 12:11:13.185894 ARM64: Done test exception
367 12:11:13.192309 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:11:13.195827 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:11:13.209974 Probing TPM: . done!
370 12:11:13.210088 TPM ready after 0 ms
371 12:11:13.216757 Connected to device vid:did:rid of 1ae0:0028:00
372 12:11:13.223672 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:11:13.282112 Initialized TPM device CR50 revision 0
374 12:11:13.294462 tlcl_send_startup: Startup return code is 0
375 12:11:13.294558 TPM: setup succeeded
376 12:11:13.305582 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:11:13.314749 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:11:13.324819 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:11:13.333940 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:11:13.337544 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:11:13.343682 in-header: 03 07 00 00 08 00 00 00
382 12:11:13.347719 in-data: aa e4 47 04 13 02 00 00
383 12:11:13.351331 Chrome EC: UHEPI supported
384 12:11:13.358589 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:11:13.362244 in-header: 03 ad 00 00 08 00 00 00
386 12:11:13.365767 in-data: 00 20 20 08 00 00 00 00
387 12:11:13.365866 Phase 1
388 12:11:13.369504 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:11:13.377009 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:11:13.380609 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:11:13.384343 Recovery requested (1009000e)
392 12:11:13.393537 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:11:13.399724 tlcl_extend: response is 0
394 12:11:13.409931 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:11:13.415644 tlcl_extend: response is 0
396 12:11:13.422927 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:11:13.443391 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:11:13.450102 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:11:13.450190
400 12:11:13.450260
401 12:11:13.459664 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:11:13.463226 ARM64: Exception handlers installed.
403 12:11:13.466364 ARM64: Testing exception
404 12:11:13.466450 ARM64: Done test exception
405 12:11:13.488744 pmic_efuse_setting: Set efuses in 11 msecs
406 12:11:13.492150 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:11:13.498878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:11:13.502325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:11:13.505907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:11:13.512619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:11:13.515757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:11:13.522484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:11:13.526243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:11:13.529514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:11:13.537249 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:11:13.541032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:11:13.544099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:11:13.550908 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:11:13.554461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:11:13.561008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:11:13.567704 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:11:13.571339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:11:13.578794 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:11:13.582247 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:11:13.589540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:11:13.596062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:11:13.599777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:11:13.606296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:11:13.609897 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:11:13.616356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:11:13.623097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:11:13.626666 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:11:13.633410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:11:13.636256 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:11:13.643507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:11:13.646414 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:11:13.652602 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:11:13.656157 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:11:13.662941 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:11:13.666036 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:11:13.672698 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:11:13.676289 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:11:13.682863 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:11:13.685957 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:11:13.692621 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:11:13.696094 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:11:13.699279 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:11:13.706085 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:11:13.709632 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:11:13.713330 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:11:13.717072 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:11:13.723749 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:11:13.726814 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:11:13.730301 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:11:13.733997 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:11:13.740417 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:11:13.743611 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:11:13.750307 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:11:13.760339 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:11:13.763843 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:11:13.773645 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:11:13.779989 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:11:13.786957 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:11:13.790039 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:11:13.793537 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:11:13.800676 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
467 12:11:13.807438 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:11:13.810952 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:11:13.814010 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:11:13.825351 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 12:11:13.835142 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 12:11:13.844309 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 12:11:13.853870 [RTC]rtc_get_frequency_meter,154: input=17, output=819
474 12:11:13.863487 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 12:11:13.866905 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 12:11:13.873599 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 12:11:13.876704 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 12:11:13.880204 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 12:11:13.883806 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 12:11:13.886892 ADC[4]: Raw value=902507 ID=7
481 12:11:13.889946 ADC[3]: Raw value=213179 ID=1
482 12:11:13.893515 RAM Code: 0x71
483 12:11:13.896641 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 12:11:13.900129 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 12:11:13.910228 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 12:11:13.916743 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 12:11:13.920221 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 12:11:13.923505 in-header: 03 07 00 00 08 00 00 00
489 12:11:13.926897 in-data: aa e4 47 04 13 02 00 00
490 12:11:13.930784 Chrome EC: UHEPI supported
491 12:11:13.937140 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 12:11:13.942514 in-header: 03 ed 00 00 08 00 00 00
493 12:11:13.946028 in-data: 80 20 60 08 00 00 00 00
494 12:11:13.949577 MRC: failed to locate region type 0.
495 12:11:13.957039 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 12:11:13.960781 DRAM-K: Running full calibration
497 12:11:13.964305 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 12:11:13.968026 header.status = 0x0
499 12:11:13.971817 header.version = 0x6 (expected: 0x6)
500 12:11:13.975710 header.size = 0xd00 (expected: 0xd00)
501 12:11:13.975797 header.flags = 0x0
502 12:11:13.982901 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 12:11:13.999543 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
504 12:11:14.006474 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 12:11:14.009573 dram_init: ddr_geometry: 2
506 12:11:14.013308 [EMI] MDL number = 2
507 12:11:14.013393 [EMI] Get MDL freq = 0
508 12:11:14.016335 dram_init: ddr_type: 0
509 12:11:14.016447 is_discrete_lpddr4: 1
510 12:11:14.019448 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 12:11:14.019561
512 12:11:14.019695
513 12:11:14.023060 [Bian_co] ETT version 0.0.0.1
514 12:11:14.029473 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 12:11:14.029559
516 12:11:14.032910 dramc_set_vcore_voltage set vcore to 650000
517 12:11:14.036137 Read voltage for 800, 4
518 12:11:14.036261 Vio18 = 0
519 12:11:14.036364 Vcore = 650000
520 12:11:14.039746 Vdram = 0
521 12:11:14.039858 Vddq = 0
522 12:11:14.039956 Vmddr = 0
523 12:11:14.042817 dram_init: config_dvfs: 1
524 12:11:14.046614 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 12:11:14.053977 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 12:11:14.057583 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 12:11:14.061172 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 12:11:14.065018 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 12:11:14.068825 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 12:11:14.068937 MEM_TYPE=3, freq_sel=18
531 12:11:14.071811 sv_algorithm_assistance_LP4_1600
532 12:11:14.079208 ============ PULL DRAM RESETB DOWN ============
533 12:11:14.082401 ========== PULL DRAM RESETB DOWN end =========
534 12:11:14.085634 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 12:11:14.088655 ===================================
536 12:11:14.092380 LPDDR4 DRAM CONFIGURATION
537 12:11:14.095479 ===================================
538 12:11:14.095628 EX_ROW_EN[0] = 0x0
539 12:11:14.099092 EX_ROW_EN[1] = 0x0
540 12:11:14.102023 LP4Y_EN = 0x0
541 12:11:14.102109 WORK_FSP = 0x0
542 12:11:14.105375 WL = 0x2
543 12:11:14.105487 RL = 0x2
544 12:11:14.109048 BL = 0x2
545 12:11:14.109140 RPST = 0x0
546 12:11:14.112250 RD_PRE = 0x0
547 12:11:14.112354 WR_PRE = 0x1
548 12:11:14.115301 WR_PST = 0x0
549 12:11:14.115423 DBI_WR = 0x0
550 12:11:14.118933 DBI_RD = 0x0
551 12:11:14.119056 OTF = 0x1
552 12:11:14.122050 ===================================
553 12:11:14.125218 ===================================
554 12:11:14.128847 ANA top config
555 12:11:14.132042 ===================================
556 12:11:14.132158 DLL_ASYNC_EN = 0
557 12:11:14.135195 ALL_SLAVE_EN = 1
558 12:11:14.138600 NEW_RANK_MODE = 1
559 12:11:14.142036 DLL_IDLE_MODE = 1
560 12:11:14.142153 LP45_APHY_COMB_EN = 1
561 12:11:14.145186 TX_ODT_DIS = 1
562 12:11:14.148772 NEW_8X_MODE = 1
563 12:11:14.151825 ===================================
564 12:11:14.155421 ===================================
565 12:11:14.158415 data_rate = 1600
566 12:11:14.161987 CKR = 1
567 12:11:14.165074 DQ_P2S_RATIO = 8
568 12:11:14.168692 ===================================
569 12:11:14.168805 CA_P2S_RATIO = 8
570 12:11:14.171702 DQ_CA_OPEN = 0
571 12:11:14.175086 DQ_SEMI_OPEN = 0
572 12:11:14.178376 CA_SEMI_OPEN = 0
573 12:11:14.181746 CA_FULL_RATE = 0
574 12:11:14.185045 DQ_CKDIV4_EN = 1
575 12:11:14.185160 CA_CKDIV4_EN = 1
576 12:11:14.188714 CA_PREDIV_EN = 0
577 12:11:14.191949 PH8_DLY = 0
578 12:11:14.195351 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 12:11:14.198498 DQ_AAMCK_DIV = 4
580 12:11:14.201719 CA_AAMCK_DIV = 4
581 12:11:14.201808 CA_ADMCK_DIV = 4
582 12:11:14.205255 DQ_TRACK_CA_EN = 0
583 12:11:14.208346 CA_PICK = 800
584 12:11:14.211762 CA_MCKIO = 800
585 12:11:14.215288 MCKIO_SEMI = 0
586 12:11:14.218338 PLL_FREQ = 3068
587 12:11:14.221863 DQ_UI_PI_RATIO = 32
588 12:11:14.221941 CA_UI_PI_RATIO = 0
589 12:11:14.224931 ===================================
590 12:11:14.228568 ===================================
591 12:11:14.231751 memory_type:LPDDR4
592 12:11:14.235209 GP_NUM : 10
593 12:11:14.235315 SRAM_EN : 1
594 12:11:14.238803 MD32_EN : 0
595 12:11:14.242732 ===================================
596 12:11:14.242838 [ANA_INIT] >>>>>>>>>>>>>>
597 12:11:14.246637 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 12:11:14.250214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:11:14.253830 ===================================
600 12:11:14.257574 data_rate = 1600,PCW = 0X7600
601 12:11:14.260719 ===================================
602 12:11:14.264432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 12:11:14.268068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 12:11:14.274738 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 12:11:14.278275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 12:11:14.281843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 12:11:14.284706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 12:11:14.288042 [ANA_INIT] flow start
609 12:11:14.288149 [ANA_INIT] PLL >>>>>>>>
610 12:11:14.291472 [ANA_INIT] PLL <<<<<<<<
611 12:11:14.294857 [ANA_INIT] MIDPI >>>>>>>>
612 12:11:14.298183 [ANA_INIT] MIDPI <<<<<<<<
613 12:11:14.298294 [ANA_INIT] DLL >>>>>>>>
614 12:11:14.301451 [ANA_INIT] flow end
615 12:11:14.304960 ============ LP4 DIFF to SE enter ============
616 12:11:14.308458 ============ LP4 DIFF to SE exit ============
617 12:11:14.311673 [ANA_INIT] <<<<<<<<<<<<<
618 12:11:14.314694 [Flow] Enable top DCM control >>>>>
619 12:11:14.318356 [Flow] Enable top DCM control <<<<<
620 12:11:14.321453 Enable DLL master slave shuffle
621 12:11:14.325080 ==============================================================
622 12:11:14.328156 Gating Mode config
623 12:11:14.334827 ==============================================================
624 12:11:14.334940 Config description:
625 12:11:14.344908 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 12:11:14.351771 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 12:11:14.358265 SELPH_MODE 0: By rank 1: By Phase
628 12:11:14.361557 ==============================================================
629 12:11:14.364970 GAT_TRACK_EN = 1
630 12:11:14.368051 RX_GATING_MODE = 2
631 12:11:14.371635 RX_GATING_TRACK_MODE = 2
632 12:11:14.374824 SELPH_MODE = 1
633 12:11:14.377965 PICG_EARLY_EN = 1
634 12:11:14.381408 VALID_LAT_VALUE = 1
635 12:11:14.384514 ==============================================================
636 12:11:14.387960 Enter into Gating configuration >>>>
637 12:11:14.391484 Exit from Gating configuration <<<<
638 12:11:14.394728 Enter into DVFS_PRE_config >>>>>
639 12:11:14.408047 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 12:11:14.408178 Exit from DVFS_PRE_config <<<<<
641 12:11:14.411604 Enter into PICG configuration >>>>
642 12:11:14.414662 Exit from PICG configuration <<<<
643 12:11:14.418103 [RX_INPUT] configuration >>>>>
644 12:11:14.421221 [RX_INPUT] configuration <<<<<
645 12:11:14.427741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 12:11:14.431499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 12:11:14.437747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 12:11:14.444607 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 12:11:14.451026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 12:11:14.457993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 12:11:14.461269 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 12:11:14.465053 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 12:11:14.469040 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 12:11:14.472149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 12:11:14.478611 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 12:11:14.482298 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 12:11:14.485954 ===================================
658 12:11:14.486074 LPDDR4 DRAM CONFIGURATION
659 12:11:14.489637 ===================================
660 12:11:14.493530 EX_ROW_EN[0] = 0x0
661 12:11:14.493647 EX_ROW_EN[1] = 0x0
662 12:11:14.497142 LP4Y_EN = 0x0
663 12:11:14.497226 WORK_FSP = 0x0
664 12:11:14.500831 WL = 0x2
665 12:11:14.500953 RL = 0x2
666 12:11:14.504332 BL = 0x2
667 12:11:14.504442 RPST = 0x0
668 12:11:14.507867 RD_PRE = 0x0
669 12:11:14.507963 WR_PRE = 0x1
670 12:11:14.511725 WR_PST = 0x0
671 12:11:14.511839 DBI_WR = 0x0
672 12:11:14.515342 DBI_RD = 0x0
673 12:11:14.515461 OTF = 0x1
674 12:11:14.519179 ===================================
675 12:11:14.522763 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 12:11:14.526502 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 12:11:14.529841 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 12:11:14.533644 ===================================
679 12:11:14.537318 LPDDR4 DRAM CONFIGURATION
680 12:11:14.541053 ===================================
681 12:11:14.541138 EX_ROW_EN[0] = 0x10
682 12:11:14.544682 EX_ROW_EN[1] = 0x0
683 12:11:14.544770 LP4Y_EN = 0x0
684 12:11:14.548318 WORK_FSP = 0x0
685 12:11:14.548400 WL = 0x2
686 12:11:14.551919 RL = 0x2
687 12:11:14.551999 BL = 0x2
688 12:11:14.555628 RPST = 0x0
689 12:11:14.555712 RD_PRE = 0x0
690 12:11:14.559637 WR_PRE = 0x1
691 12:11:14.559748 WR_PST = 0x0
692 12:11:14.563295 DBI_WR = 0x0
693 12:11:14.563377 DBI_RD = 0x0
694 12:11:14.563445 OTF = 0x1
695 12:11:14.567535 ===================================
696 12:11:14.574227 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 12:11:14.578843 nWR fixed to 40
698 12:11:14.582473 [ModeRegInit_LP4] CH0 RK0
699 12:11:14.582595 [ModeRegInit_LP4] CH0 RK1
700 12:11:14.586108 [ModeRegInit_LP4] CH1 RK0
701 12:11:14.586223 [ModeRegInit_LP4] CH1 RK1
702 12:11:14.589618 match AC timing 13
703 12:11:14.593270 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 12:11:14.596974 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 12:11:14.601129 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 12:11:14.608211 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 12:11:14.612140 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 12:11:14.612223 [EMI DOE] emi_dcm 0
709 12:11:14.615771 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 12:11:14.619277 ==
711 12:11:14.619392 Dram Type= 6, Freq= 0, CH_0, rank 0
712 12:11:14.626909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 12:11:14.626994 ==
714 12:11:14.630350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 12:11:14.637709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 12:11:14.645953 [CA 0] Center 38 (7~69) winsize 63
717 12:11:14.649507 [CA 1] Center 38 (7~69) winsize 63
718 12:11:14.653055 [CA 2] Center 35 (5~66) winsize 62
719 12:11:14.656944 [CA 3] Center 35 (5~66) winsize 62
720 12:11:14.660084 [CA 4] Center 34 (4~65) winsize 62
721 12:11:14.663495 [CA 5] Center 34 (3~65) winsize 63
722 12:11:14.663579
723 12:11:14.667731 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 12:11:14.667822
725 12:11:14.671414 [CATrainingPosCal] consider 1 rank data
726 12:11:14.675101 u2DelayCellTimex100 = 270/100 ps
727 12:11:14.678773 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 12:11:14.682521 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 12:11:14.686068 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 12:11:14.689769 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 12:11:14.693316 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
732 12:11:14.693403 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
733 12:11:14.697314
734 12:11:14.700592 CA PerBit enable=1, Macro0, CA PI delay=34
735 12:11:14.700710
736 12:11:14.700816 [CBTSetCACLKResult] CA Dly = 34
737 12:11:14.704229 CS Dly: 5 (0~36)
738 12:11:14.704334 ==
739 12:11:14.707792 Dram Type= 6, Freq= 0, CH_0, rank 1
740 12:11:14.711340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 12:11:14.711456 ==
742 12:11:14.718886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 12:11:14.722405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 12:11:14.732147 [CA 0] Center 38 (7~69) winsize 63
745 12:11:14.736209 [CA 1] Center 38 (8~69) winsize 62
746 12:11:14.739976 [CA 2] Center 36 (6~67) winsize 62
747 12:11:14.743550 [CA 3] Center 35 (5~66) winsize 62
748 12:11:14.747262 [CA 4] Center 35 (4~66) winsize 63
749 12:11:14.750952 [CA 5] Center 34 (4~65) winsize 62
750 12:11:14.751038
751 12:11:14.755027 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 12:11:14.755113
753 12:11:14.758684 [CATrainingPosCal] consider 2 rank data
754 12:11:14.758772 u2DelayCellTimex100 = 270/100 ps
755 12:11:14.762351 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 12:11:14.765741 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 12:11:14.769385 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 12:11:14.773084 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 12:11:14.776786 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 12:11:14.780529 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
761 12:11:14.780617
762 12:11:14.784214 CA PerBit enable=1, Macro0, CA PI delay=34
763 12:11:14.784334
764 12:11:14.787219 [CBTSetCACLKResult] CA Dly = 34
765 12:11:14.790700 CS Dly: 6 (0~38)
766 12:11:14.790808
767 12:11:14.794184 ----->DramcWriteLeveling(PI) begin...
768 12:11:14.794290 ==
769 12:11:14.797208 Dram Type= 6, Freq= 0, CH_0, rank 0
770 12:11:14.800681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 12:11:14.800787 ==
772 12:11:14.803826 Write leveling (Byte 0): 30 => 30
773 12:11:14.807484 Write leveling (Byte 1): 29 => 29
774 12:11:14.810946 DramcWriteLeveling(PI) end<-----
775 12:11:14.811033
776 12:11:14.811103 ==
777 12:11:14.813872 Dram Type= 6, Freq= 0, CH_0, rank 0
778 12:11:14.817963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 12:11:14.818080 ==
780 12:11:14.820957 [Gating] SW mode calibration
781 12:11:14.828086 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 12:11:14.834796 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 12:11:14.838091 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 12:11:14.841687 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
785 12:11:14.849054 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:11:14.852701 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:11:14.855791 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:11:14.858815 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:11:14.865703 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:11:14.868706 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:11:14.871992 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:11:14.878992 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:11:14.882197 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:11:14.885742 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:11:14.892040 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:11:14.895664 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:11:14.898715 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:11:14.902207 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:11:14.908785 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:11:14.912323 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
801 12:11:14.915231 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 12:11:14.921821 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:11:14.925256 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:11:14.928707 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:11:14.935179 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:11:14.938831 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:11:14.941873 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:11:14.948655 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
809 12:11:14.951725 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 12:11:14.955274 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
811 12:11:14.961599 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:11:14.965186 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:11:14.968429 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 12:11:14.975346 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:11:14.978334 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:11:14.981826 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
817 12:11:14.988302 0 10 8 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
818 12:11:14.991857 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
819 12:11:14.995041 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:11:15.001892 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:11:15.004956 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:11:15.008464 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:11:15.015266 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:11:15.018340 0 11 4 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
825 12:11:15.021901 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
826 12:11:15.028478 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
827 12:11:15.031338 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:11:15.034994 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:11:15.041486 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:11:15.045067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:11:15.048131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 12:11:15.051335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 12:11:15.058530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 12:11:15.061706 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:11:15.064777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:11:15.071809 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:11:15.075026 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:11:15.078386 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:11:15.084713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:11:15.087897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:11:15.091584 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:11:15.098418 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:11:15.101599 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:11:15.104872 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:11:15.111444 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:11:15.114506 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:11:15.118278 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:11:15.124522 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 12:11:15.127954 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 12:11:15.131539 Total UI for P1: 0, mck2ui 16
851 12:11:15.134577 best dqsien dly found for B0: ( 0, 14, 4)
852 12:11:15.137908 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 12:11:15.141340 Total UI for P1: 0, mck2ui 16
854 12:11:15.144778 best dqsien dly found for B1: ( 0, 14, 6)
855 12:11:15.147874 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 12:11:15.151391 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
857 12:11:15.151507
858 12:11:15.154586 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 12:11:15.161314 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
860 12:11:15.161428 [Gating] SW calibration Done
861 12:11:15.161542 ==
862 12:11:15.164679 Dram Type= 6, Freq= 0, CH_0, rank 0
863 12:11:15.171523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 12:11:15.171638 ==
865 12:11:15.171741 RX Vref Scan: 0
866 12:11:15.171842
867 12:11:15.174630 RX Vref 0 -> 0, step: 1
868 12:11:15.174733
869 12:11:15.178215 RX Delay -130 -> 252, step: 16
870 12:11:15.181760 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 12:11:15.184730 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 12:11:15.188245 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 12:11:15.194947 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 12:11:15.197960 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 12:11:15.201721 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 12:11:15.204793 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
877 12:11:15.208375 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 12:11:15.214857 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 12:11:15.217909 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
880 12:11:15.221447 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 12:11:15.225027 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 12:11:15.228128 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 12:11:15.234570 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 12:11:15.238012 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 12:11:15.241260 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
886 12:11:15.241343 ==
887 12:11:15.244649 Dram Type= 6, Freq= 0, CH_0, rank 0
888 12:11:15.248054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 12:11:15.248163 ==
890 12:11:15.251193 DQS Delay:
891 12:11:15.251296 DQS0 = 0, DQS1 = 0
892 12:11:15.254699 DQM Delay:
893 12:11:15.254800 DQM0 = 90, DQM1 = 80
894 12:11:15.254897 DQ Delay:
895 12:11:15.257799 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 12:11:15.261328 DQ4 =85, DQ5 =77, DQ6 =109, DQ7 =101
897 12:11:15.264316 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
898 12:11:15.267899 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
899 12:11:15.268014
900 12:11:15.271184
901 12:11:15.271290 ==
902 12:11:15.274258 Dram Type= 6, Freq= 0, CH_0, rank 0
903 12:11:15.277945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 12:11:15.278056 ==
905 12:11:15.278152
906 12:11:15.278254
907 12:11:15.281032 TX Vref Scan disable
908 12:11:15.281143 == TX Byte 0 ==
909 12:11:15.284132 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 12:11:15.291072 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 12:11:15.291185 == TX Byte 1 ==
912 12:11:15.294160 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
913 12:11:15.301104 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
914 12:11:15.301213 ==
915 12:11:15.304216 Dram Type= 6, Freq= 0, CH_0, rank 0
916 12:11:15.307781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 12:11:15.307887 ==
918 12:11:15.320857 TX Vref=22, minBit 8, minWin=26, winSum=436
919 12:11:15.324523 TX Vref=24, minBit 9, minWin=27, winSum=446
920 12:11:15.327741 TX Vref=26, minBit 6, minWin=27, winSum=445
921 12:11:15.331267 TX Vref=28, minBit 3, minWin=28, winSum=452
922 12:11:15.334748 TX Vref=30, minBit 4, minWin=28, winSum=454
923 12:11:15.337855 TX Vref=32, minBit 13, minWin=27, winSum=453
924 12:11:15.344494 [TxChooseVref] Worse bit 4, Min win 28, Win sum 454, Final Vref 30
925 12:11:15.344603
926 12:11:15.347937 Final TX Range 1 Vref 30
927 12:11:15.348021
928 12:11:15.348088 ==
929 12:11:15.351023 Dram Type= 6, Freq= 0, CH_0, rank 0
930 12:11:15.354175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 12:11:15.354284 ==
932 12:11:15.354382
933 12:11:15.357808
934 12:11:15.357894 TX Vref Scan disable
935 12:11:15.361278 == TX Byte 0 ==
936 12:11:15.364224 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 12:11:15.367897 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 12:11:15.370874 == TX Byte 1 ==
939 12:11:15.374448 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
940 12:11:15.380842 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
941 12:11:15.380947
942 12:11:15.381023 [DATLAT]
943 12:11:15.381089 Freq=800, CH0 RK0
944 12:11:15.381150
945 12:11:15.384061 DATLAT Default: 0xa
946 12:11:15.384161 0, 0xFFFF, sum = 0
947 12:11:15.387581 1, 0xFFFF, sum = 0
948 12:11:15.387684 2, 0xFFFF, sum = 0
949 12:11:15.390608 3, 0xFFFF, sum = 0
950 12:11:15.394118 4, 0xFFFF, sum = 0
951 12:11:15.394194 5, 0xFFFF, sum = 0
952 12:11:15.397639 6, 0xFFFF, sum = 0
953 12:11:15.397722 7, 0xFFFF, sum = 0
954 12:11:15.400924 8, 0xFFFF, sum = 0
955 12:11:15.400999 9, 0x0, sum = 1
956 12:11:15.401064 10, 0x0, sum = 2
957 12:11:15.404025 11, 0x0, sum = 3
958 12:11:15.404130 12, 0x0, sum = 4
959 12:11:15.407740 best_step = 10
960 12:11:15.407840
961 12:11:15.407932 ==
962 12:11:15.410806 Dram Type= 6, Freq= 0, CH_0, rank 0
963 12:11:15.413964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 12:11:15.414063 ==
965 12:11:15.417549 RX Vref Scan: 1
966 12:11:15.417626
967 12:11:15.420516 Set Vref Range= 32 -> 127
968 12:11:15.420618
969 12:11:15.420710 RX Vref 32 -> 127, step: 1
970 12:11:15.420812
971 12:11:15.424052 RX Delay -79 -> 252, step: 8
972 12:11:15.424122
973 12:11:15.427172 Set Vref, RX VrefLevel [Byte0]: 32
974 12:11:15.430926 [Byte1]: 32
975 12:11:15.431027
976 12:11:15.433986 Set Vref, RX VrefLevel [Byte0]: 33
977 12:11:15.437410 [Byte1]: 33
978 12:11:15.441393
979 12:11:15.441497 Set Vref, RX VrefLevel [Byte0]: 34
980 12:11:15.447454 [Byte1]: 34
981 12:11:15.447556
982 12:11:15.450841 Set Vref, RX VrefLevel [Byte0]: 35
983 12:11:15.454303 [Byte1]: 35
984 12:11:15.454376
985 12:11:15.457791 Set Vref, RX VrefLevel [Byte0]: 36
986 12:11:15.460972 [Byte1]: 36
987 12:11:15.461064
988 12:11:15.464389 Set Vref, RX VrefLevel [Byte0]: 37
989 12:11:15.467885 [Byte1]: 37
990 12:11:15.471338
991 12:11:15.471444 Set Vref, RX VrefLevel [Byte0]: 38
992 12:11:15.474537 [Byte1]: 38
993 12:11:15.478846
994 12:11:15.478952 Set Vref, RX VrefLevel [Byte0]: 39
995 12:11:15.482442 [Byte1]: 39
996 12:11:15.486625
997 12:11:15.486731 Set Vref, RX VrefLevel [Byte0]: 40
998 12:11:15.490098 [Byte1]: 40
999 12:11:15.493876
1000 12:11:15.497556 Set Vref, RX VrefLevel [Byte0]: 41
1001 12:11:15.497636 [Byte1]: 41
1002 12:11:15.501910
1003 12:11:15.502016 Set Vref, RX VrefLevel [Byte0]: 42
1004 12:11:15.505079 [Byte1]: 42
1005 12:11:15.509259
1006 12:11:15.509336 Set Vref, RX VrefLevel [Byte0]: 43
1007 12:11:15.512497 [Byte1]: 43
1008 12:11:15.516846
1009 12:11:15.516930 Set Vref, RX VrefLevel [Byte0]: 44
1010 12:11:15.519927 [Byte1]: 44
1011 12:11:15.524067
1012 12:11:15.524159 Set Vref, RX VrefLevel [Byte0]: 45
1013 12:11:15.527591 [Byte1]: 45
1014 12:11:15.531762
1015 12:11:15.531879 Set Vref, RX VrefLevel [Byte0]: 46
1016 12:11:15.534924 [Byte1]: 46
1017 12:11:15.539427
1018 12:11:15.539532 Set Vref, RX VrefLevel [Byte0]: 47
1019 12:11:15.542451 [Byte1]: 47
1020 12:11:15.546934
1021 12:11:15.547021 Set Vref, RX VrefLevel [Byte0]: 48
1022 12:11:15.550013 [Byte1]: 48
1023 12:11:15.554513
1024 12:11:15.554623 Set Vref, RX VrefLevel [Byte0]: 49
1025 12:11:15.557510 [Byte1]: 49
1026 12:11:15.562047
1027 12:11:15.562132 Set Vref, RX VrefLevel [Byte0]: 50
1028 12:11:15.565133 [Byte1]: 50
1029 12:11:15.569240
1030 12:11:15.569318 Set Vref, RX VrefLevel [Byte0]: 51
1031 12:11:15.572745 [Byte1]: 51
1032 12:11:15.577018
1033 12:11:15.577095 Set Vref, RX VrefLevel [Byte0]: 52
1034 12:11:15.580533 [Byte1]: 52
1035 12:11:15.584807
1036 12:11:15.584884 Set Vref, RX VrefLevel [Byte0]: 53
1037 12:11:15.587885 [Byte1]: 53
1038 12:11:15.592027
1039 12:11:15.592131 Set Vref, RX VrefLevel [Byte0]: 54
1040 12:11:15.595148 [Byte1]: 54
1041 12:11:15.599755
1042 12:11:15.599862 Set Vref, RX VrefLevel [Byte0]: 55
1043 12:11:15.602719 [Byte1]: 55
1044 12:11:15.607266
1045 12:11:15.607385 Set Vref, RX VrefLevel [Byte0]: 56
1046 12:11:15.610489 [Byte1]: 56
1047 12:11:15.614711
1048 12:11:15.614817 Set Vref, RX VrefLevel [Byte0]: 57
1049 12:11:15.617780 [Byte1]: 57
1050 12:11:15.622446
1051 12:11:15.622548 Set Vref, RX VrefLevel [Byte0]: 58
1052 12:11:15.625525 [Byte1]: 58
1053 12:11:15.629701
1054 12:11:15.629802 Set Vref, RX VrefLevel [Byte0]: 59
1055 12:11:15.633126 [Byte1]: 59
1056 12:11:15.637476
1057 12:11:15.637583 Set Vref, RX VrefLevel [Byte0]: 60
1058 12:11:15.640656 [Byte1]: 60
1059 12:11:15.644674
1060 12:11:15.644783 Set Vref, RX VrefLevel [Byte0]: 61
1061 12:11:15.648333 [Byte1]: 61
1062 12:11:15.652220
1063 12:11:15.652323 Set Vref, RX VrefLevel [Byte0]: 62
1064 12:11:15.655804 [Byte1]: 62
1065 12:11:15.659763
1066 12:11:15.659865 Set Vref, RX VrefLevel [Byte0]: 63
1067 12:11:15.663170 [Byte1]: 63
1068 12:11:15.667409
1069 12:11:15.667515 Set Vref, RX VrefLevel [Byte0]: 64
1070 12:11:15.671042 [Byte1]: 64
1071 12:11:15.675116
1072 12:11:15.675228 Set Vref, RX VrefLevel [Byte0]: 65
1073 12:11:15.678181 [Byte1]: 65
1074 12:11:15.682415
1075 12:11:15.682527 Set Vref, RX VrefLevel [Byte0]: 66
1076 12:11:15.686008 [Byte1]: 66
1077 12:11:15.690112
1078 12:11:15.690192 Set Vref, RX VrefLevel [Byte0]: 67
1079 12:11:15.693706 [Byte1]: 67
1080 12:11:15.697858
1081 12:11:15.697946 Set Vref, RX VrefLevel [Byte0]: 68
1082 12:11:15.700937 [Byte1]: 68
1083 12:11:15.705623
1084 12:11:15.705698 Set Vref, RX VrefLevel [Byte0]: 69
1085 12:11:15.708962 [Byte1]: 69
1086 12:11:15.712951
1087 12:11:15.713060 Set Vref, RX VrefLevel [Byte0]: 70
1088 12:11:15.716047 [Byte1]: 70
1089 12:11:15.720525
1090 12:11:15.720638 Set Vref, RX VrefLevel [Byte0]: 71
1091 12:11:15.723886 [Byte1]: 71
1092 12:11:15.727934
1093 12:11:15.728010 Set Vref, RX VrefLevel [Byte0]: 72
1094 12:11:15.731134 [Byte1]: 72
1095 12:11:15.735493
1096 12:11:15.735599 Set Vref, RX VrefLevel [Byte0]: 73
1097 12:11:15.738542 [Byte1]: 73
1098 12:11:15.743340
1099 12:11:15.743445 Set Vref, RX VrefLevel [Byte0]: 74
1100 12:11:15.746536 [Byte1]: 74
1101 12:11:15.750734
1102 12:11:15.750843 Set Vref, RX VrefLevel [Byte0]: 75
1103 12:11:15.753741 [Byte1]: 75
1104 12:11:15.757973
1105 12:11:15.758080 Set Vref, RX VrefLevel [Byte0]: 76
1106 12:11:15.761512 [Byte1]: 76
1107 12:11:15.765470
1108 12:11:15.765546 Set Vref, RX VrefLevel [Byte0]: 77
1109 12:11:15.768968 [Byte1]: 77
1110 12:11:15.773121
1111 12:11:15.773222 Set Vref, RX VrefLevel [Byte0]: 78
1112 12:11:15.776757 [Byte1]: 78
1113 12:11:15.780732
1114 12:11:15.780823 Set Vref, RX VrefLevel [Byte0]: 79
1115 12:11:15.783954 [Byte1]: 79
1116 12:11:15.788022
1117 12:11:15.788104 Set Vref, RX VrefLevel [Byte0]: 80
1118 12:11:15.791712 [Byte1]: 80
1119 12:11:15.795872
1120 12:11:15.795956 Final RX Vref Byte 0 = 61 to rank0
1121 12:11:15.799170 Final RX Vref Byte 1 = 61 to rank0
1122 12:11:15.802412 Final RX Vref Byte 0 = 61 to rank1
1123 12:11:15.806074 Final RX Vref Byte 1 = 61 to rank1==
1124 12:11:15.809125 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 12:11:15.815773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 12:11:15.815887 ==
1127 12:11:15.815985 DQS Delay:
1128 12:11:15.816086 DQS0 = 0, DQS1 = 0
1129 12:11:15.818905 DQM Delay:
1130 12:11:15.819008 DQM0 = 93, DQM1 = 83
1131 12:11:15.822567 DQ Delay:
1132 12:11:15.825883 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1133 12:11:15.828953 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1134 12:11:15.832441 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1135 12:11:15.835623 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1136 12:11:15.835733
1137 12:11:15.835853
1138 12:11:15.842814 [DQSOSCAuto] RK0, (LSB)MR18= 0x403c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1139 12:11:15.845750 CH0 RK0: MR19=606, MR18=403C
1140 12:11:15.852562 CH0_RK0: MR19=0x606, MR18=0x403C, DQSOSC=393, MR23=63, INC=95, DEC=63
1141 12:11:15.852642
1142 12:11:15.855945 ----->DramcWriteLeveling(PI) begin...
1143 12:11:15.856034 ==
1144 12:11:15.859344 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 12:11:15.862381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 12:11:15.862473 ==
1147 12:11:15.866047 Write leveling (Byte 0): 29 => 29
1148 12:11:15.869216 Write leveling (Byte 1): 29 => 29
1149 12:11:15.872744 DramcWriteLeveling(PI) end<-----
1150 12:11:15.872866
1151 12:11:15.872963 ==
1152 12:11:15.875812 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 12:11:15.879536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 12:11:15.879623 ==
1155 12:11:15.882505 [Gating] SW mode calibration
1156 12:11:15.889228 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 12:11:15.933230 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 12:11:15.933524 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 12:11:15.933606 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1160 12:11:15.933699 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:11:15.933765 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:11:15.933840 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:11:15.933903 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:11:15.933964 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:11:15.934034 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:11:15.934095 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:11:15.977269 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:11:15.977544 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:11:15.977642 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:11:15.977728 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:11:15.977795 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:11:15.977858 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:11:15.978361 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:11:15.978625 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:11:15.978697 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1176 12:11:15.978801 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:11:16.012440 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:11:16.012973 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:11:16.013239 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:11:16.013312 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:11:16.013377 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:11:16.013439 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:11:16.013511 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:11:16.016755 0 9 8 | B1->B0 | 2e2e 3333 | 1 1 | (1 1) (1 1)
1185 12:11:16.019857 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:11:16.023343 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:11:16.026566 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:11:16.030077 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 12:11:16.036696 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 12:11:16.039975 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 12:11:16.043026 0 10 4 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 1)
1192 12:11:16.050012 0 10 8 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
1193 12:11:16.053082 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:11:16.056673 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:11:16.063300 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:11:16.066824 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:11:16.070502 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 12:11:16.073826 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 12:11:16.081135 0 11 4 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
1200 12:11:16.084217 0 11 8 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
1201 12:11:16.087834 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:11:16.094700 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:11:16.098400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:11:16.101485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 12:11:16.104595 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 12:11:16.111295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 12:11:16.114740 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1208 12:11:16.117856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 12:11:16.124509 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:11:16.128085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:11:16.131129 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:11:16.137826 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:11:16.141334 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:11:16.144476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:11:16.151203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:11:16.154610 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:11:16.157684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:11:16.164496 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:11:16.168005 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:11:16.171486 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:11:16.174388 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:11:16.181236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:11:16.184556 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1224 12:11:16.187547 Total UI for P1: 0, mck2ui 16
1225 12:11:16.191121 best dqsien dly found for B0: ( 0, 14, 2)
1226 12:11:16.194257 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 12:11:16.197869 Total UI for P1: 0, mck2ui 16
1228 12:11:16.200883 best dqsien dly found for B1: ( 0, 14, 4)
1229 12:11:16.204172 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1230 12:11:16.210778 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1231 12:11:16.210861
1232 12:11:16.214356 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1233 12:11:16.217384 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1234 12:11:16.220954 [Gating] SW calibration Done
1235 12:11:16.221037 ==
1236 12:11:16.224067 Dram Type= 6, Freq= 0, CH_0, rank 1
1237 12:11:16.227477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1238 12:11:16.227565 ==
1239 12:11:16.227633 RX Vref Scan: 0
1240 12:11:16.230776
1241 12:11:16.230861 RX Vref 0 -> 0, step: 1
1242 12:11:16.230930
1243 12:11:16.233966 RX Delay -130 -> 252, step: 16
1244 12:11:16.237587 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1245 12:11:16.240726 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1246 12:11:16.247482 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1247 12:11:16.250561 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1248 12:11:16.254218 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1249 12:11:16.257476 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1250 12:11:16.260462 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1251 12:11:16.267248 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1252 12:11:16.270872 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1253 12:11:16.274114 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1254 12:11:16.277118 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1255 12:11:16.280845 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1256 12:11:16.287469 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1257 12:11:16.290582 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1258 12:11:16.294122 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1259 12:11:16.297193 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1260 12:11:16.297276 ==
1261 12:11:16.300615 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 12:11:16.307282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 12:11:16.307368 ==
1264 12:11:16.307438 DQS Delay:
1265 12:11:16.310412 DQS0 = 0, DQS1 = 0
1266 12:11:16.310517 DQM Delay:
1267 12:11:16.310609 DQM0 = 90, DQM1 = 79
1268 12:11:16.313667 DQ Delay:
1269 12:11:16.316883 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1270 12:11:16.320544 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =109
1271 12:11:16.323687 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1272 12:11:16.326819 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1273 12:11:16.326904
1274 12:11:16.326972
1275 12:11:16.327035 ==
1276 12:11:16.330446 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 12:11:16.333475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 12:11:16.333562 ==
1279 12:11:16.333650
1280 12:11:16.333726
1281 12:11:16.337020 TX Vref Scan disable
1282 12:11:16.340217 == TX Byte 0 ==
1283 12:11:16.343369 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1284 12:11:16.346985 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1285 12:11:16.350208 == TX Byte 1 ==
1286 12:11:16.353242 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1287 12:11:16.356974 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1288 12:11:16.357048 ==
1289 12:11:16.360096 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 12:11:16.363454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 12:11:16.366491 ==
1292 12:11:16.378025 TX Vref=22, minBit 8, minWin=27, winSum=442
1293 12:11:16.381135 TX Vref=24, minBit 8, minWin=27, winSum=444
1294 12:11:16.384718 TX Vref=26, minBit 8, minWin=27, winSum=449
1295 12:11:16.387684 TX Vref=28, minBit 8, minWin=27, winSum=448
1296 12:11:16.391279 TX Vref=30, minBit 8, minWin=27, winSum=453
1297 12:11:16.394211 TX Vref=32, minBit 1, minWin=28, winSum=453
1298 12:11:16.401257 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 32
1299 12:11:16.401365
1300 12:11:16.404436 Final TX Range 1 Vref 32
1301 12:11:16.404535
1302 12:11:16.404626 ==
1303 12:11:16.407915 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 12:11:16.410911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 12:11:16.410984 ==
1306 12:11:16.414579
1307 12:11:16.414650
1308 12:11:16.414710 TX Vref Scan disable
1309 12:11:16.417702 == TX Byte 0 ==
1310 12:11:16.420799 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1311 12:11:16.427634 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1312 12:11:16.427707 == TX Byte 1 ==
1313 12:11:16.430827 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1314 12:11:16.437566 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1315 12:11:16.437644
1316 12:11:16.437706 [DATLAT]
1317 12:11:16.437766 Freq=800, CH0 RK1
1318 12:11:16.437833
1319 12:11:16.441108 DATLAT Default: 0xa
1320 12:11:16.441180 0, 0xFFFF, sum = 0
1321 12:11:16.444300 1, 0xFFFF, sum = 0
1322 12:11:16.444373 2, 0xFFFF, sum = 0
1323 12:11:16.447255 3, 0xFFFF, sum = 0
1324 12:11:16.451024 4, 0xFFFF, sum = 0
1325 12:11:16.451098 5, 0xFFFF, sum = 0
1326 12:11:16.454202 6, 0xFFFF, sum = 0
1327 12:11:16.454276 7, 0xFFFF, sum = 0
1328 12:11:16.457350 8, 0xFFFF, sum = 0
1329 12:11:16.457424 9, 0x0, sum = 1
1330 12:11:16.457487 10, 0x0, sum = 2
1331 12:11:16.460956 11, 0x0, sum = 3
1332 12:11:16.461062 12, 0x0, sum = 4
1333 12:11:16.464020 best_step = 10
1334 12:11:16.464121
1335 12:11:16.464216 ==
1336 12:11:16.467498 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 12:11:16.470662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 12:11:16.470745 ==
1339 12:11:16.474259 RX Vref Scan: 0
1340 12:11:16.474341
1341 12:11:16.474406 RX Vref 0 -> 0, step: 1
1342 12:11:16.477512
1343 12:11:16.477594 RX Delay -79 -> 252, step: 8
1344 12:11:16.484219 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1345 12:11:16.487810 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1346 12:11:16.490936 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1347 12:11:16.494444 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1348 12:11:16.497506 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1349 12:11:16.504128 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1350 12:11:16.507816 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1351 12:11:16.510712 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1352 12:11:16.514194 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1353 12:11:16.517215 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1354 12:11:16.524020 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1355 12:11:16.527235 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1356 12:11:16.530844 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1357 12:11:16.533920 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1358 12:11:16.537599 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1359 12:11:16.544135 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1360 12:11:16.544219 ==
1361 12:11:16.547309 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 12:11:16.550945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 12:11:16.551031 ==
1364 12:11:16.551098 DQS Delay:
1365 12:11:16.554217 DQS0 = 0, DQS1 = 0
1366 12:11:16.554301 DQM Delay:
1367 12:11:16.557441 DQM0 = 90, DQM1 = 81
1368 12:11:16.557525 DQ Delay:
1369 12:11:16.560643 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1370 12:11:16.564280 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1371 12:11:16.567433 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1372 12:11:16.570450 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1373 12:11:16.570534
1374 12:11:16.570601
1375 12:11:16.580908 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1376 12:11:16.580995 CH0 RK1: MR19=606, MR18=421D
1377 12:11:16.587568 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1378 12:11:16.590687 [RxdqsGatingPostProcess] freq 800
1379 12:11:16.597289 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1380 12:11:16.600661 Pre-setting of DQS Precalculation
1381 12:11:16.604201 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1382 12:11:16.604289 ==
1383 12:11:16.607190 Dram Type= 6, Freq= 0, CH_1, rank 0
1384 12:11:16.610678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 12:11:16.613724 ==
1386 12:11:16.617093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1387 12:11:16.623768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1388 12:11:16.633033 [CA 0] Center 36 (6~67) winsize 62
1389 12:11:16.636159 [CA 1] Center 37 (6~68) winsize 63
1390 12:11:16.639142 [CA 2] Center 35 (5~65) winsize 61
1391 12:11:16.642895 [CA 3] Center 34 (4~65) winsize 62
1392 12:11:16.646165 [CA 4] Center 34 (4~65) winsize 62
1393 12:11:16.649233 [CA 5] Center 34 (4~65) winsize 62
1394 12:11:16.649319
1395 12:11:16.652501 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1396 12:11:16.652585
1397 12:11:16.656028 [CATrainingPosCal] consider 1 rank data
1398 12:11:16.659207 u2DelayCellTimex100 = 270/100 ps
1399 12:11:16.662900 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1400 12:11:16.669086 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1401 12:11:16.672748 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 12:11:16.675897 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1403 12:11:16.678938 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1404 12:11:16.682662 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1405 12:11:16.682749
1406 12:11:16.685824 CA PerBit enable=1, Macro0, CA PI delay=34
1407 12:11:16.685909
1408 12:11:16.688905 [CBTSetCACLKResult] CA Dly = 34
1409 12:11:16.689017 CS Dly: 5 (0~36)
1410 12:11:16.692428 ==
1411 12:11:16.695591 Dram Type= 6, Freq= 0, CH_1, rank 1
1412 12:11:16.699132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 12:11:16.699246 ==
1414 12:11:16.702566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1415 12:11:16.708980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1416 12:11:16.719064 [CA 0] Center 37 (7~67) winsize 61
1417 12:11:16.722142 [CA 1] Center 37 (6~68) winsize 63
1418 12:11:16.725389 [CA 2] Center 35 (5~66) winsize 62
1419 12:11:16.728959 [CA 3] Center 34 (4~65) winsize 62
1420 12:11:16.732539 [CA 4] Center 35 (5~65) winsize 61
1421 12:11:16.735737 [CA 5] Center 34 (4~64) winsize 61
1422 12:11:16.735852
1423 12:11:16.739534 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1424 12:11:16.739638
1425 12:11:16.743689 [CATrainingPosCal] consider 2 rank data
1426 12:11:16.746912 u2DelayCellTimex100 = 270/100 ps
1427 12:11:16.750825 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1428 12:11:16.754366 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1429 12:11:16.758540 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 12:11:16.762211 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 12:11:16.765862 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1432 12:11:16.769516 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1433 12:11:16.769600
1434 12:11:16.772715 CA PerBit enable=1, Macro0, CA PI delay=34
1435 12:11:16.772820
1436 12:11:16.775837 [CBTSetCACLKResult] CA Dly = 34
1437 12:11:16.775921 CS Dly: 6 (0~38)
1438 12:11:16.775990
1439 12:11:16.779450 ----->DramcWriteLeveling(PI) begin...
1440 12:11:16.779536 ==
1441 12:11:16.782449 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 12:11:16.789128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 12:11:16.789214 ==
1444 12:11:16.792745 Write leveling (Byte 0): 27 => 27
1445 12:11:16.795808 Write leveling (Byte 1): 29 => 29
1446 12:11:16.795895 DramcWriteLeveling(PI) end<-----
1447 12:11:16.795963
1448 12:11:16.798941 ==
1449 12:11:16.802554 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 12:11:16.805639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 12:11:16.805725 ==
1452 12:11:16.809086 [Gating] SW mode calibration
1453 12:11:16.815749 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1454 12:11:16.819239 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1455 12:11:16.825660 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 12:11:16.829165 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1457 12:11:16.832181 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:11:16.839213 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:11:16.842280 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:11:16.845849 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:11:16.852518 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:11:16.855586 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:11:16.859142 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:11:16.865977 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:11:16.868937 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:11:16.872479 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:11:16.879052 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:11:16.882652 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:11:16.885621 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:11:16.889130 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:11:16.895850 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1472 12:11:16.898899 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:11:16.902466 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:11:16.908962 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:11:16.912465 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:11:16.915491 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:11:16.922483 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:11:16.925715 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:11:16.928692 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:11:16.935782 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1481 12:11:16.938845 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1482 12:11:16.941993 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:11:16.948827 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:11:16.951943 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:11:16.955612 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 12:11:16.962018 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 12:11:16.965608 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1488 12:11:16.968687 0 10 4 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
1489 12:11:16.975679 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:11:16.978858 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:11:16.981946 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:11:16.988613 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:11:16.992169 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:11:16.995190 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:11:17.001985 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 12:11:17.005466 0 11 4 | B1->B0 | 3131 3232 | 1 0 | (0 0) (0 0)
1497 12:11:17.008541 0 11 8 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1498 12:11:17.015523 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:11:17.018850 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:11:17.021723 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:11:17.025201 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:11:17.031761 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 12:11:17.035110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1504 12:11:17.038642 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1505 12:11:17.044908 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:11:17.048666 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:11:17.051806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:11:17.058468 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:11:17.061948 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:11:17.065248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:11:17.071877 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:11:17.074979 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:11:17.078636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:11:17.085333 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:11:17.088480 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:11:17.092039 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:11:17.098702 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:11:17.101820 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:11:17.104877 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:11:17.111506 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1521 12:11:17.111592 Total UI for P1: 0, mck2ui 16
1522 12:11:17.118483 best dqsien dly found for B0: ( 0, 14, 2)
1523 12:11:17.121449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 12:11:17.124924 Total UI for P1: 0, mck2ui 16
1525 12:11:17.128331 best dqsien dly found for B1: ( 0, 14, 4)
1526 12:11:17.131428 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1527 12:11:17.135074 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1528 12:11:17.135176
1529 12:11:17.138111 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1530 12:11:17.141540 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1531 12:11:17.144696 [Gating] SW calibration Done
1532 12:11:17.144800 ==
1533 12:11:17.148186 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 12:11:17.151258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 12:11:17.151345 ==
1536 12:11:17.154875 RX Vref Scan: 0
1537 12:11:17.154961
1538 12:11:17.157965 RX Vref 0 -> 0, step: 1
1539 12:11:17.158050
1540 12:11:17.158118 RX Delay -130 -> 252, step: 16
1541 12:11:17.164858 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1542 12:11:17.168254 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1543 12:11:17.171312 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1544 12:11:17.174757 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1545 12:11:17.178221 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1546 12:11:17.184869 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1547 12:11:17.188078 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1548 12:11:17.191173 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1549 12:11:17.194880 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1550 12:11:17.197874 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1551 12:11:17.204585 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1552 12:11:17.207729 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1553 12:11:17.211206 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1554 12:11:17.214710 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1555 12:11:17.221373 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1556 12:11:17.224279 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1557 12:11:17.224354 ==
1558 12:11:17.227698 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 12:11:17.231121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 12:11:17.231207 ==
1561 12:11:17.234732 DQS Delay:
1562 12:11:17.234816 DQS0 = 0, DQS1 = 0
1563 12:11:17.234882 DQM Delay:
1564 12:11:17.237771 DQM0 = 92, DQM1 = 80
1565 12:11:17.237855 DQ Delay:
1566 12:11:17.241342 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1567 12:11:17.244254 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1568 12:11:17.247730 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1569 12:11:17.250819 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1570 12:11:17.250895
1571 12:11:17.250960
1572 12:11:17.251021 ==
1573 12:11:17.254423 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 12:11:17.261000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 12:11:17.261100 ==
1576 12:11:17.261167
1577 12:11:17.261237
1578 12:11:17.261309 TX Vref Scan disable
1579 12:11:17.264653 == TX Byte 0 ==
1580 12:11:17.267935 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1581 12:11:17.274420 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1582 12:11:17.274505 == TX Byte 1 ==
1583 12:11:17.277624 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1584 12:11:17.284025 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1585 12:11:17.284100 ==
1586 12:11:17.287741 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 12:11:17.290741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 12:11:17.290813 ==
1589 12:11:17.303512 TX Vref=22, minBit 8, minWin=27, winSum=448
1590 12:11:17.306744 TX Vref=24, minBit 8, minWin=27, winSum=450
1591 12:11:17.310262 TX Vref=26, minBit 10, minWin=27, winSum=453
1592 12:11:17.313346 TX Vref=28, minBit 15, minWin=27, winSum=456
1593 12:11:17.317340 TX Vref=30, minBit 12, minWin=27, winSum=458
1594 12:11:17.320728 TX Vref=32, minBit 8, minWin=27, winSum=455
1595 12:11:17.327426 [TxChooseVref] Worse bit 12, Min win 27, Win sum 458, Final Vref 30
1596 12:11:17.327507
1597 12:11:17.330907 Final TX Range 1 Vref 30
1598 12:11:17.331012
1599 12:11:17.331077 ==
1600 12:11:17.334298 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 12:11:17.337400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 12:11:17.337485 ==
1603 12:11:17.337551
1604 12:11:17.337612
1605 12:11:17.340541 TX Vref Scan disable
1606 12:11:17.343975 == TX Byte 0 ==
1607 12:11:17.347067 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1608 12:11:17.350726 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1609 12:11:17.353779 == TX Byte 1 ==
1610 12:11:17.357343 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1611 12:11:17.360587 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1612 12:11:17.360675
1613 12:11:17.363793 [DATLAT]
1614 12:11:17.363877 Freq=800, CH1 RK0
1615 12:11:17.363946
1616 12:11:17.367310 DATLAT Default: 0xa
1617 12:11:17.367420 0, 0xFFFF, sum = 0
1618 12:11:17.370869 1, 0xFFFF, sum = 0
1619 12:11:17.370996 2, 0xFFFF, sum = 0
1620 12:11:17.373941 3, 0xFFFF, sum = 0
1621 12:11:17.374017 4, 0xFFFF, sum = 0
1622 12:11:17.377056 5, 0xFFFF, sum = 0
1623 12:11:17.377156 6, 0xFFFF, sum = 0
1624 12:11:17.380282 7, 0xFFFF, sum = 0
1625 12:11:17.380368 8, 0xFFFF, sum = 0
1626 12:11:17.383937 9, 0x0, sum = 1
1627 12:11:17.384050 10, 0x0, sum = 2
1628 12:11:17.387103 11, 0x0, sum = 3
1629 12:11:17.387231 12, 0x0, sum = 4
1630 12:11:17.390253 best_step = 10
1631 12:11:17.390338
1632 12:11:17.390405 ==
1633 12:11:17.393767 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 12:11:17.396962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 12:11:17.397075 ==
1636 12:11:17.400745 RX Vref Scan: 1
1637 12:11:17.400853
1638 12:11:17.400921 Set Vref Range= 32 -> 127
1639 12:11:17.400986
1640 12:11:17.403805 RX Vref 32 -> 127, step: 1
1641 12:11:17.403889
1642 12:11:17.407379 RX Delay -95 -> 252, step: 8
1643 12:11:17.407469
1644 12:11:17.410545 Set Vref, RX VrefLevel [Byte0]: 32
1645 12:11:17.413544 [Byte1]: 32
1646 12:11:17.413628
1647 12:11:17.417026 Set Vref, RX VrefLevel [Byte0]: 33
1648 12:11:17.420362 [Byte1]: 33
1649 12:11:17.423921
1650 12:11:17.424010 Set Vref, RX VrefLevel [Byte0]: 34
1651 12:11:17.427316 [Byte1]: 34
1652 12:11:17.431701
1653 12:11:17.431811 Set Vref, RX VrefLevel [Byte0]: 35
1654 12:11:17.434664 [Byte1]: 35
1655 12:11:17.439171
1656 12:11:17.439257 Set Vref, RX VrefLevel [Byte0]: 36
1657 12:11:17.442706 [Byte1]: 36
1658 12:11:17.446857
1659 12:11:17.446941 Set Vref, RX VrefLevel [Byte0]: 37
1660 12:11:17.450391 [Byte1]: 37
1661 12:11:17.454422
1662 12:11:17.454506 Set Vref, RX VrefLevel [Byte0]: 38
1663 12:11:17.457537 [Byte1]: 38
1664 12:11:17.461984
1665 12:11:17.462082 Set Vref, RX VrefLevel [Byte0]: 39
1666 12:11:17.465164 [Byte1]: 39
1667 12:11:17.469771
1668 12:11:17.469845 Set Vref, RX VrefLevel [Byte0]: 40
1669 12:11:17.472948 [Byte1]: 40
1670 12:11:17.477136
1671 12:11:17.477220 Set Vref, RX VrefLevel [Byte0]: 41
1672 12:11:17.480682 [Byte1]: 41
1673 12:11:17.484865
1674 12:11:17.484974 Set Vref, RX VrefLevel [Byte0]: 42
1675 12:11:17.487962 [Byte1]: 42
1676 12:11:17.492595
1677 12:11:17.492679 Set Vref, RX VrefLevel [Byte0]: 43
1678 12:11:17.495585 [Byte1]: 43
1679 12:11:17.499773
1680 12:11:17.499858 Set Vref, RX VrefLevel [Byte0]: 44
1681 12:11:17.502998 [Byte1]: 44
1682 12:11:17.507467
1683 12:11:17.507551 Set Vref, RX VrefLevel [Byte0]: 45
1684 12:11:17.511003 [Byte1]: 45
1685 12:11:17.515208
1686 12:11:17.515320 Set Vref, RX VrefLevel [Byte0]: 46
1687 12:11:17.518243 [Byte1]: 46
1688 12:11:17.522463
1689 12:11:17.522568 Set Vref, RX VrefLevel [Byte0]: 47
1690 12:11:17.525999 [Byte1]: 47
1691 12:11:17.530363
1692 12:11:17.530473 Set Vref, RX VrefLevel [Byte0]: 48
1693 12:11:17.533422 [Byte1]: 48
1694 12:11:17.537706
1695 12:11:17.537780 Set Vref, RX VrefLevel [Byte0]: 49
1696 12:11:17.541095 [Byte1]: 49
1697 12:11:17.545586
1698 12:11:17.545693 Set Vref, RX VrefLevel [Byte0]: 50
1699 12:11:17.548543 [Byte1]: 50
1700 12:11:17.553292
1701 12:11:17.553375 Set Vref, RX VrefLevel [Byte0]: 51
1702 12:11:17.556231 [Byte1]: 51
1703 12:11:17.560710
1704 12:11:17.560841 Set Vref, RX VrefLevel [Byte0]: 52
1705 12:11:17.563885 [Byte1]: 52
1706 12:11:17.568568
1707 12:11:17.568668 Set Vref, RX VrefLevel [Byte0]: 53
1708 12:11:17.571681 [Byte1]: 53
1709 12:11:17.575896
1710 12:11:17.575973 Set Vref, RX VrefLevel [Byte0]: 54
1711 12:11:17.579024 [Byte1]: 54
1712 12:11:17.583713
1713 12:11:17.583824 Set Vref, RX VrefLevel [Byte0]: 55
1714 12:11:17.586613 [Byte1]: 55
1715 12:11:17.591013
1716 12:11:17.591122 Set Vref, RX VrefLevel [Byte0]: 56
1717 12:11:17.594645 [Byte1]: 56
1718 12:11:17.598805
1719 12:11:17.598916 Set Vref, RX VrefLevel [Byte0]: 57
1720 12:11:17.601869 [Byte1]: 57
1721 12:11:17.606017
1722 12:11:17.606150 Set Vref, RX VrefLevel [Byte0]: 58
1723 12:11:17.609566 [Byte1]: 58
1724 12:11:17.614030
1725 12:11:17.614136 Set Vref, RX VrefLevel [Byte0]: 59
1726 12:11:17.617178 [Byte1]: 59
1727 12:11:17.621285
1728 12:11:17.621357 Set Vref, RX VrefLevel [Byte0]: 60
1729 12:11:17.624538 [Byte1]: 60
1730 12:11:17.629138
1731 12:11:17.629213 Set Vref, RX VrefLevel [Byte0]: 61
1732 12:11:17.632080 [Byte1]: 61
1733 12:11:17.636654
1734 12:11:17.636761 Set Vref, RX VrefLevel [Byte0]: 62
1735 12:11:17.640151 [Byte1]: 62
1736 12:11:17.644220
1737 12:11:17.644333 Set Vref, RX VrefLevel [Byte0]: 63
1738 12:11:17.647603 [Byte1]: 63
1739 12:11:17.651718
1740 12:11:17.651822 Set Vref, RX VrefLevel [Byte0]: 64
1741 12:11:17.655207 [Byte1]: 64
1742 12:11:17.659212
1743 12:11:17.659318 Set Vref, RX VrefLevel [Byte0]: 65
1744 12:11:17.662653 [Byte1]: 65
1745 12:11:17.667257
1746 12:11:17.667360 Set Vref, RX VrefLevel [Byte0]: 66
1747 12:11:17.670404 [Byte1]: 66
1748 12:11:17.674566
1749 12:11:17.674669 Set Vref, RX VrefLevel [Byte0]: 67
1750 12:11:17.677623 [Byte1]: 67
1751 12:11:17.682288
1752 12:11:17.682389 Set Vref, RX VrefLevel [Byte0]: 68
1753 12:11:17.685493 [Byte1]: 68
1754 12:11:17.689999
1755 12:11:17.690078 Set Vref, RX VrefLevel [Byte0]: 69
1756 12:11:17.692904 [Byte1]: 69
1757 12:11:17.697540
1758 12:11:17.697641 Set Vref, RX VrefLevel [Byte0]: 70
1759 12:11:17.700627 [Byte1]: 70
1760 12:11:17.705215
1761 12:11:17.705292 Set Vref, RX VrefLevel [Byte0]: 71
1762 12:11:17.708320 [Byte1]: 71
1763 12:11:17.712597
1764 12:11:17.712703 Set Vref, RX VrefLevel [Byte0]: 72
1765 12:11:17.716079 [Byte1]: 72
1766 12:11:17.720139
1767 12:11:17.720241 Set Vref, RX VrefLevel [Byte0]: 73
1768 12:11:17.723248 [Byte1]: 73
1769 12:11:17.727799
1770 12:11:17.727899 Set Vref, RX VrefLevel [Byte0]: 74
1771 12:11:17.730832 [Byte1]: 74
1772 12:11:17.735443
1773 12:11:17.735546 Set Vref, RX VrefLevel [Byte0]: 75
1774 12:11:17.738555 [Byte1]: 75
1775 12:11:17.743020
1776 12:11:17.743130 Final RX Vref Byte 0 = 53 to rank0
1777 12:11:17.746353 Final RX Vref Byte 1 = 62 to rank0
1778 12:11:17.749828 Final RX Vref Byte 0 = 53 to rank1
1779 12:11:17.752998 Final RX Vref Byte 1 = 62 to rank1==
1780 12:11:17.756369 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 12:11:17.762872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 12:11:17.762984 ==
1783 12:11:17.763081 DQS Delay:
1784 12:11:17.763182 DQS0 = 0, DQS1 = 0
1785 12:11:17.766267 DQM Delay:
1786 12:11:17.766371 DQM0 = 92, DQM1 = 84
1787 12:11:17.769852 DQ Delay:
1788 12:11:17.772896 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1789 12:11:17.775972 DQ4 =88, DQ5 =108, DQ6 =100, DQ7 =88
1790 12:11:17.779596 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1791 12:11:17.782846 DQ12 =96, DQ13 =88, DQ14 =88, DQ15 =88
1792 12:11:17.782958
1793 12:11:17.783053
1794 12:11:17.789700 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1795 12:11:17.792655 CH1 RK0: MR19=606, MR18=314E
1796 12:11:17.799692 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1797 12:11:17.799808
1798 12:11:17.802780 ----->DramcWriteLeveling(PI) begin...
1799 12:11:17.802868 ==
1800 12:11:17.806321 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 12:11:17.809390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 12:11:17.809478 ==
1803 12:11:17.812926 Write leveling (Byte 0): 28 => 28
1804 12:11:17.816048 Write leveling (Byte 1): 31 => 31
1805 12:11:17.819260 DramcWriteLeveling(PI) end<-----
1806 12:11:17.819345
1807 12:11:17.819412 ==
1808 12:11:17.822757 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 12:11:17.825857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 12:11:17.825942 ==
1811 12:11:17.829382 [Gating] SW mode calibration
1812 12:11:17.836097 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 12:11:17.842566 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 12:11:17.845951 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1815 12:11:17.852491 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1816 12:11:17.855955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:11:17.859300 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:11:17.865552 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:11:17.869012 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:11:17.872663 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:11:17.875721 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:11:17.882266 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:11:17.885869 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:11:17.888940 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:11:17.895745 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:11:17.899271 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:11:17.902222 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:11:17.908955 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:11:17.912584 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:11:17.915767 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1831 12:11:17.922497 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1832 12:11:17.925538 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:11:17.928937 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:11:17.935612 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:11:17.938752 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:11:17.942311 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:11:17.948917 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:11:17.952461 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:11:17.955326 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1840 12:11:17.962184 0 9 8 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
1841 12:11:17.965744 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:11:17.968685 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 12:11:17.975494 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 12:11:17.978671 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 12:11:17.982007 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 12:11:17.988742 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 12:11:17.991954 0 10 4 | B1->B0 | 2d2d 3333 | 1 0 | (1 0) (0 1)
1848 12:11:17.995632 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1849 12:11:17.998725 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:11:18.005710 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:11:18.008701 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:11:18.012192 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:11:18.018911 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:11:18.022066 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:11:18.025639 0 11 4 | B1->B0 | 3131 2d2d | 1 0 | (0 0) (0 0)
1856 12:11:18.032095 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1857 12:11:18.035091 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:11:18.038886 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 12:11:18.045139 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 12:11:18.048596 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:11:18.051721 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 12:11:18.058627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:11:18.061677 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1864 12:11:18.065194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:11:18.071847 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:11:18.075397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:11:18.078415 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:11:18.084969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:11:18.088640 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:11:18.091862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:11:18.098371 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:11:18.101497 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:11:18.105137 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:11:18.111521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:11:18.115100 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:11:18.118352 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:11:18.125002 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:11:18.128085 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1879 12:11:18.131249 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 12:11:18.134743 Total UI for P1: 0, mck2ui 16
1881 12:11:18.138027 best dqsien dly found for B0: ( 0, 14, 2)
1882 12:11:18.141538 Total UI for P1: 0, mck2ui 16
1883 12:11:18.144722 best dqsien dly found for B1: ( 0, 14, 0)
1884 12:11:18.148199 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1885 12:11:18.151312 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1886 12:11:18.151385
1887 12:11:18.154935 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1888 12:11:18.161342 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1889 12:11:18.161484 [Gating] SW calibration Done
1890 12:11:18.161594 ==
1891 12:11:18.164805 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 12:11:18.171164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 12:11:18.171249 ==
1894 12:11:18.171315 RX Vref Scan: 0
1895 12:11:18.171379
1896 12:11:18.174674 RX Vref 0 -> 0, step: 1
1897 12:11:18.174757
1898 12:11:18.177798 RX Delay -130 -> 252, step: 16
1899 12:11:18.181449 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1900 12:11:18.184487 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1901 12:11:18.188058 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1902 12:11:18.194754 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1903 12:11:18.197773 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1904 12:11:18.200975 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1905 12:11:18.204611 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1906 12:11:18.207744 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1907 12:11:18.214289 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1908 12:11:18.217677 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1909 12:11:18.220902 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1910 12:11:18.224514 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1911 12:11:18.227480 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1912 12:11:18.234220 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1913 12:11:18.237719 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1914 12:11:18.240660 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1915 12:11:18.240745 ==
1916 12:11:18.244116 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:11:18.247639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 12:11:18.247748 ==
1919 12:11:18.250702 DQS Delay:
1920 12:11:18.250785 DQS0 = 0, DQS1 = 0
1921 12:11:18.254264 DQM Delay:
1922 12:11:18.254348 DQM0 = 91, DQM1 = 84
1923 12:11:18.254416 DQ Delay:
1924 12:11:18.257424 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1925 12:11:18.260474 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1926 12:11:18.263989 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1927 12:11:18.267351 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1928 12:11:18.267434
1929 12:11:18.270612
1930 12:11:18.270694 ==
1931 12:11:18.274102 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 12:11:18.277511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 12:11:18.277595 ==
1934 12:11:18.277662
1935 12:11:18.277726
1936 12:11:18.280520 TX Vref Scan disable
1937 12:11:18.280603 == TX Byte 0 ==
1938 12:11:18.287102 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1939 12:11:18.290687 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1940 12:11:18.290771 == TX Byte 1 ==
1941 12:11:18.297280 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1942 12:11:18.300489 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1943 12:11:18.300607 ==
1944 12:11:18.303985 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 12:11:18.307183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 12:11:18.307267 ==
1947 12:11:18.320678 TX Vref=22, minBit 13, minWin=27, winSum=453
1948 12:11:18.324242 TX Vref=24, minBit 13, minWin=27, winSum=454
1949 12:11:18.327466 TX Vref=26, minBit 8, minWin=27, winSum=454
1950 12:11:18.330503 TX Vref=28, minBit 8, minWin=27, winSum=454
1951 12:11:18.334036 TX Vref=30, minBit 8, minWin=28, winSum=461
1952 12:11:18.340943 TX Vref=32, minBit 8, minWin=28, winSum=459
1953 12:11:18.343978 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1954 12:11:18.344062
1955 12:11:18.347436 Final TX Range 1 Vref 30
1956 12:11:18.347596
1957 12:11:18.347705 ==
1958 12:11:18.350520 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 12:11:18.354063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 12:11:18.357151 ==
1961 12:11:18.357226
1962 12:11:18.357289
1963 12:11:18.357348 TX Vref Scan disable
1964 12:11:18.360879 == TX Byte 0 ==
1965 12:11:18.363942 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1966 12:11:18.370853 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1967 12:11:18.370957 == TX Byte 1 ==
1968 12:11:18.374315 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1969 12:11:18.380789 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1970 12:11:18.380906
1971 12:11:18.380999 [DATLAT]
1972 12:11:18.381088 Freq=800, CH1 RK1
1973 12:11:18.381176
1974 12:11:18.384193 DATLAT Default: 0xa
1975 12:11:18.384272 0, 0xFFFF, sum = 0
1976 12:11:18.387249 1, 0xFFFF, sum = 0
1977 12:11:18.387351 2, 0xFFFF, sum = 0
1978 12:11:18.390786 3, 0xFFFF, sum = 0
1979 12:11:18.394248 4, 0xFFFF, sum = 0
1980 12:11:18.394351 5, 0xFFFF, sum = 0
1981 12:11:18.397305 6, 0xFFFF, sum = 0
1982 12:11:18.397407 7, 0xFFFF, sum = 0
1983 12:11:18.400911 8, 0xFFFF, sum = 0
1984 12:11:18.401015 9, 0x0, sum = 1
1985 12:11:18.401109 10, 0x0, sum = 2
1986 12:11:18.403929 11, 0x0, sum = 3
1987 12:11:18.404025 12, 0x0, sum = 4
1988 12:11:18.407475 best_step = 10
1989 12:11:18.407573
1990 12:11:18.407664 ==
1991 12:11:18.410680 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 12:11:18.414190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 12:11:18.414291 ==
1994 12:11:18.417213 RX Vref Scan: 0
1995 12:11:18.417310
1996 12:11:18.417400 RX Vref 0 -> 0, step: 1
1997 12:11:18.417487
1998 12:11:18.420710 RX Delay -95 -> 252, step: 8
1999 12:11:18.427734 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2000 12:11:18.430771 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2001 12:11:18.434303 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2002 12:11:18.437428 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2003 12:11:18.441056 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2004 12:11:18.447821 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2005 12:11:18.450828 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2006 12:11:18.454164 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2007 12:11:18.457690 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2008 12:11:18.460798 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2009 12:11:18.467406 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2010 12:11:18.470913 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2011 12:11:18.473919 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2012 12:11:18.477304 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2013 12:11:18.480664 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2014 12:11:18.487576 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2015 12:11:18.487704 ==
2016 12:11:18.490715 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 12:11:18.494319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 12:11:18.494403 ==
2019 12:11:18.494470 DQS Delay:
2020 12:11:18.497135 DQS0 = 0, DQS1 = 0
2021 12:11:18.497221 DQM Delay:
2022 12:11:18.500678 DQM0 = 92, DQM1 = 85
2023 12:11:18.500807 DQ Delay:
2024 12:11:18.503813 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2025 12:11:18.507433 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2026 12:11:18.510624 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2027 12:11:18.514203 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =96
2028 12:11:18.514306
2029 12:11:18.514401
2030 12:11:18.520836 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2031 12:11:18.523980 CH1 RK1: MR19=606, MR18=3D12
2032 12:11:18.530504 CH1_RK1: MR19=0x606, MR18=0x3D12, DQSOSC=394, MR23=63, INC=95, DEC=63
2033 12:11:18.534225 [RxdqsGatingPostProcess] freq 800
2034 12:11:18.540988 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 12:11:18.543969 Pre-setting of DQS Precalculation
2036 12:11:18.547569 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 12:11:18.554172 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 12:11:18.560703 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 12:11:18.560816
2040 12:11:18.560888
2041 12:11:18.563793 [Calibration Summary] 1600 Mbps
2042 12:11:18.567520 CH 0, Rank 0
2043 12:11:18.567621 SW Impedance : PASS
2044 12:11:18.570733 DUTY Scan : NO K
2045 12:11:18.573680 ZQ Calibration : PASS
2046 12:11:18.573776 Jitter Meter : NO K
2047 12:11:18.577229 CBT Training : PASS
2048 12:11:18.580276 Write leveling : PASS
2049 12:11:18.580368 RX DQS gating : PASS
2050 12:11:18.583863 RX DQ/DQS(RDDQC) : PASS
2051 12:11:18.586751 TX DQ/DQS : PASS
2052 12:11:18.586840 RX DATLAT : PASS
2053 12:11:18.590326 RX DQ/DQS(Engine): PASS
2054 12:11:18.593533 TX OE : NO K
2055 12:11:18.593620 All Pass.
2056 12:11:18.593685
2057 12:11:18.593753 CH 0, Rank 1
2058 12:11:18.597175 SW Impedance : PASS
2059 12:11:18.600118 DUTY Scan : NO K
2060 12:11:18.600201 ZQ Calibration : PASS
2061 12:11:18.603841 Jitter Meter : NO K
2062 12:11:18.603930 CBT Training : PASS
2063 12:11:18.606801 Write leveling : PASS
2064 12:11:18.609875 RX DQS gating : PASS
2065 12:11:18.609960 RX DQ/DQS(RDDQC) : PASS
2066 12:11:18.613470 TX DQ/DQS : PASS
2067 12:11:18.616543 RX DATLAT : PASS
2068 12:11:18.616620 RX DQ/DQS(Engine): PASS
2069 12:11:18.620196 TX OE : NO K
2070 12:11:18.620279 All Pass.
2071 12:11:18.620345
2072 12:11:18.623463 CH 1, Rank 0
2073 12:11:18.623539 SW Impedance : PASS
2074 12:11:18.626644 DUTY Scan : NO K
2075 12:11:18.630176 ZQ Calibration : PASS
2076 12:11:18.630257 Jitter Meter : NO K
2077 12:11:18.633127 CBT Training : PASS
2078 12:11:18.636630 Write leveling : PASS
2079 12:11:18.636733 RX DQS gating : PASS
2080 12:11:18.639740 RX DQ/DQS(RDDQC) : PASS
2081 12:11:18.643395 TX DQ/DQS : PASS
2082 12:11:18.643478 RX DATLAT : PASS
2083 12:11:18.646487 RX DQ/DQS(Engine): PASS
2084 12:11:18.650056 TX OE : NO K
2085 12:11:18.650149 All Pass.
2086 12:11:18.650223
2087 12:11:18.650285 CH 1, Rank 1
2088 12:11:18.653178 SW Impedance : PASS
2089 12:11:18.656859 DUTY Scan : NO K
2090 12:11:18.656940 ZQ Calibration : PASS
2091 12:11:18.659687 Jitter Meter : NO K
2092 12:11:18.659759 CBT Training : PASS
2093 12:11:18.663150 Write leveling : PASS
2094 12:11:18.666727 RX DQS gating : PASS
2095 12:11:18.666807 RX DQ/DQS(RDDQC) : PASS
2096 12:11:18.669864 TX DQ/DQS : PASS
2097 12:11:18.673547 RX DATLAT : PASS
2098 12:11:18.673622 RX DQ/DQS(Engine): PASS
2099 12:11:18.676533 TX OE : NO K
2100 12:11:18.676624 All Pass.
2101 12:11:18.676688
2102 12:11:18.680054 DramC Write-DBI off
2103 12:11:18.683490 PER_BANK_REFRESH: Hybrid Mode
2104 12:11:18.683571 TX_TRACKING: ON
2105 12:11:18.686436 [GetDramInforAfterCalByMRR] Vendor 6.
2106 12:11:18.689751 [GetDramInforAfterCalByMRR] Revision 606.
2107 12:11:18.693136 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 12:11:18.696239 MR0 0x3b3b
2109 12:11:18.696320 MR8 0x5151
2110 12:11:18.699746 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 12:11:18.699820
2112 12:11:18.702942 MR0 0x3b3b
2113 12:11:18.703025 MR8 0x5151
2114 12:11:18.706432 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 12:11:18.706518
2116 12:11:18.716122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 12:11:18.719743 [FAST_K] Save calibration result to emmc
2118 12:11:18.722776 [FAST_K] Save calibration result to emmc
2119 12:11:18.726440 dram_init: config_dvfs: 1
2120 12:11:18.729633 dramc_set_vcore_voltage set vcore to 662500
2121 12:11:18.729709 Read voltage for 1200, 2
2122 12:11:18.733221 Vio18 = 0
2123 12:11:18.733302 Vcore = 662500
2124 12:11:18.733367 Vdram = 0
2125 12:11:18.736151 Vddq = 0
2126 12:11:18.736228 Vmddr = 0
2127 12:11:18.739725 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 12:11:18.746430 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 12:11:18.749475 MEM_TYPE=3, freq_sel=15
2130 12:11:18.752996 sv_algorithm_assistance_LP4_1600
2131 12:11:18.756573 ============ PULL DRAM RESETB DOWN ============
2132 12:11:18.759722 ========== PULL DRAM RESETB DOWN end =========
2133 12:11:18.762686 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 12:11:18.766294 ===================================
2135 12:11:18.769307 LPDDR4 DRAM CONFIGURATION
2136 12:11:18.772894 ===================================
2137 12:11:18.776566 EX_ROW_EN[0] = 0x0
2138 12:11:18.776649 EX_ROW_EN[1] = 0x0
2139 12:11:18.779569 LP4Y_EN = 0x0
2140 12:11:18.779651 WORK_FSP = 0x0
2141 12:11:18.783045 WL = 0x4
2142 12:11:18.783126 RL = 0x4
2143 12:11:18.786464 BL = 0x2
2144 12:11:18.786572 RPST = 0x0
2145 12:11:18.789491 RD_PRE = 0x0
2146 12:11:18.789573 WR_PRE = 0x1
2147 12:11:18.792876 WR_PST = 0x0
2148 12:11:18.796378 DBI_WR = 0x0
2149 12:11:18.796475 DBI_RD = 0x0
2150 12:11:18.799872 OTF = 0x1
2151 12:11:18.802928 ===================================
2152 12:11:18.806453 ===================================
2153 12:11:18.806530 ANA top config
2154 12:11:18.809589 ===================================
2155 12:11:18.813045 DLL_ASYNC_EN = 0
2156 12:11:18.813123 ALL_SLAVE_EN = 0
2157 12:11:18.816169 NEW_RANK_MODE = 1
2158 12:11:18.819330 DLL_IDLE_MODE = 1
2159 12:11:18.822939 LP45_APHY_COMB_EN = 1
2160 12:11:18.825986 TX_ODT_DIS = 1
2161 12:11:18.826070 NEW_8X_MODE = 1
2162 12:11:18.829622 ===================================
2163 12:11:18.832761 ===================================
2164 12:11:18.835917 data_rate = 2400
2165 12:11:18.839330 CKR = 1
2166 12:11:18.842836 DQ_P2S_RATIO = 8
2167 12:11:18.845904 ===================================
2168 12:11:18.849587 CA_P2S_RATIO = 8
2169 12:11:18.852669 DQ_CA_OPEN = 0
2170 12:11:18.852754 DQ_SEMI_OPEN = 0
2171 12:11:18.856240 CA_SEMI_OPEN = 0
2172 12:11:18.859454 CA_FULL_RATE = 0
2173 12:11:18.862863 DQ_CKDIV4_EN = 0
2174 12:11:18.865981 CA_CKDIV4_EN = 0
2175 12:11:18.869524 CA_PREDIV_EN = 0
2176 12:11:18.869608 PH8_DLY = 17
2177 12:11:18.872519 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 12:11:18.875663 DQ_AAMCK_DIV = 4
2179 12:11:18.879217 CA_AAMCK_DIV = 4
2180 12:11:18.882643 CA_ADMCK_DIV = 4
2181 12:11:18.885802 DQ_TRACK_CA_EN = 0
2182 12:11:18.885945 CA_PICK = 1200
2183 12:11:18.889430 CA_MCKIO = 1200
2184 12:11:18.892384 MCKIO_SEMI = 0
2185 12:11:18.895918 PLL_FREQ = 2366
2186 12:11:18.899316 DQ_UI_PI_RATIO = 32
2187 12:11:18.902681 CA_UI_PI_RATIO = 0
2188 12:11:18.906127 ===================================
2189 12:11:18.909248 ===================================
2190 12:11:18.909332 memory_type:LPDDR4
2191 12:11:18.912893 GP_NUM : 10
2192 12:11:18.916172 SRAM_EN : 1
2193 12:11:18.916256 MD32_EN : 0
2194 12:11:18.919276 ===================================
2195 12:11:18.922837 [ANA_INIT] >>>>>>>>>>>>>>
2196 12:11:18.925857 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 12:11:18.928961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 12:11:18.932636 ===================================
2199 12:11:18.935712 data_rate = 2400,PCW = 0X5b00
2200 12:11:18.938879 ===================================
2201 12:11:18.942505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 12:11:18.945978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 12:11:18.952142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 12:11:18.955735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 12:11:18.959253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 12:11:18.965481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 12:11:18.965599 [ANA_INIT] flow start
2208 12:11:18.969002 [ANA_INIT] PLL >>>>>>>>
2209 12:11:18.972120 [ANA_INIT] PLL <<<<<<<<
2210 12:11:18.972257 [ANA_INIT] MIDPI >>>>>>>>
2211 12:11:18.975638 [ANA_INIT] MIDPI <<<<<<<<
2212 12:11:18.979120 [ANA_INIT] DLL >>>>>>>>
2213 12:11:18.979241 [ANA_INIT] DLL <<<<<<<<
2214 12:11:18.982358 [ANA_INIT] flow end
2215 12:11:18.985833 ============ LP4 DIFF to SE enter ============
2216 12:11:18.988987 ============ LP4 DIFF to SE exit ============
2217 12:11:18.992108 [ANA_INIT] <<<<<<<<<<<<<
2218 12:11:18.995618 [Flow] Enable top DCM control >>>>>
2219 12:11:18.998662 [Flow] Enable top DCM control <<<<<
2220 12:11:19.002167 Enable DLL master slave shuffle
2221 12:11:19.008882 ==============================================================
2222 12:11:19.008962 Gating Mode config
2223 12:11:19.015233 ==============================================================
2224 12:11:19.015318 Config description:
2225 12:11:19.025459 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 12:11:19.032038 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 12:11:19.038818 SELPH_MODE 0: By rank 1: By Phase
2228 12:11:19.041924 ==============================================================
2229 12:11:19.045377 GAT_TRACK_EN = 1
2230 12:11:19.048863 RX_GATING_MODE = 2
2231 12:11:19.051946 RX_GATING_TRACK_MODE = 2
2232 12:11:19.055462 SELPH_MODE = 1
2233 12:11:19.058421 PICG_EARLY_EN = 1
2234 12:11:19.061977 VALID_LAT_VALUE = 1
2235 12:11:19.068626 ==============================================================
2236 12:11:19.072288 Enter into Gating configuration >>>>
2237 12:11:19.075367 Exit from Gating configuration <<<<
2238 12:11:19.075468 Enter into DVFS_PRE_config >>>>>
2239 12:11:19.088629 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 12:11:19.091739 Exit from DVFS_PRE_config <<<<<
2241 12:11:19.095383 Enter into PICG configuration >>>>
2242 12:11:19.098524 Exit from PICG configuration <<<<
2243 12:11:19.098608 [RX_INPUT] configuration >>>>>
2244 12:11:19.101974 [RX_INPUT] configuration <<<<<
2245 12:11:19.108317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 12:11:19.111757 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 12:11:19.118805 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 12:11:19.125095 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 12:11:19.131768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 12:11:19.138126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 12:11:19.141799 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 12:11:19.144948 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 12:11:19.151446 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 12:11:19.155003 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 12:11:19.158102 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 12:11:19.161638 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 12:11:19.164704 ===================================
2258 12:11:19.168451 LPDDR4 DRAM CONFIGURATION
2259 12:11:19.171520 ===================================
2260 12:11:19.175011 EX_ROW_EN[0] = 0x0
2261 12:11:19.175089 EX_ROW_EN[1] = 0x0
2262 12:11:19.178049 LP4Y_EN = 0x0
2263 12:11:19.178123 WORK_FSP = 0x0
2264 12:11:19.181603 WL = 0x4
2265 12:11:19.181701 RL = 0x4
2266 12:11:19.184640 BL = 0x2
2267 12:11:19.184721 RPST = 0x0
2268 12:11:19.188299 RD_PRE = 0x0
2269 12:11:19.188372 WR_PRE = 0x1
2270 12:11:19.191502 WR_PST = 0x0
2271 12:11:19.191571 DBI_WR = 0x0
2272 12:11:19.194597 DBI_RD = 0x0
2273 12:11:19.198227 OTF = 0x1
2274 12:11:19.198314 ===================================
2275 12:11:19.204985 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 12:11:19.207989 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 12:11:19.211341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 12:11:19.214783 ===================================
2279 12:11:19.218062 LPDDR4 DRAM CONFIGURATION
2280 12:11:19.221345 ===================================
2281 12:11:19.224821 EX_ROW_EN[0] = 0x10
2282 12:11:19.224898 EX_ROW_EN[1] = 0x0
2283 12:11:19.228229 LP4Y_EN = 0x0
2284 12:11:19.228305 WORK_FSP = 0x0
2285 12:11:19.231535 WL = 0x4
2286 12:11:19.231618 RL = 0x4
2287 12:11:19.234583 BL = 0x2
2288 12:11:19.234662 RPST = 0x0
2289 12:11:19.238272 RD_PRE = 0x0
2290 12:11:19.238352 WR_PRE = 0x1
2291 12:11:19.241385 WR_PST = 0x0
2292 12:11:19.241462 DBI_WR = 0x0
2293 12:11:19.244481 DBI_RD = 0x0
2294 12:11:19.244550 OTF = 0x1
2295 12:11:19.248176 ===================================
2296 12:11:19.254784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 12:11:19.254866 ==
2298 12:11:19.258154 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 12:11:19.264643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 12:11:19.264721 ==
2301 12:11:19.264801 [Duty_Offset_Calibration]
2302 12:11:19.267823 B0:2 B1:0 CA:1
2303 12:11:19.267900
2304 12:11:19.270860 [DutyScan_Calibration_Flow] k_type=0
2305 12:11:19.279143
2306 12:11:19.279219 ==CLK 0==
2307 12:11:19.282796 Final CLK duty delay cell = -4
2308 12:11:19.285751 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2309 12:11:19.289217 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2310 12:11:19.292708 [-4] AVG Duty = 4953%(X100)
2311 12:11:19.292784
2312 12:11:19.295740 CH0 CLK Duty spec in!! Max-Min= 156%
2313 12:11:19.299342 [DutyScan_Calibration_Flow] ====Done====
2314 12:11:19.299413
2315 12:11:19.302327 [DutyScan_Calibration_Flow] k_type=1
2316 12:11:19.318378
2317 12:11:19.318456 ==DQS 0 ==
2318 12:11:19.321240 Final DQS duty delay cell = 0
2319 12:11:19.324982 [0] MAX Duty = 5187%(X100), DQS PI = 32
2320 12:11:19.327869 [0] MIN Duty = 4938%(X100), DQS PI = 2
2321 12:11:19.327943 [0] AVG Duty = 5062%(X100)
2322 12:11:19.331310
2323 12:11:19.331381 ==DQS 1 ==
2324 12:11:19.334681 Final DQS duty delay cell = -4
2325 12:11:19.338062 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2326 12:11:19.341639 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2327 12:11:19.344761 [-4] AVG Duty = 5031%(X100)
2328 12:11:19.344868
2329 12:11:19.347848 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2330 12:11:19.347917
2331 12:11:19.351423 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2332 12:11:19.354580 [DutyScan_Calibration_Flow] ====Done====
2333 12:11:19.354646
2334 12:11:19.357612 [DutyScan_Calibration_Flow] k_type=3
2335 12:11:19.374244
2336 12:11:19.374327 ==DQM 0 ==
2337 12:11:19.377678 Final DQM duty delay cell = 0
2338 12:11:19.380696 [0] MAX Duty = 5062%(X100), DQS PI = 24
2339 12:11:19.383820 [0] MIN Duty = 4875%(X100), DQS PI = 0
2340 12:11:19.383896 [0] AVG Duty = 4968%(X100)
2341 12:11:19.387488
2342 12:11:19.387567 ==DQM 1 ==
2343 12:11:19.390603 Final DQM duty delay cell = -4
2344 12:11:19.393619 [-4] MAX Duty = 5000%(X100), DQS PI = 34
2345 12:11:19.397038 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2346 12:11:19.400212 [-4] AVG Duty = 4906%(X100)
2347 12:11:19.400367
2348 12:11:19.403877 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2349 12:11:19.404027
2350 12:11:19.406946 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2351 12:11:19.410542 [DutyScan_Calibration_Flow] ====Done====
2352 12:11:19.410656
2353 12:11:19.413703 [DutyScan_Calibration_Flow] k_type=2
2354 12:11:19.430306
2355 12:11:19.430391 ==DQ 0 ==
2356 12:11:19.433323 Final DQ duty delay cell = -4
2357 12:11:19.436714 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2358 12:11:19.440159 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2359 12:11:19.443548 [-4] AVG Duty = 4968%(X100)
2360 12:11:19.443632
2361 12:11:19.443699 ==DQ 1 ==
2362 12:11:19.446874 Final DQ duty delay cell = 0
2363 12:11:19.449952 [0] MAX Duty = 4938%(X100), DQS PI = 4
2364 12:11:19.453584 [0] MIN Duty = 4907%(X100), DQS PI = 0
2365 12:11:19.456602 [0] AVG Duty = 4922%(X100)
2366 12:11:19.456713
2367 12:11:19.459736 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2368 12:11:19.459845
2369 12:11:19.463328 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2370 12:11:19.466126 [DutyScan_Calibration_Flow] ====Done====
2371 12:11:19.466238 ==
2372 12:11:19.469529 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 12:11:19.473208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 12:11:19.473296 ==
2375 12:11:19.476693 [Duty_Offset_Calibration]
2376 12:11:19.476807 B0:0 B1:-1 CA:2
2377 12:11:19.476905
2378 12:11:19.479720 [DutyScan_Calibration_Flow] k_type=0
2379 12:11:19.490182
2380 12:11:19.490293 ==CLK 0==
2381 12:11:19.493733 Final CLK duty delay cell = 0
2382 12:11:19.496704 [0] MAX Duty = 5156%(X100), DQS PI = 16
2383 12:11:19.500259 [0] MIN Duty = 4938%(X100), DQS PI = 44
2384 12:11:19.500364 [0] AVG Duty = 5047%(X100)
2385 12:11:19.503424
2386 12:11:19.507199 CH1 CLK Duty spec in!! Max-Min= 218%
2387 12:11:19.510293 [DutyScan_Calibration_Flow] ====Done====
2388 12:11:19.510377
2389 12:11:19.513362 [DutyScan_Calibration_Flow] k_type=1
2390 12:11:19.529501
2391 12:11:19.529586 ==DQS 0 ==
2392 12:11:19.532738 Final DQS duty delay cell = 0
2393 12:11:19.536427 [0] MAX Duty = 5093%(X100), DQS PI = 24
2394 12:11:19.539534 [0] MIN Duty = 4969%(X100), DQS PI = 0
2395 12:11:19.542824 [0] AVG Duty = 5031%(X100)
2396 12:11:19.543004
2397 12:11:19.543155 ==DQS 1 ==
2398 12:11:19.546162 Final DQS duty delay cell = 0
2399 12:11:19.549481 [0] MAX Duty = 5156%(X100), DQS PI = 0
2400 12:11:19.552972 [0] MIN Duty = 4875%(X100), DQS PI = 34
2401 12:11:19.556065 [0] AVG Duty = 5015%(X100)
2402 12:11:19.556141
2403 12:11:19.559225 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2404 12:11:19.559299
2405 12:11:19.562746 CH1 DQS 1 Duty spec in!! Max-Min= 281%
2406 12:11:19.565845 [DutyScan_Calibration_Flow] ====Done====
2407 12:11:19.565930
2408 12:11:19.569282 [DutyScan_Calibration_Flow] k_type=3
2409 12:11:19.586046
2410 12:11:19.586130 ==DQM 0 ==
2411 12:11:19.589775 Final DQM duty delay cell = 4
2412 12:11:19.592789 [4] MAX Duty = 5093%(X100), DQS PI = 6
2413 12:11:19.596269 [4] MIN Duty = 4969%(X100), DQS PI = 28
2414 12:11:19.596338 [4] AVG Duty = 5031%(X100)
2415 12:11:19.599938
2416 12:11:19.600039 ==DQM 1 ==
2417 12:11:19.602885 Final DQM duty delay cell = -4
2418 12:11:19.606487 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2419 12:11:19.609616 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2420 12:11:19.612711 [-4] AVG Duty = 4875%(X100)
2421 12:11:19.612832
2422 12:11:19.616261 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2423 12:11:19.616372
2424 12:11:19.619296 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2425 12:11:19.623068 [DutyScan_Calibration_Flow] ====Done====
2426 12:11:19.623152
2427 12:11:19.626027 [DutyScan_Calibration_Flow] k_type=2
2428 12:11:19.642842
2429 12:11:19.642928 ==DQ 0 ==
2430 12:11:19.646175 Final DQ duty delay cell = 0
2431 12:11:19.649663 [0] MAX Duty = 5062%(X100), DQS PI = 18
2432 12:11:19.653061 [0] MIN Duty = 4938%(X100), DQS PI = 44
2433 12:11:19.653166 [0] AVG Duty = 5000%(X100)
2434 12:11:19.656558
2435 12:11:19.656643 ==DQ 1 ==
2436 12:11:19.659944 Final DQ duty delay cell = 0
2437 12:11:19.663194 [0] MAX Duty = 5031%(X100), DQS PI = 2
2438 12:11:19.666365 [0] MIN Duty = 4813%(X100), DQS PI = 36
2439 12:11:19.666451 [0] AVG Duty = 4922%(X100)
2440 12:11:19.666519
2441 12:11:19.669411 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 12:11:19.669496
2443 12:11:19.673104 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2444 12:11:19.679700 [DutyScan_Calibration_Flow] ====Done====
2445 12:11:19.682744 nWR fixed to 30
2446 12:11:19.682830 [ModeRegInit_LP4] CH0 RK0
2447 12:11:19.686426 [ModeRegInit_LP4] CH0 RK1
2448 12:11:19.689588 [ModeRegInit_LP4] CH1 RK0
2449 12:11:19.689675 [ModeRegInit_LP4] CH1 RK1
2450 12:11:19.692686 match AC timing 7
2451 12:11:19.696279 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 12:11:19.699290 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 12:11:19.706017 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 12:11:19.709442 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 12:11:19.715996 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 12:11:19.716095 ==
2457 12:11:19.719641 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 12:11:19.722715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 12:11:19.722829 ==
2460 12:11:19.729799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 12:11:19.732901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 12:11:19.742616 [CA 0] Center 38 (8~69) winsize 62
2463 12:11:19.745989 [CA 1] Center 38 (7~69) winsize 63
2464 12:11:19.749734 [CA 2] Center 35 (5~66) winsize 62
2465 12:11:19.752688 [CA 3] Center 35 (4~66) winsize 63
2466 12:11:19.756114 [CA 4] Center 34 (4~65) winsize 62
2467 12:11:19.759350 [CA 5] Center 33 (3~63) winsize 61
2468 12:11:19.759448
2469 12:11:19.762610 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2470 12:11:19.762696
2471 12:11:19.765730 [CATrainingPosCal] consider 1 rank data
2472 12:11:19.769321 u2DelayCellTimex100 = 270/100 ps
2473 12:11:19.772445 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2474 12:11:19.779056 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2475 12:11:19.782613 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 12:11:19.786041 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2477 12:11:19.789108 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 12:11:19.792271 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 12:11:19.792435
2480 12:11:19.795895 CA PerBit enable=1, Macro0, CA PI delay=33
2481 12:11:19.795978
2482 12:11:19.798969 [CBTSetCACLKResult] CA Dly = 33
2483 12:11:19.799052 CS Dly: 6 (0~37)
2484 12:11:19.802367 ==
2485 12:11:19.805956 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 12:11:19.808966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 12:11:19.809050 ==
2488 12:11:19.812492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 12:11:19.818986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 12:11:19.828848 [CA 0] Center 39 (8~70) winsize 63
2491 12:11:19.831946 [CA 1] Center 38 (8~69) winsize 62
2492 12:11:19.835502 [CA 2] Center 35 (5~66) winsize 62
2493 12:11:19.838538 [CA 3] Center 35 (5~66) winsize 62
2494 12:11:19.842093 [CA 4] Center 34 (4~65) winsize 62
2495 12:11:19.845202 [CA 5] Center 33 (3~64) winsize 62
2496 12:11:19.845287
2497 12:11:19.848603 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2498 12:11:19.848714
2499 12:11:19.852184 [CATrainingPosCal] consider 2 rank data
2500 12:11:19.855493 u2DelayCellTimex100 = 270/100 ps
2501 12:11:19.858485 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2502 12:11:19.861944 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 12:11:19.868367 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 12:11:19.871846 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 12:11:19.875019 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 12:11:19.878547 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2507 12:11:19.878632
2508 12:11:19.881682 CA PerBit enable=1, Macro0, CA PI delay=33
2509 12:11:19.881768
2510 12:11:19.885048 [CBTSetCACLKResult] CA Dly = 33
2511 12:11:19.885134 CS Dly: 7 (0~39)
2512 12:11:19.885202
2513 12:11:19.888552 ----->DramcWriteLeveling(PI) begin...
2514 12:11:19.891640 ==
2515 12:11:19.895251 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:11:19.898350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:11:19.898436 ==
2518 12:11:19.901472 Write leveling (Byte 0): 34 => 34
2519 12:11:19.905057 Write leveling (Byte 1): 29 => 29
2520 12:11:19.908226 DramcWriteLeveling(PI) end<-----
2521 12:11:19.908311
2522 12:11:19.908379 ==
2523 12:11:19.911770 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 12:11:19.914774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 12:11:19.914860 ==
2526 12:11:19.918231 [Gating] SW mode calibration
2527 12:11:19.925020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 12:11:19.931712 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 12:11:19.934935 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2530 12:11:19.937966 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
2531 12:11:19.944696 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:11:19.948327 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 12:11:19.951313 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 12:11:19.954671 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 12:11:19.961599 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2536 12:11:19.964586 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2537 12:11:19.968136 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2538 12:11:19.974570 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 12:11:19.978078 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:11:19.981713 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 12:11:19.988015 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 12:11:19.991443 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 12:11:19.994458 1 0 24 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
2544 12:11:20.001159 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2545 12:11:20.004750 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2546 12:11:20.007785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:11:20.014373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:11:20.017999 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:11:20.021049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 12:11:20.028223 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 12:11:20.031159 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:11:20.034723 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 12:11:20.041085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 12:11:20.044658 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:11:20.047826 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:11:20.054539 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:11:20.057925 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:11:20.061332 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:11:20.067748 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:11:20.071177 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:11:20.074142 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:11:20.081016 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:11:20.084627 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:11:20.087728 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:11:20.090814 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:11:20.097651 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:11:20.100692 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 12:11:20.104270 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 12:11:20.110840 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 12:11:20.114482 Total UI for P1: 0, mck2ui 16
2571 12:11:20.117628 best dqsien dly found for B0: ( 1, 3, 26)
2572 12:11:20.120652 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 12:11:20.124276 Total UI for P1: 0, mck2ui 16
2574 12:11:20.127403 best dqsien dly found for B1: ( 1, 4, 0)
2575 12:11:20.130995 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2576 12:11:20.134588 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 12:11:20.134694
2578 12:11:20.137667 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2579 12:11:20.140732 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 12:11:20.144399 [Gating] SW calibration Done
2581 12:11:20.144500 ==
2582 12:11:20.147888 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 12:11:20.150952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 12:11:20.154022 ==
2585 12:11:20.154134 RX Vref Scan: 0
2586 12:11:20.154228
2587 12:11:20.157635 RX Vref 0 -> 0, step: 1
2588 12:11:20.157736
2589 12:11:20.160672 RX Delay -40 -> 252, step: 8
2590 12:11:20.164236 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2591 12:11:20.167635 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2592 12:11:20.170628 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2593 12:11:20.174168 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2594 12:11:20.180843 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2595 12:11:20.183858 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2596 12:11:20.187298 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2597 12:11:20.190674 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2598 12:11:20.194246 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2599 12:11:20.197308 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2600 12:11:20.203916 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2601 12:11:20.207553 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2602 12:11:20.210643 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2603 12:11:20.214293 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2604 12:11:20.220296 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2605 12:11:20.224147 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2606 12:11:20.224235 ==
2607 12:11:20.227271 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 12:11:20.230261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 12:11:20.230344 ==
2610 12:11:20.233870 DQS Delay:
2611 12:11:20.233952 DQS0 = 0, DQS1 = 0
2612 12:11:20.234026 DQM Delay:
2613 12:11:20.237426 DQM0 = 122, DQM1 = 110
2614 12:11:20.237505 DQ Delay:
2615 12:11:20.240622 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2616 12:11:20.243693 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2617 12:11:20.247426 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2618 12:11:20.253695 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2619 12:11:20.253771
2620 12:11:20.253835
2621 12:11:20.253900 ==
2622 12:11:20.257211 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 12:11:20.260363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 12:11:20.260435 ==
2625 12:11:20.260509
2626 12:11:20.260571
2627 12:11:20.263910 TX Vref Scan disable
2628 12:11:20.263986 == TX Byte 0 ==
2629 12:11:20.270334 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2630 12:11:20.273829 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2631 12:11:20.273905 == TX Byte 1 ==
2632 12:11:20.280273 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2633 12:11:20.283298 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2634 12:11:20.283377 ==
2635 12:11:20.286641 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 12:11:20.289993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 12:11:20.290071 ==
2638 12:11:20.303118 TX Vref=22, minBit 6, minWin=23, winSum=402
2639 12:11:20.306505 TX Vref=24, minBit 2, minWin=24, winSum=407
2640 12:11:20.309579 TX Vref=26, minBit 0, minWin=24, winSum=410
2641 12:11:20.313044 TX Vref=28, minBit 1, minWin=25, winSum=413
2642 12:11:20.316192 TX Vref=30, minBit 1, minWin=25, winSum=416
2643 12:11:20.323319 TX Vref=32, minBit 1, minWin=25, winSum=413
2644 12:11:20.326546 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 30
2645 12:11:20.326640
2646 12:11:20.329686 Final TX Range 1 Vref 30
2647 12:11:20.329765
2648 12:11:20.329863 ==
2649 12:11:20.332719 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 12:11:20.336364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 12:11:20.336452 ==
2652 12:11:20.339457
2653 12:11:20.339530
2654 12:11:20.339603 TX Vref Scan disable
2655 12:11:20.343078 == TX Byte 0 ==
2656 12:11:20.346060 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2657 12:11:20.349691 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2658 12:11:20.352779 == TX Byte 1 ==
2659 12:11:20.356468 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2660 12:11:20.359544 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2661 12:11:20.362770
2662 12:11:20.362852 [DATLAT]
2663 12:11:20.362917 Freq=1200, CH0 RK0
2664 12:11:20.362987
2665 12:11:20.366338 DATLAT Default: 0xd
2666 12:11:20.366419 0, 0xFFFF, sum = 0
2667 12:11:20.369772 1, 0xFFFF, sum = 0
2668 12:11:20.369855 2, 0xFFFF, sum = 0
2669 12:11:20.372658 3, 0xFFFF, sum = 0
2670 12:11:20.372734 4, 0xFFFF, sum = 0
2671 12:11:20.376127 5, 0xFFFF, sum = 0
2672 12:11:20.379739 6, 0xFFFF, sum = 0
2673 12:11:20.379821 7, 0xFFFF, sum = 0
2674 12:11:20.382795 8, 0xFFFF, sum = 0
2675 12:11:20.382880 9, 0xFFFF, sum = 0
2676 12:11:20.386129 10, 0xFFFF, sum = 0
2677 12:11:20.386233 11, 0xFFFF, sum = 0
2678 12:11:20.389717 12, 0x0, sum = 1
2679 12:11:20.389804 13, 0x0, sum = 2
2680 12:11:20.392590 14, 0x0, sum = 3
2681 12:11:20.392709 15, 0x0, sum = 4
2682 12:11:20.392813 best_step = 13
2683 12:11:20.396246
2684 12:11:20.396328 ==
2685 12:11:20.399324 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:11:20.402863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:11:20.402968 ==
2688 12:11:20.403079 RX Vref Scan: 1
2689 12:11:20.403173
2690 12:11:20.406014 Set Vref Range= 32 -> 127
2691 12:11:20.406105
2692 12:11:20.409279 RX Vref 32 -> 127, step: 1
2693 12:11:20.409361
2694 12:11:20.412723 RX Delay -13 -> 252, step: 4
2695 12:11:20.412836
2696 12:11:20.415869 Set Vref, RX VrefLevel [Byte0]: 32
2697 12:11:20.419426 [Byte1]: 32
2698 12:11:20.419510
2699 12:11:20.422376 Set Vref, RX VrefLevel [Byte0]: 33
2700 12:11:20.425990 [Byte1]: 33
2701 12:11:20.429195
2702 12:11:20.429274 Set Vref, RX VrefLevel [Byte0]: 34
2703 12:11:20.432408 [Byte1]: 34
2704 12:11:20.436948
2705 12:11:20.437035 Set Vref, RX VrefLevel [Byte0]: 35
2706 12:11:20.440478 [Byte1]: 35
2707 12:11:20.445074
2708 12:11:20.445190 Set Vref, RX VrefLevel [Byte0]: 36
2709 12:11:20.448254 [Byte1]: 36
2710 12:11:20.452998
2711 12:11:20.453079 Set Vref, RX VrefLevel [Byte0]: 37
2712 12:11:20.456057 [Byte1]: 37
2713 12:11:20.460779
2714 12:11:20.460866 Set Vref, RX VrefLevel [Byte0]: 38
2715 12:11:20.464308 [Byte1]: 38
2716 12:11:20.468445
2717 12:11:20.468520 Set Vref, RX VrefLevel [Byte0]: 39
2718 12:11:20.472067 [Byte1]: 39
2719 12:11:20.476550
2720 12:11:20.476655 Set Vref, RX VrefLevel [Byte0]: 40
2721 12:11:20.479943 [Byte1]: 40
2722 12:11:20.484416
2723 12:11:20.484528 Set Vref, RX VrefLevel [Byte0]: 41
2724 12:11:20.488013 [Byte1]: 41
2725 12:11:20.492460
2726 12:11:20.492565 Set Vref, RX VrefLevel [Byte0]: 42
2727 12:11:20.495428 [Byte1]: 42
2728 12:11:20.500114
2729 12:11:20.500192 Set Vref, RX VrefLevel [Byte0]: 43
2730 12:11:20.503572 [Byte1]: 43
2731 12:11:20.508171
2732 12:11:20.508250 Set Vref, RX VrefLevel [Byte0]: 44
2733 12:11:20.511657 [Byte1]: 44
2734 12:11:20.515605
2735 12:11:20.519155 Set Vref, RX VrefLevel [Byte0]: 45
2736 12:11:20.522336 [Byte1]: 45
2737 12:11:20.522422
2738 12:11:20.525918 Set Vref, RX VrefLevel [Byte0]: 46
2739 12:11:20.529042 [Byte1]: 46
2740 12:11:20.529127
2741 12:11:20.532644 Set Vref, RX VrefLevel [Byte0]: 47
2742 12:11:20.535754 [Byte1]: 47
2743 12:11:20.539495
2744 12:11:20.539580 Set Vref, RX VrefLevel [Byte0]: 48
2745 12:11:20.543029 [Byte1]: 48
2746 12:11:20.547646
2747 12:11:20.547731 Set Vref, RX VrefLevel [Byte0]: 49
2748 12:11:20.550802 [Byte1]: 49
2749 12:11:20.555339
2750 12:11:20.555422 Set Vref, RX VrefLevel [Byte0]: 50
2751 12:11:20.558933 [Byte1]: 50
2752 12:11:20.563424
2753 12:11:20.563507 Set Vref, RX VrefLevel [Byte0]: 51
2754 12:11:20.566564 [Byte1]: 51
2755 12:11:20.571288
2756 12:11:20.571399 Set Vref, RX VrefLevel [Byte0]: 52
2757 12:11:20.574727 [Byte1]: 52
2758 12:11:20.579413
2759 12:11:20.579529 Set Vref, RX VrefLevel [Byte0]: 53
2760 12:11:20.582372 [Byte1]: 53
2761 12:11:20.586840
2762 12:11:20.586938 Set Vref, RX VrefLevel [Byte0]: 54
2763 12:11:20.590495 [Byte1]: 54
2764 12:11:20.594986
2765 12:11:20.595084 Set Vref, RX VrefLevel [Byte0]: 55
2766 12:11:20.598304 [Byte1]: 55
2767 12:11:20.602819
2768 12:11:20.602926 Set Vref, RX VrefLevel [Byte0]: 56
2769 12:11:20.606010 [Byte1]: 56
2770 12:11:20.610592
2771 12:11:20.610718 Set Vref, RX VrefLevel [Byte0]: 57
2772 12:11:20.614147 [Byte1]: 57
2773 12:11:20.618691
2774 12:11:20.618803 Set Vref, RX VrefLevel [Byte0]: 58
2775 12:11:20.622089 [Byte1]: 58
2776 12:11:20.626653
2777 12:11:20.626735 Set Vref, RX VrefLevel [Byte0]: 59
2778 12:11:20.629769 [Byte1]: 59
2779 12:11:20.634383
2780 12:11:20.634488 Set Vref, RX VrefLevel [Byte0]: 60
2781 12:11:20.637465 [Byte1]: 60
2782 12:11:20.642081
2783 12:11:20.642165 Set Vref, RX VrefLevel [Byte0]: 61
2784 12:11:20.645630 [Byte1]: 61
2785 12:11:20.650007
2786 12:11:20.650130 Set Vref, RX VrefLevel [Byte0]: 62
2787 12:11:20.653649 [Byte1]: 62
2788 12:11:20.658261
2789 12:11:20.658383 Set Vref, RX VrefLevel [Byte0]: 63
2790 12:11:20.661411 [Byte1]: 63
2791 12:11:20.666133
2792 12:11:20.666242 Set Vref, RX VrefLevel [Byte0]: 64
2793 12:11:20.669212 [Byte1]: 64
2794 12:11:20.673902
2795 12:11:20.674003 Set Vref, RX VrefLevel [Byte0]: 65
2796 12:11:20.676990 [Byte1]: 65
2797 12:11:20.681914
2798 12:11:20.682017 Set Vref, RX VrefLevel [Byte0]: 66
2799 12:11:20.684912 [Byte1]: 66
2800 12:11:20.689411
2801 12:11:20.689483 Set Vref, RX VrefLevel [Byte0]: 67
2802 12:11:20.692812 [Byte1]: 67
2803 12:11:20.697363
2804 12:11:20.697451 Set Vref, RX VrefLevel [Byte0]: 68
2805 12:11:20.700886 [Byte1]: 68
2806 12:11:20.705206
2807 12:11:20.705293 Set Vref, RX VrefLevel [Byte0]: 69
2808 12:11:20.708684 [Byte1]: 69
2809 12:11:20.713211
2810 12:11:20.713298 Final RX Vref Byte 0 = 58 to rank0
2811 12:11:20.716777 Final RX Vref Byte 1 = 50 to rank0
2812 12:11:20.719715 Final RX Vref Byte 0 = 58 to rank1
2813 12:11:20.723137 Final RX Vref Byte 1 = 50 to rank1==
2814 12:11:20.726754 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 12:11:20.733463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 12:11:20.733547 ==
2817 12:11:20.733616 DQS Delay:
2818 12:11:20.733680 DQS0 = 0, DQS1 = 0
2819 12:11:20.736528 DQM Delay:
2820 12:11:20.736629 DQM0 = 123, DQM1 = 109
2821 12:11:20.739691 DQ Delay:
2822 12:11:20.743244 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2823 12:11:20.746292 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2824 12:11:20.749939 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2825 12:11:20.753291 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2826 12:11:20.753371
2827 12:11:20.753437
2828 12:11:20.760091 [DQSOSCAuto] RK0, (LSB)MR18= 0x905, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2829 12:11:20.763239 CH0 RK0: MR19=404, MR18=905
2830 12:11:20.769737 CH0_RK0: MR19=0x404, MR18=0x905, DQSOSC=406, MR23=63, INC=39, DEC=26
2831 12:11:20.769815
2832 12:11:20.772883 ----->DramcWriteLeveling(PI) begin...
2833 12:11:20.772958 ==
2834 12:11:20.776459 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 12:11:20.779578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 12:11:20.783105 ==
2837 12:11:20.783191 Write leveling (Byte 0): 34 => 34
2838 12:11:20.786124 Write leveling (Byte 1): 31 => 31
2839 12:11:20.789571 DramcWriteLeveling(PI) end<-----
2840 12:11:20.789650
2841 12:11:20.789716 ==
2842 12:11:20.793027 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 12:11:20.799829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 12:11:20.799939 ==
2845 12:11:20.800036 [Gating] SW mode calibration
2846 12:11:20.809693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 12:11:20.812669 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 12:11:20.819323 0 15 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2849 12:11:20.822980 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 12:11:20.825836 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 12:11:20.832869 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 12:11:20.835878 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 12:11:20.839501 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 12:11:20.842654 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2855 12:11:20.849290 0 15 28 | B1->B0 | 3131 2c2c | 1 0 | (1 1) (0 0)
2856 12:11:20.852491 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 12:11:20.856034 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 12:11:20.862700 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 12:11:20.865805 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 12:11:20.869451 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 12:11:20.876189 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 12:11:20.879209 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2863 12:11:20.882873 1 0 28 | B1->B0 | 3535 4141 | 0 1 | (0 0) (0 0)
2864 12:11:20.888980 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 12:11:20.892447 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 12:11:20.895507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 12:11:20.902451 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 12:11:20.905837 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 12:11:20.909390 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 12:11:20.915803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 12:11:20.919286 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2872 12:11:20.922580 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2873 12:11:20.929272 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:11:20.932250 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:11:20.935673 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:11:20.942429 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:11:20.945447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:11:20.948615 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:11:20.955372 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:11:20.959046 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:11:20.962005 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:11:20.968727 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:11:20.972381 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:11:20.975400 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:11:20.982044 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:11:20.985196 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:11:20.988870 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2888 12:11:20.991905 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2889 12:11:20.995445 Total UI for P1: 0, mck2ui 16
2890 12:11:20.998902 best dqsien dly found for B0: ( 1, 3, 28)
2891 12:11:21.002042 Total UI for P1: 0, mck2ui 16
2892 12:11:21.005386 best dqsien dly found for B1: ( 1, 3, 28)
2893 12:11:21.008943 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2894 12:11:21.012001 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2895 12:11:21.015452
2896 12:11:21.018414 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2897 12:11:21.021833 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2898 12:11:21.025441 [Gating] SW calibration Done
2899 12:11:21.025519 ==
2900 12:11:21.028844 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 12:11:21.031799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 12:11:21.031877 ==
2903 12:11:21.031949 RX Vref Scan: 0
2904 12:11:21.035392
2905 12:11:21.035471 RX Vref 0 -> 0, step: 1
2906 12:11:21.035546
2907 12:11:21.038260 RX Delay -40 -> 252, step: 8
2908 12:11:21.041814 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2909 12:11:21.044909 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2910 12:11:21.051717 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2911 12:11:21.055278 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2912 12:11:21.058405 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2913 12:11:21.061536 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2914 12:11:21.065040 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2915 12:11:21.071880 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2916 12:11:21.074948 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2917 12:11:21.078513 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2918 12:11:21.081695 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2919 12:11:21.084732 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2920 12:11:21.091518 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2921 12:11:21.095188 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2922 12:11:21.098228 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2923 12:11:21.101774 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2924 12:11:21.101851 ==
2925 12:11:21.105209 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 12:11:21.111697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 12:11:21.111782 ==
2928 12:11:21.111849 DQS Delay:
2929 12:11:21.115106 DQS0 = 0, DQS1 = 0
2930 12:11:21.115190 DQM Delay:
2931 12:11:21.115283 DQM0 = 120, DQM1 = 108
2932 12:11:21.118101 DQ Delay:
2933 12:11:21.121311 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2934 12:11:21.124910 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2935 12:11:21.127979 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2936 12:11:21.131431 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2937 12:11:21.131516
2938 12:11:21.131584
2939 12:11:21.131662 ==
2940 12:11:21.134955 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 12:11:21.137981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 12:11:21.141406 ==
2943 12:11:21.141495
2944 12:11:21.141578
2945 12:11:21.141643 TX Vref Scan disable
2946 12:11:21.144842 == TX Byte 0 ==
2947 12:11:21.147942 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2948 12:11:21.151498 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2949 12:11:21.154695 == TX Byte 1 ==
2950 12:11:21.158308 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2951 12:11:21.161452 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2952 12:11:21.161536 ==
2953 12:11:21.164631 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 12:11:21.171143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 12:11:21.171236 ==
2956 12:11:21.182183 TX Vref=22, minBit 1, minWin=24, winSum=406
2957 12:11:21.185972 TX Vref=24, minBit 0, minWin=24, winSum=411
2958 12:11:21.188969 TX Vref=26, minBit 1, minWin=24, winSum=413
2959 12:11:21.192600 TX Vref=28, minBit 1, minWin=24, winSum=412
2960 12:11:21.195714 TX Vref=30, minBit 1, minWin=25, winSum=417
2961 12:11:21.198835 TX Vref=32, minBit 1, minWin=25, winSum=415
2962 12:11:21.205443 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 30
2963 12:11:21.205540
2964 12:11:21.209039 Final TX Range 1 Vref 30
2965 12:11:21.209140
2966 12:11:21.209208 ==
2967 12:11:21.212392 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 12:11:21.215289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 12:11:21.215401 ==
2970 12:11:21.218871
2971 12:11:21.218986
2972 12:11:21.219088 TX Vref Scan disable
2973 12:11:21.221890 == TX Byte 0 ==
2974 12:11:21.225441 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2975 12:11:21.231813 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2976 12:11:21.231906 == TX Byte 1 ==
2977 12:11:21.235401 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2978 12:11:21.242197 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2979 12:11:21.242305
2980 12:11:21.242400 [DATLAT]
2981 12:11:21.242498 Freq=1200, CH0 RK1
2982 12:11:21.242598
2983 12:11:21.245150 DATLAT Default: 0xd
2984 12:11:21.245230 0, 0xFFFF, sum = 0
2985 12:11:21.248675 1, 0xFFFF, sum = 0
2986 12:11:21.251822 2, 0xFFFF, sum = 0
2987 12:11:21.251930 3, 0xFFFF, sum = 0
2988 12:11:21.255438 4, 0xFFFF, sum = 0
2989 12:11:21.255542 5, 0xFFFF, sum = 0
2990 12:11:21.258438 6, 0xFFFF, sum = 0
2991 12:11:21.258541 7, 0xFFFF, sum = 0
2992 12:11:21.261959 8, 0xFFFF, sum = 0
2993 12:11:21.262032 9, 0xFFFF, sum = 0
2994 12:11:21.265015 10, 0xFFFF, sum = 0
2995 12:11:21.265088 11, 0xFFFF, sum = 0
2996 12:11:21.268682 12, 0x0, sum = 1
2997 12:11:21.268791 13, 0x0, sum = 2
2998 12:11:21.271707 14, 0x0, sum = 3
2999 12:11:21.271808 15, 0x0, sum = 4
3000 12:11:21.275242 best_step = 13
3001 12:11:21.275348
3002 12:11:21.275446 ==
3003 12:11:21.278274 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 12:11:21.281951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 12:11:21.282046 ==
3006 12:11:21.282119 RX Vref Scan: 0
3007 12:11:21.282185
3008 12:11:21.285061 RX Vref 0 -> 0, step: 1
3009 12:11:21.285139
3010 12:11:21.288647 RX Delay -21 -> 252, step: 4
3011 12:11:21.291723 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3012 12:11:21.298352 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3013 12:11:21.301539 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3014 12:11:21.305097 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3015 12:11:21.308083 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3016 12:11:21.311539 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3017 12:11:21.318089 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3018 12:11:21.321391 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3019 12:11:21.324762 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3020 12:11:21.328242 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3021 12:11:21.331256 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3022 12:11:21.338110 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3023 12:11:21.341318 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3024 12:11:21.344959 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3025 12:11:21.348076 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3026 12:11:21.354670 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3027 12:11:21.354754 ==
3028 12:11:21.358229 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 12:11:21.361474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 12:11:21.361558 ==
3031 12:11:21.361625 DQS Delay:
3032 12:11:21.364697 DQS0 = 0, DQS1 = 0
3033 12:11:21.364811 DQM Delay:
3034 12:11:21.367813 DQM0 = 119, DQM1 = 107
3035 12:11:21.367899 DQ Delay:
3036 12:11:21.371422 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3037 12:11:21.374404 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3038 12:11:21.377840 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3039 12:11:21.381299 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3040 12:11:21.381383
3041 12:11:21.381452
3042 12:11:21.391042 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3043 12:11:21.391128 CH0 RK1: MR19=403, MR18=DF4
3044 12:11:21.398193 CH0_RK1: MR19=0x403, MR18=0xDF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3045 12:11:21.401287 [RxdqsGatingPostProcess] freq 1200
3046 12:11:21.408115 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3047 12:11:21.411160 best DQS0 dly(2T, 0.5T) = (0, 11)
3048 12:11:21.414717 best DQS1 dly(2T, 0.5T) = (0, 12)
3049 12:11:21.417725 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3050 12:11:21.421223 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3051 12:11:21.424190 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 12:11:21.427701 best DQS1 dly(2T, 0.5T) = (0, 11)
3053 12:11:21.431275 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 12:11:21.434282 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3055 12:11:21.434367 Pre-setting of DQS Precalculation
3056 12:11:21.441039 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3057 12:11:21.441125 ==
3058 12:11:21.444174 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 12:11:21.447860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 12:11:21.447944 ==
3061 12:11:21.454355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3062 12:11:21.460934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3063 12:11:21.468251 [CA 0] Center 37 (7~68) winsize 62
3064 12:11:21.471452 [CA 1] Center 37 (7~68) winsize 62
3065 12:11:21.474967 [CA 2] Center 35 (5~65) winsize 61
3066 12:11:21.478086 [CA 3] Center 34 (4~65) winsize 62
3067 12:11:21.481598 [CA 4] Center 34 (4~64) winsize 61
3068 12:11:21.484622 [CA 5] Center 33 (3~64) winsize 62
3069 12:11:21.484707
3070 12:11:21.488261 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3071 12:11:21.488372
3072 12:11:21.491360 [CATrainingPosCal] consider 1 rank data
3073 12:11:21.494925 u2DelayCellTimex100 = 270/100 ps
3074 12:11:21.498138 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 12:11:21.501229 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 12:11:21.507841 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3077 12:11:21.511460 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3078 12:11:21.514537 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3079 12:11:21.517981 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3080 12:11:21.518125
3081 12:11:21.521491 CA PerBit enable=1, Macro0, CA PI delay=33
3082 12:11:21.521595
3083 12:11:21.524859 [CBTSetCACLKResult] CA Dly = 33
3084 12:11:21.524937 CS Dly: 5 (0~36)
3085 12:11:21.527873 ==
3086 12:11:21.531363 Dram Type= 6, Freq= 0, CH_1, rank 1
3087 12:11:21.534445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 12:11:21.534521 ==
3089 12:11:21.537723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 12:11:21.544476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 12:11:21.553628 [CA 0] Center 38 (8~68) winsize 61
3092 12:11:21.557165 [CA 1] Center 38 (7~69) winsize 63
3093 12:11:21.560647 [CA 2] Center 35 (5~66) winsize 62
3094 12:11:21.563625 [CA 3] Center 35 (5~65) winsize 61
3095 12:11:21.567203 [CA 4] Center 34 (5~64) winsize 60
3096 12:11:21.570410 [CA 5] Center 33 (3~64) winsize 62
3097 12:11:21.570520
3098 12:11:21.573516 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 12:11:21.573602
3100 12:11:21.577164 [CATrainingPosCal] consider 2 rank data
3101 12:11:21.580322 u2DelayCellTimex100 = 270/100 ps
3102 12:11:21.583803 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3103 12:11:21.587286 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3104 12:11:21.593514 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3105 12:11:21.597010 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3106 12:11:21.600126 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3107 12:11:21.603731 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3108 12:11:21.603831
3109 12:11:21.606907 CA PerBit enable=1, Macro0, CA PI delay=33
3110 12:11:21.607010
3111 12:11:21.610486 [CBTSetCACLKResult] CA Dly = 33
3112 12:11:21.610584 CS Dly: 6 (0~39)
3113 12:11:21.610676
3114 12:11:21.613599 ----->DramcWriteLeveling(PI) begin...
3115 12:11:21.616744 ==
3116 12:11:21.620447 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 12:11:21.623707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 12:11:21.623816 ==
3119 12:11:21.626724 Write leveling (Byte 0): 24 => 24
3120 12:11:21.630170 Write leveling (Byte 1): 28 => 28
3121 12:11:21.633815 DramcWriteLeveling(PI) end<-----
3122 12:11:21.633895
3123 12:11:21.633962 ==
3124 12:11:21.637146 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 12:11:21.640294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 12:11:21.640398 ==
3127 12:11:21.643849 [Gating] SW mode calibration
3128 12:11:21.650626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3129 12:11:21.653629 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3130 12:11:21.660155 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 12:11:21.663673 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 12:11:21.667119 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 12:11:21.673764 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 12:11:21.676863 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 12:11:21.680440 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 12:11:21.687001 0 15 24 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (1 0)
3137 12:11:21.690534 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 12:11:21.693902 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 12:11:21.700572 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 12:11:21.703810 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 12:11:21.706935 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 12:11:21.713629 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 12:11:21.716702 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3144 12:11:21.720438 1 0 24 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
3145 12:11:21.726588 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 12:11:21.730131 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 12:11:21.733621 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 12:11:21.740026 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 12:11:21.743533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 12:11:21.746571 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 12:11:21.753425 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3152 12:11:21.756388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3153 12:11:21.760023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3154 12:11:21.766549 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:11:21.769921 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:11:21.773024 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:11:21.779714 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:11:21.783265 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:11:21.786452 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:11:21.793116 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:11:21.796508 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:11:21.799655 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:11:21.803187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:11:21.809645 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:11:21.813077 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:11:21.816722 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:11:21.822874 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3168 12:11:21.826611 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3169 12:11:21.829716 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3170 12:11:21.833187 Total UI for P1: 0, mck2ui 16
3171 12:11:21.836211 best dqsien dly found for B0: ( 1, 3, 22)
3172 12:11:21.842789 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 12:11:21.842872 Total UI for P1: 0, mck2ui 16
3174 12:11:21.849422 best dqsien dly found for B1: ( 1, 3, 26)
3175 12:11:21.852773 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3176 12:11:21.856216 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3177 12:11:21.856304
3178 12:11:21.859616 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3179 12:11:21.863289 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3180 12:11:21.866251 [Gating] SW calibration Done
3181 12:11:21.866339 ==
3182 12:11:21.869804 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 12:11:21.872640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 12:11:21.872746 ==
3185 12:11:21.876230 RX Vref Scan: 0
3186 12:11:21.876304
3187 12:11:21.876369 RX Vref 0 -> 0, step: 1
3188 12:11:21.876434
3189 12:11:21.879701 RX Delay -40 -> 252, step: 8
3190 12:11:21.885946 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3191 12:11:21.889634 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3192 12:11:21.892679 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3193 12:11:21.895870 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3194 12:11:21.899404 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3195 12:11:21.905848 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3196 12:11:21.909067 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3197 12:11:21.912633 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3198 12:11:21.915711 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3199 12:11:21.919402 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3200 12:11:21.922465 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3201 12:11:21.929198 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3202 12:11:21.932284 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3203 12:11:21.935884 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3204 12:11:21.939206 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3205 12:11:21.945540 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3206 12:11:21.945626 ==
3207 12:11:21.949044 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 12:11:21.952225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 12:11:21.952312 ==
3210 12:11:21.952381 DQS Delay:
3211 12:11:21.955674 DQS0 = 0, DQS1 = 0
3212 12:11:21.955759 DQM Delay:
3213 12:11:21.959157 DQM0 = 120, DQM1 = 112
3214 12:11:21.959242 DQ Delay:
3215 12:11:21.962258 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3216 12:11:21.965810 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =123
3217 12:11:21.968928 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3218 12:11:21.972539 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3219 12:11:21.972624
3220 12:11:21.972692
3221 12:11:21.975473 ==
3222 12:11:21.975558 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 12:11:21.982194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 12:11:21.982279 ==
3225 12:11:21.982348
3226 12:11:21.982410
3227 12:11:21.985316 TX Vref Scan disable
3228 12:11:21.985401 == TX Byte 0 ==
3229 12:11:21.989003 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3230 12:11:21.995811 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3231 12:11:21.995897 == TX Byte 1 ==
3232 12:11:21.998850 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3233 12:11:22.005472 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3234 12:11:22.005559 ==
3235 12:11:22.009010 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 12:11:22.012120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 12:11:22.012207 ==
3238 12:11:22.024088 TX Vref=22, minBit 1, minWin=24, winSum=405
3239 12:11:22.027546 TX Vref=24, minBit 3, minWin=25, winSum=412
3240 12:11:22.030543 TX Vref=26, minBit 9, minWin=25, winSum=417
3241 12:11:22.033644 TX Vref=28, minBit 9, minWin=25, winSum=421
3242 12:11:22.037142 TX Vref=30, minBit 10, minWin=25, winSum=420
3243 12:11:22.044229 TX Vref=32, minBit 1, minWin=26, winSum=425
3244 12:11:22.047034 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 32
3245 12:11:22.047143
3246 12:11:22.050453 Final TX Range 1 Vref 32
3247 12:11:22.050567
3248 12:11:22.050677 ==
3249 12:11:22.053736 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 12:11:22.057273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 12:11:22.057380 ==
3252 12:11:22.060624
3253 12:11:22.060733
3254 12:11:22.060846 TX Vref Scan disable
3255 12:11:22.063526 == TX Byte 0 ==
3256 12:11:22.067031 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3257 12:11:22.073780 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3258 12:11:22.073885 == TX Byte 1 ==
3259 12:11:22.076735 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3260 12:11:22.083889 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3261 12:11:22.083970
3262 12:11:22.084037 [DATLAT]
3263 12:11:22.084116 Freq=1200, CH1 RK0
3264 12:11:22.084216
3265 12:11:22.086854 DATLAT Default: 0xd
3266 12:11:22.086953 0, 0xFFFF, sum = 0
3267 12:11:22.090477 1, 0xFFFF, sum = 0
3268 12:11:22.093556 2, 0xFFFF, sum = 0
3269 12:11:22.093664 3, 0xFFFF, sum = 0
3270 12:11:22.096595 4, 0xFFFF, sum = 0
3271 12:11:22.096701 5, 0xFFFF, sum = 0
3272 12:11:22.100144 6, 0xFFFF, sum = 0
3273 12:11:22.100265 7, 0xFFFF, sum = 0
3274 12:11:22.103291 8, 0xFFFF, sum = 0
3275 12:11:22.103397 9, 0xFFFF, sum = 0
3276 12:11:22.106757 10, 0xFFFF, sum = 0
3277 12:11:22.106861 11, 0xFFFF, sum = 0
3278 12:11:22.110245 12, 0x0, sum = 1
3279 12:11:22.110354 13, 0x0, sum = 2
3280 12:11:22.113234 14, 0x0, sum = 3
3281 12:11:22.113339 15, 0x0, sum = 4
3282 12:11:22.116496 best_step = 13
3283 12:11:22.116597
3284 12:11:22.116692 ==
3285 12:11:22.120160 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 12:11:22.123255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 12:11:22.123360 ==
3288 12:11:22.123456 RX Vref Scan: 1
3289 12:11:22.126948
3290 12:11:22.127045 Set Vref Range= 32 -> 127
3291 12:11:22.127136
3292 12:11:22.130003 RX Vref 32 -> 127, step: 1
3293 12:11:22.130071
3294 12:11:22.133464 RX Delay -13 -> 252, step: 4
3295 12:11:22.133534
3296 12:11:22.136592 Set Vref, RX VrefLevel [Byte0]: 32
3297 12:11:22.139752 [Byte1]: 32
3298 12:11:22.139833
3299 12:11:22.143167 Set Vref, RX VrefLevel [Byte0]: 33
3300 12:11:22.146454 [Byte1]: 33
3301 12:11:22.150028
3302 12:11:22.150139 Set Vref, RX VrefLevel [Byte0]: 34
3303 12:11:22.153440 [Byte1]: 34
3304 12:11:22.157916
3305 12:11:22.157990 Set Vref, RX VrefLevel [Byte0]: 35
3306 12:11:22.161263 [Byte1]: 35
3307 12:11:22.165708
3308 12:11:22.165813 Set Vref, RX VrefLevel [Byte0]: 36
3309 12:11:22.169263 [Byte1]: 36
3310 12:11:22.173741
3311 12:11:22.173845 Set Vref, RX VrefLevel [Byte0]: 37
3312 12:11:22.177266 [Byte1]: 37
3313 12:11:22.181992
3314 12:11:22.182097 Set Vref, RX VrefLevel [Byte0]: 38
3315 12:11:22.185013 [Byte1]: 38
3316 12:11:22.189627
3317 12:11:22.189740 Set Vref, RX VrefLevel [Byte0]: 39
3318 12:11:22.193248 [Byte1]: 39
3319 12:11:22.197676
3320 12:11:22.197778 Set Vref, RX VrefLevel [Byte0]: 40
3321 12:11:22.200731 [Byte1]: 40
3322 12:11:22.205527
3323 12:11:22.205638 Set Vref, RX VrefLevel [Byte0]: 41
3324 12:11:22.208540 [Byte1]: 41
3325 12:11:22.213205
3326 12:11:22.213313 Set Vref, RX VrefLevel [Byte0]: 42
3327 12:11:22.216733 [Byte1]: 42
3328 12:11:22.220989
3329 12:11:22.221092 Set Vref, RX VrefLevel [Byte0]: 43
3330 12:11:22.224525 [Byte1]: 43
3331 12:11:22.229234
3332 12:11:22.229319 Set Vref, RX VrefLevel [Byte0]: 44
3333 12:11:22.232370 [Byte1]: 44
3334 12:11:22.236977
3335 12:11:22.237076 Set Vref, RX VrefLevel [Byte0]: 45
3336 12:11:22.240051 [Byte1]: 45
3337 12:11:22.244653
3338 12:11:22.244757 Set Vref, RX VrefLevel [Byte0]: 46
3339 12:11:22.248152 [Byte1]: 46
3340 12:11:22.252633
3341 12:11:22.252741 Set Vref, RX VrefLevel [Byte0]: 47
3342 12:11:22.256150 [Byte1]: 47
3343 12:11:22.260377
3344 12:11:22.260502 Set Vref, RX VrefLevel [Byte0]: 48
3345 12:11:22.263752 [Byte1]: 48
3346 12:11:22.268654
3347 12:11:22.268797 Set Vref, RX VrefLevel [Byte0]: 49
3348 12:11:22.271612 [Byte1]: 49
3349 12:11:22.276609
3350 12:11:22.276714 Set Vref, RX VrefLevel [Byte0]: 50
3351 12:11:22.279732 [Byte1]: 50
3352 12:11:22.284470
3353 12:11:22.284575 Set Vref, RX VrefLevel [Byte0]: 51
3354 12:11:22.287478 [Byte1]: 51
3355 12:11:22.291901
3356 12:11:22.292018 Set Vref, RX VrefLevel [Byte0]: 52
3357 12:11:22.295425 [Byte1]: 52
3358 12:11:22.299972
3359 12:11:22.300073 Set Vref, RX VrefLevel [Byte0]: 53
3360 12:11:22.303011 [Byte1]: 53
3361 12:11:22.307817
3362 12:11:22.307934 Set Vref, RX VrefLevel [Byte0]: 54
3363 12:11:22.310958 [Byte1]: 54
3364 12:11:22.316020
3365 12:11:22.316139 Set Vref, RX VrefLevel [Byte0]: 55
3366 12:11:22.319150 [Byte1]: 55
3367 12:11:22.323366
3368 12:11:22.323458 Set Vref, RX VrefLevel [Byte0]: 56
3369 12:11:22.326933 [Byte1]: 56
3370 12:11:22.331617
3371 12:11:22.331735 Set Vref, RX VrefLevel [Byte0]: 57
3372 12:11:22.334658 [Byte1]: 57
3373 12:11:22.339228
3374 12:11:22.339362 Set Vref, RX VrefLevel [Byte0]: 58
3375 12:11:22.342934 [Byte1]: 58
3376 12:11:22.347342
3377 12:11:22.347447 Set Vref, RX VrefLevel [Byte0]: 59
3378 12:11:22.350447 [Byte1]: 59
3379 12:11:22.355480
3380 12:11:22.355557 Set Vref, RX VrefLevel [Byte0]: 60
3381 12:11:22.358346 [Byte1]: 60
3382 12:11:22.363141
3383 12:11:22.363243 Set Vref, RX VrefLevel [Byte0]: 61
3384 12:11:22.366437 [Byte1]: 61
3385 12:11:22.370861
3386 12:11:22.370966 Set Vref, RX VrefLevel [Byte0]: 62
3387 12:11:22.374193 [Byte1]: 62
3388 12:11:22.379026
3389 12:11:22.379130 Set Vref, RX VrefLevel [Byte0]: 63
3390 12:11:22.382025 [Byte1]: 63
3391 12:11:22.386530
3392 12:11:22.386636 Set Vref, RX VrefLevel [Byte0]: 64
3393 12:11:22.390205 [Byte1]: 64
3394 12:11:22.394546
3395 12:11:22.394652 Set Vref, RX VrefLevel [Byte0]: 65
3396 12:11:22.397634 [Byte1]: 65
3397 12:11:22.402231
3398 12:11:22.402337 Set Vref, RX VrefLevel [Byte0]: 66
3399 12:11:22.405772 [Byte1]: 66
3400 12:11:22.410530
3401 12:11:22.410634 Set Vref, RX VrefLevel [Byte0]: 67
3402 12:11:22.413717 [Byte1]: 67
3403 12:11:22.418372
3404 12:11:22.418478 Final RX Vref Byte 0 = 53 to rank0
3405 12:11:22.421852 Final RX Vref Byte 1 = 55 to rank0
3406 12:11:22.424891 Final RX Vref Byte 0 = 53 to rank1
3407 12:11:22.428456 Final RX Vref Byte 1 = 55 to rank1==
3408 12:11:22.431584 Dram Type= 6, Freq= 0, CH_1, rank 0
3409 12:11:22.435185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3410 12:11:22.438236 ==
3411 12:11:22.438340 DQS Delay:
3412 12:11:22.438442 DQS0 = 0, DQS1 = 0
3413 12:11:22.441421 DQM Delay:
3414 12:11:22.441523 DQM0 = 119, DQM1 = 113
3415 12:11:22.444901 DQ Delay:
3416 12:11:22.448009 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3417 12:11:22.451670 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =116
3418 12:11:22.454731 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3419 12:11:22.457879 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3420 12:11:22.457983
3421 12:11:22.458079
3422 12:11:22.468361 [DQSOSCAuto] RK0, (LSB)MR18= 0x417, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3423 12:11:22.468479 CH1 RK0: MR19=404, MR18=417
3424 12:11:22.474802 CH1_RK0: MR19=0x404, MR18=0x417, DQSOSC=401, MR23=63, INC=40, DEC=27
3425 12:11:22.474891
3426 12:11:22.477816 ----->DramcWriteLeveling(PI) begin...
3427 12:11:22.477903 ==
3428 12:11:22.481399 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 12:11:22.484866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 12:11:22.487846 ==
3431 12:11:22.487926 Write leveling (Byte 0): 25 => 25
3432 12:11:22.491547 Write leveling (Byte 1): 29 => 29
3433 12:11:22.494649 DramcWriteLeveling(PI) end<-----
3434 12:11:22.494736
3435 12:11:22.494806 ==
3436 12:11:22.498030 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 12:11:22.504810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 12:11:22.504898 ==
3439 12:11:22.504968 [Gating] SW mode calibration
3440 12:11:22.515022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3441 12:11:22.518195 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3442 12:11:22.521425 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 12:11:22.527974 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 12:11:22.531386 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 12:11:22.534563 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 12:11:22.541418 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 12:11:22.544514 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 12:11:22.548117 0 15 24 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 0)
3449 12:11:22.554717 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (1 0)
3450 12:11:22.557826 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 12:11:22.561241 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 12:11:22.567744 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 12:11:22.571115 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 12:11:22.574494 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 12:11:22.581444 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3456 12:11:22.584462 1 0 24 | B1->B0 | 3e3e 2f2f | 0 0 | (0 0) (1 1)
3457 12:11:22.587928 1 0 28 | B1->B0 | 4646 3e3e | 0 1 | (0 0) (1 1)
3458 12:11:22.594733 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 12:11:22.597786 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 12:11:22.601232 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 12:11:22.607620 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 12:11:22.611124 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 12:11:22.614326 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3464 12:11:22.620904 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3465 12:11:22.623962 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 12:11:22.627590 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:11:22.634256 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:11:22.637391 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:11:22.640604 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:11:22.647731 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:11:22.650872 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:11:22.654000 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:11:22.660644 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:11:22.663802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:11:22.667517 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:11:22.673671 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:11:22.677224 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:11:22.680017 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:11:22.686953 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3480 12:11:22.690475 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3481 12:11:22.693403 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 12:11:22.696922 Total UI for P1: 0, mck2ui 16
3483 12:11:22.700049 best dqsien dly found for B0: ( 1, 3, 22)
3484 12:11:22.703685 Total UI for P1: 0, mck2ui 16
3485 12:11:22.706987 best dqsien dly found for B1: ( 1, 3, 24)
3486 12:11:22.710067 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3487 12:11:22.713758 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3488 12:11:22.713843
3489 12:11:22.716967 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3490 12:11:22.723443 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3491 12:11:22.723528 [Gating] SW calibration Done
3492 12:11:22.723596 ==
3493 12:11:22.726582 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 12:11:22.733169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 12:11:22.733255 ==
3496 12:11:22.733327 RX Vref Scan: 0
3497 12:11:22.733391
3498 12:11:22.736467 RX Vref 0 -> 0, step: 1
3499 12:11:22.736578
3500 12:11:22.740179 RX Delay -40 -> 252, step: 8
3501 12:11:22.743252 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3502 12:11:22.746698 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3503 12:11:22.749800 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3504 12:11:22.756632 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3505 12:11:22.760254 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3506 12:11:22.763236 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3507 12:11:22.766718 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3508 12:11:22.769764 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3509 12:11:22.776359 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3510 12:11:22.779882 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3511 12:11:22.783269 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3512 12:11:22.786702 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3513 12:11:22.789699 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3514 12:11:22.796603 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3515 12:11:22.799530 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3516 12:11:22.803191 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3517 12:11:22.803305 ==
3518 12:11:22.806271 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 12:11:22.809689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 12:11:22.809805 ==
3521 12:11:22.813075 DQS Delay:
3522 12:11:22.813160 DQS0 = 0, DQS1 = 0
3523 12:11:22.816710 DQM Delay:
3524 12:11:22.816820 DQM0 = 119, DQM1 = 112
3525 12:11:22.816890 DQ Delay:
3526 12:11:22.822856 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3527 12:11:22.826472 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3528 12:11:22.829671 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3529 12:11:22.832723 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3530 12:11:22.832817
3531 12:11:22.832887
3532 12:11:22.832950 ==
3533 12:11:22.836171 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 12:11:22.839607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 12:11:22.839722 ==
3536 12:11:22.839819
3537 12:11:22.839911
3538 12:11:22.843301 TX Vref Scan disable
3539 12:11:22.846270 == TX Byte 0 ==
3540 12:11:22.849299 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3541 12:11:22.853003 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3542 12:11:22.856110 == TX Byte 1 ==
3543 12:11:22.859669 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3544 12:11:22.862894 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3545 12:11:22.863001 ==
3546 12:11:22.865921 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 12:11:22.869443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 12:11:22.872627 ==
3549 12:11:22.882915 TX Vref=22, minBit 1, minWin=25, winSum=416
3550 12:11:22.886427 TX Vref=24, minBit 3, minWin=25, winSum=422
3551 12:11:22.889383 TX Vref=26, minBit 1, minWin=26, winSum=424
3552 12:11:22.892748 TX Vref=28, minBit 1, minWin=26, winSum=428
3553 12:11:22.896072 TX Vref=30, minBit 9, minWin=25, winSum=427
3554 12:11:22.902840 TX Vref=32, minBit 1, minWin=26, winSum=429
3555 12:11:22.905929 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 32
3556 12:11:22.906014
3557 12:11:22.909434 Final TX Range 1 Vref 32
3558 12:11:22.909546
3559 12:11:22.909623 ==
3560 12:11:22.912443 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 12:11:22.915822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 12:11:22.918882 ==
3563 12:11:22.918987
3564 12:11:22.919084
3565 12:11:22.919208 TX Vref Scan disable
3566 12:11:22.922492 == TX Byte 0 ==
3567 12:11:22.925709 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3568 12:11:22.932452 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3569 12:11:22.932536 == TX Byte 1 ==
3570 12:11:22.936029 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3571 12:11:22.942590 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3572 12:11:22.942674
3573 12:11:22.942741 [DATLAT]
3574 12:11:22.942850 Freq=1200, CH1 RK1
3575 12:11:22.942952
3576 12:11:22.945780 DATLAT Default: 0xd
3577 12:11:22.948970 0, 0xFFFF, sum = 0
3578 12:11:22.949072 1, 0xFFFF, sum = 0
3579 12:11:22.952121 2, 0xFFFF, sum = 0
3580 12:11:22.952205 3, 0xFFFF, sum = 0
3581 12:11:22.955850 4, 0xFFFF, sum = 0
3582 12:11:22.955934 5, 0xFFFF, sum = 0
3583 12:11:22.958830 6, 0xFFFF, sum = 0
3584 12:11:22.958930 7, 0xFFFF, sum = 0
3585 12:11:22.962386 8, 0xFFFF, sum = 0
3586 12:11:22.962471 9, 0xFFFF, sum = 0
3587 12:11:22.965871 10, 0xFFFF, sum = 0
3588 12:11:22.965956 11, 0xFFFF, sum = 0
3589 12:11:22.969014 12, 0x0, sum = 1
3590 12:11:22.969099 13, 0x0, sum = 2
3591 12:11:22.972122 14, 0x0, sum = 3
3592 12:11:22.972207 15, 0x0, sum = 4
3593 12:11:22.975717 best_step = 13
3594 12:11:22.975800
3595 12:11:22.975903 ==
3596 12:11:22.978629 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 12:11:22.982329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 12:11:22.982416 ==
3599 12:11:22.985240 RX Vref Scan: 0
3600 12:11:22.985331
3601 12:11:22.985446 RX Vref 0 -> 0, step: 1
3602 12:11:22.985541
3603 12:11:22.988418 RX Delay -13 -> 252, step: 4
3604 12:11:22.995273 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3605 12:11:22.998641 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3606 12:11:23.001967 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3607 12:11:23.005283 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3608 12:11:23.008745 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3609 12:11:23.015141 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3610 12:11:23.018078 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3611 12:11:23.021505 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3612 12:11:23.025114 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3613 12:11:23.028244 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3614 12:11:23.034719 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3615 12:11:23.038400 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3616 12:11:23.041487 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3617 12:11:23.045006 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3618 12:11:23.047983 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3619 12:11:23.054647 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3620 12:11:23.054760 ==
3621 12:11:23.058234 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 12:11:23.061364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 12:11:23.061476 ==
3624 12:11:23.061577 DQS Delay:
3625 12:11:23.064388 DQS0 = 0, DQS1 = 0
3626 12:11:23.064479 DQM Delay:
3627 12:11:23.067999 DQM0 = 119, DQM1 = 113
3628 12:11:23.068110 DQ Delay:
3629 12:11:23.071114 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3630 12:11:23.074727 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3631 12:11:23.077872 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3632 12:11:23.084577 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =124
3633 12:11:23.084728
3634 12:11:23.084870
3635 12:11:23.091372 [DQSOSCAuto] RK1, (LSB)MR18= 0xaee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3636 12:11:23.094496 CH1 RK1: MR19=403, MR18=AEE
3637 12:11:23.100867 CH1_RK1: MR19=0x403, MR18=0xAEE, DQSOSC=406, MR23=63, INC=39, DEC=26
3638 12:11:23.104226 [RxdqsGatingPostProcess] freq 1200
3639 12:11:23.107646 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3640 12:11:23.110898 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 12:11:23.114448 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 12:11:23.117449 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 12:11:23.121088 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 12:11:23.124015 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 12:11:23.127475 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 12:11:23.130669 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 12:11:23.134265 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 12:11:23.137408 Pre-setting of DQS Precalculation
3649 12:11:23.140472 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3650 12:11:23.150751 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3651 12:11:23.157078 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3652 12:11:23.157190
3653 12:11:23.157289
3654 12:11:23.160706 [Calibration Summary] 2400 Mbps
3655 12:11:23.160820 CH 0, Rank 0
3656 12:11:23.163746 SW Impedance : PASS
3657 12:11:23.163851 DUTY Scan : NO K
3658 12:11:23.166957 ZQ Calibration : PASS
3659 12:11:23.170603 Jitter Meter : NO K
3660 12:11:23.170709 CBT Training : PASS
3661 12:11:23.173706 Write leveling : PASS
3662 12:11:23.176822 RX DQS gating : PASS
3663 12:11:23.176923 RX DQ/DQS(RDDQC) : PASS
3664 12:11:23.180351 TX DQ/DQS : PASS
3665 12:11:23.183561 RX DATLAT : PASS
3666 12:11:23.183634 RX DQ/DQS(Engine): PASS
3667 12:11:23.186759 TX OE : NO K
3668 12:11:23.186834 All Pass.
3669 12:11:23.186899
3670 12:11:23.190254 CH 0, Rank 1
3671 12:11:23.190352 SW Impedance : PASS
3672 12:11:23.193314 DUTY Scan : NO K
3673 12:11:23.193420 ZQ Calibration : PASS
3674 12:11:23.197028 Jitter Meter : NO K
3675 12:11:23.199976 CBT Training : PASS
3676 12:11:23.200090 Write leveling : PASS
3677 12:11:23.203496 RX DQS gating : PASS
3678 12:11:23.206979 RX DQ/DQS(RDDQC) : PASS
3679 12:11:23.207072 TX DQ/DQS : PASS
3680 12:11:23.209856 RX DATLAT : PASS
3681 12:11:23.213385 RX DQ/DQS(Engine): PASS
3682 12:11:23.213488 TX OE : NO K
3683 12:11:23.216680 All Pass.
3684 12:11:23.216789
3685 12:11:23.216885 CH 1, Rank 0
3686 12:11:23.219681 SW Impedance : PASS
3687 12:11:23.219781 DUTY Scan : NO K
3688 12:11:23.223308 ZQ Calibration : PASS
3689 12:11:23.226642 Jitter Meter : NO K
3690 12:11:23.226751 CBT Training : PASS
3691 12:11:23.229610 Write leveling : PASS
3692 12:11:23.233043 RX DQS gating : PASS
3693 12:11:23.233159 RX DQ/DQS(RDDQC) : PASS
3694 12:11:23.236187 TX DQ/DQS : PASS
3695 12:11:23.239795 RX DATLAT : PASS
3696 12:11:23.239870 RX DQ/DQS(Engine): PASS
3697 12:11:23.242968 TX OE : NO K
3698 12:11:23.243044 All Pass.
3699 12:11:23.243109
3700 12:11:23.246151 CH 1, Rank 1
3701 12:11:23.246222 SW Impedance : PASS
3702 12:11:23.249713 DUTY Scan : NO K
3703 12:11:23.252745 ZQ Calibration : PASS
3704 12:11:23.252839 Jitter Meter : NO K
3705 12:11:23.256395 CBT Training : PASS
3706 12:11:23.259270 Write leveling : PASS
3707 12:11:23.259356 RX DQS gating : PASS
3708 12:11:23.262897 RX DQ/DQS(RDDQC) : PASS
3709 12:11:23.262981 TX DQ/DQS : PASS
3710 12:11:23.265943 RX DATLAT : PASS
3711 12:11:23.269617 RX DQ/DQS(Engine): PASS
3712 12:11:23.269701 TX OE : NO K
3713 12:11:23.272729 All Pass.
3714 12:11:23.272830
3715 12:11:23.272898 DramC Write-DBI off
3716 12:11:23.275829 PER_BANK_REFRESH: Hybrid Mode
3717 12:11:23.279404 TX_TRACKING: ON
3718 12:11:23.286151 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3719 12:11:23.289291 [FAST_K] Save calibration result to emmc
3720 12:11:23.296018 dramc_set_vcore_voltage set vcore to 650000
3721 12:11:23.296103 Read voltage for 600, 5
3722 12:11:23.296173 Vio18 = 0
3723 12:11:23.299207 Vcore = 650000
3724 12:11:23.299290 Vdram = 0
3725 12:11:23.299363 Vddq = 0
3726 12:11:23.302332 Vmddr = 0
3727 12:11:23.305905 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3728 12:11:23.312464 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3729 12:11:23.315392 MEM_TYPE=3, freq_sel=19
3730 12:11:23.315537 sv_algorithm_assistance_LP4_1600
3731 12:11:23.322233 ============ PULL DRAM RESETB DOWN ============
3732 12:11:23.325683 ========== PULL DRAM RESETB DOWN end =========
3733 12:11:23.329052 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3734 12:11:23.332322 ===================================
3735 12:11:23.335576 LPDDR4 DRAM CONFIGURATION
3736 12:11:23.338643 ===================================
3737 12:11:23.342241 EX_ROW_EN[0] = 0x0
3738 12:11:23.342353 EX_ROW_EN[1] = 0x0
3739 12:11:23.345312 LP4Y_EN = 0x0
3740 12:11:23.345437 WORK_FSP = 0x0
3741 12:11:23.348475 WL = 0x2
3742 12:11:23.348573 RL = 0x2
3743 12:11:23.352060 BL = 0x2
3744 12:11:23.352157 RPST = 0x0
3745 12:11:23.355218 RD_PRE = 0x0
3746 12:11:23.355305 WR_PRE = 0x1
3747 12:11:23.358847 WR_PST = 0x0
3748 12:11:23.358938 DBI_WR = 0x0
3749 12:11:23.361839 DBI_RD = 0x0
3750 12:11:23.365409 OTF = 0x1
3751 12:11:23.368277 ===================================
3752 12:11:23.371513 ===================================
3753 12:11:23.371621 ANA top config
3754 12:11:23.375080 ===================================
3755 12:11:23.378214 DLL_ASYNC_EN = 0
3756 12:11:23.381849 ALL_SLAVE_EN = 1
3757 12:11:23.381922 NEW_RANK_MODE = 1
3758 12:11:23.384983 DLL_IDLE_MODE = 1
3759 12:11:23.388058 LP45_APHY_COMB_EN = 1
3760 12:11:23.391342 TX_ODT_DIS = 1
3761 12:11:23.391466 NEW_8X_MODE = 1
3762 12:11:23.394953 ===================================
3763 12:11:23.398129 ===================================
3764 12:11:23.401217 data_rate = 1200
3765 12:11:23.404450 CKR = 1
3766 12:11:23.407982 DQ_P2S_RATIO = 8
3767 12:11:23.411614 ===================================
3768 12:11:23.414595 CA_P2S_RATIO = 8
3769 12:11:23.418165 DQ_CA_OPEN = 0
3770 12:11:23.421212 DQ_SEMI_OPEN = 0
3771 12:11:23.421298 CA_SEMI_OPEN = 0
3772 12:11:23.424621 CA_FULL_RATE = 0
3773 12:11:23.427586 DQ_CKDIV4_EN = 1
3774 12:11:23.431119 CA_CKDIV4_EN = 1
3775 12:11:23.434572 CA_PREDIV_EN = 0
3776 12:11:23.437903 PH8_DLY = 0
3777 12:11:23.437979 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3778 12:11:23.440780 DQ_AAMCK_DIV = 4
3779 12:11:23.444290 CA_AAMCK_DIV = 4
3780 12:11:23.447379 CA_ADMCK_DIV = 4
3781 12:11:23.450910 DQ_TRACK_CA_EN = 0
3782 12:11:23.454132 CA_PICK = 600
3783 12:11:23.454214 CA_MCKIO = 600
3784 12:11:23.457710 MCKIO_SEMI = 0
3785 12:11:23.460693 PLL_FREQ = 2288
3786 12:11:23.464333 DQ_UI_PI_RATIO = 32
3787 12:11:23.467400 CA_UI_PI_RATIO = 0
3788 12:11:23.470886 ===================================
3789 12:11:23.474066 ===================================
3790 12:11:23.477181 memory_type:LPDDR4
3791 12:11:23.477256 GP_NUM : 10
3792 12:11:23.480811 SRAM_EN : 1
3793 12:11:23.480885 MD32_EN : 0
3794 12:11:23.483871 ===================================
3795 12:11:23.487457 [ANA_INIT] >>>>>>>>>>>>>>
3796 12:11:23.490636 <<<<<< [CONFIGURE PHASE]: ANA_TX
3797 12:11:23.493714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3798 12:11:23.497443 ===================================
3799 12:11:23.500652 data_rate = 1200,PCW = 0X5800
3800 12:11:23.503748 ===================================
3801 12:11:23.507242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3802 12:11:23.513524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 12:11:23.517062 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 12:11:23.523596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3805 12:11:23.527122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3806 12:11:23.530002 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3807 12:11:23.530081 [ANA_INIT] flow start
3808 12:11:23.533356 [ANA_INIT] PLL >>>>>>>>
3809 12:11:23.536652 [ANA_INIT] PLL <<<<<<<<
3810 12:11:23.536726 [ANA_INIT] MIDPI >>>>>>>>
3811 12:11:23.540039 [ANA_INIT] MIDPI <<<<<<<<
3812 12:11:23.543517 [ANA_INIT] DLL >>>>>>>>
3813 12:11:23.543590 [ANA_INIT] flow end
3814 12:11:23.549756 ============ LP4 DIFF to SE enter ============
3815 12:11:23.553541 ============ LP4 DIFF to SE exit ============
3816 12:11:23.556592 [ANA_INIT] <<<<<<<<<<<<<
3817 12:11:23.559743 [Flow] Enable top DCM control >>>>>
3818 12:11:23.563228 [Flow] Enable top DCM control <<<<<
3819 12:11:23.566399 Enable DLL master slave shuffle
3820 12:11:23.570011 ==============================================================
3821 12:11:23.572906 Gating Mode config
3822 12:11:23.576531 ==============================================================
3823 12:11:23.579680 Config description:
3824 12:11:23.589891 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3825 12:11:23.596166 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3826 12:11:23.599792 SELPH_MODE 0: By rank 1: By Phase
3827 12:11:23.606430 ==============================================================
3828 12:11:23.609487 GAT_TRACK_EN = 1
3829 12:11:23.612438 RX_GATING_MODE = 2
3830 12:11:23.615998 RX_GATING_TRACK_MODE = 2
3831 12:11:23.619141 SELPH_MODE = 1
3832 12:11:23.622795 PICG_EARLY_EN = 1
3833 12:11:23.625946 VALID_LAT_VALUE = 1
3834 12:11:23.629463 ==============================================================
3835 12:11:23.632391 Enter into Gating configuration >>>>
3836 12:11:23.635734 Exit from Gating configuration <<<<
3837 12:11:23.639147 Enter into DVFS_PRE_config >>>>>
3838 12:11:23.649235 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3839 12:11:23.652583 Exit from DVFS_PRE_config <<<<<
3840 12:11:23.655889 Enter into PICG configuration >>>>
3841 12:11:23.659483 Exit from PICG configuration <<<<
3842 12:11:23.662530 [RX_INPUT] configuration >>>>>
3843 12:11:23.666020 [RX_INPUT] configuration <<<<<
3844 12:11:23.672248 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3845 12:11:23.675582 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3846 12:11:23.682131 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 12:11:23.688798 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 12:11:23.695366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 12:11:23.702189 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 12:11:23.705153 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3851 12:11:23.708665 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3852 12:11:23.712157 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3853 12:11:23.718471 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3854 12:11:23.722234 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3855 12:11:23.725333 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 12:11:23.728446 ===================================
3857 12:11:23.732083 LPDDR4 DRAM CONFIGURATION
3858 12:11:23.735051 ===================================
3859 12:11:23.738625 EX_ROW_EN[0] = 0x0
3860 12:11:23.738743 EX_ROW_EN[1] = 0x0
3861 12:11:23.741932 LP4Y_EN = 0x0
3862 12:11:23.742018 WORK_FSP = 0x0
3863 12:11:23.745295 WL = 0x2
3864 12:11:23.745375 RL = 0x2
3865 12:11:23.748717 BL = 0x2
3866 12:11:23.748813 RPST = 0x0
3867 12:11:23.752066 RD_PRE = 0x0
3868 12:11:23.752139 WR_PRE = 0x1
3869 12:11:23.755307 WR_PST = 0x0
3870 12:11:23.755421 DBI_WR = 0x0
3871 12:11:23.758765 DBI_RD = 0x0
3872 12:11:23.758842 OTF = 0x1
3873 12:11:23.761580 ===================================
3874 12:11:23.764905 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3875 12:11:23.771386 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3876 12:11:23.775055 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 12:11:23.778151 ===================================
3878 12:11:23.781775 LPDDR4 DRAM CONFIGURATION
3879 12:11:23.784777 ===================================
3880 12:11:23.784887 EX_ROW_EN[0] = 0x10
3881 12:11:23.788415 EX_ROW_EN[1] = 0x0
3882 12:11:23.791500 LP4Y_EN = 0x0
3883 12:11:23.791610 WORK_FSP = 0x0
3884 12:11:23.794927 WL = 0x2
3885 12:11:23.795030 RL = 0x2
3886 12:11:23.798057 BL = 0x2
3887 12:11:23.798163 RPST = 0x0
3888 12:11:23.801792 RD_PRE = 0x0
3889 12:11:23.801898 WR_PRE = 0x1
3890 12:11:23.804829 WR_PST = 0x0
3891 12:11:23.804931 DBI_WR = 0x0
3892 12:11:23.808029 DBI_RD = 0x0
3893 12:11:23.808128 OTF = 0x1
3894 12:11:23.811634 ===================================
3895 12:11:23.818227 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3896 12:11:23.822394 nWR fixed to 30
3897 12:11:23.825919 [ModeRegInit_LP4] CH0 RK0
3898 12:11:23.826026 [ModeRegInit_LP4] CH0 RK1
3899 12:11:23.829045 [ModeRegInit_LP4] CH1 RK0
3900 12:11:23.832127 [ModeRegInit_LP4] CH1 RK1
3901 12:11:23.832227 match AC timing 17
3902 12:11:23.838642 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3903 12:11:23.842237 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3904 12:11:23.845218 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3905 12:11:23.852009 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3906 12:11:23.855291 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3907 12:11:23.855395 ==
3908 12:11:23.858627 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 12:11:23.861889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3910 12:11:23.861981 ==
3911 12:11:23.868627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3912 12:11:23.875304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3913 12:11:23.878661 [CA 0] Center 36 (6~67) winsize 62
3914 12:11:23.881687 [CA 1] Center 36 (6~67) winsize 62
3915 12:11:23.885240 [CA 2] Center 34 (4~65) winsize 62
3916 12:11:23.888315 [CA 3] Center 34 (4~65) winsize 62
3917 12:11:23.891419 [CA 4] Center 33 (3~64) winsize 62
3918 12:11:23.894549 [CA 5] Center 33 (2~64) winsize 63
3919 12:11:23.894634
3920 12:11:23.897969 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3921 12:11:23.898054
3922 12:11:23.901154 [CATrainingPosCal] consider 1 rank data
3923 12:11:23.904748 u2DelayCellTimex100 = 270/100 ps
3924 12:11:23.907798 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3925 12:11:23.911474 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3926 12:11:23.914587 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3927 12:11:23.921250 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3928 12:11:23.924282 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3929 12:11:23.927380 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3930 12:11:23.927477
3931 12:11:23.930617 CA PerBit enable=1, Macro0, CA PI delay=33
3932 12:11:23.930699
3933 12:11:23.934179 [CBTSetCACLKResult] CA Dly = 33
3934 12:11:23.934261 CS Dly: 4 (0~35)
3935 12:11:23.937144 ==
3936 12:11:23.940774 Dram Type= 6, Freq= 0, CH_0, rank 1
3937 12:11:23.944016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 12:11:23.944099 ==
3939 12:11:23.947197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 12:11:23.953716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3941 12:11:23.957704 [CA 0] Center 36 (6~67) winsize 62
3942 12:11:23.961120 [CA 1] Center 36 (6~67) winsize 62
3943 12:11:23.964546 [CA 2] Center 34 (4~65) winsize 62
3944 12:11:23.967428 [CA 3] Center 34 (4~65) winsize 62
3945 12:11:23.970856 [CA 4] Center 33 (3~64) winsize 62
3946 12:11:23.974166 [CA 5] Center 33 (3~64) winsize 62
3947 12:11:23.974249
3948 12:11:23.977514 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3949 12:11:23.977614
3950 12:11:23.980944 [CATrainingPosCal] consider 2 rank data
3951 12:11:23.984309 u2DelayCellTimex100 = 270/100 ps
3952 12:11:23.987298 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3953 12:11:23.993916 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3954 12:11:23.997238 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3955 12:11:24.000658 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3956 12:11:24.003804 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3957 12:11:24.006982 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3958 12:11:24.007090
3959 12:11:24.010668 CA PerBit enable=1, Macro0, CA PI delay=33
3960 12:11:24.010777
3961 12:11:24.013812 [CBTSetCACLKResult] CA Dly = 33
3962 12:11:24.017027 CS Dly: 5 (0~37)
3963 12:11:24.017104
3964 12:11:24.020549 ----->DramcWriteLeveling(PI) begin...
3965 12:11:24.020651 ==
3966 12:11:24.023649 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 12:11:24.026730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 12:11:24.026830 ==
3969 12:11:24.029892 Write leveling (Byte 0): 31 => 31
3970 12:11:24.033542 Write leveling (Byte 1): 30 => 30
3971 12:11:24.036618 DramcWriteLeveling(PI) end<-----
3972 12:11:24.036727
3973 12:11:24.036861 ==
3974 12:11:24.040273 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 12:11:24.043240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 12:11:24.043314 ==
3977 12:11:24.046898 [Gating] SW mode calibration
3978 12:11:24.053181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3979 12:11:24.059567 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3980 12:11:24.063142 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 12:11:24.066581 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 12:11:24.072878 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3983 12:11:24.076279 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (0 0) (0 0)
3984 12:11:24.079761 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
3985 12:11:24.086209 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:11:24.089649 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 12:11:24.093043 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 12:11:24.099593 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 12:11:24.102723 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 12:11:24.106303 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 12:11:24.113084 0 10 12 | B1->B0 | 2424 3b3b | 0 1 | (0 0) (1 1)
3992 12:11:24.116186 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3993 12:11:24.119266 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:11:24.125900 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 12:11:24.129497 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 12:11:24.132575 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 12:11:24.139247 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 12:11:24.142366 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 12:11:24.145505 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 12:11:24.152227 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:11:24.155376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:11:24.158465 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:11:24.165483 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:11:24.168481 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:11:24.172073 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:11:24.178208 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:11:24.181655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:11:24.185075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:11:24.191796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:11:24.194674 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:11:24.198193 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:11:24.204602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:11:24.208172 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:11:24.211405 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:11:24.218166 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4016 12:11:24.221260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4017 12:11:24.224494 Total UI for P1: 0, mck2ui 16
4018 12:11:24.228016 best dqsien dly found for B0: ( 0, 13, 12)
4019 12:11:24.231201 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:11:24.234827 Total UI for P1: 0, mck2ui 16
4021 12:11:24.237855 best dqsien dly found for B1: ( 0, 13, 16)
4022 12:11:24.241026 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4023 12:11:24.248172 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4024 12:11:24.248256
4025 12:11:24.251287 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4026 12:11:24.254482 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4027 12:11:24.258038 [Gating] SW calibration Done
4028 12:11:24.258144 ==
4029 12:11:24.261147 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 12:11:24.264218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 12:11:24.264300 ==
4032 12:11:24.267741 RX Vref Scan: 0
4033 12:11:24.267841
4034 12:11:24.267933 RX Vref 0 -> 0, step: 1
4035 12:11:24.268026
4036 12:11:24.271110 RX Delay -230 -> 252, step: 16
4037 12:11:24.274213 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4038 12:11:24.280840 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 12:11:24.284183 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4040 12:11:24.287734 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4041 12:11:24.290978 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4042 12:11:24.297367 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4043 12:11:24.300510 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4044 12:11:24.303917 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4045 12:11:24.307286 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 12:11:24.310650 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4047 12:11:24.317259 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4048 12:11:24.320508 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4049 12:11:24.323672 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4050 12:11:24.327168 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4051 12:11:24.333882 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 12:11:24.336946 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4053 12:11:24.337023 ==
4054 12:11:24.340520 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 12:11:24.343572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 12:11:24.343681 ==
4057 12:11:24.346743 DQS Delay:
4058 12:11:24.346851 DQS0 = 0, DQS1 = 0
4059 12:11:24.350341 DQM Delay:
4060 12:11:24.350450 DQM0 = 50, DQM1 = 38
4061 12:11:24.350547 DQ Delay:
4062 12:11:24.353423 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4063 12:11:24.356985 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4064 12:11:24.359994 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =25
4065 12:11:24.363605 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4066 12:11:24.363749
4067 12:11:24.363847
4068 12:11:24.363956 ==
4069 12:11:24.366838 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 12:11:24.373260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 12:11:24.373377 ==
4072 12:11:24.373477
4073 12:11:24.373571
4074 12:11:24.373661 TX Vref Scan disable
4075 12:11:24.377227 == TX Byte 0 ==
4076 12:11:24.380439 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 12:11:24.387045 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 12:11:24.387131 == TX Byte 1 ==
4079 12:11:24.390368 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4080 12:11:24.397174 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4081 12:11:24.397273 ==
4082 12:11:24.400418 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 12:11:24.403547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 12:11:24.403632 ==
4085 12:11:24.403701
4086 12:11:24.403764
4087 12:11:24.406893 TX Vref Scan disable
4088 12:11:24.410206 == TX Byte 0 ==
4089 12:11:24.413468 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 12:11:24.416644 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 12:11:24.419866 == TX Byte 1 ==
4092 12:11:24.423529 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4093 12:11:24.426680 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4094 12:11:24.426765
4095 12:11:24.429704 [DATLAT]
4096 12:11:24.429789 Freq=600, CH0 RK0
4097 12:11:24.429858
4098 12:11:24.433439 DATLAT Default: 0x9
4099 12:11:24.433524 0, 0xFFFF, sum = 0
4100 12:11:24.436440 1, 0xFFFF, sum = 0
4101 12:11:24.436527 2, 0xFFFF, sum = 0
4102 12:11:24.439582 3, 0xFFFF, sum = 0
4103 12:11:24.439671 4, 0xFFFF, sum = 0
4104 12:11:24.442693 5, 0xFFFF, sum = 0
4105 12:11:24.442784 6, 0xFFFF, sum = 0
4106 12:11:24.446438 7, 0xFFFF, sum = 0
4107 12:11:24.446524 8, 0x0, sum = 1
4108 12:11:24.449698 9, 0x0, sum = 2
4109 12:11:24.449785 10, 0x0, sum = 3
4110 12:11:24.453213 11, 0x0, sum = 4
4111 12:11:24.453299 best_step = 9
4112 12:11:24.453367
4113 12:11:24.453431 ==
4114 12:11:24.456260 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 12:11:24.459945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 12:11:24.463100 ==
4117 12:11:24.463185 RX Vref Scan: 1
4118 12:11:24.463254
4119 12:11:24.466164 RX Vref 0 -> 0, step: 1
4120 12:11:24.466249
4121 12:11:24.469688 RX Delay -179 -> 252, step: 8
4122 12:11:24.469773
4123 12:11:24.472655 Set Vref, RX VrefLevel [Byte0]: 58
4124 12:11:24.472739 [Byte1]: 50
4125 12:11:24.478110
4126 12:11:24.478194 Final RX Vref Byte 0 = 58 to rank0
4127 12:11:24.481238 Final RX Vref Byte 1 = 50 to rank0
4128 12:11:24.484240 Final RX Vref Byte 0 = 58 to rank1
4129 12:11:24.487866 Final RX Vref Byte 1 = 50 to rank1==
4130 12:11:24.490949 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 12:11:24.497426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 12:11:24.497530 ==
4133 12:11:24.497626 DQS Delay:
4134 12:11:24.500697 DQS0 = 0, DQS1 = 0
4135 12:11:24.500809 DQM Delay:
4136 12:11:24.500880 DQM0 = 49, DQM1 = 37
4137 12:11:24.504257 DQ Delay:
4138 12:11:24.507649 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =48
4139 12:11:24.510746 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4140 12:11:24.514314 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4141 12:11:24.517216 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4142 12:11:24.517292
4143 12:11:24.517357
4144 12:11:24.524115 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4145 12:11:24.527571 CH0 RK0: MR19=808, MR18=5B55
4146 12:11:24.534154 CH0_RK0: MR19=0x808, MR18=0x5B55, DQSOSC=392, MR23=63, INC=170, DEC=113
4147 12:11:24.534255
4148 12:11:24.537342 ----->DramcWriteLeveling(PI) begin...
4149 12:11:24.537459 ==
4150 12:11:24.540278 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 12:11:24.543893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 12:11:24.544005 ==
4153 12:11:24.546872 Write leveling (Byte 0): 33 => 33
4154 12:11:24.550528 Write leveling (Byte 1): 32 => 32
4155 12:11:24.553661 DramcWriteLeveling(PI) end<-----
4156 12:11:24.553773
4157 12:11:24.553869 ==
4158 12:11:24.556730 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 12:11:24.560444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 12:11:24.563624 ==
4161 12:11:24.563708 [Gating] SW mode calibration
4162 12:11:24.573118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 12:11:24.576668 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 12:11:24.579660 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 12:11:24.586825 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 12:11:24.589855 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 12:11:24.593439 0 9 12 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 0)
4168 12:11:24.599584 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
4169 12:11:24.602916 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 12:11:24.606261 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 12:11:24.613175 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 12:11:24.616682 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 12:11:24.619662 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 12:11:24.626614 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4175 12:11:24.629507 0 10 12 | B1->B0 | 2e2e 3131 | 0 1 | (0 0) (0 0)
4176 12:11:24.632796 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 12:11:24.639350 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 12:11:24.642976 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 12:11:24.646034 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 12:11:24.652681 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 12:11:24.655746 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 12:11:24.659406 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 12:11:24.665726 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4184 12:11:24.669226 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:11:24.672474 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:11:24.679224 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:11:24.682186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:11:24.685613 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:11:24.692214 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:11:24.695802 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:11:24.698912 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:11:24.705535 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:11:24.708688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:11:24.712134 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:11:24.718670 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:11:24.722118 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:11:24.725467 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:11:24.731917 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:11:24.735309 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4200 12:11:24.738679 Total UI for P1: 0, mck2ui 16
4201 12:11:24.741973 best dqsien dly found for B1: ( 0, 13, 10)
4202 12:11:24.745240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 12:11:24.748394 Total UI for P1: 0, mck2ui 16
4204 12:11:24.751472 best dqsien dly found for B0: ( 0, 13, 12)
4205 12:11:24.755172 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 12:11:24.758202 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4207 12:11:24.758286
4208 12:11:24.764909 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 12:11:24.767986 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4210 12:11:24.771577 [Gating] SW calibration Done
4211 12:11:24.771678 ==
4212 12:11:24.774772 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 12:11:24.777882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 12:11:24.777971 ==
4215 12:11:24.778040 RX Vref Scan: 0
4216 12:11:24.781355
4217 12:11:24.781449 RX Vref 0 -> 0, step: 1
4218 12:11:24.781513
4219 12:11:24.784474 RX Delay -230 -> 252, step: 16
4220 12:11:24.787968 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4221 12:11:24.794486 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4222 12:11:24.797561 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4223 12:11:24.801158 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4224 12:11:24.804143 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4225 12:11:24.811177 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4226 12:11:24.814069 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4227 12:11:24.817155 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4228 12:11:24.820711 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4229 12:11:24.823746 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4230 12:11:24.830586 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4231 12:11:24.833877 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4232 12:11:24.837416 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4233 12:11:24.840469 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4234 12:11:24.847126 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4235 12:11:24.850661 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4236 12:11:24.850747 ==
4237 12:11:24.853814 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 12:11:24.856937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 12:11:24.857024 ==
4240 12:11:24.860439 DQS Delay:
4241 12:11:24.860532 DQS0 = 0, DQS1 = 0
4242 12:11:24.860602 DQM Delay:
4243 12:11:24.863655 DQM0 = 52, DQM1 = 42
4244 12:11:24.863741 DQ Delay:
4245 12:11:24.866753 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4246 12:11:24.870241 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4247 12:11:24.873295 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4248 12:11:24.876926 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4249 12:11:24.877019
4250 12:11:24.877090
4251 12:11:24.877155 ==
4252 12:11:24.879930 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 12:11:24.886509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 12:11:24.886587 ==
4255 12:11:24.886655
4256 12:11:24.886722
4257 12:11:24.886783 TX Vref Scan disable
4258 12:11:24.890656 == TX Byte 0 ==
4259 12:11:24.894119 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4260 12:11:24.900702 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4261 12:11:24.900813 == TX Byte 1 ==
4262 12:11:24.903874 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4263 12:11:24.910272 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4264 12:11:24.910354 ==
4265 12:11:24.913832 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 12:11:24.916867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 12:11:24.916948 ==
4268 12:11:24.917018
4269 12:11:24.917083
4270 12:11:24.920476 TX Vref Scan disable
4271 12:11:24.923485 == TX Byte 0 ==
4272 12:11:24.927142 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4273 12:11:24.930153 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4274 12:11:24.933606 == TX Byte 1 ==
4275 12:11:24.936914 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4276 12:11:24.940263 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4277 12:11:24.940366
4278 12:11:24.940462 [DATLAT]
4279 12:11:24.943603 Freq=600, CH0 RK1
4280 12:11:24.943678
4281 12:11:24.946907 DATLAT Default: 0x9
4282 12:11:24.946980 0, 0xFFFF, sum = 0
4283 12:11:24.949756 1, 0xFFFF, sum = 0
4284 12:11:24.949830 2, 0xFFFF, sum = 0
4285 12:11:24.953521 3, 0xFFFF, sum = 0
4286 12:11:24.953624 4, 0xFFFF, sum = 0
4287 12:11:24.956445 5, 0xFFFF, sum = 0
4288 12:11:24.956550 6, 0xFFFF, sum = 0
4289 12:11:24.959984 7, 0xFFFF, sum = 0
4290 12:11:24.960059 8, 0x0, sum = 1
4291 12:11:24.963105 9, 0x0, sum = 2
4292 12:11:24.963207 10, 0x0, sum = 3
4293 12:11:24.966128 11, 0x0, sum = 4
4294 12:11:24.966226 best_step = 9
4295 12:11:24.966318
4296 12:11:24.966407 ==
4297 12:11:24.969729 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 12:11:24.972940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 12:11:24.973013 ==
4300 12:11:24.976084 RX Vref Scan: 0
4301 12:11:24.976186
4302 12:11:24.979715 RX Vref 0 -> 0, step: 1
4303 12:11:24.979815
4304 12:11:24.979910 RX Delay -163 -> 252, step: 8
4305 12:11:24.987460 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4306 12:11:24.990657 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4307 12:11:24.994231 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4308 12:11:24.997317 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4309 12:11:25.000851 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4310 12:11:25.007088 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4311 12:11:25.010636 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4312 12:11:25.013655 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4313 12:11:25.017321 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4314 12:11:25.023981 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4315 12:11:25.027629 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4316 12:11:25.030507 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4317 12:11:25.034055 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4318 12:11:25.037519 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4319 12:11:25.043633 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4320 12:11:25.047083 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4321 12:11:25.047185 ==
4322 12:11:25.050525 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 12:11:25.053762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 12:11:25.053876 ==
4325 12:11:25.057001 DQS Delay:
4326 12:11:25.057108 DQS0 = 0, DQS1 = 0
4327 12:11:25.060282 DQM Delay:
4328 12:11:25.060386 DQM0 = 49, DQM1 = 41
4329 12:11:25.060484 DQ Delay:
4330 12:11:25.063546 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4331 12:11:25.066639 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4332 12:11:25.070243 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4333 12:11:25.073687 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =52
4334 12:11:25.073790
4335 12:11:25.073885
4336 12:11:25.083631 [DQSOSCAuto] RK1, (LSB)MR18= 0x6331, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4337 12:11:25.086737 CH0 RK1: MR19=808, MR18=6331
4338 12:11:25.093478 CH0_RK1: MR19=0x808, MR18=0x6331, DQSOSC=391, MR23=63, INC=171, DEC=114
4339 12:11:25.093562 [RxdqsGatingPostProcess] freq 600
4340 12:11:25.099985 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 12:11:25.103529 Pre-setting of DQS Precalculation
4342 12:11:25.106519 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 12:11:25.110151 ==
4344 12:11:25.110258 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 12:11:25.116382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 12:11:25.116487 ==
4347 12:11:25.120039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 12:11:25.126205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4349 12:11:25.130243 [CA 0] Center 35 (5~66) winsize 62
4350 12:11:25.133747 [CA 1] Center 35 (5~66) winsize 62
4351 12:11:25.136743 [CA 2] Center 34 (4~65) winsize 62
4352 12:11:25.139862 [CA 3] Center 33 (3~64) winsize 62
4353 12:11:25.143448 [CA 4] Center 33 (3~64) winsize 62
4354 12:11:25.146517 [CA 5] Center 33 (3~64) winsize 62
4355 12:11:25.146590
4356 12:11:25.150057 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4357 12:11:25.150124
4358 12:11:25.153217 [CATrainingPosCal] consider 1 rank data
4359 12:11:25.156640 u2DelayCellTimex100 = 270/100 ps
4360 12:11:25.159694 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4361 12:11:25.166303 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4362 12:11:25.169973 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4363 12:11:25.172985 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4364 12:11:25.176643 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4365 12:11:25.179605 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 12:11:25.179701
4367 12:11:25.183230 CA PerBit enable=1, Macro0, CA PI delay=33
4368 12:11:25.183326
4369 12:11:25.186382 [CBTSetCACLKResult] CA Dly = 33
4370 12:11:25.189866 CS Dly: 4 (0~35)
4371 12:11:25.189937 ==
4372 12:11:25.192953 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 12:11:25.196461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 12:11:25.196535 ==
4375 12:11:25.203182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 12:11:25.206180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 12:11:25.210159 [CA 0] Center 35 (5~66) winsize 62
4378 12:11:25.213791 [CA 1] Center 35 (5~66) winsize 62
4379 12:11:25.216627 [CA 2] Center 34 (4~65) winsize 62
4380 12:11:25.220240 [CA 3] Center 34 (4~65) winsize 62
4381 12:11:25.223438 [CA 4] Center 34 (4~64) winsize 61
4382 12:11:25.226548 [CA 5] Center 33 (3~64) winsize 62
4383 12:11:25.226650
4384 12:11:25.230091 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 12:11:25.230197
4386 12:11:25.233194 [CATrainingPosCal] consider 2 rank data
4387 12:11:25.236672 u2DelayCellTimex100 = 270/100 ps
4388 12:11:25.239864 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 12:11:25.246645 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4390 12:11:25.249610 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 12:11:25.253136 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4392 12:11:25.256338 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4393 12:11:25.259758 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4394 12:11:25.259860
4395 12:11:25.262785 CA PerBit enable=1, Macro0, CA PI delay=33
4396 12:11:25.262888
4397 12:11:25.266509 [CBTSetCACLKResult] CA Dly = 33
4398 12:11:25.269623 CS Dly: 4 (0~36)
4399 12:11:25.269726
4400 12:11:25.272994 ----->DramcWriteLeveling(PI) begin...
4401 12:11:25.273095 ==
4402 12:11:25.276308 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 12:11:25.279647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 12:11:25.279753 ==
4405 12:11:25.282764 Write leveling (Byte 0): 30 => 30
4406 12:11:25.285968 Write leveling (Byte 1): 30 => 30
4407 12:11:25.289563 DramcWriteLeveling(PI) end<-----
4408 12:11:25.289663
4409 12:11:25.289755 ==
4410 12:11:25.292599 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 12:11:25.296147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 12:11:25.296253 ==
4413 12:11:25.299203 [Gating] SW mode calibration
4414 12:11:25.305950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 12:11:25.312866 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 12:11:25.316046 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 12:11:25.319513 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 12:11:25.326243 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4419 12:11:25.329342 0 9 12 | B1->B0 | 2626 2929 | 0 1 | (1 0) (1 0)
4420 12:11:25.332431 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:11:25.339146 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 12:11:25.342311 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 12:11:25.345849 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 12:11:25.352384 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 12:11:25.355954 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 12:11:25.359094 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4427 12:11:25.365653 0 10 12 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
4428 12:11:25.368788 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:11:25.371908 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:11:25.378886 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 12:11:25.381844 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 12:11:25.385135 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 12:11:25.391761 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 12:11:25.395478 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 12:11:25.398649 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4436 12:11:25.404986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:11:25.408392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:11:25.411490 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:11:25.418516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:11:25.421466 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:11:25.425096 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:11:25.431273 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:11:25.434970 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:11:25.438061 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:11:25.444882 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:11:25.447992 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:11:25.451007 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:11:25.458145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:11:25.461249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:11:25.464686 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4451 12:11:25.471197 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4452 12:11:25.471284 Total UI for P1: 0, mck2ui 16
4453 12:11:25.477854 best dqsien dly found for B0: ( 0, 13, 8)
4454 12:11:25.480874 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 12:11:25.484249 Total UI for P1: 0, mck2ui 16
4456 12:11:25.487701 best dqsien dly found for B1: ( 0, 13, 12)
4457 12:11:25.491026 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4458 12:11:25.494566 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4459 12:11:25.494653
4460 12:11:25.497594 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4461 12:11:25.500623 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4462 12:11:25.504257 [Gating] SW calibration Done
4463 12:11:25.504370 ==
4464 12:11:25.507596 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 12:11:25.510696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 12:11:25.514384 ==
4467 12:11:25.514471 RX Vref Scan: 0
4468 12:11:25.514539
4469 12:11:25.517473 RX Vref 0 -> 0, step: 1
4470 12:11:25.517558
4471 12:11:25.520900 RX Delay -230 -> 252, step: 16
4472 12:11:25.524154 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4473 12:11:25.527277 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4474 12:11:25.530374 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 12:11:25.537223 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4476 12:11:25.540522 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4477 12:11:25.543888 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4478 12:11:25.547350 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 12:11:25.550421 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4480 12:11:25.557168 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4481 12:11:25.560220 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4482 12:11:25.563722 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4483 12:11:25.566631 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 12:11:25.573342 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4485 12:11:25.576935 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4486 12:11:25.580067 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4487 12:11:25.583165 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4488 12:11:25.586709 ==
4489 12:11:25.586819 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 12:11:25.593396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 12:11:25.593476 ==
4492 12:11:25.593543 DQS Delay:
4493 12:11:25.596360 DQS0 = 0, DQS1 = 0
4494 12:11:25.596456 DQM Delay:
4495 12:11:25.599790 DQM0 = 51, DQM1 = 41
4496 12:11:25.599875 DQ Delay:
4497 12:11:25.603268 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4498 12:11:25.606464 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4499 12:11:25.609527 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4500 12:11:25.613177 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4501 12:11:25.613261
4502 12:11:25.613329
4503 12:11:25.613391 ==
4504 12:11:25.616216 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 12:11:25.619910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 12:11:25.619993 ==
4507 12:11:25.620077
4508 12:11:25.620152
4509 12:11:25.622950 TX Vref Scan disable
4510 12:11:25.626196 == TX Byte 0 ==
4511 12:11:25.629674 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 12:11:25.632630 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 12:11:25.636359 == TX Byte 1 ==
4514 12:11:25.639478 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 12:11:25.643052 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 12:11:25.643137 ==
4517 12:11:25.646207 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 12:11:25.652657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 12:11:25.652742 ==
4520 12:11:25.652831
4521 12:11:25.652925
4522 12:11:25.653026 TX Vref Scan disable
4523 12:11:25.656698 == TX Byte 0 ==
4524 12:11:25.660479 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 12:11:25.663673 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 12:11:25.667218 == TX Byte 1 ==
4527 12:11:25.670243 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4528 12:11:25.676505 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4529 12:11:25.676588
4530 12:11:25.676654 [DATLAT]
4531 12:11:25.676733 Freq=600, CH1 RK0
4532 12:11:25.676814
4533 12:11:25.679994 DATLAT Default: 0x9
4534 12:11:25.683199 0, 0xFFFF, sum = 0
4535 12:11:25.683283 1, 0xFFFF, sum = 0
4536 12:11:25.686759 2, 0xFFFF, sum = 0
4537 12:11:25.686842 3, 0xFFFF, sum = 0
4538 12:11:25.689819 4, 0xFFFF, sum = 0
4539 12:11:25.689903 5, 0xFFFF, sum = 0
4540 12:11:25.693306 6, 0xFFFF, sum = 0
4541 12:11:25.693389 7, 0xFFFF, sum = 0
4542 12:11:25.696635 8, 0x0, sum = 1
4543 12:11:25.696721 9, 0x0, sum = 2
4544 12:11:25.696799 10, 0x0, sum = 3
4545 12:11:25.700066 11, 0x0, sum = 4
4546 12:11:25.700155 best_step = 9
4547 12:11:25.700243
4548 12:11:25.702958 ==
4549 12:11:25.703041 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 12:11:25.709842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 12:11:25.709925 ==
4552 12:11:25.709991 RX Vref Scan: 1
4553 12:11:25.710052
4554 12:11:25.712869 RX Vref 0 -> 0, step: 1
4555 12:11:25.712981
4556 12:11:25.716113 RX Delay -179 -> 252, step: 8
4557 12:11:25.716191
4558 12:11:25.719758 Set Vref, RX VrefLevel [Byte0]: 53
4559 12:11:25.723263 [Byte1]: 55
4560 12:11:25.723346
4561 12:11:25.726298 Final RX Vref Byte 0 = 53 to rank0
4562 12:11:25.729354 Final RX Vref Byte 1 = 55 to rank0
4563 12:11:25.732608 Final RX Vref Byte 0 = 53 to rank1
4564 12:11:25.736003 Final RX Vref Byte 1 = 55 to rank1==
4565 12:11:25.739260 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 12:11:25.742884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 12:11:25.745956 ==
4568 12:11:25.746041 DQS Delay:
4569 12:11:25.746109 DQS0 = 0, DQS1 = 0
4570 12:11:25.749447 DQM Delay:
4571 12:11:25.749558 DQM0 = 49, DQM1 = 42
4572 12:11:25.752477 DQ Delay:
4573 12:11:25.752588 DQ0 =52, DQ1 =48, DQ2 =36, DQ3 =44
4574 12:11:25.755915 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4575 12:11:25.758940 DQ8 =28, DQ9 =32, DQ10 =48, DQ11 =32
4576 12:11:25.762593 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4577 12:11:25.765658
4578 12:11:25.765741
4579 12:11:25.772290 [DQSOSCAuto] RK0, (LSB)MR18= 0x5178, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
4580 12:11:25.775306 CH1 RK0: MR19=808, MR18=5178
4581 12:11:25.781969 CH1_RK0: MR19=0x808, MR18=0x5178, DQSOSC=387, MR23=63, INC=175, DEC=116
4582 12:11:25.782054
4583 12:11:25.785571 ----->DramcWriteLeveling(PI) begin...
4584 12:11:25.785658 ==
4585 12:11:25.788735 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 12:11:25.791802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 12:11:25.791879 ==
4588 12:11:25.795366 Write leveling (Byte 0): 27 => 27
4589 12:11:25.798464 Write leveling (Byte 1): 31 => 31
4590 12:11:25.801915 DramcWriteLeveling(PI) end<-----
4591 12:11:25.802000
4592 12:11:25.802068 ==
4593 12:11:25.805407 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 12:11:25.808478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 12:11:25.808564 ==
4596 12:11:25.811964 [Gating] SW mode calibration
4597 12:11:25.818231 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 12:11:25.824929 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 12:11:25.828498 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 12:11:25.834901 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 12:11:25.838368 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4602 12:11:25.841521 0 9 12 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (1 0)
4603 12:11:25.848246 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 12:11:25.851407 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 12:11:25.854972 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 12:11:25.861508 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 12:11:25.864660 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 12:11:25.867774 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 12:11:25.874417 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 12:11:25.878011 0 10 12 | B1->B0 | 4343 3333 | 0 0 | (0 0) (0 0)
4611 12:11:25.881057 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4612 12:11:25.887484 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 12:11:25.891115 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 12:11:25.894343 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 12:11:25.900683 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 12:11:25.904339 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 12:11:25.907501 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4618 12:11:25.914388 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4619 12:11:25.917734 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:11:25.921001 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:11:25.927331 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:11:25.930900 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:11:25.934195 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:11:25.940645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:11:25.944235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:11:25.947384 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:11:25.950543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:11:25.957271 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:11:25.960414 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:11:25.963882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:11:25.970505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:11:25.974150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:11:25.977214 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4634 12:11:25.983645 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 12:11:25.987234 Total UI for P1: 0, mck2ui 16
4636 12:11:25.990213 best dqsien dly found for B0: ( 0, 13, 8)
4637 12:11:25.993801 Total UI for P1: 0, mck2ui 16
4638 12:11:25.996669 best dqsien dly found for B1: ( 0, 13, 8)
4639 12:11:26.000405 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4640 12:11:26.003407 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4641 12:11:26.003510
4642 12:11:26.007001 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4643 12:11:26.010231 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4644 12:11:26.013788 [Gating] SW calibration Done
4645 12:11:26.013878 ==
4646 12:11:26.016681 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 12:11:26.020268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 12:11:26.020374 ==
4649 12:11:26.023405 RX Vref Scan: 0
4650 12:11:26.023508
4651 12:11:26.023602 RX Vref 0 -> 0, step: 1
4652 12:11:26.023696
4653 12:11:26.026491 RX Delay -230 -> 252, step: 16
4654 12:11:26.033606 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4655 12:11:26.036977 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4656 12:11:26.039862 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4657 12:11:26.043331 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4658 12:11:26.046385 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4659 12:11:26.053001 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4660 12:11:26.056527 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4661 12:11:26.059717 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4662 12:11:26.063264 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4663 12:11:26.069802 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4664 12:11:26.072929 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4665 12:11:26.076535 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4666 12:11:26.079600 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4667 12:11:26.086171 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4668 12:11:26.089740 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4669 12:11:26.092882 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4670 12:11:26.092965 ==
4671 12:11:26.096343 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 12:11:26.099619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 12:11:26.099703 ==
4674 12:11:26.102795 DQS Delay:
4675 12:11:26.102878 DQS0 = 0, DQS1 = 0
4676 12:11:26.106334 DQM Delay:
4677 12:11:26.106417 DQM0 = 52, DQM1 = 45
4678 12:11:26.106484 DQ Delay:
4679 12:11:26.109491 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4680 12:11:26.112990 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4681 12:11:26.116061 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4682 12:11:26.119676 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =65
4683 12:11:26.119760
4684 12:11:26.119826
4685 12:11:26.122546 ==
4686 12:11:26.122629 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 12:11:26.129183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 12:11:26.129266 ==
4689 12:11:26.129334
4690 12:11:26.129395
4691 12:11:26.132665 TX Vref Scan disable
4692 12:11:26.132748 == TX Byte 0 ==
4693 12:11:26.139068 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4694 12:11:26.142424 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4695 12:11:26.142508 == TX Byte 1 ==
4696 12:11:26.149037 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4697 12:11:26.152452 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4698 12:11:26.152535 ==
4699 12:11:26.155782 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 12:11:26.158899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 12:11:26.158982 ==
4702 12:11:26.159049
4703 12:11:26.159110
4704 12:11:26.162547 TX Vref Scan disable
4705 12:11:26.165609 == TX Byte 0 ==
4706 12:11:26.169152 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4707 12:11:26.172243 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4708 12:11:26.175555 == TX Byte 1 ==
4709 12:11:26.179064 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4710 12:11:26.182140 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4711 12:11:26.182223
4712 12:11:26.185753 [DATLAT]
4713 12:11:26.185837 Freq=600, CH1 RK1
4714 12:11:26.185903
4715 12:11:26.188827 DATLAT Default: 0x9
4716 12:11:26.188910 0, 0xFFFF, sum = 0
4717 12:11:26.192422 1, 0xFFFF, sum = 0
4718 12:11:26.192506 2, 0xFFFF, sum = 0
4719 12:11:26.195456 3, 0xFFFF, sum = 0
4720 12:11:26.195568 4, 0xFFFF, sum = 0
4721 12:11:26.198979 5, 0xFFFF, sum = 0
4722 12:11:26.199080 6, 0xFFFF, sum = 0
4723 12:11:26.201904 7, 0xFFFF, sum = 0
4724 12:11:26.201988 8, 0x0, sum = 1
4725 12:11:26.205515 9, 0x0, sum = 2
4726 12:11:26.205599 10, 0x0, sum = 3
4727 12:11:26.208617 11, 0x0, sum = 4
4728 12:11:26.208728 best_step = 9
4729 12:11:26.208849
4730 12:11:26.208918 ==
4731 12:11:26.211787 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 12:11:26.218539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 12:11:26.218623 ==
4734 12:11:26.218689 RX Vref Scan: 0
4735 12:11:26.218754
4736 12:11:26.221628 RX Vref 0 -> 0, step: 1
4737 12:11:26.221711
4738 12:11:26.225143 RX Delay -179 -> 252, step: 8
4739 12:11:26.228609 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4740 12:11:26.235187 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4741 12:11:26.238446 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4742 12:11:26.241752 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4743 12:11:26.244779 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4744 12:11:26.248362 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4745 12:11:26.254805 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4746 12:11:26.258140 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4747 12:11:26.261685 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4748 12:11:26.264783 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4749 12:11:26.267890 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4750 12:11:26.274870 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4751 12:11:26.277907 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4752 12:11:26.281545 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4753 12:11:26.284541 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4754 12:11:26.291457 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4755 12:11:26.291544 ==
4756 12:11:26.294464 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 12:11:26.298061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 12:11:26.298176 ==
4759 12:11:26.298273 DQS Delay:
4760 12:11:26.301198 DQS0 = 0, DQS1 = 0
4761 12:11:26.301331 DQM Delay:
4762 12:11:26.304675 DQM0 = 50, DQM1 = 44
4763 12:11:26.304784 DQ Delay:
4764 12:11:26.307742 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =48
4765 12:11:26.310900 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4766 12:11:26.314435 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =40
4767 12:11:26.317546 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4768 12:11:26.317621
4769 12:11:26.317686
4770 12:11:26.324209 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4771 12:11:26.327645 CH1 RK1: MR19=808, MR18=5B20
4772 12:11:26.334183 CH1_RK1: MR19=0x808, MR18=0x5B20, DQSOSC=392, MR23=63, INC=170, DEC=113
4773 12:11:26.337302 [RxdqsGatingPostProcess] freq 600
4774 12:11:26.344381 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4775 12:11:26.347831 Pre-setting of DQS Precalculation
4776 12:11:26.350790 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4777 12:11:26.357557 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4778 12:11:26.364236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4779 12:11:26.364323
4780 12:11:26.364392
4781 12:11:26.367512 [Calibration Summary] 1200 Mbps
4782 12:11:26.370750 CH 0, Rank 0
4783 12:11:26.370836 SW Impedance : PASS
4784 12:11:26.373940 DUTY Scan : NO K
4785 12:11:26.377480 ZQ Calibration : PASS
4786 12:11:26.377566 Jitter Meter : NO K
4787 12:11:26.380508 CBT Training : PASS
4788 12:11:26.384201 Write leveling : PASS
4789 12:11:26.384287 RX DQS gating : PASS
4790 12:11:26.387156 RX DQ/DQS(RDDQC) : PASS
4791 12:11:26.390869 TX DQ/DQS : PASS
4792 12:11:26.390954 RX DATLAT : PASS
4793 12:11:26.393939 RX DQ/DQS(Engine): PASS
4794 12:11:26.394024 TX OE : NO K
4795 12:11:26.397001 All Pass.
4796 12:11:26.397086
4797 12:11:26.397154 CH 0, Rank 1
4798 12:11:26.400504 SW Impedance : PASS
4799 12:11:26.400590 DUTY Scan : NO K
4800 12:11:26.403648 ZQ Calibration : PASS
4801 12:11:26.407191 Jitter Meter : NO K
4802 12:11:26.407277 CBT Training : PASS
4803 12:11:26.410199 Write leveling : PASS
4804 12:11:26.413722 RX DQS gating : PASS
4805 12:11:26.413865 RX DQ/DQS(RDDQC) : PASS
4806 12:11:26.416922 TX DQ/DQS : PASS
4807 12:11:26.420371 RX DATLAT : PASS
4808 12:11:26.420455 RX DQ/DQS(Engine): PASS
4809 12:11:26.423415 TX OE : NO K
4810 12:11:26.423501 All Pass.
4811 12:11:26.423570
4812 12:11:26.426995 CH 1, Rank 0
4813 12:11:26.427120 SW Impedance : PASS
4814 12:11:26.430068 DUTY Scan : NO K
4815 12:11:26.433630 ZQ Calibration : PASS
4816 12:11:26.433715 Jitter Meter : NO K
4817 12:11:26.436583 CBT Training : PASS
4818 12:11:26.440243 Write leveling : PASS
4819 12:11:26.440327 RX DQS gating : PASS
4820 12:11:26.443376 RX DQ/DQS(RDDQC) : PASS
4821 12:11:26.446505 TX DQ/DQS : PASS
4822 12:11:26.446591 RX DATLAT : PASS
4823 12:11:26.449987 RX DQ/DQS(Engine): PASS
4824 12:11:26.453277 TX OE : NO K
4825 12:11:26.453384 All Pass.
4826 12:11:26.453494
4827 12:11:26.453558 CH 1, Rank 1
4828 12:11:26.456605 SW Impedance : PASS
4829 12:11:26.459881 DUTY Scan : NO K
4830 12:11:26.460004 ZQ Calibration : PASS
4831 12:11:26.463493 Jitter Meter : NO K
4832 12:11:26.466401 CBT Training : PASS
4833 12:11:26.466486 Write leveling : PASS
4834 12:11:26.469899 RX DQS gating : PASS
4835 12:11:26.469997 RX DQ/DQS(RDDQC) : PASS
4836 12:11:26.473305 TX DQ/DQS : PASS
4837 12:11:26.476279 RX DATLAT : PASS
4838 12:11:26.476365 RX DQ/DQS(Engine): PASS
4839 12:11:26.479860 TX OE : NO K
4840 12:11:26.479974 All Pass.
4841 12:11:26.480071
4842 12:11:26.483249 DramC Write-DBI off
4843 12:11:26.486441 PER_BANK_REFRESH: Hybrid Mode
4844 12:11:26.486556 TX_TRACKING: ON
4845 12:11:26.496164 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4846 12:11:26.499779 [FAST_K] Save calibration result to emmc
4847 12:11:26.502795 dramc_set_vcore_voltage set vcore to 662500
4848 12:11:26.506415 Read voltage for 933, 3
4849 12:11:26.506513 Vio18 = 0
4850 12:11:26.506581 Vcore = 662500
4851 12:11:26.509507 Vdram = 0
4852 12:11:26.509590 Vddq = 0
4853 12:11:26.509658 Vmddr = 0
4854 12:11:26.516450 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4855 12:11:26.519459 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4856 12:11:26.523061 MEM_TYPE=3, freq_sel=17
4857 12:11:26.526216 sv_algorithm_assistance_LP4_1600
4858 12:11:26.529347 ============ PULL DRAM RESETB DOWN ============
4859 12:11:26.532931 ========== PULL DRAM RESETB DOWN end =========
4860 12:11:26.539369 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 12:11:26.542860 ===================================
4862 12:11:26.545887 LPDDR4 DRAM CONFIGURATION
4863 12:11:26.549556 ===================================
4864 12:11:26.549643 EX_ROW_EN[0] = 0x0
4865 12:11:26.552512 EX_ROW_EN[1] = 0x0
4866 12:11:26.552613 LP4Y_EN = 0x0
4867 12:11:26.556002 WORK_FSP = 0x0
4868 12:11:26.556079 WL = 0x3
4869 12:11:26.559506 RL = 0x3
4870 12:11:26.559613 BL = 0x2
4871 12:11:26.562666 RPST = 0x0
4872 12:11:26.562740 RD_PRE = 0x0
4873 12:11:26.566101 WR_PRE = 0x1
4874 12:11:26.566186 WR_PST = 0x0
4875 12:11:26.569280 DBI_WR = 0x0
4876 12:11:26.572370 DBI_RD = 0x0
4877 12:11:26.572455 OTF = 0x1
4878 12:11:26.575772 ===================================
4879 12:11:26.579147 ===================================
4880 12:11:26.579233 ANA top config
4881 12:11:26.582789 ===================================
4882 12:11:26.585832 DLL_ASYNC_EN = 0
4883 12:11:26.589202 ALL_SLAVE_EN = 1
4884 12:11:26.592425 NEW_RANK_MODE = 1
4885 12:11:26.595525 DLL_IDLE_MODE = 1
4886 12:11:26.595610 LP45_APHY_COMB_EN = 1
4887 12:11:26.599079 TX_ODT_DIS = 1
4888 12:11:26.602247 NEW_8X_MODE = 1
4889 12:11:26.605734 ===================================
4890 12:11:26.608853 ===================================
4891 12:11:26.612499 data_rate = 1866
4892 12:11:26.615581 CKR = 1
4893 12:11:26.615695 DQ_P2S_RATIO = 8
4894 12:11:26.618801 ===================================
4895 12:11:26.622417 CA_P2S_RATIO = 8
4896 12:11:26.625561 DQ_CA_OPEN = 0
4897 12:11:26.629142 DQ_SEMI_OPEN = 0
4898 12:11:26.632246 CA_SEMI_OPEN = 0
4899 12:11:26.635781 CA_FULL_RATE = 0
4900 12:11:26.635871 DQ_CKDIV4_EN = 1
4901 12:11:26.638733 CA_CKDIV4_EN = 1
4902 12:11:26.642265 CA_PREDIV_EN = 0
4903 12:11:26.645256 PH8_DLY = 0
4904 12:11:26.648430 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4905 12:11:26.651943 DQ_AAMCK_DIV = 4
4906 12:11:26.652055 CA_AAMCK_DIV = 4
4907 12:11:26.655033 CA_ADMCK_DIV = 4
4908 12:11:26.658612 DQ_TRACK_CA_EN = 0
4909 12:11:26.661655 CA_PICK = 933
4910 12:11:26.665177 CA_MCKIO = 933
4911 12:11:26.668643 MCKIO_SEMI = 0
4912 12:11:26.671913 PLL_FREQ = 3732
4913 12:11:26.672026 DQ_UI_PI_RATIO = 32
4914 12:11:26.675103 CA_UI_PI_RATIO = 0
4915 12:11:26.678766 ===================================
4916 12:11:26.681618 ===================================
4917 12:11:26.685021 memory_type:LPDDR4
4918 12:11:26.688018 GP_NUM : 10
4919 12:11:26.688132 SRAM_EN : 1
4920 12:11:26.691493 MD32_EN : 0
4921 12:11:26.694757 ===================================
4922 12:11:26.698475 [ANA_INIT] >>>>>>>>>>>>>>
4923 12:11:26.701714 <<<<<< [CONFIGURE PHASE]: ANA_TX
4924 12:11:26.704668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4925 12:11:26.708354 ===================================
4926 12:11:26.708442 data_rate = 1866,PCW = 0X8f00
4927 12:11:26.711210 ===================================
4928 12:11:26.714779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4929 12:11:26.721492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 12:11:26.727662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 12:11:26.731138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4932 12:11:26.734382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4933 12:11:26.737860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4934 12:11:26.741070 [ANA_INIT] flow start
4935 12:11:26.744267 [ANA_INIT] PLL >>>>>>>>
4936 12:11:26.744371 [ANA_INIT] PLL <<<<<<<<
4937 12:11:26.747641 [ANA_INIT] MIDPI >>>>>>>>
4938 12:11:26.751061 [ANA_INIT] MIDPI <<<<<<<<
4939 12:11:26.751168 [ANA_INIT] DLL >>>>>>>>
4940 12:11:26.754171 [ANA_INIT] flow end
4941 12:11:26.757809 ============ LP4 DIFF to SE enter ============
4942 12:11:26.760827 ============ LP4 DIFF to SE exit ============
4943 12:11:26.763914 [ANA_INIT] <<<<<<<<<<<<<
4944 12:11:26.767493 [Flow] Enable top DCM control >>>>>
4945 12:11:26.770392 [Flow] Enable top DCM control <<<<<
4946 12:11:26.773977 Enable DLL master slave shuffle
4947 12:11:26.780695 ==============================================================
4948 12:11:26.780804 Gating Mode config
4949 12:11:26.787426 ==============================================================
4950 12:11:26.790274 Config description:
4951 12:11:26.797053 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4952 12:11:26.803700 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4953 12:11:26.810503 SELPH_MODE 0: By rank 1: By Phase
4954 12:11:26.813688 ==============================================================
4955 12:11:26.817093 GAT_TRACK_EN = 1
4956 12:11:26.820626 RX_GATING_MODE = 2
4957 12:11:26.823658 RX_GATING_TRACK_MODE = 2
4958 12:11:26.827195 SELPH_MODE = 1
4959 12:11:26.830751 PICG_EARLY_EN = 1
4960 12:11:26.833830 VALID_LAT_VALUE = 1
4961 12:11:26.840533 ==============================================================
4962 12:11:26.843555 Enter into Gating configuration >>>>
4963 12:11:26.846696 Exit from Gating configuration <<<<
4964 12:11:26.850104 Enter into DVFS_PRE_config >>>>>
4965 12:11:26.859964 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4966 12:11:26.863592 Exit from DVFS_PRE_config <<<<<
4967 12:11:26.866744 Enter into PICG configuration >>>>
4968 12:11:26.870295 Exit from PICG configuration <<<<
4969 12:11:26.873356 [RX_INPUT] configuration >>>>>
4970 12:11:26.873463 [RX_INPUT] configuration <<<<<
4971 12:11:26.879892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4972 12:11:26.886755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4973 12:11:26.889859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 12:11:26.896713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 12:11:26.903110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 12:11:26.909653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 12:11:26.913170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4978 12:11:26.916363 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4979 12:11:26.922831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4980 12:11:26.926025 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4981 12:11:26.929585 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4982 12:11:26.936146 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4983 12:11:26.939889 ===================================
4984 12:11:26.939990 LPDDR4 DRAM CONFIGURATION
4985 12:11:26.942992 ===================================
4986 12:11:26.946164 EX_ROW_EN[0] = 0x0
4987 12:11:26.949412 EX_ROW_EN[1] = 0x0
4988 12:11:26.949515 LP4Y_EN = 0x0
4989 12:11:26.952752 WORK_FSP = 0x0
4990 12:11:26.952891 WL = 0x3
4991 12:11:26.956252 RL = 0x3
4992 12:11:26.956353 BL = 0x2
4993 12:11:26.959154 RPST = 0x0
4994 12:11:26.959258 RD_PRE = 0x0
4995 12:11:26.962608 WR_PRE = 0x1
4996 12:11:26.962707 WR_PST = 0x0
4997 12:11:26.966116 DBI_WR = 0x0
4998 12:11:26.966220 DBI_RD = 0x0
4999 12:11:26.969169 OTF = 0x1
5000 12:11:26.972383 ===================================
5001 12:11:26.975843 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5002 12:11:26.979226 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5003 12:11:26.985531 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5004 12:11:26.989126 ===================================
5005 12:11:26.989229 LPDDR4 DRAM CONFIGURATION
5006 12:11:26.992384 ===================================
5007 12:11:26.995534 EX_ROW_EN[0] = 0x10
5008 12:11:26.999187 EX_ROW_EN[1] = 0x0
5009 12:11:26.999291 LP4Y_EN = 0x0
5010 12:11:27.002615 WORK_FSP = 0x0
5011 12:11:27.002716 WL = 0x3
5012 12:11:27.005637 RL = 0x3
5013 12:11:27.005741 BL = 0x2
5014 12:11:27.009064 RPST = 0x0
5015 12:11:27.009167 RD_PRE = 0x0
5016 12:11:27.012320 WR_PRE = 0x1
5017 12:11:27.012425 WR_PST = 0x0
5018 12:11:27.015747 DBI_WR = 0x0
5019 12:11:27.015853 DBI_RD = 0x0
5020 12:11:27.019185 OTF = 0x1
5021 12:11:27.022303 ===================================
5022 12:11:27.028968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5023 12:11:27.032010 nWR fixed to 30
5024 12:11:27.032115 [ModeRegInit_LP4] CH0 RK0
5025 12:11:27.035443 [ModeRegInit_LP4] CH0 RK1
5026 12:11:27.038645 [ModeRegInit_LP4] CH1 RK0
5027 12:11:27.042293 [ModeRegInit_LP4] CH1 RK1
5028 12:11:27.042395 match AC timing 9
5029 12:11:27.045341 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5030 12:11:27.052177 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5031 12:11:27.055251 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5032 12:11:27.061773 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5033 12:11:27.065101 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5034 12:11:27.065185 ==
5035 12:11:27.068196 Dram Type= 6, Freq= 0, CH_0, rank 0
5036 12:11:27.071426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5037 12:11:27.071504 ==
5038 12:11:27.078229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5039 12:11:27.084664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5040 12:11:27.088193 [CA 0] Center 38 (7~69) winsize 63
5041 12:11:27.091495 [CA 1] Center 38 (8~69) winsize 62
5042 12:11:27.094548 [CA 2] Center 35 (5~66) winsize 62
5043 12:11:27.097718 [CA 3] Center 35 (4~66) winsize 63
5044 12:11:27.101394 [CA 4] Center 34 (4~65) winsize 62
5045 12:11:27.104413 [CA 5] Center 33 (3~64) winsize 62
5046 12:11:27.104525
5047 12:11:27.107946 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5048 12:11:27.108046
5049 12:11:27.110985 [CATrainingPosCal] consider 1 rank data
5050 12:11:27.114554 u2DelayCellTimex100 = 270/100 ps
5051 12:11:27.117483 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5052 12:11:27.120753 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5053 12:11:27.124239 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5054 12:11:27.127410 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5055 12:11:27.131005 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5056 12:11:27.137092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5057 12:11:27.137203
5058 12:11:27.140557 CA PerBit enable=1, Macro0, CA PI delay=33
5059 12:11:27.140658
5060 12:11:27.144176 [CBTSetCACLKResult] CA Dly = 33
5061 12:11:27.144280 CS Dly: 7 (0~38)
5062 12:11:27.144376 ==
5063 12:11:27.147158 Dram Type= 6, Freq= 0, CH_0, rank 1
5064 12:11:27.150352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 12:11:27.154021 ==
5066 12:11:27.157110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 12:11:27.163816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5068 12:11:27.167100 [CA 0] Center 38 (8~69) winsize 62
5069 12:11:27.170590 [CA 1] Center 38 (8~69) winsize 62
5070 12:11:27.173606 [CA 2] Center 36 (6~66) winsize 61
5071 12:11:27.177342 [CA 3] Center 35 (5~66) winsize 62
5072 12:11:27.180215 [CA 4] Center 34 (4~65) winsize 62
5073 12:11:27.183472 [CA 5] Center 34 (4~64) winsize 61
5074 12:11:27.183576
5075 12:11:27.186915 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5076 12:11:27.187019
5077 12:11:27.189976 [CATrainingPosCal] consider 2 rank data
5078 12:11:27.193604 u2DelayCellTimex100 = 270/100 ps
5079 12:11:27.196858 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 12:11:27.200051 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5081 12:11:27.206642 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5082 12:11:27.210143 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5083 12:11:27.213084 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5084 12:11:27.216743 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 12:11:27.216862
5086 12:11:27.219929 CA PerBit enable=1, Macro0, CA PI delay=34
5087 12:11:27.220032
5088 12:11:27.223076 [CBTSetCACLKResult] CA Dly = 34
5089 12:11:27.223183 CS Dly: 7 (0~39)
5090 12:11:27.223281
5091 12:11:27.226611 ----->DramcWriteLeveling(PI) begin...
5092 12:11:27.229975 ==
5093 12:11:27.233240 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 12:11:27.236267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 12:11:27.236376 ==
5096 12:11:27.239774 Write leveling (Byte 0): 30 => 30
5097 12:11:27.242834 Write leveling (Byte 1): 29 => 29
5098 12:11:27.246433 DramcWriteLeveling(PI) end<-----
5099 12:11:27.246540
5100 12:11:27.246640 ==
5101 12:11:27.249568 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 12:11:27.253115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 12:11:27.253220 ==
5104 12:11:27.256152 [Gating] SW mode calibration
5105 12:11:27.262847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5106 12:11:27.269460 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5107 12:11:27.272801 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5108 12:11:27.276257 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 12:11:27.282908 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 12:11:27.286017 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 12:11:27.289063 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 12:11:27.295617 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 12:11:27.299186 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
5114 12:11:27.302332 0 14 28 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
5115 12:11:27.308941 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5116 12:11:27.312120 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:11:27.315608 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 12:11:27.322494 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 12:11:27.325617 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 12:11:27.329153 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 12:11:27.335576 0 15 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
5122 12:11:27.338931 0 15 28 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
5123 12:11:27.342295 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5124 12:11:27.348839 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:11:27.352304 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 12:11:27.355613 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 12:11:27.358698 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 12:11:27.365866 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 12:11:27.368870 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 12:11:27.372448 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 12:11:27.378773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:11:27.382109 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:11:27.385142 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:11:27.391968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:11:27.395442 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:11:27.398451 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:11:27.405159 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:11:27.408384 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:11:27.411545 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:11:27.418342 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:11:27.421940 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:11:27.424989 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:11:27.431663 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:11:27.434670 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:11:27.438252 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5146 12:11:27.444715 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 12:11:27.448145 Total UI for P1: 0, mck2ui 16
5148 12:11:27.451314 best dqsien dly found for B0: ( 1, 2, 24)
5149 12:11:27.454699 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5150 12:11:27.457985 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 12:11:27.461028 Total UI for P1: 0, mck2ui 16
5152 12:11:27.464646 best dqsien dly found for B1: ( 1, 2, 30)
5153 12:11:27.467654 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5154 12:11:27.471195 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5155 12:11:27.474349
5156 12:11:27.478025 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5157 12:11:27.481048 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5158 12:11:27.484692 [Gating] SW calibration Done
5159 12:11:27.484848 ==
5160 12:11:27.487844 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 12:11:27.490904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 12:11:27.491005 ==
5163 12:11:27.491102 RX Vref Scan: 0
5164 12:11:27.494587
5165 12:11:27.494685 RX Vref 0 -> 0, step: 1
5166 12:11:27.494781
5167 12:11:27.497616 RX Delay -80 -> 252, step: 8
5168 12:11:27.501111 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5169 12:11:27.504172 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5170 12:11:27.510914 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5171 12:11:27.514057 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5172 12:11:27.517607 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5173 12:11:27.520665 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5174 12:11:27.524170 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5175 12:11:27.530386 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5176 12:11:27.533968 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5177 12:11:27.537279 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5178 12:11:27.540460 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5179 12:11:27.543614 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5180 12:11:27.547030 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5181 12:11:27.553661 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5182 12:11:27.557135 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5183 12:11:27.560163 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5184 12:11:27.560265 ==
5185 12:11:27.563576 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 12:11:27.566755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 12:11:27.566856 ==
5188 12:11:27.570355 DQS Delay:
5189 12:11:27.570459 DQS0 = 0, DQS1 = 0
5190 12:11:27.570555 DQM Delay:
5191 12:11:27.573349 DQM0 = 105, DQM1 = 90
5192 12:11:27.573452 DQ Delay:
5193 12:11:27.576967 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5194 12:11:27.580129 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5195 12:11:27.583184 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5196 12:11:27.586632 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5197 12:11:27.586741
5198 12:11:27.590127
5199 12:11:27.590231 ==
5200 12:11:27.593192 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 12:11:27.596740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 12:11:27.596855 ==
5203 12:11:27.596961
5204 12:11:27.597055
5205 12:11:27.599828 TX Vref Scan disable
5206 12:11:27.599928 == TX Byte 0 ==
5207 12:11:27.606351 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5208 12:11:27.609965 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5209 12:11:27.610073 == TX Byte 1 ==
5210 12:11:27.616683 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5211 12:11:27.619720 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5212 12:11:27.619802 ==
5213 12:11:27.623376 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 12:11:27.626416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 12:11:27.626533 ==
5216 12:11:27.626632
5217 12:11:27.626734
5218 12:11:27.629895 TX Vref Scan disable
5219 12:11:27.632927 == TX Byte 0 ==
5220 12:11:27.636084 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5221 12:11:27.639579 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5222 12:11:27.643150 == TX Byte 1 ==
5223 12:11:27.646143 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5224 12:11:27.649715 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5225 12:11:27.649828
5226 12:11:27.652747 [DATLAT]
5227 12:11:27.652863 Freq=933, CH0 RK0
5228 12:11:27.652963
5229 12:11:27.656206 DATLAT Default: 0xd
5230 12:11:27.656315 0, 0xFFFF, sum = 0
5231 12:11:27.659688 1, 0xFFFF, sum = 0
5232 12:11:27.659792 2, 0xFFFF, sum = 0
5233 12:11:27.662893 3, 0xFFFF, sum = 0
5234 12:11:27.663001 4, 0xFFFF, sum = 0
5235 12:11:27.665972 5, 0xFFFF, sum = 0
5236 12:11:27.666091 6, 0xFFFF, sum = 0
5237 12:11:27.669346 7, 0xFFFF, sum = 0
5238 12:11:27.669461 8, 0xFFFF, sum = 0
5239 12:11:27.672586 9, 0xFFFF, sum = 0
5240 12:11:27.672706 10, 0x0, sum = 1
5241 12:11:27.675836 11, 0x0, sum = 2
5242 12:11:27.675945 12, 0x0, sum = 3
5243 12:11:27.679273 13, 0x0, sum = 4
5244 12:11:27.679385 best_step = 11
5245 12:11:27.679485
5246 12:11:27.679583 ==
5247 12:11:27.682787 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 12:11:27.688983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 12:11:27.689095 ==
5250 12:11:27.689192 RX Vref Scan: 1
5251 12:11:27.689291
5252 12:11:27.692591 RX Vref 0 -> 0, step: 1
5253 12:11:27.692700
5254 12:11:27.695513 RX Delay -53 -> 252, step: 4
5255 12:11:27.695623
5256 12:11:27.699107 Set Vref, RX VrefLevel [Byte0]: 58
5257 12:11:27.702197 [Byte1]: 50
5258 12:11:27.702319
5259 12:11:27.705681 Final RX Vref Byte 0 = 58 to rank0
5260 12:11:27.708747 Final RX Vref Byte 1 = 50 to rank0
5261 12:11:27.712456 Final RX Vref Byte 0 = 58 to rank1
5262 12:11:27.715615 Final RX Vref Byte 1 = 50 to rank1==
5263 12:11:27.718605 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 12:11:27.722182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 12:11:27.722290 ==
5266 12:11:27.725347 DQS Delay:
5267 12:11:27.725448 DQS0 = 0, DQS1 = 0
5268 12:11:27.728948 DQM Delay:
5269 12:11:27.729055 DQM0 = 107, DQM1 = 91
5270 12:11:27.729150 DQ Delay:
5271 12:11:27.731992 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =104
5272 12:11:27.735598 DQ4 =108, DQ5 =98, DQ6 =120, DQ7 =116
5273 12:11:27.738826 DQ8 =88, DQ9 =76, DQ10 =90, DQ11 =90
5274 12:11:27.745456 DQ12 =94, DQ13 =92, DQ14 =102, DQ15 =100
5275 12:11:27.745561
5276 12:11:27.745659
5277 12:11:27.752110 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5278 12:11:27.755600 CH0 RK0: MR19=505, MR18=2723
5279 12:11:27.762133 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5280 12:11:27.762236
5281 12:11:27.765137 ----->DramcWriteLeveling(PI) begin...
5282 12:11:27.765216 ==
5283 12:11:27.768340 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 12:11:27.771981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:11:27.772084 ==
5286 12:11:27.774990 Write leveling (Byte 0): 35 => 35
5287 12:11:27.778530 Write leveling (Byte 1): 28 => 28
5288 12:11:27.781711 DramcWriteLeveling(PI) end<-----
5289 12:11:27.781797
5290 12:11:27.781869 ==
5291 12:11:27.784960 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 12:11:27.788459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 12:11:27.788533 ==
5294 12:11:27.791949 [Gating] SW mode calibration
5295 12:11:27.798491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 12:11:27.805064 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 12:11:27.808171 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 12:11:27.814670 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 12:11:27.817753 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 12:11:27.821574 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 12:11:27.827649 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 12:11:27.831332 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 12:11:27.834392 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
5304 12:11:27.840971 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
5305 12:11:27.844581 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 12:11:27.847545 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 12:11:27.854202 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 12:11:27.857868 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 12:11:27.860924 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 12:11:27.867534 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 12:11:27.870635 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5312 12:11:27.874202 0 15 28 | B1->B0 | 3939 4141 | 0 0 | (0 0) (1 1)
5313 12:11:27.880630 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 12:11:27.884115 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 12:11:27.887210 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 12:11:27.893981 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 12:11:27.897235 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 12:11:27.900788 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 12:11:27.906848 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5320 12:11:27.910517 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5321 12:11:27.913579 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:11:27.920589 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:11:27.923768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:11:27.926927 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:11:27.933737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:11:27.937233 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:11:27.940245 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:11:27.947042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:11:27.950143 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:11:27.953601 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:11:27.959739 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:11:27.963209 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:11:27.966372 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:11:27.973563 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:11:27.976755 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:11:27.979824 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 12:11:27.986379 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 12:11:27.986465 Total UI for P1: 0, mck2ui 16
5339 12:11:27.993225 best dqsien dly found for B0: ( 1, 2, 28)
5340 12:11:27.993310 Total UI for P1: 0, mck2ui 16
5341 12:11:27.996422 best dqsien dly found for B1: ( 1, 2, 28)
5342 12:11:28.002838 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5343 12:11:28.006099 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5344 12:11:28.006189
5345 12:11:28.009644 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 12:11:28.012754 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5347 12:11:28.016376 [Gating] SW calibration Done
5348 12:11:28.016461 ==
5349 12:11:28.019461 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 12:11:28.022640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 12:11:28.022726 ==
5352 12:11:28.026230 RX Vref Scan: 0
5353 12:11:28.026314
5354 12:11:28.026382 RX Vref 0 -> 0, step: 1
5355 12:11:28.026445
5356 12:11:28.029280 RX Delay -80 -> 252, step: 8
5357 12:11:28.032814 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5358 12:11:28.039384 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5359 12:11:28.042457 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5360 12:11:28.046112 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5361 12:11:28.049164 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5362 12:11:28.052387 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5363 12:11:28.055827 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5364 12:11:28.062367 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5365 12:11:28.065597 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5366 12:11:28.069279 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5367 12:11:28.072220 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5368 12:11:28.075758 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5369 12:11:28.078919 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5370 12:11:28.085620 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5371 12:11:28.089062 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5372 12:11:28.091953 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5373 12:11:28.092039 ==
5374 12:11:28.095281 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 12:11:28.098969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 12:11:28.099067 ==
5377 12:11:28.101915 DQS Delay:
5378 12:11:28.102004 DQS0 = 0, DQS1 = 0
5379 12:11:28.105537 DQM Delay:
5380 12:11:28.105642 DQM0 = 105, DQM1 = 90
5381 12:11:28.105712 DQ Delay:
5382 12:11:28.108561 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5383 12:11:28.111747 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5384 12:11:28.115191 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5385 12:11:28.121988 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5386 12:11:28.122075
5387 12:11:28.122143
5388 12:11:28.122206 ==
5389 12:11:28.125434 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 12:11:28.128730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 12:11:28.128832 ==
5392 12:11:28.128901
5393 12:11:28.128965
5394 12:11:28.131747 TX Vref Scan disable
5395 12:11:28.131831 == TX Byte 0 ==
5396 12:11:28.138487 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5397 12:11:28.141667 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5398 12:11:28.141752 == TX Byte 1 ==
5399 12:11:28.148256 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5400 12:11:28.151408 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5401 12:11:28.151515 ==
5402 12:11:28.154961 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 12:11:28.158129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 12:11:28.158240 ==
5405 12:11:28.158337
5406 12:11:28.161613
5407 12:11:28.161698 TX Vref Scan disable
5408 12:11:28.164882 == TX Byte 0 ==
5409 12:11:28.167955 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5410 12:11:28.171650 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5411 12:11:28.174793 == TX Byte 1 ==
5412 12:11:28.178293 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5413 12:11:28.181391 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5414 12:11:28.184876
5415 12:11:28.184967 [DATLAT]
5416 12:11:28.185035 Freq=933, CH0 RK1
5417 12:11:28.185100
5418 12:11:28.188006 DATLAT Default: 0xb
5419 12:11:28.188115 0, 0xFFFF, sum = 0
5420 12:11:28.191552 1, 0xFFFF, sum = 0
5421 12:11:28.191632 2, 0xFFFF, sum = 0
5422 12:11:28.194555 3, 0xFFFF, sum = 0
5423 12:11:28.194657 4, 0xFFFF, sum = 0
5424 12:11:28.197900 5, 0xFFFF, sum = 0
5425 12:11:28.201221 6, 0xFFFF, sum = 0
5426 12:11:28.201313 7, 0xFFFF, sum = 0
5427 12:11:28.204322 8, 0xFFFF, sum = 0
5428 12:11:28.204428 9, 0xFFFF, sum = 0
5429 12:11:28.207953 10, 0x0, sum = 1
5430 12:11:28.208028 11, 0x0, sum = 2
5431 12:11:28.208094 12, 0x0, sum = 3
5432 12:11:28.211086 13, 0x0, sum = 4
5433 12:11:28.211180 best_step = 11
5434 12:11:28.211250
5435 12:11:28.214557 ==
5436 12:11:28.214646 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 12:11:28.221135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 12:11:28.221224 ==
5439 12:11:28.221294 RX Vref Scan: 0
5440 12:11:28.221361
5441 12:11:28.224181 RX Vref 0 -> 0, step: 1
5442 12:11:28.224270
5443 12:11:28.227592 RX Delay -53 -> 252, step: 4
5444 12:11:28.231107 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5445 12:11:28.237368 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5446 12:11:28.240835 iDelay=199, Bit 2, Center 104 (19 ~ 190) 172
5447 12:11:28.244031 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5448 12:11:28.247603 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5449 12:11:28.250605 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5450 12:11:28.257671 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5451 12:11:28.260820 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5452 12:11:28.263852 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5453 12:11:28.267376 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5454 12:11:28.270726 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5455 12:11:28.277491 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5456 12:11:28.280654 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5457 12:11:28.283628 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5458 12:11:28.287182 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5459 12:11:28.290307 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5460 12:11:28.290379 ==
5461 12:11:28.293911 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 12:11:28.300357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 12:11:28.300465 ==
5464 12:11:28.300568 DQS Delay:
5465 12:11:28.303783 DQS0 = 0, DQS1 = 0
5466 12:11:28.303891 DQM Delay:
5467 12:11:28.307430 DQM0 = 105, DQM1 = 92
5468 12:11:28.307545 DQ Delay:
5469 12:11:28.310334 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =98
5470 12:11:28.313432 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5471 12:11:28.317173 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5472 12:11:28.320151 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =96
5473 12:11:28.320242
5474 12:11:28.320310
5475 12:11:28.330331 [DQSOSCAuto] RK1, (LSB)MR18= 0x290a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5476 12:11:28.330419 CH0 RK1: MR19=505, MR18=290A
5477 12:11:28.336852 CH0_RK1: MR19=0x505, MR18=0x290A, DQSOSC=408, MR23=63, INC=65, DEC=43
5478 12:11:28.339888 [RxdqsGatingPostProcess] freq 933
5479 12:11:28.346605 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 12:11:28.350083 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 12:11:28.353186 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 12:11:28.356268 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 12:11:28.359785 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 12:11:28.362962 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 12:11:28.363039 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 12:11:28.366524 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 12:11:28.369674 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 12:11:28.373074 Pre-setting of DQS Precalculation
5489 12:11:28.379690 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 12:11:28.379802 ==
5491 12:11:28.382815 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 12:11:28.385816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 12:11:28.385925 ==
5494 12:11:28.392532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 12:11:28.399374 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5496 12:11:28.402324 [CA 0] Center 37 (7~68) winsize 62
5497 12:11:28.405872 [CA 1] Center 37 (7~68) winsize 62
5498 12:11:28.409337 [CA 2] Center 35 (5~66) winsize 62
5499 12:11:28.412496 [CA 3] Center 34 (4~65) winsize 62
5500 12:11:28.415681 [CA 4] Center 35 (5~65) winsize 61
5501 12:11:28.419120 [CA 5] Center 34 (4~65) winsize 62
5502 12:11:28.419265
5503 12:11:28.422390 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5504 12:11:28.422530
5505 12:11:28.425531 [CATrainingPosCal] consider 1 rank data
5506 12:11:28.429035 u2DelayCellTimex100 = 270/100 ps
5507 12:11:28.432415 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5508 12:11:28.435346 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5509 12:11:28.439236 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5510 12:11:28.442200 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5511 12:11:28.445747 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5512 12:11:28.448963 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5513 12:11:28.449042
5514 12:11:28.455660 CA PerBit enable=1, Macro0, CA PI delay=34
5515 12:11:28.455745
5516 12:11:28.455813 [CBTSetCACLKResult] CA Dly = 34
5517 12:11:28.458764 CS Dly: 6 (0~37)
5518 12:11:28.458866 ==
5519 12:11:28.462247 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 12:11:28.465399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 12:11:28.465480 ==
5522 12:11:28.472064 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 12:11:28.479120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 12:11:28.482195 [CA 0] Center 38 (8~69) winsize 62
5525 12:11:28.485406 [CA 1] Center 38 (8~69) winsize 62
5526 12:11:28.488815 [CA 2] Center 36 (6~67) winsize 62
5527 12:11:28.491843 [CA 3] Center 35 (5~65) winsize 61
5528 12:11:28.495351 [CA 4] Center 35 (5~66) winsize 62
5529 12:11:28.498927 [CA 5] Center 35 (5~65) winsize 61
5530 12:11:28.499015
5531 12:11:28.501893 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 12:11:28.501982
5533 12:11:28.505571 [CATrainingPosCal] consider 2 rank data
5534 12:11:28.508587 u2DelayCellTimex100 = 270/100 ps
5535 12:11:28.511674 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5536 12:11:28.515395 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5537 12:11:28.518556 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5538 12:11:28.522215 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5539 12:11:28.525419 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5540 12:11:28.532097 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5541 12:11:28.532190
5542 12:11:28.535062 CA PerBit enable=1, Macro0, CA PI delay=35
5543 12:11:28.535177
5544 12:11:28.538659 [CBTSetCACLKResult] CA Dly = 35
5545 12:11:28.538747 CS Dly: 7 (0~40)
5546 12:11:28.538816
5547 12:11:28.541755 ----->DramcWriteLeveling(PI) begin...
5548 12:11:28.541842 ==
5549 12:11:28.545084 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 12:11:28.548417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 12:11:28.551336 ==
5552 12:11:28.554959 Write leveling (Byte 0): 26 => 26
5553 12:11:28.555071 Write leveling (Byte 1): 29 => 29
5554 12:11:28.558067 DramcWriteLeveling(PI) end<-----
5555 12:11:28.558199
5556 12:11:28.558318 ==
5557 12:11:28.561643 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 12:11:28.568171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 12:11:28.568280 ==
5560 12:11:28.571252 [Gating] SW mode calibration
5561 12:11:28.577936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 12:11:28.581467 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 12:11:28.588132 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:11:28.591293 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 12:11:28.594669 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 12:11:28.601260 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 12:11:28.604314 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 12:11:28.607940 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5569 12:11:28.614227 0 14 24 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
5570 12:11:28.617652 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5571 12:11:28.621153 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 12:11:28.627387 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 12:11:28.630876 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 12:11:28.633924 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 12:11:28.640947 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 12:11:28.643956 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 12:11:28.647593 0 15 24 | B1->B0 | 2727 2d2d | 0 1 | (0 0) (1 1)
5578 12:11:28.654026 0 15 28 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
5579 12:11:28.657372 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:11:28.660871 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 12:11:28.667443 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 12:11:28.670915 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 12:11:28.673953 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 12:11:28.680713 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 12:11:28.683921 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5586 12:11:28.686957 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:11:28.693665 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:11:28.697147 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:11:28.700562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:11:28.703524 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:11:28.710621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:11:28.713599 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:11:28.720141 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:11:28.723231 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:11:28.726838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:11:28.733112 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:11:28.736673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:11:28.739762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:11:28.743354 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:11:28.749998 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:11:28.753254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5602 12:11:28.756465 Total UI for P1: 0, mck2ui 16
5603 12:11:28.759972 best dqsien dly found for B0: ( 1, 2, 22)
5604 12:11:28.763253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 12:11:28.766745 Total UI for P1: 0, mck2ui 16
5606 12:11:28.769853 best dqsien dly found for B1: ( 1, 2, 24)
5607 12:11:28.772890 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5608 12:11:28.779315 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5609 12:11:28.779396
5610 12:11:28.783004 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5611 12:11:28.786204 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5612 12:11:28.789213 [Gating] SW calibration Done
5613 12:11:28.789299 ==
5614 12:11:28.792691 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 12:11:28.795914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 12:11:28.795999 ==
5617 12:11:28.799047 RX Vref Scan: 0
5618 12:11:28.799131
5619 12:11:28.799199 RX Vref 0 -> 0, step: 1
5620 12:11:28.799262
5621 12:11:28.802499 RX Delay -80 -> 252, step: 8
5622 12:11:28.805815 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5623 12:11:28.812437 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5624 12:11:28.815509 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5625 12:11:28.819222 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5626 12:11:28.822305 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5627 12:11:28.825857 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5628 12:11:28.828828 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5629 12:11:28.835379 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5630 12:11:28.838958 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5631 12:11:28.842102 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5632 12:11:28.845563 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5633 12:11:28.848619 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5634 12:11:28.852329 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5635 12:11:28.858359 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5636 12:11:28.862032 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5637 12:11:28.865090 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5638 12:11:28.865226 ==
5639 12:11:28.868569 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 12:11:28.871580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 12:11:28.871684 ==
5642 12:11:28.875048 DQS Delay:
5643 12:11:28.875168 DQS0 = 0, DQS1 = 0
5644 12:11:28.878538 DQM Delay:
5645 12:11:28.878639 DQM0 = 102, DQM1 = 95
5646 12:11:28.881462 DQ Delay:
5647 12:11:28.881536 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5648 12:11:28.884952 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5649 12:11:28.888067 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5650 12:11:28.895117 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5651 12:11:28.895220
5652 12:11:28.895346
5653 12:11:28.895437 ==
5654 12:11:28.898170 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 12:11:28.901400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 12:11:28.901490 ==
5657 12:11:28.901559
5658 12:11:28.901626
5659 12:11:28.904892 TX Vref Scan disable
5660 12:11:28.905067 == TX Byte 0 ==
5661 12:11:28.911255 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5662 12:11:28.914772 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5663 12:11:28.914880 == TX Byte 1 ==
5664 12:11:28.921346 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5665 12:11:28.924813 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5666 12:11:28.924918 ==
5667 12:11:28.927900 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 12:11:28.931470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 12:11:28.931559 ==
5670 12:11:28.931630
5671 12:11:28.934627
5672 12:11:28.934717 TX Vref Scan disable
5673 12:11:28.938166 == TX Byte 0 ==
5674 12:11:28.941360 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5675 12:11:28.944573 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5676 12:11:28.948125 == TX Byte 1 ==
5677 12:11:28.951173 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5678 12:11:28.954704 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5679 12:11:28.954789
5680 12:11:28.957698 [DATLAT]
5681 12:11:28.957782 Freq=933, CH1 RK0
5682 12:11:28.957850
5683 12:11:28.961004 DATLAT Default: 0xd
5684 12:11:28.961089 0, 0xFFFF, sum = 0
5685 12:11:28.964555 1, 0xFFFF, sum = 0
5686 12:11:28.964641 2, 0xFFFF, sum = 0
5687 12:11:28.967679 3, 0xFFFF, sum = 0
5688 12:11:28.967765 4, 0xFFFF, sum = 0
5689 12:11:28.971082 5, 0xFFFF, sum = 0
5690 12:11:28.974347 6, 0xFFFF, sum = 0
5691 12:11:28.974434 7, 0xFFFF, sum = 0
5692 12:11:28.977882 8, 0xFFFF, sum = 0
5693 12:11:28.977968 9, 0xFFFF, sum = 0
5694 12:11:28.980859 10, 0x0, sum = 1
5695 12:11:28.980967 11, 0x0, sum = 2
5696 12:11:28.981074 12, 0x0, sum = 3
5697 12:11:28.984400 13, 0x0, sum = 4
5698 12:11:28.984485 best_step = 11
5699 12:11:28.984553
5700 12:11:28.987667 ==
5701 12:11:28.987752 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 12:11:28.994010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 12:11:28.994095 ==
5704 12:11:28.994162 RX Vref Scan: 1
5705 12:11:28.994227
5706 12:11:28.997483 RX Vref 0 -> 0, step: 1
5707 12:11:28.997586
5708 12:11:29.001162 RX Delay -53 -> 252, step: 4
5709 12:11:29.001242
5710 12:11:29.004156 Set Vref, RX VrefLevel [Byte0]: 53
5711 12:11:29.007370 [Byte1]: 55
5712 12:11:29.007470
5713 12:11:29.010904 Final RX Vref Byte 0 = 53 to rank0
5714 12:11:29.014421 Final RX Vref Byte 1 = 55 to rank0
5715 12:11:29.017359 Final RX Vref Byte 0 = 53 to rank1
5716 12:11:29.020737 Final RX Vref Byte 1 = 55 to rank1==
5717 12:11:29.023907 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 12:11:29.027626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 12:11:29.027710 ==
5720 12:11:29.030738 DQS Delay:
5721 12:11:29.030827 DQS0 = 0, DQS1 = 0
5722 12:11:29.034076 DQM Delay:
5723 12:11:29.034179 DQM0 = 104, DQM1 = 97
5724 12:11:29.037100 DQ Delay:
5725 12:11:29.040729 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5726 12:11:29.043846 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5727 12:11:29.047012 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =92
5728 12:11:29.050660 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5729 12:11:29.050743
5730 12:11:29.050810
5731 12:11:29.057129 [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5732 12:11:29.060130 CH1 RK0: MR19=505, MR18=1930
5733 12:11:29.066771 CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43
5734 12:11:29.066882
5735 12:11:29.070386 ----->DramcWriteLeveling(PI) begin...
5736 12:11:29.070495 ==
5737 12:11:29.073212 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 12:11:29.076891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 12:11:29.076970 ==
5740 12:11:29.079866 Write leveling (Byte 0): 27 => 27
5741 12:11:29.083409 Write leveling (Byte 1): 28 => 28
5742 12:11:29.086691 DramcWriteLeveling(PI) end<-----
5743 12:11:29.086793
5744 12:11:29.086884 ==
5745 12:11:29.089940 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 12:11:29.096648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 12:11:29.096750 ==
5748 12:11:29.096891 [Gating] SW mode calibration
5749 12:11:29.106619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5750 12:11:29.109604 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5751 12:11:29.116322 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5752 12:11:29.119361 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 12:11:29.122745 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 12:11:29.129325 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 12:11:29.132926 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 12:11:29.135967 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 12:11:29.142631 0 14 24 | B1->B0 | 2f2f 3333 | 0 1 | (0 1) (1 1)
5758 12:11:29.145966 0 14 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
5759 12:11:29.149630 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5760 12:11:29.152657 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 12:11:29.159214 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 12:11:29.162754 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 12:11:29.165806 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 12:11:29.172459 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 12:11:29.176141 0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
5766 12:11:29.179139 0 15 28 | B1->B0 | 4040 3838 | 0 1 | (0 0) (0 0)
5767 12:11:29.186005 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5768 12:11:29.189051 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 12:11:29.192567 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 12:11:29.199207 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 12:11:29.202363 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 12:11:29.205470 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 12:11:29.212134 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5774 12:11:29.215711 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5775 12:11:29.218714 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:11:29.225535 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:11:29.229016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:11:29.232085 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:11:29.238669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:11:29.242307 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:11:29.245284 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:11:29.251920 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:11:29.255117 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:11:29.258748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:11:29.265086 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:11:29.268584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:11:29.271729 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:11:29.278512 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:11:29.281468 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5790 12:11:29.285011 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5791 12:11:29.288076 Total UI for P1: 0, mck2ui 16
5792 12:11:29.291584 best dqsien dly found for B1: ( 1, 2, 24)
5793 12:11:29.297884 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 12:11:29.297968 Total UI for P1: 0, mck2ui 16
5795 12:11:29.304679 best dqsien dly found for B0: ( 1, 2, 28)
5796 12:11:29.308020 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5797 12:11:29.310977 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5798 12:11:29.311082
5799 12:11:29.314454 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5800 12:11:29.317987 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 12:11:29.321150 [Gating] SW calibration Done
5802 12:11:29.321260 ==
5803 12:11:29.324655 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 12:11:29.327596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 12:11:29.327701 ==
5806 12:11:29.331107 RX Vref Scan: 0
5807 12:11:29.331219
5808 12:11:29.331315 RX Vref 0 -> 0, step: 1
5809 12:11:29.334613
5810 12:11:29.334690 RX Delay -80 -> 252, step: 8
5811 12:11:29.340728 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5812 12:11:29.344419 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5813 12:11:29.347346 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5814 12:11:29.351028 iDelay=200, Bit 3, Center 107 (24 ~ 191) 168
5815 12:11:29.354183 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5816 12:11:29.360381 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5817 12:11:29.364005 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5818 12:11:29.367550 iDelay=200, Bit 7, Center 107 (24 ~ 191) 168
5819 12:11:29.370608 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5820 12:11:29.373760 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5821 12:11:29.377441 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5822 12:11:29.383718 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5823 12:11:29.387186 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5824 12:11:29.390670 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5825 12:11:29.393768 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5826 12:11:29.396942 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5827 12:11:29.400511 ==
5828 12:11:29.400595 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 12:11:29.406842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 12:11:29.406928 ==
5831 12:11:29.406995 DQS Delay:
5832 12:11:29.410146 DQS0 = 0, DQS1 = 0
5833 12:11:29.410231 DQM Delay:
5834 12:11:29.413438 DQM0 = 103, DQM1 = 95
5835 12:11:29.413522 DQ Delay:
5836 12:11:29.417225 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =107
5837 12:11:29.420118 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =107
5838 12:11:29.423585 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5839 12:11:29.427099 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5840 12:11:29.427203
5841 12:11:29.427285
5842 12:11:29.427374 ==
5843 12:11:29.430586 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 12:11:29.433503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 12:11:29.436799 ==
5846 12:11:29.436882
5847 12:11:29.436948
5848 12:11:29.437023 TX Vref Scan disable
5849 12:11:29.439952 == TX Byte 0 ==
5850 12:11:29.443665 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5851 12:11:29.446776 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5852 12:11:29.450400 == TX Byte 1 ==
5853 12:11:29.453425 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5854 12:11:29.456578 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5855 12:11:29.460302 ==
5856 12:11:29.460385 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 12:11:29.466502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 12:11:29.466586 ==
5859 12:11:29.466652
5860 12:11:29.466711
5861 12:11:29.470149 TX Vref Scan disable
5862 12:11:29.470248 == TX Byte 0 ==
5863 12:11:29.476715 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5864 12:11:29.479808 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5865 12:11:29.479891 == TX Byte 1 ==
5866 12:11:29.486095 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 12:11:29.489730 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 12:11:29.489812
5869 12:11:29.489892 [DATLAT]
5870 12:11:29.493062 Freq=933, CH1 RK1
5871 12:11:29.493145
5872 12:11:29.493239 DATLAT Default: 0xb
5873 12:11:29.496092 0, 0xFFFF, sum = 0
5874 12:11:29.496192 1, 0xFFFF, sum = 0
5875 12:11:29.499639 2, 0xFFFF, sum = 0
5876 12:11:29.499722 3, 0xFFFF, sum = 0
5877 12:11:29.502746 4, 0xFFFF, sum = 0
5878 12:11:29.502868 5, 0xFFFF, sum = 0
5879 12:11:29.506455 6, 0xFFFF, sum = 0
5880 12:11:29.506539 7, 0xFFFF, sum = 0
5881 12:11:29.509530 8, 0xFFFF, sum = 0
5882 12:11:29.512645 9, 0xFFFF, sum = 0
5883 12:11:29.512746 10, 0x0, sum = 1
5884 12:11:29.512835 11, 0x0, sum = 2
5885 12:11:29.516050 12, 0x0, sum = 3
5886 12:11:29.516150 13, 0x0, sum = 4
5887 12:11:29.519594 best_step = 11
5888 12:11:29.519677
5889 12:11:29.519792 ==
5890 12:11:29.522580 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 12:11:29.525845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 12:11:29.525945 ==
5893 12:11:29.529197 RX Vref Scan: 0
5894 12:11:29.529296
5895 12:11:29.529393 RX Vref 0 -> 0, step: 1
5896 12:11:29.532570
5897 12:11:29.532692 RX Delay -53 -> 252, step: 4
5898 12:11:29.539916 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5899 12:11:29.543550 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5900 12:11:29.546595 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5901 12:11:29.550194 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5902 12:11:29.553131 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5903 12:11:29.559863 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5904 12:11:29.562868 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5905 12:11:29.566454 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5906 12:11:29.569591 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5907 12:11:29.573172 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5908 12:11:29.579673 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5909 12:11:29.583291 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5910 12:11:29.586410 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5911 12:11:29.589454 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5912 12:11:29.593022 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5913 12:11:29.599560 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5914 12:11:29.599669 ==
5915 12:11:29.602642 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 12:11:29.606234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 12:11:29.606308 ==
5918 12:11:29.606400 DQS Delay:
5919 12:11:29.609413 DQS0 = 0, DQS1 = 0
5920 12:11:29.609534 DQM Delay:
5921 12:11:29.612484 DQM0 = 105, DQM1 = 97
5922 12:11:29.612570 DQ Delay:
5923 12:11:29.616174 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5924 12:11:29.619054 DQ4 =106, DQ5 =116, DQ6 =114, DQ7 =102
5925 12:11:29.622629 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5926 12:11:29.625715 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5927 12:11:29.625801
5928 12:11:29.625870
5929 12:11:29.635916 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5930 12:11:29.639332 CH1 RK1: MR19=504, MR18=20FD
5931 12:11:29.642567 CH1_RK1: MR19=0x504, MR18=0x20FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5932 12:11:29.646123 [RxdqsGatingPostProcess] freq 933
5933 12:11:29.652329 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5934 12:11:29.655477 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 12:11:29.659048 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 12:11:29.662166 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 12:11:29.665796 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 12:11:29.668706 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 12:11:29.672375 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 12:11:29.675577 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 12:11:29.678918 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 12:11:29.682091 Pre-setting of DQS Precalculation
5943 12:11:29.685677 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5944 12:11:29.692279 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5945 12:11:29.698452 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5946 12:11:29.698571
5947 12:11:29.701998
5948 12:11:29.702085 [Calibration Summary] 1866 Mbps
5949 12:11:29.705567 CH 0, Rank 0
5950 12:11:29.705669 SW Impedance : PASS
5951 12:11:29.708575 DUTY Scan : NO K
5952 12:11:29.711660 ZQ Calibration : PASS
5953 12:11:29.711748 Jitter Meter : NO K
5954 12:11:29.715166 CBT Training : PASS
5955 12:11:29.718755 Write leveling : PASS
5956 12:11:29.718829 RX DQS gating : PASS
5957 12:11:29.721978 RX DQ/DQS(RDDQC) : PASS
5958 12:11:29.725268 TX DQ/DQS : PASS
5959 12:11:29.725350 RX DATLAT : PASS
5960 12:11:29.728323 RX DQ/DQS(Engine): PASS
5961 12:11:29.732028 TX OE : NO K
5962 12:11:29.732107 All Pass.
5963 12:11:29.732174
5964 12:11:29.732235 CH 0, Rank 1
5965 12:11:29.734902 SW Impedance : PASS
5966 12:11:29.738287 DUTY Scan : NO K
5967 12:11:29.738388 ZQ Calibration : PASS
5968 12:11:29.741602 Jitter Meter : NO K
5969 12:11:29.745029 CBT Training : PASS
5970 12:11:29.745108 Write leveling : PASS
5971 12:11:29.748312 RX DQS gating : PASS
5972 12:11:29.751720 RX DQ/DQS(RDDQC) : PASS
5973 12:11:29.751830 TX DQ/DQS : PASS
5974 12:11:29.754872 RX DATLAT : PASS
5975 12:11:29.754975 RX DQ/DQS(Engine): PASS
5976 12:11:29.758002 TX OE : NO K
5977 12:11:29.758078 All Pass.
5978 12:11:29.758143
5979 12:11:29.761681 CH 1, Rank 0
5980 12:11:29.761761 SW Impedance : PASS
5981 12:11:29.764645 DUTY Scan : NO K
5982 12:11:29.768264 ZQ Calibration : PASS
5983 12:11:29.768350 Jitter Meter : NO K
5984 12:11:29.771511 CBT Training : PASS
5985 12:11:29.775090 Write leveling : PASS
5986 12:11:29.775192 RX DQS gating : PASS
5987 12:11:29.778210 RX DQ/DQS(RDDQC) : PASS
5988 12:11:29.781405 TX DQ/DQS : PASS
5989 12:11:29.781500 RX DATLAT : PASS
5990 12:11:29.784893 RX DQ/DQS(Engine): PASS
5991 12:11:29.787937 TX OE : NO K
5992 12:11:29.788020 All Pass.
5993 12:11:29.788086
5994 12:11:29.788157 CH 1, Rank 1
5995 12:11:29.791538 SW Impedance : PASS
5996 12:11:29.794636 DUTY Scan : NO K
5997 12:11:29.794738 ZQ Calibration : PASS
5998 12:11:29.798191 Jitter Meter : NO K
5999 12:11:29.801155 CBT Training : PASS
6000 12:11:29.801233 Write leveling : PASS
6001 12:11:29.804638 RX DQS gating : PASS
6002 12:11:29.808050 RX DQ/DQS(RDDQC) : PASS
6003 12:11:29.808124 TX DQ/DQS : PASS
6004 12:11:29.811150 RX DATLAT : PASS
6005 12:11:29.811248 RX DQ/DQS(Engine): PASS
6006 12:11:29.814678 TX OE : NO K
6007 12:11:29.814777 All Pass.
6008 12:11:29.814869
6009 12:11:29.817901 DramC Write-DBI off
6010 12:11:29.821127 PER_BANK_REFRESH: Hybrid Mode
6011 12:11:29.821222 TX_TRACKING: ON
6012 12:11:29.831140 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6013 12:11:29.834128 [FAST_K] Save calibration result to emmc
6014 12:11:29.837698 dramc_set_vcore_voltage set vcore to 650000
6015 12:11:29.840650 Read voltage for 400, 6
6016 12:11:29.840734 Vio18 = 0
6017 12:11:29.844128 Vcore = 650000
6018 12:11:29.844206 Vdram = 0
6019 12:11:29.844273 Vddq = 0
6020 12:11:29.844340 Vmddr = 0
6021 12:11:29.850817 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6022 12:11:29.857419 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6023 12:11:29.857500 MEM_TYPE=3, freq_sel=20
6024 12:11:29.860952 sv_algorithm_assistance_LP4_800
6025 12:11:29.864033 ============ PULL DRAM RESETB DOWN ============
6026 12:11:29.871028 ========== PULL DRAM RESETB DOWN end =========
6027 12:11:29.874021 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6028 12:11:29.877275 ===================================
6029 12:11:29.880913 LPDDR4 DRAM CONFIGURATION
6030 12:11:29.883949 ===================================
6031 12:11:29.884024 EX_ROW_EN[0] = 0x0
6032 12:11:29.887309 EX_ROW_EN[1] = 0x0
6033 12:11:29.887384 LP4Y_EN = 0x0
6034 12:11:29.890922 WORK_FSP = 0x0
6035 12:11:29.890998 WL = 0x2
6036 12:11:29.893968 RL = 0x2
6037 12:11:29.894044 BL = 0x2
6038 12:11:29.897106 RPST = 0x0
6039 12:11:29.900614 RD_PRE = 0x0
6040 12:11:29.900692 WR_PRE = 0x1
6041 12:11:29.903771 WR_PST = 0x0
6042 12:11:29.903842 DBI_WR = 0x0
6043 12:11:29.906864 DBI_RD = 0x0
6044 12:11:29.906935 OTF = 0x1
6045 12:11:29.910409 ===================================
6046 12:11:29.913933 ===================================
6047 12:11:29.917031 ANA top config
6048 12:11:29.920694 ===================================
6049 12:11:29.920828 DLL_ASYNC_EN = 0
6050 12:11:29.923961 ALL_SLAVE_EN = 1
6051 12:11:29.927029 NEW_RANK_MODE = 1
6052 12:11:29.930169 DLL_IDLE_MODE = 1
6053 12:11:29.930241 LP45_APHY_COMB_EN = 1
6054 12:11:29.933775 TX_ODT_DIS = 1
6055 12:11:29.936711 NEW_8X_MODE = 1
6056 12:11:29.940227 ===================================
6057 12:11:29.943362 ===================================
6058 12:11:29.946442 data_rate = 800
6059 12:11:29.949908 CKR = 1
6060 12:11:29.953251 DQ_P2S_RATIO = 4
6061 12:11:29.956526 ===================================
6062 12:11:29.956638 CA_P2S_RATIO = 4
6063 12:11:29.959976 DQ_CA_OPEN = 0
6064 12:11:29.963315 DQ_SEMI_OPEN = 1
6065 12:11:29.966406 CA_SEMI_OPEN = 1
6066 12:11:29.969848 CA_FULL_RATE = 0
6067 12:11:29.973229 DQ_CKDIV4_EN = 0
6068 12:11:29.973306 CA_CKDIV4_EN = 1
6069 12:11:29.976331 CA_PREDIV_EN = 0
6070 12:11:29.979397 PH8_DLY = 0
6071 12:11:29.983063 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6072 12:11:29.986211 DQ_AAMCK_DIV = 0
6073 12:11:29.989277 CA_AAMCK_DIV = 0
6074 12:11:29.992686 CA_ADMCK_DIV = 4
6075 12:11:29.992826 DQ_TRACK_CA_EN = 0
6076 12:11:29.995841 CA_PICK = 800
6077 12:11:29.998986 CA_MCKIO = 400
6078 12:11:30.002587 MCKIO_SEMI = 400
6079 12:11:30.005756 PLL_FREQ = 3016
6080 12:11:30.008920 DQ_UI_PI_RATIO = 32
6081 12:11:30.012518 CA_UI_PI_RATIO = 32
6082 12:11:30.015496 ===================================
6083 12:11:30.018851 ===================================
6084 12:11:30.018930 memory_type:LPDDR4
6085 12:11:30.022483 GP_NUM : 10
6086 12:11:30.025642 SRAM_EN : 1
6087 12:11:30.025745 MD32_EN : 0
6088 12:11:30.028642 ===================================
6089 12:11:30.032347 [ANA_INIT] >>>>>>>>>>>>>>
6090 12:11:30.035446 <<<<<< [CONFIGURE PHASE]: ANA_TX
6091 12:11:30.039011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6092 12:11:30.042166 ===================================
6093 12:11:30.045603 data_rate = 800,PCW = 0X7400
6094 12:11:30.048641 ===================================
6095 12:11:30.051857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6096 12:11:30.055476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 12:11:30.068735 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 12:11:30.071820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6099 12:11:30.075294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6100 12:11:30.078330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6101 12:11:30.081407 [ANA_INIT] flow start
6102 12:11:30.085092 [ANA_INIT] PLL >>>>>>>>
6103 12:11:30.085176 [ANA_INIT] PLL <<<<<<<<
6104 12:11:30.088119 [ANA_INIT] MIDPI >>>>>>>>
6105 12:11:30.091748 [ANA_INIT] MIDPI <<<<<<<<
6106 12:11:30.091824 [ANA_INIT] DLL >>>>>>>>
6107 12:11:30.094756 [ANA_INIT] flow end
6108 12:11:30.098303 ============ LP4 DIFF to SE enter ============
6109 12:11:30.104883 ============ LP4 DIFF to SE exit ============
6110 12:11:30.104972 [ANA_INIT] <<<<<<<<<<<<<
6111 12:11:30.107934 [Flow] Enable top DCM control >>>>>
6112 12:11:30.111548 [Flow] Enable top DCM control <<<<<
6113 12:11:30.114672 Enable DLL master slave shuffle
6114 12:11:30.121290 ==============================================================
6115 12:11:30.121379 Gating Mode config
6116 12:11:30.127656 ==============================================================
6117 12:11:30.131262 Config description:
6118 12:11:30.137834 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6119 12:11:30.147753 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6120 12:11:30.150831 SELPH_MODE 0: By rank 1: By Phase
6121 12:11:30.157463 ==============================================================
6122 12:11:30.161063 GAT_TRACK_EN = 0
6123 12:11:30.161138 RX_GATING_MODE = 2
6124 12:11:30.164111 RX_GATING_TRACK_MODE = 2
6125 12:11:30.167543 SELPH_MODE = 1
6126 12:11:30.170532 PICG_EARLY_EN = 1
6127 12:11:30.174027 VALID_LAT_VALUE = 1
6128 12:11:30.180553 ==============================================================
6129 12:11:30.184073 Enter into Gating configuration >>>>
6130 12:11:30.187174 Exit from Gating configuration <<<<
6131 12:11:30.190374 Enter into DVFS_PRE_config >>>>>
6132 12:11:30.200618 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6133 12:11:30.203621 Exit from DVFS_PRE_config <<<<<
6134 12:11:30.207287 Enter into PICG configuration >>>>
6135 12:11:30.210169 Exit from PICG configuration <<<<
6136 12:11:30.213833 [RX_INPUT] configuration >>>>>
6137 12:11:30.216932 [RX_INPUT] configuration <<<<<
6138 12:11:30.219996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6139 12:11:30.227075 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6140 12:11:30.233383 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 12:11:30.240168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 12:11:30.243291 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 12:11:30.250106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 12:11:30.253246 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6145 12:11:30.259864 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6146 12:11:30.263492 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6147 12:11:30.266654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6148 12:11:30.269813 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6149 12:11:30.276567 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6150 12:11:30.279512 ===================================
6151 12:11:30.282768 LPDDR4 DRAM CONFIGURATION
6152 12:11:30.286136 ===================================
6153 12:11:30.286212 EX_ROW_EN[0] = 0x0
6154 12:11:30.289622 EX_ROW_EN[1] = 0x0
6155 12:11:30.289695 LP4Y_EN = 0x0
6156 12:11:30.292635 WORK_FSP = 0x0
6157 12:11:30.292732 WL = 0x2
6158 12:11:30.296220 RL = 0x2
6159 12:11:30.296303 BL = 0x2
6160 12:11:30.299284 RPST = 0x0
6161 12:11:30.299366 RD_PRE = 0x0
6162 12:11:30.302789 WR_PRE = 0x1
6163 12:11:30.302871 WR_PST = 0x0
6164 12:11:30.306158 DBI_WR = 0x0
6165 12:11:30.309117 DBI_RD = 0x0
6166 12:11:30.309200 OTF = 0x1
6167 12:11:30.312564 ===================================
6168 12:11:30.316212 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6169 12:11:30.319350 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6170 12:11:30.325596 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 12:11:30.328944 ===================================
6172 12:11:30.332653 LPDDR4 DRAM CONFIGURATION
6173 12:11:30.335622 ===================================
6174 12:11:30.335698 EX_ROW_EN[0] = 0x10
6175 12:11:30.339162 EX_ROW_EN[1] = 0x0
6176 12:11:30.339244 LP4Y_EN = 0x0
6177 12:11:30.342193 WORK_FSP = 0x0
6178 12:11:30.342275 WL = 0x2
6179 12:11:30.345868 RL = 0x2
6180 12:11:30.345951 BL = 0x2
6181 12:11:30.348935 RPST = 0x0
6182 12:11:30.349036 RD_PRE = 0x0
6183 12:11:30.352507 WR_PRE = 0x1
6184 12:11:30.355377 WR_PST = 0x0
6185 12:11:30.355478 DBI_WR = 0x0
6186 12:11:30.358847 DBI_RD = 0x0
6187 12:11:30.358922 OTF = 0x1
6188 12:11:30.362373 ===================================
6189 12:11:30.368517 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6190 12:11:30.372209 nWR fixed to 30
6191 12:11:30.375756 [ModeRegInit_LP4] CH0 RK0
6192 12:11:30.375841 [ModeRegInit_LP4] CH0 RK1
6193 12:11:30.379182 [ModeRegInit_LP4] CH1 RK0
6194 12:11:30.382673 [ModeRegInit_LP4] CH1 RK1
6195 12:11:30.382789 match AC timing 19
6196 12:11:30.389049 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6197 12:11:30.392126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6198 12:11:30.395447 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6199 12:11:30.402209 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6200 12:11:30.405363 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6201 12:11:30.405447 ==
6202 12:11:30.408659 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 12:11:30.412005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6204 12:11:30.412112 ==
6205 12:11:30.418687 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6206 12:11:30.425227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6207 12:11:30.428364 [CA 0] Center 36 (8~64) winsize 57
6208 12:11:30.431848 [CA 1] Center 36 (8~64) winsize 57
6209 12:11:30.435267 [CA 2] Center 36 (8~64) winsize 57
6210 12:11:30.438376 [CA 3] Center 36 (8~64) winsize 57
6211 12:11:30.441927 [CA 4] Center 36 (8~64) winsize 57
6212 12:11:30.442015 [CA 5] Center 36 (8~64) winsize 57
6213 12:11:30.445038
6214 12:11:30.448110 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6215 12:11:30.448196
6216 12:11:30.451649 [CATrainingPosCal] consider 1 rank data
6217 12:11:30.455113 u2DelayCellTimex100 = 270/100 ps
6218 12:11:30.458185 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:11:30.461570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 12:11:30.464671 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 12:11:30.468151 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 12:11:30.471814 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 12:11:30.474892 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 12:11:30.474975
6225 12:11:30.477937 CA PerBit enable=1, Macro0, CA PI delay=36
6226 12:11:30.478019
6227 12:11:30.481620 [CBTSetCACLKResult] CA Dly = 36
6228 12:11:30.484662 CS Dly: 1 (0~32)
6229 12:11:30.484746 ==
6230 12:11:30.488001 Dram Type= 6, Freq= 0, CH_0, rank 1
6231 12:11:30.491411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 12:11:30.491494 ==
6233 12:11:30.497643 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 12:11:30.504735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6235 12:11:30.507784 [CA 0] Center 36 (8~64) winsize 57
6236 12:11:30.510816 [CA 1] Center 36 (8~64) winsize 57
6237 12:11:30.514257 [CA 2] Center 36 (8~64) winsize 57
6238 12:11:30.514342 [CA 3] Center 36 (8~64) winsize 57
6239 12:11:30.517705 [CA 4] Center 36 (8~64) winsize 57
6240 12:11:30.520789 [CA 5] Center 36 (8~64) winsize 57
6241 12:11:30.520877
6242 12:11:30.524386 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6243 12:11:30.527443
6244 12:11:30.531080 [CATrainingPosCal] consider 2 rank data
6245 12:11:30.534209 u2DelayCellTimex100 = 270/100 ps
6246 12:11:30.537634 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:11:30.541156 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:11:30.544201 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:11:30.547701 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:11:30.550679 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:11:30.554304 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:11:30.554390
6253 12:11:30.557392 CA PerBit enable=1, Macro0, CA PI delay=36
6254 12:11:30.557477
6255 12:11:30.560865 [CBTSetCACLKResult] CA Dly = 36
6256 12:11:30.563903 CS Dly: 1 (0~32)
6257 12:11:30.563987
6258 12:11:30.567401 ----->DramcWriteLeveling(PI) begin...
6259 12:11:30.567487 ==
6260 12:11:30.570578 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 12:11:30.574199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 12:11:30.574285 ==
6263 12:11:30.577308 Write leveling (Byte 0): 40 => 8
6264 12:11:30.580480 Write leveling (Byte 1): 32 => 0
6265 12:11:30.584174 DramcWriteLeveling(PI) end<-----
6266 12:11:30.584258
6267 12:11:30.584327 ==
6268 12:11:30.587700 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 12:11:30.590695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 12:11:30.590779 ==
6271 12:11:30.594056 [Gating] SW mode calibration
6272 12:11:30.600229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 12:11:30.607138 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6274 12:11:30.610247 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 12:11:30.613970 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 12:11:30.620478 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 12:11:30.623432 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 12:11:30.627095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 12:11:30.633364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 12:11:30.636948 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 12:11:30.640041 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 12:11:30.646537 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 12:11:30.650121 Total UI for P1: 0, mck2ui 16
6284 12:11:30.653271 best dqsien dly found for B0: ( 0, 14, 24)
6285 12:11:30.653360 Total UI for P1: 0, mck2ui 16
6286 12:11:30.659840 best dqsien dly found for B1: ( 0, 14, 24)
6287 12:11:30.663411 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6288 12:11:30.666586 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6289 12:11:30.666670
6290 12:11:30.669812 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 12:11:30.673465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 12:11:30.676578 [Gating] SW calibration Done
6293 12:11:30.676652 ==
6294 12:11:30.680109 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 12:11:30.683205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 12:11:30.683293 ==
6297 12:11:30.686515 RX Vref Scan: 0
6298 12:11:30.686601
6299 12:11:30.686669 RX Vref 0 -> 0, step: 1
6300 12:11:30.690055
6301 12:11:30.690141 RX Delay -410 -> 252, step: 16
6302 12:11:30.696199 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6303 12:11:30.699744 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6304 12:11:30.703118 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6305 12:11:30.706466 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6306 12:11:30.712732 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6307 12:11:30.716218 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6308 12:11:30.719450 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6309 12:11:30.722865 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6310 12:11:30.729193 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6311 12:11:30.732733 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6312 12:11:30.735822 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6313 12:11:30.739508 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6314 12:11:30.745984 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6315 12:11:30.749382 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6316 12:11:30.752359 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6317 12:11:30.759042 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6318 12:11:30.759120 ==
6319 12:11:30.762601 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 12:11:30.765808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 12:11:30.765882 ==
6322 12:11:30.765944 DQS Delay:
6323 12:11:30.768734 DQS0 = 27, DQS1 = 43
6324 12:11:30.768845 DQM Delay:
6325 12:11:30.772288 DQM0 = 18, DQM1 = 13
6326 12:11:30.772369 DQ Delay:
6327 12:11:30.775818 DQ0 =24, DQ1 =24, DQ2 =16, DQ3 =8
6328 12:11:30.778897 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6329 12:11:30.782564 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6330 12:11:30.785759 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6331 12:11:30.785841
6332 12:11:30.785906
6333 12:11:30.785968 ==
6334 12:11:30.789124 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 12:11:30.792295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 12:11:30.792406 ==
6337 12:11:30.792501
6338 12:11:30.792594
6339 12:11:30.795419 TX Vref Scan disable
6340 12:11:30.798997 == TX Byte 0 ==
6341 12:11:30.802035 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 12:11:30.805671 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 12:11:30.805753 == TX Byte 1 ==
6344 12:11:30.811980 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6345 12:11:30.815302 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6346 12:11:30.815385 ==
6347 12:11:30.818606 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 12:11:30.821952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 12:11:30.822028 ==
6350 12:11:30.822096
6351 12:11:30.825166
6352 12:11:30.825242 TX Vref Scan disable
6353 12:11:30.828506 == TX Byte 0 ==
6354 12:11:30.831870 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 12:11:30.835445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 12:11:30.838469 == TX Byte 1 ==
6357 12:11:30.841683 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6358 12:11:30.845204 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6359 12:11:30.845288
6360 12:11:30.845357 [DATLAT]
6361 12:11:30.848664 Freq=400, CH0 RK0
6362 12:11:30.848750
6363 12:11:30.851696 DATLAT Default: 0xf
6364 12:11:30.851782 0, 0xFFFF, sum = 0
6365 12:11:30.855178 1, 0xFFFF, sum = 0
6366 12:11:30.855266 2, 0xFFFF, sum = 0
6367 12:11:30.858261 3, 0xFFFF, sum = 0
6368 12:11:30.858349 4, 0xFFFF, sum = 0
6369 12:11:30.861677 5, 0xFFFF, sum = 0
6370 12:11:30.861765 6, 0xFFFF, sum = 0
6371 12:11:30.865431 7, 0xFFFF, sum = 0
6372 12:11:30.865519 8, 0xFFFF, sum = 0
6373 12:11:30.868527 9, 0xFFFF, sum = 0
6374 12:11:30.868614 10, 0xFFFF, sum = 0
6375 12:11:30.871656 11, 0xFFFF, sum = 0
6376 12:11:30.871746 12, 0xFFFF, sum = 0
6377 12:11:30.875219 13, 0x0, sum = 1
6378 12:11:30.875295 14, 0x0, sum = 2
6379 12:11:30.878225 15, 0x0, sum = 3
6380 12:11:30.878300 16, 0x0, sum = 4
6381 12:11:30.881463 best_step = 14
6382 12:11:30.881549
6383 12:11:30.881619 ==
6384 12:11:30.884989 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:11:30.888186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:11:30.888265 ==
6387 12:11:30.891865 RX Vref Scan: 1
6388 12:11:30.891950
6389 12:11:30.892020 RX Vref 0 -> 0, step: 1
6390 12:11:30.892084
6391 12:11:30.894789 RX Delay -327 -> 252, step: 8
6392 12:11:30.894874
6393 12:11:30.898464 Set Vref, RX VrefLevel [Byte0]: 58
6394 12:11:30.901592 [Byte1]: 50
6395 12:11:30.906388
6396 12:11:30.906478 Final RX Vref Byte 0 = 58 to rank0
6397 12:11:30.909487 Final RX Vref Byte 1 = 50 to rank0
6398 12:11:30.912483 Final RX Vref Byte 0 = 58 to rank1
6399 12:11:30.916053 Final RX Vref Byte 1 = 50 to rank1==
6400 12:11:30.919278 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 12:11:30.925694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 12:11:30.925781 ==
6403 12:11:30.925850 DQS Delay:
6404 12:11:30.929152 DQS0 = 28, DQS1 = 48
6405 12:11:30.929227 DQM Delay:
6406 12:11:30.929292 DQM0 = 12, DQM1 = 15
6407 12:11:30.932504 DQ Delay:
6408 12:11:30.935572 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6409 12:11:30.938939 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6410 12:11:30.942605 DQ8 =12, DQ9 =0, DQ10 =12, DQ11 =12
6411 12:11:30.945654 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6412 12:11:30.945728
6413 12:11:30.945793
6414 12:11:30.952271 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
6415 12:11:30.955708 CH0 RK0: MR19=C0C, MR18=B0A7
6416 12:11:30.961950 CH0_RK0: MR19=0xC0C, MR18=0xB0A7, DQSOSC=387, MR23=63, INC=394, DEC=262
6417 12:11:30.962045 ==
6418 12:11:30.965318 Dram Type= 6, Freq= 0, CH_0, rank 1
6419 12:11:30.968904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 12:11:30.968980 ==
6421 12:11:30.971919 [Gating] SW mode calibration
6422 12:11:30.978562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 12:11:30.985184 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6424 12:11:30.988328 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 12:11:30.991828 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 12:11:30.998602 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 12:11:31.001646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 12:11:31.005205 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 12:11:31.011975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 12:11:31.015148 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 12:11:31.018281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 12:11:31.024865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 12:11:31.028506 Total UI for P1: 0, mck2ui 16
6434 12:11:31.031716 best dqsien dly found for B0: ( 0, 14, 24)
6435 12:11:31.031798 Total UI for P1: 0, mck2ui 16
6436 12:11:31.038308 best dqsien dly found for B1: ( 0, 14, 24)
6437 12:11:31.041561 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6438 12:11:31.044762 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6439 12:11:31.044859
6440 12:11:31.047868 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 12:11:31.051420 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 12:11:31.054514 [Gating] SW calibration Done
6443 12:11:31.054621 ==
6444 12:11:31.057637 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 12:11:31.060987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 12:11:31.061066 ==
6447 12:11:31.064511 RX Vref Scan: 0
6448 12:11:31.064621
6449 12:11:31.067865 RX Vref 0 -> 0, step: 1
6450 12:11:31.067949
6451 12:11:31.068020 RX Delay -410 -> 252, step: 16
6452 12:11:31.074426 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6453 12:11:31.077905 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6454 12:11:31.081012 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6455 12:11:31.084602 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6456 12:11:31.091162 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6457 12:11:31.094739 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6458 12:11:31.097848 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6459 12:11:31.100966 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6460 12:11:31.107687 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6461 12:11:31.110800 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6462 12:11:31.114468 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6463 12:11:31.120619 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6464 12:11:31.124123 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6465 12:11:31.127546 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6466 12:11:31.130983 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6467 12:11:31.137519 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6468 12:11:31.137598 ==
6469 12:11:31.140788 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 12:11:31.143864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 12:11:31.143940 ==
6472 12:11:31.144007 DQS Delay:
6473 12:11:31.147086 DQS0 = 27, DQS1 = 35
6474 12:11:31.147168 DQM Delay:
6475 12:11:31.150411 DQM0 = 9, DQM1 = 7
6476 12:11:31.150488 DQ Delay:
6477 12:11:31.153865 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6478 12:11:31.157390 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6479 12:11:31.160453 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6480 12:11:31.163562 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =8
6481 12:11:31.163669
6482 12:11:31.163767
6483 12:11:31.163858 ==
6484 12:11:31.166898 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 12:11:31.170389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 12:11:31.170469 ==
6487 12:11:31.170535
6488 12:11:31.170596
6489 12:11:31.173584 TX Vref Scan disable
6490 12:11:31.173665 == TX Byte 0 ==
6491 12:11:31.180126 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6492 12:11:31.183808 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6493 12:11:31.183905 == TX Byte 1 ==
6494 12:11:31.190373 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6495 12:11:31.193422 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6496 12:11:31.193534 ==
6497 12:11:31.196994 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 12:11:31.200155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 12:11:31.200231 ==
6500 12:11:31.200294
6501 12:11:31.200371
6502 12:11:31.203691 TX Vref Scan disable
6503 12:11:31.203770 == TX Byte 0 ==
6504 12:11:31.209889 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6505 12:11:31.213488 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6506 12:11:31.213563 == TX Byte 1 ==
6507 12:11:31.220146 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6508 12:11:31.223244 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6509 12:11:31.223319
6510 12:11:31.223391 [DATLAT]
6511 12:11:31.226330 Freq=400, CH0 RK1
6512 12:11:31.226403
6513 12:11:31.226472 DATLAT Default: 0xe
6514 12:11:31.229823 0, 0xFFFF, sum = 0
6515 12:11:31.229900 1, 0xFFFF, sum = 0
6516 12:11:31.233265 2, 0xFFFF, sum = 0
6517 12:11:31.233340 3, 0xFFFF, sum = 0
6518 12:11:31.236420 4, 0xFFFF, sum = 0
6519 12:11:31.236492 5, 0xFFFF, sum = 0
6520 12:11:31.239574 6, 0xFFFF, sum = 0
6521 12:11:31.243004 7, 0xFFFF, sum = 0
6522 12:11:31.243079 8, 0xFFFF, sum = 0
6523 12:11:31.246481 9, 0xFFFF, sum = 0
6524 12:11:31.246558 10, 0xFFFF, sum = 0
6525 12:11:31.249349 11, 0xFFFF, sum = 0
6526 12:11:31.249423 12, 0xFFFF, sum = 0
6527 12:11:31.252730 13, 0x0, sum = 1
6528 12:11:31.252858 14, 0x0, sum = 2
6529 12:11:31.256279 15, 0x0, sum = 3
6530 12:11:31.256353 16, 0x0, sum = 4
6531 12:11:31.259693 best_step = 14
6532 12:11:31.259778
6533 12:11:31.259844 ==
6534 12:11:31.262680 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 12:11:31.266166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 12:11:31.266240 ==
6537 12:11:31.266305 RX Vref Scan: 0
6538 12:11:31.269165
6539 12:11:31.269235 RX Vref 0 -> 0, step: 1
6540 12:11:31.269297
6541 12:11:31.272478 RX Delay -311 -> 252, step: 8
6542 12:11:31.279899 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6543 12:11:31.283282 iDelay=217, Bit 1, Center -20 (-247 ~ 208) 456
6544 12:11:31.286428 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6545 12:11:31.293069 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6546 12:11:31.296597 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6547 12:11:31.299660 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6548 12:11:31.303317 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6549 12:11:31.306614 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6550 12:11:31.312738 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6551 12:11:31.315936 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6552 12:11:31.319538 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6553 12:11:31.326261 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6554 12:11:31.329296 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6555 12:11:31.332877 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6556 12:11:31.335877 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6557 12:11:31.342514 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6558 12:11:31.342592 ==
6559 12:11:31.346266 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 12:11:31.349218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 12:11:31.349300 ==
6562 12:11:31.349375 DQS Delay:
6563 12:11:31.352645 DQS0 = 28, DQS1 = 44
6564 12:11:31.352747 DQM Delay:
6565 12:11:31.356167 DQM0 = 9, DQM1 = 16
6566 12:11:31.356279 DQ Delay:
6567 12:11:31.359374 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6568 12:11:31.362412 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6569 12:11:31.365797 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6570 12:11:31.369184 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =28
6571 12:11:31.369277
6572 12:11:31.369344
6573 12:11:31.375532 [DQSOSCAuto] RK1, (LSB)MR18= 0xb96c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6574 12:11:31.379023 CH0 RK1: MR19=C0C, MR18=B96C
6575 12:11:31.385614 CH0_RK1: MR19=0xC0C, MR18=0xB96C, DQSOSC=386, MR23=63, INC=396, DEC=264
6576 12:11:31.388673 [RxdqsGatingPostProcess] freq 400
6577 12:11:31.395790 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6578 12:11:31.398791 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 12:11:31.398890 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 12:11:31.402347 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 12:11:31.405459 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 12:11:31.408561 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 12:11:31.412114 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 12:11:31.415360 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 12:11:31.418560 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 12:11:31.422091 Pre-setting of DQS Precalculation
6587 12:11:31.428637 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6588 12:11:31.428750 ==
6589 12:11:31.431825 Dram Type= 6, Freq= 0, CH_1, rank 0
6590 12:11:31.435378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 12:11:31.435465 ==
6592 12:11:31.441922 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6593 12:11:31.445336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6594 12:11:31.448506 [CA 0] Center 36 (8~64) winsize 57
6595 12:11:31.451646 [CA 1] Center 36 (8~64) winsize 57
6596 12:11:31.455176 [CA 2] Center 36 (8~64) winsize 57
6597 12:11:31.458119 [CA 3] Center 36 (8~64) winsize 57
6598 12:11:31.461630 [CA 4] Center 36 (8~64) winsize 57
6599 12:11:31.464948 [CA 5] Center 36 (8~64) winsize 57
6600 12:11:31.465034
6601 12:11:31.468306 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6602 12:11:31.468422
6603 12:11:31.471239 [CATrainingPosCal] consider 1 rank data
6604 12:11:31.474447 u2DelayCellTimex100 = 270/100 ps
6605 12:11:31.478041 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:11:31.484463 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 12:11:31.488052 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 12:11:31.491223 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 12:11:31.494826 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 12:11:31.497901 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 12:11:31.498014
6612 12:11:31.501040 CA PerBit enable=1, Macro0, CA PI delay=36
6613 12:11:31.501153
6614 12:11:31.504547 [CBTSetCACLKResult] CA Dly = 36
6615 12:11:31.504654 CS Dly: 1 (0~32)
6616 12:11:31.507656 ==
6617 12:11:31.511311 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 12:11:31.514381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 12:11:31.514488 ==
6620 12:11:31.520993 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 12:11:31.524586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6622 12:11:31.527651 [CA 0] Center 36 (8~64) winsize 57
6623 12:11:31.530854 [CA 1] Center 36 (8~64) winsize 57
6624 12:11:31.534332 [CA 2] Center 36 (8~64) winsize 57
6625 12:11:31.537405 [CA 3] Center 36 (8~64) winsize 57
6626 12:11:31.541066 [CA 4] Center 36 (8~64) winsize 57
6627 12:11:31.544138 [CA 5] Center 36 (8~64) winsize 57
6628 12:11:31.544260
6629 12:11:31.547595 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6630 12:11:31.547713
6631 12:11:31.550763 [CATrainingPosCal] consider 2 rank data
6632 12:11:31.554331 u2DelayCellTimex100 = 270/100 ps
6633 12:11:31.557341 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:11:31.560440 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:11:31.563794 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:11:31.570710 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:11:31.573680 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:11:31.576980 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:11:31.577067
6640 12:11:31.580365 CA PerBit enable=1, Macro0, CA PI delay=36
6641 12:11:31.580450
6642 12:11:31.583693 [CBTSetCACLKResult] CA Dly = 36
6643 12:11:31.583779 CS Dly: 1 (0~32)
6644 12:11:31.583851
6645 12:11:31.587139 ----->DramcWriteLeveling(PI) begin...
6646 12:11:31.589956 ==
6647 12:11:31.593611 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 12:11:31.596706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 12:11:31.596799 ==
6650 12:11:31.600494 Write leveling (Byte 0): 40 => 8
6651 12:11:31.603675 Write leveling (Byte 1): 32 => 0
6652 12:11:31.603765 DramcWriteLeveling(PI) end<-----
6653 12:11:31.606629
6654 12:11:31.606720 ==
6655 12:11:31.610084 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 12:11:31.613724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 12:11:31.613802 ==
6658 12:11:31.616704 [Gating] SW mode calibration
6659 12:11:31.623672 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6660 12:11:31.626763 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6661 12:11:31.633416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 12:11:31.636493 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 12:11:31.643041 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 12:11:31.646169 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 12:11:31.649746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 12:11:31.656361 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 12:11:31.659423 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 12:11:31.662508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 12:11:31.669537 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 12:11:31.669623 Total UI for P1: 0, mck2ui 16
6671 12:11:31.672776 best dqsien dly found for B0: ( 0, 14, 24)
6672 12:11:31.676155 Total UI for P1: 0, mck2ui 16
6673 12:11:31.679606 best dqsien dly found for B1: ( 0, 14, 24)
6674 12:11:31.685967 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6675 12:11:31.689237 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6676 12:11:31.689322
6677 12:11:31.692681 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 12:11:31.695601 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 12:11:31.699168 [Gating] SW calibration Done
6680 12:11:31.699286 ==
6681 12:11:31.702720 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 12:11:31.705805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 12:11:31.705892 ==
6684 12:11:31.709412 RX Vref Scan: 0
6685 12:11:31.709498
6686 12:11:31.709566 RX Vref 0 -> 0, step: 1
6687 12:11:31.709630
6688 12:11:31.712282 RX Delay -410 -> 252, step: 16
6689 12:11:31.719358 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6690 12:11:31.722381 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6691 12:11:31.725939 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6692 12:11:31.729170 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6693 12:11:31.732223 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6694 12:11:31.739048 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6695 12:11:31.742426 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6696 12:11:31.745714 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6697 12:11:31.749075 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6698 12:11:31.755651 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6699 12:11:31.759149 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6700 12:11:31.762278 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6701 12:11:31.768583 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6702 12:11:31.772140 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6703 12:11:31.775650 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6704 12:11:31.778572 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6705 12:11:31.778658 ==
6706 12:11:31.781985 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 12:11:31.788919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 12:11:31.789008 ==
6709 12:11:31.789081 DQS Delay:
6710 12:11:31.792102 DQS0 = 19, DQS1 = 43
6711 12:11:31.792213 DQM Delay:
6712 12:11:31.795447 DQM0 = 4, DQM1 = 20
6713 12:11:31.795533 DQ Delay:
6714 12:11:31.798718 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6715 12:11:31.801981 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6716 12:11:31.802062 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6717 12:11:31.808412 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6718 12:11:31.808488
6719 12:11:31.808555
6720 12:11:31.808628 ==
6721 12:11:31.811905 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 12:11:31.814961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 12:11:31.815035 ==
6724 12:11:31.815099
6725 12:11:31.815172
6726 12:11:31.818244 TX Vref Scan disable
6727 12:11:31.818331 == TX Byte 0 ==
6728 12:11:31.821854 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 12:11:31.828656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 12:11:31.828773 == TX Byte 1 ==
6731 12:11:31.831866 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6732 12:11:31.838235 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6733 12:11:31.838317 ==
6734 12:11:31.841283 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 12:11:31.844966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 12:11:31.845045 ==
6737 12:11:31.845111
6738 12:11:31.845173
6739 12:11:31.848092 TX Vref Scan disable
6740 12:11:31.848174 == TX Byte 0 ==
6741 12:11:31.854777 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 12:11:31.857887 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 12:11:31.857968 == TX Byte 1 ==
6744 12:11:31.864441 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6745 12:11:31.867956 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6746 12:11:31.868030
6747 12:11:31.868109 [DATLAT]
6748 12:11:31.871077 Freq=400, CH1 RK0
6749 12:11:31.871150
6750 12:11:31.871219 DATLAT Default: 0xf
6751 12:11:31.874626 0, 0xFFFF, sum = 0
6752 12:11:31.874701 1, 0xFFFF, sum = 0
6753 12:11:31.877699 2, 0xFFFF, sum = 0
6754 12:11:31.877778 3, 0xFFFF, sum = 0
6755 12:11:31.880825 4, 0xFFFF, sum = 0
6756 12:11:31.880905 5, 0xFFFF, sum = 0
6757 12:11:31.884382 6, 0xFFFF, sum = 0
6758 12:11:31.887760 7, 0xFFFF, sum = 0
6759 12:11:31.887841 8, 0xFFFF, sum = 0
6760 12:11:31.891102 9, 0xFFFF, sum = 0
6761 12:11:31.891177 10, 0xFFFF, sum = 0
6762 12:11:31.894353 11, 0xFFFF, sum = 0
6763 12:11:31.894429 12, 0xFFFF, sum = 0
6764 12:11:31.897564 13, 0x0, sum = 1
6765 12:11:31.897651 14, 0x0, sum = 2
6766 12:11:31.900826 15, 0x0, sum = 3
6767 12:11:31.900913 16, 0x0, sum = 4
6768 12:11:31.904093 best_step = 14
6769 12:11:31.904177
6770 12:11:31.904245 ==
6771 12:11:31.907508 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:11:31.910794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:11:31.910879 ==
6774 12:11:31.910947 RX Vref Scan: 1
6775 12:11:31.911011
6776 12:11:31.913912 RX Vref 0 -> 0, step: 1
6777 12:11:31.913994
6778 12:11:31.917569 RX Delay -327 -> 252, step: 8
6779 12:11:31.917672
6780 12:11:31.920555 Set Vref, RX VrefLevel [Byte0]: 53
6781 12:11:31.924026 [Byte1]: 55
6782 12:11:31.928079
6783 12:11:31.928162 Final RX Vref Byte 0 = 53 to rank0
6784 12:11:31.931150 Final RX Vref Byte 1 = 55 to rank0
6785 12:11:31.934756 Final RX Vref Byte 0 = 53 to rank1
6786 12:11:31.937829 Final RX Vref Byte 1 = 55 to rank1==
6787 12:11:31.941335 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 12:11:31.947481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 12:11:31.947564 ==
6790 12:11:31.947630 DQS Delay:
6791 12:11:31.951148 DQS0 = 28, DQS1 = 40
6792 12:11:31.951230 DQM Delay:
6793 12:11:31.951296 DQM0 = 7, DQM1 = 12
6794 12:11:31.954148 DQ Delay:
6795 12:11:31.957755 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6796 12:11:31.960871 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6797 12:11:31.960954 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6798 12:11:31.964375 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6799 12:11:31.967567
6800 12:11:31.967649
6801 12:11:31.974357 [DQSOSCAuto] RK0, (LSB)MR18= 0x99d2, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6802 12:11:31.977444 CH1 RK0: MR19=C0C, MR18=99D2
6803 12:11:31.983800 CH1_RK0: MR19=0xC0C, MR18=0x99D2, DQSOSC=383, MR23=63, INC=402, DEC=268
6804 12:11:31.983883 ==
6805 12:11:31.987557 Dram Type= 6, Freq= 0, CH_1, rank 1
6806 12:11:31.990738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 12:11:31.990822 ==
6808 12:11:31.993752 [Gating] SW mode calibration
6809 12:11:32.000429 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6810 12:11:32.007013 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6811 12:11:32.010267 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 12:11:32.013669 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 12:11:32.020248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 12:11:32.023747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 12:11:32.026703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 12:11:32.033596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 12:11:32.036634 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 12:11:32.040129 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 12:11:32.046800 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 12:11:32.046885 Total UI for P1: 0, mck2ui 16
6821 12:11:32.053358 best dqsien dly found for B0: ( 0, 14, 24)
6822 12:11:32.053441 Total UI for P1: 0, mck2ui 16
6823 12:11:32.060150 best dqsien dly found for B1: ( 0, 14, 24)
6824 12:11:32.063268 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6825 12:11:32.066387 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6826 12:11:32.066470
6827 12:11:32.069847 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 12:11:32.072947 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 12:11:32.076543 [Gating] SW calibration Done
6830 12:11:32.076625 ==
6831 12:11:32.079607 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 12:11:32.083122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 12:11:32.083205 ==
6834 12:11:32.086408 RX Vref Scan: 0
6835 12:11:32.086491
6836 12:11:32.086557 RX Vref 0 -> 0, step: 1
6837 12:11:32.086641
6838 12:11:32.089854 RX Delay -410 -> 252, step: 16
6839 12:11:32.096324 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6840 12:11:32.099372 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6841 12:11:32.102821 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6842 12:11:32.106202 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6843 12:11:32.112745 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6844 12:11:32.116078 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6845 12:11:32.119340 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6846 12:11:32.122713 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6847 12:11:32.129038 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6848 12:11:32.132820 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6849 12:11:32.135892 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6850 12:11:32.139038 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6851 12:11:32.146029 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6852 12:11:32.149157 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6853 12:11:32.152211 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6854 12:11:32.159184 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6855 12:11:32.159294 ==
6856 12:11:32.162225 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 12:11:32.165379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 12:11:32.165462 ==
6859 12:11:32.165530 DQS Delay:
6860 12:11:32.169013 DQS0 = 35, DQS1 = 43
6861 12:11:32.169096 DQM Delay:
6862 12:11:32.172097 DQM0 = 20, DQM1 = 19
6863 12:11:32.172180 DQ Delay:
6864 12:11:32.175704 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6865 12:11:32.178792 DQ4 =24, DQ5 =32, DQ6 =32, DQ7 =16
6866 12:11:32.181951 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6867 12:11:32.185465 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =40
6868 12:11:32.185549
6869 12:11:32.185617
6870 12:11:32.185679 ==
6871 12:11:32.188562 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 12:11:32.192151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 12:11:32.192234 ==
6874 12:11:32.192301
6875 12:11:32.195262
6876 12:11:32.195355 TX Vref Scan disable
6877 12:11:32.198795 == TX Byte 0 ==
6878 12:11:32.201981 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6879 12:11:32.205038 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6880 12:11:32.208608 == TX Byte 1 ==
6881 12:11:32.211750 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6882 12:11:32.215123 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6883 12:11:32.215207 ==
6884 12:11:32.218744 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 12:11:32.221802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 12:11:32.221903 ==
6887 12:11:32.225087
6888 12:11:32.225187
6889 12:11:32.225287 TX Vref Scan disable
6890 12:11:32.228437 == TX Byte 0 ==
6891 12:11:32.231729 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6892 12:11:32.235061 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6893 12:11:32.238020 == TX Byte 1 ==
6894 12:11:32.241476 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6895 12:11:32.244972 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6896 12:11:32.245058
6897 12:11:32.245126 [DATLAT]
6898 12:11:32.248137 Freq=400, CH1 RK1
6899 12:11:32.248223
6900 12:11:32.251705 DATLAT Default: 0xe
6901 12:11:32.251791 0, 0xFFFF, sum = 0
6902 12:11:32.254802 1, 0xFFFF, sum = 0
6903 12:11:32.254889 2, 0xFFFF, sum = 0
6904 12:11:32.257914 3, 0xFFFF, sum = 0
6905 12:11:32.258002 4, 0xFFFF, sum = 0
6906 12:11:32.261490 5, 0xFFFF, sum = 0
6907 12:11:32.261576 6, 0xFFFF, sum = 0
6908 12:11:32.264530 7, 0xFFFF, sum = 0
6909 12:11:32.264643 8, 0xFFFF, sum = 0
6910 12:11:32.268124 9, 0xFFFF, sum = 0
6911 12:11:32.268210 10, 0xFFFF, sum = 0
6912 12:11:32.271316 11, 0xFFFF, sum = 0
6913 12:11:32.271392 12, 0xFFFF, sum = 0
6914 12:11:32.274469 13, 0x0, sum = 1
6915 12:11:32.274588 14, 0x0, sum = 2
6916 12:11:32.277820 15, 0x0, sum = 3
6917 12:11:32.277905 16, 0x0, sum = 4
6918 12:11:32.281426 best_step = 14
6919 12:11:32.281511
6920 12:11:32.281579 ==
6921 12:11:32.284468 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 12:11:32.288051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 12:11:32.288136 ==
6924 12:11:32.291143 RX Vref Scan: 0
6925 12:11:32.291231
6926 12:11:32.291310 RX Vref 0 -> 0, step: 1
6927 12:11:32.291375
6928 12:11:32.294108 RX Delay -327 -> 252, step: 8
6929 12:11:32.302232 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6930 12:11:32.305281 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6931 12:11:32.308933 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6932 12:11:32.315500 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6933 12:11:32.318477 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6934 12:11:32.322068 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6935 12:11:32.325196 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6936 12:11:32.331681 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6937 12:11:32.335027 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6938 12:11:32.338278 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6939 12:11:32.341802 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6940 12:11:32.348203 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6941 12:11:32.351827 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6942 12:11:32.354860 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6943 12:11:32.357973 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6944 12:11:32.364671 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6945 12:11:32.364802 ==
6946 12:11:32.368214 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 12:11:32.371464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 12:11:32.371549 ==
6949 12:11:32.371618 DQS Delay:
6950 12:11:32.374814 DQS0 = 32, DQS1 = 36
6951 12:11:32.374907 DQM Delay:
6952 12:11:32.377882 DQM0 = 13, DQM1 = 10
6953 12:11:32.377975 DQ Delay:
6954 12:11:32.381469 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6955 12:11:32.384624 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =8
6956 12:11:32.387664 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6957 12:11:32.391215 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6958 12:11:32.391294
6959 12:11:32.391379
6960 12:11:32.397766 [DQSOSCAuto] RK1, (LSB)MR18= 0xad56, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
6961 12:11:32.401434 CH1 RK1: MR19=C0C, MR18=AD56
6962 12:11:32.408118 CH1_RK1: MR19=0xC0C, MR18=0xAD56, DQSOSC=388, MR23=63, INC=392, DEC=261
6963 12:11:32.411112 [RxdqsGatingPostProcess] freq 400
6964 12:11:32.417751 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6965 12:11:32.420831 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 12:11:32.424062 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 12:11:32.427685 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 12:11:32.430743 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 12:11:32.434352 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 12:11:32.434435 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 12:11:32.437489 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 12:11:32.440953 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 12:11:32.444187 Pre-setting of DQS Precalculation
6974 12:11:32.450415 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6975 12:11:32.457227 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6976 12:11:32.463598 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6977 12:11:32.463716
6978 12:11:32.463839
6979 12:11:32.467297 [Calibration Summary] 800 Mbps
6980 12:11:32.470375 CH 0, Rank 0
6981 12:11:32.470522 SW Impedance : PASS
6982 12:11:32.473453 DUTY Scan : NO K
6983 12:11:32.473558 ZQ Calibration : PASS
6984 12:11:32.477134 Jitter Meter : NO K
6985 12:11:32.480195 CBT Training : PASS
6986 12:11:32.480298 Write leveling : PASS
6987 12:11:32.483698 RX DQS gating : PASS
6988 12:11:32.486776 RX DQ/DQS(RDDQC) : PASS
6989 12:11:32.486910 TX DQ/DQS : PASS
6990 12:11:32.490492 RX DATLAT : PASS
6991 12:11:32.493564 RX DQ/DQS(Engine): PASS
6992 12:11:32.493707 TX OE : NO K
6993 12:11:32.497077 All Pass.
6994 12:11:32.497219
6995 12:11:32.497355 CH 0, Rank 1
6996 12:11:32.500135 SW Impedance : PASS
6997 12:11:32.500265 DUTY Scan : NO K
6998 12:11:32.503901 ZQ Calibration : PASS
6999 12:11:32.506866 Jitter Meter : NO K
7000 12:11:32.507008 CBT Training : PASS
7001 12:11:32.510057 Write leveling : NO K
7002 12:11:32.513578 RX DQS gating : PASS
7003 12:11:32.513712 RX DQ/DQS(RDDQC) : PASS
7004 12:11:32.516655 TX DQ/DQS : PASS
7005 12:11:32.520295 RX DATLAT : PASS
7006 12:11:32.520379 RX DQ/DQS(Engine): PASS
7007 12:11:32.523380 TX OE : NO K
7008 12:11:32.523465 All Pass.
7009 12:11:32.523534
7010 12:11:32.526531 CH 1, Rank 0
7011 12:11:32.526639 SW Impedance : PASS
7012 12:11:32.530029 DUTY Scan : NO K
7013 12:11:32.533189 ZQ Calibration : PASS
7014 12:11:32.533308 Jitter Meter : NO K
7015 12:11:32.536636 CBT Training : PASS
7016 12:11:32.536756 Write leveling : PASS
7017 12:11:32.540111 RX DQS gating : PASS
7018 12:11:32.543227 RX DQ/DQS(RDDQC) : PASS
7019 12:11:32.543344 TX DQ/DQS : PASS
7020 12:11:32.546401 RX DATLAT : PASS
7021 12:11:32.549760 RX DQ/DQS(Engine): PASS
7022 12:11:32.549861 TX OE : NO K
7023 12:11:32.553040 All Pass.
7024 12:11:32.553144
7025 12:11:32.553243 CH 1, Rank 1
7026 12:11:32.556437 SW Impedance : PASS
7027 12:11:32.556515 DUTY Scan : NO K
7028 12:11:32.559822 ZQ Calibration : PASS
7029 12:11:32.563135 Jitter Meter : NO K
7030 12:11:32.563214 CBT Training : PASS
7031 12:11:32.566365 Write leveling : NO K
7032 12:11:32.569396 RX DQS gating : PASS
7033 12:11:32.569474 RX DQ/DQS(RDDQC) : PASS
7034 12:11:32.572576 TX DQ/DQS : PASS
7035 12:11:32.576151 RX DATLAT : PASS
7036 12:11:32.576236 RX DQ/DQS(Engine): PASS
7037 12:11:32.579697 TX OE : NO K
7038 12:11:32.579782 All Pass.
7039 12:11:32.579851
7040 12:11:32.582880 DramC Write-DBI off
7041 12:11:32.586037 PER_BANK_REFRESH: Hybrid Mode
7042 12:11:32.586123 TX_TRACKING: ON
7043 12:11:32.596024 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7044 12:11:32.599556 [FAST_K] Save calibration result to emmc
7045 12:11:32.602650 dramc_set_vcore_voltage set vcore to 725000
7046 12:11:32.606219 Read voltage for 1600, 0
7047 12:11:32.606304 Vio18 = 0
7048 12:11:32.606373 Vcore = 725000
7049 12:11:32.609122 Vdram = 0
7050 12:11:32.609206 Vddq = 0
7051 12:11:32.609273 Vmddr = 0
7052 12:11:32.615847 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7053 12:11:32.619362 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7054 12:11:32.622409 MEM_TYPE=3, freq_sel=13
7055 12:11:32.625876 sv_algorithm_assistance_LP4_3733
7056 12:11:32.628892 ============ PULL DRAM RESETB DOWN ============
7057 12:11:32.632547 ========== PULL DRAM RESETB DOWN end =========
7058 12:11:32.638679 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7059 12:11:32.642092 ===================================
7060 12:11:32.645557 LPDDR4 DRAM CONFIGURATION
7061 12:11:32.648695 ===================================
7062 12:11:32.648805 EX_ROW_EN[0] = 0x0
7063 12:11:32.652440 EX_ROW_EN[1] = 0x0
7064 12:11:32.652562 LP4Y_EN = 0x0
7065 12:11:32.655438 WORK_FSP = 0x1
7066 12:11:32.655522 WL = 0x5
7067 12:11:32.658735 RL = 0x5
7068 12:11:32.658820 BL = 0x2
7069 12:11:32.662197 RPST = 0x0
7070 12:11:32.662282 RD_PRE = 0x0
7071 12:11:32.665113 WR_PRE = 0x1
7072 12:11:32.665202 WR_PST = 0x1
7073 12:11:32.668568 DBI_WR = 0x0
7074 12:11:32.671821 DBI_RD = 0x0
7075 12:11:32.671913 OTF = 0x1
7076 12:11:32.675054 ===================================
7077 12:11:32.678745 ===================================
7078 12:11:32.678830 ANA top config
7079 12:11:32.681829 ===================================
7080 12:11:32.685355 DLL_ASYNC_EN = 0
7081 12:11:32.688428 ALL_SLAVE_EN = 0
7082 12:11:32.691841 NEW_RANK_MODE = 1
7083 12:11:32.695156 DLL_IDLE_MODE = 1
7084 12:11:32.695241 LP45_APHY_COMB_EN = 1
7085 12:11:32.698339 TX_ODT_DIS = 0
7086 12:11:32.701805 NEW_8X_MODE = 1
7087 12:11:32.705323 ===================================
7088 12:11:32.708516 ===================================
7089 12:11:32.711574 data_rate = 3200
7090 12:11:32.715089 CKR = 1
7091 12:11:32.715166 DQ_P2S_RATIO = 8
7092 12:11:32.718067 ===================================
7093 12:11:32.721627 CA_P2S_RATIO = 8
7094 12:11:32.724716 DQ_CA_OPEN = 0
7095 12:11:32.728340 DQ_SEMI_OPEN = 0
7096 12:11:32.731491 CA_SEMI_OPEN = 0
7097 12:11:32.734596 CA_FULL_RATE = 0
7098 12:11:32.734674 DQ_CKDIV4_EN = 0
7099 12:11:32.738287 CA_CKDIV4_EN = 0
7100 12:11:32.741355 CA_PREDIV_EN = 0
7101 12:11:32.744994 PH8_DLY = 12
7102 12:11:32.747912 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7103 12:11:32.751657 DQ_AAMCK_DIV = 4
7104 12:11:32.751766 CA_AAMCK_DIV = 4
7105 12:11:32.754630 CA_ADMCK_DIV = 4
7106 12:11:32.758303 DQ_TRACK_CA_EN = 0
7107 12:11:32.761162 CA_PICK = 1600
7108 12:11:32.764599 CA_MCKIO = 1600
7109 12:11:32.768159 MCKIO_SEMI = 0
7110 12:11:32.771565 PLL_FREQ = 3068
7111 12:11:32.774630 DQ_UI_PI_RATIO = 32
7112 12:11:32.774715 CA_UI_PI_RATIO = 0
7113 12:11:32.778054 ===================================
7114 12:11:32.781403 ===================================
7115 12:11:32.784504 memory_type:LPDDR4
7116 12:11:32.788042 GP_NUM : 10
7117 12:11:32.788132 SRAM_EN : 1
7118 12:11:32.791121 MD32_EN : 0
7119 12:11:32.794292 ===================================
7120 12:11:32.797652 [ANA_INIT] >>>>>>>>>>>>>>
7121 12:11:32.801023 <<<<<< [CONFIGURE PHASE]: ANA_TX
7122 12:11:32.804671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7123 12:11:32.807728 ===================================
7124 12:11:32.807812 data_rate = 3200,PCW = 0X7600
7125 12:11:32.811279 ===================================
7126 12:11:32.814486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7127 12:11:32.821230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 12:11:32.827418 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 12:11:32.830974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7130 12:11:32.834178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7131 12:11:32.837734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7132 12:11:32.840906 [ANA_INIT] flow start
7133 12:11:32.841007 [ANA_INIT] PLL >>>>>>>>
7134 12:11:32.844023 [ANA_INIT] PLL <<<<<<<<
7135 12:11:32.847723 [ANA_INIT] MIDPI >>>>>>>>
7136 12:11:32.850733 [ANA_INIT] MIDPI <<<<<<<<
7137 12:11:32.850834 [ANA_INIT] DLL >>>>>>>>
7138 12:11:32.854337 [ANA_INIT] DLL <<<<<<<<
7139 12:11:32.857415 [ANA_INIT] flow end
7140 12:11:32.860491 ============ LP4 DIFF to SE enter ============
7141 12:11:32.864057 ============ LP4 DIFF to SE exit ============
7142 12:11:32.867126 [ANA_INIT] <<<<<<<<<<<<<
7143 12:11:32.870569 [Flow] Enable top DCM control >>>>>
7144 12:11:32.873592 [Flow] Enable top DCM control <<<<<
7145 12:11:32.877105 Enable DLL master slave shuffle
7146 12:11:32.880637 ==============================================================
7147 12:11:32.883532 Gating Mode config
7148 12:11:32.890153 ==============================================================
7149 12:11:32.890270 Config description:
7150 12:11:32.900319 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7151 12:11:32.906721 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7152 12:11:32.909826 SELPH_MODE 0: By rank 1: By Phase
7153 12:11:32.916577 ==============================================================
7154 12:11:32.920148 GAT_TRACK_EN = 1
7155 12:11:32.923322 RX_GATING_MODE = 2
7156 12:11:32.926759 RX_GATING_TRACK_MODE = 2
7157 12:11:32.929879 SELPH_MODE = 1
7158 12:11:32.933561 PICG_EARLY_EN = 1
7159 12:11:32.936664 VALID_LAT_VALUE = 1
7160 12:11:32.939742 ==============================================================
7161 12:11:32.943229 Enter into Gating configuration >>>>
7162 12:11:32.946445 Exit from Gating configuration <<<<
7163 12:11:32.949947 Enter into DVFS_PRE_config >>>>>
7164 12:11:32.963172 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7165 12:11:32.966233 Exit from DVFS_PRE_config <<<<<
7166 12:11:32.966343 Enter into PICG configuration >>>>
7167 12:11:32.969783 Exit from PICG configuration <<<<
7168 12:11:32.973049 [RX_INPUT] configuration >>>>>
7169 12:11:32.976162 [RX_INPUT] configuration <<<<<
7170 12:11:32.983142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7171 12:11:32.986516 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7172 12:11:32.992748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 12:11:32.999437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 12:11:33.005963 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 12:11:33.012552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 12:11:33.016107 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7177 12:11:33.019168 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7178 12:11:33.022758 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7179 12:11:33.029508 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7180 12:11:33.032593 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7181 12:11:33.036118 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 12:11:33.039358 ===================================
7183 12:11:33.042914 LPDDR4 DRAM CONFIGURATION
7184 12:11:33.045906 ===================================
7185 12:11:33.049050 EX_ROW_EN[0] = 0x0
7186 12:11:33.049129 EX_ROW_EN[1] = 0x0
7187 12:11:33.052662 LP4Y_EN = 0x0
7188 12:11:33.052783 WORK_FSP = 0x1
7189 12:11:33.055803 WL = 0x5
7190 12:11:33.055904 RL = 0x5
7191 12:11:33.058888 BL = 0x2
7192 12:11:33.058989 RPST = 0x0
7193 12:11:33.062562 RD_PRE = 0x0
7194 12:11:33.062667 WR_PRE = 0x1
7195 12:11:33.065636 WR_PST = 0x1
7196 12:11:33.065735 DBI_WR = 0x0
7197 12:11:33.069184 DBI_RD = 0x0
7198 12:11:33.069285 OTF = 0x1
7199 12:11:33.072207 ===================================
7200 12:11:33.079025 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7201 12:11:33.082140 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7202 12:11:33.085722 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 12:11:33.089133 ===================================
7204 12:11:33.092129 LPDDR4 DRAM CONFIGURATION
7205 12:11:33.095424 ===================================
7206 12:11:33.098902 EX_ROW_EN[0] = 0x10
7207 12:11:33.099008 EX_ROW_EN[1] = 0x0
7208 12:11:33.102022 LP4Y_EN = 0x0
7209 12:11:33.102097 WORK_FSP = 0x1
7210 12:11:33.105547 WL = 0x5
7211 12:11:33.105652 RL = 0x5
7212 12:11:33.108553 BL = 0x2
7213 12:11:33.108656 RPST = 0x0
7214 12:11:33.111920 RD_PRE = 0x0
7215 12:11:33.112002 WR_PRE = 0x1
7216 12:11:33.115336 WR_PST = 0x1
7217 12:11:33.115454 DBI_WR = 0x0
7218 12:11:33.118303 DBI_RD = 0x0
7219 12:11:33.118419 OTF = 0x1
7220 12:11:33.121851 ===================================
7221 12:11:33.128449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7222 12:11:33.128557 ==
7223 12:11:33.131552 Dram Type= 6, Freq= 0, CH_0, rank 0
7224 12:11:33.138197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7225 12:11:33.138308 ==
7226 12:11:33.138411 [Duty_Offset_Calibration]
7227 12:11:33.141786 B0:2 B1:0 CA:1
7228 12:11:33.141894
7229 12:11:33.144995 [DutyScan_Calibration_Flow] k_type=0
7230 12:11:33.153841
7231 12:11:33.153954 ==CLK 0==
7232 12:11:33.156889 Final CLK duty delay cell = -4
7233 12:11:33.160091 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7234 12:11:33.163490 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7235 12:11:33.166631 [-4] AVG Duty = 4906%(X100)
7236 12:11:33.166732
7237 12:11:33.170261 CH0 CLK Duty spec in!! Max-Min= 187%
7238 12:11:33.173373 [DutyScan_Calibration_Flow] ====Done====
7239 12:11:33.173448
7240 12:11:33.176514 [DutyScan_Calibration_Flow] k_type=1
7241 12:11:33.192918
7242 12:11:33.193002 ==DQS 0 ==
7243 12:11:33.196280 Final DQS duty delay cell = 0
7244 12:11:33.199787 [0] MAX Duty = 5249%(X100), DQS PI = 32
7245 12:11:33.202998 [0] MIN Duty = 4969%(X100), DQS PI = 0
7246 12:11:33.206517 [0] AVG Duty = 5109%(X100)
7247 12:11:33.206625
7248 12:11:33.206720 ==DQS 1 ==
7249 12:11:33.209321 Final DQS duty delay cell = -4
7250 12:11:33.212944 [-4] MAX Duty = 5156%(X100), DQS PI = 46
7251 12:11:33.215954 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7252 12:11:33.219334 [-4] AVG Duty = 5015%(X100)
7253 12:11:33.219450
7254 12:11:33.222866 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7255 12:11:33.222976
7256 12:11:33.225959 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7257 12:11:33.229100 [DutyScan_Calibration_Flow] ====Done====
7258 12:11:33.229184
7259 12:11:33.232578 [DutyScan_Calibration_Flow] k_type=3
7260 12:11:33.249526
7261 12:11:33.249636 ==DQM 0 ==
7262 12:11:33.253015 Final DQM duty delay cell = 0
7263 12:11:33.256064 [0] MAX Duty = 5093%(X100), DQS PI = 26
7264 12:11:33.259695 [0] MIN Duty = 4813%(X100), DQS PI = 50
7265 12:11:33.262915 [0] AVG Duty = 4953%(X100)
7266 12:11:33.263021
7267 12:11:33.263113 ==DQM 1 ==
7268 12:11:33.266291 Final DQM duty delay cell = -4
7269 12:11:33.269460 [-4] MAX Duty = 5031%(X100), DQS PI = 44
7270 12:11:33.272656 [-4] MIN Duty = 4751%(X100), DQS PI = 18
7271 12:11:33.276141 [-4] AVG Duty = 4891%(X100)
7272 12:11:33.276216
7273 12:11:33.279210 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7274 12:11:33.279283
7275 12:11:33.282953 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7276 12:11:33.285837 [DutyScan_Calibration_Flow] ====Done====
7277 12:11:33.285909
7278 12:11:33.289549 [DutyScan_Calibration_Flow] k_type=2
7279 12:11:33.307099
7280 12:11:33.307233 ==DQ 0 ==
7281 12:11:33.310461 Final DQ duty delay cell = 0
7282 12:11:33.313801 [0] MAX Duty = 5156%(X100), DQS PI = 38
7283 12:11:33.316985 [0] MIN Duty = 5000%(X100), DQS PI = 0
7284 12:11:33.317168 [0] AVG Duty = 5078%(X100)
7285 12:11:33.320216
7286 12:11:33.320380 ==DQ 1 ==
7287 12:11:33.323742 Final DQ duty delay cell = 0
7288 12:11:33.327309 [0] MAX Duty = 4969%(X100), DQS PI = 50
7289 12:11:33.330289 [0] MIN Duty = 4875%(X100), DQS PI = 10
7290 12:11:33.330465 [0] AVG Duty = 4922%(X100)
7291 12:11:33.334070
7292 12:11:33.337164 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7293 12:11:33.337402
7294 12:11:33.340124 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7295 12:11:33.343920 [DutyScan_Calibration_Flow] ====Done====
7296 12:11:33.344001 ==
7297 12:11:33.347145 Dram Type= 6, Freq= 0, CH_1, rank 0
7298 12:11:33.350336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 12:11:33.350504 ==
7300 12:11:33.353702 [Duty_Offset_Calibration]
7301 12:11:33.353868 B0:0 B1:-1 CA:2
7302 12:11:33.353944
7303 12:11:33.356918 [DutyScan_Calibration_Flow] k_type=0
7304 12:11:33.367504
7305 12:11:33.367703 ==CLK 0==
7306 12:11:33.370709 Final CLK duty delay cell = 0
7307 12:11:33.373859 [0] MAX Duty = 5187%(X100), DQS PI = 14
7308 12:11:33.377430 [0] MIN Duty = 4938%(X100), DQS PI = 46
7309 12:11:33.377525 [0] AVG Duty = 5062%(X100)
7310 12:11:33.380506
7311 12:11:33.383606 CH1 CLK Duty spec in!! Max-Min= 249%
7312 12:11:33.387429 [DutyScan_Calibration_Flow] ====Done====
7313 12:11:33.387536
7314 12:11:33.390129 [DutyScan_Calibration_Flow] k_type=1
7315 12:11:33.407176
7316 12:11:33.407291 ==DQS 0 ==
7317 12:11:33.410229 Final DQS duty delay cell = 0
7318 12:11:33.413957 [0] MAX Duty = 5124%(X100), DQS PI = 26
7319 12:11:33.417493 [0] MIN Duty = 4969%(X100), DQS PI = 0
7320 12:11:33.420313 [0] AVG Duty = 5046%(X100)
7321 12:11:33.421093
7322 12:11:33.421750 ==DQS 1 ==
7323 12:11:33.423658 Final DQS duty delay cell = 0
7324 12:11:33.426884 [0] MAX Duty = 5187%(X100), DQS PI = 0
7325 12:11:33.430487 [0] MIN Duty = 4844%(X100), DQS PI = 34
7326 12:11:33.433423 [0] AVG Duty = 5015%(X100)
7327 12:11:33.434025
7328 12:11:33.436838 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7329 12:11:33.437513
7330 12:11:33.440336 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7331 12:11:33.443604 [DutyScan_Calibration_Flow] ====Done====
7332 12:11:33.444230
7333 12:11:33.446726 [DutyScan_Calibration_Flow] k_type=3
7334 12:11:33.464992
7335 12:11:33.465571 ==DQM 0 ==
7336 12:11:33.468675 Final DQM duty delay cell = 4
7337 12:11:33.471741 [4] MAX Duty = 5156%(X100), DQS PI = 24
7338 12:11:33.475209 [4] MIN Duty = 5000%(X100), DQS PI = 30
7339 12:11:33.475769 [4] AVG Duty = 5078%(X100)
7340 12:11:33.478216
7341 12:11:33.478800 ==DQM 1 ==
7342 12:11:33.481795 Final DQM duty delay cell = 0
7343 12:11:33.484873 [0] MAX Duty = 5281%(X100), DQS PI = 58
7344 12:11:33.488374 [0] MIN Duty = 4907%(X100), DQS PI = 34
7345 12:11:33.491471 [0] AVG Duty = 5094%(X100)
7346 12:11:33.492016
7347 12:11:33.494968 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7348 12:11:33.495551
7349 12:11:33.498507 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7350 12:11:33.501554 [DutyScan_Calibration_Flow] ====Done====
7351 12:11:33.502148
7352 12:11:33.505040 [DutyScan_Calibration_Flow] k_type=2
7353 12:11:33.522111
7354 12:11:33.522731 ==DQ 0 ==
7355 12:11:33.525176 Final DQ duty delay cell = 0
7356 12:11:33.528870 [0] MAX Duty = 5093%(X100), DQS PI = 18
7357 12:11:33.531966 [0] MIN Duty = 4969%(X100), DQS PI = 46
7358 12:11:33.532389 [0] AVG Duty = 5031%(X100)
7359 12:11:33.535228
7360 12:11:33.535855 ==DQ 1 ==
7361 12:11:33.538678 Final DQ duty delay cell = 0
7362 12:11:33.541574 [0] MAX Duty = 5062%(X100), DQS PI = 2
7363 12:11:33.545204 [0] MIN Duty = 4813%(X100), DQS PI = 34
7364 12:11:33.545753 [0] AVG Duty = 4937%(X100)
7365 12:11:33.546173
7366 12:11:33.551675 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7367 12:11:33.552378
7368 12:11:33.554894 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7369 12:11:33.558166 [DutyScan_Calibration_Flow] ====Done====
7370 12:11:33.561704 nWR fixed to 30
7371 12:11:33.562316 [ModeRegInit_LP4] CH0 RK0
7372 12:11:33.564904 [ModeRegInit_LP4] CH0 RK1
7373 12:11:33.567993 [ModeRegInit_LP4] CH1 RK0
7374 12:11:33.571516 [ModeRegInit_LP4] CH1 RK1
7375 12:11:33.572071 match AC timing 5
7376 12:11:33.578240 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7377 12:11:33.581312 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7378 12:11:33.584974 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7379 12:11:33.591397 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7380 12:11:33.594446 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7381 12:11:33.594988 [MiockJmeterHQA]
7382 12:11:33.595523
7383 12:11:33.597849 [DramcMiockJmeter] u1RxGatingPI = 0
7384 12:11:33.601282 0 : 4257, 4029
7385 12:11:33.601854 4 : 4254, 4027
7386 12:11:33.604311 8 : 4253, 4027
7387 12:11:33.604933 12 : 4252, 4027
7388 12:11:33.605472 16 : 4255, 4029
7389 12:11:33.607961 20 : 4363, 4137
7390 12:11:33.608522 24 : 4252, 4027
7391 12:11:33.611156 28 : 4252, 4027
7392 12:11:33.611695 32 : 4253, 4026
7393 12:11:33.614290 36 : 4255, 4030
7394 12:11:33.614919 40 : 4252, 4027
7395 12:11:33.617560 44 : 4363, 4137
7396 12:11:33.618183 48 : 4363, 4137
7397 12:11:33.618723 52 : 4253, 4026
7398 12:11:33.620976 56 : 4252, 4027
7399 12:11:33.621601 60 : 4253, 4026
7400 12:11:33.624185 64 : 4250, 4026
7401 12:11:33.624297 68 : 4250, 4027
7402 12:11:33.627348 72 : 4252, 4030
7403 12:11:33.627459 76 : 4257, 4029
7404 12:11:33.630349 80 : 4255, 4029
7405 12:11:33.630453 84 : 4250, 4026
7406 12:11:33.630550 88 : 4252, 3705
7407 12:11:33.633712 92 : 4250, 1
7408 12:11:33.633811 96 : 4250, 0
7409 12:11:33.637520 100 : 4250, 0
7410 12:11:33.637604 104 : 4250, 0
7411 12:11:33.637671 108 : 4249, 0
7412 12:11:33.640912 112 : 4250, 0
7413 12:11:33.640999 116 : 4250, 0
7414 12:11:33.643822 120 : 4363, 0
7415 12:11:33.643939 124 : 4249, 0
7416 12:11:33.644036 128 : 4250, 0
7417 12:11:33.647539 132 : 4255, 0
7418 12:11:33.648098 136 : 4250, 0
7419 12:11:33.648457 140 : 4254, 0
7420 12:11:33.650969 144 : 4250, 0
7421 12:11:33.651408 148 : 4250, 0
7422 12:11:33.654093 152 : 4250, 0
7423 12:11:33.654528 156 : 4361, 0
7424 12:11:33.655001 160 : 4250, 0
7425 12:11:33.657247 164 : 4250, 0
7426 12:11:33.657827 168 : 4250, 0
7427 12:11:33.660820 172 : 4250, 0
7428 12:11:33.661368 176 : 4250, 0
7429 12:11:33.661771 180 : 4252, 0
7430 12:11:33.664016 184 : 4255, 0
7431 12:11:33.664553 188 : 4361, 0
7432 12:11:33.667586 192 : 4360, 0
7433 12:11:33.668279 196 : 4255, 0
7434 12:11:33.668923 200 : 4361, 8
7435 12:11:33.670643 204 : 4250, 2491
7436 12:11:33.671141 208 : 4363, 4140
7437 12:11:33.674082 212 : 4250, 4026
7438 12:11:33.674600 216 : 4361, 4137
7439 12:11:33.677233 220 : 4361, 4137
7440 12:11:33.677767 224 : 4250, 4027
7441 12:11:33.680653 228 : 4249, 4027
7442 12:11:33.681147 232 : 4250, 4027
7443 12:11:33.683743 236 : 4250, 4027
7444 12:11:33.684284 240 : 4250, 4027
7445 12:11:33.687143 244 : 4255, 4029
7446 12:11:33.687572 248 : 4250, 4026
7447 12:11:33.687917 252 : 4253, 4029
7448 12:11:33.690684 256 : 4250, 4027
7449 12:11:33.691116 260 : 4250, 4026
7450 12:11:33.693665 264 : 4361, 4137
7451 12:11:33.694100 268 : 4250, 4027
7452 12:11:33.697302 272 : 4360, 4138
7453 12:11:33.697737 276 : 4250, 4026
7454 12:11:33.700338 280 : 4250, 4027
7455 12:11:33.700810 284 : 4250, 4026
7456 12:11:33.703721 288 : 4250, 4027
7457 12:11:33.704154 292 : 4250, 4027
7458 12:11:33.706866 296 : 4250, 4027
7459 12:11:33.707417 300 : 4250, 4026
7460 12:11:33.710860 304 : 4252, 4029
7461 12:11:33.711451 308 : 4250, 4027
7462 12:11:33.713810 312 : 4250, 3855
7463 12:11:33.714404 316 : 4360, 2060
7464 12:11:33.714792
7465 12:11:33.716876 MIOCK jitter meter ch=0
7466 12:11:33.717349
7467 12:11:33.720307 1T = (316-92) = 224 dly cells
7468 12:11:33.723438 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 12:11:33.723978 ==
7470 12:11:33.726488 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 12:11:33.733357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 12:11:33.734078 ==
7473 12:11:33.736873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 12:11:33.743151 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 12:11:33.746443 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 12:11:33.753114 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 12:11:33.760893 [CA 0] Center 43 (13~73) winsize 61
7478 12:11:33.764028 [CA 1] Center 43 (13~73) winsize 61
7479 12:11:33.767657 [CA 2] Center 38 (8~68) winsize 61
7480 12:11:33.770787 [CA 3] Center 37 (8~67) winsize 60
7481 12:11:33.773890 [CA 4] Center 36 (6~66) winsize 61
7482 12:11:33.777370 [CA 5] Center 35 (5~65) winsize 61
7483 12:11:33.777916
7484 12:11:33.780426 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 12:11:33.781041
7486 12:11:33.787081 [CATrainingPosCal] consider 1 rank data
7487 12:11:33.787554 u2DelayCellTimex100 = 290/100 ps
7488 12:11:33.793648 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7489 12:11:33.796630 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7490 12:11:33.800301 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7491 12:11:33.803363 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7492 12:11:33.806911 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 12:11:33.809960 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7494 12:11:33.810551
7495 12:11:33.813602 CA PerBit enable=1, Macro0, CA PI delay=35
7496 12:11:33.814041
7497 12:11:33.816836 [CBTSetCACLKResult] CA Dly = 35
7498 12:11:33.819909 CS Dly: 9 (0~40)
7499 12:11:33.823153 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 12:11:33.826786 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 12:11:33.827213 ==
7502 12:11:33.829893 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 12:11:33.836816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 12:11:33.837333 ==
7505 12:11:33.839808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 12:11:33.846116 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 12:11:33.849730 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 12:11:33.856237 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 12:11:33.863962 [CA 0] Center 43 (13~73) winsize 61
7510 12:11:33.867297 [CA 1] Center 43 (13~73) winsize 61
7511 12:11:33.870625 [CA 2] Center 37 (8~67) winsize 60
7512 12:11:33.874065 [CA 3] Center 38 (8~68) winsize 61
7513 12:11:33.877494 [CA 4] Center 36 (6~66) winsize 61
7514 12:11:33.880366 [CA 5] Center 36 (6~66) winsize 61
7515 12:11:33.880922
7516 12:11:33.883941 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 12:11:33.884365
7518 12:11:33.887036 [CATrainingPosCal] consider 2 rank data
7519 12:11:33.890602 u2DelayCellTimex100 = 290/100 ps
7520 12:11:33.897381 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7521 12:11:33.900259 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7522 12:11:33.903898 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7523 12:11:33.907113 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 12:11:33.910211 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7525 12:11:33.913387 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7526 12:11:33.913807
7527 12:11:33.916934 CA PerBit enable=1, Macro0, CA PI delay=35
7528 12:11:33.917357
7529 12:11:33.919969 [CBTSetCACLKResult] CA Dly = 35
7530 12:11:33.923579 CS Dly: 10 (0~43)
7531 12:11:33.926696 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 12:11:33.930477 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 12:11:33.931014
7534 12:11:33.933469 ----->DramcWriteLeveling(PI) begin...
7535 12:11:33.933953 ==
7536 12:11:33.937023 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 12:11:33.943314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 12:11:33.944009 ==
7539 12:11:33.946899 Write leveling (Byte 0): 36 => 36
7540 12:11:33.949689 Write leveling (Byte 1): 30 => 30
7541 12:11:33.950176 DramcWriteLeveling(PI) end<-----
7542 12:11:33.950608
7543 12:11:33.953098 ==
7544 12:11:33.956679 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 12:11:33.959754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 12:11:33.960283 ==
7547 12:11:33.962961 [Gating] SW mode calibration
7548 12:11:33.969708 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 12:11:33.973161 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 12:11:33.979751 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 12:11:33.982750 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 12:11:33.986262 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7553 12:11:33.992842 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7554 12:11:33.995817 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7555 12:11:33.999466 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7556 12:11:34.006100 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 12:11:34.009221 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 12:11:34.012886 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 12:11:34.019339 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 12:11:34.022560 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7561 12:11:34.026199 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7562 12:11:34.032735 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7563 12:11:34.035872 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7564 12:11:34.038894 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 12:11:34.045464 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 12:11:34.049078 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 12:11:34.052253 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7568 12:11:34.058325 1 6 8 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
7569 12:11:34.061874 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7570 12:11:34.065014 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7571 12:11:34.071853 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7572 12:11:34.074876 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 12:11:34.078261 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 12:11:34.085092 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 12:11:34.087932 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 12:11:34.091510 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 12:11:34.098321 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7578 12:11:34.101316 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 12:11:34.104927 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 12:11:34.111499 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:11:34.114592 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:11:34.117823 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:11:34.124392 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:11:34.128006 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:11:34.131067 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:11:34.137813 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:11:34.141376 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:11:34.144386 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:11:34.150923 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 12:11:34.154090 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 12:11:34.157681 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 12:11:34.164217 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 12:11:34.167351 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 12:11:34.170536 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 12:11:34.174161 Total UI for P1: 0, mck2ui 16
7596 12:11:34.177332 best dqsien dly found for B0: ( 1, 9, 10)
7597 12:11:34.183595 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 12:11:34.187181 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 12:11:34.190342 Total UI for P1: 0, mck2ui 16
7600 12:11:34.193789 best dqsien dly found for B1: ( 1, 9, 18)
7601 12:11:34.197194 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7602 12:11:34.200538 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7603 12:11:34.200638
7604 12:11:34.203606 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7605 12:11:34.207180 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7606 12:11:34.210408 [Gating] SW calibration Done
7607 12:11:34.210491 ==
7608 12:11:34.213465 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 12:11:34.220172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 12:11:34.220258 ==
7611 12:11:34.220325 RX Vref Scan: 0
7612 12:11:34.220389
7613 12:11:34.223377 RX Vref 0 -> 0, step: 1
7614 12:11:34.223462
7615 12:11:34.226767 RX Delay 0 -> 252, step: 8
7616 12:11:34.229734 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7617 12:11:34.233209 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7618 12:11:34.236337 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7619 12:11:34.240036 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7620 12:11:34.246599 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7621 12:11:34.249774 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7622 12:11:34.253124 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7623 12:11:34.256196 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7624 12:11:34.259836 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7625 12:11:34.266092 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7626 12:11:34.269573 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7627 12:11:34.272685 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7628 12:11:34.276310 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7629 12:11:34.279359 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7630 12:11:34.285783 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7631 12:11:34.289348 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7632 12:11:34.289428 ==
7633 12:11:34.292387 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 12:11:34.295993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 12:11:34.296070 ==
7636 12:11:34.299376 DQS Delay:
7637 12:11:34.299494 DQS0 = 0, DQS1 = 0
7638 12:11:34.299596 DQM Delay:
7639 12:11:34.302377 DQM0 = 137, DQM1 = 126
7640 12:11:34.302485 DQ Delay:
7641 12:11:34.305817 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7642 12:11:34.312004 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7643 12:11:34.315631 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7644 12:11:34.318752 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7645 12:11:34.318857
7646 12:11:34.318953
7647 12:11:34.319046 ==
7648 12:11:34.322324 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 12:11:34.325331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 12:11:34.325445 ==
7651 12:11:34.325543
7652 12:11:34.325634
7653 12:11:34.328833 TX Vref Scan disable
7654 12:11:34.332274 == TX Byte 0 ==
7655 12:11:34.335453 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7656 12:11:34.338538 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7657 12:11:34.342227 == TX Byte 1 ==
7658 12:11:34.345353 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7659 12:11:34.348854 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7660 12:11:34.348959 ==
7661 12:11:34.352024 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 12:11:34.358330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 12:11:34.358414 ==
7664 12:11:34.370540
7665 12:11:34.373625 TX Vref early break, caculate TX vref
7666 12:11:34.376693 TX Vref=16, minBit 6, minWin=23, winSum=380
7667 12:11:34.380314 TX Vref=18, minBit 8, minWin=23, winSum=390
7668 12:11:34.383458 TX Vref=20, minBit 2, minWin=23, winSum=394
7669 12:11:34.386931 TX Vref=22, minBit 12, minWin=24, winSum=408
7670 12:11:34.393170 TX Vref=24, minBit 12, minWin=24, winSum=415
7671 12:11:34.396738 TX Vref=26, minBit 0, minWin=25, winSum=422
7672 12:11:34.399817 TX Vref=28, minBit 2, minWin=26, winSum=431
7673 12:11:34.403324 TX Vref=30, minBit 0, minWin=25, winSum=422
7674 12:11:34.406662 TX Vref=32, minBit 0, minWin=25, winSum=415
7675 12:11:34.409871 TX Vref=34, minBit 0, minWin=25, winSum=408
7676 12:11:34.416743 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
7677 12:11:34.416851
7678 12:11:34.419693 Final TX Range 0 Vref 28
7679 12:11:34.419792
7680 12:11:34.419863 ==
7681 12:11:34.422835 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 12:11:34.426479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 12:11:34.426558 ==
7684 12:11:34.426623
7685 12:11:34.426684
7686 12:11:34.429582 TX Vref Scan disable
7687 12:11:34.436602 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7688 12:11:34.436687 == TX Byte 0 ==
7689 12:11:34.439720 u2DelayCellOfst[0]=10 cells (3 PI)
7690 12:11:34.442912 u2DelayCellOfst[1]=16 cells (5 PI)
7691 12:11:34.446577 u2DelayCellOfst[2]=10 cells (3 PI)
7692 12:11:34.449524 u2DelayCellOfst[3]=10 cells (3 PI)
7693 12:11:34.452962 u2DelayCellOfst[4]=6 cells (2 PI)
7694 12:11:34.456144 u2DelayCellOfst[5]=0 cells (0 PI)
7695 12:11:34.459563 u2DelayCellOfst[6]=16 cells (5 PI)
7696 12:11:34.462555 u2DelayCellOfst[7]=13 cells (4 PI)
7697 12:11:34.466153 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7698 12:11:34.469135 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7699 12:11:34.472628 == TX Byte 1 ==
7700 12:11:34.476051 u2DelayCellOfst[8]=0 cells (0 PI)
7701 12:11:34.479148 u2DelayCellOfst[9]=0 cells (0 PI)
7702 12:11:34.482303 u2DelayCellOfst[10]=6 cells (2 PI)
7703 12:11:34.482396 u2DelayCellOfst[11]=3 cells (1 PI)
7704 12:11:34.485965 u2DelayCellOfst[12]=13 cells (4 PI)
7705 12:11:34.489000 u2DelayCellOfst[13]=10 cells (3 PI)
7706 12:11:34.492433 u2DelayCellOfst[14]=13 cells (4 PI)
7707 12:11:34.495857 u2DelayCellOfst[15]=10 cells (3 PI)
7708 12:11:34.502098 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7709 12:11:34.505583 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7710 12:11:34.505656 DramC Write-DBI on
7711 12:11:34.509121 ==
7712 12:11:34.509197 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 12:11:34.515477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 12:11:34.515556 ==
7715 12:11:34.515621
7716 12:11:34.515682
7717 12:11:34.518686 TX Vref Scan disable
7718 12:11:34.518771 == TX Byte 0 ==
7719 12:11:34.525527 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7720 12:11:34.525643 == TX Byte 1 ==
7721 12:11:34.528529 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7722 12:11:34.532135 DramC Write-DBI off
7723 12:11:34.532210
7724 12:11:34.532277 [DATLAT]
7725 12:11:34.535220 Freq=1600, CH0 RK0
7726 12:11:34.535334
7727 12:11:34.535431 DATLAT Default: 0xf
7728 12:11:34.538666 0, 0xFFFF, sum = 0
7729 12:11:34.538741 1, 0xFFFF, sum = 0
7730 12:11:34.542066 2, 0xFFFF, sum = 0
7731 12:11:34.542142 3, 0xFFFF, sum = 0
7732 12:11:34.545056 4, 0xFFFF, sum = 0
7733 12:11:34.545181 5, 0xFFFF, sum = 0
7734 12:11:34.548685 6, 0xFFFF, sum = 0
7735 12:11:34.551702 7, 0xFFFF, sum = 0
7736 12:11:34.551834 8, 0xFFFF, sum = 0
7737 12:11:34.554840 9, 0xFFFF, sum = 0
7738 12:11:34.554962 10, 0xFFFF, sum = 0
7739 12:11:34.558668 11, 0xFFFF, sum = 0
7740 12:11:34.558778 12, 0xFFFF, sum = 0
7741 12:11:34.561550 13, 0xFFFF, sum = 0
7742 12:11:34.561654 14, 0x0, sum = 1
7743 12:11:34.565066 15, 0x0, sum = 2
7744 12:11:34.565143 16, 0x0, sum = 3
7745 12:11:34.568405 17, 0x0, sum = 4
7746 12:11:34.568509 best_step = 15
7747 12:11:34.568614
7748 12:11:34.568708 ==
7749 12:11:34.571583 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 12:11:34.574856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 12:11:34.574959 ==
7752 12:11:34.578332 RX Vref Scan: 1
7753 12:11:34.578455
7754 12:11:34.581834 Set Vref Range= 24 -> 127
7755 12:11:34.581939
7756 12:11:34.582044 RX Vref 24 -> 127, step: 1
7757 12:11:34.585030
7758 12:11:34.585102 RX Delay 19 -> 252, step: 4
7759 12:11:34.585166
7760 12:11:34.588117 Set Vref, RX VrefLevel [Byte0]: 24
7761 12:11:34.591702 [Byte1]: 24
7762 12:11:34.594893
7763 12:11:34.595006 Set Vref, RX VrefLevel [Byte0]: 25
7764 12:11:34.598430 [Byte1]: 25
7765 12:11:34.602504
7766 12:11:34.602609 Set Vref, RX VrefLevel [Byte0]: 26
7767 12:11:34.606089 [Byte1]: 26
7768 12:11:34.610322
7769 12:11:34.610426 Set Vref, RX VrefLevel [Byte0]: 27
7770 12:11:34.613462 [Byte1]: 27
7771 12:11:34.617598
7772 12:11:34.617699 Set Vref, RX VrefLevel [Byte0]: 28
7773 12:11:34.621085 [Byte1]: 28
7774 12:11:34.625463
7775 12:11:34.625635 Set Vref, RX VrefLevel [Byte0]: 29
7776 12:11:34.628864 [Byte1]: 29
7777 12:11:34.633078
7778 12:11:34.633183 Set Vref, RX VrefLevel [Byte0]: 30
7779 12:11:34.639597 [Byte1]: 30
7780 12:11:34.639675
7781 12:11:34.642638 Set Vref, RX VrefLevel [Byte0]: 31
7782 12:11:34.646060 [Byte1]: 31
7783 12:11:34.646130
7784 12:11:34.649152 Set Vref, RX VrefLevel [Byte0]: 32
7785 12:11:34.652728 [Byte1]: 32
7786 12:11:34.655773
7787 12:11:34.655905 Set Vref, RX VrefLevel [Byte0]: 33
7788 12:11:34.658927 [Byte1]: 33
7789 12:11:34.663071
7790 12:11:34.663166 Set Vref, RX VrefLevel [Byte0]: 34
7791 12:11:34.666737 [Byte1]: 34
7792 12:11:34.670750
7793 12:11:34.670829 Set Vref, RX VrefLevel [Byte0]: 35
7794 12:11:34.674123 [Byte1]: 35
7795 12:11:34.678417
7796 12:11:34.678501 Set Vref, RX VrefLevel [Byte0]: 36
7797 12:11:34.681581 [Byte1]: 36
7798 12:11:34.686102
7799 12:11:34.686209 Set Vref, RX VrefLevel [Byte0]: 37
7800 12:11:34.689188 [Byte1]: 37
7801 12:11:34.693356
7802 12:11:34.693440 Set Vref, RX VrefLevel [Byte0]: 38
7803 12:11:34.696986 [Byte1]: 38
7804 12:11:34.701135
7805 12:11:34.701234 Set Vref, RX VrefLevel [Byte0]: 39
7806 12:11:34.704429 [Byte1]: 39
7807 12:11:34.708659
7808 12:11:34.708742 Set Vref, RX VrefLevel [Byte0]: 40
7809 12:11:34.711819 [Byte1]: 40
7810 12:11:34.716378
7811 12:11:34.716462 Set Vref, RX VrefLevel [Byte0]: 41
7812 12:11:34.719377 [Byte1]: 41
7813 12:11:34.723948
7814 12:11:34.724035 Set Vref, RX VrefLevel [Byte0]: 42
7815 12:11:34.727024 [Byte1]: 42
7816 12:11:34.731174
7817 12:11:34.731278 Set Vref, RX VrefLevel [Byte0]: 43
7818 12:11:34.734705 [Byte1]: 43
7819 12:11:34.738739
7820 12:11:34.738847 Set Vref, RX VrefLevel [Byte0]: 44
7821 12:11:34.742056 [Byte1]: 44
7822 12:11:34.746541
7823 12:11:34.746636 Set Vref, RX VrefLevel [Byte0]: 45
7824 12:11:34.749577 [Byte1]: 45
7825 12:11:34.753911
7826 12:11:34.754048 Set Vref, RX VrefLevel [Byte0]: 46
7827 12:11:34.757538 [Byte1]: 46
7828 12:11:34.761736
7829 12:11:34.761853 Set Vref, RX VrefLevel [Byte0]: 47
7830 12:11:34.764704 [Byte1]: 47
7831 12:11:34.768960
7832 12:11:34.769048 Set Vref, RX VrefLevel [Byte0]: 48
7833 12:11:34.772520 [Byte1]: 48
7834 12:11:34.776493
7835 12:11:34.776576 Set Vref, RX VrefLevel [Byte0]: 49
7836 12:11:34.780103 [Byte1]: 49
7837 12:11:34.784360
7838 12:11:34.784440 Set Vref, RX VrefLevel [Byte0]: 50
7839 12:11:34.787851 [Byte1]: 50
7840 12:11:34.792102
7841 12:11:34.792181 Set Vref, RX VrefLevel [Byte0]: 51
7842 12:11:34.795127 [Byte1]: 51
7843 12:11:34.799437
7844 12:11:34.799527 Set Vref, RX VrefLevel [Byte0]: 52
7845 12:11:34.802597 [Byte1]: 52
7846 12:11:34.807147
7847 12:11:34.807236 Set Vref, RX VrefLevel [Byte0]: 53
7848 12:11:34.810166 [Byte1]: 53
7849 12:11:34.814704
7850 12:11:34.814789 Set Vref, RX VrefLevel [Byte0]: 54
7851 12:11:34.817846 [Byte1]: 54
7852 12:11:34.822076
7853 12:11:34.822158 Set Vref, RX VrefLevel [Byte0]: 55
7854 12:11:34.825272 [Byte1]: 55
7855 12:11:34.829953
7856 12:11:34.830069 Set Vref, RX VrefLevel [Byte0]: 56
7857 12:11:34.833023 [Byte1]: 56
7858 12:11:34.837256
7859 12:11:34.837337 Set Vref, RX VrefLevel [Byte0]: 57
7860 12:11:34.840897 [Byte1]: 57
7861 12:11:34.844975
7862 12:11:34.845067 Set Vref, RX VrefLevel [Byte0]: 58
7863 12:11:34.848024 [Byte1]: 58
7864 12:11:34.852357
7865 12:11:34.852497 Set Vref, RX VrefLevel [Byte0]: 59
7866 12:11:34.855696 [Byte1]: 59
7867 12:11:34.859938
7868 12:11:34.860025 Set Vref, RX VrefLevel [Byte0]: 60
7869 12:11:34.863156 [Byte1]: 60
7870 12:11:34.867382
7871 12:11:34.870862 Set Vref, RX VrefLevel [Byte0]: 61
7872 12:11:34.873885 [Byte1]: 61
7873 12:11:34.873985
7874 12:11:34.877427 Set Vref, RX VrefLevel [Byte0]: 62
7875 12:11:34.880525 [Byte1]: 62
7876 12:11:34.880643
7877 12:11:34.884026 Set Vref, RX VrefLevel [Byte0]: 63
7878 12:11:34.887103 [Byte1]: 63
7879 12:11:34.887186
7880 12:11:34.890775 Set Vref, RX VrefLevel [Byte0]: 64
7881 12:11:34.893969 [Byte1]: 64
7882 12:11:34.898056
7883 12:11:34.898139 Set Vref, RX VrefLevel [Byte0]: 65
7884 12:11:34.901297 [Byte1]: 65
7885 12:11:34.905485
7886 12:11:34.905576 Set Vref, RX VrefLevel [Byte0]: 66
7887 12:11:34.908523 [Byte1]: 66
7888 12:11:34.913112
7889 12:11:34.913208 Set Vref, RX VrefLevel [Byte0]: 67
7890 12:11:34.916627 [Byte1]: 67
7891 12:11:34.920408
7892 12:11:34.920492 Set Vref, RX VrefLevel [Byte0]: 68
7893 12:11:34.924073 [Byte1]: 68
7894 12:11:34.928279
7895 12:11:34.928374 Set Vref, RX VrefLevel [Byte0]: 69
7896 12:11:34.931420 [Byte1]: 69
7897 12:11:34.935650
7898 12:11:34.935757 Set Vref, RX VrefLevel [Byte0]: 70
7899 12:11:34.939195 [Byte1]: 70
7900 12:11:34.943408
7901 12:11:34.943527 Set Vref, RX VrefLevel [Byte0]: 71
7902 12:11:34.946492 [Byte1]: 71
7903 12:11:34.950936
7904 12:11:34.951047 Set Vref, RX VrefLevel [Byte0]: 72
7905 12:11:34.954085 [Byte1]: 72
7906 12:11:34.958510
7907 12:11:34.958635 Set Vref, RX VrefLevel [Byte0]: 73
7908 12:11:34.961786 [Byte1]: 73
7909 12:11:34.965680
7910 12:11:34.969130 Set Vref, RX VrefLevel [Byte0]: 74
7911 12:11:34.972593 [Byte1]: 74
7912 12:11:34.972697
7913 12:11:34.975730 Set Vref, RX VrefLevel [Byte0]: 75
7914 12:11:34.978915 [Byte1]: 75
7915 12:11:34.979024
7916 12:11:34.982679 Set Vref, RX VrefLevel [Byte0]: 76
7917 12:11:34.985567 [Byte1]: 76
7918 12:11:34.985662
7919 12:11:34.988846 Set Vref, RX VrefLevel [Byte0]: 77
7920 12:11:34.992438 [Byte1]: 77
7921 12:11:34.996565
7922 12:11:34.996670 Set Vref, RX VrefLevel [Byte0]: 78
7923 12:11:34.999580 [Byte1]: 78
7924 12:11:35.003685
7925 12:11:35.003791 Set Vref, RX VrefLevel [Byte0]: 79
7926 12:11:35.007327 [Byte1]: 79
7927 12:11:35.011662
7928 12:11:35.011780 Set Vref, RX VrefLevel [Byte0]: 80
7929 12:11:35.014696 [Byte1]: 80
7930 12:11:35.019224
7931 12:11:35.019312 Set Vref, RX VrefLevel [Byte0]: 81
7932 12:11:35.022503 [Byte1]: 81
7933 12:11:35.026727
7934 12:11:35.026814 Final RX Vref Byte 0 = 62 to rank0
7935 12:11:35.029824 Final RX Vref Byte 1 = 60 to rank0
7936 12:11:35.033544 Final RX Vref Byte 0 = 62 to rank1
7937 12:11:35.036575 Final RX Vref Byte 1 = 60 to rank1==
7938 12:11:35.039555 Dram Type= 6, Freq= 0, CH_0, rank 0
7939 12:11:35.046546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7940 12:11:35.046637 ==
7941 12:11:35.046718 DQS Delay:
7942 12:11:35.049698 DQS0 = 0, DQS1 = 0
7943 12:11:35.049785 DQM Delay:
7944 12:11:35.049858 DQM0 = 136, DQM1 = 124
7945 12:11:35.053134 DQ Delay:
7946 12:11:35.056543 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7947 12:11:35.059645 DQ4 =140, DQ5 =126, DQ6 =144, DQ7 =144
7948 12:11:35.063379 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7949 12:11:35.066329 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =132
7950 12:11:35.066411
7951 12:11:35.066479
7952 12:11:35.066553
7953 12:11:35.069713 [DramC_TX_OE_Calibration] TA2
7954 12:11:35.072969 Original DQ_B0 (3 6) =30, OEN = 27
7955 12:11:35.076342 Original DQ_B1 (3 6) =30, OEN = 27
7956 12:11:35.079179 24, 0x0, End_B0=24 End_B1=24
7957 12:11:35.082735 25, 0x0, End_B0=25 End_B1=25
7958 12:11:35.082828 26, 0x0, End_B0=26 End_B1=26
7959 12:11:35.085827 27, 0x0, End_B0=27 End_B1=27
7960 12:11:35.089218 28, 0x0, End_B0=28 End_B1=28
7961 12:11:35.092370 29, 0x0, End_B0=29 End_B1=29
7962 12:11:35.092461 30, 0x0, End_B0=30 End_B1=30
7963 12:11:35.095895 31, 0x4141, End_B0=30 End_B1=30
7964 12:11:35.098888 Byte0 end_step=30 best_step=27
7965 12:11:35.102576 Byte1 end_step=30 best_step=27
7966 12:11:35.105798 Byte0 TX OE(2T, 0.5T) = (3, 3)
7967 12:11:35.108900 Byte1 TX OE(2T, 0.5T) = (3, 3)
7968 12:11:35.108980
7969 12:11:35.109048
7970 12:11:35.115765 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
7971 12:11:35.118779 CH0 RK0: MR19=303, MR18=201E
7972 12:11:35.125505 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
7973 12:11:35.125596
7974 12:11:35.128583 ----->DramcWriteLeveling(PI) begin...
7975 12:11:35.128691 ==
7976 12:11:35.132057 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 12:11:35.135134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 12:11:35.135242 ==
7979 12:11:35.138416 Write leveling (Byte 0): 38 => 38
7980 12:11:35.142174 Write leveling (Byte 1): 28 => 28
7981 12:11:35.145167 DramcWriteLeveling(PI) end<-----
7982 12:11:35.145272
7983 12:11:35.145367 ==
7984 12:11:35.148375 Dram Type= 6, Freq= 0, CH_0, rank 1
7985 12:11:35.155035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 12:11:35.155142 ==
7987 12:11:35.155239 [Gating] SW mode calibration
7988 12:11:35.164822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7989 12:11:35.167868 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7990 12:11:35.174663 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 12:11:35.178150 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 12:11:35.181068 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 12:11:35.187649 1 4 12 | B1->B0 | 2525 3030 | 0 1 | (0 0) (0 0)
7994 12:11:35.191325 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 12:11:35.194491 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 12:11:35.201164 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 12:11:35.204716 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 12:11:35.207952 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 12:11:35.214698 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 12:11:35.217749 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 12:11:35.220815 1 5 12 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 1)
8002 12:11:35.227356 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8003 12:11:35.230545 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 12:11:35.233775 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 12:11:35.240534 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 12:11:35.244078 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 12:11:35.247156 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 12:11:35.254035 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8009 12:11:35.257018 1 6 12 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8010 12:11:35.260109 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 12:11:35.267240 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 12:11:35.270436 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 12:11:35.273438 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 12:11:35.280148 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 12:11:35.283609 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 12:11:35.286821 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 12:11:35.293494 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8018 12:11:35.296578 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 12:11:35.299607 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 12:11:35.306477 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 12:11:35.310099 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 12:11:35.313252 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 12:11:35.319574 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 12:11:35.323161 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 12:11:35.326355 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 12:11:35.333081 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 12:11:35.336085 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 12:11:35.339317 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 12:11:35.346116 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 12:11:35.349756 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 12:11:35.352749 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 12:11:35.356204 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8033 12:11:35.362637 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8034 12:11:35.366244 Total UI for P1: 0, mck2ui 16
8035 12:11:35.369363 best dqsien dly found for B0: ( 1, 9, 8)
8036 12:11:35.372525 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8037 12:11:35.376182 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 12:11:35.379359 Total UI for P1: 0, mck2ui 16
8039 12:11:35.382429 best dqsien dly found for B1: ( 1, 9, 14)
8040 12:11:35.385934 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8041 12:11:35.392086 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8042 12:11:35.392170
8043 12:11:35.395654 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8044 12:11:35.398710 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8045 12:11:35.402121 [Gating] SW calibration Done
8046 12:11:35.402196 ==
8047 12:11:35.405309 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 12:11:35.408945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 12:11:35.409018 ==
8050 12:11:35.412056 RX Vref Scan: 0
8051 12:11:35.412198
8052 12:11:35.412294 RX Vref 0 -> 0, step: 1
8053 12:11:35.412390
8054 12:11:35.415522 RX Delay 0 -> 252, step: 8
8055 12:11:35.418643 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8056 12:11:35.425044 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8057 12:11:35.428609 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8058 12:11:35.431727 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8059 12:11:35.435229 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8060 12:11:35.438432 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8061 12:11:35.442109 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8062 12:11:35.448556 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8063 12:11:35.451750 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8064 12:11:35.454890 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8065 12:11:35.458495 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8066 12:11:35.465149 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8067 12:11:35.468519 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8068 12:11:35.471597 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8069 12:11:35.475167 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8070 12:11:35.478209 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8071 12:11:35.481412 ==
8072 12:11:35.481499 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 12:11:35.488081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 12:11:35.488193 ==
8075 12:11:35.488291 DQS Delay:
8076 12:11:35.491633 DQS0 = 0, DQS1 = 0
8077 12:11:35.491718 DQM Delay:
8078 12:11:35.494580 DQM0 = 136, DQM1 = 125
8079 12:11:35.494666 DQ Delay:
8080 12:11:35.498318 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8081 12:11:35.501526 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8082 12:11:35.504998 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8083 12:11:35.507832 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8084 12:11:35.507912
8085 12:11:35.507979
8086 12:11:35.508045 ==
8087 12:11:35.511502 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 12:11:35.518153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 12:11:35.518262 ==
8090 12:11:35.518359
8091 12:11:35.518463
8092 12:11:35.518555 TX Vref Scan disable
8093 12:11:35.521817 == TX Byte 0 ==
8094 12:11:35.525018 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8095 12:11:35.531414 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8096 12:11:35.531522 == TX Byte 1 ==
8097 12:11:35.535091 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8098 12:11:35.541525 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8099 12:11:35.541611 ==
8100 12:11:35.544693 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 12:11:35.547913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 12:11:35.547990 ==
8103 12:11:35.563128
8104 12:11:35.566592 TX Vref early break, caculate TX vref
8105 12:11:35.569640 TX Vref=16, minBit 2, minWin=23, winSum=390
8106 12:11:35.573289 TX Vref=18, minBit 0, minWin=24, winSum=396
8107 12:11:35.576295 TX Vref=20, minBit 0, minWin=24, winSum=403
8108 12:11:35.579848 TX Vref=22, minBit 8, minWin=24, winSum=412
8109 12:11:35.582920 TX Vref=24, minBit 2, minWin=25, winSum=421
8110 12:11:35.589694 TX Vref=26, minBit 0, minWin=26, winSum=429
8111 12:11:35.592790 TX Vref=28, minBit 0, minWin=26, winSum=426
8112 12:11:35.596249 TX Vref=30, minBit 0, minWin=26, winSum=429
8113 12:11:35.599453 TX Vref=32, minBit 1, minWin=25, winSum=421
8114 12:11:35.602426 TX Vref=34, minBit 2, minWin=24, winSum=410
8115 12:11:35.606068 TX Vref=36, minBit 2, minWin=24, winSum=404
8116 12:11:35.612559 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8117 12:11:35.612665
8118 12:11:35.615842 Final TX Range 0 Vref 26
8119 12:11:35.615953
8120 12:11:35.616048 ==
8121 12:11:35.619184 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 12:11:35.622665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 12:11:35.622754 ==
8124 12:11:35.625651
8125 12:11:35.625738
8126 12:11:35.625805 TX Vref Scan disable
8127 12:11:35.632421 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8128 12:11:35.632532 == TX Byte 0 ==
8129 12:11:35.635566 u2DelayCellOfst[0]=13 cells (4 PI)
8130 12:11:35.639182 u2DelayCellOfst[1]=20 cells (6 PI)
8131 12:11:35.642346 u2DelayCellOfst[2]=13 cells (4 PI)
8132 12:11:35.645597 u2DelayCellOfst[3]=13 cells (4 PI)
8133 12:11:35.648894 u2DelayCellOfst[4]=10 cells (3 PI)
8134 12:11:35.652001 u2DelayCellOfst[5]=0 cells (0 PI)
8135 12:11:35.655315 u2DelayCellOfst[6]=16 cells (5 PI)
8136 12:11:35.658954 u2DelayCellOfst[7]=20 cells (6 PI)
8137 12:11:35.662006 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8138 12:11:35.665204 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8139 12:11:35.668731 == TX Byte 1 ==
8140 12:11:35.671655 u2DelayCellOfst[8]=0 cells (0 PI)
8141 12:11:35.675359 u2DelayCellOfst[9]=0 cells (0 PI)
8142 12:11:35.678539 u2DelayCellOfst[10]=6 cells (2 PI)
8143 12:11:35.681929 u2DelayCellOfst[11]=3 cells (1 PI)
8144 12:11:35.685008 u2DelayCellOfst[12]=13 cells (4 PI)
8145 12:11:35.688328 u2DelayCellOfst[13]=13 cells (4 PI)
8146 12:11:35.688433 u2DelayCellOfst[14]=13 cells (4 PI)
8147 12:11:35.691930 u2DelayCellOfst[15]=10 cells (3 PI)
8148 12:11:35.698674 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8149 12:11:35.701689 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8150 12:11:35.704869 DramC Write-DBI on
8151 12:11:35.704969 ==
8152 12:11:35.708526 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:11:35.711707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:11:35.711814 ==
8155 12:11:35.711891
8156 12:11:35.711985
8157 12:11:35.714766 TX Vref Scan disable
8158 12:11:35.714857 == TX Byte 0 ==
8159 12:11:35.721385 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8160 12:11:35.721498 == TX Byte 1 ==
8161 12:11:35.728263 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8162 12:11:35.728376 DramC Write-DBI off
8163 12:11:35.728474
8164 12:11:35.728568 [DATLAT]
8165 12:11:35.731674 Freq=1600, CH0 RK1
8166 12:11:35.731786
8167 12:11:35.731883 DATLAT Default: 0xf
8168 12:11:35.734640 0, 0xFFFF, sum = 0
8169 12:11:35.738202 1, 0xFFFF, sum = 0
8170 12:11:35.738317 2, 0xFFFF, sum = 0
8171 12:11:35.741353 3, 0xFFFF, sum = 0
8172 12:11:35.741467 4, 0xFFFF, sum = 0
8173 12:11:35.744466 5, 0xFFFF, sum = 0
8174 12:11:35.744574 6, 0xFFFF, sum = 0
8175 12:11:35.747984 7, 0xFFFF, sum = 0
8176 12:11:35.748095 8, 0xFFFF, sum = 0
8177 12:11:35.751052 9, 0xFFFF, sum = 0
8178 12:11:35.751156 10, 0xFFFF, sum = 0
8179 12:11:35.754757 11, 0xFFFF, sum = 0
8180 12:11:35.754859 12, 0xFFFF, sum = 0
8181 12:11:35.757867 13, 0xFFFF, sum = 0
8182 12:11:35.757988 14, 0x0, sum = 1
8183 12:11:35.761084 15, 0x0, sum = 2
8184 12:11:35.761189 16, 0x0, sum = 3
8185 12:11:35.764645 17, 0x0, sum = 4
8186 12:11:35.764760 best_step = 15
8187 12:11:35.764838
8188 12:11:35.764906 ==
8189 12:11:35.767714 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 12:11:35.774518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 12:11:35.774633 ==
8192 12:11:35.774733 RX Vref Scan: 0
8193 12:11:35.774828
8194 12:11:35.777659 RX Vref 0 -> 0, step: 1
8195 12:11:35.777760
8196 12:11:35.780714 RX Delay 11 -> 252, step: 4
8197 12:11:35.784250 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8198 12:11:35.787341 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8199 12:11:35.790980 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8200 12:11:35.797528 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8201 12:11:35.800594 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8202 12:11:35.803992 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8203 12:11:35.807247 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8204 12:11:35.810349 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8205 12:11:35.817323 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8206 12:11:35.820427 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8207 12:11:35.823945 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8208 12:11:35.826938 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8209 12:11:35.833727 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8210 12:11:35.837178 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8211 12:11:35.840391 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8212 12:11:35.843738 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8213 12:11:35.843852 ==
8214 12:11:35.846797 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 12:11:35.853324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 12:11:35.853442 ==
8217 12:11:35.853547 DQS Delay:
8218 12:11:35.853647 DQS0 = 0, DQS1 = 0
8219 12:11:35.857016 DQM Delay:
8220 12:11:35.857102 DQM0 = 133, DQM1 = 123
8221 12:11:35.860163 DQ Delay:
8222 12:11:35.863299 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8223 12:11:35.866858 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8224 12:11:35.869961 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8225 12:11:35.873672 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8226 12:11:35.873785
8227 12:11:35.873882
8228 12:11:35.873974
8229 12:11:35.876964 [DramC_TX_OE_Calibration] TA2
8230 12:11:35.880103 Original DQ_B0 (3 6) =30, OEN = 27
8231 12:11:35.883481 Original DQ_B1 (3 6) =30, OEN = 27
8232 12:11:35.886488 24, 0x0, End_B0=24 End_B1=24
8233 12:11:35.886574 25, 0x0, End_B0=25 End_B1=25
8234 12:11:35.890132 26, 0x0, End_B0=26 End_B1=26
8235 12:11:35.893100 27, 0x0, End_B0=27 End_B1=27
8236 12:11:35.896664 28, 0x0, End_B0=28 End_B1=28
8237 12:11:35.899729 29, 0x0, End_B0=29 End_B1=29
8238 12:11:35.899826 30, 0x0, End_B0=30 End_B1=30
8239 12:11:35.902783 31, 0x4141, End_B0=30 End_B1=30
8240 12:11:35.906370 Byte0 end_step=30 best_step=27
8241 12:11:35.909777 Byte1 end_step=30 best_step=27
8242 12:11:35.912976 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 12:11:35.916643 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 12:11:35.916748
8245 12:11:35.916833
8246 12:11:35.923176 [DQSOSCAuto] RK1, (LSB)MR18= 0x230f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8247 12:11:35.926314 CH0 RK1: MR19=303, MR18=230F
8248 12:11:35.932850 CH0_RK1: MR19=0x303, MR18=0x230F, DQSOSC=392, MR23=63, INC=24, DEC=16
8249 12:11:35.936122 [RxdqsGatingPostProcess] freq 1600
8250 12:11:35.939324 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 12:11:35.942855 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 12:11:35.945784 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 12:11:35.949301 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 12:11:35.952850 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 12:11:35.955894 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 12:11:35.958925 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 12:11:35.962649 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 12:11:35.965893 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 12:11:35.969117 Pre-setting of DQS Precalculation
8260 12:11:35.972285 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 12:11:35.972398 ==
8262 12:11:35.975819 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 12:11:35.982164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 12:11:35.982275 ==
8265 12:11:35.985754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 12:11:35.992322 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 12:11:35.995375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 12:11:36.002029 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 12:11:36.009399 [CA 0] Center 40 (11~70) winsize 60
8270 12:11:36.012474 [CA 1] Center 41 (11~71) winsize 61
8271 12:11:36.016180 [CA 2] Center 37 (8~67) winsize 60
8272 12:11:36.019347 [CA 3] Center 36 (7~66) winsize 60
8273 12:11:36.022631 [CA 4] Center 36 (7~66) winsize 60
8274 12:11:36.025912 [CA 5] Center 35 (5~66) winsize 62
8275 12:11:36.026025
8276 12:11:36.029509 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8277 12:11:36.029617
8278 12:11:36.032619 [CATrainingPosCal] consider 1 rank data
8279 12:11:36.035727 u2DelayCellTimex100 = 290/100 ps
8280 12:11:36.042552 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8281 12:11:36.045986 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8282 12:11:36.049004 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
8283 12:11:36.052546 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8284 12:11:36.055907 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8285 12:11:36.058923 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8286 12:11:36.059026
8287 12:11:36.062460 CA PerBit enable=1, Macro0, CA PI delay=35
8288 12:11:36.062568
8289 12:11:36.065565 [CBTSetCACLKResult] CA Dly = 35
8290 12:11:36.069107 CS Dly: 8 (0~39)
8291 12:11:36.072282 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 12:11:36.075432 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 12:11:36.075537 ==
8294 12:11:36.079079 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 12:11:36.082217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 12:11:36.085879 ==
8297 12:11:36.088832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 12:11:36.092467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 12:11:36.098590 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 12:11:36.105452 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 12:11:36.112735 [CA 0] Center 42 (13~72) winsize 60
8302 12:11:36.115636 [CA 1] Center 42 (12~72) winsize 61
8303 12:11:36.119189 [CA 2] Center 38 (9~68) winsize 60
8304 12:11:36.122370 [CA 3] Center 37 (8~67) winsize 60
8305 12:11:36.125644 [CA 4] Center 38 (9~67) winsize 59
8306 12:11:36.129253 [CA 5] Center 37 (8~67) winsize 60
8307 12:11:36.129337
8308 12:11:36.132237 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 12:11:36.132321
8310 12:11:36.135801 [CATrainingPosCal] consider 2 rank data
8311 12:11:36.139297 u2DelayCellTimex100 = 290/100 ps
8312 12:11:36.145551 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8313 12:11:36.149070 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8314 12:11:36.152187 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8315 12:11:36.155658 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8316 12:11:36.158823 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8317 12:11:36.162353 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8318 12:11:36.162436
8319 12:11:36.165774 CA PerBit enable=1, Macro0, CA PI delay=37
8320 12:11:36.165858
8321 12:11:36.168758 [CBTSetCACLKResult] CA Dly = 37
8322 12:11:36.171797 CS Dly: 10 (0~43)
8323 12:11:36.175319 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 12:11:36.178506 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 12:11:36.178589
8326 12:11:36.182166 ----->DramcWriteLeveling(PI) begin...
8327 12:11:36.182277 ==
8328 12:11:36.185388 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 12:11:36.191977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 12:11:36.192053 ==
8331 12:11:36.194884 Write leveling (Byte 0): 24 => 24
8332 12:11:36.198665 Write leveling (Byte 1): 29 => 29
8333 12:11:36.198768 DramcWriteLeveling(PI) end<-----
8334 12:11:36.201680
8335 12:11:36.201757 ==
8336 12:11:36.204773 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 12:11:36.208324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 12:11:36.208403 ==
8339 12:11:36.211372 [Gating] SW mode calibration
8340 12:11:36.218181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 12:11:36.224797 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 12:11:36.227910 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:11:36.231061 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:11:36.237802 1 4 8 | B1->B0 | 2c2c 2e2e | 0 1 | (0 0) (1 1)
8345 12:11:36.240795 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 12:11:36.244320 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 12:11:36.251078 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 12:11:36.253988 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 12:11:36.257462 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 12:11:36.263789 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 12:11:36.267283 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8352 12:11:36.270734 1 5 8 | B1->B0 | 2d2d 2828 | 0 0 | (0 1) (1 0)
8353 12:11:36.277254 1 5 12 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
8354 12:11:36.280384 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 12:11:36.284052 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 12:11:36.287138 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 12:11:36.293974 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 12:11:36.297011 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 12:11:36.300562 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8360 12:11:36.307133 1 6 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8361 12:11:36.310198 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 12:11:36.313708 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 12:11:36.320315 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 12:11:36.323329 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 12:11:36.326688 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 12:11:36.333394 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 12:11:36.336441 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8368 12:11:36.340019 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8369 12:11:36.346491 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8370 12:11:36.350122 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 12:11:36.353194 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 12:11:36.359802 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 12:11:36.363322 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 12:11:36.366346 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 12:11:36.373005 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 12:11:36.376513 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 12:11:36.379393 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 12:11:36.385895 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 12:11:36.389598 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 12:11:36.392713 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:11:36.399443 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:11:36.402800 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:11:36.406340 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:11:36.412489 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8385 12:11:36.416005 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8386 12:11:36.419035 Total UI for P1: 0, mck2ui 16
8387 12:11:36.422718 best dqsien dly found for B0: ( 1, 9, 8)
8388 12:11:36.425957 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 12:11:36.429410 Total UI for P1: 0, mck2ui 16
8390 12:11:36.432425 best dqsien dly found for B1: ( 1, 9, 10)
8391 12:11:36.435940 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8392 12:11:36.439462 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8393 12:11:36.439546
8394 12:11:36.445863 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8395 12:11:36.449286 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8396 12:11:36.452387 [Gating] SW calibration Done
8397 12:11:36.452471 ==
8398 12:11:36.455423 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 12:11:36.458989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 12:11:36.459077 ==
8401 12:11:36.459145 RX Vref Scan: 0
8402 12:11:36.462083
8403 12:11:36.462169 RX Vref 0 -> 0, step: 1
8404 12:11:36.462248
8405 12:11:36.465580 RX Delay 0 -> 252, step: 8
8406 12:11:36.469131 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8407 12:11:36.472078 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8408 12:11:36.478769 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8409 12:11:36.482249 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8410 12:11:36.485502 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8411 12:11:36.488805 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8412 12:11:36.492330 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8413 12:11:36.495469 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8414 12:11:36.502294 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8415 12:11:36.505242 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8416 12:11:36.508637 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8417 12:11:36.512006 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8418 12:11:36.515582 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8419 12:11:36.522176 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8420 12:11:36.525311 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8421 12:11:36.528560 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8422 12:11:36.528659 ==
8423 12:11:36.531989 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 12:11:36.535007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 12:11:36.538687 ==
8426 12:11:36.538774 DQS Delay:
8427 12:11:36.538841 DQS0 = 0, DQS1 = 0
8428 12:11:36.541722 DQM Delay:
8429 12:11:36.541806 DQM0 = 138, DQM1 = 130
8430 12:11:36.544777 DQ Delay:
8431 12:11:36.548400 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8432 12:11:36.551445 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8433 12:11:36.555074 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8434 12:11:36.558198 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8435 12:11:36.558288
8436 12:11:36.558390
8437 12:11:36.558455 ==
8438 12:11:36.561304 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 12:11:36.564962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 12:11:36.568061 ==
8441 12:11:36.568146
8442 12:11:36.568213
8443 12:11:36.568280 TX Vref Scan disable
8444 12:11:36.571586 == TX Byte 0 ==
8445 12:11:36.574714 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8446 12:11:36.577891 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8447 12:11:36.581636 == TX Byte 1 ==
8448 12:11:36.584802 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8449 12:11:36.587917 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8450 12:11:36.588003 ==
8451 12:11:36.591474 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 12:11:36.597625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 12:11:36.597710 ==
8454 12:11:36.609926
8455 12:11:36.612964 TX Vref early break, caculate TX vref
8456 12:11:36.616494 TX Vref=16, minBit 9, minWin=21, winSum=366
8457 12:11:36.619563 TX Vref=18, minBit 10, minWin=21, winSum=378
8458 12:11:36.623179 TX Vref=20, minBit 10, minWin=22, winSum=384
8459 12:11:36.626260 TX Vref=22, minBit 10, minWin=22, winSum=392
8460 12:11:36.633069 TX Vref=24, minBit 10, minWin=23, winSum=404
8461 12:11:36.636535 TX Vref=26, minBit 10, minWin=24, winSum=415
8462 12:11:36.639537 TX Vref=28, minBit 9, minWin=25, winSum=419
8463 12:11:36.643247 TX Vref=30, minBit 8, minWin=24, winSum=410
8464 12:11:36.646500 TX Vref=32, minBit 11, minWin=23, winSum=399
8465 12:11:36.649516 TX Vref=34, minBit 8, minWin=23, winSum=394
8466 12:11:36.656259 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8467 12:11:36.656353
8468 12:11:36.659777 Final TX Range 0 Vref 28
8469 12:11:36.659863
8470 12:11:36.659932 ==
8471 12:11:36.662848 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 12:11:36.665911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 12:11:36.666006 ==
8474 12:11:36.666076
8475 12:11:36.669519
8476 12:11:36.669601 TX Vref Scan disable
8477 12:11:36.676152 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8478 12:11:36.676246 == TX Byte 0 ==
8479 12:11:36.679276 u2DelayCellOfst[0]=16 cells (5 PI)
8480 12:11:36.682551 u2DelayCellOfst[1]=10 cells (3 PI)
8481 12:11:36.685652 u2DelayCellOfst[2]=0 cells (0 PI)
8482 12:11:36.689160 u2DelayCellOfst[3]=6 cells (2 PI)
8483 12:11:36.692339 u2DelayCellOfst[4]=6 cells (2 PI)
8484 12:11:36.695981 u2DelayCellOfst[5]=16 cells (5 PI)
8485 12:11:36.699120 u2DelayCellOfst[6]=16 cells (5 PI)
8486 12:11:36.702056 u2DelayCellOfst[7]=3 cells (1 PI)
8487 12:11:36.705762 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8488 12:11:36.709126 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8489 12:11:36.712137 == TX Byte 1 ==
8490 12:11:36.715611 u2DelayCellOfst[8]=0 cells (0 PI)
8491 12:11:36.718519 u2DelayCellOfst[9]=3 cells (1 PI)
8492 12:11:36.722068 u2DelayCellOfst[10]=10 cells (3 PI)
8493 12:11:36.725177 u2DelayCellOfst[11]=3 cells (1 PI)
8494 12:11:36.728645 u2DelayCellOfst[12]=13 cells (4 PI)
8495 12:11:36.728722 u2DelayCellOfst[13]=16 cells (5 PI)
8496 12:11:36.731795 u2DelayCellOfst[14]=20 cells (6 PI)
8497 12:11:36.735467 u2DelayCellOfst[15]=16 cells (5 PI)
8498 12:11:36.741987 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8499 12:11:36.745037 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8500 12:11:36.745149 DramC Write-DBI on
8501 12:11:36.748569 ==
8502 12:11:36.751727 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 12:11:36.754879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 12:11:36.754985 ==
8505 12:11:36.755082
8506 12:11:36.755173
8507 12:11:36.758626 TX Vref Scan disable
8508 12:11:36.758702 == TX Byte 0 ==
8509 12:11:36.764975 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8510 12:11:36.765058 == TX Byte 1 ==
8511 12:11:36.768493 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8512 12:11:36.771602 DramC Write-DBI off
8513 12:11:36.771679
8514 12:11:36.771745 [DATLAT]
8515 12:11:36.774743 Freq=1600, CH1 RK0
8516 12:11:36.774815
8517 12:11:36.774878 DATLAT Default: 0xf
8518 12:11:36.778177 0, 0xFFFF, sum = 0
8519 12:11:36.778254 1, 0xFFFF, sum = 0
8520 12:11:36.781243 2, 0xFFFF, sum = 0
8521 12:11:36.781331 3, 0xFFFF, sum = 0
8522 12:11:36.784483 4, 0xFFFF, sum = 0
8523 12:11:36.788109 5, 0xFFFF, sum = 0
8524 12:11:36.788216 6, 0xFFFF, sum = 0
8525 12:11:36.791372 7, 0xFFFF, sum = 0
8526 12:11:36.791475 8, 0xFFFF, sum = 0
8527 12:11:36.794936 9, 0xFFFF, sum = 0
8528 12:11:36.795053 10, 0xFFFF, sum = 0
8529 12:11:36.798206 11, 0xFFFF, sum = 0
8530 12:11:36.798279 12, 0xFFFF, sum = 0
8531 12:11:36.801300 13, 0xFFFF, sum = 0
8532 12:11:36.801400 14, 0x0, sum = 1
8533 12:11:36.804781 15, 0x0, sum = 2
8534 12:11:36.804855 16, 0x0, sum = 3
8535 12:11:36.807824 17, 0x0, sum = 4
8536 12:11:36.807924 best_step = 15
8537 12:11:36.807995
8538 12:11:36.808058 ==
8539 12:11:36.811354 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 12:11:36.814263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 12:11:36.817646 ==
8542 12:11:36.817737 RX Vref Scan: 1
8543 12:11:36.817804
8544 12:11:36.821286 Set Vref Range= 24 -> 127
8545 12:11:36.821368
8546 12:11:36.824211 RX Vref 24 -> 127, step: 1
8547 12:11:36.824287
8548 12:11:36.824366 RX Delay 19 -> 252, step: 4
8549 12:11:36.824429
8550 12:11:36.827853 Set Vref, RX VrefLevel [Byte0]: 24
8551 12:11:36.830776 [Byte1]: 24
8552 12:11:36.834848
8553 12:11:36.834955 Set Vref, RX VrefLevel [Byte0]: 25
8554 12:11:36.838059 [Byte1]: 25
8555 12:11:36.842247
8556 12:11:36.842329 Set Vref, RX VrefLevel [Byte0]: 26
8557 12:11:36.845658 [Byte1]: 26
8558 12:11:36.849794
8559 12:11:36.849879 Set Vref, RX VrefLevel [Byte0]: 27
8560 12:11:36.853004 [Byte1]: 27
8561 12:11:36.857660
8562 12:11:36.857744 Set Vref, RX VrefLevel [Byte0]: 28
8563 12:11:36.860758 [Byte1]: 28
8564 12:11:36.864885
8565 12:11:36.864998 Set Vref, RX VrefLevel [Byte0]: 29
8566 12:11:36.868573 [Byte1]: 29
8567 12:11:36.872564
8568 12:11:36.872670 Set Vref, RX VrefLevel [Byte0]: 30
8569 12:11:36.875756 [Byte1]: 30
8570 12:11:36.879911
8571 12:11:36.879996 Set Vref, RX VrefLevel [Byte0]: 31
8572 12:11:36.883540 [Byte1]: 31
8573 12:11:36.887686
8574 12:11:36.887769 Set Vref, RX VrefLevel [Byte0]: 32
8575 12:11:36.890930 [Byte1]: 32
8576 12:11:36.895457
8577 12:11:36.895567 Set Vref, RX VrefLevel [Byte0]: 33
8578 12:11:36.898583 [Byte1]: 33
8579 12:11:36.902784
8580 12:11:36.902858 Set Vref, RX VrefLevel [Byte0]: 34
8581 12:11:36.905910 [Byte1]: 34
8582 12:11:36.910734
8583 12:11:36.910810 Set Vref, RX VrefLevel [Byte0]: 35
8584 12:11:36.913558 [Byte1]: 35
8585 12:11:36.918157
8586 12:11:36.918272 Set Vref, RX VrefLevel [Byte0]: 36
8587 12:11:36.921095 [Byte1]: 36
8588 12:11:36.925646
8589 12:11:36.925757 Set Vref, RX VrefLevel [Byte0]: 37
8590 12:11:36.928628 [Byte1]: 37
8591 12:11:36.933293
8592 12:11:36.933377 Set Vref, RX VrefLevel [Byte0]: 38
8593 12:11:36.936308 [Byte1]: 38
8594 12:11:36.940524
8595 12:11:36.940636 Set Vref, RX VrefLevel [Byte0]: 39
8596 12:11:36.944120 [Byte1]: 39
8597 12:11:36.948402
8598 12:11:36.948513 Set Vref, RX VrefLevel [Byte0]: 40
8599 12:11:36.951467 [Byte1]: 40
8600 12:11:36.956195
8601 12:11:36.956271 Set Vref, RX VrefLevel [Byte0]: 41
8602 12:11:36.959188 [Byte1]: 41
8603 12:11:36.963520
8604 12:11:36.963597 Set Vref, RX VrefLevel [Byte0]: 42
8605 12:11:36.966741 [Byte1]: 42
8606 12:11:36.971012
8607 12:11:36.971096 Set Vref, RX VrefLevel [Byte0]: 43
8608 12:11:36.974546 [Byte1]: 43
8609 12:11:36.978632
8610 12:11:36.978716 Set Vref, RX VrefLevel [Byte0]: 44
8611 12:11:36.981793 [Byte1]: 44
8612 12:11:36.986296
8613 12:11:36.986381 Set Vref, RX VrefLevel [Byte0]: 45
8614 12:11:36.989423 [Byte1]: 45
8615 12:11:36.993646
8616 12:11:36.993756 Set Vref, RX VrefLevel [Byte0]: 46
8617 12:11:36.997210 [Byte1]: 46
8618 12:11:37.001395
8619 12:11:37.001479 Set Vref, RX VrefLevel [Byte0]: 47
8620 12:11:37.004433 [Byte1]: 47
8621 12:11:37.009044
8622 12:11:37.009127 Set Vref, RX VrefLevel [Byte0]: 48
8623 12:11:37.012112 [Byte1]: 48
8624 12:11:37.016234
8625 12:11:37.016318 Set Vref, RX VrefLevel [Byte0]: 49
8626 12:11:37.019951 [Byte1]: 49
8627 12:11:37.023889
8628 12:11:37.023994 Set Vref, RX VrefLevel [Byte0]: 50
8629 12:11:37.027344 [Byte1]: 50
8630 12:11:37.031678
8631 12:11:37.031781 Set Vref, RX VrefLevel [Byte0]: 51
8632 12:11:37.034987 [Byte1]: 51
8633 12:11:37.039195
8634 12:11:37.039279 Set Vref, RX VrefLevel [Byte0]: 52
8635 12:11:37.042710 [Byte1]: 52
8636 12:11:37.046847
8637 12:11:37.046940 Set Vref, RX VrefLevel [Byte0]: 53
8638 12:11:37.050051 [Byte1]: 53
8639 12:11:37.054459
8640 12:11:37.054544 Set Vref, RX VrefLevel [Byte0]: 54
8641 12:11:37.057464 [Byte1]: 54
8642 12:11:37.061676
8643 12:11:37.061762 Set Vref, RX VrefLevel [Byte0]: 55
8644 12:11:37.065347 [Byte1]: 55
8645 12:11:37.069443
8646 12:11:37.069557 Set Vref, RX VrefLevel [Byte0]: 56
8647 12:11:37.072951 [Byte1]: 56
8648 12:11:37.076979
8649 12:11:37.077065 Set Vref, RX VrefLevel [Byte0]: 57
8650 12:11:37.080602 [Byte1]: 57
8651 12:11:37.084620
8652 12:11:37.084706 Set Vref, RX VrefLevel [Byte0]: 58
8653 12:11:37.087860 [Byte1]: 58
8654 12:11:37.092337
8655 12:11:37.092423 Set Vref, RX VrefLevel [Byte0]: 59
8656 12:11:37.095432 [Byte1]: 59
8657 12:11:37.099570
8658 12:11:37.099656 Set Vref, RX VrefLevel [Byte0]: 60
8659 12:11:37.103068 [Byte1]: 60
8660 12:11:37.107296
8661 12:11:37.107383 Set Vref, RX VrefLevel [Byte0]: 61
8662 12:11:37.110400 [Byte1]: 61
8663 12:11:37.115106
8664 12:11:37.115192 Set Vref, RX VrefLevel [Byte0]: 62
8665 12:11:37.118400 [Byte1]: 62
8666 12:11:37.122596
8667 12:11:37.122680 Set Vref, RX VrefLevel [Byte0]: 63
8668 12:11:37.125933 [Byte1]: 63
8669 12:11:37.130062
8670 12:11:37.130140 Set Vref, RX VrefLevel [Byte0]: 64
8671 12:11:37.133560 [Byte1]: 64
8672 12:11:37.137497
8673 12:11:37.137572 Set Vref, RX VrefLevel [Byte0]: 65
8674 12:11:37.140959 [Byte1]: 65
8675 12:11:37.145217
8676 12:11:37.145301 Set Vref, RX VrefLevel [Byte0]: 66
8677 12:11:37.148349 [Byte1]: 66
8678 12:11:37.152867
8679 12:11:37.152941 Set Vref, RX VrefLevel [Byte0]: 67
8680 12:11:37.155922 [Byte1]: 67
8681 12:11:37.160180
8682 12:11:37.160266 Set Vref, RX VrefLevel [Byte0]: 68
8683 12:11:37.163998 [Byte1]: 68
8684 12:11:37.168149
8685 12:11:37.168224 Set Vref, RX VrefLevel [Byte0]: 69
8686 12:11:37.171121 [Byte1]: 69
8687 12:11:37.175792
8688 12:11:37.175865 Set Vref, RX VrefLevel [Byte0]: 70
8689 12:11:37.178870 [Byte1]: 70
8690 12:11:37.182903
8691 12:11:37.182993 Set Vref, RX VrefLevel [Byte0]: 71
8692 12:11:37.186477 [Byte1]: 71
8693 12:11:37.190620
8694 12:11:37.190704 Set Vref, RX VrefLevel [Byte0]: 72
8695 12:11:37.193975 [Byte1]: 72
8696 12:11:37.198410
8697 12:11:37.198498 Set Vref, RX VrefLevel [Byte0]: 73
8698 12:11:37.201509 [Byte1]: 73
8699 12:11:37.205758
8700 12:11:37.205844 Final RX Vref Byte 0 = 53 to rank0
8701 12:11:37.209262 Final RX Vref Byte 1 = 61 to rank0
8702 12:11:37.212344 Final RX Vref Byte 0 = 53 to rank1
8703 12:11:37.215932 Final RX Vref Byte 1 = 61 to rank1==
8704 12:11:37.218976 Dram Type= 6, Freq= 0, CH_1, rank 0
8705 12:11:37.225615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8706 12:11:37.225712 ==
8707 12:11:37.225783 DQS Delay:
8708 12:11:37.229095 DQS0 = 0, DQS1 = 0
8709 12:11:37.229182 DQM Delay:
8710 12:11:37.229250 DQM0 = 133, DQM1 = 129
8711 12:11:37.232150 DQ Delay:
8712 12:11:37.235685 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8713 12:11:37.238699 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8714 12:11:37.242239 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8715 12:11:37.245802 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8716 12:11:37.245911
8717 12:11:37.246008
8718 12:11:37.246100
8719 12:11:37.248651 [DramC_TX_OE_Calibration] TA2
8720 12:11:37.252011 Original DQ_B0 (3 6) =30, OEN = 27
8721 12:11:37.255516 Original DQ_B1 (3 6) =30, OEN = 27
8722 12:11:37.258585 24, 0x0, End_B0=24 End_B1=24
8723 12:11:37.258690 25, 0x0, End_B0=25 End_B1=25
8724 12:11:37.262080 26, 0x0, End_B0=26 End_B1=26
8725 12:11:37.265640 27, 0x0, End_B0=27 End_B1=27
8726 12:11:37.268785 28, 0x0, End_B0=28 End_B1=28
8727 12:11:37.271965 29, 0x0, End_B0=29 End_B1=29
8728 12:11:37.272079 30, 0x0, End_B0=30 End_B1=30
8729 12:11:37.275557 31, 0x4141, End_B0=30 End_B1=30
8730 12:11:37.278682 Byte0 end_step=30 best_step=27
8731 12:11:37.281762 Byte1 end_step=30 best_step=27
8732 12:11:37.285291 Byte0 TX OE(2T, 0.5T) = (3, 3)
8733 12:11:37.288299 Byte1 TX OE(2T, 0.5T) = (3, 3)
8734 12:11:37.288409
8735 12:11:37.288506
8736 12:11:37.294891 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8737 12:11:37.298549 CH1 RK0: MR19=303, MR18=1927
8738 12:11:37.304775 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8739 12:11:37.304862
8740 12:11:37.308401 ----->DramcWriteLeveling(PI) begin...
8741 12:11:37.308496 ==
8742 12:11:37.311903 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 12:11:37.315037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8744 12:11:37.315125 ==
8745 12:11:37.318092 Write leveling (Byte 0): 22 => 22
8746 12:11:37.321762 Write leveling (Byte 1): 28 => 28
8747 12:11:37.324904 DramcWriteLeveling(PI) end<-----
8748 12:11:37.325006
8749 12:11:37.325102 ==
8750 12:11:37.328029 Dram Type= 6, Freq= 0, CH_1, rank 1
8751 12:11:37.331597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8752 12:11:37.331711 ==
8753 12:11:37.334622 [Gating] SW mode calibration
8754 12:11:37.341331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8755 12:11:37.348059 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8756 12:11:37.351239 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 12:11:37.358219 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 12:11:37.361315 1 4 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8759 12:11:37.364435 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8760 12:11:37.371035 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 12:11:37.374582 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 12:11:37.377635 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 12:11:37.384359 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 12:11:37.387908 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 12:11:37.390892 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8766 12:11:37.397481 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8767 12:11:37.401020 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 0)
8768 12:11:37.403955 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8769 12:11:37.410514 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 12:11:37.414114 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 12:11:37.417211 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 12:11:37.423796 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 12:11:37.427394 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 12:11:37.430478 1 6 8 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8775 12:11:37.437226 1 6 12 | B1->B0 | 4646 3e3e | 0 1 | (0 0) (1 1)
8776 12:11:37.440546 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:11:37.443612 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 12:11:37.450215 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 12:11:37.453867 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 12:11:37.456918 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 12:11:37.463327 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 12:11:37.466899 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 12:11:37.470566 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:11:37.476706 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:11:37.480325 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:11:37.483421 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:11:37.490286 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:11:37.493293 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:11:37.496685 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:11:37.503339 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:11:37.506797 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:11:37.509908 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:11:37.516235 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:11:37.519836 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:11:37.522954 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 12:11:37.529759 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 12:11:37.532984 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 12:11:37.536296 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8799 12:11:37.543073 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8800 12:11:37.543188 Total UI for P1: 0, mck2ui 16
8801 12:11:37.546171 best dqsien dly found for B1: ( 1, 9, 8)
8802 12:11:37.552901 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 12:11:37.556026 Total UI for P1: 0, mck2ui 16
8804 12:11:37.559666 best dqsien dly found for B0: ( 1, 9, 10)
8805 12:11:37.562716 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8806 12:11:37.566153 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8807 12:11:37.566263
8808 12:11:37.569635 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8809 12:11:37.572613 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8810 12:11:37.575986 [Gating] SW calibration Done
8811 12:11:37.576104 ==
8812 12:11:37.579079 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 12:11:37.582305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 12:11:37.582392 ==
8815 12:11:37.585932 RX Vref Scan: 0
8816 12:11:37.586016
8817 12:11:37.589112 RX Vref 0 -> 0, step: 1
8818 12:11:37.589196
8819 12:11:37.589263 RX Delay 0 -> 252, step: 8
8820 12:11:37.595870 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8821 12:11:37.598997 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8822 12:11:37.602418 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8823 12:11:37.605590 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8824 12:11:37.608733 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8825 12:11:37.615677 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8826 12:11:37.618710 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8827 12:11:37.621818 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8828 12:11:37.625519 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8829 12:11:37.628687 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8830 12:11:37.635020 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8831 12:11:37.638646 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8832 12:11:37.641783 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8833 12:11:37.645037 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8834 12:11:37.651719 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8835 12:11:37.654717 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8836 12:11:37.654820 ==
8837 12:11:37.658521 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 12:11:37.661723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 12:11:37.661828 ==
8840 12:11:37.661923 DQS Delay:
8841 12:11:37.664755 DQS0 = 0, DQS1 = 0
8842 12:11:37.664860 DQM Delay:
8843 12:11:37.668287 DQM0 = 136, DQM1 = 132
8844 12:11:37.668386 DQ Delay:
8845 12:11:37.671274 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8846 12:11:37.674692 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8847 12:11:37.678147 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8848 12:11:37.684708 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8849 12:11:37.684818
8850 12:11:37.684913
8851 12:11:37.685004 ==
8852 12:11:37.687875 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 12:11:37.691085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 12:11:37.691172 ==
8855 12:11:37.691242
8856 12:11:37.691305
8857 12:11:37.694721 TX Vref Scan disable
8858 12:11:37.694808 == TX Byte 0 ==
8859 12:11:37.701205 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8860 12:11:37.704179 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8861 12:11:37.704266 == TX Byte 1 ==
8862 12:11:37.711025 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8863 12:11:37.714581 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8864 12:11:37.714697 ==
8865 12:11:37.717506 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 12:11:37.720588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 12:11:37.724139 ==
8868 12:11:37.736705
8869 12:11:37.739838 TX Vref early break, caculate TX vref
8870 12:11:37.742981 TX Vref=16, minBit 9, minWin=22, winSum=384
8871 12:11:37.746584 TX Vref=18, minBit 9, minWin=22, winSum=387
8872 12:11:37.749560 TX Vref=20, minBit 9, minWin=23, winSum=396
8873 12:11:37.753099 TX Vref=22, minBit 9, minWin=24, winSum=404
8874 12:11:37.756106 TX Vref=24, minBit 12, minWin=24, winSum=417
8875 12:11:37.762724 TX Vref=26, minBit 10, minWin=24, winSum=416
8876 12:11:37.766359 TX Vref=28, minBit 10, minWin=24, winSum=420
8877 12:11:37.769583 TX Vref=30, minBit 8, minWin=25, winSum=414
8878 12:11:37.772516 TX Vref=32, minBit 10, minWin=24, winSum=411
8879 12:11:37.776072 TX Vref=34, minBit 9, minWin=24, winSum=399
8880 12:11:37.782535 TX Vref=36, minBit 8, minWin=22, winSum=390
8881 12:11:37.785907 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 30
8882 12:11:37.786016
8883 12:11:37.788924 Final TX Range 0 Vref 30
8884 12:11:37.789029
8885 12:11:37.789126 ==
8886 12:11:37.792717 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 12:11:37.798882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 12:11:37.798995 ==
8889 12:11:37.799093
8890 12:11:37.799186
8891 12:11:37.799277 TX Vref Scan disable
8892 12:11:37.806187 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8893 12:11:37.806274 == TX Byte 0 ==
8894 12:11:37.809206 u2DelayCellOfst[0]=16 cells (5 PI)
8895 12:11:37.812743 u2DelayCellOfst[1]=13 cells (4 PI)
8896 12:11:37.815748 u2DelayCellOfst[2]=0 cells (0 PI)
8897 12:11:37.819417 u2DelayCellOfst[3]=6 cells (2 PI)
8898 12:11:37.822705 u2DelayCellOfst[4]=10 cells (3 PI)
8899 12:11:37.825843 u2DelayCellOfst[5]=20 cells (6 PI)
8900 12:11:37.829322 u2DelayCellOfst[6]=20 cells (6 PI)
8901 12:11:37.832366 u2DelayCellOfst[7]=6 cells (2 PI)
8902 12:11:37.835584 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8903 12:11:37.839204 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8904 12:11:37.842411 == TX Byte 1 ==
8905 12:11:37.845544 u2DelayCellOfst[8]=0 cells (0 PI)
8906 12:11:37.848807 u2DelayCellOfst[9]=6 cells (2 PI)
8907 12:11:37.851858 u2DelayCellOfst[10]=10 cells (3 PI)
8908 12:11:37.855391 u2DelayCellOfst[11]=6 cells (2 PI)
8909 12:11:37.858968 u2DelayCellOfst[12]=16 cells (5 PI)
8910 12:11:37.861775 u2DelayCellOfst[13]=20 cells (6 PI)
8911 12:11:37.865427 u2DelayCellOfst[14]=20 cells (6 PI)
8912 12:11:37.868557 u2DelayCellOfst[15]=20 cells (6 PI)
8913 12:11:37.871649 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8914 12:11:37.875445 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8915 12:11:37.878549 DramC Write-DBI on
8916 12:11:37.878681 ==
8917 12:11:37.881616 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 12:11:37.885236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 12:11:37.885321 ==
8920 12:11:37.885451
8921 12:11:37.885536
8922 12:11:37.888600 TX Vref Scan disable
8923 12:11:37.888733 == TX Byte 0 ==
8924 12:11:37.894817 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8925 12:11:37.894922 == TX Byte 1 ==
8926 12:11:37.901469 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8927 12:11:37.901557 DramC Write-DBI off
8928 12:11:37.901626
8929 12:11:37.901689 [DATLAT]
8930 12:11:37.904776 Freq=1600, CH1 RK1
8931 12:11:37.904877
8932 12:11:37.904943 DATLAT Default: 0xf
8933 12:11:37.908528 0, 0xFFFF, sum = 0
8934 12:11:37.911552 1, 0xFFFF, sum = 0
8935 12:11:37.911672 2, 0xFFFF, sum = 0
8936 12:11:37.915002 3, 0xFFFF, sum = 0
8937 12:11:37.915082 4, 0xFFFF, sum = 0
8938 12:11:37.917998 5, 0xFFFF, sum = 0
8939 12:11:37.918077 6, 0xFFFF, sum = 0
8940 12:11:37.921229 7, 0xFFFF, sum = 0
8941 12:11:37.921316 8, 0xFFFF, sum = 0
8942 12:11:37.924874 9, 0xFFFF, sum = 0
8943 12:11:37.924980 10, 0xFFFF, sum = 0
8944 12:11:37.927868 11, 0xFFFF, sum = 0
8945 12:11:37.927975 12, 0xFFFF, sum = 0
8946 12:11:37.931365 13, 0xFFFF, sum = 0
8947 12:11:37.931472 14, 0x0, sum = 1
8948 12:11:37.934529 15, 0x0, sum = 2
8949 12:11:37.934612 16, 0x0, sum = 3
8950 12:11:37.937676 17, 0x0, sum = 4
8951 12:11:37.937798 best_step = 15
8952 12:11:37.937898
8953 12:11:37.937990 ==
8954 12:11:37.941381 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 12:11:37.947484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 12:11:37.947601 ==
8957 12:11:37.947705 RX Vref Scan: 0
8958 12:11:37.947823
8959 12:11:37.950751 RX Vref 0 -> 0, step: 1
8960 12:11:37.950854
8961 12:11:37.954501 RX Delay 19 -> 252, step: 4
8962 12:11:37.957550 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8963 12:11:37.961072 iDelay=195, Bit 1, Center 128 (83 ~ 174) 92
8964 12:11:37.964054 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8965 12:11:37.970743 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8966 12:11:37.974003 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8967 12:11:37.977717 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8968 12:11:37.980829 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8969 12:11:37.983764 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8970 12:11:37.990691 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8971 12:11:37.993709 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8972 12:11:37.997196 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8973 12:11:38.000662 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8974 12:11:38.003670 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8975 12:11:38.010618 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8976 12:11:38.013702 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8977 12:11:38.016681 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8978 12:11:38.016795 ==
8979 12:11:38.020216 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 12:11:38.023473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 12:11:38.023590 ==
8982 12:11:38.026998 DQS Delay:
8983 12:11:38.027101 DQS0 = 0, DQS1 = 0
8984 12:11:38.030069 DQM Delay:
8985 12:11:38.030173 DQM0 = 133, DQM1 = 129
8986 12:11:38.033392 DQ Delay:
8987 12:11:38.036971 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =130
8988 12:11:38.040059 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
8989 12:11:38.043283 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8990 12:11:38.046888 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
8991 12:11:38.046988
8992 12:11:38.047080
8993 12:11:38.047172
8994 12:11:38.049953 [DramC_TX_OE_Calibration] TA2
8995 12:11:38.053626 Original DQ_B0 (3 6) =30, OEN = 27
8996 12:11:38.056651 Original DQ_B1 (3 6) =30, OEN = 27
8997 12:11:38.056748 24, 0x0, End_B0=24 End_B1=24
8998 12:11:38.060333 25, 0x0, End_B0=25 End_B1=25
8999 12:11:38.063282 26, 0x0, End_B0=26 End_B1=26
9000 12:11:38.066857 27, 0x0, End_B0=27 End_B1=27
9001 12:11:38.069730 28, 0x0, End_B0=28 End_B1=28
9002 12:11:38.069850 29, 0x0, End_B0=29 End_B1=29
9003 12:11:38.073274 30, 0x0, End_B0=30 End_B1=30
9004 12:11:38.076415 31, 0x4545, End_B0=30 End_B1=30
9005 12:11:38.080091 Byte0 end_step=30 best_step=27
9006 12:11:38.083223 Byte1 end_step=30 best_step=27
9007 12:11:38.086815 Byte0 TX OE(2T, 0.5T) = (3, 3)
9008 12:11:38.086900 Byte1 TX OE(2T, 0.5T) = (3, 3)
9009 12:11:38.086970
9010 12:11:38.089938
9011 12:11:38.096295 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9012 12:11:38.099746 CH1 RK1: MR19=303, MR18=1B06
9013 12:11:38.106636 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9014 12:11:38.109529 [RxdqsGatingPostProcess] freq 1600
9015 12:11:38.112999 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9016 12:11:38.116012 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 12:11:38.119733 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 12:11:38.122745 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 12:11:38.126353 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 12:11:38.129430 best DQS0 dly(2T, 0.5T) = (1, 1)
9021 12:11:38.132983 best DQS1 dly(2T, 0.5T) = (1, 1)
9022 12:11:38.136032 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9023 12:11:38.139468 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9024 12:11:38.142554 Pre-setting of DQS Precalculation
9025 12:11:38.146331 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9026 12:11:38.152568 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9027 12:11:38.159314 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9028 12:11:38.159401
9029 12:11:38.162475
9030 12:11:38.162563 [Calibration Summary] 3200 Mbps
9031 12:11:38.165999 CH 0, Rank 0
9032 12:11:38.166119 SW Impedance : PASS
9033 12:11:38.169062 DUTY Scan : NO K
9034 12:11:38.172686 ZQ Calibration : PASS
9035 12:11:38.172802 Jitter Meter : NO K
9036 12:11:38.175643 CBT Training : PASS
9037 12:11:38.179349 Write leveling : PASS
9038 12:11:38.179462 RX DQS gating : PASS
9039 12:11:38.182446 RX DQ/DQS(RDDQC) : PASS
9040 12:11:38.185600 TX DQ/DQS : PASS
9041 12:11:38.185715 RX DATLAT : PASS
9042 12:11:38.188868 RX DQ/DQS(Engine): PASS
9043 12:11:38.192405 TX OE : PASS
9044 12:11:38.192521 All Pass.
9045 12:11:38.192619
9046 12:11:38.192711 CH 0, Rank 1
9047 12:11:38.195829 SW Impedance : PASS
9048 12:11:38.198828 DUTY Scan : NO K
9049 12:11:38.198919 ZQ Calibration : PASS
9050 12:11:38.202149 Jitter Meter : NO K
9051 12:11:38.205597 CBT Training : PASS
9052 12:11:38.205705 Write leveling : PASS
9053 12:11:38.208978 RX DQS gating : PASS
9054 12:11:38.211889 RX DQ/DQS(RDDQC) : PASS
9055 12:11:38.211992 TX DQ/DQS : PASS
9056 12:11:38.215354 RX DATLAT : PASS
9057 12:11:38.215430 RX DQ/DQS(Engine): PASS
9058 12:11:38.218458 TX OE : PASS
9059 12:11:38.218531 All Pass.
9060 12:11:38.218594
9061 12:11:38.222051 CH 1, Rank 0
9062 12:11:38.225078 SW Impedance : PASS
9063 12:11:38.225151 DUTY Scan : NO K
9064 12:11:38.228546 ZQ Calibration : PASS
9065 12:11:38.228648 Jitter Meter : NO K
9066 12:11:38.232086 CBT Training : PASS
9067 12:11:38.235104 Write leveling : PASS
9068 12:11:38.235213 RX DQS gating : PASS
9069 12:11:38.238284 RX DQ/DQS(RDDQC) : PASS
9070 12:11:38.241807 TX DQ/DQS : PASS
9071 12:11:38.241881 RX DATLAT : PASS
9072 12:11:38.244793 RX DQ/DQS(Engine): PASS
9073 12:11:38.248438 TX OE : PASS
9074 12:11:38.248535 All Pass.
9075 12:11:38.248629
9076 12:11:38.248721 CH 1, Rank 1
9077 12:11:38.251520 SW Impedance : PASS
9078 12:11:38.255147 DUTY Scan : NO K
9079 12:11:38.255244 ZQ Calibration : PASS
9080 12:11:38.258282 Jitter Meter : NO K
9081 12:11:38.261431 CBT Training : PASS
9082 12:11:38.261504 Write leveling : PASS
9083 12:11:38.265052 RX DQS gating : PASS
9084 12:11:38.268059 RX DQ/DQS(RDDQC) : PASS
9085 12:11:38.268129 TX DQ/DQS : PASS
9086 12:11:38.271512 RX DATLAT : PASS
9087 12:11:38.275035 RX DQ/DQS(Engine): PASS
9088 12:11:38.275152 TX OE : PASS
9089 12:11:38.275274 All Pass.
9090 12:11:38.278158
9091 12:11:38.278230 DramC Write-DBI on
9092 12:11:38.281249 PER_BANK_REFRESH: Hybrid Mode
9093 12:11:38.281321 TX_TRACKING: ON
9094 12:11:38.291119 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9095 12:11:38.297852 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9096 12:11:38.307700 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9097 12:11:38.311079 [FAST_K] Save calibration result to emmc
9098 12:11:38.314592 sync common calibartion params.
9099 12:11:38.314669 sync cbt_mode0:1, 1:1
9100 12:11:38.318002 dram_init: ddr_geometry: 2
9101 12:11:38.320960 dram_init: ddr_geometry: 2
9102 12:11:38.321057 dram_init: ddr_geometry: 2
9103 12:11:38.324568 0:dram_rank_size:100000000
9104 12:11:38.327553 1:dram_rank_size:100000000
9105 12:11:38.334616 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9106 12:11:38.334731 DFS_SHUFFLE_HW_MODE: ON
9107 12:11:38.337706 dramc_set_vcore_voltage set vcore to 725000
9108 12:11:38.340923 Read voltage for 1600, 0
9109 12:11:38.341020 Vio18 = 0
9110 12:11:38.344530 Vcore = 725000
9111 12:11:38.344613 Vdram = 0
9112 12:11:38.344679 Vddq = 0
9113 12:11:38.347585 Vmddr = 0
9114 12:11:38.347667 switch to 3200 Mbps bootup
9115 12:11:38.350733 [DramcRunTimeConfig]
9116 12:11:38.350817 PHYPLL
9117 12:11:38.354391 DPM_CONTROL_AFTERK: ON
9118 12:11:38.354473 PER_BANK_REFRESH: ON
9119 12:11:38.357546 REFRESH_OVERHEAD_REDUCTION: ON
9120 12:11:38.360519 CMD_PICG_NEW_MODE: OFF
9121 12:11:38.360627 XRTWTW_NEW_MODE: ON
9122 12:11:38.364181 XRTRTR_NEW_MODE: ON
9123 12:11:38.364264 TX_TRACKING: ON
9124 12:11:38.367383 RDSEL_TRACKING: OFF
9125 12:11:38.370523 DQS Precalculation for DVFS: ON
9126 12:11:38.370606 RX_TRACKING: OFF
9127 12:11:38.374116 HW_GATING DBG: ON
9128 12:11:38.374199 ZQCS_ENABLE_LP4: ON
9129 12:11:38.377153 RX_PICG_NEW_MODE: ON
9130 12:11:38.377252 TX_PICG_NEW_MODE: ON
9131 12:11:38.380603 ENABLE_RX_DCM_DPHY: ON
9132 12:11:38.383755 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9133 12:11:38.386968 DUMMY_READ_FOR_TRACKING: OFF
9134 12:11:38.387051 !!! SPM_CONTROL_AFTERK: OFF
9135 12:11:38.390687 !!! SPM could not control APHY
9136 12:11:38.393729 IMPEDANCE_TRACKING: ON
9137 12:11:38.393812 TEMP_SENSOR: ON
9138 12:11:38.396756 HW_SAVE_FOR_SR: OFF
9139 12:11:38.400381 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9140 12:11:38.403316 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9141 12:11:38.406807 Read ODT Tracking: ON
9142 12:11:38.406891 Refresh Rate DeBounce: ON
9143 12:11:38.410126 DFS_NO_QUEUE_FLUSH: ON
9144 12:11:38.413466 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9145 12:11:38.416478 ENABLE_DFS_RUNTIME_MRW: OFF
9146 12:11:38.416561 DDR_RESERVE_NEW_MODE: ON
9147 12:11:38.420388 MR_CBT_SWITCH_FREQ: ON
9148 12:11:38.423310 =========================
9149 12:11:38.440605 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9150 12:11:38.444170 dram_init: ddr_geometry: 2
9151 12:11:38.462654 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9152 12:11:38.465653 dram_init: dram init end (result: 0)
9153 12:11:38.472545 DRAM-K: Full calibration passed in 24501 msecs
9154 12:11:38.475580 MRC: failed to locate region type 0.
9155 12:11:38.475664 DRAM rank0 size:0x100000000,
9156 12:11:38.479185 DRAM rank1 size=0x100000000
9157 12:11:38.488742 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9158 12:11:38.495370 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9159 12:11:38.501967 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9160 12:11:38.512056 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9161 12:11:38.512182 DRAM rank0 size:0x100000000,
9162 12:11:38.515166 DRAM rank1 size=0x100000000
9163 12:11:38.515249 CBMEM:
9164 12:11:38.518598 IMD: root @ 0xfffff000 254 entries.
9165 12:11:38.521952 IMD: root @ 0xffffec00 62 entries.
9166 12:11:38.525344 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9167 12:11:38.531802 WARNING: RO_VPD is uninitialized or empty.
9168 12:11:38.534840 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9169 12:11:38.542567 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9170 12:11:38.555356 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9171 12:11:38.566730 BS: romstage times (exec / console): total (unknown) / 24002 ms
9172 12:11:38.566814
9173 12:11:38.566881
9174 12:11:38.576659 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9175 12:11:38.580160 ARM64: Exception handlers installed.
9176 12:11:38.583157 ARM64: Testing exception
9177 12:11:38.586150 ARM64: Done test exception
9178 12:11:38.586234 Enumerating buses...
9179 12:11:38.589737 Show all devs... Before device enumeration.
9180 12:11:38.592785 Root Device: enabled 1
9181 12:11:38.596404 CPU_CLUSTER: 0: enabled 1
9182 12:11:38.596516 CPU: 00: enabled 1
9183 12:11:38.599569 Compare with tree...
9184 12:11:38.599653 Root Device: enabled 1
9185 12:11:38.602689 CPU_CLUSTER: 0: enabled 1
9186 12:11:38.606116 CPU: 00: enabled 1
9187 12:11:38.606202 Root Device scanning...
9188 12:11:38.609192 scan_static_bus for Root Device
9189 12:11:38.612701 CPU_CLUSTER: 0 enabled
9190 12:11:38.616193 scan_static_bus for Root Device done
9191 12:11:38.619495 scan_bus: bus Root Device finished in 8 msecs
9192 12:11:38.619582 done
9193 12:11:38.625884 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9194 12:11:38.629149 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9195 12:11:38.635893 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9196 12:11:38.642166 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9197 12:11:38.642252 Allocating resources...
9198 12:11:38.645547 Reading resources...
9199 12:11:38.648815 Root Device read_resources bus 0 link: 0
9200 12:11:38.652437 DRAM rank0 size:0x100000000,
9201 12:11:38.652520 DRAM rank1 size=0x100000000
9202 12:11:38.659049 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9203 12:11:38.659148 CPU: 00 missing read_resources
9204 12:11:38.665156 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9205 12:11:38.668310 Root Device read_resources bus 0 link: 0 done
9206 12:11:38.671729 Done reading resources.
9207 12:11:38.675394 Show resources in subtree (Root Device)...After reading.
9208 12:11:38.678552 Root Device child on link 0 CPU_CLUSTER: 0
9209 12:11:38.681671 CPU_CLUSTER: 0 child on link 0 CPU: 00
9210 12:11:38.691378 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9211 12:11:38.691488 CPU: 00
9212 12:11:38.697843 Root Device assign_resources, bus 0 link: 0
9213 12:11:38.701614 CPU_CLUSTER: 0 missing set_resources
9214 12:11:38.704744 Root Device assign_resources, bus 0 link: 0 done
9215 12:11:38.707795 Done setting resources.
9216 12:11:38.711391 Show resources in subtree (Root Device)...After assigning values.
9217 12:11:38.718062 Root Device child on link 0 CPU_CLUSTER: 0
9218 12:11:38.721384 CPU_CLUSTER: 0 child on link 0 CPU: 00
9219 12:11:38.727727 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9220 12:11:38.730976 CPU: 00
9221 12:11:38.731069 Done allocating resources.
9222 12:11:38.737912 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9223 12:11:38.738011 Enabling resources...
9224 12:11:38.740959 done.
9225 12:11:38.744079 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9226 12:11:38.747641 Initializing devices...
9227 12:11:38.747725 Root Device init
9228 12:11:38.750736 init hardware done!
9229 12:11:38.754339 0x00000018: ctrlr->caps
9230 12:11:38.754425 52.000 MHz: ctrlr->f_max
9231 12:11:38.757440 0.400 MHz: ctrlr->f_min
9232 12:11:38.760595 0x40ff8080: ctrlr->voltages
9233 12:11:38.760722 sclk: 390625
9234 12:11:38.760854 Bus Width = 1
9235 12:11:38.764104 sclk: 390625
9236 12:11:38.764193 Bus Width = 1
9237 12:11:38.767209 Early init status = 3
9238 12:11:38.770436 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9239 12:11:38.774564 in-header: 03 fc 00 00 01 00 00 00
9240 12:11:38.778220 in-data: 00
9241 12:11:38.781352 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9242 12:11:38.787022 in-header: 03 fd 00 00 00 00 00 00
9243 12:11:38.790179 in-data:
9244 12:11:38.793582 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9245 12:11:38.798132 in-header: 03 fc 00 00 01 00 00 00
9246 12:11:38.801117 in-data: 00
9247 12:11:38.804644 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9248 12:11:38.810368 in-header: 03 fd 00 00 00 00 00 00
9249 12:11:38.813280 in-data:
9250 12:11:38.816888 [SSUSB] Setting up USB HOST controller...
9251 12:11:38.820030 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9252 12:11:38.823618 [SSUSB] phy power-on done.
9253 12:11:38.827119 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9254 12:11:38.833475 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9255 12:11:38.836744 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9256 12:11:38.843490 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9257 12:11:38.849532 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9258 12:11:38.856302 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9259 12:11:38.862986 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9260 12:11:38.869547 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9261 12:11:38.873105 SPM: binary array size = 0x9dc
9262 12:11:38.876304 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9263 12:11:38.882920 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9264 12:11:38.889507 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9265 12:11:38.896000 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9266 12:11:38.899490 configure_display: Starting display init
9267 12:11:38.933543 anx7625_power_on_init: Init interface.
9268 12:11:38.936491 anx7625_disable_pd_protocol: Disabled PD feature.
9269 12:11:38.939791 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9270 12:11:38.967832 anx7625_start_dp_work: Secure OCM version=00
9271 12:11:38.970845 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9272 12:11:38.985732 sp_tx_get_edid_block: EDID Block = 1
9273 12:11:39.088455 Extracted contents:
9274 12:11:39.091560 header: 00 ff ff ff ff ff ff 00
9275 12:11:39.095207 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9276 12:11:39.098306 version: 01 04
9277 12:11:39.101386 basic params: 95 1f 11 78 0a
9278 12:11:39.104937 chroma info: 76 90 94 55 54 90 27 21 50 54
9279 12:11:39.107905 established: 00 00 00
9280 12:11:39.114924 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9281 12:11:39.121196 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9282 12:11:39.124942 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9283 12:11:39.131348 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9284 12:11:39.137523 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9285 12:11:39.141124 extensions: 00
9286 12:11:39.141207 checksum: fb
9287 12:11:39.141317
9288 12:11:39.147532 Manufacturer: IVO Model 57d Serial Number 0
9289 12:11:39.147617 Made week 0 of 2020
9290 12:11:39.151115 EDID version: 1.4
9291 12:11:39.151198 Digital display
9292 12:11:39.154454 6 bits per primary color channel
9293 12:11:39.157426 DisplayPort interface
9294 12:11:39.157511 Maximum image size: 31 cm x 17 cm
9295 12:11:39.160998 Gamma: 220%
9296 12:11:39.161084 Check DPMS levels
9297 12:11:39.167443 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9298 12:11:39.170817 First detailed timing is preferred timing
9299 12:11:39.173945 Established timings supported:
9300 12:11:39.174026 Standard timings supported:
9301 12:11:39.177081 Detailed timings
9302 12:11:39.180515 Hex of detail: 383680a07038204018303c0035ae10000019
9303 12:11:39.187155 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9304 12:11:39.190338 0780 0798 07c8 0820 hborder 0
9305 12:11:39.193523 0438 043b 0447 0458 vborder 0
9306 12:11:39.197076 -hsync -vsync
9307 12:11:39.197160 Did detailed timing
9308 12:11:39.203504 Hex of detail: 000000000000000000000000000000000000
9309 12:11:39.207044 Manufacturer-specified data, tag 0
9310 12:11:39.209988 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9311 12:11:39.213653 ASCII string: InfoVision
9312 12:11:39.216550 Hex of detail: 000000fe00523134304e574635205248200a
9313 12:11:39.220054 ASCII string: R140NWF5 RH
9314 12:11:39.220136 Checksum
9315 12:11:39.223530 Checksum: 0xfb (valid)
9316 12:11:39.226518 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9317 12:11:39.229984 DSI data_rate: 832800000 bps
9318 12:11:39.236947 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9319 12:11:39.239846 anx7625_parse_edid: pixelclock(138800).
9320 12:11:39.243168 hactive(1920), hsync(48), hfp(24), hbp(88)
9321 12:11:39.246583 vactive(1080), vsync(12), vfp(3), vbp(17)
9322 12:11:39.249633 anx7625_dsi_config: config dsi.
9323 12:11:39.256509 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9324 12:11:39.270574 anx7625_dsi_config: success to config DSI
9325 12:11:39.274059 anx7625_dp_start: MIPI phy setup OK.
9326 12:11:39.277136 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9327 12:11:39.280575 mtk_ddp_mode_set invalid vrefresh 60
9328 12:11:39.283565 main_disp_path_setup
9329 12:11:39.283708 ovl_layer_smi_id_en
9330 12:11:39.287128 ovl_layer_smi_id_en
9331 12:11:39.287226 ccorr_config
9332 12:11:39.287315 aal_config
9333 12:11:39.290384 gamma_config
9334 12:11:39.290465 postmask_config
9335 12:11:39.293560 dither_config
9336 12:11:39.296713 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9337 12:11:39.303539 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9338 12:11:39.306595 Root Device init finished in 555 msecs
9339 12:11:39.310042 CPU_CLUSTER: 0 init
9340 12:11:39.316521 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9341 12:11:39.323338 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9342 12:11:39.323420 APU_MBOX 0x190000b0 = 0x10001
9343 12:11:39.326346 APU_MBOX 0x190001b0 = 0x10001
9344 12:11:39.329515 APU_MBOX 0x190005b0 = 0x10001
9345 12:11:39.333166 APU_MBOX 0x190006b0 = 0x10001
9346 12:11:39.339313 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9347 12:11:39.349426 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9348 12:11:39.361827 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9349 12:11:39.368326 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9350 12:11:39.380047 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9351 12:11:39.389198 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9352 12:11:39.392323 CPU_CLUSTER: 0 init finished in 81 msecs
9353 12:11:39.395990 Devices initialized
9354 12:11:39.399059 Show all devs... After init.
9355 12:11:39.399142 Root Device: enabled 1
9356 12:11:39.402203 CPU_CLUSTER: 0: enabled 1
9357 12:11:39.405767 CPU: 00: enabled 1
9358 12:11:39.408932 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9359 12:11:39.412117 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9360 12:11:39.415730 ELOG: NV offset 0x57f000 size 0x1000
9361 12:11:39.422323 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9362 12:11:39.428688 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9363 12:11:39.432053 ELOG: Event(17) added with size 13 at 2023-06-06 12:11:42 UTC
9364 12:11:39.438730 out: cmd=0x121: 03 db 21 01 00 00 00 00
9365 12:11:39.441807 in-header: 03 2a 00 00 2c 00 00 00
9366 12:11:39.455112 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9367 12:11:39.458594 ELOG: Event(A1) added with size 10 at 2023-06-06 12:11:42 UTC
9368 12:11:39.464923 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9369 12:11:39.471335 ELOG: Event(A0) added with size 9 at 2023-06-06 12:11:42 UTC
9370 12:11:39.474632 elog_add_boot_reason: Logged dev mode boot
9371 12:11:39.481649 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9372 12:11:39.481735 Finalize devices...
9373 12:11:39.484654 Devices finalized
9374 12:11:39.487837 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9375 12:11:39.491341 Writing coreboot table at 0xffe64000
9376 12:11:39.497736 0. 000000000010a000-0000000000113fff: RAMSTAGE
9377 12:11:39.500915 1. 0000000040000000-00000000400fffff: RAM
9378 12:11:39.504556 2. 0000000040100000-000000004032afff: RAMSTAGE
9379 12:11:39.507682 3. 000000004032b000-00000000545fffff: RAM
9380 12:11:39.510881 4. 0000000054600000-000000005465ffff: BL31
9381 12:11:39.514455 5. 0000000054660000-00000000ffe63fff: RAM
9382 12:11:39.521041 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9383 12:11:39.523987 7. 0000000100000000-000000023fffffff: RAM
9384 12:11:39.527604 Passing 5 GPIOs to payload:
9385 12:11:39.530510 NAME | PORT | POLARITY | VALUE
9386 12:11:39.537135 EC in RW | 0x000000aa | low | undefined
9387 12:11:39.540788 EC interrupt | 0x00000005 | low | undefined
9388 12:11:39.546984 TPM interrupt | 0x000000ab | high | undefined
9389 12:11:39.550633 SD card detect | 0x00000011 | high | undefined
9390 12:11:39.553543 speaker enable | 0x00000093 | high | undefined
9391 12:11:39.556886 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9392 12:11:39.560891 in-header: 03 f9 00 00 02 00 00 00
9393 12:11:39.563796 in-data: 02 00
9394 12:11:39.567228 ADC[4]: Raw value=901032 ID=7
9395 12:11:39.570775 ADC[3]: Raw value=213179 ID=1
9396 12:11:39.570860 RAM Code: 0x71
9397 12:11:39.573772 ADC[6]: Raw value=74502 ID=0
9398 12:11:39.577507 ADC[5]: Raw value=212441 ID=1
9399 12:11:39.577593 SKU Code: 0x1
9400 12:11:39.583650 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9401 12:11:39.583735 coreboot table: 964 bytes.
9402 12:11:39.587070 IMD ROOT 0. 0xfffff000 0x00001000
9403 12:11:39.590779 IMD SMALL 1. 0xffffe000 0x00001000
9404 12:11:39.593905 RO MCACHE 2. 0xffffc000 0x00001104
9405 12:11:39.597348 CONSOLE 3. 0xfff7c000 0x00080000
9406 12:11:39.600472 FMAP 4. 0xfff7b000 0x00000452
9407 12:11:39.603634 TIME STAMP 5. 0xfff7a000 0x00000910
9408 12:11:39.606715 VBOOT WORK 6. 0xfff66000 0x00014000
9409 12:11:39.610357 RAMOOPS 7. 0xffe66000 0x00100000
9410 12:11:39.613432 COREBOOT 8. 0xffe64000 0x00002000
9411 12:11:39.616598 IMD small region:
9412 12:11:39.620168 IMD ROOT 0. 0xffffec00 0x00000400
9413 12:11:39.623335 VPD 1. 0xffffeba0 0x0000004c
9414 12:11:39.626684 MMC STATUS 2. 0xffffeb80 0x00000004
9415 12:11:39.633280 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9416 12:11:39.633396 Probing TPM: done!
9417 12:11:39.640163 Connected to device vid:did:rid of 1ae0:0028:00
9418 12:11:39.646831 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9419 12:11:39.650448 Initialized TPM device CR50 revision 0
9420 12:11:39.653528 Checking cr50 for pending updates
9421 12:11:39.658878 Reading cr50 TPM mode
9422 12:11:39.667371 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9423 12:11:39.674178 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9424 12:11:39.714321 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9425 12:11:39.717341 Checking segment from ROM address 0x40100000
9426 12:11:39.720795 Checking segment from ROM address 0x4010001c
9427 12:11:39.727501 Loading segment from ROM address 0x40100000
9428 12:11:39.727615 code (compression=0)
9429 12:11:39.737489 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9430 12:11:39.744030 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9431 12:11:39.744138 it's not compressed!
9432 12:11:39.750801 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9433 12:11:39.757499 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9434 12:11:39.774669 Loading segment from ROM address 0x4010001c
9435 12:11:39.774778 Entry Point 0x80000000
9436 12:11:39.777762 Loaded segments
9437 12:11:39.781119 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9438 12:11:39.787789 Jumping to boot code at 0x80000000(0xffe64000)
9439 12:11:39.794439 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9440 12:11:39.801183 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9441 12:11:39.808920 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9442 12:11:39.812605 Checking segment from ROM address 0x40100000
9443 12:11:39.815740 Checking segment from ROM address 0x4010001c
9444 12:11:39.822552 Loading segment from ROM address 0x40100000
9445 12:11:39.822662 code (compression=1)
9446 12:11:39.828671 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9447 12:11:39.838899 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9448 12:11:39.838986 using LZMA
9449 12:11:39.847468 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9450 12:11:39.853655 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9451 12:11:39.857243 Loading segment from ROM address 0x4010001c
9452 12:11:39.857323 Entry Point 0x54601000
9453 12:11:39.860318 Loaded segments
9454 12:11:39.864046 NOTICE: MT8192 bl31_setup
9455 12:11:39.870994 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9456 12:11:39.874486 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9457 12:11:39.877493 WARNING: region 0:
9458 12:11:39.880920 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 12:11:39.881001 WARNING: region 1:
9460 12:11:39.887807 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9461 12:11:39.890937 WARNING: region 2:
9462 12:11:39.894091 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9463 12:11:39.897539 WARNING: region 3:
9464 12:11:39.901201 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 12:11:39.904248 WARNING: region 4:
9466 12:11:39.910857 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9467 12:11:39.910944 WARNING: region 5:
9468 12:11:39.914016 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 12:11:39.917506 WARNING: region 6:
9470 12:11:39.920503 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 12:11:39.924164 WARNING: region 7:
9472 12:11:39.927409 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 12:11:39.934107 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9474 12:11:39.937619 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9475 12:11:39.941061 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9476 12:11:39.947581 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9477 12:11:39.950536 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9478 12:11:39.954154 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9479 12:11:39.960851 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9480 12:11:39.964057 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9481 12:11:39.970596 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9482 12:11:39.974056 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9483 12:11:39.977536 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9484 12:11:39.984122 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9485 12:11:39.987348 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9486 12:11:39.990700 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9487 12:11:39.996849 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9488 12:11:40.000646 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9489 12:11:40.007177 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9490 12:11:40.010290 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9491 12:11:40.013815 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9492 12:11:40.020613 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9493 12:11:40.023768 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9494 12:11:40.030461 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9495 12:11:40.033577 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9496 12:11:40.037181 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9497 12:11:40.043712 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9498 12:11:40.047057 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9499 12:11:40.053754 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9500 12:11:40.057172 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9501 12:11:40.060022 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9502 12:11:40.066782 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9503 12:11:40.070275 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9504 12:11:40.076717 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9505 12:11:40.080137 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9506 12:11:40.083637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9507 12:11:40.087083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9508 12:11:40.093224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9509 12:11:40.096679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9510 12:11:40.100238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9511 12:11:40.103312 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9512 12:11:40.106780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9513 12:11:40.113584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9514 12:11:40.117043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9515 12:11:40.120191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9516 12:11:40.126512 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9517 12:11:40.130123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9518 12:11:40.133188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9519 12:11:40.136705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9520 12:11:40.143039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9521 12:11:40.146723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9522 12:11:40.150024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9523 12:11:40.156449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9524 12:11:40.160006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9525 12:11:40.166561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9526 12:11:40.169656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9527 12:11:40.176455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9528 12:11:40.180029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9529 12:11:40.183012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9530 12:11:40.189546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9531 12:11:40.193057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9532 12:11:40.199527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9533 12:11:40.203073 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9534 12:11:40.209670 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9535 12:11:40.212669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9536 12:11:40.219618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9537 12:11:40.222603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9538 12:11:40.229237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9539 12:11:40.232869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9540 12:11:40.236047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9541 12:11:40.242676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9542 12:11:40.245882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9543 12:11:40.252456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9544 12:11:40.255961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9545 12:11:40.262601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9546 12:11:40.265761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9547 12:11:40.269196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9548 12:11:40.275816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9549 12:11:40.278793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9550 12:11:40.285456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9551 12:11:40.288939 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9552 12:11:40.295493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9553 12:11:40.298984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9554 12:11:40.305368 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9555 12:11:40.309026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9556 12:11:40.312030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9557 12:11:40.318529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9558 12:11:40.322140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9559 12:11:40.328639 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9560 12:11:40.331781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9561 12:11:40.338472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9562 12:11:40.341997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9563 12:11:40.345069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9564 12:11:40.352262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9565 12:11:40.355268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9566 12:11:40.362031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9567 12:11:40.365156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9568 12:11:40.371850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9569 12:11:40.375428 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9570 12:11:40.378354 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9571 12:11:40.381845 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9572 12:11:40.388595 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9573 12:11:40.391780 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9574 12:11:40.395277 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9575 12:11:40.401781 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9576 12:11:40.405305 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9577 12:11:40.411857 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9578 12:11:40.414997 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9579 12:11:40.418432 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9580 12:11:40.424715 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9581 12:11:40.428226 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9582 12:11:40.434963 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9583 12:11:40.438084 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9584 12:11:40.441689 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9585 12:11:40.447824 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9586 12:11:40.451534 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9587 12:11:40.458114 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9588 12:11:40.461264 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9589 12:11:40.464740 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9590 12:11:40.471535 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9591 12:11:40.475110 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9592 12:11:40.478324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9593 12:11:40.481744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9594 12:11:40.487941 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9595 12:11:40.491581 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9596 12:11:40.494663 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9597 12:11:40.501244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9598 12:11:40.504668 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9599 12:11:40.508064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9600 12:11:40.514708 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9601 12:11:40.518304 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9602 12:11:40.524367 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9603 12:11:40.527539 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9604 12:11:40.531127 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9605 12:11:40.537829 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9606 12:11:40.540936 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9607 12:11:40.547593 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9608 12:11:40.551277 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9609 12:11:40.554355 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9610 12:11:40.561034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9611 12:11:40.564149 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9612 12:11:40.567621 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9613 12:11:40.574268 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9614 12:11:40.577476 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9615 12:11:40.584265 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9616 12:11:40.587340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9617 12:11:40.590867 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9618 12:11:40.597402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9619 12:11:40.600973 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9620 12:11:40.607566 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9621 12:11:40.611195 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9622 12:11:40.614081 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9623 12:11:40.620635 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9624 12:11:40.624229 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9625 12:11:40.627617 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9626 12:11:40.634293 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9627 12:11:40.637106 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9628 12:11:40.643747 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9629 12:11:40.647369 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9630 12:11:40.654063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9631 12:11:40.657102 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9632 12:11:40.660536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9633 12:11:40.667272 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9634 12:11:40.670353 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9635 12:11:40.673656 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9636 12:11:40.680432 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9637 12:11:40.683520 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9638 12:11:40.690612 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9639 12:11:40.693509 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9640 12:11:40.697097 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9641 12:11:40.703587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9642 12:11:40.706910 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9643 12:11:40.713535 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9644 12:11:40.716594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9645 12:11:40.720017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9646 12:11:40.726676 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9647 12:11:40.730193 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9648 12:11:40.736986 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9649 12:11:40.739879 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9650 12:11:40.743433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9651 12:11:40.750141 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9652 12:11:40.753311 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9653 12:11:40.759933 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9654 12:11:40.762999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9655 12:11:40.766695 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9656 12:11:40.772914 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9657 12:11:40.776459 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9658 12:11:40.783095 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9659 12:11:40.786141 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9660 12:11:40.789678 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9661 12:11:40.796368 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9662 12:11:40.799499 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9663 12:11:40.805945 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9664 12:11:40.809467 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9665 12:11:40.815942 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9666 12:11:40.819445 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9667 12:11:40.822435 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9668 12:11:40.829490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9669 12:11:40.832468 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9670 12:11:40.839048 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9671 12:11:40.842578 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9672 12:11:40.846044 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9673 12:11:40.852664 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9674 12:11:40.855694 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9675 12:11:40.862441 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9676 12:11:40.865529 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9677 12:11:40.872344 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9678 12:11:40.875559 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9679 12:11:40.879096 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9680 12:11:40.885689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9681 12:11:40.888785 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9682 12:11:40.895476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9683 12:11:40.898574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9684 12:11:40.902054 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9685 12:11:40.908785 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9686 12:11:40.911721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9687 12:11:40.918540 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9688 12:11:40.921934 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9689 12:11:40.928271 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9690 12:11:40.931845 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9691 12:11:40.935000 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9692 12:11:40.941532 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9693 12:11:40.945159 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9694 12:11:40.951856 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9695 12:11:40.954906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9696 12:11:40.961614 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9697 12:11:40.965149 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9698 12:11:40.968162 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9699 12:11:40.974883 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9700 12:11:40.978027 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9701 12:11:40.984544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9702 12:11:40.988114 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9703 12:11:40.991119 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9704 12:11:40.994425 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9705 12:11:41.000997 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9706 12:11:41.004585 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9707 12:11:41.007662 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9708 12:11:41.014376 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9709 12:11:41.017734 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9710 12:11:41.020510 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9711 12:11:41.027300 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9712 12:11:41.030597 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9713 12:11:41.037264 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9714 12:11:41.040726 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9715 12:11:41.043705 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9716 12:11:41.050400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9717 12:11:41.053782 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9718 12:11:41.057227 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9719 12:11:41.063956 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9720 12:11:41.067151 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9721 12:11:41.070671 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9722 12:11:41.076757 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9723 12:11:41.080411 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9724 12:11:41.086573 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9725 12:11:41.089968 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9726 12:11:41.093611 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9727 12:11:41.099781 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9728 12:11:41.103372 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9729 12:11:41.106565 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9730 12:11:41.113325 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9731 12:11:41.116977 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9732 12:11:41.120004 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9733 12:11:41.126828 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9734 12:11:41.130023 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9735 12:11:41.136665 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9736 12:11:41.139945 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9737 12:11:41.143153 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9738 12:11:41.149662 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9739 12:11:41.153288 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9740 12:11:41.159749 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9741 12:11:41.162949 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9742 12:11:41.166037 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9743 12:11:41.169561 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9744 12:11:41.176088 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9745 12:11:41.179213 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9746 12:11:41.182833 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9747 12:11:41.185871 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9748 12:11:41.189339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9749 12:11:41.195724 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9750 12:11:41.199365 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9751 12:11:41.202473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9752 12:11:41.206197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9753 12:11:41.212646 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9754 12:11:41.216174 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9755 12:11:41.222543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9756 12:11:41.225608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9757 12:11:41.229225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9758 12:11:41.235665 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9759 12:11:41.239057 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9760 12:11:41.245640 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9761 12:11:41.248929 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9762 12:11:41.252210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9763 12:11:41.258687 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9764 12:11:41.262285 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9765 12:11:41.268535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9766 12:11:41.272027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9767 12:11:41.278751 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9768 12:11:41.281921 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9769 12:11:41.285554 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9770 12:11:41.291757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9771 12:11:41.295422 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9772 12:11:41.301645 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9773 12:11:41.305140 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9774 12:11:41.308358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9775 12:11:41.315072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9776 12:11:41.318358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9777 12:11:41.325052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9778 12:11:41.328073 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9779 12:11:41.331653 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9780 12:11:41.338234 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9781 12:11:41.341304 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9782 12:11:41.348335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9783 12:11:41.351164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9784 12:11:41.357990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9785 12:11:41.361145 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9786 12:11:41.364486 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9787 12:11:41.370948 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9788 12:11:41.374559 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9789 12:11:41.381415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9790 12:11:41.384461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9791 12:11:41.391053 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9792 12:11:41.394007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9793 12:11:41.397664 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9794 12:11:41.404112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9795 12:11:41.407597 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9796 12:11:41.414225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9797 12:11:41.417318 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9798 12:11:41.420533 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9799 12:11:41.427509 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9800 12:11:41.430617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9801 12:11:41.437194 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9802 12:11:41.440254 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9803 12:11:41.444022 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9804 12:11:41.450159 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9805 12:11:41.453620 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9806 12:11:41.460099 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9807 12:11:41.463415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9808 12:11:41.470075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9809 12:11:41.473478 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9810 12:11:41.476801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9811 12:11:41.483568 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9812 12:11:41.486786 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9813 12:11:41.493507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9814 12:11:41.496565 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9815 12:11:41.503009 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9816 12:11:41.506634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9817 12:11:41.509608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9818 12:11:41.516179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9819 12:11:41.519791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9820 12:11:41.525972 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9821 12:11:41.529696 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9822 12:11:41.532719 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9823 12:11:41.539464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9824 12:11:41.542532 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9825 12:11:41.549158 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9826 12:11:41.552682 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9827 12:11:41.558959 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9828 12:11:41.562385 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9829 12:11:41.565683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9830 12:11:41.572321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9831 12:11:41.575472 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9832 12:11:41.582262 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9833 12:11:41.585597 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9834 12:11:41.591949 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9835 12:11:41.595623 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9836 12:11:41.601855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9837 12:11:41.605396 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9838 12:11:41.608499 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9839 12:11:41.615384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9840 12:11:41.618375 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9841 12:11:41.625093 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9842 12:11:41.628318 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9843 12:11:41.635107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9844 12:11:41.638584 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9845 12:11:41.644736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9846 12:11:41.648269 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9847 12:11:41.652250 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9848 12:11:41.658440 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9849 12:11:41.661529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9850 12:11:41.667912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9851 12:11:41.671540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9852 12:11:41.677824 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9853 12:11:41.681091 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9854 12:11:41.687735 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9855 12:11:41.690984 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9856 12:11:41.694328 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9857 12:11:41.701324 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9858 12:11:41.704453 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9859 12:11:41.711036 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9860 12:11:41.714806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9861 12:11:41.720934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9862 12:11:41.724025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9863 12:11:41.730814 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9864 12:11:41.733869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9865 12:11:41.737582 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9866 12:11:41.744108 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9867 12:11:41.747163 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9868 12:11:41.753836 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9869 12:11:41.757040 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9870 12:11:41.763869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9871 12:11:41.767105 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9872 12:11:41.770688 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9873 12:11:41.777126 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9874 12:11:41.780344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9875 12:11:41.787169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9876 12:11:41.790324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9877 12:11:41.796954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9878 12:11:41.800136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9879 12:11:41.806753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9880 12:11:41.810451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9881 12:11:41.813532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9882 12:11:41.820152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9883 12:11:41.823622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9884 12:11:41.830292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9885 12:11:41.833335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9886 12:11:41.840143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9887 12:11:41.843214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9888 12:11:41.849551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9889 12:11:41.853117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9890 12:11:41.859675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9891 12:11:41.863225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9892 12:11:41.869461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9893 12:11:41.873094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9894 12:11:41.879369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9895 12:11:41.883003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9896 12:11:41.889668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9897 12:11:41.892966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9898 12:11:41.899567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9899 12:11:41.902487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9900 12:11:41.909202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9901 12:11:41.912423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9902 12:11:41.919045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9903 12:11:41.922586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9904 12:11:41.929069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9905 12:11:41.932706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9906 12:11:41.939342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9907 12:11:41.942473 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9908 12:11:41.945532 INFO: [APUAPC] vio 0
9909 12:11:41.949124 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9910 12:11:41.955675 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9911 12:11:41.958656 INFO: [APUAPC] D0_APC_0: 0x400510
9912 12:11:41.962085 INFO: [APUAPC] D0_APC_1: 0x0
9913 12:11:41.965120 INFO: [APUAPC] D0_APC_2: 0x1540
9914 12:11:41.965222 INFO: [APUAPC] D0_APC_3: 0x0
9915 12:11:41.968749 INFO: [APUAPC] D1_APC_0: 0xffffffff
9916 12:11:41.974952 INFO: [APUAPC] D1_APC_1: 0xffffffff
9917 12:11:41.978511 INFO: [APUAPC] D1_APC_2: 0x3fffff
9918 12:11:41.978614 INFO: [APUAPC] D1_APC_3: 0x0
9919 12:11:41.981958 INFO: [APUAPC] D2_APC_0: 0xffffffff
9920 12:11:41.985010 INFO: [APUAPC] D2_APC_1: 0xffffffff
9921 12:11:41.988577 INFO: [APUAPC] D2_APC_2: 0x3fffff
9922 12:11:41.991609 INFO: [APUAPC] D2_APC_3: 0x0
9923 12:11:41.995175 INFO: [APUAPC] D3_APC_0: 0xffffffff
9924 12:11:41.998136 INFO: [APUAPC] D3_APC_1: 0xffffffff
9925 12:11:42.001697 INFO: [APUAPC] D3_APC_2: 0x3fffff
9926 12:11:42.004706 INFO: [APUAPC] D3_APC_3: 0x0
9927 12:11:42.008100 INFO: [APUAPC] D4_APC_0: 0xffffffff
9928 12:11:42.011506 INFO: [APUAPC] D4_APC_1: 0xffffffff
9929 12:11:42.014484 INFO: [APUAPC] D4_APC_2: 0x3fffff
9930 12:11:42.017897 INFO: [APUAPC] D4_APC_3: 0x0
9931 12:11:42.021111 INFO: [APUAPC] D5_APC_0: 0xffffffff
9932 12:11:42.024596 INFO: [APUAPC] D5_APC_1: 0xffffffff
9933 12:11:42.028057 INFO: [APUAPC] D5_APC_2: 0x3fffff
9934 12:11:42.031165 INFO: [APUAPC] D5_APC_3: 0x0
9935 12:11:42.034772 INFO: [APUAPC] D6_APC_0: 0xffffffff
9936 12:11:42.038011 INFO: [APUAPC] D6_APC_1: 0xffffffff
9937 12:11:42.041039 INFO: [APUAPC] D6_APC_2: 0x3fffff
9938 12:11:42.044347 INFO: [APUAPC] D6_APC_3: 0x0
9939 12:11:42.047969 INFO: [APUAPC] D7_APC_0: 0xffffffff
9940 12:11:42.050992 INFO: [APUAPC] D7_APC_1: 0xffffffff
9941 12:11:42.054618 INFO: [APUAPC] D7_APC_2: 0x3fffff
9942 12:11:42.057808 INFO: [APUAPC] D7_APC_3: 0x0
9943 12:11:42.060968 INFO: [APUAPC] D8_APC_0: 0xffffffff
9944 12:11:42.064570 INFO: [APUAPC] D8_APC_1: 0xffffffff
9945 12:11:42.067592 INFO: [APUAPC] D8_APC_2: 0x3fffff
9946 12:11:42.070813 INFO: [APUAPC] D8_APC_3: 0x0
9947 12:11:42.074296 INFO: [APUAPC] D9_APC_0: 0xffffffff
9948 12:11:42.077405 INFO: [APUAPC] D9_APC_1: 0xffffffff
9949 12:11:42.080541 INFO: [APUAPC] D9_APC_2: 0x3fffff
9950 12:11:42.083985 INFO: [APUAPC] D9_APC_3: 0x0
9951 12:11:42.087502 INFO: [APUAPC] D10_APC_0: 0xffffffff
9952 12:11:42.090557 INFO: [APUAPC] D10_APC_1: 0xffffffff
9953 12:11:42.093638 INFO: [APUAPC] D10_APC_2: 0x3fffff
9954 12:11:42.097413 INFO: [APUAPC] D10_APC_3: 0x0
9955 12:11:42.100424 INFO: [APUAPC] D11_APC_0: 0xffffffff
9956 12:11:42.103878 INFO: [APUAPC] D11_APC_1: 0xffffffff
9957 12:11:42.107427 INFO: [APUAPC] D11_APC_2: 0x3fffff
9958 12:11:42.110473 INFO: [APUAPC] D11_APC_3: 0x0
9959 12:11:42.113745 INFO: [APUAPC] D12_APC_0: 0xffffffff
9960 12:11:42.117058 INFO: [APUAPC] D12_APC_1: 0xffffffff
9961 12:11:42.120492 INFO: [APUAPC] D12_APC_2: 0x3fffff
9962 12:11:42.123481 INFO: [APUAPC] D12_APC_3: 0x0
9963 12:11:42.126959 INFO: [APUAPC] D13_APC_0: 0xffffffff
9964 12:11:42.130432 INFO: [APUAPC] D13_APC_1: 0xffffffff
9965 12:11:42.133414 INFO: [APUAPC] D13_APC_2: 0x3fffff
9966 12:11:42.136943 INFO: [APUAPC] D13_APC_3: 0x0
9967 12:11:42.140487 INFO: [APUAPC] D14_APC_0: 0xffffffff
9968 12:11:42.143611 INFO: [APUAPC] D14_APC_1: 0xffffffff
9969 12:11:42.146748 INFO: [APUAPC] D14_APC_2: 0x3fffff
9970 12:11:42.149852 INFO: [APUAPC] D14_APC_3: 0x0
9971 12:11:42.153513 INFO: [APUAPC] D15_APC_0: 0xffffffff
9972 12:11:42.156700 INFO: [APUAPC] D15_APC_1: 0xffffffff
9973 12:11:42.159741 INFO: [APUAPC] D15_APC_2: 0x3fffff
9974 12:11:42.163366 INFO: [APUAPC] D15_APC_3: 0x0
9975 12:11:42.166598 INFO: [APUAPC] APC_CON: 0x4
9976 12:11:42.170116 INFO: [NOCDAPC] D0_APC_0: 0x0
9977 12:11:42.173299 INFO: [NOCDAPC] D0_APC_1: 0x0
9978 12:11:42.176714 INFO: [NOCDAPC] D1_APC_0: 0x0
9979 12:11:42.179711 INFO: [NOCDAPC] D1_APC_1: 0xfff
9980 12:11:42.179810 INFO: [NOCDAPC] D2_APC_0: 0x0
9981 12:11:42.183385 INFO: [NOCDAPC] D2_APC_1: 0xfff
9982 12:11:42.186503 INFO: [NOCDAPC] D3_APC_0: 0x0
9983 12:11:42.190061 INFO: [NOCDAPC] D3_APC_1: 0xfff
9984 12:11:42.193068 INFO: [NOCDAPC] D4_APC_0: 0x0
9985 12:11:42.196207 INFO: [NOCDAPC] D4_APC_1: 0xfff
9986 12:11:42.199863 INFO: [NOCDAPC] D5_APC_0: 0x0
9987 12:11:42.202987 INFO: [NOCDAPC] D5_APC_1: 0xfff
9988 12:11:42.206547 INFO: [NOCDAPC] D6_APC_0: 0x0
9989 12:11:42.209414 INFO: [NOCDAPC] D6_APC_1: 0xfff
9990 12:11:42.212901 INFO: [NOCDAPC] D7_APC_0: 0x0
9991 12:11:42.215940 INFO: [NOCDAPC] D7_APC_1: 0xfff
9992 12:11:42.216022 INFO: [NOCDAPC] D8_APC_0: 0x0
9993 12:11:42.219381 INFO: [NOCDAPC] D8_APC_1: 0xfff
9994 12:11:42.222752 INFO: [NOCDAPC] D9_APC_0: 0x0
9995 12:11:42.226093 INFO: [NOCDAPC] D9_APC_1: 0xfff
9996 12:11:42.229143 INFO: [NOCDAPC] D10_APC_0: 0x0
9997 12:11:42.232569 INFO: [NOCDAPC] D10_APC_1: 0xfff
9998 12:11:42.235981 INFO: [NOCDAPC] D11_APC_0: 0x0
9999 12:11:42.239270 INFO: [NOCDAPC] D11_APC_1: 0xfff
10000 12:11:42.242506 INFO: [NOCDAPC] D12_APC_0: 0x0
10001 12:11:42.245493 INFO: [NOCDAPC] D12_APC_1: 0xfff
10002 12:11:42.249052 INFO: [NOCDAPC] D13_APC_0: 0x0
10003 12:11:42.252232 INFO: [NOCDAPC] D13_APC_1: 0xfff
10004 12:11:42.255406 INFO: [NOCDAPC] D14_APC_0: 0x0
10005 12:11:42.259032 INFO: [NOCDAPC] D14_APC_1: 0xfff
10006 12:11:42.262240 INFO: [NOCDAPC] D15_APC_0: 0x0
10007 12:11:42.265347 INFO: [NOCDAPC] D15_APC_1: 0xfff
10008 12:11:42.265423 INFO: [NOCDAPC] APC_CON: 0x4
10009 12:11:42.268987 INFO: [APUAPC] set_apusys_apc done
10010 12:11:42.272105 INFO: [DEVAPC] devapc_init done
10011 12:11:42.278730 INFO: GICv3 without legacy support detected.
10012 12:11:42.282296 INFO: ARM GICv3 driver initialized in EL3
10013 12:11:42.285430 INFO: Maximum SPI INTID supported: 639
10014 12:11:42.288559 INFO: BL31: Initializing runtime services
10015 12:11:42.295296 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10016 12:11:42.298480 INFO: SPM: enable CPC mode
10017 12:11:42.302069 INFO: mcdi ready for mcusys-off-idle and system suspend
10018 12:11:42.308291 INFO: BL31: Preparing for EL3 exit to normal world
10019 12:11:42.311856 INFO: Entry point address = 0x80000000
10020 12:11:42.311939 INFO: SPSR = 0x8
10021 12:11:42.319062
10022 12:11:42.319144
10023 12:11:42.319210
10024 12:11:42.322250 Starting depthcharge on Spherion...
10025 12:11:42.322348
10026 12:11:42.322415 Wipe memory regions:
10027 12:11:42.322478
10028 12:11:42.323225 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10029 12:11:42.323361 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10030 12:11:42.323476 Setting prompt string to ['asurada:']
10031 12:11:42.323587 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10032 12:11:42.325735 [0x00000040000000, 0x00000054600000)
10033 12:11:42.448051
10034 12:11:42.448189 [0x00000054660000, 0x00000080000000)
10035 12:11:42.708584
10036 12:11:42.708733 [0x000000821a7280, 0x000000ffe64000)
10037 12:11:43.453636
10038 12:11:43.453837 [0x00000100000000, 0x00000240000000)
10039 12:11:45.343741
10040 12:11:45.346867 Initializing XHCI USB controller at 0x11200000.
10041 12:11:46.384779
10042 12:11:46.388510 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10043 12:11:46.388603
10044 12:11:46.388670
10045 12:11:46.388732
10046 12:11:46.389045 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 12:11:46.489374 asurada: tftpboot 192.168.201.1 10605395/tftp-deploy-6cskc8xc/kernel/image.itb 10605395/tftp-deploy-6cskc8xc/kernel/cmdline
10049 12:11:46.489528 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10050 12:11:46.489617 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10051 12:11:46.493587 tftpboot 192.168.201.1 10605395/tftp-deploy-6cskc8xc/kernel/image.itp-deploy-6cskc8xc/kernel/cmdline
10052 12:11:46.493673
10053 12:11:46.493740 Waiting for link
10054 12:11:46.653969
10055 12:11:46.654116 R8152: Initializing
10056 12:11:46.654187
10057 12:11:46.657317 Version 9 (ocp_data = 6010)
10058 12:11:46.657401
10059 12:11:46.660344 R8152: Done initializing
10060 12:11:46.660428
10061 12:11:46.660495 Adding net device
10062 12:11:48.606625
10063 12:11:48.606783 done.
10064 12:11:48.606857
10065 12:11:48.606920 MAC: 00:e0:4c:72:2d:d6
10066 12:11:48.606980
10067 12:11:48.609637 Sending DHCP discover... done.
10068 12:11:48.609722
10069 12:11:48.612693 Waiting for reply... done.
10070 12:11:48.612797
10071 12:11:48.616466 Sending DHCP request... done.
10072 12:11:48.616550
10073 12:11:48.621011 Waiting for reply... done.
10074 12:11:48.621095
10075 12:11:48.621162 My ip is 192.168.201.21
10076 12:11:48.621224
10077 12:11:48.624482 The DHCP server ip is 192.168.201.1
10078 12:11:48.624566
10079 12:11:48.630697 TFTP server IP predefined by user: 192.168.201.1
10080 12:11:48.630784
10081 12:11:48.637787 Bootfile predefined by user: 10605395/tftp-deploy-6cskc8xc/kernel/image.itb
10082 12:11:48.637878
10083 12:11:48.640749 Sending tftp read request... done.
10084 12:11:48.640868
10085 12:11:48.640940 Waiting for the transfer...
10086 12:11:48.644089
10087 12:11:48.914696 00000000 ################################################################
10088 12:11:48.914836
10089 12:11:49.186512 00080000 ################################################################
10090 12:11:49.186667
10091 12:11:49.474910 00100000 ################################################################
10092 12:11:49.475086
10093 12:11:49.738941 00180000 ################################################################
10094 12:11:49.739084
10095 12:11:50.028538 00200000 ################################################################
10096 12:11:50.028696
10097 12:11:50.315439 00280000 ################################################################
10098 12:11:50.315605
10099 12:11:50.596515 00300000 ################################################################
10100 12:11:50.596672
10101 12:11:50.884083 00380000 ################################################################
10102 12:11:50.884216
10103 12:11:51.159994 00400000 ################################################################
10104 12:11:51.160154
10105 12:11:51.452280 00480000 ################################################################
10106 12:11:51.452518
10107 12:11:51.748689 00500000 ################################################################
10108 12:11:51.748874
10109 12:11:52.017296 00580000 ################################################################
10110 12:11:52.017430
10111 12:11:52.283666 00600000 ################################################################
10112 12:11:52.283804
10113 12:11:52.569718 00680000 ################################################################
10114 12:11:52.569857
10115 12:11:52.855097 00700000 ################################################################
10116 12:11:52.855231
10117 12:11:53.134220 00780000 ################################################################
10118 12:11:53.134399
10119 12:11:53.427901 00800000 ################################################################
10120 12:11:53.428078
10121 12:11:53.701870 00880000 ################################################################
10122 12:11:53.702022
10123 12:11:53.977993 00900000 ################################################################
10124 12:11:53.978148
10125 12:11:54.267995 00980000 ################################################################
10126 12:11:54.268168
10127 12:11:54.555532 00a00000 ################################################################
10128 12:11:54.555710
10129 12:11:54.850872 00a80000 ################################################################
10130 12:11:54.851046
10131 12:11:55.125475 00b00000 ################################################################
10132 12:11:55.125655
10133 12:11:55.425091 00b80000 ################################################################
10134 12:11:55.425248
10135 12:11:55.710755 00c00000 ################################################################
10136 12:11:55.710912
10137 12:11:55.989785 00c80000 ################################################################
10138 12:11:55.989929
10139 12:11:56.295545 00d00000 ################################################################
10140 12:11:56.295733
10141 12:11:56.591720 00d80000 ################################################################
10142 12:11:56.591896
10143 12:11:56.869366 00e00000 ################################################################
10144 12:11:56.869569
10145 12:11:57.151864 00e80000 ################################################################
10146 12:11:57.152023
10147 12:11:57.416981 00f00000 ################################################################
10148 12:11:57.417121
10149 12:11:57.693951 00f80000 ################################################################
10150 12:11:57.694089
10151 12:11:57.962946 01000000 ################################################################
10152 12:11:57.963086
10153 12:11:58.238270 01080000 ################################################################
10154 12:11:58.238450
10155 12:11:58.513373 01100000 ################################################################
10156 12:11:58.513530
10157 12:11:58.787469 01180000 ################################################################
10158 12:11:58.787662
10159 12:11:59.062944 01200000 ################################################################
10160 12:11:59.063144
10161 12:11:59.343040 01280000 ################################################################
10162 12:11:59.343203
10163 12:11:59.631459 01300000 ################################################################
10164 12:11:59.631601
10165 12:11:59.908454 01380000 ################################################################
10166 12:11:59.908634
10167 12:12:00.186214 01400000 ################################################################
10168 12:12:00.186369
10169 12:12:00.464453 01480000 ################################################################
10170 12:12:00.464635
10171 12:12:00.742878 01500000 ################################################################
10172 12:12:00.743017
10173 12:12:01.017869 01580000 ################################################################
10174 12:12:01.018038
10175 12:12:01.289705 01600000 ################################################################
10176 12:12:01.289894
10177 12:12:01.567483 01680000 ################################################################
10178 12:12:01.567651
10179 12:12:01.840706 01700000 ################################################################
10180 12:12:01.840867
10181 12:12:02.125617 01780000 ################################################################
10182 12:12:02.125759
10183 12:12:02.417433 01800000 ################################################################
10184 12:12:02.417586
10185 12:12:02.704581 01880000 ################################################################
10186 12:12:02.704720
10187 12:12:02.980986 01900000 ################################################################
10188 12:12:02.981131
10189 12:12:03.252789 01980000 ################################################################
10190 12:12:03.252931
10191 12:12:03.526829 01a00000 ################################################################
10192 12:12:03.526971
10193 12:12:03.802260 01a80000 ################################################################
10194 12:12:03.802412
10195 12:12:04.100262 01b00000 ################################################################
10196 12:12:04.100435
10197 12:12:04.395605 01b80000 ################################################################
10198 12:12:04.395775
10199 12:12:04.665336 01c00000 ################################################################
10200 12:12:04.665501
10201 12:12:04.936798 01c80000 ################################################################
10202 12:12:04.936968
10203 12:12:05.205449 01d00000 ################################################################
10204 12:12:05.205637
10205 12:12:05.489205 01d80000 ################################################################
10206 12:12:05.489373
10207 12:12:05.756180 01e00000 ################################################################
10208 12:12:05.756366
10209 12:12:06.037639 01e80000 ################################################################
10210 12:12:06.037815
10211 12:12:06.315006 01f00000 ################################################################
10212 12:12:06.315174
10213 12:12:06.610365 01f80000 ################################################################
10214 12:12:06.610523
10215 12:12:06.881199 02000000 ################################################################
10216 12:12:06.881351
10217 12:12:07.156956 02080000 ################################################################
10218 12:12:07.157119
10219 12:12:07.429938 02100000 ################################################################
10220 12:12:07.430076
10221 12:12:07.698684 02180000 ################################################################
10222 12:12:07.698866
10223 12:12:07.979480 02200000 ################################################################
10224 12:12:07.979636
10225 12:12:08.269044 02280000 ################################################################
10226 12:12:08.269194
10227 12:12:08.546719 02300000 ################################################################
10228 12:12:08.546867
10229 12:12:08.815514 02380000 ################################################################
10230 12:12:08.815665
10231 12:12:09.108344 02400000 ################################################################
10232 12:12:09.108488
10233 12:12:09.384151 02480000 ################################################################
10234 12:12:09.384344
10235 12:12:09.661497 02500000 ################################################################
10236 12:12:09.661682
10237 12:12:09.951459 02580000 ################################################################
10238 12:12:09.951630
10239 12:12:10.226110 02600000 ################################################################
10240 12:12:10.226288
10241 12:12:10.497439 02680000 ################################################################
10242 12:12:10.497615
10243 12:12:10.789375 02700000 ################################################################
10244 12:12:10.789553
10245 12:12:11.093252 02780000 ################################################################
10246 12:12:11.093423
10247 12:12:11.362698 02800000 ################################################################
10248 12:12:11.362882
10249 12:12:11.630096 02880000 ################################################################
10250 12:12:11.630254
10251 12:12:11.910146 02900000 ################################################################
10252 12:12:11.910293
10253 12:12:12.183614 02980000 ################################################################
10254 12:12:12.183770
10255 12:12:12.471901 02a00000 ################################################################
10256 12:12:12.472061
10257 12:12:12.742023 02a80000 ################################################################
10258 12:12:12.742182
10259 12:12:13.009766 02b00000 ################################################################
10260 12:12:13.009914
10261 12:12:13.280528 02b80000 ################################################################
10262 12:12:13.280693
10263 12:12:13.547548 02c00000 ################################################################
10264 12:12:13.547729
10265 12:12:13.830884 02c80000 ################################################################
10266 12:12:13.831038
10267 12:12:14.120619 02d00000 ################################################################
10268 12:12:14.120774
10269 12:12:14.395255 02d80000 ################################################################
10270 12:12:14.395409
10271 12:12:14.674727 02e00000 ################################################################
10272 12:12:14.674921
10273 12:12:14.944269 02e80000 ################################################################
10274 12:12:14.944448
10275 12:12:15.220991 02f00000 ################################################################
10276 12:12:15.221144
10277 12:12:15.496147 02f80000 ################################################################
10278 12:12:15.496303
10279 12:12:15.788146 03000000 ################################################################
10280 12:12:15.788300
10281 12:12:16.055078 03080000 ################################################################
10282 12:12:16.055245
10283 12:12:16.339832 03100000 ################################################################
10284 12:12:16.339981
10285 12:12:16.632892 03180000 ################################################################
10286 12:12:16.633038
10287 12:12:16.929098 03200000 ################################################################
10288 12:12:16.929233
10289 12:12:17.194224 03280000 ################################################################
10290 12:12:17.194381
10291 12:12:17.461761 03300000 ################################################################
10292 12:12:17.461918
10293 12:12:17.742292 03380000 ################################################################
10294 12:12:17.742445
10295 12:12:18.028809 03400000 ################################################################
10296 12:12:18.029045
10297 12:12:18.306224 03480000 ################################################################
10298 12:12:18.306377
10299 12:12:18.582744 03500000 ################################################################
10300 12:12:18.582935
10301 12:12:18.863814 03580000 ################################################################
10302 12:12:18.864020
10303 12:12:19.127511 03600000 ################################################################
10304 12:12:19.127665
10305 12:12:19.391530 03680000 ################################################################
10306 12:12:19.391673
10307 12:12:19.682593 03700000 ################################################################
10308 12:12:19.682753
10309 12:12:19.956466 03780000 ################################################################
10310 12:12:19.956603
10311 12:12:20.223500 03800000 ################################################################
10312 12:12:20.223654
10313 12:12:20.507352 03880000 ################################################################
10314 12:12:20.507521
10315 12:12:20.814148 03900000 ################################################################
10316 12:12:20.814317
10317 12:12:21.100514 03980000 ################################################################
10318 12:12:21.100697
10319 12:12:21.389029 03a00000 ################################################################
10320 12:12:21.389181
10321 12:12:21.692445 03a80000 ################################################################
10322 12:12:21.692642
10323 12:12:21.957949 03b00000 ################################################################
10324 12:12:21.958095
10325 12:12:22.243888 03b80000 ################################################################
10326 12:12:22.244045
10327 12:12:22.542871 03c00000 ################################################################
10328 12:12:22.543030
10329 12:12:22.844292 03c80000 ################################################################
10330 12:12:22.844459
10331 12:12:23.150483 03d00000 ################################################################
10332 12:12:23.150634
10333 12:12:23.440214 03d80000 ################################################################
10334 12:12:23.440359
10335 12:12:23.721314 03e00000 ################################################################
10336 12:12:23.721471
10337 12:12:23.988677 03e80000 ################################################################
10338 12:12:23.988845
10339 12:12:24.245461 03f00000 ########################################################### done.
10340 12:12:24.245609
10341 12:12:24.248805 The bootfile was 66538766 bytes long.
10342 12:12:24.248884
10343 12:12:24.251863 Sending tftp read request... done.
10344 12:12:24.251964
10345 12:12:24.255387 Waiting for the transfer...
10346 12:12:24.255490
10347 12:12:24.255587 00000000 # done.
10348 12:12:24.258638
10349 12:12:24.265180 Command line loaded dynamically from TFTP file: 10605395/tftp-deploy-6cskc8xc/kernel/cmdline
10350 12:12:24.265257
10351 12:12:24.274864 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10352 12:12:24.274951
10353 12:12:24.278307 Loading FIT.
10354 12:12:24.278417
10355 12:12:24.281582 Image ramdisk-1 has 56395188 bytes.
10356 12:12:24.281666
10357 12:12:24.281733 Image fdt-1 has 46924 bytes.
10358 12:12:24.284625
10359 12:12:24.284709 Image kernel-1 has 10094623 bytes.
10360 12:12:24.284802
10361 12:12:24.294963 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10362 12:12:24.295048
10363 12:12:24.310886 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10364 12:12:24.314403
10365 12:12:24.317877 Choosing best match conf-1 for compat google,spherion-rev2.
10366 12:12:24.321959
10367 12:12:24.326062 Connected to device vid:did:rid of 1ae0:0028:00
10368 12:12:24.333449
10369 12:12:24.336514 tpm_get_response: command 0x17b, return code 0x0
10370 12:12:24.336624
10371 12:12:24.343353 ec_init: CrosEC protocol v3 supported (256, 248)
10372 12:12:24.343461
10373 12:12:24.346628 tpm_cleanup: add release locality here.
10374 12:12:24.346734
10375 12:12:24.349957 Shutting down all USB controllers.
10376 12:12:24.350058
10377 12:12:24.353161 Removing current net device
10378 12:12:24.353239
10379 12:12:24.356347 Exiting depthcharge with code 4 at timestamp: 71343393
10380 12:12:24.356481
10381 12:12:24.360132 LZMA decompressing kernel-1 to 0x821a6718
10382 12:12:24.360216
10383 12:12:24.363239 LZMA decompressing kernel-1 to 0x40000000
10384 12:12:25.633075
10385 12:12:25.633229 jumping to kernel
10386 12:12:25.633667 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10387 12:12:25.633771 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10388 12:12:25.633850 Setting prompt string to ['Linux version [0-9]']
10389 12:12:25.633923 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10390 12:12:25.633996 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10391 12:12:25.715030
10392 12:12:25.718007 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10393 12:12:25.721693 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10394 12:12:25.721820 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10395 12:12:25.721938 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10396 12:12:25.722048 Using line separator: #'\n'#
10397 12:12:25.722143 No login prompt set.
10398 12:12:25.722243 Parsing kernel messages
10399 12:12:25.722334 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10400 12:12:25.722509 [login-action] Waiting for messages, (timeout 00:03:42)
10401 12:12:25.741031 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10402 12:12:25.744429 [ 0.000000] random: crng init done
10403 12:12:25.751192 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10404 12:12:25.751304 [ 0.000000] efi: UEFI not found.
10405 12:12:25.760652 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10406 12:12:25.767645 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10407 12:12:25.777442 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10408 12:12:25.787166 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10409 12:12:25.793734 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10410 12:12:25.800249 [ 0.000000] printk: bootconsole [mtk8250] enabled
10411 12:12:25.807221 [ 0.000000] NUMA: No NUMA configuration found
10412 12:12:25.813500 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10413 12:12:25.816923 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10414 12:12:25.820440 [ 0.000000] Zone ranges:
10415 12:12:25.827000 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10416 12:12:25.830325 [ 0.000000] DMA32 empty
10417 12:12:25.836897 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10418 12:12:25.839973 [ 0.000000] Movable zone start for each node
10419 12:12:25.843388 [ 0.000000] Early memory node ranges
10420 12:12:25.850208 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10421 12:12:25.856643 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10422 12:12:25.863055 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10423 12:12:25.869918 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10424 12:12:25.876431 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10425 12:12:25.882739 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10426 12:12:25.938486 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10427 12:12:25.945052 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10428 12:12:25.951480 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10429 12:12:25.954952 [ 0.000000] psci: probing for conduit method from DT.
10430 12:12:25.961482 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10431 12:12:25.964981 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10432 12:12:25.971428 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10433 12:12:25.974848 [ 0.000000] psci: SMC Calling Convention v1.2
10434 12:12:25.981128 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10435 12:12:25.984486 [ 0.000000] Detected VIPT I-cache on CPU0
10436 12:12:25.991200 [ 0.000000] CPU features: detected: GIC system register CPU interface
10437 12:12:25.997530 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10438 12:12:26.004131 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10439 12:12:26.010709 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10440 12:12:26.020931 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10441 12:12:26.027453 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10442 12:12:26.030444 [ 0.000000] alternatives: applying boot alternatives
10443 12:12:26.037390 [ 0.000000] Fallback order for Node 0: 0
10444 12:12:26.043879 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10445 12:12:26.046997 [ 0.000000] Policy zone: Normal
10446 12:12:26.057413 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10447 12:12:26.070345 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10448 12:12:26.080670 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10449 12:12:26.090365 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10450 12:12:26.097374 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10451 12:12:26.100057 <6>[ 0.000000] software IO TLB: area num 8.
10452 12:12:26.158194 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10453 12:12:26.307181 <6>[ 0.000000] Memory: 7917868K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434900K reserved, 32768K cma-reserved)
10454 12:12:26.313776 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10455 12:12:26.320261 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10456 12:12:26.323259 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10457 12:12:26.330184 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10458 12:12:26.336415 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10459 12:12:26.343402 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10460 12:12:26.349842 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10461 12:12:26.356301 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10462 12:12:26.362829 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10463 12:12:26.369913 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10464 12:12:26.372930 <6>[ 0.000000] GICv3: 608 SPIs implemented
10465 12:12:26.376206 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10466 12:12:26.382819 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10467 12:12:26.386345 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10468 12:12:26.392761 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10469 12:12:26.406086 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10470 12:12:26.419186 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10471 12:12:26.425880 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10472 12:12:26.433984 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10473 12:12:26.446910 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10474 12:12:26.453538 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10475 12:12:26.460389 <6>[ 0.009177] Console: colour dummy device 80x25
10476 12:12:26.470234 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10477 12:12:26.476793 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10478 12:12:26.480197 <6>[ 0.029245] LSM: Security Framework initializing
10479 12:12:26.486705 <6>[ 0.034214] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10480 12:12:26.496495 <6>[ 0.042028] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10481 12:12:26.506334 <6>[ 0.051460] cblist_init_generic: Setting adjustable number of callback queues.
10482 12:12:26.509864 <6>[ 0.058959] cblist_init_generic: Setting shift to 3 and lim to 1.
10483 12:12:26.516308 <6>[ 0.065298] cblist_init_generic: Setting shift to 3 and lim to 1.
10484 12:12:26.522992 <6>[ 0.071742] rcu: Hierarchical SRCU implementation.
10485 12:12:26.529324 <6>[ 0.076787] rcu: Max phase no-delay instances is 1000.
10486 12:12:26.536333 <6>[ 0.083842] EFI services will not be available.
10487 12:12:26.539218 <6>[ 0.088840] smp: Bringing up secondary CPUs ...
10488 12:12:26.547493 <6>[ 0.093895] Detected VIPT I-cache on CPU1
10489 12:12:26.553969 <6>[ 0.093966] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10490 12:12:26.560334 <6>[ 0.093997] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10491 12:12:26.564123 <6>[ 0.094331] Detected VIPT I-cache on CPU2
10492 12:12:26.573583 <6>[ 0.094381] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10493 12:12:26.580086 <6>[ 0.094396] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10494 12:12:26.583449 <6>[ 0.094654] Detected VIPT I-cache on CPU3
10495 12:12:26.590062 <6>[ 0.094702] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10496 12:12:26.596446 <6>[ 0.094715] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10497 12:12:26.602929 <6>[ 0.095021] CPU features: detected: Spectre-v4
10498 12:12:26.606265 <6>[ 0.095028] CPU features: detected: Spectre-BHB
10499 12:12:26.609682 <6>[ 0.095033] Detected PIPT I-cache on CPU4
10500 12:12:26.616274 <6>[ 0.095093] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10501 12:12:26.626520 <6>[ 0.095109] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10502 12:12:26.629961 <6>[ 0.095404] Detected PIPT I-cache on CPU5
10503 12:12:26.635944 <6>[ 0.095468] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10504 12:12:26.642857 <6>[ 0.095484] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10505 12:12:26.646160 <6>[ 0.095767] Detected PIPT I-cache on CPU6
10506 12:12:26.656146 <6>[ 0.095831] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10507 12:12:26.662501 <6>[ 0.095847] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10508 12:12:26.665655 <6>[ 0.096145] Detected PIPT I-cache on CPU7
10509 12:12:26.672218 <6>[ 0.096210] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10510 12:12:26.679157 <6>[ 0.096226] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10511 12:12:26.682236 <6>[ 0.096273] smp: Brought up 1 node, 8 CPUs
10512 12:12:26.689162 <6>[ 0.237686] SMP: Total of 8 processors activated.
10513 12:12:26.695595 <6>[ 0.242607] CPU features: detected: 32-bit EL0 Support
10514 12:12:26.702144 <6>[ 0.247971] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10515 12:12:26.708553 <6>[ 0.256770] CPU features: detected: Common not Private translations
10516 12:12:26.715418 <6>[ 0.263286] CPU features: detected: CRC32 instructions
10517 12:12:26.721949 <6>[ 0.268637] CPU features: detected: RCpc load-acquire (LDAPR)
10518 12:12:26.725433 <6>[ 0.274597] CPU features: detected: LSE atomic instructions
10519 12:12:26.731892 <6>[ 0.280378] CPU features: detected: Privileged Access Never
10520 12:12:26.738508 <6>[ 0.286158] CPU features: detected: RAS Extension Support
10521 12:12:26.744953 <6>[ 0.291766] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10522 12:12:26.748281 <6>[ 0.298990] CPU: All CPU(s) started at EL2
10523 12:12:26.754875 <6>[ 0.303307] alternatives: applying system-wide alternatives
10524 12:12:26.765066 <6>[ 0.314022] devtmpfs: initialized
10525 12:12:26.780656 <6>[ 0.322987] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10526 12:12:26.787274 <6>[ 0.332949] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10527 12:12:26.793733 <6>[ 0.340801] pinctrl core: initialized pinctrl subsystem
10528 12:12:26.797112 <6>[ 0.347467] DMI not present or invalid.
10529 12:12:26.803422 <6>[ 0.351877] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10530 12:12:26.813368 <6>[ 0.358732] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10531 12:12:26.820205 <6>[ 0.366312] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10532 12:12:26.829754 <6>[ 0.374528] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10533 12:12:26.833288 <6>[ 0.382772] audit: initializing netlink subsys (disabled)
10534 12:12:26.843255 <5>[ 0.388465] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10535 12:12:26.849768 <6>[ 0.389177] thermal_sys: Registered thermal governor 'step_wise'
10536 12:12:26.856551 <6>[ 0.396432] thermal_sys: Registered thermal governor 'power_allocator'
10537 12:12:26.859945 <6>[ 0.402683] cpuidle: using governor menu
10538 12:12:26.866438 <6>[ 0.413641] NET: Registered PF_QIPCRTR protocol family
10539 12:12:26.872879 <6>[ 0.419118] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10540 12:12:26.879214 <6>[ 0.426221] ASID allocator initialised with 32768 entries
10541 12:12:26.882675 <6>[ 0.432792] Serial: AMBA PL011 UART driver
10542 12:12:26.892170 <4>[ 0.441464] Trying to register duplicate clock ID: 134
10543 12:12:26.946065 <6>[ 0.498521] KASLR enabled
10544 12:12:26.960452 <6>[ 0.506272] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10545 12:12:26.966925 <6>[ 0.513285] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10546 12:12:26.973938 <6>[ 0.519775] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10547 12:12:26.980088 <6>[ 0.526781] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10548 12:12:26.986919 <6>[ 0.533268] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10549 12:12:26.993391 <6>[ 0.540271] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10550 12:12:26.999764 <6>[ 0.546757] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10551 12:12:27.006694 <6>[ 0.553760] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10552 12:12:27.009740 <6>[ 0.561283] ACPI: Interpreter disabled.
10553 12:12:27.018730 <6>[ 0.567680] iommu: Default domain type: Translated
10554 12:12:27.025113 <6>[ 0.572791] iommu: DMA domain TLB invalidation policy: strict mode
10555 12:12:27.028623 <5>[ 0.579446] SCSI subsystem initialized
10556 12:12:27.035171 <6>[ 0.583611] usbcore: registered new interface driver usbfs
10557 12:12:27.041607 <6>[ 0.589346] usbcore: registered new interface driver hub
10558 12:12:27.045184 <6>[ 0.594896] usbcore: registered new device driver usb
10559 12:12:27.052158 <6>[ 0.600980] pps_core: LinuxPPS API ver. 1 registered
10560 12:12:27.061961 <6>[ 0.606173] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10561 12:12:27.065166 <6>[ 0.615520] PTP clock support registered
10562 12:12:27.068251 <6>[ 0.619762] EDAC MC: Ver: 3.0.0
10563 12:12:27.075867 <6>[ 0.624906] FPGA manager framework
10564 12:12:27.082233 <6>[ 0.628583] Advanced Linux Sound Architecture Driver Initialized.
10565 12:12:27.085514 <6>[ 0.635359] vgaarb: loaded
10566 12:12:27.091877 <6>[ 0.638524] clocksource: Switched to clocksource arch_sys_counter
10567 12:12:27.095434 <5>[ 0.644962] VFS: Disk quotas dquot_6.6.0
10568 12:12:27.101908 <6>[ 0.649145] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10569 12:12:27.105238 <6>[ 0.656337] pnp: PnP ACPI: disabled
10570 12:12:27.114145 <6>[ 0.663080] NET: Registered PF_INET protocol family
10571 12:12:27.123740 <6>[ 0.668678] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10572 12:12:27.135453 <6>[ 0.680995] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10573 12:12:27.145405 <6>[ 0.689808] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10574 12:12:27.151891 <6>[ 0.697778] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10575 12:12:27.161626 <6>[ 0.706474] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10576 12:12:27.168269 <6>[ 0.716226] TCP: Hash tables configured (established 65536 bind 65536)
10577 12:12:27.174968 <6>[ 0.723079] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10578 12:12:27.184900 <6>[ 0.730276] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10579 12:12:27.191307 <6>[ 0.737973] NET: Registered PF_UNIX/PF_LOCAL protocol family
10580 12:12:27.194806 <6>[ 0.744050] RPC: Registered named UNIX socket transport module.
10581 12:12:27.201408 <6>[ 0.750196] RPC: Registered udp transport module.
10582 12:12:27.204865 <6>[ 0.755127] RPC: Registered tcp transport module.
10583 12:12:27.211189 <6>[ 0.760059] RPC: Registered tcp NFSv4.1 backchannel transport module.
10584 12:12:27.217651 <6>[ 0.766722] PCI: CLS 0 bytes, default 64
10585 12:12:27.221169 <6>[ 0.771036] Unpacking initramfs...
10586 12:12:27.230958 <6>[ 0.775134] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10587 12:12:27.237447 <6>[ 0.783789] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10588 12:12:27.243899 <6>[ 0.792656] kvm [1]: IPA Size Limit: 40 bits
10589 12:12:27.247402 <6>[ 0.797183] kvm [1]: GICv3: no GICV resource entry
10590 12:12:27.253786 <6>[ 0.802205] kvm [1]: disabling GICv2 emulation
10591 12:12:27.260473 <6>[ 0.806891] kvm [1]: GIC system register CPU interface enabled
10592 12:12:27.263946 <6>[ 0.813064] kvm [1]: vgic interrupt IRQ18
10593 12:12:27.267274 <6>[ 0.817418] kvm [1]: VHE mode initialized successfully
10594 12:12:27.274752 <5>[ 0.823832] Initialise system trusted keyrings
10595 12:12:27.281162 <6>[ 0.828649] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10596 12:12:27.289665 <6>[ 0.838715] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10597 12:12:27.296494 <5>[ 0.845131] NFS: Registering the id_resolver key type
10598 12:12:27.299375 <5>[ 0.850439] Key type id_resolver registered
10599 12:12:27.305958 <5>[ 0.854856] Key type id_legacy registered
10600 12:12:27.312886 <6>[ 0.859143] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10601 12:12:27.319238 <6>[ 0.866069] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10602 12:12:27.326145 <6>[ 0.873804] 9p: Installing v9fs 9p2000 file system support
10603 12:12:27.363145 <5>[ 0.912293] Key type asymmetric registered
10604 12:12:27.366687 <5>[ 0.916626] Asymmetric key parser 'x509' registered
10605 12:12:27.376416 <6>[ 0.921786] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10606 12:12:27.379861 <6>[ 0.929396] io scheduler mq-deadline registered
10607 12:12:27.383043 <6>[ 0.934156] io scheduler kyber registered
10608 12:12:27.402343 <6>[ 0.951135] EINJ: ACPI disabled.
10609 12:12:27.434427 <4>[ 0.976747] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 12:12:27.444278 <4>[ 0.987402] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 12:12:27.459323 <6>[ 1.008196] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10612 12:12:27.466989 <6>[ 1.016193] printk: console [ttyS0] disabled
10613 12:12:27.494839 <6>[ 1.040843] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10614 12:12:27.501776 <6>[ 1.050320] printk: console [ttyS0] enabled
10615 12:12:27.504841 <6>[ 1.050320] printk: console [ttyS0] enabled
10616 12:12:27.511660 <6>[ 1.059216] printk: bootconsole [mtk8250] disabled
10617 12:12:27.514790 <6>[ 1.059216] printk: bootconsole [mtk8250] disabled
10618 12:12:27.521346 <6>[ 1.070433] SuperH (H)SCI(F) driver initialized
10619 12:12:27.524757 <6>[ 1.075701] msm_serial: driver initialized
10620 12:12:27.538741 <6>[ 1.084586] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10621 12:12:27.548990 <6>[ 1.093132] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10622 12:12:27.555568 <6>[ 1.101673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10623 12:12:27.565589 <6>[ 1.110302] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10624 12:12:27.575252 <6>[ 1.119009] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10625 12:12:27.581645 <6>[ 1.127722] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10626 12:12:27.591631 <6>[ 1.136262] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10627 12:12:27.598143 <6>[ 1.145055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10628 12:12:27.608348 <6>[ 1.153598] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10629 12:12:27.620178 <6>[ 1.169228] loop: module loaded
10630 12:12:27.626611 <6>[ 1.175336] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10631 12:12:27.649699 <4>[ 1.198814] mtk-pmic-keys: Failed to locate of_node [id: -1]
10632 12:12:27.656608 <6>[ 1.205770] megasas: 07.719.03.00-rc1
10633 12:12:27.666273 <6>[ 1.215293] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10634 12:12:27.676956 <6>[ 1.225906] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10635 12:12:27.693493 <6>[ 1.242584] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10636 12:12:27.753564 <6>[ 1.296197] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10637 12:12:29.658359 <6>[ 3.207114] Freeing initrd memory: 55068K
10638 12:12:29.668427 <6>[ 3.217376] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10639 12:12:29.679358 <6>[ 3.228210] tun: Universal TUN/TAP device driver, 1.6
10640 12:12:29.682539 <6>[ 3.234256] thunder_xcv, ver 1.0
10641 12:12:29.686041 <6>[ 3.237758] thunder_bgx, ver 1.0
10642 12:12:29.688892 <6>[ 3.241251] nicpf, ver 1.0
10643 12:12:29.699721 <6>[ 3.245245] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10644 12:12:29.702769 <6>[ 3.252720] hns3: Copyright (c) 2017 Huawei Corporation.
10645 12:12:29.709430 <6>[ 3.258306] hclge is initializing
10646 12:12:29.712823 <6>[ 3.261882] e1000: Intel(R) PRO/1000 Network Driver
10647 12:12:29.719705 <6>[ 3.267011] e1000: Copyright (c) 1999-2006 Intel Corporation.
10648 12:12:29.722819 <6>[ 3.273024] e1000e: Intel(R) PRO/1000 Network Driver
10649 12:12:29.729473 <6>[ 3.278239] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10650 12:12:29.736039 <6>[ 3.284426] igb: Intel(R) Gigabit Ethernet Network Driver
10651 12:12:29.742771 <6>[ 3.290076] igb: Copyright (c) 2007-2014 Intel Corporation.
10652 12:12:29.749398 <6>[ 3.295917] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10653 12:12:29.755968 <6>[ 3.302435] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10654 12:12:29.759059 <6>[ 3.308891] sky2: driver version 1.30
10655 12:12:29.765629 <6>[ 3.313874] VFIO - User Level meta-driver version: 0.3
10656 12:12:29.773063 <6>[ 3.322059] usbcore: registered new interface driver usb-storage
10657 12:12:29.779742 <6>[ 3.328504] usbcore: registered new device driver onboard-usb-hub
10658 12:12:29.788877 <6>[ 3.337576] mt6397-rtc mt6359-rtc: registered as rtc0
10659 12:12:29.798940 <6>[ 3.343045] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:12:32 UTC (1686053552)
10660 12:12:29.801897 <6>[ 3.352605] i2c_dev: i2c /dev entries driver
10661 12:12:29.818402 <6>[ 3.364389] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10662 12:12:29.825617 <6>[ 3.374494] sdhci: Secure Digital Host Controller Interface driver
10663 12:12:29.832273 <6>[ 3.380934] sdhci: Copyright(c) Pierre Ossman
10664 12:12:29.838348 <6>[ 3.386331] Synopsys Designware Multimedia Card Interface Driver
10665 12:12:29.841845 <6>[ 3.392957] mmc0: CQHCI version 5.10
10666 12:12:29.848398 <6>[ 3.393488] sdhci-pltfm: SDHCI platform and OF driver helper
10667 12:12:29.855546 <6>[ 3.404866] ledtrig-cpu: registered to indicate activity on CPUs
10668 12:12:29.866306 <6>[ 3.412228] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10669 12:12:29.872817 <6>[ 3.419623] usbcore: registered new interface driver usbhid
10670 12:12:29.876390 <6>[ 3.425456] usbhid: USB HID core driver
10671 12:12:29.882528 <6>[ 3.429703] spi_master spi0: will run message pump with realtime priority
10672 12:12:29.927117 <6>[ 3.469425] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10673 12:12:29.945744 <6>[ 3.484352] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10674 12:12:29.948888 <6>[ 3.497940] mmc0: Command Queue Engine enabled
10675 12:12:29.955754 <6>[ 3.499380] cros-ec-spi spi0.0: Chrome EC device registered
10676 12:12:29.962049 <6>[ 3.502674] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10677 12:12:29.965511 <6>[ 3.515779] mmcblk0: mmc0:0001 DA4128 116 GiB
10678 12:12:29.980036 <6>[ 3.525652] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10679 12:12:29.986323 <6>[ 3.527990] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10680 12:12:29.993079 <6>[ 3.537043] NET: Registered PF_PACKET protocol family
10681 12:12:29.996452 <6>[ 3.542250] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10682 12:12:30.003208 <6>[ 3.546301] 9pnet: Installing 9P2000 support
10683 12:12:30.006321 <6>[ 3.552101] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10684 12:12:30.013395 <5>[ 3.555983] Key type dns_resolver registered
10685 12:12:30.019979 <6>[ 3.561836] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10686 12:12:30.022676 <6>[ 3.566210] registered taskstats version 1
10687 12:12:30.026229 <5>[ 3.576593] Loading compiled-in X.509 certificates
10688 12:12:30.061791 <4>[ 3.604213] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10689 12:12:30.071628 <4>[ 3.614941] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10690 12:12:30.081835 <3>[ 3.627788] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10691 12:12:30.093914 <6>[ 3.643411] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10692 12:12:30.101402 <6>[ 3.650344] xhci-mtk 11200000.usb: xHCI Host Controller
10693 12:12:30.107916 <6>[ 3.655860] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10694 12:12:30.117877 <6>[ 3.663815] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10695 12:12:30.124417 <6>[ 3.673271] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10696 12:12:30.131409 <6>[ 3.679362] xhci-mtk 11200000.usb: xHCI Host Controller
10697 12:12:30.137969 <6>[ 3.684844] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10698 12:12:30.144654 <6>[ 3.692496] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10699 12:12:30.151275 <6>[ 3.700391] hub 1-0:1.0: USB hub found
10700 12:12:30.154828 <6>[ 3.704430] hub 1-0:1.0: 1 port detected
10701 12:12:30.164844 <6>[ 3.708802] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10702 12:12:30.167898 <6>[ 3.717616] hub 2-0:1.0: USB hub found
10703 12:12:30.171208 <6>[ 3.721654] hub 2-0:1.0: 1 port detected
10704 12:12:30.179673 <6>[ 3.728790] mtk-msdc 11f70000.mmc: Got CD GPIO
10705 12:12:30.201018 <6>[ 3.746445] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10706 12:12:30.207465 <6>[ 3.754600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10707 12:12:30.217146 <4>[ 3.762609] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10708 12:12:30.227455 <6>[ 3.772302] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10709 12:12:30.233989 <6>[ 3.780390] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10710 12:12:30.243547 <6>[ 3.788444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10711 12:12:30.250232 <6>[ 3.796364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10712 12:12:30.256693 <6>[ 3.804227] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10713 12:12:30.266732 <6>[ 3.812051] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10714 12:12:30.277132 <6>[ 3.822745] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10715 12:12:30.286695 <6>[ 3.831113] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10716 12:12:30.293439 <6>[ 3.839500] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10717 12:12:30.303286 <6>[ 3.847847] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10718 12:12:30.310227 <6>[ 3.856215] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10719 12:12:30.320091 <6>[ 3.864562] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10720 12:12:30.326598 <6>[ 3.872930] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10721 12:12:30.336336 <6>[ 3.881274] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10722 12:12:30.342836 <6>[ 3.889638] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10723 12:12:30.353128 <6>[ 3.897982] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10724 12:12:30.359534 <6>[ 3.906327] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10725 12:12:30.369446 <6>[ 3.914676] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10726 12:12:30.376147 <6>[ 3.923020] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10727 12:12:30.385914 <6>[ 3.931363] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10728 12:12:30.392494 <6>[ 3.939706] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10729 12:12:30.399602 <6>[ 3.948629] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10730 12:12:30.406905 <6>[ 3.956117] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10731 12:12:30.413929 <6>[ 3.963220] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10732 12:12:30.424304 <6>[ 3.970386] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10733 12:12:30.430792 <6>[ 3.977712] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10734 12:12:30.440997 <6>[ 3.984630] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10735 12:12:30.447370 <6>[ 3.993771] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10736 12:12:30.457059 <6>[ 4.002930] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10737 12:12:30.467038 <6>[ 4.012245] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10738 12:12:30.477296 <6>[ 4.021721] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10739 12:12:30.487387 <6>[ 4.031195] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10740 12:12:30.497134 <6>[ 4.040322] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10741 12:12:30.503609 <6>[ 4.049797] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10742 12:12:30.513291 <6>[ 4.058924] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10743 12:12:30.523391 <6>[ 4.068225] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10744 12:12:30.533283 <6>[ 4.078390] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10745 12:12:30.544057 <6>[ 4.089752] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10746 12:12:30.564585 <6>[ 4.110740] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10747 12:12:30.591503 <6>[ 4.140620] hub 2-1:1.0: USB hub found
10748 12:12:30.594599 <6>[ 4.144973] hub 2-1:1.0: 3 ports detected
10749 12:12:30.716673 <6>[ 4.262795] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10750 12:12:30.871658 <6>[ 4.420504] hub 1-1:1.0: USB hub found
10751 12:12:30.874951 <6>[ 4.424974] hub 1-1:1.0: 4 ports detected
10752 12:12:30.949037 <6>[ 4.495050] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10753 12:12:31.196729 <6>[ 4.742801] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10754 12:12:31.329917 <6>[ 4.879119] hub 1-1.4:1.0: USB hub found
10755 12:12:31.333369 <6>[ 4.883822] hub 1-1.4:1.0: 2 ports detected
10756 12:12:31.632392 <6>[ 5.178798] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10757 12:12:31.824851 <6>[ 5.370799] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10758 12:12:42.841186 <6>[ 16.395417] ALSA device list:
10759 12:12:42.847524 <6>[ 16.398670] No soundcards found.
10760 12:12:42.860238 <6>[ 16.411093] Freeing unused kernel memory: 8384K
10761 12:12:42.863807 <6>[ 16.416022] Run /init as init process
10762 12:12:42.894219 <6>[ 16.444692] NET: Registered PF_INET6 protocol family
10763 12:12:42.900523 <6>[ 16.451043] Segment Routing with IPv6
10764 12:12:42.903531 <6>[ 16.454990] In-situ OAM (IOAM) with IPv6
10765 12:12:42.938691 <30>[ 16.469368] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10766 12:12:42.941522 <30>[ 16.493142] systemd[1]: Detected architecture arm64.
10767 12:12:42.941607
10768 12:12:42.948305 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10769 12:12:42.948390
10770 12:12:42.963952 <30>[ 16.514917] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10771 12:12:43.102464 <30>[ 16.650004] systemd[1]: Queued start job for default target Graphical Interface.
10772 12:12:43.137177 <30>[ 16.688140] systemd[1]: Created slice system-getty.slice.
10773 12:12:43.143657 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10774 12:12:43.160222 <30>[ 16.711397] systemd[1]: Created slice system-modprobe.slice.
10775 12:12:43.167336 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10776 12:12:43.184947 <30>[ 16.735922] systemd[1]: Created slice system-serial\x2dgetty.slice.
10777 12:12:43.194962 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10778 12:12:43.208322 <30>[ 16.759277] systemd[1]: Created slice User and Session Slice.
10779 12:12:43.215138 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10780 12:12:43.235834 <30>[ 16.783348] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10781 12:12:43.245526 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10782 12:12:43.263478 <30>[ 16.810938] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10783 12:12:43.270124 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10784 12:12:43.290286 <30>[ 16.834852] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10785 12:12:43.297220 <30>[ 16.846884] systemd[1]: Reached target Local Encrypted Volumes.
10786 12:12:43.303808 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10787 12:12:43.320339 <30>[ 16.871148] systemd[1]: Reached target Paths.
10788 12:12:43.323365 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10789 12:12:43.339938 <30>[ 16.890777] systemd[1]: Reached target Remote File Systems.
10790 12:12:43.346700 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10791 12:12:43.360232 <30>[ 16.910754] systemd[1]: Reached target Slices.
10792 12:12:43.363087 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10793 12:12:43.380108 <30>[ 16.930838] systemd[1]: Reached target Swap.
10794 12:12:43.383146 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10795 12:12:43.403487 <30>[ 16.951139] systemd[1]: Listening on initctl Compatibility Named Pipe.
10796 12:12:43.410293 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10797 12:12:43.416927 <30>[ 16.965833] systemd[1]: Listening on Journal Audit Socket.
10798 12:12:43.423376 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10799 12:12:43.436319 <30>[ 16.987033] systemd[1]: Listening on Journal Socket (/dev/log).
10800 12:12:43.442915 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10801 12:12:43.460471 <30>[ 17.011104] systemd[1]: Listening on Journal Socket.
10802 12:12:43.467107 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10803 12:12:43.480426 <30>[ 17.031106] systemd[1]: Listening on udev Control Socket.
10804 12:12:43.487046 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10805 12:12:43.504633 <30>[ 17.055455] systemd[1]: Listening on udev Kernel Socket.
10806 12:12:43.511215 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10807 12:12:43.548129 <30>[ 17.099150] systemd[1]: Mounting Huge Pages File System...
10808 12:12:43.554600 Mounting [0;1;39mHuge Pages File System[0m...
10809 12:12:43.570002 <30>[ 17.120899] systemd[1]: Mounting POSIX Message Queue File System...
10810 12:12:43.576573 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10811 12:12:43.593945 <30>[ 17.144871] systemd[1]: Mounting Kernel Debug File System...
10812 12:12:43.600324 Mounting [0;1;39mKernel Debug File System[0m...
10813 12:12:43.619601 <30>[ 17.167055] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10814 12:12:43.639548 <30>[ 17.187295] systemd[1]: Starting Create list of static device nodes for the current kernel...
10815 12:12:43.645980 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10816 12:12:43.666160 <30>[ 17.217163] systemd[1]: Starting Load Kernel Module configfs...
10817 12:12:43.672673 Starting [0;1;39mLoad Kernel Module configfs[0m...
10818 12:12:43.690244 <30>[ 17.241109] systemd[1]: Starting Load Kernel Module drm...
10819 12:12:43.696810 Starting [0;1;39mLoad Kernel Module drm[0m...
10820 12:12:43.715155 <30>[ 17.262944] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10821 12:12:43.725739 <30>[ 17.276771] systemd[1]: Starting Journal Service...
10822 12:12:43.729177 Starting [0;1;39mJournal Service[0m...
10823 12:12:43.746978 <30>[ 17.297602] systemd[1]: Starting Load Kernel Modules...
10824 12:12:43.753501 Starting [0;1;39mLoad Kernel Modules[0m...
10825 12:12:43.774453 <30>[ 17.321801] systemd[1]: Starting Remount Root and Kernel File Systems...
10826 12:12:43.780720 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10827 12:12:43.798829 <30>[ 17.349416] systemd[1]: Starting Coldplug All udev Devices...
10828 12:12:43.804840 Starting [0;1;39mColdplug All udev Devices[0m...
10829 12:12:43.822409 <30>[ 17.373538] systemd[1]: Mounted Huge Pages File System.
10830 12:12:43.829320 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10831 12:12:43.844160 <30>[ 17.395230] systemd[1]: Started Journal Service.
10832 12:12:43.851111 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10833 12:12:43.865496 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10834 12:12:43.880621 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10835 12:12:43.900281 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10836 12:12:43.917514 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10837 12:12:43.933381 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10838 12:12:43.949177 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10839 12:12:43.968381 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10840 12:12:43.984029 See 'systemctl status systemd-remount-fs.service' for details.
10841 12:12:44.048652 Mounting [0;1;39mKernel Configuration File System[0m...
10842 12:12:44.070660 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10843 12:12:44.087606 <46>[ 17.635134] systemd-journald[177]: Received client request to flush runtime journal.
10844 12:12:44.096380 Starting [0;1;39mLoad/Save Random Seed[0m...
10845 12:12:44.115579 Starting [0;1;39mApply Kernel Variables[0m...
10846 12:12:44.135208 Starting [0;1;39mCreate System Users[0m...
10847 12:12:44.153676 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10848 12:12:44.172283 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10849 12:12:44.184841 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10850 12:12:44.201017 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10851 12:12:44.217221 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10852 12:12:44.233006 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10853 12:12:44.280991 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10854 12:12:44.304922 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10855 12:12:44.320454 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10856 12:12:44.339884 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10857 12:12:44.384179 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10858 12:12:44.407657 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10859 12:12:44.424983 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10860 12:12:44.444919 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10861 12:12:44.465264 Starting [0;1;39mNetwork Time Synchronization[0m...
10862 12:12:44.484147 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10863 12:12:44.512125 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10864 12:12:44.575343 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10865 12:12:44.594323 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10866 12:12:44.616290 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10867 12:12:44.626189 [[0;32m OK [0m] Reached targ<6>[ 18.173751] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10868 12:12:44.629304 et [0;1;39mSystem Time Set[0m.
10869 12:12:44.636925 <6>[ 18.187739] remoteproc remoteproc0: scp is available
10870 12:12:44.646473 <4>[ 18.193585] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10871 12:12:44.653037 <6>[ 18.203473] remoteproc remoteproc0: powering up scp
10872 12:12:44.663005 <4>[ 18.208655] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10873 12:12:44.673146 [[0;32m OK [<6>[ 18.219825] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10874 12:12:44.679624 0m] Reached targ<3>[ 18.219833] remoteproc remoteproc0: request_firmware failed: -2
10875 12:12:44.689544 et [0;1;39mSyst<6>[ 18.236577] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10876 12:12:44.699624 em Time Synchron<3>[ 18.237122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 12:12:44.699750 ized[0m.
10878 12:12:44.702728 <6>[ 18.241857] mc: Linux media interface: v0.10
10879 12:12:44.712885 <6>[ 18.245492] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10880 12:12:44.722531 <3>[ 18.269565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 12:12:44.726062 <6>[ 18.272418] usbcore: registered new interface driver r8152
10882 12:12:44.735716 <3>[ 18.277705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10883 12:12:44.748960 [[0;32m OK [0m] Started [0;1;39mDiscard unu<3>[ 18.295810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10884 12:12:44.758923 sed blocks once <3>[ 18.304221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 12:12:44.759019 a week[0m.
10886 12:12:44.765439 <4>[ 18.305108] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10887 12:12:44.772074 <6>[ 18.307593] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10888 12:12:44.778429 <6>[ 18.307595] videodev: Linux video capture interface: v2.00
10889 12:12:44.788553 <3>[ 18.313541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10890 12:12:44.794971 <3>[ 18.313557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 12:12:44.805263 <3>[ 18.313567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 12:12:44.811825 <3>[ 18.332093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 12:12:44.821690 <4>[ 18.345424] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10894 12:12:44.824753 <4>[ 18.345424] Fallback method does not support PEC.
10895 12:12:44.831696 <4>[ 18.353201] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10896 12:12:44.838168 <6>[ 18.363140] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10897 12:12:44.848249 <3>[ 18.369823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10898 12:12:44.858073 <3>[ 18.384423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 12:12:44.864996 <3>[ 18.388806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 12:12:44.871255 <6>[ 18.413867] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10901 12:12:44.881784 <3>[ 18.421057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10902 12:12:44.888774 <4>[ 18.421748] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10903 12:12:44.895649 <4>[ 18.421760] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10904 12:12:44.902103 <6>[ 18.427934] pci_bus 0000:00: root bus resource [bus 00-ff]
10905 12:12:44.912643 <3>[ 18.437860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 12:12:44.919418 <3>[ 18.443561] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 12:12:44.929286 <3>[ 18.444377] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10908 12:12:44.935932 <6>[ 18.445186] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10909 12:12:44.942896 <3>[ 18.453153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 12:12:44.952564 <6>[ 18.458880] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10911 12:12:44.962918 <3>[ 18.466964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10912 12:12:44.969648 <3>[ 18.466974] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10913 12:12:44.976611 <3>[ 18.466983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 12:12:44.983217 <3>[ 18.466995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 12:12:44.993323 <3>[ 18.467651] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 12:12:44.996873 <6>[ 18.474708] r8152 2-1.3:1.0 eth0: v1.12.13
10917 12:12:45.003372 <6>[ 18.475855] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10918 12:12:45.013471 <3>[ 18.484962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 12:12:45.020319 <3>[ 18.488248] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 12:12:45.027298 <6>[ 18.492062] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10921 12:12:45.037353 <6>[ 18.511189] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10922 12:12:45.044236 <6>[ 18.518248] pci 0000:00:00.0: supports D1 D2
10923 12:12:45.050770 <3>[ 18.522065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 12:12:45.060886 <6>[ 18.525163] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10925 12:12:45.067903 <6>[ 18.532683] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10926 12:12:45.074553 <6>[ 18.534648] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10927 12:12:45.084377 <3>[ 18.544835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 12:12:45.091072 <6>[ 18.549660] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10929 12:12:45.097524 <3>[ 18.566897] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10930 12:12:45.104635 <6>[ 18.568261] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10931 12:12:45.114922 <3>[ 18.575332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 12:12:45.121203 <3>[ 18.595742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 12:12:45.131366 <6>[ 18.599097] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10934 12:12:45.138350 <3>[ 18.629298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 12:12:45.144777 <6>[ 18.632026] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10936 12:12:45.151761 <3>[ 18.674985] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10937 12:12:45.158268 <6>[ 18.678727] pci 0000:01:00.0: supports D1 D2
10938 12:12:45.164944 <3>[ 18.694904] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10939 12:12:45.171314 <6>[ 18.702357] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10940 12:12:45.181109 <6>[ 18.708878] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10941 12:12:45.188054 <6>[ 18.722760] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10942 12:12:45.194659 <6>[ 18.736820] usbcore: registered new interface driver cdc_ether
10943 12:12:45.200994 <6>[ 18.743177] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10944 12:12:45.207753 <6>[ 18.757332] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10945 12:12:45.217909 <6>[ 18.757353] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10946 12:12:45.225066 <6>[ 18.757957] usbcore: registered new interface driver r8153_ecm
10947 12:12:45.231358 [[0;32m OK [<6>[ 18.760406] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10948 12:12:45.244840 0m] Reached targ<6>[ 18.764635] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10949 12:12:45.251205 <6>[ 18.764869] usbcore: registered new interface driver uvcvideo
10950 12:12:45.254770 <6>[ 18.774890] Bluetooth: Core ver 2.22
10951 12:12:45.264437 <6>[ 18.779443] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10952 12:12:45.271098 <6>[ 18.780762] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10953 12:12:45.274554 <6>[ 18.787960] NET: Registered PF_BLUETOOTH protocol family
10954 12:12:45.281021 <6>[ 18.788828] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10955 12:12:45.287778 <6>[ 18.792642] remoteproc remoteproc0: powering up scp
10956 12:12:45.297227 <4>[ 18.792691] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10957 12:12:45.304120 <3>[ 18.792699] remoteproc remoteproc0: request_firmware failed: -2
10958 12:12:45.310518 <3>[ 18.792703] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10959 12:12:45.317486 <6>[ 18.801691] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10960 12:12:45.324090 <6>[ 18.807680] Bluetooth: HCI device and connection manager initialized
10961 12:12:45.330617 <6>[ 18.807700] Bluetooth: HCI socket layer initialized
10962 12:12:45.333641 <6>[ 18.811520] pci 0000:00:00.0: PCI bridge to [bus 01]
10963 12:12:45.340424 <6>[ 18.819508] Bluetooth: L2CAP socket layer initialized
10964 12:12:45.346962 <6>[ 18.819522] Bluetooth: SCO socket layer initialized
10965 12:12:45.353894 <6>[ 18.825598] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10966 12:12:45.360312 <6>[ 18.875159] usbcore: registered new interface driver btusb
10967 12:12:45.370277 <4>[ 18.875948] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10968 12:12:45.377040 <3>[ 18.875957] Bluetooth: hci0: Failed to load firmware file (-2)
10969 12:12:45.383548 <3>[ 18.875961] Bluetooth: hci0: Failed to set up firmware (-2)
10970 12:12:45.393364 <4>[ 18.875964] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10971 12:12:45.399761 <6>[ 18.881140] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10972 12:12:45.406489 et [0;1;39mTime<6>[ 18.955773] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10973 12:12:45.406587 rs[0m.
10974 12:12:45.413003 <6>[ 18.963244] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10975 12:12:45.423899 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10976 12:12:45.433829 <5>[ 18.981631] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10977 12:12:45.440161 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10978 12:12:45.455830 <5>[ 19.003342] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10979 12:12:45.462212 <4>[ 19.010315] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10980 12:12:45.468749 <6>[ 19.019226] cfg80211: failed to load regulatory.db
10981 12:12:45.475327 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10982 12:12:45.514093 <6>[ 19.061699] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10983 12:12:45.520541 <6>[ 19.069279] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10984 12:12:45.527163 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10985 12:12:45.543471 <6>[ 19.094717] mt7921e 0000:01:00.0: ASIC revision: 79610010
10986 12:12:45.551832 Starting [0;1;39mUser Login Management[0m...
10987 12:12:45.570270 Starting [0;1;39mPermit User Sessions[0m...
10988 12:12:45.589609 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10989 12:12:45.616349 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10990 12:12:45.657978 <4>[ 19.202775] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10991 12:12:45.776107 <4>[ 19.320765] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10992 12:12:45.804356 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10993 12:12:45.815541 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10994 12:12:45.831890 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10995 12:12:45.855251 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10996 12:12:45.900760 <4>[ 19.445131] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 12:12:45.906737 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10998 12:12:45.965184 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10999 12:12:45.971961 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11000 12:12:45.988376 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11001 12:12:46.005724 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11002 12:12:46.021170 <4>[ 19.565961] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11003 12:12:46.064060 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11004 12:12:46.086254 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11005 12:12:46.106055 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11006 12:12:46.142451 Startin<4>[ 19.687589] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11007 12:12:46.148960 g [0;1;39mLoad/Save RF Kill Switch Status[0m...
11008 12:12:46.160033 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11009 12:12:46.184580 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11010 12:12:46.236443
11011 12:12:46.236606
11012 12:12:46.240024 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11013 12:12:46.240138
11014 12:12:46.242900 debian-bullseye-arm64 login: root (automatic login)
11015 12:12:46.243013
11016 12:12:46.243115
11017 12:12:46.265929 <4>[ 19.810145] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11018 12:12:46.272141 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
11019 12:12:46.272268
11020 12:12:46.278852 The programs included with the Debian GNU/Linux system are free software;
11021 12:12:46.285255 the exact distribution terms for each program are described in the
11022 12:12:46.288846 individual files in /usr/share/doc/*/copyright.
11023 12:12:46.288964
11024 12:12:46.295189 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11025 12:12:46.298818 permitted by applicable law.
11026 12:12:46.299300 Matched prompt #10: / #
11028 12:12:46.299611 Setting prompt string to ['/ #']
11029 12:12:46.299735 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11031 12:12:46.300038 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11032 12:12:46.300126 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11033 12:12:46.300199 Setting prompt string to ['/ #']
11034 12:12:46.300292 Forcing a shell prompt, looking for ['/ #']
11036 12:12:46.350548 / #
11037 12:12:46.350736 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11038 12:12:46.350845 Waiting using forced prompt support (timeout 00:02:30)
11039 12:12:46.355587
11040 12:12:46.355859 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11041 12:12:46.355954 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11042 12:12:46.356048 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11043 12:12:46.356134 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11044 12:12:46.356217 end: 2 depthcharge-action (duration 00:01:39) [common]
11045 12:12:46.356302 start: 3 lava-test-retry (timeout 00:07:57) [common]
11046 12:12:46.356387 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
11047 12:12:46.356457 Using namespace: common
11049 12:12:46.456755 / # #
11050 12:12:46.456951 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11051 12:12:46.457067 <4>[ 19.933200] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11052 12:12:46.461715 #
11053 12:12:46.462017 Using /lava-10605395
11055 12:12:46.562392 / # export SHELL=/bin/sh
11056 12:12:46.562633 <4>[ 20.053014] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11057 12:12:46.567683 export SHELL=/bin/sh
11059 12:12:46.668254 / # . /lava-10605395/environment
11060 12:12:46.668493 <4>[ 20.173045] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11061 12:12:46.673498 . /lava-10605395/environment
11063 12:12:46.774004 / # /lava-10605395/bin/lava-test-runner /lava-10605395/0
11064 12:12:46.774177 Test shell timeout: 10s (minimum of the action and connection timeout)
11065 12:12:46.774549 /lava-10605395/bin/lava-test-runner /lava-10605395/0<4>[ 20.292830] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11066 12:12:46.778825
11067 12:12:46.820908 + export TESTRUN_ID=0_igt-kms-medi<8>[ 20.354545] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 10605395_1.5.2.3.1>
11068 12:12:46.821051 atek
11069 12:12:46.821165 + cd /lava-10605395/0/tests/0_igt-kms-mediatek
11070 12:12:46.821236 + cat uuid
11071 12:12:46.821494 Received signal: <STARTRUN> 0_igt-kms-mediatek 10605395_1.5.2.3.1
11072 12:12:46.821569 Starting test lava.0_igt-kms-mediatek (10605395_1.5.2.3.1)
11073 12:12:46.821666 Skipping test definition patterns.
11074 12:12:46.821781 + UUID=10605395_1.5.2.3.1
11075 12:12:46.821849 + set +x
11076 12:12:46.834854 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_<8>[ 20.386070] <LAVA_SIGNAL_TESTSET START core_auth>
11077 12:12:46.835122 Received signal: <TESTSET> START core_auth
11078 12:12:46.835207 Starting test_set core_auth
11079 12:12:46.841304 flip_event_leak kms_prop_blob kms_setmode kms_vblank
11080 12:12:46.860731 <3>[ 20.411952] mt7921e 0000:01:00.0: hardware init failed
11081 12:12:46.867834 <14>[ 20.419265] [IGT] core_auth: executing
11082 12:12:46.874742 IGT-Version: 1.2<14>[ 20.423657] [IGT] core_auth: starting subtest getclient-simple
11083 12:12:46.881160 7.1-g766edf9 (aa<14>[ 20.431356] [IGT] core_auth: exiting, ret=0
11084 12:12:46.884184 rch64) (Linux: 6.1.31 aarch64)
11085 12:12:46.887720 Starting subtest: getclient-simple
11086 12:12:46.894327 Opened devic<8>[ 20.443170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11087 12:12:46.894578 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11089 12:12:46.897285 e: /dev/dri/card0
11090 12:12:46.900758 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11091 12:12:46.917044 <14>[ 20.468374] [IGT] core_auth: executing
11092 12:12:46.923686 IGT-Version: 1.2<14>[ 20.472750] [IGT] core_auth: starting subtest getclient-master-drop
11093 12:12:46.930269 7.1-g766edf9 (aa<14>[ 20.481016] [IGT] core_auth: exiting, ret=0
11094 12:12:46.933469 rch64) (Linux: 6.1.31 aarch64)
11095 12:12:46.936927 Starting subtest: getclient-master-drop
11096 12:12:46.943513 Opened <8>[ 20.492277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11097 12:12:46.943775 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11099 12:12:46.946605 device: /dev/dri/card0
11100 12:12:46.953191 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11101 12:12:46.967106 <14>[ 20.518417] [IGT] core_auth: executing
11102 12:12:46.973580 IGT-Version: 1.2<14>[ 20.523054] [IGT] core_auth: starting subtest basic-auth
11103 12:12:46.980558 7.1-g766edf9 (aa<14>[ 20.530122] [IGT] core_auth: exiting, ret=0
11104 12:12:46.983633 rch64) (Linux: 6.1.31 aarch64)
11105 12:12:46.983710 Opened device: /dev/dri/card0
11106 12:12:46.993559 Starting subtest:<8>[ 20.541633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11107 12:12:46.993636 basic-auth
11108 12:12:46.993871 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11110 12:12:47.000097 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11111 12:12:47.016399 <14>[ 20.567592] [IGT] core_auth: executing
11112 12:12:47.022763 IGT-Version: 1.2<14>[ 20.572109] [IGT] core_auth: starting subtest many-magics
11113 12:12:47.025980 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11114 12:12:47.029241 Opened device: /dev/dri/card0
11115 12:12:47.032562 Starting subtest: many-magics
11116 12:12:47.035832 Reopening device failed after 1020 opens
11117 12:12:47.042407 [1mSubtest many<14>[ 20.592582] [IGT] core_auth: exiting, ret=0
11118 12:12:47.045921 -magics: SUCCESS (0.013s)[0m
11119 12:12:47.056433 <8>[ 20.604930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11120 12:12:47.056689 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11122 12:12:47.060053 <8>[ 20.613428] <LAVA_SIGNAL_TESTSET STOP>
11123 12:12:47.060321 Received signal: <TESTSET> STOP
11124 12:12:47.060394 Closing test_set core_auth
11125 12:12:47.102335 <14>[ 20.653570] [IGT] core_getclient: executing
11126 12:12:47.108793 IGT-Version: 1.2<14>[ 20.658603] [IGT] core_getclient: exiting, ret=0
11127 12:12:47.112452 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11128 12:12:47.115495 Opened device: /dev/dri/card0
11129 12:12:47.121917 S<8>[ 20.670464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11130 12:12:47.122170 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11132 12:12:47.125316 UCCESS (0.006s)
11133 12:12:47.162519 <14>[ 20.713866] [IGT] core_getstats: executing
11134 12:12:47.169452 IGT-Version: 1.2<14>[ 20.718822] [IGT] core_getstats: exiting, ret=0
11135 12:12:47.172530 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11136 12:12:47.175643 Opened device: /dev/dri/card0
11137 12:12:47.182536 S<8>[ 20.730459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11138 12:12:47.182616 UCCESS (0.006s)
11139 12:12:47.182853 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11141 12:12:47.223039 <14>[ 20.774372] [IGT] core_getversion: executing
11142 12:12:47.229745 IGT-Version: 1.2<14>[ 20.779400] [IGT] core_getversion: exiting, ret=0
11143 12:12:47.232694 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11144 12:12:47.236390 Opened device: /dev/dri/card0
11145 12:12:47.243057 S<8>[ 20.791708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11146 12:12:47.243312 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11148 12:12:47.246201 UCCESS (0.006s)
11149 12:12:47.284928 <14>[ 20.836168] [IGT] core_setmaster_vs_auth: executing
11150 12:12:47.291528 IGT-Version: 1.2<14>[ 20.842010] [IGT] core_setmaster_vs_auth: exiting, ret=0
11151 12:12:47.298331 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11152 12:12:47.298417 Opened device: /dev/dri/card0
11153 12:12:47.307985 S<8>[ 20.854791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11154 12:12:47.308070 UCCESS (0.007s)
11155 12:12:47.308308 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11157 12:12:47.332630 <8>[ 20.884010] <LAVA_SIGNAL_TESTSET START drm_read>
11158 12:12:47.332885 Received signal: <TESTSET> START drm_read
11159 12:12:47.332957 Starting test_set drm_read
11160 12:12:47.355667 <14>[ 20.906858] [IGT] drm_read: executing
11161 12:12:47.362089 IGT-Version: 1.2<14>[ 20.911428] [IGT] drm_read: exiting, ret=77
11162 12:12:47.365324 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11163 12:12:47.368496 Opened device: /dev/dri/card0
11164 12:12:47.375449 N<8>[ 20.923465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11165 12:12:47.375706 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11167 12:12:47.378425 o KMS driver or no outputs, pipes: 8, outputs: 0
11168 12:12:47.381943 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11169 12:12:47.396895 <14>[ 20.948279] [IGT] drm_read: executing
11170 12:12:47.403623 IGT-Version: 1.2<14>[ 20.952930] [IGT] drm_read: exiting, ret=77
11171 12:12:47.407099 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11172 12:12:47.410097 Opened device: /dev/dri/card0
11173 12:12:47.417164 N<8>[ 20.964604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11174 12:12:47.417419 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11176 12:12:47.420127 o KMS driver or no outputs, pipes: 8, outputs: 0
11177 12:12:47.423197 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11178 12:12:47.438353 <14>[ 20.989455] [IGT] drm_read: executing
11179 12:12:47.444857 IGT-Version: 1.2<14>[ 20.994017] [IGT] drm_read: exiting, ret=77
11180 12:12:47.447852 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11181 12:12:47.451245 Opened device: /dev/dri/card0
11182 12:12:47.457720 N<8>[ 21.005989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11183 12:12:47.457977 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11185 12:12:47.461026 o KMS driver or no outputs, pipes: 8, outputs: 0
11186 12:12:47.464492 [1mSubtest empty-block: SKIP (0.000s)[0m
11187 12:12:47.479127 <14>[ 21.030645] [IGT] drm_read: executing
11188 12:12:47.485540 IGT-Version: 1.2<14>[ 21.035224] [IGT] drm_read: exiting, ret=77
11189 12:12:47.489111 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11190 12:12:47.492155 Opened device: /dev/dri/card0
11191 12:12:47.498798 N<8>[ 21.047048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11192 12:12:47.499056 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11194 12:12:47.502376 o KMS driver or no outputs, pipes: 8, outputs: 0
11195 12:12:47.505639 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11196 12:12:47.520882 <14>[ 21.072037] [IGT] drm_read: executing
11197 12:12:47.527456 IGT-Version: 1.2<14>[ 21.076594] [IGT] drm_read: exiting, ret=77
11198 12:12:47.530346 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11199 12:12:47.533830 Opened device: /dev/dri/card0
11200 12:12:47.540549 N<8>[ 21.088305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11201 12:12:47.540812 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11203 12:12:47.543498 o KMS driver or no outputs, pipes: 8, outputs: 0
11204 12:12:47.550422 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11205 12:12:47.562388 <14>[ 21.113679] [IGT] drm_read: executing
11206 12:12:47.569008 IGT-Version: 1.2<14>[ 21.118240] [IGT] drm_read: exiting, ret=77
11207 12:12:47.572240 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11208 12:12:47.575457 Opened device: /dev/dri/card0
11209 12:12:47.582290 N<8>[ 21.130054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11210 12:12:47.582578 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11212 12:12:47.585530 o KMS driver or no outputs, pipes: 8, outputs: 0
11213 12:12:47.591861 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11214 12:12:47.604210 <14>[ 21.155558] [IGT] drm_read: executing
11215 12:12:47.610689 IGT-Version: 1.2<14>[ 21.160098] [IGT] drm_read: exiting, ret=77
11216 12:12:47.614096 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11217 12:12:47.617073 Opened device: /dev/dri/card0
11218 12:12:47.624096 N<8>[ 21.171962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11219 12:12:47.624381 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11221 12:12:47.630723 o KMS driver or no outputs, pipe<8>[ 21.182065] <LAVA_SIGNAL_TESTSET STOP>
11222 12:12:47.630981 Received signal: <TESTSET> STOP
11223 12:12:47.631080 Closing test_set drm_read
11224 12:12:47.634107 s: 8, outputs: 0
11225 12:12:47.637024 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11226 12:12:47.656026 <8>[ 21.207616] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11227 12:12:47.656279 Received signal: <TESTSET> START kms_addfb_basic
11228 12:12:47.656350 Starting test_set kms_addfb_basic
11229 12:12:47.678521 <14>[ 21.229966] [IGT] kms_addfb_basic: executing
11230 12:12:47.685220 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11231 12:12:47.691827 <14>[ 21.239612] [IGT] kms_addfb_basic: starting subtest unused-handle
11232 12:12:47.691906 Opened device: /dev/dri/card0
11233 12:12:47.695236 Starting subtest: unused-handle
11234 12:12:47.701428 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11235 12:12:47.708409 Test requirement<14>[ 21.257255] [IGT] kms_addfb_basic: exiting, ret=0
11236 12:12:47.711349 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11237 12:12:47.721285 Test requirem<8>[ 21.269669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11238 12:12:47.721546 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11240 12:12:47.724794 ent: is_i915_device(fd)
11241 12:12:47.731284 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11242 12:12:47.734311 Test requirement: is_i915_device(fd)
11243 12:12:47.737935 No KMS driver or no outputs, pipes: 8, outputs: 0
11244 12:12:47.741397 <14>[ 21.294545] [IGT] kms_addfb_basic: executing
11245 12:12:47.747863 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11246 12:12:47.754860 <14>[ 21.303881] [IGT] kms_addfb_basic: starting subtest unused-pitches
11247 12:12:47.757895 Opened device: /dev/dri/card0
11248 12:12:47.761248 Starting subtest: unused-pitches
11249 12:12:47.764606 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11250 12:12:47.771261 Test requirement<14>[ 21.321483] [IGT] kms_addfb_basic: exiting, ret=0
11251 12:12:47.777664 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11252 12:12:47.784096 Test requirem<8>[ 21.334266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11253 12:12:47.784357 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11255 12:12:47.787726 ent: is_i915_device(fd)
11256 12:12:47.794207 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11257 12:12:47.797529 Test requirement: is_i915_device(fd)
11258 12:12:47.804171 No KMS driver or no outputs, pipes: 8, outputs: 0
11259 12:12:47.807075 <14>[ 21.359224] [IGT] kms_addfb_basic: executing
11260 12:12:47.814004 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11261 12:12:47.820330 <14>[ 21.368627] [IGT] kms_addfb_basic: starting subtest unused-offsets
11262 12:12:47.823806 Opened device: /dev/dri/card0
11263 12:12:47.823912 Starting subtest: unused-offsets
11264 12:12:47.830250 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11265 12:12:47.836905 Test requirement<14>[ 21.386146] [IGT] kms_addfb_basic: exiting, ret=0
11266 12:12:47.843321 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11267 12:12:47.850385 Test requirem<8>[ 21.398744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11268 12:12:47.850678 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11270 12:12:47.853392 ent: is_i915_device(fd)
11271 12:12:47.859761 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11272 12:12:47.863227 Test requirement: is_i915_device(fd)
11273 12:12:47.866712 No KMS driver or no outputs, pipes: 8, outputs: 0
11274 12:12:47.872973 <14>[ 21.424046] [IGT] kms_addfb_basic: executing
11275 12:12:47.876532 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11276 12:12:47.883045 <14>[ 21.433418] [IGT] kms_addfb_basic: starting subtest unused-modifier
11277 12:12:47.886062 Opened device: /dev/dri/card0
11278 12:12:47.889380 Starting subtest: unused-modifier
11279 12:12:47.896178 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11280 12:12:47.902710 Test requirement<14>[ 21.451157] [IGT] kms_addfb_basic: exiting, ret=0
11281 12:12:47.905908 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11282 12:12:47.916090 Test requirem<8>[ 21.463917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11283 12:12:47.916174 ent: is_i915_device(fd)
11284 12:12:47.916413 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11286 12:12:47.925860 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11287 12:12:47.929279 Test requirement: is_i915_device(fd)
11288 12:12:47.932671 No KMS driver or no outputs, pipes: 8, outputs: 0
11289 12:12:47.935703 <14>[ 21.489282] [IGT] kms_addfb_basic: executing
11290 12:12:47.942822 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11291 12:12:47.949349 <14>[ 21.498670] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11292 12:12:47.952314 Opened device: /dev/dri/card0
11293 12:12:47.955629 Starting subtest: clobberred-modifier
11294 12:12:47.965793 Test requirement not met in function igt_require_i915, fil<14>[ 21.516711] [IGT] kms_addfb_basic: exiting, ret=77
11295 12:12:47.968722 e ../lib/drmtest.c:721:
11296 12:12:47.972215 Test requirement: is_i915_device(fd)
11297 12:12:47.982252 [1mSubtest clobb<8>[ 21.529254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11298 12:12:47.982534 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11300 12:12:47.985394 erred-modifier: SKIP (0.000s)[0m
11301 12:12:47.991917 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11302 12:12:47.995277 Test requirement: is_i915_device(fd)
11303 12:12:48.001970 Test requirement not met in function igt_require_i91<14>[ 21.554754] [IGT] kms_addfb_basic: executing
11304 12:12:48.005227 5, file ../lib/drmtest.c:721:
11305 12:12:48.015358 Test requirement: is_i915_device(<14>[ 21.564792] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11306 12:12:48.018654 fd)
11307 12:12:48.022085 No KMS driver or no outputs, pipes: 8, outputs: 0
11308 12:12:48.028382 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11309 12:12:48.031808 Opened d<14>[ 21.583627] [IGT] kms_addfb_basic: exiting, ret=77
11310 12:12:48.035353 evice: /dev/dri/card0
11311 12:12:48.038457 Starting subtest: invalid-smem-bo-on-discrete
11312 12:12:48.048323 Test requi<8>[ 21.595992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11313 12:12:48.048605 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11315 12:12:48.054865 rement not met in function igt_require_intel, file ../lib/drmtest.c:716:
11316 12:12:48.058259 Test requirement: is_intel_device(fd)
11317 12:12:48.064918 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11318 12:12:48.071522 Test requirement not met in functio<14>[ 21.622241] [IGT] kms_addfb_basic: executing
11319 12:12:48.074564 n igt_require_i915, file ../lib/drmtest.c:721:
11320 12:12:48.084444 Test requirement<14>[ 21.632206] [IGT] kms_addfb_basic: starting subtest legacy-format
11321 12:12:48.084568 : is_i915_device(fd)
11322 12:12:48.091084 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11323 12:12:48.094700 Test requirement: is_i915_device(fd)
11324 12:12:48.100905 No KMS driver or no outputs, pipes: 8, outputs: 0
11325 12:12:48.104326 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11326 12:12:48.111085 Opened device:<14>[ 21.662342] [IGT] kms_addfb_basic: exiting, ret=0
11327 12:12:48.114459 /dev/dri/card0
11328 12:12:48.117623 Starting subtest: legacy-format
11329 12:12:48.124124 Successfully fuzzed 10000 {bpp<8>[ 21.674465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11330 12:12:48.124381 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11332 12:12:48.127384 , depth} variations
11333 12:12:48.130646 [1mSubtest legacy-format: SUCCESS (0.013s)[0m
11334 12:12:48.140703 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11335 12:12:48.143785 Test requirement: is_i915_device(fd)
11336 12:12:48.147419 Test requirement <14>[ 21.699516] [IGT] kms_addfb_basic: executing
11337 12:12:48.153814 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11338 12:12:48.163782 Test requirement: is_i915_devi<14>[ 21.712195] [IGT] kms_addfb_basic: starting subtest no-handle
11339 12:12:48.163867 ce(fd)
11340 12:12:48.166854 No KMS driver or no outputs, pipes: 8, outputs: 0
11341 12:12:48.176949 IGT-Version: 1.27.1-g766edf9 (aarch64<14>[ 21.726954] [IGT] kms_addfb_basic: exiting, ret=0
11342 12:12:48.180423 ) (Linux: 6.1.31 aarch64)
11343 12:12:48.180506 Opened device: /dev/dri/card0
11344 12:12:48.190355 Starting subtest: no-h<8>[ 21.739148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11345 12:12:48.190438 andle
11346 12:12:48.190675 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11348 12:12:48.193410 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11349 12:12:48.199982 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11350 12:12:48.203520 Test requirement: is_i915_device(fd)
11351 12:12:48.213396 Test requirement not met in functio<14>[ 21.763751] [IGT] kms_addfb_basic: executing
11352 12:12:48.216653 n igt_require_i915, file ../lib/drmtest.c:721:
11353 12:12:48.220008 Test requirement: is_i915_device(fd)
11354 12:12:48.226535 No KMS dri<14>[ 21.776629] [IGT] kms_addfb_basic: starting subtest basic
11355 12:12:48.229828 ver or no outputs, pipes: 8, outputs: 0
11356 12:12:48.239835 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 a<14>[ 21.790763] [IGT] kms_addfb_basic: exiting, ret=0
11357 12:12:48.239920 arch64)
11358 12:12:48.242845 Opened device: /dev/dri/card0
11359 12:12:48.246300 Starting subtest: basic
11360 12:12:48.252791 [1mSubtest bas<8>[ 21.802928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11361 12:12:48.253045 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11363 12:12:48.256342 ic: SUCCESS (0.000s)[0m
11364 12:12:48.262883 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11365 12:12:48.266226 Test requirement: is_i915_device(fd)
11366 12:12:48.275916 Test requirement not met in function igt_require_i915, file .<14>[ 21.827311] [IGT] kms_addfb_basic: executing
11367 12:12:48.279484 ./lib/drmtest.c:721:
11368 12:12:48.282520 Test requirement: is_i915_device(fd)
11369 12:12:48.289260 No KMS driver or no outputs, pipes: <14>[ 21.839956] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11370 12:12:48.292290 8, outputs: 0
11371 12:12:48.299374 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11372 12:12:48.305930 Opened device: /d<14>[ 21.854884] [IGT] kms_addfb_basic: exiting, ret=0
11373 12:12:48.306014 ev/dri/card0
11374 12:12:48.309016 Starting subtest: bad-pitch-0
11375 12:12:48.318817 [1mSubtest bad-pitch-0: SUCCESS (0<8>[ 21.867068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11376 12:12:48.318902 .000s)[0m
11377 12:12:48.319142 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11379 12:12:48.325522 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11380 12:12:48.328752 Test requirement: is_i915_device(fd)
11381 12:12:48.342159 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<14>[ 21.892019] [IGT] kms_addfb_basic: executing
11382 12:12:48.342309 c:721:
11383 12:12:48.345216 Test requirement: is_i915_device(fd)
11384 12:12:48.348784 No KMS driver or no outputs, pipes: 8, outputs: 0
11385 12:12:48.355131 <14>[ 21.904640] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11386 12:12:48.355218
11387 12:12:48.362173 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11388 12:12:48.365276 Opened device: /dev/dri/card0
11389 12:12:48.368620 <14>[ 21.919562] [IGT] kms_addfb_basic: exiting, ret=0
11390 12:12:48.371957 Starting subtest: bad-pitch-32
11391 12:12:48.374991 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11392 12:12:48.381667 <8>[ 21.931787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11393 12:12:48.381925 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11395 12:12:48.391616 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11396 12:12:48.395142 Test requirement: is_i915_device(fd)
11397 12:12:48.401658 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11398 12:12:48.404707 Test<14>[ 21.956593] [IGT] kms_addfb_basic: executing
11399 12:12:48.408266 requirement: is_i915_device(fd)
11400 12:12:48.411167 No KMS driver or no outputs, pipes: 8, outputs: 0
11401 12:12:48.421594 IGT-Version<14>[ 21.969408] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11402 12:12:48.424578 : 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11403 12:12:48.427941 Opened device: /dev/dri/card0
11404 12:12:48.434707 Starting sub<14>[ 21.984259] [IGT] kms_addfb_basic: exiting, ret=0
11405 12:12:48.434797 test: bad-pitch-63
11406 12:12:48.441278 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11407 12:12:48.447866 Test require<8>[ 21.996391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11408 12:12:48.448128 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11410 12:12:48.454202 ment not met in function igt_require_i915, file ../lib/drmtest.c:721:
11411 12:12:48.457570 Test requirement: is_i915_device(fd)
11412 12:12:48.464189 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11413 12:12:48.470653 Test requirement<14>[ 22.021283] [IGT] kms_addfb_basic: executing
11414 12:12:48.470744 : is_i915_device(fd)
11415 12:12:48.477098 No KMS driver or no outputs, pipes: 8, outputs: 0
11416 12:12:48.483963 IGT-Version: 1.27.1-g76<14>[ 22.034010] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11417 12:12:48.487060 6edf9 (aarch64) (Linux: 6.1.31 aarch64)
11418 12:12:48.490536 Opened device: /dev/dri/card0
11419 12:12:48.497078 Starting subtest: bad-pi<14>[ 22.049208] [IGT] kms_addfb_basic: exiting, ret=0
11420 12:12:48.500023 tch-128
11421 12:12:48.503553 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11422 12:12:48.513678 Test requirement not m<8>[ 22.061222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11423 12:12:48.513933 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11425 12:12:48.517083 et in function igt_require_i915, file ../lib/drmtest.c:721:
11426 12:12:48.519966 Test requirement: is_i915_device(fd)
11427 12:12:48.527003 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11428 12:12:48.536640 Test requirement: is_i915_<14>[ 22.086237] [IGT] kms_addfb_basic: executing
11429 12:12:48.536732 device(fd)
11430 12:12:48.539947 No KMS driver or no outputs, pipes: 8, outputs: 0
11431 12:12:48.549654 IGT-Version: 1.27.1-g766edf9 (aar<14>[ 22.099050] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11432 12:12:48.552949 ch64) (Linux: 6.1.31 aarch64)
11433 12:12:48.556588 Opened device: /dev/dri/card0
11434 12:12:48.559696 Starting subtest: bad-pitch-256
11435 12:12:48.563187 <14>[ 22.113853] [IGT] kms_addfb_basic: exiting, ret=0
11436 12:12:48.566128 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11437 12:12:48.575911 Test requirement not met in func<8>[ 22.126125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11438 12:12:48.576173 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11440 12:12:48.582618 tion igt_require_i915, file ../lib/drmtest.c:721:
11441 12:12:48.585671 Test requirement: is_i915_device(fd)
11442 12:12:48.592341 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11443 12:12:48.599114 Test requirement: is_i915_device(fd)<14>[ 22.151201] [IGT] kms_addfb_basic: executing
11444 12:12:48.599201
11445 12:12:48.605370 No KMS driver or no outputs, pipes: 8, outputs: 0
11446 12:12:48.615556 IGT-Version: 1.27.1-g766edf9 (aarch64) (Lin<14>[ 22.163874] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11447 12:12:48.615641 ux: 6.1.31 aarch64)
11448 12:12:48.619015 Opened device: /dev/dri/card0
11449 12:12:48.621999 Starting subtest: bad-pitch-1024
11450 12:12:48.628792 [1mSubtes<14>[ 22.179029] [IGT] kms_addfb_basic: exiting, ret=0
11451 12:12:48.631946 t bad-pitch-1024: SUCCESS (0.000s)[0m
11452 12:12:48.642004 Test requirement not met in function igt<8>[ 22.191293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11453 12:12:48.642278 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11455 12:12:48.645363 _require_i915, file ../lib/drmtest.c:721:
11456 12:12:48.648562 Test requirement: is_i915_device(fd)
11457 12:12:48.658350 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11458 12:12:48.661808 Test requirement: is_i915_device(fd)
11459 12:12:48.664883 No KMS<14>[ 22.216326] [IGT] kms_addfb_basic: executing
11460 12:12:48.668466 driver or no outputs, pipes: 8, outputs: 0
11461 12:12:48.681108 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.<14>[ 22.228999] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11462 12:12:48.681191 31 aarch64)
11463 12:12:48.684481 Opened device: /dev/dri/card0
11464 12:12:48.687981 Starting subtest: bad-pitch-999
11465 12:12:48.694484 [1mSubtest bad-pit<14>[ 22.243989] [IGT] kms_addfb_basic: exiting, ret=0
11466 12:12:48.694582 ch-999: SUCCESS (0.000s)[0m
11467 12:12:48.707776 Test requirement not met in function igt_require_i<8>[ 22.256357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11468 12:12:48.708043 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11470 12:12:48.710876 915, file ../lib/drmtest.c:721:
11471 12:12:48.713991 Test requirement: is_i915_device(fd)
11472 12:12:48.721135 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11473 12:12:48.723942 Test requirement: is_i915_device(fd)
11474 12:12:48.730898 No KMS driver or<14>[ 22.281311] [IGT] kms_addfb_basic: executing
11475 12:12:48.734004 no outputs, pipes: 8, outputs: 0
11476 12:12:48.744087 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64<14>[ 22.294043] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11477 12:12:48.744175 )
11478 12:12:48.747066 Opened device: /dev/dri/card0
11479 12:12:48.750484 Starting subtest: bad-pitch-65536
11480 12:12:48.757199 [1mSubtest bad-pitch-65536<14>[ 22.309283] [IGT] kms_addfb_basic: exiting, ret=0
11481 12:12:48.760332 : SUCCESS (0.000s)[0m
11482 12:12:48.773622 Test requirement not met in function igt_require_i915, f<8>[ 22.321389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11483 12:12:48.773712 ile ../lib/drmtest.c:721:
11484 12:12:48.773970 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11486 12:12:48.777035 Test requirement: is_i915_device(fd)
11487 12:12:48.786669 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11488 12:12:48.790109 Test requirement: is_i915_device(fd)
11489 12:12:48.796560 No KMS driver or no ou<14>[ 22.346488] [IGT] kms_addfb_basic: executing
11490 12:12:48.796641 tputs, pipes: 8, outputs: 0
11491 12:12:48.803198 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11492 12:12:48.806587 Opened device: /dev/dri/card0
11493 12:12:48.813176 <14>[ 22.361880] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11494 12:12:48.816587 Starting subtest: invalid-get-prop-any
11495 12:12:48.823150 [1mSubtest invalid-get-<14>[ 22.375103] [IGT] kms_addfb_basic: exiting, ret=0
11496 12:12:48.826143 prop-any: SUCCESS (0.000s)[0m
11497 12:12:48.839566 Test requirement not met in function igt_require<8>[ 22.387043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11498 12:12:48.839823 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11500 12:12:48.843042 _i915, file ../lib/drmtest.c:721:
11501 12:12:48.846108 Test requirement: is_i915_device(fd)
11502 12:12:48.852724 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11503 12:12:48.856175 Test requirement: is_i915_device(fd)
11504 12:12:48.862906 No KMS driver <14>[ 22.412463] [IGT] kms_addfb_basic: executing
11505 12:12:48.866157 or no outputs, pipes: 8, outputs: 0
11506 12:12:48.869459 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11507 12:12:48.879520 Opened device: /dev/dri/car<14>[ 22.427731] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11508 12:12:48.879608 d0
11509 12:12:48.882508 Starting subtest: invalid-get-prop
11510 12:12:48.889138 [1mSubtest invalid-get-prop<14>[ 22.441018] [IGT] kms_addfb_basic: exiting, ret=0
11511 12:12:48.892508 : SUCCESS (0.000s)[0m
11512 12:12:48.905587 Test requirement not met in function igt_require_i915, f<8>[ 22.453179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11513 12:12:48.905676 ile ../lib/drmtest.c:721:
11514 12:12:48.905936 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11516 12:12:48.908695 Test requirement: is_i915_device(fd)
11517 12:12:48.918575 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11518 12:12:48.922163 Test requirement: is_i915_device(fd)
11519 12:12:48.928586 No KMS driver or no ou<14>[ 22.478262] [IGT] kms_addfb_basic: executing
11520 12:12:48.928674 tputs, pipes: 8, outputs: 0
11521 12:12:48.934982 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11522 12:12:48.938514 Opened device: /dev/dri/card0
11523 12:12:48.945092 <14>[ 22.493463] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11524 12:12:48.948510 Starting subtest: invalid-set-prop-any
11525 12:12:48.955081 [1mSubtest invalid-set-<14>[ 22.506999] [IGT] kms_addfb_basic: exiting, ret=0
11526 12:12:48.958173 prop-any: SUCCESS (0.000s)[0m
11527 12:12:48.971520 Test requirement not met in function igt_require<8>[ 22.518784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11528 12:12:48.971855 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11530 12:12:48.974779 _i915, file ../lib/drmtest.c:721:
11531 12:12:48.978099 Test requirement: is_i915_device(fd)
11532 12:12:48.984843 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11533 12:12:48.987802 Test requirement: is_i915_device(fd)
11534 12:12:48.994790 No KMS driver <14>[ 22.544497] [IGT] kms_addfb_basic: executing
11535 12:12:48.998161 or no outputs, pipes: 8, outputs: 0
11536 12:12:49.001225 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11537 12:12:49.011265 Opened device: /dev/dri/car<14>[ 22.559529] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11538 12:12:49.011350 d0
11539 12:12:49.014600 Starting subtest: invalid-set-prop
11540 12:12:49.021091 [1mSubtest invalid-set-prop<14>[ 22.572801] [IGT] kms_addfb_basic: exiting, ret=0
11541 12:12:49.024530 : SUCCESS (0.000s)[0m
11542 12:12:49.037465 Test requirement not met in function igt_require_i915, f<8>[ 22.584852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11543 12:12:49.037558 ile ../lib/drmtest.c:721:
11544 12:12:49.037818 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11546 12:12:49.040779 Test requirement: is_i915_device(fd)
11547 12:12:49.047803 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11548 12:12:49.050808 Test requirement: is_i915_device(fd)
11549 12:12:49.057277 No KMS driver or no ou<14>[ 22.610286] [IGT] kms_addfb_basic: executing
11550 12:12:49.060762 tputs, pipes: 8, outputs: 0
11551 12:12:49.067758 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11552 12:12:49.070554 Opened device: /dev/dri/card0
11553 12:12:49.077219 <14>[ 22.627522] [IGT] kms_addfb_basic: starting subtest master-rmfb
11554 12:12:49.080596 Starting subtest: master-rmfb
11555 12:12:49.087184 [1mSubtest maste<14>[ 22.636919] [IGT] kms_addfb_basic: exiting, ret=0
11556 12:12:49.090470 r-rmfb: SUCCESS (0.000s)[0m
11557 12:12:49.100444 Test requirement not met in function igt_require_i<8>[ 22.649755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11558 12:12:49.100720 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11560 12:12:49.103928 915, file ../lib/drmtest.c:721:
11561 12:12:49.107002 Test requirement: is_i915_device(fd)
11562 12:12:49.113551 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11563 12:12:49.116987 Test requirement: is_i915_device(fd)
11564 12:12:49.123488 No KMS driver or<14>[ 22.674543] [IGT] kms_addfb_basic: executing
11565 12:12:49.126973 no outputs, pipes: 8, outputs: 0
11566 12:12:49.133264 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11567 12:12:49.133384 Opened device: /dev/dri/card0
11568 12:12:49.145558 <14>[ 22.693867] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11569 12:12:49.152064 Starting subtest<14>[ 22.701828] [IGT] kms_addfb_basic: exiting, ret=0
11570 12:12:49.152155 : addfb25-modifier-no-flag
11571 12:12:49.165173 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000<8>[ 22.714246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11572 12:12:49.165263 s)[0m
11573 12:12:49.165547 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11575 12:12:49.175208 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11576 12:12:49.178317 Test requirement: is_i915_device(fd)
11577 12:12:49.188575 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 22.739840] [IGT] kms_addfb_basic: executing
11578 12:12:49.188676 1:
11579 12:12:49.191758 Test requirement: is_i915_device(fd)
11580 12:12:49.198411 No KMS driver or no outputs, pipes: 8, outputs: 0
11581 12:12:49.201482 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11582 12:12:49.211963 Opened device: /dev<14>[ 22.759937] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11583 12:12:49.212052 /dri/card0
11584 12:12:49.214782 Starting subtest: addfb25-bad-modifier
11585 12:12:49.228297 (kms_addfb_basic:432) CRITICAL: Test assertion failure function addfb25_<14>[ 22.777668] [IGT] kms_addfb_basic: exiting, ret=98
11586 12:12:49.231629 tests, file ../tests/kms_addfb_basic.c:662:
11587 12:12:49.241615 (kms_addfb_basic:432) CRITICAL: Fai<8>[ 22.790408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11588 12:12:49.241880 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11590 12:12:49.258107 led assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11591 12:12:49.264482 (kms_addfb_basic:432) CRITICAL: error<14>[ 22.815919] [IGT] kms_addfb_basic: executing
11592 12:12:49.264588 : 0 != -1
11593 12:12:49.268029 Stack trace:
11594 12:12:49.271069 #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11595 12:12:49.274615 #1 [<unknown>+0xbe3247e0]
11596 12:12:49.274723 #2 [<unknown>+0xbe326278]
11597 12:12:49.277614 #3 [<unknown>+0xbe32167c]
11598 12:12:49.284369 #4 [__libc_st<14>[ 22.835808] [IGT] kms_addfb_basic: exiting, ret=77
11599 12:12:49.287611 art_main+0xe8]
11600 12:12:49.287698 #5 [<unknown>+0xbe3216b4]
11601 12:12:49.291021 #6 [<unknown>+0xbe3216b4]
11602 12:12:49.300963 Subtes<8>[ 22.848184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11603 12:12:49.301275 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11605 12:12:49.304130 t addfb25-bad-modifier failed.
11606 12:12:49.304240 **** DEBUG ****
11607 12:12:49.313963 (kms_addfb_basic:432) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11608 12:12:49.323953 (kms_addfb_basic:432) CRITICAL: Test assertion failure function <14>[ 22.874490] [IGT] kms_addfb_basic: executing
11609 12:12:49.327398 addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11610 12:12:49.343706 (kms_addfb_basic:432) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0<14>[ 22.894833] [IGT] kms_addfb_basic: exiting, ret=77
11611 12:12:49.356967 xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -<8>[ 22.907226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11612 12:12:49.357246 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11614 12:12:49.360419 1
11615 12:12:49.363447 (kms_addfb_basic:432) CRITICAL: error: 0 != -1
11616 12:12:49.366982 (kms_addfb_basic:432) igt_core-INFO: Stack trace:
11617 12:12:49.373390 (kms_addfb_basic:432) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11618 12:12:49.380035 (kms_addfb_basic:432<14>[ 22.932702] [IGT] kms_addfb_basic: executing
11619 12:12:49.386930 ) igt_core-INFO: #1 [<unknown>+0xbe3247e0]
11620 12:12:49.390188 (kms_addfb_basic:432) igt_core-INFO: #2 [<unknown>+0xbe326278]
11621 12:12:49.403313 (kms_addfb_basic:432) igt_core-INFO: #3 [<unknown>+0xbe32167c]<14>[ 22.952584] [IGT] kms_addfb_basic: exiting, ret=77
11622 12:12:49.403424
11623 12:12:49.406219 (kms_addfb_basic:432) igt_core-INFO: #4 [__libc_start_main+0xe8]
11624 12:12:49.416351 (kms_addfb<8>[ 22.964769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11625 12:12:49.416622 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11627 12:12:49.423017 _basic:432) igt_core-INFO: #5 [<unknown>+0xbe3216b4]
11628 12:12:49.429567 (kms_addfb_basic:432) igt_core-INFO: #6 [<unknown>+0xbe3216b4]
11629 12:12:49.429653 **** END ****
11630 12:12:49.433063 [1mSubtest addfb25-bad-modifier: FAIL (0.009s)[0m
11631 12:12:49.439455 Test requirement<14>[ 22.991281] [IGT] kms_addfb_basic: executing
11632 12:12:49.446160 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11633 12:12:49.449271 Test requirement: is_i915_device(fd)
11634 12:12:49.459390 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 23.011563] [IGT] kms_addfb_basic: exiting, ret=77
11635 12:12:49.462681 est.c:721:
11636 12:12:49.465675 Test requirement: is_i915_device(fd)
11637 12:12:49.475753 No KMS driver or no outputs, p<8>[ 23.023754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11638 12:12:49.475842 ipes: 8, outputs: 0
11639 12:12:49.476089 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11641 12:12:49.482296 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11642 12:12:49.485753 Opened device: /dev/dri/card0
11643 12:12:49.492389 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11644 12:12:49.499138 Test requ<14>[ 23.049207] [IGT] kms_addfb_basic: executing
11645 12:12:49.499224 irement: is_i915_device(fd)
11646 12:12:49.505601 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11647 12:12:49.512014 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11648 12:12:49.518576 <14>[ 23.069224] [IGT] kms_addfb_basic: exiting, ret=77
11649 12:12:49.522093 Test requirement: is_i915_device(fd)
11650 12:12:49.531762 No KMS driver or no outputs, pipes: 8, out<8>[ 23.081618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11651 12:12:49.532023 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11653 12:12:49.535259 puts: 0
11654 12:12:49.538429 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11655 12:12:49.541962 Opened device: /dev/dri/card0
11656 12:12:49.548472 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11657 12:12:49.554935 Test requirement: is_<14>[ 23.107510] [IGT] kms_addfb_basic: executing
11658 12:12:49.557986 i915_device(fd)
11659 12:12:49.561340 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11660 12:12:49.568180 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11661 12:12:49.578282 Test requirement: is_<14>[ 23.127642] [IGT] kms_addfb_basic: exiting, ret=77
11662 12:12:49.578369 i915_device(fd)
11663 12:12:49.581280 No KMS driver or no outputs, pipes: 8, outputs: 0
11664 12:12:49.591220 IGT-Version:<8>[ 23.139786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11665 12:12:49.591482 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11667 12:12:49.594694 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11668 12:12:49.597831 Opened device: /dev/dri/card0
11669 12:12:49.604494 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11670 12:12:49.608239 Test requirement: is_i915_device(fd)
11671 12:12:49.614500 [1m<14>[ 23.165057] [IGT] kms_addfb_basic: executing
11672 12:12:49.617922 Subtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11673 12:12:49.627844 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11674 12:12:49.634441 Test requirement: is_i915_devic<14>[ 23.185160] [IGT] kms_addfb_basic: exiting, ret=77
11675 12:12:49.634526 e(fd)
11676 12:12:49.640983 No KMS driver or no outputs, pipes: 8, outputs: 0
11677 12:12:49.647368 IGT-Version: 1.27.1-g7<8>[ 23.197268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11678 12:12:49.647642 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11680 12:12:49.654310 66edf9 (aarch64) (Linux: 6.1.31 aarch64)
11681 12:12:49.654396 Opened device: /dev/dri/card0
11682 12:12:49.663857 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11683 12:12:49.667273 Test requirement: is_i915_device(fd)
11684 12:12:49.670652 Test requireme<14>[ 23.222930] [IGT] kms_addfb_basic: executing
11685 12:12:49.677114 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11686 12:12:49.680647 Test requirement: is_i915_device(fd)
11687 12:12:49.684098 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11688 12:12:49.690512 No KMS driver or<14>[ 23.243009] [IGT] kms_addfb_basic: exiting, ret=77
11689 12:12:49.693512 no outputs, pipes: 8, outputs: 0
11690 12:12:49.706661 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux<8>[ 23.254961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11691 12:12:49.706777 : 6.1.31 aarch64)
11692 12:12:49.707051 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11694 12:12:49.709967 Opened device: /dev/dri/card0
11695 12:12:49.716508 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11696 12:12:49.720312 Test requirement: is_i915_device(fd)
11697 12:12:49.726537 Test requirement not met in function <14>[ 23.279368] [IGT] kms_addfb_basic: executing
11698 12:12:49.733465 igt_require_i915, file ../lib/drmtest.c:721:
11699 12:12:49.736461 Test requirement: is_i915_device(fd)
11700 12:12:49.740029 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11701 12:12:49.749937 No KMS driver or no outputs, pipes<14>[ 23.299625] [IGT] kms_addfb_basic: exiting, ret=77
11702 12:12:49.750060 : 8, outputs: 0
11703 12:12:49.756485 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11704 12:12:49.762994 <8>[ 23.311994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11705 12:12:49.763076
11706 12:12:49.763316 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11708 12:12:49.766547 Opened device: /dev/dri/card0
11709 12:12:49.772823 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11710 12:12:49.776365 Test requirement: is_i915_device(fd)
11711 12:12:49.786325 Test requirement not met in function igt_require_i915, <14>[ 23.336288] [IGT] kms_addfb_basic: executing
11712 12:12:49.786410 file ../lib/drmtest.c:721:
11713 12:12:49.789701 Test requirement: is_i915_device(fd)
11714 12:12:49.796283 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11715 12:12:49.799391 No KMS driver or no outputs, pipes: 8, outputs: 0
11716 12:12:49.805870 IGT-Ver<14>[ 23.356444] [IGT] kms_addfb_basic: exiting, ret=77
11717 12:12:49.809342 sion: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11718 12:12:49.819094 Opened device: /dev/dri<8>[ 23.368400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11719 12:12:49.819178 /card0
11720 12:12:49.819463 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11722 12:12:49.826012 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11723 12:12:49.828869 Test requirement: is_i915_device(fd)
11724 12:12:49.841951 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 23.393153] [IGT] kms_addfb_basic: executing
11725 12:12:49.842063 1:
11726 12:12:49.845461 Test requirement: is_i915_device(fd)
11727 12:12:49.848570 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11728 12:12:49.855513 No KMS driver or no outputs, pipes: 8, outputs: 0
11729 12:12:49.861964 IGT-Version: 1.27.1-g766edf9 (<14>[ 23.413102] [IGT] kms_addfb_basic: exiting, ret=77
11730 12:12:49.865476 aarch64) (Linux: 6.1.31 aarch64)
11731 12:12:49.868413 Opened device: /dev/dri/card0
11732 12:12:49.875349 Test requiremen<8>[ 23.424995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11733 12:12:49.875635 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11735 12:12:49.881748 t not met in function igt_require_i915, file ../lib/drmtest.c:721:
11736 12:12:49.885336 Test requirement: is_i915_device(fd)
11737 12:12:49.891743 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11738 12:12:49.898259 Test requirement: i<14>[ 23.449772] [IGT] kms_addfb_basic: executing
11739 12:12:49.901795 s_i915_device(fd)
11740 12:12:49.904777 No KMS driver or no outputs, pipes: 8, outputs: 0
11741 12:12:49.908331 [1mSubtest size-max: SKIP (0.000s)[0m
11742 12:12:49.914660 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11743 12:12:49.918232 O<14>[ 23.470089] [IGT] kms_addfb_basic: exiting, ret=77
11744 12:12:49.921250 pened device: /dev/dri/card0
11745 12:12:49.931487 Test requirement not met in function igt_require_i<8>[ 23.482368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11746 12:12:49.931842 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11748 12:12:49.934603 915, file ../lib/drmtest.c:721:
11749 12:12:49.937749 Test requirement: is_i915_device(fd)
11750 12:12:49.947955 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11751 12:12:49.951161 Test requirement: is_i915_device(fd)
11752 12:12:49.954127 No KMS driver or<14>[ 23.506792] [IGT] kms_addfb_basic: executing
11753 12:12:49.957606 no outputs, pipes: 8, outputs: 0
11754 12:12:49.961292 [1mSubtest too-wide: SKIP (0.000s)[0m
11755 12:12:49.967724 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11756 12:12:49.970704 Opened device: /dev/dri/card0
11757 12:12:49.977371 Test <14>[ 23.526820] [IGT] kms_addfb_basic: exiting, ret=77
11758 12:12:49.984121 requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11759 12:12:49.990734 Te<8>[ 23.539049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11760 12:12:49.990990 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11762 12:12:49.994352 st requirement: is_i915_device(fd)
11763 12:12:50.000502 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11764 12:12:50.004175 Test requirement: is_i915_device(fd)
11765 12:12:50.010674 No KMS driver or no outputs, pipes: 8, outputs: 0
11766 12:12:50.013809 <14>[ 23.564740] [IGT] kms_addfb_basic: executing
11767 12:12:50.017248 [1mSubtest too-high: SKIP (0.000s)[0m
11768 12:12:50.023712 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11769 12:12:50.027142 Opened device: /dev/dri/card0
11770 12:12:50.033735 Test requirement not met in function igt<14>[ 23.585242] [IGT] kms_addfb_basic: exiting, ret=77
11771 12:12:50.037050 _require_i915, file ../lib/drmtest.c:721:
11772 12:12:50.040277 Test requirement: is_i915_device(fd)
11773 12:12:50.050301 <8>[ 23.597630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11774 12:12:50.050382
11775 12:12:50.050618 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11777 12:12:50.056642 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11778 12:12:50.060016 Test requirement: is_i915_device(fd)
11779 12:12:50.063611 No KMS driver or no outputs, pipes: 8, outputs: 0
11780 12:12:50.073417 [1mSubtest bo-too-small: SKIP (0.0<14>[ 23.623036] [IGT] kms_addfb_basic: executing
11781 12:12:50.073535 00s)[0m
11782 12:12:50.079949 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11783 12:12:50.080059 Opened device: /dev/dri/card0
11784 12:12:50.093023 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 23.643092] [IGT] kms_addfb_basic: exiting, ret=77
11785 12:12:50.093108 est.c:721:
11786 12:12:50.096506 Test requirement: is_i915_device(fd)
11787 12:12:50.106224 Test requirement not met in fu<8>[ 23.655410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11788 12:12:50.106480 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11790 12:12:50.112521 nction igt_require_i915, file ../lib/drmtest.c:721:
11791 12:12:50.116005 Test requirement: is_i915_device(fd)
11792 12:12:50.119586 No KMS driver or no outputs, pipes: 8, outputs: 0
11793 12:12:50.122760 [1mSubtest small-bo: SKIP (0.000s)[0m
11794 12:12:50.129353 IGT-Version: 1.27.1-g766e<14>[ 23.680927] [IGT] kms_addfb_basic: executing
11795 12:12:50.132786 df9 (aarch64) (Linux: 6.1.31 aarch64)
11796 12:12:50.136216 Opened device: /dev/dri/card0
11797 12:12:50.142738 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11798 12:12:50.149355 Test requirement: is_i9<14>[ 23.701072] [IGT] kms_addfb_basic: exiting, ret=77
11799 12:12:50.152501 15_device(fd)
11800 12:12:50.165702 Test requirement not met in function igt_require_i915, file ../li<8>[ 23.713510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11801 12:12:50.165788 b/drmtest.c:721:
11802 12:12:50.166028 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11804 12:12:50.168926 Test requirement: is_i915_device(fd)
11805 12:12:50.175383 No KMS driver or no outputs, pipes: 8, outputs: 0
11806 12:12:50.178849 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11807 12:12:50.188706 IGT-Version: 1.27.1-g766edf9 (aarch64) (Li<14>[ 23.739519] [IGT] kms_addfb_basic: executing
11808 12:12:50.188813 nux: 6.1.31 aarch64)
11809 12:12:50.192251 Opened device: /dev/dri/card0
11810 12:12:50.198670 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11811 12:12:50.202295 Test requirement: is_i915_device(fd)
11812 12:12:50.208705 Te<14>[ 23.759366] [IGT] kms_addfb_basic: exiting, ret=77
11813 12:12:50.215199 st requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11814 12:12:50.221782 <8>[ 23.771842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11815 12:12:50.221865
11816 12:12:50.222122 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11818 12:12:50.228436 Test requirement: is_i915_devic<8>[ 23.781249] <LAVA_SIGNAL_TESTSET STOP>
11819 12:12:50.228695 Received signal: <TESTSET> STOP
11820 12:12:50.228829 Closing test_set kms_addfb_basic
11821 12:12:50.231435 e(fd)
11822 12:12:50.235015 No KMS driver or no outputs, pipes: 8, outputs: 0
11823 12:12:50.238618 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11824 12:12:50.245101 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11825 12:12:50.248066 Opened device: /dev/dri/card0
11826 12:12:50.254837 Test requirement not met in func<8>[ 23.806927] <LAVA_SIGNAL_TESTSET START kms_atomic>
11827 12:12:50.255099 Received signal: <TESTSET> START kms_atomic
11828 12:12:50.255201 Starting test_set kms_atomic
11829 12:12:50.261261 tion igt_require_i915, file ../lib/drmtest.c:721:
11830 12:12:50.264756 Test requirement: is_i915_device(fd)
11831 12:12:50.271310 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11832 12:12:50.277775 Test requirement: is_i915_device(fd)<14>[ 23.829227] [IGT] kms_atomic: executing
11833 12:12:50.277907
11834 12:12:50.284473 No KMS driver <14>[ 23.835275] [IGT] kms_atomic: exiting, ret=77
11835 12:12:50.287508 or no outputs, pipes: 8, outputs: 0
11836 12:12:50.297691 [1mSubtest addfb25-yf-tiled-legacy: SKIP (<8>[ 23.846796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11837 12:12:50.297947 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11839 12:12:50.301085 0.000s)[0m
11840 12:12:50.304485 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11841 12:12:50.307490 Opened device: /dev/dri/card0
11842 12:12:50.314041 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11843 12:12:50.320469 Test requirement:<14>[ 23.872690] [IGT] kms_atomic: executing
11844 12:12:50.327593 is_i915_device(<14>[ 23.878056] [IGT] kms_atomic: exiting, ret=77
11845 12:12:50.327678 fd)
11846 12:12:50.340674 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<8>[ 23.889972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11847 12:12:50.340934 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11849 12:12:50.344049 c:721:
11850 12:12:50.346950 Test requirement: is_i915_device(fd)
11851 12:12:50.350282 No KMS driver or no outputs, pipes: 8, outputs: 0
11852 12:12:50.353790 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11853 12:12:50.360383 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11854 12:12:50.363614 Op<14>[ 23.916497] [IGT] kms_atomic: executing
11855 12:12:50.370246 ened device: /de<14>[ 23.922658] [IGT] kms_atomic: exiting, ret=77
11856 12:12:50.373515 v/dri/card0
11857 12:12:50.387081 Test requirement not met in function igt_require_i915, file ../lib/<8>[ 23.934191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11858 12:12:50.387342 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11860 12:12:50.390291 drmtest.c:721:
11861 12:12:50.393794 Test requirement: is_i915_device(fd)
11862 12:12:50.400115 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11863 12:12:50.403566 Test requirement: is_i915_device(fd)
11864 12:12:50.410220 No KMS driver or no outputs, pipe<14>[ 23.960761] [IGT] kms_atomic: executing
11865 12:12:50.416929 s: 8, outputs: 0<14>[ 23.966625] [IGT] kms_atomic: exiting, ret=77
11866 12:12:50.417012
11867 12:12:50.419949 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11868 12:12:50.429856 IGT-Version: 1.27.1-g766edf9 (<8>[ 23.978326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11869 12:12:50.430109 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11871 12:12:50.433009 aarch64) (Linux: 6.1.31 aarch64)
11872 12:12:50.436533 Opened device: /dev/dri/card0
11873 12:12:50.439713 No KMS driver or no outputs, pipes: 8, outputs: 0
11874 12:12:50.446646 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11875 12:12:50.453038 IGT-Version: 1.27.1-g766edf9 (aarch64) <14>[ 24.004260] [IGT] kms_atomic: executing
11876 12:12:50.459690 (Linux: 6.1.31 a<14>[ 24.009653] [IGT] kms_atomic: exiting, ret=77
11877 12:12:50.459774 arch64)
11878 12:12:50.463231 Opened device: /dev/dri/card0
11879 12:12:50.472652 No KMS driver or no outputs, pipes: 8, o<8>[ 24.021546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11880 12:12:50.472737 utputs: 0
11881 12:12:50.473013 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11883 12:12:50.476034 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11884 12:12:50.482657 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11885 12:12:50.485866 Opened device: /dev/dri/card0
11886 12:12:50.495927 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 24.046229] [IGT] kms_atomic: executing
11887 12:12:50.496011
11888 12:12:50.499365 [1mSubtest pl<14>[ 24.051734] [IGT] kms_atomic: exiting, ret=77
11889 12:12:50.505817 ane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11890 12:12:50.515810 IGT-Version: 1.27.1-g766edf<8>[ 24.063605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11891 12:12:50.516065 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11893 12:12:50.519332 9 (aarch64) (Linux: 6.1.31 aarch64)
11894 12:12:50.522347 Opened device: /dev/dri/card0
11895 12:12:50.525779 No KMS driver or no outputs, pipes: 8, outputs: 0
11896 12:12:50.529230 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11897 12:12:50.539285 IGT-Version: 1.27.1-g766edf9 (aarch6<14>[ 24.089184] [IGT] kms_atomic: executing
11898 12:12:50.542269 4) (Linux: 6.1.3<14>[ 24.094732] [IGT] kms_atomic: exiting, ret=77
11899 12:12:50.545818 1 aarch64)
11900 12:12:50.548737 Opened device: /dev/dri/card0
11901 12:12:50.558886 No KMS driver or no outputs, pipes: 8<8>[ 24.106387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11902 12:12:50.558981 , outputs: 0
11903 12:12:50.559225 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11905 12:12:50.561921 [1mSubtest test-only: SKIP (0.000s)[0m
11906 12:12:50.568807 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11907 12:12:50.572138 Opened device: /dev/dri/card0
11908 12:12:50.574989 No KMS driver or no outputs, pipes: 8, outputs: 0
11909 12:12:50.581823 [1mSu<14>[ 24.132368] [IGT] kms_atomic: executing
11910 12:12:50.585199 btest plane-curs<14>[ 24.137648] [IGT] kms_atomic: exiting, ret=77
11911 12:12:50.588417 or-legacy: SKIP (0.000s)[0m
11912 12:12:50.601650 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1<8>[ 24.149433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11913 12:12:50.601736 .31 aarch64)
11914 12:12:50.601977 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11916 12:12:50.604906 Opened device: /dev/dri/card0
11917 12:12:50.611342 No KMS driver or no outputs, pipes: 8, outputs: 0
11918 12:12:50.614847 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11919 12:12:50.624495 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch<14>[ 24.175749] [IGT] kms_atomic: executing
11920 12:12:50.624581 64)
11921 12:12:50.631095 Opened devi<14>[ 24.181202] [IGT] kms_atomic: exiting, ret=77
11922 12:12:50.631179 ce: /dev/dri/card0
11923 12:12:50.634759 No KMS driver or no outputs, pipes: 8, outputs: 0
11924 12:12:50.644419 [1mSubte<8>[ 24.192926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11925 12:12:50.644674 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11927 12:12:50.647924 st plane-invalid-params-fence: SKIP (0.000s)[0m
11928 12:12:50.654340 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11929 12:12:50.657858 Opened device: /dev/dri/card0
11930 12:12:50.661176 No KMS driver or no outputs, pipes: 8, outputs: 0
11931 12:12:50.667776 [1mSubtest <14>[ 24.218948] [IGT] kms_atomic: executing
11932 12:12:50.673974 crtc-invalid-par<14>[ 24.224131] [IGT] kms_atomic: exiting, ret=77
11933 12:12:50.674053 ams: SKIP (0.000s)[0m
11934 12:12:50.687352 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aa<8>[ 24.235929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11935 12:12:50.687436 rch64)
11936 12:12:50.687682 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11938 12:12:50.690737 Opened device: /dev/dri/card0
11939 12:12:50.697353 No KMS driver or no outputs, pipes: 8, outputs: 0
11940 12:12:50.700552 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11941 12:12:50.710099 <14>[ 24.262053] [IGT] kms_atomic: executing
11942 12:12:50.716675 IGT-Version: 1.2<14>[ 24.266869] [IGT] kms_atomic: exiting, ret=77
11943 12:12:50.719776 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11944 12:12:50.723353 Opened device: /dev/dri/card0
11945 12:12:50.729944 N<8>[ 24.278486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11946 12:12:50.730199 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11948 12:12:50.733364 o KMS driver or no outputs, pipes: 8, outputs: 0
11949 12:12:50.739775 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11950 12:12:50.752794 <14>[ 24.304413] [IGT] kms_atomic: executing
11951 12:12:50.759417 IGT-Version: 1.2<14>[ 24.309129] [IGT] kms_atomic: exiting, ret=77
11952 12:12:50.762313 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11953 12:12:50.765818 Opened device: /dev/dri/card0
11954 12:12:50.772303 N<8>[ 24.321285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11955 12:12:50.772620 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11957 12:12:50.779100 o KMS driver or no outputs, pipe<8>[ 24.331335] <LAVA_SIGNAL_TESTSET STOP>
11958 12:12:50.779375 Received signal: <TESTSET> STOP
11959 12:12:50.779473 Closing test_set kms_atomic
11960 12:12:50.782505 s: 8, outputs: 0
11961 12:12:50.785572 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11962 12:12:50.805265 <8>[ 24.356898] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11963 12:12:50.805515 Received signal: <TESTSET> START kms_flip_event_leak
11964 12:12:50.805589 Starting test_set kms_flip_event_leak
11965 12:12:50.827996 <14>[ 24.379939] [IGT] kms_flip_event_leak: executing
11966 12:12:50.834957 IGT-Version: 1.2<14>[ 24.385421] [IGT] kms_flip_event_leak: exiting, ret=77
11967 12:12:50.837918 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11968 12:12:50.841436 Opened device: /dev/dri/card0
11969 12:12:50.848117 N<8>[ 24.398206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11970 12:12:50.848371 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11972 12:12:50.854539 o KMS driver or no outputs, pipe<8>[ 24.407269] <LAVA_SIGNAL_TESTSET STOP>
11973 12:12:50.854792 Received signal: <TESTSET> STOP
11974 12:12:50.854861 Closing test_set kms_flip_event_leak
11975 12:12:50.858105 s: 8, outputs: 0
11976 12:12:50.861074 [1mSubtest basic: SKIP (0.000s)[0m
11977 12:12:50.880954 <8>[ 24.432836] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11978 12:12:50.881208 Received signal: <TESTSET> START kms_prop_blob
11979 12:12:50.881278 Starting test_set kms_prop_blob
11980 12:12:50.903516 <14>[ 24.455449] [IGT] kms_prop_blob: executing
11981 12:12:50.910280 IGT-Version: 1.2<14>[ 24.460261] [IGT] kms_prop_blob: starting subtest basic
11982 12:12:50.917036 7.1-g766edf9 (aa<14>[ 24.467166] [IGT] kms_prop_blob: exiting, ret=0
11983 12:12:50.920389 rch64) (Linux: 6.1.31 aarch64)
11984 12:12:50.923725 Opened device: /dev/dri/card0
11985 12:12:50.929953 Starting subtest:<8>[ 24.479697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11986 12:12:50.930064 basic
11987 12:12:50.930334 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11989 12:12:50.933504 [1mSubtest basic: SUCCESS (0.000s)[0m
11990 12:12:50.952173 <14>[ 24.503968] [IGT] kms_prop_blob: executing
11991 12:12:50.958839 IGT-Version: 1.2<14>[ 24.508798] [IGT] kms_prop_blob: starting subtest blob-prop-core
11992 12:12:50.965191 7.1-g766edf9 (aa<14>[ 24.516451] [IGT] kms_prop_blob: exiting, ret=0
11993 12:12:50.968638 rch64) (Linux: 6.1.31 aarch64)
11994 12:12:50.972195 Opened device: /dev/dri/card0
11995 12:12:50.978602 Starting subtest:<8>[ 24.528591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11996 12:12:50.978889 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11998 12:12:50.982051 blob-prop-core
11999 12:12:50.984987 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12000 12:12:51.001971 <14>[ 24.553957] [IGT] kms_prop_blob: executing
12001 12:12:51.008760 IGT-Version: 1.2<14>[ 24.559084] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12002 12:12:51.015359 7.1-g766edf9 (aa<14>[ 24.567004] [IGT] kms_prop_blob: exiting, ret=0
12003 12:12:51.018646 rch64) (Linux: 6.1.31 aarch64)
12004 12:12:51.021982 Opened device: /dev/dri/card0
12005 12:12:51.032079 Starting subtest:<8>[ 24.579491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12006 12:12:51.032189 blob-prop-validate
12007 12:12:51.032457 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12009 12:12:51.038228 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12010 12:12:51.052720 <14>[ 24.604914] [IGT] kms_prop_blob: executing
12011 12:12:51.059314 IGT-Version: 1.2<14>[ 24.609835] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12012 12:12:51.066320 7.1-g766edf9 (aa<14>[ 24.617906] [IGT] kms_prop_blob: exiting, ret=0
12013 12:12:51.069425 rch64) (Linux: 6.1.31 aarch64)
12014 12:12:51.073024 Opened device: /dev/dri/card0
12015 12:12:51.082815 Starting subtest:<8>[ 24.630149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12016 12:12:51.082897 blob-prop-lifetime
12017 12:12:51.083139 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12019 12:12:51.088758 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12020 12:12:51.103671 <14>[ 24.655465] [IGT] kms_prop_blob: executing
12021 12:12:51.110204 IGT-Version: 1.2<14>[ 24.660410] [IGT] kms_prop_blob: starting subtest blob-multiple
12022 12:12:51.116708 7.1-g766edf9 (aa<14>[ 24.668131] [IGT] kms_prop_blob: exiting, ret=0
12023 12:12:51.120033 rch64) (Linux: 6.1.31 aarch64)
12024 12:12:51.123527 Opened device: /dev/dri/card0
12025 12:12:51.130073 Starting subtest:<8>[ 24.680402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12026 12:12:51.130352 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12028 12:12:51.133231 blob-multiple
12029 12:12:51.136350 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12030 12:12:51.153897 <14>[ 24.705497] [IGT] kms_prop_blob: executing
12031 12:12:51.160468 IGT-Version: 1.2<14>[ 24.710466] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12032 12:12:51.167102 7.1-g766edf9 (aa<14>[ 24.718603] [IGT] kms_prop_blob: exiting, ret=0
12033 12:12:51.169931 rch64) (Linux: 6.1.31 aarch64)
12034 12:12:51.173525 Opened device: /dev/dri/card0
12035 12:12:51.183411 Starting subtest:<8>[ 24.730711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12036 12:12:51.183537 invalid-get-prop-any
12037 12:12:51.183844 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12039 12:12:51.190156 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12040 12:12:51.204423 <14>[ 24.756369] [IGT] kms_prop_blob: executing
12041 12:12:51.211370 IGT-Version: 1.2<14>[ 24.761377] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12042 12:12:51.217798 7.1-g766edf9 (aa<14>[ 24.769260] [IGT] kms_prop_blob: exiting, ret=0
12043 12:12:51.221341 rch64) (Linux: 6.1.31 aarch64)
12044 12:12:51.224268 Opened device: /dev/dri/card0
12045 12:12:51.231033 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12047 12:12:51.234664 Starting subtest:<8>[ 24.781080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12048 12:12:51.234763 invalid-get-prop
12049 12:12:51.237773 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12050 12:12:51.254711 <14>[ 24.806753] [IGT] kms_prop_blob: executing
12051 12:12:51.261281 IGT-Version: 1.2<14>[ 24.811677] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12052 12:12:51.267921 7.1-g766edf9 (aa<14>[ 24.819953] [IGT] kms_prop_blob: exiting, ret=0
12053 12:12:51.271438 rch64) (Linux: 6.1.31 aarch64)
12054 12:12:51.274948 Opened device: /dev/dri/card0
12055 12:12:51.284190 Starting subtest:<8>[ 24.832099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12056 12:12:51.284295 invalid-set-prop-any
12057 12:12:51.284568 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12059 12:12:51.290715 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12060 12:12:51.307294 <14>[ 24.859016] [IGT] kms_prop_blob: executing
12061 12:12:51.313817 IGT-Version: 1.2<14>[ 24.864046] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12062 12:12:51.320304 7.1-g766edf9 (aa<14>[ 24.871842] [IGT] kms_prop_blob: exiting, ret=0
12063 12:12:51.323855 rch64) (Linux: 6.1.31 aarch64)
12064 12:12:51.326762 Opened device: /dev/dri/card0
12065 12:12:51.336561 Starting subtest:<8>[ 24.884289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12066 12:12:51.336648 invalid-set-prop
12067 12:12:51.336890 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12069 12:12:51.343426 [1mSubtest i<8>[ 24.893955] <LAVA_SIGNAL_TESTSET STOP>
12070 12:12:51.343682 Received signal: <TESTSET> STOP
12071 12:12:51.343753 Closing test_set kms_prop_blob
12072 12:12:51.346734 nvalid-set-prop: SUCCESS (0.000s)[0m
12073 12:12:51.367836 <8>[ 24.919579] <LAVA_SIGNAL_TESTSET START kms_setmode>
12074 12:12:51.368094 Received signal: <TESTSET> START kms_setmode
12075 12:12:51.368168 Starting test_set kms_setmode
12076 12:12:51.389968 <14>[ 24.941940] [IGT] kms_setmode: executing
12077 12:12:51.396908 IGT-Version: 1.2<14>[ 24.946794] [IGT] kms_setmode: starting subtest basic
12078 12:12:51.403278 7.1-g766edf9 (aa<14>[ 24.953282] [IGT] kms_setmode: exiting, ret=77
12079 12:12:51.406522 rch64) (Linux: 6.1.31 aarch64)
12080 12:12:51.406607 Opened device: /dev/dri/card0
12081 12:12:51.416404 Starting subtest:<8>[ 24.965157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12082 12:12:51.416488 basic
12083 12:12:51.416726 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12085 12:12:51.419398 No dynamic tests executed.
12086 12:12:51.422959 [1mSubtest basic: SKIP (0.000s)[0m
12087 12:12:51.438320 <14>[ 24.989898] [IGT] kms_setmode: executing
12088 12:12:51.444601 IGT-Version: 1.2<14>[ 24.994713] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12089 12:12:51.451311 7.1-g766edf9 (aa<14>[ 25.002830] [IGT] kms_setmode: exiting, ret=77
12090 12:12:51.454499 rch64) (Linux: 6.1.31 aarch64)
12091 12:12:51.457719 Opened device: /dev/dri/card0
12092 12:12:51.467731 Starting subtest:<8>[ 25.015287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12093 12:12:51.467816 basic-clone-single-crtc
12094 12:12:51.468053 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12096 12:12:51.471253 No dynamic tests executed.
12097 12:12:51.477334 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12098 12:12:51.489293 <14>[ 25.041291] [IGT] kms_setmode: executing
12099 12:12:51.495969 IGT-Version: 1.2<14>[ 25.046090] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12100 12:12:51.502642 7.1-g766edf9 (aa<14>[ 25.054483] [IGT] kms_setmode: exiting, ret=77
12101 12:12:51.506203 rch64) (Linux: 6.1.31 aarch64)
12102 12:12:51.509127 Opened device: /dev/dri/card0
12103 12:12:51.519067 Starting subtest:<8>[ 25.066733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12104 12:12:51.519324 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12106 12:12:51.522481 invalid-clone-single-crtc
12107 12:12:51.522563 No dynamic tests executed.
12108 12:12:51.529233 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12109 12:12:51.540907 <14>[ 25.092775] [IGT] kms_setmode: executing
12110 12:12:51.550708 IGT-Version: 1.2<14>[ 25.097616] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12111 12:12:51.554076 7.1-g766edf9 (aa<14>[ 25.106257] [IGT] kms_setmode: exiting, ret=77
12112 12:12:51.557314 rch64) (Linux: 6.1.31 aarch64)
12113 12:12:51.560880 Opened device: /dev/dri/card0
12114 12:12:51.570632 Starting subtest:<8>[ 25.118384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12115 12:12:51.570891 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12117 12:12:51.574051 invalid-clone-exclusive-crtc
12118 12:12:51.577056 No dynamic tests executed.
12119 12:12:51.580629 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12120 12:12:51.593127 <14>[ 25.145085] [IGT] kms_setmode: executing
12121 12:12:51.599895 IGT-Version: 1.2<14>[ 25.149810] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12122 12:12:51.606479 7.1-g766edf9 (aa<14>[ 25.157733] [IGT] kms_setmode: exiting, ret=77
12123 12:12:51.610003 rch64) (Linux: 6.1.31 aarch64)
12124 12:12:51.612967 Opened device: /dev/dri/card0
12125 12:12:51.623692 Starting subtest:<8>[ 25.169929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12126 12:12:51.623806 clone-exclusive-crtc
12127 12:12:51.624078 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12129 12:12:51.626096 No dynamic tests executed.
12130 12:12:51.629200 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12131 12:12:51.644172 <14>[ 25.195724] [IGT] kms_setmode: executing
12132 12:12:51.653632 IGT-Version: 1.2<14>[ 25.200454] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12133 12:12:51.660501 7.1-g766edf9 (aa<14>[ 25.209713] [IGT] kms_setmode: exiting, ret=77
12134 12:12:51.660607 rch64) (Linux: 6.1.31 aarch64)
12135 12:12:51.663718 Opened device: /dev/dri/card0
12136 12:12:51.673606 Starting subtest:<8>[ 25.221762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12137 12:12:51.673902 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12139 12:12:51.679992 invalid-clone-single-crtc-steal<8>[ 25.233116] <LAVA_SIGNAL_TESTSET STOP>
12140 12:12:51.680246 Received signal: <TESTSET> STOP
12141 12:12:51.680371 Closing test_set kms_setmode
12142 12:12:51.683506 ing
12143 12:12:51.683590 No dynamic tests executed.
12144 12:12:51.690042 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12145 12:12:51.707359 <8>[ 25.259151] <LAVA_SIGNAL_TESTSET START kms_vblank>
12146 12:12:51.707618 Received signal: <TESTSET> START kms_vblank
12147 12:12:51.707690 Starting test_set kms_vblank
12148 12:12:51.729689 <14>[ 25.281503] [IGT] kms_vblank: executing
12149 12:12:51.736279 IGT-Version: 1.2<14>[ 25.286482] [IGT] kms_vblank: exiting, ret=77
12150 12:12:51.739744 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12151 12:12:51.742776 Opened device: /dev/dri/card0
12152 12:12:51.749385 N<8>[ 25.298226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12153 12:12:51.749706 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12155 12:12:51.752719 o KMS driver or no outputs, pipes: 8, outputs: 0
12156 12:12:51.755776 [1mSubtest invalid: SKIP (0.000s)[0m
12157 12:12:51.770608 <14>[ 25.322504] [IGT] kms_vblank: executing
12158 12:12:51.777278 IGT-Version: 1.2<14>[ 25.327562] [IGT] kms_vblank: exiting, ret=77
12159 12:12:51.780646 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12160 12:12:51.784034 Opened device: /dev/dri/card0
12161 12:12:51.790360 N<8>[ 25.339383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12162 12:12:51.790619 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12164 12:12:51.793833 o KMS driver or no outputs, pipes: 8, outputs: 0
12165 12:12:51.796728 [1mSubtest crtc-id: SKIP (0.000s)[0m
12166 12:12:51.811600 <14>[ 25.363672] [IGT] kms_vblank: executing
12167 12:12:51.818680 IGT-Version: 1.2<14>[ 25.368770] [IGT] kms_vblank: exiting, ret=77
12168 12:12:51.821633 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12169 12:12:51.825009 Opened device: /dev/dri/card0
12170 12:12:51.831575 N<8>[ 25.380378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12171 12:12:51.831839 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12173 12:12:51.834952 o KMS driver or no outputs, pipes: 8, outputs: 0
12174 12:12:51.841487 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12175 12:12:51.854405 <14>[ 25.406224] [IGT] kms_vblank: executing
12176 12:12:51.860849 IGT-Version: 1.2<14>[ 25.411327] [IGT] kms_vblank: exiting, ret=77
12177 12:12:51.864356 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12178 12:12:51.867409 Opened device: /dev/dri/card0
12179 12:12:51.874176 N<8>[ 25.422870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12180 12:12:51.874437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12182 12:12:51.877770 o KMS driver or no outputs, pipes: 8, outputs: 0
12183 12:12:51.883856 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12184 12:12:51.896116 <14>[ 25.448128] [IGT] kms_vblank: executing
12185 12:12:51.902748 IGT-Version: 1.2<14>[ 25.453224] [IGT] kms_vblank: exiting, ret=77
12186 12:12:51.905769 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12187 12:12:51.909214 Opened device: /dev/dri/card0
12188 12:12:51.916095 N<8>[ 25.464826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12189 12:12:51.916382 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12191 12:12:51.922566 o KMS driver or no outputs, pipes: 8, outputs: 0
12192 12:12:51.925594 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12193 12:12:51.938831 <14>[ 25.490768] [IGT] kms_vblank: executing
12194 12:12:51.945351 IGT-Version: 1.2<14>[ 25.495761] [IGT] kms_vblank: exiting, ret=77
12195 12:12:51.948374 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12196 12:12:51.952008 Opened device: /dev/dri/card0
12197 12:12:51.958631 N<8>[ 25.507444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12198 12:12:51.958939 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12200 12:12:51.961654 o KMS driver or no outputs, pipes: 8, outputs: 0
12201 12:12:51.968525 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12202 12:12:51.981024 <14>[ 25.532855] [IGT] kms_vblank: executing
12203 12:12:51.987709 IGT-Version: 1.2<14>[ 25.537963] [IGT] kms_vblank: exiting, ret=77
12204 12:12:51.990964 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12205 12:12:51.994178 Opened device: /dev/dri/card0
12206 12:12:52.000515 N<8>[ 25.549676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12207 12:12:52.000807 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12209 12:12:52.007201 o KMS driver or no outputs, pipes: 8, outputs: 0
12210 12:12:52.010290 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12211 12:12:52.023469 <14>[ 25.575580] [IGT] kms_vblank: executing
12212 12:12:52.030065 IGT-Version: 1.2<14>[ 25.580584] [IGT] kms_vblank: exiting, ret=77
12213 12:12:52.033601 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12214 12:12:52.036986 Opened device: /dev/dri/card0
12215 12:12:52.043579 N<8>[ 25.592384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12216 12:12:52.043845 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12218 12:12:52.046529 o KMS driver or no outputs, pipes: 8, outputs: 0
12219 12:12:52.053105 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12220 12:12:52.065861 <14>[ 25.617685] [IGT] kms_vblank: executing
12221 12:12:52.072544 IGT-Version: 1.2<14>[ 25.622903] [IGT] kms_vblank: exiting, ret=77
12222 12:12:52.075392 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12223 12:12:52.078954 Opened device: /dev/dri/card0
12224 12:12:52.085475 N<8>[ 25.634360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12225 12:12:52.085734 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12227 12:12:52.092116 o KMS driver or no outputs, pipes: 8, outputs: 0
12228 12:12:52.095375 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12229 12:12:52.108474 <14>[ 25.660381] [IGT] kms_vblank: executing
12230 12:12:52.114988 IGT-Version: 1.2<14>[ 25.665396] [IGT] kms_vblank: exiting, ret=77
12231 12:12:52.118199 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12232 12:12:52.121753 Opened device: /dev/dri/card0
12233 12:12:52.128280 N<8>[ 25.677261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12234 12:12:52.128537 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12236 12:12:52.134750 o KMS driver or no outputs, pipes: 8, outputs: 0
12237 12:12:52.138059 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12238 12:12:52.152128 <14>[ 25.704210] [IGT] kms_vblank: executing
12239 12:12:52.158817 IGT-Version: 1.2<14>[ 25.709197] [IGT] kms_vblank: exiting, ret=77
12240 12:12:52.162205 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12241 12:12:52.165537 Opened device: /dev/dri/card0
12242 12:12:52.172149 N<8>[ 25.720687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12243 12:12:52.172407 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12245 12:12:52.178686 o KMS driver or no outputs, pipes: 8, outputs: 0
12246 12:12:52.181772 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12247 12:12:52.196489 <14>[ 25.748488] [IGT] kms_vblank: executing
12248 12:12:52.203187 IGT-Version: 1.2<14>[ 25.753530] [IGT] kms_vblank: exiting, ret=77
12249 12:12:52.206523 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12250 12:12:52.209851 Opened device: /dev/dri/card0
12251 12:12:52.216396 N<8>[ 25.765555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12252 12:12:52.216680 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12254 12:12:52.219508 o KMS driver or no outputs, pipes: 8, outputs: 0
12255 12:12:52.225953 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12256 12:12:52.238289 <14>[ 25.790251] [IGT] kms_vblank: executing
12257 12:12:52.244612 IGT-Version: 1.2<14>[ 25.795503] [IGT] kms_vblank: exiting, ret=77
12258 12:12:52.248143 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12259 12:12:52.251592 Opened device: /dev/dri/card0
12260 12:12:52.257785 N<8>[ 25.806454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12261 12:12:52.258075 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12263 12:12:52.261479 o KMS driver or no outputs, pipes: 8, outputs: 0
12264 12:12:52.267913 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12265 12:12:52.280506 <14>[ 25.832414] [IGT] kms_vblank: executing
12266 12:12:52.286954 IGT-Version: 1.2<14>[ 25.837474] [IGT] kms_vblank: exiting, ret=77
12267 12:12:52.290405 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12268 12:12:52.293371 Opened device: /dev/dri/card0
12269 12:12:52.300196 N<8>[ 25.849493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12270 12:12:52.300482 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12272 12:12:52.303296 o KMS driver or no outputs, pipes: 8, outputs: 0
12273 12:12:52.309831 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12274 12:12:52.322651 <14>[ 25.874771] [IGT] kms_vblank: executing
12275 12:12:52.329662 IGT-Version: 1.2<14>[ 25.879841] [IGT] kms_vblank: exiting, ret=77
12276 12:12:52.332880 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12277 12:12:52.335842 Opened device: /dev/dri/card0
12278 12:12:52.342966 N<8>[ 25.891657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12279 12:12:52.343225 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12281 12:12:52.345791 o KMS driver or no outputs, pipes: 8, outputs: 0
12282 12:12:52.352759 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12283 12:12:52.365272 <14>[ 25.917438] [IGT] kms_vblank: executing
12284 12:12:52.372116 IGT-Version: 1.2<14>[ 25.922424] [IGT] kms_vblank: exiting, ret=77
12285 12:12:52.375509 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12286 12:12:52.378971 Opened device: /dev/dri/card0
12287 12:12:52.385482 N<8>[ 25.934360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12288 12:12:52.385737 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12290 12:12:52.389107 o KMS driver or no outputs, pipes: 8, outputs: 0
12291 12:12:52.395138 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12292 12:12:52.407469 <14>[ 25.959385] [IGT] kms_vblank: executing
12293 12:12:52.414052 IGT-Version: 1.2<14>[ 25.964447] [IGT] kms_vblank: exiting, ret=77
12294 12:12:52.417488 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12295 12:12:52.420354 Opened device: /dev/dri/card0
12296 12:12:52.427172 N<8>[ 25.976249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12297 12:12:52.427428 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12299 12:12:52.430809 o KMS driver or no outputs, pipes: 8, outputs: 0
12300 12:12:52.436782 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12301 12:12:52.451115 <14>[ 26.002944] [IGT] kms_vblank: executing
12302 12:12:52.457716 IGT-Version: 1.2<14>[ 26.007982] [IGT] kms_vblank: exiting, ret=77
12303 12:12:52.460660 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12304 12:12:52.464262 Opened device: /dev/dri/card0
12305 12:12:52.470746 N<8>[ 26.019480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12306 12:12:52.471073 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12308 12:12:52.474188 o KMS driver or no outputs, pipes: 8, outputs: 0
12309 12:12:52.480440 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12310 12:12:52.493465 <14>[ 26.045356] [IGT] kms_vblank: executing
12311 12:12:52.500061 IGT-Version: 1.2<14>[ 26.050353] [IGT] kms_vblank: exiting, ret=77
12312 12:12:52.503097 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12313 12:12:52.506377 Opened device: /dev/dri/card0
12314 12:12:52.513274 N<8>[ 26.061429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12315 12:12:52.513561 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12317 12:12:52.519737 o KMS driver or no outputs, pipes: 8, outputs: 0
12318 12:12:52.522993 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12319 12:12:52.536687 <14>[ 26.088472] [IGT] kms_vblank: executing
12320 12:12:52.542798 IGT-Version: 1.2<14>[ 26.093566] [IGT] kms_vblank: exiting, ret=77
12321 12:12:52.546260 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12322 12:12:52.549603 Opened device: /dev/dri/card0
12323 12:12:52.556091 N<8>[ 26.104806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12324 12:12:52.556348 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12326 12:12:52.563569 o KMS driver or no outputs, pipes: 8, outputs: 0
12327 12:12:52.566230 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12328 12:12:52.579686 <14>[ 26.131433] [IGT] kms_vblank: executing
12329 12:12:52.586073 IGT-Version: 1.2<14>[ 26.136513] [IGT] kms_vblank: exiting, ret=77
12330 12:12:52.589599 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12331 12:12:52.592633 Opened device: /dev/dri/card0
12332 12:12:52.599249 N<8>[ 26.147613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12333 12:12:52.599536 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12335 12:12:52.605787 o KMS driver or no outputs, pipes: 8, outputs: 0
12336 12:12:52.609174 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12337 12:12:52.622967 <14>[ 26.174871] [IGT] kms_vblank: executing
12338 12:12:52.629653 IGT-Version: 1.2<14>[ 26.179882] [IGT] kms_vblank: exiting, ret=77
12339 12:12:52.633087 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12340 12:12:52.636059 Opened device: /dev/dri/card0
12341 12:12:52.643041 N<8>[ 26.191131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12342 12:12:52.643355 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12344 12:12:52.649505 o KMS driver or no outputs, pipes: 8, outputs: 0
12345 12:12:52.652658 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12346 12:12:52.667324 <14>[ 26.219283] [IGT] kms_vblank: executing
12347 12:12:52.673808 IGT-Version: 1.2<14>[ 26.224272] [IGT] kms_vblank: exiting, ret=77
12348 12:12:52.677238 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12349 12:12:52.680317 Opened device: /dev/dri/card0
12350 12:12:52.686800 N<8>[ 26.235786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12351 12:12:52.687084 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12353 12:12:52.693618 o KMS driver or no outputs, pipes: 8, outputs: 0
12354 12:12:52.700173 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12355 12:12:52.710747 <14>[ 26.262546] [IGT] kms_vblank: executing
12356 12:12:52.717054 IGT-Version: 1.2<14>[ 26.267564] [IGT] kms_vblank: exiting, ret=77
12357 12:12:52.720598 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12358 12:12:52.723743 Opened device: /dev/dri/card0
12359 12:12:52.730513 N<8>[ 26.278714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12360 12:12:52.730818 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12362 12:12:52.737085 o KMS driver or no outputs, pipes: 8, outputs: 0
12363 12:12:52.740156 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12364 12:12:52.754173 <14>[ 26.305789] [IGT] kms_vblank: executing
12365 12:12:52.760640 IGT-Version: 1.2<14>[ 26.310900] [IGT] kms_vblank: exiting, ret=77
12366 12:12:52.763765 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12367 12:12:52.766939 Opened device: /dev/dri/card0
12368 12:12:52.773238 N<8>[ 26.321900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12369 12:12:52.773500 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12371 12:12:52.779812 o KMS driver or no outputs, pipes: 8, outputs: 0
12372 12:12:52.783355 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12373 12:12:52.796595 <14>[ 26.348813] [IGT] kms_vblank: executing
12374 12:12:52.803383 IGT-Version: 1.2<14>[ 26.353818] [IGT] kms_vblank: exiting, ret=77
12375 12:12:52.806402 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12376 12:12:52.809959 Opened device: /dev/dri/card0
12377 12:12:52.816393 N<8>[ 26.365002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12378 12:12:52.816665 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12380 12:12:52.823226 o KMS driver or no outputs, pipes: 8, outputs: 0
12381 12:12:52.829795 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12382 12:12:52.840254 <14>[ 26.392502] [IGT] kms_vblank: executing
12383 12:12:52.846991 IGT-Version: 1.2<14>[ 26.397512] [IGT] kms_vblank: exiting, ret=77
12384 12:12:52.850436 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12385 12:12:52.853400 Opened device: /dev/dri/card0
12386 12:12:52.860204 N<8>[ 26.408716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12387 12:12:52.860510 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12389 12:12:52.866839 o KMS driver or no outputs, pipes: 8, outputs: 0
12390 12:12:52.873096 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12391 12:12:52.883719 <14>[ 26.435963] [IGT] kms_vblank: executing
12392 12:12:52.890622 IGT-Version: 1.2<14>[ 26.441113] [IGT] kms_vblank: exiting, ret=77
12393 12:12:52.893642 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12394 12:12:52.897094 Opened device: /dev/dri/card0
12395 12:12:52.903515 N<8>[ 26.452243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12396 12:12:52.903783 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12398 12:12:52.907143 o KMS driver or no outputs, pipes: 8, outputs: 0
12399 12:12:52.913638 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12400 12:12:52.925903 <14>[ 26.478115] [IGT] kms_vblank: executing
12401 12:12:52.933072 IGT-Version: 1.2<14>[ 26.483390] [IGT] kms_vblank: exiting, ret=77
12402 12:12:52.935922 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12403 12:12:52.939280 Opened device: /dev/dri/card0
12404 12:12:52.945988 N<8>[ 26.494375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12405 12:12:52.946293 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12407 12:12:52.949144 o KMS driver or no outputs, pipes: 8, outputs: 0
12408 12:12:52.955612 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12409 12:12:52.967965 <14>[ 26.520116] [IGT] kms_vblank: executing
12410 12:12:52.974694 IGT-Version: 1.2<14>[ 26.525162] [IGT] kms_vblank: exiting, ret=77
12411 12:12:52.977878 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12412 12:12:52.981115 Opened device: /dev/dri/card0
12413 12:12:52.987872 N<8>[ 26.536377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12414 12:12:52.988135 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12416 12:12:52.990970 o KMS driver or no outputs, pipes: 8, outputs: 0
12417 12:12:52.997495 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12418 12:12:53.010292 <14>[ 26.562441] [IGT] kms_vblank: executing
12419 12:12:53.016682 IGT-Version: 1.2<14>[ 26.567485] [IGT] kms_vblank: exiting, ret=77
12420 12:12:53.020194 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12421 12:12:53.023738 Opened device: /dev/dri/card0
12422 12:12:53.029955 N<8>[ 26.578851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12423 12:12:53.030268 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12425 12:12:53.033456 o KMS driver or no outputs, pipes: 8, outputs: 0
12426 12:12:53.039807 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12427 12:12:53.052591 <14>[ 26.604809] [IGT] kms_vblank: executing
12428 12:12:53.059565 IGT-Version: 1.2<14>[ 26.609811] [IGT] kms_vblank: exiting, ret=77
12429 12:12:53.062506 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12430 12:12:53.065959 Opened device: /dev/dri/card0
12431 12:12:53.072389 N<8>[ 26.621371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12432 12:12:53.072701 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12434 12:12:53.079213 o KMS driver or no outputs, pipes: 8, outputs: 0
12435 12:12:53.082190 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12436 12:12:53.095553 <14>[ 26.647616] [IGT] kms_vblank: executing
12437 12:12:53.102126 IGT-Version: 1.2<14>[ 26.652599] [IGT] kms_vblank: exiting, ret=77
12438 12:12:53.105430 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12439 12:12:53.109066 Opened device: /dev/dri/card0
12440 12:12:53.115539 N<8>[ 26.664344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12441 12:12:53.115862 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12443 12:12:53.118585 o KMS driver or no outputs, pipes: 8, outputs: 0
12444 12:12:53.125089 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12445 12:12:53.138547 <14>[ 26.690774] [IGT] kms_vblank: executing
12446 12:12:53.145556 IGT-Version: 1.2<14>[ 26.695754] [IGT] kms_vblank: exiting, ret=77
12447 12:12:53.148400 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12448 12:12:53.151869 Opened device: /dev/dri/card0
12449 12:12:53.158661 N<8>[ 26.707989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12450 12:12:53.158945 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12452 12:12:53.161600 o KMS driver or no outputs, pipes: 8, outputs: 0
12453 12:12:53.168518 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12454 12:12:53.181425 <14>[ 26.733203] [IGT] kms_vblank: executing
12455 12:12:53.187544 IGT-Version: 1.2<14>[ 26.738325] [IGT] kms_vblank: exiting, ret=77
12456 12:12:53.191193 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12457 12:12:53.194108 Opened device: /dev/dri/card0
12458 12:12:53.201111 N<8>[ 26.749718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12459 12:12:53.201427 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12461 12:12:53.207498 o KMS driver or no outputs, pipes: 8, outputs: 0
12462 12:12:53.210836 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12463 12:12:53.224029 <14>[ 26.775954] [IGT] kms_vblank: executing
12464 12:12:53.230564 IGT-Version: 1.2<14>[ 26.780965] [IGT] kms_vblank: exiting, ret=77
12465 12:12:53.234010 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12466 12:12:53.237291 Opened device: /dev/dri/card0
12467 12:12:53.243721 N<8>[ 26.792349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12468 12:12:53.244038 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12470 12:12:53.250165 o KMS driver or no outputs, pipes: 8, outputs: 0
12471 12:12:53.253452 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12472 12:12:53.267075 <14>[ 26.818941] [IGT] kms_vblank: executing
12473 12:12:53.273459 IGT-Version: 1.2<14>[ 26.823944] [IGT] kms_vblank: exiting, ret=77
12474 12:12:53.277054 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12475 12:12:53.280020 Opened device: /dev/dri/card0
12476 12:12:53.286805 N<8>[ 26.835337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12477 12:12:53.287116 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12479 12:12:53.289825 o KMS driver or no outputs, pipes: 8, outputs: 0
12480 12:12:53.296496 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12481 12:12:53.308482 <14>[ 26.860729] [IGT] kms_vblank: executing
12482 12:12:53.315372 IGT-Version: 1.2<14>[ 26.865758] [IGT] kms_vblank: exiting, ret=77
12483 12:12:53.318494 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12484 12:12:53.322122 Opened device: /dev/dri/card0
12485 12:12:53.328518 N<8>[ 26.877130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12486 12:12:53.328828 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12488 12:12:53.332166 o KMS driver or no outputs, pipes: 8, outputs: 0
12489 12:12:53.338532 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12490 12:12:53.351242 <14>[ 26.903146] [IGT] kms_vblank: executing
12491 12:12:53.357563 IGT-Version: 1.2<14>[ 26.908148] [IGT] kms_vblank: exiting, ret=77
12492 12:12:53.361186 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12493 12:12:53.364227 Opened device: /dev/dri/card0
12494 12:12:53.370672 N<8>[ 26.919529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12495 12:12:53.370985 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12497 12:12:53.374173 o KMS driver or no outputs, pipes: 8, outputs: 0
12498 12:12:53.380477 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12499 12:12:53.392858 <14>[ 26.944991] [IGT] kms_vblank: executing
12500 12:12:53.399810 IGT-Version: 1.2<14>[ 26.949998] [IGT] kms_vblank: exiting, ret=77
12501 12:12:53.402687 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12502 12:12:53.406336 Opened device: /dev/dri/card0
12503 12:12:53.412657 N<8>[ 26.961362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12504 12:12:53.413000 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12506 12:12:53.416261 o KMS driver or no outputs, pipes: 8, outputs: 0
12507 12:12:53.422718 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12508 12:12:53.435267 <14>[ 26.987523] [IGT] kms_vblank: executing
12509 12:12:53.442297 IGT-Version: 1.2<14>[ 26.992536] [IGT] kms_vblank: exiting, ret=77
12510 12:12:53.445369 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12511 12:12:53.448390 Opened device: /dev/dri/card0
12512 12:12:53.454913 N<8>[ 27.004016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12513 12:12:53.455234 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12515 12:12:53.458477 o KMS driver or no outputs, pipes: 8, outputs: 0
12516 12:12:53.464681 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12517 12:12:53.477321 <14>[ 27.029244] [IGT] kms_vblank: executing
12518 12:12:53.483449 IGT-Version: 1.2<14>[ 27.034224] [IGT] kms_vblank: exiting, ret=77
12519 12:12:53.486958 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12520 12:12:53.490122 Opened device: /dev/dri/card0
12521 12:12:53.497191 N<8>[ 27.045572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12522 12:12:53.497519 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12524 12:12:53.500256 o KMS driver or no outputs, pipes: 8, outputs: 0
12525 12:12:53.506668 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12526 12:12:53.519559 <14>[ 27.071480] [IGT] kms_vblank: executing
12527 12:12:53.525992 IGT-Version: 1.2<14>[ 27.076562] [IGT] kms_vblank: exiting, ret=77
12528 12:12:53.529472 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12529 12:12:53.532440 Opened device: /dev/dri/card0
12530 12:12:53.539427 N<8>[ 27.088013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12531 12:12:53.539741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12533 12:12:53.542447 o KMS driver or no outputs, pipes: 8, outputs: 0
12534 12:12:53.549156 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12535 12:12:53.562029 <14>[ 27.113898] [IGT] kms_vblank: executing
12536 12:12:53.568515 IGT-Version: 1.2<14>[ 27.118951] [IGT] kms_vblank: exiting, ret=77
12537 12:12:53.571486 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12538 12:12:53.575041 Opened device: /dev/dri/card0
12539 12:12:53.581472 N<8>[ 27.130202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12540 12:12:53.581798 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12542 12:12:53.588368 o KMS driver or no outputs, pipes: 8, outputs: 0
12543 12:12:53.591478 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12544 12:12:53.604779 <14>[ 27.156784] [IGT] kms_vblank: executing
12545 12:12:53.611309 IGT-Version: 1.2<14>[ 27.161763] [IGT] kms_vblank: exiting, ret=77
12546 12:12:53.614759 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12547 12:12:53.618139 Opened device: /dev/dri/card0
12548 12:12:53.624895 N<8>[ 27.173040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12549 12:12:53.625178 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12551 12:12:53.631179 o KMS driver or no outputs, pipes: 8, outputs: 0
12552 12:12:53.634584 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12553 12:12:53.647276 <14>[ 27.199457] [IGT] kms_vblank: executing
12554 12:12:53.654194 IGT-Version: 1.2<14>[ 27.204565] [IGT] kms_vblank: exiting, ret=77
12555 12:12:53.657138 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12556 12:12:53.660557 Opened device: /dev/dri/card0
12557 12:12:53.666953 N<8>[ 27.215895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12558 12:12:53.667267 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12560 12:12:53.673848 o KMS driver or no outputs, pipes: 8, outputs: 0
12561 12:12:53.676761 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12562 12:12:53.690546 <14>[ 27.242542] [IGT] kms_vblank: executing
12563 12:12:53.697104 IGT-Version: 1.2<14>[ 27.247556] [IGT] kms_vblank: exiting, ret=77
12564 12:12:53.700487 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12565 12:12:53.703798 Opened device: /dev/dri/card0
12566 12:12:53.710194 N<8>[ 27.258914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12567 12:12:53.710594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12569 12:12:53.716675 o KMS driver or no outputs, pipes: 8, outputs: 0
12570 12:12:53.720115 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12571 12:12:53.733416 <14>[ 27.285486] [IGT] kms_vblank: executing
12572 12:12:53.739851 IGT-Version: 1.2<14>[ 27.290559] [IGT] kms_vblank: exiting, ret=77
12573 12:12:53.743269 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12574 12:12:53.746710 Opened device: /dev/dri/card0
12575 12:12:53.753285 N<8>[ 27.301823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12576 12:12:53.753641 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12578 12:12:53.759471 o KMS driver or no outputs, pipes: 8, outputs: 0
12579 12:12:53.766062 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12580 12:12:53.777139 <14>[ 27.328940] [IGT] kms_vblank: executing
12581 12:12:53.783598 IGT-Version: 1.2<14>[ 27.333927] [IGT] kms_vblank: exiting, ret=77
12582 12:12:53.786758 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12583 12:12:53.789824 Opened device: /dev/dri/card0
12584 12:12:53.796548 N<8>[ 27.345351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12585 12:12:53.796865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12587 12:12:53.803118 o KMS driver or no outputs, pipes: 8, outputs: 0
12588 12:12:53.806097 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12589 12:12:53.819958 <14>[ 27.371977] [IGT] kms_vblank: executing
12590 12:12:53.826528 IGT-Version: 1.2<14>[ 27.376985] [IGT] kms_vblank: exiting, ret=77
12591 12:12:53.829814 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12592 12:12:53.833130 Opened device: /dev/dri/card0
12593 12:12:53.839606 N<8>[ 27.388431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12594 12:12:53.839924 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12596 12:12:53.846498 o KMS driver or no outputs, pipes: 8, outputs: 0
12597 12:12:53.849545 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12598 12:12:53.862869 <14>[ 27.415223] [IGT] kms_vblank: executing
12599 12:12:53.869967 IGT-Version: 1.2<14>[ 27.420250] [IGT] kms_vblank: exiting, ret=77
12600 12:12:53.873010 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12601 12:12:53.876435 Opened device: /dev/dri/card0
12602 12:12:53.882841 N<8>[ 27.431693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12603 12:12:53.883132 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12605 12:12:53.889399 o KMS driver or no outputs, pipes: 8, outputs: 0
12606 12:12:53.895855 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12607 12:12:53.906820 <14>[ 27.458824] [IGT] kms_vblank: executing
12608 12:12:53.913174 IGT-Version: 1.2<14>[ 27.463882] [IGT] kms_vblank: exiting, ret=77
12609 12:12:53.916548 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12610 12:12:53.920077 Opened device: /dev/dri/card0
12611 12:12:53.926700 N<8>[ 27.475403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12612 12:12:53.927016 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12614 12:12:53.933139 o KMS driver or no outputs, pipes: 8, outputs: 0
12615 12:12:53.939574 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12616 12:12:53.949691 <14>[ 27.502067] [IGT] kms_vblank: executing
12617 12:12:53.956208 IGT-Version: 1.2<14>[ 27.507168] [IGT] kms_vblank: exiting, ret=77
12618 12:12:53.959787 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12619 12:12:53.962801 Opened device: /dev/dri/card0
12620 12:12:53.969579 N<8>[ 27.518413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12621 12:12:53.969911 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12623 12:12:53.973038 o KMS driver or no outputs, pipes: 8, outputs: 0
12624 12:12:53.979631 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12625 12:12:53.991974 <14>[ 27.544252] [IGT] kms_vblank: executing
12626 12:12:53.998577 IGT-Version: 1.2<14>[ 27.549259] [IGT] kms_vblank: exiting, ret=77
12627 12:12:54.001955 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12628 12:12:54.004954 Opened device: /dev/dri/card0
12629 12:12:54.012010 N<8>[ 27.560630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12630 12:12:54.012321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12632 12:12:54.014917 o KMS driver or no outputs, pipes: 8, outputs: 0
12633 12:12:54.021744 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12634 12:12:54.033858 <14>[ 27.586196] [IGT] kms_vblank: executing
12635 12:12:54.040785 IGT-Version: 1.2<14>[ 27.591405] [IGT] kms_vblank: exiting, ret=77
12636 12:12:54.044080 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12637 12:12:54.047349 Opened device: /dev/dri/card0
12638 12:12:54.053826 N<8>[ 27.602537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12639 12:12:54.054121 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12641 12:12:54.057390 o KMS driver or no outputs, pipes: 8, outputs: 0
12642 12:12:54.063804 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12643 12:12:54.076076 <14>[ 27.628417] [IGT] kms_vblank: executing
12644 12:12:54.082930 IGT-Version: 1.2<14>[ 27.633414] [IGT] kms_vblank: exiting, ret=77
12645 12:12:54.085841 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12646 12:12:54.089138 Opened device: /dev/dri/card0
12647 12:12:54.095782 N<8>[ 27.644778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12648 12:12:54.096091 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12650 12:12:54.099355 o KMS driver or no outputs, pipes: 8, outputs: 0
12651 12:12:54.105592 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12652 12:12:54.118220 <14>[ 27.670498] [IGT] kms_vblank: executing
12653 12:12:54.125230 IGT-Version: 1.2<14>[ 27.675496] [IGT] kms_vblank: exiting, ret=77
12654 12:12:54.128192 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12655 12:12:54.131761 Opened device: /dev/dri/card0
12656 12:12:54.138403 N<8>[ 27.686959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12657 12:12:54.138695 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12659 12:12:54.141211 o KMS driver or no outputs, pipes: 8, outputs: 0
12660 12:12:54.147757 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12661 12:12:54.160996 <14>[ 27.712938] [IGT] kms_vblank: executing
12662 12:12:54.167345 IGT-Version: 1.2<14>[ 27.717944] [IGT] kms_vblank: exiting, ret=77
12663 12:12:54.170842 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12664 12:12:54.173864 Opened device: /dev/dri/card0
12665 12:12:54.180597 N<8>[ 27.729202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12666 12:12:54.180919 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12668 12:12:54.183675 o KMS driver or no outputs, pipes: 8, outputs: 0
12669 12:12:54.190669 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12670 12:12:54.202832 <14>[ 27.754883] [IGT] kms_vblank: executing
12671 12:12:54.209024 IGT-Version: 1.2<14>[ 27.759867] [IGT] kms_vblank: exiting, ret=77
12672 12:12:54.212273 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12673 12:12:54.215741 Opened device: /dev/dri/card0
12674 12:12:54.222300 N<8>[ 27.771315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12675 12:12:54.222588 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12677 12:12:54.225773 o KMS driver or no outputs, pipes: 8, outputs: 0
12678 12:12:54.232147 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12679 12:12:54.244740 <14>[ 27.797053] [IGT] kms_vblank: executing
12680 12:12:54.251236 IGT-Version: 1.2<14>[ 27.802057] [IGT] kms_vblank: exiting, ret=77
12681 12:12:54.254755 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12682 12:12:54.258231 Opened device: /dev/dri/card0
12683 12:12:54.264780 N<8>[ 27.813374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12684 12:12:54.265084 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12686 12:12:54.268041 o KMS driver or no outputs, pipes: 8, outputs: 0
12687 12:12:54.274410 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12688 12:12:54.287576 <14>[ 27.839681] [IGT] kms_vblank: executing
12689 12:12:54.294251 IGT-Version: 1.2<14>[ 27.844655] [IGT] kms_vblank: exiting, ret=77
12690 12:12:54.297574 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12691 12:12:54.300578 Opened device: /dev/dri/card0
12692 12:12:54.307198 N<8>[ 27.856113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12693 12:12:54.307513 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12695 12:12:54.314097 o KMS driver or no outputs, pipes: 8, outputs: 0
12696 12:12:54.317288 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12697 12:12:54.330292 <14>[ 27.882451] [IGT] kms_vblank: executing
12698 12:12:54.336695 IGT-Version: 1.2<14>[ 27.887514] [IGT] kms_vblank: exiting, ret=77
12699 12:12:54.340207 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12700 12:12:54.343248 Opened device: /dev/dri/card0
12701 12:12:54.349793 N<8>[ 27.898989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12702 12:12:54.350085 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12704 12:12:54.353218 o KMS driver or no outputs, pipes: 8, outputs: 0
12705 12:12:54.359831 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12706 12:12:54.372200 <14>[ 27.924393] [IGT] kms_vblank: executing
12707 12:12:54.378648 IGT-Version: 1.2<14>[ 27.929452] [IGT] kms_vblank: exiting, ret=77
12708 12:12:54.381929 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12709 12:12:54.385170 Opened device: /dev/dri/card0
12710 12:12:54.391679 N<8>[ 27.940871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12711 12:12:54.392034 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12713 12:12:54.395190 o KMS driver or no outputs, pipes: 8, outputs: 0
12714 12:12:54.401989 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12715 12:12:54.414191 <14>[ 27.966586] [IGT] kms_vblank: executing
12716 12:12:54.420772 IGT-Version: 1.2<14>[ 27.971576] [IGT] kms_vblank: exiting, ret=77
12717 12:12:54.424382 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12718 12:12:54.427371 Opened device: /dev/dri/card0
12719 12:12:54.433843 N<8>[ 27.983080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12720 12:12:54.434178 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12722 12:12:54.437174 o KMS driver or no outputs, pipes: 8, outputs: 0
12723 12:12:54.443656 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12724 12:12:54.456702 <14>[ 28.008676] [IGT] kms_vblank: executing
12725 12:12:54.463024 IGT-Version: 1.2<14>[ 28.013656] [IGT] kms_vblank: exiting, ret=77
12726 12:12:54.466103 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12727 12:12:54.469613 Opened device: /dev/dri/card0
12728 12:12:54.476226 N<8>[ 28.025161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12729 12:12:54.476562 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12731 12:12:54.479801 o KMS driver or no outputs, pipes: 8, outputs: 0
12732 12:12:54.486041 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12733 12:12:54.499012 <14>[ 28.051076] [IGT] kms_vblank: executing
12734 12:12:54.505434 IGT-Version: 1.2<14>[ 28.056067] [IGT] kms_vblank: exiting, ret=77
12735 12:12:54.508882 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12736 12:12:54.511935 Opened device: /dev/dri/card0
12737 12:12:54.518853 N<8>[ 28.067599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12738 12:12:54.519149 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12740 12:12:54.521911 o KMS driver or no outputs, pipes: 8, outputs: 0
12741 12:12:54.528240 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12742 12:12:54.540692 <14>[ 28.093136] [IGT] kms_vblank: executing
12743 12:12:54.547766 IGT-Version: 1.2<14>[ 28.098122] [IGT] kms_vblank: exiting, ret=77
12744 12:12:54.550730 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12745 12:12:54.554200 Opened device: /dev/dri/card0
12746 12:12:54.560750 N<8>[ 28.109400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12747 12:12:54.561039 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12749 12:12:54.563725 o KMS driver or no outputs, pipes: 8, outputs: 0
12750 12:12:54.570303 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12751 12:12:54.582995 <14>[ 28.135542] [IGT] kms_vblank: executing
12752 12:12:54.589805 IGT-Version: 1.2<14>[ 28.140517] [IGT] kms_vblank: exiting, ret=77
12753 12:12:54.593247 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12754 12:12:54.596444 Opened device: /dev/dri/card0
12755 12:12:54.603020 N<8>[ 28.151907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12756 12:12:54.603356 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12758 12:12:54.609331 o KMS driver or no outputs, pipes: 8, outputs: 0
12759 12:12:54.612850 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12760 12:12:54.625809 <14>[ 28.178221] [IGT] kms_vblank: executing
12761 12:12:54.632733 IGT-Version: 1.2<14>[ 28.183435] [IGT] kms_vblank: exiting, ret=77
12762 12:12:54.635725 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12763 12:12:54.639240 Opened device: /dev/dri/card0
12764 12:12:54.645647 N<8>[ 28.194469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12765 12:12:54.645957 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12767 12:12:54.652231 o KMS driver or no outputs, pipes: 8, outputs: 0
12768 12:12:54.655779 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12769 12:12:54.669216 <14>[ 28.221355] [IGT] kms_vblank: executing
12770 12:12:54.675799 IGT-Version: 1.2<14>[ 28.226356] [IGT] kms_vblank: exiting, ret=77
12771 12:12:54.678826 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12772 12:12:54.682029 Opened device: /dev/dri/card0
12773 12:12:54.688544 N<8>[ 28.237834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12774 12:12:54.688842 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12776 12:12:54.695029 o KMS driver or no outputs, pipes: 8, outputs: 0
12777 12:12:54.698262 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12778 12:12:54.712113 <14>[ 28.264234] [IGT] kms_vblank: executing
12779 12:12:54.718626 IGT-Version: 1.2<14>[ 28.269272] [IGT] kms_vblank: exiting, ret=77
12780 12:12:54.721681 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12781 12:12:54.725193 Opened device: /dev/dri/card0
12782 12:12:54.731673 N<8>[ 28.280543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12783 12:12:54.731981 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12785 12:12:54.738151 o KMS driver or no outputs, pipes: 8, outputs: 0
12786 12:12:54.741243 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12787 12:12:54.755536 <14>[ 28.307627] [IGT] kms_vblank: executing
12788 12:12:54.762241 IGT-Version: 1.2<14>[ 28.312623] [IGT] kms_vblank: exiting, ret=77
12789 12:12:54.765299 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12790 12:12:54.768848 Opened device: /dev/dri/card0
12791 12:12:54.774890 N<8>[ 28.324126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12792 12:12:54.775196 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12794 12:12:54.781886 o KMS driver or no outputs, pipes: 8, outputs: 0
12795 12:12:54.784836 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12796 12:12:54.798618 <14>[ 28.350937] [IGT] kms_vblank: executing
12797 12:12:54.805225 IGT-Version: 1.2<14>[ 28.355933] [IGT] kms_vblank: exiting, ret=77
12798 12:12:54.808502 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12799 12:12:54.811725 Opened device: /dev/dri/card0
12800 12:12:54.818491 N<8>[ 28.367238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12801 12:12:54.818808 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12803 12:12:54.825325 o KMS driver or no outputs, pipes: 8, outputs: 0
12804 12:12:54.831776 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12805 12:12:54.842020 <14>[ 28.394324] [IGT] kms_vblank: executing
12806 12:12:54.848537 IGT-Version: 1.2<14>[ 28.399449] [IGT] kms_vblank: exiting, ret=77
12807 12:12:54.852004 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12808 12:12:54.855546 Opened device: /dev/dri/card0
12809 12:12:54.862018 N<8>[ 28.410551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12810 12:12:54.862321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12812 12:12:54.868662 o KMS driver or no outputs, pipes: 8, outputs: 0
12813 12:12:54.871798 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12814 12:12:54.885805 <14>[ 28.438290] [IGT] kms_vblank: executing
12815 12:12:54.892470 IGT-Version: 1.2<14>[ 28.443813] [IGT] kms_vblank: exiting, ret=77
12816 12:12:54.895956 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12817 12:12:54.899030 Opened device: /dev/dri/card0
12818 12:12:54.905962 N<8>[ 28.455492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12819 12:12:54.906253 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12821 12:12:54.912202 o KMS driver or no outputs, pipes: 8, outputs: 0
12822 12:12:54.915884 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12823 12:12:54.929304 <14>[ 28.481542] [IGT] kms_vblank: executing
12824 12:12:54.935897 IGT-Version: 1.2<14>[ 28.486673] [IGT] kms_vblank: exiting, ret=77
12825 12:12:54.939421 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12826 12:12:54.942374 Opened device: /dev/dri/card0
12827 12:12:54.949056 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12829 12:12:54.952283 N<8>[ 28.498051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12830 12:12:54.955687 o KMS driver or no outputs, pipes: 8, outputs: 0
12831 12:12:54.962004 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12832 12:12:54.972985 <14>[ 28.525226] [IGT] kms_vblank: executing
12833 12:12:54.979581 IGT-Version: 1.2<14>[ 28.530251] [IGT] kms_vblank: exiting, ret=77
12834 12:12:54.983197 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12835 12:12:54.986161 Opened device: /dev/dri/card0
12836 12:12:54.992594 N<8>[ 28.542193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12837 12:12:54.992888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12839 12:12:54.999530 o KMS driver or no outputs, pipes: 8, outputs: 0
12840 12:12:55.006064 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12841 12:12:55.016734 <14>[ 28.568645] [IGT] kms_vblank: executing
12842 12:12:55.023165 IGT-Version: 1.2<14>[ 28.573779] [IGT] kms_vblank: exiting, ret=77
12843 12:12:55.026549 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12844 12:12:55.029337 Opened device: /dev/dri/card0
12845 12:12:55.036174 N<8>[ 28.585509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12846 12:12:55.036491 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12848 12:12:55.039651 o KMS driver or no outputs, pipes: 8, outputs: 0
12849 12:12:55.046158 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12850 12:12:55.059188 <14>[ 28.611176] [IGT] kms_vblank: executing
12851 12:12:55.065765 IGT-Version: 1.2<14>[ 28.616179] [IGT] kms_vblank: exiting, ret=77
12852 12:12:55.068856 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12853 12:12:55.072313 Opened device: /dev/dri/card0
12854 12:12:55.078929 N<8>[ 28.628094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12855 12:12:55.079226 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12857 12:12:55.081963 o KMS driver or no outputs, pipes: 8, outputs: 0
12858 12:12:55.088411 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12859 12:12:55.102252 <14>[ 28.654330] [IGT] kms_vblank: executing
12860 12:12:55.108755 IGT-Version: 1.2<14>[ 28.659749] [IGT] kms_vblank: exiting, ret=77
12861 12:12:55.111791 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12862 12:12:55.115189 Opened device: /dev/dri/card0
12863 12:12:55.121931 N<8>[ 28.671077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12864 12:12:55.122214 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12866 12:12:55.125225 o KMS driver or no outputs, pipes: 8, outputs: 0
12867 12:12:55.131660 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12868 12:12:55.144341 <14>[ 28.696750] [IGT] kms_vblank: executing
12869 12:12:55.151251 IGT-Version: 1.2<14>[ 28.701729] [IGT] kms_vblank: exiting, ret=77
12870 12:12:55.154253 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12871 12:12:55.157863 Opened device: /dev/dri/card0
12872 12:12:55.164169 N<8>[ 28.713365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12873 12:12:55.164459 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12875 12:12:55.167624 o KMS driver or no outputs, pipes: 8, outputs: 0
12876 12:12:55.174135 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12877 12:12:55.186703 <14>[ 28.739210] [IGT] kms_vblank: executing
12878 12:12:55.193574 IGT-Version: 1.2<14>[ 28.744203] [IGT] kms_vblank: exiting, ret=77
12879 12:12:55.196685 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12880 12:12:55.200146 Opened device: /dev/dri/card0
12881 12:12:55.206562 N<8>[ 28.755852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12882 12:12:55.206857 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12884 12:12:55.213117 o KMS driver or no outputs, pipes: 8, outputs: 0
12885 12:12:55.216572 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12886 12:12:55.229603 <14>[ 28.781934] [IGT] kms_vblank: executing
12887 12:12:55.236146 IGT-Version: 1.2<14>[ 28.787155] [IGT] kms_vblank: exiting, ret=77
12888 12:12:55.239401 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12889 12:12:55.242632 Opened device: /dev/dri/card0
12890 12:12:55.249230 N<8>[ 28.798156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12891 12:12:55.249541 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12893 12:12:55.252711 o KMS driver or no outputs, pipes: 8, outputs: 0
12894 12:12:55.259453 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12895 12:12:55.271704 <14>[ 28.823947] [IGT] kms_vblank: executing
12896 12:12:55.278281 IGT-Version: 1.2<14>[ 28.828953] [IGT] kms_vblank: exiting, ret=77
12897 12:12:55.281786 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12898 12:12:55.284665 Opened device: /dev/dri/card0
12899 12:12:55.291822 N<8>[ 28.840550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12900 12:12:55.292108 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12902 12:12:55.294706 o KMS driver or no outputs, pipes: 8, outputs: 0
12903 12:12:55.301248 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12904 12:12:55.314100 <14>[ 28.866555] [IGT] kms_vblank: executing
12905 12:12:55.320991 IGT-Version: 1.2<14>[ 28.871666] [IGT] kms_vblank: exiting, ret=77
12906 12:12:55.323895 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12907 12:12:55.327308 Opened device: /dev/dri/card0
12908 12:12:55.333752 N<8>[ 28.883308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12909 12:12:55.334055 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12911 12:12:55.340415 o KMS driver or no outputs, pipes: 8, outputs: 0
12912 12:12:55.343685 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12913 12:12:55.356623 <14>[ 28.909210] [IGT] kms_vblank: executing
12914 12:12:55.363455 IGT-Version: 1.2<14>[ 28.914216] [IGT] kms_vblank: exiting, ret=77
12915 12:12:55.366499 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12916 12:12:55.370081 Opened device: /dev/dri/card0
12917 12:12:55.376425 N<8>[ 28.926007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12918 12:12:55.376727 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12920 12:12:55.382978 o KMS driver or no outputs, pipes: 8, outputs: 0
12921 12:12:55.386575 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12922 12:12:55.409698 <14>[ 28.962109] [IGT] kms_vblank: executing
12923 12:12:55.416229 IGT-Version: 1.2<14>[ 28.967294] [IGT] kms_vblank: exiting, ret=77
12924 12:12:55.419735 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12925 12:12:55.423262 Opened device: /dev/dri/card0
12926 12:12:55.429598 No KMS driver or <8>[ 28.979827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12927 12:12:55.429954 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12929 12:12:55.432657 no outputs, pipes: 8, outputs: 0
12930 12:12:55.439156 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12931 12:12:55.454407 <14>[ 29.006869] [IGT] kms_vblank: executing
12932 12:12:55.461391 IGT-Version: 1.2<14>[ 29.011996] [IGT] kms_vblank: exiting, ret=77
12933 12:12:55.464690 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12934 12:12:55.468100 Opened device: /dev/dri/card0
12935 12:12:55.474582 N<8>[ 29.023550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12936 12:12:55.474879 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12938 12:12:55.477434 o KMS driver or no outputs, pipes: 8, outputs: 0
12939 12:12:55.484405 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12940 12:12:55.497027 <14>[ 29.049428] [IGT] kms_vblank: executing
12941 12:12:55.503668 IGT-Version: 1.2<14>[ 29.054447] [IGT] kms_vblank: exiting, ret=77
12942 12:12:55.507189 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12943 12:12:55.510219 Opened device: /dev/dri/card0
12944 12:12:55.516636 N<8>[ 29.065982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12945 12:12:55.516934 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12947 12:12:55.520070 o KMS driver or no outputs, pipes: 8, outputs: 0
12948 12:12:55.526737 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12949 12:12:55.539290 <14>[ 29.091746] [IGT] kms_vblank: executing
12950 12:12:55.545735 IGT-Version: 1.2<14>[ 29.096839] [IGT] kms_vblank: exiting, ret=77
12951 12:12:55.549170 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12952 12:12:55.552432 Opened device: /dev/dri/card0
12953 12:12:55.559025 N<8>[ 29.108221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12954 12:12:55.559334 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12956 12:12:55.565593 o KMS driver or no outputs, pipes: 8, outputs: 0
12957 12:12:55.568665 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12958 12:12:55.581868 <14>[ 29.134167] [IGT] kms_vblank: executing
12959 12:12:55.588204 IGT-Version: 1.2<14>[ 29.139349] [IGT] kms_vblank: exiting, ret=77
12960 12:12:55.591787 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12961 12:12:55.595278 Opened device: /dev/dri/card0
12962 12:12:55.602003 N<8>[ 29.150441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12963 12:12:55.602303 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12965 12:12:55.604962 o KMS driver or no outputs, pipes: 8, outputs: 0
12966 12:12:55.611426 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12967 12:12:55.623762 <14>[ 29.176062] [IGT] kms_vblank: executing
12968 12:12:55.630268 IGT-Version: 1.2<14>[ 29.181045] [IGT] kms_vblank: exiting, ret=77
12969 12:12:55.633746 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12970 12:12:55.636929 Opened device: /dev/dri/card0
12971 12:12:55.643449 N<8>[ 29.192442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12972 12:12:55.643735 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12974 12:12:55.646969 o KMS driver or no outputs, pipes: 8, outputs: 0
12975 12:12:55.653397 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12976 12:12:55.666140 <14>[ 29.218435] [IGT] kms_vblank: executing
12977 12:12:55.672420 IGT-Version: 1.2<14>[ 29.223580] [IGT] kms_vblank: exiting, ret=77
12978 12:12:55.675795 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12979 12:12:55.679223 Opened device: /dev/dri/card0
12980 12:12:55.685700 N<8>[ 29.235393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12981 12:12:55.685998 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12983 12:12:55.692186 o KMS driver or no outputs, pipes: 8, outputs: 0
12984 12:12:55.695728 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12985 12:12:55.709760 <14>[ 29.261930] [IGT] kms_vblank: executing
12986 12:12:55.716408 IGT-Version: 1.2<14>[ 29.267229] [IGT] kms_vblank: exiting, ret=77
12987 12:12:55.719400 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12988 12:12:55.722934 Opened device: /dev/dri/card0
12989 12:12:55.729303 N<8>[ 29.278191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12990 12:12:55.729595 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12992 12:12:55.735732 o KMS driver or no outputs, pipes: 8, outputs: 0
12993 12:12:55.739185 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12994 12:12:55.752829 <14>[ 29.305002] [IGT] kms_vblank: executing
12995 12:12:55.759148 IGT-Version: 1.2<14>[ 29.309988] [IGT] kms_vblank: exiting, ret=77
12996 12:12:55.762451 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12997 12:12:55.765744 Opened device: /dev/dri/card0
12998 12:12:55.772737 N<8>[ 29.321430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12999 12:12:55.773065 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13001 12:12:55.778860 o KMS driver or no outputs, pipes: 8, outputs: 0
13002 12:12:55.782203 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13003 12:12:55.795256 <14>[ 29.347593] [IGT] kms_vblank: executing
13004 12:12:55.801801 IGT-Version: 1.2<14>[ 29.352687] [IGT] kms_vblank: exiting, ret=77
13005 12:12:55.804785 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13006 12:12:55.808289 Opened device: /dev/dri/card0
13007 12:12:55.814835 N<8>[ 29.364144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13008 12:12:55.815126 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13010 12:12:55.821447 o KMS driver or no outputs, pipes: 8, outputs: 0
13011 12:12:55.827837 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13012 12:12:55.838593 <14>[ 29.391003] [IGT] kms_vblank: executing
13013 12:12:55.845130 IGT-Version: 1.2<14>[ 29.396121] [IGT] kms_vblank: exiting, ret=77
13014 12:12:55.848696 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13015 12:12:55.851790 Opened device: /dev/dri/card0
13016 12:12:55.858243 N<8>[ 29.407493] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13017 12:12:55.858545 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13019 12:12:55.865286 o KMS driver or no outputs, pipes: 8, outputs: 0
13020 12:12:55.868203 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13021 12:12:55.882033 <14>[ 29.434166] [IGT] kms_vblank: executing
13022 12:12:55.888395 IGT-Version: 1.2<14>[ 29.439414] [IGT] kms_vblank: exiting, ret=77
13023 12:12:55.891586 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13024 12:12:55.894913 Opened device: /dev/dri/card0
13025 12:12:55.901720 N<8>[ 29.450386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13026 12:12:55.902068 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13028 12:12:55.908110 o KMS driver or no outputs, pipes: 8, outputs: 0
13029 12:12:55.914759 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13030 12:12:55.925239 <14>[ 29.477545] [IGT] kms_vblank: executing
13031 12:12:55.931646 IGT-Version: 1.2<14>[ 29.482573] [IGT] kms_vblank: exiting, ret=77
13032 12:12:55.934913 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13033 12:12:55.938419 Opened device: /dev/dri/card0
13034 12:12:55.944900 N<8>[ 29.493893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13035 12:12:55.945221 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13037 12:12:55.951501 o KMS driver or no outputs, pipes: 8, outputs: 0
13038 12:12:55.955039 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13039 12:12:55.968120 <14>[ 29.520456] [IGT] kms_vblank: executing
13040 12:12:55.974675 IGT-Version: 1.2<14>[ 29.525556] [IGT] kms_vblank: exiting, ret=77
13041 12:12:55.978082 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13042 12:12:55.981012 Opened device: /dev/dri/card0
13043 12:12:55.987876 N<8>[ 29.536793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13044 12:12:55.988185 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13046 12:12:55.994539 o KMS driver or no outputs, pipes: 8, outputs: 0
13047 12:12:55.997575 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13048 12:12:56.011462 <14>[ 29.563690] [IGT] kms_vblank: executing
13049 12:12:56.018020 IGT-Version: 1.2<14>[ 29.568818] [IGT] kms_vblank: exiting, ret=77
13050 12:12:56.021038 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13051 12:12:56.024473 Opened device: /dev/dri/card0
13052 12:12:56.031057 N<8>[ 29.580544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13053 12:12:56.031349 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13055 12:12:56.038026 o KMS driver or no outputs, pipes: 8, outputs: 0
13056 12:12:56.044538 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13057 12:12:56.056160 <14>[ 29.608412] [IGT] kms_vblank: executing
13058 12:12:56.062544 IGT-Version: 1.2<14>[ 29.613428] [IGT] kms_vblank: exiting, ret=77
13059 12:12:56.066102 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13060 12:12:56.069106 Opened device: /dev/dri/card0
13061 12:12:56.076291 N<8>[ 29.625074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13062 12:12:56.076589 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13064 12:12:56.082802 o KMS driver or no outputs, pipes: 8, outputs: 0
13065 12:12:56.086264 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13066 12:12:56.100892 <14>[ 29.653217] [IGT] kms_vblank: executing
13067 12:12:56.107323 IGT-Version: 1.2<14>[ 29.658201] [IGT] kms_vblank: exiting, ret=77
13068 12:12:56.110556 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13069 12:12:56.113827 Opened device: /dev/dri/card0
13070 12:12:56.120722 N<8>[ 29.670059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13071 12:12:56.121055 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13073 12:12:56.123816 o KMS driver or no outputs, pipes: 8, outputs: 0
13074 12:12:56.130333 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13075 12:12:56.143290 <14>[ 29.695694] [IGT] kms_vblank: executing
13076 12:12:56.149933 IGT-Version: 1.2<14>[ 29.700659] [IGT] kms_vblank: exiting, ret=77
13077 12:12:56.152954 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13078 12:12:56.156402 Opened device: /dev/dri/card0
13079 12:12:56.163098 N<8>[ 29.712371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13080 12:12:56.163404 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13082 12:12:56.166493 o KMS driver or no outputs, pipes: 8, outputs: 0
13083 12:12:56.172992 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13084 12:12:56.186670 <14>[ 29.738966] [IGT] kms_vblank: executing
13085 12:12:56.193089 IGT-Version: 1.2<14>[ 29.743962] [IGT] kms_vblank: exiting, ret=77
13086 12:12:56.196495 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13087 12:12:56.199721 Opened device: /dev/dri/card0
13088 12:12:56.206243 N<8>[ 29.755593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13089 12:12:56.206587 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13091 12:12:56.209490 o KMS driver or no outputs, pipes: 8, outputs: 0
13092 12:12:56.216010 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13093 12:12:56.229058 <14>[ 29.781298] [IGT] kms_vblank: executing
13094 12:12:56.235670 IGT-Version: 1.2<14>[ 29.786399] [IGT] kms_vblank: exiting, ret=77
13095 12:12:56.238751 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13096 12:12:56.242240 Opened device: /dev/dri/card0
13097 12:12:56.249100 N<8>[ 29.797606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13098 12:12:56.249393 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13100 12:12:56.252072 o KMS driver or no outputs, pipes: 8, outputs: 0
13101 12:12:56.258652 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13102 12:12:56.271276 <14>[ 29.823519] [IGT] kms_vblank: executing
13103 12:12:56.277636 IGT-Version: 1.2<14>[ 29.828502] [IGT] kms_vblank: exiting, ret=77
13104 12:12:56.280685 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13105 12:12:56.284219 Opened device: /dev/dri/card0
13106 12:12:56.290878 N<8>[ 29.840301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13107 12:12:56.291183 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13109 12:12:56.297686 o KMS driver or no outputs, pipes: 8, outputs: 0
13110 12:12:56.300520 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13111 12:12:56.314844 <14>[ 29.867184] [IGT] kms_vblank: executing
13112 12:12:56.321392 IGT-Version: 1.2<14>[ 29.872187] [IGT] kms_vblank: exiting, ret=77
13113 12:12:56.324631 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13114 12:12:56.327773 Opened device: /dev/dri/card0
13115 12:12:56.334727 N<8>[ 29.884205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13116 12:12:56.335066 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13118 12:12:56.337764 o KMS driver or no outputs, pipes: 8, outputs: 0
13119 12:12:56.344208 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13120 12:12:56.356625 <14>[ 29.909172] [IGT] kms_vblank: executing
13121 12:12:56.363274 IGT-Version: 1.2<14>[ 29.914290] [IGT] kms_vblank: exiting, ret=77
13122 12:12:56.366821 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13123 12:12:56.369904 Opened device: /dev/dri/card0
13124 12:12:56.376742 N<8>[ 29.925883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13125 12:12:56.377067 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13127 12:12:56.379787 o KMS driver or no outputs, pipes: 8, outputs: 0
13128 12:12:56.386870 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13129 12:12:56.399413 <14>[ 29.951700] [IGT] kms_vblank: executing
13130 12:12:56.405700 IGT-Version: 1.2<14>[ 29.956668] [IGT] kms_vblank: exiting, ret=77
13131 12:12:56.409181 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13132 12:12:56.412585 Opened device: /dev/dri/card0
13133 12:12:56.418792 N<8>[ 29.968353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13134 12:12:56.419085 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13136 12:12:56.425957 o KMS driver or no outputs, pipes: 8, outputs: 0
13137 12:12:56.428672 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13138 12:12:56.443267 <14>[ 29.995442] [IGT] kms_vblank: executing
13139 12:12:56.449734 IGT-Version: 1.2<14>[ 30.000424] [IGT] kms_vblank: exiting, ret=77
13140 12:12:56.452689 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13141 12:12:56.456212 Opened device: /dev/dri/card0
13142 12:12:56.462766 N<8>[ 30.012284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13143 12:12:56.463068 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13145 12:12:56.469273 o KMS driver or no outputs, pipes: 8, outputs: 0
13146 12:12:56.472717 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13147 12:12:56.487530 <14>[ 30.039908] [IGT] kms_vblank: executing
13148 12:12:56.494000 IGT-Version: 1.2<14>[ 30.044870] [IGT] kms_vblank: exiting, ret=77
13149 12:12:56.497545 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13150 12:12:56.500510 Opened device: /dev/dri/card0
13151 12:12:56.507467 N<8>[ 30.056734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13152 12:12:56.507756 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13154 12:12:56.510489 o KMS driver or no outputs, pipes: 8, outputs: 0
13155 12:12:56.517175 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13156 12:12:56.529735 <14>[ 30.081940] [IGT] kms_vblank: executing
13157 12:12:56.535853 IGT-Version: 1.2<14>[ 30.087195] [IGT] kms_vblank: exiting, ret=77
13158 12:12:56.539529 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13159 12:12:56.542928 Opened device: /dev/dri/card0
13160 12:12:56.549484 N<8>[ 30.098818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13161 12:12:56.549782 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13163 12:12:56.552466 o KMS driver or no outputs, pipes: 8, outputs: 0
13164 12:12:56.559323 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13165 12:12:56.572980 <14>[ 30.125293] [IGT] kms_vblank: executing
13166 12:12:56.579389 IGT-Version: 1.2<14>[ 30.130348] [IGT] kms_vblank: exiting, ret=77
13167 12:12:56.583108 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13168 12:12:56.586155 Opened device: /dev/dri/card0
13169 12:12:56.592667 N<8>[ 30.141664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13170 12:12:56.592960 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13172 12:12:56.596195 o KMS driver or no outputs, pipes: 8, outputs: 0
13173 12:12:56.602695 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13174 12:12:56.614907 <14>[ 30.167302] [IGT] kms_vblank: executing
13175 12:12:56.621512 IGT-Version: 1.2<14>[ 30.172294] [IGT] kms_vblank: exiting, ret=77
13176 12:12:56.624755 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13177 12:12:56.627976 Opened device: /dev/dri/card0
13178 12:12:56.634886 N<8>[ 30.184189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13179 12:12:56.635217 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13181 12:12:56.638229 o KMS driver or no outputs, pipes: 8, outputs: 0
13182 12:12:56.644649 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13183 12:12:56.658682 <14>[ 30.211143] [IGT] kms_vblank: executing
13184 12:12:56.665306 IGT-Version: 1.2<14>[ 30.216101] [IGT] kms_vblank: exiting, ret=77
13185 12:12:56.668798 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13186 12:12:56.671899 Opened device: /dev/dri/card0
13187 12:12:56.678326 N<8>[ 30.228354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13188 12:12:56.678737 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13190 12:12:56.681780 o KMS driver or no outputs, pipes: 8, outputs: 0
13191 12:12:56.688360 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13192 12:12:56.700522 <14>[ 30.253081] [IGT] kms_vblank: executing
13193 12:12:56.707056 IGT-Version: 1.2<14>[ 30.258252] [IGT] kms_vblank: exiting, ret=77
13194 12:12:56.710559 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13195 12:12:56.714082 Opened device: /dev/dri/card0
13196 12:12:56.720602 N<8>[ 30.269940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13197 12:12:56.720894 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13199 12:12:56.726908 o KMS driver or no outputs, pipes: 8, outputs: 0
13200 12:12:56.730253 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13201 12:12:56.742983 <14>[ 30.295633] [IGT] kms_vblank: executing
13202 12:12:56.750013 IGT-Version: 1.2<14>[ 30.300664] [IGT] kms_vblank: exiting, ret=77
13203 12:12:56.753173 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13204 12:12:56.756115 Opened device: /dev/dri/card0
13205 12:12:56.763070 N<8>[ 30.312383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13206 12:12:56.763403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13208 12:12:56.769665 o KMS driver or no outputs, pipes: 8, outputs: 0
13209 12:12:56.772679 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13210 12:12:56.787252 <14>[ 30.339553] [IGT] kms_vblank: executing
13211 12:12:56.793762 IGT-Version: 1.2<14>[ 30.344539] [IGT] kms_vblank: exiting, ret=77
13212 12:12:56.797242 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13213 12:12:56.800302 Opened device: /dev/dri/card0
13214 12:12:56.806785 N<8>[ 30.356041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13215 12:12:56.807096 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13217 12:12:56.813340 o KMS driver or no outputs, pipes: 8, outputs: 0
13218 12:12:56.816863 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13219 12:12:56.830140 <14>[ 30.382794] [IGT] kms_vblank: executing
13220 12:12:56.836724 IGT-Version: 1.2<14>[ 30.387838] [IGT] kms_vblank: exiting, ret=77
13221 12:12:56.840090 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13222 12:12:56.843445 Opened device: /dev/dri/card0
13223 12:12:56.850083 N<8>[ 30.399673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13224 12:12:56.850431 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13226 12:12:56.856836 o KMS driver or no outputs, pipes: 8, outputs: 0
13227 12:12:56.860081 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13228 12:12:56.873283 <14>[ 30.425804] [IGT] kms_vblank: executing
13229 12:12:56.880067 IGT-Version: 1.2<14>[ 30.430945] [IGT] kms_vblank: exiting, ret=77
13230 12:12:56.883443 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13231 12:12:56.886327 Opened device: /dev/dri/card0
13232 12:12:56.893162 N<8>[ 30.442088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13233 12:12:56.893522 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13235 12:12:56.899701 o KMS driver or no outputs, pipes: 8, outputs: 0
13236 12:12:56.902774 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13237 12:12:56.916247 <14>[ 30.468890] [IGT] kms_vblank: executing
13238 12:12:56.922702 IGT-Version: 1.2<14>[ 30.473997] [IGT] kms_vblank: exiting, ret=77
13239 12:12:56.926284 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13240 12:12:56.929814 Opened device: /dev/dri/card0
13241 12:12:56.936094 N<8>[ 30.485781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13242 12:12:56.936383 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13244 12:12:56.942773 o KMS driver or no outputs, pipes: 8, outputs: 0
13245 12:12:56.946098 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13246 12:12:56.960697 <14>[ 30.513372] [IGT] kms_vblank: executing
13247 12:12:56.967345 IGT-Version: 1.2<14>[ 30.518352] [IGT] kms_vblank: exiting, ret=77
13248 12:12:56.970625 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13249 12:12:56.974109 Opened device: /dev/dri/card0
13250 12:12:56.980709 N<8>[ 30.529928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13251 12:12:56.981023 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13253 12:12:56.987230 o KMS driver or no outputs, pipes: 8, outputs: 0
13254 12:12:56.993610 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13255 12:12:57.004706 <14>[ 30.557280] [IGT] kms_vblank: executing
13256 12:12:57.011231 IGT-Version: 1.2<14>[ 30.562383] [IGT] kms_vblank: exiting, ret=77
13257 12:12:57.014727 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13258 12:12:57.017812 Opened device: /dev/dri/card0
13259 12:12:57.024336 N<8>[ 30.573575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13260 12:12:57.024670 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13262 12:12:57.030899 o KMS driver or no outputs, pipes: 8, outputs: 0
13263 12:12:57.034308 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13264 12:12:57.047656 <14>[ 30.600358] [IGT] kms_vblank: executing
13265 12:12:57.054187 IGT-Version: 1.2<14>[ 30.605332] [IGT] kms_vblank: exiting, ret=77
13266 12:12:57.057957 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13267 12:12:57.060773 Opened device: /dev/dri/card0
13268 12:12:57.067379 N<8>[ 30.616690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13269 12:12:57.067700 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13271 12:12:57.074515 o KMS driver or no outputs, pipes: 8, outputs: 0
13272 12:12:57.077602 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13273 12:12:57.090668 <14>[ 30.643395] [IGT] kms_vblank: executing
13274 12:12:57.097688 IGT-Version: 1.2<14>[ 30.648555] [IGT] kms_vblank: exiting, ret=77
13275 12:12:57.100661 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13276 12:12:57.104217 Opened device: /dev/dri/card0
13277 12:12:57.111001 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13279 12:12:57.113851 N<8>[ 30.659916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13280 12:12:57.117289 o KMS driver or no outputs, pipes: 8, outputs: 0
13281 12:12:57.123936 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13282 12:12:57.134411 <14>[ 30.686982] [IGT] kms_vblank: executing
13283 12:12:57.141028 IGT-Version: 1.2<14>[ 30.692097] [IGT] kms_vblank: exiting, ret=77
13284 12:12:57.144442 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13285 12:12:57.147432 Opened device: /dev/dri/card0
13286 12:12:57.154123 N<8>[ 30.703509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13287 12:12:57.154425 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13289 12:12:57.160986 o KMS driver or no outputs, pipes: 8, outputs: 0
13290 12:12:57.167482 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13291 12:12:57.178143 <14>[ 30.730606] [IGT] kms_vblank: executing
13292 12:12:57.184569 IGT-Version: 1.2<14>[ 30.735575] [IGT] kms_vblank: exiting, ret=77
13293 12:12:57.188064 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13294 12:12:57.191050 Opened device: /dev/dri/card0
13295 12:12:57.197715 N<8>[ 30.747156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13296 12:12:57.198036 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13298 12:12:57.201215 o KMS driver or no outputs, pipes: 8, outputs: 0
13299 12:12:57.207654 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13300 12:12:57.220236 <14>[ 30.772631] [IGT] kms_vblank: executing
13301 12:12:57.226856 IGT-Version: 1.2<14>[ 30.777671] [IGT] kms_vblank: exiting, ret=77
13302 12:12:57.229805 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13303 12:12:57.233296 Opened device: /dev/dri/card0
13304 12:12:57.239899 N<8>[ 30.789110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13305 12:12:57.240184 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13307 12:12:57.242943 o KMS driver or no outputs, pipes: 8, outputs: 0
13308 12:12:57.249441 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13309 12:12:57.262186 <14>[ 30.814652] [IGT] kms_vblank: executing
13310 12:12:57.268689 IGT-Version: 1.2<14>[ 30.819676] [IGT] kms_vblank: exiting, ret=77
13311 12:12:57.271925 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13312 12:12:57.275242 Opened device: /dev/dri/card0
13313 12:12:57.281725 N<8>[ 30.831018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13314 12:12:57.282049 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13316 12:12:57.285083 o KMS driver or no outputs, pipes: 8, outputs: 0
13317 12:12:57.291660 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13318 12:12:57.304500 <14>[ 30.857011] [IGT] kms_vblank: executing
13319 12:12:57.311186 IGT-Version: 1.2<14>[ 30.862025] [IGT] kms_vblank: exiting, ret=77
13320 12:12:57.314211 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13321 12:12:57.317707 Opened device: /dev/dri/card0
13322 12:12:57.324315 N<8>[ 30.873377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13323 12:12:57.324603 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13325 12:12:57.327803 o KMS driver or no outputs, pipes: 8, outputs: 0
13326 12:12:57.334333 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13327 12:12:57.347824 <14>[ 30.900269] [IGT] kms_vblank: executing
13328 12:12:57.354325 IGT-Version: 1.2<14>[ 30.905457] [IGT] kms_vblank: exiting, ret=77
13329 12:12:57.357817 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13330 12:12:57.360720 Opened device: /dev/dri/card0
13331 12:12:57.367215 N<8>[ 30.917137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13332 12:12:57.367530 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13334 12:12:57.373848 o KMS driver or no outputs, pipes: 8, outputs: 0
13335 12:12:57.377145 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13336 12:12:57.391054 <14>[ 30.943802] [IGT] kms_vblank: executing
13337 12:12:57.398094 IGT-Version: 1.2<14>[ 30.948764] [IGT] kms_vblank: exiting, ret=77
13338 12:12:57.400973 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13339 12:12:57.404507 Opened device: /dev/dri/card0
13340 12:12:57.410985 N<8>[ 30.960517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13341 12:12:57.411305 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13343 12:12:57.414383 o KMS driver or no outputs, pipes: 8, outputs: 0
13344 12:12:57.420943 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13345 12:12:57.433090 <14>[ 30.985884] [IGT] kms_vblank: executing
13346 12:12:57.439898 IGT-Version: 1.2<14>[ 30.991133] [IGT] kms_vblank: exiting, ret=77
13347 12:12:57.443277 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13348 12:12:57.446306 Opened device: /dev/dri/card0
13349 12:12:57.453179 N<8>[ 31.002704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13350 12:12:57.453514 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13352 12:12:57.456277 o KMS driver or no outputs, pipes: 8, outputs: 0
13353 12:12:57.463349 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13354 12:12:57.475500 <14>[ 31.028352] [IGT] kms_vblank: executing
13355 12:12:57.482349 IGT-Version: 1.2<14>[ 31.033448] [IGT] kms_vblank: exiting, ret=77
13356 12:12:57.485647 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13357 12:12:57.488982 Opened device: /dev/dri/card0
13358 12:12:57.495937 N<8>[ 31.045120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13359 12:12:57.496301 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13361 12:12:57.502465 o KMS driver or no outputs, pipes: 8, outputs: 0
13362 12:12:57.505720 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13363 12:12:57.519672 <14>[ 31.072241] [IGT] kms_vblank: executing
13364 12:12:57.526283 IGT-Version: 1.2<14>[ 31.077231] [IGT] kms_vblank: exiting, ret=77
13365 12:12:57.529834 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13366 12:12:57.532990 Opened device: /dev/dri/card0
13367 12:12:57.539433 N<8>[ 31.089104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13368 12:12:57.539744 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13370 12:12:57.546027 o KMS driver or no outputs, pipes: 8, outputs: 0
13371 12:12:57.549021 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13372 12:12:57.562861 <14>[ 31.115326] [IGT] kms_vblank: executing
13373 12:12:57.569364 IGT-Version: 1.2<14>[ 31.120416] [IGT] kms_vblank: exiting, ret=77
13374 12:12:57.572996 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13375 12:12:57.575962 Opened device: /dev/dri/card0
13376 12:12:57.582763 N<8>[ 31.131778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13377 12:12:57.583088 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13379 12:12:57.585679 o KMS driver or no outputs, pipes: 8, outputs: 0
13380 12:12:57.592306 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13381 12:12:57.604389 <14>[ 31.157118] [IGT] kms_vblank: executing
13382 12:12:57.611378 IGT-Version: 1.2<14>[ 31.162230] [IGT] kms_vblank: exiting, ret=77
13383 12:12:57.614110 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13384 12:12:57.617420 Opened device: /dev/dri/card0
13385 12:12:57.624376 N<8>[ 31.173857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13386 12:12:57.624694 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13388 12:12:57.627463 o KMS driver or no outputs, pipes: 8, outputs: 0
13389 12:12:57.633983 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13390 12:12:57.647060 <14>[ 31.199499] [IGT] kms_vblank: executing
13391 12:12:57.653715 IGT-Version: 1.2<14>[ 31.204619] [IGT] kms_vblank: exiting, ret=77
13392 12:12:57.656585 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13393 12:12:57.660078 Opened device: /dev/dri/card0
13394 12:12:57.666715 N<8>[ 31.216441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13395 12:12:57.667037 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13397 12:12:57.670251 o KMS driver or no outputs, pipes: 8, outputs: 0
13398 12:12:57.676660 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13399 12:12:57.690321 <14>[ 31.243051] [IGT] kms_vblank: executing
13400 12:12:57.696943 IGT-Version: 1.2<14>[ 31.248120] [IGT] kms_vblank: exiting, ret=77
13401 12:12:57.700358 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13402 12:12:57.703676 Opened device: /dev/dri/card0
13403 12:12:57.710311 N<8>[ 31.260197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13404 12:12:57.710641 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13406 12:12:57.716846 o KMS driver or no outputs, pipes: 8, outputs: 0
13407 12:12:57.720139 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13408 12:12:57.734463 <14>[ 31.287067] [IGT] kms_vblank: executing
13409 12:12:57.740864 IGT-Version: 1.2<14>[ 31.292198] [IGT] kms_vblank: exiting, ret=77
13410 12:12:57.744434 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13411 12:12:57.747495 Opened device: /dev/dri/card0
13412 12:12:57.754179 N<8>[ 31.303889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13413 12:12:57.754502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13415 12:12:57.757624 o KMS driver or no outputs, pipes: 8, outputs: 0
13416 12:12:57.764081 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13417 12:12:57.776241 <14>[ 31.329096] [IGT] kms_vblank: executing
13418 12:12:57.782808 IGT-Version: 1.2<14>[ 31.334073] [IGT] kms_vblank: exiting, ret=77
13419 12:12:57.786224 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13420 12:12:57.789594 Opened device: /dev/dri/card0
13421 12:12:57.796205 N<8>[ 31.346038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13422 12:12:57.796496 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13424 12:12:57.799613 o KMS driver or no outputs, pipes: 8, outputs: 0
13425 12:12:57.805832 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13426 12:12:57.818761 <14>[ 31.371485] [IGT] kms_vblank: executing
13427 12:12:57.825347 IGT-Version: 1.2<14>[ 31.376569] [IGT] kms_vblank: exiting, ret=77
13428 12:12:57.828595 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13429 12:12:57.832040 Opened device: /dev/dri/card0
13430 12:12:57.838510 N<8>[ 31.387906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13431 12:12:57.838791 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13433 12:12:57.845103 o KMS driver or no outputs, pipes: 8, outputs: 0
13434 12:12:57.848703 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13435 12:12:57.861303 <14>[ 31.413842] [IGT] kms_vblank: executing
13436 12:12:57.867946 IGT-Version: 1.2<14>[ 31.418859] [IGT] kms_vblank: exiting, ret=77
13437 12:12:57.870983 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13438 12:12:57.874491 Opened device: /dev/dri/card0
13439 12:12:57.880997 N<8>[ 31.430366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13440 12:12:57.881316 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13442 12:12:57.887551 o KMS driver or no outputs, pipes: 8, outputs: 0
13443 12:12:57.890957 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13444 12:12:57.903938 <14>[ 31.456654] [IGT] kms_vblank: executing
13445 12:12:57.910667 IGT-Version: 1.2<14>[ 31.461683] [IGT] kms_vblank: exiting, ret=77
13446 12:12:57.914005 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13447 12:12:57.917279 Opened device: /dev/dri/card0
13448 12:12:57.924057 N<8>[ 31.473288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13449 12:12:57.924374 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13451 12:12:57.930603 o KMS driver or no outputs, pipes: 8, outputs: 0
13452 12:12:57.933877 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13453 12:12:57.947643 <14>[ 31.500592] [IGT] kms_vblank: executing
13454 12:12:57.954559 IGT-Version: 1.2<14>[ 31.505705] [IGT] kms_vblank: exiting, ret=77
13455 12:12:57.958104 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13456 12:12:57.960932 Opened device: /dev/dri/card0
13457 12:12:57.967953 N<8>[ 31.517523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13458 12:12:57.968281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13460 12:12:57.974511 o KMS driver or no outputs, pipes: 8, outputs: 0
13461 12:12:57.977468 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13462 12:12:57.992533 <14>[ 31.545094] [IGT] kms_vblank: executing
13463 12:12:57.998796 IGT-Version: 1.2<14>[ 31.550070] [IGT] kms_vblank: exiting, ret=77
13464 12:12:58.002353 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13465 12:12:58.005441 Opened device: /dev/dri/card0
13466 12:12:58.012456 N<8>[ 31.561989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13467 12:12:58.012752 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13469 12:12:58.018868 o KMS driver or no outputs, pipes: 8, outputs: 0
13470 12:12:58.022113 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13471 12:12:58.035767 <14>[ 31.588547] [IGT] kms_vblank: executing
13472 12:12:58.042313 IGT-Version: 1.2<14>[ 31.593561] [IGT] kms_vblank: exiting, ret=77
13473 12:12:58.045741 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13474 12:12:58.049250 Opened device: /dev/dri/card0
13475 12:12:58.055711 N<8>[ 31.604826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13476 12:12:58.056005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13478 12:12:58.062206 o KMS driver or no outputs, pipes: 8, outputs: 0
13479 12:12:58.068696 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13480 12:12:58.079317 <14>[ 31.632158] [IGT] kms_vblank: executing
13481 12:12:58.086003 IGT-Version: 1.2<14>[ 31.637192] [IGT] kms_vblank: exiting, ret=77
13482 12:12:58.089510 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13483 12:12:58.092909 Opened device: /dev/dri/card0
13484 12:12:58.099224 N<8>[ 31.648822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13485 12:12:58.099521 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13487 12:12:58.105676 o KMS driver or no outputs, pipes: 8, outputs: 0
13488 12:12:58.109185 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13489 12:12:58.123065 <14>[ 31.675453] [IGT] kms_vblank: executing
13490 12:12:58.129510 IGT-Version: 1.2<14>[ 31.680679] [IGT] kms_vblank: exiting, ret=77
13491 12:12:58.132910 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13492 12:12:58.136254 Opened device: /dev/dri/card0
13493 12:12:58.142421 N<8>[ 31.692294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13494 12:12:58.142798 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13496 12:12:58.149013 o KMS driver or no outputs, pipes: 8, outputs: 0
13497 12:12:58.152414 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13498 12:12:58.166938 <14>[ 31.719793] [IGT] kms_vblank: executing
13499 12:12:58.173842 IGT-Version: 1.2<14>[ 31.724794] [IGT] kms_vblank: exiting, ret=77
13500 12:12:58.176939 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13501 12:12:58.180454 Opened device: /dev/dri/card0
13502 12:12:58.186890 N<8>[ 31.736512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13503 12:12:58.187183 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13505 12:12:58.193523 o KMS driver or no outputs, pipes: 8, outputs: 0
13506 12:12:58.199965 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13507 12:12:58.211693 <14>[ 31.764503] [IGT] kms_vblank: executing
13508 12:12:58.218313 IGT-Version: 1.2<14>[ 31.769597] [IGT] kms_vblank: exiting, ret=77
13509 12:12:58.221760 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13510 12:12:58.225159 Opened device: /dev/dri/card0
13511 12:12:58.231396 N<8>[ 31.781229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13512 12:12:58.231708 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13514 12:12:58.238296 o KMS driver or no outputs, pipes: 8, outputs: 0
13515 12:12:58.244852 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13516 12:12:58.256737 <14>[ 31.809179] [IGT] kms_vblank: executing
13517 12:12:58.263291 IGT-Version: 1.2<14>[ 31.814270] [IGT] kms_vblank: exiting, ret=77
13518 12:12:58.266822 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13519 12:12:58.269797 Opened device: /dev/dri/card0
13520 12:12:58.276591 N<8>[ 31.826423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13521 12:12:58.276870 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13523 12:12:58.279526 o KMS driver or no outputs, pipes: 8, outputs: 0
13524 12:12:58.286226 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13525 12:12:58.300260 <14>[ 31.852844] [IGT] kms_vblank: executing
13526 12:12:58.306850 IGT-Version: 1.2<14>[ 31.858029] [IGT] kms_vblank: exiting, ret=77
13527 12:12:58.310166 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13528 12:12:58.313714 Opened device: /dev/dri/card0
13529 12:12:58.320317 N<8>[ 31.869426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13530 12:12:58.320618 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13532 12:12:58.323268 o KMS driver or no outputs, pipes: 8, outputs: 0
13533 12:12:58.330150 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13534 12:12:58.342349 <14>[ 31.895015] [IGT] kms_vblank: executing
13535 12:12:58.348947 IGT-Version: 1.2<14>[ 31.899968] [IGT] kms_vblank: exiting, ret=77
13536 12:12:58.352243 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13537 12:12:58.355503 Opened device: /dev/dri/card0
13538 12:12:58.362096 N<8>[ 31.911571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13539 12:12:58.362433 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13541 12:12:58.365516 o KMS driver or no outputs, pipes: 8, outputs: 0
13542 12:12:58.371927 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13543 12:12:58.385149 <14>[ 31.937483] [IGT] kms_vblank: executing
13544 12:12:58.391662 IGT-Version: 1.2<14>[ 31.942461] [IGT] kms_vblank: exiting, ret=77
13545 12:12:58.394687 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13546 12:12:58.397780 Opened device: /dev/dri/card0
13547 12:12:58.404443 N<8>[ 31.953798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13548 12:12:58.404775 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13550 12:12:58.408037 o KMS driver or no outputs, pipes: 8, outputs: 0
13551 12:12:58.414285 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13552 12:12:58.426748 <14>[ 31.979516] [IGT] kms_vblank: executing
13553 12:12:58.433191 IGT-Version: 1.2<14>[ 31.984539] [IGT] kms_vblank: exiting, ret=77
13554 12:12:58.436680 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13555 12:12:58.440136 Opened device: /dev/dri/card0
13556 12:12:58.446836 N<8>[ 31.996231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13557 12:12:58.447134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13559 12:12:58.453492 o KMS driver or no outputs, pipes: 8, outputs: 0
13560 12:12:58.456357 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13561 12:12:58.469168 <14>[ 32.022043] [IGT] kms_vblank: executing
13562 12:12:58.475701 IGT-Version: 1.2<14>[ 32.027119] [IGT] kms_vblank: exiting, ret=77
13563 12:12:58.479131 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13564 12:12:58.482605 Opened device: /dev/dri/card0
13565 12:12:58.489166 N<8>[ 32.038399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13566 12:12:58.489452 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13568 12:12:58.492196 o KMS driver or no outputs, pipes: 8, outputs: 0
13569 12:12:58.498839 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13570 12:12:58.511490 <14>[ 32.064076] [IGT] kms_vblank: executing
13571 12:12:58.517828 IGT-Version: 1.2<14>[ 32.069058] [IGT] kms_vblank: exiting, ret=77
13572 12:12:58.521378 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13573 12:12:58.524929 Opened device: /dev/dri/card0
13574 12:12:58.531003 N<8>[ 32.080872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13575 12:12:58.531290 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13577 12:12:58.534562 o KMS driver or no outputs, pipes: 8, outputs: 0
13578 12:12:58.541149 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13579 12:12:58.555213 <14>[ 32.107734] [IGT] kms_vblank: executing
13580 12:12:58.561691 IGT-Version: 1.2<14>[ 32.112700] [IGT] kms_vblank: exiting, ret=77
13581 12:12:58.565026 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13582 12:12:58.568290 Opened device: /dev/dri/card0
13583 12:12:58.574818 N<8>[ 32.124183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13584 12:12:58.575118 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13586 12:12:58.581659 o KMS driver or no outputs, pipes: 8, outputs: 0
13587 12:12:58.584590 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13588 12:12:58.597823 <14>[ 32.150227] [IGT] kms_vblank: executing
13589 12:12:58.604270 IGT-Version: 1.2<14>[ 32.155414] [IGT] kms_vblank: exiting, ret=77
13590 12:12:58.607316 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13591 12:12:58.610700 Opened device: /dev/dri/card0
13592 12:12:58.617272 N<8>[ 32.166816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13593 12:12:58.617610 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13595 12:12:58.623574 o KMS driver or no outputs, pipes: 8, outputs: 0
13596 12:12:58.627043 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13597 12:12:58.640548 <14>[ 32.193371] [IGT] kms_vblank: executing
13598 12:12:58.647045 IGT-Version: 1.2<14>[ 32.198376] [IGT] kms_vblank: exiting, ret=77
13599 12:12:58.650444 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13600 12:12:58.653900 Opened device: /dev/dri/card0
13601 12:12:58.660406 N<8>[ 32.209660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13602 12:12:58.660759 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13604 12:12:58.663515 o KMS driver or no outputs, pipes: 8, outputs: 0
13605 12:12:58.670169 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13606 12:12:58.682777 <14>[ 32.235364] [IGT] kms_vblank: executing
13607 12:12:58.689263 IGT-Version: 1.2<14>[ 32.240379] [IGT] kms_vblank: exiting, ret=77
13608 12:12:58.692388 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13609 12:12:58.695962 Opened device: /dev/dri/card0
13610 12:12:58.702500 N<8>[ 32.251813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13611 12:12:58.702796 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13613 12:12:58.706039 o KMS driver or no outputs, pipes: 8, outputs: 0
13614 12:12:58.712078 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13615 12:12:58.725107 <14>[ 32.277836] [IGT] kms_vblank: executing
13616 12:12:58.732107 IGT-Version: 1.2<14>[ 32.282897] [IGT] kms_vblank: exiting, ret=77
13617 12:12:58.735121 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13618 12:12:58.738541 Opened device: /dev/dri/card0
13619 12:12:58.745110 N<8>[ 32.294191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13620 12:12:58.745398 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13622 12:12:58.748118 o KMS driver or no outputs, pipes: 8, outputs: 0
13623 12:12:58.754637 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13624 12:12:58.766924 <14>[ 32.319800] [IGT] kms_vblank: executing
13625 12:12:58.773875 IGT-Version: 1.2<14>[ 32.324786] [IGT] kms_vblank: exiting, ret=77
13626 12:12:58.777064 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13627 12:12:58.780407 Opened device: /dev/dri/card0
13628 12:12:58.786833 N<8>[ 32.336773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13629 12:12:58.787127 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13631 12:12:58.789983 o KMS driver or no outputs, pipes: 8, outputs: 0
13632 12:12:58.796476 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13633 12:12:58.809601 <14>[ 32.362392] [IGT] kms_vblank: executing
13634 12:12:58.816074 IGT-Version: 1.2<14>[ 32.367405] [IGT] kms_vblank: exiting, ret=77
13635 12:12:58.819568 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13636 12:12:58.822658 Opened device: /dev/dri/card0
13637 12:12:58.829138 N<8>[ 32.378956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13638 12:12:58.829448 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13640 12:12:58.832480 o KMS driver or no outputs, pipes: 8, outputs: 0
13641 12:12:58.839057 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13642 12:12:58.851566 <14>[ 32.404430] [IGT] kms_vblank: executing
13643 12:12:58.858179 IGT-Version: 1.2<14>[ 32.409455] [IGT] kms_vblank: exiting, ret=77
13644 12:12:58.861664 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13645 12:12:58.864662 Opened device: /dev/dri/card0
13646 12:12:58.871635 N<8>[ 32.420793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13647 12:12:58.871962 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13649 12:12:58.874586 o KMS driver or no outputs, pipes: 8, outputs: 0
13650 12:12:58.881513 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13651 12:12:58.893797 <14>[ 32.446476] [IGT] kms_vblank: executing
13652 12:12:58.900285 IGT-Version: 1.2<14>[ 32.451498] [IGT] kms_vblank: exiting, ret=77
13653 12:12:58.903536 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13654 12:12:58.906952 Opened device: /dev/dri/card0
13655 12:12:58.913620 N<8>[ 32.463063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13656 12:12:58.913955 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13658 12:12:58.916634 o KMS driver or no outputs, pipes: 8, outputs: 0
13659 12:12:58.923708 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13660 12:12:58.936000 <14>[ 32.488748] [IGT] kms_vblank: executing
13661 12:12:58.942550 IGT-Version: 1.2<14>[ 32.493784] [IGT] kms_vblank: exiting, ret=77
13662 12:12:58.946208 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13663 12:12:58.949260 Opened device: /dev/dri/card0
13664 12:12:58.955792 N<8>[ 32.505128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13665 12:12:58.956098 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13667 12:12:58.962264 o KMS driver or no outputs, pipes: 8, outputs: 0
13668 12:12:58.965727 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13669 12:12:58.979132 <14>[ 32.531736] [IGT] kms_vblank: executing
13670 12:12:58.985570 IGT-Version: 1.2<14>[ 32.536871] [IGT] kms_vblank: exiting, ret=77
13671 12:12:58.988735 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13672 12:12:58.991987 Opened device: /dev/dri/card0
13673 12:12:58.998709 N<8>[ 32.548271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13674 12:12:58.999012 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13676 12:12:59.005166 o KMS driver or no outputs, pipes: 8, outputs: 0
13677 12:12:59.008307 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13678 12:12:59.021679 <14>[ 32.574594] [IGT] kms_vblank: executing
13679 12:12:59.028281 IGT-Version: 1.2<14>[ 32.579574] [IGT] kms_vblank: exiting, ret=77
13680 12:12:59.031782 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13681 12:12:59.035259 Opened device: /dev/dri/card0
13682 12:12:59.041662 N<8>[ 32.591047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13683 12:12:59.041957 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13685 12:12:59.048129 o KMS driver or no outputs, pipes: 8, outputs: 0
13686 12:12:59.051576 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13687 12:12:59.065208 <14>[ 32.617773] [IGT] kms_vblank: executing
13688 12:12:59.071701 IGT-Version: 1.2<14>[ 32.622830] [IGT] kms_vblank: exiting, ret=77
13689 12:12:59.075020 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13690 12:12:59.078113 Opened device: /dev/dri/card0
13691 12:12:59.084525 N<8>[ 32.634030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13692 12:12:59.084852 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13694 12:12:59.091204 o KMS driver or no outputs, pipes: 8, outputs: 0
13695 12:12:59.094478 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13696 12:12:59.108136 <14>[ 32.660877] [IGT] kms_vblank: executing
13697 12:12:59.114906 IGT-Version: 1.2<14>[ 32.665938] [IGT] kms_vblank: exiting, ret=77
13698 12:12:59.118152 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13699 12:12:59.121555 Opened device: /dev/dri/card0
13700 12:12:59.127981 N<8>[ 32.677357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13701 12:12:59.128293 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13703 12:12:59.134464 o KMS driver or no outputs, pipes: 8, outputs: 0
13704 12:12:59.141029 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13705 12:12:59.151842 <14>[ 32.704434] [IGT] kms_vblank: executing
13706 12:12:59.158200 IGT-Version: 1.2<14>[ 32.709518] [IGT] kms_vblank: exiting, ret=77
13707 12:12:59.161691 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13708 12:12:59.164686 Opened device: /dev/dri/card0
13709 12:12:59.171734 N<8>[ 32.721249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13710 12:12:59.172029 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13712 12:12:59.178134 o KMS driver or no outputs, pipes: 8, outputs: 0
13713 12:12:59.181522 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13714 12:12:59.196094 <14>[ 32.748822] [IGT] kms_vblank: executing
13715 12:12:59.202605 IGT-Version: 1.2<14>[ 32.753799] [IGT] kms_vblank: exiting, ret=77
13716 12:12:59.205933 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13717 12:12:59.209289 Opened device: /dev/dri/card0
13718 12:12:59.215830 N<8>[ 32.766033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13719 12:12:59.216133 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13721 12:12:59.222288 o KMS driver or no outputs, pipes: 8, outputs: 0
13722 12:12:59.225547 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13723 12:12:59.240245 <14>[ 32.793271] [IGT] kms_vblank: executing
13724 12:12:59.247097 IGT-Version: 1.2<14>[ 32.798278] [IGT] kms_vblank: exiting, ret=77
13725 12:12:59.250559 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13726 12:12:59.253604 Opened device: /dev/dri/card0
13727 12:12:59.260207 N<8>[ 32.810395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13728 12:12:59.260501 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13730 12:12:59.266706 o KMS driver or no outputs, pipes: 8, outputs: 0
13731 12:12:59.273368 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13732 12:12:59.285196 <14>[ 32.838066] [IGT] kms_vblank: executing
13733 12:12:59.291700 IGT-Version: 1.2<14>[ 32.843395] [IGT] kms_vblank: exiting, ret=77
13734 12:12:59.295210 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13735 12:12:59.298659 Opened device: /dev/dri/card0
13736 12:12:59.305020 N<8>[ 32.854837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13737 12:12:59.305320 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13739 12:12:59.311751 o KMS driver or no outputs, pipes: 8, outputs: 0
13740 12:12:59.318084 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13741 12:12:59.328819 <14>[ 32.881780] [IGT] kms_vblank: executing
13742 12:12:59.335454 IGT-Version: 1.2<14>[ 32.886880] [IGT] kms_vblank: exiting, ret=77
13743 12:12:59.338643 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13744 12:12:59.342076 Opened device: /dev/dri/card0
13745 12:12:59.348581 N<8>[ 32.898111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13746 12:12:59.348912 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13748 12:12:59.351930 o KMS driver or no outputs, pipes: 8, outputs: 0
13749 12:12:59.358366 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13750 12:12:59.371291 <14>[ 32.924029] [IGT] kms_vblank: executing
13751 12:12:59.377830 IGT-Version: 1.2<14>[ 32.929160] [IGT] kms_vblank: exiting, ret=77
13752 12:12:59.380875 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13753 12:12:59.384473 Opened device: /dev/dri/card0
13754 12:12:59.391080 N<8>[ 32.940527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13755 12:12:59.391405 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13757 12:12:59.394095 o KMS driver or no outputs, pipes: 8, outputs: 0
13758 12:12:59.400668 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13759 12:12:59.413339 <14>[ 32.965957] [IGT] kms_vblank: executing
13760 12:12:59.419737 IGT-Version: 1.2<14>[ 32.971155] [IGT] kms_vblank: exiting, ret=77
13761 12:12:59.423201 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13762 12:12:59.426155 Opened device: /dev/dri/card0
13763 12:12:59.432983 N<8>[ 32.982486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13764 12:12:59.433313 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13766 12:12:59.436313 o KMS driver or no outputs, pipes: 8, outputs: 0
13767 12:12:59.442706 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13768 12:12:59.455678 <14>[ 33.008458] [IGT] kms_vblank: executing
13769 12:12:59.462269 IGT-Version: 1.2<14>[ 33.013440] [IGT] kms_vblank: exiting, ret=77
13770 12:12:59.465357 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13771 12:12:59.468941 Opened device: /dev/dri/card0
13772 12:12:59.475352 N<8>[ 33.024892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13773 12:12:59.475685 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13775 12:12:59.478882 o KMS driver or no outputs, pipes: 8, outputs: 0
13776 12:12:59.485372 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13777 12:12:59.497922 <14>[ 33.050707] [IGT] kms_vblank: executing
13778 12:12:59.504562 IGT-Version: 1.2<14>[ 33.055816] [IGT] kms_vblank: exiting, ret=77
13779 12:12:59.507534 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13780 12:12:59.511078 Opened device: /dev/dri/card0
13781 12:12:59.517785 N<8>[ 33.067359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13782 12:12:59.518128 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13784 12:12:59.524369 o KMS driver or no outputs, pipes: 8, outputs: 0
13785 12:12:59.527338 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13786 12:12:59.540531 <14>[ 33.093267] [IGT] kms_vblank: executing
13787 12:12:59.546982 IGT-Version: 1.2<14>[ 33.098265] [IGT] kms_vblank: exiting, ret=77
13788 12:12:59.550552 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13789 12:12:59.553795 Opened device: /dev/dri/card0
13790 12:12:59.560363 N<8>[ 33.109827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13791 12:12:59.560710 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13793 12:12:59.563824 o KMS driver or no outputs, pipes: 8, outputs: 0
13794 12:12:59.569917 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13795 12:12:59.582668 <14>[ 33.135346] [IGT] kms_vblank: executing
13796 12:12:59.589205 IGT-Version: 1.2<14>[ 33.140329] [IGT] kms_vblank: exiting, ret=77
13797 12:12:59.592204 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13798 12:12:59.595682 Opened device: /dev/dri/card0
13799 12:12:59.602168 N<8>[ 33.151712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13800 12:12:59.602490 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13802 12:12:59.605800 o KMS driver or no outputs, pipes: 8, outputs: 0
13803 12:12:59.612295 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13804 12:12:59.624937 <14>[ 33.177744] [IGT] kms_vblank: executing
13805 12:12:59.631324 IGT-Version: 1.2<14>[ 33.182786] [IGT] kms_vblank: exiting, ret=77
13806 12:12:59.634475 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13807 12:12:59.637939 Opened device: /dev/dri/card0
13808 12:12:59.644482 N<8>[ 33.193817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13809 12:12:59.644796 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13811 12:12:59.651263 o KMS driver or no outputs, pipes: 8, outputs: 0
13812 12:12:59.654535 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13813 12:12:59.668790 <14>[ 33.221396] [IGT] kms_vblank: executing
13814 12:12:59.675263 IGT-Version: 1.2<14>[ 33.226617] [IGT] kms_vblank: exiting, ret=77
13815 12:12:59.678713 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13816 12:12:59.681690 Opened device: /dev/dri/card0
13817 12:12:59.688312 N<8>[ 33.237852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13818 12:12:59.688608 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13820 12:12:59.694839 o KMS driver or no outputs, pipes: 8, outputs: 0
13821 12:12:59.698292 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13822 12:12:59.712127 <14>[ 33.264735] [IGT] kms_vblank: executing
13823 12:12:59.718515 IGT-Version: 1.2<14>[ 33.269772] [IGT] kms_vblank: exiting, ret=77
13824 12:12:59.721535 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13825 12:12:59.725065 Opened device: /dev/dri/card0
13826 12:12:59.731618 N<8>[ 33.281070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13827 12:12:59.731887 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13829 12:12:59.735181 o KMS driver or no outputs, pipes: 8, outputs: 0
13830 12:12:59.741598 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13831 12:12:59.754470 <14>[ 33.307135] [IGT] kms_vblank: executing
13832 12:12:59.761087 IGT-Version: 1.2<14>[ 33.312126] [IGT] kms_vblank: exiting, ret=77
13833 12:12:59.764241 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13834 12:12:59.767510 Opened device: /dev/dri/card0
13835 12:12:59.774044 N<8>[ 33.323765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13836 12:12:59.774305 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13838 12:12:59.777213 o KMS driver or no outputs, pipes: 8, outputs: 0
13839 12:12:59.784121 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13840 12:12:59.797834 <14>[ 33.350792] [IGT] kms_vblank: executing
13841 12:12:59.804707 IGT-Version: 1.2<14>[ 33.355895] [IGT] kms_vblank: exiting, ret=77
13842 12:12:59.807766 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13843 12:12:59.811321 Opened device: /dev/dri/card0
13844 12:12:59.817822 N<8>[ 33.368004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13845 12:12:59.818077 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13847 12:12:59.821262 o KMS driver or no outputs, pipes: 8, outputs: 0
13848 12:12:59.827640 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13849 12:12:59.840672 <14>[ 33.393334] [IGT] kms_vblank: executing
13850 12:12:59.847043 IGT-Version: 1.2<14>[ 33.398421] [IGT] kms_vblank: exiting, ret=77
13851 12:12:59.850363 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13852 12:12:59.853966 Opened device: /dev/dri/card0
13853 12:12:59.860472 N<8>[ 33.409999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13854 12:12:59.860729 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13856 12:12:59.863539 o KMS driver or no outputs, pipes: 8, outputs: 0
13857 12:12:59.870126 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13858 12:12:59.884584 <14>[ 33.437082] [IGT] kms_vblank: executing
13859 12:12:59.890773 IGT-Version: 1.2<14>[ 33.442157] [IGT] kms_vblank: exiting, ret=77
13860 12:12:59.894300 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13861 12:12:59.897307 Opened device: /dev/dri/card0
13862 12:12:59.903844 N<8>[ 33.453926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13863 12:12:59.904142 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13865 12:12:59.907348 o KMS driver or no outputs, pipes: 8, outputs: 0
13866 12:12:59.913757 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13867 12:12:59.926225 <14>[ 33.479156] [IGT] kms_vblank: executing
13868 12:12:59.933237 IGT-Version: 1.2<14>[ 33.484263] [IGT] kms_vblank: exiting, ret=77
13869 12:12:59.936060 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13870 12:12:59.939632 Opened device: /dev/dri/card0
13871 12:12:59.946377 N<8>[ 33.495733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13872 12:12:59.946650 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13874 12:12:59.949372 o KMS driver or no outputs, pipes: 8, outputs: 0
13875 12:12:59.956203 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13876 12:12:59.968180 <14>[ 33.521279] [IGT] kms_vblank: executing
13877 12:12:59.975003 IGT-Version: 1.2<14>[ 33.526347] [IGT] kms_vblank: exiting, ret=77
13878 12:12:59.978194 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13879 12:12:59.981436 Opened device: /dev/dri/card0
13880 12:12:59.987993 N<8>[ 33.538195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13881 12:12:59.988306 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13883 12:12:59.994626 o KMS driver or no outputs, pipes: 8, outputs: 0
13884 12:12:59.997611 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13885 12:13:00.012170 <14>[ 33.564958] [IGT] kms_vblank: executing
13886 12:13:00.018797 IGT-Version: 1.2<14>[ 33.569917] [IGT] kms_vblank: exiting, ret=77
13887 12:13:00.022063 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13888 12:13:00.025193 Opened device: /dev/dri/card0
13889 12:13:00.031646 N<8>[ 33.582038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13890 12:13:00.031939 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13892 12:13:00.038397 o KMS driver or no outputs, pipes: 8, outputs: 0
13893 12:13:00.041877 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13894 12:13:00.055019 <14>[ 33.608102] [IGT] kms_vblank: executing
13895 12:13:00.061844 IGT-Version: 1.2<14>[ 33.613099] [IGT] kms_vblank: exiting, ret=77
13896 12:13:00.064885 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13897 12:13:00.068477 Opened device: /dev/dri/card0
13898 12:13:00.074968 N<8>[ 33.625020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13899 12:13:00.075227 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13901 12:13:00.081283 o KMS driver or no outputs, pipes: 8, outputs: 0
13902 12:13:00.084690 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13903 12:13:00.099079 <14>[ 33.652017] [IGT] kms_vblank: executing
13904 12:13:00.105804 IGT-Version: 1.2<14>[ 33.656998] [IGT] kms_vblank: exiting, ret=77
13905 12:13:00.108957 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13906 12:13:00.112456 Opened device: /dev/dri/card0
13907 12:13:00.118975 N<8>[ 33.669173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13908 12:13:00.119281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13910 12:13:00.125399 o KMS driver or no outputs, pipes: 8, outputs: 0
13911 12:13:00.128855 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13912 12:13:00.142258 <14>[ 33.695116] [IGT] kms_vblank: executing
13913 12:13:00.148682 IGT-Version: 1.2<14>[ 33.700148] [IGT] kms_vblank: exiting, ret=77
13914 12:13:00.152158 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13915 12:13:00.155231 Opened device: /dev/dri/card0
13916 12:13:00.162143 N<8>[ 33.711922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13917 12:13:00.162407 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13919 12:13:00.168552 o KMS driver or no outputs, pipes: 8, outputs: 0
13920 12:13:00.172066 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13921 12:13:00.185527 <14>[ 33.738573] [IGT] kms_vblank: executing
13922 12:13:00.192426 IGT-Version: 1.2<14>[ 33.743556] [IGT] kms_vblank: exiting, ret=77
13923 12:13:00.195577 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13924 12:13:00.198785 Opened device: /dev/dri/card0
13925 12:13:00.205506 N<8>[ 33.755429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13926 12:13:00.205830 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13928 12:13:00.212135 o KMS driver or no outputs, pipes: 8, outputs: 0
13929 12:13:00.218720 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13930 12:13:00.228981 <14>[ 33.782139] [IGT] kms_vblank: executing
13931 12:13:00.235978 IGT-Version: 1.2<14>[ 33.787462] [IGT] kms_vblank: exiting, ret=77
13932 12:13:00.238957 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13933 12:13:00.242562 Opened device: /dev/dri/card0
13934 12:13:00.248878 N<8>[ 33.799101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13935 12:13:00.249135 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13937 12:13:00.255960 o KMS driver or no outputs, pipes: 8, outputs: 0
13938 12:13:00.258938 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13939 12:13:00.272207 <14>[ 33.825321] [IGT] kms_vblank: executing
13940 12:13:00.279181 IGT-Version: 1.2<14>[ 33.830337] [IGT] kms_vblank: exiting, ret=77
13941 12:13:00.282243 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13942 12:13:00.285917 Opened device: /dev/dri/card0
13943 12:13:00.292335 N<8>[ 33.842227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13944 12:13:00.292622 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13946 12:13:00.298970 o KMS driver or no outputs, pipes: 8, outputs: 0
13947 12:13:00.301915 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13948 12:13:00.316599 <14>[ 33.869709] [IGT] kms_vblank: executing
13949 12:13:00.323530 IGT-Version: 1.2<14>[ 33.874907] [IGT] kms_vblank: exiting, ret=77
13950 12:13:00.327038 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13951 12:13:00.330242 Opened device: /dev/dri/card0
13952 12:13:00.336685 N<8>[ 33.886450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13953 12:13:00.337006 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13955 12:13:00.343460 o KMS driver or no outputs, pipes: 8, outputs: 0
13956 12:13:00.349928 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13957 12:13:00.361902 <14>[ 33.914662] [IGT] kms_vblank: executing
13958 12:13:00.368348 IGT-Version: 1.2<14>[ 33.919699] [IGT] kms_vblank: exiting, ret=77
13959 12:13:00.371593 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13960 12:13:00.375107 Opened device: /dev/dri/card0
13961 12:13:00.381356 N<8>[ 33.931483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13962 12:13:00.381651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13964 12:13:00.388358 o KMS driver or no outputs, pipe<8>[ 33.942638] <LAVA_SIGNAL_TESTSET STOP>
13965 12:13:00.388652 Received signal: <TESTSET> STOP
13966 12:13:00.388754 Closing test_set kms_vblank
13967 12:13:00.398197 s: 8, outputs: 0<8>[ 33.948412] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 10605395_1.5.2.3.1>
13968 12:13:00.398323
13969 12:13:00.398599 Received signal: <ENDRUN> 0_igt-kms-mediatek 10605395_1.5.2.3.1
13970 12:13:00.398722 Ending use of test pattern.
13971 12:13:00.398826 Ending test lava.0_igt-kms-mediatek (10605395_1.5.2.3.1), duration 13.58
13973 12:13:00.404642 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13974 12:13:00.404750 + set +x
13975 12:13:00.408131 <LAVA_TEST_RUNNER EXIT>
13976 12:13:00.408409 ok: lava_test_shell seems to have completed
13977 12:13:00.417148 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13978 12:13:00.417439 end: 3.1 lava-test-shell (duration 00:00:14) [common]
13979 12:13:00.417548 end: 3 lava-test-retry (duration 00:00:14) [common]
13980 12:13:00.417680 start: 4 finalize (timeout 00:07:43) [common]
13981 12:13:00.417812 start: 4.1 power-off (timeout 00:00:30) [common]
13982 12:13:00.418111 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
13983 12:13:00.492740 >> Command sent successfully.
13984 12:13:00.495091 Returned 0 in 0 seconds
13985 12:13:00.595502 end: 4.1 power-off (duration 00:00:00) [common]
13987 12:13:00.595963 start: 4.2 read-feedback (timeout 00:07:43) [common]
13988 12:13:00.596261 Listened to connection for namespace 'common' for up to 1s
13989 12:13:01.596865 Finalising connection for namespace 'common'
13990 12:13:01.597218 Disconnecting from shell: Finalise
13991 12:13:01.597340 / #
13992 12:13:01.697703 end: 4.2 read-feedback (duration 00:00:01) [common]
13993 12:13:01.697898 end: 4 finalize (duration 00:00:01) [common]
13994 12:13:01.698047 Cleaning after the job
13995 12:13:01.698167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/ramdisk
13996 12:13:01.704113 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/kernel
13997 12:13:01.709981 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/dtb
13998 12:13:01.710226 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605395/tftp-deploy-6cskc8xc/modules
13999 12:13:01.715590 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605395
14000 12:13:01.822271 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605395
14001 12:13:01.822490 Job finished correctly