Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
1 12:10:18.134586 lava-dispatcher, installed at version: 2023.05.1
2 12:10:18.134876 start: 0 validate
3 12:10:18.135077 Start time: 2023-06-06 12:10:18.135062+00:00 (UTC)
4 12:10:18.135265 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:10:18.135477 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:10:18.429262 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:10:18.429521 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:10:18.723559 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:10:18.723816 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:10:38.632424 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:10:38.632600 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:10:39.204254 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:10:39.204413 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:10:39.529430 validate duration: 21.39
16 12:10:39.529693 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:10:39.529830 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:10:39.529956 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:10:39.530097 Not decompressing ramdisk as can be used compressed.
20 12:10:39.530183 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 12:10:39.530248 saving as /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/ramdisk/initrd.cpio.gz
22 12:10:39.530312 total size: 4665601 (4MB)
23 12:10:42.502902 progress 0% (0MB)
24 12:10:42.504656 progress 5% (0MB)
25 12:10:42.505968 progress 10% (0MB)
26 12:10:42.507387 progress 15% (0MB)
27 12:10:42.508657 progress 20% (0MB)
28 12:10:42.509908 progress 25% (1MB)
29 12:10:42.511192 progress 30% (1MB)
30 12:10:42.512451 progress 35% (1MB)
31 12:10:42.513850 progress 40% (1MB)
32 12:10:42.515451 progress 45% (2MB)
33 12:10:42.516842 progress 50% (2MB)
34 12:10:42.518262 progress 55% (2MB)
35 12:10:42.519667 progress 60% (2MB)
36 12:10:42.521088 progress 65% (2MB)
37 12:10:42.522452 progress 70% (3MB)
38 12:10:42.523852 progress 75% (3MB)
39 12:10:42.525257 progress 80% (3MB)
40 12:10:42.526800 progress 85% (3MB)
41 12:10:42.528197 progress 90% (4MB)
42 12:10:42.529581 progress 95% (4MB)
43 12:10:42.530932 progress 100% (4MB)
44 12:10:42.531124 4MB downloaded in 3.00s (1.48MB/s)
45 12:10:42.531274 end: 1.1.1 http-download (duration 00:00:03) [common]
47 12:10:42.531515 end: 1.1 download-retry (duration 00:00:03) [common]
48 12:10:42.531601 start: 1.2 download-retry (timeout 00:09:57) [common]
49 12:10:42.531687 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 12:10:42.531822 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:10:42.531894 saving as /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/kernel/Image
52 12:10:42.531956 total size: 45746688 (43MB)
53 12:10:42.532017 No compression specified
54 12:10:42.533150 progress 0% (0MB)
55 12:10:42.545520 progress 5% (2MB)
56 12:10:42.557242 progress 10% (4MB)
57 12:10:42.568974 progress 15% (6MB)
58 12:10:42.580682 progress 20% (8MB)
59 12:10:42.592441 progress 25% (10MB)
60 12:10:42.604097 progress 30% (13MB)
61 12:10:42.615843 progress 35% (15MB)
62 12:10:42.627619 progress 40% (17MB)
63 12:10:42.639303 progress 45% (19MB)
64 12:10:42.651047 progress 50% (21MB)
65 12:10:42.662568 progress 55% (24MB)
66 12:10:42.674318 progress 60% (26MB)
67 12:10:42.685981 progress 65% (28MB)
68 12:10:42.697688 progress 70% (30MB)
69 12:10:42.709482 progress 75% (32MB)
70 12:10:42.720955 progress 80% (34MB)
71 12:10:42.732654 progress 85% (37MB)
72 12:10:42.744326 progress 90% (39MB)
73 12:10:42.755871 progress 95% (41MB)
74 12:10:42.767323 progress 100% (43MB)
75 12:10:42.767468 43MB downloaded in 0.24s (185.25MB/s)
76 12:10:42.767622 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:10:42.767868 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:10:42.767962 start: 1.3 download-retry (timeout 00:09:57) [common]
80 12:10:42.768053 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 12:10:42.768189 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:10:42.768260 saving as /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/dtb/mt8192-asurada-spherion-r0.dtb
83 12:10:42.768325 total size: 46924 (0MB)
84 12:10:42.768386 No compression specified
85 12:10:42.769534 progress 69% (0MB)
86 12:10:42.769810 progress 100% (0MB)
87 12:10:42.769965 0MB downloaded in 0.00s (27.33MB/s)
88 12:10:42.770087 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:10:42.770314 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:10:42.770401 start: 1.4 download-retry (timeout 00:09:57) [common]
92 12:10:42.770485 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 12:10:42.770596 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 12:10:42.770665 saving as /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/nfsrootfs/full.rootfs.tar
95 12:10:42.770726 total size: 200770336 (191MB)
96 12:10:42.770787 Using unxz to decompress xz
97 12:10:42.774349 progress 0% (0MB)
98 12:10:43.323197 progress 5% (9MB)
99 12:10:43.864819 progress 10% (19MB)
100 12:10:44.465043 progress 15% (28MB)
101 12:10:44.836646 progress 20% (38MB)
102 12:10:45.164223 progress 25% (47MB)
103 12:10:45.764867 progress 30% (57MB)
104 12:10:46.327875 progress 35% (67MB)
105 12:10:46.942493 progress 40% (76MB)
106 12:10:47.535617 progress 45% (86MB)
107 12:10:48.140453 progress 50% (95MB)
108 12:10:48.784527 progress 55% (105MB)
109 12:10:49.522803 progress 60% (114MB)
110 12:10:49.645897 progress 65% (124MB)
111 12:10:49.790273 progress 70% (134MB)
112 12:10:49.891554 progress 75% (143MB)
113 12:10:49.969760 progress 80% (153MB)
114 12:10:50.043882 progress 85% (162MB)
115 12:10:50.144671 progress 90% (172MB)
116 12:10:50.431312 progress 95% (181MB)
117 12:10:51.040268 progress 100% (191MB)
118 12:10:51.045684 191MB downloaded in 8.27s (23.14MB/s)
119 12:10:51.046006 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:10:51.046294 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:10:51.046389 start: 1.5 download-retry (timeout 00:09:48) [common]
123 12:10:51.046479 start: 1.5.1 http-download (timeout 00:09:48) [common]
124 12:10:51.046640 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:10:51.046743 saving as /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/modules/modules.tar
126 12:10:51.046845 total size: 8553528 (8MB)
127 12:10:51.046945 Using unxz to decompress xz
128 12:10:51.346055 progress 0% (0MB)
129 12:10:51.368459 progress 5% (0MB)
130 12:10:51.393227 progress 10% (0MB)
131 12:10:51.426052 progress 15% (1MB)
132 12:10:51.452504 progress 20% (1MB)
133 12:10:51.478629 progress 25% (2MB)
134 12:10:51.504324 progress 30% (2MB)
135 12:10:51.531464 progress 35% (2MB)
136 12:10:51.557140 progress 40% (3MB)
137 12:10:51.583173 progress 45% (3MB)
138 12:10:51.610139 progress 50% (4MB)
139 12:10:51.636310 progress 55% (4MB)
140 12:10:51.663229 progress 60% (4MB)
141 12:10:51.688938 progress 65% (5MB)
142 12:10:51.715796 progress 70% (5MB)
143 12:10:51.741851 progress 75% (6MB)
144 12:10:51.769843 progress 80% (6MB)
145 12:10:51.796137 progress 85% (6MB)
146 12:10:51.822817 progress 90% (7MB)
147 12:10:51.847673 progress 95% (7MB)
148 12:10:51.875045 progress 100% (8MB)
149 12:10:51.880015 8MB downloaded in 0.83s (9.79MB/s)
150 12:10:51.880352 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:10:51.880624 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:10:51.880718 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 12:10:51.880845 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 12:10:55.286830 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9
156 12:10:55.287060 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:10:55.287165 start: 1.6.2 lava-overlay (timeout 00:09:44) [common]
158 12:10:55.287336 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx
159 12:10:55.287476 makedir: /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin
160 12:10:55.287614 makedir: /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/tests
161 12:10:55.287753 makedir: /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/results
162 12:10:55.287887 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-add-keys
163 12:10:55.288029 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-add-sources
164 12:10:55.288168 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-background-process-start
165 12:10:55.288338 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-background-process-stop
166 12:10:55.288502 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-common-functions
167 12:10:55.288663 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-echo-ipv4
168 12:10:55.288827 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-install-packages
169 12:10:55.288975 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-installed-packages
170 12:10:55.289097 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-os-build
171 12:10:55.289219 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-probe-channel
172 12:10:55.289339 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-probe-ip
173 12:10:55.289471 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-target-ip
174 12:10:55.289634 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-target-mac
175 12:10:55.289791 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-target-storage
176 12:10:55.289954 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-case
177 12:10:55.290121 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-event
178 12:10:55.290286 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-feedback
179 12:10:55.290414 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-raise
180 12:10:55.290542 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-reference
181 12:10:55.290676 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-runner
182 12:10:55.290845 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-set
183 12:10:55.290975 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-test-shell
184 12:10:55.291100 Updating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-add-keys (debian)
185 12:10:55.291248 Updating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-add-sources (debian)
186 12:10:55.291414 Updating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-install-packages (debian)
187 12:10:55.291595 Updating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-installed-packages (debian)
188 12:10:55.291773 Updating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/bin/lava-os-build (debian)
189 12:10:55.291895 Creating /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/environment
190 12:10:55.292033 LAVA metadata
191 12:10:55.292134 - LAVA_JOB_ID=10605382
192 12:10:55.292201 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:10:55.292304 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:44) [common]
194 12:10:55.292371 skipped lava-vland-overlay
195 12:10:55.292447 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:10:55.292536 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
197 12:10:55.292628 skipped lava-multinode-overlay
198 12:10:55.292738 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:10:55.292822 start: 1.6.2.3 test-definition (timeout 00:09:44) [common]
200 12:10:55.292900 Loading test definitions
201 12:10:55.292991 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:44) [common]
202 12:10:55.293064 Using /lava-10605382 at stage 0
203 12:10:55.293394 uuid=10605382_1.6.2.3.1 testdef=None
204 12:10:55.293484 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:10:55.293570 start: 1.6.2.3.2 test-overlay (timeout 00:09:44) [common]
206 12:10:55.294011 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:10:55.294370 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:44) [common]
209 12:10:55.295179 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:10:55.295563 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
212 12:10:55.296172 runner path: /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/0/tests/0_timesync-off test_uuid 10605382_1.6.2.3.1
213 12:10:55.296340 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:10:55.296716 start: 1.6.2.3.5 git-repo-action (timeout 00:09:44) [common]
216 12:10:55.296823 Using /lava-10605382 at stage 0
217 12:10:55.296969 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:10:55.297071 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/0/tests/1_kselftest-arm64'
219 12:11:09.189012 Running '/usr/bin/git checkout kernelci.org
220 12:11:09.964046 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 12:11:09.964751 uuid=10605382_1.6.2.3.5 testdef=None
222 12:11:09.964912 end: 1.6.2.3.5 git-repo-action (duration 00:00:15) [common]
224 12:11:09.965161 start: 1.6.2.3.6 test-overlay (timeout 00:09:30) [common]
225 12:11:09.978537 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:11:09.979030 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:30) [common]
228 12:11:09.980246 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:11:09.980538 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:30) [common]
231 12:11:10.025302 runner path: /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/0/tests/1_kselftest-arm64 test_uuid 10605382_1.6.2.3.5
232 12:11:10.025422 BOARD='mt8192-asurada-spherion-r0'
233 12:11:10.025490 BRANCH='cip-gitlab'
234 12:11:10.025551 SKIPFILE='/dev/null'
235 12:11:10.025610 SKIP_INSTALL='True'
236 12:11:10.025667 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:11:10.025725 TST_CASENAME=''
238 12:11:10.025780 TST_CMDFILES='arm64'
239 12:11:10.025940 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:11:10.026151 Creating lava-test-runner.conf files
242 12:11:10.026219 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605382/lava-overlay-_u930eyx/lava-10605382/0 for stage 0
243 12:11:10.026330 - 0_timesync-off
244 12:11:10.026431 - 1_kselftest-arm64
245 12:11:10.026585 end: 1.6.2.3 test-definition (duration 00:00:15) [common]
246 12:11:10.026691 start: 1.6.2.4 compress-overlay (timeout 00:09:30) [common]
247 12:11:18.322229 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:11:18.322427 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:21) [common]
249 12:11:18.322550 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:11:18.322689 end: 1.6.2 lava-overlay (duration 00:00:23) [common]
251 12:11:18.322814 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:21) [common]
252 12:11:18.438790 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:11:18.439220 start: 1.6.4 extract-modules (timeout 00:09:21) [common]
254 12:11:18.439364 extracting modules file /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9
255 12:11:18.722905 extracting modules file /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605382/extract-overlay-ramdisk-xsak8_aw/ramdisk
256 12:11:18.981006 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 12:11:18.981209 start: 1.6.5 apply-overlay-tftp (timeout 00:09:21) [common]
258 12:11:18.981341 [common] Applying overlay to NFS
259 12:11:18.981444 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605382/compress-overlay-4w_j_btq/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9
260 12:11:20.072677 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:11:20.072851 start: 1.6.6 configure-preseed-file (timeout 00:09:19) [common]
262 12:11:20.072959 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:11:20.073057 start: 1.6.7 compress-ramdisk (timeout 00:09:19) [common]
264 12:11:20.073141 Building ramdisk /var/lib/lava/dispatcher/tmp/10605382/extract-overlay-ramdisk-xsak8_aw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605382/extract-overlay-ramdisk-xsak8_aw/ramdisk
265 12:11:20.350036 >> 117807 blocks
266 12:11:22.364856 rename /var/lib/lava/dispatcher/tmp/10605382/extract-overlay-ramdisk-xsak8_aw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/ramdisk/ramdisk.cpio.gz
267 12:11:22.365324 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:11:22.365479 start: 1.6.8 prepare-kernel (timeout 00:09:17) [common]
269 12:11:22.365633 start: 1.6.8.1 prepare-fit (timeout 00:09:17) [common]
270 12:11:22.365789 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/kernel/Image'
271 12:11:35.266284 Returned 0 in 12 seconds
272 12:11:35.366885 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/kernel/image.itb
273 12:11:35.697382 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:11:35.697725 output: Created: Tue Jun 6 13:11:35 2023
275 12:11:35.697798 output: Image 0 (kernel-1)
276 12:11:35.697866 output: Description:
277 12:11:35.697930 output: Created: Tue Jun 6 13:11:35 2023
278 12:11:35.697993 output: Type: Kernel Image
279 12:11:35.698056 output: Compression: lzma compressed
280 12:11:35.698114 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
281 12:11:35.698177 output: Architecture: AArch64
282 12:11:35.698239 output: OS: Linux
283 12:11:35.698298 output: Load Address: 0x00000000
284 12:11:35.698357 output: Entry Point: 0x00000000
285 12:11:35.698416 output: Hash algo: crc32
286 12:11:35.698472 output: Hash value: fd97082e
287 12:11:35.698525 output: Image 1 (fdt-1)
288 12:11:35.698579 output: Description: mt8192-asurada-spherion-r0
289 12:11:35.698633 output: Created: Tue Jun 6 13:11:35 2023
290 12:11:35.698687 output: Type: Flat Device Tree
291 12:11:35.698740 output: Compression: uncompressed
292 12:11:35.698794 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 12:11:35.698886 output: Architecture: AArch64
294 12:11:35.698942 output: Hash algo: crc32
295 12:11:35.698995 output: Hash value: 1df858fa
296 12:11:35.699049 output: Image 2 (ramdisk-1)
297 12:11:35.699103 output: Description: unavailable
298 12:11:35.699158 output: Created: Tue Jun 6 13:11:35 2023
299 12:11:35.699212 output: Type: RAMDisk Image
300 12:11:35.699266 output: Compression: Unknown Compression
301 12:11:35.699319 output: Data Size: 17643444 Bytes = 17229.93 KiB = 16.83 MiB
302 12:11:35.699441 output: Architecture: AArch64
303 12:11:35.699523 output: OS: Linux
304 12:11:35.699576 output: Load Address: unavailable
305 12:11:35.699629 output: Entry Point: unavailable
306 12:11:35.699682 output: Hash algo: crc32
307 12:11:35.699735 output: Hash value: 154ee90d
308 12:11:35.699789 output: Default Configuration: 'conf-1'
309 12:11:35.699843 output: Configuration 0 (conf-1)
310 12:11:35.699896 output: Description: mt8192-asurada-spherion-r0
311 12:11:35.699949 output: Kernel: kernel-1
312 12:11:35.700002 output: Init Ramdisk: ramdisk-1
313 12:11:35.700056 output: FDT: fdt-1
314 12:11:35.700109 output: Loadables: kernel-1
315 12:11:35.700163 output:
316 12:11:35.700360 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:11:35.700456 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:11:35.700561 end: 1.6 prepare-tftp-overlay (duration 00:00:44) [common]
319 12:11:35.700658 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:04) [common]
320 12:11:35.700744 No LXC device requested
321 12:11:35.700830 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:11:35.700918 start: 1.8 deploy-device-env (timeout 00:09:04) [common]
323 12:11:35.700997 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:11:35.701069 Checking files for TFTP limit of 4294967296 bytes.
325 12:11:35.701556 end: 1 tftp-deploy (duration 00:00:56) [common]
326 12:11:35.701661 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:11:35.701754 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:11:35.701880 substitutions:
329 12:11:35.701950 - {DTB}: 10605382/tftp-deploy-ppbz10u8/dtb/mt8192-asurada-spherion-r0.dtb
330 12:11:35.702017 - {INITRD}: 10605382/tftp-deploy-ppbz10u8/ramdisk/ramdisk.cpio.gz
331 12:11:35.702077 - {KERNEL}: 10605382/tftp-deploy-ppbz10u8/kernel/Image
332 12:11:35.702136 - {LAVA_MAC}: None
333 12:11:35.702193 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9
334 12:11:35.702250 - {NFS_SERVER_IP}: 192.168.201.1
335 12:11:35.702305 - {PRESEED_CONFIG}: None
336 12:11:35.702361 - {PRESEED_LOCAL}: None
337 12:11:35.702416 - {RAMDISK}: 10605382/tftp-deploy-ppbz10u8/ramdisk/ramdisk.cpio.gz
338 12:11:35.702472 - {ROOT_PART}: None
339 12:11:35.702532 - {ROOT}: None
340 12:11:35.702594 - {SERVER_IP}: 192.168.201.1
341 12:11:35.702649 - {TEE}: None
342 12:11:35.702704 Parsed boot commands:
343 12:11:35.702758 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:11:35.702962 Parsed boot commands: tftpboot 192.168.201.1 10605382/tftp-deploy-ppbz10u8/kernel/image.itb 10605382/tftp-deploy-ppbz10u8/kernel/cmdline
345 12:11:35.703057 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:11:35.703146 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:11:35.703265 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:11:35.703365 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:11:35.703470 Not connected, no need to disconnect.
350 12:11:35.703591 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:11:35.703712 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:11:35.703810 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
353 12:11:35.707541 Setting prompt string to ['lava-test: # ']
354 12:11:35.707896 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:11:35.708025 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:11:35.708141 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:11:35.708233 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:11:35.708433 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 12:11:40.842755 >> Command sent successfully.
360 12:11:40.845415 Returned 0 in 5 seconds
361 12:11:40.945827 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:11:40.946293 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:11:40.946435 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:11:40.946576 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:11:40.946687 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:11:40.946803 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:11:40.947205 [Enter `^Ec?' for help]
369 12:11:41.117909
370 12:11:41.118071
371 12:11:41.118146 F0: 102B 0000
372 12:11:41.118212
373 12:11:41.118325 F3: 1001 0000 [0200]
374 12:11:41.120953
375 12:11:41.121066 F3: 1001 0000
376 12:11:41.121178
377 12:11:41.121273 F7: 102D 0000
378 12:11:41.121379
379 12:11:41.123997 F1: 0000 0000
380 12:11:41.124120
381 12:11:41.124219 V0: 0000 0000 [0001]
382 12:11:41.124338
383 12:11:41.127176 00: 0007 8000
384 12:11:41.127302
385 12:11:41.127413 01: 0000 0000
386 12:11:41.127514
387 12:11:41.130855 BP: 0C00 0209 [0000]
388 12:11:41.130972
389 12:11:41.131087 G0: 1182 0000
390 12:11:41.131187
391 12:11:41.134465 EC: 0000 0021 [4000]
392 12:11:41.134583
393 12:11:41.134688 S7: 0000 0000 [0000]
394 12:11:41.134783
395 12:11:41.137563 CC: 0000 0000 [0001]
396 12:11:41.137685
397 12:11:41.137787 T0: 0000 0040 [010F]
398 12:11:41.137885
399 12:11:41.140767 Jump to BL
400 12:11:41.140888
401 12:11:41.164892
402 12:11:41.165074
403 12:11:41.165177
404 12:11:41.171783 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:11:41.174713 ARM64: Exception handlers installed.
406 12:11:41.178448 ARM64: Testing exception
407 12:11:41.181465 ARM64: Done test exception
408 12:11:41.188467 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:11:41.197863 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:11:41.204654 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:11:41.214926 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:11:41.221487 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:11:41.232396 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:11:41.242613 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:11:41.249572 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:11:41.267069 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:11:41.270825 WDT: Last reset was cold boot
418 12:11:41.274021 SPI1(PAD0) initialized at 2873684 Hz
419 12:11:41.277182 SPI5(PAD0) initialized at 992727 Hz
420 12:11:41.280956 VBOOT: Loading verstage.
421 12:11:41.287543 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:11:41.290616 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:11:41.294373 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:11:41.297387 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:11:41.304702 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:11:41.311061 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:11:41.322448 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 12:11:41.322609
429 12:11:41.322720
430 12:11:41.332614 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:11:41.335593 ARM64: Exception handlers installed.
432 12:11:41.339374 ARM64: Testing exception
433 12:11:41.339483 ARM64: Done test exception
434 12:11:41.346634 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:11:41.349723 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:11:41.363558 Probing TPM: . done!
437 12:11:41.363716 TPM ready after 0 ms
438 12:11:41.370471 Connected to device vid:did:rid of 1ae0:0028:00
439 12:11:41.376733 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 12:11:41.419301 Initialized TPM device CR50 revision 0
441 12:11:41.430854 tlcl_send_startup: Startup return code is 0
442 12:11:41.431000 TPM: setup succeeded
443 12:11:41.442192 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:11:41.451458 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:11:41.462648 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:11:41.471948 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:11:41.475707 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:11:41.478792 in-header: 03 07 00 00 08 00 00 00
449 12:11:41.482712 in-data: aa e4 47 04 13 02 00 00
450 12:11:41.486536 Chrome EC: UHEPI supported
451 12:11:41.493322 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:11:41.496940 in-header: 03 9d 00 00 08 00 00 00
453 12:11:41.500132 in-data: 10 20 20 08 00 00 00 00
454 12:11:41.500221 Phase 1
455 12:11:41.503906 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:11:41.510984 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:11:41.517833 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:11:41.517931 Recovery requested (1009000e)
459 12:11:41.526693 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:11:41.531597 tlcl_extend: response is 0
461 12:11:41.539881 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:11:41.545433 tlcl_extend: response is 0
463 12:11:41.551889 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:11:41.572780 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 12:11:41.580193 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:11:41.580291
467 12:11:41.580393
468 12:11:41.590777 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:11:41.590881 ARM64: Exception handlers installed.
470 12:11:41.594530 ARM64: Testing exception
471 12:11:41.597618 ARM64: Done test exception
472 12:11:41.618684 pmic_efuse_setting: Set efuses in 11 msecs
473 12:11:41.622288 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:11:41.625954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:11:41.633261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:11:41.636670 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:11:41.640238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:11:41.647323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:11:41.651027 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:11:41.658009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:11:41.661398 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:11:41.665028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:11:41.671242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:11:41.675012 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:11:41.678140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:11:41.684685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:11:41.691480 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:11:41.694575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:11:41.701444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:11:41.708029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:11:41.714353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:11:41.718031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:11:41.725577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:11:41.729189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:11:41.736376 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:11:41.739409 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:11:41.746566 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:11:41.749852 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:11:41.756513 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:11:41.764152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:11:41.767658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:11:41.770583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:11:41.777441 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:11:41.781250 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:11:41.788768 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:11:41.792232 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:11:41.796035 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:11:41.803527 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:11:41.806695 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:11:41.812752 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:11:41.816659 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:11:41.822786 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:11:41.826111 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:11:41.829768 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:11:41.836333 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:11:41.839446 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:11:41.843139 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:11:41.846088 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:11:41.852544 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:11:41.855966 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:11:41.859370 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:11:41.865966 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:11:41.868953 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:11:41.872279 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:11:41.879052 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:11:41.889280 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:11:41.892525 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:11:41.902162 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:11:41.909048 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:11:41.915553 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:11:41.919070 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:11:41.925281 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:11:41.932285 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 12:11:41.935287 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:11:41.942099 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:11:41.945727 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:11:41.954911 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 12:11:41.958622 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 12:11:41.965062 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 12:11:41.968532 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 12:11:41.971405 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 12:11:41.974987 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 12:11:41.978449 ADC[4]: Raw value=898150 ID=7
544 12:11:41.981508 ADC[3]: Raw value=212700 ID=1
545 12:11:41.985083 RAM Code: 0x71
546 12:11:41.988270 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 12:11:41.991554 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 12:11:42.002103 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 12:11:42.008736 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 12:11:42.011845 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 12:11:42.015102 in-header: 03 07 00 00 08 00 00 00
552 12:11:42.018714 in-data: aa e4 47 04 13 02 00 00
553 12:11:42.021583 Chrome EC: UHEPI supported
554 12:11:42.029153 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 12:11:42.032901 in-header: 03 d5 00 00 08 00 00 00
556 12:11:42.032989 in-data: 98 20 60 08 00 00 00 00
557 12:11:42.036527 MRC: failed to locate region type 0.
558 12:11:42.043936 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 12:11:42.047572 DRAM-K: Running full calibration
560 12:11:42.053847 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 12:11:42.053937 header.status = 0x0
562 12:11:42.057595 header.version = 0x6 (expected: 0x6)
563 12:11:42.061567 header.size = 0xd00 (expected: 0xd00)
564 12:11:42.064571 header.flags = 0x0
565 12:11:42.070810 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 12:11:42.087470 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
567 12:11:42.094270 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 12:11:42.097373 dram_init: ddr_geometry: 2
569 12:11:42.100573 [EMI] MDL number = 2
570 12:11:42.100653 [EMI] Get MDL freq = 0
571 12:11:42.103659 dram_init: ddr_type: 0
572 12:11:42.103766 is_discrete_lpddr4: 1
573 12:11:42.107442 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 12:11:42.107531
575 12:11:42.107601
576 12:11:42.110447 [Bian_co] ETT version 0.0.0.1
577 12:11:42.116972 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 12:11:42.117067
579 12:11:42.120713 dramc_set_vcore_voltage set vcore to 650000
580 12:11:42.120827 Read voltage for 800, 4
581 12:11:42.124389 Vio18 = 0
582 12:11:42.124510 Vcore = 650000
583 12:11:42.124612 Vdram = 0
584 12:11:42.128090 Vddq = 0
585 12:11:42.128176 Vmddr = 0
586 12:11:42.131193 dram_init: config_dvfs: 1
587 12:11:42.134979 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 12:11:42.138713 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 12:11:42.142479 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 12:11:42.149724 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 12:11:42.152972 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 12:11:42.156634 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 12:11:42.156712 MEM_TYPE=3, freq_sel=18
594 12:11:42.160415 sv_algorithm_assistance_LP4_1600
595 12:11:42.163887 ============ PULL DRAM RESETB DOWN ============
596 12:11:42.167389 ========== PULL DRAM RESETB DOWN end =========
597 12:11:42.174791 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 12:11:42.178444 ===================================
599 12:11:42.178573 LPDDR4 DRAM CONFIGURATION
600 12:11:42.182220 ===================================
601 12:11:42.185485 EX_ROW_EN[0] = 0x0
602 12:11:42.185601 EX_ROW_EN[1] = 0x0
603 12:11:42.189707 LP4Y_EN = 0x0
604 12:11:42.189794 WORK_FSP = 0x0
605 12:11:42.193144 WL = 0x2
606 12:11:42.193230 RL = 0x2
607 12:11:42.196723 BL = 0x2
608 12:11:42.196810 RPST = 0x0
609 12:11:42.196878 RD_PRE = 0x0
610 12:11:42.200459 WR_PRE = 0x1
611 12:11:42.200545 WR_PST = 0x0
612 12:11:42.204220 DBI_WR = 0x0
613 12:11:42.204307 DBI_RD = 0x0
614 12:11:42.208032 OTF = 0x1
615 12:11:42.211817 ===================================
616 12:11:42.214847 ===================================
617 12:11:42.214935 ANA top config
618 12:11:42.217893 ===================================
619 12:11:42.221458 DLL_ASYNC_EN = 0
620 12:11:42.224578 ALL_SLAVE_EN = 1
621 12:11:42.224668 NEW_RANK_MODE = 1
622 12:11:42.228240 DLL_IDLE_MODE = 1
623 12:11:42.231502 LP45_APHY_COMB_EN = 1
624 12:11:42.234653 TX_ODT_DIS = 1
625 12:11:42.234739 NEW_8X_MODE = 1
626 12:11:42.238342 ===================================
627 12:11:42.241494 ===================================
628 12:11:42.244497 data_rate = 1600
629 12:11:42.248200 CKR = 1
630 12:11:42.251225 DQ_P2S_RATIO = 8
631 12:11:42.254511 ===================================
632 12:11:42.257816 CA_P2S_RATIO = 8
633 12:11:42.260976 DQ_CA_OPEN = 0
634 12:11:42.264124 DQ_SEMI_OPEN = 0
635 12:11:42.264210 CA_SEMI_OPEN = 0
636 12:11:42.267364 CA_FULL_RATE = 0
637 12:11:42.270986 DQ_CKDIV4_EN = 1
638 12:11:42.274041 CA_CKDIV4_EN = 1
639 12:11:42.277647 CA_PREDIV_EN = 0
640 12:11:42.281103 PH8_DLY = 0
641 12:11:42.281190 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 12:11:42.284037 DQ_AAMCK_DIV = 4
643 12:11:42.287503 CA_AAMCK_DIV = 4
644 12:11:42.290531 CA_ADMCK_DIV = 4
645 12:11:42.294002 DQ_TRACK_CA_EN = 0
646 12:11:42.296983 CA_PICK = 800
647 12:11:42.300558 CA_MCKIO = 800
648 12:11:42.300652 MCKIO_SEMI = 0
649 12:11:42.303757 PLL_FREQ = 3068
650 12:11:42.307445 DQ_UI_PI_RATIO = 32
651 12:11:42.310552 CA_UI_PI_RATIO = 0
652 12:11:42.313736 ===================================
653 12:11:42.316915 ===================================
654 12:11:42.320591 memory_type:LPDDR4
655 12:11:42.320668 GP_NUM : 10
656 12:11:42.323698 SRAM_EN : 1
657 12:11:42.327278 MD32_EN : 0
658 12:11:42.330262 ===================================
659 12:11:42.330377 [ANA_INIT] >>>>>>>>>>>>>>
660 12:11:42.333375 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 12:11:42.337162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 12:11:42.340238 ===================================
663 12:11:42.343345 data_rate = 1600,PCW = 0X7600
664 12:11:42.346979 ===================================
665 12:11:42.349967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:11:42.356668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 12:11:42.359857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 12:11:42.366711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 12:11:42.369736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 12:11:42.373483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 12:11:42.373585 [ANA_INIT] flow start
672 12:11:42.377054 [ANA_INIT] PLL >>>>>>>>
673 12:11:42.380123 [ANA_INIT] PLL <<<<<<<<
674 12:11:42.380213 [ANA_INIT] MIDPI >>>>>>>>
675 12:11:42.383647 [ANA_INIT] MIDPI <<<<<<<<
676 12:11:42.387228 [ANA_INIT] DLL >>>>>>>>
677 12:11:42.387313 [ANA_INIT] flow end
678 12:11:42.394189 ============ LP4 DIFF to SE enter ============
679 12:11:42.398204 ============ LP4 DIFF to SE exit ============
680 12:11:42.398296 [ANA_INIT] <<<<<<<<<<<<<
681 12:11:42.401757 [Flow] Enable top DCM control >>>>>
682 12:11:42.405784 [Flow] Enable top DCM control <<<<<
683 12:11:42.409304 Enable DLL master slave shuffle
684 12:11:42.413047 ==============================================================
685 12:11:42.416255 Gating Mode config
686 12:11:42.419980 ==============================================================
687 12:11:42.423228 Config description:
688 12:11:42.433349 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 12:11:42.439757 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 12:11:42.442891 SELPH_MODE 0: By rank 1: By Phase
691 12:11:42.449673 ==============================================================
692 12:11:42.452898 GAT_TRACK_EN = 1
693 12:11:42.455934 RX_GATING_MODE = 2
694 12:11:42.459698 RX_GATING_TRACK_MODE = 2
695 12:11:42.462555 SELPH_MODE = 1
696 12:11:42.466271 PICG_EARLY_EN = 1
697 12:11:42.466378 VALID_LAT_VALUE = 1
698 12:11:42.472543 ==============================================================
699 12:11:42.476187 Enter into Gating configuration >>>>
700 12:11:42.479446 Exit from Gating configuration <<<<
701 12:11:42.482562 Enter into DVFS_PRE_config >>>>>
702 12:11:42.492752 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 12:11:42.495977 Exit from DVFS_PRE_config <<<<<
704 12:11:42.499262 Enter into PICG configuration >>>>
705 12:11:42.502759 Exit from PICG configuration <<<<
706 12:11:42.505904 [RX_INPUT] configuration >>>>>
707 12:11:42.509312 [RX_INPUT] configuration <<<<<
708 12:11:42.515506 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 12:11:42.519040 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 12:11:42.525667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 12:11:42.532535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 12:11:42.538839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 12:11:42.545467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 12:11:42.549000 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 12:11:42.552344 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 12:11:42.555327 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 12:11:42.562286 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 12:11:42.565412 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 12:11:42.569256 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 12:11:42.572387 ===================================
721 12:11:42.575426 LPDDR4 DRAM CONFIGURATION
722 12:11:42.579151 ===================================
723 12:11:42.579241 EX_ROW_EN[0] = 0x0
724 12:11:42.582427 EX_ROW_EN[1] = 0x0
725 12:11:42.585350 LP4Y_EN = 0x0
726 12:11:42.585427 WORK_FSP = 0x0
727 12:11:42.588564 WL = 0x2
728 12:11:42.588652 RL = 0x2
729 12:11:42.592247 BL = 0x2
730 12:11:42.592326 RPST = 0x0
731 12:11:42.595251 RD_PRE = 0x0
732 12:11:42.595329 WR_PRE = 0x1
733 12:11:42.598738 WR_PST = 0x0
734 12:11:42.598851 DBI_WR = 0x0
735 12:11:42.602493 DBI_RD = 0x0
736 12:11:42.602569 OTF = 0x1
737 12:11:42.605236 ===================================
738 12:11:42.608662 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 12:11:42.615229 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 12:11:42.618575 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 12:11:42.622105 ===================================
742 12:11:42.625507 LPDDR4 DRAM CONFIGURATION
743 12:11:42.628485 ===================================
744 12:11:42.628567 EX_ROW_EN[0] = 0x10
745 12:11:42.631908 EX_ROW_EN[1] = 0x0
746 12:11:42.631990 LP4Y_EN = 0x0
747 12:11:42.634927 WORK_FSP = 0x0
748 12:11:42.638139 WL = 0x2
749 12:11:42.638276 RL = 0x2
750 12:11:42.642068 BL = 0x2
751 12:11:42.642188 RPST = 0x0
752 12:11:42.645071 RD_PRE = 0x0
753 12:11:42.645186 WR_PRE = 0x1
754 12:11:42.648423 WR_PST = 0x0
755 12:11:42.648549 DBI_WR = 0x0
756 12:11:42.651563 DBI_RD = 0x0
757 12:11:42.651689 OTF = 0x1
758 12:11:42.654667 ===================================
759 12:11:42.661569 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 12:11:42.665445 nWR fixed to 40
761 12:11:42.669011 [ModeRegInit_LP4] CH0 RK0
762 12:11:42.669094 [ModeRegInit_LP4] CH0 RK1
763 12:11:42.672238 [ModeRegInit_LP4] CH1 RK0
764 12:11:42.675910 [ModeRegInit_LP4] CH1 RK1
765 12:11:42.675998 match AC timing 13
766 12:11:42.681995 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 12:11:42.685188 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 12:11:42.688856 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 12:11:42.695220 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 12:11:42.698958 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 12:11:42.702275 [EMI DOE] emi_dcm 0
772 12:11:42.705276 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 12:11:42.705393 ==
774 12:11:42.709027 Dram Type= 6, Freq= 0, CH_0, rank 0
775 12:11:42.712447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 12:11:42.712568 ==
777 12:11:42.719498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 12:11:42.723254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 12:11:42.733700 [CA 0] Center 38 (7~69) winsize 63
780 12:11:42.737244 [CA 1] Center 37 (7~68) winsize 62
781 12:11:42.741041 [CA 2] Center 35 (5~66) winsize 62
782 12:11:42.744663 [CA 3] Center 35 (5~66) winsize 62
783 12:11:42.747934 [CA 4] Center 34 (4~65) winsize 62
784 12:11:42.751849 [CA 5] Center 33 (3~64) winsize 62
785 12:11:42.751964
786 12:11:42.755510 [CmdBusTrainingLP45] Vref(ca) range 1: 32
787 12:11:42.755627
788 12:11:42.758848 [CATrainingPosCal] consider 1 rank data
789 12:11:42.762812 u2DelayCellTimex100 = 270/100 ps
790 12:11:42.766586 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
791 12:11:42.770430 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
792 12:11:42.770548 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
793 12:11:42.777580 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
794 12:11:42.777830 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
795 12:11:42.781436 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
796 12:11:42.781565
797 12:11:42.785008 CA PerBit enable=1, Macro0, CA PI delay=33
798 12:11:42.785106
799 12:11:42.788773 [CBTSetCACLKResult] CA Dly = 33
800 12:11:42.792461 CS Dly: 6 (0~37)
801 12:11:42.792539 ==
802 12:11:42.796309 Dram Type= 6, Freq= 0, CH_0, rank 1
803 12:11:42.800109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 12:11:42.800249 ==
805 12:11:42.803645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 12:11:42.810402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 12:11:42.820134 [CA 0] Center 38 (7~69) winsize 63
808 12:11:42.823602 [CA 1] Center 38 (7~69) winsize 63
809 12:11:42.827028 [CA 2] Center 35 (5~66) winsize 62
810 12:11:42.830707 [CA 3] Center 35 (5~66) winsize 62
811 12:11:42.834795 [CA 4] Center 34 (4~65) winsize 62
812 12:11:42.838495 [CA 5] Center 34 (4~65) winsize 62
813 12:11:42.838671
814 12:11:42.842049 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 12:11:42.842195
816 12:11:42.845673 [CATrainingPosCal] consider 2 rank data
817 12:11:42.845829 u2DelayCellTimex100 = 270/100 ps
818 12:11:42.852620 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 12:11:42.856345 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 12:11:42.860220 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 12:11:42.863607 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 12:11:42.867691 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 12:11:42.867806 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
824 12:11:42.871287
825 12:11:42.875055 CA PerBit enable=1, Macro0, CA PI delay=34
826 12:11:42.875167
827 12:11:42.875269 [CBTSetCACLKResult] CA Dly = 34
828 12:11:42.878726 CS Dly: 6 (0~38)
829 12:11:42.878841
830 12:11:42.882307 ----->DramcWriteLeveling(PI) begin...
831 12:11:42.882424 ==
832 12:11:42.885959 Dram Type= 6, Freq= 0, CH_0, rank 0
833 12:11:42.889670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 12:11:42.889782 ==
835 12:11:42.893370 Write leveling (Byte 0): 33 => 33
836 12:11:42.897266 Write leveling (Byte 1): 30 => 30
837 12:11:42.897376 DramcWriteLeveling(PI) end<-----
838 12:11:42.897472
839 12:11:42.897563 ==
840 12:11:42.900476 Dram Type= 6, Freq= 0, CH_0, rank 0
841 12:11:42.904258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 12:11:42.907813 ==
843 12:11:42.907923 [Gating] SW mode calibration
844 12:11:42.915716 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 12:11:42.923009 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 12:11:42.926861 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 12:11:42.930262 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 12:11:42.934123 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 12:11:42.937928 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 12:11:42.941382 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:11:42.949115 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:11:42.952178 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:11:42.955973 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:11:42.959652 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:11:42.963405 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:11:42.970744 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:11:42.974486 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:11:42.978082 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:11:42.981713 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:11:42.985808 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:11:42.992777 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:11:42.996621 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:11:43.000410 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:11:43.004244 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
865 12:11:43.008023 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
866 12:11:43.015100 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:11:43.018806 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:11:43.022392 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:11:43.026654 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:11:43.029721 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:11:43.036498 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:11:43.039509 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
873 12:11:43.043106 0 9 12 | B1->B0 | 2d2d 2f2f | 1 1 | (1 1) (1 1)
874 12:11:43.049804 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 12:11:43.053210 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 12:11:43.056199 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 12:11:43.063296 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 12:11:43.066305 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:11:43.069382 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:11:43.076099 0 10 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
881 12:11:43.079175 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
882 12:11:43.082755 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 12:11:43.089177 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 12:11:43.092686 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 12:11:43.095832 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:11:43.102574 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:11:43.105750 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:11:43.109382 0 11 8 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
889 12:11:43.115675 0 11 12 | B1->B0 | 3232 4141 | 0 0 | (0 0) (0 0)
890 12:11:43.119234 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 12:11:43.122327 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 12:11:43.129155 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 12:11:43.132625 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 12:11:43.135826 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:11:43.139410 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:11:43.145520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 12:11:43.148734 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 12:11:43.152054 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:11:43.158718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:11:43.162169 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:11:43.165327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:11:43.172246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:11:43.175278 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:11:43.178936 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:11:43.185324 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:11:43.188359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:11:43.191814 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:11:43.198804 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:11:43.202083 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:11:43.205278 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:11:43.211670 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:11:43.214855 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 12:11:43.218582 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
914 12:11:43.221622 Total UI for P1: 0, mck2ui 16
915 12:11:43.225222 best dqsien dly found for B0: ( 0, 14, 8)
916 12:11:43.228179 Total UI for P1: 0, mck2ui 16
917 12:11:43.231430 best dqsien dly found for B1: ( 0, 14, 10)
918 12:11:43.235160 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
919 12:11:43.238252 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
920 12:11:43.241851
921 12:11:43.244741 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
922 12:11:43.247932 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 12:11:43.251178 [Gating] SW calibration Done
924 12:11:43.251281 ==
925 12:11:43.254724 Dram Type= 6, Freq= 0, CH_0, rank 0
926 12:11:43.258098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 12:11:43.258204 ==
928 12:11:43.261548 RX Vref Scan: 0
929 12:11:43.261662
930 12:11:43.261765 RX Vref 0 -> 0, step: 1
931 12:11:43.261860
932 12:11:43.264479 RX Delay -130 -> 252, step: 16
933 12:11:43.268136 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
934 12:11:43.274390 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 12:11:43.278195 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
936 12:11:43.281219 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
937 12:11:43.284276 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 12:11:43.287982 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
939 12:11:43.291226 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 12:11:43.297865 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 12:11:43.301143 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 12:11:43.304529 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
943 12:11:43.307711 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 12:11:43.310871 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 12:11:43.317830 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 12:11:43.320960 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 12:11:43.324565 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 12:11:43.327582 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 12:11:43.327697 ==
950 12:11:43.331156 Dram Type= 6, Freq= 0, CH_0, rank 0
951 12:11:43.337385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 12:11:43.337494 ==
953 12:11:43.337591 DQS Delay:
954 12:11:43.341010 DQS0 = 0, DQS1 = 0
955 12:11:43.341111 DQM Delay:
956 12:11:43.344705 DQM0 = 82, DQM1 = 69
957 12:11:43.344812 DQ Delay:
958 12:11:43.347467 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
959 12:11:43.350679 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
960 12:11:43.353747 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
961 12:11:43.356909 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 12:11:43.357011
963 12:11:43.357104
964 12:11:43.357194 ==
965 12:11:43.360772 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:11:43.363621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:11:43.363721 ==
968 12:11:43.363815
969 12:11:43.363906
970 12:11:43.367474 TX Vref Scan disable
971 12:11:43.367579 == TX Byte 0 ==
972 12:11:43.374450 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
973 12:11:43.378039 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
974 12:11:43.378157 == TX Byte 1 ==
975 12:11:43.384560 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 12:11:43.387500 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 12:11:43.387607 ==
978 12:11:43.390719 Dram Type= 6, Freq= 0, CH_0, rank 0
979 12:11:43.394442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 12:11:43.394546 ==
981 12:11:43.408833 TX Vref=22, minBit 7, minWin=26, winSum=435
982 12:11:43.411777 TX Vref=24, minBit 11, minWin=26, winSum=436
983 12:11:43.415520 TX Vref=26, minBit 0, minWin=27, winSum=440
984 12:11:43.418655 TX Vref=28, minBit 10, minWin=27, winSum=444
985 12:11:43.421805 TX Vref=30, minBit 0, minWin=27, winSum=442
986 12:11:43.428731 TX Vref=32, minBit 9, minWin=26, winSum=441
987 12:11:43.431767 [TxChooseVref] Worse bit 10, Min win 27, Win sum 444, Final Vref 28
988 12:11:43.431888
989 12:11:43.435257 Final TX Range 1 Vref 28
990 12:11:43.435365
991 12:11:43.435460 ==
992 12:11:43.438360 Dram Type= 6, Freq= 0, CH_0, rank 0
993 12:11:43.442154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 12:11:43.445125 ==
995 12:11:43.445228
996 12:11:43.445324
997 12:11:43.445415 TX Vref Scan disable
998 12:11:43.448769 == TX Byte 0 ==
999 12:11:43.451949 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1000 12:11:43.458950 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1001 12:11:43.459031 == TX Byte 1 ==
1002 12:11:43.462072 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1003 12:11:43.468599 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1004 12:11:43.468709
1005 12:11:43.468806 [DATLAT]
1006 12:11:43.468898 Freq=800, CH0 RK0
1007 12:11:43.468991
1008 12:11:43.472109 DATLAT Default: 0xa
1009 12:11:43.472212 0, 0xFFFF, sum = 0
1010 12:11:43.475874 1, 0xFFFF, sum = 0
1011 12:11:43.475980 2, 0xFFFF, sum = 0
1012 12:11:43.479186 3, 0xFFFF, sum = 0
1013 12:11:43.479279 4, 0xFFFF, sum = 0
1014 12:11:43.482115 5, 0xFFFF, sum = 0
1015 12:11:43.485769 6, 0xFFFF, sum = 0
1016 12:11:43.485879 7, 0xFFFF, sum = 0
1017 12:11:43.489138 8, 0xFFFF, sum = 0
1018 12:11:43.489244 9, 0x0, sum = 1
1019 12:11:43.489342 10, 0x0, sum = 2
1020 12:11:43.492205 11, 0x0, sum = 3
1021 12:11:43.492314 12, 0x0, sum = 4
1022 12:11:43.495224 best_step = 10
1023 12:11:43.495323
1024 12:11:43.495414 ==
1025 12:11:43.498799 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 12:11:43.502014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 12:11:43.502120 ==
1028 12:11:43.505642 RX Vref Scan: 1
1029 12:11:43.505748
1030 12:11:43.505841 Set Vref Range= 32 -> 127
1031 12:11:43.508991
1032 12:11:43.509092 RX Vref 32 -> 127, step: 1
1033 12:11:43.509183
1034 12:11:43.511880 RX Delay -111 -> 252, step: 8
1035 12:11:43.511977
1036 12:11:43.515455 Set Vref, RX VrefLevel [Byte0]: 32
1037 12:11:43.518986 [Byte1]: 32
1038 12:11:43.519090
1039 12:11:43.521778 Set Vref, RX VrefLevel [Byte0]: 33
1040 12:11:43.525043 [Byte1]: 33
1041 12:11:43.529275
1042 12:11:43.529384 Set Vref, RX VrefLevel [Byte0]: 34
1043 12:11:43.532430 [Byte1]: 34
1044 12:11:43.537349
1045 12:11:43.537451 Set Vref, RX VrefLevel [Byte0]: 35
1046 12:11:43.540435 [Byte1]: 35
1047 12:11:43.544613
1048 12:11:43.544717 Set Vref, RX VrefLevel [Byte0]: 36
1049 12:11:43.547798 [Byte1]: 36
1050 12:11:43.552465
1051 12:11:43.552570 Set Vref, RX VrefLevel [Byte0]: 37
1052 12:11:43.555724 [Byte1]: 37
1053 12:11:43.560064
1054 12:11:43.560161 Set Vref, RX VrefLevel [Byte0]: 38
1055 12:11:43.563224 [Byte1]: 38
1056 12:11:43.567724
1057 12:11:43.567826 Set Vref, RX VrefLevel [Byte0]: 39
1058 12:11:43.570902 [Byte1]: 39
1059 12:11:43.575017
1060 12:11:43.575119 Set Vref, RX VrefLevel [Byte0]: 40
1061 12:11:43.581628 [Byte1]: 40
1062 12:11:43.581736
1063 12:11:43.585203 Set Vref, RX VrefLevel [Byte0]: 41
1064 12:11:43.588743 [Byte1]: 41
1065 12:11:43.588848
1066 12:11:43.591889 Set Vref, RX VrefLevel [Byte0]: 42
1067 12:11:43.594747 [Byte1]: 42
1068 12:11:43.598343
1069 12:11:43.598427 Set Vref, RX VrefLevel [Byte0]: 43
1070 12:11:43.601818 [Byte1]: 43
1071 12:11:43.606175
1072 12:11:43.606254 Set Vref, RX VrefLevel [Byte0]: 44
1073 12:11:43.609263 [Byte1]: 44
1074 12:11:43.613555
1075 12:11:43.613659 Set Vref, RX VrefLevel [Byte0]: 45
1076 12:11:43.616694 [Byte1]: 45
1077 12:11:43.621422
1078 12:11:43.621505 Set Vref, RX VrefLevel [Byte0]: 46
1079 12:11:43.624476 [Byte1]: 46
1080 12:11:43.628907
1081 12:11:43.629026 Set Vref, RX VrefLevel [Byte0]: 47
1082 12:11:43.632683 [Byte1]: 47
1083 12:11:43.636452
1084 12:11:43.636532 Set Vref, RX VrefLevel [Byte0]: 48
1085 12:11:43.639612 [Byte1]: 48
1086 12:11:43.643864
1087 12:11:43.643943 Set Vref, RX VrefLevel [Byte0]: 49
1088 12:11:43.647640 [Byte1]: 49
1089 12:11:43.652004
1090 12:11:43.652087 Set Vref, RX VrefLevel [Byte0]: 50
1091 12:11:43.655613 [Byte1]: 50
1092 12:11:43.659263
1093 12:11:43.659346 Set Vref, RX VrefLevel [Byte0]: 51
1094 12:11:43.662481 [Byte1]: 51
1095 12:11:43.666707
1096 12:11:43.666819 Set Vref, RX VrefLevel [Byte0]: 52
1097 12:11:43.670426 [Byte1]: 52
1098 12:11:43.674839
1099 12:11:43.674927 Set Vref, RX VrefLevel [Byte0]: 53
1100 12:11:43.681100 [Byte1]: 53
1101 12:11:43.681193
1102 12:11:43.684177 Set Vref, RX VrefLevel [Byte0]: 54
1103 12:11:43.687687 [Byte1]: 54
1104 12:11:43.687774
1105 12:11:43.691112 Set Vref, RX VrefLevel [Byte0]: 55
1106 12:11:43.693962 [Byte1]: 55
1107 12:11:43.697691
1108 12:11:43.697778 Set Vref, RX VrefLevel [Byte0]: 56
1109 12:11:43.701154 [Byte1]: 56
1110 12:11:43.705288
1111 12:11:43.705375 Set Vref, RX VrefLevel [Byte0]: 57
1112 12:11:43.708749 [Byte1]: 57
1113 12:11:43.713037
1114 12:11:43.713124 Set Vref, RX VrefLevel [Byte0]: 58
1115 12:11:43.716249 [Byte1]: 58
1116 12:11:43.720620
1117 12:11:43.720707 Set Vref, RX VrefLevel [Byte0]: 59
1118 12:11:43.724145 [Byte1]: 59
1119 12:11:43.728488
1120 12:11:43.728581 Set Vref, RX VrefLevel [Byte0]: 60
1121 12:11:43.731619 [Byte1]: 60
1122 12:11:43.735874
1123 12:11:43.735963 Set Vref, RX VrefLevel [Byte0]: 61
1124 12:11:43.738905 [Byte1]: 61
1125 12:11:43.743840
1126 12:11:43.743928 Set Vref, RX VrefLevel [Byte0]: 62
1127 12:11:43.746850 [Byte1]: 62
1128 12:11:43.751173
1129 12:11:43.751261 Set Vref, RX VrefLevel [Byte0]: 63
1130 12:11:43.754213 [Byte1]: 63
1131 12:11:43.758599
1132 12:11:43.758686 Set Vref, RX VrefLevel [Byte0]: 64
1133 12:11:43.762231 [Byte1]: 64
1134 12:11:43.766588
1135 12:11:43.766675 Set Vref, RX VrefLevel [Byte0]: 65
1136 12:11:43.769756 [Byte1]: 65
1137 12:11:43.774115
1138 12:11:43.774193 Set Vref, RX VrefLevel [Byte0]: 66
1139 12:11:43.777151 [Byte1]: 66
1140 12:11:43.781436
1141 12:11:43.781521 Set Vref, RX VrefLevel [Byte0]: 67
1142 12:11:43.785131 [Byte1]: 67
1143 12:11:43.789508
1144 12:11:43.789629 Set Vref, RX VrefLevel [Byte0]: 68
1145 12:11:43.792513 [Byte1]: 68
1146 12:11:43.797086
1147 12:11:43.797171 Set Vref, RX VrefLevel [Byte0]: 69
1148 12:11:43.800343 [Byte1]: 69
1149 12:11:43.804952
1150 12:11:43.805037 Set Vref, RX VrefLevel [Byte0]: 70
1151 12:11:43.808013 [Byte1]: 70
1152 12:11:43.812449
1153 12:11:43.812535 Set Vref, RX VrefLevel [Byte0]: 71
1154 12:11:43.815536 [Byte1]: 71
1155 12:11:43.820149
1156 12:11:43.820232 Set Vref, RX VrefLevel [Byte0]: 72
1157 12:11:43.823323 [Byte1]: 72
1158 12:11:43.827623
1159 12:11:43.827745 Set Vref, RX VrefLevel [Byte0]: 73
1160 12:11:43.830982 [Byte1]: 73
1161 12:11:43.835281
1162 12:11:43.835367 Set Vref, RX VrefLevel [Byte0]: 74
1163 12:11:43.838602 [Byte1]: 74
1164 12:11:43.842669
1165 12:11:43.842754 Set Vref, RX VrefLevel [Byte0]: 75
1166 12:11:43.846407 [Byte1]: 75
1167 12:11:43.850662
1168 12:11:43.850747 Set Vref, RX VrefLevel [Byte0]: 76
1169 12:11:43.854159 [Byte1]: 76
1170 12:11:43.858428
1171 12:11:43.858517 Set Vref, RX VrefLevel [Byte0]: 77
1172 12:11:43.861533 [Byte1]: 77
1173 12:11:43.865727
1174 12:11:43.865814 Set Vref, RX VrefLevel [Byte0]: 78
1175 12:11:43.869293 [Byte1]: 78
1176 12:11:43.873707
1177 12:11:43.873793 Set Vref, RX VrefLevel [Byte0]: 79
1178 12:11:43.876794 [Byte1]: 79
1179 12:11:43.881114
1180 12:11:43.881195 Set Vref, RX VrefLevel [Byte0]: 80
1181 12:11:43.884300 [Byte1]: 80
1182 12:11:43.888568
1183 12:11:43.888671 Final RX Vref Byte 0 = 55 to rank0
1184 12:11:43.891769 Final RX Vref Byte 1 = 60 to rank0
1185 12:11:43.895534 Final RX Vref Byte 0 = 55 to rank1
1186 12:11:43.898682 Final RX Vref Byte 1 = 60 to rank1==
1187 12:11:43.902219 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 12:11:43.908616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 12:11:43.908728 ==
1190 12:11:43.908828 DQS Delay:
1191 12:11:43.908922 DQS0 = 0, DQS1 = 0
1192 12:11:43.912196 DQM Delay:
1193 12:11:43.912275 DQM0 = 82, DQM1 = 67
1194 12:11:43.915126 DQ Delay:
1195 12:11:43.918378 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1196 12:11:43.921742 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1197 12:11:43.925393 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1198 12:11:43.928402 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1199 12:11:43.928518
1200 12:11:43.928617
1201 12:11:43.934911 [DQSOSCAuto] RK0, (LSB)MR18= 0x2322, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1202 12:11:43.938584 CH0 RK0: MR19=606, MR18=2322
1203 12:11:43.944805 CH0_RK0: MR19=0x606, MR18=0x2322, DQSOSC=401, MR23=63, INC=91, DEC=61
1204 12:11:43.944947
1205 12:11:43.948479 ----->DramcWriteLeveling(PI) begin...
1206 12:11:43.948565 ==
1207 12:11:43.951513 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 12:11:43.955018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 12:11:43.955109 ==
1210 12:11:43.958464 Write leveling (Byte 0): 30 => 30
1211 12:11:43.961583 Write leveling (Byte 1): 30 => 30
1212 12:11:43.965289 DramcWriteLeveling(PI) end<-----
1213 12:11:43.965393
1214 12:11:43.965485 ==
1215 12:11:43.968584 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 12:11:43.971483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 12:11:43.971568 ==
1218 12:11:43.974570 [Gating] SW mode calibration
1219 12:11:43.981413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 12:11:43.988258 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 12:11:43.991444 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 12:11:43.994546 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 12:11:44.001495 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1224 12:11:44.004750 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 12:11:44.008513 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:11:44.015014 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:11:44.017992 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:11:44.021662 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:11:44.028192 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:11:44.031233 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:11:44.034481 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:11:44.041194 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:11:44.085250 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:11:44.085626 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:11:44.085751 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:11:44.085849 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:11:44.085932 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:11:44.085996 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1239 12:11:44.086056 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1240 12:11:44.086115 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 12:11:44.086361 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:11:44.086451 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:11:44.129941 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:11:44.130274 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:11:44.130358 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:11:44.130453 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:11:44.130561 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1248 12:11:44.130844 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1249 12:11:44.130916 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 12:11:44.130978 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 12:11:44.131049 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 12:11:44.131119 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 12:11:44.160061 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 12:11:44.160663 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1255 12:11:44.160774 0 10 8 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
1256 12:11:44.161276 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:11:44.161668 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:11:44.161953 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:11:44.164969 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:11:44.165080 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:11:44.167947 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:11:44.171475 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1263 12:11:44.178160 0 11 8 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
1264 12:11:44.181526 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1265 12:11:44.184738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 12:11:44.191073 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 12:11:44.194718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:11:44.197850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 12:11:44.201646 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:11:44.209033 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1271 12:11:44.212820 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1272 12:11:44.215841 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:11:44.219539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:11:44.226302 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:11:44.230100 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:11:44.233526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:11:44.236971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:11:44.243231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:11:44.246816 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:11:44.249658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:11:44.256429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:11:44.260162 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:11:44.263290 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:11:44.269971 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:11:44.273587 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:11:44.276588 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1287 12:11:44.283354 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1288 12:11:44.283465 Total UI for P1: 0, mck2ui 16
1289 12:11:44.289751 best dqsien dly found for B0: ( 0, 14, 4)
1290 12:11:44.293510 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 12:11:44.296580 Total UI for P1: 0, mck2ui 16
1292 12:11:44.299659 best dqsien dly found for B1: ( 0, 14, 8)
1293 12:11:44.302798 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1294 12:11:44.306631 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1295 12:11:44.306741
1296 12:11:44.309670 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1297 12:11:44.312886 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 12:11:44.316016 [Gating] SW calibration Done
1299 12:11:44.316102 ==
1300 12:11:44.319970 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 12:11:44.322936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 12:11:44.325988 ==
1303 12:11:44.326074 RX Vref Scan: 0
1304 12:11:44.326141
1305 12:11:44.329701 RX Vref 0 -> 0, step: 1
1306 12:11:44.329789
1307 12:11:44.332820 RX Delay -130 -> 252, step: 16
1308 12:11:44.336543 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1309 12:11:44.339429 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1310 12:11:44.342902 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1311 12:11:44.346227 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1312 12:11:44.352709 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1313 12:11:44.356146 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1314 12:11:44.359516 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1315 12:11:44.362505 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1316 12:11:44.366175 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1317 12:11:44.372685 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1318 12:11:44.375667 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1319 12:11:44.379332 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1320 12:11:44.382203 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1321 12:11:44.385865 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1322 12:11:44.392436 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1323 12:11:44.395492 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1324 12:11:44.395585 ==
1325 12:11:44.398698 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 12:11:44.401874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 12:11:44.401965 ==
1328 12:11:44.405703 DQS Delay:
1329 12:11:44.405801 DQS0 = 0, DQS1 = 0
1330 12:11:44.408994 DQM Delay:
1331 12:11:44.409083 DQM0 = 77, DQM1 = 69
1332 12:11:44.409174 DQ Delay:
1333 12:11:44.412066 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =69
1334 12:11:44.415197 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1335 12:11:44.419039 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1336 12:11:44.422130 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1337 12:11:44.422240
1338 12:11:44.422334
1339 12:11:44.422423 ==
1340 12:11:44.425235 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 12:11:44.431746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 12:11:44.431843 ==
1343 12:11:44.431914
1344 12:11:44.431975
1345 12:11:44.432035 TX Vref Scan disable
1346 12:11:44.435593 == TX Byte 0 ==
1347 12:11:44.439236 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1348 12:11:44.445533 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1349 12:11:44.445651 == TX Byte 1 ==
1350 12:11:44.448956 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1351 12:11:44.455957 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1352 12:11:44.456069 ==
1353 12:11:44.458807 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 12:11:44.462409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 12:11:44.462520 ==
1356 12:11:44.475002 TX Vref=22, minBit 11, minWin=26, winSum=433
1357 12:11:44.478153 TX Vref=24, minBit 1, minWin=27, winSum=440
1358 12:11:44.481113 TX Vref=26, minBit 1, minWin=27, winSum=438
1359 12:11:44.484725 TX Vref=28, minBit 1, minWin=27, winSum=442
1360 12:11:44.487744 TX Vref=30, minBit 1, minWin=27, winSum=440
1361 12:11:44.494795 TX Vref=32, minBit 1, minWin=27, winSum=443
1362 12:11:44.497593 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 32
1363 12:11:44.497679
1364 12:11:44.501254 Final TX Range 1 Vref 32
1365 12:11:44.501356
1366 12:11:44.501449 ==
1367 12:11:44.504548 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 12:11:44.507708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 12:11:44.510822 ==
1370 12:11:44.510904
1371 12:11:44.510965
1372 12:11:44.511026 TX Vref Scan disable
1373 12:11:44.514522 == TX Byte 0 ==
1374 12:11:44.517621 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1375 12:11:44.524490 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1376 12:11:44.524595 == TX Byte 1 ==
1377 12:11:44.527645 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1378 12:11:44.534745 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1379 12:11:44.534838
1380 12:11:44.534906 [DATLAT]
1381 12:11:44.534966 Freq=800, CH0 RK1
1382 12:11:44.535025
1383 12:11:44.537737 DATLAT Default: 0xa
1384 12:11:44.537803 0, 0xFFFF, sum = 0
1385 12:11:44.540948 1, 0xFFFF, sum = 0
1386 12:11:44.541023 2, 0xFFFF, sum = 0
1387 12:11:44.544122 3, 0xFFFF, sum = 0
1388 12:11:44.547831 4, 0xFFFF, sum = 0
1389 12:11:44.547912 5, 0xFFFF, sum = 0
1390 12:11:44.550930 6, 0xFFFF, sum = 0
1391 12:11:44.551006 7, 0xFFFF, sum = 0
1392 12:11:44.554002 8, 0xFFFF, sum = 0
1393 12:11:44.554113 9, 0x0, sum = 1
1394 12:11:44.557667 10, 0x0, sum = 2
1395 12:11:44.557755 11, 0x0, sum = 3
1396 12:11:44.557854 12, 0x0, sum = 4
1397 12:11:44.561024 best_step = 10
1398 12:11:44.561132
1399 12:11:44.561226 ==
1400 12:11:44.564032 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 12:11:44.567582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 12:11:44.567691 ==
1403 12:11:44.570612 RX Vref Scan: 0
1404 12:11:44.570696
1405 12:11:44.574137 RX Vref 0 -> 0, step: 1
1406 12:11:44.574220
1407 12:11:44.574285 RX Delay -111 -> 252, step: 8
1408 12:11:44.581526 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1409 12:11:44.584430 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1410 12:11:44.588135 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1411 12:11:44.590965 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1412 12:11:44.594390 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1413 12:11:44.600933 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1414 12:11:44.604480 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1415 12:11:44.607728 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1416 12:11:44.610937 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1417 12:11:44.614516 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1418 12:11:44.621435 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1419 12:11:44.624453 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1420 12:11:44.627630 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1421 12:11:44.630864 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1422 12:11:44.637728 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1423 12:11:44.640858 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1424 12:11:44.640962 ==
1425 12:11:44.643933 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 12:11:44.647780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 12:11:44.647864 ==
1428 12:11:44.651341 DQS Delay:
1429 12:11:44.651426 DQS0 = 0, DQS1 = 0
1430 12:11:44.651498 DQM Delay:
1431 12:11:44.654536 DQM0 = 79, DQM1 = 70
1432 12:11:44.654645 DQ Delay:
1433 12:11:44.657655 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1434 12:11:44.660749 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1435 12:11:44.664446 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1436 12:11:44.667411 DQ12 =76, DQ13 =72, DQ14 =80, DQ15 =80
1437 12:11:44.667494
1438 12:11:44.667559
1439 12:11:44.677413 [DQSOSCAuto] RK1, (LSB)MR18= 0x441f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1440 12:11:44.677505 CH0 RK1: MR19=606, MR18=441F
1441 12:11:44.683923 CH0_RK1: MR19=0x606, MR18=0x441F, DQSOSC=392, MR23=63, INC=96, DEC=64
1442 12:11:44.687243 [RxdqsGatingPostProcess] freq 800
1443 12:11:44.694469 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 12:11:44.697743 Pre-setting of DQS Precalculation
1445 12:11:44.700549 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 12:11:44.700653 ==
1447 12:11:44.703911 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 12:11:44.710513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 12:11:44.710623 ==
1450 12:11:44.714248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 12:11:44.720463 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 12:11:44.729840 [CA 0] Center 36 (6~66) winsize 61
1453 12:11:44.732973 [CA 1] Center 36 (6~67) winsize 62
1454 12:11:44.736053 [CA 2] Center 34 (4~64) winsize 61
1455 12:11:44.739781 [CA 3] Center 34 (4~64) winsize 61
1456 12:11:44.742648 [CA 4] Center 34 (4~65) winsize 62
1457 12:11:44.746286 [CA 5] Center 34 (4~64) winsize 61
1458 12:11:44.746401
1459 12:11:44.749546 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1460 12:11:44.749651
1461 12:11:44.752611 [CATrainingPosCal] consider 1 rank data
1462 12:11:44.756234 u2DelayCellTimex100 = 270/100 ps
1463 12:11:44.759463 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1464 12:11:44.766241 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 12:11:44.769418 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 12:11:44.773113 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 12:11:44.776164 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 12:11:44.779753 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1469 12:11:44.779876
1470 12:11:44.782994 CA PerBit enable=1, Macro0, CA PI delay=34
1471 12:11:44.783119
1472 12:11:44.786186 [CBTSetCACLKResult] CA Dly = 34
1473 12:11:44.786300 CS Dly: 5 (0~36)
1474 12:11:44.789453 ==
1475 12:11:44.792796 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 12:11:44.796263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 12:11:44.796378 ==
1478 12:11:44.799573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 12:11:44.806024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 12:11:44.815793 [CA 0] Center 36 (6~67) winsize 62
1481 12:11:44.819363 [CA 1] Center 36 (6~67) winsize 62
1482 12:11:44.822546 [CA 2] Center 34 (4~65) winsize 62
1483 12:11:44.825717 [CA 3] Center 34 (4~64) winsize 61
1484 12:11:44.828870 [CA 4] Center 34 (4~64) winsize 61
1485 12:11:44.832219 [CA 5] Center 33 (3~64) winsize 62
1486 12:11:44.832347
1487 12:11:44.835898 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1488 12:11:44.836009
1489 12:11:44.838904 [CATrainingPosCal] consider 2 rank data
1490 12:11:44.841977 u2DelayCellTimex100 = 270/100 ps
1491 12:11:44.845566 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1492 12:11:44.851750 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 12:11:44.855419 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 12:11:44.858972 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 12:11:44.862781 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 12:11:44.866579 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1497 12:11:44.866692
1498 12:11:44.869779 CA PerBit enable=1, Macro0, CA PI delay=34
1499 12:11:44.869902
1500 12:11:44.873337 [CBTSetCACLKResult] CA Dly = 34
1501 12:11:44.873451 CS Dly: 6 (0~38)
1502 12:11:44.873561
1503 12:11:44.877006 ----->DramcWriteLeveling(PI) begin...
1504 12:11:44.877116 ==
1505 12:11:44.880096 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 12:11:44.883973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 12:11:44.884099 ==
1508 12:11:44.887458 Write leveling (Byte 0): 29 => 29
1509 12:11:44.891103 Write leveling (Byte 1): 29 => 29
1510 12:11:44.894558 DramcWriteLeveling(PI) end<-----
1511 12:11:44.894686
1512 12:11:44.894785 ==
1513 12:11:44.897940 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 12:11:44.901011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 12:11:44.901132 ==
1516 12:11:44.904633 [Gating] SW mode calibration
1517 12:11:44.911404 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 12:11:44.917986 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 12:11:44.920853 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 12:11:44.924365 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 12:11:44.931095 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 12:11:44.934240 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:11:44.937407 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:11:44.944150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:11:44.947827 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:11:44.950853 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:11:44.957733 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:11:44.960815 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:11:44.964067 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:11:44.970918 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:11:44.974040 0 7 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1532 12:11:44.977863 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:11:44.984152 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:11:44.987201 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:11:44.990762 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:11:44.997483 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1537 12:11:45.000525 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 12:11:45.004195 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:11:45.010605 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:11:45.014126 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:11:45.017877 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:11:45.024113 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:11:45.027043 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:11:45.030513 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:11:45.037586 0 9 8 | B1->B0 | 2b2b 2b2b | 1 0 | (0 0) (0 0)
1546 12:11:45.040638 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 12:11:45.044039 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 12:11:45.050353 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 12:11:45.053945 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 12:11:45.057026 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 12:11:45.063860 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 12:11:45.067045 0 10 4 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
1553 12:11:45.070117 0 10 8 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (1 1)
1554 12:11:45.077014 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:11:45.080381 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:11:45.083542 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:11:45.090341 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:11:45.093611 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:11:45.096723 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:11:45.103236 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1561 12:11:45.106508 0 11 8 | B1->B0 | 3b3b 3a3a | 1 0 | (0 0) (0 0)
1562 12:11:45.110115 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 12:11:45.116866 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:11:45.119926 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:11:45.123463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:11:45.126420 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 12:11:45.133006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 12:11:45.136463 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1569 12:11:45.139803 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1570 12:11:45.146500 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:11:45.149773 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:11:45.152943 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:11:45.159632 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:11:45.163010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:11:45.166668 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:11:45.173027 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:11:45.176665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:11:45.179867 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:11:45.186144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:11:45.189748 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:11:45.192955 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:11:45.199159 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:11:45.202686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:11:45.206462 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:11:45.212345 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 12:11:45.216070 Total UI for P1: 0, mck2ui 16
1587 12:11:45.218985 best dqsien dly found for B0: ( 0, 14, 6)
1588 12:11:45.219102 Total UI for P1: 0, mck2ui 16
1589 12:11:45.225558 best dqsien dly found for B1: ( 0, 14, 6)
1590 12:11:45.229049 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1591 12:11:45.232690 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1592 12:11:45.232807
1593 12:11:45.235701 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1594 12:11:45.239231 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1595 12:11:45.242211 [Gating] SW calibration Done
1596 12:11:45.242296 ==
1597 12:11:45.245664 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 12:11:45.249039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 12:11:45.249123 ==
1600 12:11:45.252165 RX Vref Scan: 0
1601 12:11:45.252242
1602 12:11:45.252305 RX Vref 0 -> 0, step: 1
1603 12:11:45.252365
1604 12:11:45.255956 RX Delay -130 -> 252, step: 16
1605 12:11:45.258984 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1606 12:11:45.265687 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1607 12:11:45.268586 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1608 12:11:45.271965 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1609 12:11:45.275570 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1610 12:11:45.281819 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1611 12:11:45.285585 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1612 12:11:45.288722 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1613 12:11:45.291913 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1614 12:11:45.295033 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1615 12:11:45.301891 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1616 12:11:45.304812 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1617 12:11:45.308333 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1618 12:11:45.311919 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1619 12:11:45.315025 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1620 12:11:45.321793 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1621 12:11:45.321906 ==
1622 12:11:45.325286 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 12:11:45.328205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 12:11:45.328321 ==
1625 12:11:45.328427 DQS Delay:
1626 12:11:45.331995 DQS0 = 0, DQS1 = 0
1627 12:11:45.332104 DQM Delay:
1628 12:11:45.334903 DQM0 = 81, DQM1 = 71
1629 12:11:45.334997 DQ Delay:
1630 12:11:45.338438 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1631 12:11:45.341559 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1632 12:11:45.345124 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1633 12:11:45.348140 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1634 12:11:45.348215
1635 12:11:45.348279
1636 12:11:45.348339 ==
1637 12:11:45.351633 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 12:11:45.355122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 12:11:45.355213 ==
1640 12:11:45.355293
1641 12:11:45.358200
1642 12:11:45.358274 TX Vref Scan disable
1643 12:11:45.361331 == TX Byte 0 ==
1644 12:11:45.365095 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1645 12:11:45.368195 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1646 12:11:45.371707 == TX Byte 1 ==
1647 12:11:45.374914 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1648 12:11:45.378012 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1649 12:11:45.378133 ==
1650 12:11:45.381905 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 12:11:45.387902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 12:11:45.388018 ==
1653 12:11:45.400047 TX Vref=22, minBit 1, minWin=26, winSum=437
1654 12:11:45.403261 TX Vref=24, minBit 1, minWin=26, winSum=438
1655 12:11:45.406336 TX Vref=26, minBit 1, minWin=27, winSum=442
1656 12:11:45.409963 TX Vref=28, minBit 1, minWin=27, winSum=443
1657 12:11:45.412917 TX Vref=30, minBit 4, minWin=27, winSum=446
1658 12:11:45.419550 TX Vref=32, minBit 4, minWin=27, winSum=445
1659 12:11:45.423219 [TxChooseVref] Worse bit 4, Min win 27, Win sum 446, Final Vref 30
1660 12:11:45.423336
1661 12:11:45.426425 Final TX Range 1 Vref 30
1662 12:11:45.426537
1663 12:11:45.426635 ==
1664 12:11:45.430102 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 12:11:45.433097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 12:11:45.433210 ==
1667 12:11:45.436562
1668 12:11:45.436676
1669 12:11:45.436775 TX Vref Scan disable
1670 12:11:45.439486 == TX Byte 0 ==
1671 12:11:45.443041 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1672 12:11:45.446622 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1673 12:11:45.449704 == TX Byte 1 ==
1674 12:11:45.453151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1675 12:11:45.459564 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1676 12:11:45.459656
1677 12:11:45.459724 [DATLAT]
1678 12:11:45.459787 Freq=800, CH1 RK0
1679 12:11:45.459848
1680 12:11:45.463049 DATLAT Default: 0xa
1681 12:11:45.463132 0, 0xFFFF, sum = 0
1682 12:11:45.466274 1, 0xFFFF, sum = 0
1683 12:11:45.466386 2, 0xFFFF, sum = 0
1684 12:11:45.469963 3, 0xFFFF, sum = 0
1685 12:11:45.470053 4, 0xFFFF, sum = 0
1686 12:11:45.472959 5, 0xFFFF, sum = 0
1687 12:11:45.476446 6, 0xFFFF, sum = 0
1688 12:11:45.476528 7, 0xFFFF, sum = 0
1689 12:11:45.479576 8, 0xFFFF, sum = 0
1690 12:11:45.479664 9, 0x0, sum = 1
1691 12:11:45.479734 10, 0x0, sum = 2
1692 12:11:45.483393 11, 0x0, sum = 3
1693 12:11:45.483471 12, 0x0, sum = 4
1694 12:11:45.486623 best_step = 10
1695 12:11:45.486701
1696 12:11:45.486769 ==
1697 12:11:45.489817 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 12:11:45.492911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 12:11:45.492986 ==
1700 12:11:45.496070 RX Vref Scan: 1
1701 12:11:45.496150
1702 12:11:45.499889 Set Vref Range= 32 -> 127
1703 12:11:45.499963
1704 12:11:45.500028 RX Vref 32 -> 127, step: 1
1705 12:11:45.500097
1706 12:11:45.502757 RX Delay -111 -> 252, step: 8
1707 12:11:45.502845
1708 12:11:45.505953 Set Vref, RX VrefLevel [Byte0]: 32
1709 12:11:45.509091 [Byte1]: 32
1710 12:11:45.512801
1711 12:11:45.512883 Set Vref, RX VrefLevel [Byte0]: 33
1712 12:11:45.515911 [Byte1]: 33
1713 12:11:45.520540
1714 12:11:45.520625 Set Vref, RX VrefLevel [Byte0]: 34
1715 12:11:45.523494 [Byte1]: 34
1716 12:11:45.527882
1717 12:11:45.527958 Set Vref, RX VrefLevel [Byte0]: 35
1718 12:11:45.531112 [Byte1]: 35
1719 12:11:45.535973
1720 12:11:45.536088 Set Vref, RX VrefLevel [Byte0]: 36
1721 12:11:45.539042 [Byte1]: 36
1722 12:11:45.543211
1723 12:11:45.543325 Set Vref, RX VrefLevel [Byte0]: 37
1724 12:11:45.546702 [Byte1]: 37
1725 12:11:45.550731
1726 12:11:45.554223 Set Vref, RX VrefLevel [Byte0]: 38
1727 12:11:45.557195 [Byte1]: 38
1728 12:11:45.557280
1729 12:11:45.560656 Set Vref, RX VrefLevel [Byte0]: 39
1730 12:11:45.563904 [Byte1]: 39
1731 12:11:45.563993
1732 12:11:45.567763 Set Vref, RX VrefLevel [Byte0]: 40
1733 12:11:45.570854 [Byte1]: 40
1734 12:11:45.573957
1735 12:11:45.574071 Set Vref, RX VrefLevel [Byte0]: 41
1736 12:11:45.577050 [Byte1]: 41
1737 12:11:45.581262
1738 12:11:45.581374 Set Vref, RX VrefLevel [Byte0]: 42
1739 12:11:45.587708 [Byte1]: 42
1740 12:11:45.587803
1741 12:11:45.591462 Set Vref, RX VrefLevel [Byte0]: 43
1742 12:11:45.594496 [Byte1]: 43
1743 12:11:45.594574
1744 12:11:45.598286 Set Vref, RX VrefLevel [Byte0]: 44
1745 12:11:45.601339 [Byte1]: 44
1746 12:11:45.604603
1747 12:11:45.604690 Set Vref, RX VrefLevel [Byte0]: 45
1748 12:11:45.607631 [Byte1]: 45
1749 12:11:45.611939
1750 12:11:45.612053 Set Vref, RX VrefLevel [Byte0]: 46
1751 12:11:45.615662 [Byte1]: 46
1752 12:11:45.619957
1753 12:11:45.620039 Set Vref, RX VrefLevel [Byte0]: 47
1754 12:11:45.623063 [Byte1]: 47
1755 12:11:45.627093
1756 12:11:45.627203 Set Vref, RX VrefLevel [Byte0]: 48
1757 12:11:45.630753 [Byte1]: 48
1758 12:11:45.635208
1759 12:11:45.635292 Set Vref, RX VrefLevel [Byte0]: 49
1760 12:11:45.638363 [Byte1]: 49
1761 12:11:45.642902
1762 12:11:45.642994 Set Vref, RX VrefLevel [Byte0]: 50
1763 12:11:45.645834 [Byte1]: 50
1764 12:11:45.649851
1765 12:11:45.653682 Set Vref, RX VrefLevel [Byte0]: 51
1766 12:11:45.656676 [Byte1]: 51
1767 12:11:45.656768
1768 12:11:45.660272 Set Vref, RX VrefLevel [Byte0]: 52
1769 12:11:45.663391 [Byte1]: 52
1770 12:11:45.663490
1771 12:11:45.666846 Set Vref, RX VrefLevel [Byte0]: 53
1772 12:11:45.669827 [Byte1]: 53
1773 12:11:45.673411
1774 12:11:45.673500 Set Vref, RX VrefLevel [Byte0]: 54
1775 12:11:45.676354 [Byte1]: 54
1776 12:11:45.680839
1777 12:11:45.680963 Set Vref, RX VrefLevel [Byte0]: 55
1778 12:11:45.684336 [Byte1]: 55
1779 12:11:45.688593
1780 12:11:45.688713 Set Vref, RX VrefLevel [Byte0]: 56
1781 12:11:45.691859 [Byte1]: 56
1782 12:11:45.696267
1783 12:11:45.696377 Set Vref, RX VrefLevel [Byte0]: 57
1784 12:11:45.699349 [Byte1]: 57
1785 12:11:45.703728
1786 12:11:45.703840 Set Vref, RX VrefLevel [Byte0]: 58
1787 12:11:45.706900 [Byte1]: 58
1788 12:11:45.711733
1789 12:11:45.711850 Set Vref, RX VrefLevel [Byte0]: 59
1790 12:11:45.714654 [Byte1]: 59
1791 12:11:45.718965
1792 12:11:45.719083 Set Vref, RX VrefLevel [Byte0]: 60
1793 12:11:45.722101 [Byte1]: 60
1794 12:11:45.726899
1795 12:11:45.726987 Set Vref, RX VrefLevel [Byte0]: 61
1796 12:11:45.730299 [Byte1]: 61
1797 12:11:45.734599
1798 12:11:45.734728 Set Vref, RX VrefLevel [Byte0]: 62
1799 12:11:45.737742 [Byte1]: 62
1800 12:11:45.742191
1801 12:11:45.742309 Set Vref, RX VrefLevel [Byte0]: 63
1802 12:11:45.745266 [Byte1]: 63
1803 12:11:45.749750
1804 12:11:45.752666 Set Vref, RX VrefLevel [Byte0]: 64
1805 12:11:45.752778 [Byte1]: 64
1806 12:11:45.757418
1807 12:11:45.757530 Set Vref, RX VrefLevel [Byte0]: 65
1808 12:11:45.760391 [Byte1]: 65
1809 12:11:45.765024
1810 12:11:45.765147 Set Vref, RX VrefLevel [Byte0]: 66
1811 12:11:45.768473 [Byte1]: 66
1812 12:11:45.772509
1813 12:11:45.772623 Set Vref, RX VrefLevel [Byte0]: 67
1814 12:11:45.776340 [Byte1]: 67
1815 12:11:45.780542
1816 12:11:45.780651 Set Vref, RX VrefLevel [Byte0]: 68
1817 12:11:45.783476 [Byte1]: 68
1818 12:11:45.787917
1819 12:11:45.788009 Set Vref, RX VrefLevel [Byte0]: 69
1820 12:11:45.791277 [Byte1]: 69
1821 12:11:45.795457
1822 12:11:45.795546 Set Vref, RX VrefLevel [Byte0]: 70
1823 12:11:45.799227 [Byte1]: 70
1824 12:11:45.803062
1825 12:11:45.803145 Set Vref, RX VrefLevel [Byte0]: 71
1826 12:11:45.806683 [Byte1]: 71
1827 12:11:45.811143
1828 12:11:45.811225 Set Vref, RX VrefLevel [Byte0]: 72
1829 12:11:45.814254 [Byte1]: 72
1830 12:11:45.818567
1831 12:11:45.818658 Set Vref, RX VrefLevel [Byte0]: 73
1832 12:11:45.821649 [Byte1]: 73
1833 12:11:45.825997
1834 12:11:45.826088 Set Vref, RX VrefLevel [Byte0]: 74
1835 12:11:45.829611 [Byte1]: 74
1836 12:11:45.833778
1837 12:11:45.833873 Final RX Vref Byte 0 = 61 to rank0
1838 12:11:45.837421 Final RX Vref Byte 1 = 61 to rank0
1839 12:11:45.840465 Final RX Vref Byte 0 = 61 to rank1
1840 12:11:45.843519 Final RX Vref Byte 1 = 61 to rank1==
1841 12:11:45.847399 Dram Type= 6, Freq= 0, CH_1, rank 0
1842 12:11:45.853586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 12:11:45.853703 ==
1844 12:11:45.853798 DQS Delay:
1845 12:11:45.857223 DQS0 = 0, DQS1 = 0
1846 12:11:45.857301 DQM Delay:
1847 12:11:45.857395 DQM0 = 80, DQM1 = 69
1848 12:11:45.860299 DQ Delay:
1849 12:11:45.863803 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1850 12:11:45.866836 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1851 12:11:45.870450 DQ8 =56, DQ9 =64, DQ10 =68, DQ11 =64
1852 12:11:45.873431 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1853 12:11:45.873536
1854 12:11:45.873629
1855 12:11:45.880096 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1856 12:11:45.883688 CH1 RK0: MR19=606, MR18=C16
1857 12:11:45.889913 CH1_RK0: MR19=0x606, MR18=0xC16, DQSOSC=404, MR23=63, INC=90, DEC=60
1858 12:11:45.890070
1859 12:11:45.893501 ----->DramcWriteLeveling(PI) begin...
1860 12:11:45.893616 ==
1861 12:11:45.896884 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 12:11:45.900248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 12:11:45.900337 ==
1864 12:11:45.903244 Write leveling (Byte 0): 27 => 27
1865 12:11:45.906645 Write leveling (Byte 1): 29 => 29
1866 12:11:45.910262 DramcWriteLeveling(PI) end<-----
1867 12:11:45.910349
1868 12:11:45.910435 ==
1869 12:11:45.913423 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 12:11:45.916625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 12:11:45.916713 ==
1872 12:11:45.920170 [Gating] SW mode calibration
1873 12:11:45.926900 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1874 12:11:45.933583 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1875 12:11:45.936697 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1876 12:11:45.940234 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1877 12:11:45.946435 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:11:45.949729 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:11:45.953445 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:11:45.959646 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:11:45.963414 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:11:45.966573 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:11:45.973113 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:11:45.976587 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:11:45.979704 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:11:45.986631 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:11:45.989589 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:11:45.993412 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:11:45.999689 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:11:46.003220 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:11:46.006159 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:11:46.013149 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1893 12:11:46.016469 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:11:46.019515 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:11:46.026061 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:11:46.029706 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:11:46.032839 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:11:46.039705 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:11:46.042692 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1900 12:11:46.046410 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1901 12:11:46.052684 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1902 12:11:46.056403 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 12:11:46.059609 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 12:11:46.062671 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 12:11:46.069849 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 12:11:46.072742 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 12:11:46.076170 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 12:11:46.082712 0 10 4 | B1->B0 | 3030 2929 | 1 0 | (1 0) (1 0)
1909 12:11:46.086188 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1910 12:11:46.089115 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:11:46.096197 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:11:46.099151 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:11:46.102297 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:11:46.109392 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 12:11:46.112241 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 12:11:46.115702 0 11 4 | B1->B0 | 2a2a 3838 | 0 0 | (1 1) (0 0)
1917 12:11:46.122341 0 11 8 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1918 12:11:46.126004 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 12:11:46.129060 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 12:11:46.135783 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 12:11:46.138822 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:11:46.142578 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 12:11:46.148742 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:11:46.152499 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1925 12:11:46.155631 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:11:46.162460 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:11:46.165609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:11:46.168620 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:11:46.175522 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:11:46.178726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:11:46.182229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:11:46.188502 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:11:46.192129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:11:46.195014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:11:46.201584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:11:46.204701 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:11:46.208602 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:11:46.215008 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:11:46.218509 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:11:46.221415 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1941 12:11:46.228441 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 12:11:46.228554 Total UI for P1: 0, mck2ui 16
1943 12:11:46.234643 best dqsien dly found for B0: ( 0, 14, 4)
1944 12:11:46.234782 Total UI for P1: 0, mck2ui 16
1945 12:11:46.241453 best dqsien dly found for B1: ( 0, 14, 6)
1946 12:11:46.244453 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1947 12:11:46.248262 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1948 12:11:46.248353
1949 12:11:46.251299 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1950 12:11:46.254394 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1951 12:11:46.258202 [Gating] SW calibration Done
1952 12:11:46.258298 ==
1953 12:11:46.261263 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:11:46.264367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:11:46.264464 ==
1956 12:11:46.268071 RX Vref Scan: 0
1957 12:11:46.268188
1958 12:11:46.268258 RX Vref 0 -> 0, step: 1
1959 12:11:46.268321
1960 12:11:46.271143 RX Delay -130 -> 252, step: 16
1961 12:11:46.274253 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1962 12:11:46.281282 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1963 12:11:46.284437 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1964 12:11:46.287666 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1965 12:11:46.290913 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1966 12:11:46.294513 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1967 12:11:46.301156 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1968 12:11:46.304039 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1969 12:11:46.307391 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1970 12:11:46.310959 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1971 12:11:46.314021 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1972 12:11:46.320658 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1973 12:11:46.324245 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1974 12:11:46.327752 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1975 12:11:46.330786 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1976 12:11:46.337275 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1977 12:11:46.337421 ==
1978 12:11:46.340836 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 12:11:46.344032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 12:11:46.344158 ==
1981 12:11:46.344257 DQS Delay:
1982 12:11:46.347064 DQS0 = 0, DQS1 = 0
1983 12:11:46.347164 DQM Delay:
1984 12:11:46.350775 DQM0 = 79, DQM1 = 76
1985 12:11:46.350899 DQ Delay:
1986 12:11:46.353974 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1987 12:11:46.356922 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =85
1988 12:11:46.360597 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =61
1989 12:11:46.363771 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1990 12:11:46.363908
1991 12:11:46.364006
1992 12:11:46.364107 ==
1993 12:11:46.366903 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 12:11:46.370553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 12:11:46.370656 ==
1996 12:11:46.370762
1997 12:11:46.373868
1998 12:11:46.373948 TX Vref Scan disable
1999 12:11:46.376834 == TX Byte 0 ==
2000 12:11:46.380583 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2001 12:11:46.383723 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2002 12:11:46.387453 == TX Byte 1 ==
2003 12:11:46.390546 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2004 12:11:46.393617 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2005 12:11:46.393717 ==
2006 12:11:46.397217 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 12:11:46.403814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 12:11:46.403969 ==
2009 12:11:46.415552 TX Vref=22, minBit 6, minWin=27, winSum=451
2010 12:11:46.418592 TX Vref=24, minBit 1, minWin=28, winSum=455
2011 12:11:46.421827 TX Vref=26, minBit 5, minWin=27, winSum=457
2012 12:11:46.425646 TX Vref=28, minBit 1, minWin=28, winSum=461
2013 12:11:46.428480 TX Vref=30, minBit 0, minWin=28, winSum=459
2014 12:11:46.435476 TX Vref=32, minBit 0, minWin=28, winSum=459
2015 12:11:46.438922 [TxChooseVref] Worse bit 1, Min win 28, Win sum 461, Final Vref 28
2016 12:11:46.439072
2017 12:11:46.441821 Final TX Range 1 Vref 28
2018 12:11:46.441918
2019 12:11:46.441987 ==
2020 12:11:46.445487 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 12:11:46.448506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 12:11:46.448626 ==
2023 12:11:46.451584
2024 12:11:46.451692
2025 12:11:46.451789 TX Vref Scan disable
2026 12:11:46.455252 == TX Byte 0 ==
2027 12:11:46.458472 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2028 12:11:46.465116 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2029 12:11:46.465229 == TX Byte 1 ==
2030 12:11:46.468936 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2031 12:11:46.475123 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2032 12:11:46.475233
2033 12:11:46.475303 [DATLAT]
2034 12:11:46.475364 Freq=800, CH1 RK1
2035 12:11:46.475424
2036 12:11:46.478833 DATLAT Default: 0xa
2037 12:11:46.478921 0, 0xFFFF, sum = 0
2038 12:11:46.482032 1, 0xFFFF, sum = 0
2039 12:11:46.485252 2, 0xFFFF, sum = 0
2040 12:11:46.485342 3, 0xFFFF, sum = 0
2041 12:11:46.488352 4, 0xFFFF, sum = 0
2042 12:11:46.488441 5, 0xFFFF, sum = 0
2043 12:11:46.491649 6, 0xFFFF, sum = 0
2044 12:11:46.491737 7, 0xFFFF, sum = 0
2045 12:11:46.495147 8, 0xFFFF, sum = 0
2046 12:11:46.495236 9, 0x0, sum = 1
2047 12:11:46.498777 10, 0x0, sum = 2
2048 12:11:46.498887 11, 0x0, sum = 3
2049 12:11:46.498957 12, 0x0, sum = 4
2050 12:11:46.501868 best_step = 10
2051 12:11:46.501955
2052 12:11:46.502020 ==
2053 12:11:46.505144 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 12:11:46.508341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 12:11:46.508432 ==
2056 12:11:46.511799 RX Vref Scan: 0
2057 12:11:46.511891
2058 12:11:46.514804 RX Vref 0 -> 0, step: 1
2059 12:11:46.514905
2060 12:11:46.514972 RX Delay -111 -> 252, step: 8
2061 12:11:46.522304 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2062 12:11:46.525446 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2063 12:11:46.528619 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2064 12:11:46.532499 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2065 12:11:46.538404 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2066 12:11:46.541903 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2067 12:11:46.545328 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2068 12:11:46.548286 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2069 12:11:46.551838 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2070 12:11:46.555430 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2071 12:11:46.561816 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2072 12:11:46.565416 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2073 12:11:46.568309 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2074 12:11:46.571494 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2075 12:11:46.578481 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2076 12:11:46.581431 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2077 12:11:46.581545 ==
2078 12:11:46.585236 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 12:11:46.588351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 12:11:46.588445 ==
2081 12:11:46.591476 DQS Delay:
2082 12:11:46.591570 DQS0 = 0, DQS1 = 0
2083 12:11:46.591649 DQM Delay:
2084 12:11:46.594647 DQM0 = 78, DQM1 = 74
2085 12:11:46.594754 DQ Delay:
2086 12:11:46.598232 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2087 12:11:46.601421 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2088 12:11:46.605183 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2089 12:11:46.608273 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2090 12:11:46.608384
2091 12:11:46.608454
2092 12:11:46.617924 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2093 12:11:46.618081 CH1 RK1: MR19=606, MR18=2139
2094 12:11:46.624904 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2095 12:11:46.628234 [RxdqsGatingPostProcess] freq 800
2096 12:11:46.634956 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2097 12:11:46.638198 Pre-setting of DQS Precalculation
2098 12:11:46.641466 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2099 12:11:46.651207 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2100 12:11:46.657730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2101 12:11:46.657903
2102 12:11:46.658022
2103 12:11:46.660759 [Calibration Summary] 1600 Mbps
2104 12:11:46.660889 CH 0, Rank 0
2105 12:11:46.663867 SW Impedance : PASS
2106 12:11:46.663994 DUTY Scan : NO K
2107 12:11:46.667616 ZQ Calibration : PASS
2108 12:11:46.670821 Jitter Meter : NO K
2109 12:11:46.670969 CBT Training : PASS
2110 12:11:46.674287 Write leveling : PASS
2111 12:11:46.677252 RX DQS gating : PASS
2112 12:11:46.677380 RX DQ/DQS(RDDQC) : PASS
2113 12:11:46.680575 TX DQ/DQS : PASS
2114 12:11:46.684315 RX DATLAT : PASS
2115 12:11:46.684446 RX DQ/DQS(Engine): PASS
2116 12:11:46.687471 TX OE : NO K
2117 12:11:46.687584 All Pass.
2118 12:11:46.687683
2119 12:11:46.690649 CH 0, Rank 1
2120 12:11:46.690779 SW Impedance : PASS
2121 12:11:46.693858 DUTY Scan : NO K
2122 12:11:46.697611 ZQ Calibration : PASS
2123 12:11:46.697736 Jitter Meter : NO K
2124 12:11:46.700672 CBT Training : PASS
2125 12:11:46.700784 Write leveling : PASS
2126 12:11:46.703799 RX DQS gating : PASS
2127 12:11:46.706949 RX DQ/DQS(RDDQC) : PASS
2128 12:11:46.707067 TX DQ/DQS : PASS
2129 12:11:46.710702 RX DATLAT : PASS
2130 12:11:46.713894 RX DQ/DQS(Engine): PASS
2131 12:11:46.714010 TX OE : NO K
2132 12:11:46.717196 All Pass.
2133 12:11:46.717306
2134 12:11:46.717402 CH 1, Rank 0
2135 12:11:46.720219 SW Impedance : PASS
2136 12:11:46.720348 DUTY Scan : NO K
2137 12:11:46.723864 ZQ Calibration : PASS
2138 12:11:46.726824 Jitter Meter : NO K
2139 12:11:46.726923 CBT Training : PASS
2140 12:11:46.730458 Write leveling : PASS
2141 12:11:46.734128 RX DQS gating : PASS
2142 12:11:46.734309 RX DQ/DQS(RDDQC) : PASS
2143 12:11:46.737418 TX DQ/DQS : PASS
2144 12:11:46.740734 RX DATLAT : PASS
2145 12:11:46.740879 RX DQ/DQS(Engine): PASS
2146 12:11:46.743871 TX OE : NO K
2147 12:11:46.743966 All Pass.
2148 12:11:46.744034
2149 12:11:46.747331 CH 1, Rank 1
2150 12:11:46.747421 SW Impedance : PASS
2151 12:11:46.750252 DUTY Scan : NO K
2152 12:11:46.753816 ZQ Calibration : PASS
2153 12:11:46.753932 Jitter Meter : NO K
2154 12:11:46.757195 CBT Training : PASS
2155 12:11:46.757281 Write leveling : PASS
2156 12:11:46.760733 RX DQS gating : PASS
2157 12:11:46.763636 RX DQ/DQS(RDDQC) : PASS
2158 12:11:46.763724 TX DQ/DQS : PASS
2159 12:11:46.767173 RX DATLAT : PASS
2160 12:11:46.770305 RX DQ/DQS(Engine): PASS
2161 12:11:46.770389 TX OE : NO K
2162 12:11:46.773414 All Pass.
2163 12:11:46.773496
2164 12:11:46.773560 DramC Write-DBI off
2165 12:11:46.776864 PER_BANK_REFRESH: Hybrid Mode
2166 12:11:46.780497 TX_TRACKING: ON
2167 12:11:46.783649 [GetDramInforAfterCalByMRR] Vendor 6.
2168 12:11:46.786793 [GetDramInforAfterCalByMRR] Revision 606.
2169 12:11:46.789980 [GetDramInforAfterCalByMRR] Revision 2 0.
2170 12:11:46.790067 MR0 0x3b3b
2171 12:11:46.790134 MR8 0x5151
2172 12:11:46.793760 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 12:11:46.796900
2174 12:11:46.796978 MR0 0x3b3b
2175 12:11:46.797041 MR8 0x5151
2176 12:11:46.799986 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 12:11:46.800062
2178 12:11:46.809967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2179 12:11:46.813631 [FAST_K] Save calibration result to emmc
2180 12:11:46.816799 [FAST_K] Save calibration result to emmc
2181 12:11:46.819909 dram_init: config_dvfs: 1
2182 12:11:46.823051 dramc_set_vcore_voltage set vcore to 662500
2183 12:11:46.826759 Read voltage for 1200, 2
2184 12:11:46.826851 Vio18 = 0
2185 12:11:46.826917 Vcore = 662500
2186 12:11:46.829793 Vdram = 0
2187 12:11:46.829871 Vddq = 0
2188 12:11:46.829934 Vmddr = 0
2189 12:11:46.836494 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2190 12:11:46.840165 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2191 12:11:46.842966 MEM_TYPE=3, freq_sel=15
2192 12:11:46.846529 sv_algorithm_assistance_LP4_1600
2193 12:11:46.849942 ============ PULL DRAM RESETB DOWN ============
2194 12:11:46.853497 ========== PULL DRAM RESETB DOWN end =========
2195 12:11:46.859626 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 12:11:46.863170 ===================================
2197 12:11:46.866511 LPDDR4 DRAM CONFIGURATION
2198 12:11:46.869952 ===================================
2199 12:11:46.870052 EX_ROW_EN[0] = 0x0
2200 12:11:46.873107 EX_ROW_EN[1] = 0x0
2201 12:11:46.873225 LP4Y_EN = 0x0
2202 12:11:46.876142 WORK_FSP = 0x0
2203 12:11:46.876268 WL = 0x4
2204 12:11:46.879676 RL = 0x4
2205 12:11:46.879799 BL = 0x2
2206 12:11:46.883167 RPST = 0x0
2207 12:11:46.883281 RD_PRE = 0x0
2208 12:11:46.886260 WR_PRE = 0x1
2209 12:11:46.886364 WR_PST = 0x0
2210 12:11:46.889399 DBI_WR = 0x0
2211 12:11:46.889514 DBI_RD = 0x0
2212 12:11:46.893218 OTF = 0x1
2213 12:11:46.896324 ===================================
2214 12:11:46.899458 ===================================
2215 12:11:46.899550 ANA top config
2216 12:11:46.903070 ===================================
2217 12:11:46.906093 DLL_ASYNC_EN = 0
2218 12:11:46.909151 ALL_SLAVE_EN = 0
2219 12:11:46.912660 NEW_RANK_MODE = 1
2220 12:11:46.915778 DLL_IDLE_MODE = 1
2221 12:11:46.915876 LP45_APHY_COMB_EN = 1
2222 12:11:46.919461 TX_ODT_DIS = 1
2223 12:11:46.922469 NEW_8X_MODE = 1
2224 12:11:46.925724 ===================================
2225 12:11:46.928925 ===================================
2226 12:11:46.932637 data_rate = 2400
2227 12:11:46.935582 CKR = 1
2228 12:11:46.935679 DQ_P2S_RATIO = 8
2229 12:11:46.939123 ===================================
2230 12:11:46.942212 CA_P2S_RATIO = 8
2231 12:11:46.945713 DQ_CA_OPEN = 0
2232 12:11:46.949396 DQ_SEMI_OPEN = 0
2233 12:11:46.952683 CA_SEMI_OPEN = 0
2234 12:11:46.955782 CA_FULL_RATE = 0
2235 12:11:46.955884 DQ_CKDIV4_EN = 0
2236 12:11:46.958798 CA_CKDIV4_EN = 0
2237 12:11:46.962057 CA_PREDIV_EN = 0
2238 12:11:46.965634 PH8_DLY = 17
2239 12:11:46.968687 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2240 12:11:46.972109 DQ_AAMCK_DIV = 4
2241 12:11:46.975617 CA_AAMCK_DIV = 4
2242 12:11:46.975717 CA_ADMCK_DIV = 4
2243 12:11:46.978434 DQ_TRACK_CA_EN = 0
2244 12:11:46.982088 CA_PICK = 1200
2245 12:11:46.985612 CA_MCKIO = 1200
2246 12:11:46.988483 MCKIO_SEMI = 0
2247 12:11:46.992184 PLL_FREQ = 2366
2248 12:11:46.995828 DQ_UI_PI_RATIO = 32
2249 12:11:46.995929 CA_UI_PI_RATIO = 0
2250 12:11:46.998956 ===================================
2251 12:11:47.002050 ===================================
2252 12:11:47.005701 memory_type:LPDDR4
2253 12:11:47.008788 GP_NUM : 10
2254 12:11:47.008885 SRAM_EN : 1
2255 12:11:47.012034 MD32_EN : 0
2256 12:11:47.015148 ===================================
2257 12:11:47.018863 [ANA_INIT] >>>>>>>>>>>>>>
2258 12:11:47.021994 <<<<<< [CONFIGURE PHASE]: ANA_TX
2259 12:11:47.025176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2260 12:11:47.028421 ===================================
2261 12:11:47.028517 data_rate = 2400,PCW = 0X5b00
2262 12:11:47.031583 ===================================
2263 12:11:47.035275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2264 12:11:47.041737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 12:11:47.048829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 12:11:47.051635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2267 12:11:47.055105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2268 12:11:47.058698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2269 12:11:47.061584 [ANA_INIT] flow start
2270 12:11:47.061686 [ANA_INIT] PLL >>>>>>>>
2271 12:11:47.064761 [ANA_INIT] PLL <<<<<<<<
2272 12:11:47.068097 [ANA_INIT] MIDPI >>>>>>>>
2273 12:11:47.071926 [ANA_INIT] MIDPI <<<<<<<<
2274 12:11:47.072115 [ANA_INIT] DLL >>>>>>>>
2275 12:11:47.074530 [ANA_INIT] DLL <<<<<<<<
2276 12:11:47.078052 [ANA_INIT] flow end
2277 12:11:47.081600 ============ LP4 DIFF to SE enter ============
2278 12:11:47.084980 ============ LP4 DIFF to SE exit ============
2279 12:11:47.088250 [ANA_INIT] <<<<<<<<<<<<<
2280 12:11:47.091287 [Flow] Enable top DCM control >>>>>
2281 12:11:47.094635 [Flow] Enable top DCM control <<<<<
2282 12:11:47.098226 Enable DLL master slave shuffle
2283 12:11:47.101470 ==============================================================
2284 12:11:47.104553 Gating Mode config
2285 12:11:47.111244 ==============================================================
2286 12:11:47.111398 Config description:
2287 12:11:47.121347 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2288 12:11:47.128173 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2289 12:11:47.131361 SELPH_MODE 0: By rank 1: By Phase
2290 12:11:47.137504 ==============================================================
2291 12:11:47.141154 GAT_TRACK_EN = 1
2292 12:11:47.144279 RX_GATING_MODE = 2
2293 12:11:47.147880 RX_GATING_TRACK_MODE = 2
2294 12:11:47.150932 SELPH_MODE = 1
2295 12:11:47.154521 PICG_EARLY_EN = 1
2296 12:11:47.157482 VALID_LAT_VALUE = 1
2297 12:11:47.161000 ==============================================================
2298 12:11:47.164134 Enter into Gating configuration >>>>
2299 12:11:47.167538 Exit from Gating configuration <<<<
2300 12:11:47.170851 Enter into DVFS_PRE_config >>>>>
2301 12:11:47.183959 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2302 12:11:47.184099 Exit from DVFS_PRE_config <<<<<
2303 12:11:47.187521 Enter into PICG configuration >>>>
2304 12:11:47.190903 Exit from PICG configuration <<<<
2305 12:11:47.194118 [RX_INPUT] configuration >>>>>
2306 12:11:47.197137 [RX_INPUT] configuration <<<<<
2307 12:11:47.204057 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2308 12:11:47.207054 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2309 12:11:47.213920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 12:11:47.220702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 12:11:47.227070 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 12:11:47.233431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 12:11:47.237081 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2314 12:11:47.240350 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2315 12:11:47.243471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2316 12:11:47.250184 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2317 12:11:47.253288 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2318 12:11:47.257165 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2319 12:11:47.260280 ===================================
2320 12:11:47.263542 LPDDR4 DRAM CONFIGURATION
2321 12:11:47.267100 ===================================
2322 12:11:47.270225 EX_ROW_EN[0] = 0x0
2323 12:11:47.270325 EX_ROW_EN[1] = 0x0
2324 12:11:47.273659 LP4Y_EN = 0x0
2325 12:11:47.273772 WORK_FSP = 0x0
2326 12:11:47.276792 WL = 0x4
2327 12:11:47.276900 RL = 0x4
2328 12:11:47.280288 BL = 0x2
2329 12:11:47.280372 RPST = 0x0
2330 12:11:47.283393 RD_PRE = 0x0
2331 12:11:47.283480 WR_PRE = 0x1
2332 12:11:47.286499 WR_PST = 0x0
2333 12:11:47.286578 DBI_WR = 0x0
2334 12:11:47.290081 DBI_RD = 0x0
2335 12:11:47.290180 OTF = 0x1
2336 12:11:47.293117 ===================================
2337 12:11:47.299745 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2338 12:11:47.303364 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2339 12:11:47.306434 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2340 12:11:47.310016 ===================================
2341 12:11:47.313477 LPDDR4 DRAM CONFIGURATION
2342 12:11:47.316434 ===================================
2343 12:11:47.320053 EX_ROW_EN[0] = 0x10
2344 12:11:47.320142 EX_ROW_EN[1] = 0x0
2345 12:11:47.322983 LP4Y_EN = 0x0
2346 12:11:47.323061 WORK_FSP = 0x0
2347 12:11:47.326136 WL = 0x4
2348 12:11:47.326237 RL = 0x4
2349 12:11:47.329854 BL = 0x2
2350 12:11:47.329969 RPST = 0x0
2351 12:11:47.333009 RD_PRE = 0x0
2352 12:11:47.333103 WR_PRE = 0x1
2353 12:11:47.336103 WR_PST = 0x0
2354 12:11:47.336192 DBI_WR = 0x0
2355 12:11:47.339916 DBI_RD = 0x0
2356 12:11:47.340006 OTF = 0x1
2357 12:11:47.343092 ===================================
2358 12:11:47.349770 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2359 12:11:47.349882 ==
2360 12:11:47.352841 Dram Type= 6, Freq= 0, CH_0, rank 0
2361 12:11:47.359904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 12:11:47.360036 ==
2363 12:11:47.360107 [Duty_Offset_Calibration]
2364 12:11:47.363081 B0:2 B1:0 CA:3
2365 12:11:47.363171
2366 12:11:47.366179 [DutyScan_Calibration_Flow] k_type=0
2367 12:11:47.374810
2368 12:11:47.374951 ==CLK 0==
2369 12:11:47.378239 Final CLK duty delay cell = 0
2370 12:11:47.381694 [0] MAX Duty = 5031%(X100), DQS PI = 12
2371 12:11:47.384563 [0] MIN Duty = 4875%(X100), DQS PI = 58
2372 12:11:47.387888 [0] AVG Duty = 4953%(X100)
2373 12:11:47.387983
2374 12:11:47.391447 CH0 CLK Duty spec in!! Max-Min= 156%
2375 12:11:47.395086 [DutyScan_Calibration_Flow] ====Done====
2376 12:11:47.395182
2377 12:11:47.398167 [DutyScan_Calibration_Flow] k_type=1
2378 12:11:47.413181
2379 12:11:47.413327 ==DQS 0 ==
2380 12:11:47.416733 Final DQS duty delay cell = 0
2381 12:11:47.420037 [0] MAX Duty = 5093%(X100), DQS PI = 28
2382 12:11:47.423526 [0] MIN Duty = 4907%(X100), DQS PI = 50
2383 12:11:47.426605 [0] AVG Duty = 5000%(X100)
2384 12:11:47.426730
2385 12:11:47.426824 ==DQS 1 ==
2386 12:11:47.429631 Final DQS duty delay cell = -4
2387 12:11:47.433389 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2388 12:11:47.436504 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2389 12:11:47.439638 [-4] AVG Duty = 4937%(X100)
2390 12:11:47.439750
2391 12:11:47.443359 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2392 12:11:47.443480
2393 12:11:47.446526 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2394 12:11:47.449632 [DutyScan_Calibration_Flow] ====Done====
2395 12:11:47.449743
2396 12:11:47.453262 [DutyScan_Calibration_Flow] k_type=3
2397 12:11:47.470652
2398 12:11:47.470852 ==DQM 0 ==
2399 12:11:47.474394 Final DQM duty delay cell = 0
2400 12:11:47.477542 [0] MAX Duty = 5124%(X100), DQS PI = 28
2401 12:11:47.480809 [0] MIN Duty = 4876%(X100), DQS PI = 0
2402 12:11:47.484452 [0] AVG Duty = 5000%(X100)
2403 12:11:47.484589
2404 12:11:47.484704 ==DQM 1 ==
2405 12:11:47.487443 Final DQM duty delay cell = 4
2406 12:11:47.490729 [4] MAX Duty = 5124%(X100), DQS PI = 50
2407 12:11:47.494218 [4] MIN Duty = 5031%(X100), DQS PI = 12
2408 12:11:47.497694 [4] AVG Duty = 5077%(X100)
2409 12:11:47.497796
2410 12:11:47.500595 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2411 12:11:47.500684
2412 12:11:47.504073 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2413 12:11:47.507163 [DutyScan_Calibration_Flow] ====Done====
2414 12:11:47.507290
2415 12:11:47.510801 [DutyScan_Calibration_Flow] k_type=2
2416 12:11:47.525661
2417 12:11:47.525862 ==DQ 0 ==
2418 12:11:47.529125 Final DQ duty delay cell = -4
2419 12:11:47.532627 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2420 12:11:47.535790 [-4] MIN Duty = 4907%(X100), DQS PI = 42
2421 12:11:47.538869 [-4] AVG Duty = 4969%(X100)
2422 12:11:47.538992
2423 12:11:47.539096 ==DQ 1 ==
2424 12:11:47.542545 Final DQ duty delay cell = -4
2425 12:11:47.545655 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2426 12:11:47.548905 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2427 12:11:47.552016 [-4] AVG Duty = 4938%(X100)
2428 12:11:47.552132
2429 12:11:47.555739 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2430 12:11:47.555871
2431 12:11:47.558686 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2432 12:11:47.561795 [DutyScan_Calibration_Flow] ====Done====
2433 12:11:47.561939 ==
2434 12:11:47.565630 Dram Type= 6, Freq= 0, CH_1, rank 0
2435 12:11:47.568820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2436 12:11:47.568952 ==
2437 12:11:47.571886 [Duty_Offset_Calibration]
2438 12:11:47.574947 B0:1 B1:-2 CA:0
2439 12:11:47.575071
2440 12:11:47.578693 [DutyScan_Calibration_Flow] k_type=0
2441 12:11:47.586347
2442 12:11:47.586521 ==CLK 0==
2443 12:11:47.590051 Final CLK duty delay cell = 0
2444 12:11:47.592967 [0] MAX Duty = 5031%(X100), DQS PI = 16
2445 12:11:47.596437 [0] MIN Duty = 4876%(X100), DQS PI = 2
2446 12:11:47.596568 [0] AVG Duty = 4953%(X100)
2447 12:11:47.599386
2448 12:11:47.602810 CH1 CLK Duty spec in!! Max-Min= 155%
2449 12:11:47.606233 [DutyScan_Calibration_Flow] ====Done====
2450 12:11:47.606361
2451 12:11:47.609681 [DutyScan_Calibration_Flow] k_type=1
2452 12:11:47.624646
2453 12:11:47.624847 ==DQS 0 ==
2454 12:11:47.628173 Final DQS duty delay cell = -4
2455 12:11:47.631084 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2456 12:11:47.635099 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2457 12:11:47.638110 [-4] AVG Duty = 4953%(X100)
2458 12:11:47.638246
2459 12:11:47.638349 ==DQS 1 ==
2460 12:11:47.641208 Final DQS duty delay cell = 0
2461 12:11:47.644451 [0] MAX Duty = 5062%(X100), DQS PI = 0
2462 12:11:47.648284 [0] MIN Duty = 4875%(X100), DQS PI = 26
2463 12:11:47.651317 [0] AVG Duty = 4968%(X100)
2464 12:11:47.651440
2465 12:11:47.654979 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2466 12:11:47.655097
2467 12:11:47.658131 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2468 12:11:47.661219 [DutyScan_Calibration_Flow] ====Done====
2469 12:11:47.661338
2470 12:11:47.664769 [DutyScan_Calibration_Flow] k_type=3
2471 12:11:47.681461
2472 12:11:47.681662 ==DQM 0 ==
2473 12:11:47.684682 Final DQM duty delay cell = 0
2474 12:11:47.687689 [0] MAX Duty = 5000%(X100), DQS PI = 22
2475 12:11:47.691299 [0] MIN Duty = 4844%(X100), DQS PI = 56
2476 12:11:47.694504 [0] AVG Duty = 4922%(X100)
2477 12:11:47.694638
2478 12:11:47.694742 ==DQM 1 ==
2479 12:11:47.697620 Final DQM duty delay cell = 0
2480 12:11:47.701259 [0] MAX Duty = 5031%(X100), DQS PI = 36
2481 12:11:47.704320 [0] MIN Duty = 4907%(X100), DQS PI = 2
2482 12:11:47.707930 [0] AVG Duty = 4969%(X100)
2483 12:11:47.708063
2484 12:11:47.710925 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2485 12:11:47.711045
2486 12:11:47.714581 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2487 12:11:47.717893 [DutyScan_Calibration_Flow] ====Done====
2488 12:11:47.718029
2489 12:11:47.721241 [DutyScan_Calibration_Flow] k_type=2
2490 12:11:47.737879
2491 12:11:47.738078 ==DQ 0 ==
2492 12:11:47.741328 Final DQ duty delay cell = 0
2493 12:11:47.744211 [0] MAX Duty = 5093%(X100), DQS PI = 26
2494 12:11:47.747540 [0] MIN Duty = 4907%(X100), DQS PI = 56
2495 12:11:47.747680 [0] AVG Duty = 5000%(X100)
2496 12:11:47.750662
2497 12:11:47.750783 ==DQ 1 ==
2498 12:11:47.754440 Final DQ duty delay cell = 0
2499 12:11:47.757523 [0] MAX Duty = 5125%(X100), DQS PI = 46
2500 12:11:47.761371 [0] MIN Duty = 4969%(X100), DQS PI = 26
2501 12:11:47.761503 [0] AVG Duty = 5047%(X100)
2502 12:11:47.761608
2503 12:11:47.767399 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2504 12:11:47.767542
2505 12:11:47.771061 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2506 12:11:47.774096 [DutyScan_Calibration_Flow] ====Done====
2507 12:11:47.777683 nWR fixed to 30
2508 12:11:47.777820 [ModeRegInit_LP4] CH0 RK0
2509 12:11:47.780968 [ModeRegInit_LP4] CH0 RK1
2510 12:11:47.783996 [ModeRegInit_LP4] CH1 RK0
2511 12:11:47.787703 [ModeRegInit_LP4] CH1 RK1
2512 12:11:47.787834 match AC timing 7
2513 12:11:47.790737 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2514 12:11:47.797694 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2515 12:11:47.800766 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2516 12:11:47.807653 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2517 12:11:47.810583 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2518 12:11:47.810720 ==
2519 12:11:47.813887 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 12:11:47.817090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 12:11:47.817215 ==
2522 12:11:47.824077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 12:11:47.830328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2524 12:11:47.837720 [CA 0] Center 40 (10~71) winsize 62
2525 12:11:47.841167 [CA 1] Center 39 (9~70) winsize 62
2526 12:11:47.844676 [CA 2] Center 36 (6~66) winsize 61
2527 12:11:47.848163 [CA 3] Center 35 (5~66) winsize 62
2528 12:11:47.851280 [CA 4] Center 34 (4~65) winsize 62
2529 12:11:47.854727 [CA 5] Center 33 (3~63) winsize 61
2530 12:11:47.854861
2531 12:11:47.857522 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2532 12:11:47.857641
2533 12:11:47.861424 [CATrainingPosCal] consider 1 rank data
2534 12:11:47.864755 u2DelayCellTimex100 = 270/100 ps
2535 12:11:47.867880 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2536 12:11:47.874504 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 12:11:47.878057 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2538 12:11:47.881090 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 12:11:47.884248 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2540 12:11:47.887956 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2541 12:11:47.888098
2542 12:11:47.891133 CA PerBit enable=1, Macro0, CA PI delay=33
2543 12:11:47.891255
2544 12:11:47.894081 [CBTSetCACLKResult] CA Dly = 33
2545 12:11:47.894198 CS Dly: 7 (0~38)
2546 12:11:47.897804 ==
2547 12:11:47.900939 Dram Type= 6, Freq= 0, CH_0, rank 1
2548 12:11:47.904071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 12:11:47.904192 ==
2550 12:11:47.907803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2551 12:11:47.914132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2552 12:11:47.924069 [CA 0] Center 40 (10~70) winsize 61
2553 12:11:47.927425 [CA 1] Center 40 (10~70) winsize 61
2554 12:11:47.930744 [CA 2] Center 35 (5~66) winsize 62
2555 12:11:47.934576 [CA 3] Center 35 (5~66) winsize 62
2556 12:11:47.937264 [CA 4] Center 34 (4~65) winsize 62
2557 12:11:47.940777 [CA 5] Center 33 (3~64) winsize 62
2558 12:11:47.940907
2559 12:11:47.943754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2560 12:11:47.943900
2561 12:11:47.946968 [CATrainingPosCal] consider 2 rank data
2562 12:11:47.950509 u2DelayCellTimex100 = 270/100 ps
2563 12:11:47.953462 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2564 12:11:47.960131 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2565 12:11:47.963699 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2566 12:11:47.967417 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 12:11:47.970583 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2568 12:11:47.973724 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2569 12:11:47.973822
2570 12:11:47.976868 CA PerBit enable=1, Macro0, CA PI delay=33
2571 12:11:47.976960
2572 12:11:47.980442 [CBTSetCACLKResult] CA Dly = 33
2573 12:11:47.983604 CS Dly: 8 (0~40)
2574 12:11:47.983728
2575 12:11:47.986669 ----->DramcWriteLeveling(PI) begin...
2576 12:11:47.986759 ==
2577 12:11:47.990466 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 12:11:47.993727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 12:11:47.993819 ==
2580 12:11:47.996784 Write leveling (Byte 0): 32 => 32
2581 12:11:47.999985 Write leveling (Byte 1): 29 => 29
2582 12:11:48.003715 DramcWriteLeveling(PI) end<-----
2583 12:11:48.003807
2584 12:11:48.003875 ==
2585 12:11:48.006864 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 12:11:48.010038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 12:11:48.010128 ==
2588 12:11:48.013284 [Gating] SW mode calibration
2589 12:11:48.020029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2590 12:11:48.026780 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2591 12:11:48.030110 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 12:11:48.033058 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2593 12:11:48.039865 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 12:11:48.043179 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 12:11:48.046622 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 12:11:48.053083 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 12:11:48.056188 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 12:11:48.059829 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2599 12:11:48.066557 1 0 0 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 1)
2600 12:11:48.070182 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2601 12:11:48.072999 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 12:11:48.079949 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:11:48.083071 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 12:11:48.086569 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 12:11:48.092730 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 12:11:48.095948 1 0 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
2607 12:11:48.099580 1 1 0 | B1->B0 | 2b2b 3636 | 1 0 | (0 0) (0 0)
2608 12:11:48.105862 1 1 4 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
2609 12:11:48.109680 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 12:11:48.112812 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 12:11:48.119210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 12:11:48.122305 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 12:11:48.126123 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 12:11:48.132244 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 12:11:48.135604 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2616 12:11:48.139264 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 12:11:48.145764 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:11:48.149105 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:11:48.152593 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:11:48.158967 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:11:48.162582 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:11:48.165564 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:11:48.172078 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:11:48.175695 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:11:48.178685 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:11:48.185632 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:11:48.188668 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:11:48.192271 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:11:48.198533 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:11:48.202141 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2631 12:11:48.205287 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2632 12:11:48.208457 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2633 12:11:48.212104 Total UI for P1: 0, mck2ui 16
2634 12:11:48.215208 best dqsien dly found for B0: ( 1, 3, 30)
2635 12:11:48.222174 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 12:11:48.225321 Total UI for P1: 0, mck2ui 16
2637 12:11:48.228434 best dqsien dly found for B1: ( 1, 4, 2)
2638 12:11:48.232195 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2639 12:11:48.235364 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2640 12:11:48.235489
2641 12:11:48.238464 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2642 12:11:48.241886 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2643 12:11:48.244899 [Gating] SW calibration Done
2644 12:11:48.244996 ==
2645 12:11:48.248578 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 12:11:48.251561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 12:11:48.251657 ==
2648 12:11:48.255089 RX Vref Scan: 0
2649 12:11:48.255182
2650 12:11:48.258542 RX Vref 0 -> 0, step: 1
2651 12:11:48.258662
2652 12:11:48.258771 RX Delay -40 -> 252, step: 8
2653 12:11:48.264831 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2654 12:11:48.267985 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2655 12:11:48.271859 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2656 12:11:48.274690 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2657 12:11:48.278165 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2658 12:11:48.284818 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2659 12:11:48.287864 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2660 12:11:48.291595 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2661 12:11:48.294735 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2662 12:11:48.297995 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2663 12:11:48.301738 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2664 12:11:48.308021 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2665 12:11:48.311184 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2666 12:11:48.314995 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2667 12:11:48.318157 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2668 12:11:48.324366 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2669 12:11:48.324490 ==
2670 12:11:48.328062 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 12:11:48.331138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 12:11:48.331239 ==
2673 12:11:48.331315 DQS Delay:
2674 12:11:48.334344 DQS0 = 0, DQS1 = 0
2675 12:11:48.334443 DQM Delay:
2676 12:11:48.338094 DQM0 = 112, DQM1 = 102
2677 12:11:48.338189 DQ Delay:
2678 12:11:48.341211 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2679 12:11:48.344186 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =119
2680 12:11:48.348042 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2681 12:11:48.350791 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2682 12:11:48.350904
2683 12:11:48.350971
2684 12:11:48.351039 ==
2685 12:11:48.354256 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:11:48.360790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:11:48.360909 ==
2688 12:11:48.360984
2689 12:11:48.361045
2690 12:11:48.361105 TX Vref Scan disable
2691 12:11:48.364892 == TX Byte 0 ==
2692 12:11:48.368302 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2693 12:11:48.371810 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2694 12:11:48.374915 == TX Byte 1 ==
2695 12:11:48.377942 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2696 12:11:48.381536 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2697 12:11:48.385001 ==
2698 12:11:48.388025 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 12:11:48.391601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 12:11:48.391698 ==
2701 12:11:48.402755 TX Vref=22, minBit 0, minWin=26, winSum=419
2702 12:11:48.405799 TX Vref=24, minBit 1, minWin=26, winSum=424
2703 12:11:48.409606 TX Vref=26, minBit 7, minWin=26, winSum=431
2704 12:11:48.412723 TX Vref=28, minBit 1, minWin=27, winSum=438
2705 12:11:48.415994 TX Vref=30, minBit 0, minWin=27, winSum=435
2706 12:11:48.422338 TX Vref=32, minBit 8, minWin=26, winSum=431
2707 12:11:48.426132 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 28
2708 12:11:48.426254
2709 12:11:48.429317 Final TX Range 1 Vref 28
2710 12:11:48.429408
2711 12:11:48.429479 ==
2712 12:11:48.432313 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 12:11:48.436075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 12:11:48.436225 ==
2715 12:11:48.439205
2716 12:11:48.439309
2717 12:11:48.439404 TX Vref Scan disable
2718 12:11:48.442351 == TX Byte 0 ==
2719 12:11:48.446188 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2720 12:11:48.452356 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2721 12:11:48.452464 == TX Byte 1 ==
2722 12:11:48.455883 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2723 12:11:48.462283 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2724 12:11:48.462442
2725 12:11:48.462548 [DATLAT]
2726 12:11:48.462642 Freq=1200, CH0 RK0
2727 12:11:48.462740
2728 12:11:48.465591 DATLAT Default: 0xd
2729 12:11:48.469058 0, 0xFFFF, sum = 0
2730 12:11:48.469173 1, 0xFFFF, sum = 0
2731 12:11:48.472547 2, 0xFFFF, sum = 0
2732 12:11:48.472636 3, 0xFFFF, sum = 0
2733 12:11:48.475288 4, 0xFFFF, sum = 0
2734 12:11:48.475366 5, 0xFFFF, sum = 0
2735 12:11:48.478859 6, 0xFFFF, sum = 0
2736 12:11:48.478941 7, 0xFFFF, sum = 0
2737 12:11:48.482008 8, 0xFFFF, sum = 0
2738 12:11:48.482086 9, 0xFFFF, sum = 0
2739 12:11:48.485578 10, 0xFFFF, sum = 0
2740 12:11:48.485704 11, 0xFFFF, sum = 0
2741 12:11:48.488689 12, 0x0, sum = 1
2742 12:11:48.488774 13, 0x0, sum = 2
2743 12:11:48.492497 14, 0x0, sum = 3
2744 12:11:48.492594 15, 0x0, sum = 4
2745 12:11:48.495348 best_step = 13
2746 12:11:48.495439
2747 12:11:48.495506 ==
2748 12:11:48.498843 Dram Type= 6, Freq= 0, CH_0, rank 0
2749 12:11:48.502570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2750 12:11:48.502671 ==
2751 12:11:48.502743 RX Vref Scan: 1
2752 12:11:48.505688
2753 12:11:48.505779 Set Vref Range= 32 -> 127
2754 12:11:48.505846
2755 12:11:48.508571 RX Vref 32 -> 127, step: 1
2756 12:11:48.508660
2757 12:11:48.512035 RX Delay -37 -> 252, step: 4
2758 12:11:48.512154
2759 12:11:48.515759 Set Vref, RX VrefLevel [Byte0]: 32
2760 12:11:48.518979 [Byte1]: 32
2761 12:11:48.519074
2762 12:11:48.522138 Set Vref, RX VrefLevel [Byte0]: 33
2763 12:11:48.525234 [Byte1]: 33
2764 12:11:48.529054
2765 12:11:48.529152 Set Vref, RX VrefLevel [Byte0]: 34
2766 12:11:48.532184 [Byte1]: 34
2767 12:11:48.536966
2768 12:11:48.537115 Set Vref, RX VrefLevel [Byte0]: 35
2769 12:11:48.540546 [Byte1]: 35
2770 12:11:48.544980
2771 12:11:48.545102 Set Vref, RX VrefLevel [Byte0]: 36
2772 12:11:48.548160 [Byte1]: 36
2773 12:11:48.553210
2774 12:11:48.553320 Set Vref, RX VrefLevel [Byte0]: 37
2775 12:11:48.556276 [Byte1]: 37
2776 12:11:48.561043
2777 12:11:48.561158 Set Vref, RX VrefLevel [Byte0]: 38
2778 12:11:48.564518 [Byte1]: 38
2779 12:11:48.569178
2780 12:11:48.569294 Set Vref, RX VrefLevel [Byte0]: 39
2781 12:11:48.572494 [Byte1]: 39
2782 12:11:48.577134
2783 12:11:48.577256 Set Vref, RX VrefLevel [Byte0]: 40
2784 12:11:48.580622 [Byte1]: 40
2785 12:11:48.585320
2786 12:11:48.585436 Set Vref, RX VrefLevel [Byte0]: 41
2787 12:11:48.588242 [Byte1]: 41
2788 12:11:48.593108
2789 12:11:48.593235 Set Vref, RX VrefLevel [Byte0]: 42
2790 12:11:48.596173 [Byte1]: 42
2791 12:11:48.601189
2792 12:11:48.601312 Set Vref, RX VrefLevel [Byte0]: 43
2793 12:11:48.604266 [Byte1]: 43
2794 12:11:48.609104
2795 12:11:48.609225 Set Vref, RX VrefLevel [Byte0]: 44
2796 12:11:48.612730 [Byte1]: 44
2797 12:11:48.617275
2798 12:11:48.617398 Set Vref, RX VrefLevel [Byte0]: 45
2799 12:11:48.620771 [Byte1]: 45
2800 12:11:48.625297
2801 12:11:48.625416 Set Vref, RX VrefLevel [Byte0]: 46
2802 12:11:48.628260 [Byte1]: 46
2803 12:11:48.633338
2804 12:11:48.633455 Set Vref, RX VrefLevel [Byte0]: 47
2805 12:11:48.636693 [Byte1]: 47
2806 12:11:48.640886
2807 12:11:48.641005 Set Vref, RX VrefLevel [Byte0]: 48
2808 12:11:48.644748 [Byte1]: 48
2809 12:11:48.649046
2810 12:11:48.649161 Set Vref, RX VrefLevel [Byte0]: 49
2811 12:11:48.652298 [Byte1]: 49
2812 12:11:48.657294
2813 12:11:48.657402 Set Vref, RX VrefLevel [Byte0]: 50
2814 12:11:48.660349 [Byte1]: 50
2815 12:11:48.665281
2816 12:11:48.665395 Set Vref, RX VrefLevel [Byte0]: 51
2817 12:11:48.668220 [Byte1]: 51
2818 12:11:48.672967
2819 12:11:48.673087 Set Vref, RX VrefLevel [Byte0]: 52
2820 12:11:48.676399 [Byte1]: 52
2821 12:11:48.681013
2822 12:11:48.681136 Set Vref, RX VrefLevel [Byte0]: 53
2823 12:11:48.684465 [Byte1]: 53
2824 12:11:48.689114
2825 12:11:48.689236 Set Vref, RX VrefLevel [Byte0]: 54
2826 12:11:48.692649 [Byte1]: 54
2827 12:11:48.696946
2828 12:11:48.697083 Set Vref, RX VrefLevel [Byte0]: 55
2829 12:11:48.700715 [Byte1]: 55
2830 12:11:48.705141
2831 12:11:48.705255 Set Vref, RX VrefLevel [Byte0]: 56
2832 12:11:48.708228 [Byte1]: 56
2833 12:11:48.713336
2834 12:11:48.713446 Set Vref, RX VrefLevel [Byte0]: 57
2835 12:11:48.716233 [Byte1]: 57
2836 12:11:48.720959
2837 12:11:48.721102 Set Vref, RX VrefLevel [Byte0]: 58
2838 12:11:48.724626 [Byte1]: 58
2839 12:11:48.728928
2840 12:11:48.729098 Set Vref, RX VrefLevel [Byte0]: 59
2841 12:11:48.732603 [Byte1]: 59
2842 12:11:48.737146
2843 12:11:48.737295 Set Vref, RX VrefLevel [Byte0]: 60
2844 12:11:48.740329 [Byte1]: 60
2845 12:11:48.745065
2846 12:11:48.745198 Set Vref, RX VrefLevel [Byte0]: 61
2847 12:11:48.748185 [Byte1]: 61
2848 12:11:48.753262
2849 12:11:48.753390 Set Vref, RX VrefLevel [Byte0]: 62
2850 12:11:48.756478 [Byte1]: 62
2851 12:11:48.760964
2852 12:11:48.761090 Set Vref, RX VrefLevel [Byte0]: 63
2853 12:11:48.764638 [Byte1]: 63
2854 12:11:48.769007
2855 12:11:48.769136 Set Vref, RX VrefLevel [Byte0]: 64
2856 12:11:48.772698 [Byte1]: 64
2857 12:11:48.777233
2858 12:11:48.777379 Set Vref, RX VrefLevel [Byte0]: 65
2859 12:11:48.780222 [Byte1]: 65
2860 12:11:48.785285
2861 12:11:48.785400 Set Vref, RX VrefLevel [Byte0]: 66
2862 12:11:48.788231 [Byte1]: 66
2863 12:11:48.793438
2864 12:11:48.793580 Set Vref, RX VrefLevel [Byte0]: 67
2865 12:11:48.796256 [Byte1]: 67
2866 12:11:48.801067
2867 12:11:48.801220 Set Vref, RX VrefLevel [Byte0]: 68
2868 12:11:48.804501 [Byte1]: 68
2869 12:11:48.809333
2870 12:11:48.809481 Set Vref, RX VrefLevel [Byte0]: 69
2871 12:11:48.812536 [Byte1]: 69
2872 12:11:48.817565
2873 12:11:48.817716 Set Vref, RX VrefLevel [Byte0]: 70
2874 12:11:48.820614 [Byte1]: 70
2875 12:11:48.824964
2876 12:11:48.825110 Set Vref, RX VrefLevel [Byte0]: 71
2877 12:11:48.828526 [Byte1]: 71
2878 12:11:48.833292
2879 12:11:48.833449 Set Vref, RX VrefLevel [Byte0]: 72
2880 12:11:48.836767 [Byte1]: 72
2881 12:11:48.841224
2882 12:11:48.841391 Set Vref, RX VrefLevel [Byte0]: 73
2883 12:11:48.844236 [Byte1]: 73
2884 12:11:48.849370
2885 12:11:48.849528 Final RX Vref Byte 0 = 62 to rank0
2886 12:11:48.852443 Final RX Vref Byte 1 = 47 to rank0
2887 12:11:48.855624 Final RX Vref Byte 0 = 62 to rank1
2888 12:11:48.859478 Final RX Vref Byte 1 = 47 to rank1==
2889 12:11:48.862642 Dram Type= 6, Freq= 0, CH_0, rank 0
2890 12:11:48.868759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 12:11:48.868987 ==
2892 12:11:48.869134 DQS Delay:
2893 12:11:48.869260 DQS0 = 0, DQS1 = 0
2894 12:11:48.872052 DQM Delay:
2895 12:11:48.872199 DQM0 = 113, DQM1 = 98
2896 12:11:48.875836 DQ Delay:
2897 12:11:48.878741 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2898 12:11:48.881903 DQ4 =114, DQ5 =104, DQ6 =120, DQ7 =120
2899 12:11:48.885529 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2900 12:11:48.889013 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2901 12:11:48.889162
2902 12:11:48.889256
2903 12:11:48.895417 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2904 12:11:48.898806 CH0 RK0: MR19=303, MR18=FEFE
2905 12:11:48.905322 CH0_RK0: MR19=0x303, MR18=0xFEFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2906 12:11:48.905488
2907 12:11:48.909000 ----->DramcWriteLeveling(PI) begin...
2908 12:11:48.909119 ==
2909 12:11:48.911787 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 12:11:48.918626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 12:11:48.918773 ==
2912 12:11:48.922456 Write leveling (Byte 0): 33 => 33
2913 12:11:48.922571 Write leveling (Byte 1): 29 => 29
2914 12:11:48.925679 DramcWriteLeveling(PI) end<-----
2915 12:11:48.925786
2916 12:11:48.925855 ==
2917 12:11:48.928785 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 12:11:48.935274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 12:11:48.935430 ==
2920 12:11:48.938289 [Gating] SW mode calibration
2921 12:11:48.944939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2922 12:11:48.948451 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2923 12:11:48.955302 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2924 12:11:48.958552 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 12:11:48.961510 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 12:11:48.968508 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 12:11:48.971640 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 12:11:48.974820 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 12:11:48.981652 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 12:11:48.985316 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2931 12:11:48.988213 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2932 12:11:48.994591 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 12:11:48.998128 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 12:11:49.001552 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 12:11:49.008579 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 12:11:49.011331 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 12:11:49.014722 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2938 12:11:49.018129 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2939 12:11:49.024847 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2940 12:11:49.027993 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 12:11:49.031054 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 12:11:49.037692 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 12:11:49.041653 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 12:11:49.044381 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 12:11:49.051135 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 12:11:49.054604 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2947 12:11:49.057768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2948 12:11:49.064609 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:11:49.067790 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:11:49.070748 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:11:49.077661 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:11:49.080787 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:11:49.083924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:11:49.090856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:11:49.093784 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:11:49.097526 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 12:11:49.103818 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 12:11:49.107218 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 12:11:49.110626 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 12:11:49.117046 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 12:11:49.120578 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2962 12:11:49.123829 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2963 12:11:49.127062 Total UI for P1: 0, mck2ui 16
2964 12:11:49.130089 best dqsien dly found for B0: ( 1, 3, 24)
2965 12:11:49.137144 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2966 12:11:49.140168 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 12:11:49.144211 Total UI for P1: 0, mck2ui 16
2968 12:11:49.146818 best dqsien dly found for B1: ( 1, 3, 30)
2969 12:11:49.150434 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2970 12:11:49.153685 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2971 12:11:49.153883
2972 12:11:49.156712 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2973 12:11:49.160531 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2974 12:11:49.163720 [Gating] SW calibration Done
2975 12:11:49.163840 ==
2976 12:11:49.166773 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 12:11:49.173574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 12:11:49.173726 ==
2979 12:11:49.173808 RX Vref Scan: 0
2980 12:11:49.173873
2981 12:11:49.176664 RX Vref 0 -> 0, step: 1
2982 12:11:49.176769
2983 12:11:49.179890 RX Delay -40 -> 252, step: 8
2984 12:11:49.183686 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2985 12:11:49.186745 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2986 12:11:49.189846 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2987 12:11:49.193603 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2988 12:11:49.200043 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2989 12:11:49.203578 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2990 12:11:49.206526 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2991 12:11:49.209864 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2992 12:11:49.213226 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2993 12:11:49.219481 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2994 12:11:49.222921 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2995 12:11:49.226803 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2996 12:11:49.229569 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2997 12:11:49.232976 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2998 12:11:49.239694 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2999 12:11:49.242746 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3000 12:11:49.242880 ==
3001 12:11:49.246561 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 12:11:49.249758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 12:11:49.249877 ==
3004 12:11:49.252775 DQS Delay:
3005 12:11:49.252884 DQS0 = 0, DQS1 = 0
3006 12:11:49.252981 DQM Delay:
3007 12:11:49.256400 DQM0 = 112, DQM1 = 101
3008 12:11:49.256488 DQ Delay:
3009 12:11:49.259563 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3010 12:11:49.263241 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3011 12:11:49.266245 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3012 12:11:49.272842 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
3013 12:11:49.272968
3014 12:11:49.273039
3015 12:11:49.273100 ==
3016 12:11:49.275952 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 12:11:49.279756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 12:11:49.279854 ==
3019 12:11:49.279924
3020 12:11:49.279987
3021 12:11:49.282970 TX Vref Scan disable
3022 12:11:49.283060 == TX Byte 0 ==
3023 12:11:49.289187 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3024 12:11:49.292956 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3025 12:11:49.293062 == TX Byte 1 ==
3026 12:11:49.299336 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3027 12:11:49.302497 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3028 12:11:49.302599 ==
3029 12:11:49.306191 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 12:11:49.309425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 12:11:49.309556 ==
3032 12:11:49.322452 TX Vref=22, minBit 1, minWin=26, winSum=425
3033 12:11:49.325878 TX Vref=24, minBit 1, minWin=26, winSum=432
3034 12:11:49.328729 TX Vref=26, minBit 1, minWin=26, winSum=436
3035 12:11:49.332103 TX Vref=28, minBit 1, minWin=27, winSum=440
3036 12:11:49.335379 TX Vref=30, minBit 1, minWin=26, winSum=440
3037 12:11:49.342225 TX Vref=32, minBit 1, minWin=26, winSum=438
3038 12:11:49.345491 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 28
3039 12:11:49.345636
3040 12:11:49.348922 Final TX Range 1 Vref 28
3041 12:11:49.349041
3042 12:11:49.349140 ==
3043 12:11:49.351996 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 12:11:49.355156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 12:11:49.358900 ==
3046 12:11:49.359042
3047 12:11:49.359146
3048 12:11:49.359239 TX Vref Scan disable
3049 12:11:49.361839 == TX Byte 0 ==
3050 12:11:49.365526 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3051 12:11:49.368522 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3052 12:11:49.371852 == TX Byte 1 ==
3053 12:11:49.375630 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3054 12:11:49.381787 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3055 12:11:49.381948
3056 12:11:49.382059 [DATLAT]
3057 12:11:49.382174 Freq=1200, CH0 RK1
3058 12:11:49.382269
3059 12:11:49.385564 DATLAT Default: 0xd
3060 12:11:49.385690 0, 0xFFFF, sum = 0
3061 12:11:49.388721 1, 0xFFFF, sum = 0
3062 12:11:49.388857 2, 0xFFFF, sum = 0
3063 12:11:49.391978 3, 0xFFFF, sum = 0
3064 12:11:49.395162 4, 0xFFFF, sum = 0
3065 12:11:49.395269 5, 0xFFFF, sum = 0
3066 12:11:49.398978 6, 0xFFFF, sum = 0
3067 12:11:49.399080 7, 0xFFFF, sum = 0
3068 12:11:49.402114 8, 0xFFFF, sum = 0
3069 12:11:49.402232 9, 0xFFFF, sum = 0
3070 12:11:49.405276 10, 0xFFFF, sum = 0
3071 12:11:49.405369 11, 0xFFFF, sum = 0
3072 12:11:49.408512 12, 0x0, sum = 1
3073 12:11:49.408604 13, 0x0, sum = 2
3074 12:11:49.411631 14, 0x0, sum = 3
3075 12:11:49.411758 15, 0x0, sum = 4
3076 12:11:49.411857 best_step = 13
3077 12:11:49.414981
3078 12:11:49.415110 ==
3079 12:11:49.418700 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 12:11:49.421799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 12:11:49.421904 ==
3082 12:11:49.421974 RX Vref Scan: 0
3083 12:11:49.422038
3084 12:11:49.424829 RX Vref 0 -> 0, step: 1
3085 12:11:49.424974
3086 12:11:49.428343 RX Delay -37 -> 252, step: 4
3087 12:11:49.431628 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3088 12:11:49.438529 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3089 12:11:49.441389 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3090 12:11:49.444668 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3091 12:11:49.448013 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3092 12:11:49.451549 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3093 12:11:49.458508 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3094 12:11:49.461522 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3095 12:11:49.464545 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3096 12:11:49.468182 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3097 12:11:49.471398 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3098 12:11:49.477977 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3099 12:11:49.481499 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3100 12:11:49.484406 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3101 12:11:49.488202 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3102 12:11:49.494534 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3103 12:11:49.494667 ==
3104 12:11:49.498231 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 12:11:49.501296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 12:11:49.501413 ==
3107 12:11:49.501501 DQS Delay:
3108 12:11:49.504451 DQS0 = 0, DQS1 = 0
3109 12:11:49.504543 DQM Delay:
3110 12:11:49.508213 DQM0 = 111, DQM1 = 99
3111 12:11:49.508306 DQ Delay:
3112 12:11:49.511220 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3113 12:11:49.514861 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3114 12:11:49.518027 DQ8 =88, DQ9 =82, DQ10 =100, DQ11 =90
3115 12:11:49.521010 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =108
3116 12:11:49.521137
3117 12:11:49.521233
3118 12:11:49.530952 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3119 12:11:49.531089 CH0 RK1: MR19=403, MR18=FF6
3120 12:11:49.537925 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3121 12:11:49.540702 [RxdqsGatingPostProcess] freq 1200
3122 12:11:49.547514 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3123 12:11:49.551023 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 12:11:49.554285 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 12:11:49.557690 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 12:11:49.560938 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 12:11:49.563850 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 12:11:49.567255 best DQS1 dly(2T, 0.5T) = (0, 11)
3129 12:11:49.570843 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 12:11:49.573926 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3131 12:11:49.574061 Pre-setting of DQS Precalculation
3132 12:11:49.580840 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3133 12:11:49.580958 ==
3134 12:11:49.583880 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 12:11:49.586920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 12:11:49.587017 ==
3137 12:11:49.593639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 12:11:49.600248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3139 12:11:49.607972 [CA 0] Center 37 (7~67) winsize 61
3140 12:11:49.611158 [CA 1] Center 38 (8~68) winsize 61
3141 12:11:49.614398 [CA 2] Center 34 (5~64) winsize 60
3142 12:11:49.618142 [CA 3] Center 33 (3~64) winsize 62
3143 12:11:49.621364 [CA 4] Center 34 (4~64) winsize 61
3144 12:11:49.624368 [CA 5] Center 33 (3~63) winsize 61
3145 12:11:49.624524
3146 12:11:49.628070 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3147 12:11:49.628203
3148 12:11:49.631173 [CATrainingPosCal] consider 1 rank data
3149 12:11:49.634332 u2DelayCellTimex100 = 270/100 ps
3150 12:11:49.637986 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3151 12:11:49.644089 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 12:11:49.647620 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3153 12:11:49.650560 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3154 12:11:49.654036 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 12:11:49.657629 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3156 12:11:49.657755
3157 12:11:49.660672 CA PerBit enable=1, Macro0, CA PI delay=33
3158 12:11:49.660778
3159 12:11:49.664062 [CBTSetCACLKResult] CA Dly = 33
3160 12:11:49.667719 CS Dly: 6 (0~37)
3161 12:11:49.667851 ==
3162 12:11:49.670464 Dram Type= 6, Freq= 0, CH_1, rank 1
3163 12:11:49.674120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 12:11:49.674265 ==
3165 12:11:49.680769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 12:11:49.683859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3167 12:11:49.693704 [CA 0] Center 37 (8~67) winsize 60
3168 12:11:49.696663 [CA 1] Center 37 (7~68) winsize 62
3169 12:11:49.700188 [CA 2] Center 34 (4~65) winsize 62
3170 12:11:49.703294 [CA 3] Center 33 (3~64) winsize 62
3171 12:11:49.706959 [CA 4] Center 34 (4~65) winsize 62
3172 12:11:49.710050 [CA 5] Center 32 (2~63) winsize 62
3173 12:11:49.710151
3174 12:11:49.713227 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3175 12:11:49.713323
3176 12:11:49.716936 [CATrainingPosCal] consider 2 rank data
3177 12:11:49.720113 u2DelayCellTimex100 = 270/100 ps
3178 12:11:49.723192 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3179 12:11:49.729983 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3180 12:11:49.733122 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3181 12:11:49.736293 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 12:11:49.740163 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 12:11:49.743135 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3184 12:11:49.743244
3185 12:11:49.746488 CA PerBit enable=1, Macro0, CA PI delay=33
3186 12:11:49.746621
3187 12:11:49.749679 [CBTSetCACLKResult] CA Dly = 33
3188 12:11:49.752686 CS Dly: 7 (0~40)
3189 12:11:49.752793
3190 12:11:49.756294 ----->DramcWriteLeveling(PI) begin...
3191 12:11:49.756397 ==
3192 12:11:49.759335 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:11:49.763129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:11:49.763233 ==
3195 12:11:49.766487 Write leveling (Byte 0): 26 => 26
3196 12:11:49.769520 Write leveling (Byte 1): 32 => 32
3197 12:11:49.772778 DramcWriteLeveling(PI) end<-----
3198 12:11:49.772904
3199 12:11:49.772978 ==
3200 12:11:49.776213 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 12:11:49.779837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 12:11:49.779960 ==
3203 12:11:49.782657 [Gating] SW mode calibration
3204 12:11:49.789417 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3205 12:11:49.796092 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3206 12:11:49.799480 0 15 0 | B1->B0 | 2e2e 2929 | 1 1 | (0 0) (0 0)
3207 12:11:49.802438 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 12:11:49.809552 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 12:11:49.812512 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 12:11:49.815685 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 12:11:49.821973 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 12:11:49.825825 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3213 12:11:49.828942 0 15 28 | B1->B0 | 2d2d 2e2e | 0 0 | (0 1) (0 0)
3214 12:11:49.835638 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3215 12:11:49.838762 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 12:11:49.841952 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 12:11:49.848706 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 12:11:49.852078 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 12:11:49.855136 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 12:11:49.861827 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3221 12:11:49.865447 1 0 28 | B1->B0 | 4040 3b3b | 0 0 | (0 0) (0 0)
3222 12:11:49.868282 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3223 12:11:49.875398 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 12:11:49.878650 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 12:11:49.881672 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 12:11:49.888052 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 12:11:49.891680 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 12:11:49.894721 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 12:11:49.901767 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3230 12:11:49.904744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:11:49.907806 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:11:49.914370 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:11:49.918035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:11:49.921120 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:11:49.927488 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:11:49.931298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:11:49.934450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:11:49.941312 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 12:11:49.944363 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 12:11:49.947545 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 12:11:49.954121 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 12:11:49.957672 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 12:11:49.961026 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 12:11:49.967287 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 12:11:49.970784 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3246 12:11:49.973749 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 12:11:49.977238 Total UI for P1: 0, mck2ui 16
3248 12:11:49.980523 best dqsien dly found for B0: ( 1, 3, 28)
3249 12:11:49.983963 Total UI for P1: 0, mck2ui 16
3250 12:11:49.987469 best dqsien dly found for B1: ( 1, 3, 28)
3251 12:11:49.990686 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3252 12:11:49.993926 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3253 12:11:49.994036
3254 12:11:50.000378 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3255 12:11:50.003766 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3256 12:11:50.003883 [Gating] SW calibration Done
3257 12:11:50.007130 ==
3258 12:11:50.010288 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 12:11:50.013968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 12:11:50.014105 ==
3261 12:11:50.014176 RX Vref Scan: 0
3262 12:11:50.014240
3263 12:11:50.017096 RX Vref 0 -> 0, step: 1
3264 12:11:50.017216
3265 12:11:50.020673 RX Delay -40 -> 252, step: 8
3266 12:11:50.023738 iDelay=200, Bit 0, Center 119 (40 ~ 199) 160
3267 12:11:50.026861 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3268 12:11:50.033577 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3269 12:11:50.037347 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3270 12:11:50.040365 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3271 12:11:50.043446 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3272 12:11:50.047359 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3273 12:11:50.053436 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3274 12:11:50.056600 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3275 12:11:50.060103 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3276 12:11:50.063765 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3277 12:11:50.066802 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3278 12:11:50.070603 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3279 12:11:50.076982 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3280 12:11:50.080135 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3281 12:11:50.083595 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3282 12:11:50.083792 ==
3283 12:11:50.087039 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 12:11:50.089934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 12:11:50.093427 ==
3286 12:11:50.093540 DQS Delay:
3287 12:11:50.093608 DQS0 = 0, DQS1 = 0
3288 12:11:50.096952 DQM Delay:
3289 12:11:50.097048 DQM0 = 113, DQM1 = 106
3290 12:11:50.100220 DQ Delay:
3291 12:11:50.103682 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3292 12:11:50.106566 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3293 12:11:50.110193 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3294 12:11:50.113130 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3295 12:11:50.113268
3296 12:11:50.113398
3297 12:11:50.113499 ==
3298 12:11:50.116644 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:11:50.119746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:11:50.119842 ==
3301 12:11:50.119910
3302 12:11:50.119976
3303 12:11:50.122900 TX Vref Scan disable
3304 12:11:50.126583 == TX Byte 0 ==
3305 12:11:50.129934 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3306 12:11:50.133240 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3307 12:11:50.136446 == TX Byte 1 ==
3308 12:11:50.139555 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3309 12:11:50.143404 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3310 12:11:50.143540 ==
3311 12:11:50.146295 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 12:11:50.153166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 12:11:50.153330 ==
3314 12:11:50.164181 TX Vref=22, minBit 3, minWin=25, winSum=418
3315 12:11:50.166885 TX Vref=24, minBit 1, minWin=26, winSum=422
3316 12:11:50.170685 TX Vref=26, minBit 1, minWin=26, winSum=428
3317 12:11:50.173876 TX Vref=28, minBit 1, minWin=26, winSum=432
3318 12:11:50.176970 TX Vref=30, minBit 1, minWin=26, winSum=432
3319 12:11:50.180825 TX Vref=32, minBit 9, minWin=25, winSum=425
3320 12:11:50.186936 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
3321 12:11:50.187094
3322 12:11:50.190693 Final TX Range 1 Vref 28
3323 12:11:50.190866
3324 12:11:50.190951 ==
3325 12:11:50.193678 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 12:11:50.197265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 12:11:50.197392 ==
3328 12:11:50.197462
3329 12:11:50.200414
3330 12:11:50.200506 TX Vref Scan disable
3331 12:11:50.203725 == TX Byte 0 ==
3332 12:11:50.207182 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3333 12:11:50.210237 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3334 12:11:50.213717 == TX Byte 1 ==
3335 12:11:50.217264 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3336 12:11:50.220139 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3337 12:11:50.220238
3338 12:11:50.223799 [DATLAT]
3339 12:11:50.223929 Freq=1200, CH1 RK0
3340 12:11:50.224035
3341 12:11:50.226980 DATLAT Default: 0xd
3342 12:11:50.227092 0, 0xFFFF, sum = 0
3343 12:11:50.230545 1, 0xFFFF, sum = 0
3344 12:11:50.230679 2, 0xFFFF, sum = 0
3345 12:11:50.233601 3, 0xFFFF, sum = 0
3346 12:11:50.233725 4, 0xFFFF, sum = 0
3347 12:11:50.237408 5, 0xFFFF, sum = 0
3348 12:11:50.240213 6, 0xFFFF, sum = 0
3349 12:11:50.240347 7, 0xFFFF, sum = 0
3350 12:11:50.243463 8, 0xFFFF, sum = 0
3351 12:11:50.243578 9, 0xFFFF, sum = 0
3352 12:11:50.246565 10, 0xFFFF, sum = 0
3353 12:11:50.246687 11, 0xFFFF, sum = 0
3354 12:11:50.250469 12, 0x0, sum = 1
3355 12:11:50.250588 13, 0x0, sum = 2
3356 12:11:50.253549 14, 0x0, sum = 3
3357 12:11:50.253657 15, 0x0, sum = 4
3358 12:11:50.256690 best_step = 13
3359 12:11:50.256801
3360 12:11:50.256911 ==
3361 12:11:50.259829 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 12:11:50.263642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 12:11:50.263770 ==
3364 12:11:50.263866 RX Vref Scan: 1
3365 12:11:50.263961
3366 12:11:50.266668 Set Vref Range= 32 -> 127
3367 12:11:50.266787
3368 12:11:50.269710 RX Vref 32 -> 127, step: 1
3369 12:11:50.269790
3370 12:11:50.273369 RX Delay -21 -> 252, step: 4
3371 12:11:50.273471
3372 12:11:50.276542 Set Vref, RX VrefLevel [Byte0]: 32
3373 12:11:50.279818 [Byte1]: 32
3374 12:11:50.279953
3375 12:11:50.283476 Set Vref, RX VrefLevel [Byte0]: 33
3376 12:11:50.286639 [Byte1]: 33
3377 12:11:50.289742
3378 12:11:50.289867 Set Vref, RX VrefLevel [Byte0]: 34
3379 12:11:50.293252 [Byte1]: 34
3380 12:11:50.298078
3381 12:11:50.298209 Set Vref, RX VrefLevel [Byte0]: 35
3382 12:11:50.301109 [Byte1]: 35
3383 12:11:50.305796
3384 12:11:50.305924 Set Vref, RX VrefLevel [Byte0]: 36
3385 12:11:50.309237 [Byte1]: 36
3386 12:11:50.313905
3387 12:11:50.314033 Set Vref, RX VrefLevel [Byte0]: 37
3388 12:11:50.317197 [Byte1]: 37
3389 12:11:50.321813
3390 12:11:50.321913 Set Vref, RX VrefLevel [Byte0]: 38
3391 12:11:50.325173 [Byte1]: 38
3392 12:11:50.329990
3393 12:11:50.330113 Set Vref, RX VrefLevel [Byte0]: 39
3394 12:11:50.332990 [Byte1]: 39
3395 12:11:50.337573
3396 12:11:50.337668 Set Vref, RX VrefLevel [Byte0]: 40
3397 12:11:50.340621 [Byte1]: 40
3398 12:11:50.345399
3399 12:11:50.348597 Set Vref, RX VrefLevel [Byte0]: 41
3400 12:11:50.348760 [Byte1]: 41
3401 12:11:50.353575
3402 12:11:50.353686 Set Vref, RX VrefLevel [Byte0]: 42
3403 12:11:50.356733 [Byte1]: 42
3404 12:11:50.361037
3405 12:11:50.361149 Set Vref, RX VrefLevel [Byte0]: 43
3406 12:11:50.364689 [Byte1]: 43
3407 12:11:50.369227
3408 12:11:50.369359 Set Vref, RX VrefLevel [Byte0]: 44
3409 12:11:50.372205 [Byte1]: 44
3410 12:11:50.377129
3411 12:11:50.377258 Set Vref, RX VrefLevel [Byte0]: 45
3412 12:11:50.380223 [Byte1]: 45
3413 12:11:50.385350
3414 12:11:50.385467 Set Vref, RX VrefLevel [Byte0]: 46
3415 12:11:50.388632 [Byte1]: 46
3416 12:11:50.392876
3417 12:11:50.392990 Set Vref, RX VrefLevel [Byte0]: 47
3418 12:11:50.395995 [Byte1]: 47
3419 12:11:50.400628
3420 12:11:50.400751 Set Vref, RX VrefLevel [Byte0]: 48
3421 12:11:50.404562 [Byte1]: 48
3422 12:11:50.408544
3423 12:11:50.408676 Set Vref, RX VrefLevel [Byte0]: 49
3424 12:11:50.412026 [Byte1]: 49
3425 12:11:50.416657
3426 12:11:50.416755 Set Vref, RX VrefLevel [Byte0]: 50
3427 12:11:50.420218 [Byte1]: 50
3428 12:11:50.424886
3429 12:11:50.425008 Set Vref, RX VrefLevel [Byte0]: 51
3430 12:11:50.427688 [Byte1]: 51
3431 12:11:50.432383
3432 12:11:50.432479 Set Vref, RX VrefLevel [Byte0]: 52
3433 12:11:50.435943 [Byte1]: 52
3434 12:11:50.440349
3435 12:11:50.440479 Set Vref, RX VrefLevel [Byte0]: 53
3436 12:11:50.446586 [Byte1]: 53
3437 12:11:50.446721
3438 12:11:50.450322 Set Vref, RX VrefLevel [Byte0]: 54
3439 12:11:50.453339 [Byte1]: 54
3440 12:11:50.453465
3441 12:11:50.456520 Set Vref, RX VrefLevel [Byte0]: 55
3442 12:11:50.460168 [Byte1]: 55
3443 12:11:50.464430
3444 12:11:50.464562 Set Vref, RX VrefLevel [Byte0]: 56
3445 12:11:50.467607 [Byte1]: 56
3446 12:11:50.471974
3447 12:11:50.472109 Set Vref, RX VrefLevel [Byte0]: 57
3448 12:11:50.475220 [Byte1]: 57
3449 12:11:50.479899
3450 12:11:50.480024 Set Vref, RX VrefLevel [Byte0]: 58
3451 12:11:50.483776 [Byte1]: 58
3452 12:11:50.488107
3453 12:11:50.488208 Set Vref, RX VrefLevel [Byte0]: 59
3454 12:11:50.491339 [Byte1]: 59
3455 12:11:50.495829
3456 12:11:50.495955 Set Vref, RX VrefLevel [Byte0]: 60
3457 12:11:50.499728 [Byte1]: 60
3458 12:11:50.503802
3459 12:11:50.503900 Set Vref, RX VrefLevel [Byte0]: 61
3460 12:11:50.507511 [Byte1]: 61
3461 12:11:50.511762
3462 12:11:50.511856 Set Vref, RX VrefLevel [Byte0]: 62
3463 12:11:50.515264 [Byte1]: 62
3464 12:11:50.519945
3465 12:11:50.520074 Set Vref, RX VrefLevel [Byte0]: 63
3466 12:11:50.522923 [Byte1]: 63
3467 12:11:50.527777
3468 12:11:50.527906 Set Vref, RX VrefLevel [Byte0]: 64
3469 12:11:50.530652 [Byte1]: 64
3470 12:11:50.535446
3471 12:11:50.535544 Set Vref, RX VrefLevel [Byte0]: 65
3472 12:11:50.539019 [Byte1]: 65
3473 12:11:50.543152
3474 12:11:50.546713 Final RX Vref Byte 0 = 55 to rank0
3475 12:11:50.546852 Final RX Vref Byte 1 = 50 to rank0
3476 12:11:50.549704 Final RX Vref Byte 0 = 55 to rank1
3477 12:11:50.552889 Final RX Vref Byte 1 = 50 to rank1==
3478 12:11:50.556619 Dram Type= 6, Freq= 0, CH_1, rank 0
3479 12:11:50.563442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 12:11:50.563563 ==
3481 12:11:50.563635 DQS Delay:
3482 12:11:50.566442 DQS0 = 0, DQS1 = 0
3483 12:11:50.566529 DQM Delay:
3484 12:11:50.566596 DQM0 = 114, DQM1 = 105
3485 12:11:50.569734 DQ Delay:
3486 12:11:50.572766 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3487 12:11:50.576450 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =112
3488 12:11:50.579518 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3489 12:11:50.583107 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3490 12:11:50.583194
3491 12:11:50.583264
3492 12:11:50.593045 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3493 12:11:50.593173 CH1 RK0: MR19=303, MR18=EFF6
3494 12:11:50.599227 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3495 12:11:50.599333
3496 12:11:50.602960 ----->DramcWriteLeveling(PI) begin...
3497 12:11:50.603080 ==
3498 12:11:50.606218 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 12:11:50.612971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 12:11:50.613092 ==
3501 12:11:50.616109 Write leveling (Byte 0): 25 => 25
3502 12:11:50.619252 Write leveling (Byte 1): 29 => 29
3503 12:11:50.619370 DramcWriteLeveling(PI) end<-----
3504 12:11:50.622703
3505 12:11:50.622819 ==
3506 12:11:50.625612 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 12:11:50.629233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 12:11:50.629386 ==
3509 12:11:50.632232 [Gating] SW mode calibration
3510 12:11:50.639196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3511 12:11:50.642112 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3512 12:11:50.648845 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 12:11:50.652563 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 12:11:50.655748 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 12:11:50.661950 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 12:11:50.665503 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 12:11:50.668606 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3518 12:11:50.675446 0 15 24 | B1->B0 | 3333 2727 | 1 0 | (1 0) (1 0)
3519 12:11:50.678629 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3520 12:11:50.681739 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 12:11:50.688396 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 12:11:50.691600 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 12:11:50.695394 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 12:11:50.702087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 12:11:50.705182 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
3526 12:11:50.708277 1 0 24 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
3527 12:11:50.714983 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 12:11:50.718177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 12:11:50.721377 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 12:11:50.728098 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 12:11:50.731531 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 12:11:50.735029 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 12:11:50.741480 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 12:11:50.744880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3535 12:11:50.747883 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3536 12:11:50.754424 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:11:50.758262 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:11:50.761301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:11:50.768132 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:11:50.771160 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:11:50.774117 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:11:50.780943 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:11:50.784148 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:11:50.787303 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:11:50.794050 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:11:50.797097 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:11:50.800716 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:11:50.806814 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 12:11:50.810515 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 12:11:50.813612 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3551 12:11:50.820165 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3552 12:11:50.823321 Total UI for P1: 0, mck2ui 16
3553 12:11:50.827121 best dqsien dly found for B0: ( 1, 3, 24)
3554 12:11:50.830305 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 12:11:50.833822 Total UI for P1: 0, mck2ui 16
3556 12:11:50.836721 best dqsien dly found for B1: ( 1, 3, 26)
3557 12:11:50.840292 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3558 12:11:50.843727 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3559 12:11:50.843859
3560 12:11:50.846540 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3561 12:11:50.853034 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3562 12:11:50.853167 [Gating] SW calibration Done
3563 12:11:50.853266 ==
3564 12:11:50.856640 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 12:11:50.863188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 12:11:50.863307 ==
3567 12:11:50.863379 RX Vref Scan: 0
3568 12:11:50.863443
3569 12:11:50.866219 RX Vref 0 -> 0, step: 1
3570 12:11:50.866308
3571 12:11:50.869943 RX Delay -40 -> 252, step: 8
3572 12:11:50.873230 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3573 12:11:50.876275 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3574 12:11:50.879830 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3575 12:11:50.886529 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3576 12:11:50.889675 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3577 12:11:50.892747 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3578 12:11:50.896251 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3579 12:11:50.899351 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3580 12:11:50.906341 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3581 12:11:50.909351 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3582 12:11:50.912620 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3583 12:11:50.915695 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3584 12:11:50.919174 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3585 12:11:50.926030 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3586 12:11:50.929244 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3587 12:11:50.932586 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3588 12:11:50.932702 ==
3589 12:11:50.936021 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 12:11:50.939091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 12:11:50.939215 ==
3592 12:11:50.942683 DQS Delay:
3593 12:11:50.942781 DQS0 = 0, DQS1 = 0
3594 12:11:50.945408 DQM Delay:
3595 12:11:50.945495 DQM0 = 110, DQM1 = 106
3596 12:11:50.948883 DQ Delay:
3597 12:11:50.952375 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3598 12:11:50.955791 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3599 12:11:50.958792 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3600 12:11:50.962440 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3601 12:11:50.962538
3602 12:11:50.962606
3603 12:11:50.962668 ==
3604 12:11:50.965429 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 12:11:50.968889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 12:11:50.968982 ==
3607 12:11:50.969070
3608 12:11:50.969133
3609 12:11:50.972022 TX Vref Scan disable
3610 12:11:50.975084 == TX Byte 0 ==
3611 12:11:50.978641 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3612 12:11:50.981618 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3613 12:11:50.985192 == TX Byte 1 ==
3614 12:11:50.988212 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3615 12:11:50.991883 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3616 12:11:50.991982 ==
3617 12:11:50.994979 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 12:11:51.001458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 12:11:51.001582 ==
3620 12:11:51.012272 TX Vref=22, minBit 0, minWin=26, winSum=425
3621 12:11:51.015513 TX Vref=24, minBit 0, minWin=26, winSum=429
3622 12:11:51.019029 TX Vref=26, minBit 8, minWin=26, winSum=432
3623 12:11:51.022168 TX Vref=28, minBit 8, minWin=26, winSum=434
3624 12:11:51.025167 TX Vref=30, minBit 1, minWin=26, winSum=434
3625 12:11:51.031881 TX Vref=32, minBit 8, minWin=25, winSum=432
3626 12:11:51.034977 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28
3627 12:11:51.035078
3628 12:11:51.038755 Final TX Range 1 Vref 28
3629 12:11:51.038877
3630 12:11:51.038945 ==
3631 12:11:51.041936 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 12:11:51.044910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 12:11:51.048482 ==
3634 12:11:51.048587
3635 12:11:51.048708
3636 12:11:51.048769 TX Vref Scan disable
3637 12:11:51.052022 == TX Byte 0 ==
3638 12:11:51.055489 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3639 12:11:51.061822 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3640 12:11:51.061933 == TX Byte 1 ==
3641 12:11:51.065329 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3642 12:11:51.071848 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3643 12:11:51.071993
3644 12:11:51.072064 [DATLAT]
3645 12:11:51.072145 Freq=1200, CH1 RK1
3646 12:11:51.072207
3647 12:11:51.074759 DATLAT Default: 0xd
3648 12:11:51.078336 0, 0xFFFF, sum = 0
3649 12:11:51.078425 1, 0xFFFF, sum = 0
3650 12:11:51.081381 2, 0xFFFF, sum = 0
3651 12:11:51.081462 3, 0xFFFF, sum = 0
3652 12:11:51.085062 4, 0xFFFF, sum = 0
3653 12:11:51.085153 5, 0xFFFF, sum = 0
3654 12:11:51.088113 6, 0xFFFF, sum = 0
3655 12:11:51.088277 7, 0xFFFF, sum = 0
3656 12:11:51.091150 8, 0xFFFF, sum = 0
3657 12:11:51.091247 9, 0xFFFF, sum = 0
3658 12:11:51.094754 10, 0xFFFF, sum = 0
3659 12:11:51.094888 11, 0xFFFF, sum = 0
3660 12:11:51.097967 12, 0x0, sum = 1
3661 12:11:51.098089 13, 0x0, sum = 2
3662 12:11:51.101166 14, 0x0, sum = 3
3663 12:11:51.101269 15, 0x0, sum = 4
3664 12:11:51.104808 best_step = 13
3665 12:11:51.104897
3666 12:11:51.104963 ==
3667 12:11:51.107736 Dram Type= 6, Freq= 0, CH_1, rank 1
3668 12:11:51.111439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3669 12:11:51.111609 ==
3670 12:11:51.114435 RX Vref Scan: 0
3671 12:11:51.114523
3672 12:11:51.114601 RX Vref 0 -> 0, step: 1
3673 12:11:51.114668
3674 12:11:51.117562 RX Delay -21 -> 252, step: 4
3675 12:11:51.124344 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3676 12:11:51.127966 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3677 12:11:51.130820 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3678 12:11:51.134039 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3679 12:11:51.137770 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3680 12:11:51.144087 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3681 12:11:51.147277 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3682 12:11:51.150389 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3683 12:11:51.154128 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3684 12:11:51.160242 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3685 12:11:51.163670 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3686 12:11:51.167033 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3687 12:11:51.170448 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3688 12:11:51.173497 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3689 12:11:51.179989 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3690 12:11:51.183655 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3691 12:11:51.183784 ==
3692 12:11:51.186669 Dram Type= 6, Freq= 0, CH_1, rank 1
3693 12:11:51.190251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3694 12:11:51.190377 ==
3695 12:11:51.193474 DQS Delay:
3696 12:11:51.193594 DQS0 = 0, DQS1 = 0
3697 12:11:51.193695 DQM Delay:
3698 12:11:51.196644 DQM0 = 111, DQM1 = 109
3699 12:11:51.196773 DQ Delay:
3700 12:11:51.200254 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3701 12:11:51.203334 DQ4 =112, DQ5 =118, DQ6 =120, DQ7 =110
3702 12:11:51.206509 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =102
3703 12:11:51.213172 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =116
3704 12:11:51.213311
3705 12:11:51.213413
3706 12:11:51.220067 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3707 12:11:51.223223 CH1 RK1: MR19=304, MR18=FB0A
3708 12:11:51.229525 CH1_RK1: MR19=0x304, MR18=0xFB0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3709 12:11:51.233115 [RxdqsGatingPostProcess] freq 1200
3710 12:11:51.236184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3711 12:11:51.239880 best DQS0 dly(2T, 0.5T) = (0, 11)
3712 12:11:51.243054 best DQS1 dly(2T, 0.5T) = (0, 11)
3713 12:11:51.246287 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3714 12:11:51.249502 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3715 12:11:51.253159 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 12:11:51.256436 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 12:11:51.259499 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 12:11:51.262549 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 12:11:51.266197 Pre-setting of DQS Precalculation
3720 12:11:51.272432 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3721 12:11:51.278965 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3722 12:11:51.285826 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3723 12:11:51.285983
3724 12:11:51.286090
3725 12:11:51.288849 [Calibration Summary] 2400 Mbps
3726 12:11:51.288957 CH 0, Rank 0
3727 12:11:51.292358 SW Impedance : PASS
3728 12:11:51.295936 DUTY Scan : NO K
3729 12:11:51.296033 ZQ Calibration : PASS
3730 12:11:51.299024 Jitter Meter : NO K
3731 12:11:51.302214 CBT Training : PASS
3732 12:11:51.302321 Write leveling : PASS
3733 12:11:51.305295 RX DQS gating : PASS
3734 12:11:51.308736 RX DQ/DQS(RDDQC) : PASS
3735 12:11:51.308829 TX DQ/DQS : PASS
3736 12:11:51.312353 RX DATLAT : PASS
3737 12:11:51.312455 RX DQ/DQS(Engine): PASS
3738 12:11:51.315435 TX OE : NO K
3739 12:11:51.315516 All Pass.
3740 12:11:51.315581
3741 12:11:51.318508 CH 0, Rank 1
3742 12:11:51.322113 SW Impedance : PASS
3743 12:11:51.322196 DUTY Scan : NO K
3744 12:11:51.325137 ZQ Calibration : PASS
3745 12:11:51.325213 Jitter Meter : NO K
3746 12:11:51.328442 CBT Training : PASS
3747 12:11:51.331584 Write leveling : PASS
3748 12:11:51.331661 RX DQS gating : PASS
3749 12:11:51.335265 RX DQ/DQS(RDDQC) : PASS
3750 12:11:51.338238 TX DQ/DQS : PASS
3751 12:11:51.338358 RX DATLAT : PASS
3752 12:11:51.342065 RX DQ/DQS(Engine): PASS
3753 12:11:51.345105 TX OE : NO K
3754 12:11:51.345231 All Pass.
3755 12:11:51.345332
3756 12:11:51.345424 CH 1, Rank 0
3757 12:11:51.348214 SW Impedance : PASS
3758 12:11:51.351572 DUTY Scan : NO K
3759 12:11:51.351695 ZQ Calibration : PASS
3760 12:11:51.354723 Jitter Meter : NO K
3761 12:11:51.358401 CBT Training : PASS
3762 12:11:51.358513 Write leveling : PASS
3763 12:11:51.361523 RX DQS gating : PASS
3764 12:11:51.364757 RX DQ/DQS(RDDQC) : PASS
3765 12:11:51.364876 TX DQ/DQS : PASS
3766 12:11:51.368223 RX DATLAT : PASS
3767 12:11:51.371133 RX DQ/DQS(Engine): PASS
3768 12:11:51.371262 TX OE : NO K
3769 12:11:51.374667 All Pass.
3770 12:11:51.374776
3771 12:11:51.374880 CH 1, Rank 1
3772 12:11:51.378185 SW Impedance : PASS
3773 12:11:51.378277 DUTY Scan : NO K
3774 12:11:51.381286 ZQ Calibration : PASS
3775 12:11:51.384745 Jitter Meter : NO K
3776 12:11:51.384840 CBT Training : PASS
3777 12:11:51.387738 Write leveling : PASS
3778 12:11:51.391169 RX DQS gating : PASS
3779 12:11:51.391266 RX DQ/DQS(RDDQC) : PASS
3780 12:11:51.394703 TX DQ/DQS : PASS
3781 12:11:51.394784 RX DATLAT : PASS
3782 12:11:51.397705 RX DQ/DQS(Engine): PASS
3783 12:11:51.401357 TX OE : NO K
3784 12:11:51.401451 All Pass.
3785 12:11:51.401521
3786 12:11:51.404477 DramC Write-DBI off
3787 12:11:51.404556 PER_BANK_REFRESH: Hybrid Mode
3788 12:11:51.407637 TX_TRACKING: ON
3789 12:11:51.417755 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3790 12:11:51.420825 [FAST_K] Save calibration result to emmc
3791 12:11:51.424520 dramc_set_vcore_voltage set vcore to 650000
3792 12:11:51.427687 Read voltage for 600, 5
3793 12:11:51.427790 Vio18 = 0
3794 12:11:51.427859 Vcore = 650000
3795 12:11:51.430807 Vdram = 0
3796 12:11:51.430932 Vddq = 0
3797 12:11:51.431029 Vmddr = 0
3798 12:11:51.437174 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3799 12:11:51.440848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3800 12:11:51.443898 MEM_TYPE=3, freq_sel=19
3801 12:11:51.447331 sv_algorithm_assistance_LP4_1600
3802 12:11:51.450550 ============ PULL DRAM RESETB DOWN ============
3803 12:11:51.453626 ========== PULL DRAM RESETB DOWN end =========
3804 12:11:51.460591 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3805 12:11:51.463657 ===================================
3806 12:11:51.463779 LPDDR4 DRAM CONFIGURATION
3807 12:11:51.466770 ===================================
3808 12:11:51.470527 EX_ROW_EN[0] = 0x0
3809 12:11:51.473589 EX_ROW_EN[1] = 0x0
3810 12:11:51.473699 LP4Y_EN = 0x0
3811 12:11:51.477029 WORK_FSP = 0x0
3812 12:11:51.477112 WL = 0x2
3813 12:11:51.479931 RL = 0x2
3814 12:11:51.480014 BL = 0x2
3815 12:11:51.483654 RPST = 0x0
3816 12:11:51.483775 RD_PRE = 0x0
3817 12:11:51.486550 WR_PRE = 0x1
3818 12:11:51.486679 WR_PST = 0x0
3819 12:11:51.489906 DBI_WR = 0x0
3820 12:11:51.490029 DBI_RD = 0x0
3821 12:11:51.493359 OTF = 0x1
3822 12:11:51.496883 ===================================
3823 12:11:51.499892 ===================================
3824 12:11:51.500014 ANA top config
3825 12:11:51.503421 ===================================
3826 12:11:51.506427 DLL_ASYNC_EN = 0
3827 12:11:51.509486 ALL_SLAVE_EN = 1
3828 12:11:51.513193 NEW_RANK_MODE = 1
3829 12:11:51.513336 DLL_IDLE_MODE = 1
3830 12:11:51.516471 LP45_APHY_COMB_EN = 1
3831 12:11:51.519588 TX_ODT_DIS = 1
3832 12:11:51.523086 NEW_8X_MODE = 1
3833 12:11:51.526566 ===================================
3834 12:11:51.529705 ===================================
3835 12:11:51.532818 data_rate = 1200
3836 12:11:51.535906 CKR = 1
3837 12:11:51.536020 DQ_P2S_RATIO = 8
3838 12:11:51.539680 ===================================
3839 12:11:51.542805 CA_P2S_RATIO = 8
3840 12:11:51.545870 DQ_CA_OPEN = 0
3841 12:11:51.549327 DQ_SEMI_OPEN = 0
3842 12:11:51.552425 CA_SEMI_OPEN = 0
3843 12:11:51.555593 CA_FULL_RATE = 0
3844 12:11:51.555710 DQ_CKDIV4_EN = 1
3845 12:11:51.559440 CA_CKDIV4_EN = 1
3846 12:11:51.562619 CA_PREDIV_EN = 0
3847 12:11:51.565772 PH8_DLY = 0
3848 12:11:51.568935 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3849 12:11:51.572648 DQ_AAMCK_DIV = 4
3850 12:11:51.572766 CA_AAMCK_DIV = 4
3851 12:11:51.575888 CA_ADMCK_DIV = 4
3852 12:11:51.578895 DQ_TRACK_CA_EN = 0
3853 12:11:51.581928 CA_PICK = 600
3854 12:11:51.585748 CA_MCKIO = 600
3855 12:11:51.588546 MCKIO_SEMI = 0
3856 12:11:51.592007 PLL_FREQ = 2288
3857 12:11:51.595445 DQ_UI_PI_RATIO = 32
3858 12:11:51.595568 CA_UI_PI_RATIO = 0
3859 12:11:51.598801 ===================================
3860 12:11:51.601805 ===================================
3861 12:11:51.605571 memory_type:LPDDR4
3862 12:11:51.608643 GP_NUM : 10
3863 12:11:51.608766 SRAM_EN : 1
3864 12:11:51.611890 MD32_EN : 0
3865 12:11:51.615089 ===================================
3866 12:11:51.618396 [ANA_INIT] >>>>>>>>>>>>>>
3867 12:11:51.621493 <<<<<< [CONFIGURE PHASE]: ANA_TX
3868 12:11:51.625217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3869 12:11:51.628168 ===================================
3870 12:11:51.628296 data_rate = 1200,PCW = 0X5800
3871 12:11:51.631667 ===================================
3872 12:11:51.634620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3873 12:11:51.641293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 12:11:51.648438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 12:11:51.651159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3876 12:11:51.654769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3877 12:11:51.657920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3878 12:11:51.661102 [ANA_INIT] flow start
3879 12:11:51.664157 [ANA_INIT] PLL >>>>>>>>
3880 12:11:51.664254 [ANA_INIT] PLL <<<<<<<<
3881 12:11:51.667983 [ANA_INIT] MIDPI >>>>>>>>
3882 12:11:51.671169 [ANA_INIT] MIDPI <<<<<<<<
3883 12:11:51.671290 [ANA_INIT] DLL >>>>>>>>
3884 12:11:51.674385 [ANA_INIT] flow end
3885 12:11:51.677463 ============ LP4 DIFF to SE enter ============
3886 12:11:51.684489 ============ LP4 DIFF to SE exit ============
3887 12:11:51.684647 [ANA_INIT] <<<<<<<<<<<<<
3888 12:11:51.687566 [Flow] Enable top DCM control >>>>>
3889 12:11:51.690472 [Flow] Enable top DCM control <<<<<
3890 12:11:51.694148 Enable DLL master slave shuffle
3891 12:11:51.700541 ==============================================================
3892 12:11:51.700688 Gating Mode config
3893 12:11:51.706942 ==============================================================
3894 12:11:51.710620 Config description:
3895 12:11:51.720707 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3896 12:11:51.727030 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3897 12:11:51.730068 SELPH_MODE 0: By rank 1: By Phase
3898 12:11:51.736968 ==============================================================
3899 12:11:51.739819 GAT_TRACK_EN = 1
3900 12:11:51.743807 RX_GATING_MODE = 2
3901 12:11:51.743931 RX_GATING_TRACK_MODE = 2
3902 12:11:51.746782 SELPH_MODE = 1
3903 12:11:51.749877 PICG_EARLY_EN = 1
3904 12:11:51.753024 VALID_LAT_VALUE = 1
3905 12:11:51.759696 ==============================================================
3906 12:11:51.763292 Enter into Gating configuration >>>>
3907 12:11:51.766427 Exit from Gating configuration <<<<
3908 12:11:51.770163 Enter into DVFS_PRE_config >>>>>
3909 12:11:51.779613 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3910 12:11:51.782706 Exit from DVFS_PRE_config <<<<<
3911 12:11:51.786050 Enter into PICG configuration >>>>
3912 12:11:51.789693 Exit from PICG configuration <<<<
3913 12:11:51.792892 [RX_INPUT] configuration >>>>>
3914 12:11:51.795960 [RX_INPUT] configuration <<<<<
3915 12:11:51.799624 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3916 12:11:51.805674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3917 12:11:51.812589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 12:11:51.819314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 12:11:51.825597 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 12:11:51.832547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 12:11:51.835580 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3922 12:11:51.838767 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3923 12:11:51.842499 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3924 12:11:51.845572 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3925 12:11:51.851795 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3926 12:11:51.855604 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 12:11:51.858727 ===================================
3928 12:11:51.862149 LPDDR4 DRAM CONFIGURATION
3929 12:11:51.865039 ===================================
3930 12:11:51.865153 EX_ROW_EN[0] = 0x0
3931 12:11:51.868264 EX_ROW_EN[1] = 0x0
3932 12:11:51.868343 LP4Y_EN = 0x0
3933 12:11:51.871487 WORK_FSP = 0x0
3934 12:11:51.875189 WL = 0x2
3935 12:11:51.875286 RL = 0x2
3936 12:11:51.878254 BL = 0x2
3937 12:11:51.878341 RPST = 0x0
3938 12:11:51.881555 RD_PRE = 0x0
3939 12:11:51.881645 WR_PRE = 0x1
3940 12:11:51.885120 WR_PST = 0x0
3941 12:11:51.885213 DBI_WR = 0x0
3942 12:11:51.888302 DBI_RD = 0x0
3943 12:11:51.888396 OTF = 0x1
3944 12:11:51.891448 ===================================
3945 12:11:51.894570 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3946 12:11:51.901434 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3947 12:11:51.904443 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3948 12:11:51.908083 ===================================
3949 12:11:51.911150 LPDDR4 DRAM CONFIGURATION
3950 12:11:51.914710 ===================================
3951 12:11:51.914849 EX_ROW_EN[0] = 0x10
3952 12:11:51.917513 EX_ROW_EN[1] = 0x0
3953 12:11:51.921022 LP4Y_EN = 0x0
3954 12:11:51.921112 WORK_FSP = 0x0
3955 12:11:51.924563 WL = 0x2
3956 12:11:51.924654 RL = 0x2
3957 12:11:51.927462 BL = 0x2
3958 12:11:51.927551 RPST = 0x0
3959 12:11:51.931001 RD_PRE = 0x0
3960 12:11:51.931120 WR_PRE = 0x1
3961 12:11:51.934197 WR_PST = 0x0
3962 12:11:51.934307 DBI_WR = 0x0
3963 12:11:51.937353 DBI_RD = 0x0
3964 12:11:51.937467 OTF = 0x1
3965 12:11:51.941104 ===================================
3966 12:11:51.947358 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3967 12:11:51.952053 nWR fixed to 30
3968 12:11:51.954895 [ModeRegInit_LP4] CH0 RK0
3969 12:11:51.955005 [ModeRegInit_LP4] CH0 RK1
3970 12:11:51.958408 [ModeRegInit_LP4] CH1 RK0
3971 12:11:51.961491 [ModeRegInit_LP4] CH1 RK1
3972 12:11:51.961612 match AC timing 17
3973 12:11:51.968593 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3974 12:11:51.971774 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3975 12:11:51.974929 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3976 12:11:51.981284 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3977 12:11:51.985204 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3978 12:11:51.985323 ==
3979 12:11:51.988268 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 12:11:51.991433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 12:11:51.991531 ==
3982 12:11:51.998307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 12:11:52.004441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3984 12:11:52.008066 [CA 0] Center 37 (7~67) winsize 61
3985 12:11:52.011164 [CA 1] Center 37 (7~67) winsize 61
3986 12:11:52.014162 [CA 2] Center 35 (5~65) winsize 61
3987 12:11:52.017439 [CA 3] Center 34 (4~65) winsize 62
3988 12:11:52.021410 [CA 4] Center 34 (4~65) winsize 62
3989 12:11:52.024347 [CA 5] Center 34 (4~64) winsize 61
3990 12:11:52.024468
3991 12:11:52.027445 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3992 12:11:52.027535
3993 12:11:52.030960 [CATrainingPosCal] consider 1 rank data
3994 12:11:52.034379 u2DelayCellTimex100 = 270/100 ps
3995 12:11:52.037444 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3996 12:11:52.040891 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3997 12:11:52.044155 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3998 12:11:52.050598 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3999 12:11:52.053906 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4000 12:11:52.057552 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4001 12:11:52.057659
4002 12:11:52.060625 CA PerBit enable=1, Macro0, CA PI delay=34
4003 12:11:52.060709
4004 12:11:52.063608 [CBTSetCACLKResult] CA Dly = 34
4005 12:11:52.063705 CS Dly: 6 (0~37)
4006 12:11:52.063775 ==
4007 12:11:52.067111 Dram Type= 6, Freq= 0, CH_0, rank 1
4008 12:11:52.073763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 12:11:52.073884 ==
4010 12:11:52.076936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4011 12:11:52.083298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4012 12:11:52.087305 [CA 0] Center 37 (7~67) winsize 61
4013 12:11:52.090504 [CA 1] Center 37 (7~67) winsize 61
4014 12:11:52.093655 [CA 2] Center 35 (5~65) winsize 61
4015 12:11:52.096815 [CA 3] Center 35 (5~65) winsize 61
4016 12:11:52.100141 [CA 4] Center 34 (4~65) winsize 62
4017 12:11:52.104273 [CA 5] Center 33 (3~64) winsize 62
4018 12:11:52.104406
4019 12:11:52.107230 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4020 12:11:52.107346
4021 12:11:52.110480 [CATrainingPosCal] consider 2 rank data
4022 12:11:52.113711 u2DelayCellTimex100 = 270/100 ps
4023 12:11:52.116855 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4024 12:11:52.123640 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4025 12:11:52.126938 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4026 12:11:52.130306 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4027 12:11:52.133407 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4028 12:11:52.136864 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4029 12:11:52.136972
4030 12:11:52.140497 CA PerBit enable=1, Macro0, CA PI delay=34
4031 12:11:52.140596
4032 12:11:52.143125 [CBTSetCACLKResult] CA Dly = 34
4033 12:11:52.146631 CS Dly: 6 (0~38)
4034 12:11:52.146724
4035 12:11:52.149535 ----->DramcWriteLeveling(PI) begin...
4036 12:11:52.149663 ==
4037 12:11:52.152906 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 12:11:52.156495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 12:11:52.156621 ==
4040 12:11:52.159804 Write leveling (Byte 0): 33 => 33
4041 12:11:52.163158 Write leveling (Byte 1): 30 => 30
4042 12:11:52.166244 DramcWriteLeveling(PI) end<-----
4043 12:11:52.166366
4044 12:11:52.166493 ==
4045 12:11:52.169788 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 12:11:52.172822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 12:11:52.172941 ==
4048 12:11:52.176274 [Gating] SW mode calibration
4049 12:11:52.182751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4050 12:11:52.189112 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4051 12:11:52.192348 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 12:11:52.195612 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 12:11:52.202651 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 12:11:52.205998 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4055 12:11:52.209217 0 9 16 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
4056 12:11:52.215551 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 12:11:52.218717 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 12:11:52.222021 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 12:11:52.228897 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 12:11:52.232132 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 12:11:52.235483 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 12:11:52.241950 0 10 12 | B1->B0 | 2828 2e2e | 1 1 | (0 0) (0 0)
4063 12:11:52.245451 0 10 16 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
4064 12:11:52.248354 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4065 12:11:52.254813 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 12:11:52.258333 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 12:11:52.261981 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 12:11:52.268258 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 12:11:52.271495 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 12:11:52.274974 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 12:11:52.281359 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4072 12:11:52.285018 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:11:52.287993 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:11:52.294722 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:11:52.298008 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:11:52.301134 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:11:52.308143 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:11:52.311350 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:11:52.314440 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:11:52.321018 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:11:52.324468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:11:52.327520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:11:52.334613 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:11:52.337838 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 12:11:52.340838 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 12:11:52.347498 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4087 12:11:52.350600 Total UI for P1: 0, mck2ui 16
4088 12:11:52.354286 best dqsien dly found for B0: ( 0, 13, 10)
4089 12:11:52.357390 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4090 12:11:52.360872 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 12:11:52.363910 Total UI for P1: 0, mck2ui 16
4092 12:11:52.367530 best dqsien dly found for B1: ( 0, 13, 16)
4093 12:11:52.370590 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4094 12:11:52.377586 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4095 12:11:52.377748
4096 12:11:52.380532 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4097 12:11:52.383870 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4098 12:11:52.387149 [Gating] SW calibration Done
4099 12:11:52.387252 ==
4100 12:11:52.390386 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 12:11:52.394113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 12:11:52.394230 ==
4103 12:11:52.397261 RX Vref Scan: 0
4104 12:11:52.397358
4105 12:11:52.397444 RX Vref 0 -> 0, step: 1
4106 12:11:52.397508
4107 12:11:52.400763 RX Delay -230 -> 252, step: 16
4108 12:11:52.403705 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4109 12:11:52.410140 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4110 12:11:52.413383 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4111 12:11:52.417351 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4112 12:11:52.420436 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4113 12:11:52.426716 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4114 12:11:52.429943 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4115 12:11:52.433027 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4116 12:11:52.436947 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4117 12:11:52.439559 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4118 12:11:52.446454 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4119 12:11:52.449514 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4120 12:11:52.453152 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4121 12:11:52.456142 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4122 12:11:52.462837 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4123 12:11:52.466481 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4124 12:11:52.466609 ==
4125 12:11:52.469477 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 12:11:52.473207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 12:11:52.473338 ==
4128 12:11:52.476221 DQS Delay:
4129 12:11:52.476333 DQS0 = 0, DQS1 = 0
4130 12:11:52.479454 DQM Delay:
4131 12:11:52.479567 DQM0 = 38, DQM1 = 29
4132 12:11:52.479666 DQ Delay:
4133 12:11:52.482560 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4134 12:11:52.486329 DQ4 =33, DQ5 =25, DQ6 =57, DQ7 =49
4135 12:11:52.489571 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4136 12:11:52.492761 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4137 12:11:52.492855
4138 12:11:52.492923
4139 12:11:52.495973 ==
4140 12:11:52.499160 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 12:11:52.502468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:11:52.502565 ==
4143 12:11:52.502648
4144 12:11:52.502713
4145 12:11:52.505529 TX Vref Scan disable
4146 12:11:52.505651 == TX Byte 0 ==
4147 12:11:52.512318 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4148 12:11:52.515369 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4149 12:11:52.515494 == TX Byte 1 ==
4150 12:11:52.522340 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4151 12:11:52.525584 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4152 12:11:52.525695 ==
4153 12:11:52.528730 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 12:11:52.531897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 12:11:52.532001 ==
4156 12:11:52.532073
4157 12:11:52.532136
4158 12:11:52.535219 TX Vref Scan disable
4159 12:11:52.538485 == TX Byte 0 ==
4160 12:11:52.541660 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4161 12:11:52.548764 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4162 12:11:52.548941 == TX Byte 1 ==
4163 12:11:52.551694 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4164 12:11:52.558405 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4165 12:11:52.558522
4166 12:11:52.558593 [DATLAT]
4167 12:11:52.558656 Freq=600, CH0 RK0
4168 12:11:52.558718
4169 12:11:52.561774 DATLAT Default: 0x9
4170 12:11:52.561852 0, 0xFFFF, sum = 0
4171 12:11:52.565205 1, 0xFFFF, sum = 0
4172 12:11:52.568058 2, 0xFFFF, sum = 0
4173 12:11:52.568144 3, 0xFFFF, sum = 0
4174 12:11:52.571544 4, 0xFFFF, sum = 0
4175 12:11:52.571628 5, 0xFFFF, sum = 0
4176 12:11:52.574615 6, 0xFFFF, sum = 0
4177 12:11:52.574732 7, 0xFFFF, sum = 0
4178 12:11:52.578153 8, 0x0, sum = 1
4179 12:11:52.578279 9, 0x0, sum = 2
4180 12:11:52.578376 10, 0x0, sum = 3
4181 12:11:52.581748 11, 0x0, sum = 4
4182 12:11:52.581856 best_step = 9
4183 12:11:52.581949
4184 12:11:52.584617 ==
4185 12:11:52.584735 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 12:11:52.591245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 12:11:52.591387 ==
4188 12:11:52.591488 RX Vref Scan: 1
4189 12:11:52.591580
4190 12:11:52.594503 RX Vref 0 -> 0, step: 1
4191 12:11:52.594612
4192 12:11:52.598390 RX Delay -195 -> 252, step: 8
4193 12:11:52.598500
4194 12:11:52.601526 Set Vref, RX VrefLevel [Byte0]: 62
4195 12:11:52.604697 [Byte1]: 47
4196 12:11:52.604839
4197 12:11:52.607924 Final RX Vref Byte 0 = 62 to rank0
4198 12:11:52.610962 Final RX Vref Byte 1 = 47 to rank0
4199 12:11:52.614462 Final RX Vref Byte 0 = 62 to rank1
4200 12:11:52.617920 Final RX Vref Byte 1 = 47 to rank1==
4201 12:11:52.621213 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 12:11:52.624111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 12:11:52.627976 ==
4204 12:11:52.628102 DQS Delay:
4205 12:11:52.628222 DQS0 = 0, DQS1 = 0
4206 12:11:52.631046 DQM Delay:
4207 12:11:52.631161 DQM0 = 34, DQM1 = 29
4208 12:11:52.634326 DQ Delay:
4209 12:11:52.637493 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4210 12:11:52.637605 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4211 12:11:52.640714 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4212 12:11:52.644376 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =40
4213 12:11:52.647464
4214 12:11:52.647579
4215 12:11:52.654273 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4216 12:11:52.657190 CH0 RK0: MR19=808, MR18=3E3E
4217 12:11:52.663621 CH0_RK0: MR19=0x808, MR18=0x3E3E, DQSOSC=398, MR23=63, INC=165, DEC=110
4218 12:11:52.663796
4219 12:11:52.667094 ----->DramcWriteLeveling(PI) begin...
4220 12:11:52.667201 ==
4221 12:11:52.670467 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 12:11:52.673692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 12:11:52.673815 ==
4224 12:11:52.677371 Write leveling (Byte 0): 34 => 34
4225 12:11:52.680577 Write leveling (Byte 1): 31 => 31
4226 12:11:52.683586 DramcWriteLeveling(PI) end<-----
4227 12:11:52.683723
4228 12:11:52.683789 ==
4229 12:11:52.687144 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 12:11:52.689954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 12:11:52.690130 ==
4232 12:11:52.693608 [Gating] SW mode calibration
4233 12:11:52.700482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4234 12:11:52.706687 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4235 12:11:52.709841 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 12:11:52.716197 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 12:11:52.719890 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 12:11:52.723113 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4239 12:11:52.729734 0 9 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
4240 12:11:52.732752 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 12:11:52.736482 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 12:11:52.742798 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 12:11:52.745989 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 12:11:52.749325 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 12:11:52.755659 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 12:11:52.758856 0 10 12 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)
4247 12:11:52.762510 0 10 16 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
4248 12:11:52.768888 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 12:11:52.772230 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 12:11:52.775459 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 12:11:52.781933 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 12:11:52.785532 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 12:11:52.788848 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 12:11:52.795350 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4255 12:11:52.798836 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:11:52.801766 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:11:52.808418 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:11:52.811796 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:11:52.815538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:11:52.821939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:11:52.825168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:11:52.828345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:11:52.834990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:11:52.838040 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:11:53.127796 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:11:53.128263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:11:53.128402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:11:53.128515 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 12:11:53.128626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4270 12:11:53.128734 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4271 12:11:53.128843 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 12:11:53.128956 Total UI for P1: 0, mck2ui 16
4273 12:11:53.129066 best dqsien dly found for B0: ( 0, 13, 10)
4274 12:11:53.129172 Total UI for P1: 0, mck2ui 16
4275 12:11:53.129279 best dqsien dly found for B1: ( 0, 13, 14)
4276 12:11:53.129388 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4277 12:11:53.129487 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4278 12:11:53.129590
4279 12:11:53.129694 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4280 12:11:53.129799 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4281 12:11:53.129910 [Gating] SW calibration Done
4282 12:11:53.130019 ==
4283 12:11:53.130120 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 12:11:53.130217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 12:11:53.130321 ==
4286 12:11:53.130423 RX Vref Scan: 0
4287 12:11:53.130526
4288 12:11:53.130628 RX Vref 0 -> 0, step: 1
4289 12:11:53.130730
4290 12:11:53.130845 RX Delay -230 -> 252, step: 16
4291 12:11:53.130950 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4292 12:11:53.131055 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4293 12:11:53.131166 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4294 12:11:53.131272 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4295 12:11:53.131381 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4296 12:11:53.131478 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4297 12:11:53.131579 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4298 12:11:53.131682 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4299 12:11:53.131785 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4300 12:11:53.131888 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4301 12:11:53.131992 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4302 12:11:53.132095 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4303 12:11:53.132199 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4304 12:11:53.132303 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4305 12:11:53.132407 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4306 12:11:53.132513 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4307 12:11:53.132621 ==
4308 12:11:53.132745 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 12:11:53.132848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 12:11:53.132951 ==
4311 12:11:53.133051 DQS Delay:
4312 12:11:53.133151 DQS0 = 0, DQS1 = 0
4313 12:11:53.133251 DQM Delay:
4314 12:11:53.133353 DQM0 = 40, DQM1 = 32
4315 12:11:53.133474 DQ Delay:
4316 12:11:53.133604 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4317 12:11:53.133732 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4318 12:11:53.133847 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4319 12:11:53.133948 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4320 12:11:53.134039
4321 12:11:53.134137
4322 12:11:53.134234 ==
4323 12:11:53.134331 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 12:11:53.134428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 12:11:53.134525 ==
4326 12:11:53.134621
4327 12:11:53.134716
4328 12:11:53.134811 TX Vref Scan disable
4329 12:11:53.134915 == TX Byte 0 ==
4330 12:11:53.135041 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4331 12:11:53.135137 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4332 12:11:53.135232 == TX Byte 1 ==
4333 12:11:53.135385 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4334 12:11:53.135480 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4335 12:11:53.135566 ==
4336 12:11:53.135642 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 12:11:53.135718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 12:11:53.135814 ==
4339 12:11:53.135889
4340 12:11:53.135983
4341 12:11:53.136078 TX Vref Scan disable
4342 12:11:53.136173 == TX Byte 0 ==
4343 12:11:53.136268 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4344 12:11:53.136363 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4345 12:11:53.136458 == TX Byte 1 ==
4346 12:11:53.136552 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4347 12:11:53.136646 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4348 12:11:53.136740
4349 12:11:53.136834 [DATLAT]
4350 12:11:53.136928 Freq=600, CH0 RK1
4351 12:11:53.137023
4352 12:11:53.137116 DATLAT Default: 0x9
4353 12:11:53.137210 0, 0xFFFF, sum = 0
4354 12:11:53.137306 1, 0xFFFF, sum = 0
4355 12:11:53.137403 2, 0xFFFF, sum = 0
4356 12:11:53.137498 3, 0xFFFF, sum = 0
4357 12:11:53.137594 4, 0xFFFF, sum = 0
4358 12:11:53.137689 5, 0xFFFF, sum = 0
4359 12:11:53.137785 6, 0xFFFF, sum = 0
4360 12:11:53.137880 7, 0xFFFF, sum = 0
4361 12:11:53.137978 8, 0x0, sum = 1
4362 12:11:53.138072 9, 0x0, sum = 2
4363 12:11:53.138172 10, 0x0, sum = 3
4364 12:11:53.138265 11, 0x0, sum = 4
4365 12:11:53.138353 best_step = 9
4366 12:11:53.138438
4367 12:11:53.138523 ==
4368 12:11:53.138606 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 12:11:53.138691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 12:11:53.138774 ==
4371 12:11:53.138866 RX Vref Scan: 0
4372 12:11:53.138951
4373 12:11:53.139033 RX Vref 0 -> 0, step: 1
4374 12:11:53.139116
4375 12:11:53.139198 RX Delay -195 -> 252, step: 8
4376 12:11:53.139281 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4377 12:11:53.139363 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4378 12:11:53.139444 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4379 12:11:53.139526 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4380 12:11:53.139635 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4381 12:11:53.139722 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4382 12:11:53.141152 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4383 12:11:53.144773 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4384 12:11:53.147862 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4385 12:11:53.154064 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4386 12:11:53.157900 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4387 12:11:53.161197 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4388 12:11:53.164152 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4389 12:11:53.170529 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4390 12:11:53.174437 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4391 12:11:53.177507 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4392 12:11:53.177604 ==
4393 12:11:53.180789 Dram Type= 6, Freq= 0, CH_0, rank 1
4394 12:11:53.184018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 12:11:53.187507 ==
4396 12:11:53.187652 DQS Delay:
4397 12:11:53.187749 DQS0 = 0, DQS1 = 0
4398 12:11:53.190715 DQM Delay:
4399 12:11:53.190838 DQM0 = 34, DQM1 = 28
4400 12:11:53.194062 DQ Delay:
4401 12:11:53.194164 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4402 12:11:53.197217 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4403 12:11:53.200255 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4404 12:11:53.203947 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4405 12:11:53.207181
4406 12:11:53.207390
4407 12:11:53.213861 [DQSOSCAuto] RK1, (LSB)MR18= 0x6938, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4408 12:11:53.217034 CH0 RK1: MR19=808, MR18=6938
4409 12:11:53.223670 CH0_RK1: MR19=0x808, MR18=0x6938, DQSOSC=390, MR23=63, INC=172, DEC=114
4410 12:11:53.226926 [RxdqsGatingPostProcess] freq 600
4411 12:11:53.229833 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4412 12:11:53.233491 Pre-setting of DQS Precalculation
4413 12:11:53.240175 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4414 12:11:53.240319 ==
4415 12:11:53.243242 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 12:11:53.246349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 12:11:53.246442 ==
4418 12:11:53.253108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 12:11:53.259861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4420 12:11:53.263167 [CA 0] Center 36 (6~66) winsize 61
4421 12:11:53.266232 [CA 1] Center 35 (5~66) winsize 62
4422 12:11:53.269489 [CA 2] Center 34 (4~65) winsize 62
4423 12:11:53.272814 [CA 3] Center 34 (3~65) winsize 63
4424 12:11:53.275982 [CA 4] Center 34 (4~65) winsize 62
4425 12:11:53.279113 [CA 5] Center 33 (3~64) winsize 62
4426 12:11:53.279236
4427 12:11:53.282964 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4428 12:11:53.283092
4429 12:11:53.286132 [CATrainingPosCal] consider 1 rank data
4430 12:11:53.289359 u2DelayCellTimex100 = 270/100 ps
4431 12:11:53.292547 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 12:11:53.295822 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4433 12:11:53.299086 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 12:11:53.302102 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4435 12:11:53.305541 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 12:11:53.309094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 12:11:53.309218
4438 12:11:53.315406 CA PerBit enable=1, Macro0, CA PI delay=33
4439 12:11:53.315537
4440 12:11:53.318982 [CBTSetCACLKResult] CA Dly = 33
4441 12:11:53.319097 CS Dly: 3 (0~34)
4442 12:11:53.319191 ==
4443 12:11:53.321891 Dram Type= 6, Freq= 0, CH_1, rank 1
4444 12:11:53.325434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 12:11:53.325548 ==
4446 12:11:53.332021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4447 12:11:53.338402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4448 12:11:53.341966 [CA 0] Center 36 (6~66) winsize 61
4449 12:11:53.345421 [CA 1] Center 36 (6~67) winsize 62
4450 12:11:53.348093 [CA 2] Center 34 (4~65) winsize 62
4451 12:11:53.351908 [CA 3] Center 34 (3~65) winsize 63
4452 12:11:53.354806 [CA 4] Center 34 (4~65) winsize 62
4453 12:11:53.358482 [CA 5] Center 34 (3~65) winsize 63
4454 12:11:53.358596
4455 12:11:53.361546 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4456 12:11:53.361664
4457 12:11:53.364699 [CATrainingPosCal] consider 2 rank data
4458 12:11:53.368539 u2DelayCellTimex100 = 270/100 ps
4459 12:11:53.371665 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4460 12:11:53.374685 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4461 12:11:53.377910 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 12:11:53.384794 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4463 12:11:53.387779 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 12:11:53.391444 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4465 12:11:53.391570
4466 12:11:53.394476 CA PerBit enable=1, Macro0, CA PI delay=33
4467 12:11:53.394593
4468 12:11:53.397681 [CBTSetCACLKResult] CA Dly = 33
4469 12:11:53.397796 CS Dly: 4 (0~36)
4470 12:11:53.397893
4471 12:11:53.400916 ----->DramcWriteLeveling(PI) begin...
4472 12:11:53.404700 ==
4473 12:11:53.407714 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 12:11:53.411212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 12:11:53.411346 ==
4476 12:11:53.414281 Write leveling (Byte 0): 28 => 28
4477 12:11:53.417604 Write leveling (Byte 1): 29 => 29
4478 12:11:53.420668 DramcWriteLeveling(PI) end<-----
4479 12:11:53.420786
4480 12:11:53.420884 ==
4481 12:11:53.424390 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 12:11:53.427235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 12:11:53.427347 ==
4484 12:11:53.430716 [Gating] SW mode calibration
4485 12:11:53.437187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4486 12:11:53.443844 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4487 12:11:53.447393 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 12:11:53.450457 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 12:11:53.457203 0 9 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
4490 12:11:53.460220 0 9 12 | B1->B0 | 3333 3131 | 0 0 | (0 1) (0 1)
4491 12:11:53.463456 0 9 16 | B1->B0 | 2626 2727 | 0 0 | (0 0) (1 0)
4492 12:11:53.470198 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 12:11:53.473344 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 12:11:53.476940 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 12:11:53.483272 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 12:11:53.487150 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 12:11:53.490019 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 12:11:53.496582 0 10 12 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
4499 12:11:53.499684 0 10 16 | B1->B0 | 3c3c 3f3f | 0 0 | (0 0) (0 0)
4500 12:11:53.503410 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 12:11:53.510067 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 12:11:53.513194 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 12:11:53.516192 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 12:11:53.523008 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 12:11:53.526212 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 12:11:53.529949 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4507 12:11:53.536494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4508 12:11:53.539508 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:11:53.542941 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:11:53.549570 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:11:53.553159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:11:53.556101 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:11:53.562621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:11:53.566122 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:11:53.569343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:11:53.575608 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:11:53.579287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:11:53.582426 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:11:53.589368 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:11:53.592435 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:11:53.595444 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 12:11:53.602183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4523 12:11:53.605347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 12:11:53.609005 Total UI for P1: 0, mck2ui 16
4525 12:11:53.612046 best dqsien dly found for B0: ( 0, 13, 12)
4526 12:11:53.615738 Total UI for P1: 0, mck2ui 16
4527 12:11:53.618733 best dqsien dly found for B1: ( 0, 13, 12)
4528 12:11:53.622314 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4529 12:11:53.625418 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4530 12:11:53.625530
4531 12:11:53.628649 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4532 12:11:53.632305 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4533 12:11:53.635386 [Gating] SW calibration Done
4534 12:11:53.635504 ==
4535 12:11:53.638617 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 12:11:53.641752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 12:11:53.645178 ==
4538 12:11:53.645281 RX Vref Scan: 0
4539 12:11:53.645373
4540 12:11:53.648497 RX Vref 0 -> 0, step: 1
4541 12:11:53.648605
4542 12:11:53.651386 RX Delay -230 -> 252, step: 16
4543 12:11:53.654751 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4544 12:11:53.658151 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4545 12:11:53.661645 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4546 12:11:53.668403 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4547 12:11:53.671489 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4548 12:11:53.674935 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4549 12:11:53.677780 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4550 12:11:53.681520 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4551 12:11:53.687703 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4552 12:11:53.690851 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4553 12:11:53.694597 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4554 12:11:53.697618 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4555 12:11:53.704300 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4556 12:11:53.708148 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4557 12:11:53.711284 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4558 12:11:53.714119 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4559 12:11:53.717945 ==
4560 12:11:53.721069 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 12:11:53.723909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 12:11:53.724031 ==
4563 12:11:53.724131 DQS Delay:
4564 12:11:53.727373 DQS0 = 0, DQS1 = 0
4565 12:11:53.727482 DQM Delay:
4566 12:11:53.730487 DQM0 = 38, DQM1 = 30
4567 12:11:53.730595 DQ Delay:
4568 12:11:53.734175 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4569 12:11:53.737456 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4570 12:11:53.740409 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4571 12:11:53.743602 DQ12 =41, DQ13 =41, DQ14 =33, DQ15 =33
4572 12:11:53.743710
4573 12:11:53.743805
4574 12:11:53.743901 ==
4575 12:11:53.747374 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 12:11:53.750432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 12:11:53.750548 ==
4578 12:11:53.750645
4579 12:11:53.753480
4580 12:11:53.753589 TX Vref Scan disable
4581 12:11:53.757013 == TX Byte 0 ==
4582 12:11:53.760491 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4583 12:11:53.763334 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4584 12:11:53.766793 == TX Byte 1 ==
4585 12:11:53.770388 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4586 12:11:53.773398 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4587 12:11:53.773516 ==
4588 12:11:53.776641 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 12:11:53.782989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 12:11:53.783101 ==
4591 12:11:53.783173
4592 12:11:53.783250
4593 12:11:53.786293 TX Vref Scan disable
4594 12:11:53.786406 == TX Byte 0 ==
4595 12:11:53.793160 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 12:11:53.796275 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 12:11:53.796399 == TX Byte 1 ==
4598 12:11:53.803073 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4599 12:11:53.806490 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4600 12:11:53.806609
4601 12:11:53.806705 [DATLAT]
4602 12:11:53.809710 Freq=600, CH1 RK0
4603 12:11:53.809824
4604 12:11:53.809920 DATLAT Default: 0x9
4605 12:11:53.812957 0, 0xFFFF, sum = 0
4606 12:11:53.813074 1, 0xFFFF, sum = 0
4607 12:11:53.816526 2, 0xFFFF, sum = 0
4608 12:11:53.816618 3, 0xFFFF, sum = 0
4609 12:11:53.819612 4, 0xFFFF, sum = 0
4610 12:11:53.823538 5, 0xFFFF, sum = 0
4611 12:11:53.823633 6, 0xFFFF, sum = 0
4612 12:11:53.826454 7, 0xFFFF, sum = 0
4613 12:11:53.826571 8, 0x0, sum = 1
4614 12:11:53.826670 9, 0x0, sum = 2
4615 12:11:53.829459 10, 0x0, sum = 3
4616 12:11:53.829549 11, 0x0, sum = 4
4617 12:11:53.833048 best_step = 9
4618 12:11:53.833138
4619 12:11:53.833207 ==
4620 12:11:53.836145 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 12:11:53.839468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 12:11:53.839559 ==
4623 12:11:53.843074 RX Vref Scan: 1
4624 12:11:53.843202
4625 12:11:53.843297 RX Vref 0 -> 0, step: 1
4626 12:11:53.843388
4627 12:11:53.846218 RX Delay -195 -> 252, step: 8
4628 12:11:53.846305
4629 12:11:53.849333 Set Vref, RX VrefLevel [Byte0]: 55
4630 12:11:53.852999 [Byte1]: 50
4631 12:11:53.856683
4632 12:11:53.856776 Final RX Vref Byte 0 = 55 to rank0
4633 12:11:53.860360 Final RX Vref Byte 1 = 50 to rank0
4634 12:11:53.863186 Final RX Vref Byte 0 = 55 to rank1
4635 12:11:53.866724 Final RX Vref Byte 1 = 50 to rank1==
4636 12:11:53.870116 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 12:11:53.876829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 12:11:53.876940 ==
4639 12:11:53.877012 DQS Delay:
4640 12:11:53.879824 DQS0 = 0, DQS1 = 0
4641 12:11:53.879911 DQM Delay:
4642 12:11:53.880000 DQM0 = 39, DQM1 = 28
4643 12:11:53.883117 DQ Delay:
4644 12:11:53.886283 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4645 12:11:53.889913 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4646 12:11:53.892950 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4647 12:11:53.896500 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4648 12:11:53.896586
4649 12:11:53.896652
4650 12:11:53.903243 [DQSOSCAuto] RK0, (LSB)MR18= 0x2633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4651 12:11:53.906279 CH1 RK0: MR19=808, MR18=2633
4652 12:11:53.912904 CH1_RK0: MR19=0x808, MR18=0x2633, DQSOSC=400, MR23=63, INC=163, DEC=109
4653 12:11:53.913005
4654 12:11:53.915939 ----->DramcWriteLeveling(PI) begin...
4655 12:11:53.916023 ==
4656 12:11:53.919638 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 12:11:53.922731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 12:11:53.922842 ==
4659 12:11:53.925942 Write leveling (Byte 0): 31 => 31
4660 12:11:53.928995 Write leveling (Byte 1): 31 => 31
4661 12:11:53.932611 DramcWriteLeveling(PI) end<-----
4662 12:11:53.932721
4663 12:11:53.932813 ==
4664 12:11:53.935631 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 12:11:53.942757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 12:11:53.942907 ==
4667 12:11:53.942978 [Gating] SW mode calibration
4668 12:11:53.952515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4669 12:11:53.955568 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4670 12:11:53.958625 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 12:11:53.965406 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 12:11:53.968938 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4673 12:11:53.972215 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 0)
4674 12:11:53.978683 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4675 12:11:53.982229 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 12:11:53.985202 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 12:11:53.991984 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 12:11:53.994990 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 12:11:53.998526 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 12:11:54.005003 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4681 12:11:54.008649 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
4682 12:11:54.011819 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4683 12:11:54.018476 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 12:11:54.021619 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 12:11:54.024815 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 12:11:54.031359 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 12:11:54.034887 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 12:11:54.038230 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 12:11:54.044511 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4690 12:11:54.047782 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4691 12:11:54.050881 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:11:54.057654 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:11:54.060856 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:11:54.064515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:11:54.070635 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:11:54.074401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:11:54.080311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:11:54.083910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:11:54.087435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:11:54.094008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:11:54.097025 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:11:54.100059 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:11:54.107217 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:11:54.110259 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:11:54.113318 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4706 12:11:54.116886 Total UI for P1: 0, mck2ui 16
4707 12:11:54.119885 best dqsien dly found for B0: ( 0, 13, 10)
4708 12:11:54.126732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 12:11:54.126923 Total UI for P1: 0, mck2ui 16
4710 12:11:54.129983 best dqsien dly found for B1: ( 0, 13, 12)
4711 12:11:54.136263 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4712 12:11:54.140151 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4713 12:11:54.140294
4714 12:11:54.143124 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4715 12:11:54.146194 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4716 12:11:54.149894 [Gating] SW calibration Done
4717 12:11:54.150029 ==
4718 12:11:54.153006 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 12:11:54.156220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 12:11:54.156354 ==
4721 12:11:54.159226 RX Vref Scan: 0
4722 12:11:54.159346
4723 12:11:54.159457 RX Vref 0 -> 0, step: 1
4724 12:11:54.162386
4725 12:11:54.162500 RX Delay -230 -> 252, step: 16
4726 12:11:54.169273 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4727 12:11:54.172483 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4728 12:11:54.175566 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4729 12:11:54.179506 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4730 12:11:54.185670 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4731 12:11:54.189274 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4732 12:11:54.192525 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4733 12:11:54.195548 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4734 12:11:54.199177 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4735 12:11:54.205781 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4736 12:11:54.208843 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4737 12:11:54.212360 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4738 12:11:54.215357 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4739 12:11:54.222007 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4740 12:11:54.225485 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4741 12:11:54.229077 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4742 12:11:54.229194 ==
4743 12:11:54.232124 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 12:11:54.235325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 12:11:54.239009 ==
4746 12:11:54.239094 DQS Delay:
4747 12:11:54.239162 DQS0 = 0, DQS1 = 0
4748 12:11:54.242189 DQM Delay:
4749 12:11:54.242265 DQM0 = 34, DQM1 = 29
4750 12:11:54.245316 DQ Delay:
4751 12:11:54.248943 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4752 12:11:54.249024 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4753 12:11:54.252009 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4754 12:11:54.255017 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4755 12:11:54.258780
4756 12:11:54.258878
4757 12:11:54.258946 ==
4758 12:11:54.262064 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 12:11:54.265201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 12:11:54.265288 ==
4761 12:11:54.265356
4762 12:11:54.265419
4763 12:11:54.268294 TX Vref Scan disable
4764 12:11:54.268384 == TX Byte 0 ==
4765 12:11:54.275232 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4766 12:11:54.278418 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4767 12:11:54.278504 == TX Byte 1 ==
4768 12:11:54.284874 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4769 12:11:54.287946 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4770 12:11:54.288072 ==
4771 12:11:54.291559 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 12:11:54.294951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 12:11:54.295038 ==
4774 12:11:54.295106
4775 12:11:54.297747
4776 12:11:54.297821 TX Vref Scan disable
4777 12:11:54.301379 == TX Byte 0 ==
4778 12:11:54.305065 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4779 12:11:54.311756 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4780 12:11:54.311839 == TX Byte 1 ==
4781 12:11:54.314744 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4782 12:11:54.321196 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4783 12:11:54.321282
4784 12:11:54.321349 [DATLAT]
4785 12:11:54.321409 Freq=600, CH1 RK1
4786 12:11:54.321469
4787 12:11:54.324797 DATLAT Default: 0x9
4788 12:11:54.324907 0, 0xFFFF, sum = 0
4789 12:11:54.328115 1, 0xFFFF, sum = 0
4790 12:11:54.331101 2, 0xFFFF, sum = 0
4791 12:11:54.331186 3, 0xFFFF, sum = 0
4792 12:11:54.334685 4, 0xFFFF, sum = 0
4793 12:11:54.334771 5, 0xFFFF, sum = 0
4794 12:11:54.337907 6, 0xFFFF, sum = 0
4795 12:11:54.337993 7, 0xFFFF, sum = 0
4796 12:11:54.341059 8, 0x0, sum = 1
4797 12:11:54.341143 9, 0x0, sum = 2
4798 12:11:54.341212 10, 0x0, sum = 3
4799 12:11:54.344142 11, 0x0, sum = 4
4800 12:11:54.344227 best_step = 9
4801 12:11:54.344294
4802 12:11:54.347778 ==
4803 12:11:54.347867 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 12:11:54.354484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 12:11:54.354610 ==
4806 12:11:54.354708 RX Vref Scan: 0
4807 12:11:54.354799
4808 12:11:54.357596 RX Vref 0 -> 0, step: 1
4809 12:11:54.357675
4810 12:11:54.360651 RX Delay -195 -> 252, step: 8
4811 12:11:54.367473 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4812 12:11:54.370677 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4813 12:11:54.374239 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4814 12:11:54.377358 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4815 12:11:54.380460 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4816 12:11:54.387438 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4817 12:11:54.390649 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4818 12:11:54.393683 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4819 12:11:54.397323 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4820 12:11:54.403806 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4821 12:11:54.406788 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4822 12:11:54.410436 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4823 12:11:54.413849 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4824 12:11:54.420261 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4825 12:11:54.423350 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4826 12:11:54.426938 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4827 12:11:54.427027 ==
4828 12:11:54.430464 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 12:11:54.433256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 12:11:54.436884 ==
4831 12:11:54.436965 DQS Delay:
4832 12:11:54.437032 DQS0 = 0, DQS1 = 0
4833 12:11:54.439935 DQM Delay:
4834 12:11:54.440019 DQM0 = 36, DQM1 = 30
4835 12:11:54.443558 DQ Delay:
4836 12:11:54.443675 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4837 12:11:54.446758 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4838 12:11:54.449860 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4839 12:11:54.453411 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =36
4840 12:11:54.456346
4841 12:11:54.456432
4842 12:11:54.463046 [DQSOSCAuto] RK1, (LSB)MR18= 0x3556, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4843 12:11:54.466097 CH1 RK1: MR19=808, MR18=3556
4844 12:11:54.473077 CH1_RK1: MR19=0x808, MR18=0x3556, DQSOSC=393, MR23=63, INC=169, DEC=113
4845 12:11:54.476144 [RxdqsGatingPostProcess] freq 600
4846 12:11:54.479824 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4847 12:11:54.482934 Pre-setting of DQS Precalculation
4848 12:11:54.489313 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4849 12:11:54.496159 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4850 12:11:54.502371 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4851 12:11:54.502459
4852 12:11:54.502527
4853 12:11:54.506012 [Calibration Summary] 1200 Mbps
4854 12:11:54.506106 CH 0, Rank 0
4855 12:11:54.509079 SW Impedance : PASS
4856 12:11:54.512505 DUTY Scan : NO K
4857 12:11:54.512591 ZQ Calibration : PASS
4858 12:11:54.516178 Jitter Meter : NO K
4859 12:11:54.519083 CBT Training : PASS
4860 12:11:54.519194 Write leveling : PASS
4861 12:11:54.522514 RX DQS gating : PASS
4862 12:11:54.525945 RX DQ/DQS(RDDQC) : PASS
4863 12:11:54.526030 TX DQ/DQS : PASS
4864 12:11:54.528945 RX DATLAT : PASS
4865 12:11:54.532013 RX DQ/DQS(Engine): PASS
4866 12:11:54.532100 TX OE : NO K
4867 12:11:54.535395 All Pass.
4868 12:11:54.535480
4869 12:11:54.535571 CH 0, Rank 1
4870 12:11:54.539091 SW Impedance : PASS
4871 12:11:54.539197 DUTY Scan : NO K
4872 12:11:54.542205 ZQ Calibration : PASS
4873 12:11:54.545670 Jitter Meter : NO K
4874 12:11:54.545786 CBT Training : PASS
4875 12:11:54.549056 Write leveling : PASS
4876 12:11:54.549160 RX DQS gating : PASS
4877 12:11:54.552191 RX DQ/DQS(RDDQC) : PASS
4878 12:11:54.555855 TX DQ/DQS : PASS
4879 12:11:54.555984 RX DATLAT : PASS
4880 12:11:54.558783 RX DQ/DQS(Engine): PASS
4881 12:11:54.562330 TX OE : NO K
4882 12:11:54.562444 All Pass.
4883 12:11:54.562547
4884 12:11:54.562638 CH 1, Rank 0
4885 12:11:54.565257 SW Impedance : PASS
4886 12:11:54.568352 DUTY Scan : NO K
4887 12:11:54.568436 ZQ Calibration : PASS
4888 12:11:54.572047 Jitter Meter : NO K
4889 12:11:54.575207 CBT Training : PASS
4890 12:11:54.575318 Write leveling : PASS
4891 12:11:54.578337 RX DQS gating : PASS
4892 12:11:54.581979 RX DQ/DQS(RDDQC) : PASS
4893 12:11:54.582066 TX DQ/DQS : PASS
4894 12:11:54.585065 RX DATLAT : PASS
4895 12:11:54.588118 RX DQ/DQS(Engine): PASS
4896 12:11:54.588202 TX OE : NO K
4897 12:11:54.591884 All Pass.
4898 12:11:54.591969
4899 12:11:54.592036 CH 1, Rank 1
4900 12:11:54.594961 SW Impedance : PASS
4901 12:11:54.595045 DUTY Scan : NO K
4902 12:11:54.598011 ZQ Calibration : PASS
4903 12:11:54.601382 Jitter Meter : NO K
4904 12:11:54.601466 CBT Training : PASS
4905 12:11:54.604566 Write leveling : PASS
4906 12:11:54.608070 RX DQS gating : PASS
4907 12:11:54.608155 RX DQ/DQS(RDDQC) : PASS
4908 12:11:54.611177 TX DQ/DQS : PASS
4909 12:11:54.615015 RX DATLAT : PASS
4910 12:11:54.615099 RX DQ/DQS(Engine): PASS
4911 12:11:54.617867 TX OE : NO K
4912 12:11:54.617952 All Pass.
4913 12:11:54.618028
4914 12:11:54.621243 DramC Write-DBI off
4915 12:11:54.624404 PER_BANK_REFRESH: Hybrid Mode
4916 12:11:54.624490 TX_TRACKING: ON
4917 12:11:54.634253 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4918 12:11:54.637797 [FAST_K] Save calibration result to emmc
4919 12:11:54.641301 dramc_set_vcore_voltage set vcore to 662500
4920 12:11:54.644010 Read voltage for 933, 3
4921 12:11:54.644097 Vio18 = 0
4922 12:11:54.644166 Vcore = 662500
4923 12:11:54.647584 Vdram = 0
4924 12:11:54.647673 Vddq = 0
4925 12:11:54.647742 Vmddr = 0
4926 12:11:54.653872 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4927 12:11:54.657688 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4928 12:11:54.660959 MEM_TYPE=3, freq_sel=17
4929 12:11:54.663920 sv_algorithm_assistance_LP4_1600
4930 12:11:54.667387 ============ PULL DRAM RESETB DOWN ============
4931 12:11:54.670415 ========== PULL DRAM RESETB DOWN end =========
4932 12:11:54.677244 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4933 12:11:54.680233 ===================================
4934 12:11:54.683452 LPDDR4 DRAM CONFIGURATION
4935 12:11:54.687223 ===================================
4936 12:11:54.687301 EX_ROW_EN[0] = 0x0
4937 12:11:54.690363 EX_ROW_EN[1] = 0x0
4938 12:11:54.690437 LP4Y_EN = 0x0
4939 12:11:54.693560 WORK_FSP = 0x0
4940 12:11:54.693646 WL = 0x3
4941 12:11:54.696708 RL = 0x3
4942 12:11:54.696786 BL = 0x2
4943 12:11:54.700456 RPST = 0x0
4944 12:11:54.700529 RD_PRE = 0x0
4945 12:11:54.703619 WR_PRE = 0x1
4946 12:11:54.703703 WR_PST = 0x0
4947 12:11:54.706738 DBI_WR = 0x0
4948 12:11:54.710484 DBI_RD = 0x0
4949 12:11:54.710592 OTF = 0x1
4950 12:11:54.713433 ===================================
4951 12:11:54.716588 ===================================
4952 12:11:54.716661 ANA top config
4953 12:11:54.720208 ===================================
4954 12:11:54.723292 DLL_ASYNC_EN = 0
4955 12:11:54.726731 ALL_SLAVE_EN = 1
4956 12:11:54.729788 NEW_RANK_MODE = 1
4957 12:11:54.733222 DLL_IDLE_MODE = 1
4958 12:11:54.733303 LP45_APHY_COMB_EN = 1
4959 12:11:54.736806 TX_ODT_DIS = 1
4960 12:11:54.739733 NEW_8X_MODE = 1
4961 12:11:54.742872 ===================================
4962 12:11:54.746365 ===================================
4963 12:11:54.749425 data_rate = 1866
4964 12:11:54.752981 CKR = 1
4965 12:11:54.755984 DQ_P2S_RATIO = 8
4966 12:11:54.759650 ===================================
4967 12:11:54.759766 CA_P2S_RATIO = 8
4968 12:11:54.762395 DQ_CA_OPEN = 0
4969 12:11:54.766084 DQ_SEMI_OPEN = 0
4970 12:11:54.769157 CA_SEMI_OPEN = 0
4971 12:11:54.772750 CA_FULL_RATE = 0
4972 12:11:54.775725 DQ_CKDIV4_EN = 1
4973 12:11:54.775835 CA_CKDIV4_EN = 1
4974 12:11:54.779035 CA_PREDIV_EN = 0
4975 12:11:54.782158 PH8_DLY = 0
4976 12:11:54.785875 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4977 12:11:54.788915 DQ_AAMCK_DIV = 4
4978 12:11:54.792033 CA_AAMCK_DIV = 4
4979 12:11:54.792149 CA_ADMCK_DIV = 4
4980 12:11:54.795903 DQ_TRACK_CA_EN = 0
4981 12:11:54.798974 CA_PICK = 933
4982 12:11:54.802115 CA_MCKIO = 933
4983 12:11:54.805296 MCKIO_SEMI = 0
4984 12:11:54.808392 PLL_FREQ = 3732
4985 12:11:54.812128 DQ_UI_PI_RATIO = 32
4986 12:11:54.815227 CA_UI_PI_RATIO = 0
4987 12:11:54.818887 ===================================
4988 12:11:54.822001 ===================================
4989 12:11:54.822113 memory_type:LPDDR4
4990 12:11:54.825108 GP_NUM : 10
4991 12:11:54.828159 SRAM_EN : 1
4992 12:11:54.828285 MD32_EN : 0
4993 12:11:54.831793 ===================================
4994 12:11:54.835332 [ANA_INIT] >>>>>>>>>>>>>>
4995 12:11:54.838297 <<<<<< [CONFIGURE PHASE]: ANA_TX
4996 12:11:54.841676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4997 12:11:54.844663 ===================================
4998 12:11:54.848226 data_rate = 1866,PCW = 0X8f00
4999 12:11:54.851235 ===================================
5000 12:11:54.854916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5001 12:11:54.858182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 12:11:54.864731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 12:11:54.868239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5004 12:11:54.871027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5005 12:11:54.874691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5006 12:11:54.877577 [ANA_INIT] flow start
5007 12:11:54.881293 [ANA_INIT] PLL >>>>>>>>
5008 12:11:54.881393 [ANA_INIT] PLL <<<<<<<<
5009 12:11:54.884397 [ANA_INIT] MIDPI >>>>>>>>
5010 12:11:54.887471 [ANA_INIT] MIDPI <<<<<<<<
5011 12:11:54.891352 [ANA_INIT] DLL >>>>>>>>
5012 12:11:54.891438 [ANA_INIT] flow end
5013 12:11:54.894496 ============ LP4 DIFF to SE enter ============
5014 12:11:54.900751 ============ LP4 DIFF to SE exit ============
5015 12:11:54.900845 [ANA_INIT] <<<<<<<<<<<<<
5016 12:11:54.903930 [Flow] Enable top DCM control >>>>>
5017 12:11:54.907697 [Flow] Enable top DCM control <<<<<
5018 12:11:54.910818 Enable DLL master slave shuffle
5019 12:11:54.917346 ==============================================================
5020 12:11:54.917441 Gating Mode config
5021 12:11:54.924177 ==============================================================
5022 12:11:54.927364 Config description:
5023 12:11:54.937199 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5024 12:11:54.944035 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5025 12:11:54.946981 SELPH_MODE 0: By rank 1: By Phase
5026 12:11:54.953896 ==============================================================
5027 12:11:54.956820 GAT_TRACK_EN = 1
5028 12:11:54.960387 RX_GATING_MODE = 2
5029 12:11:54.960476 RX_GATING_TRACK_MODE = 2
5030 12:11:54.963461 SELPH_MODE = 1
5031 12:11:54.967183 PICG_EARLY_EN = 1
5032 12:11:54.970368 VALID_LAT_VALUE = 1
5033 12:11:54.976864 ==============================================================
5034 12:11:54.979921 Enter into Gating configuration >>>>
5035 12:11:54.983426 Exit from Gating configuration <<<<
5036 12:11:54.986384 Enter into DVFS_PRE_config >>>>>
5037 12:11:54.996382 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5038 12:11:55.000291 Exit from DVFS_PRE_config <<<<<
5039 12:11:55.003293 Enter into PICG configuration >>>>
5040 12:11:55.006567 Exit from PICG configuration <<<<
5041 12:11:55.009620 [RX_INPUT] configuration >>>>>
5042 12:11:55.013369 [RX_INPUT] configuration <<<<<
5043 12:11:55.016608 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5044 12:11:55.022999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5045 12:11:55.029468 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 12:11:55.036488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 12:11:55.043080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 12:11:55.046043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 12:11:55.053105 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5050 12:11:55.056041 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5051 12:11:55.059438 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5052 12:11:55.062499 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5053 12:11:55.069572 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5054 12:11:55.072503 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 12:11:55.076160 ===================================
5056 12:11:55.078980 LPDDR4 DRAM CONFIGURATION
5057 12:11:55.082639 ===================================
5058 12:11:55.082724 EX_ROW_EN[0] = 0x0
5059 12:11:55.085487 EX_ROW_EN[1] = 0x0
5060 12:11:55.085572 LP4Y_EN = 0x0
5061 12:11:55.088971 WORK_FSP = 0x0
5062 12:11:55.089057 WL = 0x3
5063 12:11:55.092313 RL = 0x3
5064 12:11:55.095564 BL = 0x2
5065 12:11:55.095650 RPST = 0x0
5066 12:11:55.099119 RD_PRE = 0x0
5067 12:11:55.099204 WR_PRE = 0x1
5068 12:11:55.102168 WR_PST = 0x0
5069 12:11:55.102258 DBI_WR = 0x0
5070 12:11:55.105577 DBI_RD = 0x0
5071 12:11:55.105661 OTF = 0x1
5072 12:11:55.108835 ===================================
5073 12:11:55.111900 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5074 12:11:55.118705 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5075 12:11:55.121864 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 12:11:55.125604 ===================================
5077 12:11:55.128650 LPDDR4 DRAM CONFIGURATION
5078 12:11:55.131908 ===================================
5079 12:11:55.132001 EX_ROW_EN[0] = 0x10
5080 12:11:55.135067 EX_ROW_EN[1] = 0x0
5081 12:11:55.135151 LP4Y_EN = 0x0
5082 12:11:55.138210 WORK_FSP = 0x0
5083 12:11:55.141972 WL = 0x3
5084 12:11:55.142051 RL = 0x3
5085 12:11:55.145128 BL = 0x2
5086 12:11:55.145229 RPST = 0x0
5087 12:11:55.148129 RD_PRE = 0x0
5088 12:11:55.148239 WR_PRE = 0x1
5089 12:11:55.151646 WR_PST = 0x0
5090 12:11:55.151730 DBI_WR = 0x0
5091 12:11:55.155148 DBI_RD = 0x0
5092 12:11:55.155238 OTF = 0x1
5093 12:11:55.158108 ===================================
5094 12:11:55.164762 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5095 12:11:55.168955 nWR fixed to 30
5096 12:11:55.172364 [ModeRegInit_LP4] CH0 RK0
5097 12:11:55.172471 [ModeRegInit_LP4] CH0 RK1
5098 12:11:55.175369 [ModeRegInit_LP4] CH1 RK0
5099 12:11:55.179091 [ModeRegInit_LP4] CH1 RK1
5100 12:11:55.179198 match AC timing 9
5101 12:11:55.185466 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5102 12:11:55.188433 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5103 12:11:55.191928 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5104 12:11:55.198475 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5105 12:11:55.201787 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5106 12:11:55.201876 ==
5107 12:11:55.205053 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 12:11:55.208152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 12:11:55.208255 ==
5110 12:11:55.215084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 12:11:55.221450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5112 12:11:55.225162 [CA 0] Center 38 (8~69) winsize 62
5113 12:11:55.228376 [CA 1] Center 38 (7~69) winsize 63
5114 12:11:55.231433 [CA 2] Center 35 (5~65) winsize 61
5115 12:11:55.235114 [CA 3] Center 35 (5~65) winsize 61
5116 12:11:55.238222 [CA 4] Center 34 (3~65) winsize 63
5117 12:11:55.241386 [CA 5] Center 33 (3~64) winsize 62
5118 12:11:55.241496
5119 12:11:55.244685 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5120 12:11:55.244773
5121 12:11:55.247736 [CATrainingPosCal] consider 1 rank data
5122 12:11:55.251579 u2DelayCellTimex100 = 270/100 ps
5123 12:11:55.254650 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5124 12:11:55.257684 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5125 12:11:55.261139 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5126 12:11:55.267484 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5127 12:11:55.270811 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5128 12:11:55.274296 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5129 12:11:55.274404
5130 12:11:55.277526 CA PerBit enable=1, Macro0, CA PI delay=33
5131 12:11:55.277647
5132 12:11:55.281052 [CBTSetCACLKResult] CA Dly = 33
5133 12:11:55.281162 CS Dly: 7 (0~38)
5134 12:11:55.281259 ==
5135 12:11:55.283951 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 12:11:55.290631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 12:11:55.290745 ==
5138 12:11:55.294117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 12:11:55.300811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5140 12:11:55.304139 [CA 0] Center 38 (8~69) winsize 62
5141 12:11:55.307480 [CA 1] Center 38 (8~69) winsize 62
5142 12:11:55.310436 [CA 2] Center 35 (5~66) winsize 62
5143 12:11:55.314242 [CA 3] Center 35 (5~66) winsize 62
5144 12:11:55.317505 [CA 4] Center 34 (4~64) winsize 61
5145 12:11:55.320648 [CA 5] Center 33 (3~64) winsize 62
5146 12:11:55.320736
5147 12:11:55.323726 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5148 12:11:55.323812
5149 12:11:55.326900 [CATrainingPosCal] consider 2 rank data
5150 12:11:55.330100 u2DelayCellTimex100 = 270/100 ps
5151 12:11:55.333804 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5152 12:11:55.340619 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5153 12:11:55.343777 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5154 12:11:55.347060 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5155 12:11:55.350685 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5156 12:11:55.353842 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5157 12:11:55.353948
5158 12:11:55.357031 CA PerBit enable=1, Macro0, CA PI delay=33
5159 12:11:55.357136
5160 12:11:55.360079 [CBTSetCACLKResult] CA Dly = 33
5161 12:11:55.363523 CS Dly: 7 (0~39)
5162 12:11:55.363628
5163 12:11:55.366892 ----->DramcWriteLeveling(PI) begin...
5164 12:11:55.367005 ==
5165 12:11:55.370421 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 12:11:55.373338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 12:11:55.373451 ==
5168 12:11:55.376604 Write leveling (Byte 0): 33 => 33
5169 12:11:55.380032 Write leveling (Byte 1): 33 => 33
5170 12:11:55.383054 DramcWriteLeveling(PI) end<-----
5171 12:11:55.383148
5172 12:11:55.383232 ==
5173 12:11:55.386590 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 12:11:55.389967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 12:11:55.390076 ==
5176 12:11:55.392963 [Gating] SW mode calibration
5177 12:11:55.399636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5178 12:11:55.406408 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5179 12:11:55.409735 0 14 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
5180 12:11:55.416247 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5181 12:11:55.419341 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 12:11:55.422485 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 12:11:55.429417 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 12:11:55.432639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 12:11:55.435708 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 12:11:55.442440 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5187 12:11:55.446055 0 15 0 | B1->B0 | 3333 2a2a | 1 0 | (0 0) (1 0)
5188 12:11:55.449412 0 15 4 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5189 12:11:55.455699 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 12:11:55.459016 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 12:11:55.462131 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 12:11:55.469122 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 12:11:55.472179 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 12:11:55.475208 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5195 12:11:55.482154 1 0 0 | B1->B0 | 2929 3939 | 0 1 | (0 0) (0 0)
5196 12:11:55.485062 1 0 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5197 12:11:55.488531 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 12:11:55.494932 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 12:11:55.498419 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 12:11:55.501928 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 12:11:55.508348 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 12:11:55.512005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 12:11:55.514731 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5204 12:11:55.521777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5205 12:11:55.524853 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:11:55.528060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:11:55.535004 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:11:55.538105 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:11:55.541253 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:11:55.547656 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:11:55.551459 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:11:55.554527 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:11:55.561063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:11:55.564251 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:11:55.567542 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:11:55.574166 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:11:55.577199 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:11:55.580846 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:11:55.587148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5220 12:11:55.587251 Total UI for P1: 0, mck2ui 16
5221 12:11:55.593678 best dqsien dly found for B0: ( 1, 2, 30)
5222 12:11:55.597318 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5223 12:11:55.600278 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 12:11:55.603828 Total UI for P1: 0, mck2ui 16
5225 12:11:55.606785 best dqsien dly found for B1: ( 1, 3, 2)
5226 12:11:55.610288 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5227 12:11:55.613730 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5228 12:11:55.613852
5229 12:11:55.619866 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5230 12:11:55.623245 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5231 12:11:55.623357 [Gating] SW calibration Done
5232 12:11:55.626793 ==
5233 12:11:55.630104 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 12:11:55.633342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 12:11:55.633417 ==
5236 12:11:55.633482 RX Vref Scan: 0
5237 12:11:55.633542
5238 12:11:55.636599 RX Vref 0 -> 0, step: 1
5239 12:11:55.636687
5240 12:11:55.639765 RX Delay -80 -> 252, step: 8
5241 12:11:55.642881 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5242 12:11:55.646097 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5243 12:11:55.649858 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5244 12:11:55.656639 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5245 12:11:55.659709 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5246 12:11:55.662773 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5247 12:11:55.665923 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5248 12:11:55.669707 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5249 12:11:55.675962 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5250 12:11:55.679604 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5251 12:11:55.682524 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5252 12:11:55.686133 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5253 12:11:55.689219 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5254 12:11:55.696093 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5255 12:11:55.699207 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5256 12:11:55.702308 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5257 12:11:55.702429 ==
5258 12:11:55.705876 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:11:55.708865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:11:55.712374 ==
5261 12:11:55.712466 DQS Delay:
5262 12:11:55.712536 DQS0 = 0, DQS1 = 0
5263 12:11:55.715811 DQM Delay:
5264 12:11:55.715890 DQM0 = 94, DQM1 = 82
5265 12:11:55.718789 DQ Delay:
5266 12:11:55.718896 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5267 12:11:55.722398 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5268 12:11:55.725408 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5269 12:11:55.732041 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5270 12:11:55.732143
5271 12:11:55.732214
5272 12:11:55.732276 ==
5273 12:11:55.735038 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 12:11:55.738668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 12:11:55.738757 ==
5276 12:11:55.738824
5277 12:11:55.738897
5278 12:11:55.741685 TX Vref Scan disable
5279 12:11:55.741793 == TX Byte 0 ==
5280 12:11:55.748400 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5281 12:11:55.751675 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5282 12:11:55.751768 == TX Byte 1 ==
5283 12:11:55.758386 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5284 12:11:55.761560 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5285 12:11:55.761644 ==
5286 12:11:55.764629 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 12:11:55.768411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 12:11:55.768501 ==
5289 12:11:55.768568
5290 12:11:55.771458
5291 12:11:55.771544 TX Vref Scan disable
5292 12:11:55.774516 == TX Byte 0 ==
5293 12:11:55.778305 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5294 12:11:55.784591 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5295 12:11:55.784694 == TX Byte 1 ==
5296 12:11:55.788109 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5297 12:11:55.794338 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5298 12:11:55.794454
5299 12:11:55.794550 [DATLAT]
5300 12:11:55.794654 Freq=933, CH0 RK0
5301 12:11:55.794768
5302 12:11:55.798093 DATLAT Default: 0xd
5303 12:11:55.798173 0, 0xFFFF, sum = 0
5304 12:11:55.800962 1, 0xFFFF, sum = 0
5305 12:11:55.801043 2, 0xFFFF, sum = 0
5306 12:11:55.804603 3, 0xFFFF, sum = 0
5307 12:11:55.807836 4, 0xFFFF, sum = 0
5308 12:11:55.807954 5, 0xFFFF, sum = 0
5309 12:11:55.810739 6, 0xFFFF, sum = 0
5310 12:11:55.810847 7, 0xFFFF, sum = 0
5311 12:11:55.814464 8, 0xFFFF, sum = 0
5312 12:11:55.814568 9, 0xFFFF, sum = 0
5313 12:11:55.817748 10, 0x0, sum = 1
5314 12:11:55.817826 11, 0x0, sum = 2
5315 12:11:55.820574 12, 0x0, sum = 3
5316 12:11:55.820655 13, 0x0, sum = 4
5317 12:11:55.820721 best_step = 11
5318 12:11:55.824126
5319 12:11:55.824210 ==
5320 12:11:55.827643 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 12:11:55.830613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 12:11:55.830693 ==
5323 12:11:55.830773 RX Vref Scan: 1
5324 12:11:55.830877
5325 12:11:55.833994 RX Vref 0 -> 0, step: 1
5326 12:11:55.834077
5327 12:11:55.837707 RX Delay -69 -> 252, step: 4
5328 12:11:55.837783
5329 12:11:55.840648 Set Vref, RX VrefLevel [Byte0]: 62
5330 12:11:55.843963 [Byte1]: 47
5331 12:11:55.847193
5332 12:11:55.847270 Final RX Vref Byte 0 = 62 to rank0
5333 12:11:55.850209 Final RX Vref Byte 1 = 47 to rank0
5334 12:11:55.854070 Final RX Vref Byte 0 = 62 to rank1
5335 12:11:55.857141 Final RX Vref Byte 1 = 47 to rank1==
5336 12:11:55.860173 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 12:11:55.867067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 12:11:55.867158 ==
5339 12:11:55.867240 DQS Delay:
5340 12:11:55.870085 DQS0 = 0, DQS1 = 0
5341 12:11:55.870161 DQM Delay:
5342 12:11:55.870224 DQM0 = 95, DQM1 = 82
5343 12:11:55.873776 DQ Delay:
5344 12:11:55.876871 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5345 12:11:55.880024 DQ4 =96, DQ5 =86, DQ6 =102, DQ7 =106
5346 12:11:55.883245 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =76
5347 12:11:55.886889 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5348 12:11:55.886972
5349 12:11:55.887037
5350 12:11:55.893174 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps
5351 12:11:55.896345 CH0 RK0: MR19=505, MR18=F0E
5352 12:11:55.903242 CH0_RK0: MR19=0x505, MR18=0xF0E, DQSOSC=417, MR23=63, INC=62, DEC=41
5353 12:11:55.903322
5354 12:11:55.906740 ----->DramcWriteLeveling(PI) begin...
5355 12:11:55.906819 ==
5356 12:11:55.909790 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 12:11:55.912848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 12:11:55.912928 ==
5359 12:11:55.916555 Write leveling (Byte 0): 30 => 30
5360 12:11:55.919574 Write leveling (Byte 1): 29 => 29
5361 12:11:55.922705 DramcWriteLeveling(PI) end<-----
5362 12:11:55.922803
5363 12:11:55.922884 ==
5364 12:11:55.926325 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 12:11:55.929367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 12:11:55.932731 ==
5367 12:11:55.932813 [Gating] SW mode calibration
5368 12:11:55.939353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5369 12:11:55.946349 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5370 12:11:55.949455 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5371 12:11:55.956226 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 12:11:55.959165 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 12:11:55.962778 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 12:11:55.969076 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 12:11:55.972205 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 12:11:55.975899 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 12:11:55.982084 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
5378 12:11:55.985268 0 15 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
5379 12:11:55.988535 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 12:11:55.995267 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 12:11:55.999065 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 12:11:56.002124 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 12:11:56.008425 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 12:11:56.011944 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 12:11:56.015013 0 15 28 | B1->B0 | 2626 3838 | 0 0 | (0 0) (1 1)
5386 12:11:56.021454 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
5387 12:11:56.025206 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 12:11:56.028538 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 12:11:56.034877 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 12:11:56.038117 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 12:11:56.041542 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 12:11:56.048338 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 12:11:56.051236 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5394 12:11:56.054369 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5395 12:11:56.061394 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:11:56.064468 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:11:56.067408 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:11:56.074490 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:11:56.077609 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:11:56.080715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:11:56.087774 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:11:56.091034 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:11:56.094346 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:11:56.100654 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:11:56.103853 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:11:56.106936 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:11:56.113805 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:11:56.116826 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5409 12:11:56.120304 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5410 12:11:56.127151 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5411 12:11:56.130391 Total UI for P1: 0, mck2ui 16
5412 12:11:56.133374 best dqsien dly found for B0: ( 1, 2, 26)
5413 12:11:56.136938 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 12:11:56.139932 Total UI for P1: 0, mck2ui 16
5415 12:11:56.143652 best dqsien dly found for B1: ( 1, 2, 30)
5416 12:11:56.146544 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5417 12:11:56.150219 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5418 12:11:56.150341
5419 12:11:56.153045 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5420 12:11:56.160028 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5421 12:11:56.160133 [Gating] SW calibration Done
5422 12:11:56.160203 ==
5423 12:11:56.163082 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 12:11:56.169780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 12:11:56.169906 ==
5426 12:11:56.170003 RX Vref Scan: 0
5427 12:11:56.170095
5428 12:11:56.173303 RX Vref 0 -> 0, step: 1
5429 12:11:56.173413
5430 12:11:56.176502 RX Delay -80 -> 252, step: 8
5431 12:11:56.179604 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5432 12:11:56.182723 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5433 12:11:56.186513 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5434 12:11:56.192521 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5435 12:11:56.196273 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5436 12:11:56.199418 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5437 12:11:56.202605 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5438 12:11:56.206172 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5439 12:11:56.212476 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5440 12:11:56.216254 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5441 12:11:56.219282 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5442 12:11:56.222716 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5443 12:11:56.225768 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5444 12:11:56.232133 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5445 12:11:56.235826 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5446 12:11:56.239047 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5447 12:11:56.239133 ==
5448 12:11:56.242020 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 12:11:56.245555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 12:11:56.245673 ==
5451 12:11:56.249216 DQS Delay:
5452 12:11:56.249321 DQS0 = 0, DQS1 = 0
5453 12:11:56.251868 DQM Delay:
5454 12:11:56.251945 DQM0 = 91, DQM1 = 81
5455 12:11:56.252009 DQ Delay:
5456 12:11:56.255458 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5457 12:11:56.258901 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5458 12:11:56.261799 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =71
5459 12:11:56.265265 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5460 12:11:56.265355
5461 12:11:56.265422
5462 12:11:56.268600 ==
5463 12:11:56.272224 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 12:11:56.275203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 12:11:56.275296 ==
5466 12:11:56.275362
5467 12:11:56.275423
5468 12:11:56.278711 TX Vref Scan disable
5469 12:11:56.278822 == TX Byte 0 ==
5470 12:11:56.284963 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5471 12:11:56.288099 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5472 12:11:56.288190 == TX Byte 1 ==
5473 12:11:56.294780 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5474 12:11:56.298551 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5475 12:11:56.298694 ==
5476 12:11:56.301834 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 12:11:56.304973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 12:11:56.305063 ==
5479 12:11:56.305130
5480 12:11:56.305192
5481 12:11:56.308012 TX Vref Scan disable
5482 12:11:56.311724 == TX Byte 0 ==
5483 12:11:56.314860 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5484 12:11:56.317968 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5485 12:11:56.321542 == TX Byte 1 ==
5486 12:11:56.324501 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5487 12:11:56.328130 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5488 12:11:56.328224
5489 12:11:56.331626 [DATLAT]
5490 12:11:56.331718 Freq=933, CH0 RK1
5491 12:11:56.331786
5492 12:11:56.334774 DATLAT Default: 0xb
5493 12:11:56.334886 0, 0xFFFF, sum = 0
5494 12:11:56.337911 1, 0xFFFF, sum = 0
5495 12:11:56.337997 2, 0xFFFF, sum = 0
5496 12:11:56.341009 3, 0xFFFF, sum = 0
5497 12:11:56.341098 4, 0xFFFF, sum = 0
5498 12:11:56.344789 5, 0xFFFF, sum = 0
5499 12:11:56.344892 6, 0xFFFF, sum = 0
5500 12:11:56.347854 7, 0xFFFF, sum = 0
5501 12:11:56.347957 8, 0xFFFF, sum = 0
5502 12:11:56.350778 9, 0xFFFF, sum = 0
5503 12:11:56.350911 10, 0x0, sum = 1
5504 12:11:56.354372 11, 0x0, sum = 2
5505 12:11:56.354514 12, 0x0, sum = 3
5506 12:11:56.357360 13, 0x0, sum = 4
5507 12:11:56.357458 best_step = 11
5508 12:11:56.357533
5509 12:11:56.357590 ==
5510 12:11:56.360758 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 12:11:56.367573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 12:11:56.367677 ==
5513 12:11:56.367784 RX Vref Scan: 0
5514 12:11:56.367844
5515 12:11:56.370820 RX Vref 0 -> 0, step: 1
5516 12:11:56.370939
5517 12:11:56.374018 RX Delay -77 -> 252, step: 4
5518 12:11:56.377125 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5519 12:11:56.384185 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5520 12:11:56.387120 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5521 12:11:56.390240 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5522 12:11:56.393997 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5523 12:11:56.396933 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5524 12:11:56.400598 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5525 12:11:56.407060 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5526 12:11:56.410278 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5527 12:11:56.413358 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5528 12:11:56.417001 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5529 12:11:56.423199 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5530 12:11:56.427347 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5531 12:11:56.430191 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5532 12:11:56.433080 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5533 12:11:56.436707 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5534 12:11:56.436825 ==
5535 12:11:56.439936 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 12:11:56.446959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 12:11:56.447092 ==
5538 12:11:56.447195 DQS Delay:
5539 12:11:56.449914 DQS0 = 0, DQS1 = 0
5540 12:11:56.450034 DQM Delay:
5541 12:11:56.450106 DQM0 = 92, DQM1 = 84
5542 12:11:56.453005 DQ Delay:
5543 12:11:56.456669 DQ0 =92, DQ1 =94, DQ2 =88, DQ3 =88
5544 12:11:56.459481 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5545 12:11:56.463133 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5546 12:11:56.466304 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5547 12:11:56.466419
5548 12:11:56.466516
5549 12:11:56.472775 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5550 12:11:56.476161 CH0 RK1: MR19=505, MR18=2A0B
5551 12:11:56.483074 CH0_RK1: MR19=0x505, MR18=0x2A0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5552 12:11:56.486305 [RxdqsGatingPostProcess] freq 933
5553 12:11:56.492450 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5554 12:11:56.492578 best DQS0 dly(2T, 0.5T) = (0, 10)
5555 12:11:56.496188 best DQS1 dly(2T, 0.5T) = (0, 11)
5556 12:11:56.499470 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5557 12:11:56.502635 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5558 12:11:56.505653 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 12:11:56.509404 best DQS1 dly(2T, 0.5T) = (0, 10)
5560 12:11:56.512605 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 12:11:56.515723 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5562 12:11:56.519354 Pre-setting of DQS Precalculation
5563 12:11:56.525528 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5564 12:11:56.525642 ==
5565 12:11:56.528715 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 12:11:56.532342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:11:56.532433 ==
5568 12:11:56.538558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 12:11:56.545391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5570 12:11:56.548570 [CA 0] Center 37 (7~67) winsize 61
5571 12:11:56.551704 [CA 1] Center 37 (7~68) winsize 62
5572 12:11:56.554789 [CA 2] Center 35 (6~64) winsize 59
5573 12:11:56.558028 [CA 3] Center 34 (4~64) winsize 61
5574 12:11:56.561869 [CA 4] Center 34 (4~64) winsize 61
5575 12:11:56.564731 [CA 5] Center 33 (4~63) winsize 60
5576 12:11:56.564809
5577 12:11:56.568075 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5578 12:11:56.568200
5579 12:11:56.571283 [CATrainingPosCal] consider 1 rank data
5580 12:11:56.574710 u2DelayCellTimex100 = 270/100 ps
5581 12:11:56.578245 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5582 12:11:56.581081 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5583 12:11:56.584722 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5584 12:11:56.587893 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5585 12:11:56.591006 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5586 12:11:56.594601 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5587 12:11:56.597762
5588 12:11:56.601213 CA PerBit enable=1, Macro0, CA PI delay=33
5589 12:11:56.601335
5590 12:11:56.604172 [CBTSetCACLKResult] CA Dly = 33
5591 12:11:56.604275 CS Dly: 6 (0~37)
5592 12:11:56.604374 ==
5593 12:11:56.607976 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 12:11:56.611025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 12:11:56.611108 ==
5596 12:11:56.617459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5597 12:11:56.623961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5598 12:11:56.627083 [CA 0] Center 38 (8~68) winsize 61
5599 12:11:56.630847 [CA 1] Center 38 (7~69) winsize 63
5600 12:11:56.633862 [CA 2] Center 35 (5~65) winsize 61
5601 12:11:56.636856 [CA 3] Center 34 (4~64) winsize 61
5602 12:11:56.640364 [CA 4] Center 34 (4~65) winsize 62
5603 12:11:56.643745 [CA 5] Center 33 (3~64) winsize 62
5604 12:11:56.643828
5605 12:11:56.646871 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5606 12:11:56.646945
5607 12:11:56.650495 [CATrainingPosCal] consider 2 rank data
5608 12:11:56.653715 u2DelayCellTimex100 = 270/100 ps
5609 12:11:56.656802 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5610 12:11:56.660551 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5611 12:11:56.663633 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5612 12:11:56.669825 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5613 12:11:56.673287 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5614 12:11:56.676832 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5615 12:11:56.676942
5616 12:11:56.679645 CA PerBit enable=1, Macro0, CA PI delay=33
5617 12:11:56.679720
5618 12:11:56.683217 [CBTSetCACLKResult] CA Dly = 33
5619 12:11:56.683302 CS Dly: 6 (0~38)
5620 12:11:56.683370
5621 12:11:56.686733 ----->DramcWriteLeveling(PI) begin...
5622 12:11:56.689523 ==
5623 12:11:56.693047 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 12:11:56.696228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 12:11:56.696326 ==
5626 12:11:56.699745 Write leveling (Byte 0): 25 => 25
5627 12:11:56.702701 Write leveling (Byte 1): 27 => 27
5628 12:11:56.706519 DramcWriteLeveling(PI) end<-----
5629 12:11:56.706606
5630 12:11:56.706673 ==
5631 12:11:56.709684 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 12:11:56.712679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 12:11:56.712795 ==
5634 12:11:56.716368 [Gating] SW mode calibration
5635 12:11:56.722635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5636 12:11:56.729320 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5637 12:11:56.732487 0 14 0 | B1->B0 | 3030 3333 | 0 1 | (0 0) (1 1)
5638 12:11:56.735586 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 12:11:56.742355 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 12:11:56.745942 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 12:11:56.748913 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 12:11:56.755758 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 12:11:56.758864 0 14 24 | B1->B0 | 3434 3535 | 1 0 | (1 0) (0 0)
5644 12:11:56.761989 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
5645 12:11:56.768890 0 15 0 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5646 12:11:56.772119 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 12:11:56.775209 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 12:11:56.781802 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 12:11:56.785336 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 12:11:56.788285 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 12:11:56.795100 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 12:11:56.798583 0 15 28 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
5653 12:11:56.801439 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 12:11:56.808376 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 12:11:56.811500 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 12:11:56.815283 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 12:11:56.821205 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 12:11:56.825052 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 12:11:56.828260 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 12:11:56.834490 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5661 12:11:56.838132 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:11:56.841164 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:11:56.847848 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:11:56.851409 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:11:56.854527 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:11:56.860867 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:11:56.864615 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:11:56.867747 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:11:56.874027 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:11:56.877798 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:11:56.880963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:11:56.887664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:11:56.890791 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:11:56.893738 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:11:56.900363 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 12:11:56.903870 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5677 12:11:56.907358 Total UI for P1: 0, mck2ui 16
5678 12:11:56.910223 best dqsien dly found for B1: ( 1, 2, 26)
5679 12:11:56.913749 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5680 12:11:56.917224 Total UI for P1: 0, mck2ui 16
5681 12:11:56.920244 best dqsien dly found for B0: ( 1, 2, 28)
5682 12:11:56.923365 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5683 12:11:56.927042 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5684 12:11:56.927128
5685 12:11:56.933768 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5686 12:11:56.936828 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5687 12:11:56.939908 [Gating] SW calibration Done
5688 12:11:56.939993 ==
5689 12:11:56.942968 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 12:11:56.946722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 12:11:56.946839 ==
5692 12:11:56.946909 RX Vref Scan: 0
5693 12:11:56.946972
5694 12:11:56.949747 RX Vref 0 -> 0, step: 1
5695 12:11:56.949855
5696 12:11:56.953375 RX Delay -80 -> 252, step: 8
5697 12:11:56.956468 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5698 12:11:56.959575 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5699 12:11:56.966503 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5700 12:11:56.969629 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5701 12:11:56.972857 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5702 12:11:56.975917 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5703 12:11:56.979745 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5704 12:11:56.986050 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5705 12:11:56.989283 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5706 12:11:56.992904 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5707 12:11:56.995923 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5708 12:11:56.999479 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5709 12:11:57.005902 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5710 12:11:57.009241 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5711 12:11:57.012165 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5712 12:11:57.015773 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5713 12:11:57.015887 ==
5714 12:11:57.019254 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 12:11:57.022121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 12:11:57.025340 ==
5717 12:11:57.025455 DQS Delay:
5718 12:11:57.025564 DQS0 = 0, DQS1 = 0
5719 12:11:57.029004 DQM Delay:
5720 12:11:57.029091 DQM0 = 94, DQM1 = 87
5721 12:11:57.032130 DQ Delay:
5722 12:11:57.035175 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5723 12:11:57.038712 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5724 12:11:57.041706 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5725 12:11:57.045404 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5726 12:11:57.045518
5727 12:11:57.045619
5728 12:11:57.045711 ==
5729 12:11:57.048293 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 12:11:57.052049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 12:11:57.052162 ==
5732 12:11:57.052258
5733 12:11:57.052353
5734 12:11:57.055149 TX Vref Scan disable
5735 12:11:57.055226 == TX Byte 0 ==
5736 12:11:57.061910 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5737 12:11:57.065050 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5738 12:11:57.065161 == TX Byte 1 ==
5739 12:11:57.071390 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5740 12:11:57.074991 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5741 12:11:57.075076 ==
5742 12:11:57.078102 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 12:11:57.081116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 12:11:57.084226 ==
5745 12:11:57.084335
5746 12:11:57.084430
5747 12:11:57.084521 TX Vref Scan disable
5748 12:11:57.088086 == TX Byte 0 ==
5749 12:11:57.091095 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5750 12:11:57.097906 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5751 12:11:57.097993 == TX Byte 1 ==
5752 12:11:57.101080 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5753 12:11:57.107863 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5754 12:11:57.107950
5755 12:11:57.108019 [DATLAT]
5756 12:11:57.108090 Freq=933, CH1 RK0
5757 12:11:57.108152
5758 12:11:57.111022 DATLAT Default: 0xd
5759 12:11:57.114187 0, 0xFFFF, sum = 0
5760 12:11:57.114296 1, 0xFFFF, sum = 0
5761 12:11:57.117615 2, 0xFFFF, sum = 0
5762 12:11:57.117707 3, 0xFFFF, sum = 0
5763 12:11:57.120989 4, 0xFFFF, sum = 0
5764 12:11:57.121072 5, 0xFFFF, sum = 0
5765 12:11:57.124408 6, 0xFFFF, sum = 0
5766 12:11:57.124492 7, 0xFFFF, sum = 0
5767 12:11:57.127181 8, 0xFFFF, sum = 0
5768 12:11:57.127288 9, 0xFFFF, sum = 0
5769 12:11:57.130837 10, 0x0, sum = 1
5770 12:11:57.130940 11, 0x0, sum = 2
5771 12:11:57.133915 12, 0x0, sum = 3
5772 12:11:57.134024 13, 0x0, sum = 4
5773 12:11:57.137102 best_step = 11
5774 12:11:57.137219
5775 12:11:57.137317 ==
5776 12:11:57.140784 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 12:11:57.143760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 12:11:57.143837 ==
5779 12:11:57.143902 RX Vref Scan: 1
5780 12:11:57.147259
5781 12:11:57.147381 RX Vref 0 -> 0, step: 1
5782 12:11:57.147463
5783 12:11:57.150770 RX Delay -69 -> 252, step: 4
5784 12:11:57.150881
5785 12:11:57.153698 Set Vref, RX VrefLevel [Byte0]: 55
5786 12:11:57.157457 [Byte1]: 50
5787 12:11:57.160586
5788 12:11:57.160672 Final RX Vref Byte 0 = 55 to rank0
5789 12:11:57.164101 Final RX Vref Byte 1 = 50 to rank0
5790 12:11:57.167131 Final RX Vref Byte 0 = 55 to rank1
5791 12:11:57.170217 Final RX Vref Byte 1 = 50 to rank1==
5792 12:11:57.174079 Dram Type= 6, Freq= 0, CH_1, rank 0
5793 12:11:57.180445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 12:11:57.180558 ==
5795 12:11:57.180661 DQS Delay:
5796 12:11:57.183579 DQS0 = 0, DQS1 = 0
5797 12:11:57.183658 DQM Delay:
5798 12:11:57.183723 DQM0 = 96, DQM1 = 87
5799 12:11:57.186812 DQ Delay:
5800 12:11:57.190143 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
5801 12:11:57.193881 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5802 12:11:57.196947 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =80
5803 12:11:57.200081 DQ12 =96, DQ13 =92, DQ14 =94, DQ15 =94
5804 12:11:57.200167
5805 12:11:57.200236
5806 12:11:57.206826 [DQSOSCAuto] RK0, (LSB)MR18= 0xff07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5807 12:11:57.209946 CH1 RK0: MR19=405, MR18=FF07
5808 12:11:57.216468 CH1_RK0: MR19=0x405, MR18=0xFF07, DQSOSC=419, MR23=63, INC=61, DEC=41
5809 12:11:57.216559
5810 12:11:57.220175 ----->DramcWriteLeveling(PI) begin...
5811 12:11:57.220263 ==
5812 12:11:57.222787 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 12:11:57.226124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 12:11:57.226215 ==
5815 12:11:57.229695 Write leveling (Byte 0): 27 => 27
5816 12:11:57.233034 Write leveling (Byte 1): 28 => 28
5817 12:11:57.236000 DramcWriteLeveling(PI) end<-----
5818 12:11:57.236077
5819 12:11:57.236142 ==
5820 12:11:57.239102 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 12:11:57.246298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 12:11:57.246383 ==
5823 12:11:57.246482 [Gating] SW mode calibration
5824 12:11:57.255888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5825 12:11:57.259101 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5826 12:11:57.265592 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 12:11:57.269119 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 12:11:57.272363 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 12:11:57.278718 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 12:11:57.282464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 12:11:57.285463 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5832 12:11:57.292379 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5833 12:11:57.295409 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5834 12:11:57.298537 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5835 12:11:57.305539 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 12:11:57.308513 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 12:11:57.311687 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 12:11:57.318300 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 12:11:57.321910 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 12:11:57.324942 0 15 24 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (1 1)
5841 12:11:57.331524 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5842 12:11:57.334734 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 12:11:57.338284 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 12:11:57.344713 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 12:11:57.347640 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 12:11:57.350988 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 12:11:57.358037 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 12:11:57.360920 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5849 12:11:57.364170 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5850 12:11:57.371291 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:11:57.374474 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:11:57.377509 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:11:57.383886 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:11:57.387623 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 12:11:57.390813 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 12:11:57.397063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 12:11:57.400852 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:11:57.403984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:11:57.410731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:11:57.413840 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:11:57.417011 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:11:57.423534 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:11:57.427180 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:11:57.430244 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:11:57.437031 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5866 12:11:57.437122 Total UI for P1: 0, mck2ui 16
5867 12:11:57.443229 best dqsien dly found for B0: ( 1, 2, 26)
5868 12:11:57.447033 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 12:11:57.449780 Total UI for P1: 0, mck2ui 16
5870 12:11:57.453245 best dqsien dly found for B1: ( 1, 2, 28)
5871 12:11:57.456588 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5872 12:11:57.460004 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5873 12:11:57.460089
5874 12:11:57.463453 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5875 12:11:57.466687 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5876 12:11:57.469718 [Gating] SW calibration Done
5877 12:11:57.469806 ==
5878 12:11:57.473464 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 12:11:57.476276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 12:11:57.479552 ==
5881 12:11:57.479644 RX Vref Scan: 0
5882 12:11:57.479759
5883 12:11:57.483039 RX Vref 0 -> 0, step: 1
5884 12:11:57.483154
5885 12:11:57.486631 RX Delay -80 -> 252, step: 8
5886 12:11:57.489832 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5887 12:11:57.493143 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5888 12:11:57.496229 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5889 12:11:57.499442 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5890 12:11:57.506284 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5891 12:11:57.509478 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5892 12:11:57.512537 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5893 12:11:57.516253 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5894 12:11:57.519446 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5895 12:11:57.522609 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5896 12:11:57.529253 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5897 12:11:57.532413 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5898 12:11:57.536064 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5899 12:11:57.539280 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5900 12:11:57.542477 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5901 12:11:57.548855 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5902 12:11:57.548966 ==
5903 12:11:57.552291 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 12:11:57.555491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 12:11:57.555573 ==
5906 12:11:57.555639 DQS Delay:
5907 12:11:57.559198 DQS0 = 0, DQS1 = 0
5908 12:11:57.559323 DQM Delay:
5909 12:11:57.562001 DQM0 = 93, DQM1 = 88
5910 12:11:57.562091 DQ Delay:
5911 12:11:57.565379 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5912 12:11:57.568737 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5913 12:11:57.572126 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5914 12:11:57.575281 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5915 12:11:57.575367
5916 12:11:57.575435
5917 12:11:57.575501 ==
5918 12:11:57.578988 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 12:11:57.581843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 12:11:57.585458 ==
5921 12:11:57.585542
5922 12:11:57.585614
5923 12:11:57.585677 TX Vref Scan disable
5924 12:11:57.588890 == TX Byte 0 ==
5925 12:11:57.591721 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5926 12:11:57.595162 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5927 12:11:57.598319 == TX Byte 1 ==
5928 12:11:57.601467 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5929 12:11:57.608405 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5930 12:11:57.608517 ==
5931 12:11:57.611547 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 12:11:57.614683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 12:11:57.614761 ==
5934 12:11:57.614825
5935 12:11:57.614896
5936 12:11:57.618441 TX Vref Scan disable
5937 12:11:57.618520 == TX Byte 0 ==
5938 12:11:57.624609 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5939 12:11:57.628219 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5940 12:11:57.628337 == TX Byte 1 ==
5941 12:11:57.634808 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5942 12:11:57.638034 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5943 12:11:57.638110
5944 12:11:57.638177 [DATLAT]
5945 12:11:57.641206 Freq=933, CH1 RK1
5946 12:11:57.641305
5947 12:11:57.641394 DATLAT Default: 0xb
5948 12:11:57.644798 0, 0xFFFF, sum = 0
5949 12:11:57.648019 1, 0xFFFF, sum = 0
5950 12:11:57.648100 2, 0xFFFF, sum = 0
5951 12:11:57.651183 3, 0xFFFF, sum = 0
5952 12:11:57.651264 4, 0xFFFF, sum = 0
5953 12:11:57.654743 5, 0xFFFF, sum = 0
5954 12:11:57.654840 6, 0xFFFF, sum = 0
5955 12:11:57.657676 7, 0xFFFF, sum = 0
5956 12:11:57.657760 8, 0xFFFF, sum = 0
5957 12:11:57.661260 9, 0xFFFF, sum = 0
5958 12:11:57.661348 10, 0x0, sum = 1
5959 12:11:57.664385 11, 0x0, sum = 2
5960 12:11:57.664470 12, 0x0, sum = 3
5961 12:11:57.667714 13, 0x0, sum = 4
5962 12:11:57.667797 best_step = 11
5963 12:11:57.667867
5964 12:11:57.667980 ==
5965 12:11:57.671391 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 12:11:57.674109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 12:11:57.674192 ==
5968 12:11:57.677440 RX Vref Scan: 0
5969 12:11:57.677538
5970 12:11:57.680728 RX Vref 0 -> 0, step: 1
5971 12:11:57.680851
5972 12:11:57.680977 RX Delay -69 -> 252, step: 4
5973 12:11:57.689172 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5974 12:11:57.692245 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5975 12:11:57.695243 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5976 12:11:57.698808 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5977 12:11:57.701920 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5978 12:11:57.708649 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5979 12:11:57.711832 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5980 12:11:57.715600 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5981 12:11:57.718611 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5982 12:11:57.721638 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5983 12:11:57.725364 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5984 12:11:57.731574 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5985 12:11:57.735211 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5986 12:11:57.738738 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5987 12:11:57.741793 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5988 12:11:57.744939 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5989 12:11:57.745023 ==
5990 12:11:57.748096 Dram Type= 6, Freq= 0, CH_1, rank 1
5991 12:11:57.755048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5992 12:11:57.755179 ==
5993 12:11:57.755265 DQS Delay:
5994 12:11:57.757949 DQS0 = 0, DQS1 = 0
5995 12:11:57.758060 DQM Delay:
5996 12:11:57.761532 DQM0 = 90, DQM1 = 89
5997 12:11:57.761637 DQ Delay:
5998 12:11:57.764614 DQ0 =94, DQ1 =86, DQ2 =80, DQ3 =88
5999 12:11:57.768221 DQ4 =88, DQ5 =100, DQ6 =102, DQ7 =88
6000 12:11:57.771367 DQ8 =76, DQ9 =80, DQ10 =94, DQ11 =84
6001 12:11:57.774336 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
6002 12:11:57.774443
6003 12:11:57.774534
6004 12:11:57.780963 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
6005 12:11:57.784476 CH1 RK1: MR19=505, MR18=B1F
6006 12:11:57.790761 CH1_RK1: MR19=0x505, MR18=0xB1F, DQSOSC=412, MR23=63, INC=63, DEC=42
6007 12:11:57.794402 [RxdqsGatingPostProcess] freq 933
6008 12:11:57.801206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6009 12:11:57.801300 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 12:11:57.804269 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 12:11:57.807783 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 12:11:57.810842 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 12:11:57.813967 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 12:11:57.817270 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 12:11:57.820409 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 12:11:57.823583 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 12:11:57.827098 Pre-setting of DQS Precalculation
6018 12:11:57.834018 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6019 12:11:57.840403 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6020 12:11:57.846968 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6021 12:11:57.847057
6022 12:11:57.847123
6023 12:11:57.850129 [Calibration Summary] 1866 Mbps
6024 12:11:57.850212 CH 0, Rank 0
6025 12:11:57.853423 SW Impedance : PASS
6026 12:11:57.856515 DUTY Scan : NO K
6027 12:11:57.856594 ZQ Calibration : PASS
6028 12:11:57.860244 Jitter Meter : NO K
6029 12:11:57.863072 CBT Training : PASS
6030 12:11:57.863156 Write leveling : PASS
6031 12:11:57.866698 RX DQS gating : PASS
6032 12:11:57.869570 RX DQ/DQS(RDDQC) : PASS
6033 12:11:57.869647 TX DQ/DQS : PASS
6034 12:11:57.873338 RX DATLAT : PASS
6035 12:11:57.876500 RX DQ/DQS(Engine): PASS
6036 12:11:57.876572 TX OE : NO K
6037 12:11:57.879353 All Pass.
6038 12:11:57.879491
6039 12:11:57.879586 CH 0, Rank 1
6040 12:11:57.882825 SW Impedance : PASS
6041 12:11:57.882965 DUTY Scan : NO K
6042 12:11:57.886162 ZQ Calibration : PASS
6043 12:11:57.889841 Jitter Meter : NO K
6044 12:11:57.889925 CBT Training : PASS
6045 12:11:57.892789 Write leveling : PASS
6046 12:11:57.895968 RX DQS gating : PASS
6047 12:11:57.896051 RX DQ/DQS(RDDQC) : PASS
6048 12:11:57.899522 TX DQ/DQS : PASS
6049 12:11:57.902490 RX DATLAT : PASS
6050 12:11:57.902573 RX DQ/DQS(Engine): PASS
6051 12:11:57.906325 TX OE : NO K
6052 12:11:57.906409 All Pass.
6053 12:11:57.906475
6054 12:11:57.909265 CH 1, Rank 0
6055 12:11:57.909347 SW Impedance : PASS
6056 12:11:57.912314 DUTY Scan : NO K
6057 12:11:57.916025 ZQ Calibration : PASS
6058 12:11:57.916108 Jitter Meter : NO K
6059 12:11:57.919170 CBT Training : PASS
6060 12:11:57.922274 Write leveling : PASS
6061 12:11:57.922389 RX DQS gating : PASS
6062 12:11:57.925383 RX DQ/DQS(RDDQC) : PASS
6063 12:11:57.925487 TX DQ/DQS : PASS
6064 12:11:57.929128 RX DATLAT : PASS
6065 12:11:57.932280 RX DQ/DQS(Engine): PASS
6066 12:11:57.932360 TX OE : NO K
6067 12:11:57.935337 All Pass.
6068 12:11:57.935409
6069 12:11:57.935471 CH 1, Rank 1
6070 12:11:57.939022 SW Impedance : PASS
6071 12:11:57.939135 DUTY Scan : NO K
6072 12:11:57.941992 ZQ Calibration : PASS
6073 12:11:57.945612 Jitter Meter : NO K
6074 12:11:57.945728 CBT Training : PASS
6075 12:11:57.948585 Write leveling : PASS
6076 12:11:57.951796 RX DQS gating : PASS
6077 12:11:57.951937 RX DQ/DQS(RDDQC) : PASS
6078 12:11:57.955540 TX DQ/DQS : PASS
6079 12:11:57.958755 RX DATLAT : PASS
6080 12:11:57.958897 RX DQ/DQS(Engine): PASS
6081 12:11:57.961940 TX OE : NO K
6082 12:11:57.962024 All Pass.
6083 12:11:57.962089
6084 12:11:57.965042 DramC Write-DBI off
6085 12:11:57.968595 PER_BANK_REFRESH: Hybrid Mode
6086 12:11:57.968679 TX_TRACKING: ON
6087 12:11:57.978098 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6088 12:11:57.981791 [FAST_K] Save calibration result to emmc
6089 12:11:57.984685 dramc_set_vcore_voltage set vcore to 650000
6090 12:11:57.988414 Read voltage for 400, 6
6091 12:11:57.988514 Vio18 = 0
6092 12:11:57.988595 Vcore = 650000
6093 12:11:57.991242 Vdram = 0
6094 12:11:57.991341 Vddq = 0
6095 12:11:57.991421 Vmddr = 0
6096 12:11:57.997987 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6097 12:11:58.001443 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6098 12:11:58.004874 MEM_TYPE=3, freq_sel=20
6099 12:11:58.007872 sv_algorithm_assistance_LP4_800
6100 12:11:58.011075 ============ PULL DRAM RESETB DOWN ============
6101 12:11:58.017949 ========== PULL DRAM RESETB DOWN end =========
6102 12:11:58.021249 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6103 12:11:58.024535 ===================================
6104 12:11:58.027568 LPDDR4 DRAM CONFIGURATION
6105 12:11:58.031176 ===================================
6106 12:11:58.031280 EX_ROW_EN[0] = 0x0
6107 12:11:58.034270 EX_ROW_EN[1] = 0x0
6108 12:11:58.034366 LP4Y_EN = 0x0
6109 12:11:58.037403 WORK_FSP = 0x0
6110 12:11:58.037500 WL = 0x2
6111 12:11:58.041007 RL = 0x2
6112 12:11:58.041109 BL = 0x2
6113 12:11:58.044035 RPST = 0x0
6114 12:11:58.047827 RD_PRE = 0x0
6115 12:11:58.047932 WR_PRE = 0x1
6116 12:11:58.050890 WR_PST = 0x0
6117 12:11:58.050968 DBI_WR = 0x0
6118 12:11:58.054016 DBI_RD = 0x0
6119 12:11:58.054100 OTF = 0x1
6120 12:11:58.057918 ===================================
6121 12:11:58.061062 ===================================
6122 12:11:58.064251 ANA top config
6123 12:11:58.067410 ===================================
6124 12:11:58.067490 DLL_ASYNC_EN = 0
6125 12:11:58.070504 ALL_SLAVE_EN = 1
6126 12:11:58.073958 NEW_RANK_MODE = 1
6127 12:11:58.076995 DLL_IDLE_MODE = 1
6128 12:11:58.077081 LP45_APHY_COMB_EN = 1
6129 12:11:58.080632 TX_ODT_DIS = 1
6130 12:11:58.083640 NEW_8X_MODE = 1
6131 12:11:58.087329 ===================================
6132 12:11:58.090483 ===================================
6133 12:11:58.093600 data_rate = 800
6134 12:11:58.097203 CKR = 1
6135 12:11:58.100604 DQ_P2S_RATIO = 4
6136 12:11:58.103671 ===================================
6137 12:11:58.103780 CA_P2S_RATIO = 4
6138 12:11:58.107181 DQ_CA_OPEN = 0
6139 12:11:58.110038 DQ_SEMI_OPEN = 1
6140 12:11:58.113591 CA_SEMI_OPEN = 1
6141 12:11:58.117168 CA_FULL_RATE = 0
6142 12:11:58.120417 DQ_CKDIV4_EN = 0
6143 12:11:58.120522 CA_CKDIV4_EN = 1
6144 12:11:58.123452 CA_PREDIV_EN = 0
6145 12:11:58.126861 PH8_DLY = 0
6146 12:11:58.130084 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6147 12:11:58.133178 DQ_AAMCK_DIV = 0
6148 12:11:58.136755 CA_AAMCK_DIV = 0
6149 12:11:58.136858 CA_ADMCK_DIV = 4
6150 12:11:58.139949 DQ_TRACK_CA_EN = 0
6151 12:11:58.143015 CA_PICK = 800
6152 12:11:58.146100 CA_MCKIO = 400
6153 12:11:58.149948 MCKIO_SEMI = 400
6154 12:11:58.153066 PLL_FREQ = 3016
6155 12:11:58.156529 DQ_UI_PI_RATIO = 32
6156 12:11:58.159632 CA_UI_PI_RATIO = 32
6157 12:11:58.162680 ===================================
6158 12:11:58.165986 ===================================
6159 12:11:58.166071 memory_type:LPDDR4
6160 12:11:58.169803 GP_NUM : 10
6161 12:11:58.172888 SRAM_EN : 1
6162 12:11:58.172976 MD32_EN : 0
6163 12:11:58.175916 ===================================
6164 12:11:58.179065 [ANA_INIT] >>>>>>>>>>>>>>
6165 12:11:58.182557 <<<<<< [CONFIGURE PHASE]: ANA_TX
6166 12:11:58.186166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6167 12:11:58.189288 ===================================
6168 12:11:58.192458 data_rate = 800,PCW = 0X7400
6169 12:11:58.195639 ===================================
6170 12:11:58.198854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6171 12:11:58.202368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 12:11:58.215783 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 12:11:58.218951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6174 12:11:58.222556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6175 12:11:58.225541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6176 12:11:58.228650 [ANA_INIT] flow start
6177 12:11:58.232160 [ANA_INIT] PLL >>>>>>>>
6178 12:11:58.232271 [ANA_INIT] PLL <<<<<<<<
6179 12:11:58.235139 [ANA_INIT] MIDPI >>>>>>>>
6180 12:11:58.238895 [ANA_INIT] MIDPI <<<<<<<<
6181 12:11:58.239004 [ANA_INIT] DLL >>>>>>>>
6182 12:11:58.242059 [ANA_INIT] flow end
6183 12:11:58.245189 ============ LP4 DIFF to SE enter ============
6184 12:11:58.248819 ============ LP4 DIFF to SE exit ============
6185 12:11:58.251901 [ANA_INIT] <<<<<<<<<<<<<
6186 12:11:58.255019 [Flow] Enable top DCM control >>>>>
6187 12:11:58.258068 [Flow] Enable top DCM control <<<<<
6188 12:11:58.261813 Enable DLL master slave shuffle
6189 12:11:58.268202 ==============================================================
6190 12:11:58.268315 Gating Mode config
6191 12:11:58.274857 ==============================================================
6192 12:11:58.278054 Config description:
6193 12:11:58.284829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6194 12:11:58.291261 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6195 12:11:58.298170 SELPH_MODE 0: By rank 1: By Phase
6196 12:11:58.304504 ==============================================================
6197 12:11:58.307580 GAT_TRACK_EN = 0
6198 12:11:58.307667 RX_GATING_MODE = 2
6199 12:11:58.311091 RX_GATING_TRACK_MODE = 2
6200 12:11:58.314485 SELPH_MODE = 1
6201 12:11:58.317347 PICG_EARLY_EN = 1
6202 12:11:58.320802 VALID_LAT_VALUE = 1
6203 12:11:58.327675 ==============================================================
6204 12:11:58.330721 Enter into Gating configuration >>>>
6205 12:11:58.333700 Exit from Gating configuration <<<<
6206 12:11:58.337391 Enter into DVFS_PRE_config >>>>>
6207 12:11:58.347619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6208 12:11:58.350199 Exit from DVFS_PRE_config <<<<<
6209 12:11:58.354034 Enter into PICG configuration >>>>
6210 12:11:58.357151 Exit from PICG configuration <<<<
6211 12:11:58.360162 [RX_INPUT] configuration >>>>>
6212 12:11:58.363705 [RX_INPUT] configuration <<<<<
6213 12:11:58.366904 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6214 12:11:58.373175 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6215 12:11:58.380003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 12:11:58.386710 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 12:11:58.393385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6218 12:11:58.396357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6219 12:11:58.403447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6220 12:11:58.406599 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6221 12:11:58.409682 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6222 12:11:58.412875 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6223 12:11:58.419541 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6224 12:11:58.422600 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6225 12:11:58.426046 ===================================
6226 12:11:58.429590 LPDDR4 DRAM CONFIGURATION
6227 12:11:58.432570 ===================================
6228 12:11:58.432657 EX_ROW_EN[0] = 0x0
6229 12:11:58.436111 EX_ROW_EN[1] = 0x0
6230 12:11:58.436194 LP4Y_EN = 0x0
6231 12:11:58.439629 WORK_FSP = 0x0
6232 12:11:58.442402 WL = 0x2
6233 12:11:58.442485 RL = 0x2
6234 12:11:58.446128 BL = 0x2
6235 12:11:58.446212 RPST = 0x0
6236 12:11:58.449052 RD_PRE = 0x0
6237 12:11:58.449133 WR_PRE = 0x1
6238 12:11:58.452811 WR_PST = 0x0
6239 12:11:58.452901 DBI_WR = 0x0
6240 12:11:58.455849 DBI_RD = 0x0
6241 12:11:58.455928 OTF = 0x1
6242 12:11:58.458949 ===================================
6243 12:11:58.462593 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6244 12:11:58.468619 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6245 12:11:58.472411 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6246 12:11:58.475480 ===================================
6247 12:11:58.478514 LPDDR4 DRAM CONFIGURATION
6248 12:11:58.482253 ===================================
6249 12:11:58.482336 EX_ROW_EN[0] = 0x10
6250 12:11:58.485149 EX_ROW_EN[1] = 0x0
6251 12:11:58.485237 LP4Y_EN = 0x0
6252 12:11:58.489038 WORK_FSP = 0x0
6253 12:11:58.491950 WL = 0x2
6254 12:11:58.492034 RL = 0x2
6255 12:11:58.495769 BL = 0x2
6256 12:11:58.495851 RPST = 0x0
6257 12:11:58.498651 RD_PRE = 0x0
6258 12:11:58.498730 WR_PRE = 0x1
6259 12:11:58.501820 WR_PST = 0x0
6260 12:11:58.501927 DBI_WR = 0x0
6261 12:11:58.505392 DBI_RD = 0x0
6262 12:11:58.505475 OTF = 0x1
6263 12:11:58.508558 ===================================
6264 12:11:58.514769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6265 12:11:58.519319 nWR fixed to 30
6266 12:11:58.522854 [ModeRegInit_LP4] CH0 RK0
6267 12:11:58.522956 [ModeRegInit_LP4] CH0 RK1
6268 12:11:58.526046 [ModeRegInit_LP4] CH1 RK0
6269 12:11:58.529136 [ModeRegInit_LP4] CH1 RK1
6270 12:11:58.529220 match AC timing 19
6271 12:11:58.536191 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6272 12:11:58.539165 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6273 12:11:58.542623 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6274 12:11:58.548783 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6275 12:11:58.552435 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6276 12:11:58.552552 ==
6277 12:11:58.555432 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 12:11:58.559081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:11:58.559168 ==
6280 12:11:58.566022 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 12:11:58.572135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6282 12:11:58.575766 [CA 0] Center 36 (8~64) winsize 57
6283 12:11:58.578718 [CA 1] Center 36 (8~64) winsize 57
6284 12:11:58.581843 [CA 2] Center 36 (8~64) winsize 57
6285 12:11:58.585571 [CA 3] Center 36 (8~64) winsize 57
6286 12:11:58.588855 [CA 4] Center 36 (8~64) winsize 57
6287 12:11:58.591648 [CA 5] Center 36 (8~64) winsize 57
6288 12:11:58.591733
6289 12:11:58.595363 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6290 12:11:58.595443
6291 12:11:58.598338 [CATrainingPosCal] consider 1 rank data
6292 12:11:58.602070 u2DelayCellTimex100 = 270/100 ps
6293 12:11:58.604860 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:11:58.608095 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:11:58.611887 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:11:58.615089 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:11:58.618233 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:11:58.621930 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:11:58.622014
6300 12:11:58.625084 CA PerBit enable=1, Macro0, CA PI delay=36
6301 12:11:58.628032
6302 12:11:58.628115 [CBTSetCACLKResult] CA Dly = 36
6303 12:11:58.631811 CS Dly: 1 (0~32)
6304 12:11:58.631895 ==
6305 12:11:58.634803 Dram Type= 6, Freq= 0, CH_0, rank 1
6306 12:11:58.637897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 12:11:58.637981 ==
6308 12:11:58.644924 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6309 12:11:58.651578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6310 12:11:58.654472 [CA 0] Center 36 (8~64) winsize 57
6311 12:11:58.657949 [CA 1] Center 36 (8~64) winsize 57
6312 12:11:58.661053 [CA 2] Center 36 (8~64) winsize 57
6313 12:11:58.664642 [CA 3] Center 36 (8~64) winsize 57
6314 12:11:58.664798 [CA 4] Center 36 (8~64) winsize 57
6315 12:11:58.667791 [CA 5] Center 36 (8~64) winsize 57
6316 12:11:58.667880
6317 12:11:58.674089 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6318 12:11:58.674203
6319 12:11:58.677557 [CATrainingPosCal] consider 2 rank data
6320 12:11:58.680665 u2DelayCellTimex100 = 270/100 ps
6321 12:11:58.684205 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 12:11:58.687400 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 12:11:58.690573 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 12:11:58.694179 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 12:11:58.697147 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 12:11:58.700266 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 12:11:58.700351
6328 12:11:58.704096 CA PerBit enable=1, Macro0, CA PI delay=36
6329 12:11:58.704181
6330 12:11:58.707055 [CBTSetCACLKResult] CA Dly = 36
6331 12:11:58.710920 CS Dly: 1 (0~32)
6332 12:11:58.711004
6333 12:11:58.713865 ----->DramcWriteLeveling(PI) begin...
6334 12:11:58.713950 ==
6335 12:11:58.716947 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 12:11:58.720025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 12:11:58.720108 ==
6338 12:11:58.723833 Write leveling (Byte 0): 40 => 8
6339 12:11:58.727063 Write leveling (Byte 1): 40 => 8
6340 12:11:58.730118 DramcWriteLeveling(PI) end<-----
6341 12:11:58.730200
6342 12:11:58.730265 ==
6343 12:11:58.733172 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 12:11:58.736924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 12:11:58.737008 ==
6346 12:11:58.740217 [Gating] SW mode calibration
6347 12:11:58.746838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6348 12:11:58.753446 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6349 12:11:58.756246 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 12:11:58.763300 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 12:11:58.766476 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 12:11:58.769560 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 12:11:58.776244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 12:11:58.779166 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 12:11:58.782893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 12:11:58.789688 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 12:11:58.792701 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 12:11:58.795827 Total UI for P1: 0, mck2ui 16
6359 12:11:58.799525 best dqsien dly found for B0: ( 0, 14, 24)
6360 12:11:58.802666 Total UI for P1: 0, mck2ui 16
6361 12:11:58.805897 best dqsien dly found for B1: ( 0, 14, 24)
6362 12:11:58.809063 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6363 12:11:58.812629 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6364 12:11:58.812701
6365 12:11:58.815637 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 12:11:58.819362 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 12:11:58.822512 [Gating] SW calibration Done
6368 12:11:58.822584 ==
6369 12:11:58.825612 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 12:11:58.832424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 12:11:58.832507 ==
6372 12:11:58.832571 RX Vref Scan: 0
6373 12:11:58.832631
6374 12:11:58.835517 RX Vref 0 -> 0, step: 1
6375 12:11:58.835592
6376 12:11:58.839190 RX Delay -410 -> 252, step: 16
6377 12:11:58.842397 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6378 12:11:58.845590 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6379 12:11:58.852306 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6380 12:11:58.855265 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6381 12:11:58.858818 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6382 12:11:58.861706 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6383 12:11:58.868631 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6384 12:11:58.871690 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6385 12:11:58.875312 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6386 12:11:58.878333 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6387 12:11:58.884993 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6388 12:11:58.888135 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6389 12:11:58.891767 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6390 12:11:58.898104 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6391 12:11:58.901716 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6392 12:11:58.904732 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6393 12:11:58.904825 ==
6394 12:11:58.908532 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 12:11:58.911642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 12:11:58.911764 ==
6397 12:11:58.914842 DQS Delay:
6398 12:11:58.914942 DQS0 = 59, DQS1 = 59
6399 12:11:58.917852 DQM Delay:
6400 12:11:58.917935 DQM0 = 18, DQM1 = 10
6401 12:11:58.921455 DQ Delay:
6402 12:11:58.921539 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6403 12:11:58.924648 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6404 12:11:58.927753 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6405 12:11:58.931516 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6406 12:11:58.931601
6407 12:11:58.931665
6408 12:11:58.934559 ==
6409 12:11:58.937614 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 12:11:58.941167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 12:11:58.941252 ==
6412 12:11:58.941317
6413 12:11:58.941377
6414 12:11:58.944369 TX Vref Scan disable
6415 12:11:58.944452 == TX Byte 0 ==
6416 12:11:58.947521 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 12:11:58.954244 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 12:11:58.954334 == TX Byte 1 ==
6419 12:11:58.957233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 12:11:58.964210 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 12:11:58.964304 ==
6422 12:11:58.967616 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 12:11:58.970477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 12:11:58.970562 ==
6425 12:11:58.970668
6426 12:11:58.970761
6427 12:11:58.974114 TX Vref Scan disable
6428 12:11:58.974213 == TX Byte 0 ==
6429 12:11:58.977480 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 12:11:58.984006 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 12:11:58.984095 == TX Byte 1 ==
6432 12:11:58.986768 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 12:11:58.993828 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 12:11:58.993959
6435 12:11:58.994055 [DATLAT]
6436 12:11:58.996917 Freq=400, CH0 RK0
6437 12:11:58.997020
6438 12:11:58.997148 DATLAT Default: 0xf
6439 12:11:58.999831 0, 0xFFFF, sum = 0
6440 12:11:58.999948 1, 0xFFFF, sum = 0
6441 12:11:59.003674 2, 0xFFFF, sum = 0
6442 12:11:59.003759 3, 0xFFFF, sum = 0
6443 12:11:59.006603 4, 0xFFFF, sum = 0
6444 12:11:59.006692 5, 0xFFFF, sum = 0
6445 12:11:59.009792 6, 0xFFFF, sum = 0
6446 12:11:59.009892 7, 0xFFFF, sum = 0
6447 12:11:59.013499 8, 0xFFFF, sum = 0
6448 12:11:59.013610 9, 0xFFFF, sum = 0
6449 12:11:59.016787 10, 0xFFFF, sum = 0
6450 12:11:59.016889 11, 0xFFFF, sum = 0
6451 12:11:59.019926 12, 0xFFFF, sum = 0
6452 12:11:59.023036 13, 0x0, sum = 1
6453 12:11:59.023146 14, 0x0, sum = 2
6454 12:11:59.023242 15, 0x0, sum = 3
6455 12:11:59.026633 16, 0x0, sum = 4
6456 12:11:59.026738 best_step = 14
6457 12:11:59.026852
6458 12:11:59.026956 ==
6459 12:11:59.029661 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 12:11:59.036469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 12:11:59.036550 ==
6462 12:11:59.036638 RX Vref Scan: 1
6463 12:11:59.036702
6464 12:11:59.039516 RX Vref 0 -> 0, step: 1
6465 12:11:59.039600
6466 12:11:59.043076 RX Delay -359 -> 252, step: 8
6467 12:11:59.043205
6468 12:11:59.045938 Set Vref, RX VrefLevel [Byte0]: 62
6469 12:11:59.050011 [Byte1]: 47
6470 12:11:59.053155
6471 12:11:59.053231 Final RX Vref Byte 0 = 62 to rank0
6472 12:11:59.056217 Final RX Vref Byte 1 = 47 to rank0
6473 12:11:59.059511 Final RX Vref Byte 0 = 62 to rank1
6474 12:11:59.063127 Final RX Vref Byte 1 = 47 to rank1==
6475 12:11:59.066579 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 12:11:59.072770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 12:11:59.072865 ==
6478 12:11:59.072933 DQS Delay:
6479 12:11:59.076390 DQS0 = 60, DQS1 = 68
6480 12:11:59.076476 DQM Delay:
6481 12:11:59.076543 DQM0 = 15, DQM1 = 14
6482 12:11:59.079248 DQ Delay:
6483 12:11:59.082721 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =12
6484 12:11:59.085976 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6485 12:11:59.089597 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6486 12:11:59.092972 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6487 12:11:59.093107
6488 12:11:59.093206
6489 12:11:59.099358 [DQSOSCAuto] RK0, (LSB)MR18= 0x8180, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6490 12:11:59.102208 CH0 RK0: MR19=C0C, MR18=8180
6491 12:11:59.108975 CH0_RK0: MR19=0xC0C, MR18=0x8180, DQSOSC=393, MR23=63, INC=382, DEC=254
6492 12:11:59.109069 ==
6493 12:11:59.112040 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 12:11:59.115968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 12:11:59.116054 ==
6496 12:11:59.119125 [Gating] SW mode calibration
6497 12:11:59.125908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6498 12:11:59.132118 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6499 12:11:59.135270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 12:11:59.142146 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 12:11:59.145179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 12:11:59.148195 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 12:11:59.155113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 12:11:59.158132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 12:11:59.161898 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 12:11:59.168279 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 12:11:59.171187 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 12:11:59.174704 Total UI for P1: 0, mck2ui 16
6509 12:11:59.177904 best dqsien dly found for B0: ( 0, 14, 24)
6510 12:11:59.181396 Total UI for P1: 0, mck2ui 16
6511 12:11:59.184483 best dqsien dly found for B1: ( 0, 14, 24)
6512 12:11:59.187940 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6513 12:11:59.191224 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6514 12:11:59.191315
6515 12:11:59.194692 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 12:11:59.197778 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 12:11:59.201248 [Gating] SW calibration Done
6518 12:11:59.201334 ==
6519 12:11:59.204441 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 12:11:59.207636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 12:11:59.210708 ==
6522 12:11:59.210825 RX Vref Scan: 0
6523 12:11:59.210935
6524 12:11:59.214369 RX Vref 0 -> 0, step: 1
6525 12:11:59.214457
6526 12:11:59.217678 RX Delay -410 -> 252, step: 16
6527 12:11:59.220901 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6528 12:11:59.224034 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6529 12:11:59.227140 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6530 12:11:59.233887 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6531 12:11:59.237048 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6532 12:11:59.240877 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6533 12:11:59.247094 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6534 12:11:59.250656 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6535 12:11:59.253610 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6536 12:11:59.257320 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6537 12:11:59.263587 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6538 12:11:59.267189 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6539 12:11:59.270369 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6540 12:11:59.273626 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6541 12:11:59.280378 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6542 12:11:59.283067 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6543 12:11:59.283155 ==
6544 12:11:59.286726 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 12:11:59.289849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 12:11:59.289935 ==
6547 12:11:59.293288 DQS Delay:
6548 12:11:59.293379 DQS0 = 59, DQS1 = 59
6549 12:11:59.296392 DQM Delay:
6550 12:11:59.296476 DQM0 = 16, DQM1 = 10
6551 12:11:59.296543 DQ Delay:
6552 12:11:59.300210 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6553 12:11:59.303145 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6554 12:11:59.306274 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6555 12:11:59.309945 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6556 12:11:59.310054
6557 12:11:59.310118
6558 12:11:59.310179 ==
6559 12:11:59.312917 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 12:11:59.319799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 12:11:59.319879 ==
6562 12:11:59.319945
6563 12:11:59.320048
6564 12:11:59.322794 TX Vref Scan disable
6565 12:11:59.322911 == TX Byte 0 ==
6566 12:11:59.326236 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6567 12:11:59.332695 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6568 12:11:59.332779 == TX Byte 1 ==
6569 12:11:59.336156 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6570 12:11:59.342918 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6571 12:11:59.343005 ==
6572 12:11:59.346170 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 12:11:59.349269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 12:11:59.349354 ==
6575 12:11:59.349420
6576 12:11:59.349481
6577 12:11:59.352893 TX Vref Scan disable
6578 12:11:59.352980 == TX Byte 0 ==
6579 12:11:59.356032 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6580 12:11:59.362389 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6581 12:11:59.362498 == TX Byte 1 ==
6582 12:11:59.365603 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6583 12:11:59.372382 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6584 12:11:59.372471
6585 12:11:59.372555 [DATLAT]
6586 12:11:59.372638 Freq=400, CH0 RK1
6587 12:11:59.372720
6588 12:11:59.375381 DATLAT Default: 0xe
6589 12:11:59.379169 0, 0xFFFF, sum = 0
6590 12:11:59.379257 1, 0xFFFF, sum = 0
6591 12:11:59.382273 2, 0xFFFF, sum = 0
6592 12:11:59.382367 3, 0xFFFF, sum = 0
6593 12:11:59.385319 4, 0xFFFF, sum = 0
6594 12:11:59.385396 5, 0xFFFF, sum = 0
6595 12:11:59.388800 6, 0xFFFF, sum = 0
6596 12:11:59.388936 7, 0xFFFF, sum = 0
6597 12:11:59.392343 8, 0xFFFF, sum = 0
6598 12:11:59.392441 9, 0xFFFF, sum = 0
6599 12:11:59.395392 10, 0xFFFF, sum = 0
6600 12:11:59.395476 11, 0xFFFF, sum = 0
6601 12:11:59.398437 12, 0xFFFF, sum = 0
6602 12:11:59.398520 13, 0x0, sum = 1
6603 12:11:59.402072 14, 0x0, sum = 2
6604 12:11:59.402155 15, 0x0, sum = 3
6605 12:11:59.405077 16, 0x0, sum = 4
6606 12:11:59.405160 best_step = 14
6607 12:11:59.405233
6608 12:11:59.405302 ==
6609 12:11:59.408283 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 12:11:59.415145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 12:11:59.415229 ==
6612 12:11:59.415294 RX Vref Scan: 0
6613 12:11:59.415354
6614 12:11:59.418298 RX Vref 0 -> 0, step: 1
6615 12:11:59.418380
6616 12:11:59.421887 RX Delay -359 -> 252, step: 8
6617 12:11:59.428535 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6618 12:11:59.431942 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6619 12:11:59.434822 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6620 12:11:59.438090 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6621 12:11:59.444858 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6622 12:11:59.448042 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6623 12:11:59.451633 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6624 12:11:59.454721 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6625 12:11:59.460864 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6626 12:11:59.464496 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6627 12:11:59.467863 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6628 12:11:59.474561 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6629 12:11:59.477706 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6630 12:11:59.480920 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6631 12:11:59.484150 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6632 12:11:59.490688 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6633 12:11:59.490803 ==
6634 12:11:59.493765 Dram Type= 6, Freq= 0, CH_0, rank 1
6635 12:11:59.497278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 12:11:59.497379 ==
6637 12:11:59.497499 DQS Delay:
6638 12:11:59.500706 DQS0 = 60, DQS1 = 68
6639 12:11:59.500780 DQM Delay:
6640 12:11:59.504193 DQM0 = 11, DQM1 = 13
6641 12:11:59.504328 DQ Delay:
6642 12:11:59.507065 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6643 12:11:59.510563 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6644 12:11:59.514202 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6645 12:11:59.517204 DQ12 =20, DQ13 =24, DQ14 =20, DQ15 =20
6646 12:11:59.517301
6647 12:11:59.517380
6648 12:11:59.523571 [DQSOSCAuto] RK1, (LSB)MR18= 0xc177, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6649 12:11:59.527360 CH0 RK1: MR19=C0C, MR18=C177
6650 12:11:59.533662 CH0_RK1: MR19=0xC0C, MR18=0xC177, DQSOSC=385, MR23=63, INC=398, DEC=265
6651 12:11:59.537294 [RxdqsGatingPostProcess] freq 400
6652 12:11:59.543617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6653 12:11:59.547016 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 12:11:59.550419 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 12:11:59.553534 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 12:11:59.556634 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 12:11:59.559791 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 12:11:59.559877 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 12:11:59.562852 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 12:11:59.566457 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 12:11:59.570179 Pre-setting of DQS Precalculation
6662 12:11:59.576322 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6663 12:11:59.576410 ==
6664 12:11:59.580038 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 12:11:59.583133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:11:59.583218 ==
6667 12:11:59.589410 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 12:11:59.596333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6669 12:11:59.599409 [CA 0] Center 36 (8~64) winsize 57
6670 12:11:59.602937 [CA 1] Center 36 (8~64) winsize 57
6671 12:11:59.605937 [CA 2] Center 36 (8~64) winsize 57
6672 12:11:59.606023 [CA 3] Center 36 (8~64) winsize 57
6673 12:11:59.609479 [CA 4] Center 36 (8~64) winsize 57
6674 12:11:59.612912 [CA 5] Center 36 (8~64) winsize 57
6675 12:11:59.612998
6676 12:11:59.619185 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6677 12:11:59.619275
6678 12:11:59.622724 [CATrainingPosCal] consider 1 rank data
6679 12:11:59.625919 u2DelayCellTimex100 = 270/100 ps
6680 12:11:59.628967 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:11:59.632608 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:11:59.635668 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:11:59.639497 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:11:59.642071 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:11:59.645556 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:11:59.645666
6687 12:11:59.648731 CA PerBit enable=1, Macro0, CA PI delay=36
6688 12:11:59.648810
6689 12:11:59.652375 [CBTSetCACLKResult] CA Dly = 36
6690 12:11:59.655687 CS Dly: 1 (0~32)
6691 12:11:59.655775 ==
6692 12:11:59.658754 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 12:11:59.661862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 12:11:59.661948 ==
6695 12:11:59.668472 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6696 12:11:59.675717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6697 12:11:59.675813 [CA 0] Center 36 (8~64) winsize 57
6698 12:11:59.678744 [CA 1] Center 36 (8~64) winsize 57
6699 12:11:59.681824 [CA 2] Center 36 (8~64) winsize 57
6700 12:11:59.685068 [CA 3] Center 36 (8~64) winsize 57
6701 12:11:59.688819 [CA 4] Center 36 (8~64) winsize 57
6702 12:11:59.691932 [CA 5] Center 36 (8~64) winsize 57
6703 12:11:59.692044
6704 12:11:59.695106 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6705 12:11:59.695182
6706 12:11:59.698252 [CATrainingPosCal] consider 2 rank data
6707 12:11:59.702057 u2DelayCellTimex100 = 270/100 ps
6708 12:11:59.705180 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 12:11:59.711929 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 12:11:59.714800 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 12:11:59.718251 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 12:11:59.721594 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 12:11:59.725254 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 12:11:59.725361
6715 12:11:59.728083 CA PerBit enable=1, Macro0, CA PI delay=36
6716 12:11:59.728201
6717 12:11:59.731605 [CBTSetCACLKResult] CA Dly = 36
6718 12:11:59.735104 CS Dly: 1 (0~32)
6719 12:11:59.735195
6720 12:11:59.738131 ----->DramcWriteLeveling(PI) begin...
6721 12:11:59.738294 ==
6722 12:11:59.741456 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 12:11:59.744442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 12:11:59.744530 ==
6725 12:11:59.748068 Write leveling (Byte 0): 40 => 8
6726 12:11:59.751603 Write leveling (Byte 1): 40 => 8
6727 12:11:59.754661 DramcWriteLeveling(PI) end<-----
6728 12:11:59.754774
6729 12:11:59.754889 ==
6730 12:11:59.757612 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 12:11:59.761189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 12:11:59.761297 ==
6733 12:11:59.764759 [Gating] SW mode calibration
6734 12:11:59.771101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6735 12:11:59.777810 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6736 12:11:59.780904 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 12:11:59.783993 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 12:11:59.790702 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 12:11:59.793905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 12:11:59.797037 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 12:11:59.803973 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 12:11:59.807179 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 12:11:59.810123 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 12:11:59.816928 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 12:11:59.820151 Total UI for P1: 0, mck2ui 16
6746 12:11:59.823484 best dqsien dly found for B0: ( 0, 14, 24)
6747 12:11:59.827061 Total UI for P1: 0, mck2ui 16
6748 12:11:59.830096 best dqsien dly found for B1: ( 0, 14, 24)
6749 12:11:59.833162 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6750 12:11:59.836683 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6751 12:11:59.836770
6752 12:11:59.840146 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 12:11:59.843627 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 12:11:59.846781 [Gating] SW calibration Done
6755 12:11:59.846902 ==
6756 12:11:59.849889 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 12:11:59.853010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 12:11:59.853147 ==
6759 12:11:59.856766 RX Vref Scan: 0
6760 12:11:59.856943
6761 12:11:59.859643 RX Vref 0 -> 0, step: 1
6762 12:11:59.859781
6763 12:11:59.863155 RX Delay -410 -> 252, step: 16
6764 12:11:59.866069 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6765 12:11:59.869794 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6766 12:11:59.873309 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6767 12:11:59.879777 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6768 12:11:59.883004 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6769 12:11:59.886057 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6770 12:11:59.889678 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6771 12:11:59.895863 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6772 12:11:59.899564 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6773 12:11:59.902772 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6774 12:11:59.905899 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6775 12:11:59.912739 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6776 12:11:59.915652 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6777 12:11:59.918872 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6778 12:11:59.925613 iDelay=230, Bit 14, Center -51 (-314 ~ 213) 528
6779 12:11:59.928688 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6780 12:11:59.928802 ==
6781 12:11:59.932264 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 12:11:59.936070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 12:11:59.936210 ==
6784 12:11:59.938692 DQS Delay:
6785 12:11:59.938804 DQS0 = 51, DQS1 = 67
6786 12:11:59.938890 DQM Delay:
6787 12:11:59.942353 DQM0 = 13, DQM1 = 17
6788 12:11:59.942470 DQ Delay:
6789 12:11:59.945172 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6790 12:11:59.948822 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6791 12:11:59.952078 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6792 12:11:59.955235 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6793 12:11:59.955387
6794 12:11:59.955499
6795 12:11:59.955610 ==
6796 12:11:59.958947 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 12:11:59.962090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 12:11:59.965082 ==
6799 12:11:59.965194
6800 12:11:59.965295
6801 12:11:59.965391 TX Vref Scan disable
6802 12:11:59.968599 == TX Byte 0 ==
6803 12:11:59.971970 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 12:11:59.974986 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 12:11:59.978309 == TX Byte 1 ==
6806 12:11:59.981804 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 12:11:59.985335 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 12:11:59.985460 ==
6809 12:11:59.988477 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 12:11:59.995048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 12:11:59.995170 ==
6812 12:11:59.995239
6813 12:11:59.995302
6814 12:11:59.995361 TX Vref Scan disable
6815 12:11:59.998529 == TX Byte 0 ==
6816 12:12:00.001680 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 12:12:00.004790 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 12:12:00.008606 == TX Byte 1 ==
6819 12:12:00.011701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 12:12:00.014909 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 12:12:00.014992
6822 12:12:00.018422 [DATLAT]
6823 12:12:00.018511 Freq=400, CH1 RK0
6824 12:12:00.018576
6825 12:12:00.021560 DATLAT Default: 0xf
6826 12:12:00.021645 0, 0xFFFF, sum = 0
6827 12:12:00.237337 1, 0xFFFF, sum = 0
6828 12:12:00.237583 2, 0xFFFF, sum = 0
6829 12:12:00.237889 3, 0xFFFF, sum = 0
6830 12:12:00.237991 4, 0xFFFF, sum = 0
6831 12:12:00.238086 5, 0xFFFF, sum = 0
6832 12:12:00.238176 6, 0xFFFF, sum = 0
6833 12:12:00.238268 7, 0xFFFF, sum = 0
6834 12:12:00.238355 8, 0xFFFF, sum = 0
6835 12:12:00.238446 9, 0xFFFF, sum = 0
6836 12:12:00.238533 10, 0xFFFF, sum = 0
6837 12:12:00.238622 11, 0xFFFF, sum = 0
6838 12:12:00.238709 12, 0xFFFF, sum = 0
6839 12:12:00.238798 13, 0x0, sum = 1
6840 12:12:00.238923 14, 0x0, sum = 2
6841 12:12:00.239013 15, 0x0, sum = 3
6842 12:12:00.239099 16, 0x0, sum = 4
6843 12:12:00.239188 best_step = 14
6844 12:12:00.239270
6845 12:12:00.239356 ==
6846 12:12:00.239471 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 12:12:00.239559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 12:12:00.239644 ==
6849 12:12:00.239731 RX Vref Scan: 1
6850 12:12:00.239815
6851 12:12:00.239899 RX Vref 0 -> 0, step: 1
6852 12:12:00.239985
6853 12:12:00.240069 RX Delay -375 -> 252, step: 8
6854 12:12:00.240156
6855 12:12:00.240239 Set Vref, RX VrefLevel [Byte0]: 55
6856 12:12:00.240326 [Byte1]: 50
6857 12:12:00.240409
6858 12:12:00.240495 Final RX Vref Byte 0 = 55 to rank0
6859 12:12:00.240580 Final RX Vref Byte 1 = 50 to rank0
6860 12:12:00.240664 Final RX Vref Byte 0 = 55 to rank1
6861 12:12:00.240751 Final RX Vref Byte 1 = 50 to rank1==
6862 12:12:00.240835 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 12:12:00.240921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 12:12:00.241005 ==
6865 12:12:00.241093 DQS Delay:
6866 12:12:00.241176 DQS0 = 52, DQS1 = 64
6867 12:12:00.241262 DQM Delay:
6868 12:12:00.241352 DQM0 = 9, DQM1 = 11
6869 12:12:00.241437 DQ Delay:
6870 12:12:00.241525 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6871 12:12:00.241608 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6872 12:12:00.241692 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6873 12:12:00.241779 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6874 12:12:00.241861
6875 12:12:00.241937
6876 12:12:00.241993 [DQSOSCAuto] RK0, (LSB)MR18= 0x5669, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6877 12:12:00.242074 CH1 RK0: MR19=C0C, MR18=5669
6878 12:12:00.242209 CH1_RK0: MR19=0xC0C, MR18=0x5669, DQSOSC=396, MR23=63, INC=376, DEC=251
6879 12:12:00.242321 ==
6880 12:12:00.242433 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 12:12:00.242549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 12:12:00.242660 ==
6883 12:12:00.242774 [Gating] SW mode calibration
6884 12:12:00.242897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6885 12:12:00.243011 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6886 12:12:00.243122 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 12:12:00.243231 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6888 12:12:00.243340 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 12:12:00.243476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 12:12:00.243586 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 12:12:00.243695 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 12:12:00.243802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 12:12:00.243913 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 12:12:00.244022 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 12:12:00.244131 Total UI for P1: 0, mck2ui 16
6896 12:12:00.244240 best dqsien dly found for B0: ( 0, 14, 24)
6897 12:12:00.244343 Total UI for P1: 0, mck2ui 16
6898 12:12:00.244449 best dqsien dly found for B1: ( 0, 14, 24)
6899 12:12:00.244549 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6900 12:12:00.244652 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6901 12:12:00.244750
6902 12:12:00.244852 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 12:12:00.244949 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 12:12:00.245046 [Gating] SW calibration Done
6905 12:12:00.245142 ==
6906 12:12:00.245247 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 12:12:00.245343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 12:12:00.245441 ==
6909 12:12:00.245537 RX Vref Scan: 0
6910 12:12:00.245633
6911 12:12:00.245728 RX Vref 0 -> 0, step: 1
6912 12:12:00.245824
6913 12:12:00.245919 RX Delay -410 -> 252, step: 16
6914 12:12:00.246043 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6915 12:12:00.247899 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6916 12:12:00.251096 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6917 12:12:00.257715 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6918 12:12:00.261312 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6919 12:12:00.264020 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6920 12:12:00.267877 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6921 12:12:00.274155 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6922 12:12:00.277269 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6923 12:12:00.280969 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6924 12:12:00.284115 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6925 12:12:00.290416 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6926 12:12:00.293926 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6927 12:12:00.297219 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6928 12:12:00.300598 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6929 12:12:00.307005 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6930 12:12:00.307105 ==
6931 12:12:00.310381 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 12:12:00.313423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 12:12:00.313551 ==
6934 12:12:00.313669 DQS Delay:
6935 12:12:00.317207 DQS0 = 59, DQS1 = 59
6936 12:12:00.317316 DQM Delay:
6937 12:12:00.320368 DQM0 = 19, DQM1 = 14
6938 12:12:00.320498 DQ Delay:
6939 12:12:00.323448 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6940 12:12:00.326603 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6941 12:12:00.330290 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6942 12:12:00.333174 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6943 12:12:00.333256
6944 12:12:00.333332
6945 12:12:00.333395 ==
6946 12:12:00.336882 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 12:12:00.340025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 12:12:00.343242 ==
6949 12:12:00.343339
6950 12:12:00.343408
6951 12:12:00.343472 TX Vref Scan disable
6952 12:12:00.346808 == TX Byte 0 ==
6953 12:12:00.349900 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6954 12:12:00.352963 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6955 12:12:00.356665 == TX Byte 1 ==
6956 12:12:00.360054 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6957 12:12:00.362953 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6958 12:12:00.363044 ==
6959 12:12:00.366557 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 12:12:00.373060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 12:12:00.373148 ==
6962 12:12:00.373215
6963 12:12:00.373277
6964 12:12:00.373336 TX Vref Scan disable
6965 12:12:00.375895 == TX Byte 0 ==
6966 12:12:00.379618 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6967 12:12:00.382711 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6968 12:12:00.386463 == TX Byte 1 ==
6969 12:12:00.389571 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6970 12:12:00.392677 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6971 12:12:00.392761
6972 12:12:00.395910 [DATLAT]
6973 12:12:00.395996 Freq=400, CH1 RK1
6974 12:12:00.396063
6975 12:12:00.399404 DATLAT Default: 0xe
6976 12:12:00.399488 0, 0xFFFF, sum = 0
6977 12:12:00.402365 1, 0xFFFF, sum = 0
6978 12:12:00.402451 2, 0xFFFF, sum = 0
6979 12:12:00.405677 3, 0xFFFF, sum = 0
6980 12:12:00.405765 4, 0xFFFF, sum = 0
6981 12:12:00.409083 5, 0xFFFF, sum = 0
6982 12:12:00.409167 6, 0xFFFF, sum = 0
6983 12:12:00.412224 7, 0xFFFF, sum = 0
6984 12:12:00.415651 8, 0xFFFF, sum = 0
6985 12:12:00.415765 9, 0xFFFF, sum = 0
6986 12:12:00.419109 10, 0xFFFF, sum = 0
6987 12:12:00.419198 11, 0xFFFF, sum = 0
6988 12:12:00.422208 12, 0xFFFF, sum = 0
6989 12:12:00.422309 13, 0x0, sum = 1
6990 12:12:00.425328 14, 0x0, sum = 2
6991 12:12:00.425415 15, 0x0, sum = 3
6992 12:12:00.429005 16, 0x0, sum = 4
6993 12:12:00.429092 best_step = 14
6994 12:12:00.429159
6995 12:12:00.429221 ==
6996 12:12:00.432193 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 12:12:00.435247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 12:12:00.438722 ==
6999 12:12:00.438840 RX Vref Scan: 0
7000 12:12:00.438910
7001 12:12:00.441737 RX Vref 0 -> 0, step: 1
7002 12:12:00.441822
7003 12:12:00.444936 RX Delay -359 -> 252, step: 8
7004 12:12:00.451698 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7005 12:12:00.454772 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7006 12:12:00.458587 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7007 12:12:00.461557 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7008 12:12:00.468004 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7009 12:12:00.471563 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7010 12:12:00.474437 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7011 12:12:00.478179 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7012 12:12:00.484702 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7013 12:12:00.487922 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7014 12:12:00.490904 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7015 12:12:00.494524 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7016 12:12:00.500954 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7017 12:12:00.504132 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7018 12:12:00.507754 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7019 12:12:00.514318 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7020 12:12:00.514433 ==
7021 12:12:00.517272 Dram Type= 6, Freq= 0, CH_1, rank 1
7022 12:12:00.520779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7023 12:12:00.520884 ==
7024 12:12:00.520983 DQS Delay:
7025 12:12:00.523650 DQS0 = 60, DQS1 = 64
7026 12:12:00.523757 DQM Delay:
7027 12:12:00.527161 DQM0 = 13, DQM1 = 10
7028 12:12:00.527265 DQ Delay:
7029 12:12:00.530319 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7030 12:12:00.533522 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7031 12:12:00.537107 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7032 12:12:00.540103 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7033 12:12:00.540207
7034 12:12:00.540306
7035 12:12:00.546585 [DQSOSCAuto] RK1, (LSB)MR18= 0x7baa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7036 12:12:00.550138 CH1 RK1: MR19=C0C, MR18=7BAA
7037 12:12:00.556797 CH1_RK1: MR19=0xC0C, MR18=0x7BAA, DQSOSC=388, MR23=63, INC=392, DEC=261
7038 12:12:00.559976 [RxdqsGatingPostProcess] freq 400
7039 12:12:00.566268 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7040 12:12:00.569478 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 12:12:00.572728 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 12:12:00.576502 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 12:12:00.579464 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 12:12:00.583120 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 12:12:00.583230 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 12:12:00.586064 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 12:12:00.589477 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 12:12:00.593100 Pre-setting of DQS Precalculation
7049 12:12:00.599331 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7050 12:12:00.606214 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7051 12:12:00.612935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7052 12:12:00.613049
7053 12:12:00.613149
7054 12:12:00.615947 [Calibration Summary] 800 Mbps
7055 12:12:00.619095 CH 0, Rank 0
7056 12:12:00.619202 SW Impedance : PASS
7057 12:12:00.622241 DUTY Scan : NO K
7058 12:12:00.622354 ZQ Calibration : PASS
7059 12:12:00.625852 Jitter Meter : NO K
7060 12:12:00.629274 CBT Training : PASS
7061 12:12:00.629388 Write leveling : PASS
7062 12:12:00.632633 RX DQS gating : PASS
7063 12:12:00.635686 RX DQ/DQS(RDDQC) : PASS
7064 12:12:00.635792 TX DQ/DQS : PASS
7065 12:12:00.639489 RX DATLAT : PASS
7066 12:12:00.642404 RX DQ/DQS(Engine): PASS
7067 12:12:00.642503 TX OE : NO K
7068 12:12:00.645440 All Pass.
7069 12:12:00.645525
7070 12:12:00.645592 CH 0, Rank 1
7071 12:12:00.648985 SW Impedance : PASS
7072 12:12:00.649069 DUTY Scan : NO K
7073 12:12:00.652215 ZQ Calibration : PASS
7074 12:12:00.655547 Jitter Meter : NO K
7075 12:12:00.655658 CBT Training : PASS
7076 12:12:00.658659 Write leveling : NO K
7077 12:12:00.661876 RX DQS gating : PASS
7078 12:12:00.661989 RX DQ/DQS(RDDQC) : PASS
7079 12:12:00.665034 TX DQ/DQS : PASS
7080 12:12:00.668203 RX DATLAT : PASS
7081 12:12:00.668287 RX DQ/DQS(Engine): PASS
7082 12:12:00.671819 TX OE : NO K
7083 12:12:00.671931 All Pass.
7084 12:12:00.672025
7085 12:12:00.674932 CH 1, Rank 0
7086 12:12:00.675020 SW Impedance : PASS
7087 12:12:00.678125 DUTY Scan : NO K
7088 12:12:00.681175 ZQ Calibration : PASS
7089 12:12:00.681285 Jitter Meter : NO K
7090 12:12:00.684947 CBT Training : PASS
7091 12:12:00.687997 Write leveling : PASS
7092 12:12:00.688108 RX DQS gating : PASS
7093 12:12:00.691600 RX DQ/DQS(RDDQC) : PASS
7094 12:12:00.695062 TX DQ/DQS : PASS
7095 12:12:00.695149 RX DATLAT : PASS
7096 12:12:00.697976 RX DQ/DQS(Engine): PASS
7097 12:12:00.701517 TX OE : NO K
7098 12:12:00.701627 All Pass.
7099 12:12:00.701722
7100 12:12:00.701811 CH 1, Rank 1
7101 12:12:00.704645 SW Impedance : PASS
7102 12:12:00.707843 DUTY Scan : NO K
7103 12:12:00.707927 ZQ Calibration : PASS
7104 12:12:00.711011 Jitter Meter : NO K
7105 12:12:00.714718 CBT Training : PASS
7106 12:12:00.714802 Write leveling : NO K
7107 12:12:00.717560 RX DQS gating : PASS
7108 12:12:00.721383 RX DQ/DQS(RDDQC) : PASS
7109 12:12:00.721493 TX DQ/DQS : PASS
7110 12:12:00.724494 RX DATLAT : PASS
7111 12:12:00.724579 RX DQ/DQS(Engine): PASS
7112 12:12:00.727629 TX OE : NO K
7113 12:12:00.727713 All Pass.
7114 12:12:00.727779
7115 12:12:00.730652 DramC Write-DBI off
7116 12:12:00.734322 PER_BANK_REFRESH: Hybrid Mode
7117 12:12:00.734426 TX_TRACKING: ON
7118 12:12:00.743769 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7119 12:12:00.747515 [FAST_K] Save calibration result to emmc
7120 12:12:00.750477 dramc_set_vcore_voltage set vcore to 725000
7121 12:12:00.754021 Read voltage for 1600, 0
7122 12:12:00.754136 Vio18 = 0
7123 12:12:00.757690 Vcore = 725000
7124 12:12:00.757801 Vdram = 0
7125 12:12:00.757897 Vddq = 0
7126 12:12:00.757988 Vmddr = 0
7127 12:12:00.763926 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7128 12:12:00.770534 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7129 12:12:00.770671 MEM_TYPE=3, freq_sel=13
7130 12:12:00.773699 sv_algorithm_assistance_LP4_3733
7131 12:12:00.777446 ============ PULL DRAM RESETB DOWN ============
7132 12:12:00.784004 ========== PULL DRAM RESETB DOWN end =========
7133 12:12:00.787021 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7134 12:12:00.790712 ===================================
7135 12:12:00.793569 LPDDR4 DRAM CONFIGURATION
7136 12:12:00.797159 ===================================
7137 12:12:00.797271 EX_ROW_EN[0] = 0x0
7138 12:12:00.800112 EX_ROW_EN[1] = 0x0
7139 12:12:00.803726 LP4Y_EN = 0x0
7140 12:12:00.803810 WORK_FSP = 0x1
7141 12:12:00.807231 WL = 0x5
7142 12:12:00.807316 RL = 0x5
7143 12:12:00.810356 BL = 0x2
7144 12:12:00.810429 RPST = 0x0
7145 12:12:00.813455 RD_PRE = 0x0
7146 12:12:00.813540 WR_PRE = 0x1
7147 12:12:00.816619 WR_PST = 0x1
7148 12:12:00.816702 DBI_WR = 0x0
7149 12:12:00.820485 DBI_RD = 0x0
7150 12:12:00.820575 OTF = 0x1
7151 12:12:00.823524 ===================================
7152 12:12:00.826526 ===================================
7153 12:12:00.830192 ANA top config
7154 12:12:00.833339 ===================================
7155 12:12:00.833491 DLL_ASYNC_EN = 0
7156 12:12:00.836478 ALL_SLAVE_EN = 0
7157 12:12:00.839487 NEW_RANK_MODE = 1
7158 12:12:00.843256 DLL_IDLE_MODE = 1
7159 12:12:00.846040 LP45_APHY_COMB_EN = 1
7160 12:12:00.846201 TX_ODT_DIS = 0
7161 12:12:00.849505 NEW_8X_MODE = 1
7162 12:12:00.852861 ===================================
7163 12:12:00.856460 ===================================
7164 12:12:00.859427 data_rate = 3200
7165 12:12:00.862807 CKR = 1
7166 12:12:00.866329 DQ_P2S_RATIO = 8
7167 12:12:00.869418 ===================================
7168 12:12:00.872492 CA_P2S_RATIO = 8
7169 12:12:00.872843 DQ_CA_OPEN = 0
7170 12:12:00.876386 DQ_SEMI_OPEN = 0
7171 12:12:00.879665 CA_SEMI_OPEN = 0
7172 12:12:00.882662 CA_FULL_RATE = 0
7173 12:12:00.885719 DQ_CKDIV4_EN = 0
7174 12:12:00.889471 CA_CKDIV4_EN = 0
7175 12:12:00.889895 CA_PREDIV_EN = 0
7176 12:12:00.892567 PH8_DLY = 12
7177 12:12:00.895765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7178 12:12:00.899310 DQ_AAMCK_DIV = 4
7179 12:12:00.902530 CA_AAMCK_DIV = 4
7180 12:12:00.906121 CA_ADMCK_DIV = 4
7181 12:12:00.909019 DQ_TRACK_CA_EN = 0
7182 12:12:00.909470 CA_PICK = 1600
7183 12:12:00.912482 CA_MCKIO = 1600
7184 12:12:00.915583 MCKIO_SEMI = 0
7185 12:12:00.919377 PLL_FREQ = 3068
7186 12:12:00.922476 DQ_UI_PI_RATIO = 32
7187 12:12:00.925487 CA_UI_PI_RATIO = 0
7188 12:12:00.928965 ===================================
7189 12:12:00.932109 ===================================
7190 12:12:00.935374 memory_type:LPDDR4
7191 12:12:00.935796 GP_NUM : 10
7192 12:12:00.938573 SRAM_EN : 1
7193 12:12:00.939047 MD32_EN : 0
7194 12:12:00.942082 ===================================
7195 12:12:00.945058 [ANA_INIT] >>>>>>>>>>>>>>
7196 12:12:00.948668 <<<<<< [CONFIGURE PHASE]: ANA_TX
7197 12:12:00.951829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7198 12:12:00.955330 ===================================
7199 12:12:00.958319 data_rate = 3200,PCW = 0X7600
7200 12:12:00.961757 ===================================
7201 12:12:00.964781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7202 12:12:00.971494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 12:12:00.975160 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 12:12:00.981543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7205 12:12:00.984675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7206 12:12:00.987946 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7207 12:12:00.988535 [ANA_INIT] flow start
7208 12:12:00.991682 [ANA_INIT] PLL >>>>>>>>
7209 12:12:00.994866 [ANA_INIT] PLL <<<<<<<<
7210 12:12:00.995460 [ANA_INIT] MIDPI >>>>>>>>
7211 12:12:00.997954 [ANA_INIT] MIDPI <<<<<<<<
7212 12:12:01.000981 [ANA_INIT] DLL >>>>>>>>
7213 12:12:01.004665 [ANA_INIT] DLL <<<<<<<<
7214 12:12:01.005239 [ANA_INIT] flow end
7215 12:12:01.007743 ============ LP4 DIFF to SE enter ============
7216 12:12:01.014680 ============ LP4 DIFF to SE exit ============
7217 12:12:01.015316 [ANA_INIT] <<<<<<<<<<<<<
7218 12:12:01.017555 [Flow] Enable top DCM control >>>>>
7219 12:12:01.021059 [Flow] Enable top DCM control <<<<<
7220 12:12:01.024451 Enable DLL master slave shuffle
7221 12:12:01.030720 ==============================================================
7222 12:12:01.031449 Gating Mode config
7223 12:12:01.037306 ==============================================================
7224 12:12:01.041091 Config description:
7225 12:12:01.050594 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7226 12:12:01.057543 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7227 12:12:01.060735 SELPH_MODE 0: By rank 1: By Phase
7228 12:12:01.067373 ==============================================================
7229 12:12:01.070380 GAT_TRACK_EN = 1
7230 12:12:01.073388 RX_GATING_MODE = 2
7231 12:12:01.076895 RX_GATING_TRACK_MODE = 2
7232 12:12:01.077455 SELPH_MODE = 1
7233 12:12:01.080315 PICG_EARLY_EN = 1
7234 12:12:01.083285 VALID_LAT_VALUE = 1
7235 12:12:01.090144 ==============================================================
7236 12:12:01.093221 Enter into Gating configuration >>>>
7237 12:12:01.096333 Exit from Gating configuration <<<<
7238 12:12:01.100272 Enter into DVFS_PRE_config >>>>>
7239 12:12:01.109857 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7240 12:12:01.113103 Exit from DVFS_PRE_config <<<<<
7241 12:12:01.116317 Enter into PICG configuration >>>>
7242 12:12:01.119994 Exit from PICG configuration <<<<
7243 12:12:01.122715 [RX_INPUT] configuration >>>>>
7244 12:12:01.126312 [RX_INPUT] configuration <<<<<
7245 12:12:01.129867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7246 12:12:01.136517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7247 12:12:01.142596 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 12:12:01.149359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 12:12:01.156054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7250 12:12:01.162385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7251 12:12:01.166073 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7252 12:12:01.169216 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7253 12:12:01.172231 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7254 12:12:01.179029 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7255 12:12:01.182637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7256 12:12:01.185630 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7257 12:12:01.189118 ===================================
7258 12:12:01.192663 LPDDR4 DRAM CONFIGURATION
7259 12:12:01.195679 ===================================
7260 12:12:01.196101 EX_ROW_EN[0] = 0x0
7261 12:12:01.199281 EX_ROW_EN[1] = 0x0
7262 12:12:01.199701 LP4Y_EN = 0x0
7263 12:12:01.202511 WORK_FSP = 0x1
7264 12:12:01.205781 WL = 0x5
7265 12:12:01.206203 RL = 0x5
7266 12:12:01.208867 BL = 0x2
7267 12:12:01.209290 RPST = 0x0
7268 12:12:01.212531 RD_PRE = 0x0
7269 12:12:01.212955 WR_PRE = 0x1
7270 12:12:01.215656 WR_PST = 0x1
7271 12:12:01.216076 DBI_WR = 0x0
7272 12:12:01.218741 DBI_RD = 0x0
7273 12:12:01.219224 OTF = 0x1
7274 12:12:01.221895 ===================================
7275 12:12:01.225704 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7276 12:12:01.231958 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7277 12:12:01.235548 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7278 12:12:01.238662 ===================================
7279 12:12:01.242322 LPDDR4 DRAM CONFIGURATION
7280 12:12:01.245251 ===================================
7281 12:12:01.245840 EX_ROW_EN[0] = 0x10
7282 12:12:01.248665 EX_ROW_EN[1] = 0x0
7283 12:12:01.249103 LP4Y_EN = 0x0
7284 12:12:01.251708 WORK_FSP = 0x1
7285 12:12:01.255346 WL = 0x5
7286 12:12:01.255786 RL = 0x5
7287 12:12:01.258267 BL = 0x2
7288 12:12:01.258709 RPST = 0x0
7289 12:12:01.261998 RD_PRE = 0x0
7290 12:12:01.262547 WR_PRE = 0x1
7291 12:12:01.265097 WR_PST = 0x1
7292 12:12:01.265676 DBI_WR = 0x0
7293 12:12:01.268366 DBI_RD = 0x0
7294 12:12:01.268805 OTF = 0x1
7295 12:12:01.271527 ===================================
7296 12:12:01.277956 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7297 12:12:01.278442 ==
7298 12:12:01.281557 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 12:12:01.284788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 12:12:01.288273 ==
7301 12:12:01.288707 [Duty_Offset_Calibration]
7302 12:12:01.291655 B0:2 B1:0 CA:3
7303 12:12:01.292092
7304 12:12:01.294204 [DutyScan_Calibration_Flow] k_type=0
7305 12:12:01.303315
7306 12:12:01.303749 ==CLK 0==
7307 12:12:01.306485 Final CLK duty delay cell = 0
7308 12:12:01.309802 [0] MAX Duty = 5031%(X100), DQS PI = 12
7309 12:12:01.313460 [0] MIN Duty = 4875%(X100), DQS PI = 54
7310 12:12:01.316759 [0] AVG Duty = 4953%(X100)
7311 12:12:01.317271
7312 12:12:01.319943 CH0 CLK Duty spec in!! Max-Min= 156%
7313 12:12:01.323611 [DutyScan_Calibration_Flow] ====Done====
7314 12:12:01.324043
7315 12:12:01.326696 [DutyScan_Calibration_Flow] k_type=1
7316 12:12:01.343335
7317 12:12:01.343899 ==DQS 0 ==
7318 12:12:01.346277 Final DQS duty delay cell = 0
7319 12:12:01.349905 [0] MAX Duty = 5094%(X100), DQS PI = 12
7320 12:12:01.353022 [0] MIN Duty = 4875%(X100), DQS PI = 48
7321 12:12:01.356268 [0] AVG Duty = 4984%(X100)
7322 12:12:01.356913
7323 12:12:01.357464 ==DQS 1 ==
7324 12:12:01.359314 Final DQS duty delay cell = 0
7325 12:12:01.362877 [0] MAX Duty = 5156%(X100), DQS PI = 30
7326 12:12:01.366563 [0] MIN Duty = 5031%(X100), DQS PI = 14
7327 12:12:01.369612 [0] AVG Duty = 5093%(X100)
7328 12:12:01.370177
7329 12:12:01.372848 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7330 12:12:01.373416
7331 12:12:01.375868 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7332 12:12:01.379561 [DutyScan_Calibration_Flow] ====Done====
7333 12:12:01.380048
7334 12:12:01.382508 [DutyScan_Calibration_Flow] k_type=3
7335 12:12:01.400837
7336 12:12:01.401392 ==DQM 0 ==
7337 12:12:01.404484 Final DQM duty delay cell = 0
7338 12:12:01.407760 [0] MAX Duty = 5156%(X100), DQS PI = 30
7339 12:12:01.410680 [0] MIN Duty = 4875%(X100), DQS PI = 0
7340 12:12:01.414537 [0] AVG Duty = 5015%(X100)
7341 12:12:01.414927
7342 12:12:01.415252 ==DQM 1 ==
7343 12:12:01.417694 Final DQM duty delay cell = 4
7344 12:12:01.420825 [4] MAX Duty = 5187%(X100), DQS PI = 60
7345 12:12:01.424055 [4] MIN Duty = 5000%(X100), DQS PI = 14
7346 12:12:01.427213 [4] AVG Duty = 5093%(X100)
7347 12:12:01.427641
7348 12:12:01.431016 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7349 12:12:01.431449
7350 12:12:01.434090 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7351 12:12:01.437106 [DutyScan_Calibration_Flow] ====Done====
7352 12:12:01.437538
7353 12:12:01.440703 [DutyScan_Calibration_Flow] k_type=2
7354 12:12:01.457234
7355 12:12:01.457859 ==DQ 0 ==
7356 12:12:01.460236 Final DQ duty delay cell = -4
7357 12:12:01.463794 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7358 12:12:01.466876 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7359 12:12:01.470330 [-4] AVG Duty = 4938%(X100)
7360 12:12:01.471019
7361 12:12:01.471607 ==DQ 1 ==
7362 12:12:01.473489 Final DQ duty delay cell = 0
7363 12:12:01.476780 [0] MAX Duty = 5156%(X100), DQS PI = 60
7364 12:12:01.480554 [0] MIN Duty = 4969%(X100), DQS PI = 20
7365 12:12:01.483490 [0] AVG Duty = 5062%(X100)
7366 12:12:01.484058
7367 12:12:01.486976 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7368 12:12:01.487577
7369 12:12:01.489825 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7370 12:12:01.493457 [DutyScan_Calibration_Flow] ====Done====
7371 12:12:01.493772 ==
7372 12:12:01.496482 Dram Type= 6, Freq= 0, CH_1, rank 0
7373 12:12:01.499630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7374 12:12:01.499882 ==
7375 12:12:01.503321 [Duty_Offset_Calibration]
7376 12:12:01.503535 B0:1 B1:-2 CA:1
7377 12:12:01.503714
7378 12:12:01.506498 [DutyScan_Calibration_Flow] k_type=0
7379 12:12:01.517080
7380 12:12:01.517199 ==CLK 0==
7381 12:12:01.520770 Final CLK duty delay cell = 0
7382 12:12:01.523786 [0] MAX Duty = 5062%(X100), DQS PI = 22
7383 12:12:01.527512 [0] MIN Duty = 4844%(X100), DQS PI = 58
7384 12:12:01.530620 [0] AVG Duty = 4953%(X100)
7385 12:12:01.530722
7386 12:12:01.533682 CH1 CLK Duty spec in!! Max-Min= 218%
7387 12:12:01.536845 [DutyScan_Calibration_Flow] ====Done====
7388 12:12:01.536924
7389 12:12:01.540479 [DutyScan_Calibration_Flow] k_type=1
7390 12:12:01.556291
7391 12:12:01.556404 ==DQS 0 ==
7392 12:12:01.559684 Final DQS duty delay cell = -4
7393 12:12:01.562630 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7394 12:12:01.566360 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7395 12:12:01.569176 [-4] AVG Duty = 4922%(X100)
7396 12:12:01.569285
7397 12:12:01.569383 ==DQS 1 ==
7398 12:12:01.572546 Final DQS duty delay cell = 0
7399 12:12:01.575966 [0] MAX Duty = 5093%(X100), DQS PI = 60
7400 12:12:01.578975 [0] MIN Duty = 4844%(X100), DQS PI = 24
7401 12:12:01.582600 [0] AVG Duty = 4968%(X100)
7402 12:12:01.582705
7403 12:12:01.585810 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7404 12:12:01.585902
7405 12:12:01.589040 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7406 12:12:01.592518 [DutyScan_Calibration_Flow] ====Done====
7407 12:12:01.592619
7408 12:12:01.595469 [DutyScan_Calibration_Flow] k_type=3
7409 12:12:01.613560
7410 12:12:01.613670 ==DQM 0 ==
7411 12:12:01.616597 Final DQM duty delay cell = 0
7412 12:12:01.619641 [0] MAX Duty = 5031%(X100), DQS PI = 24
7413 12:12:01.623166 [0] MIN Duty = 4813%(X100), DQS PI = 54
7414 12:12:01.626443 [0] AVG Duty = 4922%(X100)
7415 12:12:01.626544
7416 12:12:01.626635 ==DQM 1 ==
7417 12:12:01.629686 Final DQM duty delay cell = 0
7418 12:12:01.633369 [0] MAX Duty = 5062%(X100), DQS PI = 34
7419 12:12:01.636481 [0] MIN Duty = 4875%(X100), DQS PI = 26
7420 12:12:01.639717 [0] AVG Duty = 4968%(X100)
7421 12:12:01.639796
7422 12:12:01.642779 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7423 12:12:01.642886
7424 12:12:01.646355 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7425 12:12:01.649332 [DutyScan_Calibration_Flow] ====Done====
7426 12:12:01.649406
7427 12:12:01.653032 [DutyScan_Calibration_Flow] k_type=2
7428 12:12:01.670373
7429 12:12:01.670496 ==DQ 0 ==
7430 12:12:01.673320 Final DQ duty delay cell = 0
7431 12:12:01.676929 [0] MAX Duty = 5093%(X100), DQS PI = 22
7432 12:12:01.680004 [0] MIN Duty = 4938%(X100), DQS PI = 0
7433 12:12:01.680109 [0] AVG Duty = 5015%(X100)
7434 12:12:01.683598
7435 12:12:01.683703 ==DQ 1 ==
7436 12:12:01.686692 Final DQ duty delay cell = 0
7437 12:12:01.690225 [0] MAX Duty = 5156%(X100), DQS PI = 36
7438 12:12:01.693188 [0] MIN Duty = 4969%(X100), DQS PI = 24
7439 12:12:01.693300 [0] AVG Duty = 5062%(X100)
7440 12:12:01.693396
7441 12:12:01.700515 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7442 12:12:01.700626
7443 12:12:01.703442 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7444 12:12:01.706540 [DutyScan_Calibration_Flow] ====Done====
7445 12:12:01.709707 nWR fixed to 30
7446 12:12:01.709811 [ModeRegInit_LP4] CH0 RK0
7447 12:12:01.713387 [ModeRegInit_LP4] CH0 RK1
7448 12:12:01.716437 [ModeRegInit_LP4] CH1 RK0
7449 12:12:01.720160 [ModeRegInit_LP4] CH1 RK1
7450 12:12:01.720261 match AC timing 5
7451 12:12:01.726250 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7452 12:12:01.729989 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7453 12:12:01.732979 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7454 12:12:01.739909 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7455 12:12:01.743095 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7456 12:12:01.743172 [MiockJmeterHQA]
7457 12:12:01.743244
7458 12:12:01.746106 [DramcMiockJmeter] u1RxGatingPI = 0
7459 12:12:01.749226 0 : 4368, 4140
7460 12:12:01.749333 4 : 4255, 4029
7461 12:12:01.752927 8 : 4257, 4029
7462 12:12:01.753030 12 : 4366, 4140
7463 12:12:01.756022 16 : 4258, 4029
7464 12:12:01.756133 20 : 4255, 4029
7465 12:12:01.756230 24 : 4366, 4139
7466 12:12:01.759061 28 : 4252, 4027
7467 12:12:01.759137 32 : 4368, 4140
7468 12:12:01.762834 36 : 4255, 4029
7469 12:12:01.762946 40 : 4252, 4029
7470 12:12:01.765933 44 : 4255, 4030
7471 12:12:01.766012 48 : 4258, 4032
7472 12:12:01.769033 52 : 4255, 4029
7473 12:12:01.769152 56 : 4252, 4030
7474 12:12:01.769250 60 : 4250, 4027
7475 12:12:01.772055 64 : 4253, 4029
7476 12:12:01.772167 68 : 4257, 4031
7477 12:12:01.775678 72 : 4255, 4029
7478 12:12:01.775792 76 : 4363, 4140
7479 12:12:01.779035 80 : 4255, 4029
7480 12:12:01.779154 84 : 4366, 4140
7481 12:12:01.781928 88 : 4252, 4030
7482 12:12:01.782050 92 : 4253, 4026
7483 12:12:01.782150 96 : 4363, 4140
7484 12:12:01.785558 100 : 4253, 4029
7485 12:12:01.785654 104 : 4255, 3540
7486 12:12:01.788652 108 : 4252, 5
7487 12:12:01.788743 112 : 4258, 0
7488 12:12:01.792180 116 : 4255, 0
7489 12:12:01.792271 120 : 4253, 0
7490 12:12:01.792341 124 : 4257, 0
7491 12:12:01.795068 128 : 4257, 0
7492 12:12:01.795179 132 : 4363, 0
7493 12:12:01.798628 136 : 4363, 0
7494 12:12:01.798745 140 : 4250, 0
7495 12:12:01.798854 144 : 4252, 0
7496 12:12:01.802006 148 : 4255, 0
7497 12:12:01.802094 152 : 4252, 0
7498 12:12:01.804803 156 : 4255, 0
7499 12:12:01.804926 160 : 4365, 0
7500 12:12:01.805026 164 : 4360, 0
7501 12:12:01.808386 168 : 4253, 0
7502 12:12:01.808502 172 : 4253, 0
7503 12:12:01.811467 176 : 4253, 0
7504 12:12:01.811586 180 : 4257, 0
7505 12:12:01.811686 184 : 4252, 0
7506 12:12:01.815105 188 : 4361, 0
7507 12:12:01.815207 192 : 4255, 0
7508 12:12:01.815321 196 : 4252, 0
7509 12:12:01.818163 200 : 4363, 0
7510 12:12:01.818273 204 : 4253, 0
7511 12:12:01.821300 208 : 4254, 0
7512 12:12:01.821415 212 : 4253, 0
7513 12:12:01.821529 216 : 4252, 0
7514 12:12:01.824946 220 : 4257, 0
7515 12:12:01.825036 224 : 4252, 0
7516 12:12:01.828146 228 : 4255, 0
7517 12:12:01.828233 232 : 4258, 0
7518 12:12:01.828301 236 : 4363, 1389
7519 12:12:01.831321 240 : 4253, 4029
7520 12:12:01.831435 244 : 4255, 4029
7521 12:12:01.834902 248 : 4255, 4029
7522 12:12:01.835031 252 : 4252, 4029
7523 12:12:01.838111 256 : 4254, 4029
7524 12:12:01.838239 260 : 4257, 4031
7525 12:12:01.841291 264 : 4255, 4029
7526 12:12:01.841416 268 : 4366, 4140
7527 12:12:01.844400 272 : 4252, 4029
7528 12:12:01.844505 276 : 4255, 4029
7529 12:12:01.848294 280 : 4255, 4029
7530 12:12:01.848384 284 : 4255, 4029
7531 12:12:01.851196 288 : 4363, 4140
7532 12:12:01.851281 292 : 4255, 4029
7533 12:12:01.854358 296 : 4363, 4139
7534 12:12:01.854472 300 : 4366, 4140
7535 12:12:01.854571 304 : 4250, 4026
7536 12:12:01.858050 308 : 4363, 4140
7537 12:12:01.858174 312 : 4255, 4029
7538 12:12:01.861282 316 : 4255, 4029
7539 12:12:01.861398 320 : 4366, 4140
7540 12:12:01.864431 324 : 4252, 4030
7541 12:12:01.864525 328 : 4254, 4029
7542 12:12:01.867592 332 : 4252, 4029
7543 12:12:01.867690 336 : 4363, 4140
7544 12:12:01.870697 340 : 4363, 4139
7545 12:12:01.870816 344 : 4252, 4030
7546 12:12:01.874346 348 : 4255, 4029
7547 12:12:01.874463 352 : 4255, 4006
7548 12:12:01.877764 356 : 4252, 2965
7549 12:12:01.877877 360 : 4255, 1
7550 12:12:01.877983
7551 12:12:01.880807 MIOCK jitter meter ch=0
7552 12:12:01.880919
7553 12:12:01.883937 1T = (360-108) = 252 dly cells
7554 12:12:01.887606 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7555 12:12:01.887725 ==
7556 12:12:01.890522 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 12:12:01.897189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 12:12:01.897313 ==
7559 12:12:01.900883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7560 12:12:01.907378 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7561 12:12:01.910276 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7562 12:12:01.917084 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7563 12:12:01.925284 [CA 0] Center 44 (14~75) winsize 62
7564 12:12:01.928243 [CA 1] Center 43 (13~74) winsize 62
7565 12:12:01.931846 [CA 2] Center 40 (11~69) winsize 59
7566 12:12:01.934967 [CA 3] Center 39 (10~69) winsize 60
7567 12:12:01.938609 [CA 4] Center 37 (8~67) winsize 60
7568 12:12:01.941616 [CA 5] Center 36 (7~66) winsize 60
7569 12:12:01.941727
7570 12:12:01.944841 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7571 12:12:01.944921
7572 12:12:01.951283 [CATrainingPosCal] consider 1 rank data
7573 12:12:01.951387 u2DelayCellTimex100 = 258/100 ps
7574 12:12:01.958198 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7575 12:12:01.961176 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7576 12:12:01.964885 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7577 12:12:01.967979 CA3 delay=39 (10~69),Diff = 3 PI (11 cell)
7578 12:12:01.971139 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7579 12:12:01.974289 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7580 12:12:01.974406
7581 12:12:01.978053 CA PerBit enable=1, Macro0, CA PI delay=36
7582 12:12:01.981202
7583 12:12:01.981299 [CBTSetCACLKResult] CA Dly = 36
7584 12:12:01.984043 CS Dly: 11 (0~42)
7585 12:12:01.987937 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7586 12:12:01.991010 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7587 12:12:01.994076 ==
7588 12:12:01.994188 Dram Type= 6, Freq= 0, CH_0, rank 1
7589 12:12:02.000955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 12:12:02.001104 ==
7591 12:12:02.003962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7592 12:12:02.010914 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7593 12:12:02.013959 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7594 12:12:02.020735 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7595 12:12:02.029145 [CA 0] Center 44 (13~75) winsize 63
7596 12:12:02.032066 [CA 1] Center 43 (13~74) winsize 62
7597 12:12:02.035724 [CA 2] Center 39 (10~69) winsize 60
7598 12:12:02.038753 [CA 3] Center 39 (10~68) winsize 59
7599 12:12:02.041910 [CA 4] Center 37 (8~67) winsize 60
7600 12:12:02.045602 [CA 5] Center 36 (7~66) winsize 60
7601 12:12:02.045739
7602 12:12:02.048557 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7603 12:12:02.052323
7604 12:12:02.055442 [CATrainingPosCal] consider 2 rank data
7605 12:12:02.055552 u2DelayCellTimex100 = 258/100 ps
7606 12:12:02.061731 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7607 12:12:02.065384 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7608 12:12:02.068430 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7609 12:12:02.072255 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7610 12:12:02.075452 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7611 12:12:02.078487 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7612 12:12:02.078601
7613 12:12:02.081556 CA PerBit enable=1, Macro0, CA PI delay=36
7614 12:12:02.085397
7615 12:12:02.085492 [CBTSetCACLKResult] CA Dly = 36
7616 12:12:02.088385 CS Dly: 11 (0~43)
7617 12:12:02.091591 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7618 12:12:02.095206 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7619 12:12:02.095296
7620 12:12:02.098339 ----->DramcWriteLeveling(PI) begin...
7621 12:12:02.101892 ==
7622 12:12:02.104971 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 12:12:02.108002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 12:12:02.108114 ==
7625 12:12:02.111655 Write leveling (Byte 0): 35 => 35
7626 12:12:02.114757 Write leveling (Byte 1): 27 => 27
7627 12:12:02.117966 DramcWriteLeveling(PI) end<-----
7628 12:12:02.118048
7629 12:12:02.118113 ==
7630 12:12:02.121181 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 12:12:02.124741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 12:12:02.124863 ==
7633 12:12:02.127671 [Gating] SW mode calibration
7634 12:12:02.134657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7635 12:12:02.140846 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7636 12:12:02.144579 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 12:12:02.147998 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 12:12:02.154090 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 12:12:02.157647 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 12:12:02.160882 1 4 16 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7641 12:12:02.167869 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7642 12:12:02.170938 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7643 12:12:02.174096 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 12:12:02.180505 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 12:12:02.184312 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 12:12:02.187293 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 12:12:02.193895 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 12:12:02.196911 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7649 12:12:02.200740 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7650 12:12:02.207061 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7651 12:12:02.210595 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 12:12:02.213595 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 12:12:02.220469 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 12:12:02.223553 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 12:12:02.226529 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7656 12:12:02.233597 1 6 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7657 12:12:02.236508 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7658 12:12:02.240091 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7659 12:12:02.246737 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 12:12:02.249929 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 12:12:02.253043 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 12:12:02.259588 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 12:12:02.262651 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 12:12:02.266350 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7665 12:12:02.272751 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7666 12:12:02.276364 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7667 12:12:02.279483 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7668 12:12:02.285735 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:12:02.289502 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:12:02.292566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:12:02.299245 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:12:02.302378 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:12:02.305441 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 12:12:02.312218 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 12:12:02.315520 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 12:12:02.319087 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 12:12:02.325044 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 12:12:02.328881 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 12:12:02.332000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7680 12:12:02.338689 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7681 12:12:02.341640 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7682 12:12:02.345176 Total UI for P1: 0, mck2ui 16
7683 12:12:02.348279 best dqsien dly found for B0: ( 1, 9, 14)
7684 12:12:02.352062 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7685 12:12:02.358418 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7686 12:12:02.361562 Total UI for P1: 0, mck2ui 16
7687 12:12:02.365313 best dqsien dly found for B1: ( 1, 9, 22)
7688 12:12:02.368380 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7689 12:12:02.371896 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7690 12:12:02.371992
7691 12:12:02.374936 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7692 12:12:02.378000 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7693 12:12:02.381772 [Gating] SW calibration Done
7694 12:12:02.381912 ==
7695 12:12:02.384955 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 12:12:02.387849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 12:12:02.387961 ==
7698 12:12:02.391568 RX Vref Scan: 0
7699 12:12:02.391668
7700 12:12:02.394763 RX Vref 0 -> 0, step: 1
7701 12:12:02.394906
7702 12:12:02.394971 RX Delay 0 -> 252, step: 8
7703 12:12:02.401540 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7704 12:12:02.404469 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7705 12:12:02.408140 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7706 12:12:02.411246 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7707 12:12:02.414344 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7708 12:12:02.421287 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7709 12:12:02.424734 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7710 12:12:02.427869 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7711 12:12:02.431194 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7712 12:12:02.434331 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7713 12:12:02.440822 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7714 12:12:02.444224 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7715 12:12:02.447648 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7716 12:12:02.451156 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7717 12:12:02.454202 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7718 12:12:02.461072 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7719 12:12:02.461176 ==
7720 12:12:02.463977 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 12:12:02.467076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 12:12:02.467157 ==
7723 12:12:02.467224 DQS Delay:
7724 12:12:02.470880 DQS0 = 0, DQS1 = 0
7725 12:12:02.470986 DQM Delay:
7726 12:12:02.473828 DQM0 = 128, DQM1 = 124
7727 12:12:02.473930 DQ Delay:
7728 12:12:02.477485 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7729 12:12:02.480536 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =139
7730 12:12:02.483666 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7731 12:12:02.490610 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7732 12:12:02.490720
7733 12:12:02.490815
7734 12:12:02.490917 ==
7735 12:12:02.493573 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 12:12:02.496717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 12:12:02.496821 ==
7738 12:12:02.496912
7739 12:12:02.496974
7740 12:12:02.500482 TX Vref Scan disable
7741 12:12:02.500583 == TX Byte 0 ==
7742 12:12:02.506640 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7743 12:12:02.510104 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7744 12:12:02.510185 == TX Byte 1 ==
7745 12:12:02.516297 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7746 12:12:02.520059 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7747 12:12:02.520136 ==
7748 12:12:02.523141 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 12:12:02.526351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 12:12:02.529565 ==
7751 12:12:02.541701
7752 12:12:02.544591 TX Vref early break, caculate TX vref
7753 12:12:02.548164 TX Vref=16, minBit 8, minWin=21, winSum=357
7754 12:12:02.551757 TX Vref=18, minBit 8, minWin=21, winSum=368
7755 12:12:02.554509 TX Vref=20, minBit 8, minWin=23, winSum=379
7756 12:12:02.557839 TX Vref=22, minBit 8, minWin=23, winSum=388
7757 12:12:02.561356 TX Vref=24, minBit 4, minWin=24, winSum=399
7758 12:12:02.568039 TX Vref=26, minBit 11, minWin=24, winSum=407
7759 12:12:02.571157 TX Vref=28, minBit 8, minWin=23, winSum=402
7760 12:12:02.574302 TX Vref=30, minBit 8, minWin=23, winSum=398
7761 12:12:02.577500 TX Vref=32, minBit 8, minWin=23, winSum=388
7762 12:12:02.581152 TX Vref=34, minBit 8, minWin=22, winSum=378
7763 12:12:02.587764 [TxChooseVref] Worse bit 11, Min win 24, Win sum 407, Final Vref 26
7764 12:12:02.587846
7765 12:12:02.590911 Final TX Range 0 Vref 26
7766 12:12:02.591012
7767 12:12:02.591106 ==
7768 12:12:02.594064 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 12:12:02.597740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 12:12:02.597870 ==
7771 12:12:02.597985
7772 12:12:02.598098
7773 12:12:02.600937 TX Vref Scan disable
7774 12:12:02.607220 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7775 12:12:02.607331 == TX Byte 0 ==
7776 12:12:02.610809 u2DelayCellOfst[0]=15 cells (4 PI)
7777 12:12:02.613755 u2DelayCellOfst[1]=22 cells (6 PI)
7778 12:12:02.616959 u2DelayCellOfst[2]=11 cells (3 PI)
7779 12:12:02.620661 u2DelayCellOfst[3]=15 cells (4 PI)
7780 12:12:02.623790 u2DelayCellOfst[4]=11 cells (3 PI)
7781 12:12:02.626978 u2DelayCellOfst[5]=0 cells (0 PI)
7782 12:12:02.630526 u2DelayCellOfst[6]=22 cells (6 PI)
7783 12:12:02.633654 u2DelayCellOfst[7]=18 cells (5 PI)
7784 12:12:02.636798 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7785 12:12:02.639971 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7786 12:12:02.643772 == TX Byte 1 ==
7787 12:12:02.646679 u2DelayCellOfst[8]=0 cells (0 PI)
7788 12:12:02.650063 u2DelayCellOfst[9]=3 cells (1 PI)
7789 12:12:02.653187 u2DelayCellOfst[10]=7 cells (2 PI)
7790 12:12:02.656750 u2DelayCellOfst[11]=3 cells (1 PI)
7791 12:12:02.659694 u2DelayCellOfst[12]=11 cells (3 PI)
7792 12:12:02.663137 u2DelayCellOfst[13]=11 cells (3 PI)
7793 12:12:02.666424 u2DelayCellOfst[14]=15 cells (4 PI)
7794 12:12:02.669643 u2DelayCellOfst[15]=11 cells (3 PI)
7795 12:12:02.672970 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7796 12:12:02.676645 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7797 12:12:02.679794 DramC Write-DBI on
7798 12:12:02.679894 ==
7799 12:12:02.682985 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 12:12:02.686089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 12:12:02.686170 ==
7802 12:12:02.686234
7803 12:12:02.686292
7804 12:12:02.689630 TX Vref Scan disable
7805 12:12:02.689748 == TX Byte 0 ==
7806 12:12:02.696361 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7807 12:12:02.696467 == TX Byte 1 ==
7808 12:12:02.702508 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7809 12:12:02.702628 DramC Write-DBI off
7810 12:12:02.702723
7811 12:12:02.702816 [DATLAT]
7812 12:12:02.706083 Freq=1600, CH0 RK0
7813 12:12:02.706166
7814 12:12:02.709222 DATLAT Default: 0xf
7815 12:12:02.709336 0, 0xFFFF, sum = 0
7816 12:12:02.712923 1, 0xFFFF, sum = 0
7817 12:12:02.713027 2, 0xFFFF, sum = 0
7818 12:12:02.715942 3, 0xFFFF, sum = 0
7819 12:12:02.716049 4, 0xFFFF, sum = 0
7820 12:12:02.719063 5, 0xFFFF, sum = 0
7821 12:12:02.719146 6, 0xFFFF, sum = 0
7822 12:12:02.722663 7, 0xFFFF, sum = 0
7823 12:12:02.722780 8, 0xFFFF, sum = 0
7824 12:12:02.725793 9, 0xFFFF, sum = 0
7825 12:12:02.725925 10, 0xFFFF, sum = 0
7826 12:12:02.728957 11, 0xFFFF, sum = 0
7827 12:12:02.729058 12, 0xFFFF, sum = 0
7828 12:12:02.732181 13, 0xFFFF, sum = 0
7829 12:12:02.732285 14, 0x0, sum = 1
7830 12:12:02.735924 15, 0x0, sum = 2
7831 12:12:02.736026 16, 0x0, sum = 3
7832 12:12:02.739054 17, 0x0, sum = 4
7833 12:12:02.739131 best_step = 15
7834 12:12:02.739193
7835 12:12:02.739280 ==
7836 12:12:02.742246 Dram Type= 6, Freq= 0, CH_0, rank 0
7837 12:12:02.749218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7838 12:12:02.749333 ==
7839 12:12:02.749428 RX Vref Scan: 1
7840 12:12:02.749528
7841 12:12:02.752226 Set Vref Range= 24 -> 127
7842 12:12:02.752326
7843 12:12:02.755840 RX Vref 24 -> 127, step: 1
7844 12:12:02.755948
7845 12:12:02.758641 RX Delay 11 -> 252, step: 4
7846 12:12:02.758743
7847 12:12:02.762284 Set Vref, RX VrefLevel [Byte0]: 24
7848 12:12:02.765141 [Byte1]: 24
7849 12:12:02.765229
7850 12:12:02.768798 Set Vref, RX VrefLevel [Byte0]: 25
7851 12:12:02.771781 [Byte1]: 25
7852 12:12:02.771883
7853 12:12:02.775334 Set Vref, RX VrefLevel [Byte0]: 26
7854 12:12:02.778550 [Byte1]: 26
7855 12:12:02.781879
7856 12:12:02.781986 Set Vref, RX VrefLevel [Byte0]: 27
7857 12:12:02.784950 [Byte1]: 27
7858 12:12:02.789327
7859 12:12:02.789437 Set Vref, RX VrefLevel [Byte0]: 28
7860 12:12:02.793236 [Byte1]: 28
7861 12:12:02.797156
7862 12:12:02.797264 Set Vref, RX VrefLevel [Byte0]: 29
7863 12:12:02.800561 [Byte1]: 29
7864 12:12:02.804822
7865 12:12:02.804909 Set Vref, RX VrefLevel [Byte0]: 30
7866 12:12:02.807906 [Byte1]: 30
7867 12:12:02.812238
7868 12:12:02.812323 Set Vref, RX VrefLevel [Byte0]: 31
7869 12:12:02.815407 [Byte1]: 31
7870 12:12:02.819703
7871 12:12:02.819787 Set Vref, RX VrefLevel [Byte0]: 32
7872 12:12:02.823326 [Byte1]: 32
7873 12:12:02.827452
7874 12:12:02.827537 Set Vref, RX VrefLevel [Byte0]: 33
7875 12:12:02.830706 [Byte1]: 33
7876 12:12:02.834899
7877 12:12:02.835009 Set Vref, RX VrefLevel [Byte0]: 34
7878 12:12:02.838210 [Byte1]: 34
7879 12:12:02.842552
7880 12:12:02.842666 Set Vref, RX VrefLevel [Byte0]: 35
7881 12:12:02.845667 [Byte1]: 35
7882 12:12:02.849997
7883 12:12:02.850085 Set Vref, RX VrefLevel [Byte0]: 36
7884 12:12:02.853830 [Byte1]: 36
7885 12:12:02.858090
7886 12:12:02.858203 Set Vref, RX VrefLevel [Byte0]: 37
7887 12:12:02.860994 [Byte1]: 37
7888 12:12:02.865216
7889 12:12:02.865331 Set Vref, RX VrefLevel [Byte0]: 38
7890 12:12:02.868669 [Byte1]: 38
7891 12:12:02.872952
7892 12:12:02.873069 Set Vref, RX VrefLevel [Byte0]: 39
7893 12:12:02.876092 [Byte1]: 39
7894 12:12:02.880831
7895 12:12:02.880973 Set Vref, RX VrefLevel [Byte0]: 40
7896 12:12:02.883731 [Byte1]: 40
7897 12:12:02.888329
7898 12:12:02.888446 Set Vref, RX VrefLevel [Byte0]: 41
7899 12:12:02.891289 [Byte1]: 41
7900 12:12:02.895677
7901 12:12:02.895779 Set Vref, RX VrefLevel [Byte0]: 42
7902 12:12:02.899348 [Byte1]: 42
7903 12:12:02.903316
7904 12:12:02.903429 Set Vref, RX VrefLevel [Byte0]: 43
7905 12:12:02.906726 [Byte1]: 43
7906 12:12:02.910948
7907 12:12:02.911032 Set Vref, RX VrefLevel [Byte0]: 44
7908 12:12:02.914440 [Byte1]: 44
7909 12:12:02.918802
7910 12:12:02.918913 Set Vref, RX VrefLevel [Byte0]: 45
7911 12:12:02.922010 [Byte1]: 45
7912 12:12:02.926079
7913 12:12:02.926177 Set Vref, RX VrefLevel [Byte0]: 46
7914 12:12:02.929543 [Byte1]: 46
7915 12:12:02.933867
7916 12:12:02.933965 Set Vref, RX VrefLevel [Byte0]: 47
7917 12:12:02.936996 [Byte1]: 47
7918 12:12:02.941393
7919 12:12:02.941476 Set Vref, RX VrefLevel [Byte0]: 48
7920 12:12:02.945186 [Byte1]: 48
7921 12:12:02.948985
7922 12:12:02.949068 Set Vref, RX VrefLevel [Byte0]: 49
7923 12:12:02.952731 [Byte1]: 49
7924 12:12:02.957030
7925 12:12:02.957114 Set Vref, RX VrefLevel [Byte0]: 50
7926 12:12:02.960158 [Byte1]: 50
7927 12:12:02.964144
7928 12:12:02.964262 Set Vref, RX VrefLevel [Byte0]: 51
7929 12:12:02.967980 [Byte1]: 51
7930 12:12:02.972322
7931 12:12:02.972408 Set Vref, RX VrefLevel [Byte0]: 52
7932 12:12:02.975216 [Byte1]: 52
7933 12:12:02.979807
7934 12:12:02.979882 Set Vref, RX VrefLevel [Byte0]: 53
7935 12:12:02.982760 [Byte1]: 53
7936 12:12:02.987263
7937 12:12:02.987340 Set Vref, RX VrefLevel [Byte0]: 54
7938 12:12:02.990610 [Byte1]: 54
7939 12:12:02.994613
7940 12:12:02.994696 Set Vref, RX VrefLevel [Byte0]: 55
7941 12:12:02.998126 [Byte1]: 55
7942 12:12:03.002668
7943 12:12:03.002743 Set Vref, RX VrefLevel [Byte0]: 56
7944 12:12:03.005622 [Byte1]: 56
7945 12:12:03.009911
7946 12:12:03.009990 Set Vref, RX VrefLevel [Byte0]: 57
7947 12:12:03.013392 [Byte1]: 57
7948 12:12:03.017617
7949 12:12:03.017726 Set Vref, RX VrefLevel [Byte0]: 58
7950 12:12:03.021206 [Byte1]: 58
7951 12:12:03.025592
7952 12:12:03.025666 Set Vref, RX VrefLevel [Byte0]: 59
7953 12:12:03.028554 [Byte1]: 59
7954 12:12:03.032666
7955 12:12:03.032744 Set Vref, RX VrefLevel [Byte0]: 60
7956 12:12:03.036357 [Byte1]: 60
7957 12:12:03.040662
7958 12:12:03.040746 Set Vref, RX VrefLevel [Byte0]: 61
7959 12:12:03.043684 [Byte1]: 61
7960 12:12:03.048044
7961 12:12:03.048127 Set Vref, RX VrefLevel [Byte0]: 62
7962 12:12:03.051674 [Byte1]: 62
7963 12:12:03.055559
7964 12:12:03.055642 Set Vref, RX VrefLevel [Byte0]: 63
7965 12:12:03.059206 [Byte1]: 63
7966 12:12:03.063524
7967 12:12:03.063624 Set Vref, RX VrefLevel [Byte0]: 64
7968 12:12:03.066624 [Byte1]: 64
7969 12:12:03.070949
7970 12:12:03.071033 Set Vref, RX VrefLevel [Byte0]: 65
7971 12:12:03.074039 [Byte1]: 65
7972 12:12:03.078403
7973 12:12:03.078509 Set Vref, RX VrefLevel [Byte0]: 66
7974 12:12:03.081977 [Byte1]: 66
7975 12:12:03.086458
7976 12:12:03.086577 Set Vref, RX VrefLevel [Byte0]: 67
7977 12:12:03.089499 [Byte1]: 67
7978 12:12:03.093596
7979 12:12:03.093681 Set Vref, RX VrefLevel [Byte0]: 68
7980 12:12:03.097407 [Byte1]: 68
7981 12:12:03.101406
7982 12:12:03.101504 Set Vref, RX VrefLevel [Byte0]: 69
7983 12:12:03.104545 [Byte1]: 69
7984 12:12:03.108865
7985 12:12:03.108949 Set Vref, RX VrefLevel [Byte0]: 70
7986 12:12:03.112532 [Byte1]: 70
7987 12:12:03.117125
7988 12:12:03.117211 Set Vref, RX VrefLevel [Byte0]: 71
7989 12:12:03.119790 [Byte1]: 71
7990 12:12:03.124000
7991 12:12:03.124084 Set Vref, RX VrefLevel [Byte0]: 72
7992 12:12:03.127536 [Byte1]: 72
7993 12:12:03.131832
7994 12:12:03.131915 Set Vref, RX VrefLevel [Byte0]: 73
7995 12:12:03.135404 [Byte1]: 73
7996 12:12:03.139660
7997 12:12:03.139744 Set Vref, RX VrefLevel [Byte0]: 74
7998 12:12:03.143062 [Byte1]: 74
7999 12:12:03.147338
8000 12:12:03.147422 Set Vref, RX VrefLevel [Byte0]: 75
8001 12:12:03.150487 [Byte1]: 75
8002 12:12:03.154782
8003 12:12:03.154904 Set Vref, RX VrefLevel [Byte0]: 76
8004 12:12:03.158076 [Byte1]: 76
8005 12:12:03.162448
8006 12:12:03.162557 Final RX Vref Byte 0 = 65 to rank0
8007 12:12:03.165567 Final RX Vref Byte 1 = 59 to rank0
8008 12:12:03.169316 Final RX Vref Byte 0 = 65 to rank1
8009 12:12:03.172227 Final RX Vref Byte 1 = 59 to rank1==
8010 12:12:03.175415 Dram Type= 6, Freq= 0, CH_0, rank 0
8011 12:12:03.182324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 12:12:03.182408 ==
8013 12:12:03.182510 DQS Delay:
8014 12:12:03.185221 DQS0 = 0, DQS1 = 0
8015 12:12:03.185305 DQM Delay:
8016 12:12:03.185372 DQM0 = 126, DQM1 = 120
8017 12:12:03.188922 DQ Delay:
8018 12:12:03.191904 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8019 12:12:03.195043 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8020 12:12:03.198608 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8021 12:12:03.201710 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
8022 12:12:03.201794
8023 12:12:03.201860
8024 12:12:03.201922
8025 12:12:03.205167 [DramC_TX_OE_Calibration] TA2
8026 12:12:03.208567 Original DQ_B0 (3 6) =30, OEN = 27
8027 12:12:03.211570 Original DQ_B1 (3 6) =30, OEN = 27
8028 12:12:03.214654 24, 0x0, End_B0=24 End_B1=24
8029 12:12:03.218550 25, 0x0, End_B0=25 End_B1=25
8030 12:12:03.218663 26, 0x0, End_B0=26 End_B1=26
8031 12:12:03.221614 27, 0x0, End_B0=27 End_B1=27
8032 12:12:03.224705 28, 0x0, End_B0=28 End_B1=28
8033 12:12:03.227695 29, 0x0, End_B0=29 End_B1=29
8034 12:12:03.231172 30, 0x0, End_B0=30 End_B1=30
8035 12:12:03.231257 31, 0x4141, End_B0=30 End_B1=30
8036 12:12:03.234137 Byte0 end_step=30 best_step=27
8037 12:12:03.237753 Byte1 end_step=30 best_step=27
8038 12:12:03.241344 Byte0 TX OE(2T, 0.5T) = (3, 3)
8039 12:12:03.244411 Byte1 TX OE(2T, 0.5T) = (3, 3)
8040 12:12:03.244494
8041 12:12:03.244559
8042 12:12:03.250819 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
8043 12:12:03.254024 CH0 RK0: MR19=303, MR18=1010
8044 12:12:03.260928 CH0_RK0: MR19=0x303, MR18=0x1010, DQSOSC=401, MR23=63, INC=22, DEC=15
8045 12:12:03.261013
8046 12:12:03.264025 ----->DramcWriteLeveling(PI) begin...
8047 12:12:03.264109 ==
8048 12:12:03.266998 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 12:12:03.270753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 12:12:03.273855 ==
8051 12:12:03.273964 Write leveling (Byte 0): 34 => 34
8052 12:12:03.277532 Write leveling (Byte 1): 27 => 27
8053 12:12:03.280624 DramcWriteLeveling(PI) end<-----
8054 12:12:03.280709
8055 12:12:03.280776 ==
8056 12:12:03.283700 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 12:12:03.290121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 12:12:03.290205 ==
8059 12:12:03.293718 [Gating] SW mode calibration
8060 12:12:03.300004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8061 12:12:03.303214 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8062 12:12:03.309831 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 12:12:03.313129 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 12:12:03.316571 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 12:12:03.323226 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8066 12:12:03.326411 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8067 12:12:03.330136 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 12:12:03.336674 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 12:12:03.339538 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 12:12:03.343063 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 12:12:03.349839 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 12:12:03.353051 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8073 12:12:03.356293 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8074 12:12:03.363206 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8075 12:12:03.366323 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8076 12:12:03.369282 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 12:12:03.376212 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 12:12:03.379314 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 12:12:03.382450 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 12:12:03.389289 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8081 12:12:03.392314 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8082 12:12:03.395939 1 6 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8083 12:12:03.402623 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8084 12:12:03.405696 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 12:12:03.408820 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 12:12:03.415412 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 12:12:03.419042 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 12:12:03.421977 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 12:12:03.428584 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 12:12:03.432285 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 12:12:03.435549 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 12:12:03.442272 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 12:12:03.445234 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:12:03.448723 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:12:03.455262 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:12:03.458995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:12:03.462137 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:12:03.468473 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:12:03.472179 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:12:03.475266 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:12:03.481599 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:12:03.485274 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:12:03.488457 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 12:12:03.495229 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 12:12:03.498328 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8106 12:12:03.501917 Total UI for P1: 0, mck2ui 16
8107 12:12:03.504987 best dqsien dly found for B0: ( 1, 9, 6)
8108 12:12:03.508107 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8109 12:12:03.511810 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 12:12:03.518392 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 12:12:03.521395 Total UI for P1: 0, mck2ui 16
8112 12:12:03.525105 best dqsien dly found for B1: ( 1, 9, 20)
8113 12:12:03.528484 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8114 12:12:03.531331 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8115 12:12:03.531413
8116 12:12:03.534891 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8117 12:12:03.538315 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8118 12:12:03.541442 [Gating] SW calibration Done
8119 12:12:03.541541 ==
8120 12:12:03.544579 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 12:12:03.547615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 12:12:03.547698 ==
8123 12:12:03.551293 RX Vref Scan: 0
8124 12:12:03.551401
8125 12:12:03.554762 RX Vref 0 -> 0, step: 1
8126 12:12:03.554902
8127 12:12:03.554982 RX Delay 0 -> 252, step: 8
8128 12:12:03.560939 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8129 12:12:03.564173 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8130 12:12:03.567971 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8131 12:12:03.571093 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8132 12:12:03.574247 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8133 12:12:03.580660 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8134 12:12:03.584487 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8135 12:12:03.587464 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8136 12:12:03.591087 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8137 12:12:03.594127 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8138 12:12:03.601000 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8139 12:12:03.604031 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8140 12:12:03.607066 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8141 12:12:03.610747 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8142 12:12:03.617131 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8143 12:12:03.620365 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8144 12:12:03.620467 ==
8145 12:12:03.624036 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 12:12:03.627222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 12:12:03.627322 ==
8148 12:12:03.630334 DQS Delay:
8149 12:12:03.630432 DQS0 = 0, DQS1 = 0
8150 12:12:03.630521 DQM Delay:
8151 12:12:03.633721 DQM0 = 128, DQM1 = 121
8152 12:12:03.633803 DQ Delay:
8153 12:12:03.636787 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8154 12:12:03.640222 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8155 12:12:03.643751 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8156 12:12:03.650409 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8157 12:12:03.650517
8158 12:12:03.650609
8159 12:12:03.650696 ==
8160 12:12:03.653431 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 12:12:03.657037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 12:12:03.657120 ==
8163 12:12:03.657185
8164 12:12:03.657287
8165 12:12:03.660303 TX Vref Scan disable
8166 12:12:03.660385 == TX Byte 0 ==
8167 12:12:03.666783 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8168 12:12:03.669857 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8169 12:12:03.669980 == TX Byte 1 ==
8170 12:12:03.676692 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8171 12:12:03.679795 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8172 12:12:03.679892 ==
8173 12:12:03.682981 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 12:12:03.686136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 12:12:03.686219 ==
8176 12:12:03.701132
8177 12:12:03.704437 TX Vref early break, caculate TX vref
8178 12:12:03.708083 TX Vref=16, minBit 11, minWin=21, winSum=363
8179 12:12:03.711201 TX Vref=18, minBit 1, minWin=22, winSum=370
8180 12:12:03.714414 TX Vref=20, minBit 8, minWin=22, winSum=382
8181 12:12:03.718108 TX Vref=22, minBit 3, minWin=23, winSum=391
8182 12:12:03.721262 TX Vref=24, minBit 0, minWin=24, winSum=397
8183 12:12:03.727565 TX Vref=26, minBit 0, minWin=24, winSum=405
8184 12:12:03.731157 TX Vref=28, minBit 8, minWin=24, winSum=411
8185 12:12:03.734116 TX Vref=30, minBit 8, minWin=24, winSum=407
8186 12:12:03.737841 TX Vref=32, minBit 9, minWin=23, winSum=396
8187 12:12:03.740766 TX Vref=34, minBit 8, minWin=22, winSum=388
8188 12:12:03.747174 [TxChooseVref] Worse bit 8, Min win 24, Win sum 411, Final Vref 28
8189 12:12:03.747277
8190 12:12:03.750461 Final TX Range 0 Vref 28
8191 12:12:03.750562
8192 12:12:03.750656 ==
8193 12:12:03.753791 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 12:12:03.757281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 12:12:03.757415 ==
8196 12:12:03.757509
8197 12:12:03.757597
8198 12:12:03.760935 TX Vref Scan disable
8199 12:12:03.767545 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8200 12:12:03.767654 == TX Byte 0 ==
8201 12:12:03.770450 u2DelayCellOfst[0]=15 cells (4 PI)
8202 12:12:03.774010 u2DelayCellOfst[1]=18 cells (5 PI)
8203 12:12:03.777220 u2DelayCellOfst[2]=11 cells (3 PI)
8204 12:12:03.780402 u2DelayCellOfst[3]=15 cells (4 PI)
8205 12:12:03.783548 u2DelayCellOfst[4]=7 cells (2 PI)
8206 12:12:03.787248 u2DelayCellOfst[5]=0 cells (0 PI)
8207 12:12:03.790407 u2DelayCellOfst[6]=18 cells (5 PI)
8208 12:12:03.793558 u2DelayCellOfst[7]=18 cells (5 PI)
8209 12:12:03.797215 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8210 12:12:03.800115 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8211 12:12:03.803438 == TX Byte 1 ==
8212 12:12:03.807171 u2DelayCellOfst[8]=3 cells (1 PI)
8213 12:12:03.810398 u2DelayCellOfst[9]=0 cells (0 PI)
8214 12:12:03.813403 u2DelayCellOfst[10]=7 cells (2 PI)
8215 12:12:03.813505 u2DelayCellOfst[11]=7 cells (2 PI)
8216 12:12:03.816877 u2DelayCellOfst[12]=15 cells (4 PI)
8217 12:12:03.819884 u2DelayCellOfst[13]=15 cells (4 PI)
8218 12:12:03.823058 u2DelayCellOfst[14]=15 cells (4 PI)
8219 12:12:03.826914 u2DelayCellOfst[15]=15 cells (4 PI)
8220 12:12:03.833092 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8221 12:12:03.836820 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8222 12:12:03.836926 DramC Write-DBI on
8223 12:12:03.839859 ==
8224 12:12:03.842894 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 12:12:03.846602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 12:12:03.846704 ==
8227 12:12:03.846796
8228 12:12:03.846923
8229 12:12:03.849509 TX Vref Scan disable
8230 12:12:03.849612 == TX Byte 0 ==
8231 12:12:03.855912 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8232 12:12:03.856016 == TX Byte 1 ==
8233 12:12:03.859304 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8234 12:12:03.862932 DramC Write-DBI off
8235 12:12:03.863035
8236 12:12:03.863131 [DATLAT]
8237 12:12:03.866082 Freq=1600, CH0 RK1
8238 12:12:03.866193
8239 12:12:03.866288 DATLAT Default: 0xf
8240 12:12:03.869170 0, 0xFFFF, sum = 0
8241 12:12:03.869255 1, 0xFFFF, sum = 0
8242 12:12:03.872688 2, 0xFFFF, sum = 0
8243 12:12:03.875790 3, 0xFFFF, sum = 0
8244 12:12:03.875887 4, 0xFFFF, sum = 0
8245 12:12:03.879304 5, 0xFFFF, sum = 0
8246 12:12:03.879424 6, 0xFFFF, sum = 0
8247 12:12:03.882315 7, 0xFFFF, sum = 0
8248 12:12:03.882421 8, 0xFFFF, sum = 0
8249 12:12:03.885404 9, 0xFFFF, sum = 0
8250 12:12:03.885506 10, 0xFFFF, sum = 0
8251 12:12:03.889149 11, 0xFFFF, sum = 0
8252 12:12:03.889262 12, 0xFFFF, sum = 0
8253 12:12:03.892297 13, 0xCFFF, sum = 0
8254 12:12:03.892407 14, 0x0, sum = 1
8255 12:12:03.895424 15, 0x0, sum = 2
8256 12:12:03.895525 16, 0x0, sum = 3
8257 12:12:03.898519 17, 0x0, sum = 4
8258 12:12:03.898619 best_step = 15
8259 12:12:03.898711
8260 12:12:03.898838 ==
8261 12:12:03.902132 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 12:12:03.908924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 12:12:03.909038 ==
8264 12:12:03.909132 RX Vref Scan: 0
8265 12:12:03.909226
8266 12:12:03.912055 RX Vref 0 -> 0, step: 1
8267 12:12:03.912155
8268 12:12:03.915136 RX Delay 3 -> 252, step: 4
8269 12:12:03.918254 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8270 12:12:03.921860 iDelay=191, Bit 1, Center 128 (75 ~ 182) 108
8271 12:12:03.925200 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8272 12:12:03.932089 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8273 12:12:03.935353 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8274 12:12:03.938536 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8275 12:12:03.941870 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8276 12:12:03.945048 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8277 12:12:03.951729 iDelay=191, Bit 8, Center 110 (51 ~ 170) 120
8278 12:12:03.954880 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8279 12:12:03.957988 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8280 12:12:03.961382 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8281 12:12:03.967909 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8282 12:12:03.970974 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8283 12:12:03.974766 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8284 12:12:03.977848 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8285 12:12:03.977947 ==
8286 12:12:03.981464 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 12:12:03.987820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 12:12:03.987912 ==
8289 12:12:03.987979 DQS Delay:
8290 12:12:03.990970 DQS0 = 0, DQS1 = 0
8291 12:12:03.991053 DQM Delay:
8292 12:12:03.994142 DQM0 = 125, DQM1 = 117
8293 12:12:03.994236 DQ Delay:
8294 12:12:03.997298 DQ0 =124, DQ1 =128, DQ2 =122, DQ3 =122
8295 12:12:04.001149 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8296 12:12:04.004241 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8297 12:12:04.007113 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8298 12:12:04.007218
8299 12:12:04.007311
8300 12:12:04.007411
8301 12:12:04.010994 [DramC_TX_OE_Calibration] TA2
8302 12:12:04.014110 Original DQ_B0 (3 6) =30, OEN = 27
8303 12:12:04.017074 Original DQ_B1 (3 6) =30, OEN = 27
8304 12:12:04.020784 24, 0x0, End_B0=24 End_B1=24
8305 12:12:04.023956 25, 0x0, End_B0=25 End_B1=25
8306 12:12:04.024069 26, 0x0, End_B0=26 End_B1=26
8307 12:12:04.027138 27, 0x0, End_B0=27 End_B1=27
8308 12:12:04.030183 28, 0x0, End_B0=28 End_B1=28
8309 12:12:04.034036 29, 0x0, End_B0=29 End_B1=29
8310 12:12:04.034138 30, 0x0, End_B0=30 End_B1=30
8311 12:12:04.037141 31, 0x4141, End_B0=30 End_B1=30
8312 12:12:04.040248 Byte0 end_step=30 best_step=27
8313 12:12:04.043415 Byte1 end_step=30 best_step=27
8314 12:12:04.047171 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 12:12:04.050262 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 12:12:04.050332
8317 12:12:04.050399
8318 12:12:04.056821 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8319 12:12:04.059750 CH0 RK1: MR19=303, MR18=2412
8320 12:12:04.066397 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8321 12:12:04.069821 [RxdqsGatingPostProcess] freq 1600
8322 12:12:04.076559 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 12:12:04.079719 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 12:12:04.079815 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 12:12:04.083337 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 12:12:04.086420 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 12:12:04.089430 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 12:12:04.093044 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 12:12:04.096336 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 12:12:04.099558 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 12:12:04.102677 Pre-setting of DQS Precalculation
8332 12:12:04.106361 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 12:12:04.109482 ==
8334 12:12:04.112517 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 12:12:04.115740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 12:12:04.115829 ==
8337 12:12:04.119523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 12:12:04.125582 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 12:12:04.129170 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 12:12:04.135430 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 12:12:04.144199 [CA 0] Center 41 (12~71) winsize 60
8342 12:12:04.147346 [CA 1] Center 42 (12~72) winsize 61
8343 12:12:04.150646 [CA 2] Center 37 (9~66) winsize 58
8344 12:12:04.153680 [CA 3] Center 37 (8~66) winsize 59
8345 12:12:04.157405 [CA 4] Center 37 (8~67) winsize 60
8346 12:12:04.160307 [CA 5] Center 36 (7~66) winsize 60
8347 12:12:04.160383
8348 12:12:04.163971 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 12:12:04.164059
8350 12:12:04.170404 [CATrainingPosCal] consider 1 rank data
8351 12:12:04.170498 u2DelayCellTimex100 = 258/100 ps
8352 12:12:04.176899 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8353 12:12:04.180371 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8354 12:12:04.183565 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8355 12:12:04.186645 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8356 12:12:04.190369 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8357 12:12:04.193425 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 12:12:04.193510
8359 12:12:04.197015 CA PerBit enable=1, Macro0, CA PI delay=36
8360 12:12:04.197122
8361 12:12:04.199946 [CBTSetCACLKResult] CA Dly = 36
8362 12:12:04.203144 CS Dly: 9 (0~40)
8363 12:12:04.206345 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 12:12:04.210150 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 12:12:04.210231 ==
8366 12:12:04.213153 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 12:12:04.219735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 12:12:04.219811 ==
8369 12:12:04.222817 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 12:12:04.229760 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 12:12:04.232848 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 12:12:04.239755 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 12:12:04.247232 [CA 0] Center 42 (13~72) winsize 60
8374 12:12:04.250420 [CA 1] Center 43 (13~73) winsize 61
8375 12:12:04.253602 [CA 2] Center 38 (9~67) winsize 59
8376 12:12:04.257199 [CA 3] Center 36 (7~66) winsize 60
8377 12:12:04.260418 [CA 4] Center 38 (8~68) winsize 61
8378 12:12:04.263676 [CA 5] Center 37 (7~67) winsize 61
8379 12:12:04.263758
8380 12:12:04.267361 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8381 12:12:04.267445
8382 12:12:04.273700 [CATrainingPosCal] consider 2 rank data
8383 12:12:04.273782 u2DelayCellTimex100 = 258/100 ps
8384 12:12:04.280115 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8385 12:12:04.283614 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8386 12:12:04.286921 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8387 12:12:04.289990 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8388 12:12:04.293107 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8389 12:12:04.296773 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 12:12:04.296870
8391 12:12:04.299762 CA PerBit enable=1, Macro0, CA PI delay=36
8392 12:12:04.299842
8393 12:12:04.302899 [CBTSetCACLKResult] CA Dly = 36
8394 12:12:04.306475 CS Dly: 11 (0~44)
8395 12:12:04.309649 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 12:12:04.313261 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 12:12:04.313336
8398 12:12:04.316418 ----->DramcWriteLeveling(PI) begin...
8399 12:12:04.316502 ==
8400 12:12:04.319386 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 12:12:04.326110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 12:12:04.326192 ==
8403 12:12:04.329214 Write leveling (Byte 0): 25 => 25
8404 12:12:04.332863 Write leveling (Byte 1): 28 => 28
8405 12:12:04.336344 DramcWriteLeveling(PI) end<-----
8406 12:12:04.336425
8407 12:12:04.336489 ==
8408 12:12:04.339479 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 12:12:04.342564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 12:12:04.342632 ==
8411 12:12:04.346225 [Gating] SW mode calibration
8412 12:12:04.352327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 12:12:04.359266 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 12:12:04.362467 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 12:12:04.365661 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 12:12:04.372531 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 12:12:04.375606 1 4 12 | B1->B0 | 2727 2423 | 0 1 | (0 0) (1 1)
8418 12:12:04.378805 1 4 16 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
8419 12:12:04.385214 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 12:12:04.388907 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 12:12:04.392359 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 12:12:04.398646 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 12:12:04.402295 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 12:12:04.405526 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 12:12:04.411667 1 5 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8426 12:12:04.415097 1 5 16 | B1->B0 | 2929 2828 | 0 0 | (1 0) (1 0)
8427 12:12:04.418219 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 12:12:04.425082 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 12:12:04.428189 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 12:12:04.431357 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 12:12:04.438211 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 12:12:04.441210 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 12:12:04.444975 1 6 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
8434 12:12:04.451184 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8435 12:12:04.454420 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 12:12:04.458211 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 12:12:04.464383 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 12:12:04.467542 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 12:12:04.471202 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 12:12:04.477566 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 12:12:04.481035 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 12:12:04.484034 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8443 12:12:04.490581 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:12:04.494169 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:12:04.497255 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:12:04.504128 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:12:04.507159 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:12:04.511087 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:12:04.517109 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:12:04.520521 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 12:12:04.523519 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:12:04.530002 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:12:04.533738 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:12:04.536880 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:12:04.543446 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 12:12:04.546547 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 12:12:04.549634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 12:12:04.556375 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 12:12:04.559644 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8460 12:12:04.562750 Total UI for P1: 0, mck2ui 16
8461 12:12:04.566438 best dqsien dly found for B0: ( 1, 9, 14)
8462 12:12:04.569647 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 12:12:04.572810 Total UI for P1: 0, mck2ui 16
8464 12:12:04.575939 best dqsien dly found for B1: ( 1, 9, 16)
8465 12:12:04.579703 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8466 12:12:04.582673 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8467 12:12:04.582793
8468 12:12:04.589589 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8469 12:12:04.592557 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8470 12:12:04.596119 [Gating] SW calibration Done
8471 12:12:04.596239 ==
8472 12:12:04.599197 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 12:12:04.602968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 12:12:04.603079 ==
8475 12:12:04.603145 RX Vref Scan: 0
8476 12:12:04.603207
8477 12:12:04.605961 RX Vref 0 -> 0, step: 1
8478 12:12:04.606090
8479 12:12:04.609392 RX Delay 0 -> 252, step: 8
8480 12:12:04.612397 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8481 12:12:04.615541 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8482 12:12:04.622687 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8483 12:12:04.625794 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8484 12:12:04.629292 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8485 12:12:04.632288 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8486 12:12:04.635635 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8487 12:12:04.642126 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8488 12:12:04.645247 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8489 12:12:04.648924 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8490 12:12:04.652028 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8491 12:12:04.655293 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8492 12:12:04.662347 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8493 12:12:04.665493 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8494 12:12:04.668535 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8495 12:12:04.671763 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8496 12:12:04.671873 ==
8497 12:12:04.675393 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 12:12:04.681508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8499 12:12:04.681618 ==
8500 12:12:04.681731 DQS Delay:
8501 12:12:04.685165 DQS0 = 0, DQS1 = 0
8502 12:12:04.685270 DQM Delay:
8503 12:12:04.688321 DQM0 = 131, DQM1 = 126
8504 12:12:04.688434 DQ Delay:
8505 12:12:04.692058 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8506 12:12:04.695312 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8507 12:12:04.698534 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8508 12:12:04.702042 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8509 12:12:04.702145
8510 12:12:04.702243
8511 12:12:04.702337 ==
8512 12:12:04.704875 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 12:12:04.711682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 12:12:04.711794 ==
8515 12:12:04.711891
8516 12:12:04.711987
8517 12:12:04.712077 TX Vref Scan disable
8518 12:12:04.715125 == TX Byte 0 ==
8519 12:12:04.718111 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8520 12:12:04.724505 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8521 12:12:04.724618 == TX Byte 1 ==
8522 12:12:04.728301 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8523 12:12:04.734886 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8524 12:12:04.734995 ==
8525 12:12:04.737958 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 12:12:04.741002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 12:12:04.741115 ==
8528 12:12:04.754579
8529 12:12:04.758428 TX Vref early break, caculate TX vref
8530 12:12:04.761548 TX Vref=16, minBit 9, minWin=21, winSum=361
8531 12:12:04.764752 TX Vref=18, minBit 9, minWin=21, winSum=370
8532 12:12:04.767928 TX Vref=20, minBit 5, minWin=22, winSum=384
8533 12:12:04.771167 TX Vref=22, minBit 11, minWin=23, winSum=391
8534 12:12:04.774892 TX Vref=24, minBit 5, minWin=24, winSum=400
8535 12:12:04.781049 TX Vref=26, minBit 0, minWin=25, winSum=413
8536 12:12:04.784327 TX Vref=28, minBit 5, minWin=25, winSum=416
8537 12:12:04.787930 TX Vref=30, minBit 9, minWin=24, winSum=413
8538 12:12:04.791033 TX Vref=32, minBit 1, minWin=23, winSum=401
8539 12:12:04.794240 TX Vref=34, minBit 1, minWin=22, winSum=398
8540 12:12:04.801184 TX Vref=36, minBit 0, minWin=22, winSum=380
8541 12:12:04.804357 [TxChooseVref] Worse bit 5, Min win 25, Win sum 416, Final Vref 28
8542 12:12:04.804465
8543 12:12:04.807418 Final TX Range 0 Vref 28
8544 12:12:04.807523
8545 12:12:04.807626 ==
8546 12:12:04.811079 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 12:12:04.813875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 12:12:04.817405 ==
8549 12:12:04.817517
8550 12:12:04.817613
8551 12:12:04.817713 TX Vref Scan disable
8552 12:12:04.824287 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8553 12:12:04.824391 == TX Byte 0 ==
8554 12:12:04.827127 u2DelayCellOfst[0]=15 cells (4 PI)
8555 12:12:04.830842 u2DelayCellOfst[1]=11 cells (3 PI)
8556 12:12:04.833861 u2DelayCellOfst[2]=0 cells (0 PI)
8557 12:12:04.837437 u2DelayCellOfst[3]=7 cells (2 PI)
8558 12:12:04.840577 u2DelayCellOfst[4]=7 cells (2 PI)
8559 12:12:04.843788 u2DelayCellOfst[5]=18 cells (5 PI)
8560 12:12:04.847353 u2DelayCellOfst[6]=18 cells (5 PI)
8561 12:12:04.850339 u2DelayCellOfst[7]=7 cells (2 PI)
8562 12:12:04.853736 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8563 12:12:04.857208 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8564 12:12:04.860183 == TX Byte 1 ==
8565 12:12:04.863859 u2DelayCellOfst[8]=0 cells (0 PI)
8566 12:12:04.867000 u2DelayCellOfst[9]=7 cells (2 PI)
8567 12:12:04.870128 u2DelayCellOfst[10]=15 cells (4 PI)
8568 12:12:04.873332 u2DelayCellOfst[11]=7 cells (2 PI)
8569 12:12:04.877035 u2DelayCellOfst[12]=18 cells (5 PI)
8570 12:12:04.880134 u2DelayCellOfst[13]=22 cells (6 PI)
8571 12:12:04.883206 u2DelayCellOfst[14]=22 cells (6 PI)
8572 12:12:04.883286 u2DelayCellOfst[15]=22 cells (6 PI)
8573 12:12:04.890180 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8574 12:12:04.893351 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8575 12:12:04.897156 DramC Write-DBI on
8576 12:12:04.897255 ==
8577 12:12:04.900228 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 12:12:04.903439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 12:12:04.903547 ==
8580 12:12:04.903644
8581 12:12:04.903733
8582 12:12:04.906557 TX Vref Scan disable
8583 12:12:04.906654 == TX Byte 0 ==
8584 12:12:04.913472 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8585 12:12:04.913578 == TX Byte 1 ==
8586 12:12:04.916594 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8587 12:12:04.919561 DramC Write-DBI off
8588 12:12:04.919673
8589 12:12:04.919776 [DATLAT]
8590 12:12:04.923108 Freq=1600, CH1 RK0
8591 12:12:04.923216
8592 12:12:04.923310 DATLAT Default: 0xf
8593 12:12:04.926184 0, 0xFFFF, sum = 0
8594 12:12:04.926292 1, 0xFFFF, sum = 0
8595 12:12:04.929653 2, 0xFFFF, sum = 0
8596 12:12:04.933049 3, 0xFFFF, sum = 0
8597 12:12:04.933158 4, 0xFFFF, sum = 0
8598 12:12:04.936413 5, 0xFFFF, sum = 0
8599 12:12:04.936522 6, 0xFFFF, sum = 0
8600 12:12:04.939328 7, 0xFFFF, sum = 0
8601 12:12:04.939439 8, 0xFFFF, sum = 0
8602 12:12:04.942929 9, 0xFFFF, sum = 0
8603 12:12:04.943009 10, 0xFFFF, sum = 0
8604 12:12:04.946021 11, 0xFFFF, sum = 0
8605 12:12:04.946097 12, 0xFFFF, sum = 0
8606 12:12:04.949118 13, 0x8FFF, sum = 0
8607 12:12:04.949222 14, 0x0, sum = 1
8608 12:12:04.952921 15, 0x0, sum = 2
8609 12:12:04.953036 16, 0x0, sum = 3
8610 12:12:04.955912 17, 0x0, sum = 4
8611 12:12:04.956015 best_step = 15
8612 12:12:04.956110
8613 12:12:04.956199 ==
8614 12:12:04.959413 Dram Type= 6, Freq= 0, CH_1, rank 0
8615 12:12:04.966131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8616 12:12:04.966245 ==
8617 12:12:04.966344 RX Vref Scan: 1
8618 12:12:04.966436
8619 12:12:04.969008 Set Vref Range= 24 -> 127
8620 12:12:04.969113
8621 12:12:04.972480 RX Vref 24 -> 127, step: 1
8622 12:12:04.972563
8623 12:12:04.972629 RX Delay 11 -> 252, step: 4
8624 12:12:04.975592
8625 12:12:04.975676 Set Vref, RX VrefLevel [Byte0]: 24
8626 12:12:04.978683 [Byte1]: 24
8627 12:12:04.983504
8628 12:12:04.983587 Set Vref, RX VrefLevel [Byte0]: 25
8629 12:12:04.986685 [Byte1]: 25
8630 12:12:04.991047
8631 12:12:04.991131 Set Vref, RX VrefLevel [Byte0]: 26
8632 12:12:04.994179 [Byte1]: 26
8633 12:12:04.998562
8634 12:12:04.998645 Set Vref, RX VrefLevel [Byte0]: 27
8635 12:12:05.001665 [Byte1]: 27
8636 12:12:05.006102
8637 12:12:05.006185 Set Vref, RX VrefLevel [Byte0]: 28
8638 12:12:05.009375 [Byte1]: 28
8639 12:12:05.013786
8640 12:12:05.013870 Set Vref, RX VrefLevel [Byte0]: 29
8641 12:12:05.016948 [Byte1]: 29
8642 12:12:05.021248
8643 12:12:05.021331 Set Vref, RX VrefLevel [Byte0]: 30
8644 12:12:05.024322 [Byte1]: 30
8645 12:12:05.028789
8646 12:12:05.028866 Set Vref, RX VrefLevel [Byte0]: 31
8647 12:12:05.032795 [Byte1]: 31
8648 12:12:05.036549
8649 12:12:05.036653 Set Vref, RX VrefLevel [Byte0]: 32
8650 12:12:05.039924 [Byte1]: 32
8651 12:12:05.044032
8652 12:12:05.044133 Set Vref, RX VrefLevel [Byte0]: 33
8653 12:12:05.047522 [Byte1]: 33
8654 12:12:05.052073
8655 12:12:05.052145 Set Vref, RX VrefLevel [Byte0]: 34
8656 12:12:05.055134 [Byte1]: 34
8657 12:12:05.059555
8658 12:12:05.059625 Set Vref, RX VrefLevel [Byte0]: 35
8659 12:12:05.062497 [Byte1]: 35
8660 12:12:05.067139
8661 12:12:05.067216 Set Vref, RX VrefLevel [Byte0]: 36
8662 12:12:05.070234 [Byte1]: 36
8663 12:12:05.074737
8664 12:12:05.074823 Set Vref, RX VrefLevel [Byte0]: 37
8665 12:12:05.077648 [Byte1]: 37
8666 12:12:05.082227
8667 12:12:05.082311 Set Vref, RX VrefLevel [Byte0]: 38
8668 12:12:05.085379 [Byte1]: 38
8669 12:12:05.089676
8670 12:12:05.089760 Set Vref, RX VrefLevel [Byte0]: 39
8671 12:12:05.092819 [Byte1]: 39
8672 12:12:05.097738
8673 12:12:05.097821 Set Vref, RX VrefLevel [Byte0]: 40
8674 12:12:05.100907 [Byte1]: 40
8675 12:12:05.105303
8676 12:12:05.105387 Set Vref, RX VrefLevel [Byte0]: 41
8677 12:12:05.108404 [Byte1]: 41
8678 12:12:05.112734
8679 12:12:05.112817 Set Vref, RX VrefLevel [Byte0]: 42
8680 12:12:05.115899 [Byte1]: 42
8681 12:12:05.120410
8682 12:12:05.120537 Set Vref, RX VrefLevel [Byte0]: 43
8683 12:12:05.123326 [Byte1]: 43
8684 12:12:05.127717
8685 12:12:05.127803 Set Vref, RX VrefLevel [Byte0]: 44
8686 12:12:05.131489 [Byte1]: 44
8687 12:12:05.135294
8688 12:12:05.135377 Set Vref, RX VrefLevel [Byte0]: 45
8689 12:12:05.139004 [Byte1]: 45
8690 12:12:05.143037
8691 12:12:05.143169 Set Vref, RX VrefLevel [Byte0]: 46
8692 12:12:05.146573 [Byte1]: 46
8693 12:12:05.150626
8694 12:12:05.150738 Set Vref, RX VrefLevel [Byte0]: 47
8695 12:12:05.154099 [Byte1]: 47
8696 12:12:05.158157
8697 12:12:05.158275 Set Vref, RX VrefLevel [Byte0]: 48
8698 12:12:05.161567 [Byte1]: 48
8699 12:12:05.165729
8700 12:12:05.165838 Set Vref, RX VrefLevel [Byte0]: 49
8701 12:12:05.169363 [Byte1]: 49
8702 12:12:05.173611
8703 12:12:05.173695 Set Vref, RX VrefLevel [Byte0]: 50
8704 12:12:05.176824 [Byte1]: 50
8705 12:12:05.180863
8706 12:12:05.180947 Set Vref, RX VrefLevel [Byte0]: 51
8707 12:12:05.184587 [Byte1]: 51
8708 12:12:05.188462
8709 12:12:05.188576 Set Vref, RX VrefLevel [Byte0]: 52
8710 12:12:05.192175 [Byte1]: 52
8711 12:12:05.196380
8712 12:12:05.196464 Set Vref, RX VrefLevel [Byte0]: 53
8713 12:12:05.199510 [Byte1]: 53
8714 12:12:05.203874
8715 12:12:05.203990 Set Vref, RX VrefLevel [Byte0]: 54
8716 12:12:05.206972 [Byte1]: 54
8717 12:12:05.211513
8718 12:12:05.211632 Set Vref, RX VrefLevel [Byte0]: 55
8719 12:12:05.214671 [Byte1]: 55
8720 12:12:05.219028
8721 12:12:05.219139 Set Vref, RX VrefLevel [Byte0]: 56
8722 12:12:05.222246 [Byte1]: 56
8723 12:12:05.226608
8724 12:12:05.226710 Set Vref, RX VrefLevel [Byte0]: 57
8725 12:12:05.229822 [Byte1]: 57
8726 12:12:05.234676
8727 12:12:05.234776 Set Vref, RX VrefLevel [Byte0]: 58
8728 12:12:05.237775 [Byte1]: 58
8729 12:12:05.241980
8730 12:12:05.242083 Set Vref, RX VrefLevel [Byte0]: 59
8731 12:12:05.245249 [Byte1]: 59
8732 12:12:05.249423
8733 12:12:05.249529 Set Vref, RX VrefLevel [Byte0]: 60
8734 12:12:05.252920 [Byte1]: 60
8735 12:12:05.257045
8736 12:12:05.257166 Set Vref, RX VrefLevel [Byte0]: 61
8737 12:12:05.260593 [Byte1]: 61
8738 12:12:05.265222
8739 12:12:05.265362 Set Vref, RX VrefLevel [Byte0]: 62
8740 12:12:05.268055 [Byte1]: 62
8741 12:12:05.272451
8742 12:12:05.272559 Set Vref, RX VrefLevel [Byte0]: 63
8743 12:12:05.275825 [Byte1]: 63
8744 12:12:05.280086
8745 12:12:05.280188 Set Vref, RX VrefLevel [Byte0]: 64
8746 12:12:05.283228 [Byte1]: 64
8747 12:12:05.287571
8748 12:12:05.287672 Set Vref, RX VrefLevel [Byte0]: 65
8749 12:12:05.291157 [Byte1]: 65
8750 12:12:05.295280
8751 12:12:05.295414 Set Vref, RX VrefLevel [Byte0]: 66
8752 12:12:05.298796 [Byte1]: 66
8753 12:12:05.302641
8754 12:12:05.302741 Set Vref, RX VrefLevel [Byte0]: 67
8755 12:12:05.306426 [Byte1]: 67
8756 12:12:05.310855
8757 12:12:05.310943 Set Vref, RX VrefLevel [Byte0]: 68
8758 12:12:05.313895 [Byte1]: 68
8759 12:12:05.318304
8760 12:12:05.318403 Set Vref, RX VrefLevel [Byte0]: 69
8761 12:12:05.321429 [Byte1]: 69
8762 12:12:05.325857
8763 12:12:05.325955 Set Vref, RX VrefLevel [Byte0]: 70
8764 12:12:05.329049 [Byte1]: 70
8765 12:12:05.333583
8766 12:12:05.333682 Final RX Vref Byte 0 = 57 to rank0
8767 12:12:05.336776 Final RX Vref Byte 1 = 53 to rank0
8768 12:12:05.339884 Final RX Vref Byte 0 = 57 to rank1
8769 12:12:05.343489 Final RX Vref Byte 1 = 53 to rank1==
8770 12:12:05.346544 Dram Type= 6, Freq= 0, CH_1, rank 0
8771 12:12:05.352873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 12:12:05.352975 ==
8773 12:12:05.353071 DQS Delay:
8774 12:12:05.356667 DQS0 = 0, DQS1 = 0
8775 12:12:05.356762 DQM Delay:
8776 12:12:05.356852 DQM0 = 131, DQM1 = 123
8777 12:12:05.359614 DQ Delay:
8778 12:12:05.363136 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8779 12:12:05.366138 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8780 12:12:05.369747 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8781 12:12:05.372779 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8782 12:12:05.372900
8783 12:12:05.373000
8784 12:12:05.373093
8785 12:12:05.376382 [DramC_TX_OE_Calibration] TA2
8786 12:12:05.379170 Original DQ_B0 (3 6) =30, OEN = 27
8787 12:12:05.382580 Original DQ_B1 (3 6) =30, OEN = 27
8788 12:12:05.386039 24, 0x0, End_B0=24 End_B1=24
8789 12:12:05.389011 25, 0x0, End_B0=25 End_B1=25
8790 12:12:05.389114 26, 0x0, End_B0=26 End_B1=26
8791 12:12:05.392834 27, 0x0, End_B0=27 End_B1=27
8792 12:12:05.395813 28, 0x0, End_B0=28 End_B1=28
8793 12:12:05.399491 29, 0x0, End_B0=29 End_B1=29
8794 12:12:05.399598 30, 0x0, End_B0=30 End_B1=30
8795 12:12:05.402886 31, 0x4141, End_B0=30 End_B1=30
8796 12:12:05.405564 Byte0 end_step=30 best_step=27
8797 12:12:05.409383 Byte1 end_step=30 best_step=27
8798 12:12:05.412511 Byte0 TX OE(2T, 0.5T) = (3, 3)
8799 12:12:05.415604 Byte1 TX OE(2T, 0.5T) = (3, 3)
8800 12:12:05.415709
8801 12:12:05.415803
8802 12:12:05.422451 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8803 12:12:05.425584 CH1 RK0: MR19=303, MR18=70B
8804 12:12:05.432347 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8805 12:12:05.432451
8806 12:12:05.435551 ----->DramcWriteLeveling(PI) begin...
8807 12:12:05.435653 ==
8808 12:12:05.438902 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 12:12:05.442050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 12:12:05.442155 ==
8811 12:12:05.445119 Write leveling (Byte 0): 24 => 24
8812 12:12:05.448773 Write leveling (Byte 1): 28 => 28
8813 12:12:05.451986 DramcWriteLeveling(PI) end<-----
8814 12:12:05.452083
8815 12:12:05.452173 ==
8816 12:12:05.455081 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 12:12:05.458846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 12:12:05.461989 ==
8819 12:12:05.462112 [Gating] SW mode calibration
8820 12:12:05.471535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8821 12:12:05.475053 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8822 12:12:05.478451 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 12:12:05.485067 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 12:12:05.487878 1 4 8 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
8825 12:12:05.491235 1 4 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8826 12:12:05.498178 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 12:12:05.501078 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 12:12:05.504612 1 4 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 1)
8829 12:12:05.511109 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 12:12:05.514421 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:12:05.517752 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:12:05.524201 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8833 12:12:05.527999 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
8834 12:12:05.531077 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 12:12:05.537447 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 12:12:05.540532 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 12:12:05.544296 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 12:12:05.550508 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:12:05.554130 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8840 12:12:05.557182 1 6 8 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
8841 12:12:05.564053 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8842 12:12:05.567108 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 12:12:05.570408 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 12:12:05.577263 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 12:12:05.580196 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 12:12:05.583795 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:12:05.590110 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:12:05.593591 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8849 12:12:05.597068 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8850 12:12:05.603420 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 12:12:05.606622 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 12:12:05.610309 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 12:12:05.616496 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:12:05.619918 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:12:05.623407 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:12:05.630051 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:12:05.633305 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:12:05.636466 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:12:05.642617 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:12:05.646409 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:12:05.649483 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:12:05.656416 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:12:05.659490 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:12:05.662574 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8865 12:12:05.669433 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8866 12:12:05.672529 Total UI for P1: 0, mck2ui 16
8867 12:12:05.675690 best dqsien dly found for B0: ( 1, 9, 8)
8868 12:12:05.679545 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 12:12:05.682664 Total UI for P1: 0, mck2ui 16
8870 12:12:05.685888 best dqsien dly found for B1: ( 1, 9, 12)
8871 12:12:05.689383 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8872 12:12:05.692175 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8873 12:12:05.692258
8874 12:12:05.695528 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8875 12:12:05.702054 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8876 12:12:05.702150 [Gating] SW calibration Done
8877 12:12:05.702246 ==
8878 12:12:05.705620 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 12:12:05.711927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 12:12:05.712039 ==
8881 12:12:05.712133 RX Vref Scan: 0
8882 12:12:05.712230
8883 12:12:05.715297 RX Vref 0 -> 0, step: 1
8884 12:12:05.715399
8885 12:12:05.719011 RX Delay 0 -> 252, step: 8
8886 12:12:05.722108 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8887 12:12:05.725358 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8888 12:12:05.728270 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8889 12:12:05.735236 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8890 12:12:05.738294 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8891 12:12:05.741488 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8892 12:12:05.745352 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8893 12:12:05.748380 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8894 12:12:05.755123 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8895 12:12:05.758155 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8896 12:12:05.761583 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8897 12:12:05.764711 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8898 12:12:05.768470 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8899 12:12:05.774858 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8900 12:12:05.778061 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8901 12:12:05.781165 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8902 12:12:05.781269 ==
8903 12:12:05.784390 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 12:12:05.788137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 12:12:05.791290 ==
8906 12:12:05.791396 DQS Delay:
8907 12:12:05.791505 DQS0 = 0, DQS1 = 0
8908 12:12:05.794303 DQM Delay:
8909 12:12:05.794409 DQM0 = 132, DQM1 = 128
8910 12:12:05.797734 DQ Delay:
8911 12:12:05.801141 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8912 12:12:05.804256 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8913 12:12:05.807553 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8914 12:12:05.811214 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8915 12:12:05.811376
8916 12:12:05.811477
8917 12:12:05.811553 ==
8918 12:12:05.814189 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 12:12:05.817206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 12:12:05.820719 ==
8921 12:12:05.820832
8922 12:12:05.820937
8923 12:12:05.821039 TX Vref Scan disable
8924 12:12:05.824120 == TX Byte 0 ==
8925 12:12:05.827145 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8926 12:12:05.830752 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 12:12:05.833919 == TX Byte 1 ==
8928 12:12:05.837038 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8929 12:12:05.840589 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8930 12:12:05.843473 ==
8931 12:12:05.847274 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 12:12:05.850377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 12:12:05.850500 ==
8934 12:12:05.862898
8935 12:12:05.866195 TX Vref early break, caculate TX vref
8936 12:12:05.869424 TX Vref=16, minBit 0, minWin=23, winSum=381
8937 12:12:05.872636 TX Vref=18, minBit 0, minWin=23, winSum=392
8938 12:12:05.875785 TX Vref=20, minBit 0, minWin=23, winSum=399
8939 12:12:05.879109 TX Vref=22, minBit 0, minWin=24, winSum=408
8940 12:12:05.882350 TX Vref=24, minBit 0, minWin=24, winSum=415
8941 12:12:05.889490 TX Vref=26, minBit 0, minWin=25, winSum=420
8942 12:12:05.892676 TX Vref=28, minBit 5, minWin=25, winSum=425
8943 12:12:05.895651 TX Vref=30, minBit 1, minWin=24, winSum=419
8944 12:12:05.899399 TX Vref=32, minBit 1, minWin=23, winSum=415
8945 12:12:05.902419 TX Vref=34, minBit 1, minWin=22, winSum=401
8946 12:12:05.909169 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 28
8947 12:12:05.909290
8948 12:12:05.912249 Final TX Range 0 Vref 28
8949 12:12:05.912358
8950 12:12:05.912453 ==
8951 12:12:05.915376 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 12:12:05.919056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 12:12:05.919170 ==
8954 12:12:05.919269
8955 12:12:05.919362
8956 12:12:05.922147 TX Vref Scan disable
8957 12:12:05.929048 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8958 12:12:05.929163 == TX Byte 0 ==
8959 12:12:05.931778 u2DelayCellOfst[0]=18 cells (5 PI)
8960 12:12:05.935689 u2DelayCellOfst[1]=15 cells (4 PI)
8961 12:12:05.938864 u2DelayCellOfst[2]=0 cells (0 PI)
8962 12:12:05.942040 u2DelayCellOfst[3]=7 cells (2 PI)
8963 12:12:05.944963 u2DelayCellOfst[4]=11 cells (3 PI)
8964 12:12:05.948734 u2DelayCellOfst[5]=26 cells (7 PI)
8965 12:12:05.951908 u2DelayCellOfst[6]=22 cells (6 PI)
8966 12:12:05.954978 u2DelayCellOfst[7]=7 cells (2 PI)
8967 12:12:05.958769 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8968 12:12:05.962023 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8969 12:12:05.965311 == TX Byte 1 ==
8970 12:12:05.968325 u2DelayCellOfst[8]=0 cells (0 PI)
8971 12:12:05.971490 u2DelayCellOfst[9]=7 cells (2 PI)
8972 12:12:05.974719 u2DelayCellOfst[10]=15 cells (4 PI)
8973 12:12:05.974844 u2DelayCellOfst[11]=7 cells (2 PI)
8974 12:12:05.977913 u2DelayCellOfst[12]=18 cells (5 PI)
8975 12:12:05.981259 u2DelayCellOfst[13]=18 cells (5 PI)
8976 12:12:05.985036 u2DelayCellOfst[14]=22 cells (6 PI)
8977 12:12:05.988155 u2DelayCellOfst[15]=18 cells (5 PI)
8978 12:12:05.994446 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8979 12:12:05.998214 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8980 12:12:05.998304 DramC Write-DBI on
8981 12:12:06.001315 ==
8982 12:12:06.001429 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 12:12:06.007790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 12:12:06.007917 ==
8985 12:12:06.008021
8986 12:12:06.008122
8987 12:12:06.011165 TX Vref Scan disable
8988 12:12:06.011252 == TX Byte 0 ==
8989 12:12:06.017477 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8990 12:12:06.017563 == TX Byte 1 ==
8991 12:12:06.021209 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8992 12:12:06.024356 DramC Write-DBI off
8993 12:12:06.024442
8994 12:12:06.024509 [DATLAT]
8995 12:12:06.027465 Freq=1600, CH1 RK1
8996 12:12:06.027551
8997 12:12:06.027618 DATLAT Default: 0xf
8998 12:12:06.030878 0, 0xFFFF, sum = 0
8999 12:12:06.030967 1, 0xFFFF, sum = 0
9000 12:12:06.034461 2, 0xFFFF, sum = 0
9001 12:12:06.034548 3, 0xFFFF, sum = 0
9002 12:12:06.037471 4, 0xFFFF, sum = 0
9003 12:12:06.037559 5, 0xFFFF, sum = 0
9004 12:12:06.040742 6, 0xFFFF, sum = 0
9005 12:12:06.040857 7, 0xFFFF, sum = 0
9006 12:12:06.043809 8, 0xFFFF, sum = 0
9007 12:12:06.047588 9, 0xFFFF, sum = 0
9008 12:12:06.047672 10, 0xFFFF, sum = 0
9009 12:12:06.050594 11, 0xFFFF, sum = 0
9010 12:12:06.050683 12, 0xFFFF, sum = 0
9011 12:12:06.053700 13, 0x8FFF, sum = 0
9012 12:12:06.053779 14, 0x0, sum = 1
9013 12:12:06.057226 15, 0x0, sum = 2
9014 12:12:06.057314 16, 0x0, sum = 3
9015 12:12:06.060317 17, 0x0, sum = 4
9016 12:12:06.060403 best_step = 15
9017 12:12:06.060473
9018 12:12:06.060537 ==
9019 12:12:06.064060 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 12:12:06.067193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 12:12:06.070318 ==
9022 12:12:06.070404 RX Vref Scan: 0
9023 12:12:06.070502
9024 12:12:06.073578 RX Vref 0 -> 0, step: 1
9025 12:12:06.073666
9026 12:12:06.076741 RX Delay 11 -> 252, step: 4
9027 12:12:06.079925 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9028 12:12:06.083817 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9029 12:12:06.086431 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9030 12:12:06.093312 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9031 12:12:06.096481 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9032 12:12:06.099652 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9033 12:12:06.103443 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9034 12:12:06.106567 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9035 12:12:06.113330 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9036 12:12:06.116657 iDelay=195, Bit 9, Center 114 (59 ~ 170) 112
9037 12:12:06.119538 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9038 12:12:06.123192 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9039 12:12:06.126263 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9040 12:12:06.132992 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9041 12:12:06.136752 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9042 12:12:06.139697 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9043 12:12:06.139806 ==
9044 12:12:06.142835 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 12:12:06.145951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 12:12:06.149806 ==
9047 12:12:06.149922 DQS Delay:
9048 12:12:06.150040 DQS0 = 0, DQS1 = 0
9049 12:12:06.152699 DQM Delay:
9050 12:12:06.152804 DQM0 = 130, DQM1 = 125
9051 12:12:06.156298 DQ Delay:
9052 12:12:06.159502 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9053 12:12:06.162542 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =126
9054 12:12:06.166132 DQ8 =112, DQ9 =114, DQ10 =130, DQ11 =120
9055 12:12:06.169175 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =136
9056 12:12:06.169252
9057 12:12:06.169318
9058 12:12:06.169378
9059 12:12:06.172395 [DramC_TX_OE_Calibration] TA2
9060 12:12:06.176170 Original DQ_B0 (3 6) =30, OEN = 27
9061 12:12:06.179383 Original DQ_B1 (3 6) =30, OEN = 27
9062 12:12:06.182545 24, 0x0, End_B0=24 End_B1=24
9063 12:12:06.182631 25, 0x0, End_B0=25 End_B1=25
9064 12:12:06.185703 26, 0x0, End_B0=26 End_B1=26
9065 12:12:06.188806 27, 0x0, End_B0=27 End_B1=27
9066 12:12:06.192539 28, 0x0, End_B0=28 End_B1=28
9067 12:12:06.195553 29, 0x0, End_B0=29 End_B1=29
9068 12:12:06.195639 30, 0x0, End_B0=30 End_B1=30
9069 12:12:06.198861 31, 0x4141, End_B0=30 End_B1=30
9070 12:12:06.202583 Byte0 end_step=30 best_step=27
9071 12:12:06.205728 Byte1 end_step=30 best_step=27
9072 12:12:06.208660 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 12:12:06.212268 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 12:12:06.212356
9075 12:12:06.212424
9076 12:12:06.218972 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9077 12:12:06.221955 CH1 RK1: MR19=303, MR18=E1A
9078 12:12:06.228752 CH1_RK1: MR19=0x303, MR18=0xE1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9079 12:12:06.231768 [RxdqsGatingPostProcess] freq 1600
9080 12:12:06.235450 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 12:12:06.238637 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 12:12:06.242112 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 12:12:06.245075 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 12:12:06.248806 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 12:12:06.252031 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 12:12:06.255102 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 12:12:06.258160 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 12:12:06.261900 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 12:12:06.264946 Pre-setting of DQS Precalculation
9090 12:12:06.268083 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 12:12:06.274865 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 12:12:06.284725 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 12:12:06.284809
9094 12:12:06.284874
9095 12:12:06.284950 [Calibration Summary] 3200 Mbps
9096 12:12:06.287974 CH 0, Rank 0
9097 12:12:06.291658 SW Impedance : PASS
9098 12:12:06.291740 DUTY Scan : NO K
9099 12:12:06.294991 ZQ Calibration : PASS
9100 12:12:06.295074 Jitter Meter : NO K
9101 12:12:06.298194 CBT Training : PASS
9102 12:12:06.301430 Write leveling : PASS
9103 12:12:06.301513 RX DQS gating : PASS
9104 12:12:06.304717 RX DQ/DQS(RDDQC) : PASS
9105 12:12:06.307971 TX DQ/DQS : PASS
9106 12:12:06.308063 RX DATLAT : PASS
9107 12:12:06.311147 RX DQ/DQS(Engine): PASS
9108 12:12:06.314091 TX OE : PASS
9109 12:12:06.314161 All Pass.
9110 12:12:06.314222
9111 12:12:06.314281 CH 0, Rank 1
9112 12:12:06.317954 SW Impedance : PASS
9113 12:12:06.320896 DUTY Scan : NO K
9114 12:12:06.320979 ZQ Calibration : PASS
9115 12:12:06.324547 Jitter Meter : NO K
9116 12:12:06.327417 CBT Training : PASS
9117 12:12:06.327500 Write leveling : PASS
9118 12:12:06.330990 RX DQS gating : PASS
9119 12:12:06.334543 RX DQ/DQS(RDDQC) : PASS
9120 12:12:06.334642 TX DQ/DQS : PASS
9121 12:12:06.337541 RX DATLAT : PASS
9122 12:12:06.341242 RX DQ/DQS(Engine): PASS
9123 12:12:06.341351 TX OE : PASS
9124 12:12:06.341465 All Pass.
9125 12:12:06.344295
9126 12:12:06.344397 CH 1, Rank 0
9127 12:12:06.347367 SW Impedance : PASS
9128 12:12:06.347485 DUTY Scan : NO K
9129 12:12:06.350968 ZQ Calibration : PASS
9130 12:12:06.354167 Jitter Meter : NO K
9131 12:12:06.354269 CBT Training : PASS
9132 12:12:06.357213 Write leveling : PASS
9133 12:12:06.357314 RX DQS gating : PASS
9134 12:12:06.360851 RX DQ/DQS(RDDQC) : PASS
9135 12:12:06.363886 TX DQ/DQS : PASS
9136 12:12:06.364014 RX DATLAT : PASS
9137 12:12:06.367625 RX DQ/DQS(Engine): PASS
9138 12:12:06.370840 TX OE : PASS
9139 12:12:06.370982 All Pass.
9140 12:12:06.371076
9141 12:12:06.371156 CH 1, Rank 1
9142 12:12:06.374144 SW Impedance : PASS
9143 12:12:06.377088 DUTY Scan : NO K
9144 12:12:06.377207 ZQ Calibration : PASS
9145 12:12:06.380544 Jitter Meter : NO K
9146 12:12:06.383730 CBT Training : PASS
9147 12:12:06.383815 Write leveling : PASS
9148 12:12:06.387525 RX DQS gating : PASS
9149 12:12:06.390821 RX DQ/DQS(RDDQC) : PASS
9150 12:12:06.390944 TX DQ/DQS : PASS
9151 12:12:06.394151 RX DATLAT : PASS
9152 12:12:06.397349 RX DQ/DQS(Engine): PASS
9153 12:12:06.397432 TX OE : PASS
9154 12:12:06.400731 All Pass.
9155 12:12:06.400815
9156 12:12:06.400895 DramC Write-DBI on
9157 12:12:06.403720 PER_BANK_REFRESH: Hybrid Mode
9158 12:12:06.403798 TX_TRACKING: ON
9159 12:12:06.413210 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 12:12:06.423362 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 12:12:06.430162 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 12:12:06.433152 [FAST_K] Save calibration result to emmc
9163 12:12:06.436823 sync common calibartion params.
9164 12:12:06.436933 sync cbt_mode0:1, 1:1
9165 12:12:06.439864 dram_init: ddr_geometry: 2
9166 12:12:06.443129 dram_init: ddr_geometry: 2
9167 12:12:06.443209 dram_init: ddr_geometry: 2
9168 12:12:06.446170 0:dram_rank_size:100000000
9169 12:12:06.450051 1:dram_rank_size:100000000
9170 12:12:06.456155 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 12:12:06.456238 DFS_SHUFFLE_HW_MODE: ON
9172 12:12:06.462787 dramc_set_vcore_voltage set vcore to 725000
9173 12:12:06.462889 Read voltage for 1600, 0
9174 12:12:06.462960 Vio18 = 0
9175 12:12:06.466401 Vcore = 725000
9176 12:12:06.466476 Vdram = 0
9177 12:12:06.466539 Vddq = 0
9178 12:12:06.469538 Vmddr = 0
9179 12:12:06.469621 switch to 3200 Mbps bootup
9180 12:12:06.472860 [DramcRunTimeConfig]
9181 12:12:06.472958 PHYPLL
9182 12:12:06.476105 DPM_CONTROL_AFTERK: ON
9183 12:12:06.476208 PER_BANK_REFRESH: ON
9184 12:12:06.479372 REFRESH_OVERHEAD_REDUCTION: ON
9185 12:12:06.482747 CMD_PICG_NEW_MODE: OFF
9186 12:12:06.482840 XRTWTW_NEW_MODE: ON
9187 12:12:06.485803 XRTRTR_NEW_MODE: ON
9188 12:12:06.485887 TX_TRACKING: ON
9189 12:12:06.489059 RDSEL_TRACKING: OFF
9190 12:12:06.492978 DQS Precalculation for DVFS: ON
9191 12:12:06.493060 RX_TRACKING: OFF
9192 12:12:06.496218 HW_GATING DBG: ON
9193 12:12:06.496303 ZQCS_ENABLE_LP4: ON
9194 12:12:06.499608 RX_PICG_NEW_MODE: ON
9195 12:12:06.502383 TX_PICG_NEW_MODE: ON
9196 12:12:06.502468 ENABLE_RX_DCM_DPHY: ON
9197 12:12:06.505714 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 12:12:06.509036 DUMMY_READ_FOR_TRACKING: OFF
9199 12:12:06.512416 !!! SPM_CONTROL_AFTERK: OFF
9200 12:12:06.512535 !!! SPM could not control APHY
9201 12:12:06.515617 IMPEDANCE_TRACKING: ON
9202 12:12:06.518851 TEMP_SENSOR: ON
9203 12:12:06.518925 HW_SAVE_FOR_SR: OFF
9204 12:12:06.522595 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 12:12:06.525852 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 12:12:06.529166 Read ODT Tracking: ON
9207 12:12:06.529271 Refresh Rate DeBounce: ON
9208 12:12:06.532070 DFS_NO_QUEUE_FLUSH: ON
9209 12:12:06.535377 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 12:12:06.539089 ENABLE_DFS_RUNTIME_MRW: OFF
9211 12:12:06.539173 DDR_RESERVE_NEW_MODE: ON
9212 12:12:06.542260 MR_CBT_SWITCH_FREQ: ON
9213 12:12:06.545353 =========================
9214 12:12:06.563303 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 12:12:06.566496 dram_init: ddr_geometry: 2
9216 12:12:06.584815 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 12:12:06.588512 dram_init: dram init end (result: 0)
9218 12:12:06.594857 DRAM-K: Full calibration passed in 24536 msecs
9219 12:12:06.598079 MRC: failed to locate region type 0.
9220 12:12:06.598193 DRAM rank0 size:0x100000000,
9221 12:12:06.601306 DRAM rank1 size=0x100000000
9222 12:12:06.611454 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 12:12:06.617961 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 12:12:06.624550 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 12:12:06.634642 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 12:12:06.634735 DRAM rank0 size:0x100000000,
9227 12:12:06.637615 DRAM rank1 size=0x100000000
9228 12:12:06.637691 CBMEM:
9229 12:12:06.641111 IMD: root @ 0xfffff000 254 entries.
9230 12:12:06.644065 IMD: root @ 0xffffec00 62 entries.
9231 12:12:06.647726 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 12:12:06.653946 WARNING: RO_VPD is uninitialized or empty.
9233 12:12:06.657586 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 12:12:06.665112 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 12:12:06.677912 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9236 12:12:06.689483 BS: romstage times (exec / console): total (unknown) / 24006 ms
9237 12:12:06.689596
9238 12:12:06.689704
9239 12:12:06.698849 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 12:12:06.702737 ARM64: Exception handlers installed.
9241 12:12:06.705969 ARM64: Testing exception
9242 12:12:06.709265 ARM64: Done test exception
9243 12:12:06.709383 Enumerating buses...
9244 12:12:06.712533 Show all devs... Before device enumeration.
9245 12:12:06.715828 Root Device: enabled 1
9246 12:12:06.719167 CPU_CLUSTER: 0: enabled 1
9247 12:12:06.719276 CPU: 00: enabled 1
9248 12:12:06.722296 Compare with tree...
9249 12:12:06.722406 Root Device: enabled 1
9250 12:12:06.725734 CPU_CLUSTER: 0: enabled 1
9251 12:12:06.728988 CPU: 00: enabled 1
9252 12:12:06.729104 Root Device scanning...
9253 12:12:06.732365 scan_static_bus for Root Device
9254 12:12:06.735600 CPU_CLUSTER: 0 enabled
9255 12:12:06.738839 scan_static_bus for Root Device done
9256 12:12:06.741913 scan_bus: bus Root Device finished in 8 msecs
9257 12:12:06.741993 done
9258 12:12:06.748626 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 12:12:06.751803 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 12:12:06.758575 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 12:12:06.761533 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 12:12:06.765215 Allocating resources...
9263 12:12:06.768267 Reading resources...
9264 12:12:06.771723 Root Device read_resources bus 0 link: 0
9265 12:12:06.774861 DRAM rank0 size:0x100000000,
9266 12:12:06.774983 DRAM rank1 size=0x100000000
9267 12:12:06.781283 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 12:12:06.781400 CPU: 00 missing read_resources
9269 12:12:06.787740 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 12:12:06.791540 Root Device read_resources bus 0 link: 0 done
9271 12:12:06.794606 Done reading resources.
9272 12:12:06.797841 Show resources in subtree (Root Device)...After reading.
9273 12:12:06.800806 Root Device child on link 0 CPU_CLUSTER: 0
9274 12:12:06.804398 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 12:12:06.814680 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 12:12:06.814804 CPU: 00
9277 12:12:06.821127 Root Device assign_resources, bus 0 link: 0
9278 12:12:06.824283 CPU_CLUSTER: 0 missing set_resources
9279 12:12:06.827351 Root Device assign_resources, bus 0 link: 0 done
9280 12:12:06.827466 Done setting resources.
9281 12:12:06.834284 Show resources in subtree (Root Device)...After assigning values.
9282 12:12:06.837544 Root Device child on link 0 CPU_CLUSTER: 0
9283 12:12:06.840688 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 12:12:06.850932 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 12:12:06.851057 CPU: 00
9286 12:12:06.854062 Done allocating resources.
9287 12:12:06.860800 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 12:12:06.860911 Enabling resources...
9289 12:12:06.863849 done.
9290 12:12:06.866898 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 12:12:06.870333 Initializing devices...
9292 12:12:06.870445 Root Device init
9293 12:12:06.873941 init hardware done!
9294 12:12:06.874055 0x00000018: ctrlr->caps
9295 12:12:06.877066 52.000 MHz: ctrlr->f_max
9296 12:12:06.880101 0.400 MHz: ctrlr->f_min
9297 12:12:06.880217 0x40ff8080: ctrlr->voltages
9298 12:12:06.883704 sclk: 390625
9299 12:12:06.883816 Bus Width = 1
9300 12:12:06.886982 sclk: 390625
9301 12:12:06.887093 Bus Width = 1
9302 12:12:06.890314 Early init status = 3
9303 12:12:06.893540 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 12:12:06.896829 in-header: 03 fb 00 00 01 00 00 00
9305 12:12:06.899920 in-data: 01
9306 12:12:06.903833 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9307 12:12:06.906757 in-header: 03 fb 00 00 01 00 00 00
9308 12:12:06.910478 in-data: 01
9309 12:12:06.913540 [SSUSB] Setting up USB HOST controller...
9310 12:12:06.917041 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9311 12:12:06.920063 [SSUSB] phy power-on done.
9312 12:12:06.923363 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9313 12:12:06.929861 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9314 12:12:06.933175 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9315 12:12:06.940170 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9316 12:12:06.946441 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9317 12:12:06.952963 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9318 12:12:06.960068 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9319 12:12:06.966347 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9320 12:12:06.969607 SPM: binary array size = 0x9dc
9321 12:12:06.973363 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9322 12:12:06.979589 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9323 12:12:06.986402 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9324 12:12:06.992622 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9325 12:12:06.996279 configure_display: Starting display init
9326 12:12:07.030775 anx7625_power_on_init: Init interface.
9327 12:12:07.033964 anx7625_disable_pd_protocol: Disabled PD feature.
9328 12:12:07.037382 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9329 12:12:07.064964 anx7625_start_dp_work: Secure OCM version=00
9330 12:12:07.068074 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9331 12:12:07.082933 sp_tx_get_edid_block: EDID Block = 1
9332 12:12:07.185808 Extracted contents:
9333 12:12:07.189136 header: 00 ff ff ff ff ff ff 00
9334 12:12:07.192409 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9335 12:12:07.195452 version: 01 04
9336 12:12:07.198678 basic params: 95 1f 11 78 0a
9337 12:12:07.201843 chroma info: 76 90 94 55 54 90 27 21 50 54
9338 12:12:07.205139 established: 00 00 00
9339 12:12:07.211708 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9340 12:12:07.215481 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9341 12:12:07.221906 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 12:12:07.228283 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9343 12:12:07.235155 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9344 12:12:07.238305 extensions: 00
9345 12:12:07.238423 checksum: fb
9346 12:12:07.238520
9347 12:12:07.244736 Manufacturer: IVO Model 57d Serial Number 0
9348 12:12:07.244853 Made week 0 of 2020
9349 12:12:07.247923 EDID version: 1.4
9350 12:12:07.248036 Digital display
9351 12:12:07.251226 6 bits per primary color channel
9352 12:12:07.254978 DisplayPort interface
9353 12:12:07.255097 Maximum image size: 31 cm x 17 cm
9354 12:12:07.258047 Gamma: 220%
9355 12:12:07.258155 Check DPMS levels
9356 12:12:07.264275 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9357 12:12:07.267877 First detailed timing is preferred timing
9358 12:12:07.271252 Established timings supported:
9359 12:12:07.271369 Standard timings supported:
9360 12:12:07.274507 Detailed timings
9361 12:12:07.277486 Hex of detail: 383680a07038204018303c0035ae10000019
9362 12:12:07.284281 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9363 12:12:07.287472 0780 0798 07c8 0820 hborder 0
9364 12:12:07.290525 0438 043b 0447 0458 vborder 0
9365 12:12:07.294333 -hsync -vsync
9366 12:12:07.294448 Did detailed timing
9367 12:12:07.301125 Hex of detail: 000000000000000000000000000000000000
9368 12:12:07.303930 Manufacturer-specified data, tag 0
9369 12:12:07.307185 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9370 12:12:07.310450 ASCII string: InfoVision
9371 12:12:07.313659 Hex of detail: 000000fe00523134304e574635205248200a
9372 12:12:07.316996 ASCII string: R140NWF5 RH
9373 12:12:07.317106 Checksum
9374 12:12:07.320162 Checksum: 0xfb (valid)
9375 12:12:07.323567 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9376 12:12:07.326819 DSI data_rate: 832800000 bps
9377 12:12:07.333540 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9378 12:12:07.336700 anx7625_parse_edid: pixelclock(138800).
9379 12:12:07.340487 hactive(1920), hsync(48), hfp(24), hbp(88)
9380 12:12:07.343614 vactive(1080), vsync(12), vfp(3), vbp(17)
9381 12:12:07.346566 anx7625_dsi_config: config dsi.
9382 12:12:07.353384 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9383 12:12:07.367655 anx7625_dsi_config: success to config DSI
9384 12:12:07.370725 anx7625_dp_start: MIPI phy setup OK.
9385 12:12:07.374237 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9386 12:12:07.377402 mtk_ddp_mode_set invalid vrefresh 60
9387 12:12:07.380886 main_disp_path_setup
9388 12:12:07.380998 ovl_layer_smi_id_en
9389 12:12:07.383999 ovl_layer_smi_id_en
9390 12:12:07.384102 ccorr_config
9391 12:12:07.384196 aal_config
9392 12:12:07.387502 gamma_config
9393 12:12:07.387615 postmask_config
9394 12:12:07.390465 dither_config
9395 12:12:07.394011 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9396 12:12:07.400213 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9397 12:12:07.403478 Root Device init finished in 529 msecs
9398 12:12:07.407079 CPU_CLUSTER: 0 init
9399 12:12:07.413482 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9400 12:12:07.420501 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9401 12:12:07.420613 APU_MBOX 0x190000b0 = 0x10001
9402 12:12:07.423778 APU_MBOX 0x190001b0 = 0x10001
9403 12:12:07.426868 APU_MBOX 0x190005b0 = 0x10001
9404 12:12:07.430037 APU_MBOX 0x190006b0 = 0x10001
9405 12:12:07.436405 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9406 12:12:07.446359 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9407 12:12:07.458738 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9408 12:12:07.465623 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9409 12:12:07.477125 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9410 12:12:07.486565 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9411 12:12:07.489600 CPU_CLUSTER: 0 init finished in 81 msecs
9412 12:12:07.493146 Devices initialized
9413 12:12:07.496093 Show all devs... After init.
9414 12:12:07.496199 Root Device: enabled 1
9415 12:12:07.499477 CPU_CLUSTER: 0: enabled 1
9416 12:12:07.502942 CPU: 00: enabled 1
9417 12:12:07.506045 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9418 12:12:07.509190 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9419 12:12:07.512898 ELOG: NV offset 0x57f000 size 0x1000
9420 12:12:07.519498 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9421 12:12:07.525794 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9422 12:12:07.529676 ELOG: Event(17) added with size 13 at 2023-06-06 12:12:13 UTC
9423 12:12:07.535851 out: cmd=0x121: 03 db 21 01 00 00 00 00
9424 12:12:07.539099 in-header: 03 93 00 00 2c 00 00 00
9425 12:12:07.552401 in-data: cc 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9426 12:12:07.555480 ELOG: Event(A1) added with size 10 at 2023-06-06 12:12:13 UTC
9427 12:12:07.565317 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9428 12:12:07.569047 ELOG: Event(A0) added with size 9 at 2023-06-06 12:12:13 UTC
9429 12:12:07.572131 elog_add_boot_reason: Logged dev mode boot
9430 12:12:07.578540 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9431 12:12:07.582256 Finalize devices...
9432 12:12:07.582348 Devices finalized
9433 12:12:07.588319 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9434 12:12:07.591389 Writing coreboot table at 0xffe64000
9435 12:12:07.594925 0. 000000000010a000-0000000000113fff: RAMSTAGE
9436 12:12:07.598304 1. 0000000040000000-00000000400fffff: RAM
9437 12:12:07.601625 2. 0000000040100000-000000004032afff: RAMSTAGE
9438 12:12:07.604588 3. 000000004032b000-00000000545fffff: RAM
9439 12:12:07.611707 4. 0000000054600000-000000005465ffff: BL31
9440 12:12:07.614886 5. 0000000054660000-00000000ffe63fff: RAM
9441 12:12:07.617952 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9442 12:12:07.621127 7. 0000000100000000-000000023fffffff: RAM
9443 12:12:07.624948 Passing 5 GPIOs to payload:
9444 12:12:07.631135 NAME | PORT | POLARITY | VALUE
9445 12:12:07.634845 EC in RW | 0x000000aa | low | undefined
9446 12:12:07.638008 EC interrupt | 0x00000005 | low | undefined
9447 12:12:07.644328 TPM interrupt | 0x000000ab | high | undefined
9448 12:12:07.647499 SD card detect | 0x00000011 | high | undefined
9449 12:12:07.654589 speaker enable | 0x00000093 | high | undefined
9450 12:12:07.657771 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9451 12:12:07.660999 in-header: 03 f9 00 00 02 00 00 00
9452 12:12:07.661107 in-data: 02 00
9453 12:12:07.664313 ADC[4]: Raw value=892971 ID=7
9454 12:12:07.667781 ADC[3]: Raw value=213440 ID=1
9455 12:12:07.667888 RAM Code: 0x71
9456 12:12:07.670633 ADC[6]: Raw value=74722 ID=0
9457 12:12:07.674422 ADC[5]: Raw value=212330 ID=1
9458 12:12:07.674532 SKU Code: 0x1
9459 12:12:07.680745 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9460 12:12:07.684039 coreboot table: 964 bytes.
9461 12:12:07.687106 IMD ROOT 0. 0xfffff000 0x00001000
9462 12:12:07.690774 IMD SMALL 1. 0xffffe000 0x00001000
9463 12:12:07.693889 RO MCACHE 2. 0xffffc000 0x00001104
9464 12:12:07.697554 CONSOLE 3. 0xfff7c000 0x00080000
9465 12:12:07.700595 FMAP 4. 0xfff7b000 0x00000452
9466 12:12:07.703639 TIME STAMP 5. 0xfff7a000 0x00000910
9467 12:12:07.707300 VBOOT WORK 6. 0xfff66000 0x00014000
9468 12:12:07.710440 RAMOOPS 7. 0xffe66000 0x00100000
9469 12:12:07.713485 COREBOOT 8. 0xffe64000 0x00002000
9470 12:12:07.713591 IMD small region:
9471 12:12:07.717035 IMD ROOT 0. 0xffffec00 0x00000400
9472 12:12:07.720103 VPD 1. 0xffffeba0 0x0000004c
9473 12:12:07.723896 MMC STATUS 2. 0xffffeb80 0x00000004
9474 12:12:07.729949 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9475 12:12:07.733378 Probing TPM: done!
9476 12:12:07.736622 Connected to device vid:did:rid of 1ae0:0028:00
9477 12:12:07.746946 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9478 12:12:07.750304 Initialized TPM device CR50 revision 0
9479 12:12:07.753547 Checking cr50 for pending updates
9480 12:12:07.756967 Reading cr50 TPM mode
9481 12:12:07.765340 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9482 12:12:07.772227 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 12:12:07.812374 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9484 12:12:07.815518 Checking segment from ROM address 0x40100000
9485 12:12:07.819166 Checking segment from ROM address 0x4010001c
9486 12:12:07.825538 Loading segment from ROM address 0x40100000
9487 12:12:07.825650 code (compression=0)
9488 12:12:07.835753 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 12:12:07.842423 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 12:12:07.842509 it's not compressed!
9491 12:12:07.848846 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 12:12:07.855135 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 12:12:07.873100 Loading segment from ROM address 0x4010001c
9494 12:12:07.873227 Entry Point 0x80000000
9495 12:12:07.876339 Loaded segments
9496 12:12:07.879771 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 12:12:07.885846 Jumping to boot code at 0x80000000(0xffe64000)
9498 12:12:07.892740 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 12:12:07.899271 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 12:12:07.907404 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9501 12:12:07.910464 Checking segment from ROM address 0x40100000
9502 12:12:07.914103 Checking segment from ROM address 0x4010001c
9503 12:12:07.920743 Loading segment from ROM address 0x40100000
9504 12:12:07.920860 code (compression=1)
9505 12:12:07.927334 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 12:12:07.937207 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 12:12:07.937297 using LZMA
9508 12:12:07.945668 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 12:12:07.952486 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 12:12:07.955126 Loading segment from ROM address 0x4010001c
9511 12:12:07.955235 Entry Point 0x54601000
9512 12:12:07.958436 Loaded segments
9513 12:12:07.961684 NOTICE: MT8192 bl31_setup
9514 12:12:07.969134 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 12:12:07.972352 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 12:12:07.975515 WARNING: region 0:
9517 12:12:07.978760 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 12:12:07.978893 WARNING: region 1:
9519 12:12:07.985758 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 12:12:07.988920 WARNING: region 2:
9521 12:12:07.992105 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 12:12:07.995234 WARNING: region 3:
9523 12:12:07.998706 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 12:12:08.001859 WARNING: region 4:
9525 12:12:08.009014 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 12:12:08.009129 WARNING: region 5:
9527 12:12:08.012101 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 12:12:08.015113 WARNING: region 6:
9529 12:12:08.018632 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 12:12:08.022221 WARNING: region 7:
9531 12:12:08.025312 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 12:12:08.031882 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 12:12:08.035413 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 12:12:08.041576 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 12:12:08.045294 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 12:12:08.048472 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 12:12:08.054702 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 12:12:08.058517 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 12:12:08.061705 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 12:12:08.067930 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 12:12:08.071186 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 12:12:08.078388 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 12:12:08.081682 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 12:12:08.084826 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 12:12:08.091115 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 12:12:08.094329 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 12:12:08.098320 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 12:12:08.104497 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 12:12:08.107836 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 12:12:08.114551 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 12:12:08.117846 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 12:12:08.120793 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 12:12:08.127814 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 12:12:08.130778 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 12:12:08.137470 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 12:12:08.141068 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 12:12:08.144617 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 12:12:08.150809 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 12:12:08.154160 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 12:12:08.160727 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 12:12:08.163949 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 12:12:08.167815 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 12:12:08.174271 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 12:12:08.177317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 12:12:08.180595 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 12:12:08.187569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 12:12:08.190796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 12:12:08.193822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 12:12:08.197098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 12:12:08.204279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 12:12:08.207257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 12:12:08.210251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 12:12:08.214244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 12:12:08.220681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 12:12:08.224055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 12:12:08.226890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 12:12:08.230560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 12:12:08.237068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 12:12:08.240071 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 12:12:08.243619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 12:12:08.250484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 12:12:08.253867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 12:12:08.260041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 12:12:08.263843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 12:12:08.270339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 12:12:08.273636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 12:12:08.276748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 12:12:08.283447 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 12:12:08.286695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 12:12:08.293620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 12:12:08.296946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 12:12:08.303533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 12:12:08.306590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 12:12:08.313049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 12:12:08.316669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 12:12:08.319889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 12:12:08.326761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 12:12:08.329968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 12:12:08.336286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 12:12:08.340044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 12:12:08.346263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 12:12:08.349965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 12:12:08.352936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 12:12:08.360002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 12:12:08.362785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 12:12:08.369475 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 12:12:08.373164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 12:12:08.379689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 12:12:08.382800 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 12:12:08.389773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 12:12:08.392827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 12:12:08.395991 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 12:12:08.403072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 12:12:08.406304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 12:12:08.412628 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 12:12:08.416562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 12:12:08.422647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 12:12:08.426509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 12:12:08.429794 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 12:12:08.435952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 12:12:08.439425 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 12:12:08.446303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 12:12:08.449268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 12:12:08.455842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 12:12:08.459357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 12:12:08.465966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 12:12:08.468943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 12:12:08.472345 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 12:12:08.478680 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 12:12:08.482617 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 12:12:08.485799 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 12:12:08.489052 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 12:12:08.495577 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 12:12:08.498659 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 12:12:08.505664 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 12:12:08.508831 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 12:12:08.511976 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 12:12:08.518937 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 12:12:08.522305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 12:12:08.528944 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 12:12:08.532125 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 12:12:08.535419 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 12:12:08.541762 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 12:12:08.545184 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 12:12:08.552192 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 12:12:08.555394 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 12:12:08.558364 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 12:12:08.565068 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 12:12:08.568630 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 12:12:08.571638 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 12:12:08.578584 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 12:12:08.581927 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 12:12:08.584811 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 12:12:08.588640 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 12:12:08.595116 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 12:12:08.598359 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 12:12:08.601402 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 12:12:08.608383 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 12:12:08.611698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 12:12:08.618481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 12:12:08.621528 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 12:12:08.624681 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 12:12:08.631474 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 12:12:08.635043 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 12:12:08.638063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 12:12:08.644457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 12:12:08.648206 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 12:12:08.654560 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 12:12:08.657817 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 12:12:08.660979 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 12:12:08.667589 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 12:12:08.671009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 12:12:08.677780 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 12:12:08.681298 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 12:12:08.684523 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 12:12:08.691053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 12:12:08.694506 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 12:12:08.700871 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 12:12:08.704328 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 12:12:08.708032 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 12:12:08.714344 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 12:12:08.717396 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 12:12:08.724258 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 12:12:08.727482 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 12:12:08.730641 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 12:12:08.737317 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 12:12:08.740444 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 12:12:08.747269 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 12:12:08.750335 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 12:12:08.753812 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 12:12:08.760150 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 12:12:08.763501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 12:12:08.770103 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 12:12:08.773755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 12:12:08.776713 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 12:12:08.783492 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 12:12:08.786559 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 12:12:08.793569 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 12:12:08.796590 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 12:12:08.800151 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 12:12:08.806271 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 12:12:08.809857 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 12:12:08.816409 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 12:12:08.820005 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 12:12:08.823083 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 12:12:08.829400 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 12:12:08.833127 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 12:12:08.839864 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 12:12:08.842981 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 12:12:08.846078 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 12:12:08.852660 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 12:12:08.855679 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 12:12:08.862450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 12:12:08.865527 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 12:12:08.869335 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 12:12:08.875944 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 12:12:08.879077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 12:12:08.885471 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 12:12:08.889009 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 12:12:08.892010 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 12:12:08.898526 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 12:12:08.901997 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 12:12:08.908396 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 12:12:08.911883 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 12:12:08.918705 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 12:12:08.921666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 12:12:08.925296 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 12:12:08.931703 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 12:12:08.935253 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 12:12:08.941513 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 12:12:08.944810 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 12:12:08.951372 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 12:12:08.955103 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 12:12:08.958358 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 12:12:08.964392 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 12:12:08.968159 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 12:12:08.974451 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 12:12:08.977694 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 12:12:08.984386 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 12:12:08.987550 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 12:12:08.990700 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 12:12:08.997869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 12:12:09.000887 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 12:12:09.007636 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 12:12:09.010548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 12:12:09.017506 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 12:12:09.020478 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 12:12:09.023907 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 12:12:09.030483 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 12:12:09.033736 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 12:12:09.040103 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 12:12:09.043917 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 12:12:09.050164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 12:12:09.053964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 12:12:09.057091 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 12:12:09.063231 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 12:12:09.066781 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 12:12:09.073378 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 12:12:09.076535 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 12:12:09.082750 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 12:12:09.086501 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 12:12:09.089368 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 12:12:09.092986 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 12:12:09.099254 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 12:12:09.103106 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 12:12:09.106035 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 12:12:09.112308 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 12:12:09.115811 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 12:12:09.119243 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 12:12:09.125848 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 12:12:09.129112 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 12:12:09.132540 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 12:12:09.138912 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 12:12:09.142011 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 12:12:09.148539 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 12:12:09.151843 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 12:12:09.155036 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 12:12:09.162068 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 12:12:09.165249 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 12:12:09.168128 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 12:12:09.174813 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 12:12:09.178519 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 12:12:09.184865 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 12:12:09.188055 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 12:12:09.191138 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 12:12:09.198111 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 12:12:09.201362 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 12:12:09.207859 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 12:12:09.211012 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 12:12:09.215001 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 12:12:09.221403 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 12:12:09.224355 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 12:12:09.227937 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 12:12:09.234447 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 12:12:09.238004 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 12:12:09.241027 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 12:12:09.247707 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 12:12:09.250832 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 12:12:09.257296 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 12:12:09.260487 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 12:12:09.263667 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 12:12:09.266957 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 12:12:09.273846 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 12:12:09.276880 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 12:12:09.280562 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 12:12:09.283740 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 12:12:09.289945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 12:12:09.293844 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 12:12:09.297002 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 12:12:09.300129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 12:12:09.306454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 12:12:09.310332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 12:12:09.313454 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 12:12:09.320292 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 12:12:09.323385 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 12:12:09.329961 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 12:12:09.333024 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 12:12:09.339519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 12:12:09.343231 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 12:12:09.346153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 12:12:09.352643 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 12:12:09.355741 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 12:12:09.362717 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 12:12:09.365911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 12:12:09.369170 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 12:12:09.375552 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 12:12:09.378807 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 12:12:09.385509 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 12:12:09.389038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 12:12:09.395379 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 12:12:09.398976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 12:12:09.402197 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 12:12:09.408581 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 12:12:09.411824 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 12:12:09.418795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 12:12:09.421950 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 12:12:09.425116 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 12:12:09.431813 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 12:12:09.434803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 12:12:09.441889 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 12:12:09.445024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 12:12:09.451327 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 12:12:09.454815 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 12:12:09.461678 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 12:12:09.464671 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 12:12:09.467686 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 12:12:09.474573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 12:12:09.477716 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 12:12:09.484698 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 12:12:09.487691 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 12:12:09.490889 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 12:12:09.498118 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 12:12:09.501223 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 12:12:09.507376 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 12:12:09.510586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 12:12:09.513804 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 12:12:09.520716 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 12:12:09.523877 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 12:12:09.530651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 12:12:09.533841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 12:12:09.540620 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 12:12:09.543849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 12:12:09.546642 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 12:12:09.553395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 12:12:09.556982 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 12:12:09.563368 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 12:12:09.566797 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 12:12:09.573465 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 12:12:09.576700 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 12:12:09.579833 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 12:12:09.586805 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 12:12:09.589887 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 12:12:09.596821 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 12:12:09.599771 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 12:12:09.602820 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 12:12:09.609495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 12:12:09.613046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 12:12:09.619265 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 12:12:09.623045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 12:12:09.629341 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 12:12:09.632520 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 12:12:09.636091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 12:12:09.642759 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 12:12:09.645911 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 12:12:09.652314 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 12:12:09.655715 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 12:12:09.662314 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 12:12:09.665489 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 12:12:09.668968 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 12:12:09.675589 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 12:12:09.678664 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 12:12:09.685554 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 12:12:09.688669 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 12:12:09.695274 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 12:12:09.698335 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 12:12:09.705105 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 12:12:09.708189 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 12:12:09.711840 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 12:12:09.717972 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 12:12:09.721660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 12:12:09.728187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 12:12:09.731356 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 12:12:09.738054 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 12:12:09.741439 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 12:12:09.747766 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 12:12:09.750866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 12:12:09.757905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 12:12:09.761014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 12:12:09.764526 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 12:12:09.770971 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 12:12:09.774502 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 12:12:09.780801 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 12:12:09.784469 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 12:12:09.790679 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 12:12:09.793803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 12:12:09.800486 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 12:12:09.803679 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 12:12:09.807449 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 12:12:09.813676 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 12:12:09.817323 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 12:12:09.823865 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 12:12:09.827012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 12:12:09.833764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 12:12:09.836993 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 12:12:09.840187 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 12:12:09.846809 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 12:12:09.849927 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 12:12:09.856917 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 12:12:09.860053 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 12:12:09.866779 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 12:12:09.869882 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 12:12:09.876456 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 12:12:09.879988 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 12:12:09.882874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 12:12:09.889388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 12:12:09.893259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 12:12:09.899560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 12:12:09.902584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 12:12:09.909161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 12:12:09.912371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 12:12:09.919451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 12:12:09.922416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 12:12:09.929468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 12:12:09.932480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 12:12:09.939270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 12:12:09.942400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 12:12:09.949257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 12:12:09.952219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 12:12:09.958565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 12:12:09.962254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 12:12:09.968551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 12:12:09.971686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 12:12:09.978337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 12:12:09.982010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 12:12:09.988512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 12:12:09.991339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 12:12:09.998007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 12:12:10.001845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 12:12:10.007973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 12:12:10.011643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 12:12:10.017780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 12:12:10.021525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 12:12:10.027689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 12:12:10.031291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 12:12:10.037964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 12:12:10.041107 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 12:12:10.044196 INFO: [APUAPC] vio 0
9968 12:12:10.047988 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 12:12:10.054356 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 12:12:10.058191 INFO: [APUAPC] D0_APC_0: 0x400510
9971 12:12:10.058376 INFO: [APUAPC] D0_APC_1: 0x0
9972 12:12:10.061164 INFO: [APUAPC] D0_APC_2: 0x1540
9973 12:12:10.064615 INFO: [APUAPC] D0_APC_3: 0x0
9974 12:12:10.067937 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 12:12:10.070940 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 12:12:10.074126 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 12:12:10.077464 INFO: [APUAPC] D1_APC_3: 0x0
9978 12:12:10.080848 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 12:12:10.083887 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 12:12:10.087598 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 12:12:10.091157 INFO: [APUAPC] D2_APC_3: 0x0
9982 12:12:10.094014 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 12:12:10.097062 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 12:12:10.100644 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 12:12:10.103851 INFO: [APUAPC] D3_APC_3: 0x0
9986 12:12:10.107462 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 12:12:10.110543 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 12:12:10.113656 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 12:12:10.116806 INFO: [APUAPC] D4_APC_3: 0x0
9990 12:12:10.120032 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 12:12:10.123899 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 12:12:10.127154 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 12:12:10.130171 INFO: [APUAPC] D5_APC_3: 0x0
9994 12:12:10.133282 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 12:12:10.137011 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 12:12:10.140037 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 12:12:10.143010 INFO: [APUAPC] D6_APC_3: 0x0
9998 12:12:10.146780 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 12:12:10.149922 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 12:12:10.153010 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 12:12:10.156593 INFO: [APUAPC] D7_APC_3: 0x0
10002 12:12:10.159627 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 12:12:10.162750 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 12:12:10.165813 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 12:12:10.169535 INFO: [APUAPC] D8_APC_3: 0x0
10006 12:12:10.172594 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 12:12:10.176155 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 12:12:10.179399 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 12:12:10.182484 INFO: [APUAPC] D9_APC_3: 0x0
10010 12:12:10.185777 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 12:12:10.189011 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 12:12:10.192568 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 12:12:10.196381 INFO: [APUAPC] D10_APC_3: 0x0
10014 12:12:10.198995 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 12:12:10.202519 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 12:12:10.205404 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 12:12:10.208986 INFO: [APUAPC] D11_APC_3: 0x0
10018 12:12:10.212134 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 12:12:10.215728 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 12:12:10.218772 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 12:12:10.222424 INFO: [APUAPC] D12_APC_3: 0x0
10022 12:12:10.225585 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 12:12:10.228928 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 12:12:10.231914 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 12:12:10.235140 INFO: [APUAPC] D13_APC_3: 0x0
10026 12:12:10.238838 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 12:12:10.241938 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 12:12:10.245144 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 12:12:10.248774 INFO: [APUAPC] D14_APC_3: 0x0
10030 12:12:10.251920 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 12:12:10.255132 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 12:12:10.258722 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 12:12:10.261917 INFO: [APUAPC] D15_APC_3: 0x0
10034 12:12:10.265047 INFO: [APUAPC] APC_CON: 0x4
10035 12:12:10.268493 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 12:12:10.271626 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 12:12:10.274765 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 12:12:10.278443 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 12:12:10.278530 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 12:12:10.281560 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 12:12:10.284801 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 12:12:10.288514 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 12:12:10.291598 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 12:12:10.294755 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 12:12:10.298397 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 12:12:10.301299 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 12:12:10.304883 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 12:12:10.307990 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 12:12:10.311556 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 12:12:10.311641 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 12:12:10.314404 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 12:12:10.317754 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 12:12:10.321299 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 12:12:10.324852 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 12:12:10.327723 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 12:12:10.331597 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 12:12:10.334682 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 12:12:10.337711 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 12:12:10.340815 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 12:12:10.344676 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 12:12:10.347959 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 12:12:10.351168 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 12:12:10.354090 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 12:12:10.357659 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 12:12:10.360748 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 12:12:10.360885 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 12:12:10.363887 INFO: [NOCDAPC] APC_CON: 0x4
10068 12:12:10.367633 INFO: [APUAPC] set_apusys_apc done
10069 12:12:10.370729 INFO: [DEVAPC] devapc_init done
10070 12:12:10.377062 INFO: GICv3 without legacy support detected.
10071 12:12:10.380281 INFO: ARM GICv3 driver initialized in EL3
10072 12:12:10.383969 INFO: Maximum SPI INTID supported: 639
10073 12:12:10.387091 INFO: BL31: Initializing runtime services
10074 12:12:10.393455 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 12:12:10.397326 INFO: SPM: enable CPC mode
10076 12:12:10.400440 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 12:12:10.406945 INFO: BL31: Preparing for EL3 exit to normal world
10078 12:12:10.410050 INFO: Entry point address = 0x80000000
10079 12:12:10.410140 INFO: SPSR = 0x8
10080 12:12:10.417019
10081 12:12:10.417110
10082 12:12:10.417181
10083 12:12:10.420613 Starting depthcharge on Spherion...
10084 12:12:10.420710
10085 12:12:10.420779 Wipe memory regions:
10086 12:12:10.420842
10087 12:12:10.421482 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10088 12:12:10.421589 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10089 12:12:10.421676 Setting prompt string to ['asurada:']
10090 12:12:10.421777 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10091 12:12:10.423658 [0x00000040000000, 0x00000054600000)
10092 12:12:10.546306
10093 12:12:10.546454 [0x00000054660000, 0x00000080000000)
10094 12:12:10.807093
10095 12:12:10.807246 [0x000000821a7280, 0x000000ffe64000)
10096 12:12:11.551473
10097 12:12:11.551645 [0x00000100000000, 0x00000240000000)
10098 12:12:13.441502
10099 12:12:13.444367 Initializing XHCI USB controller at 0x11200000.
10100 12:12:14.483085
10101 12:12:14.486564 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 12:12:14.486651
10103 12:12:14.486718
10104 12:12:14.486782
10105 12:12:14.487104 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 12:12:14.587397 asurada: tftpboot 192.168.201.1 10605382/tftp-deploy-ppbz10u8/kernel/image.itb 10605382/tftp-deploy-ppbz10u8/kernel/cmdline
10108 12:12:14.587552 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10109 12:12:14.587673 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10110 12:12:14.591655 tftpboot 192.168.201.1 10605382/tftp-deploy-ppbz10u8/kernel/image.ittp-deploy-ppbz10u8/kernel/cmdline
10111 12:12:14.591741
10112 12:12:14.591808 Waiting for link
10113 12:12:14.752475
10114 12:12:14.752647 R8152: Initializing
10115 12:12:14.752762
10116 12:12:14.755128 Version 6 (ocp_data = 5c30)
10117 12:12:14.755232
10118 12:12:14.758845 R8152: Done initializing
10119 12:12:14.758922
10120 12:12:14.758987 Adding net device
10121 12:12:16.615440
10122 12:12:16.615597 done.
10123 12:12:16.615671
10124 12:12:16.615782 MAC: 00:24:32:30:78:ff
10125 12:12:16.615886
10126 12:12:16.618529 Sending DHCP discover... done.
10127 12:12:16.618635
10128 12:12:16.622183 Waiting for reply... done.
10129 12:12:16.622276
10130 12:12:16.625450 Sending DHCP request... done.
10131 12:12:16.625529
10132 12:12:16.632724 Waiting for reply... done.
10133 12:12:16.632808
10134 12:12:16.632871 My ip is 192.168.201.21
10135 12:12:16.632930
10136 12:12:16.635662 The DHCP server ip is 192.168.201.1
10137 12:12:16.635737
10138 12:12:16.642568 TFTP server IP predefined by user: 192.168.201.1
10139 12:12:16.642683
10140 12:12:16.649473 Bootfile predefined by user: 10605382/tftp-deploy-ppbz10u8/kernel/image.itb
10141 12:12:16.649552
10142 12:12:16.652272 Sending tftp read request... done.
10143 12:12:16.652391
10144 12:12:16.655724 Waiting for the transfer...
10145 12:12:16.655801
10146 12:12:17.188484 00000000 ################################################################
10147 12:12:17.188665
10148 12:12:17.720595 00080000 ################################################################
10149 12:12:17.720760
10150 12:12:18.255203 00100000 ################################################################
10151 12:12:18.255340
10152 12:12:18.786593 00180000 ################################################################
10153 12:12:18.786764
10154 12:12:19.327796 00200000 ################################################################
10155 12:12:19.327971
10156 12:12:19.859719 00280000 ################################################################
10157 12:12:19.859862
10158 12:12:20.394998 00300000 ################################################################
10159 12:12:20.395167
10160 12:12:20.927015 00380000 ################################################################
10161 12:12:20.927155
10162 12:12:21.463073 00400000 ################################################################
10163 12:12:21.463218
10164 12:12:22.027747 00480000 ################################################################
10165 12:12:22.027913
10166 12:12:22.559218 00500000 ################################################################
10167 12:12:22.559391
10168 12:12:23.095848 00580000 ################################################################
10169 12:12:23.095988
10170 12:12:23.622122 00600000 ################################################################
10171 12:12:23.622309
10172 12:12:24.168122 00680000 ################################################################
10173 12:12:24.168296
10174 12:12:24.734485 00700000 ################################################################
10175 12:12:24.734667
10176 12:12:25.305299 00780000 ################################################################
10177 12:12:25.305488
10178 12:12:25.844457 00800000 ################################################################
10179 12:12:25.844602
10180 12:12:26.389991 00880000 ################################################################
10181 12:12:26.390157
10182 12:12:26.921997 00900000 ################################################################
10183 12:12:26.922163
10184 12:12:27.493737 00980000 ################################################################
10185 12:12:27.493919
10186 12:12:28.029565 00a00000 ################################################################
10187 12:12:28.029742
10188 12:12:28.566306 00a80000 ################################################################
10189 12:12:28.566483
10190 12:12:29.094150 00b00000 ################################################################
10191 12:12:29.094331
10192 12:12:29.621663 00b80000 ################################################################
10193 12:12:29.621809
10194 12:12:30.145963 00c00000 ################################################################
10195 12:12:30.146138
10196 12:12:30.668411 00c80000 ################################################################
10197 12:12:30.668598
10198 12:12:31.229990 00d00000 ################################################################
10199 12:12:31.230145
10200 12:12:31.757066 00d80000 ################################################################
10201 12:12:31.757253
10202 12:12:32.324258 00e00000 ################################################################
10203 12:12:32.324440
10204 12:12:32.858112 00e80000 ################################################################
10205 12:12:32.858283
10206 12:12:33.393490 00f00000 ################################################################
10207 12:12:33.393682
10208 12:12:33.925337 00f80000 ################################################################
10209 12:12:33.925532
10210 12:12:34.455411 01000000 ################################################################
10211 12:12:34.455566
10212 12:12:34.981455 01080000 ################################################################
10213 12:12:34.981637
10214 12:12:35.519887 01100000 ################################################################
10215 12:12:35.520062
10216 12:12:36.053139 01180000 ################################################################
10217 12:12:36.053316
10218 12:12:36.573458 01200000 ################################################################
10219 12:12:36.573597
10220 12:12:37.105115 01280000 ################################################################
10221 12:12:37.105260
10222 12:12:37.625658 01300000 ################################################################
10223 12:12:37.625832
10224 12:12:38.150467 01380000 ################################################################
10225 12:12:38.150638
10226 12:12:38.684689 01400000 ################################################################
10227 12:12:38.684836
10228 12:12:39.218578 01480000 ################################################################
10229 12:12:39.218750
10230 12:12:39.752315 01500000 ################################################################
10231 12:12:39.752485
10232 12:12:40.274439 01580000 ################################################################
10233 12:12:40.274583
10234 12:12:40.814848 01600000 ################################################################
10235 12:12:40.815024
10236 12:12:41.365944 01680000 ################################################################
10237 12:12:41.366120
10238 12:12:41.906990 01700000 ################################################################
10239 12:12:41.907128
10240 12:12:42.465185 01780000 ################################################################
10241 12:12:42.465351
10242 12:12:43.032814 01800000 ################################################################
10243 12:12:43.032969
10244 12:12:43.619640 01880000 ################################################################
10245 12:12:43.619791
10246 12:12:44.159535 01900000 ################################################################
10247 12:12:44.159678
10248 12:12:44.706811 01980000 ################################################################
10249 12:12:44.706955
10250 12:12:45.273434 01a00000 ################################################################ done.
10251 12:12:45.273616
10252 12:12:45.276235 The bootfile was 27787022 bytes long.
10253 12:12:45.276351
10254 12:12:45.279952 Sending tftp read request... done.
10255 12:12:45.280071
10256 12:12:45.280186 Waiting for the transfer...
10257 12:12:45.280278
10258 12:12:45.283084 00000000 # done.
10259 12:12:45.283217
10260 12:12:45.289534 Command line loaded dynamically from TFTP file: 10605382/tftp-deploy-ppbz10u8/kernel/cmdline
10261 12:12:45.289648
10262 12:12:45.309409 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10263 12:12:45.309566
10264 12:12:45.312400 Loading FIT.
10265 12:12:45.312524
10266 12:12:45.316371 Image ramdisk-1 has 17643444 bytes.
10267 12:12:45.316482
10268 12:12:45.316583 Image fdt-1 has 46924 bytes.
10269 12:12:45.316675
10270 12:12:45.319406 Image kernel-1 has 10094623 bytes.
10271 12:12:45.319514
10272 12:12:45.328973 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10273 12:12:45.329094
10274 12:12:45.345601 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10275 12:12:45.345753
10276 12:12:45.352385 Choosing best match conf-1 for compat google,spherion-rev2.
10277 12:12:45.356589
10278 12:12:45.361002 Connected to device vid:did:rid of 1ae0:0028:00
10279 12:12:45.367722
10280 12:12:45.371222 tpm_get_response: command 0x17b, return code 0x0
10281 12:12:45.371346
10282 12:12:45.374381 ec_init: CrosEC protocol v3 supported (256, 248)
10283 12:12:45.378489
10284 12:12:45.382301 tpm_cleanup: add release locality here.
10285 12:12:45.382379
10286 12:12:45.382444 Shutting down all USB controllers.
10287 12:12:45.385432
10288 12:12:45.385517 Removing current net device
10289 12:12:45.385585
10290 12:12:45.391639 Exiting depthcharge with code 4 at timestamp: 64223651
10291 12:12:45.391726
10292 12:12:45.395295 LZMA decompressing kernel-1 to 0x821a6718
10293 12:12:45.395384
10294 12:12:45.398355 LZMA decompressing kernel-1 to 0x40000000
10295 12:12:46.666798
10296 12:12:46.666946 jumping to kernel
10297 12:12:46.667354 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10298 12:12:46.667459 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10299 12:12:46.667539 Setting prompt string to ['Linux version [0-9]']
10300 12:12:46.667610 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10301 12:12:46.667681 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10302 12:12:46.748230
10303 12:12:46.751955 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10304 12:12:46.755063 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10305 12:12:46.755157 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10306 12:12:46.755248 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10307 12:12:46.755324 Using line separator: #'\n'#
10308 12:12:46.755387 No login prompt set.
10309 12:12:46.755453 Parsing kernel messages
10310 12:12:46.755510 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10311 12:12:46.755615 [login-action] Waiting for messages, (timeout 00:03:49)
10312 12:12:46.774468 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10313 12:12:46.778207 [ 0.000000] random: crng init done
10314 12:12:46.784838 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 12:12:46.787782 [ 0.000000] efi: UEFI not found.
10316 12:12:46.794531 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 12:12:46.800862 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 12:12:46.811346 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 12:12:46.821009 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 12:12:46.827381 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 12:12:46.833960 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 12:12:46.840389 [ 0.000000] NUMA: No NUMA configuration found
10323 12:12:46.847732 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 12:12:46.850595 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10325 12:12:46.854222 [ 0.000000] Zone ranges:
10326 12:12:46.860554 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 12:12:46.863577 [ 0.000000] DMA32 empty
10328 12:12:46.870190 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 12:12:46.873309 [ 0.000000] Movable zone start for each node
10330 12:12:46.877147 [ 0.000000] Early memory node ranges
10331 12:12:46.883369 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 12:12:46.889870 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 12:12:46.896595 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 12:12:46.903331 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 12:12:46.910028 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 12:12:46.916129 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 12:12:46.972711 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 12:12:46.979365 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 12:12:46.985508 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 12:12:46.989434 [ 0.000000] psci: probing for conduit method from DT.
10341 12:12:46.995454 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 12:12:46.998802 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 12:12:47.005720 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 12:12:47.008910 [ 0.000000] psci: SMC Calling Convention v1.2
10345 12:12:47.015253 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10346 12:12:47.018753 [ 0.000000] Detected VIPT I-cache on CPU0
10347 12:12:47.024942 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 12:12:47.031846 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 12:12:47.038137 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 12:12:47.045008 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 12:12:47.054776 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 12:12:47.061327 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 12:12:47.064374 [ 0.000000] alternatives: applying boot alternatives
10354 12:12:47.071635 [ 0.000000] Fallback order for Node 0: 0
10355 12:12:47.078064 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 12:12:47.081135 [ 0.000000] Policy zone: Normal
10357 12:12:47.101136 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10358 12:12:47.110938 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 12:12:47.122758 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 12:12:47.132693 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 12:12:47.139579 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 12:12:47.142564 <6>[ 0.000000] software IO TLB: area num 8.
10363 12:12:47.200682 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 12:12:47.350058 <6>[ 0.000000] Memory: 7955716K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397052K reserved, 32768K cma-reserved)
10365 12:12:47.356275 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 12:12:47.363131 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 12:12:47.366287 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 12:12:47.373048 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 12:12:47.379260 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 12:12:47.382948 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 12:12:47.392695 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 12:12:47.399571 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 12:12:47.405843 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 12:12:47.412695 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 12:12:47.415549 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 12:12:47.418968 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 12:12:47.425226 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 12:12:47.428934 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 12:12:47.435201 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 12:12:47.448682 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 12:12:47.461741 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 12:12:47.467986 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 12:12:47.476397 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 12:12:47.489658 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 12:12:47.496276 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 12:12:47.503108 <6>[ 0.009176] Console: colour dummy device 80x25
10387 12:12:47.512445 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 12:12:47.519139 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10389 12:12:47.522674 <6>[ 0.029217] LSM: Security Framework initializing
10390 12:12:47.529279 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 12:12:47.539350 <6>[ 0.041969] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 12:12:47.549087 <6>[ 0.051385] cblist_init_generic: Setting adjustable number of callback queues.
10393 12:12:47.552383 <6>[ 0.058839] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 12:12:47.559055 <6>[ 0.065178] cblist_init_generic: Setting shift to 3 and lim to 1.
10395 12:12:47.565418 <6>[ 0.071625] rcu: Hierarchical SRCU implementation.
10396 12:12:47.571719 <6>[ 0.076639] rcu: Max phase no-delay instances is 1000.
10397 12:12:47.578634 <6>[ 0.083657] EFI services will not be available.
10398 12:12:47.581896 <6>[ 0.088627] smp: Bringing up secondary CPUs ...
10399 12:12:47.589494 <6>[ 0.093710] Detected VIPT I-cache on CPU1
10400 12:12:47.596109 <6>[ 0.093781] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10401 12:12:47.602807 <6>[ 0.093813] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10402 12:12:47.606027 <6>[ 0.094148] Detected VIPT I-cache on CPU2
10403 12:12:47.616108 <6>[ 0.094197] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10404 12:12:47.622638 <6>[ 0.094212] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10405 12:12:47.625986 <6>[ 0.094470] Detected VIPT I-cache on CPU3
10406 12:12:47.632396 <6>[ 0.094516] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10407 12:12:47.639278 <6>[ 0.094530] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10408 12:12:47.645927 <6>[ 0.094835] CPU features: detected: Spectre-v4
10409 12:12:47.648879 <6>[ 0.094842] CPU features: detected: Spectre-BHB
10410 12:12:47.652603 <6>[ 0.094847] Detected PIPT I-cache on CPU4
10411 12:12:47.658832 <6>[ 0.094905] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10412 12:12:47.665806 <6>[ 0.094922] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10413 12:12:47.671951 <6>[ 0.095216] Detected PIPT I-cache on CPU5
10414 12:12:47.678783 <6>[ 0.095278] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10415 12:12:47.685433 <6>[ 0.095294] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10416 12:12:47.688548 <6>[ 0.095578] Detected PIPT I-cache on CPU6
10417 12:12:47.694983 <6>[ 0.095643] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10418 12:12:47.705151 <6>[ 0.095659] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10419 12:12:47.708350 <6>[ 0.095956] Detected PIPT I-cache on CPU7
10420 12:12:47.714937 <6>[ 0.096021] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10421 12:12:47.721429 <6>[ 0.096037] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10422 12:12:47.725047 <6>[ 0.096084] smp: Brought up 1 node, 8 CPUs
10423 12:12:47.731210 <6>[ 0.237374] SMP: Total of 8 processors activated.
10424 12:12:47.734777 <6>[ 0.242296] CPU features: detected: 32-bit EL0 Support
10425 12:12:47.744628 <6>[ 0.247692] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10426 12:12:47.751324 <6>[ 0.256492] CPU features: detected: Common not Private translations
10427 12:12:47.757812 <6>[ 0.262968] CPU features: detected: CRC32 instructions
10428 12:12:47.764225 <6>[ 0.268353] CPU features: detected: RCpc load-acquire (LDAPR)
10429 12:12:47.767693 <6>[ 0.274313] CPU features: detected: LSE atomic instructions
10430 12:12:47.774231 <6>[ 0.280094] CPU features: detected: Privileged Access Never
10431 12:12:47.780377 <6>[ 0.285910] CPU features: detected: RAS Extension Support
10432 12:12:47.787368 <6>[ 0.291518] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10433 12:12:47.790559 <6>[ 0.298739] CPU: All CPU(s) started at EL2
10434 12:12:47.796826 <6>[ 0.303056] alternatives: applying system-wide alternatives
10435 12:12:47.807262 <6>[ 0.313802] devtmpfs: initialized
10436 12:12:47.822639 <6>[ 0.322664] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10437 12:12:47.829181 <6>[ 0.332629] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10438 12:12:47.836051 <6>[ 0.340794] pinctrl core: initialized pinctrl subsystem
10439 12:12:47.839123 <6>[ 0.347457] DMI not present or invalid.
10440 12:12:47.845767 <6>[ 0.351867] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10441 12:12:47.855497 <6>[ 0.358733] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10442 12:12:47.862294 <6>[ 0.366313] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10443 12:12:47.872088 <6>[ 0.374522] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10444 12:12:47.875283 <6>[ 0.382766] audit: initializing netlink subsys (disabled)
10445 12:12:47.885483 <5>[ 0.388461] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10446 12:12:47.892239 <6>[ 0.389164] thermal_sys: Registered thermal governor 'step_wise'
10447 12:12:47.898664 <6>[ 0.396427] thermal_sys: Registered thermal governor 'power_allocator'
10448 12:12:47.901934 <6>[ 0.402681] cpuidle: using governor menu
10449 12:12:47.908781 <6>[ 0.413644] NET: Registered PF_QIPCRTR protocol family
10450 12:12:47.915481 <6>[ 0.419132] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10451 12:12:47.921625 <6>[ 0.426233] ASID allocator initialised with 32768 entries
10452 12:12:47.924560 <6>[ 0.432799] Serial: AMBA PL011 UART driver
10453 12:12:47.934890 <4>[ 0.441497] Trying to register duplicate clock ID: 134
10454 12:12:47.989070 <6>[ 0.498812] KASLR enabled
10455 12:12:48.003401 <6>[ 0.506517] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10456 12:12:48.010257 <6>[ 0.513530] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10457 12:12:48.016468 <6>[ 0.520020] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10458 12:12:48.023095 <6>[ 0.527025] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10459 12:12:48.030007 <6>[ 0.533511] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10460 12:12:48.036613 <6>[ 0.540515] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10461 12:12:48.042995 <6>[ 0.547002] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10462 12:12:48.049326 <6>[ 0.554006] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10463 12:12:48.052558 <6>[ 0.561480] ACPI: Interpreter disabled.
10464 12:12:48.061554 <6>[ 0.567918] iommu: Default domain type: Translated
10465 12:12:48.068256 <6>[ 0.573031] iommu: DMA domain TLB invalidation policy: strict mode
10466 12:12:48.071406 <5>[ 0.579691] SCSI subsystem initialized
10467 12:12:48.077749 <6>[ 0.583927] usbcore: registered new interface driver usbfs
10468 12:12:48.084694 <6>[ 0.589658] usbcore: registered new interface driver hub
10469 12:12:48.087893 <6>[ 0.595210] usbcore: registered new device driver usb
10470 12:12:48.095359 <6>[ 0.601314] pps_core: LinuxPPS API ver. 1 registered
10471 12:12:48.104571 <6>[ 0.606508] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10472 12:12:48.107812 <6>[ 0.615848] PTP clock support registered
10473 12:12:48.110871 <6>[ 0.620087] EDAC MC: Ver: 3.0.0
10474 12:12:48.119120 <6>[ 0.625273] FPGA manager framework
10475 12:12:48.125584 <6>[ 0.628951] Advanced Linux Sound Architecture Driver Initialized.
10476 12:12:48.128596 <6>[ 0.635718] vgaarb: loaded
10477 12:12:48.135386 <6>[ 0.638898] clocksource: Switched to clocksource arch_sys_counter
10478 12:12:48.138484 <5>[ 0.645346] VFS: Disk quotas dquot_6.6.0
10479 12:12:48.145308 <6>[ 0.649533] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10480 12:12:48.148389 <6>[ 0.656727] pnp: PnP ACPI: disabled
10481 12:12:48.157095 <6>[ 0.663392] NET: Registered PF_INET protocol family
10482 12:12:48.166824 <6>[ 0.668975] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10483 12:12:48.178261 <6>[ 0.681291] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10484 12:12:48.188038 <6>[ 0.690107] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10485 12:12:48.194411 <6>[ 0.698075] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10486 12:12:48.204345 <6>[ 0.706774] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10487 12:12:48.211277 <6>[ 0.716522] TCP: Hash tables configured (established 65536 bind 65536)
10488 12:12:48.217832 <6>[ 0.723383] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10489 12:12:48.227422 <6>[ 0.730577] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 12:12:48.234038 <6>[ 0.738281] NET: Registered PF_UNIX/PF_LOCAL protocol family
10491 12:12:48.240552 <6>[ 0.744451] RPC: Registered named UNIX socket transport module.
10492 12:12:48.244228 <6>[ 0.750604] RPC: Registered udp transport module.
10493 12:12:48.250377 <6>[ 0.755538] RPC: Registered tcp transport module.
10494 12:12:48.257022 <6>[ 0.760468] RPC: Registered tcp NFSv4.1 backchannel transport module.
10495 12:12:48.260721 <6>[ 0.767136] PCI: CLS 0 bytes, default 64
10496 12:12:48.263893 <6>[ 0.771522] Unpacking initramfs...
10497 12:12:48.273641 <6>[ 0.775323] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10498 12:12:48.280251 <6>[ 0.783959] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10499 12:12:48.286741 <6>[ 0.792785] kvm [1]: IPA Size Limit: 40 bits
10500 12:12:48.290354 <6>[ 0.797311] kvm [1]: GICv3: no GICV resource entry
10501 12:12:48.296790 <6>[ 0.802334] kvm [1]: disabling GICv2 emulation
10502 12:12:48.299922 <6>[ 0.807018] kvm [1]: GIC system register CPU interface enabled
10503 12:12:48.306749 <6>[ 0.813182] kvm [1]: vgic interrupt IRQ18
10504 12:12:48.309932 <6>[ 0.817546] kvm [1]: VHE mode initialized successfully
10505 12:12:48.317517 <5>[ 0.824017] Initialise system trusted keyrings
10506 12:12:48.324227 <6>[ 0.828831] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10507 12:12:48.332599 <6>[ 0.838831] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10508 12:12:48.338984 <5>[ 0.845211] NFS: Registering the id_resolver key type
10509 12:12:48.342174 <5>[ 0.850512] Key type id_resolver registered
10510 12:12:48.348810 <5>[ 0.854927] Key type id_legacy registered
10511 12:12:48.355401 <6>[ 0.859208] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10512 12:12:48.361798 <6>[ 0.866127] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10513 12:12:48.368577 <6>[ 0.873870] 9p: Installing v9fs 9p2000 file system support
10514 12:12:48.405044 <5>[ 0.911674] Key type asymmetric registered
10515 12:12:48.408609 <5>[ 0.916008] Asymmetric key parser 'x509' registered
10516 12:12:48.417977 <6>[ 0.921154] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10517 12:12:48.421780 <6>[ 0.928766] io scheduler mq-deadline registered
10518 12:12:48.424652 <6>[ 0.933526] io scheduler kyber registered
10519 12:12:48.443897 <6>[ 0.950468] EINJ: ACPI disabled.
10520 12:12:48.475918 <4>[ 0.975783] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10521 12:12:48.485831 <4>[ 0.986419] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 12:12:48.500759 <6>[ 1.007310] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10523 12:12:48.508368 <6>[ 1.015314] printk: console [ttyS0] disabled
10524 12:12:48.536551 <6>[ 1.039955] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10525 12:12:48.543450 <6>[ 1.049429] printk: console [ttyS0] enabled
10526 12:12:48.546444 <6>[ 1.049429] printk: console [ttyS0] enabled
10527 12:12:48.553313 <6>[ 1.058327] printk: bootconsole [mtk8250] disabled
10528 12:12:48.556283 <6>[ 1.058327] printk: bootconsole [mtk8250] disabled
10529 12:12:48.563172 <6>[ 1.069562] SuperH (H)SCI(F) driver initialized
10530 12:12:48.566271 <6>[ 1.074825] msm_serial: driver initialized
10531 12:12:48.580826 <6>[ 1.083718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10532 12:12:48.590511 <6>[ 1.092266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10533 12:12:48.597285 <6>[ 1.100812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10534 12:12:48.606933 <6>[ 1.109444] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10535 12:12:48.616905 <6>[ 1.118157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10536 12:12:48.623678 <6>[ 1.126879] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10537 12:12:48.633116 <6>[ 1.135421] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10538 12:12:48.640181 <6>[ 1.144238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10539 12:12:48.650026 <6>[ 1.152781] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10540 12:12:48.661673 <6>[ 1.168265] loop: module loaded
10541 12:12:48.668726 <6>[ 1.174338] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10542 12:12:48.690938 <4>[ 1.197702] mtk-pmic-keys: Failed to locate of_node [id: -1]
10543 12:12:48.697827 <6>[ 1.204527] megasas: 07.719.03.00-rc1
10544 12:12:48.707369 <6>[ 1.214100] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10545 12:12:48.719982 <6>[ 1.226280] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10546 12:12:48.736596 <6>[ 1.242911] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10547 12:12:48.796831 <6>[ 1.296845] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10548 12:12:48.998002 <6>[ 1.504265] Freeing initrd memory: 17224K
10549 12:12:49.008239 <6>[ 1.514507] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10550 12:12:49.018791 <6>[ 1.525404] tun: Universal TUN/TAP device driver, 1.6
10551 12:12:49.022605 <6>[ 1.531448] thunder_xcv, ver 1.0
10552 12:12:49.025610 <6>[ 1.534948] thunder_bgx, ver 1.0
10553 12:12:49.028714 <6>[ 1.538437] nicpf, ver 1.0
10554 12:12:49.039061 <6>[ 1.542429] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10555 12:12:49.042523 <6>[ 1.549904] hns3: Copyright (c) 2017 Huawei Corporation.
10556 12:12:49.049394 <6>[ 1.555490] hclge is initializing
10557 12:12:49.052537 <6>[ 1.559070] e1000: Intel(R) PRO/1000 Network Driver
10558 12:12:49.059417 <6>[ 1.564199] e1000: Copyright (c) 1999-2006 Intel Corporation.
10559 12:12:49.062423 <6>[ 1.570212] e1000e: Intel(R) PRO/1000 Network Driver
10560 12:12:49.068997 <6>[ 1.575428] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10561 12:12:49.075593 <6>[ 1.581616] igb: Intel(R) Gigabit Ethernet Network Driver
10562 12:12:49.082467 <6>[ 1.587267] igb: Copyright (c) 2007-2014 Intel Corporation.
10563 12:12:49.089063 <6>[ 1.593102] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10564 12:12:49.095932 <6>[ 1.599621] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10565 12:12:49.099176 <6>[ 1.606083] sky2: driver version 1.30
10566 12:12:49.105408 <6>[ 1.611071] VFIO - User Level meta-driver version: 0.3
10567 12:12:49.112498 <6>[ 1.619276] usbcore: registered new interface driver usb-storage
10568 12:12:49.119706 <6>[ 1.625719] usbcore: registered new device driver onboard-usb-hub
10569 12:12:49.128432 <6>[ 1.634798] mt6397-rtc mt6359-rtc: registered as rtc0
10570 12:12:49.138350 <6>[ 1.640264] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:12:54 UTC (1686053574)
10571 12:12:49.141315 <6>[ 1.649822] i2c_dev: i2c /dev entries driver
10572 12:12:49.158437 <6>[ 1.661474] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10573 12:12:49.165079 <6>[ 1.671691] sdhci: Secure Digital Host Controller Interface driver
10574 12:12:49.171931 <6>[ 1.678129] sdhci: Copyright(c) Pierre Ossman
10575 12:12:49.178383 <6>[ 1.683532] Synopsys Designware Multimedia Card Interface Driver
10576 12:12:49.181600 <6>[ 1.690108] mmc0: CQHCI version 5.10
10577 12:12:49.188364 <6>[ 1.690689] sdhci-pltfm: SDHCI platform and OF driver helper
10578 12:12:49.195309 <6>[ 1.701976] ledtrig-cpu: registered to indicate activity on CPUs
10579 12:12:49.206232 <6>[ 1.709313] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10580 12:12:49.209232 <6>[ 1.716700] usbcore: registered new interface driver usbhid
10581 12:12:49.216069 <6>[ 1.722531] usbhid: USB HID core driver
10582 12:12:49.222534 <6>[ 1.726770] spi_master spi0: will run message pump with realtime priority
10583 12:12:49.268536 <6>[ 1.768072] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10584 12:12:49.286754 <6>[ 1.783107] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10585 12:12:49.289746 <6>[ 1.796663] mmc0: Command Queue Engine enabled
10586 12:12:49.296447 <6>[ 1.801460] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10587 12:12:49.303399 <6>[ 1.808606] cros-ec-spi spi0.0: Chrome EC device registered
10588 12:12:49.306534 <6>[ 1.808830] mmcblk0: mmc0:0001 DA4128 116 GiB
10589 12:12:49.321018 <6>[ 1.827790] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10590 12:12:49.328386 <6>[ 1.835102] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10591 12:12:49.335279 <6>[ 1.841096] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10592 12:12:49.341467 <6>[ 1.847269] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10593 12:12:49.351327 <6>[ 1.849178] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10594 12:12:49.358562 <6>[ 1.865209] NET: Registered PF_PACKET protocol family
10595 12:12:49.365472 <6>[ 1.870654] 9pnet: Installing 9P2000 support
10596 12:12:49.368431 <5>[ 1.875255] Key type dns_resolver registered
10597 12:12:49.371911 <6>[ 1.880407] registered taskstats version 1
10598 12:12:49.378618 <5>[ 1.884838] Loading compiled-in X.509 certificates
10599 12:12:49.414453 <4>[ 1.914069] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10600 12:12:49.424280 <4>[ 1.924763] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 12:12:49.434209 <3>[ 1.937410] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10602 12:12:49.446431 <6>[ 1.952970] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10603 12:12:49.453372 <6>[ 1.959733] xhci-mtk 11200000.usb: xHCI Host Controller
10604 12:12:49.460087 <6>[ 1.965232] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10605 12:12:49.469768 <6>[ 1.973096] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10606 12:12:49.476495 <6>[ 1.982528] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10607 12:12:49.482825 <6>[ 1.988616] xhci-mtk 11200000.usb: xHCI Host Controller
10608 12:12:49.489571 <6>[ 1.994191] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10609 12:12:49.496546 <6>[ 2.001873] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10610 12:12:49.502790 <6>[ 2.009752] hub 1-0:1.0: USB hub found
10611 12:12:49.506462 <6>[ 2.013784] hub 1-0:1.0: 1 port detected
10612 12:12:49.515827 <6>[ 2.018132] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10613 12:12:49.519758 <6>[ 2.026927] hub 2-0:1.0: USB hub found
10614 12:12:49.522722 <6>[ 2.030957] hub 2-0:1.0: 1 port detected
10615 12:12:49.531994 <6>[ 2.038125] mtk-msdc 11f70000.mmc: Got CD GPIO
10616 12:12:49.548892 <6>[ 2.051928] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10617 12:12:49.555235 <6>[ 2.060052] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10618 12:12:49.565474 <4>[ 2.068046] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10619 12:12:49.575198 <6>[ 2.077733] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10620 12:12:49.581977 <6>[ 2.085823] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10621 12:12:49.592296 <6>[ 2.093895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10622 12:12:49.598480 <6>[ 2.101821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10623 12:12:49.605315 <6>[ 2.109679] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10624 12:12:49.615001 <6>[ 2.117502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10625 12:12:49.625362 <6>[ 2.128265] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10626 12:12:49.635005 <6>[ 2.136628] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10627 12:12:49.641899 <6>[ 2.145018] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10628 12:12:49.651738 <6>[ 2.153365] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10629 12:12:49.657884 <6>[ 2.161734] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10630 12:12:49.667912 <6>[ 2.170081] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10631 12:12:49.674632 <6>[ 2.178449] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10632 12:12:49.684502 <6>[ 2.186794] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10633 12:12:49.691399 <6>[ 2.195158] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10634 12:12:49.701230 <6>[ 2.203506] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10635 12:12:49.707805 <6>[ 2.211850] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10636 12:12:49.717580 <6>[ 2.220193] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10637 12:12:49.724458 <6>[ 2.228537] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10638 12:12:49.733777 <6>[ 2.236880] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10639 12:12:49.740828 <6>[ 2.245224] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10640 12:12:49.747594 <6>[ 2.254122] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10641 12:12:49.755103 <6>[ 2.261551] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10642 12:12:49.762311 <6>[ 2.268554] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10643 12:12:49.772120 <6>[ 2.275640] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10644 12:12:49.778786 <6>[ 2.282917] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10645 12:12:49.789100 <6>[ 2.289813] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10646 12:12:49.795383 <6>[ 2.298952] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10647 12:12:49.805698 <6>[ 2.308127] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10648 12:12:49.815290 <6>[ 2.317548] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10649 12:12:49.825381 <6>[ 2.327026] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10650 12:12:49.834721 <6>[ 2.336501] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10651 12:12:49.844716 <6>[ 2.345628] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10652 12:12:49.851757 <6>[ 2.355103] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10653 12:12:49.861467 <6>[ 2.364231] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10654 12:12:49.871360 <6>[ 2.373532] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10655 12:12:49.881095 <6>[ 2.383718] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10656 12:12:49.891957 <6>[ 2.395562] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10657 12:12:49.898792 <6>[ 2.405382] Trying to probe devices needed for running init ...
10658 12:12:49.939893 <6>[ 2.443180] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10659 12:12:50.093966 <6>[ 2.600545] hub 1-1:1.0: USB hub found
10660 12:12:50.097118 <6>[ 2.604998] hub 1-1:1.0: 4 ports detected
10661 12:12:50.220413 <6>[ 2.723367] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10662 12:12:50.245666 <6>[ 2.751564] hub 2-1:1.0: USB hub found
10663 12:12:50.248786 <6>[ 2.755958] hub 2-1:1.0: 3 ports detected
10664 12:12:50.419732 <6>[ 2.923171] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10665 12:12:50.552808 <6>[ 3.059392] hub 1-1.4:1.0: USB hub found
10666 12:12:50.556072 <6>[ 3.064064] hub 1-1.4:1.0: 2 ports detected
10667 12:12:50.631866 <6>[ 3.135415] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10668 12:12:50.851482 <6>[ 3.355169] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10669 12:12:51.043727 <6>[ 3.547171] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10670 12:13:02.188581 <6>[ 14.699740] ALSA device list:
10671 12:13:02.194837 <6>[ 14.702999] No soundcards found.
10672 12:13:02.207229 <6>[ 14.715388] Freeing unused kernel memory: 8384K
10673 12:13:02.210808 <6>[ 14.720304] Run /init as init process
10674 12:13:02.220905 Loading, please wait...
10675 12:13:02.240104 Starting version 247.3-7+deb11u2
10676 12:13:02.557078 <6>[ 15.062021] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10677 12:13:02.566084 <6>[ 15.074100] remoteproc remoteproc0: scp is available
10678 12:13:02.575716 <4>[ 15.080188] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10679 12:13:02.582824 <6>[ 15.090191] remoteproc remoteproc0: powering up scp
10680 12:13:02.592577 <4>[ 15.095369] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10681 12:13:02.598810 <3>[ 15.105202] remoteproc remoteproc0: request_firmware failed: -2
10682 12:13:02.612143 <6>[ 15.116666] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10683 12:13:02.618561 <6>[ 15.124355] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10684 12:13:02.628660 <6>[ 15.133069] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10685 12:13:02.638745 <3>[ 15.142499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 12:13:02.645112 <3>[ 15.150623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:13:02.654851 <3>[ 15.158712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 12:13:02.665878 <3>[ 15.170362] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:13:02.672228 <4>[ 15.173009] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10690 12:13:02.682135 <3>[ 15.178571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 12:13:02.685198 <6>[ 15.179405] mc: Linux media interface: v0.10
10692 12:13:02.691971 <4>[ 15.193778] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10693 12:13:02.701861 <3>[ 15.193947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 12:13:02.708623 <3>[ 15.213973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 12:13:02.715213 <6>[ 15.221812] usbcore: registered new interface driver r8152
10696 12:13:02.722036 <3>[ 15.222190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 12:13:02.731708 <6>[ 15.225991] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10698 12:13:02.738283 <3>[ 15.243731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 12:13:02.744697 <6>[ 15.244743] videodev: Linux video capture interface: v2.00
10700 12:13:02.751167 <3>[ 15.251971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 12:13:02.761009 <4>[ 15.265124] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10702 12:13:02.767765 <4>[ 15.265124] Fallback method does not support PEC.
10703 12:13:02.774653 <6>[ 15.265239] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10704 12:13:02.777751 <6>[ 15.265247] pci_bus 0000:00: root bus resource [bus 00-ff]
10705 12:13:02.784877 <6>[ 15.265253] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10706 12:13:02.794932 <6>[ 15.265258] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10707 12:13:02.801359 <6>[ 15.265290] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10708 12:13:02.808352 <6>[ 15.265310] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10709 12:13:02.815291 <6>[ 15.265393] pci 0000:00:00.0: supports D1 D2
10710 12:13:02.821654 <6>[ 15.265397] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 12:13:02.828187 <3>[ 15.266005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 12:13:02.838324 <6>[ 15.267070] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10713 12:13:02.844710 <6>[ 15.267192] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10714 12:13:02.851460 <6>[ 15.267224] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10715 12:13:02.858034 <6>[ 15.267245] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10716 12:13:02.867668 <6>[ 15.267264] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10717 12:13:02.870989 <6>[ 15.267384] pci 0000:01:00.0: supports D1 D2
10718 12:13:02.877565 <6>[ 15.267388] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 12:13:02.884278 <6>[ 15.282977] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10720 12:13:02.894023 <3>[ 15.286178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 12:13:02.900686 <6>[ 15.291943] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10722 12:13:02.910762 <3>[ 15.296181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 12:13:02.917538 <3>[ 15.299097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 12:13:02.926825 <6>[ 15.308941] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10725 12:13:02.933281 <6>[ 15.310045] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10726 12:13:02.943112 <6>[ 15.311140] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10727 12:13:02.949725 <3>[ 15.315196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 12:13:02.959743 <3>[ 15.319136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 12:13:02.966300 <6>[ 15.322678] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10730 12:13:02.976279 <3>[ 15.327190] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 12:13:02.982963 <3>[ 15.327199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 12:13:02.990075 <6>[ 15.334223] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10733 12:13:02.999413 <6>[ 15.339451] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10734 12:13:03.009487 <6>[ 15.339791] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10735 12:13:03.019532 <3>[ 15.342202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 12:13:03.025728 <6>[ 15.350512] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10737 12:13:03.032612 <6>[ 15.350992] usbcore: registered new interface driver cdc_ether
10738 12:13:03.039388 <3>[ 15.357791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:13:03.045652 <6>[ 15.358426] usbcore: registered new interface driver r8153_ecm
10740 12:13:03.052271 <6>[ 15.364395] pci 0000:00:00.0: PCI bridge to [bus 01]
10741 12:13:03.055475 <6>[ 15.380086] Bluetooth: Core ver 2.22
10742 12:13:03.062390 <6>[ 15.383839] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10743 12:13:03.068954 <6>[ 15.390773] NET: Registered PF_BLUETOOTH protocol family
10744 12:13:03.075604 <6>[ 15.398222] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10745 12:13:03.082622 <6>[ 15.398233] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10746 12:13:03.091829 <4>[ 15.399124] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10747 12:13:03.098764 <4>[ 15.399138] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10748 12:13:03.105067 <6>[ 15.399285] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10749 12:13:03.111444 <6>[ 15.399869] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10750 12:13:03.118260 <6>[ 15.405708] Bluetooth: HCI device and connection manager initialized
10751 12:13:03.125381 <6>[ 15.405757] Bluetooth: HCI socket layer initialized
10752 12:13:03.134885 <6>[ 15.415010] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10753 12:13:03.141556 <6>[ 15.422723] Bluetooth: L2CAP socket layer initialized
10754 12:13:03.148223 <5>[ 15.425308] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10755 12:13:03.154663 <6>[ 15.431125] usbcore: registered new interface driver uvcvideo
10756 12:13:03.161582 <5>[ 15.436183] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10757 12:13:03.171080 <4>[ 15.436261] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10758 12:13:03.174624 <6>[ 15.436270] cfg80211: failed to load regulatory.db
10759 12:13:03.181584 <6>[ 15.438786] Bluetooth: SCO socket layer initialized
10760 12:13:03.187645 <6>[ 15.440070] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10761 12:13:03.194619 <6>[ 15.541094] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10762 12:13:03.197614 <6>[ 15.576757] r8152 2-1.3:1.0 eth0: v1.12.13
10763 12:13:03.204381 <6>[ 15.582467] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10764 12:13:03.211144 <6>[ 15.597976] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10765 12:13:03.217767 <6>[ 15.605657] usbcore: registered new interface driver btusb
10766 12:13:03.227339 <4>[ 15.606115] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10767 12:13:03.233951 <3>[ 15.606126] Bluetooth: hci0: Failed to load firmware file (-2)
10768 12:13:03.240641 <3>[ 15.606129] Bluetooth: hci0: Failed to set up firmware (-2)
10769 12:13:03.250509 <4>[ 15.606133] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10770 12:13:03.256749 <6>[ 15.623075] mt7921e 0000:01:00.0: ASIC revision: 79610010
10771 12:13:03.361178 <4>[ 15.862776] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 12:13:03.374788 Begin: Loading essential drivers ... done.
10773 12:13:03.378071 Begin: Running /scripts/init-premount ... done.
10774 12:13:03.384444 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10775 12:13:03.394617 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10776 12:13:03.397495 Device /sys/class/net/enx0024323078ff found
10777 12:13:03.397578 done.
10778 12:13:03.429849 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10779 12:13:03.479936 <4>[ 15.981316] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:13:03.599258 <4>[ 16.100822] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 12:13:03.714735 <4>[ 16.216675] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 12:13:03.831235 <4>[ 16.332581] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 12:13:03.946832 <4>[ 16.448725] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 12:13:04.062708 <4>[ 16.564635] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 12:13:04.178769 <4>[ 16.680546] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 12:13:04.294757 <4>[ 16.796556] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 12:13:04.410427 <4>[ 16.912496] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 12:13:04.517796 <3>[ 17.026289] mt7921e 0000:01:00.0: hardware init failed
10789 12:13:04.607844 <6>[ 17.116327] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10790 12:13:04.631693 IP-Config: no response after 2 secs - giving up
10791 12:13:04.674073 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10792 12:13:05.910019 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10793 12:13:05.916674 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10794 12:13:05.926005 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10795 12:13:05.932988 host : mt8192-asurada-spherion-r0-cbg-8
10796 12:13:05.939532 domain : lava-rack
10797 12:13:05.942617 rootserver: 192.168.201.1 rootpath:
10798 12:13:05.942704 filename :
10799 12:13:05.970315 done.
10800 12:13:05.978841 Begin: Running /scripts/nfs-bottom ... done.
10801 12:13:05.996386 Begin: Running /scripts/init-bottom ... done.
10802 12:13:07.146422 <6>[ 19.655053] NET: Registered PF_INET6 protocol family
10803 12:13:07.153177 <6>[ 19.661957] Segment Routing with IPv6
10804 12:13:07.156898 <6>[ 19.665951] In-situ OAM (IOAM) with IPv6
10805 12:13:07.278532 <30>[ 19.767090] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10806 12:13:07.281534 <30>[ 19.790922] systemd[1]: Detected architecture arm64.
10807 12:13:07.302452
10808 12:13:07.305882 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10809 12:13:07.305963
10810 12:13:07.321340 <30>[ 19.829718] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10811 12:13:07.927131 <30>[ 20.432492] systemd[1]: Queued start job for default target Graphical Interface.
10812 12:13:07.943905 <30>[ 20.452255] systemd[1]: Created slice system-getty.slice.
10813 12:13:07.950362 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10814 12:13:07.967144 <30>[ 20.475919] systemd[1]: Created slice system-modprobe.slice.
10815 12:13:07.973954 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10816 12:13:07.991054 <30>[ 20.499818] systemd[1]: Created slice system-serial\x2dgetty.slice.
10817 12:13:08.001158 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10818 12:13:08.015303 <30>[ 20.523681] systemd[1]: Created slice User and Session Slice.
10819 12:13:08.021387 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10820 12:13:08.042535 <30>[ 20.547716] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10821 12:13:08.052376 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10822 12:13:08.069889 <30>[ 20.575316] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10823 12:13:08.076634 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10824 12:13:08.097470 <30>[ 20.599286] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10825 12:13:08.103725 <30>[ 20.611308] systemd[1]: Reached target Local Encrypted Volumes.
10826 12:13:08.109974 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10827 12:13:08.126982 <30>[ 20.635548] systemd[1]: Reached target Paths.
10828 12:13:08.130068 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10829 12:13:08.146575 <30>[ 20.655209] systemd[1]: Reached target Remote File Systems.
10830 12:13:08.153277 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10831 12:13:08.166461 <30>[ 20.675135] systemd[1]: Reached target Slices.
10832 12:13:08.169955 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10833 12:13:08.186635 <30>[ 20.695225] systemd[1]: Reached target Swap.
10834 12:13:08.189801 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10835 12:13:08.210178 <30>[ 20.715543] systemd[1]: Listening on initctl Compatibility Named Pipe.
10836 12:13:08.217098 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10837 12:13:08.223018 <30>[ 20.731013] systemd[1]: Listening on Journal Audit Socket.
10838 12:13:08.229741 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10839 12:13:08.243217 <30>[ 20.752216] systemd[1]: Listening on Journal Socket (/dev/log).
10840 12:13:08.249825 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10841 12:13:08.267444 <30>[ 20.775977] systemd[1]: Listening on Journal Socket.
10842 12:13:08.273803 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10843 12:13:08.291482 <30>[ 20.796557] systemd[1]: Listening on Network Service Netlink Socket.
10844 12:13:08.297723 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10845 12:13:08.313200 <30>[ 20.822073] systemd[1]: Listening on udev Control Socket.
10846 12:13:08.320163 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10847 12:13:08.334698 <30>[ 20.843473] systemd[1]: Listening on udev Kernel Socket.
10848 12:13:08.341290 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10849 12:13:08.374972 <30>[ 20.883500] systemd[1]: Mounting Huge Pages File System...
10850 12:13:08.381524 Mounting [0;1;39mHuge Pages File System[0m...
10851 12:13:08.397276 <30>[ 20.905679] systemd[1]: Mounting POSIX Message Queue File System...
10852 12:13:08.404190 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10853 12:13:08.420785 <30>[ 20.929593] systemd[1]: Mounting Kernel Debug File System...
10854 12:13:08.427394 Mounting [0;1;39mKernel Debug File System[0m...
10855 12:13:08.445996 <30>[ 20.951385] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10856 12:13:08.468685 <30>[ 20.974543] systemd[1]: Starting Create list of static device nodes for the current kernel...
10857 12:13:08.479011 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10858 12:13:08.493294 <30>[ 21.001985] systemd[1]: Starting Load Kernel Module configfs...
10859 12:13:08.499753 Starting [0;1;39mLoad Kernel Module configfs[0m...
10860 12:13:08.517311 <30>[ 21.025843] systemd[1]: Starting Load Kernel Module drm...
10861 12:13:08.523447 Starting [0;1;39mLoad Kernel Module drm[0m...
10862 12:13:08.541049 <30>[ 21.049662] systemd[1]: Starting Load Kernel Module fuse...
10863 12:13:08.547396 Starting [0;1;39mLoad Kernel Module fuse[0m...
10864 12:13:08.581285 <6>[ 21.090195] fuse: init (API version 7.37)
10865 12:13:08.591427 <30>[ 21.091582] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10866 12:13:08.627202 <30>[ 21.135862] systemd[1]: Starting Journal Service...
10867 12:13:08.630397 Starting [0;1;39mJournal Service[0m...
10868 12:13:08.655103 <30>[ 21.163840] systemd[1]: Starting Load Kernel Modules...
10869 12:13:08.661458 Starting [0;1;39mLoad Kernel Modules[0m...
10870 12:13:08.680692 <30>[ 21.186000] systemd[1]: Starting Remount Root and Kernel File Systems...
10871 12:13:08.687427 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10872 12:13:08.702373 <30>[ 21.210974] systemd[1]: Starting Coldplug All udev Devices...
10873 12:13:08.708717 Starting [0;1;39mColdplug All udev Devices[0m...
10874 12:13:08.725865 <30>[ 21.234379] systemd[1]: Mounted Huge Pages File System.
10875 12:13:08.732119 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10876 12:13:08.746943 <30>[ 21.255783] systemd[1]: Mounted POSIX Message Queue File System.
10877 12:13:08.753507 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10878 12:13:08.771260 <30>[ 21.279559] systemd[1]: Mounted Kernel Debug File System.
10879 12:13:08.777368 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10880 12:13:08.795909 <3>[ 21.301738] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 12:13:08.806338 <30>[ 21.311987] systemd[1]: Finished Create list of static device nodes for the current kernel.
10882 12:13:08.816922 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10883 12:13:08.826754 <3>[ 21.332369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 12:13:08.833752 <30>[ 21.342279] systemd[1]: modprobe@configfs.service: Succeeded.
10885 12:13:08.840546 <30>[ 21.349079] systemd[1]: Finished Load Kernel Module configfs.
10886 12:13:08.847348 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10887 12:13:08.863425 <30>[ 21.372267] systemd[1]: modprobe@drm.service: Succeeded.
10888 12:13:08.873513 <3>[ 21.376589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:13:08.880257 <30>[ 21.378753] systemd[1]: Finished Load Kernel Module drm.
10890 12:13:08.883184 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10891 12:13:08.899407 <30>[ 21.408049] systemd[1]: modprobe@fuse.service: Succeeded.
10892 12:13:08.909539 <3>[ 21.408313] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:13:08.915707 <30>[ 21.414367] systemd[1]: Finished Load Kernel Module fuse.
10894 12:13:08.922203 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10895 12:13:08.935702 <30>[ 21.444310] systemd[1]: Finished Load Kernel Modules.
10896 12:13:08.945504 <3>[ 21.448801] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:13:08.952111 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10898 12:13:08.968485 <30>[ 21.476743] systemd[1]: Finished Remount Root and Kernel File Systems.
10899 12:13:08.978382 <3>[ 21.482909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 12:13:08.985186 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10901 12:13:09.014547 <3>[ 21.519735] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 12:13:09.035039 <30>[ 21.543574] systemd[1]: Mounting FUSE Control File System...
10903 12:13:09.045386 Mountin<3>[ 21.550035] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 12:13:09.048385 g [0;1;39mFUSE Control File System[0m...
10905 12:13:09.064960 <30>[ 21.573740] systemd[1]: Mounting Kernel Configuration File System...
10906 12:13:09.078381 Mountin<3>[ 21.581259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 12:13:09.081560 g [0;1;39mKernel Configuration File System[0m...
10908 12:13:09.107293 <3>[ 21.612782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 12:13:09.116851 <30>[ 21.614858] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10910 12:13:09.127041 <30>[ 21.631529] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10911 12:13:09.170922 <30>[ 21.679610] systemd[1]: Starting Load/Save Random Seed...
10912 12:13:09.177526 Starting [0;1;39mLoad/Save Random Seed[0m...
10913 12:13:09.193058 <30>[ 21.701802] systemd[1]: Starting Apply Kernel Variables...
10914 12:13:09.199742 Starting [0;1;39mApply Kernel Variables[0m...
10915 12:13:09.218144 <30>[ 21.726811] systemd[1]: Starting Create System Users...
10916 12:13:09.238368 Starting [0;1;39mCreate System Users[<4>[ 21.736422] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10917 12:13:09.238514 0m...
10918 12:13:09.248133 <3>[ 21.752649] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10919 12:13:09.254930 <30>[ 21.763205] systemd[1]: Started Journal Service.
10920 12:13:09.261142 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10921 12:13:09.280665 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10922 12:13:09.294456 See 'systemctl status systemd-udev-trigger.service' for details.
10923 12:13:09.311184 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10924 12:13:09.327040 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10925 12:13:09.343190 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10926 12:13:09.359309 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10927 12:13:09.375286 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10928 12:13:09.427294 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10929 12:13:09.444756 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10930 12:13:09.496400 <46>[ 22.002105] systemd-journald[289]: Received client request to flush runtime journal.
10931 12:13:10.156812 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10932 12:13:10.170621 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10933 12:13:10.186417 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10934 12:13:10.242751 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10935 12:13:10.889966 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10936 12:13:10.926720 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10937 12:13:11.003593 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10938 12:13:11.063906 Starting [0;1;39mNetwork Service[0m...
10939 12:13:11.344320 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10940 12:13:11.367107 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10941 12:13:11.434515 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10942 12:13:11.602461 <6>[ 24.111208] remoteproc remoteproc0: powering up scp
10943 12:13:11.636113 <4>[ 24.141859] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10944 12:13:11.642460 <3>[ 24.151812] remoteproc remoteproc0: request_firmware failed: -2
10945 12:13:11.652479 <3>[ 24.157992] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10946 12:13:11.796915 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10947 12:13:11.810602 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10948 12:13:11.830152 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10949 12:13:11.842357 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10950 12:13:11.890475 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10951 12:13:11.954780 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10952 12:13:12.003307 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10953 12:13:12.046359 Starting [0;1;39mNetwork Name Resolution[0m...
10954 12:13:12.074716 Starting [0;1;39mNetwork Time Synchronization[0m...
10955 12:13:12.097173 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10956 12:13:12.139584 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10957 12:13:12.317616 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10958 12:13:12.334544 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10959 12:13:12.353400 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10960 12:13:12.366286 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10961 12:13:12.382266 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10962 12:13:12.518647 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10963 12:13:12.562234 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10964 12:13:12.587521 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10965 12:13:12.618192 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10966 12:13:12.630118 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10967 12:13:12.667906 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10968 12:13:12.682147 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10969 12:13:12.698250 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10970 12:13:12.742922 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10971 12:13:12.775980 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10972 12:13:12.834982 Starting [0;1;39mUser Login Management[0m...
10973 12:13:12.851123 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10974 12:13:12.866853 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10975 12:13:12.885471 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10976 12:13:12.918360 Starting [0;1;39mPermit User Sessions[0m...
10977 12:13:13.060321 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10978 12:13:13.106536 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10979 12:13:13.124854 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10980 12:13:13.142676 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10981 12:13:13.163344 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10982 12:13:13.179754 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10983 12:13:13.195119 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10984 12:13:13.210133 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10985 12:13:13.242179 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10986 12:13:13.320779 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10987 12:13:13.381775
10988 12:13:13.381915
10989 12:13:13.384767 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10990 12:13:13.384854
10991 12:13:13.387965 debian-bullseye-arm64 login: root (automatic login)
10992 12:13:13.388054
10993 12:13:13.388121
10994 12:13:13.709354 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
10995 12:13:13.709577
10996 12:13:13.715478 The programs included with the Debian GNU/Linux system are free software;
10997 12:13:13.722421 the exact distribution terms for each program are described in the
10998 12:13:13.725348 individual files in /usr/share/doc/*/copyright.
10999 12:13:13.725447
11000 12:13:13.732404 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11001 12:13:13.735233 permitted by applicable law.
11002 12:13:14.570209 Matched prompt #10: / #
11004 12:13:14.570610 Setting prompt string to ['/ #']
11005 12:13:14.570739 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11007 12:13:14.571070 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11008 12:13:14.571193 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11009 12:13:14.571278 Setting prompt string to ['/ #']
11010 12:13:14.571342 Forcing a shell prompt, looking for ['/ #']
11012 12:13:14.621543 / #
11013 12:13:14.621712 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11014 12:13:14.621818 Waiting using forced prompt support (timeout 00:02:30)
11015 12:13:14.627195
11016 12:13:14.627488 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11017 12:13:14.627587 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11019 12:13:14.727962 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9'
11020 12:13:14.732968 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605382/extract-nfsrootfs-q2cnzsx9'
11022 12:13:14.833653 / # export NFS_SERVER_IP='192.168.201.1'
11023 12:13:14.838796 export NFS_SERVER_IP='192.168.201.1'
11024 12:13:14.839156 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11025 12:13:14.839262 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11026 12:13:14.839355 end: 2 depthcharge-action (duration 00:01:39) [common]
11027 12:13:14.839444 start: 3 lava-test-retry (timeout 00:07:25) [common]
11028 12:13:14.839531 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11029 12:13:14.839606 Using namespace: common
11031 12:13:14.939917 / # #
11032 12:13:14.940134 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11033 12:13:14.944731 #
11034 12:13:14.945041 Using /lava-10605382
11036 12:13:15.045394 / # export SHELL=/bin/bash
11037 12:13:15.050268 export SHELL=/bin/bash
11039 12:13:15.150891 / # . /lava-10605382/environment
11040 12:13:15.156266 . /lava-10605382/environment
11042 12:13:15.262162 / # /lava-10605382/bin/lava-test-runner /lava-10605382/0
11043 12:13:15.262313 Test shell timeout: 10s (minimum of the action and connection timeout)
11044 12:13:15.267447 /lava-10605382/bin/lava-test-runner /lava-10605382/0
11045 12:13:15.542682 + export TESTRUN_ID=0_timesync-off
11046 12:13:15.545761 + TESTRUN_ID=0_timesync-off
11047 12:13:15.549518 + cd /lava-10605382/0/tests/0_timesync-off
11048 12:13:15.552609 ++ cat uuid
11049 12:13:15.561516 + UUID=10605382_1.6.2.3.1
11050 12:13:15.561647 + set +x
11051 12:13:15.568177 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10605382_1.6.2.3.1>
11052 12:13:15.568469 Received signal: <STARTRUN> 0_timesync-off 10605382_1.6.2.3.1
11053 12:13:15.568550 Starting test lava.0_timesync-off (10605382_1.6.2.3.1)
11054 12:13:15.568644 Skipping test definition patterns.
11055 12:13:15.571274 + systemctl stop systemd-timesyncd
11056 12:13:15.611661 + set +x
11057 12:13:15.615233 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10605382_1.6.2.3.1>
11058 12:13:15.615513 Received signal: <ENDRUN> 0_timesync-off 10605382_1.6.2.3.1
11059 12:13:15.615605 Ending use of test pattern.
11060 12:13:15.615668 Ending test lava.0_timesync-off (10605382_1.6.2.3.1), duration 0.05
11062 12:13:15.702250 + export TESTRUN_ID=1_kselftest-arm64
11063 12:13:15.702432 + TESTRUN_ID=1_kselftest-arm64
11064 12:13:15.708939 + cd /lava-10605382/0/tests/1_kselftest-arm64
11065 12:13:15.709048 ++ cat uuid
11066 12:13:15.714084 + UUID=10605382_1.6.2.3.5
11067 12:13:15.714186 + set +x
11068 12:13:15.720354 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10605382_1.6.2.3.5>
11069 12:13:15.720672 Received signal: <STARTRUN> 1_kselftest-arm64 10605382_1.6.2.3.5
11070 12:13:15.720776 Starting test lava.1_kselftest-arm64 (10605382_1.6.2.3.5)
11071 12:13:15.720900 Skipping test definition patterns.
11072 12:13:15.723823 + cd ./automated/linux/kselftest/
11073 12:13:15.749947 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11074 12:13:15.794000 INFO: install_deps skipped
11075 12:13:15.912400 --2023-06-06 12:13:21-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11076 12:13:15.918794 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11077 12:13:16.057113 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11078 12:13:16.202976 HTTP request sent, awaiting response... 200 OK
11079 12:13:16.206590 Length: 2704052 (2.6M) [application/octet-stream]
11080 12:13:16.209612 Saving to: 'kselftest.tar.xz'
11081 12:13:16.209723
11082 12:13:16.209815
11083 12:13:16.484458 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11084 12:13:16.765255 kselftest.tar.xz 1%[ ] 46.39K 166KB/s
11085 12:13:17.046820 kselftest.tar.xz 8%[> ] 213.25K 380KB/s
11086 12:13:17.329619 kselftest.tar.xz 20%[===> ] 542.73K 644KB/s
11087 12:13:17.616231 kselftest.tar.xz 33%[=====> ] 879.28K 782KB/s
11088 12:13:17.897871 kselftest.tar.xz 46%[========> ] 1.21M 875KB/s
11089 12:13:18.178718 kselftest.tar.xz 60%[===========> ] 1.57M 951KB/s
11090 12:13:18.378643 kselftest.tar.xz 75%[==============> ] 1.95M 1013KB/s
11091 12:13:18.603631 kselftest.tar.xz 90%[=================> ] 2.34M 1.08MB/s
11092 12:13:18.609787 kselftest.tar.xz 99%[==================> ] 2.56M 1.07MB/s
11093 12:13:18.616829 kselftest.tar.xz 100%[===================>] 2.58M 1.07MB/s in 2.4s
11094 12:13:18.616958
11095 12:13:18.845569 2023-06-06 12:13:24 (1.07 MB/s) - 'kselftest.tar.xz' saved [2704052/2704052]
11096 12:13:18.845726
11097 12:13:24.686396 skiplist:
11098 12:13:24.689321 ========================================
11099 12:13:24.692899 ========================================
11100 12:13:24.739632 arm64:tags_test
11101 12:13:24.742722 arm64:run_tags_test.sh
11102 12:13:24.742839 arm64:fake_sigreturn_bad_magic
11103 12:13:24.746429 arm64:fake_sigreturn_bad_size
11104 12:13:24.749931 arm64:fake_sigreturn_bad_size_for_magic0
11105 12:13:24.753082 arm64:fake_sigreturn_duplicated_fpsimd
11106 12:13:24.756446 arm64:fake_sigreturn_misaligned_sp
11107 12:13:24.759532 arm64:fake_sigreturn_missing_fpsimd
11108 12:13:24.762492 arm64:fake_sigreturn_sme_change_vl
11109 12:13:24.766280 arm64:fake_sigreturn_sve_change_vl
11110 12:13:24.769183 arm64:mangle_pstate_invalid_compat_toggle
11111 12:13:24.772872 arm64:mangle_pstate_invalid_daif_bits
11112 12:13:24.775884 arm64:mangle_pstate_invalid_mode_el1h
11113 12:13:24.779210 arm64:mangle_pstate_invalid_mode_el1t
11114 12:13:24.782767 arm64:mangle_pstate_invalid_mode_el2h
11115 12:13:24.785856 arm64:mangle_pstate_invalid_mode_el2t
11116 12:13:24.788918 arm64:mangle_pstate_invalid_mode_el3h
11117 12:13:24.795706 arm64:mangle_pstate_invalid_mode_el3t
11118 12:13:24.795787 arm64:sme_trap_no_sm
11119 12:13:24.798703 arm64:sme_trap_non_streaming
11120 12:13:24.798824 arm64:sme_trap_za
11121 12:13:24.802214 arm64:sme_vl
11122 12:13:24.802296 arm64:ssve_regs
11123 12:13:24.806133 arm64:sve_regs
11124 12:13:24.806215 arm64:sve_vl
11125 12:13:24.806278 arm64:za_no_regs
11126 12:13:24.808756 arm64:za_regs
11127 12:13:24.808839 arm64:pac
11128 12:13:24.812478 arm64:fp-stress
11129 12:13:24.812562 arm64:sve-ptrace
11130 12:13:24.815534 arm64:sve-probe-vls
11131 12:13:24.815617 arm64:vec-syscfg
11132 12:13:24.815684 arm64:za-fork
11133 12:13:24.818641 arm64:za-ptrace
11134 12:13:24.822352 arm64:check_buffer_fill
11135 12:13:24.822435 arm64:check_child_memory
11136 12:13:24.825377 arm64:check_gcr_el1_cswitch
11137 12:13:24.828655 arm64:check_ksm_options
11138 12:13:24.828738 arm64:check_mmap_options
11139 12:13:24.832280 arm64:check_prctl
11140 12:13:24.835314 arm64:check_tags_inclusion
11141 12:13:24.835399 arm64:check_user_mem
11142 12:13:24.838442 arm64:btitest
11143 12:13:24.838549 arm64:nobtitest
11144 12:13:24.838641 arm64:hwcap
11145 12:13:24.841711 arm64:ptrace
11146 12:13:24.841792 arm64:syscall-abi
11147 12:13:24.845537 arm64:tpidr2
11148 12:13:24.848537 ============== Tests to run ===============
11149 12:13:24.848620 arm64:tags_test
11150 12:13:24.851719 arm64:run_tags_test.sh
11151 12:13:24.855235 arm64:fake_sigreturn_bad_magic
11152 12:13:24.858298 arm64:fake_sigreturn_bad_size
11153 12:13:24.861775 arm64:fake_sigreturn_bad_size_for_magic0
11154 12:13:24.864721 arm64:fake_sigreturn_duplicated_fpsimd
11155 12:13:24.868274 arm64:fake_sigreturn_misaligned_sp
11156 12:13:24.871735 arm64:fake_sigreturn_missing_fpsimd
11157 12:13:24.874746 arm64:fake_sigreturn_sme_change_vl
11158 12:13:24.878407 arm64:fake_sigreturn_sve_change_vl
11159 12:13:24.881283 arm64:mangle_pstate_invalid_compat_toggle
11160 12:13:24.884832 arm64:mangle_pstate_invalid_daif_bits
11161 12:13:24.887905 arm64:mangle_pstate_invalid_mode_el1h
11162 12:13:24.891621 arm64:mangle_pstate_invalid_mode_el1t
11163 12:13:24.894632 arm64:mangle_pstate_invalid_mode_el2h
11164 12:13:24.898293 arm64:mangle_pstate_invalid_mode_el2t
11165 12:13:24.901316 arm64:mangle_pstate_invalid_mode_el3h
11166 12:13:24.904334 arm64:mangle_pstate_invalid_mode_el3t
11167 12:13:24.904416 arm64:sme_trap_no_sm
11168 12:13:24.907805 arm64:sme_trap_non_streaming
11169 12:13:24.911346 arm64:sme_trap_za
11170 12:13:24.911429 arm64:sme_vl
11171 12:13:24.914181 arm64:ssve_regs
11172 12:13:24.914262 arm64:sve_regs
11173 12:13:24.914326 arm64:sve_vl
11174 12:13:24.918056 arm64:za_no_regs
11175 12:13:24.918137 arm64:za_regs
11176 12:13:24.918201 arm64:pac
11177 12:13:24.921124 arm64:fp-stress
11178 12:13:24.921207 arm64:sve-ptrace
11179 12:13:24.924290 arm64:sve-probe-vls
11180 12:13:24.924374 arm64:vec-syscfg
11181 12:13:24.927951 arm64:za-fork
11182 12:13:24.928034 arm64:za-ptrace
11183 12:13:24.931114 arm64:check_buffer_fill
11184 12:13:24.934168 arm64:check_child_memory
11185 12:13:24.934251 arm64:check_gcr_el1_cswitch
11186 12:13:24.937242 arm64:check_ksm_options
11187 12:13:24.940912 arm64:check_mmap_options
11188 12:13:24.940995 arm64:check_prctl
11189 12:13:24.944129 arm64:check_tags_inclusion
11190 12:13:24.947416 arm64:check_user_mem
11191 12:13:24.947514 arm64:btitest
11192 12:13:24.947581 arm64:nobtitest
11193 12:13:24.950616 arm64:hwcap
11194 12:13:24.950700 arm64:ptrace
11195 12:13:24.953675 arm64:syscall-abi
11196 12:13:24.953758 arm64:tpidr2
11197 12:13:24.957513 ===========End Tests to run ===============
11198 12:13:25.229795 <12>[ 37.740523] kselftest: Running tests in arm64
11199 12:13:25.239544 TAP version 13
11200 12:13:25.252450 1..48
11201 12:13:25.270461 # selftests: arm64: tags_test
11202 12:13:25.662735 ok 1 selftests: arm64: tags_test
11203 12:13:25.677944 # selftests: arm64: run_tags_test.sh
11204 12:13:25.731731 # --------------------
11205 12:13:25.735007 # running tags test
11206 12:13:25.735096 # --------------------
11207 12:13:25.738017 # [PASS]
11208 12:13:25.741367 ok 2 selftests: arm64: run_tags_test.sh
11209 12:13:25.756880 # selftests: arm64: fake_sigreturn_bad_magic
11210 12:13:25.811347 # Registered handlers for all signals.
11211 12:13:25.811457 # Detected MINSTKSIGSZ:4720
11212 12:13:25.814566 # Testcase initialized.
11213 12:13:25.817678 # uc context validated.
11214 12:13:25.821348 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11215 12:13:25.824463 # Handled SIG_COPYCTX
11216 12:13:25.824547 # Available space:3568
11217 12:13:25.830823 # Using badly built context - ERR: BAD MAGIC !
11218 12:13:25.837991 # SIG_OK -- SP:0xFFFFD898E1E0 si_addr@:0xffffd898e1e0 si_code:2 token@:0xffffd898cf80 offset:-4704
11219 12:13:25.841337 # ==>> completed. PASS(1)
11220 12:13:25.847849 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11221 12:13:25.854401 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD898CF80
11222 12:13:25.860875 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11223 12:13:25.864150 # selftests: arm64: fake_sigreturn_bad_size
11224 12:13:25.884818 # Registered handlers for all signals.
11225 12:13:25.884944 # Detected MINSTKSIGSZ:4720
11226 12:13:25.888528 # Testcase initialized.
11227 12:13:25.891744 # uc context validated.
11228 12:13:25.894792 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11229 12:13:25.898120 # Handled SIG_COPYCTX
11230 12:13:25.898226 # Available space:3568
11231 12:13:25.901192 # uc context validated.
11232 12:13:25.908010 # Using badly built context - ERR: Bad size for esr_context
11233 12:13:25.914737 # SIG_OK -- SP:0xFFFFD8BAF4C0 si_addr@:0xffffd8baf4c0 si_code:2 token@:0xffffd8bae260 offset:-4704
11234 12:13:25.917791 # ==>> completed. PASS(1)
11235 12:13:25.924715 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11236 12:13:25.930987 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD8BAE260
11237 12:13:25.934543 ok 4 selftests: arm64: fake_sigreturn_bad_size
11238 12:13:25.940904 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11239 12:13:25.961171 # Registered handlers for all signals.
11240 12:13:25.961256 # Detected MINSTKSIGSZ:4720
11241 12:13:25.964526 # Testcase initialized.
11242 12:13:25.967879 # uc context validated.
11243 12:13:25.971092 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11244 12:13:25.974331 # Handled SIG_COPYCTX
11245 12:13:25.974434 # Available space:3568
11246 12:13:25.981054 # Using badly built context - ERR: Bad size for terminator
11247 12:13:25.991311 # SIG_OK -- SP:0xFFFFFEA06400 si_addr@:0xfffffea06400 si_code:2 token@:0xfffffea051a0 offset:-4704
11248 12:13:25.991413 # ==>> completed. PASS(1)
11249 12:13:26.000732 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11250 12:13:26.007810 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFEA051A0
11251 12:13:26.010942 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11252 12:13:26.017620 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11253 12:13:26.037670 # Registered handlers for all signals.
11254 12:13:26.037756 # Detected MINSTKSIGSZ:4720
11255 12:13:26.040753 # Testcase initialized.
11256 12:13:26.044467 # uc context validated.
11257 12:13:26.047513 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11258 12:13:26.051036 # Handled SIG_COPYCTX
11259 12:13:26.051118 # Available space:3568
11260 12:13:26.057562 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11261 12:13:26.067201 # SIG_OK -- SP:0xFFFFFA28F880 si_addr@:0xfffffa28f880 si_code:2 token@:0xfffffa28e620 offset:-4704
11262 12:13:26.067309 # ==>> completed. PASS(1)
11263 12:13:26.077017 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11264 12:13:26.083931 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFA28E620
11265 12:13:26.086865 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11266 12:13:26.090433 # selftests: arm64: fake_sigreturn_misaligned_sp
11267 12:13:26.108873 # Registered handlers for all signals.
11268 12:13:26.108981 # Detected MINSTKSIGSZ:4720
11269 12:13:26.112052 # Testcase initialized.
11270 12:13:26.115140 # uc context validated.
11271 12:13:26.118854 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11272 12:13:26.121871 # Handled SIG_COPYCTX
11273 12:13:26.128688 # SIG_OK -- SP:0xFFFFCE8720F3 si_addr@:0xffffce8720f3 si_code:2 token@:0xffffce8720f3 offset:0
11274 12:13:26.131824 # ==>> completed. PASS(1)
11275 12:13:26.138236 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11276 12:13:26.145047 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCE8720F3
11277 12:13:26.151978 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11278 12:13:26.154938 # selftests: arm64: fake_sigreturn_missing_fpsimd
11279 12:13:26.184987 # Registered handlers for all signals.
11280 12:13:26.185114 # Detected MINSTKSIGSZ:4720
11281 12:13:26.188384 # Testcase initialized.
11282 12:13:26.191804 # uc context validated.
11283 12:13:26.194535 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11284 12:13:26.197949 # Handled SIG_COPYCTX
11285 12:13:26.200996 # Mangling template header. Spare space:4096
11286 12:13:26.204582 # Using badly built context - ERR: Missing FPSIMD
11287 12:13:26.214078 # SIG_OK -- SP:0xFFFFC3DAAF10 si_addr@:0xffffc3daaf10 si_code:2 token@:0xffffc3da9cb0 offset:-4704
11288 12:13:26.217607 # ==>> completed. PASS(1)
11289 12:13:26.224447 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11290 12:13:26.230789 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC3DA9CB0
11291 12:13:26.234018 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11292 12:13:26.240777 # selftests: arm64: fake_sigreturn_sme_change_vl
11293 12:13:26.261226 # Registered handlers for all signals.
11294 12:13:26.261339 # Detected MINSTKSIGSZ:4720
11295 12:13:26.264164 # ==>> completed. SKIP.
11296 12:13:26.270839 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11297 12:13:26.274113 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11298 12:13:26.280920 # selftests: arm64: fake_sigreturn_sve_change_vl
11299 12:13:26.334698 # Registered handlers for all signals.
11300 12:13:26.334864 # Detected MINSTKSIGSZ:4720
11301 12:13:26.338530 # ==>> completed. SKIP.
11302 12:13:26.344660 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11303 12:13:26.347928 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11304 12:13:26.356682 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11305 12:13:26.410933 # Registered handlers for all signals.
11306 12:13:26.411095 # Detected MINSTKSIGSZ:4720
11307 12:13:26.413924 # Testcase initialized.
11308 12:13:26.417548 # uc context validated.
11309 12:13:26.417635 # Handled SIG_TRIG
11310 12:13:26.427338 # SIG_OK -- SP:0xFFFFC3391170 si_addr@:0xffffc3391170 si_code:2 token@:(nil) offset:-281473957040496
11311 12:13:26.430567 # ==>> completed. PASS(1)
11312 12:13:26.436835 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11313 12:13:26.443588 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11314 12:13:26.446844 # selftests: arm64: mangle_pstate_invalid_daif_bits
11315 12:13:26.487739 # Registered handlers for all signals.
11316 12:13:26.487852 # Detected MINSTKSIGSZ:4720
11317 12:13:26.490702 # Testcase initialized.
11318 12:13:26.494191 # uc context validated.
11319 12:13:26.494277 # Handled SIG_TRIG
11320 12:13:26.503790 # SIG_OK -- SP:0xFFFFC90AD8B0 si_addr@:0xffffc90ad8b0 si_code:2 token@:(nil) offset:-281474054674608
11321 12:13:26.507311 # ==>> completed. PASS(1)
11322 12:13:26.513653 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11323 12:13:26.516968 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11324 12:13:26.524067 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11325 12:13:26.562945 # Registered handlers for all signals.
11326 12:13:26.563054 # Detected MINSTKSIGSZ:4720
11327 12:13:26.566046 # Testcase initialized.
11328 12:13:26.569664 # uc context validated.
11329 12:13:26.569750 # Handled SIG_TRIG
11330 12:13:26.579508 # SIG_OK -- SP:0xFFFFF33C7500 si_addr@:0xfffff33c7500 si_code:2 token@:(nil) offset:-281474762568960
11331 12:13:26.582503 # ==>> completed. PASS(1)
11332 12:13:26.589240 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11333 12:13:26.592304 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11334 12:13:26.598711 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11335 12:13:26.630660 # Registered handlers for all signals.
11336 12:13:26.630771 # Detected MINSTKSIGSZ:4720
11337 12:13:26.634105 # Testcase initialized.
11338 12:13:26.637225 # uc context validated.
11339 12:13:26.637312 # Handled SIG_TRIG
11340 12:13:26.647165 # SIG_OK -- SP:0xFFFFFD6B1E30 si_addr@:0xfffffd6b1e30 si_code:2 token@:(nil) offset:-281474933399088
11341 12:13:26.650755 # ==>> completed. PASS(1)
11342 12:13:26.657101 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11343 12:13:26.660255 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11344 12:13:26.667164 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11345 12:13:26.701415 # Registered handlers for all signals.
11346 12:13:26.701502 # Detected MINSTKSIGSZ:4720
11347 12:13:26.704117 # Testcase initialized.
11348 12:13:26.707663 # uc context validated.
11349 12:13:26.707771 # Handled SIG_TRIG
11350 12:13:26.717297 # SIG_OK -- SP:0xFFFFDD4DE7A0 si_addr@:0xffffdd4de7a0 si_code:2 token@:(nil) offset:-281474394613664
11351 12:13:26.720814 # ==>> completed. PASS(1)
11352 12:13:26.727257 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11353 12:13:26.730714 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11354 12:13:26.736925 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11355 12:13:26.772467 # Registered handlers for all signals.
11356 12:13:26.772634 # Detected MINSTKSIGSZ:4720
11357 12:13:26.775633 # Testcase initialized.
11358 12:13:26.779364 # uc context validated.
11359 12:13:26.779508 # Handled SIG_TRIG
11360 12:13:26.789272 # SIG_OK -- SP:0xFFFFFAE65030 si_addr@:0xfffffae65030 si_code:2 token@:(nil) offset:-281474891141168
11361 12:13:26.792269 # ==>> completed. PASS(1)
11362 12:13:26.799182 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11363 12:13:26.802305 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11364 12:13:26.808978 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11365 12:13:26.843244 # Registered handlers for all signals.
11366 12:13:26.843345 # Detected MINSTKSIGSZ:4720
11367 12:13:26.846002 # Testcase initialized.
11368 12:13:26.849796 # uc context validated.
11369 12:13:26.849874 # Handled SIG_TRIG
11370 12:13:26.859154 # SIG_OK -- SP:0xFFFFF89E6D70 si_addr@:0xfffff89e6d70 si_code:2 token@:(nil) offset:-281474852875632
11371 12:13:26.862798 # ==>> completed. PASS(1)
11372 12:13:26.868975 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11373 12:13:26.872721 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11374 12:13:26.879055 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11375 12:13:26.914156 # Registered handlers for all signals.
11376 12:13:26.914254 # Detected MINSTKSIGSZ:4720
11377 12:13:26.917688 # Testcase initialized.
11378 12:13:26.920854 # uc context validated.
11379 12:13:26.920934 # Handled SIG_TRIG
11380 12:13:26.930590 # SIG_OK -- SP:0xFFFFD4E2E070 si_addr@:0xffffd4e2e070 si_code:2 token@:(nil) offset:-281474253381744
11381 12:13:26.933675 # ==>> completed. PASS(1)
11382 12:13:26.940334 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11383 12:13:26.943805 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11384 12:13:26.947140 # selftests: arm64: sme_trap_no_sm
11385 12:13:26.983052 # Registered handlers for all signals.
11386 12:13:26.983186 # Detected MINSTKSIGSZ:4720
11387 12:13:26.986270 # ==>> completed. SKIP.
11388 12:13:26.996400 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11389 12:13:26.999809 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11390 12:13:27.002841 # selftests: arm64: sme_trap_non_streaming
11391 12:13:27.050149 # Registered handlers for all signals.
11392 12:13:27.050285 # Detected MINSTKSIGSZ:4720
11393 12:13:27.053654 # ==>> completed. SKIP.
11394 12:13:27.063402 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11395 12:13:27.070199 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11396 12:13:27.073305 # selftests: arm64: sme_trap_za
11397 12:13:27.121325 # Registered handlers for all signals.
11398 12:13:27.121427 # Detected MINSTKSIGSZ:4720
11399 12:13:27.124243 # Testcase initialized.
11400 12:13:27.134217 # SIG_OK -- SP:0xFFFFC869DC50 si_addr@:0xaaaab19e2510 si_code:1 token@:(nil) offset:-187650101093648
11401 12:13:27.137342 # ==>> completed. PASS(1)
11402 12:13:27.144298 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11403 12:13:27.147139 ok 21 selftests: arm64: sme_trap_za
11404 12:13:27.147245 # selftests: arm64: sme_vl
11405 12:13:27.193544 # Registered handlers for all signals.
11406 12:13:27.193639 # Detected MINSTKSIGSZ:4720
11407 12:13:27.197189 # ==>> completed. SKIP.
11408 12:13:27.203221 # # SME VL :: Check that we get the right SME VL reported
11409 12:13:27.206953 ok 22 selftests: arm64: sme_vl # SKIP
11410 12:13:27.210057 # selftests: arm64: ssve_regs
11411 12:13:27.264888 # Registered handlers for all signals.
11412 12:13:27.264994 # Detected MINSTKSIGSZ:4720
11413 12:13:27.268276 # ==>> completed. SKIP.
11414 12:13:27.274680 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11415 12:13:27.281427 ok 23 selftests: arm64: ssve_regs # SKIP
11416 12:13:27.281508 # selftests: arm64: sve_regs
11417 12:13:27.335450 # Registered handlers for all signals.
11418 12:13:27.335550 # Detected MINSTKSIGSZ:4720
11419 12:13:27.338462 # ==>> completed. SKIP.
11420 12:13:27.345331 # # SVE registers :: Check that we get the right SVE registers reported
11421 12:13:27.348478 ok 24 selftests: arm64: sve_regs # SKIP
11422 12:13:27.352621 # selftests: arm64: sve_vl
11423 12:13:27.410207 # Registered handlers for all signals.
11424 12:13:27.410346 # Detected MINSTKSIGSZ:4720
11425 12:13:27.413879 # ==>> completed. SKIP.
11426 12:13:27.419969 # # SVE VL :: Check that we get the right SVE VL reported
11427 12:13:27.423654 ok 25 selftests: arm64: sve_vl # SKIP
11428 12:13:27.429171 # selftests: arm64: za_no_regs
11429 12:13:27.487579 # Registered handlers for all signals.
11430 12:13:27.487718 # Detected MINSTKSIGSZ:4720
11431 12:13:27.490433 # ==>> completed. SKIP.
11432 12:13:27.496976 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11433 12:13:27.500045 ok 26 selftests: arm64: za_no_regs # SKIP
11434 12:13:27.504228 # selftests: arm64: za_regs
11435 12:13:27.561274 # Registered handlers for all signals.
11436 12:13:27.561415 # Detected MINSTKSIGSZ:4720
11437 12:13:27.565170 # ==>> completed. SKIP.
11438 12:13:27.571480 # # ZA register :: Check that we get the right ZA registers reported
11439 12:13:27.574986 ok 27 selftests: arm64: za_regs # SKIP
11440 12:13:27.579167 # selftests: arm64: pac
11441 12:13:27.635990 # TAP version 13
11442 12:13:27.636142 # 1..7
11443 12:13:27.639649 # # Starting 7 tests from 1 test cases.
11444 12:13:27.642795 # # RUN global.corrupt_pac ...
11445 12:13:27.645699 # # SKIP PAUTH not enabled
11446 12:13:27.649559 # # OK global.corrupt_pac
11447 12:13:27.652608 # ok 1 # SKIP PAUTH not enabled
11448 12:13:27.658957 # # RUN global.pac_instructions_not_nop ...
11449 12:13:27.662702 # # SKIP PAUTH not enabled
11450 12:13:27.665796 # # OK global.pac_instructions_not_nop
11451 12:13:27.668963 # ok 2 # SKIP PAUTH not enabled
11452 12:13:27.675929 # # RUN global.pac_instructions_not_nop_generic ...
11453 12:13:27.678737 # # SKIP Generic PAUTH not enabled
11454 12:13:27.682452 # # OK global.pac_instructions_not_nop_generic
11455 12:13:27.688888 # ok 3 # SKIP Generic PAUTH not enabled
11456 12:13:27.692390 # # RUN global.single_thread_different_keys ...
11457 12:13:27.695343 # # SKIP PAUTH not enabled
11458 12:13:27.702193 # # OK global.single_thread_different_keys
11459 12:13:27.702299 # ok 4 # SKIP PAUTH not enabled
11460 12:13:27.708928 # # RUN global.exec_changed_keys ...
11461 12:13:27.711792 # # SKIP PAUTH not enabled
11462 12:13:27.715376 # # OK global.exec_changed_keys
11463 12:13:27.718346 # ok 5 # SKIP PAUTH not enabled
11464 12:13:27.722184 # # RUN global.context_switch_keep_keys ...
11465 12:13:27.725292 # # SKIP PAUTH not enabled
11466 12:13:27.731975 # # OK global.context_switch_keep_keys
11467 12:13:27.735016 # ok 6 # SKIP PAUTH not enabled
11468 12:13:27.738209 # # RUN global.context_switch_keep_keys_generic ...
11469 12:13:27.741951 # # SKIP Generic PAUTH not enabled
11470 12:13:27.748084 # # OK global.context_switch_keep_keys_generic
11471 12:13:27.751559 # ok 7 # SKIP Generic PAUTH not enabled
11472 12:13:27.755298 # # PASSED: 7 / 7 tests passed.
11473 12:13:27.758475 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11474 12:13:27.761552 ok 28 selftests: arm64: pac
11475 12:13:27.764717 # selftests: arm64: fp-stress
11476 12:13:33.640364 <6>[ 46.154980] vpu: disabling
11477 12:13:33.644076 <6>[ 46.158036] vproc2: disabling
11478 12:13:33.647183 <6>[ 46.161653] vproc1: disabling
11479 12:13:33.650943 <6>[ 46.165315] vaud18: disabling
11480 12:13:33.657438 <6>[ 46.168879] vsram_others: disabling
11481 12:13:33.661175 <6>[ 46.172900] va09: disabling
11482 12:13:33.664004 <6>[ 46.176141] vsram_md: disabling
11483 12:13:33.667670 <6>[ 46.179773] Vgpu: disabling
11484 12:13:37.720966 # TAP version 13
11485 12:13:37.721149 # 1..16
11486 12:13:37.724379 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11487 12:13:37.727536 # # Will run for 10s
11488 12:13:37.727673 # # Started FPSIMD-0-0
11489 12:13:37.730634 # # Started FPSIMD-0-1
11490 12:13:37.734084 # # Started FPSIMD-1-0
11491 12:13:37.734166 # # Started FPSIMD-1-1
11492 12:13:37.737629 # # Started FPSIMD-2-0
11493 12:13:37.740499 # # Started FPSIMD-2-1
11494 12:13:37.740584 # # Started FPSIMD-3-0
11495 12:13:37.744239 # # Started FPSIMD-3-1
11496 12:13:37.747420 # # Started FPSIMD-4-0
11497 12:13:37.747497 # # Started FPSIMD-4-1
11498 12:13:37.750618 # # Started FPSIMD-5-0
11499 12:13:37.750730 # # Started FPSIMD-5-1
11500 12:13:37.753752 # # Started FPSIMD-6-0
11501 12:13:37.756940 # # Started FPSIMD-6-1
11502 12:13:37.757047 # # Started FPSIMD-7-0
11503 12:13:37.760747 # # Started FPSIMD-7-1
11504 12:13:37.763994 # # FPSIMD-1-1: Vector length: 128 bits
11505 12:13:37.767156 # # FPSIMD-1-1: PID: 1123
11506 12:13:37.770263 # # FPSIMD-2-0: Vector length: 128 bits
11507 12:13:37.773414 # # FPSIMD-2-0: PID: 1124
11508 12:13:37.777178 # # FPSIMD-2-1: Vector length: 128 bits
11509 12:13:37.777259 # # FPSIMD-2-1: PID: 1125
11510 12:13:37.780348 # # FPSIMD-4-0: Vector length: 128 bits
11511 12:13:37.783504 # # FPSIMD-4-0: PID: 1128
11512 12:13:37.786726 # # FPSIMD-5-1: Vector length: 128 bits
11513 12:13:37.789884 # # FPSIMD-5-1: PID: 1131
11514 12:13:37.793660 # # FPSIMD-4-1: Vector length: 128 bits
11515 12:13:37.796787 # # FPSIMD-4-1: PID: 1129
11516 12:13:37.800057 # # FPSIMD-5-0: Vector length: 128 bits
11517 12:13:37.800145 # # FPSIMD-5-0: PID: 1130
11518 12:13:37.806365 # # FPSIMD-0-0: Vector length: 128 bits
11519 12:13:37.806444 # # FPSIMD-0-0: PID: 1120
11520 12:13:37.810095 # # FPSIMD-6-0: Vector length: 128 bits
11521 12:13:37.813127 # # FPSIMD-6-0: PID: 1132
11522 12:13:37.816782 # # FPSIMD-1-0: Vector length: 128 bits
11523 12:13:37.819944 # # FPSIMD-1-0: PID: 1122
11524 12:13:37.823016 # # FPSIMD-0-1: Vector length: 128 bits
11525 12:13:37.826578 # # FPSIMD-0-1: PID: 1121
11526 12:13:37.829648 # # FPSIMD-3-1: Vector length: 128 bits
11527 12:13:37.829726 # # FPSIMD-3-1: PID: 1127
11528 12:13:37.836349 # # FPSIMD-3-0: Vector length: 128 bits
11529 12:13:37.836428 # # FPSIMD-3-0: PID: 1126
11530 12:13:37.839443 # # FPSIMD-7-0: Vector length: 128 bits
11531 12:13:37.842436 # # FPSIMD-7-0: PID: 1134
11532 12:13:37.846030 # # FPSIMD-7-1: Vector length: 128 bits
11533 12:13:37.849523 # # FPSIMD-7-1: PID: 1135
11534 12:13:37.852888 # # FPSIMD-6-1: Vector length: 128 bits
11535 12:13:37.856144 # # FPSIMD-6-1: PID: 1133
11536 12:13:37.856227 # # Finishing up...
11537 12:13:37.862451 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=346442, signals=10
11538 12:13:37.869462 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=987134, signals=10
11539 12:13:37.879423 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=781471, signals=10
11540 12:13:37.885748 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1129531, signals=10
11541 12:13:37.892157 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=715826, signals=10
11542 12:13:37.899189 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=806026, signals=10
11543 12:13:37.905276 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=579838, signals=10
11544 12:13:37.908901 # ok 1 FPSIMD-0-0
11545 12:13:37.908976 # ok 2 FPSIMD-0-1
11546 12:13:37.912073 # ok 3 FPSIMD-1-0
11547 12:13:37.912145 # ok 4 FPSIMD-1-1
11548 12:13:37.915113 # ok 5 FPSIMD-2-0
11549 12:13:37.915185 # ok 6 FPSIMD-2-1
11550 12:13:37.918785 # ok 7 FPSIMD-3-0
11551 12:13:37.918909 # ok 8 FPSIMD-3-1
11552 12:13:37.921863 # ok 9 FPSIMD-4-0
11553 12:13:37.921932 # ok 10 FPSIMD-4-1
11554 12:13:37.924951 # ok 11 FPSIMD-5-0
11555 12:13:37.925034 # ok 12 FPSIMD-5-1
11556 12:13:37.928763 # ok 13 FPSIMD-6-0
11557 12:13:37.928846 # ok 14 FPSIMD-6-1
11558 12:13:37.931782 # ok 15 FPSIMD-7-0
11559 12:13:37.931864 # ok 16 FPSIMD-7-1
11560 12:13:37.941691 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=926469, signals=9
11561 12:13:37.948316 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=348091, signals=10
11562 12:13:37.954771 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=484497, signals=10
11563 12:13:37.961885 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1514795, signals=10
11564 12:13:37.968320 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=605533, signals=9
11565 12:13:37.974676 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=425454, signals=10
11566 12:13:37.984725 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=970837, signals=10
11567 12:13:37.991101 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1409439, signals=10
11568 12:13:37.998101 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=739109, signals=9
11569 12:13:38.001177 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11570 12:13:38.004377 ok 29 selftests: arm64: fp-stress
11571 12:13:38.007555 # selftests: arm64: sve-ptrace
11572 12:13:38.010641 # TAP version 13
11573 12:13:38.010739 # 1..4104
11574 12:13:38.014390 # ok 2 # SKIP SVE not available
11575 12:13:38.017499 # # Planned tests != run tests (4104 != 1)
11576 12:13:38.023872 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11577 12:13:38.027662 ok 30 selftests: arm64: sve-ptrace # SKIP
11578 12:13:38.030625 # selftests: arm64: sve-probe-vls
11579 12:13:38.030708 # TAP version 13
11580 12:13:38.030774 # 1..2
11581 12:13:38.033809 # ok 2 # SKIP SVE not available
11582 12:13:38.037606 # # Planned tests != run tests (2 != 1)
11583 12:13:38.043515 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11584 12:13:38.047007 ok 31 selftests: arm64: sve-probe-vls # SKIP
11585 12:13:38.050015 # selftests: arm64: vec-syscfg
11586 12:13:38.050098 # TAP version 13
11587 12:13:38.053536 # 1..20
11588 12:13:38.053617 # ok 1 # SKIP SVE not supported
11589 12:13:38.056572 # ok 2 # SKIP SVE not supported
11590 12:13:38.060076 # ok 3 # SKIP SVE not supported
11591 12:13:38.063790 # ok 4 # SKIP SVE not supported
11592 12:13:38.066812 # ok 5 # SKIP SVE not supported
11593 12:13:38.069993 # ok 6 # SKIP SVE not supported
11594 12:13:38.073650 # ok 7 # SKIP SVE not supported
11595 12:13:38.076837 # ok 8 # SKIP SVE not supported
11596 12:13:38.076923 # ok 9 # SKIP SVE not supported
11597 12:13:38.080149 # ok 10 # SKIP SVE not supported
11598 12:13:38.083088 # ok 11 # SKIP SME not supported
11599 12:13:38.086250 # ok 12 # SKIP SME not supported
11600 12:13:38.090034 # ok 13 # SKIP SME not supported
11601 12:13:38.093192 # ok 14 # SKIP SME not supported
11602 12:13:38.096400 # ok 15 # SKIP SME not supported
11603 12:13:38.099625 # ok 16 # SKIP SME not supported
11604 12:13:38.102767 # ok 17 # SKIP SME not supported
11605 12:13:38.102902 # ok 18 # SKIP SME not supported
11606 12:13:38.106045 # ok 19 # SKIP SME not supported
11607 12:13:38.109933 # ok 20 # SKIP SME not supported
11608 12:13:38.116268 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11609 12:13:38.119381 ok 32 selftests: arm64: vec-syscfg
11610 12:13:38.119465 # selftests: arm64: za-fork
11611 12:13:38.123100 # TAP version 13
11612 12:13:38.123181 # 1..1
11613 12:13:38.126299 # # PID: 1206
11614 12:13:38.126381 # # SME support not present
11615 12:13:38.129546 # ok 0 skipped
11616 12:13:38.132614 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11617 12:13:38.136175 ok 33 selftests: arm64: za-fork
11618 12:13:38.139303 # selftests: arm64: za-ptrace
11619 12:13:38.139411 # TAP version 13
11620 12:13:38.142544 # 1..1
11621 12:13:38.145711 # ok 2 # SKIP SME not available
11622 12:13:38.149418 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11623 12:13:38.152792 ok 34 selftests: arm64: za-ptrace # SKIP
11624 12:13:38.155655 # selftests: arm64: check_buffer_fill
11625 12:13:38.162883 # # SKIP: MTE features unavailable
11626 12:13:38.170065 ok 35 selftests: arm64: check_buffer_fill # SKIP
11627 12:13:38.185066 # selftests: arm64: check_child_memory
11628 12:13:38.233343 # # SKIP: MTE features unavailable
11629 12:13:38.240170 ok 36 selftests: arm64: check_child_memory # SKIP
11630 12:13:38.256310 # selftests: arm64: check_gcr_el1_cswitch
11631 12:13:38.302797 # # SKIP: MTE features unavailable
11632 12:13:38.309788 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11633 12:13:38.324360 # selftests: arm64: check_ksm_options
11634 12:13:38.372258 # # SKIP: MTE features unavailable
11635 12:13:38.379153 ok 38 selftests: arm64: check_ksm_options # SKIP
11636 12:13:38.393161 # selftests: arm64: check_mmap_options
11637 12:13:38.441775 # # SKIP: MTE features unavailable
11638 12:13:38.448352 ok 39 selftests: arm64: check_mmap_options # SKIP
11639 12:13:38.460331 # selftests: arm64: check_prctl
11640 12:13:38.509263 # TAP version 13
11641 12:13:38.509398 # 1..5
11642 12:13:38.512949 # ok 1 check_basic_read
11643 12:13:38.513060 # ok 2 NONE
11644 12:13:38.516092 # ok 3 # SKIP SYNC
11645 12:13:38.516173 # ok 4 # SKIP ASYNC
11646 12:13:38.519270 # ok 5 # SKIP SYNC+ASYNC
11647 12:13:38.522443 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11648 12:13:38.526179 ok 40 selftests: arm64: check_prctl
11649 12:13:38.532349 # selftests: arm64: check_tags_inclusion
11650 12:13:38.578053 # # SKIP: MTE features unavailable
11651 12:13:38.585297 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11652 12:13:38.595465 # selftests: arm64: check_user_mem
11653 12:13:38.645143 # # SKIP: MTE features unavailable
11654 12:13:38.652009 ok 42 selftests: arm64: check_user_mem # SKIP
11655 12:13:38.663339 # selftests: arm64: btitest
11656 12:13:38.713530 # TAP version 13
11657 12:13:38.713648 # 1..18
11658 12:13:38.717219 # # HWCAP_PACA not present
11659 12:13:38.720272 # # HWCAP2_BTI not present
11660 12:13:38.720377 # # Test binary built for BTI
11661 12:13:38.727057 # ok 1 nohint_func/call_using_br_x0 # SKIP
11662 12:13:38.730172 # ok 1 nohint_func/call_using_br_x16 # SKIP
11663 12:13:38.733257 # ok 1 nohint_func/call_using_blr # SKIP
11664 12:13:38.737107 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11665 12:13:38.740233 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11666 12:13:38.746474 # ok 1 bti_none_func/call_using_blr # SKIP
11667 12:13:38.750174 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11668 12:13:38.753399 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11669 12:13:38.756530 # ok 1 bti_c_func/call_using_blr # SKIP
11670 12:13:38.759817 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11671 12:13:38.763090 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11672 12:13:38.766258 # ok 1 bti_j_func/call_using_blr # SKIP
11673 12:13:38.769558 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11674 12:13:38.776694 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11675 12:13:38.779787 # ok 1 bti_jc_func/call_using_blr # SKIP
11676 12:13:38.783244 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11677 12:13:38.786275 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11678 12:13:38.789802 # ok 1 paciasp_func/call_using_blr # SKIP
11679 12:13:38.796220 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11680 12:13:38.799159 # # WARNING - EXPECTED TEST COUNT WRONG
11681 12:13:38.802946 ok 43 selftests: arm64: btitest
11682 12:13:38.805999 # selftests: arm64: nobtitest
11683 12:13:38.806075 # TAP version 13
11684 12:13:38.806168 # 1..18
11685 12:13:38.809144 # # HWCAP_PACA not present
11686 12:13:38.812375 # # HWCAP2_BTI not present
11687 12:13:38.816133 # # Test binary not built for BTI
11688 12:13:38.819183 # ok 1 nohint_func/call_using_br_x0 # SKIP
11689 12:13:38.822356 # ok 1 nohint_func/call_using_br_x16 # SKIP
11690 12:13:38.825994 # ok 1 nohint_func/call_using_blr # SKIP
11691 12:13:38.828948 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11692 12:13:38.835869 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11693 12:13:38.839064 # ok 1 bti_none_func/call_using_blr # SKIP
11694 12:13:38.842235 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11695 12:13:38.845443 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11696 12:13:38.848645 # ok 1 bti_c_func/call_using_blr # SKIP
11697 12:13:38.851897 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11698 12:13:38.855732 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11699 12:13:38.859097 # ok 1 bti_j_func/call_using_blr # SKIP
11700 12:13:38.865204 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11701 12:13:38.868419 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11702 12:13:38.872161 # ok 1 bti_jc_func/call_using_blr # SKIP
11703 12:13:38.875440 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11704 12:13:38.878634 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11705 12:13:38.881692 # ok 1 paciasp_func/call_using_blr # SKIP
11706 12:13:38.888483 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11707 12:13:38.892027 # # WARNING - EXPECTED TEST COUNT WRONG
11708 12:13:38.895053 ok 44 selftests: arm64: nobtitest
11709 12:13:38.898040 # selftests: arm64: hwcap
11710 12:13:38.898124 # TAP version 13
11711 12:13:38.898195 # 1..28
11712 12:13:38.901757 # ok 1 cpuinfo_match_RNG
11713 12:13:38.904894 # # SIGILL reported for RNG
11714 12:13:38.908058 # ok 2 # SKIP sigill_RNG
11715 12:13:38.908142 # ok 3 cpuinfo_match_SME
11716 12:13:38.911685 # ok 4 sigill_SME
11717 12:13:38.911767 # ok 5 cpuinfo_match_SVE
11718 12:13:38.914959 # ok 6 sigill_SVE
11719 12:13:38.918114 # ok 7 cpuinfo_match_SVE 2
11720 12:13:38.918196 # # SIGILL reported for SVE 2
11721 12:13:38.921419 # ok 8 # SKIP sigill_SVE 2
11722 12:13:38.924566 # ok 9 cpuinfo_match_SVE AES
11723 12:13:38.928199 # # SIGILL reported for SVE AES
11724 12:13:38.931314 # ok 10 # SKIP sigill_SVE AES
11725 12:13:38.935135 # ok 11 cpuinfo_match_SVE2 PMULL
11726 12:13:38.937987 # # SIGILL reported for SVE2 PMULL
11727 12:13:38.938066 # ok 12 # SKIP sigill_SVE2 PMULL
11728 12:13:38.941513 # ok 13 cpuinfo_match_SVE2 BITPERM
11729 12:13:38.944535 # # SIGILL reported for SVE2 BITPERM
11730 12:13:38.947720 # ok 14 # SKIP sigill_SVE2 BITPERM
11731 12:13:38.950936 # ok 15 cpuinfo_match_SVE2 SHA3
11732 12:13:38.954414 # # SIGILL reported for SVE2 SHA3
11733 12:13:38.957491 # ok 16 # SKIP sigill_SVE2 SHA3
11734 12:13:38.961315 # ok 17 cpuinfo_match_SVE2 SM4
11735 12:13:38.964483 # # SIGILL reported for SVE2 SM4
11736 12:13:38.967577 # ok 18 # SKIP sigill_SVE2 SM4
11737 12:13:38.967682 # ok 19 cpuinfo_match_SVE2 I8MM
11738 12:13:38.970702 # # SIGILL reported for SVE2 I8MM
11739 12:13:38.973920 # ok 20 # SKIP sigill_SVE2 I8MM
11740 12:13:38.977618 # ok 21 cpuinfo_match_SVE2 F32MM
11741 12:13:38.980800 # # SIGILL reported for SVE2 F32MM
11742 12:13:38.984081 # ok 22 # SKIP sigill_SVE2 F32MM
11743 12:13:38.987427 # ok 23 cpuinfo_match_SVE2 F64MM
11744 12:13:38.990470 # # SIGILL reported for SVE2 F64MM
11745 12:13:38.994268 # ok 24 # SKIP sigill_SVE2 F64MM
11746 12:13:38.997104 # ok 25 cpuinfo_match_SVE2 BF16
11747 12:13:38.997187 # # SIGILL reported for SVE2 BF16
11748 12:13:39.000818 # ok 26 # SKIP sigill_SVE2 BF16
11749 12:13:39.003773 # ok 27 cpuinfo_match_SVE2 EBF16
11750 12:13:39.006917 # ok 28 # SKIP sigill_SVE2 EBF16
11751 12:13:39.013646 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11752 12:13:39.017480 ok 45 selftests: arm64: hwcap
11753 12:13:39.017564 # selftests: arm64: ptrace
11754 12:13:39.020053 # TAP version 13
11755 12:13:39.020136 # 1..7
11756 12:13:39.023698 # # Parent is 1435, child is 1436
11757 12:13:39.023820 # ok 1 read_tpidr_one
11758 12:13:39.026746 # ok 2 write_tpidr_one
11759 12:13:39.030588 # ok 3 verify_tpidr_one
11760 12:13:39.030661 # ok 4 count_tpidrs
11761 12:13:39.033775 # ok 5 tpidr2_write
11762 12:13:39.033846 # ok 6 tpidr2_read
11763 12:13:39.036974 # ok 7 write_tpidr_only
11764 12:13:39.043557 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11765 12:13:39.043642 ok 46 selftests: arm64: ptrace
11766 12:13:39.046556 # selftests: arm64: syscall-abi
11767 12:13:39.050247 # TAP version 13
11768 12:13:39.050331 # 1..2
11769 12:13:39.053437 # ok 1 getpid() FPSIMD
11770 12:13:39.053522 # ok 2 sched_yield() FPSIMD
11771 12:13:39.060179 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11772 12:13:39.063289 ok 47 selftests: arm64: syscall-abi
11773 12:13:39.066467 # selftests: arm64: tpidr2
11774 12:13:39.069622 # TAP version 13
11775 12:13:39.069706 # 1..5
11776 12:13:39.069773 # # PID: 1470
11777 12:13:39.072876 # # SME support not present
11778 12:13:39.076023 # ok 0 skipped, TPIDR2 not supported
11779 12:13:39.079853 # ok 1 skipped, TPIDR2 not supported
11780 12:13:39.083070 # ok 2 skipped, TPIDR2 not supported
11781 12:13:39.086283 # ok 3 skipped, TPIDR2 not supported
11782 12:13:39.089463 # ok 4 skipped, TPIDR2 not supported
11783 12:13:39.095975 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11784 12:13:39.098947 ok 48 selftests: arm64: tpidr2
11785 12:13:39.609695 arm64_tags_test pass
11786 12:13:39.612787 arm64_run_tags_test_sh pass
11787 12:13:39.616011 arm64_fake_sigreturn_bad_magic pass
11788 12:13:39.619330 arm64_fake_sigreturn_bad_size pass
11789 12:13:39.622531 arm64_fake_sigreturn_bad_size_for_magic0 pass
11790 12:13:39.625878 arm64_fake_sigreturn_duplicated_fpsimd pass
11791 12:13:39.629104 arm64_fake_sigreturn_misaligned_sp pass
11792 12:13:39.632742 arm64_fake_sigreturn_missing_fpsimd pass
11793 12:13:39.635730 arm64_fake_sigreturn_sme_change_vl skip
11794 12:13:39.642499 arm64_fake_sigreturn_sve_change_vl skip
11795 12:13:39.645551 arm64_mangle_pstate_invalid_compat_toggle pass
11796 12:13:39.648962 arm64_mangle_pstate_invalid_daif_bits pass
11797 12:13:39.652451 arm64_mangle_pstate_invalid_mode_el1h pass
11798 12:13:39.655499 arm64_mangle_pstate_invalid_mode_el1t pass
11799 12:13:39.659156 arm64_mangle_pstate_invalid_mode_el2h pass
11800 12:13:39.665836 arm64_mangle_pstate_invalid_mode_el2t pass
11801 12:13:39.669061 arm64_mangle_pstate_invalid_mode_el3h pass
11802 12:13:39.672262 arm64_mangle_pstate_invalid_mode_el3t pass
11803 12:13:39.675564 arm64_sme_trap_no_sm skip
11804 12:13:39.678734 arm64_sme_trap_non_streaming skip
11805 12:13:39.678855 arm64_sme_trap_za pass
11806 12:13:39.681889 arm64_sme_vl skip
11807 12:13:39.681999 arm64_ssve_regs skip
11808 12:13:39.685040 arm64_sve_regs skip
11809 12:13:39.685156 arm64_sve_vl skip
11810 12:13:39.688965 arm64_za_no_regs skip
11811 12:13:39.689085 arm64_za_regs skip
11812 12:13:39.691859 arm64_pac_PAUTH_not_enabled skip
11813 12:13:39.694940 arm64_pac_PAUTH_not_enabled skip
11814 12:13:39.698460 arm64_pac_Generic_PAUTH_not_enabled skip
11815 12:13:39.701844 arm64_pac_PAUTH_not_enabled skip
11816 12:13:39.705142 arm64_pac_PAUTH_not_enabled skip
11817 12:13:39.708641 arm64_pac_PAUTH_not_enabled skip
11818 12:13:39.711912 arm64_pac_Generic_PAUTH_not_enabled skip
11819 12:13:39.715053 arm64_pac pass
11820 12:13:39.715137 arm64_fp-stress_FPSIMD-0-0 pass
11821 12:13:39.718190 arm64_fp-stress_FPSIMD-0-1 pass
11822 12:13:39.721961 arm64_fp-stress_FPSIMD-1-0 pass
11823 12:13:39.725227 arm64_fp-stress_FPSIMD-1-1 pass
11824 12:13:39.728511 arm64_fp-stress_FPSIMD-2-0 pass
11825 12:13:39.731672 arm64_fp-stress_FPSIMD-2-1 pass
11826 12:13:39.734709 arm64_fp-stress_FPSIMD-3-0 pass
11827 12:13:39.737958 arm64_fp-stress_FPSIMD-3-1 pass
11828 12:13:39.738060 arm64_fp-stress_FPSIMD-4-0 pass
11829 12:13:39.741590 arm64_fp-stress_FPSIMD-4-1 pass
11830 12:13:39.744717 arm64_fp-stress_FPSIMD-5-0 pass
11831 12:13:39.747921 arm64_fp-stress_FPSIMD-5-1 pass
11832 12:13:39.751135 arm64_fp-stress_FPSIMD-6-0 pass
11833 12:13:39.754284 arm64_fp-stress_FPSIMD-6-1 pass
11834 12:13:39.757939 arm64_fp-stress_FPSIMD-7-0 pass
11835 12:13:39.758023 arm64_fp-stress_FPSIMD-7-1 pass
11836 12:13:39.761000 arm64_fp-stress pass
11837 12:13:39.764390 arm64_sve-ptrace_SVE_not_available skip
11838 12:13:39.767996 arm64_sve-ptrace skip
11839 12:13:39.770888 arm64_sve-probe-vls_SVE_not_available skip
11840 12:13:39.774467 arm64_sve-probe-vls skip
11841 12:13:39.777701 arm64_vec-syscfg_SVE_not_supported skip
11842 12:13:39.780821 arm64_vec-syscfg_SVE_not_supported skip
11843 12:13:39.784557 arm64_vec-syscfg_SVE_not_supported skip
11844 12:13:39.787606 arm64_vec-syscfg_SVE_not_supported skip
11845 12:13:39.790709 arm64_vec-syscfg_SVE_not_supported skip
11846 12:13:39.793964 arm64_vec-syscfg_SVE_not_supported skip
11847 12:13:39.797202 arm64_vec-syscfg_SVE_not_supported skip
11848 12:13:39.800463 arm64_vec-syscfg_SVE_not_supported skip
11849 12:13:39.804161 arm64_vec-syscfg_SVE_not_supported skip
11850 12:13:39.807147 arm64_vec-syscfg_SVE_not_supported skip
11851 12:13:39.810689 arm64_vec-syscfg_SME_not_supported skip
11852 12:13:39.817075 arm64_vec-syscfg_SME_not_supported skip
11853 12:13:39.820243 arm64_vec-syscfg_SME_not_supported skip
11854 12:13:39.824079 arm64_vec-syscfg_SME_not_supported skip
11855 12:13:39.827310 arm64_vec-syscfg_SME_not_supported skip
11856 12:13:39.830469 arm64_vec-syscfg_SME_not_supported skip
11857 12:13:39.833620 arm64_vec-syscfg_SME_not_supported skip
11858 12:13:39.836749 arm64_vec-syscfg_SME_not_supported skip
11859 12:13:39.840456 arm64_vec-syscfg_SME_not_supported skip
11860 12:13:39.843545 arm64_vec-syscfg_SME_not_supported skip
11861 12:13:39.846730 arm64_vec-syscfg pass
11862 12:13:39.846849 arm64_za-fork_skipped pass
11863 12:13:39.850039 arm64_za-fork pass
11864 12:13:39.853811 arm64_za-ptrace_SME_not_available skip
11865 12:13:39.857050 arm64_za-ptrace skip
11866 12:13:39.857156 arm64_check_buffer_fill skip
11867 12:13:39.860139 arm64_check_child_memory skip
11868 12:13:39.863337 arm64_check_gcr_el1_cswitch skip
11869 12:13:39.866442 arm64_check_ksm_options skip
11870 12:13:39.870008 arm64_check_mmap_options skip
11871 12:13:39.873518 arm64_check_prctl_check_basic_read pass
11872 12:13:39.876567 arm64_check_prctl_NONE pass
11873 12:13:39.876664 arm64_check_prctl_SYNC skip
11874 12:13:39.880045 arm64_check_prctl_ASYNC skip
11875 12:13:39.883067 arm64_check_prctl_SYNC_ASYNC skip
11876 12:13:39.887122 arm64_check_prctl pass
11877 12:13:39.889936 arm64_check_tags_inclusion skip
11878 12:13:39.890019 arm64_check_user_mem skip
11879 12:13:39.896655 arm64_btitest_nohint_func_call_using_br_x0 skip
11880 12:13:39.899770 arm64_btitest_nohint_func_call_using_br_x16 skip
11881 12:13:39.902814 arm64_btitest_nohint_func_call_using_blr skip
11882 12:13:39.906094 arm64_btitest_bti_none_func_call_using_br_x0 skip
11883 12:13:39.913069 arm64_btitest_bti_none_func_call_using_br_x16 skip
11884 12:13:39.916365 arm64_btitest_bti_none_func_call_using_blr skip
11885 12:13:39.919128 arm64_btitest_bti_c_func_call_using_br_x0 skip
11886 12:13:39.926050 arm64_btitest_bti_c_func_call_using_br_x16 skip
11887 12:13:39.929242 arm64_btitest_bti_c_func_call_using_blr skip
11888 12:13:39.932525 arm64_btitest_bti_j_func_call_using_br_x0 skip
11889 12:13:39.935684 arm64_btitest_bti_j_func_call_using_br_x16 skip
11890 12:13:39.942731 arm64_btitest_bti_j_func_call_using_blr skip
11891 12:13:39.946074 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11892 12:13:39.949028 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11893 12:13:39.952245 arm64_btitest_bti_jc_func_call_using_blr skip
11894 12:13:39.959306 arm64_btitest_paciasp_func_call_using_br_x0 skip
11895 12:13:39.962375 arm64_btitest_paciasp_func_call_using_br_x16 skip
11896 12:13:39.965679 arm64_btitest_paciasp_func_call_using_blr skip
11897 12:13:39.968671 arm64_btitest pass
11898 12:13:39.972527 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11899 12:13:39.978726 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11900 12:13:39.982279 arm64_nobtitest_nohint_func_call_using_blr skip
11901 12:13:39.985151 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11902 12:13:39.991838 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11903 12:13:39.995632 arm64_nobtitest_bti_none_func_call_using_blr skip
11904 12:13:39.998724 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11905 12:13:40.005473 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11906 12:13:40.008456 arm64_nobtitest_bti_c_func_call_using_blr skip
11907 12:13:40.012051 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11908 12:13:40.018333 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11909 12:13:40.021554 arm64_nobtitest_bti_j_func_call_using_blr skip
11910 12:13:40.025120 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11911 12:13:40.031696 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11912 12:13:40.034694 arm64_nobtitest_bti_jc_func_call_using_blr skip
11913 12:13:40.037919 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11914 12:13:40.044899 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11915 12:13:40.048006 arm64_nobtitest_paciasp_func_call_using_blr skip
11916 12:13:40.051211 arm64_nobtitest pass
11917 12:13:40.054666 arm64_hwcap_cpuinfo_match_RNG pass
11918 12:13:40.054781 arm64_hwcap_sigill_RNG skip
11919 12:13:40.057893 arm64_hwcap_cpuinfo_match_SME pass
11920 12:13:40.061148 arm64_hwcap_sigill_SME pass
11921 12:13:40.064388 arm64_hwcap_cpuinfo_match_SVE pass
11922 12:13:40.067596 arm64_hwcap_sigill_SVE pass
11923 12:13:40.070793 arm64_hwcap_cpuinfo_match_SVE_2 pass
11924 12:13:40.074629 arm64_hwcap_sigill_SVE_2 skip
11925 12:13:40.077697 arm64_hwcap_cpuinfo_match_SVE_AES pass
11926 12:13:40.077795 arm64_hwcap_sigill_SVE_AES skip
11927 12:13:40.083891 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11928 12:13:40.087498 arm64_hwcap_sigill_SVE2_PMULL skip
11929 12:13:40.090536 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11930 12:13:40.094198 arm64_hwcap_sigill_SVE2_BITPERM skip
11931 12:13:40.097213 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11932 12:13:40.100410 arm64_hwcap_sigill_SVE2_SHA3 skip
11933 12:13:40.104087 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11934 12:13:40.107129 arm64_hwcap_sigill_SVE2_SM4 skip
11935 12:13:40.110723 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11936 12:13:40.113986 arm64_hwcap_sigill_SVE2_I8MM skip
11937 12:13:40.117130 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11938 12:13:40.120311 arm64_hwcap_sigill_SVE2_F32MM skip
11939 12:13:40.123548 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11940 12:13:40.127232 arm64_hwcap_sigill_SVE2_F64MM skip
11941 12:13:40.130288 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11942 12:13:40.133565 arm64_hwcap_sigill_SVE2_BF16 skip
11943 12:13:40.136599 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11944 12:13:40.140396 arm64_hwcap_sigill_SVE2_EBF16 skip
11945 12:13:40.143206 arm64_hwcap pass
11946 12:13:40.143290 arm64_ptrace_read_tpidr_one pass
11947 12:13:40.147008 arm64_ptrace_write_tpidr_one pass
11948 12:13:40.150247 arm64_ptrace_verify_tpidr_one pass
11949 12:13:40.153538 arm64_ptrace_count_tpidrs pass
11950 12:13:40.156538 arm64_ptrace_tpidr2_write pass
11951 12:13:40.160133 arm64_ptrace_tpidr2_read pass
11952 12:13:40.163314 arm64_ptrace_write_tpidr_only pass
11953 12:13:40.163411 arm64_ptrace pass
11954 12:13:40.166397 arm64_syscall-abi_getpid_FPSIMD pass
11955 12:13:40.169506 arm64_syscall-abi_sched_yield_FPSIMD pass
11956 12:13:40.173177 arm64_syscall-abi pass
11957 12:13:40.176392 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11958 12:13:40.183200 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11959 12:13:40.186408 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11960 12:13:40.189550 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11961 12:13:40.192484 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11962 12:13:40.196156 arm64_tpidr2 pass
11963 12:13:40.199213 + ../../utils/send-to-lava.sh ./output/result.txt
11964 12:13:40.205988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11965 12:13:40.206266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11967 12:13:40.212324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11968 12:13:40.212579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11970 12:13:40.219158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11971 12:13:40.219411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11973 12:13:40.225449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11974 12:13:40.225704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11976 12:13:40.232295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11977 12:13:40.232549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11979 12:13:40.276297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11980 12:13:40.276567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11982 12:13:40.322168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11983 12:13:40.322469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11985 12:13:40.368865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11986 12:13:40.369205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11988 12:13:40.416175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11989 12:13:40.416444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11991 12:13:40.465453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11992 12:13:40.465737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11994 12:13:40.514627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11995 12:13:40.514902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11997 12:13:40.563835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11998 12:13:40.564116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12000 12:13:40.614312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12001 12:13:40.614590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12003 12:13:40.665070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12004 12:13:40.665362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12006 12:13:40.720485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12007 12:13:40.720758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12009 12:13:40.772997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12010 12:13:40.773276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12012 12:13:40.828370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12013 12:13:40.828643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12015 12:13:40.883644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12016 12:13:40.883967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12018 12:13:40.928468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12019 12:13:40.928739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12021 12:13:40.980424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12023 12:13:40.983459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12024 12:13:41.031567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12025 12:13:41.031893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12027 12:13:41.079214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12028 12:13:41.079498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12030 12:13:41.128029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12031 12:13:41.128329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12033 12:13:41.182597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12034 12:13:41.182926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12036 12:13:41.233836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12037 12:13:41.234134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12039 12:13:41.286106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12040 12:13:41.286413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12042 12:13:41.333596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12043 12:13:41.333862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12045 12:13:41.382910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12047 12:13:41.386201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12048 12:13:41.432954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12050 12:13:41.436271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12051 12:13:41.484617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12052 12:13:41.484924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12054 12:13:41.530547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12056 12:13:41.533419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12057 12:13:41.582366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12059 12:13:41.585181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12060 12:13:41.633297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12062 12:13:41.636148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12063 12:13:41.689961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12064 12:13:41.690269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12066 12:13:41.741193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12067 12:13:41.741470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12069 12:13:41.794779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12070 12:13:41.795072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12072 12:13:41.842398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12073 12:13:41.842668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12075 12:13:41.893156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12076 12:13:41.893439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12078 12:13:41.948240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12079 12:13:41.948568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12081 12:13:41.997783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12082 12:13:41.998066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12084 12:13:42.049044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12085 12:13:42.049330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12087 12:13:42.107173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12088 12:13:42.107448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12090 12:13:42.159914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12091 12:13:42.160193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12093 12:13:42.211247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12094 12:13:42.211511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12096 12:13:42.259011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12097 12:13:42.259284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12099 12:13:42.310345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12100 12:13:42.310611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12102 12:13:42.355770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12104 12:13:42.358507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12105 12:13:42.409655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12106 12:13:42.409940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12108 12:13:42.461245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12109 12:13:42.461550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12111 12:13:42.516996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12112 12:13:42.517271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12114 12:13:42.566848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12115 12:13:42.567128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12117 12:13:43.281319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12118 12:13:43.281631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12120 12:13:44.249838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12121 12:13:44.250154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12123 12:13:44.300819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12124 12:13:44.301161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12126 12:13:44.356527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12127 12:13:44.356811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12129 12:13:44.402688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12130 12:13:44.402989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12132 12:13:44.454674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12133 12:13:44.454952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12135 12:13:44.781414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12136 12:13:44.781727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12138 12:13:44.835807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12139 12:13:44.836073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12141 12:13:44.886184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12142 12:13:44.886459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12144 12:13:44.934441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12145 12:13:44.934702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12147 12:13:44.983386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12148 12:13:44.983652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12150 12:13:45.030058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12151 12:13:45.030317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12153 12:13:45.074803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12154 12:13:45.075123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12156 12:13:45.124892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12157 12:13:45.125159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12159 12:13:45.170019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12160 12:13:45.170427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12162 12:13:45.220380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12163 12:13:45.220674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12165 12:13:45.269093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12166 12:13:45.269440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12168 12:13:45.317016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12169 12:13:45.317349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12171 12:13:45.366706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12172 12:13:45.367032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12174 12:13:45.420879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12175 12:13:45.421150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12177 12:13:45.468427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12178 12:13:45.468751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12180 12:13:45.515103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12181 12:13:45.515396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12183 12:13:45.562421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12184 12:13:45.562728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12186 12:13:45.611779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12187 12:13:45.612046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12189 12:13:45.659215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12190 12:13:45.659504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12192 12:13:45.710045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12193 12:13:45.710308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12195 12:13:45.762196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12196 12:13:45.762507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12198 12:13:45.814313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12199 12:13:45.814581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12201 12:13:45.864390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12202 12:13:45.864669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12204 12:13:45.907668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12205 12:13:45.907942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12207 12:13:45.954744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12208 12:13:45.955045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12210 12:13:46.003859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12211 12:13:46.004139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12213 12:13:46.061160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12215 12:13:46.063740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12216 12:13:46.111578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12217 12:13:46.111848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12219 12:13:46.163478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12220 12:13:46.163834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12222 12:13:46.213784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12223 12:13:46.214107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12225 12:13:46.266474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12226 12:13:46.266752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12228 12:13:46.317480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12229 12:13:46.317753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12231 12:13:46.368458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12232 12:13:46.368757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12234 12:13:46.417757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12236 12:13:46.420762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12237 12:13:46.467032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12238 12:13:46.467315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12240 12:13:46.517326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12241 12:13:46.517618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12243 12:13:46.569742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12244 12:13:46.570030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12246 12:13:46.623834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12247 12:13:46.624118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12249 12:13:46.678715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12250 12:13:46.679041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12252 12:13:46.727682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12253 12:13:46.728027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12255 12:13:46.776351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12256 12:13:46.776669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12258 12:13:46.831330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12259 12:13:46.831617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12261 12:13:46.878038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12262 12:13:46.878325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12264 12:13:46.925942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12265 12:13:46.926211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12267 12:13:46.977456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12268 12:13:46.977767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12270 12:13:47.027922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12271 12:13:47.028187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12273 12:13:47.075609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12274 12:13:47.075896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12276 12:13:47.126136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12277 12:13:47.126406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12279 12:13:47.175107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12280 12:13:47.175398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12282 12:13:47.225557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12283 12:13:47.225858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12285 12:13:47.273645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12286 12:13:47.273938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12288 12:13:47.320019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12289 12:13:47.320296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12291 12:13:47.367036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12292 12:13:47.367311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12294 12:13:47.414085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12295 12:13:47.414460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12297 12:13:47.461977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12298 12:13:47.462263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12300 12:13:47.512707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12301 12:13:47.512979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12303 12:13:47.566950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12304 12:13:47.567229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12306 12:13:47.615527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12307 12:13:47.615797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12309 12:13:47.662512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12310 12:13:47.662790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12312 12:13:47.713980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12313 12:13:47.714332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12315 12:13:47.765036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12316 12:13:47.765328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12318 12:13:47.815047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12319 12:13:47.815364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12321 12:13:47.872857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12322 12:13:47.873144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12324 12:13:47.922124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12325 12:13:47.922426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12327 12:13:47.976339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12328 12:13:47.976631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12330 12:13:48.028179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12331 12:13:48.028460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12333 12:13:48.080757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12334 12:13:48.081069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12336 12:13:48.131352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12337 12:13:48.131629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12339 12:13:48.180573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12340 12:13:48.180896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12342 12:13:48.230940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12343 12:13:48.231214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12345 12:13:48.282320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12346 12:13:48.282643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12348 12:13:48.337694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12349 12:13:48.337977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12351 12:13:48.389279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12352 12:13:48.389613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12354 12:13:48.439478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12355 12:13:48.439806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12357 12:13:48.488600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12358 12:13:48.488914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12360 12:13:48.547003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12361 12:13:48.547305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12363 12:13:48.594576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12364 12:13:48.594868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12366 12:13:48.651574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12367 12:13:48.651841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12369 12:13:48.697739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12370 12:13:48.698077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12372 12:13:48.755664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12373 12:13:48.755967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12375 12:13:48.802077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12376 12:13:48.802462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12378 12:13:48.853216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12379 12:13:48.853541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12381 12:13:48.898323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12382 12:13:48.898636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12384 12:13:48.951909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12385 12:13:48.952186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12387 12:13:48.997156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12388 12:13:48.997427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12390 12:13:49.045734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12391 12:13:49.046062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12393 12:13:49.095272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12394 12:13:49.095583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12396 12:13:49.141796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12397 12:13:49.142071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12399 12:13:49.190143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12400 12:13:49.190438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12402 12:13:49.234546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12403 12:13:49.234812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12405 12:13:49.280744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12407 12:13:49.283642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12408 12:13:49.328853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12409 12:13:49.329193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12411 12:13:49.379513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12413 12:13:49.382853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12414 12:13:49.430002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12415 12:13:49.430299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12417 12:13:49.474910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12419 12:13:49.478337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12420 12:13:49.533138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12421 12:13:49.533422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12423 12:13:49.581135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12424 12:13:49.581422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12426 12:13:49.634324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12427 12:13:49.634610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12429 12:13:49.685524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12430 12:13:49.685809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12432 12:13:49.736835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12433 12:13:49.737116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12435 12:13:49.784823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12437 12:13:49.787855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12438 12:13:49.837563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12439 12:13:49.837851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12441 12:13:49.891442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12442 12:13:49.891718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12444 12:13:49.936871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12445 12:13:49.937160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12447 12:13:49.984634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12449 12:13:49.987568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12450 12:13:50.030435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12452 12:13:50.033219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12453 12:13:50.085412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12454 12:13:50.085741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12456 12:13:50.128020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12457 12:13:50.128293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12459 12:13:50.174388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12460 12:13:50.174679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12462 12:13:50.221077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12463 12:13:50.221354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12465 12:13:50.271564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12466 12:13:50.271853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12468 12:13:50.314704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12469 12:13:50.314966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12471 12:13:50.366595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12472 12:13:50.366928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12474 12:13:50.412478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12475 12:13:50.412783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12477 12:13:50.457022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12478 12:13:50.457303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12480 12:13:50.508143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12481 12:13:50.508425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12483 12:13:50.556847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12484 12:13:50.557216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12486 12:13:50.599995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12487 12:13:50.600268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12489 12:13:50.653415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12490 12:13:50.653696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12492 12:13:50.704454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12493 12:13:50.704739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12495 12:13:50.751875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12496 12:13:50.751974 + set +x
12497 12:13:50.752213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12499 12:13:50.758899 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10605382_1.6.2.3.5>
12500 12:13:50.759147 Received signal: <ENDRUN> 1_kselftest-arm64 10605382_1.6.2.3.5
12501 12:13:50.759221 Ending use of test pattern.
12502 12:13:50.759284 Ending test lava.1_kselftest-arm64 (10605382_1.6.2.3.5), duration 35.04
12504 12:13:50.761960 <LAVA_TEST_RUNNER EXIT>
12505 12:13:50.762199 ok: lava_test_shell seems to have completed
12506 12:13:50.763270 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12507 12:13:50.763424 end: 3.1 lava-test-shell (duration 00:00:36) [common]
12508 12:13:50.763514 end: 3 lava-test-retry (duration 00:00:36) [common]
12509 12:13:50.763603 start: 4 finalize (timeout 00:06:49) [common]
12510 12:13:50.763693 start: 4.1 power-off (timeout 00:00:30) [common]
12511 12:13:50.763849 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12512 12:13:50.839581 >> Command sent successfully.
12513 12:13:50.841919 Returned 0 in 0 seconds
12514 12:13:50.942316 end: 4.1 power-off (duration 00:00:00) [common]
12516 12:13:50.942690 start: 4.2 read-feedback (timeout 00:06:49) [common]
12517 12:13:50.942977 Listened to connection for namespace 'common' for up to 1s
12518 12:13:51.942939 Finalising connection for namespace 'common'
12519 12:13:51.943127 Disconnecting from shell: Finalise
12520 12:13:51.943238 / #
12521 12:13:52.043599 end: 4.2 read-feedback (duration 00:00:01) [common]
12522 12:13:52.043782 end: 4 finalize (duration 00:00:01) [common]
12523 12:13:52.043933 Cleaning after the job
12524 12:13:52.044061 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/ramdisk
12525 12:13:52.046091 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/kernel
12526 12:13:52.055309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/dtb
12527 12:13:52.055544 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/nfsrootfs
12528 12:13:52.125057 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605382/tftp-deploy-ppbz10u8/modules
12529 12:13:52.130543 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605382
12530 12:13:52.648221 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605382
12531 12:13:52.648401 Job finished correctly