Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 53
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 35
1 12:10:16.772278 lava-dispatcher, installed at version: 2023.05.1
2 12:10:16.772507 start: 0 validate
3 12:10:16.772675 Start time: 2023-06-06 12:10:16.772665+00:00 (UTC)
4 12:10:16.772810 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:10:16.772943 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:10:17.061432 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:10:17.061611 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:11:02.779808 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:11:02.780488 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:11:03.077237 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:11:03.077473 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:11:03.655573 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:11:03.655733 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:11:05.663547 validate duration: 48.89
16 12:11:05.664716 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:11:05.665359 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:11:05.665951 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:11:05.666701 Not decompressing ramdisk as can be used compressed.
20 12:11:05.667397 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/initrd.cpio.gz
21 12:11:05.667981 saving as /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/ramdisk/initrd.cpio.gz
22 12:11:05.668551 total size: 4665273 (4MB)
23 12:11:05.958988 progress 0% (0MB)
24 12:11:05.960832 progress 5% (0MB)
25 12:11:05.962305 progress 10% (0MB)
26 12:11:05.963683 progress 15% (0MB)
27 12:11:05.965069 progress 20% (0MB)
28 12:11:05.966425 progress 25% (1MB)
29 12:11:05.967687 progress 30% (1MB)
30 12:11:05.968931 progress 35% (1MB)
31 12:11:05.970200 progress 40% (1MB)
32 12:11:05.971608 progress 45% (2MB)
33 12:11:05.972916 progress 50% (2MB)
34 12:11:05.974121 progress 55% (2MB)
35 12:11:05.975332 progress 60% (2MB)
36 12:11:05.976576 progress 65% (2MB)
37 12:11:05.977798 progress 70% (3MB)
38 12:11:05.979005 progress 75% (3MB)
39 12:11:05.980210 progress 80% (3MB)
40 12:11:05.981655 progress 85% (3MB)
41 12:11:05.982876 progress 90% (4MB)
42 12:11:05.984086 progress 95% (4MB)
43 12:11:05.985406 progress 100% (4MB)
44 12:11:05.985608 4MB downloaded in 0.32s (14.03MB/s)
45 12:11:05.985762 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:11:05.986001 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:11:05.986127 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:11:05.986216 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:11:05.986344 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:11:05.986416 saving as /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/kernel/Image
52 12:11:05.986477 total size: 45746688 (43MB)
53 12:11:05.986537 No compression specified
54 12:11:05.987613 progress 0% (0MB)
55 12:11:05.999704 progress 5% (2MB)
56 12:11:06.011375 progress 10% (4MB)
57 12:11:06.022988 progress 15% (6MB)
58 12:11:06.034939 progress 20% (8MB)
59 12:11:06.046677 progress 25% (10MB)
60 12:11:06.058442 progress 30% (13MB)
61 12:11:06.070266 progress 35% (15MB)
62 12:11:06.082578 progress 40% (17MB)
63 12:11:06.094250 progress 45% (19MB)
64 12:11:06.105914 progress 50% (21MB)
65 12:11:06.117450 progress 55% (24MB)
66 12:11:06.129050 progress 60% (26MB)
67 12:11:06.140759 progress 65% (28MB)
68 12:11:06.152223 progress 70% (30MB)
69 12:11:06.163700 progress 75% (32MB)
70 12:11:06.175056 progress 80% (34MB)
71 12:11:06.186849 progress 85% (37MB)
72 12:11:06.198990 progress 90% (39MB)
73 12:11:06.210817 progress 95% (41MB)
74 12:11:06.222246 progress 100% (43MB)
75 12:11:06.222446 43MB downloaded in 0.24s (184.89MB/s)
76 12:11:06.222600 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:11:06.222835 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:11:06.222925 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:11:06.223015 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:11:06.223140 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:11:06.223211 saving as /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/dtb/mt8192-asurada-spherion-r0.dtb
83 12:11:06.223274 total size: 46924 (0MB)
84 12:11:06.223334 No compression specified
85 12:11:06.224418 progress 69% (0MB)
86 12:11:06.224727 progress 100% (0MB)
87 12:11:06.224882 0MB downloaded in 0.00s (27.88MB/s)
88 12:11:06.225005 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:11:06.225227 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:11:06.225314 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:11:06.225396 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:11:06.225508 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230527.0/arm64/full.rootfs.tar.xz
94 12:11:06.225578 saving as /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/nfsrootfs/full.rootfs.tar
95 12:11:06.225640 total size: 89386020 (85MB)
96 12:11:06.225700 Using unxz to decompress xz
97 12:11:06.229217 progress 0% (0MB)
98 12:11:06.437557 progress 5% (4MB)
99 12:11:06.663092 progress 10% (8MB)
100 12:11:06.924003 progress 15% (12MB)
101 12:11:07.122285 progress 20% (17MB)
102 12:11:07.216465 progress 25% (21MB)
103 12:11:07.468948 progress 30% (25MB)
104 12:11:07.758759 progress 35% (29MB)
105 12:11:08.028980 progress 40% (34MB)
106 12:11:08.286454 progress 45% (38MB)
107 12:11:08.530477 progress 50% (42MB)
108 12:11:08.787039 progress 55% (46MB)
109 12:11:09.035757 progress 60% (51MB)
110 12:11:09.303679 progress 65% (55MB)
111 12:11:09.606121 progress 70% (59MB)
112 12:11:09.906460 progress 75% (63MB)
113 12:11:10.207048 progress 80% (68MB)
114 12:11:10.458923 progress 85% (72MB)
115 12:11:10.691171 progress 90% (76MB)
116 12:11:10.949822 progress 95% (81MB)
117 12:11:11.215017 progress 100% (85MB)
118 12:11:11.221164 85MB downloaded in 5.00s (17.06MB/s)
119 12:11:11.221483 end: 1.4.1 http-download (duration 00:00:05) [common]
121 12:11:11.221756 end: 1.4 download-retry (duration 00:00:05) [common]
122 12:11:11.221847 start: 1.5 download-retry (timeout 00:09:54) [common]
123 12:11:11.221936 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 12:11:11.222084 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:11:11.222156 saving as /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/modules/modules.tar
126 12:11:11.222217 total size: 8553528 (8MB)
127 12:11:11.222280 Using unxz to decompress xz
128 12:11:11.225878 progress 0% (0MB)
129 12:11:11.247037 progress 5% (0MB)
130 12:11:11.271268 progress 10% (0MB)
131 12:11:11.303999 progress 15% (1MB)
132 12:11:11.330857 progress 20% (1MB)
133 12:11:11.355956 progress 25% (2MB)
134 12:11:11.381023 progress 30% (2MB)
135 12:11:11.407321 progress 35% (2MB)
136 12:11:11.432750 progress 40% (3MB)
137 12:11:11.459126 progress 45% (3MB)
138 12:11:11.484232 progress 50% (4MB)
139 12:11:11.509010 progress 55% (4MB)
140 12:11:11.532924 progress 60% (4MB)
141 12:11:11.559002 progress 65% (5MB)
142 12:11:11.584392 progress 70% (5MB)
143 12:11:11.609225 progress 75% (6MB)
144 12:11:11.635787 progress 80% (6MB)
145 12:11:11.661010 progress 85% (6MB)
146 12:11:11.685939 progress 90% (7MB)
147 12:11:11.709830 progress 95% (7MB)
148 12:11:11.737374 progress 100% (8MB)
149 12:11:11.742115 8MB downloaded in 0.52s (15.69MB/s)
150 12:11:11.742402 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:11:11.742666 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:11:11.742759 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 12:11:11.742851 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 12:11:13.594309 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how
156 12:11:13.594534 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:11:13.594682 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 12:11:13.594911 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv
159 12:11:13.595092 makedir: /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin
160 12:11:13.595274 makedir: /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/tests
161 12:11:13.595414 makedir: /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/results
162 12:11:13.595561 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-add-keys
163 12:11:13.595767 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-add-sources
164 12:11:13.595950 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-background-process-start
165 12:11:13.596092 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-background-process-stop
166 12:11:13.596216 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-common-functions
167 12:11:13.596335 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-echo-ipv4
168 12:11:13.596454 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-install-packages
169 12:11:13.596647 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-installed-packages
170 12:11:13.596837 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-os-build
171 12:11:13.597022 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-probe-channel
172 12:11:13.597246 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-probe-ip
173 12:11:13.597495 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-target-ip
174 12:11:13.597677 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-target-mac
175 12:11:13.597849 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-target-storage
176 12:11:13.598014 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-case
177 12:11:13.598182 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-event
178 12:11:13.598380 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-feedback
179 12:11:13.598513 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-raise
180 12:11:13.598634 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-reference
181 12:11:13.598754 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-runner
182 12:11:13.598872 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-set
183 12:11:13.598991 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-test-shell
184 12:11:13.599110 Updating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-install-packages (oe)
185 12:11:13.599258 Updating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/bin/lava-installed-packages (oe)
186 12:11:13.599383 Creating /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/environment
187 12:11:13.599480 LAVA metadata
188 12:11:13.599550 - LAVA_JOB_ID=10605392
189 12:11:13.599611 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:11:13.599716 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 12:11:13.599782 skipped lava-vland-overlay
192 12:11:13.599854 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:11:13.599933 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 12:11:13.600003 skipped lava-multinode-overlay
195 12:11:13.600074 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:11:13.600150 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 12:11:13.600223 Loading test definitions
198 12:11:13.600313 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 12:11:13.600382 Using /lava-10605392 at stage 0
200 12:11:13.600971 uuid=10605392_1.6.2.3.1 testdef=None
201 12:11:13.601061 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:11:13.601145 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 12:11:13.601612 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:11:13.601832 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 12:11:13.602416 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:11:13.602640 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 12:11:13.603218 runner path: /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/0/tests/0_lc-compliance test_uuid 10605392_1.6.2.3.1
210 12:11:13.603373 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:11:13.603574 Creating lava-test-runner.conf files
213 12:11:13.603635 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605392/lava-overlay-413k_5xv/lava-10605392/0 for stage 0
214 12:11:13.603724 - 0_lc-compliance
215 12:11:13.603817 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 12:11:13.603900 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 12:11:13.609714 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 12:11:13.609827 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 12:11:13.609913 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 12:11:13.609996 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 12:11:13.610079 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 12:11:13.730286 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 12:11:13.730690 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 12:11:13.730851 extracting modules file /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how
225 12:11:13.941887 extracting modules file /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605392/extract-overlay-ramdisk-qmjbn_x6/ramdisk
226 12:11:14.162401 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 12:11:14.162612 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 12:11:14.162711 [common] Applying overlay to NFS
229 12:11:14.162783 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605392/compress-overlay-23ihlri5/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how
230 12:11:14.169521 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 12:11:14.169664 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 12:11:14.169761 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 12:11:14.169853 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 12:11:14.169938 Building ramdisk /var/lib/lava/dispatcher/tmp/10605392/extract-overlay-ramdisk-qmjbn_x6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605392/extract-overlay-ramdisk-qmjbn_x6/ramdisk
235 12:11:14.445601 >> 117807 blocks
236 12:11:16.379339 rename /var/lib/lava/dispatcher/tmp/10605392/extract-overlay-ramdisk-qmjbn_x6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/ramdisk/ramdisk.cpio.gz
237 12:11:16.379777 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 12:11:16.379909 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 12:11:16.380012 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 12:11:16.380133 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/kernel/Image'
241 12:11:29.247752 Returned 0 in 12 seconds
242 12:11:29.348351 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/kernel/image.itb
243 12:11:29.672467 output: FIT description: Kernel Image image with one or more FDT blobs
244 12:11:29.672867 output: Created: Tue Jun 6 13:11:29 2023
245 12:11:29.672980 output: Image 0 (kernel-1)
246 12:11:29.673086 output: Description:
247 12:11:29.673182 output: Created: Tue Jun 6 13:11:29 2023
248 12:11:29.673281 output: Type: Kernel Image
249 12:11:29.673374 output: Compression: lzma compressed
250 12:11:29.673471 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
251 12:11:29.673563 output: Architecture: AArch64
252 12:11:29.673659 output: OS: Linux
253 12:11:29.673750 output: Load Address: 0x00000000
254 12:11:29.673844 output: Entry Point: 0x00000000
255 12:11:29.673933 output: Hash algo: crc32
256 12:11:29.674020 output: Hash value: fd97082e
257 12:11:29.674109 output: Image 1 (fdt-1)
258 12:11:29.674194 output: Description: mt8192-asurada-spherion-r0
259 12:11:29.674278 output: Created: Tue Jun 6 13:11:29 2023
260 12:11:29.674365 output: Type: Flat Device Tree
261 12:11:29.674478 output: Compression: uncompressed
262 12:11:29.674628 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 12:11:29.674725 output: Architecture: AArch64
264 12:11:29.674818 output: Hash algo: crc32
265 12:11:29.674917 output: Hash value: 1df858fa
266 12:11:29.675010 output: Image 2 (ramdisk-1)
267 12:11:29.675105 output: Description: unavailable
268 12:11:29.675197 output: Created: Tue Jun 6 13:11:29 2023
269 12:11:29.675293 output: Type: RAMDisk Image
270 12:11:29.675387 output: Compression: Unknown Compression
271 12:11:29.675479 output: Data Size: 17646190 Bytes = 17232.61 KiB = 16.83 MiB
272 12:11:29.675575 output: Architecture: AArch64
273 12:11:29.675667 output: OS: Linux
274 12:11:29.675737 output: Load Address: unavailable
275 12:11:29.675792 output: Entry Point: unavailable
276 12:11:29.675846 output: Hash algo: crc32
277 12:11:29.675906 output: Hash value: 86d1df64
278 12:11:29.675990 output: Default Configuration: 'conf-1'
279 12:11:29.676074 output: Configuration 0 (conf-1)
280 12:11:29.676162 output: Description: mt8192-asurada-spherion-r0
281 12:11:29.676245 output: Kernel: kernel-1
282 12:11:29.676332 output: Init Ramdisk: ramdisk-1
283 12:11:29.676415 output: FDT: fdt-1
284 12:11:29.676532 output: Loadables: kernel-1
285 12:11:29.676680 output:
286 12:11:29.676938 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 12:11:29.677093 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 12:11:29.677272 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 12:11:29.677437 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 12:11:29.677579 No LXC device requested
291 12:11:29.677732 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 12:11:29.677887 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 12:11:29.678032 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 12:11:29.678136 Checking files for TFTP limit of 4294967296 bytes.
295 12:11:29.678687 end: 1 tftp-deploy (duration 00:00:24) [common]
296 12:11:29.678821 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 12:11:29.678949 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 12:11:29.679126 substitutions:
299 12:11:29.679223 - {DTB}: 10605392/tftp-deploy-bmp9s55c/dtb/mt8192-asurada-spherion-r0.dtb
300 12:11:29.679334 - {INITRD}: 10605392/tftp-deploy-bmp9s55c/ramdisk/ramdisk.cpio.gz
301 12:11:29.679428 - {KERNEL}: 10605392/tftp-deploy-bmp9s55c/kernel/Image
302 12:11:29.679524 - {LAVA_MAC}: None
303 12:11:29.679615 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how
304 12:11:29.679707 - {NFS_SERVER_IP}: 192.168.201.1
305 12:11:29.679798 - {PRESEED_CONFIG}: None
306 12:11:29.679856 - {PRESEED_LOCAL}: None
307 12:11:29.679945 - {RAMDISK}: 10605392/tftp-deploy-bmp9s55c/ramdisk/ramdisk.cpio.gz
308 12:11:29.680032 - {ROOT_PART}: None
309 12:11:29.680128 - {ROOT}: None
310 12:11:29.680215 - {SERVER_IP}: 192.168.201.1
311 12:11:29.680307 - {TEE}: None
312 12:11:29.680393 Parsed boot commands:
313 12:11:29.680488 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 12:11:29.680748 Parsed boot commands: tftpboot 192.168.201.1 10605392/tftp-deploy-bmp9s55c/kernel/image.itb 10605392/tftp-deploy-bmp9s55c/kernel/cmdline
315 12:11:29.680842 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 12:11:29.680957 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 12:11:29.681083 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 12:11:29.681206 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 12:11:29.681310 Not connected, no need to disconnect.
320 12:11:29.681416 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 12:11:29.681538 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 12:11:29.681636 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
323 12:11:29.684985 Setting prompt string to ['lava-test: # ']
324 12:11:29.685355 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 12:11:29.685490 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 12:11:29.685630 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 12:11:29.685757 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 12:11:29.686085 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
329 12:11:34.826132 >> Command sent successfully.
330 12:11:34.828893 Returned 0 in 5 seconds
331 12:11:34.929289 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 12:11:34.929747 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 12:11:34.929889 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 12:11:34.930016 Setting prompt string to 'Starting depthcharge on Spherion...'
336 12:11:34.930116 Changing prompt to 'Starting depthcharge on Spherion...'
337 12:11:34.930223 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 12:11:34.930588 [Enter `^Ec?' for help]
339 12:11:35.100894
340 12:11:35.101055
341 12:11:35.101126 F0: 102B 0000
342 12:11:35.101200
343 12:11:35.101263 F3: 1001 0000 [0200]
344 12:11:35.101324
345 12:11:35.104789 F3: 1001 0000
346 12:11:35.104873
347 12:11:35.104938 F7: 102D 0000
348 12:11:35.105000
349 12:11:35.105072 F1: 0000 0000
350 12:11:35.105134
351 12:11:35.108706 V0: 0000 0000 [0001]
352 12:11:35.108795
353 12:11:35.108867 00: 0007 8000
354 12:11:35.108935
355 12:11:35.111924 01: 0000 0000
356 12:11:35.112034
357 12:11:35.112170 BP: 0C00 0209 [0000]
358 12:11:35.112260
359 12:11:35.112355 G0: 1182 0000
360 12:11:35.116008
361 12:11:35.116185 EC: 0000 0021 [4000]
362 12:11:35.116308
363 12:11:35.119836 S7: 0000 0000 [0000]
364 12:11:35.119978
365 12:11:35.120130 CC: 0000 0000 [0001]
366 12:11:35.120222
367 12:11:35.122901 T0: 0000 0040 [010F]
368 12:11:35.123009
369 12:11:35.123146 Jump to BL
370 12:11:35.123258
371 12:11:35.147630
372 12:11:35.147763
373 12:11:35.147835
374 12:11:35.154547 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 12:11:35.157875 ARM64: Exception handlers installed.
376 12:11:35.161571 ARM64: Testing exception
377 12:11:35.165391 ARM64: Done test exception
378 12:11:35.172379 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 12:11:35.182704 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 12:11:35.190322 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 12:11:35.200644 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 12:11:35.207720 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 12:11:35.214244 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 12:11:35.224485 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 12:11:35.230864 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 12:11:35.250266 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 12:11:35.253469 WDT: Last reset was cold boot
388 12:11:35.256668 SPI1(PAD0) initialized at 2873684 Hz
389 12:11:35.259913 SPI5(PAD0) initialized at 992727 Hz
390 12:11:35.263117 VBOOT: Loading verstage.
391 12:11:35.269920 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 12:11:35.273487 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 12:11:35.276762 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 12:11:35.280039 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 12:11:35.287578 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 12:11:35.294408 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 12:11:35.305324 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 12:11:35.305457
399 12:11:35.305572
400 12:11:35.314911 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 12:11:35.318806 ARM64: Exception handlers installed.
402 12:11:35.322026 ARM64: Testing exception
403 12:11:35.322146 ARM64: Done test exception
404 12:11:35.328342 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 12:11:35.332200 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 12:11:35.346176 Probing TPM: . done!
407 12:11:35.346318 TPM ready after 0 ms
408 12:11:35.353257 Connected to device vid:did:rid of 1ae0:0028:00
409 12:11:35.362999 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
410 12:11:35.401440 Initialized TPM device CR50 revision 0
411 12:11:35.413589 tlcl_send_startup: Startup return code is 0
412 12:11:35.413689 TPM: setup succeeded
413 12:11:35.425629 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 12:11:35.434156 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 12:11:35.445309 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 12:11:35.453589 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 12:11:35.456750 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 12:11:35.460067 in-header: 03 07 00 00 08 00 00 00
419 12:11:35.463341 in-data: aa e4 47 04 13 02 00 00
420 12:11:35.466593 Chrome EC: UHEPI supported
421 12:11:35.473014 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 12:11:35.476763 in-header: 03 ad 00 00 08 00 00 00
423 12:11:35.479968 in-data: 00 20 20 08 00 00 00 00
424 12:11:35.480085 Phase 1
425 12:11:35.483055 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 12:11:35.489919 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 12:11:35.496767 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 12:11:35.499904 Recovery requested (1009000e)
429 12:11:35.503682 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 12:11:35.512405 tlcl_extend: response is 0
431 12:11:35.520746 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 12:11:35.525815 tlcl_extend: response is 0
433 12:11:35.532221 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 12:11:35.553171 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
435 12:11:35.559543 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 12:11:35.559632
437 12:11:35.559699
438 12:11:35.570039 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 12:11:35.573200 ARM64: Exception handlers installed.
440 12:11:35.576451 ARM64: Testing exception
441 12:11:35.576586 ARM64: Done test exception
442 12:11:35.598770 pmic_efuse_setting: Set efuses in 11 msecs
443 12:11:35.602602 pmwrap_interface_init: Select PMIF_VLD_RDY
444 12:11:35.609666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 12:11:35.612861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 12:11:35.616164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 12:11:35.622597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 12:11:35.626348 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 12:11:35.633065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 12:11:35.636386 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 12:11:35.640166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 12:11:35.646420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 12:11:35.649602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 12:11:35.656016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 12:11:35.659402 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 12:11:35.662623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 12:11:35.669677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 12:11:35.676317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 12:11:35.683352 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 12:11:35.686456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 12:11:35.693349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 12:11:35.699695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 12:11:35.706151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 12:11:35.709229 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 12:11:35.716964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 12:11:35.720114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 12:11:35.727900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 12:11:35.731067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 12:11:35.737791 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 12:11:35.741059 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 12:11:35.748142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 12:11:35.751320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 12:11:35.758474 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 12:11:35.762356 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 12:11:35.765700 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 12:11:35.772123 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 12:11:35.778688 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 12:11:35.782616 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 12:11:35.788968 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 12:11:35.792129 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 12:11:35.799089 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 12:11:35.802961 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 12:11:35.806552 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 12:11:35.809686 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 12:11:35.816630 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 12:11:35.819912 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 12:11:35.823625 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 12:11:35.826765 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 12:11:35.833142 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 12:11:35.836899 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 12:11:35.840065 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 12:11:35.846681 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 12:11:35.849845 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 12:11:35.853059 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 12:11:35.860076 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 12:11:35.869760 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 12:11:35.872997 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 12:11:35.882872 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 12:11:35.889882 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 12:11:35.896060 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 12:11:35.899768 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 12:11:35.902908 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 12:11:35.910990 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
504 12:11:35.917355 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 12:11:35.921195 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
506 12:11:35.927357 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 12:11:35.936219 [RTC]rtc_get_frequency_meter,154: input=15, output=835
508 12:11:35.945040 [RTC]rtc_get_frequency_meter,154: input=7, output=709
509 12:11:35.954854 [RTC]rtc_get_frequency_meter,154: input=11, output=772
510 12:11:35.964284 [RTC]rtc_get_frequency_meter,154: input=13, output=803
511 12:11:35.973464 [RTC]rtc_get_frequency_meter,154: input=12, output=787
512 12:11:35.983206 [RTC]rtc_get_frequency_meter,154: input=12, output=788
513 12:11:35.992429 [RTC]rtc_get_frequency_meter,154: input=13, output=804
514 12:11:35.995652 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
515 12:11:36.003236 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
516 12:11:36.006393 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 12:11:36.009718 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 12:11:36.016068 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 12:11:36.019761 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 12:11:36.022955 ADC[4]: Raw value=903031 ID=7
521 12:11:36.023069 ADC[3]: Raw value=213282 ID=1
522 12:11:36.026184 RAM Code: 0x71
523 12:11:36.029432 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 12:11:36.035914 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 12:11:36.042924 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 12:11:36.049851 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 12:11:36.053033 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 12:11:36.056231 in-header: 03 07 00 00 08 00 00 00
529 12:11:36.059379 in-data: aa e4 47 04 13 02 00 00
530 12:11:36.062632 Chrome EC: UHEPI supported
531 12:11:36.069527 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 12:11:36.072734 in-header: 03 dd 00 00 08 00 00 00
533 12:11:36.076008 in-data: 90 20 60 08 00 00 00 00
534 12:11:36.079171 MRC: failed to locate region type 0.
535 12:11:36.085660 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 12:11:36.088904 DRAM-K: Running full calibration
537 12:11:36.095816 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 12:11:36.095900 header.status = 0x0
539 12:11:36.099061 header.version = 0x6 (expected: 0x6)
540 12:11:36.102898 header.size = 0xd00 (expected: 0xd00)
541 12:11:36.105903 header.flags = 0x0
542 12:11:36.112371 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 12:11:36.129286 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 12:11:36.135747 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 12:11:36.139688 dram_init: ddr_geometry: 2
546 12:11:36.142986 [EMI] MDL number = 2
547 12:11:36.143069 [EMI] Get MDL freq = 0
548 12:11:36.146033 dram_init: ddr_type: 0
549 12:11:36.146116 is_discrete_lpddr4: 1
550 12:11:36.149173 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 12:11:36.149256
552 12:11:36.149323
553 12:11:36.152413 [Bian_co] ETT version 0.0.0.1
554 12:11:36.159475 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 12:11:36.159558
556 12:11:36.162447 dramc_set_vcore_voltage set vcore to 650000
557 12:11:36.165797 Read voltage for 800, 4
558 12:11:36.165880 Vio18 = 0
559 12:11:36.165946 Vcore = 650000
560 12:11:36.169045 Vdram = 0
561 12:11:36.169128 Vddq = 0
562 12:11:36.169194 Vmddr = 0
563 12:11:36.172829 dram_init: config_dvfs: 1
564 12:11:36.176142 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 12:11:36.182536 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 12:11:36.185733 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
567 12:11:36.189003 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
568 12:11:36.192732 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
569 12:11:36.195965 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
570 12:11:36.199087 MEM_TYPE=3, freq_sel=18
571 12:11:36.202355 sv_algorithm_assistance_LP4_1600
572 12:11:36.206066 ============ PULL DRAM RESETB DOWN ============
573 12:11:36.212403 ========== PULL DRAM RESETB DOWN end =========
574 12:11:36.215528 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 12:11:36.218702 ===================================
576 12:11:36.222524 LPDDR4 DRAM CONFIGURATION
577 12:11:36.225695 ===================================
578 12:11:36.225805 EX_ROW_EN[0] = 0x0
579 12:11:36.228917 EX_ROW_EN[1] = 0x0
580 12:11:36.228996 LP4Y_EN = 0x0
581 12:11:36.232510 WORK_FSP = 0x0
582 12:11:36.232628 WL = 0x2
583 12:11:36.235759 RL = 0x2
584 12:11:36.235840 BL = 0x2
585 12:11:36.238880 RPST = 0x0
586 12:11:36.238987 RD_PRE = 0x0
587 12:11:36.242052 WR_PRE = 0x1
588 12:11:36.242124 WR_PST = 0x0
589 12:11:36.245428 DBI_WR = 0x0
590 12:11:36.248665 DBI_RD = 0x0
591 12:11:36.248764 OTF = 0x1
592 12:11:36.252433 ===================================
593 12:11:36.255767 ===================================
594 12:11:36.255852 ANA top config
595 12:11:36.259125 ===================================
596 12:11:36.262324 DLL_ASYNC_EN = 0
597 12:11:36.265424 ALL_SLAVE_EN = 1
598 12:11:36.269181 NEW_RANK_MODE = 1
599 12:11:36.272431 DLL_IDLE_MODE = 1
600 12:11:36.272511 LP45_APHY_COMB_EN = 1
601 12:11:36.275672 TX_ODT_DIS = 1
602 12:11:36.278982 NEW_8X_MODE = 1
603 12:11:36.282107 ===================================
604 12:11:36.285782 ===================================
605 12:11:36.288943 data_rate = 1600
606 12:11:36.292294 CKR = 1
607 12:11:36.292382 DQ_P2S_RATIO = 8
608 12:11:36.295488 ===================================
609 12:11:36.298746 CA_P2S_RATIO = 8
610 12:11:36.301841 DQ_CA_OPEN = 0
611 12:11:36.305675 DQ_SEMI_OPEN = 0
612 12:11:36.308828 CA_SEMI_OPEN = 0
613 12:11:36.312025 CA_FULL_RATE = 0
614 12:11:36.312109 DQ_CKDIV4_EN = 1
615 12:11:36.315118 CA_CKDIV4_EN = 1
616 12:11:36.318324 CA_PREDIV_EN = 0
617 12:11:36.322093 PH8_DLY = 0
618 12:11:36.325153 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 12:11:36.328234 DQ_AAMCK_DIV = 4
620 12:11:36.328318 CA_AAMCK_DIV = 4
621 12:11:36.332019 CA_ADMCK_DIV = 4
622 12:11:36.335096 DQ_TRACK_CA_EN = 0
623 12:11:36.338174 CA_PICK = 800
624 12:11:36.341977 CA_MCKIO = 800
625 12:11:36.345139 MCKIO_SEMI = 0
626 12:11:36.348360 PLL_FREQ = 3068
627 12:11:36.348444 DQ_UI_PI_RATIO = 32
628 12:11:36.351528 CA_UI_PI_RATIO = 0
629 12:11:36.354654 ===================================
630 12:11:36.358270 ===================================
631 12:11:36.361453 memory_type:LPDDR4
632 12:11:36.364658 GP_NUM : 10
633 12:11:36.364741 SRAM_EN : 1
634 12:11:36.367875 MD32_EN : 0
635 12:11:36.371571 ===================================
636 12:11:36.374916 [ANA_INIT] >>>>>>>>>>>>>>
637 12:11:36.374998 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 12:11:36.378094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 12:11:36.381442 ===================================
640 12:11:36.384534 data_rate = 1600,PCW = 0X7600
641 12:11:36.387861 ===================================
642 12:11:36.391040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 12:11:36.398195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 12:11:36.404661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 12:11:36.407790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 12:11:36.411092 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 12:11:36.414352 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 12:11:36.417561 [ANA_INIT] flow start
649 12:11:36.417649 [ANA_INIT] PLL >>>>>>>>
650 12:11:36.421128 [ANA_INIT] PLL <<<<<<<<
651 12:11:36.424360 [ANA_INIT] MIDPI >>>>>>>>
652 12:11:36.427543 [ANA_INIT] MIDPI <<<<<<<<
653 12:11:36.427651 [ANA_INIT] DLL >>>>>>>>
654 12:11:36.430664 [ANA_INIT] flow end
655 12:11:36.434394 ============ LP4 DIFF to SE enter ============
656 12:11:36.437641 ============ LP4 DIFF to SE exit ============
657 12:11:36.440763 [ANA_INIT] <<<<<<<<<<<<<
658 12:11:36.443971 [Flow] Enable top DCM control >>>>>
659 12:11:36.447643 [Flow] Enable top DCM control <<<<<
660 12:11:36.450952 Enable DLL master slave shuffle
661 12:11:36.457435 ==============================================================
662 12:11:36.457525 Gating Mode config
663 12:11:36.464532 ==============================================================
664 12:11:36.464622 Config description:
665 12:11:36.474146 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 12:11:36.481141 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 12:11:36.487406 SELPH_MODE 0: By rank 1: By Phase
668 12:11:36.490714 ==============================================================
669 12:11:36.493949 GAT_TRACK_EN = 1
670 12:11:36.497114 RX_GATING_MODE = 2
671 12:11:36.500425 RX_GATING_TRACK_MODE = 2
672 12:11:36.504315 SELPH_MODE = 1
673 12:11:36.507439 PICG_EARLY_EN = 1
674 12:11:36.510661 VALID_LAT_VALUE = 1
675 12:11:36.513889 ==============================================================
676 12:11:36.517360 Enter into Gating configuration >>>>
677 12:11:36.520386 Exit from Gating configuration <<<<
678 12:11:36.524171 Enter into DVFS_PRE_config >>>>>
679 12:11:36.536950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 12:11:36.540245 Exit from DVFS_PRE_config <<<<<
681 12:11:36.543856 Enter into PICG configuration >>>>
682 12:11:36.546950 Exit from PICG configuration <<<<
683 12:11:36.547046 [RX_INPUT] configuration >>>>>
684 12:11:36.550535 [RX_INPUT] configuration <<<<<
685 12:11:36.556964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 12:11:36.560764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 12:11:36.567658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 12:11:36.575151 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 12:11:36.579038 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 12:11:36.586330 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 12:11:36.589389 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 12:11:36.593170 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 12:11:36.599713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 12:11:36.602963 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 12:11:36.606330 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 12:11:36.610174 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:11:36.613415 ===================================
698 12:11:36.617426 LPDDR4 DRAM CONFIGURATION
699 12:11:36.620699 ===================================
700 12:11:36.620782 EX_ROW_EN[0] = 0x0
701 12:11:36.624574 EX_ROW_EN[1] = 0x0
702 12:11:36.624682 LP4Y_EN = 0x0
703 12:11:36.628377 WORK_FSP = 0x0
704 12:11:36.628509 WL = 0x2
705 12:11:36.632228 RL = 0x2
706 12:11:36.632369 BL = 0x2
707 12:11:36.635470 RPST = 0x0
708 12:11:36.635595 RD_PRE = 0x0
709 12:11:36.639317 WR_PRE = 0x1
710 12:11:36.639472 WR_PST = 0x0
711 12:11:36.643210 DBI_WR = 0x0
712 12:11:36.643309 DBI_RD = 0x0
713 12:11:36.647100 OTF = 0x1
714 12:11:36.647212 ===================================
715 12:11:36.650256 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 12:11:36.657762 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 12:11:36.661620 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 12:11:36.665557 ===================================
719 12:11:36.665641 LPDDR4 DRAM CONFIGURATION
720 12:11:36.668669 ===================================
721 12:11:36.672379 EX_ROW_EN[0] = 0x10
722 12:11:36.672486 EX_ROW_EN[1] = 0x0
723 12:11:36.676453 LP4Y_EN = 0x0
724 12:11:36.676572 WORK_FSP = 0x0
725 12:11:36.679648 WL = 0x2
726 12:11:36.679732 RL = 0x2
727 12:11:36.683579 BL = 0x2
728 12:11:36.683656 RPST = 0x0
729 12:11:36.687445 RD_PRE = 0x0
730 12:11:36.687525 WR_PRE = 0x1
731 12:11:36.691311 WR_PST = 0x0
732 12:11:36.691457 DBI_WR = 0x0
733 12:11:36.694431 DBI_RD = 0x0
734 12:11:36.694506 OTF = 0x1
735 12:11:36.698272 ===================================
736 12:11:36.705375 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 12:11:36.709140 nWR fixed to 40
738 12:11:36.709226 [ModeRegInit_LP4] CH0 RK0
739 12:11:36.713035 [ModeRegInit_LP4] CH0 RK1
740 12:11:36.716227 [ModeRegInit_LP4] CH1 RK0
741 12:11:36.716304 [ModeRegInit_LP4] CH1 RK1
742 12:11:36.719574 match AC timing 13
743 12:11:36.722753 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 12:11:36.726005 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 12:11:36.732897 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 12:11:36.736496 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 12:11:36.739772 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 12:11:36.743023 [EMI DOE] emi_dcm 0
749 12:11:36.746351 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 12:11:36.746444 ==
751 12:11:36.749544 Dram Type= 6, Freq= 0, CH_0, rank 0
752 12:11:36.756344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 12:11:36.756455 ==
754 12:11:36.759493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 12:11:36.766092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 12:11:36.775009 [CA 0] Center 37 (6~68) winsize 63
757 12:11:36.778812 [CA 1] Center 36 (6~67) winsize 62
758 12:11:36.782030 [CA 2] Center 34 (4~65) winsize 62
759 12:11:36.785147 [CA 3] Center 34 (4~65) winsize 62
760 12:11:36.788473 [CA 4] Center 33 (3~64) winsize 62
761 12:11:36.792333 [CA 5] Center 33 (3~64) winsize 62
762 12:11:36.792418
763 12:11:36.795692 [CmdBusTrainingLP45] Vref(ca) range 1: 32
764 12:11:36.795778
765 12:11:36.798877 [CATrainingPosCal] consider 1 rank data
766 12:11:36.802110 u2DelayCellTimex100 = 270/100 ps
767 12:11:36.805834 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
768 12:11:36.809090 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
769 12:11:36.812411 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 12:11:36.818778 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 12:11:36.822060 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 12:11:36.825840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 12:11:36.825924
774 12:11:36.829028 CA PerBit enable=1, Macro0, CA PI delay=33
775 12:11:36.829105
776 12:11:36.832159 [CBTSetCACLKResult] CA Dly = 33
777 12:11:36.832245 CS Dly: 7 (0~38)
778 12:11:36.832310 ==
779 12:11:36.835210 Dram Type= 6, Freq= 0, CH_0, rank 1
780 12:11:36.842364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 12:11:36.842450 ==
782 12:11:36.845608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 12:11:36.852012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 12:11:36.861328 [CA 0] Center 37 (6~68) winsize 63
785 12:11:36.864438 [CA 1] Center 37 (7~68) winsize 62
786 12:11:36.868086 [CA 2] Center 34 (4~65) winsize 62
787 12:11:36.871251 [CA 3] Center 34 (4~65) winsize 62
788 12:11:36.874410 [CA 4] Center 33 (3~64) winsize 62
789 12:11:36.878175 [CA 5] Center 33 (3~64) winsize 62
790 12:11:36.878258
791 12:11:36.881275 [CmdBusTrainingLP45] Vref(ca) range 1: 30
792 12:11:36.881358
793 12:11:36.884501 [CATrainingPosCal] consider 2 rank data
794 12:11:36.887815 u2DelayCellTimex100 = 270/100 ps
795 12:11:36.891076 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
796 12:11:36.897933 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
797 12:11:36.901057 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 12:11:36.904176 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 12:11:36.907998 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 12:11:36.911716 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 12:11:36.911799
802 12:11:36.915643 CA PerBit enable=1, Macro0, CA PI delay=33
803 12:11:36.915752
804 12:11:36.918719 [CBTSetCACLKResult] CA Dly = 33
805 12:11:36.918799 CS Dly: 7 (0~38)
806 12:11:36.918882
807 12:11:36.922016 ----->DramcWriteLeveling(PI) begin...
808 12:11:36.922107 ==
809 12:11:36.925972 Dram Type= 6, Freq= 0, CH_0, rank 0
810 12:11:36.929135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:11:36.929213 ==
812 12:11:36.933080 Write leveling (Byte 0): 33 => 33
813 12:11:36.936378 Write leveling (Byte 1): 30 => 30
814 12:11:36.939433 DramcWriteLeveling(PI) end<-----
815 12:11:36.939514
816 12:11:36.939596 ==
817 12:11:36.943109 Dram Type= 6, Freq= 0, CH_0, rank 0
818 12:11:36.946428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 12:11:36.949589 ==
820 12:11:36.949706 [Gating] SW mode calibration
821 12:11:36.959630 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 12:11:36.962714 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 12:11:36.966105 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 12:11:36.973038 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 12:11:36.976381 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 12:11:36.979425 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:11:36.985934 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:11:36.989800 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:11:36.992464 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:11:36.999765 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:11:37.003030 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:11:37.006231 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:11:37.012491 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 12:11:37.015728 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 12:11:37.019103 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 12:11:37.026076 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 12:11:37.029332 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 12:11:37.032550 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:11:37.035751 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:11:37.042804 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
841 12:11:37.045966 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
842 12:11:37.049271 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:11:37.056230 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:11:37.059324 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:11:37.062459 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:11:37.069392 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:11:37.072396 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:11:37.075567 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:11:37.082593 0 9 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
850 12:11:37.085719 0 9 12 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
851 12:11:37.088820 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 12:11:37.095824 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 12:11:37.099021 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 12:11:37.102189 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 12:11:37.108705 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 12:11:37.111759 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
857 12:11:37.115439 0 10 8 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
858 12:11:37.121959 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
859 12:11:37.125796 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:11:37.128991 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:11:37.135247 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:11:37.138533 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:11:37.142378 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:11:37.148701 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:11:37.151777 0 11 8 | B1->B0 | 2727 3939 | 0 0 | (0 0) (1 1)
866 12:11:37.155714 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
867 12:11:37.162041 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 12:11:37.165249 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 12:11:37.168359 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 12:11:37.175281 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 12:11:37.178370 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 12:11:37.181666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 12:11:37.188663 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 12:11:37.191846 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 12:11:37.195197 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 12:11:37.201514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 12:11:37.204736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 12:11:37.207863 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 12:11:37.214910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 12:11:37.218732 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 12:11:37.221740 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 12:11:37.225758 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 12:11:37.229135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 12:11:37.236292 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 12:11:37.240239 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 12:11:37.243508 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 12:11:37.247345 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 12:11:37.254779 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 12:11:37.258490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
890 12:11:37.258574 Total UI for P1: 0, mck2ui 16
891 12:11:37.264986 best dqsien dly found for B0: ( 0, 14, 6)
892 12:11:37.268883 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 12:11:37.272706 Total UI for P1: 0, mck2ui 16
894 12:11:37.276345 best dqsien dly found for B1: ( 0, 14, 8)
895 12:11:37.279446 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 12:11:37.283188 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 12:11:37.283271
898 12:11:37.286389 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 12:11:37.289796 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 12:11:37.293021 [Gating] SW calibration Done
901 12:11:37.293104 ==
902 12:11:37.296847 Dram Type= 6, Freq= 0, CH_0, rank 0
903 12:11:37.300037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 12:11:37.300121 ==
905 12:11:37.300188 RX Vref Scan: 0
906 12:11:37.300249
907 12:11:37.303378 RX Vref 0 -> 0, step: 1
908 12:11:37.303461
909 12:11:37.306601 RX Delay -130 -> 252, step: 16
910 12:11:37.309746 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 12:11:37.313042 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 12:11:37.320112 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 12:11:37.323259 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 12:11:37.326390 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 12:11:37.330291 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 12:11:37.334215 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
917 12:11:37.338022 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
918 12:11:37.341307 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 12:11:37.345198 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
920 12:11:37.349122 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 12:11:37.352877 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 12:11:37.359896 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
923 12:11:37.363039 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
924 12:11:37.366226 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 12:11:37.369449 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
926 12:11:37.369530 ==
927 12:11:37.373249 Dram Type= 6, Freq= 0, CH_0, rank 0
928 12:11:37.379558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 12:11:37.379642 ==
930 12:11:37.379708 DQS Delay:
931 12:11:37.379774 DQS0 = 0, DQS1 = 0
932 12:11:37.382738 DQM Delay:
933 12:11:37.382839 DQM0 = 85, DQM1 = 73
934 12:11:37.386430 DQ Delay:
935 12:11:37.389801 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 12:11:37.389921 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
937 12:11:37.392971 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
938 12:11:37.399876 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
939 12:11:37.399974
940 12:11:37.400069
941 12:11:37.400131 ==
942 12:11:37.403038 Dram Type= 6, Freq= 0, CH_0, rank 0
943 12:11:37.406183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 12:11:37.406266 ==
945 12:11:37.406332
946 12:11:37.406392
947 12:11:37.409358 TX Vref Scan disable
948 12:11:37.409486 == TX Byte 0 ==
949 12:11:37.416536 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
950 12:11:37.419702 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
951 12:11:37.419778 == TX Byte 1 ==
952 12:11:37.426144 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
953 12:11:37.429339 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
954 12:11:37.429416 ==
955 12:11:37.433102 Dram Type= 6, Freq= 0, CH_0, rank 0
956 12:11:37.436340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 12:11:37.436419 ==
958 12:11:37.450040 TX Vref=22, minBit 3, minWin=27, winSum=440
959 12:11:37.453431 TX Vref=24, minBit 4, minWin=27, winSum=443
960 12:11:37.456680 TX Vref=26, minBit 8, minWin=27, winSum=448
961 12:11:37.460352 TX Vref=28, minBit 8, minWin=27, winSum=449
962 12:11:37.463489 TX Vref=30, minBit 11, minWin=26, winSum=447
963 12:11:37.469888 TX Vref=32, minBit 8, minWin=27, winSum=445
964 12:11:37.473661 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 28
965 12:11:37.473768
966 12:11:37.476890 Final TX Range 1 Vref 28
967 12:11:37.476963
968 12:11:37.477025 ==
969 12:11:37.480006 Dram Type= 6, Freq= 0, CH_0, rank 0
970 12:11:37.483314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 12:11:37.483443 ==
972 12:11:37.486365
973 12:11:37.486458
974 12:11:37.486525 TX Vref Scan disable
975 12:11:37.490083 == TX Byte 0 ==
976 12:11:37.493346 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 12:11:37.499832 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 12:11:37.499957 == TX Byte 1 ==
979 12:11:37.503386 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 12:11:37.509695 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 12:11:37.509792
982 12:11:37.509861 [DATLAT]
983 12:11:37.509924 Freq=800, CH0 RK0
984 12:11:37.509988
985 12:11:37.513626 DATLAT Default: 0xa
986 12:11:37.513713 0, 0xFFFF, sum = 0
987 12:11:37.516883 1, 0xFFFF, sum = 0
988 12:11:37.516976 2, 0xFFFF, sum = 0
989 12:11:37.519876 3, 0xFFFF, sum = 0
990 12:11:37.523146 4, 0xFFFF, sum = 0
991 12:11:37.523240 5, 0xFFFF, sum = 0
992 12:11:37.526414 6, 0xFFFF, sum = 0
993 12:11:37.526522 7, 0xFFFF, sum = 0
994 12:11:37.529695 8, 0xFFFF, sum = 0
995 12:11:37.529802 9, 0x0, sum = 1
996 12:11:37.533029 10, 0x0, sum = 2
997 12:11:37.533106 11, 0x0, sum = 3
998 12:11:37.533173 12, 0x0, sum = 4
999 12:11:37.536759 best_step = 10
1000 12:11:37.536853
1001 12:11:37.536949 ==
1002 12:11:37.540041 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 12:11:37.543282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 12:11:37.543364 ==
1005 12:11:37.546468 RX Vref Scan: 1
1006 12:11:37.546543
1007 12:11:37.546607 Set Vref Range= 32 -> 127
1008 12:11:37.549705
1009 12:11:37.549791 RX Vref 32 -> 127, step: 1
1010 12:11:37.549859
1011 12:11:37.553011 RX Delay -111 -> 252, step: 8
1012 12:11:37.553096
1013 12:11:37.556301 Set Vref, RX VrefLevel [Byte0]: 32
1014 12:11:37.559551 [Byte1]: 32
1015 12:11:37.563335
1016 12:11:37.563430 Set Vref, RX VrefLevel [Byte0]: 33
1017 12:11:37.566485 [Byte1]: 33
1018 12:11:37.570744
1019 12:11:37.570855 Set Vref, RX VrefLevel [Byte0]: 34
1020 12:11:37.573929 [Byte1]: 34
1021 12:11:37.578406
1022 12:11:37.578511 Set Vref, RX VrefLevel [Byte0]: 35
1023 12:11:37.581578 [Byte1]: 35
1024 12:11:37.586026
1025 12:11:37.586116 Set Vref, RX VrefLevel [Byte0]: 36
1026 12:11:37.589296 [Byte1]: 36
1027 12:11:37.594165
1028 12:11:37.594251 Set Vref, RX VrefLevel [Byte0]: 37
1029 12:11:37.597400 [Byte1]: 37
1030 12:11:37.601278
1031 12:11:37.601360 Set Vref, RX VrefLevel [Byte0]: 38
1032 12:11:37.604578 [Byte1]: 38
1033 12:11:37.608943
1034 12:11:37.612160 Set Vref, RX VrefLevel [Byte0]: 39
1035 12:11:37.612239 [Byte1]: 39
1036 12:11:37.616753
1037 12:11:37.616834 Set Vref, RX VrefLevel [Byte0]: 40
1038 12:11:37.619976 [Byte1]: 40
1039 12:11:37.624512
1040 12:11:37.624611 Set Vref, RX VrefLevel [Byte0]: 41
1041 12:11:37.627680 [Byte1]: 41
1042 12:11:37.632275
1043 12:11:37.632353 Set Vref, RX VrefLevel [Byte0]: 42
1044 12:11:37.635600 [Byte1]: 42
1045 12:11:37.640154
1046 12:11:37.640239 Set Vref, RX VrefLevel [Byte0]: 43
1047 12:11:37.643450 [Byte1]: 43
1048 12:11:37.647337
1049 12:11:37.647421 Set Vref, RX VrefLevel [Byte0]: 44
1050 12:11:37.651366 [Byte1]: 44
1051 12:11:37.655235
1052 12:11:37.655318 Set Vref, RX VrefLevel [Byte0]: 45
1053 12:11:37.658456 [Byte1]: 45
1054 12:11:37.663064
1055 12:11:37.663150 Set Vref, RX VrefLevel [Byte0]: 46
1056 12:11:37.666336 [Byte1]: 46
1057 12:11:37.670040
1058 12:11:37.670118 Set Vref, RX VrefLevel [Byte0]: 47
1059 12:11:37.673675 [Byte1]: 47
1060 12:11:37.678250
1061 12:11:37.678327 Set Vref, RX VrefLevel [Byte0]: 48
1062 12:11:37.681461 [Byte1]: 48
1063 12:11:37.685386
1064 12:11:37.685459 Set Vref, RX VrefLevel [Byte0]: 49
1065 12:11:37.688451 [Byte1]: 49
1066 12:11:37.693556
1067 12:11:37.693643 Set Vref, RX VrefLevel [Byte0]: 50
1068 12:11:37.697255 [Byte1]: 50
1069 12:11:37.701045
1070 12:11:37.701129 Set Vref, RX VrefLevel [Byte0]: 51
1071 12:11:37.704295 [Byte1]: 51
1072 12:11:37.708773
1073 12:11:37.708857 Set Vref, RX VrefLevel [Byte0]: 52
1074 12:11:37.711907 [Byte1]: 52
1075 12:11:37.716357
1076 12:11:37.716464 Set Vref, RX VrefLevel [Byte0]: 53
1077 12:11:37.719586 [Byte1]: 53
1078 12:11:37.723442
1079 12:11:37.723548 Set Vref, RX VrefLevel [Byte0]: 54
1080 12:11:37.727195 [Byte1]: 54
1081 12:11:37.731829
1082 12:11:37.731901 Set Vref, RX VrefLevel [Byte0]: 55
1083 12:11:37.735069 [Byte1]: 55
1084 12:11:37.739109
1085 12:11:37.739219 Set Vref, RX VrefLevel [Byte0]: 56
1086 12:11:37.742290 [Byte1]: 56
1087 12:11:37.746818
1088 12:11:37.746919 Set Vref, RX VrefLevel [Byte0]: 57
1089 12:11:37.750064 [Byte1]: 57
1090 12:11:37.754541
1091 12:11:37.754640 Set Vref, RX VrefLevel [Byte0]: 58
1092 12:11:37.757755 [Byte1]: 58
1093 12:11:37.762445
1094 12:11:37.762553 Set Vref, RX VrefLevel [Byte0]: 59
1095 12:11:37.765671 [Byte1]: 59
1096 12:11:37.769487
1097 12:11:37.769562 Set Vref, RX VrefLevel [Byte0]: 60
1098 12:11:37.773358 [Byte1]: 60
1099 12:11:37.777647
1100 12:11:37.777738 Set Vref, RX VrefLevel [Byte0]: 61
1101 12:11:37.780941 [Byte1]: 61
1102 12:11:37.784780
1103 12:11:37.784865 Set Vref, RX VrefLevel [Byte0]: 62
1104 12:11:37.788523 [Byte1]: 62
1105 12:11:37.792304
1106 12:11:37.792410 Set Vref, RX VrefLevel [Byte0]: 63
1107 12:11:37.796043 [Byte1]: 63
1108 12:11:37.800366
1109 12:11:37.800469 Set Vref, RX VrefLevel [Byte0]: 64
1110 12:11:37.803400 [Byte1]: 64
1111 12:11:37.807962
1112 12:11:37.808059 Set Vref, RX VrefLevel [Byte0]: 65
1113 12:11:37.811143 [Byte1]: 65
1114 12:11:37.815749
1115 12:11:37.815821 Set Vref, RX VrefLevel [Byte0]: 66
1116 12:11:37.818878 [Byte1]: 66
1117 12:11:37.823383
1118 12:11:37.823494 Set Vref, RX VrefLevel [Byte0]: 67
1119 12:11:37.826654 [Byte1]: 67
1120 12:11:37.830554
1121 12:11:37.830625 Set Vref, RX VrefLevel [Byte0]: 68
1122 12:11:37.834265 [Byte1]: 68
1123 12:11:37.838165
1124 12:11:37.838281 Set Vref, RX VrefLevel [Byte0]: 69
1125 12:11:37.841600 [Byte1]: 69
1126 12:11:37.846135
1127 12:11:37.846216 Set Vref, RX VrefLevel [Byte0]: 70
1128 12:11:37.849388 [Byte1]: 70
1129 12:11:37.854061
1130 12:11:37.854161 Set Vref, RX VrefLevel [Byte0]: 71
1131 12:11:37.857160 [Byte1]: 71
1132 12:11:37.861137
1133 12:11:37.861219 Set Vref, RX VrefLevel [Byte0]: 72
1134 12:11:37.864431 [Byte1]: 72
1135 12:11:37.869022
1136 12:11:37.869104 Set Vref, RX VrefLevel [Byte0]: 73
1137 12:11:37.872216 [Byte1]: 73
1138 12:11:37.876646
1139 12:11:37.876728 Set Vref, RX VrefLevel [Byte0]: 74
1140 12:11:37.879911 [Byte1]: 74
1141 12:11:37.884367
1142 12:11:37.884451 Set Vref, RX VrefLevel [Byte0]: 75
1143 12:11:37.887465 [Byte1]: 75
1144 12:11:37.891238
1145 12:11:37.895089 Set Vref, RX VrefLevel [Byte0]: 76
1146 12:11:37.895171 [Byte1]: 76
1147 12:11:37.899523
1148 12:11:37.899602 Set Vref, RX VrefLevel [Byte0]: 77
1149 12:11:37.903320 [Byte1]: 77
1150 12:11:37.907552
1151 12:11:37.907643 Set Vref, RX VrefLevel [Byte0]: 78
1152 12:11:37.910788 [Byte1]: 78
1153 12:11:37.914664
1154 12:11:37.914741 Set Vref, RX VrefLevel [Byte0]: 79
1155 12:11:37.918624 [Byte1]: 79
1156 12:11:37.922937
1157 12:11:37.923051 Set Vref, RX VrefLevel [Byte0]: 80
1158 12:11:37.926163 [Byte1]: 80
1159 12:11:37.930144
1160 12:11:37.930223 Set Vref, RX VrefLevel [Byte0]: 81
1161 12:11:37.933456 [Byte1]: 81
1162 12:11:37.937419
1163 12:11:37.937494 Set Vref, RX VrefLevel [Byte0]: 82
1164 12:11:37.941330 [Byte1]: 82
1165 12:11:37.945908
1166 12:11:37.945989 Set Vref, RX VrefLevel [Byte0]: 83
1167 12:11:37.949057 [Byte1]: 83
1168 12:11:37.953012
1169 12:11:37.953093 Final RX Vref Byte 0 = 61 to rank0
1170 12:11:37.956852 Final RX Vref Byte 1 = 49 to rank0
1171 12:11:37.960264 Final RX Vref Byte 0 = 61 to rank1
1172 12:11:37.964284 Final RX Vref Byte 1 = 49 to rank1==
1173 12:11:37.968190 Dram Type= 6, Freq= 0, CH_0, rank 0
1174 12:11:37.971387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 12:11:37.971472 ==
1176 12:11:37.971537 DQS Delay:
1177 12:11:37.975270 DQS0 = 0, DQS1 = 0
1178 12:11:37.975352 DQM Delay:
1179 12:11:37.978406 DQM0 = 87, DQM1 = 76
1180 12:11:37.978487 DQ Delay:
1181 12:11:37.982341 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1182 12:11:37.985299 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1183 12:11:37.989040 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1184 12:11:37.992810 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1185 12:11:37.992891
1186 12:11:37.992955
1187 12:11:38.000436 [DQSOSCAuto] RK0, (LSB)MR18= 0x4224, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1188 12:11:38.004249 CH0 RK0: MR19=606, MR18=4224
1189 12:11:38.007863 CH0_RK0: MR19=0x606, MR18=0x4224, DQSOSC=393, MR23=63, INC=95, DEC=63
1190 12:11:38.007945
1191 12:11:38.011717 ----->DramcWriteLeveling(PI) begin...
1192 12:11:38.011798 ==
1193 12:11:38.014807 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 12:11:38.018786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 12:11:38.018907 ==
1196 12:11:38.021919 Write leveling (Byte 0): 34 => 34
1197 12:11:38.066064 Write leveling (Byte 1): 29 => 29
1198 12:11:38.066180 DramcWriteLeveling(PI) end<-----
1199 12:11:38.066281
1200 12:11:38.066342 ==
1201 12:11:38.066401 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 12:11:38.066642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 12:11:38.066709 ==
1204 12:11:38.066767 [Gating] SW mode calibration
1205 12:11:38.066824 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1206 12:11:38.066880 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1207 12:11:38.066935 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1208 12:11:38.066991 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1209 12:11:38.067389 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1210 12:11:38.110236 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1211 12:11:38.110608 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:11:38.110712 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:11:38.110774 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:11:38.110832 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:11:38.110901 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:11:38.110960 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:11:38.111049 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:11:38.111582 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:11:38.111872 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:11:38.144556 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:11:38.144670 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:11:38.144738 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:11:38.145021 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:11:38.145109 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:11:38.145181 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:11:38.145272 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:11:38.145374 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:11:38.148453 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:11:38.151624 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:11:38.158689 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:11:38.161774 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:11:38.165066 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:11:38.171751 0 9 8 | B1->B0 | 2424 3333 | 0 1 | (1 1) (1 1)
1234 12:11:38.174968 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1235 12:11:38.178203 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 12:11:38.185288 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 12:11:38.188416 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 12:11:38.191663 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 12:11:38.198009 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 12:11:38.201763 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1241 12:11:38.204987 0 10 8 | B1->B0 | 3030 2727 | 0 0 | (0 0) (0 0)
1242 12:11:38.211350 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1243 12:11:38.214548 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:11:38.218078 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:11:38.224406 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:11:38.227703 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:11:38.231593 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:11:38.237935 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1249 12:11:38.241164 0 11 8 | B1->B0 | 3131 3a3a | 0 1 | (0 0) (0 0)
1250 12:11:38.245008 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
1251 12:11:38.247931 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 12:11:38.254846 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:11:38.258208 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 12:11:38.261405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 12:11:38.267704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 12:11:38.271052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 12:11:38.274850 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1258 12:11:38.281276 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:11:38.284606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:11:38.287855 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:11:38.294881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:11:38.297998 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:11:38.301007 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:11:38.307985 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:11:38.311100 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:11:38.314201 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:11:38.321172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:11:38.324316 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:11:38.327833 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:11:38.334266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:11:38.337984 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:11:38.341102 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:11:38.348003 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1274 12:11:38.348109 Total UI for P1: 0, mck2ui 16
1275 12:11:38.354235 best dqsien dly found for B0: ( 0, 14, 6)
1276 12:11:38.357577 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 12:11:38.360846 Total UI for P1: 0, mck2ui 16
1278 12:11:38.364593 best dqsien dly found for B1: ( 0, 14, 8)
1279 12:11:38.367724 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1280 12:11:38.370933 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1281 12:11:38.371037
1282 12:11:38.374146 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1283 12:11:38.377403 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1284 12:11:38.380774 [Gating] SW calibration Done
1285 12:11:38.380850 ==
1286 12:11:38.383974 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:11:38.387285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:11:38.387382 ==
1289 12:11:38.390553 RX Vref Scan: 0
1290 12:11:38.390649
1291 12:11:38.393792 RX Vref 0 -> 0, step: 1
1292 12:11:38.393890
1293 12:11:38.393979 RX Delay -130 -> 252, step: 16
1294 12:11:38.400709 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1295 12:11:38.403773 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1296 12:11:38.406977 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1297 12:11:38.410854 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1298 12:11:38.413998 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1299 12:11:38.420380 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1300 12:11:38.423546 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1301 12:11:38.427308 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1302 12:11:38.430367 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1303 12:11:38.433524 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1304 12:11:38.440143 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1305 12:11:38.443922 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1306 12:11:38.447171 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1307 12:11:38.450429 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1308 12:11:38.457330 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1309 12:11:38.460016 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1310 12:11:38.460099 ==
1311 12:11:38.463908 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 12:11:38.467081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 12:11:38.467164 ==
1314 12:11:38.470358 DQS Delay:
1315 12:11:38.470441 DQS0 = 0, DQS1 = 0
1316 12:11:38.470506 DQM Delay:
1317 12:11:38.473534 DQM0 = 85, DQM1 = 78
1318 12:11:38.473616 DQ Delay:
1319 12:11:38.476758 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1320 12:11:38.479933 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1321 12:11:38.483171 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1322 12:11:38.486998 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1323 12:11:38.487080
1324 12:11:38.487146
1325 12:11:38.487210 ==
1326 12:11:38.490103 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:11:38.496522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:11:38.496641 ==
1329 12:11:38.496707
1330 12:11:38.496767
1331 12:11:38.496831 TX Vref Scan disable
1332 12:11:38.500248 == TX Byte 0 ==
1333 12:11:38.503397 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1334 12:11:38.510329 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1335 12:11:38.510408 == TX Byte 1 ==
1336 12:11:38.513500 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1337 12:11:38.519933 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1338 12:11:38.520015 ==
1339 12:11:38.523253 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 12:11:38.526355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 12:11:38.526436 ==
1342 12:11:38.539493 TX Vref=22, minBit 1, minWin=27, winSum=443
1343 12:11:38.542744 TX Vref=24, minBit 3, minWin=27, winSum=443
1344 12:11:38.546518 TX Vref=26, minBit 0, minWin=28, winSum=449
1345 12:11:38.549847 TX Vref=28, minBit 9, minWin=27, winSum=448
1346 12:11:38.552739 TX Vref=30, minBit 9, minWin=27, winSum=447
1347 12:11:38.559565 TX Vref=32, minBit 0, minWin=27, winSum=444
1348 12:11:38.562606 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 26
1349 12:11:38.562688
1350 12:11:38.565890 Final TX Range 1 Vref 26
1351 12:11:38.565971
1352 12:11:38.566034 ==
1353 12:11:38.569337 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 12:11:38.572519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 12:11:38.575736 ==
1356 12:11:38.575816
1357 12:11:38.575879
1358 12:11:38.575937 TX Vref Scan disable
1359 12:11:38.579493 == TX Byte 0 ==
1360 12:11:38.583372 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1361 12:11:38.586613 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1362 12:11:38.589745 == TX Byte 1 ==
1363 12:11:38.593075 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1364 12:11:38.599600 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1365 12:11:38.599682
1366 12:11:38.599744 [DATLAT]
1367 12:11:38.599803 Freq=800, CH0 RK1
1368 12:11:38.599868
1369 12:11:38.602908 DATLAT Default: 0xa
1370 12:11:38.603004 0, 0xFFFF, sum = 0
1371 12:11:38.606073 1, 0xFFFF, sum = 0
1372 12:11:38.606146 2, 0xFFFF, sum = 0
1373 12:11:38.609254 3, 0xFFFF, sum = 0
1374 12:11:38.613042 4, 0xFFFF, sum = 0
1375 12:11:38.613145 5, 0xFFFF, sum = 0
1376 12:11:38.616298 6, 0xFFFF, sum = 0
1377 12:11:38.616380 7, 0xFFFF, sum = 0
1378 12:11:38.619413 8, 0xFFFF, sum = 0
1379 12:11:38.619495 9, 0x0, sum = 1
1380 12:11:38.622584 10, 0x0, sum = 2
1381 12:11:38.622665 11, 0x0, sum = 3
1382 12:11:38.622730 12, 0x0, sum = 4
1383 12:11:38.625822 best_step = 10
1384 12:11:38.625924
1385 12:11:38.625989 ==
1386 12:11:38.629632 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 12:11:38.632688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 12:11:38.632769 ==
1389 12:11:38.635829 RX Vref Scan: 0
1390 12:11:38.635909
1391 12:11:38.635973 RX Vref 0 -> 0, step: 1
1392 12:11:38.639346
1393 12:11:38.639429 RX Delay -95 -> 252, step: 8
1394 12:11:38.646460 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1395 12:11:38.649735 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1396 12:11:38.652989 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1397 12:11:38.656060 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1398 12:11:38.659701 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1399 12:11:38.665952 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1400 12:11:38.669792 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1401 12:11:38.673070 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1402 12:11:38.676335 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1403 12:11:38.679536 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1404 12:11:38.686408 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1405 12:11:38.689705 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1406 12:11:38.692983 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1407 12:11:38.696151 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1408 12:11:38.702740 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1409 12:11:38.705953 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1410 12:11:38.706033 ==
1411 12:11:38.709018 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 12:11:38.712738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 12:11:38.712820 ==
1414 12:11:38.715875 DQS Delay:
1415 12:11:38.715953 DQS0 = 0, DQS1 = 0
1416 12:11:38.716015 DQM Delay:
1417 12:11:38.719114 DQM0 = 85, DQM1 = 77
1418 12:11:38.719209 DQ Delay:
1419 12:11:38.722221 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1420 12:11:38.725478 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1421 12:11:38.728727 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1422 12:11:38.732164 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1423 12:11:38.732237
1424 12:11:38.732306
1425 12:11:38.741965 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1426 12:11:38.742049 CH0 RK1: MR19=606, MR18=3E04
1427 12:11:38.748762 CH0_RK1: MR19=0x606, MR18=0x3E04, DQSOSC=394, MR23=63, INC=95, DEC=63
1428 12:11:38.751908 [RxdqsGatingPostProcess] freq 800
1429 12:11:38.758935 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 12:11:38.761927 Pre-setting of DQS Precalculation
1431 12:11:38.765594 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1432 12:11:38.765674 ==
1433 12:11:38.768675 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 12:11:38.775762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 12:11:38.775843 ==
1436 12:11:38.778968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 12:11:38.785392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 12:11:38.794430 [CA 0] Center 36 (6~67) winsize 62
1439 12:11:38.797708 [CA 1] Center 36 (6~67) winsize 62
1440 12:11:38.800943 [CA 2] Center 34 (4~65) winsize 62
1441 12:11:38.804187 [CA 3] Center 34 (3~65) winsize 63
1442 12:11:38.808062 [CA 4] Center 34 (4~65) winsize 62
1443 12:11:38.811218 [CA 5] Center 34 (3~65) winsize 63
1444 12:11:38.811295
1445 12:11:38.814330 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1446 12:11:38.814408
1447 12:11:38.817378 [CATrainingPosCal] consider 1 rank data
1448 12:11:38.821137 u2DelayCellTimex100 = 270/100 ps
1449 12:11:38.824285 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 12:11:38.830740 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 12:11:38.834053 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 12:11:38.837795 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1453 12:11:38.841096 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 12:11:38.844147 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1455 12:11:38.844230
1456 12:11:38.847234 CA PerBit enable=1, Macro0, CA PI delay=34
1457 12:11:38.847317
1458 12:11:38.850811 [CBTSetCACLKResult] CA Dly = 34
1459 12:11:38.850895 CS Dly: 5 (0~36)
1460 12:11:38.854064 ==
1461 12:11:38.857147 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 12:11:38.860469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 12:11:38.860607 ==
1464 12:11:38.864253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 12:11:38.870405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 12:11:38.880472 [CA 0] Center 36 (6~67) winsize 62
1467 12:11:38.883879 [CA 1] Center 36 (6~67) winsize 62
1468 12:11:38.887132 [CA 2] Center 34 (4~65) winsize 62
1469 12:11:38.890926 [CA 3] Center 34 (4~65) winsize 62
1470 12:11:38.894070 [CA 4] Center 34 (4~65) winsize 62
1471 12:11:38.897445 [CA 5] Center 34 (3~65) winsize 63
1472 12:11:38.897528
1473 12:11:38.900678 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1474 12:11:38.900761
1475 12:11:38.903931 [CATrainingPosCal] consider 2 rank data
1476 12:11:38.907268 u2DelayCellTimex100 = 270/100 ps
1477 12:11:38.910616 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 12:11:38.913836 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1479 12:11:38.920728 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 12:11:38.923806 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 12:11:38.927029 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 12:11:38.930718 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1483 12:11:38.930800
1484 12:11:38.934161 CA PerBit enable=1, Macro0, CA PI delay=34
1485 12:11:38.934244
1486 12:11:38.937359 [CBTSetCACLKResult] CA Dly = 34
1487 12:11:38.937442 CS Dly: 6 (0~38)
1488 12:11:38.940479
1489 12:11:38.943840 ----->DramcWriteLeveling(PI) begin...
1490 12:11:38.943925 ==
1491 12:11:38.946798 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 12:11:38.950549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 12:11:38.950650 ==
1494 12:11:38.953525 Write leveling (Byte 0): 29 => 29
1495 12:11:38.957348 Write leveling (Byte 1): 30 => 30
1496 12:11:38.960495 DramcWriteLeveling(PI) end<-----
1497 12:11:38.960618
1498 12:11:38.960684 ==
1499 12:11:38.963922 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 12:11:38.967048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 12:11:38.967157 ==
1502 12:11:38.970273 [Gating] SW mode calibration
1503 12:11:38.977096 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 12:11:38.983455 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 12:11:38.986754 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1506 12:11:38.989959 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1507 12:11:38.996933 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:11:39.000151 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:11:39.003420 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:11:39.010441 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:11:39.013737 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:11:39.016942 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:11:39.020280 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:11:39.026608 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:11:39.030341 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:11:39.033577 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:11:39.040137 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:11:39.043289 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:11:39.046939 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:11:39.053360 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:11:39.056986 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:11:39.059969 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1523 12:11:39.066913 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1524 12:11:39.070090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:11:39.073247 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:11:39.080121 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:11:39.083263 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:11:39.086492 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:11:39.092993 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:11:39.096750 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1531 12:11:39.099999 0 9 8 | B1->B0 | 2c2c 3131 | 0 1 | (0 0) (1 1)
1532 12:11:39.106518 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 12:11:39.109752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 12:11:39.113021 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 12:11:39.119534 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:11:39.122773 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 12:11:39.126493 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 12:11:39.132660 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
1539 12:11:39.135930 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
1540 12:11:39.139053 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:11:39.146096 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:11:39.149348 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:11:39.152479 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:11:39.159288 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:11:39.162431 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:11:39.166063 0 11 4 | B1->B0 | 2a2a 2d2d | 0 0 | (0 0) (0 0)
1547 12:11:39.172347 0 11 8 | B1->B0 | 3a3a 4141 | 0 1 | (0 0) (0 0)
1548 12:11:39.175560 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 12:11:39.178705 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 12:11:39.185428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 12:11:39.188704 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:11:39.192460 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:11:39.198976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 12:11:39.202119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1555 12:11:39.205396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:11:39.212426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:11:39.215685 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:11:39.218963 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:11:39.225464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:11:39.228711 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:11:39.231801 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:11:39.238673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:11:39.241955 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:11:39.245353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:11:39.251832 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:11:39.254942 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:11:39.258160 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:11:39.264969 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:11:39.268064 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:11:39.271280 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:11:39.274981 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 12:11:39.278043 Total UI for P1: 0, mck2ui 16
1573 12:11:39.282321 best dqsien dly found for B0: ( 0, 14, 6)
1574 12:11:39.284821 Total UI for P1: 0, mck2ui 16
1575 12:11:39.288022 best dqsien dly found for B1: ( 0, 14, 6)
1576 12:11:39.291701 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1577 12:11:39.295099 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1578 12:11:39.295183
1579 12:11:39.301603 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1580 12:11:39.304727 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1581 12:11:39.308047 [Gating] SW calibration Done
1582 12:11:39.308131 ==
1583 12:11:39.311329 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 12:11:39.314508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 12:11:39.314596 ==
1586 12:11:39.314662 RX Vref Scan: 0
1587 12:11:39.314732
1588 12:11:39.318335 RX Vref 0 -> 0, step: 1
1589 12:11:39.318417
1590 12:11:39.321682 RX Delay -130 -> 252, step: 16
1591 12:11:39.324993 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1592 12:11:39.328195 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1593 12:11:39.334522 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1594 12:11:39.337720 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1595 12:11:39.341591 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1596 12:11:39.344727 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1597 12:11:39.347888 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1598 12:11:39.354442 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1599 12:11:39.357702 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1600 12:11:39.361473 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1601 12:11:39.364686 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1602 12:11:39.367690 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1603 12:11:39.374695 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1604 12:11:39.377851 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1605 12:11:39.380889 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1606 12:11:39.384097 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1607 12:11:39.384188 ==
1608 12:11:39.387868 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 12:11:39.394640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 12:11:39.394726 ==
1611 12:11:39.394792 DQS Delay:
1612 12:11:39.397769 DQS0 = 0, DQS1 = 0
1613 12:11:39.397851 DQM Delay:
1614 12:11:39.397918 DQM0 = 89, DQM1 = 78
1615 12:11:39.400988 DQ Delay:
1616 12:11:39.404235 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1617 12:11:39.407517 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1618 12:11:39.410704 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1619 12:11:39.413976 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1620 12:11:39.414059
1621 12:11:39.414126
1622 12:11:39.414187 ==
1623 12:11:39.417723 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 12:11:39.420927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 12:11:39.421011 ==
1626 12:11:39.421078
1627 12:11:39.421140
1628 12:11:39.424052 TX Vref Scan disable
1629 12:11:39.427333 == TX Byte 0 ==
1630 12:11:39.430505 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1631 12:11:39.433913 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1632 12:11:39.437757 == TX Byte 1 ==
1633 12:11:39.441049 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1634 12:11:39.444199 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1635 12:11:39.444314 ==
1636 12:11:39.447477 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 12:11:39.450589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 12:11:39.454296 ==
1639 12:11:39.465086 TX Vref=22, minBit 10, minWin=26, winSum=442
1640 12:11:39.468320 TX Vref=24, minBit 8, minWin=27, winSum=447
1641 12:11:39.472100 TX Vref=26, minBit 8, minWin=27, winSum=449
1642 12:11:39.475263 TX Vref=28, minBit 8, minWin=27, winSum=449
1643 12:11:39.478275 TX Vref=30, minBit 8, minWin=27, winSum=448
1644 12:11:39.485343 TX Vref=32, minBit 8, minWin=27, winSum=442
1645 12:11:39.488660 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 26
1646 12:11:39.488752
1647 12:11:39.491882 Final TX Range 1 Vref 26
1648 12:11:39.491964
1649 12:11:39.492030 ==
1650 12:11:39.495046 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 12:11:39.498094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 12:11:39.501282 ==
1653 12:11:39.501397
1654 12:11:39.501492
1655 12:11:39.501582 TX Vref Scan disable
1656 12:11:39.505056 == TX Byte 0 ==
1657 12:11:39.508381 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1658 12:11:39.514923 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1659 12:11:39.515039 == TX Byte 1 ==
1660 12:11:39.518677 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1661 12:11:39.525248 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1662 12:11:39.525354
1663 12:11:39.525451 [DATLAT]
1664 12:11:39.525540 Freq=800, CH1 RK0
1665 12:11:39.525631
1666 12:11:39.528401 DATLAT Default: 0xa
1667 12:11:39.528500 0, 0xFFFF, sum = 0
1668 12:11:39.531470 1, 0xFFFF, sum = 0
1669 12:11:39.534717 2, 0xFFFF, sum = 0
1670 12:11:39.534815 3, 0xFFFF, sum = 0
1671 12:11:39.537849 4, 0xFFFF, sum = 0
1672 12:11:39.537950 5, 0xFFFF, sum = 0
1673 12:11:39.541727 6, 0xFFFF, sum = 0
1674 12:11:39.541839 7, 0xFFFF, sum = 0
1675 12:11:39.544898 8, 0xFFFF, sum = 0
1676 12:11:39.545008 9, 0x0, sum = 1
1677 12:11:39.548091 10, 0x0, sum = 2
1678 12:11:39.548210 11, 0x0, sum = 3
1679 12:11:39.551174 12, 0x0, sum = 4
1680 12:11:39.551276 best_step = 10
1681 12:11:39.551384
1682 12:11:39.551481 ==
1683 12:11:39.555016 Dram Type= 6, Freq= 0, CH_1, rank 0
1684 12:11:39.558265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1685 12:11:39.558349 ==
1686 12:11:39.561487 RX Vref Scan: 1
1687 12:11:39.561584
1688 12:11:39.564730 Set Vref Range= 32 -> 127
1689 12:11:39.564811
1690 12:11:39.564876 RX Vref 32 -> 127, step: 1
1691 12:11:39.564936
1692 12:11:39.568049 RX Delay -95 -> 252, step: 8
1693 12:11:39.568130
1694 12:11:39.571215 Set Vref, RX VrefLevel [Byte0]: 32
1695 12:11:39.574364 [Byte1]: 32
1696 12:11:39.578205
1697 12:11:39.578281 Set Vref, RX VrefLevel [Byte0]: 33
1698 12:11:39.581349 [Byte1]: 33
1699 12:11:39.585734
1700 12:11:39.585827 Set Vref, RX VrefLevel [Byte0]: 34
1701 12:11:39.588778 [Byte1]: 34
1702 12:11:39.593134
1703 12:11:39.593247 Set Vref, RX VrefLevel [Byte0]: 35
1704 12:11:39.596271 [Byte1]: 35
1705 12:11:39.600746
1706 12:11:39.600834 Set Vref, RX VrefLevel [Byte0]: 36
1707 12:11:39.603960 [Byte1]: 36
1708 12:11:39.608317
1709 12:11:39.608468 Set Vref, RX VrefLevel [Byte0]: 37
1710 12:11:39.611574 [Byte1]: 37
1711 12:11:39.615980
1712 12:11:39.616065 Set Vref, RX VrefLevel [Byte0]: 38
1713 12:11:39.619238 [Byte1]: 38
1714 12:11:39.623607
1715 12:11:39.623687 Set Vref, RX VrefLevel [Byte0]: 39
1716 12:11:39.626845 [Byte1]: 39
1717 12:11:39.631307
1718 12:11:39.631394 Set Vref, RX VrefLevel [Byte0]: 40
1719 12:11:39.634552 [Byte1]: 40
1720 12:11:39.638471
1721 12:11:39.638544 Set Vref, RX VrefLevel [Byte0]: 41
1722 12:11:39.641650 [Byte1]: 41
1723 12:11:39.646114
1724 12:11:39.646194 Set Vref, RX VrefLevel [Byte0]: 42
1725 12:11:39.649260 [Byte1]: 42
1726 12:11:39.653757
1727 12:11:39.653835 Set Vref, RX VrefLevel [Byte0]: 43
1728 12:11:39.657060 [Byte1]: 43
1729 12:11:39.661561
1730 12:11:39.661653 Set Vref, RX VrefLevel [Byte0]: 44
1731 12:11:39.668013 [Byte1]: 44
1732 12:11:39.668107
1733 12:11:39.671128 Set Vref, RX VrefLevel [Byte0]: 45
1734 12:11:39.674297 [Byte1]: 45
1735 12:11:39.674371
1736 12:11:39.678011 Set Vref, RX VrefLevel [Byte0]: 46
1737 12:11:39.681227 [Byte1]: 46
1738 12:11:39.681363
1739 12:11:39.684489 Set Vref, RX VrefLevel [Byte0]: 47
1740 12:11:39.687475 [Byte1]: 47
1741 12:11:39.691983
1742 12:11:39.692157 Set Vref, RX VrefLevel [Byte0]: 48
1743 12:11:39.694908 [Byte1]: 48
1744 12:11:39.699311
1745 12:11:39.699389 Set Vref, RX VrefLevel [Byte0]: 49
1746 12:11:39.702628 [Byte1]: 49
1747 12:11:39.707081
1748 12:11:39.707164 Set Vref, RX VrefLevel [Byte0]: 50
1749 12:11:39.710249 [Byte1]: 50
1750 12:11:39.714709
1751 12:11:39.714787 Set Vref, RX VrefLevel [Byte0]: 51
1752 12:11:39.718007 [Byte1]: 51
1753 12:11:39.722000
1754 12:11:39.722087 Set Vref, RX VrefLevel [Byte0]: 52
1755 12:11:39.725730 [Byte1]: 52
1756 12:11:39.729505
1757 12:11:39.729590 Set Vref, RX VrefLevel [Byte0]: 53
1758 12:11:39.733463 [Byte1]: 53
1759 12:11:39.737272
1760 12:11:39.737361 Set Vref, RX VrefLevel [Byte0]: 54
1761 12:11:39.740607 [Byte1]: 54
1762 12:11:39.745031
1763 12:11:39.745111 Set Vref, RX VrefLevel [Byte0]: 55
1764 12:11:39.748301 [Byte1]: 55
1765 12:11:39.752722
1766 12:11:39.752824 Set Vref, RX VrefLevel [Byte0]: 56
1767 12:11:39.755877 [Byte1]: 56
1768 12:11:39.760306
1769 12:11:39.760422 Set Vref, RX VrefLevel [Byte0]: 57
1770 12:11:39.766655 [Byte1]: 57
1771 12:11:39.766765
1772 12:11:39.769906 Set Vref, RX VrefLevel [Byte0]: 58
1773 12:11:39.773093 [Byte1]: 58
1774 12:11:39.773210
1775 12:11:39.776227 Set Vref, RX VrefLevel [Byte0]: 59
1776 12:11:39.780220 [Byte1]: 59
1777 12:11:39.780328
1778 12:11:39.783370 Set Vref, RX VrefLevel [Byte0]: 60
1779 12:11:39.786512 [Byte1]: 60
1780 12:11:39.790280
1781 12:11:39.790397 Set Vref, RX VrefLevel [Byte0]: 61
1782 12:11:39.793868 [Byte1]: 61
1783 12:11:39.798372
1784 12:11:39.798452 Set Vref, RX VrefLevel [Byte0]: 62
1785 12:11:39.801530 [Byte1]: 62
1786 12:11:39.805986
1787 12:11:39.806091 Set Vref, RX VrefLevel [Byte0]: 63
1788 12:11:39.809104 [Byte1]: 63
1789 12:11:39.813528
1790 12:11:39.813660 Set Vref, RX VrefLevel [Byte0]: 64
1791 12:11:39.816816 [Byte1]: 64
1792 12:11:39.821277
1793 12:11:39.821356 Set Vref, RX VrefLevel [Byte0]: 65
1794 12:11:39.824460 [Byte1]: 65
1795 12:11:39.828246
1796 12:11:39.828323 Set Vref, RX VrefLevel [Byte0]: 66
1797 12:11:39.831928 [Byte1]: 66
1798 12:11:39.835844
1799 12:11:39.835918 Set Vref, RX VrefLevel [Byte0]: 67
1800 12:11:39.839668 [Byte1]: 67
1801 12:11:39.843520
1802 12:11:39.843600 Set Vref, RX VrefLevel [Byte0]: 68
1803 12:11:39.846804 [Byte1]: 68
1804 12:11:39.851331
1805 12:11:39.851417 Set Vref, RX VrefLevel [Byte0]: 69
1806 12:11:39.854567 [Byte1]: 69
1807 12:11:39.859017
1808 12:11:39.859094 Set Vref, RX VrefLevel [Byte0]: 70
1809 12:11:39.862036 [Byte1]: 70
1810 12:11:39.866473
1811 12:11:39.866555 Set Vref, RX VrefLevel [Byte0]: 71
1812 12:11:39.869670 [Byte1]: 71
1813 12:11:39.874153
1814 12:11:39.874255 Set Vref, RX VrefLevel [Byte0]: 72
1815 12:11:39.877270 [Byte1]: 72
1816 12:11:39.881927
1817 12:11:39.882022 Set Vref, RX VrefLevel [Byte0]: 73
1818 12:11:39.885097 [Byte1]: 73
1819 12:11:39.889540
1820 12:11:39.889616 Set Vref, RX VrefLevel [Byte0]: 74
1821 12:11:39.892732 [Byte1]: 74
1822 12:11:39.896911
1823 12:11:39.896993 Final RX Vref Byte 0 = 56 to rank0
1824 12:11:39.900069 Final RX Vref Byte 1 = 64 to rank0
1825 12:11:39.903895 Final RX Vref Byte 0 = 56 to rank1
1826 12:11:39.907011 Final RX Vref Byte 1 = 64 to rank1==
1827 12:11:39.910198 Dram Type= 6, Freq= 0, CH_1, rank 0
1828 12:11:39.916882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 12:11:39.917024 ==
1830 12:11:39.917095 DQS Delay:
1831 12:11:39.917165 DQS0 = 0, DQS1 = 0
1832 12:11:39.920134 DQM Delay:
1833 12:11:39.920216 DQM0 = 87, DQM1 = 79
1834 12:11:39.923338 DQ Delay:
1835 12:11:39.926656 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1836 12:11:39.930532 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1837 12:11:39.933666 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1838 12:11:39.936731 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1839 12:11:39.936808
1840 12:11:39.936882
1841 12:11:39.943140 [DQSOSCAuto] RK0, (LSB)MR18= 0x331f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1842 12:11:39.947268 CH1 RK0: MR19=606, MR18=331F
1843 12:11:39.953140 CH1_RK0: MR19=0x606, MR18=0x331F, DQSOSC=396, MR23=63, INC=94, DEC=62
1844 12:11:39.953252
1845 12:11:39.956857 ----->DramcWriteLeveling(PI) begin...
1846 12:11:39.956948 ==
1847 12:11:39.960098 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 12:11:39.963247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 12:11:39.963354 ==
1850 12:11:39.966333 Write leveling (Byte 0): 26 => 26
1851 12:11:39.970120 Write leveling (Byte 1): 31 => 31
1852 12:11:39.973280 DramcWriteLeveling(PI) end<-----
1853 12:11:39.973391
1854 12:11:39.973503 ==
1855 12:11:39.976448 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 12:11:39.979727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 12:11:39.979845 ==
1858 12:11:39.982885 [Gating] SW mode calibration
1859 12:11:39.989481 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1860 12:11:39.996431 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1861 12:11:39.999504 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 12:11:40.006320 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1863 12:11:40.009532 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:11:40.012822 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:11:40.019351 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:11:40.023247 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:11:40.026396 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:11:40.032733 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:11:40.035827 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:11:40.039556 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:11:40.045961 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:11:40.049073 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:11:40.052881 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:11:40.056067 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:11:40.062534 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:11:40.065814 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:11:40.068983 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:11:40.075652 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1879 12:11:40.078929 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1880 12:11:40.082678 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:11:40.089336 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:11:40.092567 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:11:40.095893 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:11:40.102296 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:11:40.105448 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:11:40.109511 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:11:40.115316 0 9 8 | B1->B0 | 302f 2626 | 1 0 | (0 0) (0 0)
1888 12:11:40.119167 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 12:11:40.122363 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 12:11:40.128727 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 12:11:40.132002 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 12:11:40.135254 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 12:11:40.141765 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 12:11:40.145776 0 10 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
1895 12:11:40.149067 0 10 8 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (0 0)
1896 12:11:40.155528 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:11:40.158649 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:11:40.161929 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:11:40.168449 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:11:40.171646 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:11:40.174930 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:11:40.182061 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1903 12:11:40.185244 0 11 8 | B1->B0 | 4343 3a3a | 1 1 | (0 0) (0 0)
1904 12:11:40.188454 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 12:11:40.194854 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 12:11:40.198710 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 12:11:40.201921 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 12:11:40.208368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 12:11:40.211369 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 12:11:40.215152 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1911 12:11:40.221513 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 12:11:40.225251 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:11:40.228305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:11:40.234743 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:11:40.238073 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:11:40.241283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:11:40.248241 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:11:40.251452 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:11:40.254657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:11:40.258348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:11:40.264888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:11:40.268028 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:11:40.271244 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:11:40.278225 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:11:40.281376 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:11:40.284634 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1927 12:11:40.288439 Total UI for P1: 0, mck2ui 16
1928 12:11:40.291515 best dqsien dly found for B1: ( 0, 14, 2)
1929 12:11:40.297893 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1930 12:11:40.301098 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 12:11:40.304978 Total UI for P1: 0, mck2ui 16
1932 12:11:40.308132 best dqsien dly found for B0: ( 0, 14, 6)
1933 12:11:40.311507 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1934 12:11:40.314577 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1935 12:11:40.314658
1936 12:11:40.317761 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1937 12:11:40.320969 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1938 12:11:40.324705 [Gating] SW calibration Done
1939 12:11:40.324787 ==
1940 12:11:40.327892 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 12:11:40.330955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 12:11:40.334160 ==
1943 12:11:40.334242 RX Vref Scan: 0
1944 12:11:40.334307
1945 12:11:40.338059 RX Vref 0 -> 0, step: 1
1946 12:11:40.338141
1947 12:11:40.340767 RX Delay -130 -> 252, step: 16
1948 12:11:40.344512 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1949 12:11:40.347742 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1950 12:11:40.350815 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1951 12:11:40.354143 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1952 12:11:40.360783 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1953 12:11:40.364459 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1954 12:11:40.367766 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1955 12:11:40.370897 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1956 12:11:40.374036 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1957 12:11:40.380968 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1958 12:11:40.383984 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1959 12:11:40.387209 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1960 12:11:40.390904 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1961 12:11:40.397333 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1962 12:11:40.400481 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1963 12:11:40.403678 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1964 12:11:40.403760 ==
1965 12:11:40.406883 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 12:11:40.410876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 12:11:40.410960 ==
1968 12:11:40.413888 DQS Delay:
1969 12:11:40.413970 DQS0 = 0, DQS1 = 0
1970 12:11:40.417248 DQM Delay:
1971 12:11:40.417331 DQM0 = 87, DQM1 = 78
1972 12:11:40.417396 DQ Delay:
1973 12:11:40.420413 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1974 12:11:40.423565 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1975 12:11:40.427397 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1976 12:11:40.430498 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1977 12:11:40.430590
1978 12:11:40.433674
1979 12:11:40.433755 ==
1980 12:11:40.436702 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:11:40.440639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:11:40.440726 ==
1983 12:11:40.440868
1984 12:11:40.440966
1985 12:11:40.443819 TX Vref Scan disable
1986 12:11:40.443934 == TX Byte 0 ==
1987 12:11:40.450335 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1988 12:11:40.453565 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1989 12:11:40.453684 == TX Byte 1 ==
1990 12:11:40.460072 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1991 12:11:40.463330 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1992 12:11:40.463449 ==
1993 12:11:40.466637 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 12:11:40.469939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 12:11:40.470043 ==
1996 12:11:40.484027 TX Vref=22, minBit 8, minWin=26, winSum=441
1997 12:11:40.487165 TX Vref=24, minBit 8, minWin=26, winSum=443
1998 12:11:40.490248 TX Vref=26, minBit 9, minWin=27, winSum=451
1999 12:11:40.494125 TX Vref=28, minBit 15, minWin=27, winSum=451
2000 12:11:40.497377 TX Vref=30, minBit 9, minWin=27, winSum=453
2001 12:11:40.503803 TX Vref=32, minBit 9, minWin=27, winSum=448
2002 12:11:40.506971 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 30
2003 12:11:40.507076
2004 12:11:40.510088 Final TX Range 1 Vref 30
2005 12:11:40.510191
2006 12:11:40.510290 ==
2007 12:11:40.513746 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 12:11:40.517059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 12:11:40.520234 ==
2010 12:11:40.520336
2011 12:11:40.520430
2012 12:11:40.520546 TX Vref Scan disable
2013 12:11:40.523938 == TX Byte 0 ==
2014 12:11:40.526953 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 12:11:40.533977 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 12:11:40.534086 == TX Byte 1 ==
2017 12:11:40.537119 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2018 12:11:40.543997 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2019 12:11:40.544109
2020 12:11:40.544210 [DATLAT]
2021 12:11:40.544304 Freq=800, CH1 RK1
2022 12:11:40.544393
2023 12:11:40.547228 DATLAT Default: 0xa
2024 12:11:40.547332 0, 0xFFFF, sum = 0
2025 12:11:40.550411 1, 0xFFFF, sum = 0
2026 12:11:40.553687 2, 0xFFFF, sum = 0
2027 12:11:40.553795 3, 0xFFFF, sum = 0
2028 12:11:40.556773 4, 0xFFFF, sum = 0
2029 12:11:40.556891 5, 0xFFFF, sum = 0
2030 12:11:40.560584 6, 0xFFFF, sum = 0
2031 12:11:40.560713 7, 0xFFFF, sum = 0
2032 12:11:40.563807 8, 0xFFFF, sum = 0
2033 12:11:40.563908 9, 0x0, sum = 1
2034 12:11:40.567077 10, 0x0, sum = 2
2035 12:11:40.567181 11, 0x0, sum = 3
2036 12:11:40.567275 12, 0x0, sum = 4
2037 12:11:40.570381 best_step = 10
2038 12:11:40.570480
2039 12:11:40.570570 ==
2040 12:11:40.573607 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 12:11:40.576863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 12:11:40.576964 ==
2043 12:11:40.580060 RX Vref Scan: 0
2044 12:11:40.580162
2045 12:11:40.583339 RX Vref 0 -> 0, step: 1
2046 12:11:40.583440
2047 12:11:40.583531 RX Delay -95 -> 252, step: 8
2048 12:11:40.590512 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2049 12:11:40.594197 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2050 12:11:40.597394 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2051 12:11:40.600625 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2052 12:11:40.603901 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2053 12:11:40.610245 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2054 12:11:40.613548 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2055 12:11:40.617473 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2056 12:11:40.620743 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2057 12:11:40.626982 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2058 12:11:40.630079 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2059 12:11:40.633749 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2060 12:11:40.636988 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2061 12:11:40.640192 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2062 12:11:40.647014 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2063 12:11:40.650265 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2064 12:11:40.650355 ==
2065 12:11:40.653489 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 12:11:40.656831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 12:11:40.656944 ==
2068 12:11:40.659942 DQS Delay:
2069 12:11:40.660040 DQS0 = 0, DQS1 = 0
2070 12:11:40.660129 DQM Delay:
2071 12:11:40.663203 DQM0 = 87, DQM1 = 78
2072 12:11:40.663274 DQ Delay:
2073 12:11:40.667098 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2074 12:11:40.670295 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2075 12:11:40.673467 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2076 12:11:40.676657 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2077 12:11:40.676739
2078 12:11:40.676803
2079 12:11:40.686804 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2080 12:11:40.686888 CH1 RK1: MR19=606, MR18=1D15
2081 12:11:40.693144 CH1_RK1: MR19=0x606, MR18=0x1D15, DQSOSC=402, MR23=63, INC=91, DEC=60
2082 12:11:40.696920 [RxdqsGatingPostProcess] freq 800
2083 12:11:40.703213 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2084 12:11:40.706546 Pre-setting of DQS Precalculation
2085 12:11:40.709817 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2086 12:11:40.720162 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2087 12:11:40.726613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2088 12:11:40.726700
2089 12:11:40.726766
2090 12:11:40.729768 [Calibration Summary] 1600 Mbps
2091 12:11:40.729849 CH 0, Rank 0
2092 12:11:40.732757 SW Impedance : PASS
2093 12:11:40.732855 DUTY Scan : NO K
2094 12:11:40.735872 ZQ Calibration : PASS
2095 12:11:40.739611 Jitter Meter : NO K
2096 12:11:40.739693 CBT Training : PASS
2097 12:11:40.742973 Write leveling : PASS
2098 12:11:40.746110 RX DQS gating : PASS
2099 12:11:40.746194 RX DQ/DQS(RDDQC) : PASS
2100 12:11:40.749287 TX DQ/DQS : PASS
2101 12:11:40.752415 RX DATLAT : PASS
2102 12:11:40.752497 RX DQ/DQS(Engine): PASS
2103 12:11:40.756165 TX OE : NO K
2104 12:11:40.756248 All Pass.
2105 12:11:40.756324
2106 12:11:40.759410 CH 0, Rank 1
2107 12:11:40.759492 SW Impedance : PASS
2108 12:11:40.762649 DUTY Scan : NO K
2109 12:11:40.765960 ZQ Calibration : PASS
2110 12:11:40.766043 Jitter Meter : NO K
2111 12:11:40.769056 CBT Training : PASS
2112 12:11:40.769184 Write leveling : PASS
2113 12:11:40.772921 RX DQS gating : PASS
2114 12:11:40.776056 RX DQ/DQS(RDDQC) : PASS
2115 12:11:40.776138 TX DQ/DQS : PASS
2116 12:11:40.779344 RX DATLAT : PASS
2117 12:11:40.782587 RX DQ/DQS(Engine): PASS
2118 12:11:40.782669 TX OE : NO K
2119 12:11:40.785836 All Pass.
2120 12:11:40.785917
2121 12:11:40.785995 CH 1, Rank 0
2122 12:11:40.789004 SW Impedance : PASS
2123 12:11:40.789095 DUTY Scan : NO K
2124 12:11:40.792870 ZQ Calibration : PASS
2125 12:11:40.796038 Jitter Meter : NO K
2126 12:11:40.796131 CBT Training : PASS
2127 12:11:40.799171 Write leveling : PASS
2128 12:11:40.802822 RX DQS gating : PASS
2129 12:11:40.802905 RX DQ/DQS(RDDQC) : PASS
2130 12:11:40.805954 TX DQ/DQS : PASS
2131 12:11:40.809170 RX DATLAT : PASS
2132 12:11:40.809258 RX DQ/DQS(Engine): PASS
2133 12:11:40.812471 TX OE : NO K
2134 12:11:40.812596 All Pass.
2135 12:11:40.812666
2136 12:11:40.815806 CH 1, Rank 1
2137 12:11:40.815892 SW Impedance : PASS
2138 12:11:40.818975 DUTY Scan : NO K
2139 12:11:40.822073 ZQ Calibration : PASS
2140 12:11:40.822182 Jitter Meter : NO K
2141 12:11:40.825309 CBT Training : PASS
2142 12:11:40.825382 Write leveling : PASS
2143 12:11:40.829198 RX DQS gating : PASS
2144 12:11:40.832485 RX DQ/DQS(RDDQC) : PASS
2145 12:11:40.832608 TX DQ/DQS : PASS
2146 12:11:40.835622 RX DATLAT : PASS
2147 12:11:40.838663 RX DQ/DQS(Engine): PASS
2148 12:11:40.838759 TX OE : NO K
2149 12:11:40.842396 All Pass.
2150 12:11:40.842567
2151 12:11:40.842725 DramC Write-DBI off
2152 12:11:40.845651 PER_BANK_REFRESH: Hybrid Mode
2153 12:11:40.848874 TX_TRACKING: ON
2154 12:11:40.852473 [GetDramInforAfterCalByMRR] Vendor 6.
2155 12:11:40.855583 [GetDramInforAfterCalByMRR] Revision 606.
2156 12:11:40.858848 [GetDramInforAfterCalByMRR] Revision 2 0.
2157 12:11:40.858961 MR0 0x3b3b
2158 12:11:40.859060 MR8 0x5151
2159 12:11:40.862175 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 12:11:40.865379
2161 12:11:40.865452 MR0 0x3b3b
2162 12:11:40.865529 MR8 0x5151
2163 12:11:40.868726 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 12:11:40.868839
2165 12:11:40.878988 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2166 12:11:40.882252 [FAST_K] Save calibration result to emmc
2167 12:11:40.885479 [FAST_K] Save calibration result to emmc
2168 12:11:40.888764 dram_init: config_dvfs: 1
2169 12:11:40.892010 dramc_set_vcore_voltage set vcore to 662500
2170 12:11:40.895250 Read voltage for 1200, 2
2171 12:11:40.895324 Vio18 = 0
2172 12:11:40.895388 Vcore = 662500
2173 12:11:40.898603 Vdram = 0
2174 12:11:40.898694 Vddq = 0
2175 12:11:40.898761 Vmddr = 0
2176 12:11:40.905516 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2177 12:11:40.908607 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2178 12:11:40.911743 MEM_TYPE=3, freq_sel=15
2179 12:11:40.915600 sv_algorithm_assistance_LP4_1600
2180 12:11:40.918886 ============ PULL DRAM RESETB DOWN ============
2181 12:11:40.922032 ========== PULL DRAM RESETB DOWN end =========
2182 12:11:40.928399 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 12:11:40.931611 ===================================
2184 12:11:40.935503 LPDDR4 DRAM CONFIGURATION
2185 12:11:40.938675 ===================================
2186 12:11:40.938761 EX_ROW_EN[0] = 0x0
2187 12:11:40.941935 EX_ROW_EN[1] = 0x0
2188 12:11:40.942022 LP4Y_EN = 0x0
2189 12:11:40.945100 WORK_FSP = 0x0
2190 12:11:40.945216 WL = 0x4
2191 12:11:40.948825 RL = 0x4
2192 12:11:40.948922 BL = 0x2
2193 12:11:40.952024 RPST = 0x0
2194 12:11:40.952106 RD_PRE = 0x0
2195 12:11:40.955108 WR_PRE = 0x1
2196 12:11:40.955193 WR_PST = 0x0
2197 12:11:40.958315 DBI_WR = 0x0
2198 12:11:40.958398 DBI_RD = 0x0
2199 12:11:40.962019 OTF = 0x1
2200 12:11:40.965295 ===================================
2201 12:11:40.968628 ===================================
2202 12:11:40.968705 ANA top config
2203 12:11:40.971713 ===================================
2204 12:11:40.975024 DLL_ASYNC_EN = 0
2205 12:11:40.978682 ALL_SLAVE_EN = 0
2206 12:11:40.981442 NEW_RANK_MODE = 1
2207 12:11:40.981524 DLL_IDLE_MODE = 1
2208 12:11:40.985156 LP45_APHY_COMB_EN = 1
2209 12:11:40.988398 TX_ODT_DIS = 1
2210 12:11:40.991598 NEW_8X_MODE = 1
2211 12:11:40.994865 ===================================
2212 12:11:40.998043 ===================================
2213 12:11:41.001961 data_rate = 2400
2214 12:11:41.002065 CKR = 1
2215 12:11:41.004944 DQ_P2S_RATIO = 8
2216 12:11:41.008188 ===================================
2217 12:11:41.011201 CA_P2S_RATIO = 8
2218 12:11:41.015010 DQ_CA_OPEN = 0
2219 12:11:41.018217 DQ_SEMI_OPEN = 0
2220 12:11:41.021483 CA_SEMI_OPEN = 0
2221 12:11:41.024610 CA_FULL_RATE = 0
2222 12:11:41.024691 DQ_CKDIV4_EN = 0
2223 12:11:41.028400 CA_CKDIV4_EN = 0
2224 12:11:41.031590 CA_PREDIV_EN = 0
2225 12:11:41.034887 PH8_DLY = 17
2226 12:11:41.038157 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2227 12:11:41.041306 DQ_AAMCK_DIV = 4
2228 12:11:41.041432 CA_AAMCK_DIV = 4
2229 12:11:41.045138 CA_ADMCK_DIV = 4
2230 12:11:41.048093 DQ_TRACK_CA_EN = 0
2231 12:11:41.051148 CA_PICK = 1200
2232 12:11:41.054448 CA_MCKIO = 1200
2233 12:11:41.058373 MCKIO_SEMI = 0
2234 12:11:41.061529 PLL_FREQ = 2366
2235 12:11:41.061610 DQ_UI_PI_RATIO = 32
2236 12:11:41.064512 CA_UI_PI_RATIO = 0
2237 12:11:41.067856 ===================================
2238 12:11:41.071055 ===================================
2239 12:11:41.074228 memory_type:LPDDR4
2240 12:11:41.078062 GP_NUM : 10
2241 12:11:41.078156 SRAM_EN : 1
2242 12:11:41.081248 MD32_EN : 0
2243 12:11:41.084407 ===================================
2244 12:11:41.087499 [ANA_INIT] >>>>>>>>>>>>>>
2245 12:11:41.087628 <<<<<< [CONFIGURE PHASE]: ANA_TX
2246 12:11:41.090732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2247 12:11:41.094584 ===================================
2248 12:11:41.097841 data_rate = 2400,PCW = 0X5b00
2249 12:11:41.101093 ===================================
2250 12:11:41.104301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2251 12:11:41.110603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 12:11:41.117258 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 12:11:41.120415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2254 12:11:41.124315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2255 12:11:41.127468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2256 12:11:41.130436 [ANA_INIT] flow start
2257 12:11:41.130534 [ANA_INIT] PLL >>>>>>>>
2258 12:11:41.134341 [ANA_INIT] PLL <<<<<<<<
2259 12:11:41.137661 [ANA_INIT] MIDPI >>>>>>>>
2260 12:11:41.141026 [ANA_INIT] MIDPI <<<<<<<<
2261 12:11:41.141127 [ANA_INIT] DLL >>>>>>>>
2262 12:11:41.144205 [ANA_INIT] DLL <<<<<<<<
2263 12:11:41.144313 [ANA_INIT] flow end
2264 12:11:41.150497 ============ LP4 DIFF to SE enter ============
2265 12:11:41.154212 ============ LP4 DIFF to SE exit ============
2266 12:11:41.157404 [ANA_INIT] <<<<<<<<<<<<<
2267 12:11:41.160678 [Flow] Enable top DCM control >>>>>
2268 12:11:41.163756 [Flow] Enable top DCM control <<<<<
2269 12:11:41.167118 Enable DLL master slave shuffle
2270 12:11:41.170196 ==============================================================
2271 12:11:41.173498 Gating Mode config
2272 12:11:41.177419 ==============================================================
2273 12:11:41.180680 Config description:
2274 12:11:41.190320 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2275 12:11:41.196844 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2276 12:11:41.200097 SELPH_MODE 0: By rank 1: By Phase
2277 12:11:41.206626 ==============================================================
2278 12:11:41.209921 GAT_TRACK_EN = 1
2279 12:11:41.213737 RX_GATING_MODE = 2
2280 12:11:41.216824 RX_GATING_TRACK_MODE = 2
2281 12:11:41.220428 SELPH_MODE = 1
2282 12:11:41.223156 PICG_EARLY_EN = 1
2283 12:11:41.223254 VALID_LAT_VALUE = 1
2284 12:11:41.230190 ==============================================================
2285 12:11:41.233489 Enter into Gating configuration >>>>
2286 12:11:41.237131 Exit from Gating configuration <<<<
2287 12:11:41.239702 Enter into DVFS_PRE_config >>>>>
2288 12:11:41.250190 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2289 12:11:41.253419 Exit from DVFS_PRE_config <<<<<
2290 12:11:41.256335 Enter into PICG configuration >>>>
2291 12:11:41.260087 Exit from PICG configuration <<<<
2292 12:11:41.263374 [RX_INPUT] configuration >>>>>
2293 12:11:41.266463 [RX_INPUT] configuration <<<<<
2294 12:11:41.273333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2295 12:11:41.276656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2296 12:11:41.282998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 12:11:41.289962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 12:11:41.296345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 12:11:41.302844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 12:11:41.306666 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2301 12:11:41.309932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2302 12:11:41.313119 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2303 12:11:41.319471 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2304 12:11:41.323166 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2305 12:11:41.326341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 12:11:41.329478 ===================================
2307 12:11:41.332768 LPDDR4 DRAM CONFIGURATION
2308 12:11:41.336004 ===================================
2309 12:11:41.336078 EX_ROW_EN[0] = 0x0
2310 12:11:41.339877 EX_ROW_EN[1] = 0x0
2311 12:11:41.339948 LP4Y_EN = 0x0
2312 12:11:41.342971 WORK_FSP = 0x0
2313 12:11:41.346259 WL = 0x4
2314 12:11:41.346341 RL = 0x4
2315 12:11:41.349476 BL = 0x2
2316 12:11:41.349557 RPST = 0x0
2317 12:11:41.352650 RD_PRE = 0x0
2318 12:11:41.352731 WR_PRE = 0x1
2319 12:11:41.355862 WR_PST = 0x0
2320 12:11:41.355951 DBI_WR = 0x0
2321 12:11:41.359644 DBI_RD = 0x0
2322 12:11:41.359725 OTF = 0x1
2323 12:11:41.362760 ===================================
2324 12:11:41.365820 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2325 12:11:41.372866 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2326 12:11:41.375827 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 12:11:41.379181 ===================================
2328 12:11:41.382550 LPDDR4 DRAM CONFIGURATION
2329 12:11:41.385722 ===================================
2330 12:11:41.385802 EX_ROW_EN[0] = 0x10
2331 12:11:41.388896 EX_ROW_EN[1] = 0x0
2332 12:11:41.388976 LP4Y_EN = 0x0
2333 12:11:41.392250 WORK_FSP = 0x0
2334 12:11:41.392331 WL = 0x4
2335 12:11:41.395983 RL = 0x4
2336 12:11:41.399084 BL = 0x2
2337 12:11:41.399161 RPST = 0x0
2338 12:11:41.402281 RD_PRE = 0x0
2339 12:11:41.402351 WR_PRE = 0x1
2340 12:11:41.405720 WR_PST = 0x0
2341 12:11:41.405823 DBI_WR = 0x0
2342 12:11:41.409470 DBI_RD = 0x0
2343 12:11:41.409549 OTF = 0x1
2344 12:11:41.412745 ===================================
2345 12:11:41.419312 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2346 12:11:41.419416 ==
2347 12:11:41.422569 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 12:11:41.425736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2349 12:11:41.425871 ==
2350 12:11:41.428932 [Duty_Offset_Calibration]
2351 12:11:41.432056 B0:1 B1:-1 CA:0
2352 12:11:41.432124
2353 12:11:41.435218 [DutyScan_Calibration_Flow] k_type=0
2354 12:11:41.443654
2355 12:11:41.443788 ==CLK 0==
2356 12:11:41.446786 Final CLK duty delay cell = 0
2357 12:11:41.450104 [0] MAX Duty = 5094%(X100), DQS PI = 14
2358 12:11:41.453420 [0] MIN Duty = 4906%(X100), DQS PI = 8
2359 12:11:41.453501 [0] AVG Duty = 5000%(X100)
2360 12:11:41.457147
2361 12:11:41.460413 CH0 CLK Duty spec in!! Max-Min= 188%
2362 12:11:41.463590 [DutyScan_Calibration_Flow] ====Done====
2363 12:11:41.463671
2364 12:11:41.466509 [DutyScan_Calibration_Flow] k_type=1
2365 12:11:41.482177
2366 12:11:41.482345 ==DQS 0 ==
2367 12:11:41.485345 Final DQS duty delay cell = -4
2368 12:11:41.489157 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2369 12:11:41.492390 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2370 12:11:41.495786 [-4] AVG Duty = 4968%(X100)
2371 12:11:41.495867
2372 12:11:41.495932 ==DQS 1 ==
2373 12:11:41.498840 Final DQS duty delay cell = 0
2374 12:11:41.502045 [0] MAX Duty = 5124%(X100), DQS PI = 4
2375 12:11:41.505293 [0] MIN Duty = 5000%(X100), DQS PI = 22
2376 12:11:41.508486 [0] AVG Duty = 5062%(X100)
2377 12:11:41.508596
2378 12:11:41.511700 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2379 12:11:41.511809
2380 12:11:41.515014 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2381 12:11:41.518296 [DutyScan_Calibration_Flow] ====Done====
2382 12:11:41.518378
2383 12:11:41.521980 [DutyScan_Calibration_Flow] k_type=3
2384 12:11:41.539394
2385 12:11:41.539510 ==DQM 0 ==
2386 12:11:41.543328 Final DQM duty delay cell = 0
2387 12:11:41.546417 [0] MAX Duty = 5031%(X100), DQS PI = 16
2388 12:11:41.549607 [0] MIN Duty = 4875%(X100), DQS PI = 6
2389 12:11:41.552748 [0] AVG Duty = 4953%(X100)
2390 12:11:41.552830
2391 12:11:41.552895 ==DQM 1 ==
2392 12:11:41.556016 Final DQM duty delay cell = 4
2393 12:11:41.559762 [4] MAX Duty = 5187%(X100), DQS PI = 14
2394 12:11:41.563008 [4] MIN Duty = 5000%(X100), DQS PI = 26
2395 12:11:41.566013 [4] AVG Duty = 5093%(X100)
2396 12:11:41.566095
2397 12:11:41.569744 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2398 12:11:41.569829
2399 12:11:41.572878 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2400 12:11:41.575997 [DutyScan_Calibration_Flow] ====Done====
2401 12:11:41.576081
2402 12:11:41.579129 [DutyScan_Calibration_Flow] k_type=2
2403 12:11:41.595631
2404 12:11:41.595722 ==DQ 0 ==
2405 12:11:41.598945 Final DQ duty delay cell = -4
2406 12:11:41.602136 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2407 12:11:41.605339 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2408 12:11:41.608523 [-4] AVG Duty = 4969%(X100)
2409 12:11:41.608609
2410 12:11:41.608675 ==DQ 1 ==
2411 12:11:41.611791 Final DQ duty delay cell = 0
2412 12:11:41.615698 [0] MAX Duty = 5093%(X100), DQS PI = 4
2413 12:11:41.618929 [0] MIN Duty = 4969%(X100), DQS PI = 42
2414 12:11:41.622158 [0] AVG Duty = 5031%(X100)
2415 12:11:41.622243
2416 12:11:41.625439 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2417 12:11:41.625524
2418 12:11:41.628640 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2419 12:11:41.631692 [DutyScan_Calibration_Flow] ====Done====
2420 12:11:41.631777 ==
2421 12:11:41.635562 Dram Type= 6, Freq= 0, CH_1, rank 0
2422 12:11:41.638666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2423 12:11:41.638753 ==
2424 12:11:41.641857 [Duty_Offset_Calibration]
2425 12:11:41.641945 B0:-1 B1:1 CA:2
2426 12:11:41.642020
2427 12:11:41.644840 [DutyScan_Calibration_Flow] k_type=0
2428 12:11:41.655733
2429 12:11:41.655824 ==CLK 0==
2430 12:11:41.659025 Final CLK duty delay cell = 0
2431 12:11:41.662312 [0] MAX Duty = 5156%(X100), DQS PI = 22
2432 12:11:41.665511 [0] MIN Duty = 4969%(X100), DQS PI = 60
2433 12:11:41.668658 [0] AVG Duty = 5062%(X100)
2434 12:11:41.668742
2435 12:11:41.672391 CH1 CLK Duty spec in!! Max-Min= 187%
2436 12:11:41.675495 [DutyScan_Calibration_Flow] ====Done====
2437 12:11:41.675572
2438 12:11:41.678538 [DutyScan_Calibration_Flow] k_type=1
2439 12:11:41.695049
2440 12:11:41.695141 ==DQS 0 ==
2441 12:11:41.698204 Final DQS duty delay cell = 0
2442 12:11:41.702017 [0] MAX Duty = 5156%(X100), DQS PI = 50
2443 12:11:41.704766 [0] MIN Duty = 4875%(X100), DQS PI = 6
2444 12:11:41.708624 [0] AVG Duty = 5015%(X100)
2445 12:11:41.708711
2446 12:11:41.708778 ==DQS 1 ==
2447 12:11:41.711681 Final DQS duty delay cell = 0
2448 12:11:41.715013 [0] MAX Duty = 5094%(X100), DQS PI = 12
2449 12:11:41.718280 [0] MIN Duty = 4969%(X100), DQS PI = 56
2450 12:11:41.721515 [0] AVG Duty = 5031%(X100)
2451 12:11:41.721621
2452 12:11:41.724796 CH1 DQS 0 Duty spec in!! Max-Min= 281%
2453 12:11:41.724869
2454 12:11:41.728016 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2455 12:11:41.731192 [DutyScan_Calibration_Flow] ====Done====
2456 12:11:41.731296
2457 12:11:41.734337 [DutyScan_Calibration_Flow] k_type=3
2458 12:11:41.750501
2459 12:11:41.750639 ==DQM 0 ==
2460 12:11:41.753747 Final DQM duty delay cell = -4
2461 12:11:41.757526 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2462 12:11:41.760675 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2463 12:11:41.763902 [-4] AVG Duty = 4969%(X100)
2464 12:11:41.764004
2465 12:11:41.764096 ==DQM 1 ==
2466 12:11:41.767067 Final DQM duty delay cell = 0
2467 12:11:41.770268 [0] MAX Duty = 5187%(X100), DQS PI = 4
2468 12:11:41.773953 [0] MIN Duty = 5000%(X100), DQS PI = 28
2469 12:11:41.777067 [0] AVG Duty = 5093%(X100)
2470 12:11:41.777174
2471 12:11:41.780582 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2472 12:11:41.780684
2473 12:11:41.783811 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2474 12:11:41.787118 [DutyScan_Calibration_Flow] ====Done====
2475 12:11:41.787221
2476 12:11:41.790810 [DutyScan_Calibration_Flow] k_type=2
2477 12:11:41.807437
2478 12:11:41.807571 ==DQ 0 ==
2479 12:11:41.810687 Final DQ duty delay cell = 0
2480 12:11:41.813819 [0] MAX Duty = 5156%(X100), DQS PI = 28
2481 12:11:41.817530 [0] MIN Duty = 4876%(X100), DQS PI = 8
2482 12:11:41.817644 [0] AVG Duty = 5016%(X100)
2483 12:11:41.817746
2484 12:11:41.820810 ==DQ 1 ==
2485 12:11:41.824012 Final DQ duty delay cell = 0
2486 12:11:41.827801 [0] MAX Duty = 5156%(X100), DQS PI = 10
2487 12:11:41.830967 [0] MIN Duty = 4969%(X100), DQS PI = 0
2488 12:11:41.831071 [0] AVG Duty = 5062%(X100)
2489 12:11:41.831164
2490 12:11:41.834231 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2491 12:11:41.834357
2492 12:11:41.837358 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2493 12:11:41.843817 [DutyScan_Calibration_Flow] ====Done====
2494 12:11:41.847548 nWR fixed to 30
2495 12:11:41.847638 [ModeRegInit_LP4] CH0 RK0
2496 12:11:41.850862 [ModeRegInit_LP4] CH0 RK1
2497 12:11:41.853681 [ModeRegInit_LP4] CH1 RK0
2498 12:11:41.853794 [ModeRegInit_LP4] CH1 RK1
2499 12:11:41.857508 match AC timing 7
2500 12:11:41.860722 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2501 12:11:41.863874 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2502 12:11:41.870345 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2503 12:11:41.873556 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2504 12:11:41.880574 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2505 12:11:41.880691 ==
2506 12:11:41.883738 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 12:11:41.886673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 12:11:41.886751 ==
2509 12:11:41.893703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 12:11:41.900185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2511 12:11:41.907223 [CA 0] Center 39 (9~70) winsize 62
2512 12:11:41.910462 [CA 1] Center 39 (9~70) winsize 62
2513 12:11:41.913658 [CA 2] Center 35 (5~66) winsize 62
2514 12:11:41.916960 [CA 3] Center 35 (5~66) winsize 62
2515 12:11:41.920740 [CA 4] Center 34 (4~64) winsize 61
2516 12:11:41.923999 [CA 5] Center 33 (4~63) winsize 60
2517 12:11:41.924091
2518 12:11:41.927254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 12:11:41.927326
2520 12:11:41.930437 [CATrainingPosCal] consider 1 rank data
2521 12:11:41.933718 u2DelayCellTimex100 = 270/100 ps
2522 12:11:41.937098 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 12:11:41.943630 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 12:11:41.946816 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 12:11:41.950630 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 12:11:41.953937 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2527 12:11:41.957115 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2528 12:11:41.957232
2529 12:11:41.960136 CA PerBit enable=1, Macro0, CA PI delay=33
2530 12:11:41.960267
2531 12:11:41.963397 [CBTSetCACLKResult] CA Dly = 33
2532 12:11:41.963496 CS Dly: 8 (0~39)
2533 12:11:41.967265 ==
2534 12:11:41.970568 Dram Type= 6, Freq= 0, CH_0, rank 1
2535 12:11:41.973674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 12:11:41.973759 ==
2537 12:11:41.976874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 12:11:41.983248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2539 12:11:41.993081 [CA 0] Center 39 (9~70) winsize 62
2540 12:11:41.996251 [CA 1] Center 39 (9~70) winsize 62
2541 12:11:41.999408 [CA 2] Center 35 (5~66) winsize 62
2542 12:11:42.002656 [CA 3] Center 34 (4~65) winsize 62
2543 12:11:42.005867 [CA 4] Center 33 (3~64) winsize 62
2544 12:11:42.009787 [CA 5] Center 33 (3~63) winsize 61
2545 12:11:42.009872
2546 12:11:42.013009 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 12:11:42.013095
2548 12:11:42.016074 [CATrainingPosCal] consider 2 rank data
2549 12:11:42.019294 u2DelayCellTimex100 = 270/100 ps
2550 12:11:42.023140 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 12:11:42.029630 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2552 12:11:42.032953 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 12:11:42.036048 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2554 12:11:42.039288 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2555 12:11:42.043063 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2556 12:11:42.043154
2557 12:11:42.046318 CA PerBit enable=1, Macro0, CA PI delay=33
2558 12:11:42.046444
2559 12:11:42.049572 [CBTSetCACLKResult] CA Dly = 33
2560 12:11:42.049698 CS Dly: 9 (0~41)
2561 12:11:42.052878
2562 12:11:42.053008 ----->DramcWriteLeveling(PI) begin...
2563 12:11:42.056276 ==
2564 12:11:42.059511 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 12:11:42.062479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 12:11:42.062583 ==
2567 12:11:42.065685 Write leveling (Byte 0): 33 => 33
2568 12:11:42.069566 Write leveling (Byte 1): 28 => 28
2569 12:11:42.072870 DramcWriteLeveling(PI) end<-----
2570 12:11:42.072954
2571 12:11:42.073020 ==
2572 12:11:42.076003 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 12:11:42.079300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 12:11:42.079385 ==
2575 12:11:42.082252 [Gating] SW mode calibration
2576 12:11:42.089262 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2577 12:11:42.095423 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2578 12:11:42.099207 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2579 12:11:42.102378 0 15 4 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
2580 12:11:42.108828 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 12:11:42.112033 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 12:11:42.115270 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 12:11:42.122309 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 12:11:42.125481 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2585 12:11:42.128622 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
2586 12:11:42.135167 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2587 12:11:42.138964 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 12:11:42.142165 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 12:11:42.148579 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 12:11:42.151843 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 12:11:42.154988 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 12:11:42.161924 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 12:11:42.165069 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2594 12:11:42.168292 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2595 12:11:42.171589 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2596 12:11:42.178675 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 12:11:42.181882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 12:11:42.188215 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 12:11:42.191459 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 12:11:42.195097 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 12:11:42.198208 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2602 12:11:42.205369 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 12:11:42.208429 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:11:42.211639 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:11:42.217985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:11:42.221863 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:11:42.225039 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:11:42.231299 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:11:42.234597 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:11:42.237972 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:11:42.245022 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:11:42.248299 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:11:42.251554 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:11:42.258139 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:11:42.261262 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:11:42.264478 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 12:11:42.271307 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 12:11:42.274482 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2619 12:11:42.277751 Total UI for P1: 0, mck2ui 16
2620 12:11:42.280977 best dqsien dly found for B0: ( 1, 3, 26)
2621 12:11:42.284740 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 12:11:42.291139 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 12:11:42.291249 Total UI for P1: 0, mck2ui 16
2624 12:11:42.298078 best dqsien dly found for B1: ( 1, 4, 2)
2625 12:11:42.301204 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2626 12:11:42.304395 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2627 12:11:42.304506
2628 12:11:42.308037 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2629 12:11:42.311212 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2630 12:11:42.314356 [Gating] SW calibration Done
2631 12:11:42.314455 ==
2632 12:11:42.317520 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 12:11:42.321410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 12:11:42.321515 ==
2635 12:11:42.324688 RX Vref Scan: 0
2636 12:11:42.324778
2637 12:11:42.324843 RX Vref 0 -> 0, step: 1
2638 12:11:42.324917
2639 12:11:42.327947 RX Delay -40 -> 252, step: 8
2640 12:11:42.331203 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2641 12:11:42.337503 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2642 12:11:42.340844 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2643 12:11:42.344090 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2644 12:11:42.347256 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2645 12:11:42.350551 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2646 12:11:42.357558 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2647 12:11:42.360746 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2648 12:11:42.364006 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2649 12:11:42.367289 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2650 12:11:42.370492 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2651 12:11:42.377224 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2652 12:11:42.380493 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2653 12:11:42.384225 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2654 12:11:42.387378 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2655 12:11:42.390666 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2656 12:11:42.393984 ==
2657 12:11:42.397270 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 12:11:42.400431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 12:11:42.400509 ==
2660 12:11:42.400585 DQS Delay:
2661 12:11:42.403492 DQS0 = 0, DQS1 = 0
2662 12:11:42.403566 DQM Delay:
2663 12:11:42.407173 DQM0 = 119, DQM1 = 107
2664 12:11:42.407246 DQ Delay:
2665 12:11:42.410389 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2666 12:11:42.413655 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2667 12:11:42.416778 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2668 12:11:42.419801 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2669 12:11:42.419876
2670 12:11:42.419939
2671 12:11:42.420008 ==
2672 12:11:42.423648 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:11:42.430154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:11:42.430240 ==
2675 12:11:42.430309
2676 12:11:42.430371
2677 12:11:42.430430 TX Vref Scan disable
2678 12:11:42.433983 == TX Byte 0 ==
2679 12:11:42.437256 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2680 12:11:42.443664 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2681 12:11:42.443745 == TX Byte 1 ==
2682 12:11:42.446941 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2683 12:11:42.453569 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2684 12:11:42.453674 ==
2685 12:11:42.456811 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:11:42.460107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:11:42.460183 ==
2688 12:11:42.472328 TX Vref=22, minBit 5, minWin=25, winSum=419
2689 12:11:42.475550 TX Vref=24, minBit 0, minWin=26, winSum=427
2690 12:11:42.478679 TX Vref=26, minBit 5, minWin=26, winSum=437
2691 12:11:42.481800 TX Vref=28, minBit 5, minWin=26, winSum=433
2692 12:11:42.485043 TX Vref=30, minBit 5, minWin=26, winSum=437
2693 12:11:42.488882 TX Vref=32, minBit 4, minWin=26, winSum=432
2694 12:11:42.495295 [TxChooseVref] Worse bit 5, Min win 26, Win sum 437, Final Vref 26
2695 12:11:42.495388
2696 12:11:42.498492 Final TX Range 1 Vref 26
2697 12:11:42.498568
2698 12:11:42.498630 ==
2699 12:11:42.501691 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 12:11:42.505441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 12:11:42.505528 ==
2702 12:11:42.508438
2703 12:11:42.508535
2704 12:11:42.508599 TX Vref Scan disable
2705 12:11:42.511546 == TX Byte 0 ==
2706 12:11:42.514874 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2707 12:11:42.518658 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2708 12:11:42.521833 == TX Byte 1 ==
2709 12:11:42.524939 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2710 12:11:42.528712 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2711 12:11:42.531938
2712 12:11:42.532021 [DATLAT]
2713 12:11:42.532087 Freq=1200, CH0 RK0
2714 12:11:42.532149
2715 12:11:42.535163 DATLAT Default: 0xd
2716 12:11:42.535236 0, 0xFFFF, sum = 0
2717 12:11:42.538404 1, 0xFFFF, sum = 0
2718 12:11:42.538489 2, 0xFFFF, sum = 0
2719 12:11:42.541604 3, 0xFFFF, sum = 0
2720 12:11:42.541689 4, 0xFFFF, sum = 0
2721 12:11:42.544833 5, 0xFFFF, sum = 0
2722 12:11:42.548565 6, 0xFFFF, sum = 0
2723 12:11:42.548653 7, 0xFFFF, sum = 0
2724 12:11:42.551771 8, 0xFFFF, sum = 0
2725 12:11:42.551855 9, 0xFFFF, sum = 0
2726 12:11:42.555010 10, 0xFFFF, sum = 0
2727 12:11:42.555097 11, 0xFFFF, sum = 0
2728 12:11:42.558336 12, 0x0, sum = 1
2729 12:11:42.558423 13, 0x0, sum = 2
2730 12:11:42.561656 14, 0x0, sum = 3
2731 12:11:42.561743 15, 0x0, sum = 4
2732 12:11:42.561830 best_step = 13
2733 12:11:42.564953
2734 12:11:42.565039 ==
2735 12:11:42.568294 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 12:11:42.571432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 12:11:42.571518 ==
2738 12:11:42.571605 RX Vref Scan: 1
2739 12:11:42.571685
2740 12:11:42.574620 Set Vref Range= 32 -> 127
2741 12:11:42.574705
2742 12:11:42.578468 RX Vref 32 -> 127, step: 1
2743 12:11:42.578554
2744 12:11:42.581599 RX Delay -21 -> 252, step: 4
2745 12:11:42.581686
2746 12:11:42.584691 Set Vref, RX VrefLevel [Byte0]: 32
2747 12:11:42.587934 [Byte1]: 32
2748 12:11:42.588012
2749 12:11:42.591104 Set Vref, RX VrefLevel [Byte0]: 33
2750 12:11:42.594401 [Byte1]: 33
2751 12:11:42.598232
2752 12:11:42.598318 Set Vref, RX VrefLevel [Byte0]: 34
2753 12:11:42.601480 [Byte1]: 34
2754 12:11:42.605911
2755 12:11:42.609159 Set Vref, RX VrefLevel [Byte0]: 35
2756 12:11:42.612721 [Byte1]: 35
2757 12:11:42.612807
2758 12:11:42.615915 Set Vref, RX VrefLevel [Byte0]: 36
2759 12:11:42.619070 [Byte1]: 36
2760 12:11:42.619155
2761 12:11:42.622186 Set Vref, RX VrefLevel [Byte0]: 37
2762 12:11:42.626011 [Byte1]: 37
2763 12:11:42.629700
2764 12:11:42.629787 Set Vref, RX VrefLevel [Byte0]: 38
2765 12:11:42.633603 [Byte1]: 38
2766 12:11:42.638032
2767 12:11:42.638117 Set Vref, RX VrefLevel [Byte0]: 39
2768 12:11:42.641293 [Byte1]: 39
2769 12:11:42.645726
2770 12:11:42.645814 Set Vref, RX VrefLevel [Byte0]: 40
2771 12:11:42.648966 [Byte1]: 40
2772 12:11:42.653922
2773 12:11:42.654034 Set Vref, RX VrefLevel [Byte0]: 41
2774 12:11:42.657122 [Byte1]: 41
2775 12:11:42.661671
2776 12:11:42.661779 Set Vref, RX VrefLevel [Byte0]: 42
2777 12:11:42.664833 [Byte1]: 42
2778 12:11:42.669351
2779 12:11:42.669457 Set Vref, RX VrefLevel [Byte0]: 43
2780 12:11:42.672675 [Byte1]: 43
2781 12:11:42.677193
2782 12:11:42.677300 Set Vref, RX VrefLevel [Byte0]: 44
2783 12:11:42.680996 [Byte1]: 44
2784 12:11:42.685425
2785 12:11:42.685534 Set Vref, RX VrefLevel [Byte0]: 45
2786 12:11:42.688604 [Byte1]: 45
2787 12:11:42.693085
2788 12:11:42.693198 Set Vref, RX VrefLevel [Byte0]: 46
2789 12:11:42.696920 [Byte1]: 46
2790 12:11:42.701453
2791 12:11:42.701561 Set Vref, RX VrefLevel [Byte0]: 47
2792 12:11:42.707449 [Byte1]: 47
2793 12:11:42.707557
2794 12:11:42.711161 Set Vref, RX VrefLevel [Byte0]: 48
2795 12:11:42.714314 [Byte1]: 48
2796 12:11:42.714418
2797 12:11:42.717887 Set Vref, RX VrefLevel [Byte0]: 49
2798 12:11:42.721090 [Byte1]: 49
2799 12:11:42.724894
2800 12:11:42.725015 Set Vref, RX VrefLevel [Byte0]: 50
2801 12:11:42.728013 [Byte1]: 50
2802 12:11:42.733121
2803 12:11:42.733233 Set Vref, RX VrefLevel [Byte0]: 51
2804 12:11:42.736222 [Byte1]: 51
2805 12:11:42.740853
2806 12:11:42.740931 Set Vref, RX VrefLevel [Byte0]: 52
2807 12:11:42.744057 [Byte1]: 52
2808 12:11:42.748568
2809 12:11:42.748737 Set Vref, RX VrefLevel [Byte0]: 53
2810 12:11:42.752291 [Byte1]: 53
2811 12:11:42.756774
2812 12:11:42.756876 Set Vref, RX VrefLevel [Byte0]: 54
2813 12:11:42.760020 [Byte1]: 54
2814 12:11:42.764389
2815 12:11:42.764496 Set Vref, RX VrefLevel [Byte0]: 55
2816 12:11:42.767677 [Byte1]: 55
2817 12:11:42.772727
2818 12:11:42.772835 Set Vref, RX VrefLevel [Byte0]: 56
2819 12:11:42.775975 [Byte1]: 56
2820 12:11:42.780400
2821 12:11:42.780502 Set Vref, RX VrefLevel [Byte0]: 57
2822 12:11:42.783531 [Byte1]: 57
2823 12:11:42.788675
2824 12:11:42.788750 Set Vref, RX VrefLevel [Byte0]: 58
2825 12:11:42.791895 [Byte1]: 58
2826 12:11:42.796282
2827 12:11:42.796406 Set Vref, RX VrefLevel [Byte0]: 59
2828 12:11:42.799509 [Byte1]: 59
2829 12:11:42.804672
2830 12:11:42.804774 Set Vref, RX VrefLevel [Byte0]: 60
2831 12:11:42.807909 [Byte1]: 60
2832 12:11:42.812444
2833 12:11:42.812569 Set Vref, RX VrefLevel [Byte0]: 61
2834 12:11:42.815613 [Byte1]: 61
2835 12:11:42.819970
2836 12:11:42.820081 Set Vref, RX VrefLevel [Byte0]: 62
2837 12:11:42.823612 [Byte1]: 62
2838 12:11:42.828043
2839 12:11:42.828151 Set Vref, RX VrefLevel [Byte0]: 63
2840 12:11:42.831281 [Byte1]: 63
2841 12:11:42.836300
2842 12:11:42.836406 Set Vref, RX VrefLevel [Byte0]: 64
2843 12:11:42.839364 [Byte1]: 64
2844 12:11:42.843822
2845 12:11:42.843929 Set Vref, RX VrefLevel [Byte0]: 65
2846 12:11:42.847062 [Byte1]: 65
2847 12:11:42.851541
2848 12:11:42.851656 Set Vref, RX VrefLevel [Byte0]: 66
2849 12:11:42.855227 [Byte1]: 66
2850 12:11:42.859703
2851 12:11:42.859811 Set Vref, RX VrefLevel [Byte0]: 67
2852 12:11:42.862964 [Byte1]: 67
2853 12:11:42.867462
2854 12:11:42.867566 Set Vref, RX VrefLevel [Byte0]: 68
2855 12:11:42.871268 [Byte1]: 68
2856 12:11:42.875751
2857 12:11:42.875830 Set Vref, RX VrefLevel [Byte0]: 69
2858 12:11:42.879020 [Byte1]: 69
2859 12:11:42.883616
2860 12:11:42.883722 Set Vref, RX VrefLevel [Byte0]: 70
2861 12:11:42.886741 [Byte1]: 70
2862 12:11:42.891880
2863 12:11:42.891985 Set Vref, RX VrefLevel [Byte0]: 71
2864 12:11:42.895071 [Byte1]: 71
2865 12:11:42.899457
2866 12:11:42.899570 Set Vref, RX VrefLevel [Byte0]: 72
2867 12:11:42.905755 [Byte1]: 72
2868 12:11:42.905864
2869 12:11:42.908989 Set Vref, RX VrefLevel [Byte0]: 73
2870 12:11:42.912729 [Byte1]: 73
2871 12:11:42.912843
2872 12:11:42.915892 Set Vref, RX VrefLevel [Byte0]: 74
2873 12:11:42.919005 [Byte1]: 74
2874 12:11:42.923384
2875 12:11:42.923493 Set Vref, RX VrefLevel [Byte0]: 75
2876 12:11:42.926622 [Byte1]: 75
2877 12:11:42.931085
2878 12:11:42.931198 Set Vref, RX VrefLevel [Byte0]: 76
2879 12:11:42.934128 [Byte1]: 76
2880 12:11:42.939136
2881 12:11:42.939248 Set Vref, RX VrefLevel [Byte0]: 77
2882 12:11:42.942195 [Byte1]: 77
2883 12:11:42.947185
2884 12:11:42.947307 Set Vref, RX VrefLevel [Byte0]: 78
2885 12:11:42.950452 [Byte1]: 78
2886 12:11:42.954958
2887 12:11:42.955065 Final RX Vref Byte 0 = 59 to rank0
2888 12:11:42.958162 Final RX Vref Byte 1 = 56 to rank0
2889 12:11:42.961332 Final RX Vref Byte 0 = 59 to rank1
2890 12:11:42.964977 Final RX Vref Byte 1 = 56 to rank1==
2891 12:11:42.968265 Dram Type= 6, Freq= 0, CH_0, rank 0
2892 12:11:42.974884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 12:11:42.975018 ==
2894 12:11:42.975131 DQS Delay:
2895 12:11:42.978112 DQS0 = 0, DQS1 = 0
2896 12:11:42.978223 DQM Delay:
2897 12:11:42.978328 DQM0 = 119, DQM1 = 107
2898 12:11:42.981322 DQ Delay:
2899 12:11:42.984593 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2900 12:11:42.987699 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =128
2901 12:11:42.991532 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2902 12:11:42.994684 DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114
2903 12:11:42.994794
2904 12:11:42.994901
2905 12:11:43.004070 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2906 12:11:43.004201 CH0 RK0: MR19=403, MR18=10FC
2907 12:11:43.010865 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2908 12:11:43.010993
2909 12:11:43.014088 ----->DramcWriteLeveling(PI) begin...
2910 12:11:43.014200 ==
2911 12:11:43.017378 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:11:43.024290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:11:43.024438 ==
2914 12:11:43.027383 Write leveling (Byte 0): 32 => 32
2915 12:11:43.031067 Write leveling (Byte 1): 27 => 27
2916 12:11:43.031186 DramcWriteLeveling(PI) end<-----
2917 12:11:43.031290
2918 12:11:43.034093 ==
2919 12:11:43.037335 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 12:11:43.040592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 12:11:43.040706 ==
2922 12:11:43.044421 [Gating] SW mode calibration
2923 12:11:43.050899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2924 12:11:43.054102 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2925 12:11:43.060442 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2926 12:11:43.064328 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2927 12:11:43.067472 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 12:11:43.074334 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 12:11:43.077490 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 12:11:43.080696 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 12:11:43.087865 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 12:11:43.090973 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2933 12:11:43.094266 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2934 12:11:43.101192 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 12:11:43.104252 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 12:11:43.107483 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 12:11:43.110657 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 12:11:43.117692 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 12:11:43.120955 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 12:11:43.124196 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2941 12:11:43.131023 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2942 12:11:43.134056 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 12:11:43.137191 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 12:11:43.144091 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 12:11:43.147230 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 12:11:43.150435 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 12:11:43.157487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2948 12:11:43.160703 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2949 12:11:43.163994 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2950 12:11:43.170452 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:11:43.174307 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:11:43.177446 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:11:43.183935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:11:43.187105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:11:43.190994 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:11:43.197640 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 12:11:43.200861 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 12:11:43.203904 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 12:11:43.210914 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 12:11:43.214136 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 12:11:43.217327 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 12:11:43.220509 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 12:11:43.227129 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 12:11:43.230855 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2965 12:11:43.234082 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2966 12:11:43.237229 Total UI for P1: 0, mck2ui 16
2967 12:11:43.240348 best dqsien dly found for B0: ( 1, 3, 28)
2968 12:11:43.246968 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 12:11:43.250561 Total UI for P1: 0, mck2ui 16
2970 12:11:43.253921 best dqsien dly found for B1: ( 1, 4, 0)
2971 12:11:43.257070 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2972 12:11:43.260308 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2973 12:11:43.260413
2974 12:11:43.263441 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2975 12:11:43.267235 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2976 12:11:43.270470 [Gating] SW calibration Done
2977 12:11:43.270580 ==
2978 12:11:43.273725 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 12:11:43.276960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 12:11:43.277076 ==
2981 12:11:43.280202 RX Vref Scan: 0
2982 12:11:43.280312
2983 12:11:43.280408 RX Vref 0 -> 0, step: 1
2984 12:11:43.283924
2985 12:11:43.284035 RX Delay -40 -> 252, step: 8
2986 12:11:43.290465 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2987 12:11:43.293823 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2988 12:11:43.296978 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2989 12:11:43.300090 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2990 12:11:43.303312 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2991 12:11:43.310302 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2992 12:11:43.313477 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2993 12:11:43.316692 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2994 12:11:43.319876 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2995 12:11:43.323556 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2996 12:11:43.326855 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2997 12:11:43.333356 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2998 12:11:43.336452 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2999 12:11:43.340131 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3000 12:11:43.343183 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3001 12:11:43.349866 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3002 12:11:43.349993 ==
3003 12:11:43.353619 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 12:11:43.356816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 12:11:43.356934 ==
3006 12:11:43.357033 DQS Delay:
3007 12:11:43.359970 DQS0 = 0, DQS1 = 0
3008 12:11:43.360090 DQM Delay:
3009 12:11:43.363202 DQM0 = 116, DQM1 = 108
3010 12:11:43.363311 DQ Delay:
3011 12:11:43.366377 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3012 12:11:43.369541 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3013 12:11:43.373337 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3014 12:11:43.376533 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3015 12:11:43.376659
3016 12:11:43.376729
3017 12:11:43.376803 ==
3018 12:11:43.379629 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 12:11:43.386608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 12:11:43.386735 ==
3021 12:11:43.386839
3022 12:11:43.386942
3023 12:11:43.387035 TX Vref Scan disable
3024 12:11:43.390336 == TX Byte 0 ==
3025 12:11:43.393470 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3026 12:11:43.400381 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3027 12:11:43.400505 == TX Byte 1 ==
3028 12:11:43.403703 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3029 12:11:43.410113 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3030 12:11:43.410227 ==
3031 12:11:43.413328 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 12:11:43.416538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 12:11:43.416655 ==
3034 12:11:43.428585 TX Vref=22, minBit 1, minWin=26, winSum=423
3035 12:11:43.431725 TX Vref=24, minBit 1, minWin=26, winSum=427
3036 12:11:43.434962 TX Vref=26, minBit 1, minWin=26, winSum=432
3037 12:11:43.438184 TX Vref=28, minBit 10, minWin=26, winSum=433
3038 12:11:43.442082 TX Vref=30, minBit 13, minWin=25, winSum=435
3039 12:11:43.448172 TX Vref=32, minBit 0, minWin=27, winSum=434
3040 12:11:43.451322 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 32
3041 12:11:43.451441
3042 12:11:43.455062 Final TX Range 1 Vref 32
3043 12:11:43.455171
3044 12:11:43.455276 ==
3045 12:11:43.458236 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 12:11:43.461308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 12:11:43.465010 ==
3048 12:11:43.465120
3049 12:11:43.465217
3050 12:11:43.465310 TX Vref Scan disable
3051 12:11:43.468192 == TX Byte 0 ==
3052 12:11:43.471565 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3053 12:11:43.478661 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3054 12:11:43.478782 == TX Byte 1 ==
3055 12:11:43.481931 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3056 12:11:43.488183 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3057 12:11:43.488306
3058 12:11:43.488412 [DATLAT]
3059 12:11:43.488569 Freq=1200, CH0 RK1
3060 12:11:43.488675
3061 12:11:43.491448 DATLAT Default: 0xd
3062 12:11:43.495083 0, 0xFFFF, sum = 0
3063 12:11:43.495194 1, 0xFFFF, sum = 0
3064 12:11:43.498333 2, 0xFFFF, sum = 0
3065 12:11:43.498441 3, 0xFFFF, sum = 0
3066 12:11:43.501699 4, 0xFFFF, sum = 0
3067 12:11:43.501810 5, 0xFFFF, sum = 0
3068 12:11:43.504812 6, 0xFFFF, sum = 0
3069 12:11:43.504923 7, 0xFFFF, sum = 0
3070 12:11:43.508049 8, 0xFFFF, sum = 0
3071 12:11:43.508160 9, 0xFFFF, sum = 0
3072 12:11:43.511314 10, 0xFFFF, sum = 0
3073 12:11:43.511422 11, 0xFFFF, sum = 0
3074 12:11:43.514408 12, 0x0, sum = 1
3075 12:11:43.514513 13, 0x0, sum = 2
3076 12:11:43.517559 14, 0x0, sum = 3
3077 12:11:43.517665 15, 0x0, sum = 4
3078 12:11:43.521303 best_step = 13
3079 12:11:43.521411
3080 12:11:43.521510 ==
3081 12:11:43.524396 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 12:11:43.527645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 12:11:43.527752 ==
3084 12:11:43.530846 RX Vref Scan: 0
3085 12:11:43.530956
3086 12:11:43.531052 RX Vref 0 -> 0, step: 1
3087 12:11:43.531146
3088 12:11:43.534712 RX Delay -21 -> 252, step: 4
3089 12:11:43.541180 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3090 12:11:43.544367 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3091 12:11:43.547573 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3092 12:11:43.550719 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3093 12:11:43.554270 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3094 12:11:43.561091 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3095 12:11:43.564138 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3096 12:11:43.567887 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3097 12:11:43.571209 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3098 12:11:43.574334 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3099 12:11:43.580720 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3100 12:11:43.583927 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3101 12:11:43.587747 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3102 12:11:43.590930 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3103 12:11:43.594254 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3104 12:11:43.600601 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3105 12:11:43.600721 ==
3106 12:11:43.603721 Dram Type= 6, Freq= 0, CH_0, rank 1
3107 12:11:43.606971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 12:11:43.607084 ==
3109 12:11:43.607180 DQS Delay:
3110 12:11:43.610295 DQS0 = 0, DQS1 = 0
3111 12:11:43.610413 DQM Delay:
3112 12:11:43.614138 DQM0 = 116, DQM1 = 109
3113 12:11:43.614247 DQ Delay:
3114 12:11:43.617429 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3115 12:11:43.620688 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3116 12:11:43.623868 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =102
3117 12:11:43.626929 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =116
3118 12:11:43.627039
3119 12:11:43.630715
3120 12:11:43.637067 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3121 12:11:43.640343 CH0 RK1: MR19=403, MR18=FE9
3122 12:11:43.646853 CH0_RK1: MR19=0x403, MR18=0xFE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3123 12:11:43.646971 [RxdqsGatingPostProcess] freq 1200
3124 12:11:43.653636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3125 12:11:43.656591 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 12:11:43.660271 best DQS1 dly(2T, 0.5T) = (0, 12)
3127 12:11:43.663432 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 12:11:43.666724 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3129 12:11:43.669993 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 12:11:43.673709 best DQS1 dly(2T, 0.5T) = (0, 12)
3131 12:11:43.676925 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 12:11:43.680285 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3133 12:11:43.683513 Pre-setting of DQS Precalculation
3134 12:11:43.686833 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3135 12:11:43.686969 ==
3136 12:11:43.690105 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 12:11:43.693330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 12:11:43.696593 ==
3139 12:11:43.699796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 12:11:43.706208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3141 12:11:43.714546 [CA 0] Center 37 (7~68) winsize 62
3142 12:11:43.717668 [CA 1] Center 37 (7~68) winsize 62
3143 12:11:43.720874 [CA 2] Center 34 (4~64) winsize 61
3144 12:11:43.724610 [CA 3] Center 33 (3~64) winsize 62
3145 12:11:43.727837 [CA 4] Center 34 (4~64) winsize 61
3146 12:11:43.730844 [CA 5] Center 33 (3~64) winsize 62
3147 12:11:43.730951
3148 12:11:43.734657 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3149 12:11:43.734762
3150 12:11:43.737835 [CATrainingPosCal] consider 1 rank data
3151 12:11:43.740879 u2DelayCellTimex100 = 270/100 ps
3152 12:11:43.744595 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 12:11:43.751035 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 12:11:43.754379 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 12:11:43.757587 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 12:11:43.760797 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 12:11:43.764404 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3158 12:11:43.764525
3159 12:11:43.767558 CA PerBit enable=1, Macro0, CA PI delay=33
3160 12:11:43.767666
3161 12:11:43.770726 [CBTSetCACLKResult] CA Dly = 33
3162 12:11:43.770839 CS Dly: 6 (0~37)
3163 12:11:43.774473 ==
3164 12:11:43.777630 Dram Type= 6, Freq= 0, CH_1, rank 1
3165 12:11:43.780860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 12:11:43.780968 ==
3167 12:11:43.784186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3168 12:11:43.790679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3169 12:11:43.800315 [CA 0] Center 37 (7~67) winsize 61
3170 12:11:43.803610 [CA 1] Center 38 (8~68) winsize 61
3171 12:11:43.806716 [CA 2] Center 34 (4~65) winsize 62
3172 12:11:43.809994 [CA 3] Center 33 (3~64) winsize 62
3173 12:11:43.813357 [CA 4] Center 34 (3~65) winsize 63
3174 12:11:43.816599 [CA 5] Center 33 (3~64) winsize 62
3175 12:11:43.816710
3176 12:11:43.819793 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3177 12:11:43.819902
3178 12:11:43.823598 [CATrainingPosCal] consider 2 rank data
3179 12:11:43.826736 u2DelayCellTimex100 = 270/100 ps
3180 12:11:43.829829 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3181 12:11:43.833588 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3182 12:11:43.839926 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 12:11:43.843732 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3184 12:11:43.846972 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3185 12:11:43.850262 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3186 12:11:43.850372
3187 12:11:43.853504 CA PerBit enable=1, Macro0, CA PI delay=33
3188 12:11:43.853609
3189 12:11:43.856680 [CBTSetCACLKResult] CA Dly = 33
3190 12:11:43.856795 CS Dly: 7 (0~40)
3191 12:11:43.856894
3192 12:11:43.859882 ----->DramcWriteLeveling(PI) begin...
3193 12:11:43.863152 ==
3194 12:11:43.866305 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 12:11:43.869873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 12:11:43.869988 ==
3197 12:11:43.872962 Write leveling (Byte 0): 24 => 24
3198 12:11:43.876257 Write leveling (Byte 1): 27 => 27
3199 12:11:43.879930 DramcWriteLeveling(PI) end<-----
3200 12:11:43.880019
3201 12:11:43.880086 ==
3202 12:11:43.883225 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 12:11:43.886487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 12:11:43.886594 ==
3205 12:11:43.889702 [Gating] SW mode calibration
3206 12:11:43.896663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3207 12:11:43.903114 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3208 12:11:43.906322 0 15 0 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
3209 12:11:43.909533 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 12:11:43.916595 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 12:11:43.919847 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 12:11:43.923092 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 12:11:43.929573 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 12:11:43.933284 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
3215 12:11:43.936549 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3216 12:11:43.939652 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 12:11:43.945991 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 12:11:43.949882 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 12:11:43.953067 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 12:11:43.959412 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 12:11:43.962640 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 12:11:43.965881 1 0 24 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
3223 12:11:43.972600 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3224 12:11:43.975801 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 12:11:43.979469 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 12:11:43.985694 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 12:11:43.989566 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 12:11:43.992731 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 12:11:43.999194 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 12:11:44.002504 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3231 12:11:44.005695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3232 12:11:44.012235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:11:44.015404 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:11:44.019288 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:11:44.025651 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:11:44.028856 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:11:44.032058 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:11:44.039028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 12:11:44.042186 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 12:11:44.045422 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 12:11:44.051834 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 12:11:44.055689 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 12:11:44.058956 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 12:11:44.065452 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 12:11:44.068580 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 12:11:44.071824 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3247 12:11:44.078547 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 12:11:44.078647 Total UI for P1: 0, mck2ui 16
3249 12:11:44.085505 best dqsien dly found for B0: ( 1, 3, 24)
3250 12:11:44.085660 Total UI for P1: 0, mck2ui 16
3251 12:11:44.092173 best dqsien dly found for B1: ( 1, 3, 24)
3252 12:11:44.095444 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3253 12:11:44.098742 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3254 12:11:44.098873
3255 12:11:44.102039 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3256 12:11:44.105205 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3257 12:11:44.108489 [Gating] SW calibration Done
3258 12:11:44.108678 ==
3259 12:11:44.111788 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 12:11:44.114963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 12:11:44.115105 ==
3262 12:11:44.118229 RX Vref Scan: 0
3263 12:11:44.118356
3264 12:11:44.118458 RX Vref 0 -> 0, step: 1
3265 12:11:44.118570
3266 12:11:44.121500 RX Delay -40 -> 252, step: 8
3267 12:11:44.125373 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3268 12:11:44.131931 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3269 12:11:44.135126 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3270 12:11:44.138338 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3271 12:11:44.141514 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3272 12:11:44.145339 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3273 12:11:44.151613 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3274 12:11:44.154834 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3275 12:11:44.158020 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3276 12:11:44.161182 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3277 12:11:44.165087 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3278 12:11:44.171688 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3279 12:11:44.174947 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3280 12:11:44.177957 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3281 12:11:44.181077 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3282 12:11:44.184877 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3283 12:11:44.187931 ==
3284 12:11:44.191005 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 12:11:44.194725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 12:11:44.194854 ==
3287 12:11:44.194974 DQS Delay:
3288 12:11:44.197981 DQS0 = 0, DQS1 = 0
3289 12:11:44.198087 DQM Delay:
3290 12:11:44.201112 DQM0 = 118, DQM1 = 109
3291 12:11:44.201219 DQ Delay:
3292 12:11:44.204348 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3293 12:11:44.207550 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3294 12:11:44.210879 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3295 12:11:44.214243 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3296 12:11:44.214354
3297 12:11:44.214452
3298 12:11:44.214544 ==
3299 12:11:44.217392 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 12:11:44.224381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 12:11:44.224508 ==
3302 12:11:44.224591
3303 12:11:44.224655
3304 12:11:44.224715 TX Vref Scan disable
3305 12:11:44.228190 == TX Byte 0 ==
3306 12:11:44.231368 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3307 12:11:44.234624 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3308 12:11:44.237923 == TX Byte 1 ==
3309 12:11:44.241075 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3310 12:11:44.244861 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3311 12:11:44.247969 ==
3312 12:11:44.251182 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 12:11:44.254317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 12:11:44.254433 ==
3315 12:11:44.265805 TX Vref=22, minBit 10, minWin=24, winSum=413
3316 12:11:44.269017 TX Vref=24, minBit 10, minWin=25, winSum=421
3317 12:11:44.272261 TX Vref=26, minBit 9, minWin=25, winSum=426
3318 12:11:44.275535 TX Vref=28, minBit 9, minWin=25, winSum=432
3319 12:11:44.278776 TX Vref=30, minBit 9, minWin=25, winSum=427
3320 12:11:44.285400 TX Vref=32, minBit 9, minWin=25, winSum=425
3321 12:11:44.288501 [TxChooseVref] Worse bit 9, Min win 25, Win sum 432, Final Vref 28
3322 12:11:44.288640
3323 12:11:44.292246 Final TX Range 1 Vref 28
3324 12:11:44.292356
3325 12:11:44.292453 ==
3326 12:11:44.295318 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 12:11:44.298483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 12:11:44.302187 ==
3329 12:11:44.302312
3330 12:11:44.302419
3331 12:11:44.302510 TX Vref Scan disable
3332 12:11:44.305320 == TX Byte 0 ==
3333 12:11:44.308499 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3334 12:11:44.315586 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3335 12:11:44.315722 == TX Byte 1 ==
3336 12:11:44.318634 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3337 12:11:44.325301 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3338 12:11:44.325422
3339 12:11:44.325520 [DATLAT]
3340 12:11:44.325610 Freq=1200, CH1 RK0
3341 12:11:44.325725
3342 12:11:44.328462 DATLAT Default: 0xd
3343 12:11:44.328589 0, 0xFFFF, sum = 0
3344 12:11:44.332348 1, 0xFFFF, sum = 0
3345 12:11:44.335466 2, 0xFFFF, sum = 0
3346 12:11:44.335572 3, 0xFFFF, sum = 0
3347 12:11:44.338787 4, 0xFFFF, sum = 0
3348 12:11:44.338893 5, 0xFFFF, sum = 0
3349 12:11:44.342031 6, 0xFFFF, sum = 0
3350 12:11:44.342149 7, 0xFFFF, sum = 0
3351 12:11:44.345344 8, 0xFFFF, sum = 0
3352 12:11:44.345454 9, 0xFFFF, sum = 0
3353 12:11:44.348533 10, 0xFFFF, sum = 0
3354 12:11:44.348631 11, 0xFFFF, sum = 0
3355 12:11:44.351765 12, 0x0, sum = 1
3356 12:11:44.351888 13, 0x0, sum = 2
3357 12:11:44.355428 14, 0x0, sum = 3
3358 12:11:44.355535 15, 0x0, sum = 4
3359 12:11:44.358438 best_step = 13
3360 12:11:44.358522
3361 12:11:44.358599 ==
3362 12:11:44.361699 Dram Type= 6, Freq= 0, CH_1, rank 0
3363 12:11:44.365483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3364 12:11:44.365589 ==
3365 12:11:44.365687 RX Vref Scan: 1
3366 12:11:44.365776
3367 12:11:44.368628 Set Vref Range= 32 -> 127
3368 12:11:44.368726
3369 12:11:44.371849 RX Vref 32 -> 127, step: 1
3370 12:11:44.371924
3371 12:11:44.375156 RX Delay -21 -> 252, step: 4
3372 12:11:44.375266
3373 12:11:44.378397 Set Vref, RX VrefLevel [Byte0]: 32
3374 12:11:44.382207 [Byte1]: 32
3375 12:11:44.382312
3376 12:11:44.384942 Set Vref, RX VrefLevel [Byte0]: 33
3377 12:11:44.388447 [Byte1]: 33
3378 12:11:44.392176
3379 12:11:44.392295 Set Vref, RX VrefLevel [Byte0]: 34
3380 12:11:44.395383 [Byte1]: 34
3381 12:11:44.399872
3382 12:11:44.399991 Set Vref, RX VrefLevel [Byte0]: 35
3383 12:11:44.403051 [Byte1]: 35
3384 12:11:44.407980
3385 12:11:44.408088 Set Vref, RX VrefLevel [Byte0]: 36
3386 12:11:44.410909 [Byte1]: 36
3387 12:11:44.416011
3388 12:11:44.416116 Set Vref, RX VrefLevel [Byte0]: 37
3389 12:11:44.419223 [Byte1]: 37
3390 12:11:44.423719
3391 12:11:44.423802 Set Vref, RX VrefLevel [Byte0]: 38
3392 12:11:44.426969 [Byte1]: 38
3393 12:11:44.431888
3394 12:11:44.431972 Set Vref, RX VrefLevel [Byte0]: 39
3395 12:11:44.435107 [Byte1]: 39
3396 12:11:44.439615
3397 12:11:44.439700 Set Vref, RX VrefLevel [Byte0]: 40
3398 12:11:44.442850 [Byte1]: 40
3399 12:11:44.447388
3400 12:11:44.447472 Set Vref, RX VrefLevel [Byte0]: 41
3401 12:11:44.450646 [Byte1]: 41
3402 12:11:44.455106
3403 12:11:44.455196 Set Vref, RX VrefLevel [Byte0]: 42
3404 12:11:44.458943 [Byte1]: 42
3405 12:11:44.463559
3406 12:11:44.463646 Set Vref, RX VrefLevel [Byte0]: 43
3407 12:11:44.466679 [Byte1]: 43
3408 12:11:44.471163
3409 12:11:44.471250 Set Vref, RX VrefLevel [Byte0]: 44
3410 12:11:44.474363 [Byte1]: 44
3411 12:11:44.478990
3412 12:11:44.479105 Set Vref, RX VrefLevel [Byte0]: 45
3413 12:11:44.482198 [Byte1]: 45
3414 12:11:44.487369
3415 12:11:44.487456 Set Vref, RX VrefLevel [Byte0]: 46
3416 12:11:44.490471 [Byte1]: 46
3417 12:11:44.495368
3418 12:11:44.495455 Set Vref, RX VrefLevel [Byte0]: 47
3419 12:11:44.498485 [Byte1]: 47
3420 12:11:44.502932
3421 12:11:44.503018 Set Vref, RX VrefLevel [Byte0]: 48
3422 12:11:44.506163 [Byte1]: 48
3423 12:11:44.510591
3424 12:11:44.510706 Set Vref, RX VrefLevel [Byte0]: 49
3425 12:11:44.514101 [Byte1]: 49
3426 12:11:44.518505
3427 12:11:44.518621 Set Vref, RX VrefLevel [Byte0]: 50
3428 12:11:44.524965 [Byte1]: 50
3429 12:11:44.525055
3430 12:11:44.528247 Set Vref, RX VrefLevel [Byte0]: 51
3431 12:11:44.532041 [Byte1]: 51
3432 12:11:44.532125
3433 12:11:44.535158 Set Vref, RX VrefLevel [Byte0]: 52
3434 12:11:44.538324 [Byte1]: 52
3435 12:11:44.542304
3436 12:11:44.542418 Set Vref, RX VrefLevel [Byte0]: 53
3437 12:11:44.545493 [Byte1]: 53
3438 12:11:44.550536
3439 12:11:44.550630 Set Vref, RX VrefLevel [Byte0]: 54
3440 12:11:44.553806 [Byte1]: 54
3441 12:11:44.558320
3442 12:11:44.558435 Set Vref, RX VrefLevel [Byte0]: 55
3443 12:11:44.561600 [Byte1]: 55
3444 12:11:44.566586
3445 12:11:44.566698 Set Vref, RX VrefLevel [Byte0]: 56
3446 12:11:44.569878 [Byte1]: 56
3447 12:11:44.574228
3448 12:11:44.574317 Set Vref, RX VrefLevel [Byte0]: 57
3449 12:11:44.577413 [Byte1]: 57
3450 12:11:44.581962
3451 12:11:44.582048 Set Vref, RX VrefLevel [Byte0]: 58
3452 12:11:44.585217 [Byte1]: 58
3453 12:11:44.589661
3454 12:11:44.589776 Set Vref, RX VrefLevel [Byte0]: 59
3455 12:11:44.593502 [Byte1]: 59
3456 12:11:44.597609
3457 12:11:44.597730 Set Vref, RX VrefLevel [Byte0]: 60
3458 12:11:44.601299 [Byte1]: 60
3459 12:11:44.605813
3460 12:11:44.605940 Set Vref, RX VrefLevel [Byte0]: 61
3461 12:11:44.609008 [Byte1]: 61
3462 12:11:44.614003
3463 12:11:44.614123 Set Vref, RX VrefLevel [Byte0]: 62
3464 12:11:44.617037 [Byte1]: 62
3465 12:11:44.621859
3466 12:11:44.621969 Set Vref, RX VrefLevel [Byte0]: 63
3467 12:11:44.624967 [Byte1]: 63
3468 12:11:44.629439
3469 12:11:44.629557 Set Vref, RX VrefLevel [Byte0]: 64
3470 12:11:44.632702 [Byte1]: 64
3471 12:11:44.637883
3472 12:11:44.638019 Set Vref, RX VrefLevel [Byte0]: 65
3473 12:11:44.641055 [Byte1]: 65
3474 12:11:44.645467
3475 12:11:44.645577 Set Vref, RX VrefLevel [Byte0]: 66
3476 12:11:44.648521 [Byte1]: 66
3477 12:11:44.653677
3478 12:11:44.653850 Final RX Vref Byte 0 = 51 to rank0
3479 12:11:44.656946 Final RX Vref Byte 1 = 60 to rank0
3480 12:11:44.660154 Final RX Vref Byte 0 = 51 to rank1
3481 12:11:44.663406 Final RX Vref Byte 1 = 60 to rank1==
3482 12:11:44.666531 Dram Type= 6, Freq= 0, CH_1, rank 0
3483 12:11:44.673478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 12:11:44.673613 ==
3485 12:11:44.673778 DQS Delay:
3486 12:11:44.673929 DQS0 = 0, DQS1 = 0
3487 12:11:44.676582 DQM Delay:
3488 12:11:44.676706 DQM0 = 116, DQM1 = 112
3489 12:11:44.679633 DQ Delay:
3490 12:11:44.683006 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =112
3491 12:11:44.686366 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =112
3492 12:11:44.690227 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3493 12:11:44.693462 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3494 12:11:44.693568
3495 12:11:44.693664
3496 12:11:44.703318 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3497 12:11:44.703467 CH1 RK0: MR19=403, MR18=4F7
3498 12:11:44.710222 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3499 12:11:44.710391
3500 12:11:44.713448 ----->DramcWriteLeveling(PI) begin...
3501 12:11:44.713590 ==
3502 12:11:44.716604 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 12:11:44.719656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 12:11:44.722902 ==
3505 12:11:44.723006 Write leveling (Byte 0): 24 => 24
3506 12:11:44.726561 Write leveling (Byte 1): 27 => 27
3507 12:11:44.729882 DramcWriteLeveling(PI) end<-----
3508 12:11:44.729989
3509 12:11:44.730089 ==
3510 12:11:44.733154 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 12:11:44.739572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 12:11:44.739683 ==
3513 12:11:44.739784 [Gating] SW mode calibration
3514 12:11:44.749695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3515 12:11:44.752942 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3516 12:11:44.759327 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3517 12:11:44.762614 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 12:11:44.766278 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 12:11:44.772592 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 12:11:44.775830 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 12:11:44.779638 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 12:11:44.786023 0 15 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
3523 12:11:44.789270 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
3524 12:11:44.792535 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 12:11:44.798950 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 12:11:44.802108 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 12:11:44.805804 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 12:11:44.812633 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 12:11:44.815681 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 12:11:44.818938 1 0 24 | B1->B0 | 3838 2828 | 0 0 | (0 0) (0 0)
3531 12:11:44.825282 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 12:11:44.828940 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 12:11:44.832228 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 12:11:44.839009 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 12:11:44.842216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 12:11:44.845343 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 12:11:44.851826 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 12:11:44.855047 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3539 12:11:44.858233 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3540 12:11:44.864656 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:11:44.868442 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:11:44.871600 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:11:44.877846 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:11:44.881689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:11:44.884907 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:11:44.891336 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:11:44.894425 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:11:44.897685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 12:11:44.904902 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 12:11:44.908023 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 12:11:44.911074 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 12:11:44.917994 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 12:11:44.921046 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 12:11:44.924214 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3555 12:11:44.931271 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3556 12:11:44.931387 Total UI for P1: 0, mck2ui 16
3557 12:11:44.937656 best dqsien dly found for B1: ( 1, 3, 24)
3558 12:11:44.940950 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 12:11:44.944103 Total UI for P1: 0, mck2ui 16
3560 12:11:44.947322 best dqsien dly found for B0: ( 1, 3, 26)
3561 12:11:44.950541 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3562 12:11:44.954199 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3563 12:11:44.954328
3564 12:11:44.957392 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3565 12:11:44.960592 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3566 12:11:44.963929 [Gating] SW calibration Done
3567 12:11:44.964059 ==
3568 12:11:44.967210 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 12:11:44.970322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 12:11:44.973592 ==
3571 12:11:44.973698 RX Vref Scan: 0
3572 12:11:44.973817
3573 12:11:44.976817 RX Vref 0 -> 0, step: 1
3574 12:11:44.976935
3575 12:11:44.977038 RX Delay -40 -> 252, step: 8
3576 12:11:44.983663 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3577 12:11:44.987294 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3578 12:11:44.990475 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3579 12:11:44.993643 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3580 12:11:45.000088 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3581 12:11:45.003992 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3582 12:11:45.007089 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3583 12:11:45.010503 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3584 12:11:45.013757 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3585 12:11:45.016876 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3586 12:11:45.023642 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3587 12:11:45.026680 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3588 12:11:45.030355 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3589 12:11:45.033611 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3590 12:11:45.039753 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3591 12:11:45.042930 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3592 12:11:45.043050 ==
3593 12:11:45.046707 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 12:11:45.049937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 12:11:45.050071 ==
3596 12:11:45.053216 DQS Delay:
3597 12:11:45.053339 DQS0 = 0, DQS1 = 0
3598 12:11:45.053451 DQM Delay:
3599 12:11:45.056443 DQM0 = 116, DQM1 = 110
3600 12:11:45.056586 DQ Delay:
3601 12:11:45.059700 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3602 12:11:45.062879 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3603 12:11:45.066160 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3604 12:11:45.072690 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3605 12:11:45.072809
3606 12:11:45.072905
3607 12:11:45.073007 ==
3608 12:11:45.075985 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 12:11:45.079175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 12:11:45.079257 ==
3611 12:11:45.079328
3612 12:11:45.079390
3613 12:11:45.082953 TX Vref Scan disable
3614 12:11:45.083059 == TX Byte 0 ==
3615 12:11:45.089167 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3616 12:11:45.092927 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3617 12:11:45.093040 == TX Byte 1 ==
3618 12:11:45.099225 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 12:11:45.102526 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 12:11:45.102656 ==
3621 12:11:45.105697 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 12:11:45.108969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 12:11:45.109084 ==
3624 12:11:45.122595 TX Vref=22, minBit 8, minWin=25, winSum=427
3625 12:11:45.125584 TX Vref=24, minBit 15, minWin=26, winSum=433
3626 12:11:45.128860 TX Vref=26, minBit 9, minWin=26, winSum=434
3627 12:11:45.131846 TX Vref=28, minBit 9, minWin=26, winSum=436
3628 12:11:45.135154 TX Vref=30, minBit 10, minWin=26, winSum=438
3629 12:11:45.141962 TX Vref=32, minBit 7, minWin=26, winSum=432
3630 12:11:45.145206 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
3631 12:11:45.148376
3632 12:11:45.148500 Final TX Range 1 Vref 30
3633 12:11:45.148618
3634 12:11:45.148712 ==
3635 12:11:45.151581 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 12:11:45.158068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 12:11:45.158193 ==
3638 12:11:45.158317
3639 12:11:45.158413
3640 12:11:45.158522 TX Vref Scan disable
3641 12:11:45.162568 == TX Byte 0 ==
3642 12:11:45.165599 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3643 12:11:45.172008 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3644 12:11:45.172148 == TX Byte 1 ==
3645 12:11:45.175271 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3646 12:11:45.182347 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3647 12:11:45.182466
3648 12:11:45.182582 [DATLAT]
3649 12:11:45.182675 Freq=1200, CH1 RK1
3650 12:11:45.182789
3651 12:11:45.184929 DATLAT Default: 0xd
3652 12:11:45.188790 0, 0xFFFF, sum = 0
3653 12:11:45.188908 1, 0xFFFF, sum = 0
3654 12:11:45.191810 2, 0xFFFF, sum = 0
3655 12:11:45.191928 3, 0xFFFF, sum = 0
3656 12:11:45.194915 4, 0xFFFF, sum = 0
3657 12:11:45.195022 5, 0xFFFF, sum = 0
3658 12:11:45.198602 6, 0xFFFF, sum = 0
3659 12:11:45.198709 7, 0xFFFF, sum = 0
3660 12:11:45.201874 8, 0xFFFF, sum = 0
3661 12:11:45.201978 9, 0xFFFF, sum = 0
3662 12:11:45.205154 10, 0xFFFF, sum = 0
3663 12:11:45.205240 11, 0xFFFF, sum = 0
3664 12:11:45.208416 12, 0x0, sum = 1
3665 12:11:45.208562 13, 0x0, sum = 2
3666 12:11:45.211469 14, 0x0, sum = 3
3667 12:11:45.211580 15, 0x0, sum = 4
3668 12:11:45.214810 best_step = 13
3669 12:11:45.214923
3670 12:11:45.215047 ==
3671 12:11:45.217925 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 12:11:45.221641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 12:11:45.221764 ==
3674 12:11:45.224944 RX Vref Scan: 0
3675 12:11:45.225058
3676 12:11:45.225201 RX Vref 0 -> 0, step: 1
3677 12:11:45.225295
3678 12:11:45.228046 RX Delay -21 -> 252, step: 4
3679 12:11:45.234321 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3680 12:11:45.238023 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3681 12:11:45.241232 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3682 12:11:45.244220 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3683 12:11:45.251309 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3684 12:11:45.254502 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3685 12:11:45.257807 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3686 12:11:45.261042 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3687 12:11:45.264334 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3688 12:11:45.267524 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3689 12:11:45.274589 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3690 12:11:45.277814 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3691 12:11:45.280966 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3692 12:11:45.284276 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3693 12:11:45.290560 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3694 12:11:45.294443 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3695 12:11:45.294621 ==
3696 12:11:45.297555 Dram Type= 6, Freq= 0, CH_1, rank 1
3697 12:11:45.300829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3698 12:11:45.300971 ==
3699 12:11:45.304009 DQS Delay:
3700 12:11:45.304153 DQS0 = 0, DQS1 = 0
3701 12:11:45.304251 DQM Delay:
3702 12:11:45.307213 DQM0 = 117, DQM1 = 110
3703 12:11:45.307320 DQ Delay:
3704 12:11:45.310958 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =114
3705 12:11:45.314224 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3706 12:11:45.317390 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3707 12:11:45.323889 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =120
3708 12:11:45.324003
3709 12:11:45.324104
3710 12:11:45.330800 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3711 12:11:45.333937 CH1 RK1: MR19=303, MR18=F3ED
3712 12:11:45.340218 CH1_RK1: MR19=0x303, MR18=0xF3ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3713 12:11:45.343896 [RxdqsGatingPostProcess] freq 1200
3714 12:11:45.346972 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3715 12:11:45.350171 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 12:11:45.353574 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 12:11:45.356882 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 12:11:45.360123 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 12:11:45.363406 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 12:11:45.367249 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 12:11:45.370466 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 12:11:45.373605 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 12:11:45.376829 Pre-setting of DQS Precalculation
3724 12:11:45.380054 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3725 12:11:45.390309 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3726 12:11:45.396437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3727 12:11:45.396592
3728 12:11:45.396692
3729 12:11:45.400215 [Calibration Summary] 2400 Mbps
3730 12:11:45.400322 CH 0, Rank 0
3731 12:11:45.403319 SW Impedance : PASS
3732 12:11:45.403430 DUTY Scan : NO K
3733 12:11:45.406473 ZQ Calibration : PASS
3734 12:11:45.410159 Jitter Meter : NO K
3735 12:11:45.410275 CBT Training : PASS
3736 12:11:45.413393 Write leveling : PASS
3737 12:11:45.416574 RX DQS gating : PASS
3738 12:11:45.416678 RX DQ/DQS(RDDQC) : PASS
3739 12:11:45.419824 TX DQ/DQS : PASS
3740 12:11:45.423054 RX DATLAT : PASS
3741 12:11:45.423161 RX DQ/DQS(Engine): PASS
3742 12:11:45.426258 TX OE : NO K
3743 12:11:45.426373 All Pass.
3744 12:11:45.426469
3745 12:11:45.429451 CH 0, Rank 1
3746 12:11:45.429559 SW Impedance : PASS
3747 12:11:45.433234 DUTY Scan : NO K
3748 12:11:45.436429 ZQ Calibration : PASS
3749 12:11:45.436563 Jitter Meter : NO K
3750 12:11:45.439600 CBT Training : PASS
3751 12:11:45.443221 Write leveling : PASS
3752 12:11:45.443336 RX DQS gating : PASS
3753 12:11:45.446269 RX DQ/DQS(RDDQC) : PASS
3754 12:11:45.446383 TX DQ/DQS : PASS
3755 12:11:45.449423 RX DATLAT : PASS
3756 12:11:45.453060 RX DQ/DQS(Engine): PASS
3757 12:11:45.453180 TX OE : NO K
3758 12:11:45.456251 All Pass.
3759 12:11:45.456362
3760 12:11:45.456455 CH 1, Rank 0
3761 12:11:45.459530 SW Impedance : PASS
3762 12:11:45.459634 DUTY Scan : NO K
3763 12:11:45.462707 ZQ Calibration : PASS
3764 12:11:45.465901 Jitter Meter : NO K
3765 12:11:45.466008 CBT Training : PASS
3766 12:11:45.469122 Write leveling : PASS
3767 12:11:45.472475 RX DQS gating : PASS
3768 12:11:45.472614 RX DQ/DQS(RDDQC) : PASS
3769 12:11:45.476253 TX DQ/DQS : PASS
3770 12:11:45.479408 RX DATLAT : PASS
3771 12:11:45.479533 RX DQ/DQS(Engine): PASS
3772 12:11:45.482575 TX OE : NO K
3773 12:11:45.482686 All Pass.
3774 12:11:45.482787
3775 12:11:45.485787 CH 1, Rank 1
3776 12:11:45.485890 SW Impedance : PASS
3777 12:11:45.489015 DUTY Scan : NO K
3778 12:11:45.492246 ZQ Calibration : PASS
3779 12:11:45.492350 Jitter Meter : NO K
3780 12:11:45.496100 CBT Training : PASS
3781 12:11:45.499287 Write leveling : PASS
3782 12:11:45.499402 RX DQS gating : PASS
3783 12:11:45.502302 RX DQ/DQS(RDDQC) : PASS
3784 12:11:45.506001 TX DQ/DQS : PASS
3785 12:11:45.506114 RX DATLAT : PASS
3786 12:11:45.509285 RX DQ/DQS(Engine): PASS
3787 12:11:45.512556 TX OE : NO K
3788 12:11:45.512674 All Pass.
3789 12:11:45.512771
3790 12:11:45.512890 DramC Write-DBI off
3791 12:11:45.515839 PER_BANK_REFRESH: Hybrid Mode
3792 12:11:45.519043 TX_TRACKING: ON
3793 12:11:45.525631 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3794 12:11:45.528855 [FAST_K] Save calibration result to emmc
3795 12:11:45.535325 dramc_set_vcore_voltage set vcore to 650000
3796 12:11:45.535457 Read voltage for 600, 5
3797 12:11:45.538431 Vio18 = 0
3798 12:11:45.538540 Vcore = 650000
3799 12:11:45.538643 Vdram = 0
3800 12:11:45.542199 Vddq = 0
3801 12:11:45.542317 Vmddr = 0
3802 12:11:45.545425 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3803 12:11:45.552143 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3804 12:11:45.555169 MEM_TYPE=3, freq_sel=19
3805 12:11:45.558406 sv_algorithm_assistance_LP4_1600
3806 12:11:45.561623 ============ PULL DRAM RESETB DOWN ============
3807 12:11:45.564880 ========== PULL DRAM RESETB DOWN end =========
3808 12:11:45.568692 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3809 12:11:45.571895 ===================================
3810 12:11:45.574992 LPDDR4 DRAM CONFIGURATION
3811 12:11:45.578314 ===================================
3812 12:11:45.581459 EX_ROW_EN[0] = 0x0
3813 12:11:45.581582 EX_ROW_EN[1] = 0x0
3814 12:11:45.584641 LP4Y_EN = 0x0
3815 12:11:45.584748 WORK_FSP = 0x0
3816 12:11:45.587927 WL = 0x2
3817 12:11:45.588041 RL = 0x2
3818 12:11:45.591785 BL = 0x2
3819 12:11:45.594970 RPST = 0x0
3820 12:11:45.595092 RD_PRE = 0x0
3821 12:11:45.598182 WR_PRE = 0x1
3822 12:11:45.598288 WR_PST = 0x0
3823 12:11:45.601370 DBI_WR = 0x0
3824 12:11:45.601490 DBI_RD = 0x0
3825 12:11:45.604594 OTF = 0x1
3826 12:11:45.607789 ===================================
3827 12:11:45.611542 ===================================
3828 12:11:45.611663 ANA top config
3829 12:11:45.614862 ===================================
3830 12:11:45.618029 DLL_ASYNC_EN = 0
3831 12:11:45.621206 ALL_SLAVE_EN = 1
3832 12:11:45.621333 NEW_RANK_MODE = 1
3833 12:11:45.624551 DLL_IDLE_MODE = 1
3834 12:11:45.627632 LP45_APHY_COMB_EN = 1
3835 12:11:45.630906 TX_ODT_DIS = 1
3836 12:11:45.634078 NEW_8X_MODE = 1
3837 12:11:45.637898 ===================================
3838 12:11:45.638008 ===================================
3839 12:11:45.641059 data_rate = 1200
3840 12:11:45.644111 CKR = 1
3841 12:11:45.647387 DQ_P2S_RATIO = 8
3842 12:11:45.650956 ===================================
3843 12:11:45.654092 CA_P2S_RATIO = 8
3844 12:11:45.657265 DQ_CA_OPEN = 0
3845 12:11:45.660406 DQ_SEMI_OPEN = 0
3846 12:11:45.660527 CA_SEMI_OPEN = 0
3847 12:11:45.664310 CA_FULL_RATE = 0
3848 12:11:45.667569 DQ_CKDIV4_EN = 1
3849 12:11:45.670874 CA_CKDIV4_EN = 1
3850 12:11:45.674187 CA_PREDIV_EN = 0
3851 12:11:45.677364 PH8_DLY = 0
3852 12:11:45.677491 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3853 12:11:45.680602 DQ_AAMCK_DIV = 4
3854 12:11:45.683893 CA_AAMCK_DIV = 4
3855 12:11:45.686970 CA_ADMCK_DIV = 4
3856 12:11:45.690287 DQ_TRACK_CA_EN = 0
3857 12:11:45.693477 CA_PICK = 600
3858 12:11:45.696681 CA_MCKIO = 600
3859 12:11:45.696794 MCKIO_SEMI = 0
3860 12:11:45.700367 PLL_FREQ = 2288
3861 12:11:45.703580 DQ_UI_PI_RATIO = 32
3862 12:11:45.706724 CA_UI_PI_RATIO = 0
3863 12:11:45.709919 ===================================
3864 12:11:45.713601 ===================================
3865 12:11:45.716920 memory_type:LPDDR4
3866 12:11:45.717043 GP_NUM : 10
3867 12:11:45.720115 SRAM_EN : 1
3868 12:11:45.723358 MD32_EN : 0
3869 12:11:45.726597 ===================================
3870 12:11:45.726710 [ANA_INIT] >>>>>>>>>>>>>>
3871 12:11:45.729872 <<<<<< [CONFIGURE PHASE]: ANA_TX
3872 12:11:45.733166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3873 12:11:45.736329 ===================================
3874 12:11:45.739614 data_rate = 1200,PCW = 0X5800
3875 12:11:45.742715 ===================================
3876 12:11:45.746069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3877 12:11:45.752990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 12:11:45.756027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 12:11:45.762909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3880 12:11:45.766061 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3881 12:11:45.769337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3882 12:11:45.772646 [ANA_INIT] flow start
3883 12:11:45.772760 [ANA_INIT] PLL >>>>>>>>
3884 12:11:45.775955 [ANA_INIT] PLL <<<<<<<<
3885 12:11:45.779184 [ANA_INIT] MIDPI >>>>>>>>
3886 12:11:45.779299 [ANA_INIT] MIDPI <<<<<<<<
3887 12:11:45.782474 [ANA_INIT] DLL >>>>>>>>
3888 12:11:45.785672 [ANA_INIT] flow end
3889 12:11:45.788796 ============ LP4 DIFF to SE enter ============
3890 12:11:45.792608 ============ LP4 DIFF to SE exit ============
3891 12:11:45.795821 [ANA_INIT] <<<<<<<<<<<<<
3892 12:11:45.799052 [Flow] Enable top DCM control >>>>>
3893 12:11:45.802195 [Flow] Enable top DCM control <<<<<
3894 12:11:45.805483 Enable DLL master slave shuffle
3895 12:11:45.811870 ==============================================================
3896 12:11:45.811985 Gating Mode config
3897 12:11:45.818646 ==============================================================
3898 12:11:45.818773 Config description:
3899 12:11:45.828951 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3900 12:11:45.835265 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3901 12:11:45.841831 SELPH_MODE 0: By rank 1: By Phase
3902 12:11:45.845065 ==============================================================
3903 12:11:45.848275 GAT_TRACK_EN = 1
3904 12:11:45.852082 RX_GATING_MODE = 2
3905 12:11:45.855278 RX_GATING_TRACK_MODE = 2
3906 12:11:45.858248 SELPH_MODE = 1
3907 12:11:45.861991 PICG_EARLY_EN = 1
3908 12:11:45.865251 VALID_LAT_VALUE = 1
3909 12:11:45.868459 ==============================================================
3910 12:11:45.871523 Enter into Gating configuration >>>>
3911 12:11:45.874721 Exit from Gating configuration <<<<
3912 12:11:45.877952 Enter into DVFS_PRE_config >>>>>
3913 12:11:45.891450 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3914 12:11:45.894675 Exit from DVFS_PRE_config <<<<<
3915 12:11:45.897895 Enter into PICG configuration >>>>
3916 12:11:45.901175 Exit from PICG configuration <<<<
3917 12:11:45.901288 [RX_INPUT] configuration >>>>>
3918 12:11:45.904335 [RX_INPUT] configuration <<<<<
3919 12:11:45.910924 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3920 12:11:45.917732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3921 12:11:45.920897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 12:11:45.927827 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 12:11:45.934050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 12:11:45.941074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 12:11:45.944299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3926 12:11:45.947602 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3927 12:11:45.954056 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3928 12:11:45.957211 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3929 12:11:45.960411 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3930 12:11:45.967035 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 12:11:45.970813 ===================================
3932 12:11:45.970927 LPDDR4 DRAM CONFIGURATION
3933 12:11:45.973809 ===================================
3934 12:11:45.976973 EX_ROW_EN[0] = 0x0
3935 12:11:45.977083 EX_ROW_EN[1] = 0x0
3936 12:11:45.980263 LP4Y_EN = 0x0
3937 12:11:45.983574 WORK_FSP = 0x0
3938 12:11:45.983686 WL = 0x2
3939 12:11:45.986878 RL = 0x2
3940 12:11:45.986988 BL = 0x2
3941 12:11:45.990165 RPST = 0x0
3942 12:11:45.990272 RD_PRE = 0x0
3943 12:11:45.993451 WR_PRE = 0x1
3944 12:11:45.993559 WR_PST = 0x0
3945 12:11:45.997264 DBI_WR = 0x0
3946 12:11:45.997370 DBI_RD = 0x0
3947 12:11:46.000378 OTF = 0x1
3948 12:11:46.003539 ===================================
3949 12:11:46.006658 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3950 12:11:46.009967 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3951 12:11:46.017017 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3952 12:11:46.020093 ===================================
3953 12:11:46.020218 LPDDR4 DRAM CONFIGURATION
3954 12:11:46.023193 ===================================
3955 12:11:46.026864 EX_ROW_EN[0] = 0x10
3956 12:11:46.026992 EX_ROW_EN[1] = 0x0
3957 12:11:46.030196 LP4Y_EN = 0x0
3958 12:11:46.030313 WORK_FSP = 0x0
3959 12:11:46.033376 WL = 0x2
3960 12:11:46.036536 RL = 0x2
3961 12:11:46.036650 BL = 0x2
3962 12:11:46.040242 RPST = 0x0
3963 12:11:46.040376 RD_PRE = 0x0
3964 12:11:46.043482 WR_PRE = 0x1
3965 12:11:46.043600 WR_PST = 0x0
3966 12:11:46.046647 DBI_WR = 0x0
3967 12:11:46.046762 DBI_RD = 0x0
3968 12:11:46.049861 OTF = 0x1
3969 12:11:46.053148 ===================================
3970 12:11:46.059634 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3971 12:11:46.063279 nWR fixed to 30
3972 12:11:46.063369 [ModeRegInit_LP4] CH0 RK0
3973 12:11:46.066404 [ModeRegInit_LP4] CH0 RK1
3974 12:11:46.069527 [ModeRegInit_LP4] CH1 RK0
3975 12:11:46.069613 [ModeRegInit_LP4] CH1 RK1
3976 12:11:46.072723 match AC timing 17
3977 12:11:46.076439 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3978 12:11:46.082807 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3979 12:11:46.086073 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3980 12:11:46.089359 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3981 12:11:46.096348 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3982 12:11:46.096464 ==
3983 12:11:46.099626 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 12:11:46.102847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 12:11:46.102984 ==
3986 12:11:46.109293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 12:11:46.115707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3988 12:11:46.118899 [CA 0] Center 36 (6~66) winsize 61
3989 12:11:46.122174 [CA 1] Center 36 (6~66) winsize 61
3990 12:11:46.125338 [CA 2] Center 34 (4~65) winsize 62
3991 12:11:46.129192 [CA 3] Center 34 (4~65) winsize 62
3992 12:11:46.132355 [CA 4] Center 33 (3~64) winsize 62
3993 12:11:46.135502 [CA 5] Center 33 (3~64) winsize 62
3994 12:11:46.135622
3995 12:11:46.138818 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3996 12:11:46.138929
3997 12:11:46.142020 [CATrainingPosCal] consider 1 rank data
3998 12:11:46.145174 u2DelayCellTimex100 = 270/100 ps
3999 12:11:46.148832 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4000 12:11:46.151937 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4001 12:11:46.155162 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4002 12:11:46.158364 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 12:11:46.161574 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4004 12:11:46.168489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4005 12:11:46.168601
4006 12:11:46.171608 CA PerBit enable=1, Macro0, CA PI delay=33
4007 12:11:46.171695
4008 12:11:46.175150 [CBTSetCACLKResult] CA Dly = 33
4009 12:11:46.175240 CS Dly: 5 (0~36)
4010 12:11:46.175306 ==
4011 12:11:46.178240 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 12:11:46.181883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 12:11:46.184946 ==
4014 12:11:46.188193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 12:11:46.194575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4016 12:11:46.198429 [CA 0] Center 36 (6~66) winsize 61
4017 12:11:46.201760 [CA 1] Center 36 (6~66) winsize 61
4018 12:11:46.204821 [CA 2] Center 34 (4~64) winsize 61
4019 12:11:46.208072 [CA 3] Center 34 (4~64) winsize 61
4020 12:11:46.211210 [CA 4] Center 33 (3~64) winsize 62
4021 12:11:46.214515 [CA 5] Center 33 (2~64) winsize 63
4022 12:11:46.214629
4023 12:11:46.217711 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4024 12:11:46.217823
4025 12:11:46.221499 [CATrainingPosCal] consider 2 rank data
4026 12:11:46.224803 u2DelayCellTimex100 = 270/100 ps
4027 12:11:46.228006 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4028 12:11:46.231285 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4029 12:11:46.234489 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4030 12:11:46.240712 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4031 12:11:46.244541 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4032 12:11:46.247670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 12:11:46.247777
4034 12:11:46.250936 CA PerBit enable=1, Macro0, CA PI delay=33
4035 12:11:46.251048
4036 12:11:46.254118 [CBTSetCACLKResult] CA Dly = 33
4037 12:11:46.254229 CS Dly: 5 (0~36)
4038 12:11:46.254329
4039 12:11:46.257253 ----->DramcWriteLeveling(PI) begin...
4040 12:11:46.260522 ==
4041 12:11:46.264351 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 12:11:46.267612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 12:11:46.267690 ==
4044 12:11:46.270808 Write leveling (Byte 0): 32 => 32
4045 12:11:46.273903 Write leveling (Byte 1): 31 => 31
4046 12:11:46.276918 DramcWriteLeveling(PI) end<-----
4047 12:11:46.277038
4048 12:11:46.277138 ==
4049 12:11:46.280607 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 12:11:46.283664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 12:11:46.283772 ==
4052 12:11:46.286870 [Gating] SW mode calibration
4053 12:11:46.293947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4054 12:11:46.300299 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4055 12:11:46.303422 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 12:11:46.307222 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 12:11:46.313601 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 12:11:46.316868 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4059 12:11:46.320242 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
4060 12:11:46.326586 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 12:11:46.329783 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 12:11:46.333520 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 12:11:46.339704 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 12:11:46.342914 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 12:11:46.346585 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 12:11:46.352986 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4067 12:11:46.356196 0 10 16 | B1->B0 | 3535 4242 | 1 1 | (0 0) (0 0)
4068 12:11:46.359555 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 12:11:46.366044 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 12:11:46.369873 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 12:11:46.373166 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 12:11:46.379391 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 12:11:46.382995 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 12:11:46.386126 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4075 12:11:46.392962 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4076 12:11:46.396094 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:11:46.399291 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:11:46.405721 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:11:46.408966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:11:46.412326 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:11:46.419046 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:11:46.422321 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:11:46.425640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:11:46.432014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 12:11:46.435889 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 12:11:46.439035 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 12:11:46.445341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 12:11:46.448998 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 12:11:46.452279 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 12:11:46.458579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4091 12:11:46.461812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4092 12:11:46.465145 Total UI for P1: 0, mck2ui 16
4093 12:11:46.468315 best dqsien dly found for B0: ( 0, 13, 12)
4094 12:11:46.471629 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 12:11:46.475444 Total UI for P1: 0, mck2ui 16
4096 12:11:46.478608 best dqsien dly found for B1: ( 0, 13, 14)
4097 12:11:46.481863 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4098 12:11:46.484864 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4099 12:11:46.484977
4100 12:11:46.488665 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4101 12:11:46.494895 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4102 12:11:46.495009 [Gating] SW calibration Done
4103 12:11:46.495113 ==
4104 12:11:46.498659 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 12:11:46.505144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 12:11:46.505332 ==
4107 12:11:46.505456 RX Vref Scan: 0
4108 12:11:46.505600
4109 12:11:46.508383 RX Vref 0 -> 0, step: 1
4110 12:11:46.508508
4111 12:11:46.511494 RX Delay -230 -> 252, step: 16
4112 12:11:46.514683 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4113 12:11:46.517949 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4114 12:11:46.524532 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4115 12:11:46.527802 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4116 12:11:46.531056 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4117 12:11:46.534383 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4118 12:11:46.541322 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4119 12:11:46.544462 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4120 12:11:46.547645 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4121 12:11:46.550823 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4122 12:11:46.557742 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4123 12:11:46.560907 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4124 12:11:46.564015 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4125 12:11:46.567163 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4126 12:11:46.573845 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4127 12:11:46.576990 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4128 12:11:46.577074 ==
4129 12:11:46.580814 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 12:11:46.583952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 12:11:46.584042 ==
4132 12:11:46.587248 DQS Delay:
4133 12:11:46.587372 DQS0 = 0, DQS1 = 0
4134 12:11:46.587471 DQM Delay:
4135 12:11:46.590219 DQM0 = 41, DQM1 = 30
4136 12:11:46.590325 DQ Delay:
4137 12:11:46.593746 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4138 12:11:46.596921 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4139 12:11:46.600041 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4140 12:11:46.603903 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4141 12:11:46.604025
4142 12:11:46.604126
4143 12:11:46.604218 ==
4144 12:11:46.607002 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 12:11:46.613572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 12:11:46.613697 ==
4147 12:11:46.613798
4148 12:11:46.613898
4149 12:11:46.613992 TX Vref Scan disable
4150 12:11:46.616852 == TX Byte 0 ==
4151 12:11:46.620729 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4152 12:11:46.627081 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4153 12:11:46.627194 == TX Byte 1 ==
4154 12:11:46.630299 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4155 12:11:46.636940 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4156 12:11:46.637055 ==
4157 12:11:46.640203 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 12:11:46.643356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 12:11:46.643461 ==
4160 12:11:46.643554
4161 12:11:46.643652
4162 12:11:46.647039 TX Vref Scan disable
4163 12:11:46.650251 == TX Byte 0 ==
4164 12:11:46.653446 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4165 12:11:46.656493 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4166 12:11:46.659871 == TX Byte 1 ==
4167 12:11:46.663696 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4168 12:11:46.667003 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4169 12:11:46.667095
4170 12:11:46.667166 [DATLAT]
4171 12:11:46.669883 Freq=600, CH0 RK0
4172 12:11:46.669974
4173 12:11:46.673016 DATLAT Default: 0x9
4174 12:11:46.673136 0, 0xFFFF, sum = 0
4175 12:11:46.676324 1, 0xFFFF, sum = 0
4176 12:11:46.676456 2, 0xFFFF, sum = 0
4177 12:11:46.679622 3, 0xFFFF, sum = 0
4178 12:11:46.679713 4, 0xFFFF, sum = 0
4179 12:11:46.682924 5, 0xFFFF, sum = 0
4180 12:11:46.683003 6, 0xFFFF, sum = 0
4181 12:11:46.686142 7, 0xFFFF, sum = 0
4182 12:11:46.686221 8, 0x0, sum = 1
4183 12:11:46.689935 9, 0x0, sum = 2
4184 12:11:46.690050 10, 0x0, sum = 3
4185 12:11:46.692999 11, 0x0, sum = 4
4186 12:11:46.693087 best_step = 9
4187 12:11:46.693158
4188 12:11:46.693221 ==
4189 12:11:46.696119 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 12:11:46.699890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 12:11:46.700002 ==
4192 12:11:46.703035 RX Vref Scan: 1
4193 12:11:46.703150
4194 12:11:46.706271 RX Vref 0 -> 0, step: 1
4195 12:11:46.706377
4196 12:11:46.706481 RX Delay -195 -> 252, step: 8
4197 12:11:46.706594
4198 12:11:46.709514 Set Vref, RX VrefLevel [Byte0]: 59
4199 12:11:46.712710 [Byte1]: 56
4200 12:11:46.717336
4201 12:11:46.717445 Final RX Vref Byte 0 = 59 to rank0
4202 12:11:46.721206 Final RX Vref Byte 1 = 56 to rank0
4203 12:11:46.724404 Final RX Vref Byte 0 = 59 to rank1
4204 12:11:46.727648 Final RX Vref Byte 1 = 56 to rank1==
4205 12:11:46.730859 Dram Type= 6, Freq= 0, CH_0, rank 0
4206 12:11:46.737303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 12:11:46.737433 ==
4208 12:11:46.737553 DQS Delay:
4209 12:11:46.740999 DQS0 = 0, DQS1 = 0
4210 12:11:46.741129 DQM Delay:
4211 12:11:46.741224 DQM0 = 43, DQM1 = 34
4212 12:11:46.744322 DQ Delay:
4213 12:11:46.747489 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4214 12:11:46.750694 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4215 12:11:46.753872 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4216 12:11:46.757041 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4217 12:11:46.757176
4218 12:11:46.757302
4219 12:11:46.763945 [DQSOSCAuto] RK0, (LSB)MR18= 0x643b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4220 12:11:46.767208 CH0 RK0: MR19=808, MR18=643B
4221 12:11:46.773665 CH0_RK0: MR19=0x808, MR18=0x643B, DQSOSC=391, MR23=63, INC=171, DEC=114
4222 12:11:46.773807
4223 12:11:46.776947 ----->DramcWriteLeveling(PI) begin...
4224 12:11:46.777038 ==
4225 12:11:46.780216 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 12:11:46.783413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 12:11:46.783553 ==
4228 12:11:46.787226 Write leveling (Byte 0): 32 => 32
4229 12:11:46.790519 Write leveling (Byte 1): 32 => 32
4230 12:11:46.793722 DramcWriteLeveling(PI) end<-----
4231 12:11:46.793828
4232 12:11:46.793922 ==
4233 12:11:46.797130 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 12:11:46.800168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 12:11:46.803316 ==
4236 12:11:46.803422 [Gating] SW mode calibration
4237 12:11:46.813559 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4238 12:11:46.816797 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4239 12:11:46.820032 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 12:11:46.826574 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 12:11:46.829872 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 12:11:46.833124 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 12:11:46.840064 0 9 16 | B1->B0 | 2b2b 2525 | 0 0 | (1 1) (0 0)
4244 12:11:46.843272 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 12:11:46.846441 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 12:11:46.852825 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 12:11:46.856591 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 12:11:46.859789 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 12:11:46.865964 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 12:11:46.869706 0 10 12 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
4251 12:11:46.872838 0 10 16 | B1->B0 | 3e3e 3d3d | 0 0 | (0 0) (0 0)
4252 12:11:46.879114 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 12:11:46.882265 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 12:11:46.886165 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 12:11:46.892762 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 12:11:46.895979 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 12:11:46.899095 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 12:11:46.905956 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4259 12:11:46.909068 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4260 12:11:46.912276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:11:46.918754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:11:46.922075 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:11:46.925257 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:11:46.932257 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:11:46.935600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:11:46.938855 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:11:46.944950 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:11:46.948828 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 12:11:46.952012 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 12:11:46.958420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 12:11:46.961536 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 12:11:46.965299 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 12:11:46.971433 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 12:11:46.974571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 12:11:46.978312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 12:11:46.981654 Total UI for P1: 0, mck2ui 16
4277 12:11:46.984965 best dqsien dly found for B0: ( 0, 13, 14)
4278 12:11:46.988260 Total UI for P1: 0, mck2ui 16
4279 12:11:46.991554 best dqsien dly found for B1: ( 0, 13, 14)
4280 12:11:46.994841 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4281 12:11:46.998065 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4282 12:11:47.001296
4283 12:11:47.004492 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4284 12:11:47.007566 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4285 12:11:47.010698 [Gating] SW calibration Done
4286 12:11:47.010806 ==
4287 12:11:47.014356 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 12:11:47.017427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 12:11:47.017595 ==
4290 12:11:47.020645 RX Vref Scan: 0
4291 12:11:47.020757
4292 12:11:47.020907 RX Vref 0 -> 0, step: 1
4293 12:11:47.021026
4294 12:11:47.023922 RX Delay -230 -> 252, step: 16
4295 12:11:47.027126 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4296 12:11:47.034141 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4297 12:11:47.037400 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4298 12:11:47.040581 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4299 12:11:47.043769 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4300 12:11:47.050260 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4301 12:11:47.053515 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4302 12:11:47.056672 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4303 12:11:47.059943 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4304 12:11:47.066451 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4305 12:11:47.069541 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4306 12:11:47.072784 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4307 12:11:47.076389 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4308 12:11:47.083333 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4309 12:11:47.086533 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4310 12:11:47.089822 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4311 12:11:47.089901 ==
4312 12:11:47.093040 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:11:47.096164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:11:47.099415 ==
4315 12:11:47.099519 DQS Delay:
4316 12:11:47.099586 DQS0 = 0, DQS1 = 0
4317 12:11:47.102810 DQM Delay:
4318 12:11:47.102931 DQM0 = 42, DQM1 = 34
4319 12:11:47.105929 DQ Delay:
4320 12:11:47.109043 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4321 12:11:47.109152 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4322 12:11:47.112650 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4323 12:11:47.119398 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4324 12:11:47.119522
4325 12:11:47.119631
4326 12:11:47.119726 ==
4327 12:11:47.122384 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 12:11:47.125585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 12:11:47.125710 ==
4330 12:11:47.125815
4331 12:11:47.125912
4332 12:11:47.129346 TX Vref Scan disable
4333 12:11:47.129460 == TX Byte 0 ==
4334 12:11:47.135709 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4335 12:11:47.138943 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4336 12:11:47.139054 == TX Byte 1 ==
4337 12:11:47.145416 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4338 12:11:47.148602 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4339 12:11:47.148713 ==
4340 12:11:47.151949 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 12:11:47.155674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 12:11:47.155813 ==
4343 12:11:47.155955
4344 12:11:47.158917
4345 12:11:47.159022 TX Vref Scan disable
4346 12:11:47.162163 == TX Byte 0 ==
4347 12:11:47.165388 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4348 12:11:47.172270 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4349 12:11:47.172396 == TX Byte 1 ==
4350 12:11:47.175363 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4351 12:11:47.182150 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4352 12:11:47.182263
4353 12:11:47.182363 [DATLAT]
4354 12:11:47.182469 Freq=600, CH0 RK1
4355 12:11:47.182559
4356 12:11:47.185292 DATLAT Default: 0x9
4357 12:11:47.188501 0, 0xFFFF, sum = 0
4358 12:11:47.188623 1, 0xFFFF, sum = 0
4359 12:11:47.191628 2, 0xFFFF, sum = 0
4360 12:11:47.191733 3, 0xFFFF, sum = 0
4361 12:11:47.194859 4, 0xFFFF, sum = 0
4362 12:11:47.194960 5, 0xFFFF, sum = 0
4363 12:11:47.198037 6, 0xFFFF, sum = 0
4364 12:11:47.198138 7, 0xFFFF, sum = 0
4365 12:11:47.201863 8, 0x0, sum = 1
4366 12:11:47.201964 9, 0x0, sum = 2
4367 12:11:47.204970 10, 0x0, sum = 3
4368 12:11:47.205084 11, 0x0, sum = 4
4369 12:11:47.205177 best_step = 9
4370 12:11:47.205275
4371 12:11:47.208226 ==
4372 12:11:47.211514 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 12:11:47.214588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 12:11:47.214712 ==
4375 12:11:47.214809 RX Vref Scan: 0
4376 12:11:47.214912
4377 12:11:47.218363 RX Vref 0 -> 0, step: 1
4378 12:11:47.218470
4379 12:11:47.221481 RX Delay -195 -> 252, step: 8
4380 12:11:47.228312 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4381 12:11:47.231427 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4382 12:11:47.234457 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4383 12:11:47.237599 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4384 12:11:47.244548 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4385 12:11:47.247793 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4386 12:11:47.250959 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4387 12:11:47.254705 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4388 12:11:47.257937 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4389 12:11:47.264575 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4390 12:11:47.267812 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4391 12:11:47.270990 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4392 12:11:47.274391 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4393 12:11:47.280809 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4394 12:11:47.284034 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4395 12:11:47.287071 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4396 12:11:47.287172 ==
4397 12:11:47.290330 Dram Type= 6, Freq= 0, CH_0, rank 1
4398 12:11:47.297314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 12:11:47.297442 ==
4400 12:11:47.297543 DQS Delay:
4401 12:11:47.297617 DQS0 = 0, DQS1 = 0
4402 12:11:47.300395 DQM Delay:
4403 12:11:47.300520 DQM0 = 41, DQM1 = 37
4404 12:11:47.303621 DQ Delay:
4405 12:11:47.306874 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4406 12:11:47.310630 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4407 12:11:47.313738 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4408 12:11:47.316895 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4409 12:11:47.317022
4410 12:11:47.317122
4411 12:11:47.323835 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f12, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4412 12:11:47.326979 CH0 RK1: MR19=808, MR18=5F12
4413 12:11:47.333201 CH0_RK1: MR19=0x808, MR18=0x5F12, DQSOSC=391, MR23=63, INC=171, DEC=114
4414 12:11:47.336767 [RxdqsGatingPostProcess] freq 600
4415 12:11:47.339966 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4416 12:11:47.343007 Pre-setting of DQS Precalculation
4417 12:11:47.350081 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4418 12:11:47.350164 ==
4419 12:11:47.353354 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 12:11:47.356414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 12:11:47.356527 ==
4422 12:11:47.362938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4423 12:11:47.369901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4424 12:11:47.373227 [CA 0] Center 35 (5~66) winsize 62
4425 12:11:47.376326 [CA 1] Center 35 (5~66) winsize 62
4426 12:11:47.379595 [CA 2] Center 34 (4~65) winsize 62
4427 12:11:47.382573 [CA 3] Center 33 (3~64) winsize 62
4428 12:11:47.385790 [CA 4] Center 34 (4~65) winsize 62
4429 12:11:47.389062 [CA 5] Center 33 (3~64) winsize 62
4430 12:11:47.389199
4431 12:11:47.392725 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4432 12:11:47.392851
4433 12:11:47.395859 [CATrainingPosCal] consider 1 rank data
4434 12:11:47.399183 u2DelayCellTimex100 = 270/100 ps
4435 12:11:47.402399 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 12:11:47.405622 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4437 12:11:47.408702 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 12:11:47.412603 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 12:11:47.415803 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4440 12:11:47.422224 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 12:11:47.422338
4442 12:11:47.425343 CA PerBit enable=1, Macro0, CA PI delay=33
4443 12:11:47.425468
4444 12:11:47.429067 [CBTSetCACLKResult] CA Dly = 33
4445 12:11:47.429173 CS Dly: 4 (0~35)
4446 12:11:47.429274 ==
4447 12:11:47.432154 Dram Type= 6, Freq= 0, CH_1, rank 1
4448 12:11:47.435293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 12:11:47.439099 ==
4450 12:11:47.442294 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 12:11:47.448413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4452 12:11:47.452238 [CA 0] Center 35 (5~66) winsize 62
4453 12:11:47.455462 [CA 1] Center 36 (6~66) winsize 61
4454 12:11:47.458832 [CA 2] Center 34 (4~65) winsize 62
4455 12:11:47.461937 [CA 3] Center 34 (3~65) winsize 63
4456 12:11:47.465017 [CA 4] Center 34 (4~65) winsize 62
4457 12:11:47.468176 [CA 5] Center 34 (3~65) winsize 63
4458 12:11:47.468283
4459 12:11:47.471958 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4460 12:11:47.472078
4461 12:11:47.475137 [CATrainingPosCal] consider 2 rank data
4462 12:11:47.478289 u2DelayCellTimex100 = 270/100 ps
4463 12:11:47.481535 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 12:11:47.484864 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4465 12:11:47.487932 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 12:11:47.494876 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 12:11:47.498083 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 12:11:47.501199 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 12:11:47.501310
4470 12:11:47.504980 CA PerBit enable=1, Macro0, CA PI delay=33
4471 12:11:47.505094
4472 12:11:47.508347 [CBTSetCACLKResult] CA Dly = 33
4473 12:11:47.508462 CS Dly: 5 (0~37)
4474 12:11:47.508570
4475 12:11:47.511009 ----->DramcWriteLeveling(PI) begin...
4476 12:11:47.514325 ==
4477 12:11:47.518152 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 12:11:47.521362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 12:11:47.521471 ==
4480 12:11:47.524473 Write leveling (Byte 0): 28 => 28
4481 12:11:47.527590 Write leveling (Byte 1): 31 => 31
4482 12:11:47.530804 DramcWriteLeveling(PI) end<-----
4483 12:11:47.530882
4484 12:11:47.530954 ==
4485 12:11:47.534695 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 12:11:47.537814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 12:11:47.537898 ==
4488 12:11:47.540864 [Gating] SW mode calibration
4489 12:11:47.547775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4490 12:11:47.554173 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4491 12:11:47.557258 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 12:11:47.560497 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 12:11:47.567424 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 12:11:47.570590 0 9 12 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 0)
4495 12:11:47.574356 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 12:11:47.577609 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 12:11:47.584055 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 12:11:47.587381 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 12:11:47.590626 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 12:11:47.597456 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 12:11:47.600522 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 12:11:47.603705 0 10 12 | B1->B0 | 2d2d 3b3b | 0 0 | (0 0) (0 0)
4503 12:11:47.610694 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 12:11:47.613899 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 12:11:47.617090 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 12:11:47.623638 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 12:11:47.626866 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 12:11:47.630142 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:11:47.636589 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 12:11:47.640435 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4511 12:11:47.643553 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:11:47.650188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:11:47.653531 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:11:47.656698 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:11:47.663059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:11:47.666872 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:11:47.670115 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:11:47.676361 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:11:47.679588 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:11:47.682782 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:11:47.689814 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 12:11:47.693050 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 12:11:47.696204 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 12:11:47.702960 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 12:11:47.706233 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4526 12:11:47.709426 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 12:11:47.715871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 12:11:47.719779 Total UI for P1: 0, mck2ui 16
4529 12:11:47.722384 best dqsien dly found for B0: ( 0, 13, 14)
4530 12:11:47.725689 Total UI for P1: 0, mck2ui 16
4531 12:11:47.729500 best dqsien dly found for B1: ( 0, 13, 14)
4532 12:11:47.732768 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4533 12:11:47.735870 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4534 12:11:47.735952
4535 12:11:47.739124 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4536 12:11:47.742364 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4537 12:11:47.746065 [Gating] SW calibration Done
4538 12:11:47.746178 ==
4539 12:11:47.749285 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 12:11:47.752313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 12:11:47.752434 ==
4542 12:11:47.756027 RX Vref Scan: 0
4543 12:11:47.756146
4544 12:11:47.759010 RX Vref 0 -> 0, step: 1
4545 12:11:47.759117
4546 12:11:47.759212 RX Delay -230 -> 252, step: 16
4547 12:11:47.765449 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4548 12:11:47.768796 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4549 12:11:47.772002 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4550 12:11:47.775897 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4551 12:11:47.782281 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4552 12:11:47.785536 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4553 12:11:47.788689 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4554 12:11:47.791862 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4555 12:11:47.799008 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4556 12:11:47.802170 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4557 12:11:47.805330 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4558 12:11:47.808497 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4559 12:11:47.814862 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4560 12:11:47.818551 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4561 12:11:47.821675 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4562 12:11:47.824909 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4563 12:11:47.825017 ==
4564 12:11:47.828190 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 12:11:47.834739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 12:11:47.834852 ==
4567 12:11:47.834952 DQS Delay:
4568 12:11:47.837947 DQS0 = 0, DQS1 = 0
4569 12:11:47.838063 DQM Delay:
4570 12:11:47.838160 DQM0 = 45, DQM1 = 38
4571 12:11:47.841703 DQ Delay:
4572 12:11:47.844881 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4573 12:11:47.848108 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4574 12:11:47.851341 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4575 12:11:47.855120 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4576 12:11:47.855236
4577 12:11:47.855340
4578 12:11:47.855432 ==
4579 12:11:47.858237 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 12:11:47.861371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 12:11:47.861474 ==
4582 12:11:47.861568
4583 12:11:47.861656
4584 12:11:47.864453 TX Vref Scan disable
4585 12:11:47.867787 == TX Byte 0 ==
4586 12:11:47.871569 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4587 12:11:47.874914 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4588 12:11:47.878129 == TX Byte 1 ==
4589 12:11:47.881324 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4590 12:11:47.884551 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4591 12:11:47.884665 ==
4592 12:11:47.887795 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:11:47.891092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:11:47.894329 ==
4595 12:11:47.894442
4596 12:11:47.894545
4597 12:11:47.894641 TX Vref Scan disable
4598 12:11:47.898353 == TX Byte 0 ==
4599 12:11:47.901553 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4600 12:11:47.908389 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4601 12:11:47.908501 == TX Byte 1 ==
4602 12:11:47.911554 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4603 12:11:47.917888 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4604 12:11:47.917976
4605 12:11:47.918048 [DATLAT]
4606 12:11:47.918110 Freq=600, CH1 RK0
4607 12:11:47.918170
4608 12:11:47.921601 DATLAT Default: 0x9
4609 12:11:47.921713 0, 0xFFFF, sum = 0
4610 12:11:47.924908 1, 0xFFFF, sum = 0
4611 12:11:47.928145 2, 0xFFFF, sum = 0
4612 12:11:47.928253 3, 0xFFFF, sum = 0
4613 12:11:47.931310 4, 0xFFFF, sum = 0
4614 12:11:47.931415 5, 0xFFFF, sum = 0
4615 12:11:47.934568 6, 0xFFFF, sum = 0
4616 12:11:47.934680 7, 0xFFFF, sum = 0
4617 12:11:47.937851 8, 0x0, sum = 1
4618 12:11:47.937960 9, 0x0, sum = 2
4619 12:11:47.941060 10, 0x0, sum = 3
4620 12:11:47.941143 11, 0x0, sum = 4
4621 12:11:47.941210 best_step = 9
4622 12:11:47.941271
4623 12:11:47.944301 ==
4624 12:11:47.947494 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 12:11:47.950815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 12:11:47.950901 ==
4627 12:11:47.950967 RX Vref Scan: 1
4628 12:11:47.951029
4629 12:11:47.954602 RX Vref 0 -> 0, step: 1
4630 12:11:47.954696
4631 12:11:47.957826 RX Delay -195 -> 252, step: 8
4632 12:11:47.957917
4633 12:11:47.960709 Set Vref, RX VrefLevel [Byte0]: 51
4634 12:11:47.964362 [Byte1]: 60
4635 12:11:47.964475
4636 12:11:47.967613 Final RX Vref Byte 0 = 51 to rank0
4637 12:11:47.970785 Final RX Vref Byte 1 = 60 to rank0
4638 12:11:47.973971 Final RX Vref Byte 0 = 51 to rank1
4639 12:11:47.977697 Final RX Vref Byte 1 = 60 to rank1==
4640 12:11:47.980952 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 12:11:47.984256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 12:11:47.987412 ==
4643 12:11:47.987501 DQS Delay:
4644 12:11:47.987580 DQS0 = 0, DQS1 = 0
4645 12:11:47.990542 DQM Delay:
4646 12:11:47.990629 DQM0 = 47, DQM1 = 37
4647 12:11:47.994283 DQ Delay:
4648 12:11:47.996914 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4649 12:11:47.997006 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4650 12:11:48.000727 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4651 12:11:48.003968 DQ12 =44, DQ13 =48, DQ14 =44, DQ15 =48
4652 12:11:48.007189
4653 12:11:48.007321
4654 12:11:48.014180 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4655 12:11:48.017298 CH1 RK0: MR19=808, MR18=4A2F
4656 12:11:48.023804 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4657 12:11:48.023946
4658 12:11:48.027013 ----->DramcWriteLeveling(PI) begin...
4659 12:11:48.027121 ==
4660 12:11:48.030205 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 12:11:48.033459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 12:11:48.033553 ==
4663 12:11:48.036655 Write leveling (Byte 0): 29 => 29
4664 12:11:48.040452 Write leveling (Byte 1): 29 => 29
4665 12:11:48.043508 DramcWriteLeveling(PI) end<-----
4666 12:11:48.043618
4667 12:11:48.043713 ==
4668 12:11:48.046645 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 12:11:48.050305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 12:11:48.050429 ==
4671 12:11:48.053623 [Gating] SW mode calibration
4672 12:11:48.060051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4673 12:11:48.066381 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4674 12:11:48.070170 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 12:11:48.076575 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 12:11:48.079956 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 12:11:48.083147 0 9 12 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 0)
4678 12:11:48.089611 0 9 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4679 12:11:48.092745 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 12:11:48.096455 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 12:11:48.102847 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 12:11:48.106213 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 12:11:48.109364 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 12:11:48.116363 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 12:11:48.119513 0 10 12 | B1->B0 | 3636 2d2d | 0 0 | (1 1) (0 0)
4686 12:11:48.122642 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 12:11:48.129405 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 12:11:48.132646 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 12:11:48.135730 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 12:11:48.142201 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 12:11:48.145468 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 12:11:48.149263 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 12:11:48.155717 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4694 12:11:48.158966 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:11:48.162178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:11:48.169071 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:11:48.172147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:11:48.175155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:11:48.182192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:11:48.185471 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:11:48.188863 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:11:48.195184 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:11:48.198259 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:11:48.201443 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:11:48.208008 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 12:11:48.211217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 12:11:48.215043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 12:11:48.221289 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 12:11:48.224440 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 12:11:48.228095 Total UI for P1: 0, mck2ui 16
4711 12:11:48.231333 best dqsien dly found for B0: ( 0, 13, 10)
4712 12:11:48.234539 Total UI for P1: 0, mck2ui 16
4713 12:11:48.237909 best dqsien dly found for B1: ( 0, 13, 10)
4714 12:11:48.241067 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4715 12:11:48.244331 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4716 12:11:48.244442
4717 12:11:48.248241 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4718 12:11:48.251422 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4719 12:11:48.254691 [Gating] SW calibration Done
4720 12:11:48.254822 ==
4721 12:11:48.257921 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 12:11:48.260947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 12:11:48.264167 ==
4724 12:11:48.264245 RX Vref Scan: 0
4725 12:11:48.264334
4726 12:11:48.268019 RX Vref 0 -> 0, step: 1
4727 12:11:48.268096
4728 12:11:48.271092 RX Delay -230 -> 252, step: 16
4729 12:11:48.274254 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4730 12:11:48.277861 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4731 12:11:48.280878 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4732 12:11:48.287318 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4733 12:11:48.291162 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4734 12:11:48.293835 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4735 12:11:48.297567 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4736 12:11:48.300860 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4737 12:11:48.307784 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4738 12:11:48.310925 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4739 12:11:48.314281 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4740 12:11:48.317502 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4741 12:11:48.323866 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4742 12:11:48.326986 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4743 12:11:48.330638 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4744 12:11:48.333869 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4745 12:11:48.337040 ==
4746 12:11:48.337124 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 12:11:48.344143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 12:11:48.344231 ==
4749 12:11:48.344297 DQS Delay:
4750 12:11:48.347335 DQS0 = 0, DQS1 = 0
4751 12:11:48.347461 DQM Delay:
4752 12:11:48.350484 DQM0 = 43, DQM1 = 36
4753 12:11:48.350593 DQ Delay:
4754 12:11:48.353759 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4755 12:11:48.357028 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4756 12:11:48.360301 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4757 12:11:48.363493 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4758 12:11:48.363598
4759 12:11:48.363689
4760 12:11:48.363777 ==
4761 12:11:48.367209 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 12:11:48.370367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 12:11:48.370469 ==
4764 12:11:48.370560
4765 12:11:48.370656
4766 12:11:48.373674 TX Vref Scan disable
4767 12:11:48.376648 == TX Byte 0 ==
4768 12:11:48.380404 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4769 12:11:48.383562 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4770 12:11:48.386601 == TX Byte 1 ==
4771 12:11:48.389906 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4772 12:11:48.393097 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4773 12:11:48.393179 ==
4774 12:11:48.396272 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 12:11:48.402828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 12:11:48.402911 ==
4777 12:11:48.402975
4778 12:11:48.403034
4779 12:11:48.403091 TX Vref Scan disable
4780 12:11:48.407344 == TX Byte 0 ==
4781 12:11:48.411031 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4782 12:11:48.417475 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4783 12:11:48.417588 == TX Byte 1 ==
4784 12:11:48.420599 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4785 12:11:48.426941 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4786 12:11:48.427060
4787 12:11:48.427156 [DATLAT]
4788 12:11:48.427249 Freq=600, CH1 RK1
4789 12:11:48.427339
4790 12:11:48.430795 DATLAT Default: 0x9
4791 12:11:48.430872 0, 0xFFFF, sum = 0
4792 12:11:48.433916 1, 0xFFFF, sum = 0
4793 12:11:48.437145 2, 0xFFFF, sum = 0
4794 12:11:48.437226 3, 0xFFFF, sum = 0
4795 12:11:48.440357 4, 0xFFFF, sum = 0
4796 12:11:48.440465 5, 0xFFFF, sum = 0
4797 12:11:48.443558 6, 0xFFFF, sum = 0
4798 12:11:48.443640 7, 0xFFFF, sum = 0
4799 12:11:48.446853 8, 0x0, sum = 1
4800 12:11:48.446973 9, 0x0, sum = 2
4801 12:11:48.450020 10, 0x0, sum = 3
4802 12:11:48.450116 11, 0x0, sum = 4
4803 12:11:48.450183 best_step = 9
4804 12:11:48.450259
4805 12:11:48.453345 ==
4806 12:11:48.456640 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 12:11:48.459832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 12:11:48.459962 ==
4809 12:11:48.460077 RX Vref Scan: 0
4810 12:11:48.460181
4811 12:11:48.463009 RX Vref 0 -> 0, step: 1
4812 12:11:48.463127
4813 12:11:48.466880 RX Delay -195 -> 252, step: 8
4814 12:11:48.473340 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4815 12:11:48.476556 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4816 12:11:48.479553 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4817 12:11:48.483144 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4818 12:11:48.489397 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4819 12:11:48.493084 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4820 12:11:48.496319 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4821 12:11:48.499563 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4822 12:11:48.502697 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4823 12:11:48.509207 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4824 12:11:48.512404 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4825 12:11:48.516106 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4826 12:11:48.519273 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4827 12:11:48.525807 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4828 12:11:48.529124 iDelay=213, Bit 14, Center 48 (-107 ~ 204) 312
4829 12:11:48.532319 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4830 12:11:48.532430 ==
4831 12:11:48.535426 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 12:11:48.542425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 12:11:48.542564 ==
4834 12:11:48.542670 DQS Delay:
4835 12:11:48.542767 DQS0 = 0, DQS1 = 0
4836 12:11:48.545616 DQM Delay:
4837 12:11:48.545738 DQM0 = 45, DQM1 = 37
4838 12:11:48.548935 DQ Delay:
4839 12:11:48.552057 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4840 12:11:48.555288 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4841 12:11:48.558364 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4842 12:11:48.562185 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4843 12:11:48.562292
4844 12:11:48.562388
4845 12:11:48.568535 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
4846 12:11:48.571711 CH1 RK1: MR19=808, MR18=2A1F
4847 12:11:48.578308 CH1_RK1: MR19=0x808, MR18=0x2A1F, DQSOSC=401, MR23=63, INC=163, DEC=108
4848 12:11:48.581541 [RxdqsGatingPostProcess] freq 600
4849 12:11:48.585427 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4850 12:11:48.588454 Pre-setting of DQS Precalculation
4851 12:11:48.595358 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4852 12:11:48.601680 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4853 12:11:48.608091 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4854 12:11:48.608189
4855 12:11:48.608257
4856 12:11:48.611261 [Calibration Summary] 1200 Mbps
4857 12:11:48.611372 CH 0, Rank 0
4858 12:11:48.614573 SW Impedance : PASS
4859 12:11:48.618413 DUTY Scan : NO K
4860 12:11:48.618511 ZQ Calibration : PASS
4861 12:11:48.621586 Jitter Meter : NO K
4862 12:11:48.624918 CBT Training : PASS
4863 12:11:48.625029 Write leveling : PASS
4864 12:11:48.627929 RX DQS gating : PASS
4865 12:11:48.631235 RX DQ/DQS(RDDQC) : PASS
4866 12:11:48.631340 TX DQ/DQS : PASS
4867 12:11:48.634477 RX DATLAT : PASS
4868 12:11:48.638225 RX DQ/DQS(Engine): PASS
4869 12:11:48.638310 TX OE : NO K
4870 12:11:48.638377 All Pass.
4871 12:11:48.641433
4872 12:11:48.641520 CH 0, Rank 1
4873 12:11:48.644597 SW Impedance : PASS
4874 12:11:48.644681 DUTY Scan : NO K
4875 12:11:48.647984 ZQ Calibration : PASS
4876 12:11:48.651057 Jitter Meter : NO K
4877 12:11:48.651168 CBT Training : PASS
4878 12:11:48.654290 Write leveling : PASS
4879 12:11:48.657570 RX DQS gating : PASS
4880 12:11:48.657687 RX DQ/DQS(RDDQC) : PASS
4881 12:11:48.660920 TX DQ/DQS : PASS
4882 12:11:48.661032 RX DATLAT : PASS
4883 12:11:48.664145 RX DQ/DQS(Engine): PASS
4884 12:11:48.667909 TX OE : NO K
4885 12:11:48.668052 All Pass.
4886 12:11:48.668176
4887 12:11:48.668306 CH 1, Rank 0
4888 12:11:48.671057 SW Impedance : PASS
4889 12:11:48.674219 DUTY Scan : NO K
4890 12:11:48.674333 ZQ Calibration : PASS
4891 12:11:48.677353 Jitter Meter : NO K
4892 12:11:48.681140 CBT Training : PASS
4893 12:11:48.681254 Write leveling : PASS
4894 12:11:48.684280 RX DQS gating : PASS
4895 12:11:48.687363 RX DQ/DQS(RDDQC) : PASS
4896 12:11:48.687469 TX DQ/DQS : PASS
4897 12:11:48.690460 RX DATLAT : PASS
4898 12:11:48.694182 RX DQ/DQS(Engine): PASS
4899 12:11:48.694297 TX OE : NO K
4900 12:11:48.697355 All Pass.
4901 12:11:48.697474
4902 12:11:48.697576 CH 1, Rank 1
4903 12:11:48.700689 SW Impedance : PASS
4904 12:11:48.700804 DUTY Scan : NO K
4905 12:11:48.703727 ZQ Calibration : PASS
4906 12:11:48.706938 Jitter Meter : NO K
4907 12:11:48.707049 CBT Training : PASS
4908 12:11:48.710225 Write leveling : PASS
4909 12:11:48.713944 RX DQS gating : PASS
4910 12:11:48.714050 RX DQ/DQS(RDDQC) : PASS
4911 12:11:48.717202 TX DQ/DQS : PASS
4912 12:11:48.720281 RX DATLAT : PASS
4913 12:11:48.720407 RX DQ/DQS(Engine): PASS
4914 12:11:48.723387 TX OE : NO K
4915 12:11:48.723491 All Pass.
4916 12:11:48.723593
4917 12:11:48.727208 DramC Write-DBI off
4918 12:11:48.730458 PER_BANK_REFRESH: Hybrid Mode
4919 12:11:48.730589 TX_TRACKING: ON
4920 12:11:48.740267 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4921 12:11:48.743324 [FAST_K] Save calibration result to emmc
4922 12:11:48.746988 dramc_set_vcore_voltage set vcore to 662500
4923 12:11:48.750265 Read voltage for 933, 3
4924 12:11:48.750380 Vio18 = 0
4925 12:11:48.750478 Vcore = 662500
4926 12:11:48.753484 Vdram = 0
4927 12:11:48.753597 Vddq = 0
4928 12:11:48.753702 Vmddr = 0
4929 12:11:48.759919 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4930 12:11:48.763184 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4931 12:11:48.766387 MEM_TYPE=3, freq_sel=17
4932 12:11:48.770200 sv_algorithm_assistance_LP4_1600
4933 12:11:48.773436 ============ PULL DRAM RESETB DOWN ============
4934 12:11:48.776668 ========== PULL DRAM RESETB DOWN end =========
4935 12:11:48.782928 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4936 12:11:48.786705 ===================================
4937 12:11:48.786838 LPDDR4 DRAM CONFIGURATION
4938 12:11:48.789897 ===================================
4939 12:11:48.793033 EX_ROW_EN[0] = 0x0
4940 12:11:48.796183 EX_ROW_EN[1] = 0x0
4941 12:11:48.796293 LP4Y_EN = 0x0
4942 12:11:48.799288 WORK_FSP = 0x0
4943 12:11:48.799418 WL = 0x3
4944 12:11:48.803039 RL = 0x3
4945 12:11:48.803152 BL = 0x2
4946 12:11:48.806166 RPST = 0x0
4947 12:11:48.806283 RD_PRE = 0x0
4948 12:11:48.809397 WR_PRE = 0x1
4949 12:11:48.809513 WR_PST = 0x0
4950 12:11:48.812550 DBI_WR = 0x0
4951 12:11:48.812655 DBI_RD = 0x0
4952 12:11:48.815999 OTF = 0x1
4953 12:11:48.819181 ===================================
4954 12:11:48.822412 ===================================
4955 12:11:48.822541 ANA top config
4956 12:11:48.826194 ===================================
4957 12:11:48.829304 DLL_ASYNC_EN = 0
4958 12:11:48.832492 ALL_SLAVE_EN = 1
4959 12:11:48.835893 NEW_RANK_MODE = 1
4960 12:11:48.838903 DLL_IDLE_MODE = 1
4961 12:11:48.839019 LP45_APHY_COMB_EN = 1
4962 12:11:48.842068 TX_ODT_DIS = 1
4963 12:11:48.845878 NEW_8X_MODE = 1
4964 12:11:48.848965 ===================================
4965 12:11:48.852021 ===================================
4966 12:11:48.855228 data_rate = 1866
4967 12:11:48.858994 CKR = 1
4968 12:11:48.859119 DQ_P2S_RATIO = 8
4969 12:11:48.862256 ===================================
4970 12:11:48.865490 CA_P2S_RATIO = 8
4971 12:11:48.868748 DQ_CA_OPEN = 0
4972 12:11:48.872006 DQ_SEMI_OPEN = 0
4973 12:11:48.875240 CA_SEMI_OPEN = 0
4974 12:11:48.878489 CA_FULL_RATE = 0
4975 12:11:48.878608 DQ_CKDIV4_EN = 1
4976 12:11:48.881787 CA_CKDIV4_EN = 1
4977 12:11:48.885597 CA_PREDIV_EN = 0
4978 12:11:48.888821 PH8_DLY = 0
4979 12:11:48.891565 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4980 12:11:48.895346 DQ_AAMCK_DIV = 4
4981 12:11:48.895469 CA_AAMCK_DIV = 4
4982 12:11:48.898377 CA_ADMCK_DIV = 4
4983 12:11:48.902042 DQ_TRACK_CA_EN = 0
4984 12:11:48.905212 CA_PICK = 933
4985 12:11:48.908473 CA_MCKIO = 933
4986 12:11:48.911585 MCKIO_SEMI = 0
4987 12:11:48.914714 PLL_FREQ = 3732
4988 12:11:48.918401 DQ_UI_PI_RATIO = 32
4989 12:11:48.918521 CA_UI_PI_RATIO = 0
4990 12:11:48.921724 ===================================
4991 12:11:48.925014 ===================================
4992 12:11:48.928211 memory_type:LPDDR4
4993 12:11:48.931374 GP_NUM : 10
4994 12:11:48.931513 SRAM_EN : 1
4995 12:11:48.934534 MD32_EN : 0
4996 12:11:48.937804 ===================================
4997 12:11:48.941062 [ANA_INIT] >>>>>>>>>>>>>>
4998 12:11:48.944333 <<<<<< [CONFIGURE PHASE]: ANA_TX
4999 12:11:48.947588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5000 12:11:48.950856 ===================================
5001 12:11:48.950988 data_rate = 1866,PCW = 0X8f00
5002 12:11:48.954531 ===================================
5003 12:11:48.957758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5004 12:11:48.964004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5005 12:11:48.971153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 12:11:48.974488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5007 12:11:48.977524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5008 12:11:48.980859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5009 12:11:48.984011 [ANA_INIT] flow start
5010 12:11:48.987296 [ANA_INIT] PLL >>>>>>>>
5011 12:11:48.987424 [ANA_INIT] PLL <<<<<<<<
5012 12:11:48.991057 [ANA_INIT] MIDPI >>>>>>>>
5013 12:11:48.994212 [ANA_INIT] MIDPI <<<<<<<<
5014 12:11:48.994330 [ANA_INIT] DLL >>>>>>>>
5015 12:11:48.997461 [ANA_INIT] flow end
5016 12:11:49.000559 ============ LP4 DIFF to SE enter ============
5017 12:11:49.003672 ============ LP4 DIFF to SE exit ============
5018 12:11:49.007499 [ANA_INIT] <<<<<<<<<<<<<
5019 12:11:49.010659 [Flow] Enable top DCM control >>>>>
5020 12:11:49.013671 [Flow] Enable top DCM control <<<<<
5021 12:11:49.017452 Enable DLL master slave shuffle
5022 12:11:49.023799 ==============================================================
5023 12:11:49.023918 Gating Mode config
5024 12:11:49.030351 ==============================================================
5025 12:11:49.033682 Config description:
5026 12:11:49.040567 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5027 12:11:49.047103 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5028 12:11:49.053403 SELPH_MODE 0: By rank 1: By Phase
5029 12:11:49.060343 ==============================================================
5030 12:11:49.060531 GAT_TRACK_EN = 1
5031 12:11:49.063436 RX_GATING_MODE = 2
5032 12:11:49.066635 RX_GATING_TRACK_MODE = 2
5033 12:11:49.070483 SELPH_MODE = 1
5034 12:11:49.073712 PICG_EARLY_EN = 1
5035 12:11:49.076835 VALID_LAT_VALUE = 1
5036 12:11:49.083242 ==============================================================
5037 12:11:49.086493 Enter into Gating configuration >>>>
5038 12:11:49.090210 Exit from Gating configuration <<<<
5039 12:11:49.093367 Enter into DVFS_PRE_config >>>>>
5040 12:11:49.102939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5041 12:11:49.106133 Exit from DVFS_PRE_config <<<<<
5042 12:11:49.109807 Enter into PICG configuration >>>>
5043 12:11:49.113082 Exit from PICG configuration <<<<
5044 12:11:49.116123 [RX_INPUT] configuration >>>>>
5045 12:11:49.119911 [RX_INPUT] configuration <<<<<
5046 12:11:49.123063 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5047 12:11:49.129339 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5048 12:11:49.135779 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5049 12:11:49.139612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5050 12:11:49.145973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 12:11:49.152343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 12:11:49.155610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5053 12:11:49.162534 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5054 12:11:49.165644 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5055 12:11:49.168841 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5056 12:11:49.172056 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5057 12:11:49.178565 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 12:11:49.181841 ===================================
5059 12:11:49.185645 LPDDR4 DRAM CONFIGURATION
5060 12:11:49.188942 ===================================
5061 12:11:49.189056 EX_ROW_EN[0] = 0x0
5062 12:11:49.192226 EX_ROW_EN[1] = 0x0
5063 12:11:49.192337 LP4Y_EN = 0x0
5064 12:11:49.195316 WORK_FSP = 0x0
5065 12:11:49.195431 WL = 0x3
5066 12:11:49.198476 RL = 0x3
5067 12:11:49.198587 BL = 0x2
5068 12:11:49.202230 RPST = 0x0
5069 12:11:49.202363 RD_PRE = 0x0
5070 12:11:49.205401 WR_PRE = 0x1
5071 12:11:49.205513 WR_PST = 0x0
5072 12:11:49.208739 DBI_WR = 0x0
5073 12:11:49.208858 DBI_RD = 0x0
5074 12:11:49.211855 OTF = 0x1
5075 12:11:49.214936 ===================================
5076 12:11:49.218666 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5077 12:11:49.221899 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5078 12:11:49.228265 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5079 12:11:49.231468 ===================================
5080 12:11:49.234682 LPDDR4 DRAM CONFIGURATION
5081 12:11:49.237957 ===================================
5082 12:11:49.238085 EX_ROW_EN[0] = 0x10
5083 12:11:49.241202 EX_ROW_EN[1] = 0x0
5084 12:11:49.241317 LP4Y_EN = 0x0
5085 12:11:49.244419 WORK_FSP = 0x0
5086 12:11:49.244542 WL = 0x3
5087 12:11:49.248229 RL = 0x3
5088 12:11:49.248335 BL = 0x2
5089 12:11:49.251390 RPST = 0x0
5090 12:11:49.251497 RD_PRE = 0x0
5091 12:11:49.254655 WR_PRE = 0x1
5092 12:11:49.254769 WR_PST = 0x0
5093 12:11:49.257934 DBI_WR = 0x0
5094 12:11:49.261165 DBI_RD = 0x0
5095 12:11:49.261283 OTF = 0x1
5096 12:11:49.264269 ===================================
5097 12:11:49.271313 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5098 12:11:49.274494 nWR fixed to 30
5099 12:11:49.277682 [ModeRegInit_LP4] CH0 RK0
5100 12:11:49.277799 [ModeRegInit_LP4] CH0 RK1
5101 12:11:49.281503 [ModeRegInit_LP4] CH1 RK0
5102 12:11:49.284858 [ModeRegInit_LP4] CH1 RK1
5103 12:11:49.284974 match AC timing 9
5104 12:11:49.291187 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5105 12:11:49.294401 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5106 12:11:49.297685 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5107 12:11:49.304328 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5108 12:11:49.307570 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5109 12:11:49.307686 ==
5110 12:11:49.310894 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 12:11:49.314183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 12:11:49.314290 ==
5113 12:11:49.321106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 12:11:49.327986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5115 12:11:49.331076 [CA 0] Center 37 (7~68) winsize 62
5116 12:11:49.334197 [CA 1] Center 37 (7~68) winsize 62
5117 12:11:49.337474 [CA 2] Center 34 (4~65) winsize 62
5118 12:11:49.340761 [CA 3] Center 35 (5~65) winsize 61
5119 12:11:49.343939 [CA 4] Center 33 (3~64) winsize 62
5120 12:11:49.347703 [CA 5] Center 33 (4~63) winsize 60
5121 12:11:49.347822
5122 12:11:49.350768 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5123 12:11:49.350874
5124 12:11:49.353998 [CATrainingPosCal] consider 1 rank data
5125 12:11:49.357240 u2DelayCellTimex100 = 270/100 ps
5126 12:11:49.361075 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5127 12:11:49.364309 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5128 12:11:49.367366 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5129 12:11:49.370588 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5130 12:11:49.374341 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5131 12:11:49.380793 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5132 12:11:49.380920
5133 12:11:49.384030 CA PerBit enable=1, Macro0, CA PI delay=33
5134 12:11:49.384138
5135 12:11:49.387346 [CBTSetCACLKResult] CA Dly = 33
5136 12:11:49.387454 CS Dly: 7 (0~38)
5137 12:11:49.387548 ==
5138 12:11:49.390621 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 12:11:49.393966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 12:11:49.397242 ==
5141 12:11:49.400461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5142 12:11:49.406697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5143 12:11:49.410358 [CA 0] Center 37 (7~68) winsize 62
5144 12:11:49.413650 [CA 1] Center 37 (7~68) winsize 62
5145 12:11:49.416737 [CA 2] Center 34 (4~65) winsize 62
5146 12:11:49.419918 [CA 3] Center 35 (5~65) winsize 61
5147 12:11:49.423538 [CA 4] Center 33 (3~64) winsize 62
5148 12:11:49.426662 [CA 5] Center 32 (2~63) winsize 62
5149 12:11:49.426782
5150 12:11:49.429923 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5151 12:11:49.430030
5152 12:11:49.433697 [CATrainingPosCal] consider 2 rank data
5153 12:11:49.436930 u2DelayCellTimex100 = 270/100 ps
5154 12:11:49.440084 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5155 12:11:49.443365 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5156 12:11:49.449874 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5157 12:11:49.452961 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5158 12:11:49.456175 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5159 12:11:49.459911 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5160 12:11:49.460018
5161 12:11:49.463143 CA PerBit enable=1, Macro0, CA PI delay=33
5162 12:11:49.463254
5163 12:11:49.466379 [CBTSetCACLKResult] CA Dly = 33
5164 12:11:49.466499 CS Dly: 7 (0~39)
5165 12:11:49.466601
5166 12:11:49.469551 ----->DramcWriteLeveling(PI) begin...
5167 12:11:49.473253 ==
5168 12:11:49.476246 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 12:11:49.479417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 12:11:49.479534 ==
5171 12:11:49.482585 Write leveling (Byte 0): 31 => 31
5172 12:11:49.486406 Write leveling (Byte 1): 31 => 31
5173 12:11:49.489602 DramcWriteLeveling(PI) end<-----
5174 12:11:49.489711
5175 12:11:49.489806 ==
5176 12:11:49.492771 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 12:11:49.496051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 12:11:49.496167 ==
5179 12:11:49.499273 [Gating] SW mode calibration
5180 12:11:49.505721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5181 12:11:49.512692 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5182 12:11:49.515792 0 14 0 | B1->B0 | 2322 3333 | 1 1 | (0 0) (1 1)
5183 12:11:49.519005 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5184 12:11:49.525532 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 12:11:49.529268 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 12:11:49.532350 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 12:11:49.538705 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 12:11:49.542358 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 12:11:49.545595 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5190 12:11:49.552176 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
5191 12:11:49.555506 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 12:11:49.558677 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 12:11:49.565071 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 12:11:49.568312 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 12:11:49.571643 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 12:11:49.578655 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 12:11:49.581856 0 15 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5198 12:11:49.584991 1 0 0 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
5199 12:11:49.592053 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5200 12:11:49.595235 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 12:11:49.598414 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 12:11:49.604998 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 12:11:49.608119 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 12:11:49.611486 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 12:11:49.618276 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5206 12:11:49.621603 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5207 12:11:49.624919 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:11:49.631233 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:11:49.634975 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:11:49.637974 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:11:49.644712 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:11:49.647831 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:11:49.650941 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:11:49.657993 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:11:49.661281 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:11:49.664495 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:11:49.670918 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:11:49.674053 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:11:49.677309 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 12:11:49.684107 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5221 12:11:49.687319 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5222 12:11:49.690564 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5223 12:11:49.697026 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 12:11:49.697147 Total UI for P1: 0, mck2ui 16
5225 12:11:49.704147 best dqsien dly found for B0: ( 1, 2, 28)
5226 12:11:49.704274 Total UI for P1: 0, mck2ui 16
5227 12:11:49.707299 best dqsien dly found for B1: ( 1, 3, 0)
5228 12:11:49.713581 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5229 12:11:49.716776 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5230 12:11:49.716891
5231 12:11:49.720657 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5232 12:11:49.723656 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5233 12:11:49.726886 [Gating] SW calibration Done
5234 12:11:49.726996 ==
5235 12:11:49.730148 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 12:11:49.733299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 12:11:49.733405 ==
5238 12:11:49.736511 RX Vref Scan: 0
5239 12:11:49.736628
5240 12:11:49.736729 RX Vref 0 -> 0, step: 1
5241 12:11:49.736821
5242 12:11:49.739855 RX Delay -80 -> 252, step: 8
5243 12:11:49.743500 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5244 12:11:49.749707 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5245 12:11:49.753616 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5246 12:11:49.756893 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5247 12:11:49.760053 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5248 12:11:49.763222 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5249 12:11:49.766440 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5250 12:11:49.772695 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5251 12:11:49.776619 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5252 12:11:49.779887 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5253 12:11:49.782998 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5254 12:11:49.786172 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5255 12:11:49.793123 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5256 12:11:49.796346 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5257 12:11:49.799471 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5258 12:11:49.802634 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5259 12:11:49.802755 ==
5260 12:11:49.805868 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 12:11:49.812377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 12:11:49.812494 ==
5263 12:11:49.812619 DQS Delay:
5264 12:11:49.812721 DQS0 = 0, DQS1 = 0
5265 12:11:49.816346 DQM Delay:
5266 12:11:49.816458 DQM0 = 97, DQM1 = 85
5267 12:11:49.819429 DQ Delay:
5268 12:11:49.822580 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5269 12:11:49.825817 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5270 12:11:49.829127 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5271 12:11:49.832269 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5272 12:11:49.832385
5273 12:11:49.832482
5274 12:11:49.832589 ==
5275 12:11:49.835557 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 12:11:49.838851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 12:11:49.838963 ==
5278 12:11:49.839060
5279 12:11:49.839151
5280 12:11:49.842149 TX Vref Scan disable
5281 12:11:49.842256 == TX Byte 0 ==
5282 12:11:49.849011 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5283 12:11:49.852264 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5284 12:11:49.855343 == TX Byte 1 ==
5285 12:11:49.859101 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5286 12:11:49.862301 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5287 12:11:49.862411 ==
5288 12:11:49.865507 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 12:11:49.868876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:11:49.872046 ==
5291 12:11:49.872172
5292 12:11:49.872279
5293 12:11:49.872385 TX Vref Scan disable
5294 12:11:49.875230 == TX Byte 0 ==
5295 12:11:49.878418 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5296 12:11:49.885501 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5297 12:11:49.885626 == TX Byte 1 ==
5298 12:11:49.888596 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5299 12:11:49.894920 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5300 12:11:49.895044
5301 12:11:49.895147 [DATLAT]
5302 12:11:49.895258 Freq=933, CH0 RK0
5303 12:11:49.895358
5304 12:11:49.898134 DATLAT Default: 0xd
5305 12:11:49.898240 0, 0xFFFF, sum = 0
5306 12:11:49.901888 1, 0xFFFF, sum = 0
5307 12:11:49.905162 2, 0xFFFF, sum = 0
5308 12:11:49.905272 3, 0xFFFF, sum = 0
5309 12:11:49.908435 4, 0xFFFF, sum = 0
5310 12:11:49.908552 5, 0xFFFF, sum = 0
5311 12:11:49.911642 6, 0xFFFF, sum = 0
5312 12:11:49.911767 7, 0xFFFF, sum = 0
5313 12:11:49.914907 8, 0xFFFF, sum = 0
5314 12:11:49.915019 9, 0xFFFF, sum = 0
5315 12:11:49.918240 10, 0x0, sum = 1
5316 12:11:49.918351 11, 0x0, sum = 2
5317 12:11:49.921436 12, 0x0, sum = 3
5318 12:11:49.921552 13, 0x0, sum = 4
5319 12:11:49.924673 best_step = 11
5320 12:11:49.924775
5321 12:11:49.924872 ==
5322 12:11:49.927804 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 12:11:49.931595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 12:11:49.931710 ==
5325 12:11:49.931807 RX Vref Scan: 1
5326 12:11:49.931899
5327 12:11:49.934695 RX Vref 0 -> 0, step: 1
5328 12:11:49.934817
5329 12:11:49.937706 RX Delay -61 -> 252, step: 4
5330 12:11:49.937822
5331 12:11:49.941489 Set Vref, RX VrefLevel [Byte0]: 59
5332 12:11:49.944783 [Byte1]: 56
5333 12:11:49.947952
5334 12:11:49.948064 Final RX Vref Byte 0 = 59 to rank0
5335 12:11:49.951010 Final RX Vref Byte 1 = 56 to rank0
5336 12:11:49.954801 Final RX Vref Byte 0 = 59 to rank1
5337 12:11:49.958034 Final RX Vref Byte 1 = 56 to rank1==
5338 12:11:49.961175 Dram Type= 6, Freq= 0, CH_0, rank 0
5339 12:11:49.967549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 12:11:49.967665 ==
5341 12:11:49.967765 DQS Delay:
5342 12:11:49.970773 DQS0 = 0, DQS1 = 0
5343 12:11:49.970881 DQM Delay:
5344 12:11:49.970980 DQM0 = 97, DQM1 = 86
5345 12:11:49.973877 DQ Delay:
5346 12:11:49.977659 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5347 12:11:49.981032 DQ4 =98, DQ5 =88, DQ6 =102, DQ7 =108
5348 12:11:49.984226 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5349 12:11:49.987313 DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92
5350 12:11:49.987414
5351 12:11:49.987509
5352 12:11:49.994300 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5353 12:11:49.997252 CH0 RK0: MR19=505, MR18=2A10
5354 12:11:50.003988 CH0_RK0: MR19=0x505, MR18=0x2A10, DQSOSC=408, MR23=63, INC=65, DEC=43
5355 12:11:50.004114
5356 12:11:50.007088 ----->DramcWriteLeveling(PI) begin...
5357 12:11:50.007200 ==
5358 12:11:50.010327 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 12:11:50.013523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 12:11:50.013643 ==
5361 12:11:50.016705 Write leveling (Byte 0): 32 => 32
5362 12:11:50.020524 Write leveling (Byte 1): 29 => 29
5363 12:11:50.023957 DramcWriteLeveling(PI) end<-----
5364 12:11:50.024066
5365 12:11:50.024174 ==
5366 12:11:50.027219 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 12:11:50.033646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 12:11:50.033765 ==
5369 12:11:50.033861 [Gating] SW mode calibration
5370 12:11:50.043206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5371 12:11:50.046317 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5372 12:11:50.053258 0 14 0 | B1->B0 | 2626 3232 | 1 1 | (1 1) (1 1)
5373 12:11:50.056467 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5374 12:11:50.059521 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 12:11:50.062851 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 12:11:50.069940 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 12:11:50.073184 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 12:11:50.076412 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 12:11:50.082772 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5380 12:11:50.085983 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (0 1) (0 0)
5381 12:11:50.089262 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 12:11:50.096307 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 12:11:50.099407 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 12:11:50.103108 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 12:11:50.109312 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 12:11:50.112408 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 12:11:50.116218 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5388 12:11:50.122609 1 0 0 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5389 12:11:50.125930 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 12:11:50.129269 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 12:11:50.135701 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 12:11:50.139527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 12:11:50.142642 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 12:11:50.148857 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 12:11:50.152661 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5396 12:11:50.155821 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5397 12:11:50.162561 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:11:50.165755 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:11:50.168829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:11:50.175955 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:11:50.179287 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:11:50.182586 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:11:50.188916 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:11:50.192195 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:11:50.195478 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:11:50.201937 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:11:50.205046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:11:50.208194 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:11:50.214924 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:11:50.218594 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 12:11:50.221862 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 12:11:50.228305 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5413 12:11:50.231436 Total UI for P1: 0, mck2ui 16
5414 12:11:50.234627 best dqsien dly found for B0: ( 1, 2, 30)
5415 12:11:50.238459 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 12:11:50.241545 Total UI for P1: 0, mck2ui 16
5417 12:11:50.244560 best dqsien dly found for B1: ( 1, 3, 0)
5418 12:11:50.248257 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5419 12:11:50.251398 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5420 12:11:50.251517
5421 12:11:50.254447 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5422 12:11:50.258305 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5423 12:11:50.261494 [Gating] SW calibration Done
5424 12:11:50.261585 ==
5425 12:11:50.264630 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 12:11:50.267824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 12:11:50.271505 ==
5428 12:11:50.271654 RX Vref Scan: 0
5429 12:11:50.271755
5430 12:11:50.274674 RX Vref 0 -> 0, step: 1
5431 12:11:50.274802
5432 12:11:50.277998 RX Delay -80 -> 252, step: 8
5433 12:11:50.281349 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5434 12:11:50.284624 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5435 12:11:50.287849 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5436 12:11:50.290975 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5437 12:11:50.294249 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5438 12:11:50.300817 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5439 12:11:50.304099 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5440 12:11:50.307268 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5441 12:11:50.310536 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5442 12:11:50.314256 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5443 12:11:50.320871 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5444 12:11:50.323996 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5445 12:11:50.327209 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5446 12:11:50.330316 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5447 12:11:50.333535 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5448 12:11:50.340695 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5449 12:11:50.340825 ==
5450 12:11:50.343774 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 12:11:50.346964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 12:11:50.347082 ==
5453 12:11:50.347191 DQS Delay:
5454 12:11:50.350177 DQS0 = 0, DQS1 = 0
5455 12:11:50.350284 DQM Delay:
5456 12:11:50.353369 DQM0 = 96, DQM1 = 88
5457 12:11:50.353482 DQ Delay:
5458 12:11:50.357060 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5459 12:11:50.360343 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5460 12:11:50.363497 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5461 12:11:50.366674 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =91
5462 12:11:50.366788
5463 12:11:50.366897
5464 12:11:50.367000 ==
5465 12:11:50.370275 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 12:11:50.373285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 12:11:50.376397 ==
5468 12:11:50.376509
5469 12:11:50.376617
5470 12:11:50.376719 TX Vref Scan disable
5471 12:11:50.379700 == TX Byte 0 ==
5472 12:11:50.383419 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5473 12:11:50.386209 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5474 12:11:50.389531 == TX Byte 1 ==
5475 12:11:50.393294 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5476 12:11:50.399827 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5477 12:11:50.399956 ==
5478 12:11:50.402836 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 12:11:50.406126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 12:11:50.406243 ==
5481 12:11:50.406343
5482 12:11:50.406441
5483 12:11:50.409319 TX Vref Scan disable
5484 12:11:50.409429 == TX Byte 0 ==
5485 12:11:50.415987 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5486 12:11:50.419176 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5487 12:11:50.422902 == TX Byte 1 ==
5488 12:11:50.425796 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5489 12:11:50.429411 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5490 12:11:50.429519
5491 12:11:50.429620 [DATLAT]
5492 12:11:50.432486 Freq=933, CH0 RK1
5493 12:11:50.432603
5494 12:11:50.432697 DATLAT Default: 0xb
5495 12:11:50.435582 0, 0xFFFF, sum = 0
5496 12:11:50.438843 1, 0xFFFF, sum = 0
5497 12:11:50.438953 2, 0xFFFF, sum = 0
5498 12:11:50.442594 3, 0xFFFF, sum = 0
5499 12:11:50.442702 4, 0xFFFF, sum = 0
5500 12:11:50.445912 5, 0xFFFF, sum = 0
5501 12:11:50.446053 6, 0xFFFF, sum = 0
5502 12:11:50.449176 7, 0xFFFF, sum = 0
5503 12:11:50.449308 8, 0xFFFF, sum = 0
5504 12:11:50.452350 9, 0xFFFF, sum = 0
5505 12:11:50.452462 10, 0x0, sum = 1
5506 12:11:50.455373 11, 0x0, sum = 2
5507 12:11:50.455499 12, 0x0, sum = 3
5508 12:11:50.458676 13, 0x0, sum = 4
5509 12:11:50.458798 best_step = 11
5510 12:11:50.458895
5511 12:11:50.458987 ==
5512 12:11:50.462398 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 12:11:50.465597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 12:11:50.465707 ==
5515 12:11:50.468774 RX Vref Scan: 0
5516 12:11:50.468882
5517 12:11:50.471972 RX Vref 0 -> 0, step: 1
5518 12:11:50.472085
5519 12:11:50.472181 RX Delay -61 -> 252, step: 4
5520 12:11:50.480012 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5521 12:11:50.483860 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5522 12:11:50.487143 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5523 12:11:50.490327 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5524 12:11:50.493550 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5525 12:11:50.499996 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5526 12:11:50.503127 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5527 12:11:50.506390 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5528 12:11:50.510173 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5529 12:11:50.512848 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5530 12:11:50.520033 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5531 12:11:50.523179 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5532 12:11:50.526399 iDelay=203, Bit 12, Center 92 (-5 ~ 190) 196
5533 12:11:50.529552 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5534 12:11:50.532671 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5535 12:11:50.539452 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5536 12:11:50.539585 ==
5537 12:11:50.542526 Dram Type= 6, Freq= 0, CH_0, rank 1
5538 12:11:50.545628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 12:11:50.545748 ==
5540 12:11:50.545856 DQS Delay:
5541 12:11:50.549505 DQS0 = 0, DQS1 = 0
5542 12:11:50.549613 DQM Delay:
5543 12:11:50.552613 DQM0 = 95, DQM1 = 87
5544 12:11:50.552725 DQ Delay:
5545 12:11:50.555743 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5546 12:11:50.559404 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5547 12:11:50.562512 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =80
5548 12:11:50.565602 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5549 12:11:50.565715
5550 12:11:50.565816
5551 12:11:50.575606 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5552 12:11:50.575725 CH0 RK1: MR19=504, MR18=27F7
5553 12:11:50.582035 CH0_RK1: MR19=0x504, MR18=0x27F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5554 12:11:50.585151 [RxdqsGatingPostProcess] freq 933
5555 12:11:50.592161 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5556 12:11:50.594830 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 12:11:50.598021 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 12:11:50.601768 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 12:11:50.605108 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 12:11:50.608387 best DQS0 dly(2T, 0.5T) = (0, 10)
5561 12:11:50.611558 best DQS1 dly(2T, 0.5T) = (0, 11)
5562 12:11:50.614712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5563 12:11:50.617921 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5564 12:11:50.618029 Pre-setting of DQS Precalculation
5565 12:11:50.624814 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5566 12:11:50.624932 ==
5567 12:11:50.628048 Dram Type= 6, Freq= 0, CH_1, rank 0
5568 12:11:50.631299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 12:11:50.631404 ==
5570 12:11:50.638214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 12:11:50.644537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5572 12:11:50.647668 [CA 0] Center 37 (7~67) winsize 61
5573 12:11:50.651225 [CA 1] Center 37 (7~68) winsize 62
5574 12:11:50.654174 [CA 2] Center 34 (4~65) winsize 62
5575 12:11:50.657892 [CA 3] Center 34 (4~64) winsize 61
5576 12:11:50.661241 [CA 4] Center 34 (5~64) winsize 60
5577 12:11:50.664396 [CA 5] Center 33 (3~64) winsize 62
5578 12:11:50.664502
5579 12:11:50.667555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5580 12:11:50.667663
5581 12:11:50.670801 [CATrainingPosCal] consider 1 rank data
5582 12:11:50.674459 u2DelayCellTimex100 = 270/100 ps
5583 12:11:50.677620 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5584 12:11:50.680813 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5585 12:11:50.683984 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5586 12:11:50.687655 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5587 12:11:50.690734 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5588 12:11:50.697253 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5589 12:11:50.697362
5590 12:11:50.700465 CA PerBit enable=1, Macro0, CA PI delay=33
5591 12:11:50.700597
5592 12:11:50.704285 [CBTSetCACLKResult] CA Dly = 33
5593 12:11:50.704399 CS Dly: 6 (0~37)
5594 12:11:50.704495 ==
5595 12:11:50.707433 Dram Type= 6, Freq= 0, CH_1, rank 1
5596 12:11:50.710536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 12:11:50.713842 ==
5598 12:11:50.717114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5599 12:11:50.723579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5600 12:11:50.727457 [CA 0] Center 36 (6~67) winsize 62
5601 12:11:50.730814 [CA 1] Center 37 (7~68) winsize 62
5602 12:11:50.733402 [CA 2] Center 34 (4~65) winsize 62
5603 12:11:50.737209 [CA 3] Center 34 (4~65) winsize 62
5604 12:11:50.740191 [CA 4] Center 34 (4~65) winsize 62
5605 12:11:50.743313 [CA 5] Center 33 (3~64) winsize 62
5606 12:11:50.743427
5607 12:11:50.747181 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5608 12:11:50.747304
5609 12:11:50.750313 [CATrainingPosCal] consider 2 rank data
5610 12:11:50.753539 u2DelayCellTimex100 = 270/100 ps
5611 12:11:50.756696 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5612 12:11:50.759966 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5613 12:11:50.766665 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5614 12:11:50.769684 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5615 12:11:50.773434 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5616 12:11:50.776466 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5617 12:11:50.776595
5618 12:11:50.779582 CA PerBit enable=1, Macro0, CA PI delay=33
5619 12:11:50.779707
5620 12:11:50.782859 [CBTSetCACLKResult] CA Dly = 33
5621 12:11:50.782978 CS Dly: 7 (0~39)
5622 12:11:50.783088
5623 12:11:50.786507 ----->DramcWriteLeveling(PI) begin...
5624 12:11:50.789700 ==
5625 12:11:50.792892 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 12:11:50.796088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 12:11:50.796199 ==
5628 12:11:50.799326 Write leveling (Byte 0): 26 => 26
5629 12:11:50.803228 Write leveling (Byte 1): 28 => 28
5630 12:11:50.806369 DramcWriteLeveling(PI) end<-----
5631 12:11:50.806476
5632 12:11:50.806573 ==
5633 12:11:50.809478 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 12:11:50.813299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 12:11:50.813421 ==
5636 12:11:50.816534 [Gating] SW mode calibration
5637 12:11:50.823046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5638 12:11:50.829565 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5639 12:11:50.832757 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 12:11:50.835904 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 12:11:50.842174 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 12:11:50.845894 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 12:11:50.848997 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 12:11:50.855487 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 12:11:50.858665 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
5646 12:11:50.862387 0 14 28 | B1->B0 | 2c2c 2929 | 1 0 | (1 0) (0 0)
5647 12:11:50.868831 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5648 12:11:50.871925 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 12:11:50.875790 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 12:11:50.882217 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 12:11:50.885290 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 12:11:50.888400 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 12:11:50.895248 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5654 12:11:50.898435 0 15 28 | B1->B0 | 3636 3a3a | 0 0 | (0 0) (0 0)
5655 12:11:50.901728 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 12:11:50.908283 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 12:11:50.911514 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 12:11:50.915203 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 12:11:50.921527 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 12:11:50.924773 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 12:11:50.928033 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5662 12:11:50.935003 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5663 12:11:50.938257 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:11:50.941522 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:11:50.947908 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:11:50.951053 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:11:50.954388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:11:50.961260 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:11:50.964441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:11:50.968123 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:11:50.974578 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:11:50.977817 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:11:50.980805 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:11:50.987773 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:11:50.990857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 12:11:50.993898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5677 12:11:51.000894 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5678 12:11:51.004003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 12:11:51.007214 Total UI for P1: 0, mck2ui 16
5680 12:11:51.010548 best dqsien dly found for B0: ( 1, 2, 22)
5681 12:11:51.013795 Total UI for P1: 0, mck2ui 16
5682 12:11:51.017039 best dqsien dly found for B1: ( 1, 2, 24)
5683 12:11:51.020871 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5684 12:11:51.024081 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5685 12:11:51.024211
5686 12:11:51.027224 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5687 12:11:51.030483 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5688 12:11:51.033771 [Gating] SW calibration Done
5689 12:11:51.033887 ==
5690 12:11:51.036969 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 12:11:51.040220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 12:11:51.040325 ==
5693 12:11:51.044104 RX Vref Scan: 0
5694 12:11:51.044215
5695 12:11:51.047398 RX Vref 0 -> 0, step: 1
5696 12:11:51.047505
5697 12:11:51.047600 RX Delay -80 -> 252, step: 8
5698 12:11:51.054165 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5699 12:11:51.057393 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5700 12:11:51.060596 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5701 12:11:51.063774 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5702 12:11:51.066898 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5703 12:11:51.070698 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5704 12:11:51.076926 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5705 12:11:51.080154 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5706 12:11:51.083884 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5707 12:11:51.086930 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5708 12:11:51.090034 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5709 12:11:51.097003 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5710 12:11:51.100146 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5711 12:11:51.103139 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5712 12:11:51.106908 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5713 12:11:51.110195 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5714 12:11:51.113428 ==
5715 12:11:51.116699 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 12:11:51.119983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 12:11:51.120080 ==
5718 12:11:51.120169 DQS Delay:
5719 12:11:51.123139 DQS0 = 0, DQS1 = 0
5720 12:11:51.123237 DQM Delay:
5721 12:11:51.126373 DQM0 = 102, DQM1 = 90
5722 12:11:51.126480 DQ Delay:
5723 12:11:51.129532 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5724 12:11:51.132858 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5725 12:11:51.136238 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5726 12:11:51.139326 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =103
5727 12:11:51.139425
5728 12:11:51.139494
5729 12:11:51.139554 ==
5730 12:11:51.143240 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 12:11:51.146315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 12:11:51.146400 ==
5733 12:11:51.149588
5734 12:11:51.149700
5735 12:11:51.149769 TX Vref Scan disable
5736 12:11:51.152818 == TX Byte 0 ==
5737 12:11:51.155939 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5738 12:11:51.159737 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5739 12:11:51.162830 == TX Byte 1 ==
5740 12:11:51.166090 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5741 12:11:51.169324 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5742 12:11:51.172581 ==
5743 12:11:51.175919 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 12:11:51.178933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 12:11:51.179023 ==
5746 12:11:51.179092
5747 12:11:51.179154
5748 12:11:51.182133 TX Vref Scan disable
5749 12:11:51.182209 == TX Byte 0 ==
5750 12:11:51.189174 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5751 12:11:51.192197 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5752 12:11:51.192321 == TX Byte 1 ==
5753 12:11:51.198808 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5754 12:11:51.201939 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5755 12:11:51.202059
5756 12:11:51.202173 [DATLAT]
5757 12:11:51.205567 Freq=933, CH1 RK0
5758 12:11:51.205686
5759 12:11:51.205788 DATLAT Default: 0xd
5760 12:11:51.208676 0, 0xFFFF, sum = 0
5761 12:11:51.208787 1, 0xFFFF, sum = 0
5762 12:11:51.211849 2, 0xFFFF, sum = 0
5763 12:11:51.211975 3, 0xFFFF, sum = 0
5764 12:11:51.215391 4, 0xFFFF, sum = 0
5765 12:11:51.215521 5, 0xFFFF, sum = 0
5766 12:11:51.218533 6, 0xFFFF, sum = 0
5767 12:11:51.221783 7, 0xFFFF, sum = 0
5768 12:11:51.221875 8, 0xFFFF, sum = 0
5769 12:11:51.225040 9, 0xFFFF, sum = 0
5770 12:11:51.225122 10, 0x0, sum = 1
5771 12:11:51.228277 11, 0x0, sum = 2
5772 12:11:51.228387 12, 0x0, sum = 3
5773 12:11:51.228485 13, 0x0, sum = 4
5774 12:11:51.232128 best_step = 11
5775 12:11:51.232239
5776 12:11:51.232335 ==
5777 12:11:51.234818 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 12:11:51.238555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 12:11:51.238664 ==
5780 12:11:51.241848 RX Vref Scan: 1
5781 12:11:51.241955
5782 12:11:51.245025 RX Vref 0 -> 0, step: 1
5783 12:11:51.245135
5784 12:11:51.245271 RX Delay -61 -> 252, step: 4
5785 12:11:51.245378
5786 12:11:51.248195 Set Vref, RX VrefLevel [Byte0]: 51
5787 12:11:51.251478 [Byte1]: 60
5788 12:11:51.256040
5789 12:11:51.256124 Final RX Vref Byte 0 = 51 to rank0
5790 12:11:51.259231 Final RX Vref Byte 1 = 60 to rank0
5791 12:11:51.263073 Final RX Vref Byte 0 = 51 to rank1
5792 12:11:51.266628 Final RX Vref Byte 1 = 60 to rank1==
5793 12:11:51.269236 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 12:11:51.276333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 12:11:51.276456 ==
5796 12:11:51.276558 DQS Delay:
5797 12:11:51.276623 DQS0 = 0, DQS1 = 0
5798 12:11:51.279483 DQM Delay:
5799 12:11:51.279567 DQM0 = 101, DQM1 = 94
5800 12:11:51.282662 DQ Delay:
5801 12:11:51.285799 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5802 12:11:51.289653 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =98
5803 12:11:51.292824 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =86
5804 12:11:51.296030 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5805 12:11:51.296138
5806 12:11:51.296238
5807 12:11:51.302365 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5808 12:11:51.306080 CH1 RK0: MR19=505, MR18=1909
5809 12:11:51.312189 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5810 12:11:51.312300
5811 12:11:51.315906 ----->DramcWriteLeveling(PI) begin...
5812 12:11:51.316021 ==
5813 12:11:51.319378 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 12:11:51.322268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 12:11:51.322385 ==
5816 12:11:51.325387 Write leveling (Byte 0): 26 => 26
5817 12:11:51.329222 Write leveling (Byte 1): 27 => 27
5818 12:11:51.332501 DramcWriteLeveling(PI) end<-----
5819 12:11:51.332588
5820 12:11:51.332659 ==
5821 12:11:51.335623 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 12:11:51.342102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 12:11:51.342218 ==
5824 12:11:51.342325 [Gating] SW mode calibration
5825 12:11:51.352248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5826 12:11:51.355548 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5827 12:11:51.361984 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
5828 12:11:51.365117 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 12:11:51.368268 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 12:11:51.375205 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 12:11:51.378473 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 12:11:51.381671 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 12:11:51.388021 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5834 12:11:51.391316 0 14 28 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 1)
5835 12:11:51.394514 0 15 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5836 12:11:51.401525 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 12:11:51.404781 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 12:11:51.407902 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 12:11:51.414782 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 12:11:51.417928 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 12:11:51.420952 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5842 12:11:51.427694 0 15 28 | B1->B0 | 3c3c 2e2e | 0 0 | (0 0) (0 0)
5843 12:11:51.430798 1 0 0 | B1->B0 | 4646 3d3d | 0 1 | (0 0) (0 0)
5844 12:11:51.434481 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 12:11:51.440956 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 12:11:51.444288 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 12:11:51.447563 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 12:11:51.454010 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 12:11:51.457241 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5850 12:11:51.460371 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5851 12:11:51.466820 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:11:51.470507 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:11:51.473433 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:11:51.480003 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 12:11:51.483811 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 12:11:51.487081 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 12:11:51.493528 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:11:51.496746 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:11:51.500020 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:11:51.506447 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:11:51.510098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:11:51.513293 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:11:51.519645 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:11:51.523221 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:11:51.526175 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 12:11:51.533084 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 12:11:51.533179 Total UI for P1: 0, mck2ui 16
5868 12:11:51.539329 best dqsien dly found for B0: ( 1, 2, 26)
5869 12:11:51.539452 Total UI for P1: 0, mck2ui 16
5870 12:11:51.546243 best dqsien dly found for B1: ( 1, 2, 26)
5871 12:11:51.549527 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5872 12:11:51.552877 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5873 12:11:51.552976
5874 12:11:51.556043 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5875 12:11:51.559310 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5876 12:11:51.562515 [Gating] SW calibration Done
5877 12:11:51.562655 ==
5878 12:11:51.566195 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 12:11:51.569472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 12:11:51.569584 ==
5881 12:11:51.572915 RX Vref Scan: 0
5882 12:11:51.573055
5883 12:11:51.573171 RX Vref 0 -> 0, step: 1
5884 12:11:51.573287
5885 12:11:51.575905 RX Delay -80 -> 252, step: 8
5886 12:11:51.578857 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5887 12:11:51.585762 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5888 12:11:51.589067 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5889 12:11:51.592301 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5890 12:11:51.595385 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5891 12:11:51.598621 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5892 12:11:51.605063 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5893 12:11:51.608259 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5894 12:11:51.612105 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5895 12:11:51.615290 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5896 12:11:51.618423 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5897 12:11:51.625190 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5898 12:11:51.628259 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5899 12:11:51.631276 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5900 12:11:51.635001 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5901 12:11:51.638099 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5902 12:11:51.638191 ==
5903 12:11:51.641852 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 12:11:51.648186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 12:11:51.648279 ==
5906 12:11:51.648348 DQS Delay:
5907 12:11:51.651170 DQS0 = 0, DQS1 = 0
5908 12:11:51.651282 DQM Delay:
5909 12:11:51.651384 DQM0 = 100, DQM1 = 92
5910 12:11:51.654447 DQ Delay:
5911 12:11:51.658235 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5912 12:11:51.661507 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5913 12:11:51.664678 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5914 12:11:51.668073 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5915 12:11:51.668162
5916 12:11:51.668261
5917 12:11:51.668352 ==
5918 12:11:51.671196 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 12:11:51.674474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 12:11:51.674552 ==
5921 12:11:51.674615
5922 12:11:51.674676
5923 12:11:51.677892 TX Vref Scan disable
5924 12:11:51.681087 == TX Byte 0 ==
5925 12:11:51.684160 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 12:11:51.687818 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 12:11:51.691012 == TX Byte 1 ==
5928 12:11:51.694291 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5929 12:11:51.697602 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5930 12:11:51.697681 ==
5931 12:11:51.700674 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 12:11:51.707704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 12:11:51.707786 ==
5934 12:11:51.707850
5935 12:11:51.707910
5936 12:11:51.707968 TX Vref Scan disable
5937 12:11:51.711624 == TX Byte 0 ==
5938 12:11:51.714899 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5939 12:11:51.721335 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5940 12:11:51.721484 == TX Byte 1 ==
5941 12:11:51.724470 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5942 12:11:51.730884 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5943 12:11:51.731027
5944 12:11:51.731151 [DATLAT]
5945 12:11:51.731257 Freq=933, CH1 RK1
5946 12:11:51.731371
5947 12:11:51.734129 DATLAT Default: 0xb
5948 12:11:51.737872 0, 0xFFFF, sum = 0
5949 12:11:51.737988 1, 0xFFFF, sum = 0
5950 12:11:51.740911 2, 0xFFFF, sum = 0
5951 12:11:51.741028 3, 0xFFFF, sum = 0
5952 12:11:51.744549 4, 0xFFFF, sum = 0
5953 12:11:51.744675 5, 0xFFFF, sum = 0
5954 12:11:51.747543 6, 0xFFFF, sum = 0
5955 12:11:51.747656 7, 0xFFFF, sum = 0
5956 12:11:51.751223 8, 0xFFFF, sum = 0
5957 12:11:51.751334 9, 0xFFFF, sum = 0
5958 12:11:51.754261 10, 0x0, sum = 1
5959 12:11:51.754365 11, 0x0, sum = 2
5960 12:11:51.757483 12, 0x0, sum = 3
5961 12:11:51.757600 13, 0x0, sum = 4
5962 12:11:51.760604 best_step = 11
5963 12:11:51.760723
5964 12:11:51.760825 ==
5965 12:11:51.763932 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 12:11:51.767675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 12:11:51.767790 ==
5968 12:11:51.767900 RX Vref Scan: 0
5969 12:11:51.767994
5970 12:11:51.770969 RX Vref 0 -> 0, step: 1
5971 12:11:51.771076
5972 12:11:51.774168 RX Delay -61 -> 252, step: 4
5973 12:11:51.780524 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5974 12:11:51.784187 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5975 12:11:51.787258 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5976 12:11:51.790362 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5977 12:11:51.794188 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5978 12:11:51.796840 iDelay=207, Bit 5, Center 112 (23 ~ 202) 180
5979 12:11:51.804065 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5980 12:11:51.807107 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5981 12:11:51.810386 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5982 12:11:51.813637 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5983 12:11:51.816940 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5984 12:11:51.823297 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5985 12:11:51.826512 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5986 12:11:51.829734 iDelay=207, Bit 13, Center 104 (15 ~ 194) 180
5987 12:11:51.832976 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
5988 12:11:51.840050 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5989 12:11:51.840182 ==
5990 12:11:51.843067 Dram Type= 6, Freq= 0, CH_1, rank 1
5991 12:11:51.846129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5992 12:11:51.846215 ==
5993 12:11:51.846285 DQS Delay:
5994 12:11:51.849859 DQS0 = 0, DQS1 = 0
5995 12:11:51.849938 DQM Delay:
5996 12:11:51.852932 DQM0 = 101, DQM1 = 95
5997 12:11:51.853042 DQ Delay:
5998 12:11:51.856045 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
5999 12:11:51.859655 DQ4 =98, DQ5 =112, DQ6 =114, DQ7 =98
6000 12:11:51.862982 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
6001 12:11:51.866048 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =104
6002 12:11:51.866159
6003 12:11:51.866254
6004 12:11:51.875835 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6005 12:11:51.875937 CH1 RK1: MR19=505, MR18=701
6006 12:11:51.882242 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
6007 12:11:51.886149 [RxdqsGatingPostProcess] freq 933
6008 12:11:51.892494 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6009 12:11:51.895599 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 12:11:51.898847 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 12:11:51.902672 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 12:11:51.905945 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 12:11:51.909159 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 12:11:51.909242 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 12:11:51.912315 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 12:11:51.915598 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 12:11:51.918778 Pre-setting of DQS Precalculation
6018 12:11:51.925215 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6019 12:11:51.932223 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6020 12:11:51.938818 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6021 12:11:51.938940
6022 12:11:51.939041
6023 12:11:51.942043 [Calibration Summary] 1866 Mbps
6024 12:11:51.945303 CH 0, Rank 0
6025 12:11:51.945441 SW Impedance : PASS
6026 12:11:51.948328 DUTY Scan : NO K
6027 12:11:51.952050 ZQ Calibration : PASS
6028 12:11:51.952182 Jitter Meter : NO K
6029 12:11:51.955062 CBT Training : PASS
6030 12:11:51.955195 Write leveling : PASS
6031 12:11:51.958809 RX DQS gating : PASS
6032 12:11:51.961804 RX DQ/DQS(RDDQC) : PASS
6033 12:11:51.961921 TX DQ/DQS : PASS
6034 12:11:51.965427 RX DATLAT : PASS
6035 12:11:51.968474 RX DQ/DQS(Engine): PASS
6036 12:11:51.968604 TX OE : NO K
6037 12:11:51.971733 All Pass.
6038 12:11:51.971862
6039 12:11:51.971960 CH 0, Rank 1
6040 12:11:51.974903 SW Impedance : PASS
6041 12:11:51.975015 DUTY Scan : NO K
6042 12:11:51.978674 ZQ Calibration : PASS
6043 12:11:51.981940 Jitter Meter : NO K
6044 12:11:51.982047 CBT Training : PASS
6045 12:11:51.985141 Write leveling : PASS
6046 12:11:51.988454 RX DQS gating : PASS
6047 12:11:51.988591 RX DQ/DQS(RDDQC) : PASS
6048 12:11:51.991561 TX DQ/DQS : PASS
6049 12:11:51.994830 RX DATLAT : PASS
6050 12:11:51.994939 RX DQ/DQS(Engine): PASS
6051 12:11:51.997982 TX OE : NO K
6052 12:11:51.998088 All Pass.
6053 12:11:51.998196
6054 12:11:52.001818 CH 1, Rank 0
6055 12:11:52.001924 SW Impedance : PASS
6056 12:11:52.005065 DUTY Scan : NO K
6057 12:11:52.008237 ZQ Calibration : PASS
6058 12:11:52.008347 Jitter Meter : NO K
6059 12:11:52.011557 CBT Training : PASS
6060 12:11:52.011675 Write leveling : PASS
6061 12:11:52.015230 RX DQS gating : PASS
6062 12:11:52.018417 RX DQ/DQS(RDDQC) : PASS
6063 12:11:52.018524 TX DQ/DQS : PASS
6064 12:11:52.021665 RX DATLAT : PASS
6065 12:11:52.024858 RX DQ/DQS(Engine): PASS
6066 12:11:52.024950 TX OE : NO K
6067 12:11:52.028064 All Pass.
6068 12:11:52.028143
6069 12:11:52.028207 CH 1, Rank 1
6070 12:11:52.031839 SW Impedance : PASS
6071 12:11:52.031913 DUTY Scan : NO K
6072 12:11:52.034922 ZQ Calibration : PASS
6073 12:11:52.038176 Jitter Meter : NO K
6074 12:11:52.038291 CBT Training : PASS
6075 12:11:52.041522 Write leveling : PASS
6076 12:11:52.044539 RX DQS gating : PASS
6077 12:11:52.044627 RX DQ/DQS(RDDQC) : PASS
6078 12:11:52.048324 TX DQ/DQS : PASS
6079 12:11:52.051525 RX DATLAT : PASS
6080 12:11:52.051629 RX DQ/DQS(Engine): PASS
6081 12:11:52.054567 TX OE : NO K
6082 12:11:52.054674 All Pass.
6083 12:11:52.054769
6084 12:11:52.057796 DramC Write-DBI off
6085 12:11:52.061453 PER_BANK_REFRESH: Hybrid Mode
6086 12:11:52.061573 TX_TRACKING: ON
6087 12:11:52.071401 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6088 12:11:52.074546 [FAST_K] Save calibration result to emmc
6089 12:11:52.077772 dramc_set_vcore_voltage set vcore to 650000
6090 12:11:52.080819 Read voltage for 400, 6
6091 12:11:52.080928 Vio18 = 0
6092 12:11:52.081008 Vcore = 650000
6093 12:11:52.084069 Vdram = 0
6094 12:11:52.084167 Vddq = 0
6095 12:11:52.084281 Vmddr = 0
6096 12:11:52.091121 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6097 12:11:52.094142 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6098 12:11:52.097406 MEM_TYPE=3, freq_sel=20
6099 12:11:52.100642 sv_algorithm_assistance_LP4_800
6100 12:11:52.104348 ============ PULL DRAM RESETB DOWN ============
6101 12:11:52.107616 ========== PULL DRAM RESETB DOWN end =========
6102 12:11:52.114031 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6103 12:11:52.117250 ===================================
6104 12:11:52.120432 LPDDR4 DRAM CONFIGURATION
6105 12:11:52.124298 ===================================
6106 12:11:52.124408 EX_ROW_EN[0] = 0x0
6107 12:11:52.126919 EX_ROW_EN[1] = 0x0
6108 12:11:52.127046 LP4Y_EN = 0x0
6109 12:11:52.130863 WORK_FSP = 0x0
6110 12:11:52.130942 WL = 0x2
6111 12:11:52.133967 RL = 0x2
6112 12:11:52.134047 BL = 0x2
6113 12:11:52.137250 RPST = 0x0
6114 12:11:52.137331 RD_PRE = 0x0
6115 12:11:52.140338 WR_PRE = 0x1
6116 12:11:52.140439 WR_PST = 0x0
6117 12:11:52.143556 DBI_WR = 0x0
6118 12:11:52.143628 DBI_RD = 0x0
6119 12:11:52.146795 OTF = 0x1
6120 12:11:52.150724 ===================================
6121 12:11:52.153870 ===================================
6122 12:11:52.153990 ANA top config
6123 12:11:52.156965 ===================================
6124 12:11:52.160024 DLL_ASYNC_EN = 0
6125 12:11:52.163646 ALL_SLAVE_EN = 1
6126 12:11:52.166703 NEW_RANK_MODE = 1
6127 12:11:52.169925 DLL_IDLE_MODE = 1
6128 12:11:52.170042 LP45_APHY_COMB_EN = 1
6129 12:11:52.173799 TX_ODT_DIS = 1
6130 12:11:52.176817 NEW_8X_MODE = 1
6131 12:11:52.180040 ===================================
6132 12:11:52.183238 ===================================
6133 12:11:52.186422 data_rate = 800
6134 12:11:52.189614 CKR = 1
6135 12:11:52.189697 DQ_P2S_RATIO = 4
6136 12:11:52.192914 ===================================
6137 12:11:52.196800 CA_P2S_RATIO = 4
6138 12:11:52.199952 DQ_CA_OPEN = 0
6139 12:11:52.203213 DQ_SEMI_OPEN = 1
6140 12:11:52.206439 CA_SEMI_OPEN = 1
6141 12:11:52.209489 CA_FULL_RATE = 0
6142 12:11:52.209600 DQ_CKDIV4_EN = 0
6143 12:11:52.213278 CA_CKDIV4_EN = 1
6144 12:11:52.216552 CA_PREDIV_EN = 0
6145 12:11:52.219918 PH8_DLY = 0
6146 12:11:52.222957 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6147 12:11:52.226200 DQ_AAMCK_DIV = 0
6148 12:11:52.226315 CA_AAMCK_DIV = 0
6149 12:11:52.229419 CA_ADMCK_DIV = 4
6150 12:11:52.233260 DQ_TRACK_CA_EN = 0
6151 12:11:52.236500 CA_PICK = 800
6152 12:11:52.239636 CA_MCKIO = 400
6153 12:11:52.242869 MCKIO_SEMI = 400
6154 12:11:52.245977 PLL_FREQ = 3016
6155 12:11:52.249221 DQ_UI_PI_RATIO = 32
6156 12:11:52.249332 CA_UI_PI_RATIO = 32
6157 12:11:52.252525 ===================================
6158 12:11:52.255807 ===================================
6159 12:11:52.258996 memory_type:LPDDR4
6160 12:11:52.262849 GP_NUM : 10
6161 12:11:52.262967 SRAM_EN : 1
6162 12:11:52.265933 MD32_EN : 0
6163 12:11:52.269099 ===================================
6164 12:11:52.272296 [ANA_INIT] >>>>>>>>>>>>>>
6165 12:11:52.276174 <<<<<< [CONFIGURE PHASE]: ANA_TX
6166 12:11:52.279247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6167 12:11:52.282383 ===================================
6168 12:11:52.282469 data_rate = 800,PCW = 0X7400
6169 12:11:52.285522 ===================================
6170 12:11:52.289283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6171 12:11:52.295521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 12:11:52.309238 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 12:11:52.312270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6174 12:11:52.315492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6175 12:11:52.318759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6176 12:11:52.321955 [ANA_INIT] flow start
6177 12:11:52.322065 [ANA_INIT] PLL >>>>>>>>
6178 12:11:52.325195 [ANA_INIT] PLL <<<<<<<<
6179 12:11:52.328950 [ANA_INIT] MIDPI >>>>>>>>
6180 12:11:52.329066 [ANA_INIT] MIDPI <<<<<<<<
6181 12:11:52.332147 [ANA_INIT] DLL >>>>>>>>
6182 12:11:52.335459 [ANA_INIT] flow end
6183 12:11:52.338696 ============ LP4 DIFF to SE enter ============
6184 12:11:52.341959 ============ LP4 DIFF to SE exit ============
6185 12:11:52.345245 [ANA_INIT] <<<<<<<<<<<<<
6186 12:11:52.348395 [Flow] Enable top DCM control >>>>>
6187 12:11:52.351639 [Flow] Enable top DCM control <<<<<
6188 12:11:52.355381 Enable DLL master slave shuffle
6189 12:11:52.358701 ==============================================================
6190 12:11:52.361960 Gating Mode config
6191 12:11:52.368221 ==============================================================
6192 12:11:52.368339 Config description:
6193 12:11:52.378185 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6194 12:11:52.384560 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6195 12:11:52.391324 SELPH_MODE 0: By rank 1: By Phase
6196 12:11:52.394620 ==============================================================
6197 12:11:52.397927 GAT_TRACK_EN = 0
6198 12:11:52.401242 RX_GATING_MODE = 2
6199 12:11:52.404425 RX_GATING_TRACK_MODE = 2
6200 12:11:52.407696 SELPH_MODE = 1
6201 12:11:52.410972 PICG_EARLY_EN = 1
6202 12:11:52.414772 VALID_LAT_VALUE = 1
6203 12:11:52.417862 ==============================================================
6204 12:11:52.424322 Enter into Gating configuration >>>>
6205 12:11:52.424444 Exit from Gating configuration <<<<
6206 12:11:52.427484 Enter into DVFS_PRE_config >>>>>
6207 12:11:52.441013 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6208 12:11:52.444337 Exit from DVFS_PRE_config <<<<<
6209 12:11:52.447565 Enter into PICG configuration >>>>
6210 12:11:52.450807 Exit from PICG configuration <<<<
6211 12:11:52.454031 [RX_INPUT] configuration >>>>>
6212 12:11:52.454143 [RX_INPUT] configuration <<<<<
6213 12:11:52.460524 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6214 12:11:52.467047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6215 12:11:52.470238 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 12:11:52.477089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 12:11:52.483539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6218 12:11:52.489932 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6219 12:11:52.493176 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6220 12:11:52.496867 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6221 12:11:52.503162 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6222 12:11:52.506359 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6223 12:11:52.509685 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6224 12:11:52.516295 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6225 12:11:52.519460 ===================================
6226 12:11:52.519571 LPDDR4 DRAM CONFIGURATION
6227 12:11:52.523086 ===================================
6228 12:11:52.526244 EX_ROW_EN[0] = 0x0
6229 12:11:52.529495 EX_ROW_EN[1] = 0x0
6230 12:11:52.529605 LP4Y_EN = 0x0
6231 12:11:52.532844 WORK_FSP = 0x0
6232 12:11:52.532966 WL = 0x2
6233 12:11:52.536021 RL = 0x2
6234 12:11:52.536126 BL = 0x2
6235 12:11:52.539217 RPST = 0x0
6236 12:11:52.539324 RD_PRE = 0x0
6237 12:11:52.543094 WR_PRE = 0x1
6238 12:11:52.543196 WR_PST = 0x0
6239 12:11:52.546248 DBI_WR = 0x0
6240 12:11:52.546352 DBI_RD = 0x0
6241 12:11:52.549509 OTF = 0x1
6242 12:11:52.552682 ===================================
6243 12:11:52.555699 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6244 12:11:52.559575 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6245 12:11:52.566029 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6246 12:11:52.569294 ===================================
6247 12:11:52.569407 LPDDR4 DRAM CONFIGURATION
6248 12:11:52.572660 ===================================
6249 12:11:52.575657 EX_ROW_EN[0] = 0x10
6250 12:11:52.579342 EX_ROW_EN[1] = 0x0
6251 12:11:52.579444 LP4Y_EN = 0x0
6252 12:11:52.582437 WORK_FSP = 0x0
6253 12:11:52.582546 WL = 0x2
6254 12:11:52.585563 RL = 0x2
6255 12:11:52.585672 BL = 0x2
6256 12:11:52.589374 RPST = 0x0
6257 12:11:52.589484 RD_PRE = 0x0
6258 12:11:52.592607 WR_PRE = 0x1
6259 12:11:52.592715 WR_PST = 0x0
6260 12:11:52.595750 DBI_WR = 0x0
6261 12:11:52.595857 DBI_RD = 0x0
6262 12:11:52.598937 OTF = 0x1
6263 12:11:52.602204 ===================================
6264 12:11:52.609185 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6265 12:11:52.612328 nWR fixed to 30
6266 12:11:52.612442 [ModeRegInit_LP4] CH0 RK0
6267 12:11:52.615615 [ModeRegInit_LP4] CH0 RK1
6268 12:11:52.618887 [ModeRegInit_LP4] CH1 RK0
6269 12:11:52.622066 [ModeRegInit_LP4] CH1 RK1
6270 12:11:52.622183 match AC timing 19
6271 12:11:52.628932 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6272 12:11:52.632064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6273 12:11:52.635284 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6274 12:11:52.641808 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6275 12:11:52.645061 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6276 12:11:52.645170 ==
6277 12:11:52.648278 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 12:11:52.652163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:11:52.652270 ==
6280 12:11:52.658505 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 12:11:52.665283 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6282 12:11:52.668464 [CA 0] Center 36 (8~64) winsize 57
6283 12:11:52.671642 [CA 1] Center 36 (8~64) winsize 57
6284 12:11:52.674850 [CA 2] Center 36 (8~64) winsize 57
6285 12:11:52.674952 [CA 3] Center 36 (8~64) winsize 57
6286 12:11:52.678507 [CA 4] Center 36 (8~64) winsize 57
6287 12:11:52.681705 [CA 5] Center 36 (8~64) winsize 57
6288 12:11:52.681806
6289 12:11:52.688467 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6290 12:11:52.688601
6291 12:11:52.691531 [CATrainingPosCal] consider 1 rank data
6292 12:11:52.694836 u2DelayCellTimex100 = 270/100 ps
6293 12:11:52.698066 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:11:52.701155 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:11:52.704857 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:11:52.707920 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:11:52.711639 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:11:52.714810 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:11:52.714917
6300 12:11:52.718034 CA PerBit enable=1, Macro0, CA PI delay=36
6301 12:11:52.718143
6302 12:11:52.721214 [CBTSetCACLKResult] CA Dly = 36
6303 12:11:52.724447 CS Dly: 1 (0~32)
6304 12:11:52.724555 ==
6305 12:11:52.727546 Dram Type= 6, Freq= 0, CH_0, rank 1
6306 12:11:52.730764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 12:11:52.730868 ==
6308 12:11:52.737585 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6309 12:11:52.744109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6310 12:11:52.747323 [CA 0] Center 36 (8~64) winsize 57
6311 12:11:52.747434 [CA 1] Center 36 (8~64) winsize 57
6312 12:11:52.751222 [CA 2] Center 36 (8~64) winsize 57
6313 12:11:52.754463 [CA 3] Center 36 (8~64) winsize 57
6314 12:11:52.757750 [CA 4] Center 36 (8~64) winsize 57
6315 12:11:52.760893 [CA 5] Center 36 (8~64) winsize 57
6316 12:11:52.760998
6317 12:11:52.764036 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6318 12:11:52.764145
6319 12:11:52.767259 [CATrainingPosCal] consider 2 rank data
6320 12:11:52.770506 u2DelayCellTimex100 = 270/100 ps
6321 12:11:52.774312 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 12:11:52.780577 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 12:11:52.784232 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 12:11:52.787301 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 12:11:52.790977 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 12:11:52.793932 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 12:11:52.794041
6328 12:11:52.797571 CA PerBit enable=1, Macro0, CA PI delay=36
6329 12:11:52.797672
6330 12:11:52.800872 [CBTSetCACLKResult] CA Dly = 36
6331 12:11:52.800974 CS Dly: 1 (0~32)
6332 12:11:52.804135
6333 12:11:52.807221 ----->DramcWriteLeveling(PI) begin...
6334 12:11:52.807340 ==
6335 12:11:52.810696 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 12:11:52.813861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 12:11:52.813969 ==
6338 12:11:52.816989 Write leveling (Byte 0): 40 => 8
6339 12:11:52.820758 Write leveling (Byte 1): 32 => 0
6340 12:11:52.823962 DramcWriteLeveling(PI) end<-----
6341 12:11:52.824067
6342 12:11:52.824160 ==
6343 12:11:52.827162 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 12:11:52.830383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 12:11:52.830485 ==
6346 12:11:52.833492 [Gating] SW mode calibration
6347 12:11:52.840425 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6348 12:11:52.846769 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6349 12:11:52.849835 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 12:11:52.853554 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 12:11:52.860003 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 12:11:52.863302 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 12:11:52.866656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 12:11:52.873134 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 12:11:52.876311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 12:11:52.880174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 12:11:52.886562 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 12:11:52.886676 Total UI for P1: 0, mck2ui 16
6359 12:11:52.892823 best dqsien dly found for B0: ( 0, 14, 24)
6360 12:11:52.892932 Total UI for P1: 0, mck2ui 16
6361 12:11:52.899661 best dqsien dly found for B1: ( 0, 14, 24)
6362 12:11:52.903260 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6363 12:11:52.906593 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6364 12:11:52.906700
6365 12:11:52.909746 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 12:11:52.912761 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 12:11:52.916008 [Gating] SW calibration Done
6368 12:11:52.916122 ==
6369 12:11:52.919688 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 12:11:52.922849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 12:11:52.922964 ==
6372 12:11:52.925949 RX Vref Scan: 0
6373 12:11:52.926062
6374 12:11:52.926160 RX Vref 0 -> 0, step: 1
6375 12:11:52.926262
6376 12:11:52.929801 RX Delay -410 -> 252, step: 16
6377 12:11:52.936160 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6378 12:11:52.939301 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6379 12:11:52.942547 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6380 12:11:52.945840 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6381 12:11:52.952789 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6382 12:11:52.955817 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6383 12:11:52.959042 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6384 12:11:52.962300 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6385 12:11:52.969307 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6386 12:11:52.972589 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6387 12:11:52.975619 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6388 12:11:52.978844 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6389 12:11:52.985845 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6390 12:11:52.988958 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6391 12:11:52.992130 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6392 12:11:52.999057 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6393 12:11:52.999172 ==
6394 12:11:53.002266 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 12:11:53.005388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 12:11:53.005467 ==
6397 12:11:53.005539 DQS Delay:
6398 12:11:53.008483 DQS0 = 43, DQS1 = 59
6399 12:11:53.008591 DQM Delay:
6400 12:11:53.011665 DQM0 = 10, DQM1 = 13
6401 12:11:53.011764 DQ Delay:
6402 12:11:53.014983 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6403 12:11:53.018311 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6404 12:11:53.022046 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6405 12:11:53.025143 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6406 12:11:53.025264
6407 12:11:53.025365
6408 12:11:53.025458 ==
6409 12:11:53.028360 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 12:11:53.031502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 12:11:53.031609 ==
6412 12:11:53.031677
6413 12:11:53.031739
6414 12:11:53.034827 TX Vref Scan disable
6415 12:11:53.038562 == TX Byte 0 ==
6416 12:11:53.041681 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 12:11:53.044908 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 12:11:53.048179 == TX Byte 1 ==
6419 12:11:53.051438 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6420 12:11:53.054539 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6421 12:11:53.054655 ==
6422 12:11:53.058349 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 12:11:53.061662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 12:11:53.064970 ==
6425 12:11:53.065134
6426 12:11:53.065234
6427 12:11:53.065326 TX Vref Scan disable
6428 12:11:53.068286 == TX Byte 0 ==
6429 12:11:53.071391 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 12:11:53.074430 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 12:11:53.077762 == TX Byte 1 ==
6432 12:11:53.081409 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6433 12:11:53.084682 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6434 12:11:53.084773
6435 12:11:53.087893 [DATLAT]
6436 12:11:53.088044 Freq=400, CH0 RK0
6437 12:11:53.088151
6438 12:11:53.091162 DATLAT Default: 0xf
6439 12:11:53.091267 0, 0xFFFF, sum = 0
6440 12:11:53.094436 1, 0xFFFF, sum = 0
6441 12:11:53.094544 2, 0xFFFF, sum = 0
6442 12:11:53.098085 3, 0xFFFF, sum = 0
6443 12:11:53.098190 4, 0xFFFF, sum = 0
6444 12:11:53.101160 5, 0xFFFF, sum = 0
6445 12:11:53.101273 6, 0xFFFF, sum = 0
6446 12:11:53.104372 7, 0xFFFF, sum = 0
6447 12:11:53.104480 8, 0xFFFF, sum = 0
6448 12:11:53.108193 9, 0xFFFF, sum = 0
6449 12:11:53.108305 10, 0xFFFF, sum = 0
6450 12:11:53.111348 11, 0xFFFF, sum = 0
6451 12:11:53.111457 12, 0xFFFF, sum = 0
6452 12:11:53.114448 13, 0x0, sum = 1
6453 12:11:53.114550 14, 0x0, sum = 2
6454 12:11:53.117609 15, 0x0, sum = 3
6455 12:11:53.117721 16, 0x0, sum = 4
6456 12:11:53.120779 best_step = 14
6457 12:11:53.120875
6458 12:11:53.120941 ==
6459 12:11:53.124385 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 12:11:53.127561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 12:11:53.127667 ==
6462 12:11:53.131193 RX Vref Scan: 1
6463 12:11:53.131307
6464 12:11:53.131403 RX Vref 0 -> 0, step: 1
6465 12:11:53.131501
6466 12:11:53.134311 RX Delay -359 -> 252, step: 8
6467 12:11:53.134435
6468 12:11:53.137639 Set Vref, RX VrefLevel [Byte0]: 59
6469 12:11:53.140832 [Byte1]: 56
6470 12:11:53.145813
6471 12:11:53.145922 Final RX Vref Byte 0 = 59 to rank0
6472 12:11:53.148904 Final RX Vref Byte 1 = 56 to rank0
6473 12:11:53.152088 Final RX Vref Byte 0 = 59 to rank1
6474 12:11:53.155394 Final RX Vref Byte 1 = 56 to rank1==
6475 12:11:53.159117 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 12:11:53.165546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 12:11:53.165683 ==
6478 12:11:53.165793 DQS Delay:
6479 12:11:53.168773 DQS0 = 44, DQS1 = 60
6480 12:11:53.168880 DQM Delay:
6481 12:11:53.168983 DQM0 = 8, DQM1 = 11
6482 12:11:53.171956 DQ Delay:
6483 12:11:53.175191 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6484 12:11:53.178416 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6485 12:11:53.178525 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6486 12:11:53.182231 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6487 12:11:53.184896
6488 12:11:53.185008
6489 12:11:53.191474 [DQSOSCAuto] RK0, (LSB)MR18= 0xc084, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6490 12:11:53.194782 CH0 RK0: MR19=C0C, MR18=C084
6491 12:11:53.201698 CH0_RK0: MR19=0xC0C, MR18=0xC084, DQSOSC=386, MR23=63, INC=396, DEC=264
6492 12:11:53.201813 ==
6493 12:11:53.204907 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 12:11:53.207967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 12:11:53.208077 ==
6496 12:11:53.211235 [Gating] SW mode calibration
6497 12:11:53.218199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6498 12:11:53.224492 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6499 12:11:53.228251 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 12:11:53.231379 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 12:11:53.237670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 12:11:53.241564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 12:11:53.244789 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 12:11:53.251138 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 12:11:53.254383 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 12:11:53.257627 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 12:11:53.264641 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 12:11:53.264737 Total UI for P1: 0, mck2ui 16
6509 12:11:53.271137 best dqsien dly found for B0: ( 0, 14, 24)
6510 12:11:53.271238 Total UI for P1: 0, mck2ui 16
6511 12:11:53.277583 best dqsien dly found for B1: ( 0, 14, 24)
6512 12:11:53.280873 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6513 12:11:53.283989 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6514 12:11:53.284100
6515 12:11:53.287255 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 12:11:53.291036 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 12:11:53.294273 [Gating] SW calibration Done
6518 12:11:53.294383 ==
6519 12:11:53.297509 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 12:11:53.300853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 12:11:53.300934 ==
6522 12:11:53.303980 RX Vref Scan: 0
6523 12:11:53.304083
6524 12:11:53.304178 RX Vref 0 -> 0, step: 1
6525 12:11:53.304270
6526 12:11:53.307130 RX Delay -410 -> 252, step: 16
6527 12:11:53.314083 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6528 12:11:53.317282 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6529 12:11:53.320346 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6530 12:11:53.324125 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6531 12:11:53.330415 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6532 12:11:53.333518 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6533 12:11:53.337288 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6534 12:11:53.340414 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6535 12:11:53.346895 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6536 12:11:53.350093 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6537 12:11:53.353282 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6538 12:11:53.360140 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6539 12:11:53.363416 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6540 12:11:53.366620 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6541 12:11:53.369916 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6542 12:11:53.376274 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6543 12:11:53.376403 ==
6544 12:11:53.380094 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 12:11:53.383356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 12:11:53.383465 ==
6547 12:11:53.383572 DQS Delay:
6548 12:11:53.386554 DQS0 = 43, DQS1 = 59
6549 12:11:53.386663 DQM Delay:
6550 12:11:53.389837 DQM0 = 10, DQM1 = 16
6551 12:11:53.389988 DQ Delay:
6552 12:11:53.392899 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6553 12:11:53.396263 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6554 12:11:53.399417 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6555 12:11:53.402686 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6556 12:11:53.402798
6557 12:11:53.402912
6558 12:11:53.403004 ==
6559 12:11:53.405950 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 12:11:53.409864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 12:11:53.409984 ==
6562 12:11:53.410084
6563 12:11:53.410194
6564 12:11:53.412998 TX Vref Scan disable
6565 12:11:53.416194 == TX Byte 0 ==
6566 12:11:53.419839 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6567 12:11:53.422894 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6568 12:11:53.426159 == TX Byte 1 ==
6569 12:11:53.429231 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6570 12:11:53.432956 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6571 12:11:53.433036 ==
6572 12:11:53.436143 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 12:11:53.439255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 12:11:53.439433 ==
6575 12:11:53.439561
6576 12:11:53.442856
6577 12:11:53.442968 TX Vref Scan disable
6578 12:11:53.446131 == TX Byte 0 ==
6579 12:11:53.449444 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6580 12:11:53.452628 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6581 12:11:53.455895 == TX Byte 1 ==
6582 12:11:53.459597 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6583 12:11:53.462891 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6584 12:11:53.462999
6585 12:11:53.463100 [DATLAT]
6586 12:11:53.466176 Freq=400, CH0 RK1
6587 12:11:53.466279
6588 12:11:53.466373 DATLAT Default: 0xe
6589 12:11:53.469395 0, 0xFFFF, sum = 0
6590 12:11:53.472536 1, 0xFFFF, sum = 0
6591 12:11:53.472653 2, 0xFFFF, sum = 0
6592 12:11:53.475768 3, 0xFFFF, sum = 0
6593 12:11:53.475894 4, 0xFFFF, sum = 0
6594 12:11:53.478984 5, 0xFFFF, sum = 0
6595 12:11:53.479114 6, 0xFFFF, sum = 0
6596 12:11:53.482681 7, 0xFFFF, sum = 0
6597 12:11:53.482793 8, 0xFFFF, sum = 0
6598 12:11:53.485867 9, 0xFFFF, sum = 0
6599 12:11:53.485979 10, 0xFFFF, sum = 0
6600 12:11:53.489088 11, 0xFFFF, sum = 0
6601 12:11:53.489196 12, 0xFFFF, sum = 0
6602 12:11:53.492314 13, 0x0, sum = 1
6603 12:11:53.492419 14, 0x0, sum = 2
6604 12:11:53.495434 15, 0x0, sum = 3
6605 12:11:53.495551 16, 0x0, sum = 4
6606 12:11:53.499259 best_step = 14
6607 12:11:53.499365
6608 12:11:53.499466 ==
6609 12:11:53.502463 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 12:11:53.505679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 12:11:53.505791 ==
6612 12:11:53.509031 RX Vref Scan: 0
6613 12:11:53.509144
6614 12:11:53.509242 RX Vref 0 -> 0, step: 1
6615 12:11:53.509337
6616 12:11:53.512260 RX Delay -359 -> 252, step: 8
6617 12:11:53.519785 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6618 12:11:53.522907 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6619 12:11:53.526488 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6620 12:11:53.532789 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6621 12:11:53.536647 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6622 12:11:53.539680 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6623 12:11:53.542939 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6624 12:11:53.549620 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6625 12:11:53.552927 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6626 12:11:53.556159 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6627 12:11:53.559403 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6628 12:11:53.566323 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6629 12:11:53.569558 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6630 12:11:53.572479 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6631 12:11:53.576052 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6632 12:11:53.582469 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6633 12:11:53.582589 ==
6634 12:11:53.585783 Dram Type= 6, Freq= 0, CH_0, rank 1
6635 12:11:53.588974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 12:11:53.589081 ==
6637 12:11:53.589179 DQS Delay:
6638 12:11:53.592275 DQS0 = 44, DQS1 = 60
6639 12:11:53.592377 DQM Delay:
6640 12:11:53.595488 DQM0 = 8, DQM1 = 14
6641 12:11:53.595592 DQ Delay:
6642 12:11:53.599409 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6643 12:11:53.602631 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6644 12:11:53.605795 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6645 12:11:53.608908 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6646 12:11:53.609015
6647 12:11:53.609113
6648 12:11:53.615265 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23e, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6649 12:11:53.619034 CH0 RK1: MR19=C0C, MR18=B23E
6650 12:11:53.625254 CH0_RK1: MR19=0xC0C, MR18=0xB23E, DQSOSC=387, MR23=63, INC=394, DEC=262
6651 12:11:53.629084 [RxdqsGatingPostProcess] freq 400
6652 12:11:53.635134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6653 12:11:53.638976 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 12:11:53.642093 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 12:11:53.645317 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 12:11:53.648473 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 12:11:53.648600 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 12:11:53.651601 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 12:11:53.655426 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 12:11:53.658665 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 12:11:53.661876 Pre-setting of DQS Precalculation
6662 12:11:53.668660 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6663 12:11:53.668791 ==
6664 12:11:53.672001 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 12:11:53.675266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:11:53.675377 ==
6667 12:11:53.681584 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 12:11:53.688048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6669 12:11:53.691322 [CA 0] Center 36 (8~64) winsize 57
6670 12:11:53.694506 [CA 1] Center 36 (8~64) winsize 57
6671 12:11:53.694614 [CA 2] Center 36 (8~64) winsize 57
6672 12:11:53.698352 [CA 3] Center 36 (8~64) winsize 57
6673 12:11:53.701564 [CA 4] Center 36 (8~64) winsize 57
6674 12:11:53.704713 [CA 5] Center 36 (8~64) winsize 57
6675 12:11:53.704812
6676 12:11:53.707849 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6677 12:11:53.710959
6678 12:11:53.714828 [CATrainingPosCal] consider 1 rank data
6679 12:11:53.714935 u2DelayCellTimex100 = 270/100 ps
6680 12:11:53.721186 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:11:53.724309 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:11:53.727595 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:11:53.731207 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:11:53.734368 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:11:53.738107 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:11:53.738216
6687 12:11:53.741144 CA PerBit enable=1, Macro0, CA PI delay=36
6688 12:11:53.741219
6689 12:11:53.744330 [CBTSetCACLKResult] CA Dly = 36
6690 12:11:53.747654 CS Dly: 1 (0~32)
6691 12:11:53.747762 ==
6692 12:11:53.750742 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 12:11:53.754483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 12:11:53.754598 ==
6695 12:11:53.760936 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6696 12:11:53.764168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6697 12:11:53.767388 [CA 0] Center 36 (8~64) winsize 57
6698 12:11:53.770613 [CA 1] Center 36 (8~64) winsize 57
6699 12:11:53.774285 [CA 2] Center 36 (8~64) winsize 57
6700 12:11:53.777034 [CA 3] Center 36 (8~64) winsize 57
6701 12:11:53.780911 [CA 4] Center 36 (8~64) winsize 57
6702 12:11:53.783996 [CA 5] Center 36 (8~64) winsize 57
6703 12:11:53.784105
6704 12:11:53.787186 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6705 12:11:53.787293
6706 12:11:53.790401 [CATrainingPosCal] consider 2 rank data
6707 12:11:53.793604 u2DelayCellTimex100 = 270/100 ps
6708 12:11:53.796808 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 12:11:53.803799 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 12:11:53.807089 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 12:11:53.810154 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 12:11:53.813329 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 12:11:53.816521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 12:11:53.816630
6715 12:11:53.820390 CA PerBit enable=1, Macro0, CA PI delay=36
6716 12:11:53.820503
6717 12:11:53.823665 [CBTSetCACLKResult] CA Dly = 36
6718 12:11:53.827008 CS Dly: 1 (0~32)
6719 12:11:53.827112
6720 12:11:53.830146 ----->DramcWriteLeveling(PI) begin...
6721 12:11:53.830259 ==
6722 12:11:53.833274 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 12:11:53.836440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 12:11:53.836564 ==
6725 12:11:53.840182 Write leveling (Byte 0): 40 => 8
6726 12:11:53.843343 Write leveling (Byte 1): 32 => 0
6727 12:11:53.846479 DramcWriteLeveling(PI) end<-----
6728 12:11:53.846593
6729 12:11:53.846691 ==
6730 12:11:53.849673 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 12:11:53.852766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 12:11:53.852883 ==
6733 12:11:53.856536 [Gating] SW mode calibration
6734 12:11:53.862764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6735 12:11:53.869908 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6736 12:11:53.873124 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 12:11:53.876122 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 12:11:53.882671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 12:11:53.885996 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 12:11:53.889786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 12:11:53.896104 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 12:11:53.899321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 12:11:53.902538 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 12:11:53.909690 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 12:11:53.909806 Total UI for P1: 0, mck2ui 16
6746 12:11:53.916155 best dqsien dly found for B0: ( 0, 14, 24)
6747 12:11:53.916280 Total UI for P1: 0, mck2ui 16
6748 12:11:53.922659 best dqsien dly found for B1: ( 0, 14, 24)
6749 12:11:53.925894 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6750 12:11:53.929134 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6751 12:11:53.929245
6752 12:11:53.932374 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 12:11:53.935635 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 12:11:53.938832 [Gating] SW calibration Done
6755 12:11:53.938938 ==
6756 12:11:53.942535 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 12:11:53.945555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 12:11:53.945679 ==
6759 12:11:53.948657 RX Vref Scan: 0
6760 12:11:53.948764
6761 12:11:53.948881 RX Vref 0 -> 0, step: 1
6762 12:11:53.951962
6763 12:11:53.952076 RX Delay -410 -> 252, step: 16
6764 12:11:53.958846 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6765 12:11:53.962015 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6766 12:11:53.965216 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6767 12:11:53.968387 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6768 12:11:53.975400 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6769 12:11:53.978523 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6770 12:11:53.981593 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6771 12:11:53.988054 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6772 12:11:53.991297 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6773 12:11:53.995114 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6774 12:11:53.998363 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6775 12:11:54.004874 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6776 12:11:54.008183 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6777 12:11:54.011378 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6778 12:11:54.014561 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6779 12:11:54.020996 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6780 12:11:54.021127 ==
6781 12:11:54.024181 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 12:11:54.027544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 12:11:54.027656 ==
6784 12:11:54.027758 DQS Delay:
6785 12:11:54.030906 DQS0 = 43, DQS1 = 51
6786 12:11:54.031020 DQM Delay:
6787 12:11:54.034759 DQM0 = 13, DQM1 = 15
6788 12:11:54.034871 DQ Delay:
6789 12:11:54.037922 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6790 12:11:54.041259 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6791 12:11:54.044289 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =0
6792 12:11:54.048038 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6793 12:11:54.048151
6794 12:11:54.048247
6795 12:11:54.048349 ==
6796 12:11:54.051227 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 12:11:54.054313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 12:11:54.054429 ==
6799 12:11:54.054532
6800 12:11:54.057362
6801 12:11:54.057467 TX Vref Scan disable
6802 12:11:54.061118 == TX Byte 0 ==
6803 12:11:54.064365 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 12:11:54.067303 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 12:11:54.071279 == TX Byte 1 ==
6806 12:11:54.074361 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6807 12:11:54.077556 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6808 12:11:54.077669 ==
6809 12:11:54.080816 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 12:11:54.084011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 12:11:54.087118 ==
6812 12:11:54.087251
6813 12:11:54.087351
6814 12:11:54.087468 TX Vref Scan disable
6815 12:11:54.090408 == TX Byte 0 ==
6816 12:11:54.094101 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 12:11:54.097210 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 12:11:54.100381 == TX Byte 1 ==
6819 12:11:54.103566 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6820 12:11:54.106921 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6821 12:11:54.107045
6822 12:11:54.110169 [DATLAT]
6823 12:11:54.110287 Freq=400, CH1 RK0
6824 12:11:54.110396
6825 12:11:54.113585 DATLAT Default: 0xf
6826 12:11:54.113699 0, 0xFFFF, sum = 0
6827 12:11:54.116903 1, 0xFFFF, sum = 0
6828 12:11:54.117016 2, 0xFFFF, sum = 0
6829 12:11:54.120004 3, 0xFFFF, sum = 0
6830 12:11:54.120146 4, 0xFFFF, sum = 0
6831 12:11:54.123948 5, 0xFFFF, sum = 0
6832 12:11:54.124077 6, 0xFFFF, sum = 0
6833 12:11:54.127088 7, 0xFFFF, sum = 0
6834 12:11:54.127196 8, 0xFFFF, sum = 0
6835 12:11:54.130376 9, 0xFFFF, sum = 0
6836 12:11:54.133631 10, 0xFFFF, sum = 0
6837 12:11:54.133743 11, 0xFFFF, sum = 0
6838 12:11:54.136934 12, 0xFFFF, sum = 0
6839 12:11:54.137046 13, 0x0, sum = 1
6840 12:11:54.140201 14, 0x0, sum = 2
6841 12:11:54.140315 15, 0x0, sum = 3
6842 12:11:54.140417 16, 0x0, sum = 4
6843 12:11:54.143386 best_step = 14
6844 12:11:54.143494
6845 12:11:54.143590 ==
6846 12:11:54.146541 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 12:11:54.150288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 12:11:54.150402 ==
6849 12:11:54.153313 RX Vref Scan: 1
6850 12:11:54.153425
6851 12:11:54.156582 RX Vref 0 -> 0, step: 1
6852 12:11:54.156698
6853 12:11:54.156814 RX Delay -343 -> 252, step: 8
6854 12:11:54.156913
6855 12:11:54.159653 Set Vref, RX VrefLevel [Byte0]: 51
6856 12:11:54.162849 [Byte1]: 60
6857 12:11:54.168379
6858 12:11:54.168499 Final RX Vref Byte 0 = 51 to rank0
6859 12:11:54.172086 Final RX Vref Byte 1 = 60 to rank0
6860 12:11:54.175252 Final RX Vref Byte 0 = 51 to rank1
6861 12:11:54.178384 Final RX Vref Byte 1 = 60 to rank1==
6862 12:11:54.181686 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 12:11:54.188576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 12:11:54.188706 ==
6865 12:11:54.188824 DQS Delay:
6866 12:11:54.191927 DQS0 = 44, DQS1 = 56
6867 12:11:54.192038 DQM Delay:
6868 12:11:54.192141 DQM0 = 8, DQM1 = 12
6869 12:11:54.194553 DQ Delay:
6870 12:11:54.197863 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6871 12:11:54.201641 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6872 12:11:54.201766 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6873 12:11:54.204918 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6874 12:11:54.208175
6875 12:11:54.208288
6876 12:11:54.214659 [DQSOSCAuto] RK0, (LSB)MR18= 0x936a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6877 12:11:54.217843 CH1 RK0: MR19=C0C, MR18=936A
6878 12:11:54.224230 CH1_RK0: MR19=0xC0C, MR18=0x936A, DQSOSC=391, MR23=63, INC=386, DEC=257
6879 12:11:54.224352 ==
6880 12:11:54.227392 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 12:11:54.231112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 12:11:54.231248 ==
6883 12:11:54.234236 [Gating] SW mode calibration
6884 12:11:54.240745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6885 12:11:54.247253 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6886 12:11:54.250911 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 12:11:54.254027 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6888 12:11:54.260360 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 12:11:54.264141 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 12:11:54.267167 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 12:11:54.274255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 12:11:54.277121 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 12:11:54.280331 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 12:11:54.287338 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 12:11:54.290509 Total UI for P1: 0, mck2ui 16
6896 12:11:54.293829 best dqsien dly found for B0: ( 0, 14, 24)
6897 12:11:54.293918 Total UI for P1: 0, mck2ui 16
6898 12:11:54.300263 best dqsien dly found for B1: ( 0, 14, 24)
6899 12:11:54.303575 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6900 12:11:54.306767 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6901 12:11:54.306888
6902 12:11:54.309887 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 12:11:54.313142 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 12:11:54.317101 [Gating] SW calibration Done
6905 12:11:54.317217 ==
6906 12:11:54.320248 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 12:11:54.323506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 12:11:54.323615 ==
6909 12:11:54.326804 RX Vref Scan: 0
6910 12:11:54.326920
6911 12:11:54.329496 RX Vref 0 -> 0, step: 1
6912 12:11:54.329607
6913 12:11:54.329706 RX Delay -410 -> 252, step: 16
6914 12:11:54.336604 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6915 12:11:54.339891 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6916 12:11:54.343253 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6917 12:11:54.349798 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6918 12:11:54.353121 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6919 12:11:54.356202 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6920 12:11:54.359408 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6921 12:11:54.366333 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6922 12:11:54.369539 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6923 12:11:54.372896 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6924 12:11:54.376131 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6925 12:11:54.382455 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6926 12:11:54.386291 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6927 12:11:54.388919 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6928 12:11:54.392831 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6929 12:11:54.399077 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6930 12:11:54.399196 ==
6931 12:11:54.402304 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 12:11:54.405606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 12:11:54.405716 ==
6934 12:11:54.408799 DQS Delay:
6935 12:11:54.408913 DQS0 = 43, DQS1 = 51
6936 12:11:54.409011 DQM Delay:
6937 12:11:54.412092 DQM0 = 12, DQM1 = 15
6938 12:11:54.412202 DQ Delay:
6939 12:11:54.415275 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6940 12:11:54.419156 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6941 12:11:54.422471 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6942 12:11:54.425775 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6943 12:11:54.425889
6944 12:11:54.425986
6945 12:11:54.426075 ==
6946 12:11:54.429083 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 12:11:54.431794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 12:11:54.431906 ==
6949 12:11:54.435022
6950 12:11:54.435131
6951 12:11:54.435228 TX Vref Scan disable
6952 12:11:54.438887 == TX Byte 0 ==
6953 12:11:54.442048 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6954 12:11:54.445257 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6955 12:11:54.448426 == TX Byte 1 ==
6956 12:11:54.451602 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6957 12:11:54.454885 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6958 12:11:54.455035 ==
6959 12:11:54.458612 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 12:11:54.461801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 12:11:54.465037 ==
6962 12:11:54.465135
6963 12:11:54.465205
6964 12:11:54.465269 TX Vref Scan disable
6965 12:11:54.468156 == TX Byte 0 ==
6966 12:11:54.471288 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6967 12:11:54.475276 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6968 12:11:54.477979 == TX Byte 1 ==
6969 12:11:54.481802 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6970 12:11:54.485083 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6971 12:11:54.485173
6972 12:11:54.488157 [DATLAT]
6973 12:11:54.488239 Freq=400, CH1 RK1
6974 12:11:54.488304
6975 12:11:54.491382 DATLAT Default: 0xe
6976 12:11:54.491459 0, 0xFFFF, sum = 0
6977 12:11:54.494499 1, 0xFFFF, sum = 0
6978 12:11:54.494580 2, 0xFFFF, sum = 0
6979 12:11:54.497665 3, 0xFFFF, sum = 0
6980 12:11:54.497768 4, 0xFFFF, sum = 0
6981 12:11:54.501383 5, 0xFFFF, sum = 0
6982 12:11:54.501495 6, 0xFFFF, sum = 0
6983 12:11:54.504775 7, 0xFFFF, sum = 0
6984 12:11:54.504941 8, 0xFFFF, sum = 0
6985 12:11:54.508128 9, 0xFFFF, sum = 0
6986 12:11:54.508252 10, 0xFFFF, sum = 0
6987 12:11:54.511357 11, 0xFFFF, sum = 0
6988 12:11:54.514567 12, 0xFFFF, sum = 0
6989 12:11:54.514688 13, 0x0, sum = 1
6990 12:11:54.514797 14, 0x0, sum = 2
6991 12:11:54.517783 15, 0x0, sum = 3
6992 12:11:54.517904 16, 0x0, sum = 4
6993 12:11:54.521103 best_step = 14
6994 12:11:54.521212
6995 12:11:54.521304 ==
6996 12:11:54.524237 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 12:11:54.527648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 12:11:54.527734 ==
6999 12:11:54.530921 RX Vref Scan: 0
7000 12:11:54.531031
7001 12:11:54.531139 RX Vref 0 -> 0, step: 1
7002 12:11:54.531245
7003 12:11:54.534282 RX Delay -343 -> 252, step: 8
7004 12:11:54.542376 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7005 12:11:54.545684 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7006 12:11:54.548898 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7007 12:11:54.555626 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7008 12:11:54.558799 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7009 12:11:54.562035 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7010 12:11:54.565793 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7011 12:11:54.572181 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7012 12:11:54.575281 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7013 12:11:54.578899 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7014 12:11:54.582080 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7015 12:11:54.588472 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
7016 12:11:54.591649 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7017 12:11:54.594937 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7018 12:11:54.601823 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7019 12:11:54.604911 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7020 12:11:54.605028 ==
7021 12:11:54.608565 Dram Type= 6, Freq= 0, CH_1, rank 1
7022 12:11:54.611863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7023 12:11:54.611991 ==
7024 12:11:54.615153 DQS Delay:
7025 12:11:54.615276 DQS0 = 44, DQS1 = 56
7026 12:11:54.615379 DQM Delay:
7027 12:11:54.618455 DQM0 = 8, DQM1 = 11
7028 12:11:54.618560 DQ Delay:
7029 12:11:54.621589 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7030 12:11:54.624829 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7031 12:11:54.628154 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7032 12:11:54.631338 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
7033 12:11:54.631448
7034 12:11:54.631555
7035 12:11:54.641089 [DQSOSCAuto] RK1, (LSB)MR18= 0x6958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7036 12:11:54.641201 CH1 RK1: MR19=C0C, MR18=6958
7037 12:11:54.647535 CH1_RK1: MR19=0xC0C, MR18=0x6958, DQSOSC=396, MR23=63, INC=376, DEC=251
7038 12:11:54.651303 [RxdqsGatingPostProcess] freq 400
7039 12:11:54.657712 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7040 12:11:54.661070 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 12:11:54.664340 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 12:11:54.667548 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 12:11:54.670849 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 12:11:54.673850 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 12:11:54.677588 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 12:11:54.677734 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 12:11:54.680810 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 12:11:54.684050 Pre-setting of DQS Precalculation
7049 12:11:54.690475 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7050 12:11:54.697292 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7051 12:11:54.704056 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7052 12:11:54.704180
7053 12:11:54.704315
7054 12:11:54.707274 [Calibration Summary] 800 Mbps
7055 12:11:54.710507 CH 0, Rank 0
7056 12:11:54.710625 SW Impedance : PASS
7057 12:11:54.714152 DUTY Scan : NO K
7058 12:11:54.716796 ZQ Calibration : PASS
7059 12:11:54.716932 Jitter Meter : NO K
7060 12:11:54.720691 CBT Training : PASS
7061 12:11:54.720811 Write leveling : PASS
7062 12:11:54.723942 RX DQS gating : PASS
7063 12:11:54.726965 RX DQ/DQS(RDDQC) : PASS
7064 12:11:54.727079 TX DQ/DQS : PASS
7065 12:11:54.730157 RX DATLAT : PASS
7066 12:11:54.733415 RX DQ/DQS(Engine): PASS
7067 12:11:54.733537 TX OE : NO K
7068 12:11:54.736702 All Pass.
7069 12:11:54.736808
7070 12:11:54.736875 CH 0, Rank 1
7071 12:11:54.739981 SW Impedance : PASS
7072 12:11:54.740100 DUTY Scan : NO K
7073 12:11:54.743154 ZQ Calibration : PASS
7074 12:11:54.746872 Jitter Meter : NO K
7075 12:11:54.746989 CBT Training : PASS
7076 12:11:54.750121 Write leveling : NO K
7077 12:11:54.753743 RX DQS gating : PASS
7078 12:11:54.753874 RX DQ/DQS(RDDQC) : PASS
7079 12:11:54.756829 TX DQ/DQS : PASS
7080 12:11:54.760196 RX DATLAT : PASS
7081 12:11:54.760319 RX DQ/DQS(Engine): PASS
7082 12:11:54.763435 TX OE : NO K
7083 12:11:54.763514 All Pass.
7084 12:11:54.763630
7085 12:11:54.766652 CH 1, Rank 0
7086 12:11:54.766760 SW Impedance : PASS
7087 12:11:54.769790 DUTY Scan : NO K
7088 12:11:54.773083 ZQ Calibration : PASS
7089 12:11:54.773201 Jitter Meter : NO K
7090 12:11:54.776160 CBT Training : PASS
7091 12:11:54.779857 Write leveling : PASS
7092 12:11:54.779994 RX DQS gating : PASS
7093 12:11:54.782940 RX DQ/DQS(RDDQC) : PASS
7094 12:11:54.786033 TX DQ/DQS : PASS
7095 12:11:54.786161 RX DATLAT : PASS
7096 12:11:54.789242 RX DQ/DQS(Engine): PASS
7097 12:11:54.792439 TX OE : NO K
7098 12:11:54.792591 All Pass.
7099 12:11:54.792699
7100 12:11:54.792814 CH 1, Rank 1
7101 12:11:54.796231 SW Impedance : PASS
7102 12:11:54.799273 DUTY Scan : NO K
7103 12:11:54.799387 ZQ Calibration : PASS
7104 12:11:54.802389 Jitter Meter : NO K
7105 12:11:54.805807 CBT Training : PASS
7106 12:11:54.805938 Write leveling : NO K
7107 12:11:54.809129 RX DQS gating : PASS
7108 12:11:54.812340 RX DQ/DQS(RDDQC) : PASS
7109 12:11:54.812448 TX DQ/DQS : PASS
7110 12:11:54.816130 RX DATLAT : PASS
7111 12:11:54.816248 RX DQ/DQS(Engine): PASS
7112 12:11:54.819369 TX OE : NO K
7113 12:11:54.819476 All Pass.
7114 12:11:54.819571
7115 12:11:54.822670 DramC Write-DBI off
7116 12:11:54.825913 PER_BANK_REFRESH: Hybrid Mode
7117 12:11:54.826022 TX_TRACKING: ON
7118 12:11:54.835580 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7119 12:11:54.838889 [FAST_K] Save calibration result to emmc
7120 12:11:54.842160 dramc_set_vcore_voltage set vcore to 725000
7121 12:11:54.845392 Read voltage for 1600, 0
7122 12:11:54.845480 Vio18 = 0
7123 12:11:54.848651 Vcore = 725000
7124 12:11:54.848802 Vdram = 0
7125 12:11:54.848908 Vddq = 0
7126 12:11:54.849022 Vmddr = 0
7127 12:11:54.855257 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7128 12:11:54.861888 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7129 12:11:54.862048 MEM_TYPE=3, freq_sel=13
7130 12:11:54.865161 sv_algorithm_assistance_LP4_3733
7131 12:11:54.868460 ============ PULL DRAM RESETB DOWN ============
7132 12:11:54.874997 ========== PULL DRAM RESETB DOWN end =========
7133 12:11:54.878168 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7134 12:11:54.881888 ===================================
7135 12:11:54.885052 LPDDR4 DRAM CONFIGURATION
7136 12:11:54.888122 ===================================
7137 12:11:54.888230 EX_ROW_EN[0] = 0x0
7138 12:11:54.891905 EX_ROW_EN[1] = 0x0
7139 12:11:54.895275 LP4Y_EN = 0x0
7140 12:11:54.895391 WORK_FSP = 0x1
7141 12:11:54.897918 WL = 0x5
7142 12:11:54.898035 RL = 0x5
7143 12:11:54.901748 BL = 0x2
7144 12:11:54.901834 RPST = 0x0
7145 12:11:54.904858 RD_PRE = 0x0
7146 12:11:54.904939 WR_PRE = 0x1
7147 12:11:54.908071 WR_PST = 0x1
7148 12:11:54.908141 DBI_WR = 0x0
7149 12:11:54.911403 DBI_RD = 0x0
7150 12:11:54.911494 OTF = 0x1
7151 12:11:54.914565 ===================================
7152 12:11:54.917916 ===================================
7153 12:11:54.921442 ANA top config
7154 12:11:54.924672 ===================================
7155 12:11:54.924796 DLL_ASYNC_EN = 0
7156 12:11:54.928030 ALL_SLAVE_EN = 0
7157 12:11:54.931155 NEW_RANK_MODE = 1
7158 12:11:54.934222 DLL_IDLE_MODE = 1
7159 12:11:54.938099 LP45_APHY_COMB_EN = 1
7160 12:11:54.938213 TX_ODT_DIS = 0
7161 12:11:54.941414 NEW_8X_MODE = 1
7162 12:11:54.944713 ===================================
7163 12:11:54.947429 ===================================
7164 12:11:54.951380 data_rate = 3200
7165 12:11:54.954556 CKR = 1
7166 12:11:54.957744 DQ_P2S_RATIO = 8
7167 12:11:54.960996 ===================================
7168 12:11:54.964283 CA_P2S_RATIO = 8
7169 12:11:54.964399 DQ_CA_OPEN = 0
7170 12:11:54.967553 DQ_SEMI_OPEN = 0
7171 12:11:54.970831 CA_SEMI_OPEN = 0
7172 12:11:54.974111 CA_FULL_RATE = 0
7173 12:11:54.977353 DQ_CKDIV4_EN = 0
7174 12:11:54.980719 CA_CKDIV4_EN = 0
7175 12:11:54.980832 CA_PREDIV_EN = 0
7176 12:11:54.984549 PH8_DLY = 12
7177 12:11:54.987770 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7178 12:11:54.990885 DQ_AAMCK_DIV = 4
7179 12:11:54.994043 CA_AAMCK_DIV = 4
7180 12:11:54.997297 CA_ADMCK_DIV = 4
7181 12:11:54.997385 DQ_TRACK_CA_EN = 0
7182 12:11:55.001034 CA_PICK = 1600
7183 12:11:55.004295 CA_MCKIO = 1600
7184 12:11:55.007452 MCKIO_SEMI = 0
7185 12:11:55.010698 PLL_FREQ = 3068
7186 12:11:55.013990 DQ_UI_PI_RATIO = 32
7187 12:11:55.017242 CA_UI_PI_RATIO = 0
7188 12:11:55.020420 ===================================
7189 12:11:55.024257 ===================================
7190 12:11:55.024370 memory_type:LPDDR4
7191 12:11:55.027374 GP_NUM : 10
7192 12:11:55.030617 SRAM_EN : 1
7193 12:11:55.030724 MD32_EN : 0
7194 12:11:55.033975 ===================================
7195 12:11:55.037298 [ANA_INIT] >>>>>>>>>>>>>>
7196 12:11:55.040634 <<<<<< [CONFIGURE PHASE]: ANA_TX
7197 12:11:55.043887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7198 12:11:55.047131 ===================================
7199 12:11:55.050289 data_rate = 3200,PCW = 0X7600
7200 12:11:55.053564 ===================================
7201 12:11:55.056881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7202 12:11:55.060003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 12:11:55.066569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 12:11:55.069887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7205 12:11:55.073096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7206 12:11:55.077084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7207 12:11:55.080256 [ANA_INIT] flow start
7208 12:11:55.083603 [ANA_INIT] PLL >>>>>>>>
7209 12:11:55.083713 [ANA_INIT] PLL <<<<<<<<
7210 12:11:55.086883 [ANA_INIT] MIDPI >>>>>>>>
7211 12:11:55.090092 [ANA_INIT] MIDPI <<<<<<<<
7212 12:11:55.093403 [ANA_INIT] DLL >>>>>>>>
7213 12:11:55.093516 [ANA_INIT] DLL <<<<<<<<
7214 12:11:55.096425 [ANA_INIT] flow end
7215 12:11:55.099553 ============ LP4 DIFF to SE enter ============
7216 12:11:55.103406 ============ LP4 DIFF to SE exit ============
7217 12:11:55.106216 [ANA_INIT] <<<<<<<<<<<<<
7218 12:11:55.109954 [Flow] Enable top DCM control >>>>>
7219 12:11:55.113084 [Flow] Enable top DCM control <<<<<
7220 12:11:55.116245 Enable DLL master slave shuffle
7221 12:11:55.122950 ==============================================================
7222 12:11:55.123053 Gating Mode config
7223 12:11:55.129339 ==============================================================
7224 12:11:55.129429 Config description:
7225 12:11:55.139062 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7226 12:11:55.146167 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7227 12:11:55.152788 SELPH_MODE 0: By rank 1: By Phase
7228 12:11:55.159218 ==============================================================
7229 12:11:55.159339 GAT_TRACK_EN = 1
7230 12:11:55.162401 RX_GATING_MODE = 2
7231 12:11:55.165623 RX_GATING_TRACK_MODE = 2
7232 12:11:55.168908 SELPH_MODE = 1
7233 12:11:55.172188 PICG_EARLY_EN = 1
7234 12:11:55.175381 VALID_LAT_VALUE = 1
7235 12:11:55.181862 ==============================================================
7236 12:11:55.185197 Enter into Gating configuration >>>>
7237 12:11:55.188422 Exit from Gating configuration <<<<
7238 12:11:55.192293 Enter into DVFS_PRE_config >>>>>
7239 12:11:55.201607 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7240 12:11:55.204926 Exit from DVFS_PRE_config <<<<<
7241 12:11:55.208152 Enter into PICG configuration >>>>
7242 12:11:55.211959 Exit from PICG configuration <<<<
7243 12:11:55.215228 [RX_INPUT] configuration >>>>>
7244 12:11:55.218416 [RX_INPUT] configuration <<<<<
7245 12:11:55.221576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7246 12:11:55.228161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7247 12:11:55.235082 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 12:11:55.241504 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 12:11:55.244765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7250 12:11:55.251080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7251 12:11:55.254950 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7252 12:11:55.260891 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7253 12:11:55.264594 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7254 12:11:55.267839 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7255 12:11:55.270997 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7256 12:11:55.277565 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7257 12:11:55.281366 ===================================
7258 12:11:55.284070 LPDDR4 DRAM CONFIGURATION
7259 12:11:55.288074 ===================================
7260 12:11:55.288214 EX_ROW_EN[0] = 0x0
7261 12:11:55.290652 EX_ROW_EN[1] = 0x0
7262 12:11:55.290783 LP4Y_EN = 0x0
7263 12:11:55.293990 WORK_FSP = 0x1
7264 12:11:55.294109 WL = 0x5
7265 12:11:55.297784 RL = 0x5
7266 12:11:55.297900 BL = 0x2
7267 12:11:55.300898 RPST = 0x0
7268 12:11:55.301012 RD_PRE = 0x0
7269 12:11:55.303978 WR_PRE = 0x1
7270 12:11:55.304084 WR_PST = 0x1
7271 12:11:55.307294 DBI_WR = 0x0
7272 12:11:55.307411 DBI_RD = 0x0
7273 12:11:55.310533 OTF = 0x1
7274 12:11:55.313723 ===================================
7275 12:11:55.317632 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7276 12:11:55.320320 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7277 12:11:55.327444 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7278 12:11:55.330605 ===================================
7279 12:11:55.333829 LPDDR4 DRAM CONFIGURATION
7280 12:11:55.333966 ===================================
7281 12:11:55.336988 EX_ROW_EN[0] = 0x10
7282 12:11:55.340199 EX_ROW_EN[1] = 0x0
7283 12:11:55.340309 LP4Y_EN = 0x0
7284 12:11:55.344080 WORK_FSP = 0x1
7285 12:11:55.344217 WL = 0x5
7286 12:11:55.347286 RL = 0x5
7287 12:11:55.347424 BL = 0x2
7288 12:11:55.350568 RPST = 0x0
7289 12:11:55.350700 RD_PRE = 0x0
7290 12:11:55.353627 WR_PRE = 0x1
7291 12:11:55.353741 WR_PST = 0x1
7292 12:11:55.356860 DBI_WR = 0x0
7293 12:11:55.356992 DBI_RD = 0x0
7294 12:11:55.360142 OTF = 0x1
7295 12:11:55.363993 ===================================
7296 12:11:55.370492 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7297 12:11:55.370625 ==
7298 12:11:55.373822 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 12:11:55.377142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 12:11:55.377236 ==
7301 12:11:55.380392 [Duty_Offset_Calibration]
7302 12:11:55.380507 B0:1 B1:-1 CA:0
7303 12:11:55.380619
7304 12:11:55.383636 [DutyScan_Calibration_Flow] k_type=0
7305 12:11:55.394784
7306 12:11:55.394921 ==CLK 0==
7307 12:11:55.398009 Final CLK duty delay cell = 0
7308 12:11:55.401298 [0] MAX Duty = 5125%(X100), DQS PI = 20
7309 12:11:55.404252 [0] MIN Duty = 4907%(X100), DQS PI = 6
7310 12:11:55.404362 [0] AVG Duty = 5016%(X100)
7311 12:11:55.408140
7312 12:11:55.411190 CH0 CLK Duty spec in!! Max-Min= 218%
7313 12:11:55.414449 [DutyScan_Calibration_Flow] ====Done====
7314 12:11:55.414557
7315 12:11:55.417494 [DutyScan_Calibration_Flow] k_type=1
7316 12:11:55.433565
7317 12:11:55.433714 ==DQS 0 ==
7318 12:11:55.436918 Final DQS duty delay cell = -4
7319 12:11:55.440649 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7320 12:11:55.444003 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7321 12:11:55.447198 [-4] AVG Duty = 4922%(X100)
7322 12:11:55.447313
7323 12:11:55.447408 ==DQS 1 ==
7324 12:11:55.450040 Final DQS duty delay cell = 0
7325 12:11:55.453274 [0] MAX Duty = 5187%(X100), DQS PI = 4
7326 12:11:55.457045 [0] MIN Duty = 5031%(X100), DQS PI = 20
7327 12:11:55.460190 [0] AVG Duty = 5109%(X100)
7328 12:11:55.460314
7329 12:11:55.463388 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7330 12:11:55.463530
7331 12:11:55.466635 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7332 12:11:55.469834 [DutyScan_Calibration_Flow] ====Done====
7333 12:11:55.469953
7334 12:11:55.473100 [DutyScan_Calibration_Flow] k_type=3
7335 12:11:55.491162
7336 12:11:55.491323 ==DQM 0 ==
7337 12:11:55.494290 Final DQM duty delay cell = 0
7338 12:11:55.497675 [0] MAX Duty = 5124%(X100), DQS PI = 24
7339 12:11:55.501083 [0] MIN Duty = 4907%(X100), DQS PI = 8
7340 12:11:55.504705 [0] AVG Duty = 5015%(X100)
7341 12:11:55.504825
7342 12:11:55.504920 ==DQM 1 ==
7343 12:11:55.507823 Final DQM duty delay cell = 0
7344 12:11:55.511027 [0] MAX Duty = 5000%(X100), DQS PI = 4
7345 12:11:55.514095 [0] MIN Duty = 4813%(X100), DQS PI = 18
7346 12:11:55.518035 [0] AVG Duty = 4906%(X100)
7347 12:11:55.518151
7348 12:11:55.521278 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7349 12:11:55.521381
7350 12:11:55.524719 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7351 12:11:55.527893 [DutyScan_Calibration_Flow] ====Done====
7352 12:11:55.528001
7353 12:11:55.530946 [DutyScan_Calibration_Flow] k_type=2
7354 12:11:55.547479
7355 12:11:55.547614 ==DQ 0 ==
7356 12:11:55.550658 Final DQ duty delay cell = -4
7357 12:11:55.553913 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7358 12:11:55.557132 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7359 12:11:55.561109 [-4] AVG Duty = 4953%(X100)
7360 12:11:55.561193
7361 12:11:55.561270 ==DQ 1 ==
7362 12:11:55.564373 Final DQ duty delay cell = 0
7363 12:11:55.567625 [0] MAX Duty = 5125%(X100), DQS PI = 48
7364 12:11:55.570744 [0] MIN Duty = 5000%(X100), DQS PI = 36
7365 12:11:55.574126 [0] AVG Duty = 5062%(X100)
7366 12:11:55.574241
7367 12:11:55.577317 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7368 12:11:55.577428
7369 12:11:55.580550 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7370 12:11:55.583897 [DutyScan_Calibration_Flow] ====Done====
7371 12:11:55.583980 ==
7372 12:11:55.587082 Dram Type= 6, Freq= 0, CH_1, rank 0
7373 12:11:55.590374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7374 12:11:55.590518 ==
7375 12:11:55.593478 [Duty_Offset_Calibration]
7376 12:11:55.593615 B0:-1 B1:1 CA:2
7377 12:11:55.593713
7378 12:11:55.596966 [DutyScan_Calibration_Flow] k_type=0
7379 12:11:55.608111
7380 12:11:55.608245 ==CLK 0==
7381 12:11:55.611826 Final CLK duty delay cell = 0
7382 12:11:55.614881 [0] MAX Duty = 5187%(X100), DQS PI = 24
7383 12:11:55.618043 [0] MIN Duty = 5000%(X100), DQS PI = 0
7384 12:11:55.621226 [0] AVG Duty = 5093%(X100)
7385 12:11:55.621317
7386 12:11:55.624395 CH1 CLK Duty spec in!! Max-Min= 187%
7387 12:11:55.628264 [DutyScan_Calibration_Flow] ====Done====
7388 12:11:55.628371
7389 12:11:55.631389 [DutyScan_Calibration_Flow] k_type=1
7390 12:11:55.647693
7391 12:11:55.647797 ==DQS 0 ==
7392 12:11:55.650981 Final DQS duty delay cell = 0
7393 12:11:55.654190 [0] MAX Duty = 5124%(X100), DQS PI = 18
7394 12:11:55.657384 [0] MIN Duty = 4907%(X100), DQS PI = 10
7395 12:11:55.661195 [0] AVG Duty = 5015%(X100)
7396 12:11:55.661326
7397 12:11:55.661421 ==DQS 1 ==
7398 12:11:55.664410 Final DQS duty delay cell = 0
7399 12:11:55.667616 [0] MAX Duty = 5093%(X100), DQS PI = 24
7400 12:11:55.670786 [0] MIN Duty = 4969%(X100), DQS PI = 54
7401 12:11:55.674410 [0] AVG Duty = 5031%(X100)
7402 12:11:55.674526
7403 12:11:55.677734 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7404 12:11:55.677820
7405 12:11:55.680934 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7406 12:11:55.684184 [DutyScan_Calibration_Flow] ====Done====
7407 12:11:55.684323
7408 12:11:55.687486 [DutyScan_Calibration_Flow] k_type=3
7409 12:11:55.703714
7410 12:11:55.703818 ==DQM 0 ==
7411 12:11:55.707535 Final DQM duty delay cell = -4
7412 12:11:55.710842 [-4] MAX Duty = 5031%(X100), DQS PI = 34
7413 12:11:55.714029 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7414 12:11:55.717216 [-4] AVG Duty = 4906%(X100)
7415 12:11:55.717352
7416 12:11:55.717460 ==DQM 1 ==
7417 12:11:55.720341 Final DQM duty delay cell = 0
7418 12:11:55.723616 [0] MAX Duty = 5156%(X100), DQS PI = 2
7419 12:11:55.726872 [0] MIN Duty = 5000%(X100), DQS PI = 28
7420 12:11:55.730250 [0] AVG Duty = 5078%(X100)
7421 12:11:55.730389
7422 12:11:55.733446 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7423 12:11:55.733578
7424 12:11:55.737223 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7425 12:11:55.740438 [DutyScan_Calibration_Flow] ====Done====
7426 12:11:55.740552
7427 12:11:55.743600 [DutyScan_Calibration_Flow] k_type=2
7428 12:11:55.761103
7429 12:11:55.761272 ==DQ 0 ==
7430 12:11:55.764322 Final DQ duty delay cell = 0
7431 12:11:55.767493 [0] MAX Duty = 5156%(X100), DQS PI = 28
7432 12:11:55.771361 [0] MIN Duty = 4906%(X100), DQS PI = 10
7433 12:11:55.771487 [0] AVG Duty = 5031%(X100)
7434 12:11:55.774593
7435 12:11:55.774714 ==DQ 1 ==
7436 12:11:55.777833 Final DQ duty delay cell = 0
7437 12:11:55.781121 [0] MAX Duty = 5156%(X100), DQS PI = 10
7438 12:11:55.784293 [0] MIN Duty = 4969%(X100), DQS PI = 56
7439 12:11:55.784407 [0] AVG Duty = 5062%(X100)
7440 12:11:55.787551
7441 12:11:55.790850 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7442 12:11:55.790957
7443 12:11:55.794127 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7444 12:11:55.797335 [DutyScan_Calibration_Flow] ====Done====
7445 12:11:55.800566 nWR fixed to 30
7446 12:11:55.800653 [ModeRegInit_LP4] CH0 RK0
7447 12:11:55.803826 [ModeRegInit_LP4] CH0 RK1
7448 12:11:55.807533 [ModeRegInit_LP4] CH1 RK0
7449 12:11:55.810946 [ModeRegInit_LP4] CH1 RK1
7450 12:11:55.811061 match AC timing 5
7451 12:11:55.817320 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7452 12:11:55.820455 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7453 12:11:55.823629 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7454 12:11:55.830604 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7455 12:11:55.833894 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7456 12:11:55.834025 [MiockJmeterHQA]
7457 12:11:55.834125
7458 12:11:55.837023 [DramcMiockJmeter] u1RxGatingPI = 0
7459 12:11:55.840246 0 : 4258, 4029
7460 12:11:55.840371 4 : 4255, 4029
7461 12:11:55.843470 8 : 4257, 4027
7462 12:11:55.843588 12 : 4257, 4029
7463 12:11:55.846782 16 : 4257, 4029
7464 12:11:55.846908 20 : 4253, 4027
7465 12:11:55.847007 24 : 4255, 4029
7466 12:11:55.849986 28 : 4363, 4138
7467 12:11:55.850073 32 : 4253, 4027
7468 12:11:55.853186 36 : 4252, 4027
7469 12:11:55.853279 40 : 4253, 4027
7470 12:11:55.856505 44 : 4255, 4029
7471 12:11:55.856611 48 : 4253, 4027
7472 12:11:55.860191 52 : 4363, 4137
7473 12:11:55.860312 56 : 4363, 4138
7474 12:11:55.860432 60 : 4251, 4027
7475 12:11:55.863298 64 : 4252, 4026
7476 12:11:55.863424 68 : 4253, 4026
7477 12:11:55.866578 72 : 4250, 4027
7478 12:11:55.866694 76 : 4255, 4029
7479 12:11:55.870370 80 : 4361, 4137
7480 12:11:55.870462 84 : 4250, 4026
7481 12:11:55.873035 88 : 4250, 4026
7482 12:11:55.873115 92 : 4250, 729
7483 12:11:55.873199 96 : 4363, 0
7484 12:11:55.876331 100 : 4361, 0
7485 12:11:55.876449 104 : 4252, 0
7486 12:11:55.876609 108 : 4250, 0
7487 12:11:55.879623 112 : 4253, 0
7488 12:11:55.879739 116 : 4361, 0
7489 12:11:55.882823 120 : 4360, 0
7490 12:11:55.882942 124 : 4250, 0
7491 12:11:55.883056 128 : 4250, 0
7492 12:11:55.886756 132 : 4360, 0
7493 12:11:55.886868 136 : 4250, 0
7494 12:11:55.890067 140 : 4252, 0
7495 12:11:55.890182 144 : 4250, 0
7496 12:11:55.890287 148 : 4361, 0
7497 12:11:55.893303 152 : 4361, 0
7498 12:11:55.893421 156 : 4250, 0
7499 12:11:55.896570 160 : 4250, 0
7500 12:11:55.896657 164 : 4250, 0
7501 12:11:55.896750 168 : 4361, 0
7502 12:11:55.899944 172 : 4360, 0
7503 12:11:55.900054 176 : 4363, 0
7504 12:11:55.903222 180 : 4250, 0
7505 12:11:55.903305 184 : 4250, 0
7506 12:11:55.903374 188 : 4250, 0
7507 12:11:55.906361 192 : 4250, 0
7508 12:11:55.906456 196 : 4250, 0
7509 12:11:55.909543 200 : 4250, 0
7510 12:11:55.909622 204 : 4253, 0
7511 12:11:55.909698 208 : 4250, 0
7512 12:11:55.912664 212 : 4250, 0
7513 12:11:55.912743 216 : 4253, 0
7514 12:11:55.912810 220 : 4361, 0
7515 12:11:55.915807 224 : 4360, 55
7516 12:11:55.915891 228 : 4250, 2875
7517 12:11:55.919532 232 : 4361, 4138
7518 12:11:55.919622 236 : 4363, 4140
7519 12:11:55.922640 240 : 4250, 4027
7520 12:11:55.922728 244 : 4250, 4027
7521 12:11:55.925690 248 : 4363, 4140
7522 12:11:55.925785 252 : 4250, 4027
7523 12:11:55.929385 256 : 4250, 4027
7524 12:11:55.929467 260 : 4250, 4026
7525 12:11:55.932435 264 : 4253, 4029
7526 12:11:55.932558 268 : 4250, 4027
7527 12:11:55.935673 272 : 4250, 4027
7528 12:11:55.935753 276 : 4361, 4137
7529 12:11:55.935819 280 : 4250, 4026
7530 12:11:55.939296 284 : 4250, 4027
7531 12:11:55.939413 288 : 4361, 4138
7532 12:11:55.942423 292 : 4250, 4027
7533 12:11:55.942555 296 : 4250, 4026
7534 12:11:55.945497 300 : 4363, 4139
7535 12:11:55.945592 304 : 4250, 4027
7536 12:11:55.949222 308 : 4249, 4027
7537 12:11:55.949336 312 : 4250, 4026
7538 12:11:55.952366 316 : 4253, 4029
7539 12:11:55.952448 320 : 4250, 4027
7540 12:11:55.955547 324 : 4250, 4027
7541 12:11:55.955632 328 : 4361, 4137
7542 12:11:55.958819 332 : 4250, 4026
7543 12:11:55.958906 336 : 4250, 3823
7544 12:11:55.962062 340 : 4360, 1961
7545 12:11:55.962200
7546 12:11:55.962305 MIOCK jitter meter ch=0
7547 12:11:55.962396
7548 12:11:55.965755 1T = (340-92) = 248 dly cells
7549 12:11:55.972013 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7550 12:11:55.972109 ==
7551 12:11:55.975744 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 12:11:55.978987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 12:11:55.979093 ==
7554 12:11:55.985526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 12:11:55.988833 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 12:11:55.991987 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 12:11:55.998434 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 12:11:56.008237 [CA 0] Center 43 (13~74) winsize 62
7559 12:11:56.011282 [CA 1] Center 43 (13~74) winsize 62
7560 12:11:56.014558 [CA 2] Center 39 (10~69) winsize 60
7561 12:11:56.017854 [CA 3] Center 39 (9~69) winsize 61
7562 12:11:56.021229 [CA 4] Center 37 (8~66) winsize 59
7563 12:11:56.025067 [CA 5] Center 36 (7~66) winsize 60
7564 12:11:56.025168
7565 12:11:56.028167 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7566 12:11:56.028283
7567 12:11:56.034841 [CATrainingPosCal] consider 1 rank data
7568 12:11:56.034957 u2DelayCellTimex100 = 262/100 ps
7569 12:11:56.041179 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7570 12:11:56.044487 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7571 12:11:56.047472 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7572 12:11:56.051299 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7573 12:11:56.054485 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7574 12:11:56.057575 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7575 12:11:56.057694
7576 12:11:56.061272 CA PerBit enable=1, Macro0, CA PI delay=36
7577 12:11:56.061380
7578 12:11:56.064587 [CBTSetCACLKResult] CA Dly = 36
7579 12:11:56.067833 CS Dly: 12 (0~43)
7580 12:11:56.070996 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 12:11:56.073958 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 12:11:56.074065 ==
7583 12:11:56.077140 Dram Type= 6, Freq= 0, CH_0, rank 1
7584 12:11:56.084116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 12:11:56.084228 ==
7586 12:11:56.087387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7587 12:11:56.093847 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7588 12:11:56.097014 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7589 12:11:56.103540 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7590 12:11:56.111881 [CA 0] Center 43 (13~74) winsize 62
7591 12:11:56.115104 [CA 1] Center 44 (14~74) winsize 61
7592 12:11:56.118312 [CA 2] Center 38 (9~68) winsize 60
7593 12:11:56.121532 [CA 3] Center 38 (9~68) winsize 60
7594 12:11:56.125304 [CA 4] Center 36 (7~66) winsize 60
7595 12:11:56.128528 [CA 5] Center 36 (6~66) winsize 61
7596 12:11:56.128614
7597 12:11:56.131783 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7598 12:11:56.131895
7599 12:11:56.137843 [CATrainingPosCal] consider 2 rank data
7600 12:11:56.137927 u2DelayCellTimex100 = 262/100 ps
7601 12:11:56.144669 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 12:11:56.147928 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7603 12:11:56.151251 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7604 12:11:56.154462 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7605 12:11:56.158129 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7606 12:11:56.161436 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7607 12:11:56.161520
7608 12:11:56.164425 CA PerBit enable=1, Macro0, CA PI delay=36
7609 12:11:56.164545
7610 12:11:56.167664 [CBTSetCACLKResult] CA Dly = 36
7611 12:11:56.170858 CS Dly: 12 (0~44)
7612 12:11:56.174594 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7613 12:11:56.177651 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7614 12:11:56.177736
7615 12:11:56.180774 ----->DramcWriteLeveling(PI) begin...
7616 12:11:56.183928 ==
7617 12:11:56.187792 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 12:11:56.191009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 12:11:56.191115 ==
7620 12:11:56.194216 Write leveling (Byte 0): 37 => 37
7621 12:11:56.197364 Write leveling (Byte 1): 26 => 26
7622 12:11:56.200482 DramcWriteLeveling(PI) end<-----
7623 12:11:56.200584
7624 12:11:56.200649 ==
7625 12:11:56.203813 Dram Type= 6, Freq= 0, CH_0, rank 0
7626 12:11:56.207047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7627 12:11:56.207132 ==
7628 12:11:56.210334 [Gating] SW mode calibration
7629 12:11:56.216938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7630 12:11:56.223368 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7631 12:11:56.226609 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:11:56.230478 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 12:11:56.236923 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 12:11:56.240078 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7635 12:11:56.243355 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7636 12:11:56.249722 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7637 12:11:56.252960 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7638 12:11:56.256655 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 12:11:56.262950 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 12:11:56.266713 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 12:11:56.269907 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 12:11:56.276511 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7643 12:11:56.279756 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7644 12:11:56.282912 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7645 12:11:56.289740 1 5 24 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
7646 12:11:56.292677 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 12:11:56.296021 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 12:11:56.303139 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 12:11:56.306404 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 12:11:56.309576 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (1 1)
7651 12:11:56.316145 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7652 12:11:56.319402 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7653 12:11:56.322565 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7654 12:11:56.329281 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 12:11:56.332521 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 12:11:56.335818 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 12:11:56.342601 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 12:11:56.345891 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7659 12:11:56.349086 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7660 12:11:56.355422 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7661 12:11:56.359185 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7662 12:11:56.362487 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 12:11:56.368899 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 12:11:56.372101 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 12:11:56.375403 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 12:11:56.381886 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 12:11:56.385025 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 12:11:56.388885 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:11:56.395418 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:11:56.398743 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:11:56.401917 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:11:56.408238 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:11:56.411449 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7674 12:11:56.414747 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7675 12:11:56.421236 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7676 12:11:56.421347 Total UI for P1: 0, mck2ui 16
7677 12:11:56.427826 best dqsien dly found for B0: ( 1, 9, 10)
7678 12:11:56.431585 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7679 12:11:56.434731 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 12:11:56.437963 Total UI for P1: 0, mck2ui 16
7681 12:11:56.441659 best dqsien dly found for B1: ( 1, 9, 20)
7682 12:11:56.444669 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7683 12:11:56.447917 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7684 12:11:56.448023
7685 12:11:56.451124 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7686 12:11:56.458090 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7687 12:11:56.458172 [Gating] SW calibration Done
7688 12:11:56.461424 ==
7689 12:11:56.461547 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 12:11:56.467592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 12:11:56.467695 ==
7692 12:11:56.467767 RX Vref Scan: 0
7693 12:11:56.467831
7694 12:11:56.471556 RX Vref 0 -> 0, step: 1
7695 12:11:56.471642
7696 12:11:56.474668 RX Delay 0 -> 252, step: 8
7697 12:11:56.477946 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7698 12:11:56.481322 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7699 12:11:56.484526 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7700 12:11:56.491040 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7701 12:11:56.494054 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7702 12:11:56.497902 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
7703 12:11:56.501162 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7704 12:11:56.504421 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7705 12:11:56.510990 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7706 12:11:56.514274 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7707 12:11:56.517509 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7708 12:11:56.520692 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7709 12:11:56.527372 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7710 12:11:56.530415 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7711 12:11:56.534287 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7712 12:11:56.537535 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7713 12:11:56.537653 ==
7714 12:11:56.540781 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 12:11:56.547142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 12:11:56.547259 ==
7717 12:11:56.547357 DQS Delay:
7718 12:11:56.547449 DQS0 = 0, DQS1 = 0
7719 12:11:56.550582 DQM Delay:
7720 12:11:56.550686 DQM0 = 135, DQM1 = 127
7721 12:11:56.553726 DQ Delay:
7722 12:11:56.556867 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7723 12:11:56.559990 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7724 12:11:56.563897 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7725 12:11:56.567007 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7726 12:11:56.567123
7727 12:11:56.567230
7728 12:11:56.567327 ==
7729 12:11:56.570162 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 12:11:56.573373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 12:11:56.576454 ==
7732 12:11:56.576574
7733 12:11:56.576664
7734 12:11:56.576727 TX Vref Scan disable
7735 12:11:56.580255 == TX Byte 0 ==
7736 12:11:56.583370 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7737 12:11:56.586525 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7738 12:11:56.589810 == TX Byte 1 ==
7739 12:11:56.593049 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7740 12:11:56.600071 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7741 12:11:56.600190 ==
7742 12:11:56.603304 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 12:11:56.606576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 12:11:56.606707 ==
7745 12:11:56.619768
7746 12:11:56.623060 TX Vref early break, caculate TX vref
7747 12:11:56.626362 TX Vref=16, minBit 4, minWin=22, winSum=368
7748 12:11:56.629561 TX Vref=18, minBit 1, minWin=23, winSum=379
7749 12:11:56.632809 TX Vref=20, minBit 1, minWin=24, winSum=389
7750 12:11:56.635962 TX Vref=22, minBit 3, minWin=24, winSum=398
7751 12:11:56.639282 TX Vref=24, minBit 0, minWin=25, winSum=407
7752 12:11:56.645814 TX Vref=26, minBit 0, minWin=24, winSum=413
7753 12:11:56.649641 TX Vref=28, minBit 0, minWin=25, winSum=415
7754 12:11:56.652426 TX Vref=30, minBit 0, minWin=24, winSum=403
7755 12:11:56.655824 TX Vref=32, minBit 0, minWin=24, winSum=398
7756 12:11:56.658977 TX Vref=34, minBit 5, minWin=23, winSum=389
7757 12:11:56.665740 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
7758 12:11:56.665840
7759 12:11:56.669007 Final TX Range 0 Vref 28
7760 12:11:56.669090
7761 12:11:56.669156 ==
7762 12:11:56.672279 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 12:11:56.675453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 12:11:56.675562 ==
7765 12:11:56.675633
7766 12:11:56.675693
7767 12:11:56.679145 TX Vref Scan disable
7768 12:11:56.685476 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7769 12:11:56.685601 == TX Byte 0 ==
7770 12:11:56.688600 u2DelayCellOfst[0]=14 cells (4 PI)
7771 12:11:56.692434 u2DelayCellOfst[1]=18 cells (5 PI)
7772 12:11:56.695857 u2DelayCellOfst[2]=14 cells (4 PI)
7773 12:11:56.698891 u2DelayCellOfst[3]=14 cells (4 PI)
7774 12:11:56.701991 u2DelayCellOfst[4]=11 cells (3 PI)
7775 12:11:56.705160 u2DelayCellOfst[5]=0 cells (0 PI)
7776 12:11:56.708504 u2DelayCellOfst[6]=22 cells (6 PI)
7777 12:11:56.711769 u2DelayCellOfst[7]=22 cells (6 PI)
7778 12:11:56.715042 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7779 12:11:56.718769 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7780 12:11:56.721965 == TX Byte 1 ==
7781 12:11:56.725175 u2DelayCellOfst[8]=0 cells (0 PI)
7782 12:11:56.728388 u2DelayCellOfst[9]=3 cells (1 PI)
7783 12:11:56.731474 u2DelayCellOfst[10]=7 cells (2 PI)
7784 12:11:56.735260 u2DelayCellOfst[11]=3 cells (1 PI)
7785 12:11:56.738441 u2DelayCellOfst[12]=14 cells (4 PI)
7786 12:11:56.738547 u2DelayCellOfst[13]=14 cells (4 PI)
7787 12:11:56.741660 u2DelayCellOfst[14]=14 cells (4 PI)
7788 12:11:56.744894 u2DelayCellOfst[15]=11 cells (3 PI)
7789 12:11:56.751416 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7790 12:11:56.754545 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7791 12:11:56.758235 DramC Write-DBI on
7792 12:11:56.758361 ==
7793 12:11:56.761411 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 12:11:56.764523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 12:11:56.764642 ==
7796 12:11:56.764751
7797 12:11:56.764856
7798 12:11:56.768216 TX Vref Scan disable
7799 12:11:56.768340 == TX Byte 0 ==
7800 12:11:56.774636 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7801 12:11:56.774743 == TX Byte 1 ==
7802 12:11:56.777771 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7803 12:11:56.781018 DramC Write-DBI off
7804 12:11:56.781107
7805 12:11:56.781174 [DATLAT]
7806 12:11:56.784264 Freq=1600, CH0 RK0
7807 12:11:56.784369
7808 12:11:56.784464 DATLAT Default: 0xf
7809 12:11:56.787909 0, 0xFFFF, sum = 0
7810 12:11:56.788009 1, 0xFFFF, sum = 0
7811 12:11:56.791093 2, 0xFFFF, sum = 0
7812 12:11:56.794226 3, 0xFFFF, sum = 0
7813 12:11:56.794333 4, 0xFFFF, sum = 0
7814 12:11:56.797539 5, 0xFFFF, sum = 0
7815 12:11:56.797653 6, 0xFFFF, sum = 0
7816 12:11:56.801332 7, 0xFFFF, sum = 0
7817 12:11:56.801444 8, 0xFFFF, sum = 0
7818 12:11:56.804491 9, 0xFFFF, sum = 0
7819 12:11:56.804619 10, 0xFFFF, sum = 0
7820 12:11:56.807632 11, 0xFFFF, sum = 0
7821 12:11:56.807744 12, 0xFFFF, sum = 0
7822 12:11:56.810897 13, 0xFFFF, sum = 0
7823 12:11:56.811000 14, 0x0, sum = 1
7824 12:11:56.814273 15, 0x0, sum = 2
7825 12:11:56.814388 16, 0x0, sum = 3
7826 12:11:56.817607 17, 0x0, sum = 4
7827 12:11:56.817733 best_step = 15
7828 12:11:56.817834
7829 12:11:56.817943 ==
7830 12:11:56.820877 Dram Type= 6, Freq= 0, CH_0, rank 0
7831 12:11:56.827308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7832 12:11:56.827399 ==
7833 12:11:56.827466 RX Vref Scan: 1
7834 12:11:56.827528
7835 12:11:56.830568 Set Vref Range= 24 -> 127
7836 12:11:56.830652
7837 12:11:56.833964 RX Vref 24 -> 127, step: 1
7838 12:11:56.834047
7839 12:11:56.834113 RX Delay 19 -> 252, step: 4
7840 12:11:56.834175
7841 12:11:56.837047 Set Vref, RX VrefLevel [Byte0]: 24
7842 12:11:56.840512 [Byte1]: 24
7843 12:11:56.844478
7844 12:11:56.844585 Set Vref, RX VrefLevel [Byte0]: 25
7845 12:11:56.847787 [Byte1]: 25
7846 12:11:56.852349
7847 12:11:56.852468 Set Vref, RX VrefLevel [Byte0]: 26
7848 12:11:56.855460 [Byte1]: 26
7849 12:11:56.859877
7850 12:11:56.859982 Set Vref, RX VrefLevel [Byte0]: 27
7851 12:11:56.863113 [Byte1]: 27
7852 12:11:56.867422
7853 12:11:56.867542 Set Vref, RX VrefLevel [Byte0]: 28
7854 12:11:56.870538 [Byte1]: 28
7855 12:11:56.874947
7856 12:11:56.875032 Set Vref, RX VrefLevel [Byte0]: 29
7857 12:11:56.878175 [Byte1]: 29
7858 12:11:56.882563
7859 12:11:56.882646 Set Vref, RX VrefLevel [Byte0]: 30
7860 12:11:56.885627 [Byte1]: 30
7861 12:11:56.890238
7862 12:11:56.890323 Set Vref, RX VrefLevel [Byte0]: 31
7863 12:11:56.893189 [Byte1]: 31
7864 12:11:56.897596
7865 12:11:56.897683 Set Vref, RX VrefLevel [Byte0]: 32
7866 12:11:56.900824 [Byte1]: 32
7867 12:11:56.905273
7868 12:11:56.905359 Set Vref, RX VrefLevel [Byte0]: 33
7869 12:11:56.908460 [Byte1]: 33
7870 12:11:56.912786
7871 12:11:56.912873 Set Vref, RX VrefLevel [Byte0]: 34
7872 12:11:56.915946 [Byte1]: 34
7873 12:11:56.920577
7874 12:11:56.920691 Set Vref, RX VrefLevel [Byte0]: 35
7875 12:11:56.923244 [Byte1]: 35
7876 12:11:56.927819
7877 12:11:56.927930 Set Vref, RX VrefLevel [Byte0]: 36
7878 12:11:56.931147 [Byte1]: 36
7879 12:11:56.934991
7880 12:11:56.938332 Set Vref, RX VrefLevel [Byte0]: 37
7881 12:11:56.942159 [Byte1]: 37
7882 12:11:56.942262
7883 12:11:56.944815 Set Vref, RX VrefLevel [Byte0]: 38
7884 12:11:56.948601 [Byte1]: 38
7885 12:11:56.948682
7886 12:11:56.951813 Set Vref, RX VrefLevel [Byte0]: 39
7887 12:11:56.955076 [Byte1]: 39
7888 12:11:56.955183
7889 12:11:56.958376 Set Vref, RX VrefLevel [Byte0]: 40
7890 12:11:56.961581 [Byte1]: 40
7891 12:11:56.965411
7892 12:11:56.965528 Set Vref, RX VrefLevel [Byte0]: 41
7893 12:11:56.969312 [Byte1]: 41
7894 12:11:56.973528
7895 12:11:56.973642 Set Vref, RX VrefLevel [Byte0]: 42
7896 12:11:56.976590 [Byte1]: 42
7897 12:11:56.981191
7898 12:11:56.981294 Set Vref, RX VrefLevel [Byte0]: 43
7899 12:11:56.983837 [Byte1]: 43
7900 12:11:56.988299
7901 12:11:56.988404 Set Vref, RX VrefLevel [Byte0]: 44
7902 12:11:56.991480 [Byte1]: 44
7903 12:11:56.995853
7904 12:11:56.995943 Set Vref, RX VrefLevel [Byte0]: 45
7905 12:11:56.999563 [Byte1]: 45
7906 12:11:57.003389
7907 12:11:57.003492 Set Vref, RX VrefLevel [Byte0]: 46
7908 12:11:57.007013 [Byte1]: 46
7909 12:11:57.010931
7910 12:11:57.011036 Set Vref, RX VrefLevel [Byte0]: 47
7911 12:11:57.014112 [Byte1]: 47
7912 12:11:57.018673
7913 12:11:57.018779 Set Vref, RX VrefLevel [Byte0]: 48
7914 12:11:57.021864 [Byte1]: 48
7915 12:11:57.026341
7916 12:11:57.026451 Set Vref, RX VrefLevel [Byte0]: 49
7917 12:11:57.029593 [Byte1]: 49
7918 12:11:57.033963
7919 12:11:57.034074 Set Vref, RX VrefLevel [Byte0]: 50
7920 12:11:57.037219 [Byte1]: 50
7921 12:11:57.041153
7922 12:11:57.041266 Set Vref, RX VrefLevel [Byte0]: 51
7923 12:11:57.045000 [Byte1]: 51
7924 12:11:57.048902
7925 12:11:57.049007 Set Vref, RX VrefLevel [Byte0]: 52
7926 12:11:57.052104 [Byte1]: 52
7927 12:11:57.056640
7928 12:11:57.056720 Set Vref, RX VrefLevel [Byte0]: 53
7929 12:11:57.059847 [Byte1]: 53
7930 12:11:57.064368
7931 12:11:57.064473 Set Vref, RX VrefLevel [Byte0]: 54
7932 12:11:57.070656 [Byte1]: 54
7933 12:11:57.070769
7934 12:11:57.073792 Set Vref, RX VrefLevel [Byte0]: 55
7935 12:11:57.077443 [Byte1]: 55
7936 12:11:57.077564
7937 12:11:57.080488 Set Vref, RX VrefLevel [Byte0]: 56
7938 12:11:57.083875 [Byte1]: 56
7939 12:11:57.083981
7940 12:11:57.087171 Set Vref, RX VrefLevel [Byte0]: 57
7941 12:11:57.090277 [Byte1]: 57
7942 12:11:57.094113
7943 12:11:57.094235 Set Vref, RX VrefLevel [Byte0]: 58
7944 12:11:57.097880 [Byte1]: 58
7945 12:11:57.102340
7946 12:11:57.102447 Set Vref, RX VrefLevel [Byte0]: 59
7947 12:11:57.105581 [Byte1]: 59
7948 12:11:57.109880
7949 12:11:57.109990 Set Vref, RX VrefLevel [Byte0]: 60
7950 12:11:57.113093 [Byte1]: 60
7951 12:11:57.116884
7952 12:11:57.116966 Set Vref, RX VrefLevel [Byte0]: 61
7953 12:11:57.120726 [Byte1]: 61
7954 12:11:57.124533
7955 12:11:57.124610 Set Vref, RX VrefLevel [Byte0]: 62
7956 12:11:57.127835 [Byte1]: 62
7957 12:11:57.132327
7958 12:11:57.132437 Set Vref, RX VrefLevel [Byte0]: 63
7959 12:11:57.135459 [Byte1]: 63
7960 12:11:57.139909
7961 12:11:57.139992 Set Vref, RX VrefLevel [Byte0]: 64
7962 12:11:57.143281 [Byte1]: 64
7963 12:11:57.147803
7964 12:11:57.147890 Set Vref, RX VrefLevel [Byte0]: 65
7965 12:11:57.150952 [Byte1]: 65
7966 12:11:57.154956
7967 12:11:57.155079 Set Vref, RX VrefLevel [Byte0]: 66
7968 12:11:57.158116 [Byte1]: 66
7969 12:11:57.162796
7970 12:11:57.162939 Set Vref, RX VrefLevel [Byte0]: 67
7971 12:11:57.166018 [Byte1]: 67
7972 12:11:57.169951
7973 12:11:57.170039 Set Vref, RX VrefLevel [Byte0]: 68
7974 12:11:57.173784 [Byte1]: 68
7975 12:11:57.177508
7976 12:11:57.177587 Set Vref, RX VrefLevel [Byte0]: 69
7977 12:11:57.181192 [Byte1]: 69
7978 12:11:57.185461
7979 12:11:57.185554 Set Vref, RX VrefLevel [Byte0]: 70
7980 12:11:57.188573 [Byte1]: 70
7981 12:11:57.193131
7982 12:11:57.193244 Set Vref, RX VrefLevel [Byte0]: 71
7983 12:11:57.196280 [Byte1]: 71
7984 12:11:57.200594
7985 12:11:57.200716 Set Vref, RX VrefLevel [Byte0]: 72
7986 12:11:57.203852 [Byte1]: 72
7987 12:11:57.208220
7988 12:11:57.208337 Set Vref, RX VrefLevel [Byte0]: 73
7989 12:11:57.211399 [Byte1]: 73
7990 12:11:57.215315
7991 12:11:57.215452 Set Vref, RX VrefLevel [Byte0]: 74
7992 12:11:57.219095 [Byte1]: 74
7993 12:11:57.222934
7994 12:11:57.223056 Set Vref, RX VrefLevel [Byte0]: 75
7995 12:11:57.226644 [Byte1]: 75
7996 12:11:57.230516
7997 12:11:57.230637 Set Vref, RX VrefLevel [Byte0]: 76
7998 12:11:57.233743 [Byte1]: 76
7999 12:11:57.238299
8000 12:11:57.238435 Set Vref, RX VrefLevel [Byte0]: 77
8001 12:11:57.241435 [Byte1]: 77
8002 12:11:57.245907
8003 12:11:57.246042 Set Vref, RX VrefLevel [Byte0]: 78
8004 12:11:57.249196 [Byte1]: 78
8005 12:11:57.253686
8006 12:11:57.253813 Final RX Vref Byte 0 = 66 to rank0
8007 12:11:57.257021 Final RX Vref Byte 1 = 61 to rank0
8008 12:11:57.260289 Final RX Vref Byte 0 = 66 to rank1
8009 12:11:57.263527 Final RX Vref Byte 1 = 61 to rank1==
8010 12:11:57.266834 Dram Type= 6, Freq= 0, CH_0, rank 0
8011 12:11:57.273402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 12:11:57.273540 ==
8013 12:11:57.273640 DQS Delay:
8014 12:11:57.273740 DQS0 = 0, DQS1 = 0
8015 12:11:57.276843 DQM Delay:
8016 12:11:57.276939 DQM0 = 133, DQM1 = 123
8017 12:11:57.279915 DQ Delay:
8018 12:11:57.283554 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8019 12:11:57.286713 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =140
8020 12:11:57.289818 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8021 12:11:57.293123 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8022 12:11:57.293235
8023 12:11:57.293329
8024 12:11:57.293419
8025 12:11:57.296301 [DramC_TX_OE_Calibration] TA2
8026 12:11:57.299654 Original DQ_B0 (3 6) =30, OEN = 27
8027 12:11:57.303257 Original DQ_B1 (3 6) =30, OEN = 27
8028 12:11:57.306562 24, 0x0, End_B0=24 End_B1=24
8029 12:11:57.306690 25, 0x0, End_B0=25 End_B1=25
8030 12:11:57.309763 26, 0x0, End_B0=26 End_B1=26
8031 12:11:57.312847 27, 0x0, End_B0=27 End_B1=27
8032 12:11:57.316678 28, 0x0, End_B0=28 End_B1=28
8033 12:11:57.319951 29, 0x0, End_B0=29 End_B1=29
8034 12:11:57.320066 30, 0x0, End_B0=30 End_B1=30
8035 12:11:57.323175 31, 0x5151, End_B0=30 End_B1=30
8036 12:11:57.326399 Byte0 end_step=30 best_step=27
8037 12:11:57.329569 Byte1 end_step=30 best_step=27
8038 12:11:57.332740 Byte0 TX OE(2T, 0.5T) = (3, 3)
8039 12:11:57.336019 Byte1 TX OE(2T, 0.5T) = (3, 3)
8040 12:11:57.336139
8041 12:11:57.336252
8042 12:11:57.343262 [DQSOSCAuto] RK0, (LSB)MR18= 0x2314, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8043 12:11:57.346526 CH0 RK0: MR19=303, MR18=2314
8044 12:11:57.352998 CH0_RK0: MR19=0x303, MR18=0x2314, DQSOSC=392, MR23=63, INC=24, DEC=16
8045 12:11:57.353120
8046 12:11:57.356238 ----->DramcWriteLeveling(PI) begin...
8047 12:11:57.356351 ==
8048 12:11:57.359526 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 12:11:57.362917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 12:11:57.363061 ==
8051 12:11:57.366069 Write leveling (Byte 0): 36 => 36
8052 12:11:57.369246 Write leveling (Byte 1): 27 => 27
8053 12:11:57.372621 DramcWriteLeveling(PI) end<-----
8054 12:11:57.372729
8055 12:11:57.372799 ==
8056 12:11:57.375847 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 12:11:57.379098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 12:11:57.379210 ==
8059 12:11:57.382888 [Gating] SW mode calibration
8060 12:11:57.389252 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8061 12:11:57.395554 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8062 12:11:57.398874 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 12:11:57.405405 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 12:11:57.409203 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 12:11:57.412270 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 12:11:57.418769 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8067 12:11:57.421865 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (1 1) (1 1)
8068 12:11:57.425773 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 12:11:57.432237 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 12:11:57.435340 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 12:11:57.438522 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 12:11:57.444993 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 12:11:57.448115 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8074 12:11:57.451405 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8075 12:11:57.458498 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8076 12:11:57.461814 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8077 12:11:57.465090 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 12:11:57.471494 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 12:11:57.474549 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 12:11:57.477815 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 12:11:57.484844 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8082 12:11:57.488073 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8083 12:11:57.491882 1 6 20 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
8084 12:11:57.498127 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 12:11:57.501309 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 12:11:57.504487 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 12:11:57.511029 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 12:11:57.514693 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 12:11:57.518013 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8090 12:11:57.524190 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 12:11:57.527910 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8092 12:11:57.531095 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 12:11:57.537638 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:11:57.540919 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:11:57.544208 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:11:57.550596 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:11:57.553863 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:11:57.557098 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:11:57.564282 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:11:57.567551 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:11:57.570920 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:11:57.577361 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:11:57.580728 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 12:11:57.583958 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8105 12:11:57.590460 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8106 12:11:57.593550 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8107 12:11:57.597317 Total UI for P1: 0, mck2ui 16
8108 12:11:57.600571 best dqsien dly found for B0: ( 1, 9, 10)
8109 12:11:57.603766 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 12:11:57.606922 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8111 12:11:57.610171 Total UI for P1: 0, mck2ui 16
8112 12:11:57.613452 best dqsien dly found for B1: ( 1, 9, 18)
8113 12:11:57.620414 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8114 12:11:57.623584 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8115 12:11:57.623718
8116 12:11:57.626776 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8117 12:11:57.629948 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8118 12:11:57.633248 [Gating] SW calibration Done
8119 12:11:57.633375 ==
8120 12:11:57.636556 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 12:11:57.639799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 12:11:57.639908 ==
8123 12:11:57.643106 RX Vref Scan: 0
8124 12:11:57.643251
8125 12:11:57.643370 RX Vref 0 -> 0, step: 1
8126 12:11:57.643462
8127 12:11:57.646223 RX Delay 0 -> 252, step: 8
8128 12:11:57.649564 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8129 12:11:57.656101 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8130 12:11:57.659904 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8131 12:11:57.663234 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8132 12:11:57.666495 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8133 12:11:57.669749 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8134 12:11:57.676152 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8135 12:11:57.679339 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8136 12:11:57.682493 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8137 12:11:57.685778 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8138 12:11:57.688995 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8139 12:11:57.696023 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8140 12:11:57.699164 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8141 12:11:57.702394 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8142 12:11:57.705636 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8143 12:11:57.712631 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8144 12:11:57.712730 ==
8145 12:11:57.715322 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 12:11:57.719225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 12:11:57.719342 ==
8148 12:11:57.719449 DQS Delay:
8149 12:11:57.722427 DQS0 = 0, DQS1 = 0
8150 12:11:57.722540 DQM Delay:
8151 12:11:57.725702 DQM0 = 133, DQM1 = 128
8152 12:11:57.725815 DQ Delay:
8153 12:11:57.728953 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8154 12:11:57.732116 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8155 12:11:57.735342 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8156 12:11:57.738495 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8157 12:11:57.742326
8158 12:11:57.742437
8159 12:11:57.742543 ==
8160 12:11:57.745464 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 12:11:57.748706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 12:11:57.748794 ==
8163 12:11:57.748861
8164 12:11:57.748938
8165 12:11:57.751964 TX Vref Scan disable
8166 12:11:57.752072 == TX Byte 0 ==
8167 12:11:57.758433 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8168 12:11:57.761719 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8169 12:11:57.761859 == TX Byte 1 ==
8170 12:11:57.768097 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8171 12:11:57.771269 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8172 12:11:57.771390 ==
8173 12:11:57.775190 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 12:11:57.777967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 12:11:57.778097 ==
8176 12:11:57.791689
8177 12:11:57.794868 TX Vref early break, caculate TX vref
8178 12:11:57.798065 TX Vref=16, minBit 1, minWin=22, winSum=373
8179 12:11:57.801767 TX Vref=18, minBit 0, minWin=23, winSum=388
8180 12:11:57.805005 TX Vref=20, minBit 0, minWin=23, winSum=389
8181 12:11:57.808149 TX Vref=22, minBit 0, minWin=24, winSum=398
8182 12:11:57.811327 TX Vref=24, minBit 1, minWin=24, winSum=405
8183 12:11:57.817817 TX Vref=26, minBit 0, minWin=25, winSum=415
8184 12:11:57.821704 TX Vref=28, minBit 0, minWin=24, winSum=410
8185 12:11:57.824930 TX Vref=30, minBit 1, minWin=24, winSum=404
8186 12:11:57.828021 TX Vref=32, minBit 3, minWin=23, winSum=392
8187 12:11:57.834527 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
8188 12:11:57.834679
8189 12:11:57.837749 Final TX Range 0 Vref 26
8190 12:11:57.837882
8191 12:11:57.837994 ==
8192 12:11:57.840928 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 12:11:57.844163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 12:11:57.844273 ==
8195 12:11:57.844380
8196 12:11:57.844488
8197 12:11:57.847903 TX Vref Scan disable
8198 12:11:57.854300 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8199 12:11:57.854440 == TX Byte 0 ==
8200 12:11:57.857527 u2DelayCellOfst[0]=11 cells (3 PI)
8201 12:11:57.860781 u2DelayCellOfst[1]=14 cells (4 PI)
8202 12:11:57.863917 u2DelayCellOfst[2]=11 cells (3 PI)
8203 12:11:57.867613 u2DelayCellOfst[3]=11 cells (3 PI)
8204 12:11:57.870759 u2DelayCellOfst[4]=7 cells (2 PI)
8205 12:11:57.873924 u2DelayCellOfst[5]=0 cells (0 PI)
8206 12:11:57.877196 u2DelayCellOfst[6]=14 cells (4 PI)
8207 12:11:57.880406 u2DelayCellOfst[7]=14 cells (4 PI)
8208 12:11:57.884171 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8209 12:11:57.887243 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8210 12:11:57.890573 == TX Byte 1 ==
8211 12:11:57.890682 u2DelayCellOfst[8]=0 cells (0 PI)
8212 12:11:57.893874 u2DelayCellOfst[9]=0 cells (0 PI)
8213 12:11:57.897101 u2DelayCellOfst[10]=7 cells (2 PI)
8214 12:11:57.900242 u2DelayCellOfst[11]=0 cells (0 PI)
8215 12:11:57.903511 u2DelayCellOfst[12]=11 cells (3 PI)
8216 12:11:57.906739 u2DelayCellOfst[13]=11 cells (3 PI)
8217 12:11:57.909989 u2DelayCellOfst[14]=18 cells (5 PI)
8218 12:11:57.913644 u2DelayCellOfst[15]=11 cells (3 PI)
8219 12:11:57.916817 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8220 12:11:57.923607 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8221 12:11:57.923725 DramC Write-DBI on
8222 12:11:57.923822 ==
8223 12:11:57.926760 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 12:11:57.933039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 12:11:57.933148 ==
8226 12:11:57.933246
8227 12:11:57.933336
8228 12:11:57.933432 TX Vref Scan disable
8229 12:11:57.937440 == TX Byte 0 ==
8230 12:11:57.940544 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8231 12:11:57.943697 == TX Byte 1 ==
8232 12:11:57.947489 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8233 12:11:57.950209 DramC Write-DBI off
8234 12:11:57.950318
8235 12:11:57.950413 [DATLAT]
8236 12:11:57.950505 Freq=1600, CH0 RK1
8237 12:11:57.950605
8238 12:11:57.953781 DATLAT Default: 0xf
8239 12:11:57.953881 0, 0xFFFF, sum = 0
8240 12:11:57.956897 1, 0xFFFF, sum = 0
8241 12:11:57.960205 2, 0xFFFF, sum = 0
8242 12:11:57.960324 3, 0xFFFF, sum = 0
8243 12:11:57.963438 4, 0xFFFF, sum = 0
8244 12:11:57.963552 5, 0xFFFF, sum = 0
8245 12:11:57.966788 6, 0xFFFF, sum = 0
8246 12:11:57.966898 7, 0xFFFF, sum = 0
8247 12:11:57.970026 8, 0xFFFF, sum = 0
8248 12:11:57.970152 9, 0xFFFF, sum = 0
8249 12:11:57.973246 10, 0xFFFF, sum = 0
8250 12:11:57.973360 11, 0xFFFF, sum = 0
8251 12:11:57.977012 12, 0xFFFF, sum = 0
8252 12:11:57.977122 13, 0xFFFF, sum = 0
8253 12:11:57.980137 14, 0x0, sum = 1
8254 12:11:57.980268 15, 0x0, sum = 2
8255 12:11:57.983361 16, 0x0, sum = 3
8256 12:11:57.983492 17, 0x0, sum = 4
8257 12:11:57.986558 best_step = 15
8258 12:11:57.986674
8259 12:11:57.986768 ==
8260 12:11:57.989737 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 12:11:57.993499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 12:11:57.993609 ==
8263 12:11:57.996670 RX Vref Scan: 0
8264 12:11:57.996775
8265 12:11:57.996874 RX Vref 0 -> 0, step: 1
8266 12:11:57.996969
8267 12:11:57.999950 RX Delay 11 -> 252, step: 4
8268 12:11:58.006468 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8269 12:11:58.009625 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8270 12:11:58.013501 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8271 12:11:58.016635 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8272 12:11:58.019603 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8273 12:11:58.026457 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8274 12:11:58.029564 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8275 12:11:58.033297 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8276 12:11:58.036568 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8277 12:11:58.039661 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8278 12:11:58.046041 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8279 12:11:58.049605 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8280 12:11:58.052823 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8281 12:11:58.055960 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8282 12:11:58.062798 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8283 12:11:58.066009 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8284 12:11:58.066116 ==
8285 12:11:58.069329 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 12:11:58.072574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 12:11:58.072670 ==
8288 12:11:58.072777 DQS Delay:
8289 12:11:58.075774 DQS0 = 0, DQS1 = 0
8290 12:11:58.075871 DQM Delay:
8291 12:11:58.078965 DQM0 = 130, DQM1 = 125
8292 12:11:58.079072 DQ Delay:
8293 12:11:58.082316 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8294 12:11:58.085541 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8295 12:11:58.089387 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8296 12:11:58.095936 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8297 12:11:58.096064
8298 12:11:58.096182
8299 12:11:58.096285
8300 12:11:58.099026 [DramC_TX_OE_Calibration] TA2
8301 12:11:58.099138 Original DQ_B0 (3 6) =30, OEN = 27
8302 12:11:58.102223 Original DQ_B1 (3 6) =30, OEN = 27
8303 12:11:58.105381 24, 0x0, End_B0=24 End_B1=24
8304 12:11:58.108851 25, 0x0, End_B0=25 End_B1=25
8305 12:11:58.111912 26, 0x0, End_B0=26 End_B1=26
8306 12:11:58.115651 27, 0x0, End_B0=27 End_B1=27
8307 12:11:58.115739 28, 0x0, End_B0=28 End_B1=28
8308 12:11:58.118725 29, 0x0, End_B0=29 End_B1=29
8309 12:11:58.122405 30, 0x0, End_B0=30 End_B1=30
8310 12:11:58.125594 31, 0x4545, End_B0=30 End_B1=30
8311 12:11:58.128771 Byte0 end_step=30 best_step=27
8312 12:11:58.128860 Byte1 end_step=30 best_step=27
8313 12:11:58.131862 Byte0 TX OE(2T, 0.5T) = (3, 3)
8314 12:11:58.135529 Byte1 TX OE(2T, 0.5T) = (3, 3)
8315 12:11:58.135640
8316 12:11:58.135757
8317 12:11:58.145143 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8318 12:11:58.145277 CH0 RK1: MR19=303, MR18=1D00
8319 12:11:58.152021 CH0_RK1: MR19=0x303, MR18=0x1D00, DQSOSC=395, MR23=63, INC=23, DEC=15
8320 12:11:58.155116 [RxdqsGatingPostProcess] freq 1600
8321 12:11:58.162143 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8322 12:11:58.165386 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 12:11:58.168620 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 12:11:58.171891 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 12:11:58.175160 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 12:11:58.178788 best DQS0 dly(2T, 0.5T) = (1, 1)
8327 12:11:58.178899 best DQS1 dly(2T, 0.5T) = (1, 1)
8328 12:11:58.181923 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8329 12:11:58.185114 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8330 12:11:58.188402 Pre-setting of DQS Precalculation
8331 12:11:58.194948 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8332 12:11:58.195062 ==
8333 12:11:58.198124 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 12:11:58.201361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 12:11:58.201461 ==
8336 12:11:58.207826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 12:11:58.211124 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 12:11:58.214279 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 12:11:58.220610 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 12:11:58.230187 [CA 0] Center 41 (12~71) winsize 60
8341 12:11:58.233519 [CA 1] Center 42 (12~72) winsize 61
8342 12:11:58.237270 [CA 2] Center 37 (8~66) winsize 59
8343 12:11:58.240452 [CA 3] Center 36 (7~65) winsize 59
8344 12:11:58.243646 [CA 4] Center 36 (7~66) winsize 60
8345 12:11:58.246895 [CA 5] Center 36 (6~66) winsize 61
8346 12:11:58.247010
8347 12:11:58.250518 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8348 12:11:58.250630
8349 12:11:58.253566 [CATrainingPosCal] consider 1 rank data
8350 12:11:58.256664 u2DelayCellTimex100 = 262/100 ps
8351 12:11:58.259938 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8352 12:11:58.266790 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8353 12:11:58.270058 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8354 12:11:58.273268 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8355 12:11:58.276512 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8356 12:11:58.279856 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8357 12:11:58.279965
8358 12:11:58.282965 CA PerBit enable=1, Macro0, CA PI delay=36
8359 12:11:58.283070
8360 12:11:58.286766 [CBTSetCACLKResult] CA Dly = 36
8361 12:11:58.290023 CS Dly: 9 (0~40)
8362 12:11:58.293257 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 12:11:58.296360 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 12:11:58.296464 ==
8365 12:11:58.299638 Dram Type= 6, Freq= 0, CH_1, rank 1
8366 12:11:58.302811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 12:11:58.306601 ==
8368 12:11:58.309880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8369 12:11:58.313152 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8370 12:11:58.319604 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8371 12:11:58.325940 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8372 12:11:58.333474 [CA 0] Center 42 (13~72) winsize 60
8373 12:11:58.336769 [CA 1] Center 42 (13~72) winsize 60
8374 12:11:58.340390 [CA 2] Center 37 (8~67) winsize 60
8375 12:11:58.343614 [CA 3] Center 37 (8~67) winsize 60
8376 12:11:58.346839 [CA 4] Center 37 (8~67) winsize 60
8377 12:11:58.350059 [CA 5] Center 37 (8~67) winsize 60
8378 12:11:58.350177
8379 12:11:58.353264 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8380 12:11:58.353370
8381 12:11:58.360150 [CATrainingPosCal] consider 2 rank data
8382 12:11:58.360264 u2DelayCellTimex100 = 262/100 ps
8383 12:11:58.366532 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8384 12:11:58.369809 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8385 12:11:58.373413 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8386 12:11:58.376585 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8387 12:11:58.379893 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8388 12:11:58.383184 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8389 12:11:58.383289
8390 12:11:58.386320 CA PerBit enable=1, Macro0, CA PI delay=36
8391 12:11:58.386421
8392 12:11:58.389484 [CBTSetCACLKResult] CA Dly = 36
8393 12:11:58.392750 CS Dly: 10 (0~43)
8394 12:11:58.396469 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8395 12:11:58.399733 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8396 12:11:58.399840
8397 12:11:58.402945 ----->DramcWriteLeveling(PI) begin...
8398 12:11:58.403051 ==
8399 12:11:58.406213 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 12:11:58.413187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 12:11:58.413298 ==
8402 12:11:58.416437 Write leveling (Byte 0): 24 => 24
8403 12:11:58.419528 Write leveling (Byte 1): 26 => 26
8404 12:11:58.419633 DramcWriteLeveling(PI) end<-----
8405 12:11:58.419726
8406 12:11:58.422657 ==
8407 12:11:58.425891 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 12:11:58.429805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 12:11:58.429964 ==
8410 12:11:58.432825 [Gating] SW mode calibration
8411 12:11:58.439769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8412 12:11:58.442367 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8413 12:11:58.449381 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 12:11:58.452524 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 12:11:58.455792 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 12:11:58.462748 1 4 12 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
8417 12:11:58.465785 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 12:11:58.468972 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 12:11:58.475693 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 12:11:58.478888 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 12:11:58.482038 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 12:11:58.489094 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 12:11:58.492218 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8424 12:11:58.495386 1 5 12 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (1 0)
8425 12:11:58.501797 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8426 12:11:58.505653 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 12:11:58.508936 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 12:11:58.515307 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 12:11:58.518504 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 12:11:58.521826 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 12:11:58.528258 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8432 12:11:58.532014 1 6 12 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
8433 12:11:58.535267 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 12:11:58.542024 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 12:11:58.545030 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 12:11:58.548228 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 12:11:58.555119 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 12:11:58.558284 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 12:11:58.561524 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8440 12:11:58.567938 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8441 12:11:58.571629 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8442 12:11:58.574901 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 12:11:58.581061 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:11:58.585015 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:11:58.588243 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:11:58.594651 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:11:58.597779 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:11:58.600994 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:11:58.608111 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:11:58.611326 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 12:11:58.614527 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:11:58.620919 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:11:58.624759 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:11:58.627941 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:11:58.634431 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8456 12:11:58.637755 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8457 12:11:58.640866 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8458 12:11:58.644043 Total UI for P1: 0, mck2ui 16
8459 12:11:58.647737 best dqsien dly found for B0: ( 1, 9, 10)
8460 12:11:58.650863 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 12:11:58.653977 Total UI for P1: 0, mck2ui 16
8462 12:11:58.657803 best dqsien dly found for B1: ( 1, 9, 14)
8463 12:11:58.664175 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8464 12:11:58.667357 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8465 12:11:58.667460
8466 12:11:58.670505 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8467 12:11:58.674193 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8468 12:11:58.677310 [Gating] SW calibration Done
8469 12:11:58.677451 ==
8470 12:11:58.680447 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 12:11:58.684299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 12:11:58.684412 ==
8473 12:11:58.687404 RX Vref Scan: 0
8474 12:11:58.687529
8475 12:11:58.687642 RX Vref 0 -> 0, step: 1
8476 12:11:58.687710
8477 12:11:58.690660 RX Delay 0 -> 252, step: 8
8478 12:11:58.693929 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8479 12:11:58.700222 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8480 12:11:58.704019 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8481 12:11:58.707237 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8482 12:11:58.710543 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8483 12:11:58.713838 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8484 12:11:58.720212 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8485 12:11:58.723404 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8486 12:11:58.726589 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8487 12:11:58.729905 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8488 12:11:58.733118 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8489 12:11:58.740258 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8490 12:11:58.743390 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8491 12:11:58.746422 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8492 12:11:58.750215 iDelay=208, Bit 14, Center 143 (88 ~ 199) 112
8493 12:11:58.756493 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8494 12:11:58.756613 ==
8495 12:11:58.759786 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 12:11:58.763031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 12:11:58.763150 ==
8498 12:11:58.763263 DQS Delay:
8499 12:11:58.766282 DQS0 = 0, DQS1 = 0
8500 12:11:58.766388 DQM Delay:
8501 12:11:58.769561 DQM0 = 138, DQM1 = 131
8502 12:11:58.769670 DQ Delay:
8503 12:11:58.772783 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8504 12:11:58.776441 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8505 12:11:58.779668 DQ8 =119, DQ9 =115, DQ10 =135, DQ11 =123
8506 12:11:58.782744 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =139
8507 12:11:58.782870
8508 12:11:58.782975
8509 12:11:58.786478 ==
8510 12:11:58.789643 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 12:11:58.792905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 12:11:58.793023 ==
8513 12:11:58.793119
8514 12:11:58.793241
8515 12:11:58.796109 TX Vref Scan disable
8516 12:11:58.796219 == TX Byte 0 ==
8517 12:11:58.799300 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8518 12:11:58.806266 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 12:11:58.806382 == TX Byte 1 ==
8520 12:11:58.812630 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8521 12:11:58.815831 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8522 12:11:58.815943 ==
8523 12:11:58.818969 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 12:11:58.822190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 12:11:58.822308 ==
8526 12:11:58.835266
8527 12:11:58.839124 TX Vref early break, caculate TX vref
8528 12:11:58.842274 TX Vref=16, minBit 5, minWin=21, winSum=375
8529 12:11:58.845436 TX Vref=18, minBit 0, minWin=22, winSum=386
8530 12:11:58.848571 TX Vref=20, minBit 0, minWin=24, winSum=396
8531 12:11:58.851843 TX Vref=22, minBit 0, minWin=24, winSum=405
8532 12:11:58.855517 TX Vref=24, minBit 1, minWin=25, winSum=414
8533 12:11:58.861822 TX Vref=26, minBit 1, minWin=25, winSum=418
8534 12:11:58.865069 TX Vref=28, minBit 0, minWin=24, winSum=420
8535 12:11:58.868304 TX Vref=30, minBit 1, minWin=24, winSum=413
8536 12:11:58.871561 TX Vref=32, minBit 1, minWin=24, winSum=407
8537 12:11:58.875366 TX Vref=34, minBit 0, minWin=22, winSum=392
8538 12:11:58.881601 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 26
8539 12:11:58.881744
8540 12:11:58.885286 Final TX Range 0 Vref 26
8541 12:11:58.885400
8542 12:11:58.885497 ==
8543 12:11:58.888494 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 12:11:58.891717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 12:11:58.891809 ==
8546 12:11:58.891881
8547 12:11:58.891946
8548 12:11:58.894863 TX Vref Scan disable
8549 12:11:58.901445 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8550 12:11:58.901548 == TX Byte 0 ==
8551 12:11:58.904796 u2DelayCellOfst[0]=22 cells (6 PI)
8552 12:11:58.907969 u2DelayCellOfst[1]=14 cells (4 PI)
8553 12:11:58.911871 u2DelayCellOfst[2]=0 cells (0 PI)
8554 12:11:58.915065 u2DelayCellOfst[3]=7 cells (2 PI)
8555 12:11:58.918235 u2DelayCellOfst[4]=11 cells (3 PI)
8556 12:11:58.921433 u2DelayCellOfst[5]=22 cells (6 PI)
8557 12:11:58.924568 u2DelayCellOfst[6]=22 cells (6 PI)
8558 12:11:58.928469 u2DelayCellOfst[7]=7 cells (2 PI)
8559 12:11:58.931169 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8560 12:11:58.934922 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8561 12:11:58.938083 == TX Byte 1 ==
8562 12:11:58.941369 u2DelayCellOfst[8]=0 cells (0 PI)
8563 12:11:58.941477 u2DelayCellOfst[9]=3 cells (1 PI)
8564 12:11:58.944535 u2DelayCellOfst[10]=11 cells (3 PI)
8565 12:11:58.947827 u2DelayCellOfst[11]=3 cells (1 PI)
8566 12:11:58.951504 u2DelayCellOfst[12]=14 cells (4 PI)
8567 12:11:58.954639 u2DelayCellOfst[13]=18 cells (5 PI)
8568 12:11:58.957673 u2DelayCellOfst[14]=18 cells (5 PI)
8569 12:11:58.960811 u2DelayCellOfst[15]=18 cells (5 PI)
8570 12:11:58.967722 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8571 12:11:58.970949 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8572 12:11:58.971072 DramC Write-DBI on
8573 12:11:58.971172 ==
8574 12:11:58.974222 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 12:11:58.980649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 12:11:58.980762 ==
8577 12:11:58.980868
8578 12:11:58.980962
8579 12:11:58.981068 TX Vref Scan disable
8580 12:11:58.984974 == TX Byte 0 ==
8581 12:11:58.988246 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8582 12:11:58.991337 == TX Byte 1 ==
8583 12:11:58.994487 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8584 12:11:58.998247 DramC Write-DBI off
8585 12:11:58.998346
8586 12:11:58.998413 [DATLAT]
8587 12:11:58.998484 Freq=1600, CH1 RK0
8588 12:11:58.998552
8589 12:11:59.001516 DATLAT Default: 0xf
8590 12:11:59.001594 0, 0xFFFF, sum = 0
8591 12:11:59.004824 1, 0xFFFF, sum = 0
8592 12:11:59.008005 2, 0xFFFF, sum = 0
8593 12:11:59.008114 3, 0xFFFF, sum = 0
8594 12:11:59.011257 4, 0xFFFF, sum = 0
8595 12:11:59.011379 5, 0xFFFF, sum = 0
8596 12:11:59.014423 6, 0xFFFF, sum = 0
8597 12:11:59.014529 7, 0xFFFF, sum = 0
8598 12:11:59.018277 8, 0xFFFF, sum = 0
8599 12:11:59.018382 9, 0xFFFF, sum = 0
8600 12:11:59.021443 10, 0xFFFF, sum = 0
8601 12:11:59.021561 11, 0xFFFF, sum = 0
8602 12:11:59.024734 12, 0xFFFF, sum = 0
8603 12:11:59.024833 13, 0xFFFF, sum = 0
8604 12:11:59.027942 14, 0x0, sum = 1
8605 12:11:59.028023 15, 0x0, sum = 2
8606 12:11:59.031001 16, 0x0, sum = 3
8607 12:11:59.031109 17, 0x0, sum = 4
8608 12:11:59.034285 best_step = 15
8609 12:11:59.034399
8610 12:11:59.034492 ==
8611 12:11:59.037496 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 12:11:59.040839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 12:11:59.040936 ==
8614 12:11:59.044752 RX Vref Scan: 1
8615 12:11:59.044875
8616 12:11:59.044984 Set Vref Range= 24 -> 127
8617 12:11:59.045077
8618 12:11:59.047919 RX Vref 24 -> 127, step: 1
8619 12:11:59.048037
8620 12:11:59.051177 RX Delay 11 -> 252, step: 4
8621 12:11:59.051303
8622 12:11:59.054443 Set Vref, RX VrefLevel [Byte0]: 24
8623 12:11:59.057646 [Byte1]: 24
8624 12:11:59.057772
8625 12:11:59.060809 Set Vref, RX VrefLevel [Byte0]: 25
8626 12:11:59.063826 [Byte1]: 25
8627 12:11:59.067742
8628 12:11:59.067867 Set Vref, RX VrefLevel [Byte0]: 26
8629 12:11:59.070874 [Byte1]: 26
8630 12:11:59.075332
8631 12:11:59.075456 Set Vref, RX VrefLevel [Byte0]: 27
8632 12:11:59.078524 [Byte1]: 27
8633 12:11:59.082904
8634 12:11:59.083019 Set Vref, RX VrefLevel [Byte0]: 28
8635 12:11:59.086015 [Byte1]: 28
8636 12:11:59.090323
8637 12:11:59.090434 Set Vref, RX VrefLevel [Byte0]: 29
8638 12:11:59.093464 [Byte1]: 29
8639 12:11:59.097974
8640 12:11:59.098059 Set Vref, RX VrefLevel [Byte0]: 30
8641 12:11:59.101071 [Byte1]: 30
8642 12:11:59.105605
8643 12:11:59.105690 Set Vref, RX VrefLevel [Byte0]: 31
8644 12:11:59.108899 [Byte1]: 31
8645 12:11:59.113428
8646 12:11:59.113514 Set Vref, RX VrefLevel [Byte0]: 32
8647 12:11:59.116703 [Byte1]: 32
8648 12:11:59.120593
8649 12:11:59.120672 Set Vref, RX VrefLevel [Byte0]: 33
8650 12:11:59.124371 [Byte1]: 33
8651 12:11:59.128419
8652 12:11:59.128545 Set Vref, RX VrefLevel [Byte0]: 34
8653 12:11:59.131768 [Byte1]: 34
8654 12:11:59.136252
8655 12:11:59.136360 Set Vref, RX VrefLevel [Byte0]: 35
8656 12:11:59.139340 [Byte1]: 35
8657 12:11:59.143865
8658 12:11:59.143984 Set Vref, RX VrefLevel [Byte0]: 36
8659 12:11:59.147171 [Byte1]: 36
8660 12:11:59.151473
8661 12:11:59.151595 Set Vref, RX VrefLevel [Byte0]: 37
8662 12:11:59.154601 [Byte1]: 37
8663 12:11:59.159059
8664 12:11:59.159189 Set Vref, RX VrefLevel [Byte0]: 38
8665 12:11:59.162205 [Byte1]: 38
8666 12:11:59.166521
8667 12:11:59.166632 Set Vref, RX VrefLevel [Byte0]: 39
8668 12:11:59.169664 [Byte1]: 39
8669 12:11:59.174017
8670 12:11:59.174145 Set Vref, RX VrefLevel [Byte0]: 40
8671 12:11:59.177268 [Byte1]: 40
8672 12:11:59.181805
8673 12:11:59.181920 Set Vref, RX VrefLevel [Byte0]: 41
8674 12:11:59.184974 [Byte1]: 41
8675 12:11:59.189277
8676 12:11:59.189366 Set Vref, RX VrefLevel [Byte0]: 42
8677 12:11:59.192448 [Byte1]: 42
8678 12:11:59.196815
8679 12:11:59.196899 Set Vref, RX VrefLevel [Byte0]: 43
8680 12:11:59.200534 [Byte1]: 43
8681 12:11:59.204884
8682 12:11:59.204973 Set Vref, RX VrefLevel [Byte0]: 44
8683 12:11:59.208061 [Byte1]: 44
8684 12:11:59.211939
8685 12:11:59.212019 Set Vref, RX VrefLevel [Byte0]: 45
8686 12:11:59.215821 [Byte1]: 45
8687 12:11:59.219583
8688 12:11:59.219669 Set Vref, RX VrefLevel [Byte0]: 46
8689 12:11:59.223398 [Byte1]: 46
8690 12:11:59.227857
8691 12:11:59.227976 Set Vref, RX VrefLevel [Byte0]: 47
8692 12:11:59.230975 [Byte1]: 47
8693 12:11:59.234854
8694 12:11:59.234987 Set Vref, RX VrefLevel [Byte0]: 48
8695 12:11:59.238587 [Byte1]: 48
8696 12:11:59.243010
8697 12:11:59.243118 Set Vref, RX VrefLevel [Byte0]: 49
8698 12:11:59.245646 [Byte1]: 49
8699 12:11:59.250249
8700 12:11:59.250356 Set Vref, RX VrefLevel [Byte0]: 50
8701 12:11:59.253445 [Byte1]: 50
8702 12:11:59.257905
8703 12:11:59.258022 Set Vref, RX VrefLevel [Byte0]: 51
8704 12:11:59.261154 [Byte1]: 51
8705 12:11:59.265731
8706 12:11:59.265838 Set Vref, RX VrefLevel [Byte0]: 52
8707 12:11:59.268855 [Byte1]: 52
8708 12:11:59.273294
8709 12:11:59.273390 Set Vref, RX VrefLevel [Byte0]: 53
8710 12:11:59.276511 [Byte1]: 53
8711 12:11:59.280813
8712 12:11:59.280933 Set Vref, RX VrefLevel [Byte0]: 54
8713 12:11:59.284110 [Byte1]: 54
8714 12:11:59.288612
8715 12:11:59.288694 Set Vref, RX VrefLevel [Byte0]: 55
8716 12:11:59.291844 [Byte1]: 55
8717 12:11:59.295644
8718 12:11:59.295754 Set Vref, RX VrefLevel [Byte0]: 56
8719 12:11:59.299443 [Byte1]: 56
8720 12:11:59.303898
8721 12:11:59.304004 Set Vref, RX VrefLevel [Byte0]: 57
8722 12:11:59.307033 [Byte1]: 57
8723 12:11:59.311495
8724 12:11:59.311605 Set Vref, RX VrefLevel [Byte0]: 58
8725 12:11:59.314767 [Byte1]: 58
8726 12:11:59.318617
8727 12:11:59.318755 Set Vref, RX VrefLevel [Byte0]: 59
8728 12:11:59.322394 [Byte1]: 59
8729 12:11:59.326333
8730 12:11:59.326416 Set Vref, RX VrefLevel [Byte0]: 60
8731 12:11:59.330040 [Byte1]: 60
8732 12:11:59.333853
8733 12:11:59.333966 Set Vref, RX VrefLevel [Byte0]: 61
8734 12:11:59.337196 [Byte1]: 61
8735 12:11:59.341577
8736 12:11:59.341663 Set Vref, RX VrefLevel [Byte0]: 62
8737 12:11:59.344792 [Byte1]: 62
8738 12:11:59.349292
8739 12:11:59.349406 Set Vref, RX VrefLevel [Byte0]: 63
8740 12:11:59.352522 [Byte1]: 63
8741 12:11:59.357146
8742 12:11:59.357239 Set Vref, RX VrefLevel [Byte0]: 64
8743 12:11:59.360210 [Byte1]: 64
8744 12:11:59.364662
8745 12:11:59.364782 Set Vref, RX VrefLevel [Byte0]: 65
8746 12:11:59.367889 [Byte1]: 65
8747 12:11:59.372364
8748 12:11:59.372487 Set Vref, RX VrefLevel [Byte0]: 66
8749 12:11:59.375517 [Byte1]: 66
8750 12:11:59.379924
8751 12:11:59.380013 Set Vref, RX VrefLevel [Byte0]: 67
8752 12:11:59.383069 [Byte1]: 67
8753 12:11:59.387372
8754 12:11:59.387492 Set Vref, RX VrefLevel [Byte0]: 68
8755 12:11:59.390556 [Byte1]: 68
8756 12:11:59.394950
8757 12:11:59.395039 Set Vref, RX VrefLevel [Byte0]: 69
8758 12:11:59.398144 [Byte1]: 69
8759 12:11:59.402466
8760 12:11:59.402582 Set Vref, RX VrefLevel [Byte0]: 70
8761 12:11:59.405570 [Byte1]: 70
8762 12:11:59.409947
8763 12:11:59.410031 Set Vref, RX VrefLevel [Byte0]: 71
8764 12:11:59.413663 [Byte1]: 71
8765 12:11:59.418146
8766 12:11:59.418229 Final RX Vref Byte 0 = 53 to rank0
8767 12:11:59.421325 Final RX Vref Byte 1 = 57 to rank0
8768 12:11:59.424639 Final RX Vref Byte 0 = 53 to rank1
8769 12:11:59.427798 Final RX Vref Byte 1 = 57 to rank1==
8770 12:11:59.430950 Dram Type= 6, Freq= 0, CH_1, rank 0
8771 12:11:59.437981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 12:11:59.438073 ==
8773 12:11:59.438150 DQS Delay:
8774 12:11:59.438215 DQS0 = 0, DQS1 = 0
8775 12:11:59.441193 DQM Delay:
8776 12:11:59.441274 DQM0 = 134, DQM1 = 129
8777 12:11:59.444391 DQ Delay:
8778 12:11:59.447627 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8779 12:11:59.450889 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8780 12:11:59.453981 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =118
8781 12:11:59.457343 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8782 12:11:59.457455
8783 12:11:59.457549
8784 12:11:59.457640
8785 12:11:59.460280 [DramC_TX_OE_Calibration] TA2
8786 12:11:59.463634 Original DQ_B0 (3 6) =30, OEN = 27
8787 12:11:59.467421 Original DQ_B1 (3 6) =30, OEN = 27
8788 12:11:59.470622 24, 0x0, End_B0=24 End_B1=24
8789 12:11:59.473770 25, 0x0, End_B0=25 End_B1=25
8790 12:11:59.473889 26, 0x0, End_B0=26 End_B1=26
8791 12:11:59.477449 27, 0x0, End_B0=27 End_B1=27
8792 12:11:59.480643 28, 0x0, End_B0=28 End_B1=28
8793 12:11:59.483764 29, 0x0, End_B0=29 End_B1=29
8794 12:11:59.483850 30, 0x0, End_B0=30 End_B1=30
8795 12:11:59.486963 31, 0x4141, End_B0=30 End_B1=30
8796 12:11:59.490192 Byte0 end_step=30 best_step=27
8797 12:11:59.493462 Byte1 end_step=30 best_step=27
8798 12:11:59.496758 Byte0 TX OE(2T, 0.5T) = (3, 3)
8799 12:11:59.500503 Byte1 TX OE(2T, 0.5T) = (3, 3)
8800 12:11:59.500624
8801 12:11:59.500731
8802 12:11:59.506874 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8803 12:11:59.509916 CH1 RK0: MR19=303, MR18=190F
8804 12:11:59.516874 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8805 12:11:59.516991
8806 12:11:59.519960 ----->DramcWriteLeveling(PI) begin...
8807 12:11:59.520077 ==
8808 12:11:59.523132 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 12:11:59.527012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 12:11:59.527119 ==
8811 12:11:59.529646 Write leveling (Byte 0): 24 => 24
8812 12:11:59.533419 Write leveling (Byte 1): 29 => 29
8813 12:11:59.536551 DramcWriteLeveling(PI) end<-----
8814 12:11:59.536661
8815 12:11:59.536732 ==
8816 12:11:59.539808 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 12:11:59.543038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 12:11:59.546208 ==
8819 12:11:59.546289 [Gating] SW mode calibration
8820 12:11:59.556351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8821 12:11:59.559587 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8822 12:11:59.562930 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 12:11:59.569437 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 12:11:59.572683 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
8825 12:11:59.575943 1 4 12 | B1->B0 | 3434 2222 | 0 1 | (0 0) (0 0)
8826 12:11:59.582886 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8827 12:11:59.585984 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 12:11:59.589196 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 12:11:59.596020 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 12:11:59.599295 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:11:59.602561 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:11:59.608972 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8833 12:11:59.612026 1 5 12 | B1->B0 | 2626 3333 | 0 1 | (1 0) (1 0)
8834 12:11:59.615771 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8835 12:11:59.622144 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 12:11:59.625259 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 12:11:59.628541 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 12:11:59.634920 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:11:59.638873 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:11:59.641932 1 6 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8841 12:11:59.648483 1 6 12 | B1->B0 | 4646 2b2b | 0 0 | (0 0) (0 0)
8842 12:11:59.651562 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8843 12:11:59.658115 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 12:11:59.661285 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 12:11:59.665037 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 12:11:59.668262 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:11:59.674717 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:11:59.677945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:11:59.681149 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8850 12:11:59.688288 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8851 12:11:59.691290 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 12:11:59.694507 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 12:11:59.700780 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:11:59.704501 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:11:59.710893 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:11:59.714066 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:11:59.717227 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:11:59.721008 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:11:59.727380 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:11:59.730552 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:11:59.733814 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:11:59.740805 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:11:59.744073 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:11:59.747237 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8865 12:11:59.753830 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8866 12:11:59.756967 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8867 12:11:59.760264 Total UI for P1: 0, mck2ui 16
8868 12:11:59.764049 best dqsien dly found for B1: ( 1, 9, 10)
8869 12:11:59.767156 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 12:11:59.770379 Total UI for P1: 0, mck2ui 16
8871 12:11:59.773660 best dqsien dly found for B0: ( 1, 9, 12)
8872 12:11:59.776850 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8873 12:11:59.780607 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8874 12:11:59.783822
8875 12:11:59.786922 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8876 12:11:59.790022 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8877 12:11:59.793886 [Gating] SW calibration Done
8878 12:11:59.793998 ==
8879 12:11:59.796996 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 12:11:59.800141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 12:11:59.800248 ==
8882 12:11:59.803259 RX Vref Scan: 0
8883 12:11:59.803371
8884 12:11:59.803478 RX Vref 0 -> 0, step: 1
8885 12:11:59.803571
8886 12:11:59.806524 RX Delay 0 -> 252, step: 8
8887 12:11:59.809868 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8888 12:11:59.813134 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8889 12:11:59.820235 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8890 12:11:59.823406 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8891 12:11:59.826743 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8892 12:11:59.829901 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8893 12:11:59.836144 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8894 12:11:59.839914 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8895 12:11:59.843192 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8896 12:11:59.846385 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8897 12:11:59.849564 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8898 12:11:59.855885 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8899 12:11:59.859773 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8900 12:11:59.863063 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8901 12:11:59.866201 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8902 12:11:59.869513 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8903 12:11:59.872592 ==
8904 12:11:59.875801 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 12:11:59.878941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 12:11:59.879072 ==
8907 12:11:59.879182 DQS Delay:
8908 12:11:59.882901 DQS0 = 0, DQS1 = 0
8909 12:11:59.883031 DQM Delay:
8910 12:11:59.886149 DQM0 = 137, DQM1 = 129
8911 12:11:59.886257 DQ Delay:
8912 12:11:59.889327 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8913 12:11:59.892536 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8914 12:11:59.895594 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8915 12:11:59.898860 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8916 12:11:59.898983
8917 12:11:59.899080
8918 12:11:59.902074 ==
8919 12:11:59.905776 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 12:11:59.908972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 12:11:59.909103 ==
8922 12:11:59.909201
8923 12:11:59.909309
8924 12:11:59.912205 TX Vref Scan disable
8925 12:11:59.912332 == TX Byte 0 ==
8926 12:11:59.915478 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8927 12:11:59.921912 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 12:11:59.922038 == TX Byte 1 ==
8929 12:11:59.925686 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8930 12:11:59.931932 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8931 12:11:59.932047 ==
8932 12:11:59.935048 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 12:11:59.938264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 12:11:59.938378 ==
8935 12:11:59.951873
8936 12:11:59.955570 TX Vref early break, caculate TX vref
8937 12:11:59.958821 TX Vref=16, minBit 8, minWin=22, winSum=381
8938 12:11:59.961958 TX Vref=18, minBit 1, minWin=22, winSum=389
8939 12:11:59.965389 TX Vref=20, minBit 1, minWin=23, winSum=396
8940 12:11:59.968564 TX Vref=22, minBit 0, minWin=24, winSum=404
8941 12:11:59.971839 TX Vref=24, minBit 9, minWin=24, winSum=414
8942 12:11:59.978391 TX Vref=26, minBit 0, minWin=25, winSum=416
8943 12:11:59.981473 TX Vref=28, minBit 0, minWin=24, winSum=417
8944 12:11:59.984909 TX Vref=30, minBit 0, minWin=24, winSum=412
8945 12:11:59.988112 TX Vref=32, minBit 5, minWin=23, winSum=402
8946 12:11:59.991378 TX Vref=34, minBit 1, minWin=23, winSum=393
8947 12:11:59.998349 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8948 12:11:59.998437
8949 12:12:00.001503 Final TX Range 0 Vref 26
8950 12:12:00.001582
8951 12:12:00.001663 ==
8952 12:12:00.004596 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 12:12:00.007769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 12:12:00.007868 ==
8955 12:12:00.007954
8956 12:12:00.008019
8957 12:12:00.011633 TX Vref Scan disable
8958 12:12:00.018097 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8959 12:12:00.018178 == TX Byte 0 ==
8960 12:12:00.021323 u2DelayCellOfst[0]=18 cells (5 PI)
8961 12:12:00.024557 u2DelayCellOfst[1]=11 cells (3 PI)
8962 12:12:00.027743 u2DelayCellOfst[2]=0 cells (0 PI)
8963 12:12:00.030841 u2DelayCellOfst[3]=7 cells (2 PI)
8964 12:12:00.034589 u2DelayCellOfst[4]=7 cells (2 PI)
8965 12:12:00.037739 u2DelayCellOfst[5]=22 cells (6 PI)
8966 12:12:00.040807 u2DelayCellOfst[6]=22 cells (6 PI)
8967 12:12:00.044590 u2DelayCellOfst[7]=7 cells (2 PI)
8968 12:12:00.047774 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8969 12:12:00.050987 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8970 12:12:00.054760 == TX Byte 1 ==
8971 12:12:00.058164 u2DelayCellOfst[8]=0 cells (0 PI)
8972 12:12:00.058301 u2DelayCellOfst[9]=3 cells (1 PI)
8973 12:12:00.061194 u2DelayCellOfst[10]=11 cells (3 PI)
8974 12:12:00.064442 u2DelayCellOfst[11]=3 cells (1 PI)
8975 12:12:00.067699 u2DelayCellOfst[12]=14 cells (4 PI)
8976 12:12:00.070821 u2DelayCellOfst[13]=14 cells (4 PI)
8977 12:12:00.073967 u2DelayCellOfst[14]=14 cells (4 PI)
8978 12:12:00.077288 u2DelayCellOfst[15]=14 cells (4 PI)
8979 12:12:00.084266 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8980 12:12:00.087505 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8981 12:12:00.087628 DramC Write-DBI on
8982 12:12:00.087725 ==
8983 12:12:00.090737 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 12:12:00.097175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 12:12:00.097290 ==
8986 12:12:00.097390
8987 12:12:00.097497
8988 12:12:00.097603 TX Vref Scan disable
8989 12:12:00.101071 == TX Byte 0 ==
8990 12:12:00.104779 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8991 12:12:00.107851 == TX Byte 1 ==
8992 12:12:00.110992 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8993 12:12:00.114742 DramC Write-DBI off
8994 12:12:00.114880
8995 12:12:00.114975 [DATLAT]
8996 12:12:00.115089 Freq=1600, CH1 RK1
8997 12:12:00.115190
8998 12:12:00.118042 DATLAT Default: 0xf
8999 12:12:00.118132 0, 0xFFFF, sum = 0
9000 12:12:00.121261 1, 0xFFFF, sum = 0
9001 12:12:00.124567 2, 0xFFFF, sum = 0
9002 12:12:00.124674 3, 0xFFFF, sum = 0
9003 12:12:00.127777 4, 0xFFFF, sum = 0
9004 12:12:00.127896 5, 0xFFFF, sum = 0
9005 12:12:00.130878 6, 0xFFFF, sum = 0
9006 12:12:00.130996 7, 0xFFFF, sum = 0
9007 12:12:00.134547 8, 0xFFFF, sum = 0
9008 12:12:00.134661 9, 0xFFFF, sum = 0
9009 12:12:00.137784 10, 0xFFFF, sum = 0
9010 12:12:00.137909 11, 0xFFFF, sum = 0
9011 12:12:00.140795 12, 0xFFFF, sum = 0
9012 12:12:00.140919 13, 0xFFFF, sum = 0
9013 12:12:00.144550 14, 0x0, sum = 1
9014 12:12:00.144667 15, 0x0, sum = 2
9015 12:12:00.147608 16, 0x0, sum = 3
9016 12:12:00.147726 17, 0x0, sum = 4
9017 12:12:00.150923 best_step = 15
9018 12:12:00.151037
9019 12:12:00.151140 ==
9020 12:12:00.154137 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 12:12:00.157420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 12:12:00.157529 ==
9023 12:12:00.160654 RX Vref Scan: 0
9024 12:12:00.160732
9025 12:12:00.160823 RX Vref 0 -> 0, step: 1
9026 12:12:00.160903
9027 12:12:00.163804 RX Delay 11 -> 252, step: 4
9028 12:12:00.170164 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9029 12:12:00.174041 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9030 12:12:00.177215 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9031 12:12:00.180477 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9032 12:12:00.183599 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9033 12:12:00.190144 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9034 12:12:00.193928 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9035 12:12:00.197224 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9036 12:12:00.200446 iDelay=203, Bit 8, Center 114 (59 ~ 170) 112
9037 12:12:00.203752 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9038 12:12:00.210058 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9039 12:12:00.213666 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9040 12:12:00.216888 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9041 12:12:00.220176 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9042 12:12:00.226643 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9043 12:12:00.230013 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9044 12:12:00.230108 ==
9045 12:12:00.233217 Dram Type= 6, Freq= 0, CH_1, rank 1
9046 12:12:00.236277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9047 12:12:00.236383 ==
9048 12:12:00.240095 DQS Delay:
9049 12:12:00.240206 DQS0 = 0, DQS1 = 0
9050 12:12:00.240301 DQM Delay:
9051 12:12:00.243170 DQM0 = 133, DQM1 = 127
9052 12:12:00.243287 DQ Delay:
9053 12:12:00.246326 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9054 12:12:00.249392 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9055 12:12:00.253122 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9056 12:12:00.259503 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138
9057 12:12:00.259594
9058 12:12:00.259684
9059 12:12:00.259749
9060 12:12:00.262761 [DramC_TX_OE_Calibration] TA2
9061 12:12:00.266099 Original DQ_B0 (3 6) =30, OEN = 27
9062 12:12:00.266194 Original DQ_B1 (3 6) =30, OEN = 27
9063 12:12:00.269280 24, 0x0, End_B0=24 End_B1=24
9064 12:12:00.272886 25, 0x0, End_B0=25 End_B1=25
9065 12:12:00.276105 26, 0x0, End_B0=26 End_B1=26
9066 12:12:00.279253 27, 0x0, End_B0=27 End_B1=27
9067 12:12:00.279354 28, 0x0, End_B0=28 End_B1=28
9068 12:12:00.282464 29, 0x0, End_B0=29 End_B1=29
9069 12:12:00.285712 30, 0x0, End_B0=30 End_B1=30
9070 12:12:00.289608 31, 0x4141, End_B0=30 End_B1=30
9071 12:12:00.292838 Byte0 end_step=30 best_step=27
9072 12:12:00.295878 Byte1 end_step=30 best_step=27
9073 12:12:00.295982 Byte0 TX OE(2T, 0.5T) = (3, 3)
9074 12:12:00.299002 Byte1 TX OE(2T, 0.5T) = (3, 3)
9075 12:12:00.299125
9076 12:12:00.299219
9077 12:12:00.309196 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9078 12:12:00.312363 CH1 RK1: MR19=303, MR18=D09
9079 12:12:00.315501 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9080 12:12:00.319165 [RxdqsGatingPostProcess] freq 1600
9081 12:12:00.325512 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9082 12:12:00.328777 best DQS0 dly(2T, 0.5T) = (1, 1)
9083 12:12:00.332004 best DQS1 dly(2T, 0.5T) = (1, 1)
9084 12:12:00.335257 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9085 12:12:00.339010 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9086 12:12:00.342312 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 12:12:00.342400 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 12:12:00.345355 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 12:12:00.348477 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 12:12:00.352206 Pre-setting of DQS Precalculation
9091 12:12:00.358608 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9092 12:12:00.365044 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9093 12:12:00.371511 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 12:12:00.371626
9095 12:12:00.371715
9096 12:12:00.375257 [Calibration Summary] 3200 Mbps
9097 12:12:00.378277 CH 0, Rank 0
9098 12:12:00.378402 SW Impedance : PASS
9099 12:12:00.381477 DUTY Scan : NO K
9100 12:12:00.381584 ZQ Calibration : PASS
9101 12:12:00.384810 Jitter Meter : NO K
9102 12:12:00.387985 CBT Training : PASS
9103 12:12:00.388107 Write leveling : PASS
9104 12:12:00.391811 RX DQS gating : PASS
9105 12:12:00.395033 RX DQ/DQS(RDDQC) : PASS
9106 12:12:00.395154 TX DQ/DQS : PASS
9107 12:12:00.398354 RX DATLAT : PASS
9108 12:12:00.401422 RX DQ/DQS(Engine): PASS
9109 12:12:00.401532 TX OE : PASS
9110 12:12:00.404655 All Pass.
9111 12:12:00.404759
9112 12:12:00.404862 CH 0, Rank 1
9113 12:12:00.407861 SW Impedance : PASS
9114 12:12:00.407965 DUTY Scan : NO K
9115 12:12:00.411151 ZQ Calibration : PASS
9116 12:12:00.414337 Jitter Meter : NO K
9117 12:12:00.414447 CBT Training : PASS
9118 12:12:00.417927 Write leveling : PASS
9119 12:12:00.420938 RX DQS gating : PASS
9120 12:12:00.421047 RX DQ/DQS(RDDQC) : PASS
9121 12:12:00.424649 TX DQ/DQS : PASS
9122 12:12:00.427742 RX DATLAT : PASS
9123 12:12:00.427856 RX DQ/DQS(Engine): PASS
9124 12:12:00.430949 TX OE : PASS
9125 12:12:00.431060 All Pass.
9126 12:12:00.431154
9127 12:12:00.434228 CH 1, Rank 0
9128 12:12:00.434337 SW Impedance : PASS
9129 12:12:00.437491 DUTY Scan : NO K
9130 12:12:00.441257 ZQ Calibration : PASS
9131 12:12:00.441366 Jitter Meter : NO K
9132 12:12:00.444333 CBT Training : PASS
9133 12:12:00.447495 Write leveling : PASS
9134 12:12:00.447605 RX DQS gating : PASS
9135 12:12:00.451184 RX DQ/DQS(RDDQC) : PASS
9136 12:12:00.451292 TX DQ/DQS : PASS
9137 12:12:00.454240 RX DATLAT : PASS
9138 12:12:00.457352 RX DQ/DQS(Engine): PASS
9139 12:12:00.457459 TX OE : PASS
9140 12:12:00.460997 All Pass.
9141 12:12:00.461106
9142 12:12:00.461203 CH 1, Rank 1
9143 12:12:00.464212 SW Impedance : PASS
9144 12:12:00.464325 DUTY Scan : NO K
9145 12:12:00.467388 ZQ Calibration : PASS
9146 12:12:00.470671 Jitter Meter : NO K
9147 12:12:00.470780 CBT Training : PASS
9148 12:12:00.473941 Write leveling : PASS
9149 12:12:00.477157 RX DQS gating : PASS
9150 12:12:00.477296 RX DQ/DQS(RDDQC) : PASS
9151 12:12:00.480330 TX DQ/DQS : PASS
9152 12:12:00.484007 RX DATLAT : PASS
9153 12:12:00.484132 RX DQ/DQS(Engine): PASS
9154 12:12:00.487290 TX OE : PASS
9155 12:12:00.487419 All Pass.
9156 12:12:00.487518
9157 12:12:00.490503 DramC Write-DBI on
9158 12:12:00.493743 PER_BANK_REFRESH: Hybrid Mode
9159 12:12:00.493851 TX_TRACKING: ON
9160 12:12:00.503407 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9161 12:12:00.509864 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9162 12:12:00.520179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9163 12:12:00.523315 [FAST_K] Save calibration result to emmc
9164 12:12:00.523445 sync common calibartion params.
9165 12:12:00.526421 sync cbt_mode0:1, 1:1
9166 12:12:00.529497 dram_init: ddr_geometry: 2
9167 12:12:00.532761 dram_init: ddr_geometry: 2
9168 12:12:00.532867 dram_init: ddr_geometry: 2
9169 12:12:00.536510 0:dram_rank_size:100000000
9170 12:12:00.539878 1:dram_rank_size:100000000
9171 12:12:00.542542 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9172 12:12:00.546353 DFS_SHUFFLE_HW_MODE: ON
9173 12:12:00.549501 dramc_set_vcore_voltage set vcore to 725000
9174 12:12:00.552630 Read voltage for 1600, 0
9175 12:12:00.552752 Vio18 = 0
9176 12:12:00.555761 Vcore = 725000
9177 12:12:00.555867 Vdram = 0
9178 12:12:00.555980 Vddq = 0
9179 12:12:00.559459 Vmddr = 0
9180 12:12:00.559574 switch to 3200 Mbps bootup
9181 12:12:00.562546 [DramcRunTimeConfig]
9182 12:12:00.562646 PHYPLL
9183 12:12:00.565638 DPM_CONTROL_AFTERK: ON
9184 12:12:00.565728 PER_BANK_REFRESH: ON
9185 12:12:00.569377 REFRESH_OVERHEAD_REDUCTION: ON
9186 12:12:00.572652 CMD_PICG_NEW_MODE: OFF
9187 12:12:00.572757 XRTWTW_NEW_MODE: ON
9188 12:12:00.575733 XRTRTR_NEW_MODE: ON
9189 12:12:00.575816 TX_TRACKING: ON
9190 12:12:00.579063 RDSEL_TRACKING: OFF
9191 12:12:00.582212 DQS Precalculation for DVFS: ON
9192 12:12:00.582320 RX_TRACKING: OFF
9193 12:12:00.585331 HW_GATING DBG: ON
9194 12:12:00.585417 ZQCS_ENABLE_LP4: ON
9195 12:12:00.589177 RX_PICG_NEW_MODE: ON
9196 12:12:00.589252 TX_PICG_NEW_MODE: ON
9197 12:12:00.592427 ENABLE_RX_DCM_DPHY: ON
9198 12:12:00.595728 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9199 12:12:00.599000 DUMMY_READ_FOR_TRACKING: OFF
9200 12:12:00.599102 !!! SPM_CONTROL_AFTERK: OFF
9201 12:12:00.602193 !!! SPM could not control APHY
9202 12:12:00.605407 IMPEDANCE_TRACKING: ON
9203 12:12:00.605492 TEMP_SENSOR: ON
9204 12:12:00.608610 HW_SAVE_FOR_SR: OFF
9205 12:12:00.611771 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9206 12:12:00.615001 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9207 12:12:00.618771 Read ODT Tracking: ON
9208 12:12:00.618848 Refresh Rate DeBounce: ON
9209 12:12:00.622132 DFS_NO_QUEUE_FLUSH: ON
9210 12:12:00.625304 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9211 12:12:00.628476 ENABLE_DFS_RUNTIME_MRW: OFF
9212 12:12:00.628571 DDR_RESERVE_NEW_MODE: ON
9213 12:12:00.631552 MR_CBT_SWITCH_FREQ: ON
9214 12:12:00.634694 =========================
9215 12:12:00.652729 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9216 12:12:00.655850 dram_init: ddr_geometry: 2
9217 12:12:00.674285 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9218 12:12:00.677554 dram_init: dram init end (result: 0)
9219 12:12:00.683964 DRAM-K: Full calibration passed in 24583 msecs
9220 12:12:00.687665 MRC: failed to locate region type 0.
9221 12:12:00.687784 DRAM rank0 size:0x100000000,
9222 12:12:00.690831 DRAM rank1 size=0x100000000
9223 12:12:00.700500 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9224 12:12:00.707607 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9225 12:12:00.714067 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9226 12:12:00.720328 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9227 12:12:00.724138 DRAM rank0 size:0x100000000,
9228 12:12:00.727279 DRAM rank1 size=0x100000000
9229 12:12:00.727387 CBMEM:
9230 12:12:00.730484 IMD: root @ 0xfffff000 254 entries.
9231 12:12:00.733768 IMD: root @ 0xffffec00 62 entries.
9232 12:12:00.737370 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9233 12:12:00.743796 WARNING: RO_VPD is uninitialized or empty.
9234 12:12:00.746935 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9235 12:12:00.754178 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9236 12:12:00.766770 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9237 12:12:00.778353 BS: romstage times (exec / console): total (unknown) / 24080 ms
9238 12:12:00.778504
9239 12:12:00.778606
9240 12:12:00.788590 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9241 12:12:00.791770 ARM64: Exception handlers installed.
9242 12:12:00.794999 ARM64: Testing exception
9243 12:12:00.798144 ARM64: Done test exception
9244 12:12:00.798224 Enumerating buses...
9245 12:12:00.801520 Show all devs... Before device enumeration.
9246 12:12:00.804674 Root Device: enabled 1
9247 12:12:00.807977 CPU_CLUSTER: 0: enabled 1
9248 12:12:00.808088 CPU: 00: enabled 1
9249 12:12:00.811229 Compare with tree...
9250 12:12:00.811318 Root Device: enabled 1
9251 12:12:00.814534 CPU_CLUSTER: 0: enabled 1
9252 12:12:00.817945 CPU: 00: enabled 1
9253 12:12:00.818063 Root Device scanning...
9254 12:12:00.821136 scan_static_bus for Root Device
9255 12:12:00.824341 CPU_CLUSTER: 0 enabled
9256 12:12:00.828276 scan_static_bus for Root Device done
9257 12:12:00.831400 scan_bus: bus Root Device finished in 8 msecs
9258 12:12:00.831507 done
9259 12:12:00.837631 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9260 12:12:00.840861 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9261 12:12:00.847717 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9262 12:12:00.850853 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9263 12:12:00.854051 Allocating resources...
9264 12:12:00.857273 Reading resources...
9265 12:12:00.860552 Root Device read_resources bus 0 link: 0
9266 12:12:00.864248 DRAM rank0 size:0x100000000,
9267 12:12:00.864362 DRAM rank1 size=0x100000000
9268 12:12:00.870410 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9269 12:12:00.870524 CPU: 00 missing read_resources
9270 12:12:00.877370 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9271 12:12:00.880302 Root Device read_resources bus 0 link: 0 done
9272 12:12:00.883505 Done reading resources.
9273 12:12:00.887334 Show resources in subtree (Root Device)...After reading.
9274 12:12:00.890517 Root Device child on link 0 CPU_CLUSTER: 0
9275 12:12:00.893801 CPU_CLUSTER: 0 child on link 0 CPU: 00
9276 12:12:00.903463 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9277 12:12:00.903561 CPU: 00
9278 12:12:00.909946 Root Device assign_resources, bus 0 link: 0
9279 12:12:00.913261 CPU_CLUSTER: 0 missing set_resources
9280 12:12:00.916478 Root Device assign_resources, bus 0 link: 0 done
9281 12:12:00.916605 Done setting resources.
9282 12:12:00.923237 Show resources in subtree (Root Device)...After assigning values.
9283 12:12:00.926996 Root Device child on link 0 CPU_CLUSTER: 0
9284 12:12:00.930265 CPU_CLUSTER: 0 child on link 0 CPU: 00
9285 12:12:00.939803 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9286 12:12:00.939934 CPU: 00
9287 12:12:00.943504 Done allocating resources.
9288 12:12:00.949781 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9289 12:12:00.949907 Enabling resources...
9290 12:12:00.952961 done.
9291 12:12:00.956210 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9292 12:12:00.960066 Initializing devices...
9293 12:12:00.960193 Root Device init
9294 12:12:00.962734 init hardware done!
9295 12:12:00.962840 0x00000018: ctrlr->caps
9296 12:12:00.966443 52.000 MHz: ctrlr->f_max
9297 12:12:00.969650 0.400 MHz: ctrlr->f_min
9298 12:12:00.969761 0x40ff8080: ctrlr->voltages
9299 12:12:00.972862 sclk: 390625
9300 12:12:00.972972 Bus Width = 1
9301 12:12:00.975955 sclk: 390625
9302 12:12:00.976072 Bus Width = 1
9303 12:12:00.979079 Early init status = 3
9304 12:12:00.982862 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9305 12:12:00.985952 in-header: 03 fb 00 00 01 00 00 00
9306 12:12:00.989106 in-data: 01
9307 12:12:00.992354 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9308 12:12:00.999538 in-header: 03 fb 00 00 01 00 00 00
9309 12:12:00.999673 in-data: 01
9310 12:12:01.002741 [SSUSB] Setting up USB HOST controller...
9311 12:12:01.005954 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9312 12:12:01.009197 [SSUSB] phy power-on done.
9313 12:12:01.012351 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9314 12:12:01.019451 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9315 12:12:01.022631 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9316 12:12:01.028977 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9317 12:12:01.036059 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9318 12:12:01.042345 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9319 12:12:01.049184 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9320 12:12:01.055519 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9321 12:12:01.058765 SPM: binary array size = 0x9dc
9322 12:12:01.065273 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9323 12:12:01.068510 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9324 12:12:01.078482 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9325 12:12:01.081805 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9326 12:12:01.084979 configure_display: Starting display init
9327 12:12:01.120059 anx7625_power_on_init: Init interface.
9328 12:12:01.123340 anx7625_disable_pd_protocol: Disabled PD feature.
9329 12:12:01.126595 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9330 12:12:01.154466 anx7625_start_dp_work: Secure OCM version=00
9331 12:12:01.157562 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9332 12:12:01.172131 sp_tx_get_edid_block: EDID Block = 1
9333 12:12:01.274754 Extracted contents:
9334 12:12:01.277957 header: 00 ff ff ff ff ff ff 00
9335 12:12:01.281650 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9336 12:12:01.284845 version: 01 04
9337 12:12:01.288017 basic params: 95 1f 11 78 0a
9338 12:12:01.291289 chroma info: 76 90 94 55 54 90 27 21 50 54
9339 12:12:01.294408 established: 00 00 00
9340 12:12:01.301126 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9341 12:12:01.304328 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9342 12:12:01.310940 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9343 12:12:01.317457 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9344 12:12:01.324018 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9345 12:12:01.327183 extensions: 00
9346 12:12:01.327294 checksum: fb
9347 12:12:01.327394
9348 12:12:01.334151 Manufacturer: IVO Model 57d Serial Number 0
9349 12:12:01.334240 Made week 0 of 2020
9350 12:12:01.337474 EDID version: 1.4
9351 12:12:01.337557 Digital display
9352 12:12:01.340649 6 bits per primary color channel
9353 12:12:01.340733 DisplayPort interface
9354 12:12:01.343870 Maximum image size: 31 cm x 17 cm
9355 12:12:01.347697 Gamma: 220%
9356 12:12:01.347777 Check DPMS levels
9357 12:12:01.354083 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9358 12:12:01.357171 First detailed timing is preferred timing
9359 12:12:01.357290 Established timings supported:
9360 12:12:01.360319 Standard timings supported:
9361 12:12:01.363858 Detailed timings
9362 12:12:01.366851 Hex of detail: 383680a07038204018303c0035ae10000019
9363 12:12:01.373388 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9364 12:12:01.377274 0780 0798 07c8 0820 hborder 0
9365 12:12:01.380451 0438 043b 0447 0458 vborder 0
9366 12:12:01.383611 -hsync -vsync
9367 12:12:01.383726 Did detailed timing
9368 12:12:01.390122 Hex of detail: 000000000000000000000000000000000000
9369 12:12:01.393789 Manufacturer-specified data, tag 0
9370 12:12:01.396909 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9371 12:12:01.399857 ASCII string: InfoVision
9372 12:12:01.403463 Hex of detail: 000000fe00523134304e574635205248200a
9373 12:12:01.407132 ASCII string: R140NWF5 RH
9374 12:12:01.407244 Checksum
9375 12:12:01.410380 Checksum: 0xfb (valid)
9376 12:12:01.413757 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9377 12:12:01.416978 DSI data_rate: 832800000 bps
9378 12:12:01.423193 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9379 12:12:01.426403 anx7625_parse_edid: pixelclock(138800).
9380 12:12:01.430252 hactive(1920), hsync(48), hfp(24), hbp(88)
9381 12:12:01.433470 vactive(1080), vsync(12), vfp(3), vbp(17)
9382 12:12:01.436771 anx7625_dsi_config: config dsi.
9383 12:12:01.443145 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9384 12:12:01.457049 anx7625_dsi_config: success to config DSI
9385 12:12:01.460178 anx7625_dp_start: MIPI phy setup OK.
9386 12:12:01.463237 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9387 12:12:01.466455 mtk_ddp_mode_set invalid vrefresh 60
9388 12:12:01.470183 main_disp_path_setup
9389 12:12:01.470287 ovl_layer_smi_id_en
9390 12:12:01.473395 ovl_layer_smi_id_en
9391 12:12:01.473504 ccorr_config
9392 12:12:01.473601 aal_config
9393 12:12:01.476590 gamma_config
9394 12:12:01.476711 postmask_config
9395 12:12:01.479803 dither_config
9396 12:12:01.483082 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9397 12:12:01.490081 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9398 12:12:01.493174 Root Device init finished in 529 msecs
9399 12:12:01.496339 CPU_CLUSTER: 0 init
9400 12:12:01.503087 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9401 12:12:01.509378 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9402 12:12:01.509493 APU_MBOX 0x190000b0 = 0x10001
9403 12:12:01.513150 APU_MBOX 0x190001b0 = 0x10001
9404 12:12:01.516346 APU_MBOX 0x190005b0 = 0x10001
9405 12:12:01.519411 APU_MBOX 0x190006b0 = 0x10001
9406 12:12:01.525772 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9407 12:12:01.535965 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9408 12:12:01.548364 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9409 12:12:01.554815 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9410 12:12:01.566275 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9411 12:12:01.575747 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9412 12:12:01.578928 CPU_CLUSTER: 0 init finished in 81 msecs
9413 12:12:01.582144 Devices initialized
9414 12:12:01.585380 Show all devs... After init.
9415 12:12:01.585459 Root Device: enabled 1
9416 12:12:01.588524 CPU_CLUSTER: 0: enabled 1
9417 12:12:01.591780 CPU: 00: enabled 1
9418 12:12:01.595572 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9419 12:12:01.598628 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9420 12:12:01.601781 ELOG: NV offset 0x57f000 size 0x1000
9421 12:12:01.608602 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9422 12:12:01.615299 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9423 12:12:01.618516 ELOG: Event(17) added with size 13 at 2023-06-06 12:12:07 UTC
9424 12:12:01.625055 out: cmd=0x121: 03 db 21 01 00 00 00 00
9425 12:12:01.628352 in-header: 03 02 00 00 2c 00 00 00
9426 12:12:01.641860 in-data: 5d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9427 12:12:01.648040 ELOG: Event(A1) added with size 10 at 2023-06-06 12:12:07 UTC
9428 12:12:01.655156 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9429 12:12:01.658357 ELOG: Event(A0) added with size 9 at 2023-06-06 12:12:07 UTC
9430 12:12:01.661729 elog_add_boot_reason: Logged dev mode boot
9431 12:12:01.668240 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9432 12:12:01.671214 Finalize devices...
9433 12:12:01.671339 Devices finalized
9434 12:12:01.677905 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9435 12:12:01.680987 Writing coreboot table at 0xffe64000
9436 12:12:01.684203 0. 000000000010a000-0000000000113fff: RAMSTAGE
9437 12:12:01.688084 1. 0000000040000000-00000000400fffff: RAM
9438 12:12:01.691282 2. 0000000040100000-000000004032afff: RAMSTAGE
9439 12:12:01.694562 3. 000000004032b000-00000000545fffff: RAM
9440 12:12:01.700857 4. 0000000054600000-000000005465ffff: BL31
9441 12:12:01.704448 5. 0000000054660000-00000000ffe63fff: RAM
9442 12:12:01.707598 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9443 12:12:01.713898 7. 0000000100000000-000000023fffffff: RAM
9444 12:12:01.714005 Passing 5 GPIOs to payload:
9445 12:12:01.720783 NAME | PORT | POLARITY | VALUE
9446 12:12:01.724023 EC in RW | 0x000000aa | low | undefined
9447 12:12:01.727145 EC interrupt | 0x00000005 | low | undefined
9448 12:12:01.734253 TPM interrupt | 0x000000ab | high | undefined
9449 12:12:01.737397 SD card detect | 0x00000011 | high | undefined
9450 12:12:01.743768 speaker enable | 0x00000093 | high | undefined
9451 12:12:01.746978 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9452 12:12:01.750823 in-header: 03 f9 00 00 02 00 00 00
9453 12:12:01.750927 in-data: 02 00
9454 12:12:01.754213 ADC[4]: Raw value=901922 ID=7
9455 12:12:01.757378 ADC[3]: Raw value=213282 ID=1
9456 12:12:01.760590 RAM Code: 0x71
9457 12:12:01.760694 ADC[6]: Raw value=75036 ID=0
9458 12:12:01.763772 ADC[5]: Raw value=212543 ID=1
9459 12:12:01.766818 SKU Code: 0x1
9460 12:12:01.770737 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9461 12:12:01.773804 coreboot table: 964 bytes.
9462 12:12:01.776949 IMD ROOT 0. 0xfffff000 0x00001000
9463 12:12:01.780090 IMD SMALL 1. 0xffffe000 0x00001000
9464 12:12:01.783217 RO MCACHE 2. 0xffffc000 0x00001104
9465 12:12:01.787100 CONSOLE 3. 0xfff7c000 0x00080000
9466 12:12:01.790260 FMAP 4. 0xfff7b000 0x00000452
9467 12:12:01.793461 TIME STAMP 5. 0xfff7a000 0x00000910
9468 12:12:01.796827 VBOOT WORK 6. 0xfff66000 0x00014000
9469 12:12:01.800098 RAMOOPS 7. 0xffe66000 0x00100000
9470 12:12:01.803218 COREBOOT 8. 0xffe64000 0x00002000
9471 12:12:01.803323 IMD small region:
9472 12:12:01.806489 IMD ROOT 0. 0xffffec00 0x00000400
9473 12:12:01.813050 VPD 1. 0xffffeba0 0x0000004c
9474 12:12:01.816130 MMC STATUS 2. 0xffffeb80 0x00000004
9475 12:12:01.820019 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9476 12:12:01.823138 Probing TPM: done!
9477 12:12:01.826368 Connected to device vid:did:rid of 1ae0:0028:00
9478 12:12:01.836660 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9479 12:12:01.839787 Initialized TPM device CR50 revision 0
9480 12:12:01.843508 Checking cr50 for pending updates
9481 12:12:01.847470 Reading cr50 TPM mode
9482 12:12:01.855974 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9483 12:12:01.862367 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9484 12:12:01.902704 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9485 12:12:01.906009 Checking segment from ROM address 0x40100000
9486 12:12:01.909274 Checking segment from ROM address 0x4010001c
9487 12:12:01.915481 Loading segment from ROM address 0x40100000
9488 12:12:01.915563 code (compression=0)
9489 12:12:01.925862 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9490 12:12:01.931997 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9491 12:12:01.932079 it's not compressed!
9492 12:12:01.939083 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9493 12:12:01.945466 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9494 12:12:01.963316 Loading segment from ROM address 0x4010001c
9495 12:12:01.963398 Entry Point 0x80000000
9496 12:12:01.966433 Loaded segments
9497 12:12:01.969691 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9498 12:12:01.976126 Jumping to boot code at 0x80000000(0xffe64000)
9499 12:12:01.982978 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9500 12:12:01.989267 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9501 12:12:01.997621 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9502 12:12:02.000756 Checking segment from ROM address 0x40100000
9503 12:12:02.004005 Checking segment from ROM address 0x4010001c
9504 12:12:02.010412 Loading segment from ROM address 0x40100000
9505 12:12:02.010493 code (compression=1)
9506 12:12:02.017433 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9507 12:12:02.027365 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9508 12:12:02.027455 using LZMA
9509 12:12:02.035995 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9510 12:12:02.042372 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9511 12:12:02.045602 Loading segment from ROM address 0x4010001c
9512 12:12:02.045706 Entry Point 0x54601000
9513 12:12:02.048865 Loaded segments
9514 12:12:02.051976 NOTICE: MT8192 bl31_setup
9515 12:12:02.059541 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9516 12:12:02.062825 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9517 12:12:02.065899 WARNING: region 0:
9518 12:12:02.069216 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 12:12:02.069317 WARNING: region 1:
9520 12:12:02.076162 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9521 12:12:02.079423 WARNING: region 2:
9522 12:12:02.082596 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9523 12:12:02.085705 WARNING: region 3:
9524 12:12:02.089376 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9525 12:12:02.092342 WARNING: region 4:
9526 12:12:02.099158 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9527 12:12:02.099283 WARNING: region 5:
9528 12:12:02.102381 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 12:12:02.105533 WARNING: region 6:
9530 12:12:02.108858 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9531 12:12:02.112652 WARNING: region 7:
9532 12:12:02.115918 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 12:12:02.122392 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9534 12:12:02.126113 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9535 12:12:02.129300 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9536 12:12:02.135561 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9537 12:12:02.139283 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9538 12:12:02.142478 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9539 12:12:02.149161 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9540 12:12:02.152368 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9541 12:12:02.158837 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9542 12:12:02.162072 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9543 12:12:02.165317 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9544 12:12:02.172398 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9545 12:12:02.175571 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9546 12:12:02.178935 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9547 12:12:02.185484 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9548 12:12:02.188647 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9549 12:12:02.195398 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9550 12:12:02.198643 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9551 12:12:02.201785 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9552 12:12:02.208371 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9553 12:12:02.211714 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9554 12:12:02.218676 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9555 12:12:02.221974 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9556 12:12:02.225149 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9557 12:12:02.232015 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9558 12:12:02.235156 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9559 12:12:02.241531 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9560 12:12:02.244726 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9561 12:12:02.251964 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9562 12:12:02.254586 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9563 12:12:02.258294 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9564 12:12:02.264755 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9565 12:12:02.268007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9566 12:12:02.271350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9567 12:12:02.274963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9568 12:12:02.281453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9569 12:12:02.284638 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9570 12:12:02.287874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9571 12:12:02.290995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9572 12:12:02.297796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9573 12:12:02.300889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9574 12:12:02.304121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9575 12:12:02.307772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9576 12:12:02.314821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9577 12:12:02.317885 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9578 12:12:02.321133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9579 12:12:02.327645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9580 12:12:02.330796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9581 12:12:02.334039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9582 12:12:02.340959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9583 12:12:02.344099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9584 12:12:02.350979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9585 12:12:02.354170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9586 12:12:02.357479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9587 12:12:02.364482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9588 12:12:02.367743 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9589 12:12:02.374303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9590 12:12:02.377530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9591 12:12:02.383951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9592 12:12:02.387253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9593 12:12:02.390533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9594 12:12:02.397532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9595 12:12:02.400573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9596 12:12:02.407335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9597 12:12:02.410470 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9598 12:12:02.417351 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9599 12:12:02.420598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9600 12:12:02.426989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9601 12:12:02.430761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9602 12:12:02.433896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9603 12:12:02.440568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9604 12:12:02.443855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9605 12:12:02.450498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9606 12:12:02.453794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9607 12:12:02.460188 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9608 12:12:02.463388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9609 12:12:02.470100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9610 12:12:02.473341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9611 12:12:02.476627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9612 12:12:02.483227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9613 12:12:02.486549 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9614 12:12:02.493714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9615 12:12:02.496930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9616 12:12:02.503221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9617 12:12:02.507063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9618 12:12:02.510118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9619 12:12:02.516430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9620 12:12:02.520163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9621 12:12:02.526623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9622 12:12:02.529885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9623 12:12:02.536267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9624 12:12:02.540251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9625 12:12:02.546523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9626 12:12:02.549528 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9627 12:12:02.552856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9628 12:12:02.559979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9629 12:12:02.563185 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9630 12:12:02.566340 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9631 12:12:02.572765 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9632 12:12:02.576509 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9633 12:12:02.579854 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9634 12:12:02.586383 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9635 12:12:02.589629 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9636 12:12:02.592987 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9637 12:12:02.599461 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9638 12:12:02.602819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9639 12:12:02.609747 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9640 12:12:02.613061 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9641 12:12:02.616086 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9642 12:12:02.622863 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9643 12:12:02.626004 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9644 12:12:02.632374 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9645 12:12:02.635600 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9646 12:12:02.639497 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9647 12:12:02.645719 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9648 12:12:02.649446 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9649 12:12:02.652551 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9650 12:12:02.659398 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9651 12:12:02.662628 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9652 12:12:02.665902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9653 12:12:02.672289 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9654 12:12:02.675484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9655 12:12:02.678722 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9656 12:12:02.681965 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9657 12:12:02.689117 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9658 12:12:02.692225 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9659 12:12:02.698577 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9660 12:12:02.702382 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9661 12:12:02.705490 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9662 12:12:02.711930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9663 12:12:02.715521 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9664 12:12:02.721750 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9665 12:12:02.724989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9666 12:12:02.728647 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9667 12:12:02.734949 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9668 12:12:02.738940 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9669 12:12:02.744812 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9670 12:12:02.748768 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9671 12:12:02.752021 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9672 12:12:02.758613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9673 12:12:02.761558 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9674 12:12:02.765329 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9675 12:12:02.771992 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9676 12:12:02.775189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9677 12:12:02.781710 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9678 12:12:02.784977 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9679 12:12:02.788350 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9680 12:12:02.794900 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9681 12:12:02.798130 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9682 12:12:02.804938 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9683 12:12:02.808133 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9684 12:12:02.811213 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9685 12:12:02.818178 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9686 12:12:02.821344 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9687 12:12:02.828266 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9688 12:12:02.831244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9689 12:12:02.834322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9690 12:12:02.841391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9691 12:12:02.844561 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9692 12:12:02.851005 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9693 12:12:02.854204 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9694 12:12:02.857511 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9695 12:12:02.864377 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9696 12:12:02.867362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9697 12:12:02.874321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9698 12:12:02.877496 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9699 12:12:02.880738 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9700 12:12:02.887082 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9701 12:12:02.890344 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9702 12:12:02.897417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9703 12:12:02.900471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9704 12:12:02.903640 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9705 12:12:02.910611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9706 12:12:02.913887 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9707 12:12:02.920602 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9708 12:12:02.923901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9709 12:12:02.926956 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9710 12:12:02.933543 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9711 12:12:02.936849 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9712 12:12:02.943155 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9713 12:12:02.946402 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9714 12:12:02.950264 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9715 12:12:02.956115 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9716 12:12:02.959735 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9717 12:12:02.966490 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9718 12:12:02.969513 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9719 12:12:02.972609 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9720 12:12:02.979728 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9721 12:12:02.982955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9722 12:12:02.989354 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9723 12:12:02.992554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9724 12:12:02.998969 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9725 12:12:03.002715 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9726 12:12:03.006194 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9727 12:12:03.012449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9728 12:12:03.015678 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9729 12:12:03.022156 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9730 12:12:03.025266 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9731 12:12:03.032266 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9732 12:12:03.035393 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9733 12:12:03.039106 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9734 12:12:03.045496 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9735 12:12:03.048748 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9736 12:12:03.055252 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9737 12:12:03.058558 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9738 12:12:03.065529 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9739 12:12:03.068601 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9740 12:12:03.071728 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9741 12:12:03.078618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9742 12:12:03.081943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9743 12:12:03.088350 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9744 12:12:03.091671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9745 12:12:03.094826 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9746 12:12:03.101875 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9747 12:12:03.105082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9748 12:12:03.111526 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9749 12:12:03.114870 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9750 12:12:03.121714 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9751 12:12:03.124919 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9752 12:12:03.128192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9753 12:12:03.134465 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9754 12:12:03.138191 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9755 12:12:03.144405 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9756 12:12:03.148254 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9757 12:12:03.154865 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9758 12:12:03.158133 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9759 12:12:03.161363 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9760 12:12:03.167792 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9761 12:12:03.170932 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9762 12:12:03.174268 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9763 12:12:03.180995 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9764 12:12:03.184278 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9765 12:12:03.187488 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9766 12:12:03.190748 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9767 12:12:03.197228 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9768 12:12:03.200985 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9769 12:12:03.206957 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9770 12:12:03.210267 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9771 12:12:03.214277 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9772 12:12:03.220415 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9773 12:12:03.223728 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9774 12:12:03.226807 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9775 12:12:03.233980 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9776 12:12:03.237095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9777 12:12:03.243210 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9778 12:12:03.246883 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9779 12:12:03.250032 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9780 12:12:03.256559 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9781 12:12:03.259800 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9782 12:12:03.262938 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9783 12:12:03.269471 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9784 12:12:03.273094 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9785 12:12:03.279965 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9786 12:12:03.283018 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9787 12:12:03.286107 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9788 12:12:03.292636 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9789 12:12:03.295876 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9790 12:12:03.302483 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9791 12:12:03.305736 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9792 12:12:03.309567 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9793 12:12:03.315933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9794 12:12:03.319273 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9795 12:12:03.322494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9796 12:12:03.328980 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9797 12:12:03.332723 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9798 12:12:03.335977 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9799 12:12:03.342295 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9800 12:12:03.345984 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9801 12:12:03.348961 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9802 12:12:03.355794 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9803 12:12:03.358921 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9804 12:12:03.362267 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9805 12:12:03.365463 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9806 12:12:03.371952 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9807 12:12:03.375197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9808 12:12:03.378470 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9809 12:12:03.382231 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9810 12:12:03.388470 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9811 12:12:03.391620 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9812 12:12:03.394910 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9813 12:12:03.401515 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9814 12:12:03.405320 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9815 12:12:03.408512 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9816 12:12:03.415081 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9817 12:12:03.418125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9818 12:12:03.424530 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9819 12:12:03.427808 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9820 12:12:03.431597 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9821 12:12:03.437936 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9822 12:12:03.441043 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9823 12:12:03.448083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9824 12:12:03.451234 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9825 12:12:03.457542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9826 12:12:03.461284 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9827 12:12:03.464524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9828 12:12:03.470527 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9829 12:12:03.474312 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9830 12:12:03.480811 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9831 12:12:03.483969 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9832 12:12:03.487588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9833 12:12:03.493883 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9834 12:12:03.497136 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9835 12:12:03.503849 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9836 12:12:03.506871 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9837 12:12:03.513686 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9838 12:12:03.516935 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9839 12:12:03.520688 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9840 12:12:03.526851 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9841 12:12:03.530771 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9842 12:12:03.537139 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9843 12:12:03.540289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9844 12:12:03.543430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9845 12:12:03.550426 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9846 12:12:03.553601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9847 12:12:03.560355 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9848 12:12:03.563521 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9849 12:12:03.566738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9850 12:12:03.573277 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9851 12:12:03.576534 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9852 12:12:03.583036 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9853 12:12:03.586748 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9854 12:12:03.593061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9855 12:12:03.596267 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9856 12:12:03.599465 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9857 12:12:03.606106 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9858 12:12:03.609361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9859 12:12:03.616291 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9860 12:12:03.619512 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9861 12:12:03.625870 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9862 12:12:03.629144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9863 12:12:03.632490 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9864 12:12:03.639514 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9865 12:12:03.642763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9866 12:12:03.649117 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9867 12:12:03.652439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9868 12:12:03.655656 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9869 12:12:03.662345 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9870 12:12:03.665556 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9871 12:12:03.672473 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9872 12:12:03.675713 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9873 12:12:03.678899 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9874 12:12:03.685398 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9875 12:12:03.688538 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9876 12:12:03.695435 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9877 12:12:03.698608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9878 12:12:03.702255 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9879 12:12:03.708699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9880 12:12:03.711922 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9881 12:12:03.718917 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9882 12:12:03.722171 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9883 12:12:03.728519 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9884 12:12:03.731808 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9885 12:12:03.738238 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9886 12:12:03.742022 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9887 12:12:03.745215 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9888 12:12:03.751485 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9889 12:12:03.754775 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9890 12:12:03.761749 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9891 12:12:03.764831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9892 12:12:03.771775 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9893 12:12:03.774850 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9894 12:12:03.778163 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9895 12:12:03.784620 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9896 12:12:03.787766 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9897 12:12:03.794591 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9898 12:12:03.797804 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9899 12:12:03.804827 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9900 12:12:03.807888 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9901 12:12:03.814228 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9902 12:12:03.818172 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9903 12:12:03.821285 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9904 12:12:03.827813 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9905 12:12:03.830888 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9906 12:12:03.837484 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9907 12:12:03.840778 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9908 12:12:03.847106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9909 12:12:03.850889 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9910 12:12:03.854195 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9911 12:12:03.860463 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9912 12:12:03.863628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9913 12:12:03.870461 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9914 12:12:03.873538 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9915 12:12:03.880739 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9916 12:12:03.883934 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9917 12:12:03.890356 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9918 12:12:03.893574 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9919 12:12:03.896759 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9920 12:12:03.903623 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9921 12:12:03.907246 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9922 12:12:03.913543 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9923 12:12:03.916818 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9924 12:12:03.923860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9925 12:12:03.927100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9926 12:12:03.930312 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9927 12:12:03.936828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9928 12:12:03.940069 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9929 12:12:03.946507 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9930 12:12:03.949792 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9931 12:12:03.956822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9932 12:12:03.960006 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9933 12:12:03.966372 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9934 12:12:03.969585 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9935 12:12:03.973345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9936 12:12:03.979479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9937 12:12:03.983175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9938 12:12:03.989775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9939 12:12:03.992994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9940 12:12:03.999294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9941 12:12:04.002370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9942 12:12:04.009392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9943 12:12:04.012580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9944 12:12:04.019265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9945 12:12:04.022497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9946 12:12:04.028956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9947 12:12:04.032119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9948 12:12:04.038591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9949 12:12:04.042446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9950 12:12:04.048978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9951 12:12:04.052334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9952 12:12:04.058556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9953 12:12:04.061843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9954 12:12:04.068874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9955 12:12:04.072141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9956 12:12:04.078431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9957 12:12:04.081576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9958 12:12:04.088209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9959 12:12:04.091374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9960 12:12:04.098437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9961 12:12:04.101757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9962 12:12:04.107945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9963 12:12:04.111140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9964 12:12:04.117611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9965 12:12:04.121260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9966 12:12:04.128076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9967 12:12:04.131326 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9968 12:12:04.134469 INFO: [APUAPC] vio 0
9969 12:12:04.137799 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9970 12:12:04.144177 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9971 12:12:04.147564 INFO: [APUAPC] D0_APC_0: 0x400510
9972 12:12:04.147678 INFO: [APUAPC] D0_APC_1: 0x0
9973 12:12:04.150836 INFO: [APUAPC] D0_APC_2: 0x1540
9974 12:12:04.153945 INFO: [APUAPC] D0_APC_3: 0x0
9975 12:12:04.157714 INFO: [APUAPC] D1_APC_0: 0xffffffff
9976 12:12:04.160865 INFO: [APUAPC] D1_APC_1: 0xffffffff
9977 12:12:04.164111 INFO: [APUAPC] D1_APC_2: 0x3fffff
9978 12:12:04.167243 INFO: [APUAPC] D1_APC_3: 0x0
9979 12:12:04.170999 INFO: [APUAPC] D2_APC_0: 0xffffffff
9980 12:12:04.174263 INFO: [APUAPC] D2_APC_1: 0xffffffff
9981 12:12:04.177479 INFO: [APUAPC] D2_APC_2: 0x3fffff
9982 12:12:04.180464 INFO: [APUAPC] D2_APC_3: 0x0
9983 12:12:04.184143 INFO: [APUAPC] D3_APC_0: 0xffffffff
9984 12:12:04.187260 INFO: [APUAPC] D3_APC_1: 0xffffffff
9985 12:12:04.190373 INFO: [APUAPC] D3_APC_2: 0x3fffff
9986 12:12:04.194164 INFO: [APUAPC] D3_APC_3: 0x0
9987 12:12:04.197320 INFO: [APUAPC] D4_APC_0: 0xffffffff
9988 12:12:04.200622 INFO: [APUAPC] D4_APC_1: 0xffffffff
9989 12:12:04.203890 INFO: [APUAPC] D4_APC_2: 0x3fffff
9990 12:12:04.207140 INFO: [APUAPC] D4_APC_3: 0x0
9991 12:12:04.210395 INFO: [APUAPC] D5_APC_0: 0xffffffff
9992 12:12:04.213723 INFO: [APUAPC] D5_APC_1: 0xffffffff
9993 12:12:04.216567 INFO: [APUAPC] D5_APC_2: 0x3fffff
9994 12:12:04.220387 INFO: [APUAPC] D5_APC_3: 0x0
9995 12:12:04.223596 INFO: [APUAPC] D6_APC_0: 0xffffffff
9996 12:12:04.226744 INFO: [APUAPC] D6_APC_1: 0xffffffff
9997 12:12:04.229841 INFO: [APUAPC] D6_APC_2: 0x3fffff
9998 12:12:04.233387 INFO: [APUAPC] D6_APC_3: 0x0
9999 12:12:04.236587 INFO: [APUAPC] D7_APC_0: 0xffffffff
10000 12:12:04.240341 INFO: [APUAPC] D7_APC_1: 0xffffffff
10001 12:12:04.243533 INFO: [APUAPC] D7_APC_2: 0x3fffff
10002 12:12:04.246737 INFO: [APUAPC] D7_APC_3: 0x0
10003 12:12:04.250114 INFO: [APUAPC] D8_APC_0: 0xffffffff
10004 12:12:04.253139 INFO: [APUAPC] D8_APC_1: 0xffffffff
10005 12:12:04.256479 INFO: [APUAPC] D8_APC_2: 0x3fffff
10006 12:12:04.259742 INFO: [APUAPC] D8_APC_3: 0x0
10007 12:12:04.263124 INFO: [APUAPC] D9_APC_0: 0xffffffff
10008 12:12:04.266245 INFO: [APUAPC] D9_APC_1: 0xffffffff
10009 12:12:04.269479 INFO: [APUAPC] D9_APC_2: 0x3fffff
10010 12:12:04.272761 INFO: [APUAPC] D9_APC_3: 0x0
10011 12:12:04.275959 INFO: [APUAPC] D10_APC_0: 0xffffffff
10012 12:12:04.279775 INFO: [APUAPC] D10_APC_1: 0xffffffff
10013 12:12:04.282873 INFO: [APUAPC] D10_APC_2: 0x3fffff
10014 12:12:04.285963 INFO: [APUAPC] D10_APC_3: 0x0
10015 12:12:04.289093 INFO: [APUAPC] D11_APC_0: 0xffffffff
10016 12:12:04.292876 INFO: [APUAPC] D11_APC_1: 0xffffffff
10017 12:12:04.295961 INFO: [APUAPC] D11_APC_2: 0x3fffff
10018 12:12:04.299239 INFO: [APUAPC] D11_APC_3: 0x0
10019 12:12:04.302436 INFO: [APUAPC] D12_APC_0: 0xffffffff
10020 12:12:04.306269 INFO: [APUAPC] D12_APC_1: 0xffffffff
10021 12:12:04.309512 INFO: [APUAPC] D12_APC_2: 0x3fffff
10022 12:12:04.312783 INFO: [APUAPC] D12_APC_3: 0x0
10023 12:12:04.315868 INFO: [APUAPC] D13_APC_0: 0xffffffff
10024 12:12:04.319030 INFO: [APUAPC] D13_APC_1: 0xffffffff
10025 12:12:04.322198 INFO: [APUAPC] D13_APC_2: 0x3fffff
10026 12:12:04.326136 INFO: [APUAPC] D13_APC_3: 0x0
10027 12:12:04.328834 INFO: [APUAPC] D14_APC_0: 0xffffffff
10028 12:12:04.332467 INFO: [APUAPC] D14_APC_1: 0xffffffff
10029 12:12:04.335584 INFO: [APUAPC] D14_APC_2: 0x3fffff
10030 12:12:04.339346 INFO: [APUAPC] D14_APC_3: 0x0
10031 12:12:04.342544 INFO: [APUAPC] D15_APC_0: 0xffffffff
10032 12:12:04.345706 INFO: [APUAPC] D15_APC_1: 0xffffffff
10033 12:12:04.348867 INFO: [APUAPC] D15_APC_2: 0x3fffff
10034 12:12:04.352086 INFO: [APUAPC] D15_APC_3: 0x0
10035 12:12:04.355373 INFO: [APUAPC] APC_CON: 0x4
10036 12:12:04.358613 INFO: [NOCDAPC] D0_APC_0: 0x0
10037 12:12:04.361870 INFO: [NOCDAPC] D0_APC_1: 0x0
10038 12:12:04.365175 INFO: [NOCDAPC] D1_APC_0: 0x0
10039 12:12:04.365284 INFO: [NOCDAPC] D1_APC_1: 0xfff
10040 12:12:04.368354 INFO: [NOCDAPC] D2_APC_0: 0x0
10041 12:12:04.372206 INFO: [NOCDAPC] D2_APC_1: 0xfff
10042 12:12:04.375370 INFO: [NOCDAPC] D3_APC_0: 0x0
10043 12:12:04.378463 INFO: [NOCDAPC] D3_APC_1: 0xfff
10044 12:12:04.381624 INFO: [NOCDAPC] D4_APC_0: 0x0
10045 12:12:04.385430 INFO: [NOCDAPC] D4_APC_1: 0xfff
10046 12:12:04.388538 INFO: [NOCDAPC] D5_APC_0: 0x0
10047 12:12:04.391657 INFO: [NOCDAPC] D5_APC_1: 0xfff
10048 12:12:04.394698 INFO: [NOCDAPC] D6_APC_0: 0x0
10049 12:12:04.398475 INFO: [NOCDAPC] D6_APC_1: 0xfff
10050 12:12:04.401604 INFO: [NOCDAPC] D7_APC_0: 0x0
10051 12:12:04.401727 INFO: [NOCDAPC] D7_APC_1: 0xfff
10052 12:12:04.404808 INFO: [NOCDAPC] D8_APC_0: 0x0
10053 12:12:04.408000 INFO: [NOCDAPC] D8_APC_1: 0xfff
10054 12:12:04.411211 INFO: [NOCDAPC] D9_APC_0: 0x0
10055 12:12:04.415007 INFO: [NOCDAPC] D9_APC_1: 0xfff
10056 12:12:04.418241 INFO: [NOCDAPC] D10_APC_0: 0x0
10057 12:12:04.421339 INFO: [NOCDAPC] D10_APC_1: 0xfff
10058 12:12:04.424434 INFO: [NOCDAPC] D11_APC_0: 0x0
10059 12:12:04.427711 INFO: [NOCDAPC] D11_APC_1: 0xfff
10060 12:12:04.431515 INFO: [NOCDAPC] D12_APC_0: 0x0
10061 12:12:04.434655 INFO: [NOCDAPC] D12_APC_1: 0xfff
10062 12:12:04.437760 INFO: [NOCDAPC] D13_APC_0: 0x0
10063 12:12:04.441420 INFO: [NOCDAPC] D13_APC_1: 0xfff
10064 12:12:04.444768 INFO: [NOCDAPC] D14_APC_0: 0x0
10065 12:12:04.444879 INFO: [NOCDAPC] D14_APC_1: 0xfff
10066 12:12:04.447916 INFO: [NOCDAPC] D15_APC_0: 0x0
10067 12:12:04.451039 INFO: [NOCDAPC] D15_APC_1: 0xfff
10068 12:12:04.454279 INFO: [NOCDAPC] APC_CON: 0x4
10069 12:12:04.457542 INFO: [APUAPC] set_apusys_apc done
10070 12:12:04.460830 INFO: [DEVAPC] devapc_init done
10071 12:12:04.464587 INFO: GICv3 without legacy support detected.
10072 12:12:04.470806 INFO: ARM GICv3 driver initialized in EL3
10073 12:12:04.474044 INFO: Maximum SPI INTID supported: 639
10074 12:12:04.477249 INFO: BL31: Initializing runtime services
10075 12:12:04.484395 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10076 12:12:04.487652 INFO: SPM: enable CPC mode
10077 12:12:04.490833 INFO: mcdi ready for mcusys-off-idle and system suspend
10078 12:12:04.497152 INFO: BL31: Preparing for EL3 exit to normal world
10079 12:12:04.500354 INFO: Entry point address = 0x80000000
10080 12:12:04.500460 INFO: SPSR = 0x8
10081 12:12:04.507221
10082 12:12:04.507307
10083 12:12:04.507373
10084 12:12:04.510503 Starting depthcharge on Spherion...
10085 12:12:04.510587
10086 12:12:04.510661 Wipe memory regions:
10087 12:12:04.510724
10088 12:12:04.511347 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10089 12:12:04.511450 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10090 12:12:04.511540 Setting prompt string to ['asurada:']
10091 12:12:04.511624 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10092 12:12:04.513742 [0x00000040000000, 0x00000054600000)
10093 12:12:04.636356
10094 12:12:04.636561 [0x00000054660000, 0x00000080000000)
10095 12:12:04.897036
10096 12:12:04.897184 [0x000000821a7280, 0x000000ffe64000)
10097 12:12:05.641959
10098 12:12:05.642144 [0x00000100000000, 0x00000240000000)
10099 12:12:07.532392
10100 12:12:07.535413 Initializing XHCI USB controller at 0x11200000.
10101 12:12:08.517287
10102 12:12:08.517462 R8152: Initializing
10103 12:12:08.517540
10104 12:12:08.520322 Version 9 (ocp_data = 6010)
10105 12:12:08.520448
10106 12:12:08.523357 R8152: Done initializing
10107 12:12:08.523466
10108 12:12:08.523561 Adding net device
10109 12:12:09.044843
10110 12:12:09.047950 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10111 12:12:09.048076
10112 12:12:09.048191
10113 12:12:09.048299
10114 12:12:09.048598 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10116 12:12:09.148996 asurada: tftpboot 192.168.201.1 10605392/tftp-deploy-bmp9s55c/kernel/image.itb 10605392/tftp-deploy-bmp9s55c/kernel/cmdline
10117 12:12:09.149212 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 12:12:09.149349 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10119 12:12:09.153532 tftpboot 192.168.201.1 10605392/tftp-deploy-bmp9s55c/kernel/image.ittp-deploy-bmp9s55c/kernel/cmdline
10120 12:12:09.153651
10121 12:12:09.153747 Waiting for link
10122 12:12:09.356090
10123 12:12:09.356287 done.
10124 12:12:09.356392
10125 12:12:09.356502 MAC: f4:f5:e8:50:de:0a
10126 12:12:09.356604
10127 12:12:09.359358 Sending DHCP discover... done.
10128 12:12:09.359467
10129 12:12:09.362474 Waiting for reply... done.
10130 12:12:09.362613
10131 12:12:09.365532 Sending DHCP request... done.
10132 12:12:09.365642
10133 12:12:09.369335 Waiting for reply... done.
10134 12:12:09.369432
10135 12:12:09.369522 My ip is 192.168.201.14
10136 12:12:09.369611
10137 12:12:09.372592 The DHCP server ip is 192.168.201.1
10138 12:12:09.372662
10139 12:12:09.378955 TFTP server IP predefined by user: 192.168.201.1
10140 12:12:09.379067
10141 12:12:09.386020 Bootfile predefined by user: 10605392/tftp-deploy-bmp9s55c/kernel/image.itb
10142 12:12:09.386136
10143 12:12:09.389254 Sending tftp read request... done.
10144 12:12:09.389380
10145 12:12:09.392406 Waiting for the transfer...
10146 12:12:09.392507
10147 12:12:09.623992 00000000 ################################################################
10148 12:12:09.624193
10149 12:12:09.853185 00080000 ################################################################
10150 12:12:09.853362
10151 12:12:10.086324 00100000 ################################################################
10152 12:12:10.086521
10153 12:12:10.319290 00180000 ################################################################
10154 12:12:10.319476
10155 12:12:10.570740 00200000 ################################################################
10156 12:12:10.570922
10157 12:12:10.839438 00280000 ################################################################
10158 12:12:10.839610
10159 12:12:11.069780 00300000 ################################################################
10160 12:12:11.069961
10161 12:12:11.295408 00380000 ################################################################
10162 12:12:11.295573
10163 12:12:11.600273 00400000 ################################################################
10164 12:12:11.600455
10165 12:12:11.849485 00480000 ################################################################
10166 12:12:11.849640
10167 12:12:12.099772 00500000 ################################################################
10168 12:12:12.099980
10169 12:12:12.340406 00580000 ################################################################
10170 12:12:12.340583
10171 12:12:12.601106 00600000 ################################################################
10172 12:12:12.601265
10173 12:12:12.862790 00680000 ################################################################
10174 12:12:12.862958
10175 12:12:13.110439 00700000 ################################################################
10176 12:12:13.110594
10177 12:12:13.363007 00780000 ################################################################
10178 12:12:13.363162
10179 12:12:13.608260 00800000 ################################################################
10180 12:12:13.608425
10181 12:12:13.900019 00880000 ################################################################
10182 12:12:13.900169
10183 12:12:14.156380 00900000 ################################################################
10184 12:12:14.156556
10185 12:12:14.407237 00980000 ################################################################
10186 12:12:14.407403
10187 12:12:14.652405 00a00000 ################################################################
10188 12:12:14.652570
10189 12:12:14.907124 00a80000 ################################################################
10190 12:12:14.907268
10191 12:12:15.155685 00b00000 ################################################################
10192 12:12:15.155818
10193 12:12:15.416423 00b80000 ################################################################
10194 12:12:15.416629
10195 12:12:15.683455 00c00000 ################################################################
10196 12:12:15.683620
10197 12:12:15.991768 00c80000 ################################################################
10198 12:12:15.991916
10199 12:12:16.262880 00d00000 ################################################################
10200 12:12:16.263060
10201 12:12:16.541141 00d80000 ################################################################
10202 12:12:16.541320
10203 12:12:16.811133 00e00000 ################################################################
10204 12:12:16.811286
10205 12:12:17.086679 00e80000 ################################################################
10206 12:12:17.086825
10207 12:12:17.359411 00f00000 ################################################################
10208 12:12:17.359561
10209 12:12:17.682832 00f80000 ################################################################
10210 12:12:17.683011
10211 12:12:17.957789 01000000 ################################################################
10212 12:12:17.957959
10213 12:12:18.227079 01080000 ################################################################
10214 12:12:18.227257
10215 12:12:18.506689 01100000 ################################################################
10216 12:12:18.506888
10217 12:12:18.777899 01180000 ################################################################
10218 12:12:18.778076
10219 12:12:19.045969 01200000 ################################################################
10220 12:12:19.046131
10221 12:12:19.312753 01280000 ################################################################
10222 12:12:19.312914
10223 12:12:19.585849 01300000 ################################################################
10224 12:12:19.586033
10225 12:12:19.855400 01380000 ################################################################
10226 12:12:19.855575
10227 12:12:20.127089 01400000 ################################################################
10228 12:12:20.127273
10229 12:12:20.403016 01480000 ################################################################
10230 12:12:20.403213
10231 12:12:20.672548 01500000 ################################################################
10232 12:12:20.672694
10233 12:12:20.953559 01580000 ################################################################
10234 12:12:20.953710
10235 12:12:21.228201 01600000 ################################################################
10236 12:12:21.228393
10237 12:12:21.495584 01680000 ################################################################
10238 12:12:21.495752
10239 12:12:21.759439 01700000 ################################################################
10240 12:12:21.759596
10241 12:12:22.018320 01780000 ################################################################
10242 12:12:22.018471
10243 12:12:22.280699 01800000 ################################################################
10244 12:12:22.280848
10245 12:12:22.582743 01880000 ################################################################
10246 12:12:22.582975
10247 12:12:22.844091 01900000 ################################################################
10248 12:12:22.844252
10249 12:12:23.104782 01980000 ################################################################
10250 12:12:23.104967
10251 12:12:23.352891 01a00000 ################################################################
10252 12:12:23.353039
10253 12:12:23.353111 01a80000 # done.
10254 12:12:23.353176
10255 12:12:23.356231 The bootfile was 27789770 bytes long.
10256 12:12:23.356307
10257 12:12:23.359409 Sending tftp read request... done.
10258 12:12:23.359489
10259 12:12:23.362568 Waiting for the transfer...
10260 12:12:23.362669
10261 12:12:23.362740 00000000 # done.
10262 12:12:23.365841
10263 12:12:23.372213 Command line loaded dynamically from TFTP file: 10605392/tftp-deploy-bmp9s55c/kernel/cmdline
10264 12:12:23.372324
10265 12:12:23.392023 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10266 12:12:23.392147
10267 12:12:23.392244 Loading FIT.
10268 12:12:23.392338
10269 12:12:23.395768 Image ramdisk-1 has 17646190 bytes.
10270 12:12:23.395870
10271 12:12:23.398931 Image fdt-1 has 46924 bytes.
10272 12:12:23.399008
10273 12:12:23.402231 Image kernel-1 has 10094623 bytes.
10274 12:12:23.402311
10275 12:12:23.412432 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10276 12:12:23.412553
10277 12:12:23.428949 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10278 12:12:23.429059
10279 12:12:23.435099 Choosing best match conf-1 for compat google,spherion-rev2.
10280 12:12:23.435184
10281 12:12:23.442252 Connected to device vid:did:rid of 1ae0:0028:00
10282 12:12:23.449810
10283 12:12:23.453090 tpm_get_response: command 0x17b, return code 0x0
10284 12:12:23.453174
10285 12:12:23.456378 ec_init: CrosEC protocol v3 supported (256, 248)
10286 12:12:23.460287
10287 12:12:23.463493 tpm_cleanup: add release locality here.
10288 12:12:23.463576
10289 12:12:23.463642 Shutting down all USB controllers.
10290 12:12:23.466704
10291 12:12:23.466786 Removing current net device
10292 12:12:23.466852
10293 12:12:23.473675 Exiting depthcharge with code 4 at timestamp: 48322434
10294 12:12:23.473759
10295 12:12:23.476757 LZMA decompressing kernel-1 to 0x821a6718
10296 12:12:23.476841
10297 12:12:23.479975 LZMA decompressing kernel-1 to 0x40000000
10298 12:12:24.748613
10299 12:12:24.748766 jumping to kernel
10300 12:12:24.749182 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
10301 12:12:24.749285 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
10302 12:12:24.749364 Setting prompt string to ['Linux version [0-9]']
10303 12:12:24.749433 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10304 12:12:24.749501 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10305 12:12:24.830119
10306 12:12:24.833270 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10307 12:12:24.837344 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10308 12:12:24.837439 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10309 12:12:24.837522 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10310 12:12:24.837711 Using line separator: #'\n'#
10311 12:12:24.837831 No login prompt set.
10312 12:12:24.837938 Parsing kernel messages
10313 12:12:24.838023 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10314 12:12:24.838194 [login-action] Waiting for messages, (timeout 00:04:05)
10315 12:12:24.856461 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10316 12:12:24.859712 [ 0.000000] random: crng init done
10317 12:12:24.862960 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10318 12:12:24.866833 [ 0.000000] efi: UEFI not found.
10319 12:12:24.876408 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10320 12:12:24.882876 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10321 12:12:24.893147 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10322 12:12:24.902775 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10323 12:12:24.909280 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10324 12:12:24.915759 [ 0.000000] printk: bootconsole [mtk8250] enabled
10325 12:12:24.922840 [ 0.000000] NUMA: No NUMA configuration found
10326 12:12:24.928783 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10327 12:12:24.932077 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10328 12:12:24.935313 [ 0.000000] Zone ranges:
10329 12:12:24.942207 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10330 12:12:24.945427 [ 0.000000] DMA32 empty
10331 12:12:24.952321 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10332 12:12:24.955351 [ 0.000000] Movable zone start for each node
10333 12:12:24.958541 [ 0.000000] Early memory node ranges
10334 12:12:24.964954 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10335 12:12:24.972060 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10336 12:12:24.978438 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10337 12:12:24.985376 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10338 12:12:24.991945 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10339 12:12:24.998272 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10340 12:12:25.054439 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10341 12:12:25.060780 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10342 12:12:25.067730 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10343 12:12:25.070854 [ 0.000000] psci: probing for conduit method from DT.
10344 12:12:25.077302 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10345 12:12:25.080475 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10346 12:12:25.087058 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10347 12:12:25.090192 [ 0.000000] psci: SMC Calling Convention v1.2
10348 12:12:25.096854 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10349 12:12:25.100500 [ 0.000000] Detected VIPT I-cache on CPU0
10350 12:12:25.106805 [ 0.000000] CPU features: detected: GIC system register CPU interface
10351 12:12:25.113369 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10352 12:12:25.120074 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10353 12:12:25.126596 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10354 12:12:25.136850 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10355 12:12:25.143517 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10356 12:12:25.146853 [ 0.000000] alternatives: applying boot alternatives
10357 12:12:25.153074 [ 0.000000] Fallback order for Node 0: 0
10358 12:12:25.160133 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10359 12:12:25.163339 [ 0.000000] Policy zone: Normal
10360 12:12:25.182789 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10361 12:12:25.192413 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10362 12:12:25.203995 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10363 12:12:25.213577 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10364 12:12:25.220071 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10365 12:12:25.223603 <6>[ 0.000000] software IO TLB: area num 8.
10366 12:12:25.280011 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10367 12:12:25.429579 <6>[ 0.000000] Memory: 7955708K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397060K reserved, 32768K cma-reserved)
10368 12:12:25.436538 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10369 12:12:25.442812 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10370 12:12:25.446097 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10371 12:12:25.452579 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10372 12:12:25.459574 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10373 12:12:25.462887 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10374 12:12:25.472200 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10375 12:12:25.479016 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10376 12:12:25.485685 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10377 12:12:25.492149 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10378 12:12:25.495329 <6>[ 0.000000] GICv3: 608 SPIs implemented
10379 12:12:25.498565 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10380 12:12:25.505471 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10381 12:12:25.508747 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10382 12:12:25.515172 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10383 12:12:25.528627 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10384 12:12:25.541713 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10385 12:12:25.548148 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10386 12:12:25.556190 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10387 12:12:25.569490 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10388 12:12:25.576029 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10389 12:12:25.583014 <6>[ 0.009223] Console: colour dummy device 80x25
10390 12:12:25.592786 <6>[ 0.013948] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10391 12:12:25.599769 <6>[ 0.024391] pid_max: default: 32768 minimum: 301
10392 12:12:25.602917 <6>[ 0.029264] LSM: Security Framework initializing
10393 12:12:25.609401 <6>[ 0.034204] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10394 12:12:25.619184 <6>[ 0.042066] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 12:12:25.629197 <6>[ 0.051495] cblist_init_generic: Setting adjustable number of callback queues.
10396 12:12:25.632417 <6>[ 0.058950] cblist_init_generic: Setting shift to 3 and lim to 1.
10397 12:12:25.639131 <6>[ 0.065288] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 12:12:25.646109 <6>[ 0.071695] rcu: Hierarchical SRCU implementation.
10399 12:12:25.652500 <6>[ 0.076708] rcu: Max phase no-delay instances is 1000.
10400 12:12:25.658539 <6>[ 0.083760] EFI services will not be available.
10401 12:12:25.661887 <6>[ 0.088758] smp: Bringing up secondary CPUs ...
10402 12:12:25.669726 <6>[ 0.093808] Detected VIPT I-cache on CPU1
10403 12:12:25.676729 <6>[ 0.093880] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10404 12:12:25.683141 <6>[ 0.093910] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10405 12:12:25.686311 <6>[ 0.094238] Detected VIPT I-cache on CPU2
10406 12:12:25.696324 <6>[ 0.094286] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10407 12:12:25.702764 <6>[ 0.094301] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10408 12:12:25.706122 <6>[ 0.094556] Detected VIPT I-cache on CPU3
10409 12:12:25.712357 <6>[ 0.094603] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10410 12:12:25.718863 <6>[ 0.094616] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10411 12:12:25.725965 <6>[ 0.094922] CPU features: detected: Spectre-v4
10412 12:12:25.729025 <6>[ 0.094929] CPU features: detected: Spectre-BHB
10413 12:12:25.732864 <6>[ 0.094935] Detected PIPT I-cache on CPU4
10414 12:12:25.739255 <6>[ 0.094991] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10415 12:12:25.745371 <6>[ 0.095008] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10416 12:12:25.752288 <6>[ 0.095299] Detected PIPT I-cache on CPU5
10417 12:12:25.758643 <6>[ 0.095361] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10418 12:12:25.765639 <6>[ 0.095377] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10419 12:12:25.768892 <6>[ 0.095657] Detected PIPT I-cache on CPU6
10420 12:12:25.775276 <6>[ 0.095723] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10421 12:12:25.782289 <6>[ 0.095740] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10422 12:12:25.788677 <6>[ 0.096024] Detected PIPT I-cache on CPU7
10423 12:12:25.795384 <6>[ 0.096082] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10424 12:12:25.802004 <6>[ 0.096098] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10425 12:12:25.804721 <6>[ 0.096144] smp: Brought up 1 node, 8 CPUs
10426 12:12:25.811890 <6>[ 0.237433] SMP: Total of 8 processors activated.
10427 12:12:25.815143 <6>[ 0.242354] CPU features: detected: 32-bit EL0 Support
10428 12:12:25.824798 <6>[ 0.247751] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10429 12:12:25.831058 <6>[ 0.256605] CPU features: detected: Common not Private translations
10430 12:12:25.837848 <6>[ 0.263081] CPU features: detected: CRC32 instructions
10431 12:12:25.844195 <6>[ 0.268466] CPU features: detected: RCpc load-acquire (LDAPR)
10432 12:12:25.847980 <6>[ 0.274463] CPU features: detected: LSE atomic instructions
10433 12:12:25.854173 <6>[ 0.280244] CPU features: detected: Privileged Access Never
10434 12:12:25.860728 <6>[ 0.286024] CPU features: detected: RAS Extension Support
10435 12:12:25.867643 <6>[ 0.291633] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10436 12:12:25.870869 <6>[ 0.298855] CPU: All CPU(s) started at EL2
10437 12:12:25.877367 <6>[ 0.303171] alternatives: applying system-wide alternatives
10438 12:12:25.887405 <6>[ 0.313862] devtmpfs: initialized
10439 12:12:25.900145 <6>[ 0.322709] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10440 12:12:25.909562 <6>[ 0.332667] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10441 12:12:25.916615 <6>[ 0.340888] pinctrl core: initialized pinctrl subsystem
10442 12:12:25.919957 <6>[ 0.347508] DMI not present or invalid.
10443 12:12:25.926505 <6>[ 0.351920] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10444 12:12:25.936202 <6>[ 0.358808] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10445 12:12:25.942713 <6>[ 0.366390] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10446 12:12:25.952600 <6>[ 0.374617] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10447 12:12:25.955676 <6>[ 0.382862] audit: initializing netlink subsys (disabled)
10448 12:12:25.965895 <5>[ 0.388555] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10449 12:12:25.972236 <6>[ 0.389266] thermal_sys: Registered thermal governor 'step_wise'
10450 12:12:25.978741 <6>[ 0.396523] thermal_sys: Registered thermal governor 'power_allocator'
10451 12:12:25.981926 <6>[ 0.402774] cpuidle: using governor menu
10452 12:12:25.988413 <6>[ 0.413735] NET: Registered PF_QIPCRTR protocol family
10453 12:12:25.995190 <6>[ 0.419248] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10454 12:12:26.002117 <6>[ 0.426354] ASID allocator initialised with 32768 entries
10455 12:12:26.005245 <6>[ 0.432915] Serial: AMBA PL011 UART driver
10456 12:12:26.015480 <4>[ 0.441601] Trying to register duplicate clock ID: 134
10457 12:12:26.068750 <6>[ 0.498520] KASLR enabled
10458 12:12:26.083308 <6>[ 0.506265] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10459 12:12:26.089726 <6>[ 0.513275] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10460 12:12:26.096126 <6>[ 0.519765] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10461 12:12:26.103088 <6>[ 0.526771] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10462 12:12:26.109310 <6>[ 0.533259] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10463 12:12:26.116196 <6>[ 0.540263] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10464 12:12:26.122720 <6>[ 0.546751] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10465 12:12:26.129333 <6>[ 0.553755] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10466 12:12:26.132548 <6>[ 0.561272] ACPI: Interpreter disabled.
10467 12:12:26.141014 <6>[ 0.567651] iommu: Default domain type: Translated
10468 12:12:26.148185 <6>[ 0.572763] iommu: DMA domain TLB invalidation policy: strict mode
10469 12:12:26.151418 <5>[ 0.579422] SCSI subsystem initialized
10470 12:12:26.157766 <6>[ 0.583587] usbcore: registered new interface driver usbfs
10471 12:12:26.164478 <6>[ 0.589317] usbcore: registered new interface driver hub
10472 12:12:26.167609 <6>[ 0.594870] usbcore: registered new device driver usb
10473 12:12:26.174664 <6>[ 0.600948] pps_core: LinuxPPS API ver. 1 registered
10474 12:12:26.184389 <6>[ 0.606142] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10475 12:12:26.187548 <6>[ 0.615491] PTP clock support registered
10476 12:12:26.190796 <6>[ 0.619733] EDAC MC: Ver: 3.0.0
10477 12:12:26.198664 <6>[ 0.624870] FPGA manager framework
10478 12:12:26.204902 <6>[ 0.628550] Advanced Linux Sound Architecture Driver Initialized.
10479 12:12:26.208718 <6>[ 0.635317] vgaarb: loaded
10480 12:12:26.214905 <6>[ 0.638501] clocksource: Switched to clocksource arch_sys_counter
10481 12:12:26.217992 <5>[ 0.644936] VFS: Disk quotas dquot_6.6.0
10482 12:12:26.224989 <6>[ 0.649117] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10483 12:12:26.228280 <6>[ 0.656309] pnp: PnP ACPI: disabled
10484 12:12:26.236748 <6>[ 0.663025] NET: Registered PF_INET protocol family
10485 12:12:26.246131 <6>[ 0.668607] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10486 12:12:26.258039 <6>[ 0.680912] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10487 12:12:26.267656 <6>[ 0.689724] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10488 12:12:26.274320 <6>[ 0.697694] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10489 12:12:26.284429 <6>[ 0.706395] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10490 12:12:26.291081 <6>[ 0.716123] TCP: Hash tables configured (established 65536 bind 65536)
10491 12:12:26.297429 <6>[ 0.722973] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10492 12:12:26.307036 <6>[ 0.730169] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 12:12:26.314011 <6>[ 0.737869] NET: Registered PF_UNIX/PF_LOCAL protocol family
10494 12:12:26.320211 <6>[ 0.744038] RPC: Registered named UNIX socket transport module.
10495 12:12:26.324027 <6>[ 0.750192] RPC: Registered udp transport module.
10496 12:12:26.327235 <6>[ 0.755122] RPC: Registered tcp transport module.
10497 12:12:26.336840 <6>[ 0.760053] RPC: Registered tcp NFSv4.1 backchannel transport module.
10498 12:12:26.340467 <6>[ 0.766726] PCI: CLS 0 bytes, default 64
10499 12:12:26.343737 <6>[ 0.771071] Unpacking initramfs...
10500 12:12:26.360297 <6>[ 0.783076] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10501 12:12:26.369901 <6>[ 0.791720] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10502 12:12:26.373066 <6>[ 0.800559] kvm [1]: IPA Size Limit: 40 bits
10503 12:12:26.379718 <6>[ 0.805084] kvm [1]: GICv3: no GICV resource entry
10504 12:12:26.383362 <6>[ 0.810102] kvm [1]: disabling GICv2 emulation
10505 12:12:26.390044 <6>[ 0.814787] kvm [1]: GIC system register CPU interface enabled
10506 12:12:26.393183 <6>[ 0.820944] kvm [1]: vgic interrupt IRQ18
10507 12:12:26.400289 <6>[ 0.826601] kvm [1]: VHE mode initialized successfully
10508 12:12:26.406776 <5>[ 0.832976] Initialise system trusted keyrings
10509 12:12:26.413635 <6>[ 0.837813] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10510 12:12:26.421739 <6>[ 0.847838] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10511 12:12:26.428012 <5>[ 0.854242] NFS: Registering the id_resolver key type
10512 12:12:26.431308 <5>[ 0.859556] Key type id_resolver registered
10513 12:12:26.437634 <5>[ 0.863971] Key type id_legacy registered
10514 12:12:26.444239 <6>[ 0.868252] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10515 12:12:26.451340 <6>[ 0.875175] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10516 12:12:26.457469 <6>[ 0.882936] 9p: Installing v9fs 9p2000 file system support
10517 12:12:26.494771 <5>[ 0.920912] Key type asymmetric registered
10518 12:12:26.497935 <5>[ 0.925245] Asymmetric key parser 'x509' registered
10519 12:12:26.507593 <6>[ 0.930391] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10520 12:12:26.510747 <6>[ 0.938009] io scheduler mq-deadline registered
10521 12:12:26.514618 <6>[ 0.942769] io scheduler kyber registered
10522 12:12:26.533179 <6>[ 0.959632] EINJ: ACPI disabled.
10523 12:12:26.564841 <4>[ 0.984708] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 12:12:26.574522 <4>[ 0.995360] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 12:12:26.589569 <6>[ 1.016171] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10526 12:12:26.597857 <6>[ 1.024159] printk: console [ttyS0] disabled
10527 12:12:26.625987 <6>[ 1.048808] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10528 12:12:26.632369 <6>[ 1.058283] printk: console [ttyS0] enabled
10529 12:12:26.635548 <6>[ 1.058283] printk: console [ttyS0] enabled
10530 12:12:26.642038 <6>[ 1.067179] printk: bootconsole [mtk8250] disabled
10531 12:12:26.645865 <6>[ 1.067179] printk: bootconsole [mtk8250] disabled
10532 12:12:26.652453 <6>[ 1.078382] SuperH (H)SCI(F) driver initialized
10533 12:12:26.655157 <6>[ 1.083642] msm_serial: driver initialized
10534 12:12:26.669309 <6>[ 1.092497] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10535 12:12:26.679467 <6>[ 1.101044] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10536 12:12:26.686088 <6>[ 1.109585] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10537 12:12:26.695486 <6>[ 1.118212] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10538 12:12:26.705906 <6>[ 1.126918] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10539 12:12:26.712355 <6>[ 1.135639] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10540 12:12:26.722039 <6>[ 1.144180] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10541 12:12:26.729227 <6>[ 1.152987] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10542 12:12:26.738589 <6>[ 1.161532] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10543 12:12:26.750429 <6>[ 1.177047] loop: module loaded
10544 12:12:26.756939 <6>[ 1.183158] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10545 12:12:26.779999 <4>[ 1.206560] mtk-pmic-keys: Failed to locate of_node [id: -1]
10546 12:12:26.787202 <6>[ 1.213357] megasas: 07.719.03.00-rc1
10547 12:12:26.796473 <6>[ 1.222941] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10548 12:12:26.807511 <6>[ 1.233887] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10549 12:12:26.824084 <6>[ 1.250378] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10550 12:12:26.884032 <6>[ 1.304170] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10551 12:12:27.074228 <6>[ 1.500708] Freeing initrd memory: 17228K
10552 12:12:27.085020 <6>[ 1.511121] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10553 12:12:27.095202 <6>[ 1.521622] tun: Universal TUN/TAP device driver, 1.6
10554 12:12:27.098328 <6>[ 1.527667] thunder_xcv, ver 1.0
10555 12:12:27.101570 <6>[ 1.531173] thunder_bgx, ver 1.0
10556 12:12:27.104875 <6>[ 1.534669] nicpf, ver 1.0
10557 12:12:27.115829 <6>[ 1.538682] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10558 12:12:27.118904 <6>[ 1.546159] hns3: Copyright (c) 2017 Huawei Corporation.
10559 12:12:27.122142 <6>[ 1.551748] hclge is initializing
10560 12:12:27.129255 <6>[ 1.555324] e1000: Intel(R) PRO/1000 Network Driver
10561 12:12:27.135802 <6>[ 1.560453] e1000: Copyright (c) 1999-2006 Intel Corporation.
10562 12:12:27.138997 <6>[ 1.566465] e1000e: Intel(R) PRO/1000 Network Driver
10563 12:12:27.145623 <6>[ 1.571680] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10564 12:12:27.151941 <6>[ 1.577864] igb: Intel(R) Gigabit Ethernet Network Driver
10565 12:12:27.158948 <6>[ 1.583514] igb: Copyright (c) 2007-2014 Intel Corporation.
10566 12:12:27.165373 <6>[ 1.589349] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10567 12:12:27.171853 <6>[ 1.595866] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10568 12:12:27.175095 <6>[ 1.602325] sky2: driver version 1.30
10569 12:12:27.182234 <6>[ 1.607301] VFIO - User Level meta-driver version: 0.3
10570 12:12:27.189142 <6>[ 1.615480] usbcore: registered new interface driver usb-storage
10571 12:12:27.195525 <6>[ 1.621925] usbcore: registered new device driver onboard-usb-hub
10572 12:12:27.204500 <6>[ 1.631005] mt6397-rtc mt6359-rtc: registered as rtc0
10573 12:12:27.214646 <6>[ 1.636479] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:12:32 UTC (1686053552)
10574 12:12:27.217908 <6>[ 1.646054] i2c_dev: i2c /dev entries driver
10575 12:12:27.234253 <6>[ 1.657628] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10576 12:12:27.241200 <6>[ 1.667807] sdhci: Secure Digital Host Controller Interface driver
10577 12:12:27.247768 <6>[ 1.674244] sdhci: Copyright(c) Pierre Ossman
10578 12:12:27.254804 <6>[ 1.679635] Synopsys Designware Multimedia Card Interface Driver
10579 12:12:27.257936 <6>[ 1.686236] mmc0: CQHCI version 5.10
10580 12:12:27.264273 <6>[ 1.686787] sdhci-pltfm: SDHCI platform and OF driver helper
10581 12:12:27.272056 <6>[ 1.698289] ledtrig-cpu: registered to indicate activity on CPUs
10582 12:12:27.282499 <6>[ 1.705558] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10583 12:12:27.288846 <6>[ 1.712973] usbcore: registered new interface driver usbhid
10584 12:12:27.291942 <6>[ 1.718806] usbhid: USB HID core driver
10585 12:12:27.298404 <6>[ 1.723064] spi_master spi0: will run message pump with realtime priority
10586 12:12:27.346002 <6>[ 1.765929] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10587 12:12:27.364910 <6>[ 1.781185] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10588 12:12:27.368215 <6>[ 1.794762] mmc0: Command Queue Engine enabled
10589 12:12:27.375129 <6>[ 1.796966] cros-ec-spi spi0.0: Chrome EC device registered
10590 12:12:27.381775 <6>[ 1.799509] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10591 12:12:27.385076 <6>[ 1.812630] mmcblk0: mmc0:0001 DA4128 116 GiB
10592 12:12:27.399602 <6>[ 1.822742] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10593 12:12:27.405980 <6>[ 1.826459] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10594 12:12:27.413067 <6>[ 1.834219] NET: Registered PF_PACKET protocol family
10595 12:12:27.416364 <6>[ 1.838957] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10596 12:12:27.422650 <6>[ 1.843404] 9pnet: Installing 9P2000 support
10597 12:12:27.425761 <6>[ 1.849122] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10598 12:12:27.432531 <5>[ 1.853073] Key type dns_resolver registered
10599 12:12:27.439031 <6>[ 1.858953] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10600 12:12:27.442943 <6>[ 1.863394] registered taskstats version 1
10601 12:12:27.446156 <5>[ 1.873697] Loading compiled-in X.509 certificates
10602 12:12:27.480477 <4>[ 1.900529] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 12:12:27.490809 <4>[ 1.911214] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 12:12:27.500879 <3>[ 1.923920] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10605 12:12:27.512761 <6>[ 1.939385] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10606 12:12:27.519748 <6>[ 1.946199] xhci-mtk 11200000.usb: xHCI Host Controller
10607 12:12:27.529295 <6>[ 1.951720] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10608 12:12:27.536131 <6>[ 1.959584] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10609 12:12:27.542753 <6>[ 1.969022] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10610 12:12:27.549251 <6>[ 1.975227] xhci-mtk 11200000.usb: xHCI Host Controller
10611 12:12:27.555771 <6>[ 1.980723] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10612 12:12:27.562554 <6>[ 1.988390] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10613 12:12:27.570285 <6>[ 1.996270] hub 1-0:1.0: USB hub found
10614 12:12:27.573278 <6>[ 2.000309] hub 1-0:1.0: 1 port detected
10615 12:12:27.583367 <6>[ 2.004662] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10616 12:12:27.586709 <6>[ 2.013490] hub 2-0:1.0: USB hub found
10617 12:12:27.589886 <6>[ 2.017527] hub 2-0:1.0: 1 port detected
10618 12:12:27.598234 <6>[ 2.024617] mtk-msdc 11f70000.mmc: Got CD GPIO
10619 12:12:27.616761 <6>[ 2.039563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10620 12:12:27.623092 <6>[ 2.047593] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10621 12:12:27.632692 <4>[ 2.055563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10622 12:12:27.643089 <6>[ 2.065234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10623 12:12:27.649460 <6>[ 2.073316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10624 12:12:27.656113 <6>[ 2.081356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10625 12:12:27.665819 <6>[ 2.089270] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10626 12:12:27.672763 <6>[ 2.097091] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10627 12:12:27.682756 <6>[ 2.104912] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10628 12:12:27.692453 <6>[ 2.115684] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10629 12:12:27.702274 <6>[ 2.124057] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10630 12:12:27.709315 <6>[ 2.132402] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10631 12:12:27.718817 <6>[ 2.140745] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10632 12:12:27.725736 <6>[ 2.149089] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10633 12:12:27.735433 <6>[ 2.157431] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10634 12:12:27.742452 <6>[ 2.165775] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10635 12:12:27.752403 <6>[ 2.174118] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10636 12:12:27.759011 <6>[ 2.182461] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10637 12:12:27.768836 <6>[ 2.190805] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10638 12:12:27.775675 <6>[ 2.199149] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10639 12:12:27.785617 <6>[ 2.207492] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10640 12:12:27.792153 <6>[ 2.215836] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10641 12:12:27.801798 <6>[ 2.224181] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10642 12:12:27.808797 <6>[ 2.232528] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10643 12:12:27.815149 <6>[ 2.241367] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10644 12:12:27.822269 <6>[ 2.248797] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10645 12:12:27.829254 <6>[ 2.255809] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10646 12:12:27.839495 <6>[ 2.262901] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10647 12:12:27.846066 <6>[ 2.270160] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10648 12:12:27.856168 <6>[ 2.277121] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10649 12:12:27.862843 <6>[ 2.286289] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10650 12:12:27.872427 <6>[ 2.295416] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10651 12:12:27.882470 <6>[ 2.304717] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10652 12:12:27.892381 <6>[ 2.314192] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10653 12:12:27.902635 <6>[ 2.323666] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10654 12:12:27.912384 <6>[ 2.332793] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10655 12:12:27.919254 <6>[ 2.342266] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10656 12:12:27.928792 <6>[ 2.351393] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10657 12:12:27.938939 <6>[ 2.360695] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10658 12:12:27.948436 <6>[ 2.370861] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10659 12:12:27.958492 <6>[ 2.381755] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10660 12:12:27.964998 <6>[ 2.391463] Trying to probe devices needed for running init ...
10661 12:12:27.983434 <6>[ 2.406946] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10662 12:12:28.012489 <6>[ 2.438944] hub 2-1:1.0: USB hub found
10663 12:12:28.015793 <6>[ 2.443456] hub 2-1:1.0: 3 ports detected
10664 12:12:28.135130 <6>[ 2.558694] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10665 12:12:28.288249 <6>[ 2.714690] hub 1-1:1.0: USB hub found
10666 12:12:28.291417 <6>[ 2.719047] hub 1-1:1.0: 4 ports detected
10667 12:12:28.611353 <6>[ 3.034772] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10668 12:12:28.741974 <6>[ 3.168684] hub 1-1.1:1.0: USB hub found
10669 12:12:28.745091 <6>[ 3.172969] hub 1-1.1:1.0: 4 ports detected
10670 12:12:28.859346 <6>[ 3.282554] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10671 12:12:28.992443 <6>[ 3.418952] hub 1-1.4:1.0: USB hub found
10672 12:12:28.995640 <6>[ 3.423603] hub 1-1.4:1.0: 2 ports detected
10673 12:12:29.075684 <6>[ 3.498772] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10674 12:12:29.263417 <6>[ 3.686771] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10675 12:12:29.348413 <3>[ 3.774984] usb 1-1.1.4: device descriptor read/64, error -32
10676 12:12:29.540418 <3>[ 3.966980] usb 1-1.1.4: device descriptor read/64, error -32
10677 12:12:29.735481 <6>[ 4.158771] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10678 12:12:29.923455 <6>[ 4.346773] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10679 12:12:30.008113 <3>[ 4.434926] usb 1-1.1.4: device descriptor read/64, error -32
10680 12:12:30.200054 <3>[ 4.626991] usb 1-1.1.4: device descriptor read/64, error -32
10681 12:12:30.312111 <6>[ 4.739197] usb 1-1.1-port4: attempt power cycle
10682 12:12:30.398936 <6>[ 4.822770] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10683 12:12:30.922995 <6>[ 5.346772] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10684 12:12:30.929815 <4>[ 5.354293] usb 1-1.1.4: Device not responding to setup address.
10685 12:12:31.139896 <4>[ 5.567040] usb 1-1.1.4: Device not responding to setup address.
10686 12:12:31.351782 <3>[ 5.778765] usb 1-1.1.4: device not accepting address 10, error -71
10687 12:12:31.439462 <6>[ 5.862770] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10688 12:12:31.445461 <4>[ 5.870128] usb 1-1.1.4: Device not responding to setup address.
10689 12:12:31.655895 <4>[ 6.083036] usb 1-1.1.4: Device not responding to setup address.
10690 12:12:31.867485 <3>[ 6.294763] usb 1-1.1.4: device not accepting address 11, error -71
10691 12:12:31.874746 <3>[ 6.301710] usb 1-1.1-port4: unable to enumerate USB device
10692 12:12:40.235945 <6>[ 14.667384] ALSA device list:
10693 12:12:40.242331 <6>[ 14.670643] No soundcards found.
10694 12:12:40.255189 <6>[ 14.683051] Freeing unused kernel memory: 8384K
10695 12:12:40.258126 <6>[ 14.687984] Run /init as init process
10696 12:12:40.268707 Loading, please wait...
10697 12:12:40.287612 Starting version 247.3-7+deb11u2
10698 12:12:40.606959 <6>[ 15.031803] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10699 12:12:40.623282 <6>[ 15.051545] remoteproc remoteproc0: scp is available
10700 12:12:40.633620 <4>[ 15.057599] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10701 12:12:40.640337 <6>[ 15.067554] remoteproc remoteproc0: powering up scp
10702 12:12:40.649855 <4>[ 15.073266] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10703 12:12:40.656886 <3>[ 15.083255] remoteproc remoteproc0: request_firmware failed: -2
10704 12:12:40.663204 <6>[ 15.090020] mc: Linux media interface: v0.10
10705 12:12:40.669590 <6>[ 15.090332] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10706 12:12:40.676201 <6>[ 15.090671] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10707 12:12:40.686277 <6>[ 15.090699] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10708 12:12:40.692745 <6>[ 15.090709] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10709 12:12:40.699627 <6>[ 15.100717] usbcore: registered new interface driver r8152
10710 12:12:40.709107 <3>[ 15.103403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 12:12:40.716012 <3>[ 15.141111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 12:12:40.722631 <6>[ 15.144173] videodev: Linux video capture interface: v2.00
10713 12:12:40.729296 <3>[ 15.149300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 12:12:40.738773 <4>[ 15.157289] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10715 12:12:40.745566 <3>[ 15.163252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 12:12:40.751933 <4>[ 15.170767] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10717 12:12:40.762060 <3>[ 15.178572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 12:12:40.768392 <3>[ 15.194019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 12:12:40.778282 <3>[ 15.202151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 12:12:40.785066 <3>[ 15.210258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 12:12:40.791430 <6>[ 15.216031] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10722 12:12:40.801960 <3>[ 15.218396] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 12:12:40.808411 <6>[ 15.218974] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10724 12:12:40.814620 <6>[ 15.225218] pci_bus 0000:00: root bus resource [bus 00-ff]
10725 12:12:40.821568 <3>[ 15.233545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 12:12:40.828148 <6>[ 15.240585] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10727 12:12:40.837972 <3>[ 15.246337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 12:12:40.848217 <6>[ 15.254403] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10729 12:12:40.854722 <3>[ 15.261539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 12:12:40.861166 <6>[ 15.269635] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10731 12:12:40.867575 <3>[ 15.279569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 12:12:40.877990 <6>[ 15.287610] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10733 12:12:40.887860 <6>[ 15.288491] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10734 12:12:40.894225 <6>[ 15.288943] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10735 12:12:40.904241 <3>[ 15.293866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 12:12:40.914271 <6>[ 15.295262] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10737 12:12:40.917383 <6>[ 15.302029] pci 0000:00:00.0: supports D1 D2
10738 12:12:40.924324 <3>[ 15.309477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:12:40.930462 <6>[ 15.310054] usbcore: registered new interface driver cdc_ether
10740 12:12:40.937341 <6>[ 15.319581] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10741 12:12:40.944079 <6>[ 15.320557] Bluetooth: Core ver 2.22
10742 12:12:40.947102 <6>[ 15.320589] usbcore: registered new interface driver r8153_ecm
10743 12:12:40.953918 <6>[ 15.320645] NET: Registered PF_BLUETOOTH protocol family
10744 12:12:40.960116 <6>[ 15.320650] Bluetooth: HCI device and connection manager initialized
10745 12:12:40.967047 <6>[ 15.320677] Bluetooth: HCI socket layer initialized
10746 12:12:40.970218 <6>[ 15.320687] Bluetooth: L2CAP socket layer initialized
10747 12:12:40.976610 <6>[ 15.320703] Bluetooth: SCO socket layer initialized
10748 12:12:40.983802 <3>[ 15.328610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 12:12:40.993220 <6>[ 15.338753] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10750 12:12:41.000314 <3>[ 15.346012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 12:12:41.006675 <6>[ 15.350663] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10752 12:12:41.016798 <4>[ 15.353486] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10753 12:12:41.023150 <4>[ 15.353495] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10754 12:12:41.033306 <3>[ 15.358667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 12:12:41.039367 <6>[ 15.364730] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10756 12:12:41.046510 <6>[ 15.365698] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10757 12:12:41.052672 <6>[ 15.365860] usbcore: registered new interface driver btusb
10758 12:12:41.062812 <4>[ 15.366325] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10759 12:12:41.069064 <3>[ 15.366336] Bluetooth: hci0: Failed to load firmware file (-2)
10760 12:12:41.075995 <3>[ 15.366340] Bluetooth: hci0: Failed to set up firmware (-2)
10761 12:12:41.086122 <4>[ 15.366344] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10762 12:12:41.099005 <6>[ 15.368115] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10763 12:12:41.102106 <6>[ 15.368386] usbcore: registered new interface driver uvcvideo
10764 12:12:41.108989 <6>[ 15.382312] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10765 12:12:41.119018 <6>[ 15.387153] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10766 12:12:41.122211 <6>[ 15.410738] r8152 1-1.1.1:1.0 eth0: v1.12.13
10767 12:12:41.128669 <6>[ 15.417361] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10768 12:12:41.135067 <6>[ 15.434288] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10769 12:12:41.142028 <6>[ 15.440072] pci 0000:01:00.0: supports D1 D2
10770 12:12:41.148731 <6>[ 15.573736] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10771 12:12:41.155146 <4>[ 15.580732] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10772 12:12:41.161859 <4>[ 15.580732] Fallback method does not support PEC.
10773 12:12:41.168297 <6>[ 15.594707] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10774 12:12:41.175590 <6>[ 15.601620] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10775 12:12:41.185078 <6>[ 15.609709] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10776 12:12:41.191915 <3>[ 15.614440] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10777 12:12:41.201681 <6>[ 15.617713] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10778 12:12:41.208465 <6>[ 15.634503] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10779 12:12:41.218716 <6>[ 15.642519] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10780 12:12:41.221915 <6>[ 15.650528] pci 0000:00:00.0: PCI bridge to [bus 01]
10781 12:12:41.231375 <3>[ 15.651481] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10782 12:12:41.238295 <6>[ 15.655750] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10783 12:12:41.244622 <6>[ 15.672670] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10784 12:12:41.252273 <6>[ 15.679903] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10785 12:12:41.258269 <6>[ 15.686427] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10786 12:12:41.277182 <5>[ 15.701706] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10787 12:12:41.296696 <5>[ 15.721443] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10788 12:12:41.303014 <4>[ 15.728444] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10789 12:12:41.309745 <6>[ 15.737329] cfg80211: failed to load regulatory.db
10790 12:12:41.354683 <6>[ 15.779363] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10791 12:12:41.361035 <6>[ 15.786877] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10792 12:12:41.385277 <6>[ 15.813579] mt7921e 0000:01:00.0: ASIC revision: 79610010
10793 12:12:41.493002 <4>[ 15.914474] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 12:12:41.496168 Begin: Loading essential drivers ... done.
10795 12:12:41.503163 Begin: Running /scripts/init-premount ... done.
10796 12:12:41.509295 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10797 12:12:41.519621 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10798 12:12:41.522695 Device /sys/class/net/enxf4f5e850de0a found
10799 12:12:41.522808 done.
10800 12:12:41.553878 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10801 12:12:41.615246 <4>[ 16.036742] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 12:12:41.730680 <4>[ 16.152421] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10803 12:12:41.846912 <4>[ 16.268186] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 12:12:41.962737 <4>[ 16.384136] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 12:12:42.078357 <4>[ 16.499997] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 12:12:42.194337 <4>[ 16.616060] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 12:12:42.310323 <4>[ 16.731921] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 12:12:42.426654 <4>[ 16.847931] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 12:12:42.542064 <4>[ 16.963918] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 12:12:42.612709 <6>[ 17.041090] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10811 12:12:42.649595 <3>[ 17.077861] mt7921e 0000:01:00.0: hardware init failed
10812 12:12:42.708086 IP-Config: no response after 2 secs - giving up
10813 12:12:42.749892 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10814 12:12:42.752897 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10815 12:12:42.759235 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10816 12:12:42.769194 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10817 12:12:42.775805 host : mt8192-asurada-spherion-r0-cbg-9
10818 12:12:42.782412 domain : lava-rack
10819 12:12:42.786116 rootserver: 192.168.201.1 rootpath:
10820 12:12:42.786248 filename :
10821 12:12:42.795210 done.
10822 12:12:42.802640 Begin: Running /scripts/nfs-bottom ... done.
10823 12:12:42.820731 Begin: Running /scripts/init-bottom ... done.
10824 12:12:43.932823 <6>[ 18.361002] NET: Registered PF_INET6 protocol family
10825 12:12:43.939139 <6>[ 18.367904] Segment Routing with IPv6
10826 12:12:43.942360 <6>[ 18.371866] In-situ OAM (IOAM) with IPv6
10827 12:12:44.067688 <30>[ 18.476738] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10828 12:12:44.070873 <30>[ 18.500542] systemd[1]: Detected architecture arm64.
10829 12:12:44.091190
10830 12:12:44.094227 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10831 12:12:44.094309
10832 12:12:44.112456 <30>[ 18.540772] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10833 12:12:44.659608 <30>[ 19.084910] systemd[1]: Queued start job for default target Graphical Interface.
10834 12:12:44.699423 <30>[ 19.127801] systemd[1]: Created slice system-getty.slice.
10835 12:12:44.705840 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10836 12:12:44.722973 <30>[ 19.151429] systemd[1]: Created slice system-modprobe.slice.
10837 12:12:44.729234 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10838 12:12:44.749989 <30>[ 19.175377] systemd[1]: Created slice system-serial\x2dgetty.slice.
10839 12:12:44.756836 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10840 12:12:44.771325 <30>[ 19.199825] systemd[1]: Created slice User and Session Slice.
10841 12:12:44.777729 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10842 12:12:44.798214 <30>[ 19.223336] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10843 12:12:44.807784 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10844 12:12:44.825933 <30>[ 19.251289] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10845 12:12:44.832920 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10846 12:12:44.853251 <30>[ 19.274903] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10847 12:12:44.859358 <30>[ 19.286930] systemd[1]: Reached target Local Encrypted Volumes.
10848 12:12:44.866321 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10849 12:12:44.882306 <30>[ 19.311064] systemd[1]: Reached target Paths.
10850 12:12:44.886014 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10851 12:12:44.902115 <30>[ 19.330815] systemd[1]: Reached target Remote File Systems.
10852 12:12:44.909142 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10853 12:12:44.922392 <30>[ 19.350792] systemd[1]: Reached target Slices.
10854 12:12:44.925496 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10855 12:12:44.942515 <30>[ 19.370815] systemd[1]: Reached target Swap.
10856 12:12:44.945557 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10857 12:12:44.966160 <30>[ 19.391134] systemd[1]: Listening on initctl Compatibility Named Pipe.
10858 12:12:44.972345 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10859 12:12:44.979346 <30>[ 19.406367] systemd[1]: Listening on Journal Audit Socket.
10860 12:12:44.985594 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10861 12:12:44.999184 <30>[ 19.427677] systemd[1]: Listening on Journal Socket (/dev/log).
10862 12:12:45.006049 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10863 12:12:45.022723 <30>[ 19.451582] systemd[1]: Listening on Journal Socket.
10864 12:12:45.029754 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10865 12:12:45.046713 <30>[ 19.471836] systemd[1]: Listening on Network Service Netlink Socket.
10866 12:12:45.053107 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10867 12:12:45.068297 <30>[ 19.496915] systemd[1]: Listening on udev Control Socket.
10868 12:12:45.074966 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10869 12:12:45.090881 <30>[ 19.519066] systemd[1]: Listening on udev Kernel Socket.
10870 12:12:45.097061 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10871 12:12:45.138295 <30>[ 19.566923] systemd[1]: Mounting Huge Pages File System...
10872 12:12:45.144691 Mounting [0;1;39mHuge Pages File System[0m...
10873 12:12:45.160376 <30>[ 19.588920] systemd[1]: Mounting POSIX Message Queue File System...
10874 12:12:45.167094 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10875 12:12:45.184624 <30>[ 19.613150] systemd[1]: Mounting Kernel Debug File System...
10876 12:12:45.190957 Mounting [0;1;39mKernel Debug File System[0m...
10877 12:12:45.209643 <30>[ 19.635097] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10878 12:12:45.230010 <30>[ 19.655000] systemd[1]: Starting Create list of static device nodes for the current kernel...
10879 12:12:45.236326 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10880 12:12:45.256393 <30>[ 19.685238] systemd[1]: Starting Load Kernel Module configfs...
10881 12:12:45.263168 Starting [0;1;39mLoad Kernel Module configfs[0m...
10882 12:12:45.280721 <30>[ 19.709291] systemd[1]: Starting Load Kernel Module drm...
10883 12:12:45.287136 Starting [0;1;39mLoad Kernel Module drm[0m...
10884 12:12:45.304562 <30>[ 19.733228] systemd[1]: Starting Load Kernel Module fuse...
10885 12:12:45.311491 Starting [0;1;39mLoad Kernel Module fuse[0m...
10886 12:12:45.348574 <30>[ 19.773674] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10887 12:12:45.354913 <6>[ 19.774073] fuse: init (API version 7.37)
10888 12:12:45.361914 <30>[ 19.789983] systemd[1]: Starting Journal Service...
10889 12:12:45.365189 Starting [0;1;39mJournal Service[0m...
10890 12:12:45.388216 <30>[ 19.817016] systemd[1]: Starting Load Kernel Modules...
10891 12:12:45.395082 Starting [0;1;39mLoad Kernel Modules[0m...
10892 12:12:45.416955 <30>[ 19.842088] systemd[1]: Starting Remount Root and Kernel File Systems...
10893 12:12:45.423178 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10894 12:12:45.441097 <30>[ 19.869844] systemd[1]: Starting Coldplug All udev Devices...
10895 12:12:45.447985 Starting [0;1;39mColdplug All udev Devices[0m...
10896 12:12:45.465528 <30>[ 19.893779] systemd[1]: Mounted Huge Pages File System.
10897 12:12:45.471920 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10898 12:12:45.486611 <30>[ 19.915284] systemd[1]: Mounted POSIX Message Queue File System.
10899 12:12:45.493577 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10900 12:12:45.514675 <30>[ 19.943245] systemd[1]: Mounted Kernel Debug File System.
10901 12:12:45.521291 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10902 12:12:45.531664 <3>[ 19.956695] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 12:12:45.542720 <30>[ 19.967672] systemd[1]: Finished Create list of static device nodes for the current kernel.
10904 12:12:45.552038 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10905 12:12:45.566764 <3>[ 19.991578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:12:45.573009 <30>[ 20.001542] systemd[1]: modprobe@configfs.service: Succeeded.
10907 12:12:45.579908 <30>[ 20.008236] systemd[1]: Finished Load Kernel Module configfs.
10908 12:12:45.586163 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10909 12:12:45.603271 <30>[ 20.031590] systemd[1]: modprobe@drm.service: Succeeded.
10910 12:12:45.613229 <3>[ 20.034909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 12:12:45.619634 <30>[ 20.037838] systemd[1]: Finished Load Kernel Module drm.
10912 12:12:45.622724 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10913 12:12:45.646357 <3>[ 20.071503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 12:12:45.653352 <30>[ 20.072156] systemd[1]: modprobe@fuse.service: Succeeded.
10915 12:12:45.659777 <30>[ 20.087197] systemd[1]: Finished Load Kernel Module fuse.
10916 12:12:45.666028 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10917 12:12:45.687715 <3>[ 20.112750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 12:12:45.694744 <30>[ 20.123137] systemd[1]: Finished Load Kernel Modules.
10919 12:12:45.701095 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10920 12:12:45.719013 <30>[ 20.144091] systemd[1]: Finished Remount Root and Kernel File Systems.
10921 12:12:45.725505 <3>[ 20.148108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:12:45.732296 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10923 12:12:45.755562 <3>[ 20.181109] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 12:12:45.770136 <30>[ 20.198451] systemd[1]: Mounting FUSE Control File System...
10925 12:12:45.777051 Mounting [0;1;39mFUSE Control File System[0m...
10926 12:12:45.788421 <3>[ 20.213661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:12:45.800058 <30>[ 20.225454] systemd[1]: Mounting Kernel Configuration File System...
10928 12:12:45.803289 Mounting [0;1;39mKernel Configuration File System[0m...
10929 12:12:45.825406 <30>[ 20.250477] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10930 12:12:45.835533 <30>[ 20.259480] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10931 12:12:45.874951 <30>[ 20.303230] systemd[1]: Starting Load/Save Random Seed...
10932 12:12:45.881398 Starting [0;1;39mLoad/Save Random Seed[0m...
10933 12:12:45.897197 <30>[ 20.326000] systemd[1]: Starting Apply Kernel Variables...
10934 12:12:45.903808 Starting [0;1;39mApply Kernel Variables[0m...
10935 12:12:45.921568 <30>[ 20.350130] systemd[1]: Starting Create System Users...
10936 12:12:45.928279 Starting [0;1;39mCreate System Users[0m...
10937 12:12:45.943374 <30>[ 20.372215] systemd[1]: Started Journal Service.
10938 12:12:45.949917 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10939 12:12:45.967649 <4>[ 20.385938] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10940 12:12:45.977028 <3>[ 20.402185] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10941 12:12:45.983930 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10942 12:12:45.999676 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10943 12:12:46.019142 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10944 12:12:46.030029 See 'systemctl status systemd-udev-trigger.service' for details.
10945 12:12:46.047438 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10946 12:12:46.063161 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10947 12:12:46.079157 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10948 12:12:46.127417 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10949 12:12:46.144643 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10950 12:12:46.181853 <46>[ 20.607330] systemd-journald[296]: Received client request to flush runtime journal.
10951 12:12:46.400669 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10952 12:12:46.418913 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10953 12:12:46.438444 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10954 12:12:46.502347 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10955 12:12:47.564085 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10956 12:12:47.594602 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10957 12:12:47.631108 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10958 12:12:47.656022 Starting [0;1;39mNetwork Service[0m...
10959 12:12:47.985229 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10960 12:12:48.004007 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10961 12:12:48.066641 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10962 12:12:48.084457 <4>[ 22.513590] power_supply_show_property: 5 callbacks suppressed
10963 12:12:48.094686 <3>[ 22.513606] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 12:12:48.113997 <3>[ 22.539382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 12:12:48.132814 <3>[ 22.558319] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 12:12:48.166667 <3>[ 22.592295] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 12:12:48.201975 <3>[ 22.627172] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 12:12:48.222709 <6>[ 22.651075] remoteproc remoteproc0: powering up scp
10969 12:12:48.235204 <3>[ 22.660548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 12:12:48.244980 <4>[ 22.669640] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10971 12:12:48.251708 <3>[ 22.679801] remoteproc remoteproc0: request_firmware failed: -2
10972 12:12:48.259126 <3>[ 22.686162] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10973 12:12:48.268784 <3>[ 22.693757] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 12:12:48.297245 <3>[ 22.722653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 12:12:48.329357 <3>[ 22.754644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 12:12:48.350630 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10977 12:12:48.362123 <3>[ 22.787666] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 12:12:48.375495 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10979 12:12:48.399046 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10980 12:12:48.440229 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10981 12:12:48.457563 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10982 12:12:48.514244 Starting [0;1;39mNetwork Name Resolution[0m...
10983 12:12:48.538063 Starting [0;1;39mNetwork Time Synchronization[0m...
10984 12:12:48.556819 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10985 12:12:48.578526 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10986 12:12:48.607544 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10987 12:12:48.627080 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10988 12:12:48.775116 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10989 12:12:48.790566 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10990 12:12:48.808906 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10991 12:12:48.822040 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10992 12:12:48.841975 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10993 12:12:48.987732 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10994 12:12:49.031756 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10995 12:12:49.068042 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10996 12:12:49.356618 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10997 12:12:49.369881 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10998 12:12:49.623815 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10999 12:12:49.641601 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11000 12:12:49.657639 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11001 12:12:49.698205 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11002 12:12:49.834099 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11003 12:12:50.206535 Starting [0;1;39mUser Login Management[0m...
11004 12:12:50.223379 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11005 12:12:50.243557 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11006 12:12:50.261254 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11007 12:12:50.306881 Starting [0;1;39mPermit User Sessions[0m...
11008 12:12:50.398700 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11009 12:12:50.438741 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11010 12:12:50.456858 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11011 12:12:50.474213 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11012 12:12:50.494901 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11013 12:12:50.512977 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11014 12:12:50.531434 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11015 12:12:50.546097 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11016 12:12:50.605844 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11017 12:12:50.641210 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11018 12:12:50.693305
11019 12:12:50.693489
11020 12:12:50.696363 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11021 12:12:50.696476
11022 12:12:50.699620 debian-bullseye-arm64 login: root (automatic login)
11023 12:12:50.699723
11024 12:12:50.699815
11025 12:12:50.949581 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
11026 12:12:50.949737
11027 12:12:50.956178 The programs included with the Debian GNU/Linux system are free software;
11028 12:12:50.963023 the exact distribution terms for each program are described in the
11029 12:12:50.966173 individual files in /usr/share/doc/*/copyright.
11030 12:12:50.966283
11031 12:12:50.972648 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11032 12:12:50.975835 permitted by applicable law.
11033 12:12:51.051992 Matched prompt #10: / #
11035 12:12:51.052381 Setting prompt string to ['/ #']
11036 12:12:51.052507 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11038 12:12:51.052721 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11039 12:12:51.052829 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11040 12:12:51.052904 Setting prompt string to ['/ #']
11041 12:12:51.052966 Forcing a shell prompt, looking for ['/ #']
11043 12:12:51.103172 / #
11044 12:12:51.103377 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11045 12:12:51.103491 Waiting using forced prompt support (timeout 00:02:30)
11046 12:12:51.108023
11047 12:12:51.108330 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11048 12:12:51.108458 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
11050 12:12:51.208818 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how'
11051 12:12:51.214351 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605392/extract-nfsrootfs-3ej3_how'
11053 12:12:51.314932 / # export NFS_SERVER_IP='192.168.201.1'
11054 12:12:51.319794 export NFS_SERVER_IP='192.168.201.1'
11055 12:12:51.320125 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11056 12:12:51.320270 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11057 12:12:51.320398 end: 2 depthcharge-action (duration 00:01:22) [common]
11058 12:12:51.320540 start: 3 lava-test-retry (timeout 00:30:00) [common]
11059 12:12:51.320676 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11060 12:12:51.320784 Using namespace: common
11062 12:12:51.421218 / # #
11063 12:12:51.421384 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11064 12:12:51.426308 #
11065 12:12:51.426587 Using /lava-10605392
11067 12:12:51.526977 / # export SHELL=/bin/sh
11068 12:12:51.531736 export SHELL=/bin/sh
11070 12:12:51.632256 / # . /lava-10605392/environment
11071 12:12:51.637472 . /lava-10605392/environment
11073 12:12:51.742988 / # /lava-10605392/bin/lava-test-runner /lava-10605392/0
11074 12:12:51.743170 Test shell timeout: 10s (minimum of the action and connection timeout)
11075 12:12:51.747935 /lava-10605392/bin/lava-test-runner /lava-10605392/0
11076 12:12:51.947936 + export TESTRUN_ID=0_lc-compliance
11077 12:12:51.954138 + cd /lava-10605392/0/tests/0_lc-compliance
11078 12:12:51.954232 + cat uuid
11079 12:12:51.958037 + UUID=10605392_1.6.2.3.1
11080 12:12:51.958125 + set +x
11081 12:12:51.964304 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10605392_1.6.2.3.1>
11082 12:12:51.964609 Received signal: <STARTRUN> 0_lc-compliance 10605392_1.6.2.3.1
11083 12:12:51.964687 Starting test lava.0_lc-compliance (10605392_1.6.2.3.1)
11084 12:12:51.964792 Skipping test definition patterns.
11085 12:12:51.967630 + /usr/bin/lc-compliance-parser.sh
11086 12:12:53.146421 [0:00:27.458794077] [404] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-76e1cb9f
11087 12:12:53.149819 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11088 12:12:53.159922 [0:00:27.474279385] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11089 12:12:53.210114 [==========] Running 120 tests from 1 test suite.
11090 12:12:53.219644 [0:00:27.534520539] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 12:12:53.279448 [0:00:27.591842847] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11092 12:12:53.282668 [----------] Global test environment set-up.
11093 12:12:53.335734 [0:00:27.648338077] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11094 12:12:53.351228 [----------] 120 tests from CaptureTests/SingleStream
11095 12:12:53.411643 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11096 12:12:53.458331 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11097 12:12:53.458674 Received signal: <TESTSET> START CaptureTests/SingleStream
11098 12:12:53.458793 Starting test_set CaptureTests/SingleStream
11099 12:12:53.461916 Camera needs 4 requests, can't test only 1
11100 12:12:53.517705 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11101 12:12:53.571251
11102 12:12:53.637955 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (60 ms)
11103 12:12:53.703226 [0:00:28.015647539] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11104 12:12:53.709672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11105 12:12:53.709935 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11107 12:12:53.721195 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11108 12:12:53.762753 Camera needs 4 requests, can't test only 2
11109 12:12:53.824605 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11110 12:12:53.881606
11111 12:12:53.941700 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (58 ms)
11112 12:12:54.008730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11113 12:12:54.009078 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11115 12:12:54.020693 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11116 12:12:54.059664 Camera needs 4 requests, can't test only 3
11117 12:12:54.125322 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11118 12:12:54.171261 [0:00:28.483608924] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11119 12:12:54.189031
11120 12:12:54.252013 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (57 ms)
11121 12:12:54.318738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11122 12:12:54.319069 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11124 12:12:54.329143 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11125 12:12:54.368101 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (367 ms)
11126 12:12:54.441131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11127 12:12:54.441499 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11129 12:12:54.455581 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11130 12:12:54.499586 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (468 ms)
11131 12:12:54.568592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11132 12:12:54.568913 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11134 12:12:54.581084 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11135 12:12:54.893657 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (731 ms)
11136 12:12:54.903812 [0:00:29.215581231] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 12:12:54.966548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11138 12:12:54.966916 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11140 12:12:54.979294 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11141 12:12:55.794310 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (900 ms)
11142 12:12:55.804285 [0:00:30.117018231] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11143 12:12:55.871512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11144 12:12:55.871859 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11146 12:12:55.883960 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11147 12:12:57.193685 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1400 ms)
11148 12:12:57.203534 [0:00:31.515628924] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 12:12:57.267311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11150 12:12:57.267667 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11152 12:12:57.279930 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11153 12:12:59.292808 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2099 ms)
11154 12:12:59.302837 [0:00:33.615077232] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11155 12:12:59.365287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11156 12:12:59.365651 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11158 12:12:59.376460 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11159 12:13:02.493527 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3201 ms)
11160 12:13:02.503548 [0:00:36.816921386] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11161 12:13:02.561950 [0:00:36.875453232] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11162 12:13:02.575836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11163 12:13:02.576190 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11165 12:13:02.589747 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11166 12:13:02.618839 [0:00:36.932109001] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11167 12:13:02.638543 Camera needs 4 requests, can't test only 1
11168 12:13:02.678203 [0:00:36.991270155] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11169 12:13:02.705769 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11170 12:13:02.763991
11171 12:13:02.826366 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (60 ms)
11172 12:13:02.887923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11173 12:13:02.888296 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11175 12:13:02.901504 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11176 12:13:02.944849 Camera needs 4 requests, can't test only 2
11177 12:13:03.005491 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11178 12:13:03.045270 [0:00:37.358688155] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11179 12:13:03.069135
11180 12:13:03.129473 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (58 ms)
11181 12:13:03.195467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11182 12:13:03.195828 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11184 12:13:03.209704 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11185 12:13:03.250314 Camera needs 4 requests, can't test only 3
11186 12:13:03.309828 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11187 12:13:03.364090
11188 12:13:03.426018 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (58 ms)
11189 12:13:03.491870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11190 12:13:03.492232 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11192 12:13:03.503925 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11193 12:13:03.513852 [0:00:37.827941540] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11194 12:13:03.552217 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (367 ms)
11195 12:13:03.620078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11196 12:13:03.620435 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11198 12:13:03.632787 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11199 12:13:03.674700 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (469 ms)
11200 12:13:03.743686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11201 12:13:03.744015 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11203 12:13:03.758732 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11204 12:13:04.205330 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (700 ms)
11205 12:13:04.218633 [0:00:38.527780540] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 12:13:04.281539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11207 12:13:04.281898 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11209 12:13:04.294726 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11210 12:13:05.204280 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (999 ms)
11211 12:13:05.217643 [0:00:39.527214463] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 12:13:05.281760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11213 12:13:05.282082 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11215 12:13:05.294111 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11216 12:13:06.603343 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1399 ms)
11217 12:13:06.616711 [0:00:40.925336540] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 12:13:06.679289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11219 12:13:06.679643 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11221 12:13:06.691836 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11222 12:13:08.701518 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2099 ms)
11223 12:13:08.714041 [0:00:43.024396848] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 12:13:08.773111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11225 12:13:08.773428 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11227 12:13:08.785827 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11228 12:13:11.719990 <6>[ 46.154692] vpu: disabling
11229 12:13:11.723084 <6>[ 46.157748] vproc2: disabling
11230 12:13:11.726762 <6>[ 46.161021] vproc1: disabling
11231 12:13:11.729837 <6>[ 46.164282] vaud18: disabling
11232 12:13:11.736159 <6>[ 46.167688] vsram_others: disabling
11233 12:13:11.739352 <6>[ 46.171563] va09: disabling
11234 12:13:11.743136 <6>[ 46.174668] vsram_md: disabling
11235 12:13:11.746210 <6>[ 46.178151] Vgpu: disabling
11236 12:13:11.901724 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3200 ms)
11237 12:13:11.914850 [0:00:46.224496617] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11238 12:13:11.967080 [0:00:46.281297232] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11239 12:13:11.980469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11240 12:13:11.980766 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11242 12:13:11.993076 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11243 12:13:12.025093 [0:00:46.339327155] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11244 12:13:12.039068 Camera needs 4 requests, can't test only 1
11245 12:13:12.081488 [0:00:46.395904309] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11246 12:13:12.107179 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11247 12:13:12.168361
11248 12:13:12.229319 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (57 ms)
11249 12:13:12.293534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11250 12:13:12.293867 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11252 12:13:12.305806 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11253 12:13:12.351628 Camera needs 4 requests, can't test only 2
11254 12:13:12.413968 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11255 12:13:12.471283
11256 12:13:12.531006 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (58 ms)
11257 12:13:12.548493 [0:00:46.862874617] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11258 12:13:12.609427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11259 12:13:12.609777 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11261 12:13:12.619858 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11262 12:13:12.659575 Camera needs 4 requests, can't test only 3
11263 12:13:12.718755 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11264 12:13:12.775899
11265 12:13:12.841789 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (57 ms)
11266 12:13:12.912712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11267 12:13:12.913042 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11269 12:13:12.923988 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11270 12:13:12.961522 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (465 ms)
11271 12:13:13.017338 [0:00:47.331803309] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11272 12:13:13.039116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11273 12:13:13.039455 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11275 12:13:13.050226 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11276 12:13:13.091367 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (469 ms)
11277 12:13:13.155443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11278 12:13:13.155763 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11280 12:13:13.166728 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11281 12:13:13.740273 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (731 ms)
11282 12:13:13.753247 [0:00:48.063810386] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11283 12:13:13.815588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11284 12:13:13.815913 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11286 12:13:13.826684 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11287 12:13:14.641562 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (901 ms)
11288 12:13:14.654368 [0:00:48.964740386] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 12:13:14.719797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11290 12:13:14.720117 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11292 12:13:14.731284 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11293 12:13:16.043715 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1400 ms)
11294 12:13:16.053425 [0:00:50.364088771] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 12:13:16.119810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11296 12:13:16.120166 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11298 12:13:16.130499 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11299 12:13:18.139792 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2099 ms)
11300 12:13:18.152425 [0:00:52.463820310] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11301 12:13:18.217079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11302 12:13:18.217428 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11304 12:13:18.229939 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11305 12:13:21.404010 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3265 ms)
11306 12:13:21.417327 [0:00:55.727987387] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11307 12:13:21.469772 [0:00:55.785355002] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11308 12:13:21.493636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11309 12:13:21.493933 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11311 12:13:21.506489 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11312 12:13:21.527947 [0:00:55.843284541] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11313 12:13:21.557210 Camera needs 4 requests, can't test only 1
11314 12:13:21.585251 [0:00:55.900651079] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11315 12:13:21.629306 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11316 12:13:21.689837
11317 12:13:21.759060 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11318 12:13:21.834516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11319 12:13:21.834908 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11321 12:13:21.848280 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11322 12:13:21.891668 Camera needs 4 requests, can't test only 2
11323 12:13:21.958607 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11324 12:13:22.018156 [0:00:56.333822167] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11325 12:13:22.034090
11326 12:13:22.099083 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (58 ms)
11327 12:13:22.177409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11328 12:13:22.177725 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11330 12:13:22.188200 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11331 12:13:22.232855 Camera needs 4 requests, can't test only 3
11332 12:13:22.296239 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11333 12:13:22.362850
11334 12:13:22.429066 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (58 ms)
11335 12:13:22.510626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11336 12:13:22.511007 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11338 12:13:22.523364 [0:00:56.835753898] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11339 12:13:22.531447 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11340 12:13:22.569915 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (432 ms)
11341 12:13:22.641895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11342 12:13:22.642247 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11344 12:13:22.652810 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11345 12:13:22.697081 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (502 ms)
11346 12:13:22.772238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11347 12:13:22.772547 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11349 12:13:22.783913 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11350 12:13:23.210880 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (699 ms)
11351 12:13:23.223732 [0:00:57.535496732] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 12:13:23.282821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11353 12:13:23.283164 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11355 12:13:23.296640 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11356 12:13:24.147810 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (936 ms)
11357 12:13:24.160424 [0:00:58.471718185] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 12:13:24.233101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11359 12:13:24.233457 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11361 12:13:24.243759 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11362 12:13:25.546792 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1399 ms)
11363 12:13:25.559561 [0:00:59.871347638] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 12:13:25.629398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11365 12:13:25.629751 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11367 12:13:25.639857 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11368 12:13:27.679793 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2133 ms)
11369 12:13:27.692633 [0:01:02.003632317] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 12:13:27.755980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11371 12:13:27.756342 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11373 12:13:27.768826 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11374 12:13:30.911466 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3231 ms)
11375 12:13:30.924107 [0:01:05.235403602] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 12:13:30.978186 [0:01:05.293022327] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11377 12:13:30.991504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11378 12:13:30.991799 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11380 12:13:31.003423 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11381 12:13:31.035819 [0:01:05.350982555] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 12:13:31.047671 Camera needs 4 requests, can't test only 1
11383 12:13:31.093280 [0:01:05.408261063] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11384 12:13:31.108115 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11385 12:13:31.151560
11386 12:13:31.198225 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (59 ms)
11387 12:13:31.248487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11388 12:13:31.248850 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11390 12:13:31.258079 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11391 12:13:31.293099 Camera needs 4 requests, can't test only 2
11392 12:13:31.347365 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11393 12:13:31.398192
11394 12:13:31.452985 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11395 12:13:31.512436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11396 12:13:31.512794 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11398 12:13:31.527209 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11399 12:13:31.566156 Camera needs 4 requests, can't test only 3
11400 12:13:31.619691 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11401 12:13:31.668750
11402 12:13:31.720688 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (59 ms)
11403 12:13:31.778101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11404 12:13:31.778426 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11406 12:13:31.787970 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11407 12:13:32.347649 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1262 ms)
11408 12:13:32.360792 [0:01:06.671551491] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11409 12:13:32.413937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11410 12:13:32.414286 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11412 12:13:32.423074 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11413 12:13:33.774824 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1427 ms)
11414 12:13:33.787582 [0:01:08.099344100] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 12:13:33.843685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11416 12:13:33.844051 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11418 12:13:33.853614 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11419 12:13:35.832270 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2057 ms)
11420 12:13:35.844804 [0:01:10.155683181] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11421 12:13:35.894347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11422 12:13:35.894705 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11424 12:13:35.903958 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11425 12:13:38.560658 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2729 ms)
11426 12:13:38.573516 [0:01:12.883911809] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 12:13:38.623871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11428 12:13:38.624225 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11430 12:13:38.635283 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11431 12:13:42.683813 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4123 ms)
11432 12:13:42.696777 [0:01:17.007476605] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 12:13:42.763854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11434 12:13:42.764218 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11436 12:13:42.776915 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11437 12:13:49.036835 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6353 ms)
11438 12:13:49.049704 [0:01:23.359953475] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11439 12:13:49.113031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11440 12:13:49.113765 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11442 12:13:49.126464 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11443 12:13:58.690506 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9655 ms)
11444 12:13:58.703662 [0:01:33.015840457] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11445 12:13:58.758777 [0:01:33.075111163] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11446 12:13:58.776749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11447 12:13:58.777044 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11449 12:13:58.787431 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11450 12:13:58.815446 [0:01:33.131594010] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11451 12:13:58.828176 Camera needs 4 requests, can't test only 1
11452 12:13:58.875016 [0:01:33.191292322] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11453 12:13:58.878239 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11454 12:13:58.920479
11455 12:13:58.970885 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (59 ms)
11456 12:13:59.021036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11457 12:13:59.021338 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11459 12:13:59.028047 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11460 12:13:59.059924 Camera needs 4 requests, can't test only 2
11461 12:13:59.106938 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11462 12:13:59.157244
11463 12:13:59.215201 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (58 ms)
11464 12:13:59.269404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11465 12:13:59.269775 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11467 12:13:59.277902 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11468 12:13:59.320143 Camera needs 4 requests, can't test only 3
11469 12:13:59.372283 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11470 12:13:59.420012
11471 12:13:59.473078 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (59 ms)
11472 12:13:59.531446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11473 12:13:59.531755 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11475 12:13:59.539161 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11476 12:14:00.130943 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1261 ms)
11477 12:14:00.140449 [0:01:34.453745836] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 12:14:00.192943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11479 12:14:00.193243 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11481 12:14:00.199249 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11482 12:14:01.558317 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1428 ms)
11483 12:14:01.568677 [0:01:35.881843886] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 12:14:01.630755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11485 12:14:01.631065 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11487 12:14:01.637556 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11488 12:14:03.616893 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2059 ms)
11489 12:14:03.626757 [0:01:37.939936028] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 12:14:03.680792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11491 12:14:03.681115 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11493 12:14:03.688781 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11494 12:14:06.410532 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2793 ms)
11495 12:14:06.419850 [0:01:40.734470253] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 12:14:06.474303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11497 12:14:06.474727 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11499 12:14:06.481296 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11500 12:14:10.598716 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4189 ms)
11501 12:14:10.608782 [0:01:44.922230350] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 12:14:10.670848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11503 12:14:10.671232 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11505 12:14:10.679609 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11506 12:14:16.919456 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6321 ms)
11507 12:14:16.929000 [0:01:51.243351128] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 12:14:16.993355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11509 12:14:16.993715 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11511 12:14:16.999718 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11512 12:14:26.606239 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9688 ms)
11513 12:14:26.615795 [0:02:00.931613177] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 12:14:26.669906 [0:02:00.988680926] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11515 12:14:26.680182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11516 12:14:26.680499 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11518 12:14:26.687084 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11519 12:14:26.727578 [0:02:01.046295000] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 12:14:26.730700 Camera needs 4 requests, can't test only 1
11521 12:14:26.784469 [0:02:01.103563468] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11522 12:14:26.793689 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11523 12:14:26.842957
11524 12:14:26.898829 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (59 ms)
11525 12:14:26.958914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11526 12:14:26.959247 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11528 12:14:26.965409 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11529 12:14:27.002697 Camera needs 4 requests, can't test only 2
11530 12:14:27.055016 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11531 12:14:27.109924
11532 12:14:27.166469 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (57 ms)
11533 12:14:27.221345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11534 12:14:27.221676 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11536 12:14:27.228466 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11537 12:14:27.267320 Camera needs 4 requests, can't test only 3
11538 12:14:27.324390 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11539 12:14:27.380051
11540 12:14:27.443783 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11541 12:14:27.510465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11542 12:14:27.510788 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11544 12:14:27.516747 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11545 12:14:28.065598 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1286 ms)
11546 12:14:28.075606 [0:02:02.391355293] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 12:14:28.134110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11548 12:14:28.134439 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11550 12:14:28.142563 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11551 12:14:29.463345 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1397 ms)
11552 12:14:29.473075 [0:02:03.787680751] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 12:14:29.534603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11554 12:14:29.534912 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11556 12:14:29.541491 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11557 12:14:31.586747 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2123 ms)
11558 12:14:31.596858 [0:02:05.911824625] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 12:14:31.658821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11560 12:14:31.659148 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11562 12:14:31.665795 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11563 12:14:34.383833 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2797 ms)
11564 12:14:34.393862 [0:02:08.707804537] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 12:14:34.445371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11566 12:14:34.445733 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11568 12:14:34.451636 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11569 12:14:38.571146 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4187 ms)
11570 12:14:38.581093 [0:02:12.895470134] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 12:14:38.635930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11572 12:14:38.636388 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11574 12:14:38.643752 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11575 12:14:44.812784 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6240 ms)
11576 12:14:44.822277 [0:02:19.135515152] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11577 12:14:44.895994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11578 12:14:44.897002 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11580 12:14:44.905147 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11581 12:14:54.421793 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9608 ms)
11582 12:14:54.431229 [0:02:28.744113211] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11583 12:14:54.478211 [0:02:28.795112572] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11584 12:14:54.501153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11585 12:14:54.502067 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11587 12:14:54.511333 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11588 12:14:54.530514 [0:02:28.847207956] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11589 12:14:54.566198 Camera needs 4 requests, can't test only 1
11590 12:14:54.583224 [0:02:28.900100552] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11591 12:14:54.640491 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11592 12:14:54.716414
11593 12:14:54.800994 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (52 ms)
11594 12:14:54.888758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11595 12:14:54.889086 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11597 12:14:54.898621 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11598 12:14:54.943473 Camera needs 4 requests, can't test only 2
11599 12:14:55.011957 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11600 12:14:55.085693
11601 12:14:55.162514 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (52 ms)
11602 12:14:55.248917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11603 12:14:55.249222 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11605 12:14:55.259137 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11606 12:14:55.307209 Camera needs 4 requests, can't test only 3
11607 12:14:55.367481 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11608 12:14:55.423222
11609 12:14:55.486792 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11610 12:14:55.551387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11611 12:14:55.552126 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11613 12:14:55.563237 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11614 12:14:55.659312 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1081 ms)
11615 12:14:55.668619 [0:02:29.981469993] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11616 12:14:55.739859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11617 12:14:55.740197 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11619 12:14:55.747531 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11620 12:14:57.037057 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1378 ms)
11621 12:14:57.046891 [0:02:31.359555739] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11622 12:14:57.250996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11623 12:14:57.251358 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11625 12:14:57.260154 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11626 12:14:59.111773 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2075 ms)
11627 12:14:59.121168 [0:02:33.434428358] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11628 12:14:59.169802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11629 12:14:59.170150 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11631 12:14:59.177044 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11632 12:15:01.788807 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2677 ms)
11633 12:15:01.798429 [0:02:36.111435304] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11634 12:15:01.850679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11635 12:15:01.851037 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11637 12:15:01.858817 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11638 12:15:05.896721 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4108 ms)
11639 12:15:05.906309 [0:02:40.219516333] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11640 12:15:05.959844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11641 12:15:05.960208 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11643 12:15:05.968189 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11644 12:15:12.266502 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6370 ms)
11645 12:15:12.276351 [0:02:46.589379537] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11646 12:15:12.342836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11647 12:15:12.343423 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11649 12:15:12.353020 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11650 12:15:21.905592 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9640 ms)
11651 12:15:21.915414 [0:02:56.228848342] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11652 12:15:21.973960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11653 12:15:21.974285 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11655 12:15:21.983402 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11656 12:15:22.165599 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (263 ms)
11657 12:15:22.178198 [0:02:56.492104029] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11658 12:15:22.226808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11659 12:15:22.227125 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11661 12:15:22.237009 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11662 12:15:22.428111 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (262 ms)
11663 12:15:22.441273 [0:02:56.755008783] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11664 12:15:22.500973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11665 12:15:22.501307 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11667 12:15:22.511160 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11668 12:15:22.724193 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (295 ms)
11669 12:15:22.737171 [0:02:57.050403176] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11670 12:15:22.787847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11671 12:15:22.788166 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11673 12:15:22.797529 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11674 12:15:23.086118 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (362 ms)
11675 12:15:23.099521 [0:02:57.412771274] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11676 12:15:23.154399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11677 12:15:23.154724 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11679 12:15:23.165121 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11680 12:15:23.550334 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (464 ms)
11681 12:15:23.563267 [0:02:57.875980358] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11682 12:15:23.614813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11683 12:15:23.615201 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11685 12:15:23.624720 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11686 12:15:24.275985 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (726 ms)
11687 12:15:24.289305 [0:02:58.603241053] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11688 12:15:24.345025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11689 12:15:24.345488 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11691 12:15:24.355275 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11692 12:15:25.172127 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (896 ms)
11693 12:15:25.185171 [0:02:59.499257543] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11694 12:15:25.237856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11695 12:15:25.238211 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11697 12:15:25.247462 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11698 12:15:26.565911 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1394 ms)
11699 12:15:26.578706 [0:03:00.891744496] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11700 12:15:26.633287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11701 12:15:26.633632 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11703 12:15:26.644685 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11704 12:15:28.658769 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2093 ms)
11705 12:15:28.671606 [0:03:02.985019438] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11706 12:15:28.733555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11707 12:15:28.733882 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11709 12:15:28.745813 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11710 12:15:31.854514 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3196 ms)
11711 12:15:31.867700 [0:03:06.180961771] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11712 12:15:31.930287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11713 12:15:31.930648 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11715 12:15:31.940964 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11716 12:15:32.183950 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (326 ms)
11717 12:15:32.193974 [0:03:06.507296197] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11718 12:15:32.245963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11719 12:15:32.246321 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11721 12:15:32.254324 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11722 12:15:32.448505 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (264 ms)
11723 12:15:32.458149 [0:03:06.771615647] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11724 12:15:32.508946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11725 12:15:32.509305 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11727 12:15:32.517237 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11728 12:15:32.743320 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (295 ms)
11729 12:15:32.752910 [0:03:07.066843001] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11730 12:15:32.823433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11731 12:15:32.823754 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11733 12:15:32.834670 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11734 12:15:33.105299 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (362 ms)
11735 12:15:33.115010 [0:03:07.428147553] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11736 12:15:33.168178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11737 12:15:33.168495 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11739 12:15:33.175384 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11740 12:15:33.566850 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (461 ms)
11741 12:15:33.576862 [0:03:07.890402446] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11742 12:15:33.639390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11743 12:15:33.639724 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11745 12:15:33.648462 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11746 12:15:34.195294 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (629 ms)
11747 12:15:34.204812 [0:03:08.518826674] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11748 12:15:34.250344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11749 12:15:34.250670 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11751 12:15:34.258053 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11752 12:15:35.090633 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (895 ms)
11753 12:15:35.100237 [0:03:09.415768469] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11754 12:15:35.149035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11755 12:15:35.149389 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11757 12:15:35.156135 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11758 12:15:36.422043 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1332 ms)
11759 12:15:36.432205 [0:03:10.747247585] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11760 12:15:36.485301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11761 12:15:36.485633 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11763 12:15:36.491748 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11764 12:15:38.549291 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2127 ms)
11765 12:15:38.559034 [0:03:12.873496754] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11766 12:15:38.614425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11767 12:15:38.614760 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11769 12:15:38.621624 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11770 12:15:41.775736 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3227 ms)
11771 12:15:41.785445 [0:03:16.099863342] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11772 12:15:41.845020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11773 12:15:41.845353 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11775 12:15:41.853651 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11776 12:15:42.069946 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (294 ms)
11777 12:15:42.079627 [0:03:16.395240516] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11778 12:15:42.134230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11779 12:15:42.134543 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11781 12:15:42.141896 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11782 12:15:42.367332 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (297 ms)
11783 12:15:42.376500 [0:03:16.691382339] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11784 12:15:42.432452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11785 12:15:42.432798 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11787 12:15:42.440995 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11788 12:15:42.663260 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (296 ms)
11789 12:15:42.672940 [0:03:16.987582928] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11790 12:15:42.724978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11791 12:15:42.725297 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11793 12:15:42.732025 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11794 12:15:43.025508 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (363 ms)
11795 12:15:43.035815 [0:03:17.350889396] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11796 12:15:43.091449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11797 12:15:43.091797 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11799 12:15:43.099326 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11800 12:15:43.491055 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (465 ms)
11801 12:15:43.500383 [0:03:17.815638514] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11802 12:15:43.548976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11803 12:15:43.549302 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11805 12:15:43.555541 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11806 12:15:44.217974 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (727 ms)
11807 12:15:44.227845 [0:03:18.543540560] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11808 12:15:44.282442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11809 12:15:44.282781 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11811 12:15:44.288782 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11812 12:15:45.115117 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (897 ms)
11813 12:15:45.124812 [0:03:19.440679396] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11814 12:15:45.172377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11815 12:15:45.172719 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11817 12:15:45.179396 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11818 12:15:46.509808 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1395 ms)
11819 12:15:46.519330 [0:03:20.835012850] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11820 12:15:46.569934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11821 12:15:46.570254 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11823 12:15:46.579207 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11824 12:15:48.603270 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2094 ms)
11825 12:15:48.613029 [0:03:22.927494631] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11826 12:15:48.675270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11827 12:15:48.675587 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11829 12:15:48.683719 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11830 12:15:51.798805 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3195 ms)
11831 12:15:51.808438 [0:03:26.124498851] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11832 12:15:51.867392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11833 12:15:51.867792 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11835 12:15:51.877134 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11836 12:15:52.126560 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (329 ms)
11837 12:15:52.136828 [0:03:26.451933706] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11838 12:15:52.204307 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11840 12:15:52.207299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11841 12:15:52.215727 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11842 12:15:52.391511 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (264 ms)
11843 12:15:52.400919 [0:03:26.716355254] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11844 12:15:52.447343 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11846 12:15:52.450304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11847 12:15:52.458711 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11848 12:15:52.687115 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (296 ms)
11849 12:15:52.696825 [0:03:27.011955325] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11850 12:15:52.746118 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11852 12:15:52.748997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11853 12:15:52.755894 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11854 12:15:53.049660 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (362 ms)
11855 12:15:53.059403 [0:03:27.375282391] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11856 12:15:53.106845 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11858 12:15:53.109819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11859 12:15:53.116209 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11860 12:15:53.513011 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (464 ms)
11861 12:15:53.522610 [0:03:27.839225837] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11862 12:15:53.576690 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11864 12:15:53.579759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11865 12:15:53.586672 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11866 12:15:54.207551 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (695 ms)
11867 12:15:54.217706 [0:03:28.532182065] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11868 12:15:54.285088 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11870 12:15:54.288081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11871 12:15:54.297871 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11872 12:15:55.136377 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (928 ms)
11873 12:15:55.145757 [0:03:29.461317294] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11874 12:15:55.196078 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11876 12:15:55.199022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11877 12:15:55.208019 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11878 12:15:56.529336 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1393 ms)
11879 12:15:56.539129 [0:03:30.855530111] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11880 12:15:56.589340 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11882 12:15:56.592407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11883 12:15:56.599038 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11884 12:15:58.623398 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2094 ms)
11885 12:15:58.633162 [0:03:32.948237902] [404] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11886 12:15:58.680464 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11888 12:15:58.683709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11889 12:15:58.690175 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11890 12:16:01.817110 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3194 ms)
11891 12:16:01.884105 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11893 12:16:01.887284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11894 12:16:01.893861 [----------] 120 tests from CaptureTests/SingleStream (188669 ms total)
11895 12:16:01.937615
11896 12:16:01.988353 [----------] Global test environment tear-down
11897 12:16:02.036273 [==========] 120 tests from 1 test suite ran. (188669 ms total)
11898 12:16:02.088196 <LAVA_SIGNAL_TESTSET STOP>
11899 12:16:02.088553 Received signal: <TESTSET> STOP
11900 12:16:02.088663 Closing test_set CaptureTests/SingleStream
11901 12:16:02.097264 + set +x
11902 12:16:02.100387 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10605392_1.6.2.3.1>
11903 12:16:02.100661 Received signal: <ENDRUN> 0_lc-compliance 10605392_1.6.2.3.1
11904 12:16:02.100748 Ending use of test pattern.
11905 12:16:02.100811 Ending test lava.0_lc-compliance (10605392_1.6.2.3.1), duration 190.14
11907 12:16:02.103811 <LAVA_TEST_RUNNER EXIT>
11908 12:16:02.104050 ok: lava_test_shell seems to have completed
11909 12:16:02.106053 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11910 12:16:02.106228 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11911 12:16:02.106315 end: 3 lava-test-retry (duration 00:03:11) [common]
11912 12:16:02.106403 start: 4 finalize (timeout 00:10:00) [common]
11913 12:16:02.106529 start: 4.1 power-off (timeout 00:00:30) [common]
11914 12:16:02.106810 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11915 12:16:02.185881 >> Command sent successfully.
11916 12:16:02.188832 Returned 0 in 0 seconds
11917 12:16:02.289263 end: 4.1 power-off (duration 00:00:00) [common]
11919 12:16:02.289764 start: 4.2 read-feedback (timeout 00:10:00) [common]
11920 12:16:02.290200 Listened to connection for namespace 'common' for up to 1s
11921 12:16:03.291018 Finalising connection for namespace 'common'
11922 12:16:03.291200 Disconnecting from shell: Finalise
11923 12:16:03.291294 / #
11924 12:16:03.391607 end: 4.2 read-feedback (duration 00:00:01) [common]
11925 12:16:03.391776 end: 4 finalize (duration 00:00:01) [common]
11926 12:16:03.391912 Cleaning after the job
11927 12:16:03.392021 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/ramdisk
11928 12:16:03.394204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/kernel
11929 12:16:03.403077 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/dtb
11930 12:16:03.403302 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/nfsrootfs
11931 12:16:03.448271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605392/tftp-deploy-bmp9s55c/modules
11932 12:16:03.454115 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605392
11933 12:16:03.725547 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605392
11934 12:16:03.725712 Job finished correctly