Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 33
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 24
1 12:13:56.548437 lava-dispatcher, installed at version: 2023.05.1
2 12:13:56.548663 start: 0 validate
3 12:13:56.548798 Start time: 2023-06-06 12:13:56.548790+00:00 (UTC)
4 12:13:56.548929 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:13:56.549068 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:13:56.836520 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:13:56.836704 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:13:57.123852 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:13:57.124067 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:13:57.413044 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:13:57.413225 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:13:57.714606 validate duration: 1.17
14 12:13:57.716266 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:13:57.716956 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:13:57.717671 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:13:57.718415 Not decompressing ramdisk as can be used compressed.
18 12:13:57.719018 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/rootfs.cpio.gz
19 12:13:57.719513 saving as /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/ramdisk/rootfs.cpio.gz
20 12:13:57.720027 total size: 84903995 (80MB)
21 12:13:57.725010 progress 0% (0MB)
22 12:13:57.765739 progress 5% (4MB)
23 12:13:57.788086 progress 10% (8MB)
24 12:13:57.809466 progress 15% (12MB)
25 12:13:57.831086 progress 20% (16MB)
26 12:13:57.852780 progress 25% (20MB)
27 12:13:57.874308 progress 30% (24MB)
28 12:13:57.895624 progress 35% (28MB)
29 12:13:57.917248 progress 40% (32MB)
30 12:13:57.939364 progress 45% (36MB)
31 12:13:57.962005 progress 50% (40MB)
32 12:13:57.984202 progress 55% (44MB)
33 12:13:58.006184 progress 60% (48MB)
34 12:13:58.027897 progress 65% (52MB)
35 12:13:58.049533 progress 70% (56MB)
36 12:13:58.071332 progress 75% (60MB)
37 12:13:58.093048 progress 80% (64MB)
38 12:13:58.114776 progress 85% (68MB)
39 12:13:58.136355 progress 90% (72MB)
40 12:13:58.157981 progress 95% (76MB)
41 12:13:58.178919 progress 100% (80MB)
42 12:13:58.179069 80MB downloaded in 0.46s (176.39MB/s)
43 12:13:58.179232 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:13:58.179474 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:13:58.179567 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:13:58.179654 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:13:58.179782 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:13:58.179857 saving as /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/kernel/Image
50 12:13:58.179919 total size: 45746688 (43MB)
51 12:13:58.179980 No compression specified
52 12:13:58.181111 progress 0% (0MB)
53 12:13:58.192589 progress 5% (2MB)
54 12:13:58.204297 progress 10% (4MB)
55 12:13:58.215934 progress 15% (6MB)
56 12:13:58.227611 progress 20% (8MB)
57 12:13:58.239133 progress 25% (10MB)
58 12:13:58.250500 progress 30% (13MB)
59 12:13:58.262008 progress 35% (15MB)
60 12:13:58.273762 progress 40% (17MB)
61 12:13:58.285599 progress 45% (19MB)
62 12:13:58.297219 progress 50% (21MB)
63 12:13:58.308661 progress 55% (24MB)
64 12:13:58.320252 progress 60% (26MB)
65 12:13:58.331746 progress 65% (28MB)
66 12:13:58.343312 progress 70% (30MB)
67 12:13:58.355073 progress 75% (32MB)
68 12:13:58.366529 progress 80% (34MB)
69 12:13:58.377953 progress 85% (37MB)
70 12:13:58.389441 progress 90% (39MB)
71 12:13:58.400774 progress 95% (41MB)
72 12:13:58.412135 progress 100% (43MB)
73 12:13:58.412260 43MB downloaded in 0.23s (187.78MB/s)
74 12:13:58.412410 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:13:58.412641 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:13:58.412729 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:13:58.412816 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:13:58.412946 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:13:58.413024 saving as /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/dtb/mt8192-asurada-spherion-r0.dtb
81 12:13:58.413090 total size: 46924 (0MB)
82 12:13:58.413151 No compression specified
83 12:13:58.414243 progress 69% (0MB)
84 12:13:58.414515 progress 100% (0MB)
85 12:13:58.414698 0MB downloaded in 0.00s (27.88MB/s)
86 12:13:58.414817 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:13:58.415039 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:13:58.415126 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:13:58.415211 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:13:58.415322 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:13:58.415392 saving as /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/modules/modules.tar
93 12:13:58.415454 total size: 8553528 (8MB)
94 12:13:58.415513 Using unxz to decompress xz
95 12:13:58.419200 progress 0% (0MB)
96 12:13:58.440294 progress 5% (0MB)
97 12:13:58.463682 progress 10% (0MB)
98 12:13:58.494215 progress 15% (1MB)
99 12:13:58.519805 progress 20% (1MB)
100 12:13:58.544356 progress 25% (2MB)
101 12:13:58.568693 progress 30% (2MB)
102 12:13:58.594116 progress 35% (2MB)
103 12:13:58.618532 progress 40% (3MB)
104 12:13:58.643638 progress 45% (3MB)
105 12:13:58.668104 progress 50% (4MB)
106 12:13:58.692474 progress 55% (4MB)
107 12:13:58.715903 progress 60% (4MB)
108 12:13:58.740207 progress 65% (5MB)
109 12:13:58.764796 progress 70% (5MB)
110 12:13:58.788775 progress 75% (6MB)
111 12:13:58.814873 progress 80% (6MB)
112 12:13:58.839675 progress 85% (6MB)
113 12:13:58.863747 progress 90% (7MB)
114 12:13:58.886706 progress 95% (7MB)
115 12:13:58.912445 progress 100% (8MB)
116 12:13:58.916999 8MB downloaded in 0.50s (16.26MB/s)
117 12:13:58.917318 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:13:58.917722 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:13:58.917821 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:13:58.917918 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:13:58.918009 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:13:58.918098 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:13:58.918321 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f
125 12:13:58.918447 makedir: /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin
126 12:13:58.918551 makedir: /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/tests
127 12:13:58.918648 makedir: /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/results
128 12:13:58.918764 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-add-keys
129 12:13:58.918906 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-add-sources
130 12:13:58.919040 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-background-process-start
131 12:13:58.919169 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-background-process-stop
132 12:13:58.919291 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-common-functions
133 12:13:58.919437 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-echo-ipv4
134 12:13:58.919598 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-install-packages
135 12:13:58.919755 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-installed-packages
136 12:13:58.919913 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-os-build
137 12:13:58.920113 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-probe-channel
138 12:13:58.920265 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-probe-ip
139 12:13:58.920407 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-target-ip
140 12:13:58.920532 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-target-mac
141 12:13:58.920651 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-target-storage
142 12:13:58.920774 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-case
143 12:13:58.920900 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-event
144 12:13:58.921020 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-feedback
145 12:13:58.921141 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-raise
146 12:13:58.921263 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-reference
147 12:13:58.921411 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-runner
148 12:13:58.921558 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-set
149 12:13:58.921683 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-test-shell
150 12:13:58.921807 Updating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-install-packages (oe)
151 12:13:58.921959 Updating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/bin/lava-installed-packages (oe)
152 12:13:58.922082 Creating /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/environment
153 12:13:58.922190 LAVA metadata
154 12:13:58.922266 - LAVA_JOB_ID=10605425
155 12:13:58.922335 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:13:58.922442 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:13:58.922509 skipped lava-vland-overlay
158 12:13:58.922585 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:13:58.922664 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:13:58.922726 skipped lava-multinode-overlay
161 12:13:58.922799 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:13:58.922882 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:13:58.922955 Loading test definitions
164 12:13:58.923047 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 12:13:58.923119 Using /lava-10605425 at stage 0
166 12:13:58.923223 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:13:58.923310 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/0/tests/0_sleep'
168 12:13:59.599735 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/0/tests/0_sleep
169 12:13:59.601014 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:13:59.601515 uuid=10605425_1.5.2.3.1 testdef=None
171 12:13:59.601688 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:13:59.602070 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 12:13:59.602857 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:13:59.603174 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 12:13:59.603992 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:13:59.604384 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 12:13:59.605344 runner path: /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/0/tests/0_sleep test_uuid 10605425_1.5.2.3.1
181 12:13:59.605460 sleep_params='mem freeze'
182 12:13:59.605639 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:13:59.605995 Creating lava-test-runner.conf files
185 12:13:59.606089 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605425/lava-overlay-bkvu4t2f/lava-10605425/0 for stage 0
186 12:13:59.606209 - 0_sleep
187 12:13:59.606344 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:13:59.606463 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 12:13:59.731027 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:13:59.731184 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 12:13:59.731278 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:13:59.731386 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:13:59.731513 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 12:14:02.091387 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 12:14:02.091798 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
196 12:14:02.091947 extracting modules file /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605425/extract-overlay-ramdisk-9tlj2o5t/ramdisk
197 12:14:02.341033 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:14:02.341239 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 12:14:02.341370 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605425/compress-overlay-x7nf_mlk/overlay-1.5.2.4.tar.gz to ramdisk
200 12:14:02.341469 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605425/compress-overlay-x7nf_mlk/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605425/extract-overlay-ramdisk-9tlj2o5t/ramdisk
201 12:14:02.457652 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:14:02.457820 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 12:14:02.457923 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:14:02.458021 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 12:14:02.458104 Building ramdisk /var/lib/lava/dispatcher/tmp/10605425/extract-overlay-ramdisk-9tlj2o5t/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605425/extract-overlay-ramdisk-9tlj2o5t/ramdisk
206 12:14:03.843286 >> 561596 blocks
207 12:14:13.920519 rename /var/lib/lava/dispatcher/tmp/10605425/extract-overlay-ramdisk-9tlj2o5t/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/ramdisk/ramdisk.cpio.gz
208 12:14:13.920944 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 12:14:13.921072 start: 1.5.8 prepare-kernel (timeout 00:09:44) [common]
210 12:14:13.921176 start: 1.5.8.1 prepare-fit (timeout 00:09:44) [common]
211 12:14:13.921289 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/kernel/Image'
212 12:14:25.650286 Returned 0 in 11 seconds
213 12:14:25.751093 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/kernel/image.itb
214 12:14:26.985084 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:14:26.985437 output: Created: Tue Jun 6 13:14:26 2023
216 12:14:26.985533 output: Image 0 (kernel-1)
217 12:14:26.985600 output: Description:
218 12:14:26.985664 output: Created: Tue Jun 6 13:14:26 2023
219 12:14:26.985735 output: Type: Kernel Image
220 12:14:26.985798 output: Compression: lzma compressed
221 12:14:26.985864 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
222 12:14:26.985926 output: Architecture: AArch64
223 12:14:26.985983 output: OS: Linux
224 12:14:26.986038 output: Load Address: 0x00000000
225 12:14:26.986103 output: Entry Point: 0x00000000
226 12:14:26.986199 output: Hash algo: crc32
227 12:14:26.986257 output: Hash value: fd97082e
228 12:14:26.986318 output: Image 1 (fdt-1)
229 12:14:26.986404 output: Description: mt8192-asurada-spherion-r0
230 12:14:26.986463 output: Created: Tue Jun 6 13:14:26 2023
231 12:14:26.986518 output: Type: Flat Device Tree
232 12:14:26.986577 output: Compression: uncompressed
233 12:14:26.986662 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 12:14:26.986759 output: Architecture: AArch64
235 12:14:26.986847 output: Hash algo: crc32
236 12:14:26.986935 output: Hash value: 1df858fa
237 12:14:26.987018 output: Image 2 (ramdisk-1)
238 12:14:26.987101 output: Description: unavailable
239 12:14:26.987184 output: Created: Tue Jun 6 13:14:26 2023
240 12:14:26.987267 output: Type: RAMDisk Image
241 12:14:26.987358 output: Compression: Unknown Compression
242 12:14:26.987443 output: Data Size: 98131634 Bytes = 95831.67 KiB = 93.59 MiB
243 12:14:26.987526 output: Architecture: AArch64
244 12:14:26.987609 output: OS: Linux
245 12:14:26.987691 output: Load Address: unavailable
246 12:14:26.987773 output: Entry Point: unavailable
247 12:14:26.987856 output: Hash algo: crc32
248 12:14:26.987946 output: Hash value: ddeabd51
249 12:14:26.988035 output: Default Configuration: 'conf-1'
250 12:14:26.988130 output: Configuration 0 (conf-1)
251 12:14:26.988184 output: Description: mt8192-asurada-spherion-r0
252 12:14:26.988237 output: Kernel: kernel-1
253 12:14:26.988290 output: Init Ramdisk: ramdisk-1
254 12:14:26.988342 output: FDT: fdt-1
255 12:14:26.988395 output: Loadables: kernel-1
256 12:14:26.988450 output:
257 12:14:26.988658 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 12:14:26.988752 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 12:14:26.988865 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 12:14:26.988960 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
261 12:14:26.989042 No LXC device requested
262 12:14:26.989121 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:14:26.989209 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
264 12:14:26.989288 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:14:26.989357 Checking files for TFTP limit of 4294967296 bytes.
266 12:14:26.989851 end: 1 tftp-deploy (duration 00:00:29) [common]
267 12:14:26.989962 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:14:26.990053 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:14:26.990175 substitutions:
270 12:14:26.990244 - {DTB}: 10605425/tftp-deploy-3m5mim6z/dtb/mt8192-asurada-spherion-r0.dtb
271 12:14:26.990307 - {INITRD}: 10605425/tftp-deploy-3m5mim6z/ramdisk/ramdisk.cpio.gz
272 12:14:26.990366 - {KERNEL}: 10605425/tftp-deploy-3m5mim6z/kernel/Image
273 12:14:26.990425 - {LAVA_MAC}: None
274 12:14:26.990481 - {PRESEED_CONFIG}: None
275 12:14:26.990537 - {PRESEED_LOCAL}: None
276 12:14:26.990592 - {RAMDISK}: 10605425/tftp-deploy-3m5mim6z/ramdisk/ramdisk.cpio.gz
277 12:14:26.990647 - {ROOT_PART}: None
278 12:14:26.990702 - {ROOT}: None
279 12:14:26.990756 - {SERVER_IP}: 192.168.201.1
280 12:14:26.990810 - {TEE}: None
281 12:14:26.990863 Parsed boot commands:
282 12:14:26.990917 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:14:26.991082 Parsed boot commands: tftpboot 192.168.201.1 10605425/tftp-deploy-3m5mim6z/kernel/image.itb 10605425/tftp-deploy-3m5mim6z/kernel/cmdline
284 12:14:26.991171 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:14:26.991257 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:14:26.991348 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:14:26.991432 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:14:26.991506 Not connected, no need to disconnect.
289 12:14:26.991579 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:14:26.991658 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:14:26.991727 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
292 12:14:26.995151 Setting prompt string to ['lava-test: # ']
293 12:14:26.995491 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:14:26.995604 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:14:26.995706 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:14:26.995799 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:14:26.995998 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
298 12:14:32.127129 >> Command sent successfully.
299 12:14:32.129760 Returned 0 in 5 seconds
300 12:14:32.230579 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 12:14:32.232233 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 12:14:32.232908 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 12:14:32.233483 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:14:32.234007 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:14:32.234545 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:14:32.236328 [Enter `^Ec?' for help]
308 12:14:32.404095
309 12:14:32.404818
310 12:14:32.405360 F0: 102B 0000
311 12:14:32.405897
312 12:14:32.406410 F3: 1001 0000 [0200]
313 12:14:32.407476
314 12:14:32.408083 F3: 1001 0000
315 12:14:32.408494
316 12:14:32.408990 F7: 102D 0000
317 12:14:32.409471
318 12:14:32.410895 F1: 0000 0000
319 12:14:32.411379
320 12:14:32.411703 V0: 0000 0000 [0001]
321 12:14:32.412174
322 12:14:32.414425 00: 0007 8000
323 12:14:32.415041
324 12:14:32.415484 01: 0000 0000
325 12:14:32.416000
326 12:14:32.417369 BP: 0C00 0209 [0000]
327 12:14:32.417988
328 12:14:32.418527 G0: 1182 0000
329 12:14:32.419034
330 12:14:32.420681 EC: 0000 0021 [4000]
331 12:14:32.421189
332 12:14:32.421720 S7: 0000 0000 [0000]
333 12:14:32.422237
334 12:14:32.424009 CC: 0000 0000 [0001]
335 12:14:32.424459
336 12:14:32.424797 T0: 0000 0040 [010F]
337 12:14:32.425034
338 12:14:32.427219 Jump to BL
339 12:14:32.427616
340 12:14:32.451058
341 12:14:32.451478
342 12:14:32.451867
343 12:14:32.458065 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:14:32.461049 ARM64: Exception handlers installed.
345 12:14:32.465025 ARM64: Testing exception
346 12:14:32.468656 ARM64: Done test exception
347 12:14:32.475118 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:14:32.485414 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:14:32.492410 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:14:32.502523 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:14:32.508667 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:14:32.518949 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:14:32.529559 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:14:32.535834 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:14:32.554336 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:14:32.557261 WDT: Last reset was cold boot
357 12:14:32.560644 SPI1(PAD0) initialized at 2873684 Hz
358 12:14:32.564140 SPI5(PAD0) initialized at 992727 Hz
359 12:14:32.567102 VBOOT: Loading verstage.
360 12:14:32.574073 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:14:32.577304 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:14:32.580557 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:14:32.583675 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:14:32.591691 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:14:32.598033 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:14:32.608762 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 12:14:32.609194
368 12:14:32.609537
369 12:14:32.618781 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:14:32.622166 ARM64: Exception handlers installed.
371 12:14:32.625538 ARM64: Testing exception
372 12:14:32.625971 ARM64: Done test exception
373 12:14:32.632441 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:14:32.635876 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:14:32.650320 Probing TPM: . done!
376 12:14:32.650858 TPM ready after 0 ms
377 12:14:32.659575 Connected to device vid:did:rid of 1ae0:0028:00
378 12:14:32.665570 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
379 12:14:32.723366 Initialized TPM device CR50 revision 0
380 12:14:32.734238 tlcl_send_startup: Startup return code is 0
381 12:14:32.734933 TPM: setup succeeded
382 12:14:32.745798 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:14:32.754503 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:14:32.768204 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:14:32.774845 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:14:32.778261 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:14:32.784849 in-header: 03 07 00 00 08 00 00 00
388 12:14:32.788242 in-data: aa e4 47 04 13 02 00 00
389 12:14:32.791758 Chrome EC: UHEPI supported
390 12:14:32.798707 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:14:32.802821 in-header: 03 95 00 00 08 00 00 00
392 12:14:32.806297 in-data: 18 20 20 08 00 00 00 00
393 12:14:32.806382 Phase 1
394 12:14:32.810004 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:14:32.817471 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:14:32.820406 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:14:32.824320 Recovery requested (1009000e)
398 12:14:32.833293 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:14:32.838705 tlcl_extend: response is 0
400 12:14:32.848100 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:14:32.853826 tlcl_extend: response is 0
402 12:14:32.860977 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:14:32.880702 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 12:14:32.887830 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 12:14:32.888308
406 12:14:32.888655
407 12:14:32.897210 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:14:32.900674 ARM64: Exception handlers installed.
409 12:14:32.904123 ARM64: Testing exception
410 12:14:32.904553 ARM64: Done test exception
411 12:14:32.926006 pmic_efuse_setting: Set efuses in 11 msecs
412 12:14:32.929404 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:14:32.935935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:14:32.939325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:14:32.946370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:14:32.950174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:14:32.953781 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:14:32.961123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:14:32.964599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:14:32.968083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:14:32.971788 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:14:32.979101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:14:32.983220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:14:32.986683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:14:32.990184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:14:32.998433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:14:33.002413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:14:33.009532 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:14:33.017245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:14:33.020810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:14:33.028348 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:14:33.031906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:14:33.039132 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:14:33.042623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:14:33.050024 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:14:33.053873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:14:33.061286 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:14:33.064681 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:14:33.072172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:14:33.075510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:14:33.079102 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:14:33.086590 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:14:33.090161 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:14:33.093790 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:14:33.100715 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:14:33.104467 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:14:33.111449 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:14:33.115507 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:14:33.118880 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:14:33.126503 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:14:33.129533 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:14:33.133632 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:14:33.136849 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:14:33.144119 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:14:33.147922 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:14:33.151927 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:14:33.155226 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:14:33.159170 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:14:33.162683 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:14:33.170394 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:14:33.174088 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:14:33.177467 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:14:33.181193 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:14:33.188273 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:14:33.195510 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:14:33.203127 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:14:33.209979 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:14:33.217793 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:14:33.221250 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:14:33.228587 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:14:33.232015 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:14:33.239630 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
473 12:14:33.242432 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:14:33.250280 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
475 12:14:33.253791 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:14:33.263192 [RTC]rtc_get_frequency_meter,154: input=15, output=852
477 12:14:33.272911 [RTC]rtc_get_frequency_meter,154: input=7, output=724
478 12:14:33.281836 [RTC]rtc_get_frequency_meter,154: input=11, output=788
479 12:14:33.291465 [RTC]rtc_get_frequency_meter,154: input=13, output=820
480 12:14:33.300924 [RTC]rtc_get_frequency_meter,154: input=12, output=805
481 12:14:33.310554 [RTC]rtc_get_frequency_meter,154: input=11, output=787
482 12:14:33.320455 [RTC]rtc_get_frequency_meter,154: input=12, output=803
483 12:14:33.324139 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
484 12:14:33.328114 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
485 12:14:33.335233 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 12:14:33.338629 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 12:14:33.342675 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 12:14:33.346391 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 12:14:33.350358 ADC[4]: Raw value=903694 ID=7
490 12:14:33.351017 ADC[3]: Raw value=213916 ID=1
491 12:14:33.354206 RAM Code: 0x71
492 12:14:33.358049 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 12:14:33.365188 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 12:14:33.372425 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 12:14:33.379619 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 12:14:33.383710 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 12:14:33.384360 in-header: 03 07 00 00 08 00 00 00
498 12:14:33.387180 in-data: aa e4 47 04 13 02 00 00
499 12:14:33.390944 Chrome EC: UHEPI supported
500 12:14:33.397680 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 12:14:33.401917 in-header: 03 95 00 00 08 00 00 00
502 12:14:33.405300 in-data: 18 20 20 08 00 00 00 00
503 12:14:33.408762 MRC: failed to locate region type 0.
504 12:14:33.412897 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 12:14:33.416455 DRAM-K: Running full calibration
506 12:14:33.423122 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 12:14:33.426638 header.status = 0x0
508 12:14:33.427109 header.version = 0x6 (expected: 0x6)
509 12:14:33.430341 header.size = 0xd00 (expected: 0xd00)
510 12:14:33.434048 header.flags = 0x0
511 12:14:33.440889 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 12:14:33.458006 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
513 12:14:33.465451 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 12:14:33.468798 dram_init: ddr_geometry: 2
515 12:14:33.469229 [EMI] MDL number = 2
516 12:14:33.472546 [EMI] Get MDL freq = 0
517 12:14:33.472980 dram_init: ddr_type: 0
518 12:14:33.476530 is_discrete_lpddr4: 1
519 12:14:33.480026 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 12:14:33.480505
521 12:14:33.480850
522 12:14:33.481169 [Bian_co] ETT version 0.0.0.1
523 12:14:33.487106 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 12:14:33.487541
525 12:14:33.491268 dramc_set_vcore_voltage set vcore to 650000
526 12:14:33.491702 Read voltage for 800, 4
527 12:14:33.494902 Vio18 = 0
528 12:14:33.495332 Vcore = 650000
529 12:14:33.495675 Vdram = 0
530 12:14:33.495994 Vddq = 0
531 12:14:33.498162 Vmddr = 0
532 12:14:33.498592 dram_init: config_dvfs: 1
533 12:14:33.504395 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 12:14:33.511395 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 12:14:33.515423 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
536 12:14:33.519159 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
537 12:14:33.522778 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
538 12:14:33.526269 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
539 12:14:33.526706 MEM_TYPE=3, freq_sel=18
540 12:14:33.529733 sv_algorithm_assistance_LP4_1600
541 12:14:33.533249 ============ PULL DRAM RESETB DOWN ============
542 12:14:33.539904 ========== PULL DRAM RESETB DOWN end =========
543 12:14:33.543260 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 12:14:33.546751 ===================================
545 12:14:33.549693 LPDDR4 DRAM CONFIGURATION
546 12:14:33.553092 ===================================
547 12:14:33.553527 EX_ROW_EN[0] = 0x0
548 12:14:33.556618 EX_ROW_EN[1] = 0x0
549 12:14:33.557054 LP4Y_EN = 0x0
550 12:14:33.559815 WORK_FSP = 0x0
551 12:14:33.560287 WL = 0x2
552 12:14:33.562906 RL = 0x2
553 12:14:33.563342 BL = 0x2
554 12:14:33.566744 RPST = 0x0
555 12:14:33.567179 RD_PRE = 0x0
556 12:14:33.569536 WR_PRE = 0x1
557 12:14:33.573029 WR_PST = 0x0
558 12:14:33.573464 DBI_WR = 0x0
559 12:14:33.576411 DBI_RD = 0x0
560 12:14:33.576846 OTF = 0x1
561 12:14:33.579576 ===================================
562 12:14:33.583057 ===================================
563 12:14:33.583492 ANA top config
564 12:14:33.586580 ===================================
565 12:14:33.589917 DLL_ASYNC_EN = 0
566 12:14:33.592914 ALL_SLAVE_EN = 1
567 12:14:33.596338 NEW_RANK_MODE = 1
568 12:14:33.599836 DLL_IDLE_MODE = 1
569 12:14:33.600488 LP45_APHY_COMB_EN = 1
570 12:14:33.603418 TX_ODT_DIS = 1
571 12:14:33.606826 NEW_8X_MODE = 1
572 12:14:33.609538 ===================================
573 12:14:33.612998 ===================================
574 12:14:33.616384 data_rate = 1600
575 12:14:33.619863 CKR = 1
576 12:14:33.620385 DQ_P2S_RATIO = 8
577 12:14:33.622749 ===================================
578 12:14:33.626311 CA_P2S_RATIO = 8
579 12:14:33.629609 DQ_CA_OPEN = 0
580 12:14:33.633712 DQ_SEMI_OPEN = 0
581 12:14:33.636652 CA_SEMI_OPEN = 0
582 12:14:33.637109 CA_FULL_RATE = 0
583 12:14:33.640176 DQ_CKDIV4_EN = 1
584 12:14:33.643748 CA_CKDIV4_EN = 1
585 12:14:33.646729 CA_PREDIV_EN = 0
586 12:14:33.650403 PH8_DLY = 0
587 12:14:33.650836 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 12:14:33.653642 DQ_AAMCK_DIV = 4
589 12:14:33.657115 CA_AAMCK_DIV = 4
590 12:14:33.660478 CA_ADMCK_DIV = 4
591 12:14:33.663435 DQ_TRACK_CA_EN = 0
592 12:14:33.666804 CA_PICK = 800
593 12:14:33.670301 CA_MCKIO = 800
594 12:14:33.670864 MCKIO_SEMI = 0
595 12:14:33.673717 PLL_FREQ = 3068
596 12:14:33.677217 DQ_UI_PI_RATIO = 32
597 12:14:33.681408 CA_UI_PI_RATIO = 0
598 12:14:33.685227 ===================================
599 12:14:33.685680 ===================================
600 12:14:33.689454 memory_type:LPDDR4
601 12:14:33.692924 GP_NUM : 10
602 12:14:33.693405 SRAM_EN : 1
603 12:14:33.696298 MD32_EN : 0
604 12:14:33.699897 ===================================
605 12:14:33.700439 [ANA_INIT] >>>>>>>>>>>>>>
606 12:14:33.703372 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 12:14:33.707380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 12:14:33.710747 ===================================
609 12:14:33.714243 data_rate = 1600,PCW = 0X7600
610 12:14:33.717582 ===================================
611 12:14:33.720411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 12:14:33.723984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 12:14:33.730954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 12:14:33.734335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 12:14:33.737291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 12:14:33.744288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 12:14:33.744729 [ANA_INIT] flow start
618 12:14:33.747146 [ANA_INIT] PLL >>>>>>>>
619 12:14:33.750760 [ANA_INIT] PLL <<<<<<<<
620 12:14:33.751195 [ANA_INIT] MIDPI >>>>>>>>
621 12:14:33.753712 [ANA_INIT] MIDPI <<<<<<<<
622 12:14:33.757384 [ANA_INIT] DLL >>>>>>>>
623 12:14:33.757819 [ANA_INIT] flow end
624 12:14:33.760681 ============ LP4 DIFF to SE enter ============
625 12:14:33.766774 ============ LP4 DIFF to SE exit ============
626 12:14:33.767212 [ANA_INIT] <<<<<<<<<<<<<
627 12:14:33.770509 [Flow] Enable top DCM control >>>>>
628 12:14:33.773819 [Flow] Enable top DCM control <<<<<
629 12:14:33.777069 Enable DLL master slave shuffle
630 12:14:33.783795 ==============================================================
631 12:14:33.786558 Gating Mode config
632 12:14:33.790334 ==============================================================
633 12:14:33.793665 Config description:
634 12:14:33.803749 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 12:14:33.810018 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 12:14:33.813473 SELPH_MODE 0: By rank 1: By Phase
637 12:14:33.820374 ==============================================================
638 12:14:33.823540 GAT_TRACK_EN = 1
639 12:14:33.827022 RX_GATING_MODE = 2
640 12:14:33.827458 RX_GATING_TRACK_MODE = 2
641 12:14:33.830055 SELPH_MODE = 1
642 12:14:33.833552 PICG_EARLY_EN = 1
643 12:14:33.837122 VALID_LAT_VALUE = 1
644 12:14:33.843702 ==============================================================
645 12:14:33.847195 Enter into Gating configuration >>>>
646 12:14:33.850062 Exit from Gating configuration <<<<
647 12:14:33.853356 Enter into DVFS_PRE_config >>>>>
648 12:14:33.863592 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 12:14:33.866438 Exit from DVFS_PRE_config <<<<<
650 12:14:33.870040 Enter into PICG configuration >>>>
651 12:14:33.873324 Exit from PICG configuration <<<<
652 12:14:33.876820 [RX_INPUT] configuration >>>>>
653 12:14:33.879990 [RX_INPUT] configuration <<<<<
654 12:14:33.883386 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 12:14:33.889523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 12:14:33.896744 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 12:14:33.903148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 12:14:33.909412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 12:14:33.912855 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 12:14:33.919756 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 12:14:33.922583 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 12:14:33.926013 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 12:14:33.929446 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 12:14:33.933008 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 12:14:33.939366 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 12:14:33.942652 ===================================
667 12:14:33.946143 LPDDR4 DRAM CONFIGURATION
668 12:14:33.949235 ===================================
669 12:14:33.949868 EX_ROW_EN[0] = 0x0
670 12:14:33.952830 EX_ROW_EN[1] = 0x0
671 12:14:33.953457 LP4Y_EN = 0x0
672 12:14:33.955726 WORK_FSP = 0x0
673 12:14:33.956310 WL = 0x2
674 12:14:33.959193 RL = 0x2
675 12:14:33.959790 BL = 0x2
676 12:14:33.962613 RPST = 0x0
677 12:14:33.963208 RD_PRE = 0x0
678 12:14:33.966305 WR_PRE = 0x1
679 12:14:33.966736 WR_PST = 0x0
680 12:14:33.969287 DBI_WR = 0x0
681 12:14:33.969719 DBI_RD = 0x0
682 12:14:33.972757 OTF = 0x1
683 12:14:33.975471 ===================================
684 12:14:33.978898 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 12:14:33.982404 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 12:14:33.988745 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 12:14:33.992262 ===================================
688 12:14:33.995421 LPDDR4 DRAM CONFIGURATION
689 12:14:33.998785 ===================================
690 12:14:33.999342 EX_ROW_EN[0] = 0x10
691 12:14:34.002330 EX_ROW_EN[1] = 0x0
692 12:14:34.002856 LP4Y_EN = 0x0
693 12:14:34.005616 WORK_FSP = 0x0
694 12:14:34.006065 WL = 0x2
695 12:14:34.008898 RL = 0x2
696 12:14:34.009334 BL = 0x2
697 12:14:34.012028 RPST = 0x0
698 12:14:34.012496 RD_PRE = 0x0
699 12:14:34.015589 WR_PRE = 0x1
700 12:14:34.016026 WR_PST = 0x0
701 12:14:34.018937 DBI_WR = 0x0
702 12:14:34.019389 DBI_RD = 0x0
703 12:14:34.022463 OTF = 0x1
704 12:14:34.025503 ===================================
705 12:14:34.031881 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 12:14:34.035473 nWR fixed to 40
707 12:14:34.038105 [ModeRegInit_LP4] CH0 RK0
708 12:14:34.038190 [ModeRegInit_LP4] CH0 RK1
709 12:14:34.041799 [ModeRegInit_LP4] CH1 RK0
710 12:14:34.045292 [ModeRegInit_LP4] CH1 RK1
711 12:14:34.045376 match AC timing 13
712 12:14:34.051318 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 12:14:34.054871 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 12:14:34.058264 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 12:14:34.065221 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 12:14:34.068233 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 12:14:34.068351 [EMI DOE] emi_dcm 0
718 12:14:34.074710 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 12:14:34.074836 ==
720 12:14:34.078124 Dram Type= 6, Freq= 0, CH_0, rank 0
721 12:14:34.081384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 12:14:34.081468 ==
723 12:14:34.088320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 12:14:34.094695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 12:14:34.102330 [CA 0] Center 37 (7~68) winsize 62
726 12:14:34.105721 [CA 1] Center 37 (7~68) winsize 62
727 12:14:34.109162 [CA 2] Center 35 (4~66) winsize 63
728 12:14:34.112574 [CA 3] Center 35 (4~66) winsize 63
729 12:14:34.115907 [CA 4] Center 33 (3~64) winsize 62
730 12:14:34.118883 [CA 5] Center 33 (3~64) winsize 62
731 12:14:34.118967
732 12:14:34.122298 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 12:14:34.122382
734 12:14:34.126039 [CATrainingPosCal] consider 1 rank data
735 12:14:34.128782 u2DelayCellTimex100 = 270/100 ps
736 12:14:34.132012 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
737 12:14:34.138865 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
738 12:14:34.142579 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
739 12:14:34.145456 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
740 12:14:34.149110 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 12:14:34.152112 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 12:14:34.152197
743 12:14:34.155879 CA PerBit enable=1, Macro0, CA PI delay=33
744 12:14:34.155963
745 12:14:34.158601 [CBTSetCACLKResult] CA Dly = 33
746 12:14:34.162023 CS Dly: 6 (0~37)
747 12:14:34.162107 ==
748 12:14:34.165681 Dram Type= 6, Freq= 0, CH_0, rank 1
749 12:14:34.168567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 12:14:34.168651 ==
751 12:14:34.175636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 12:14:34.178592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 12:14:34.188795 [CA 0] Center 38 (7~69) winsize 63
754 12:14:34.192172 [CA 1] Center 37 (7~68) winsize 62
755 12:14:34.195573 [CA 2] Center 35 (5~66) winsize 62
756 12:14:34.198997 [CA 3] Center 35 (4~66) winsize 63
757 12:14:34.202327 [CA 4] Center 34 (3~65) winsize 63
758 12:14:34.205569 [CA 5] Center 33 (3~64) winsize 62
759 12:14:34.205669
760 12:14:34.209050 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 12:14:34.209161
762 12:14:34.212397 [CATrainingPosCal] consider 2 rank data
763 12:14:34.215398 u2DelayCellTimex100 = 270/100 ps
764 12:14:34.218802 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
765 12:14:34.225737 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 12:14:34.228839 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 12:14:34.231990 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
768 12:14:34.235674 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 12:14:34.239071 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 12:14:34.239155
771 12:14:34.241964 CA PerBit enable=1, Macro0, CA PI delay=33
772 12:14:34.242048
773 12:14:34.245298 [CBTSetCACLKResult] CA Dly = 33
774 12:14:34.248815 CS Dly: 6 (0~38)
775 12:14:34.248900
776 12:14:34.252288 ----->DramcWriteLeveling(PI) begin...
777 12:14:34.252378 ==
778 12:14:34.255759 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:14:34.259835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:14:34.259948 ==
781 12:14:34.263069 Write leveling (Byte 0): 31 => 31
782 12:14:34.263155 Write leveling (Byte 1): 25 => 25
783 12:14:34.267150 DramcWriteLeveling(PI) end<-----
784 12:14:34.267236
785 12:14:34.267303 ==
786 12:14:34.270096 Dram Type= 6, Freq= 0, CH_0, rank 0
787 12:14:34.277012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 12:14:34.277100 ==
789 12:14:34.277168 [Gating] SW mode calibration
790 12:14:34.283993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 12:14:34.290977 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 12:14:34.293847 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 12:14:34.300481 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 12:14:34.304045 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
795 12:14:34.307353 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:14:34.314131 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:14:34.317099 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:14:34.320553 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:14:34.327044 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:14:34.330559 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:14:34.333923 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:14:34.337303 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:14:34.343950 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:14:34.347185 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:14:34.350425 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:14:34.356908 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:14:34.360470 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:14:34.363429 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:14:34.370351 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
810 12:14:34.373390 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
811 12:14:34.376780 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:14:34.383947 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:14:34.386945 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:14:34.390347 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:14:34.397182 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:14:34.400455 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:14:34.403990 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:14:34.410070 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
819 12:14:34.413504 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
820 12:14:34.416906 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:14:34.423759 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:14:34.426647 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 12:14:34.430039 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 12:14:34.437077 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 12:14:34.440524 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
826 12:14:34.443414 0 10 8 | B1->B0 | 3333 2424 | 0 0 | (1 1) (0 0)
827 12:14:34.450386 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
828 12:14:34.453683 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:14:34.456715 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:14:34.463273 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:14:34.466659 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:14:34.470307 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:14:34.473731 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
834 12:14:34.480049 0 11 8 | B1->B0 | 2828 3d3d | 1 0 | (0 0) (0 0)
835 12:14:34.483618 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
836 12:14:34.486494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:14:34.493333 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:14:34.496693 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:14:34.500252 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 12:14:34.506403 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 12:14:34.509777 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
842 12:14:34.513340 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 12:14:34.519470 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:14:34.522692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:14:34.526056 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:14:34.532988 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:14:34.535985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:14:34.539355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:14:34.545762 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:14:34.549242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:14:34.552608 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:14:34.558867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:14:34.562353 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:14:34.565804 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:14:34.572283 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:14:34.575726 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:14:34.578719 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
858 12:14:34.585534 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
859 12:14:34.589023 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
860 12:14:34.592039 Total UI for P1: 0, mck2ui 16
861 12:14:34.595479 best dqsien dly found for B0: ( 0, 14, 6)
862 12:14:34.598905 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 12:14:34.602211 Total UI for P1: 0, mck2ui 16
864 12:14:34.605292 best dqsien dly found for B1: ( 0, 14, 12)
865 12:14:34.609040 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
866 12:14:34.612160 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
867 12:14:34.615430
868 12:14:34.618884 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
869 12:14:34.622161 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
870 12:14:34.625110 [Gating] SW calibration Done
871 12:14:34.625284 ==
872 12:14:34.629044 Dram Type= 6, Freq= 0, CH_0, rank 0
873 12:14:34.632415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
874 12:14:34.632542 ==
875 12:14:34.632615 RX Vref Scan: 0
876 12:14:34.632695
877 12:14:34.635890 RX Vref 0 -> 0, step: 1
878 12:14:34.635975
879 12:14:34.638869 RX Delay -130 -> 252, step: 16
880 12:14:34.642230 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
881 12:14:34.645797 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
882 12:14:34.652143 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
883 12:14:34.655896 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
884 12:14:34.659205 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
885 12:14:34.662434 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
886 12:14:34.666024 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
887 12:14:34.672492 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
888 12:14:34.675406 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
889 12:14:34.678693 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
890 12:14:34.682204 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
891 12:14:34.685838 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
892 12:14:34.692285 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
893 12:14:34.695726 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
894 12:14:34.698650 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
895 12:14:34.702101 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
896 12:14:34.702439 ==
897 12:14:34.705667 Dram Type= 6, Freq= 0, CH_0, rank 0
898 12:14:34.712071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
899 12:14:34.712470 ==
900 12:14:34.712786 DQS Delay:
901 12:14:34.715398 DQS0 = 0, DQS1 = 0
902 12:14:34.716005 DQM Delay:
903 12:14:34.716458 DQM0 = 89, DQM1 = 76
904 12:14:34.718867 DQ Delay:
905 12:14:34.722187 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
906 12:14:34.725523 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
907 12:14:34.728821 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
908 12:14:34.732159 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
909 12:14:34.732788
910 12:14:34.733363
911 12:14:34.733915 ==
912 12:14:34.735602 Dram Type= 6, Freq= 0, CH_0, rank 0
913 12:14:34.738998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 12:14:34.739640 ==
915 12:14:34.740315
916 12:14:34.740941
917 12:14:34.742197 TX Vref Scan disable
918 12:14:34.742847 == TX Byte 0 ==
919 12:14:34.748839 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
920 12:14:34.752496 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
921 12:14:34.753089 == TX Byte 1 ==
922 12:14:34.758874 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
923 12:14:34.762381 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
924 12:14:34.762816 ==
925 12:14:34.765836 Dram Type= 6, Freq= 0, CH_0, rank 0
926 12:14:34.768684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 12:14:34.769270 ==
928 12:14:34.783874 TX Vref=22, minBit 4, minWin=26, winSum=434
929 12:14:34.787424 TX Vref=24, minBit 0, minWin=27, winSum=439
930 12:14:34.790354 TX Vref=26, minBit 0, minWin=27, winSum=445
931 12:14:34.793873 TX Vref=28, minBit 1, minWin=27, winSum=451
932 12:14:34.796794 TX Vref=30, minBit 0, minWin=28, winSum=455
933 12:14:34.800428 TX Vref=32, minBit 2, minWin=27, winSum=449
934 12:14:34.806633 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
935 12:14:34.807207
936 12:14:34.810056 Final TX Range 1 Vref 30
937 12:14:34.810494
938 12:14:34.810836 ==
939 12:14:34.813630 Dram Type= 6, Freq= 0, CH_0, rank 0
940 12:14:34.816930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 12:14:34.817381 ==
942 12:14:34.819965
943 12:14:34.820493
944 12:14:34.821005 TX Vref Scan disable
945 12:14:34.823712 == TX Byte 0 ==
946 12:14:34.827207 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
947 12:14:34.833419 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
948 12:14:34.833868 == TX Byte 1 ==
949 12:14:34.836564 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
950 12:14:34.843188 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
951 12:14:34.843272
952 12:14:34.843337 [DATLAT]
953 12:14:34.843397 Freq=800, CH0 RK0
954 12:14:34.843458
955 12:14:34.846388 DATLAT Default: 0xa
956 12:14:34.846476 0, 0xFFFF, sum = 0
957 12:14:34.849655 1, 0xFFFF, sum = 0
958 12:14:34.853167 2, 0xFFFF, sum = 0
959 12:14:34.853246 3, 0xFFFF, sum = 0
960 12:14:34.856713 4, 0xFFFF, sum = 0
961 12:14:34.856792 5, 0xFFFF, sum = 0
962 12:14:34.859835 6, 0xFFFF, sum = 0
963 12:14:34.859949 7, 0xFFFF, sum = 0
964 12:14:34.862794 8, 0xFFFF, sum = 0
965 12:14:34.862882 9, 0x0, sum = 1
966 12:14:34.866073 10, 0x0, sum = 2
967 12:14:34.866145 11, 0x0, sum = 3
968 12:14:34.866206 12, 0x0, sum = 4
969 12:14:34.869592 best_step = 10
970 12:14:34.869666
971 12:14:34.869730 ==
972 12:14:34.873182 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:14:34.876532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:14:34.876659 ==
975 12:14:34.879699 RX Vref Scan: 1
976 12:14:34.880109
977 12:14:34.883424 Set Vref Range= 32 -> 127
978 12:14:34.883853
979 12:14:34.884245 RX Vref 32 -> 127, step: 1
980 12:14:34.884569
981 12:14:34.887035 RX Delay -95 -> 252, step: 8
982 12:14:34.887464
983 12:14:34.889841 Set Vref, RX VrefLevel [Byte0]: 32
984 12:14:34.893423 [Byte1]: 32
985 12:14:34.896525
986 12:14:34.897074 Set Vref, RX VrefLevel [Byte0]: 33
987 12:14:34.900086 [Byte1]: 33
988 12:14:34.904001
989 12:14:34.904619 Set Vref, RX VrefLevel [Byte0]: 34
990 12:14:34.907386 [Byte1]: 34
991 12:14:34.911784
992 12:14:34.912372 Set Vref, RX VrefLevel [Byte0]: 35
993 12:14:34.915201 [Byte1]: 35
994 12:14:34.919588
995 12:14:34.920015 Set Vref, RX VrefLevel [Byte0]: 36
996 12:14:34.922858 [Byte1]: 36
997 12:14:34.927496
998 12:14:34.927937 Set Vref, RX VrefLevel [Byte0]: 37
999 12:14:34.930514 [Byte1]: 37
1000 12:14:34.934666
1001 12:14:34.935234 Set Vref, RX VrefLevel [Byte0]: 38
1002 12:14:34.938158 [Byte1]: 38
1003 12:14:34.942708
1004 12:14:34.943266 Set Vref, RX VrefLevel [Byte0]: 39
1005 12:14:34.945899 [Byte1]: 39
1006 12:14:34.950008
1007 12:14:34.950464 Set Vref, RX VrefLevel [Byte0]: 40
1008 12:14:34.953644 [Byte1]: 40
1009 12:14:34.957607
1010 12:14:34.958047 Set Vref, RX VrefLevel [Byte0]: 41
1011 12:14:34.960574 [Byte1]: 41
1012 12:14:34.964577
1013 12:14:34.965031 Set Vref, RX VrefLevel [Byte0]: 42
1014 12:14:34.968140 [Byte1]: 42
1015 12:14:34.972337
1016 12:14:34.972774 Set Vref, RX VrefLevel [Byte0]: 43
1017 12:14:34.975522 [Byte1]: 43
1018 12:14:34.980284
1019 12:14:34.980896 Set Vref, RX VrefLevel [Byte0]: 44
1020 12:14:34.983213 [Byte1]: 44
1021 12:14:34.987951
1022 12:14:34.988435 Set Vref, RX VrefLevel [Byte0]: 45
1023 12:14:34.990876 [Byte1]: 45
1024 12:14:34.995190
1025 12:14:34.995644 Set Vref, RX VrefLevel [Byte0]: 46
1026 12:14:34.998491 [Byte1]: 46
1027 12:14:35.002614
1028 12:14:35.003045 Set Vref, RX VrefLevel [Byte0]: 47
1029 12:14:35.006300 [Byte1]: 47
1030 12:14:35.010580
1031 12:14:35.011011 Set Vref, RX VrefLevel [Byte0]: 48
1032 12:14:35.013894 [Byte1]: 48
1033 12:14:35.017921
1034 12:14:35.018385 Set Vref, RX VrefLevel [Byte0]: 49
1035 12:14:35.021438 [Byte1]: 49
1036 12:14:35.025839
1037 12:14:35.026270 Set Vref, RX VrefLevel [Byte0]: 50
1038 12:14:35.028683 [Byte1]: 50
1039 12:14:35.033298
1040 12:14:35.033728 Set Vref, RX VrefLevel [Byte0]: 51
1041 12:14:35.036253 [Byte1]: 51
1042 12:14:35.040665
1043 12:14:35.041095 Set Vref, RX VrefLevel [Byte0]: 52
1044 12:14:35.043916 [Byte1]: 52
1045 12:14:35.048555
1046 12:14:35.048996 Set Vref, RX VrefLevel [Byte0]: 53
1047 12:14:35.051864 [Byte1]: 53
1048 12:14:35.055853
1049 12:14:35.056485 Set Vref, RX VrefLevel [Byte0]: 54
1050 12:14:35.059390 [Byte1]: 54
1051 12:14:35.063315
1052 12:14:35.063769 Set Vref, RX VrefLevel [Byte0]: 55
1053 12:14:35.066867 [Byte1]: 55
1054 12:14:35.071433
1055 12:14:35.071916 Set Vref, RX VrefLevel [Byte0]: 56
1056 12:14:35.074443 [Byte1]: 56
1057 12:14:35.078957
1058 12:14:35.079384 Set Vref, RX VrefLevel [Byte0]: 57
1059 12:14:35.081802 [Byte1]: 57
1060 12:14:35.086241
1061 12:14:35.086817 Set Vref, RX VrefLevel [Byte0]: 58
1062 12:14:35.089663 [Byte1]: 58
1063 12:14:35.093915
1064 12:14:35.094361 Set Vref, RX VrefLevel [Byte0]: 59
1065 12:14:35.096830 [Byte1]: 59
1066 12:14:35.101538
1067 12:14:35.102133 Set Vref, RX VrefLevel [Byte0]: 60
1068 12:14:35.104580 [Byte1]: 60
1069 12:14:35.109249
1070 12:14:35.109694 Set Vref, RX VrefLevel [Byte0]: 61
1071 12:14:35.112254 [Byte1]: 61
1072 12:14:35.116884
1073 12:14:35.117314 Set Vref, RX VrefLevel [Byte0]: 62
1074 12:14:35.119778 [Byte1]: 62
1075 12:14:35.124307
1076 12:14:35.124811 Set Vref, RX VrefLevel [Byte0]: 63
1077 12:14:35.127636 [Byte1]: 63
1078 12:14:35.131528
1079 12:14:35.132007 Set Vref, RX VrefLevel [Byte0]: 64
1080 12:14:35.134772 [Byte1]: 64
1081 12:14:35.139567
1082 12:14:35.140110 Set Vref, RX VrefLevel [Byte0]: 65
1083 12:14:35.142384 [Byte1]: 65
1084 12:14:35.146777
1085 12:14:35.147326 Set Vref, RX VrefLevel [Byte0]: 66
1086 12:14:35.150184 [Byte1]: 66
1087 12:14:35.154551
1088 12:14:35.155023 Set Vref, RX VrefLevel [Byte0]: 67
1089 12:14:35.158180 [Byte1]: 67
1090 12:14:35.162244
1091 12:14:35.162678 Set Vref, RX VrefLevel [Byte0]: 68
1092 12:14:35.165413 [Byte1]: 68
1093 12:14:35.169738
1094 12:14:35.170203 Set Vref, RX VrefLevel [Byte0]: 69
1095 12:14:35.173216 [Byte1]: 69
1096 12:14:35.177498
1097 12:14:35.177955 Set Vref, RX VrefLevel [Byte0]: 70
1098 12:14:35.181082 [Byte1]: 70
1099 12:14:35.184910
1100 12:14:35.185376 Set Vref, RX VrefLevel [Byte0]: 71
1101 12:14:35.188461 [Byte1]: 71
1102 12:14:35.192813
1103 12:14:35.193295 Set Vref, RX VrefLevel [Byte0]: 72
1104 12:14:35.195826 [Byte1]: 72
1105 12:14:35.199990
1106 12:14:35.200554 Final RX Vref Byte 0 = 56 to rank0
1107 12:14:35.203452 Final RX Vref Byte 1 = 58 to rank0
1108 12:14:35.207260 Final RX Vref Byte 0 = 56 to rank1
1109 12:14:35.210141 Final RX Vref Byte 1 = 58 to rank1==
1110 12:14:35.213707 Dram Type= 6, Freq= 0, CH_0, rank 0
1111 12:14:35.220274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1112 12:14:35.220730 ==
1113 12:14:35.221069 DQS Delay:
1114 12:14:35.221411 DQS0 = 0, DQS1 = 0
1115 12:14:35.223808 DQM Delay:
1116 12:14:35.224286 DQM0 = 88, DQM1 = 76
1117 12:14:35.226621 DQ Delay:
1118 12:14:35.229971 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1119 12:14:35.233462 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1120 12:14:35.233884 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1121 12:14:35.240503 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1122 12:14:35.241088
1123 12:14:35.241437
1124 12:14:35.246863 [DQSOSCAuto] RK0, (LSB)MR18= 0x312a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1125 12:14:35.250214 CH0 RK0: MR19=606, MR18=312A
1126 12:14:35.256322 CH0_RK0: MR19=0x606, MR18=0x312A, DQSOSC=397, MR23=63, INC=93, DEC=62
1127 12:14:35.256766
1128 12:14:35.259801 ----->DramcWriteLeveling(PI) begin...
1129 12:14:35.260263 ==
1130 12:14:35.262988 Dram Type= 6, Freq= 0, CH_0, rank 1
1131 12:14:35.266737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 12:14:35.267293 ==
1133 12:14:35.269678 Write leveling (Byte 0): 32 => 32
1134 12:14:35.273307 Write leveling (Byte 1): 26 => 26
1135 12:14:35.276266 DramcWriteLeveling(PI) end<-----
1136 12:14:35.276697
1137 12:14:35.277035 ==
1138 12:14:35.279829 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 12:14:35.283201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 12:14:35.283631 ==
1141 12:14:35.286269 [Gating] SW mode calibration
1142 12:14:35.293085 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1143 12:14:35.299830 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1144 12:14:35.302812 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1145 12:14:35.306383 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1146 12:14:35.312925 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1147 12:14:35.316585 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:14:35.359777 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:14:35.360361 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:14:35.360621 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:14:35.360689 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:14:35.360751 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:14:35.360822 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:14:35.360893 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:14:35.361400 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:14:35.361466 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:14:35.361951 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:14:35.364173 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:14:35.367852 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:14:35.374277 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:14:35.377628 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1162 12:14:35.381185 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1163 12:14:35.387583 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:14:35.390914 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:14:35.394025 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:14:35.400805 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:14:35.404191 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:14:35.407243 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:14:35.414290 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:14:35.417146 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1171 12:14:35.420719 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1172 12:14:35.427222 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 12:14:35.430533 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 12:14:35.434180 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 12:14:35.440319 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 12:14:35.443793 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 12:14:35.447066 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
1178 12:14:35.453881 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
1179 12:14:35.456963 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:14:35.460543 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:14:35.467017 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:14:35.470332 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:14:35.473697 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:14:35.480420 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:14:35.483748 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
1186 12:14:35.487199 0 11 8 | B1->B0 | 3131 4242 | 0 0 | (0 0) (1 1)
1187 12:14:35.490688 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1188 12:14:35.497250 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:14:35.500624 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:14:35.504679 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:14:35.512131 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 12:14:35.515102 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 12:14:35.518940 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1194 12:14:35.521842 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1195 12:14:35.528881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:14:35.532475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:14:35.535978 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:14:35.539361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:14:35.545625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:14:35.549407 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:14:35.552822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:14:35.559217 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:14:35.563159 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:14:35.566191 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:14:35.572661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:14:35.576003 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:14:35.579260 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:14:35.586143 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:14:35.589474 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:14:35.592786 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1211 12:14:35.596299 Total UI for P1: 0, mck2ui 16
1212 12:14:35.599424 best dqsien dly found for B0: ( 0, 14, 6)
1213 12:14:35.605673 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 12:14:35.606101 Total UI for P1: 0, mck2ui 16
1215 12:14:35.609603 best dqsien dly found for B1: ( 0, 14, 10)
1216 12:14:35.616102 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1217 12:14:35.619023 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1218 12:14:35.619452
1219 12:14:35.622638 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1220 12:14:35.626272 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1221 12:14:35.628942 [Gating] SW calibration Done
1222 12:14:35.629402 ==
1223 12:14:35.632446 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 12:14:35.636074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 12:14:35.636516 ==
1226 12:14:35.638956 RX Vref Scan: 0
1227 12:14:35.639386
1228 12:14:35.639727 RX Vref 0 -> 0, step: 1
1229 12:14:35.640086
1230 12:14:35.642450 RX Delay -130 -> 252, step: 16
1231 12:14:35.645923 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1232 12:14:35.652346 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1233 12:14:35.655546 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1234 12:14:35.659094 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1235 12:14:35.662604 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1236 12:14:35.665331 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1237 12:14:35.671883 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1238 12:14:35.675695 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1239 12:14:35.679059 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1240 12:14:35.682428 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1241 12:14:35.685746 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1242 12:14:35.692099 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1243 12:14:35.695532 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1244 12:14:35.698931 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1245 12:14:35.702288 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1246 12:14:35.705239 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1247 12:14:35.708862 ==
1248 12:14:35.712170 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 12:14:35.715728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 12:14:35.716208 ==
1251 12:14:35.716562 DQS Delay:
1252 12:14:35.719313 DQS0 = 0, DQS1 = 0
1253 12:14:35.719745 DQM Delay:
1254 12:14:35.722254 DQM0 = 84, DQM1 = 77
1255 12:14:35.722685 DQ Delay:
1256 12:14:35.725630 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1257 12:14:35.728580 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
1258 12:14:35.732001 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1259 12:14:35.735704 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1260 12:14:35.736184
1261 12:14:35.736535
1262 12:14:35.736853 ==
1263 12:14:35.738715 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 12:14:35.742198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 12:14:35.742635 ==
1266 12:14:35.742978
1267 12:14:35.743294
1268 12:14:35.745381 TX Vref Scan disable
1269 12:14:35.748676 == TX Byte 0 ==
1270 12:14:35.752155 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1271 12:14:35.755437 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1272 12:14:35.758797 == TX Byte 1 ==
1273 12:14:35.761646 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1274 12:14:35.765165 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1275 12:14:35.765599 ==
1276 12:14:35.768478 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 12:14:35.771829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 12:14:35.775346 ==
1279 12:14:35.787287 TX Vref=22, minBit 1, minWin=27, winSum=445
1280 12:14:35.790793 TX Vref=24, minBit 1, minWin=27, winSum=446
1281 12:14:35.793823 TX Vref=26, minBit 2, minWin=27, winSum=450
1282 12:14:35.797255 TX Vref=28, minBit 1, minWin=27, winSum=449
1283 12:14:35.800639 TX Vref=30, minBit 1, minWin=27, winSum=451
1284 12:14:35.804163 TX Vref=32, minBit 1, minWin=27, winSum=449
1285 12:14:35.810520 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1286 12:14:35.810984
1287 12:14:35.813882 Final TX Range 1 Vref 30
1288 12:14:35.814400
1289 12:14:35.814743 ==
1290 12:14:35.817280 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 12:14:35.820723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 12:14:35.821158 ==
1293 12:14:35.821572
1294 12:14:35.823647
1295 12:14:35.824132 TX Vref Scan disable
1296 12:14:35.827134 == TX Byte 0 ==
1297 12:14:35.830483 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1298 12:14:35.836899 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1299 12:14:35.837320 == TX Byte 1 ==
1300 12:14:35.840427 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1301 12:14:35.846959 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1302 12:14:35.847376
1303 12:14:35.847704 [DATLAT]
1304 12:14:35.848009 Freq=800, CH0 RK1
1305 12:14:35.848360
1306 12:14:35.850264 DATLAT Default: 0xa
1307 12:14:35.850683 0, 0xFFFF, sum = 0
1308 12:14:35.853690 1, 0xFFFF, sum = 0
1309 12:14:35.856977 2, 0xFFFF, sum = 0
1310 12:14:35.857277 3, 0xFFFF, sum = 0
1311 12:14:35.860362 4, 0xFFFF, sum = 0
1312 12:14:35.860662 5, 0xFFFF, sum = 0
1313 12:14:35.863274 6, 0xFFFF, sum = 0
1314 12:14:35.863594 7, 0xFFFF, sum = 0
1315 12:14:35.866626 8, 0xFFFF, sum = 0
1316 12:14:35.866923 9, 0x0, sum = 1
1317 12:14:35.870085 10, 0x0, sum = 2
1318 12:14:35.870382 11, 0x0, sum = 3
1319 12:14:35.870635 12, 0x0, sum = 4
1320 12:14:35.873262 best_step = 10
1321 12:14:35.873554
1322 12:14:35.873785 ==
1323 12:14:35.876892 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 12:14:35.880273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 12:14:35.880568 ==
1326 12:14:35.883164 RX Vref Scan: 0
1327 12:14:35.883454
1328 12:14:35.886694 RX Vref 0 -> 0, step: 1
1329 12:14:35.887109
1330 12:14:35.887433 RX Delay -95 -> 252, step: 8
1331 12:14:35.894121 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1332 12:14:35.897405 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1333 12:14:35.900238 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1334 12:14:35.903678 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1335 12:14:35.907211 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1336 12:14:35.913565 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1337 12:14:35.916933 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1338 12:14:35.920476 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1339 12:14:35.923892 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1340 12:14:35.926907 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1341 12:14:35.933935 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1342 12:14:35.936844 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1343 12:14:35.940393 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1344 12:14:35.944098 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1345 12:14:35.950506 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1346 12:14:35.953365 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1347 12:14:35.953784 ==
1348 12:14:35.956914 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 12:14:35.960256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 12:14:35.960674 ==
1351 12:14:35.961002 DQS Delay:
1352 12:14:35.963537 DQS0 = 0, DQS1 = 0
1353 12:14:35.963954 DQM Delay:
1354 12:14:35.966833 DQM0 = 86, DQM1 = 76
1355 12:14:35.967249 DQ Delay:
1356 12:14:35.970362 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1357 12:14:35.973621 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1358 12:14:35.976901 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1359 12:14:35.979960 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1360 12:14:35.980447
1361 12:14:35.980773
1362 12:14:35.989716 [DQSOSCAuto] RK1, (LSB)MR18= 0x241f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
1363 12:14:35.990203 CH0 RK1: MR19=606, MR18=241F
1364 12:14:35.996612 CH0_RK1: MR19=0x606, MR18=0x241F, DQSOSC=400, MR23=63, INC=92, DEC=61
1365 12:14:35.999841 [RxdqsGatingPostProcess] freq 800
1366 12:14:36.006979 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1367 12:14:36.010324 Pre-setting of DQS Precalculation
1368 12:14:36.013465 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1369 12:14:36.013950 ==
1370 12:14:36.016383 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 12:14:36.022949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 12:14:36.023055 ==
1373 12:14:36.026440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1374 12:14:36.033066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1375 12:14:36.041734 [CA 0] Center 36 (6~67) winsize 62
1376 12:14:36.045207 [CA 1] Center 36 (6~67) winsize 62
1377 12:14:36.049126 [CA 2] Center 35 (5~65) winsize 61
1378 12:14:36.052522 [CA 3] Center 34 (4~65) winsize 62
1379 12:14:36.055554 [CA 4] Center 34 (4~65) winsize 62
1380 12:14:36.058954 [CA 5] Center 34 (3~65) winsize 63
1381 12:14:36.059549
1382 12:14:36.062057 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1383 12:14:36.062485
1384 12:14:36.065416 [CATrainingPosCal] consider 1 rank data
1385 12:14:36.068870 u2DelayCellTimex100 = 270/100 ps
1386 12:14:36.072214 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1387 12:14:36.075234 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1388 12:14:36.082419 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1389 12:14:36.085322 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1390 12:14:36.088656 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1391 12:14:36.092225 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1392 12:14:36.092655
1393 12:14:36.095199 CA PerBit enable=1, Macro0, CA PI delay=34
1394 12:14:36.095626
1395 12:14:36.098882 [CBTSetCACLKResult] CA Dly = 34
1396 12:14:36.099307 CS Dly: 4 (0~35)
1397 12:14:36.102178 ==
1398 12:14:36.102606 Dram Type= 6, Freq= 0, CH_1, rank 1
1399 12:14:36.108525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 12:14:36.108957 ==
1401 12:14:36.112290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 12:14:36.118272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 12:14:36.128206 [CA 0] Center 36 (6~67) winsize 62
1404 12:14:36.131473 [CA 1] Center 36 (6~67) winsize 62
1405 12:14:36.134922 [CA 2] Center 35 (5~65) winsize 61
1406 12:14:36.138443 [CA 3] Center 34 (3~65) winsize 63
1407 12:14:36.141852 [CA 4] Center 34 (3~65) winsize 63
1408 12:14:36.144893 [CA 5] Center 34 (3~65) winsize 63
1409 12:14:36.145315
1410 12:14:36.147988 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1411 12:14:36.148109
1412 12:14:36.151320 [CATrainingPosCal] consider 2 rank data
1413 12:14:36.154435 u2DelayCellTimex100 = 270/100 ps
1414 12:14:36.158012 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 12:14:36.164274 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1416 12:14:36.168318 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1417 12:14:36.171704 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1418 12:14:36.175897 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 12:14:36.175981 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1420 12:14:36.179342
1421 12:14:36.182746 CA PerBit enable=1, Macro0, CA PI delay=34
1422 12:14:36.182830
1423 12:14:36.182896 [CBTSetCACLKResult] CA Dly = 34
1424 12:14:36.186217 CS Dly: 5 (0~37)
1425 12:14:36.186300
1426 12:14:36.189985 ----->DramcWriteLeveling(PI) begin...
1427 12:14:36.190070 ==
1428 12:14:36.193996 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 12:14:36.197401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 12:14:36.197487 ==
1431 12:14:36.201006 Write leveling (Byte 0): 29 => 29
1432 12:14:36.204345 Write leveling (Byte 1): 29 => 29
1433 12:14:36.207721 DramcWriteLeveling(PI) end<-----
1434 12:14:36.207809
1435 12:14:36.207874 ==
1436 12:14:36.211013 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:14:36.214472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:14:36.214560 ==
1439 12:14:36.217376 [Gating] SW mode calibration
1440 12:14:36.224398 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1441 12:14:36.230948 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1442 12:14:36.234158 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1443 12:14:36.237789 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1444 12:14:36.244327 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1445 12:14:36.247976 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:14:36.251499 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 12:14:36.254463 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:14:36.261346 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:14:36.264241 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:14:36.267688 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:14:36.274013 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:14:36.277883 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:14:36.281219 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:14:36.287340 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:14:36.290949 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:14:36.294308 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:14:36.300650 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:14:36.304284 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:14:36.307153 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1460 12:14:36.314378 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:14:36.317407 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:14:36.320882 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:14:36.327068 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:14:36.330621 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:14:36.334034 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:14:36.340359 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:14:36.343831 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:14:36.347422 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1469 12:14:36.353738 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 12:14:36.357174 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 12:14:36.360872 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 12:14:36.367143 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 12:14:36.370844 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 12:14:36.373659 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1475 12:14:36.380407 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
1476 12:14:36.384055 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1477 12:14:36.387283 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:14:36.394193 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:14:36.397049 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:14:36.400281 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:14:36.407410 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:14:36.410611 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:14:36.413432 0 11 4 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
1484 12:14:36.420006 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1485 12:14:36.423207 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 12:14:36.426551 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 12:14:36.429919 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 12:14:36.436266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 12:14:36.439653 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 12:14:36.443013 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 12:14:36.449432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1492 12:14:36.453107 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1493 12:14:36.456516 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 12:14:36.463020 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:14:36.465970 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:14:36.469574 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:14:36.476011 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:14:36.479583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:14:36.483103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:14:36.489420 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:14:36.493041 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:14:36.495907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:14:36.502722 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:14:36.505824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:14:36.509108 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:14:36.515799 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:14:36.519349 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1508 12:14:36.522575 Total UI for P1: 0, mck2ui 16
1509 12:14:36.525919 best dqsien dly found for B0: ( 0, 14, 2)
1510 12:14:36.529185 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:14:36.532423 Total UI for P1: 0, mck2ui 16
1512 12:14:36.535696 best dqsien dly found for B1: ( 0, 14, 6)
1513 12:14:36.539394 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1514 12:14:36.542300 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1515 12:14:36.542380
1516 12:14:36.549183 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1517 12:14:36.552314 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1518 12:14:36.552427 [Gating] SW calibration Done
1519 12:14:36.555752 ==
1520 12:14:36.555846 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 12:14:36.562571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 12:14:36.562693 ==
1523 12:14:36.562764 RX Vref Scan: 0
1524 12:14:36.562831
1525 12:14:36.565577 RX Vref 0 -> 0, step: 1
1526 12:14:36.565662
1527 12:14:36.569271 RX Delay -130 -> 252, step: 16
1528 12:14:36.572596 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1529 12:14:36.575419 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1530 12:14:36.581981 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1531 12:14:36.585334 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1532 12:14:36.588998 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1533 12:14:36.591977 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1534 12:14:36.595223 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1535 12:14:36.601951 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1536 12:14:36.605289 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1537 12:14:36.608564 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1538 12:14:36.611586 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1539 12:14:36.615255 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1540 12:14:36.621735 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1541 12:14:36.625253 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1542 12:14:36.628941 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1543 12:14:36.632376 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1544 12:14:36.632725 ==
1545 12:14:36.635210 Dram Type= 6, Freq= 0, CH_1, rank 0
1546 12:14:36.641552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1547 12:14:36.641900 ==
1548 12:14:36.642245 DQS Delay:
1549 12:14:36.645094 DQS0 = 0, DQS1 = 0
1550 12:14:36.645438 DQM Delay:
1551 12:14:36.648487 DQM0 = 88, DQM1 = 84
1552 12:14:36.648831 DQ Delay:
1553 12:14:36.651874 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1554 12:14:36.654980 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1555 12:14:36.658420 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1556 12:14:36.662125 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1557 12:14:36.662572
1558 12:14:36.663014
1559 12:14:36.663431 ==
1560 12:14:36.665005 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 12:14:36.668571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 12:14:36.669018 ==
1563 12:14:36.669459
1564 12:14:36.669873
1565 12:14:36.671332 TX Vref Scan disable
1566 12:14:36.675050 == TX Byte 0 ==
1567 12:14:36.678099 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1568 12:14:36.681545 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1569 12:14:36.684869 == TX Byte 1 ==
1570 12:14:36.687830 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1571 12:14:36.691352 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1572 12:14:36.691823 ==
1573 12:14:36.694481 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 12:14:36.701640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 12:14:36.702103 ==
1576 12:14:36.712516 TX Vref=22, minBit 6, minWin=26, winSum=442
1577 12:14:36.715926 TX Vref=24, minBit 0, minWin=27, winSum=448
1578 12:14:36.719098 TX Vref=26, minBit 1, minWin=27, winSum=448
1579 12:14:36.722461 TX Vref=28, minBit 1, minWin=27, winSum=453
1580 12:14:36.726120 TX Vref=30, minBit 1, minWin=27, winSum=455
1581 12:14:36.729160 TX Vref=32, minBit 0, minWin=27, winSum=450
1582 12:14:36.735694 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 30
1583 12:14:36.736162
1584 12:14:36.739675 Final TX Range 1 Vref 30
1585 12:14:36.740159
1586 12:14:36.740620 ==
1587 12:14:36.742445 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 12:14:36.746329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 12:14:36.746774 ==
1590 12:14:36.747218
1591 12:14:36.747632
1592 12:14:36.749830 TX Vref Scan disable
1593 12:14:36.753407 == TX Byte 0 ==
1594 12:14:36.756282 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1595 12:14:36.759681 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1596 12:14:36.763146 == TX Byte 1 ==
1597 12:14:36.766568 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1598 12:14:36.769492 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1599 12:14:36.769956
1600 12:14:36.773566 [DATLAT]
1601 12:14:36.774099 Freq=800, CH1 RK0
1602 12:14:36.774482
1603 12:14:36.776442 DATLAT Default: 0xa
1604 12:14:36.776962 0, 0xFFFF, sum = 0
1605 12:14:36.779957 1, 0xFFFF, sum = 0
1606 12:14:36.780548 2, 0xFFFF, sum = 0
1607 12:14:36.783633 3, 0xFFFF, sum = 0
1608 12:14:36.784232 4, 0xFFFF, sum = 0
1609 12:14:36.786566 5, 0xFFFF, sum = 0
1610 12:14:36.787085 6, 0xFFFF, sum = 0
1611 12:14:36.790095 7, 0xFFFF, sum = 0
1612 12:14:36.790553 8, 0xFFFF, sum = 0
1613 12:14:36.792901 9, 0x0, sum = 1
1614 12:14:36.793333 10, 0x0, sum = 2
1615 12:14:36.796444 11, 0x0, sum = 3
1616 12:14:36.796939 12, 0x0, sum = 4
1617 12:14:36.800017 best_step = 10
1618 12:14:36.800482
1619 12:14:36.800819 ==
1620 12:14:36.803338 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 12:14:36.806704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 12:14:36.807231 ==
1623 12:14:36.809920 RX Vref Scan: 1
1624 12:14:36.810490
1625 12:14:36.810898 Set Vref Range= 32 -> 127
1626 12:14:36.811281
1627 12:14:36.813317 RX Vref 32 -> 127, step: 1
1628 12:14:36.813734
1629 12:14:36.816155 RX Delay -95 -> 252, step: 8
1630 12:14:36.816563
1631 12:14:36.819644 Set Vref, RX VrefLevel [Byte0]: 32
1632 12:14:36.823110 [Byte1]: 32
1633 12:14:36.823676
1634 12:14:36.826443 Set Vref, RX VrefLevel [Byte0]: 33
1635 12:14:36.829220 [Byte1]: 33
1636 12:14:36.832784
1637 12:14:36.833216 Set Vref, RX VrefLevel [Byte0]: 34
1638 12:14:36.836111 [Byte1]: 34
1639 12:14:36.840541
1640 12:14:36.841111 Set Vref, RX VrefLevel [Byte0]: 35
1641 12:14:36.843582 [Byte1]: 35
1642 12:14:36.847483
1643 12:14:36.847583 Set Vref, RX VrefLevel [Byte0]: 36
1644 12:14:36.851022 [Byte1]: 36
1645 12:14:36.855016
1646 12:14:36.855138 Set Vref, RX VrefLevel [Byte0]: 37
1647 12:14:36.858594 [Byte1]: 37
1648 12:14:36.863113
1649 12:14:36.863217 Set Vref, RX VrefLevel [Byte0]: 38
1650 12:14:36.865920 [Byte1]: 38
1651 12:14:36.870697
1652 12:14:36.870798 Set Vref, RX VrefLevel [Byte0]: 39
1653 12:14:36.873784 [Byte1]: 39
1654 12:14:36.877957
1655 12:14:36.878040 Set Vref, RX VrefLevel [Byte0]: 40
1656 12:14:36.881421 [Byte1]: 40
1657 12:14:36.885420
1658 12:14:36.885530 Set Vref, RX VrefLevel [Byte0]: 41
1659 12:14:36.889027 [Byte1]: 41
1660 12:14:36.893036
1661 12:14:36.893157 Set Vref, RX VrefLevel [Byte0]: 42
1662 12:14:36.896615 [Byte1]: 42
1663 12:14:36.900533
1664 12:14:36.900643 Set Vref, RX VrefLevel [Byte0]: 43
1665 12:14:36.904163 [Byte1]: 43
1666 12:14:36.908192
1667 12:14:36.908304 Set Vref, RX VrefLevel [Byte0]: 44
1668 12:14:36.911690 [Byte1]: 44
1669 12:14:36.916055
1670 12:14:36.916154 Set Vref, RX VrefLevel [Byte0]: 45
1671 12:14:36.919400 [Byte1]: 45
1672 12:14:36.923447
1673 12:14:36.923531 Set Vref, RX VrefLevel [Byte0]: 46
1674 12:14:36.926975 [Byte1]: 46
1675 12:14:36.931402
1676 12:14:36.931486 Set Vref, RX VrefLevel [Byte0]: 47
1677 12:14:36.934633 [Byte1]: 47
1678 12:14:36.938802
1679 12:14:36.938885 Set Vref, RX VrefLevel [Byte0]: 48
1680 12:14:36.942102 [Byte1]: 48
1681 12:14:36.946546
1682 12:14:36.946630 Set Vref, RX VrefLevel [Byte0]: 49
1683 12:14:36.949792 [Byte1]: 49
1684 12:14:36.953863
1685 12:14:36.953971 Set Vref, RX VrefLevel [Byte0]: 50
1686 12:14:36.957413 [Byte1]: 50
1687 12:14:36.961633
1688 12:14:36.961720 Set Vref, RX VrefLevel [Byte0]: 51
1689 12:14:36.964928 [Byte1]: 51
1690 12:14:36.969367
1691 12:14:36.969487 Set Vref, RX VrefLevel [Byte0]: 52
1692 12:14:36.972249 [Byte1]: 52
1693 12:14:36.976513
1694 12:14:36.976628 Set Vref, RX VrefLevel [Byte0]: 53
1695 12:14:36.979955 [Byte1]: 53
1696 12:14:36.984596
1697 12:14:36.984704 Set Vref, RX VrefLevel [Byte0]: 54
1698 12:14:36.987619 [Byte1]: 54
1699 12:14:36.992342
1700 12:14:36.992449 Set Vref, RX VrefLevel [Byte0]: 55
1701 12:14:36.995172 [Byte1]: 55
1702 12:14:36.999527
1703 12:14:36.999632 Set Vref, RX VrefLevel [Byte0]: 56
1704 12:14:37.002920 [Byte1]: 56
1705 12:14:37.007158
1706 12:14:37.007266 Set Vref, RX VrefLevel [Byte0]: 57
1707 12:14:37.010725 [Byte1]: 57
1708 12:14:37.014675
1709 12:14:37.014762 Set Vref, RX VrefLevel [Byte0]: 58
1710 12:14:37.018223 [Byte1]: 58
1711 12:14:37.022190
1712 12:14:37.022299 Set Vref, RX VrefLevel [Byte0]: 59
1713 12:14:37.025658 [Byte1]: 59
1714 12:14:37.030196
1715 12:14:37.030284 Set Vref, RX VrefLevel [Byte0]: 60
1716 12:14:37.033758 [Byte1]: 60
1717 12:14:37.037480
1718 12:14:37.037582 Set Vref, RX VrefLevel [Byte0]: 61
1719 12:14:37.041035 [Byte1]: 61
1720 12:14:37.045175
1721 12:14:37.045252 Set Vref, RX VrefLevel [Byte0]: 62
1722 12:14:37.048772 [Byte1]: 62
1723 12:14:37.053395
1724 12:14:37.053828 Set Vref, RX VrefLevel [Byte0]: 63
1725 12:14:37.056623 [Byte1]: 63
1726 12:14:37.060740
1727 12:14:37.061170 Set Vref, RX VrefLevel [Byte0]: 64
1728 12:14:37.064327 [Byte1]: 64
1729 12:14:37.068475
1730 12:14:37.069008 Set Vref, RX VrefLevel [Byte0]: 65
1731 12:14:37.071684 [Byte1]: 65
1732 12:14:37.076329
1733 12:14:37.076775 Set Vref, RX VrefLevel [Byte0]: 66
1734 12:14:37.079250 [Byte1]: 66
1735 12:14:37.083381
1736 12:14:37.083958 Set Vref, RX VrefLevel [Byte0]: 67
1737 12:14:37.087005 [Byte1]: 67
1738 12:14:37.090859
1739 12:14:37.091420 Set Vref, RX VrefLevel [Byte0]: 68
1740 12:14:37.094491 [Byte1]: 68
1741 12:14:37.099078
1742 12:14:37.099568 Set Vref, RX VrefLevel [Byte0]: 69
1743 12:14:37.101727 [Byte1]: 69
1744 12:14:37.106487
1745 12:14:37.107091 Set Vref, RX VrefLevel [Byte0]: 70
1746 12:14:37.109548 [Byte1]: 70
1747 12:14:37.114208
1748 12:14:37.114761 Set Vref, RX VrefLevel [Byte0]: 71
1749 12:14:37.117171 [Byte1]: 71
1750 12:14:37.122021
1751 12:14:37.122451 Set Vref, RX VrefLevel [Byte0]: 72
1752 12:14:37.124616 [Byte1]: 72
1753 12:14:37.129059
1754 12:14:37.129479 Set Vref, RX VrefLevel [Byte0]: 73
1755 12:14:37.132625 [Byte1]: 73
1756 12:14:37.136683
1757 12:14:37.137115 Set Vref, RX VrefLevel [Byte0]: 74
1758 12:14:37.140006 [Byte1]: 74
1759 12:14:37.144479
1760 12:14:37.144937 Set Vref, RX VrefLevel [Byte0]: 75
1761 12:14:37.147707 [Byte1]: 75
1762 12:14:37.151775
1763 12:14:37.152322 Final RX Vref Byte 0 = 57 to rank0
1764 12:14:37.155174 Final RX Vref Byte 1 = 53 to rank0
1765 12:14:37.158440 Final RX Vref Byte 0 = 57 to rank1
1766 12:14:37.161851 Final RX Vref Byte 1 = 53 to rank1==
1767 12:14:37.165413 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 12:14:37.171730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 12:14:37.172209 ==
1770 12:14:37.172568 DQS Delay:
1771 12:14:37.172889 DQS0 = 0, DQS1 = 0
1772 12:14:37.175292 DQM Delay:
1773 12:14:37.175722 DQM0 = 85, DQM1 = 80
1774 12:14:37.178543 DQ Delay:
1775 12:14:37.181545 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1776 12:14:37.184889 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1777 12:14:37.184973 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1778 12:14:37.191891 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1779 12:14:37.192102
1780 12:14:37.192199
1781 12:14:37.198458 [DQSOSCAuto] RK0, (LSB)MR18= 0x1326, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
1782 12:14:37.201242 CH1 RK0: MR19=606, MR18=1326
1783 12:14:37.208293 CH1_RK0: MR19=0x606, MR18=0x1326, DQSOSC=400, MR23=63, INC=92, DEC=61
1784 12:14:37.208420
1785 12:14:37.211105 ----->DramcWriteLeveling(PI) begin...
1786 12:14:37.211253 ==
1787 12:14:37.214616 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 12:14:37.218086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 12:14:37.218244 ==
1790 12:14:37.221148 Write leveling (Byte 0): 27 => 27
1791 12:14:37.224529 Write leveling (Byte 1): 28 => 28
1792 12:14:37.228061 DramcWriteLeveling(PI) end<-----
1793 12:14:37.228292
1794 12:14:37.228461 ==
1795 12:14:37.231506 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 12:14:37.235016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 12:14:37.235265 ==
1798 12:14:37.237874 [Gating] SW mode calibration
1799 12:14:37.244650 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 12:14:37.251078 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 12:14:37.254482 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1802 12:14:37.261305 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1803 12:14:37.264573 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 12:14:37.268008 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:14:37.270994 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:14:37.277816 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:14:37.281144 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:14:37.284748 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:14:37.291212 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:14:37.294139 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:14:37.297609 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:14:37.304138 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:14:37.307603 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:14:37.310841 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:14:37.317201 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:14:37.320494 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:14:37.323678 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1818 12:14:37.330669 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1819 12:14:37.334201 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1820 12:14:37.337058 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:14:37.343797 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:14:37.347136 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:14:37.350695 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:14:37.357143 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:14:37.360484 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:14:37.363819 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1827 12:14:37.370170 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1828 12:14:37.373517 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 12:14:37.377194 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 12:14:37.383587 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 12:14:37.387081 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 12:14:37.390038 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 12:14:37.396937 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:14:37.400026 0 10 4 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 0)
1835 12:14:37.403505 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1836 12:14:37.410462 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:14:37.414038 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:14:37.417054 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:14:37.423229 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:14:37.426789 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:14:37.430243 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:14:37.436669 0 11 4 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
1843 12:14:37.440164 0 11 8 | B1->B0 | 3635 4646 | 1 0 | (0 0) (0 0)
1844 12:14:37.443556 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 12:14:37.449985 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 12:14:37.453346 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 12:14:37.456732 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 12:14:37.463359 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 12:14:37.466862 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1850 12:14:37.470314 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1851 12:14:37.473785 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1852 12:14:37.480318 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:14:37.483339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:14:37.486856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:14:37.493605 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:14:37.496641 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:14:37.500185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:14:37.506143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:14:37.509493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:14:37.513167 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:14:37.519410 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:14:37.523366 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:14:37.526455 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:14:37.532919 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:14:37.535852 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1866 12:14:37.539378 Total UI for P1: 0, mck2ui 16
1867 12:14:37.542783 best dqsien dly found for B0: ( 0, 13, 30)
1868 12:14:37.545596 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1869 12:14:37.552616 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1870 12:14:37.555930 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:14:37.559475 Total UI for P1: 0, mck2ui 16
1872 12:14:37.562185 best dqsien dly found for B1: ( 0, 14, 8)
1873 12:14:37.565544 best DQS0 dly(MCK, UI, PI) = (0, 13, 30)
1874 12:14:37.569072 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1875 12:14:37.569555
1876 12:14:37.572449 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 30)
1877 12:14:37.578965 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1878 12:14:37.579467 [Gating] SW calibration Done
1879 12:14:37.579807 ==
1880 12:14:37.582243 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 12:14:37.589143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 12:14:37.589631 ==
1883 12:14:37.589977 RX Vref Scan: 0
1884 12:14:37.590292
1885 12:14:37.591911 RX Vref 0 -> 0, step: 1
1886 12:14:37.592432
1887 12:14:37.595323 RX Delay -130 -> 252, step: 16
1888 12:14:37.598701 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1889 12:14:37.601611 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1890 12:14:37.605205 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1891 12:14:37.611610 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1892 12:14:37.614958 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1893 12:14:37.618504 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1894 12:14:37.621379 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1895 12:14:37.624809 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1896 12:14:37.631209 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1897 12:14:37.634743 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1898 12:14:37.638392 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1899 12:14:37.641179 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1900 12:14:37.647680 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1901 12:14:37.651123 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1902 12:14:37.654483 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1903 12:14:37.658197 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1904 12:14:37.658717 ==
1905 12:14:37.661091 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 12:14:37.667749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 12:14:37.668321 ==
1908 12:14:37.668794 DQS Delay:
1909 12:14:37.671146 DQS0 = 0, DQS1 = 0
1910 12:14:37.671550 DQM Delay:
1911 12:14:37.671865 DQM0 = 83, DQM1 = 80
1912 12:14:37.674076 DQ Delay:
1913 12:14:37.677373 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1914 12:14:37.680849 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1915 12:14:37.683960 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1916 12:14:37.687362 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1917 12:14:37.687793
1918 12:14:37.688169
1919 12:14:37.688521 ==
1920 12:14:37.690985 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 12:14:37.694437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 12:14:37.694864 ==
1923 12:14:37.695201
1924 12:14:37.695510
1925 12:14:37.697197 TX Vref Scan disable
1926 12:14:37.700713 == TX Byte 0 ==
1927 12:14:37.704189 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1928 12:14:37.707630 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1929 12:14:37.710704 == TX Byte 1 ==
1930 12:14:37.714279 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1931 12:14:37.717153 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1932 12:14:37.717579 ==
1933 12:14:37.720483 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 12:14:37.724085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 12:14:37.724513 ==
1936 12:14:37.738512 TX Vref=22, minBit 1, minWin=27, winSum=449
1937 12:14:37.741225 TX Vref=24, minBit 1, minWin=27, winSum=452
1938 12:14:37.744668 TX Vref=26, minBit 1, minWin=27, winSum=451
1939 12:14:37.748153 TX Vref=28, minBit 1, minWin=27, winSum=452
1940 12:14:37.751749 TX Vref=30, minBit 0, minWin=28, winSum=456
1941 12:14:37.758012 TX Vref=32, minBit 1, minWin=27, winSum=452
1942 12:14:37.761374 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1943 12:14:37.761797
1944 12:14:37.765063 Final TX Range 1 Vref 30
1945 12:14:37.765486
1946 12:14:37.765823 ==
1947 12:14:37.767854 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 12:14:37.771636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 12:14:37.772093 ==
1950 12:14:37.772436
1951 12:14:37.774645
1952 12:14:37.775065 TX Vref Scan disable
1953 12:14:37.778148 == TX Byte 0 ==
1954 12:14:37.781516 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1955 12:14:37.784771 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1956 12:14:37.787983 == TX Byte 1 ==
1957 12:14:37.791394 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1958 12:14:37.794980 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1959 12:14:37.797963
1960 12:14:37.798400 [DATLAT]
1961 12:14:37.798746 Freq=800, CH1 RK1
1962 12:14:37.799222
1963 12:14:37.801445 DATLAT Default: 0xa
1964 12:14:37.801869 0, 0xFFFF, sum = 0
1965 12:14:37.804786 1, 0xFFFF, sum = 0
1966 12:14:37.805218 2, 0xFFFF, sum = 0
1967 12:14:37.808089 3, 0xFFFF, sum = 0
1968 12:14:37.808524 4, 0xFFFF, sum = 0
1969 12:14:37.811076 5, 0xFFFF, sum = 0
1970 12:14:37.814530 6, 0xFFFF, sum = 0
1971 12:14:37.814962 7, 0xFFFF, sum = 0
1972 12:14:37.817973 8, 0xFFFF, sum = 0
1973 12:14:37.818654 9, 0x0, sum = 1
1974 12:14:37.821470 10, 0x0, sum = 2
1975 12:14:37.822034 11, 0x0, sum = 3
1976 12:14:37.822578 12, 0x0, sum = 4
1977 12:14:37.824547 best_step = 10
1978 12:14:37.825147
1979 12:14:37.825697 ==
1980 12:14:37.827900 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:14:37.831264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:14:37.831699 ==
1983 12:14:37.835096 RX Vref Scan: 0
1984 12:14:37.835518
1985 12:14:37.835851 RX Vref 0 -> 0, step: 1
1986 12:14:37.837738
1987 12:14:37.838158 RX Delay -95 -> 252, step: 8
1988 12:14:37.844751 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1989 12:14:37.848286 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1990 12:14:37.851140 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1991 12:14:37.854863 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1992 12:14:37.858372 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1993 12:14:37.864667 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1994 12:14:37.868200 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1995 12:14:37.871680 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1996 12:14:37.874414 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1997 12:14:37.877809 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1998 12:14:37.884672 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1999 12:14:37.887975 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2000 12:14:37.891304 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2001 12:14:37.894617 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2002 12:14:37.901002 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2003 12:14:37.904561 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2004 12:14:37.904992 ==
2005 12:14:37.907457 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 12:14:37.910669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 12:14:37.911127 ==
2008 12:14:37.914320 DQS Delay:
2009 12:14:37.914749 DQS0 = 0, DQS1 = 0
2010 12:14:37.915091 DQM Delay:
2011 12:14:37.917329 DQM0 = 87, DQM1 = 82
2012 12:14:37.917758 DQ Delay:
2013 12:14:37.920780 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2014 12:14:37.924430 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2015 12:14:37.927157 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2016 12:14:37.930604 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2017 12:14:37.931093
2018 12:14:37.931496
2019 12:14:37.940200 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2020 12:14:37.943683 CH1 RK1: MR19=606, MR18=1C38
2021 12:14:37.946662 CH1_RK1: MR19=0x606, MR18=0x1C38, DQSOSC=395, MR23=63, INC=94, DEC=63
2022 12:14:37.950097 [RxdqsGatingPostProcess] freq 800
2023 12:14:37.956681 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 12:14:37.960152 Pre-setting of DQS Precalculation
2025 12:14:37.963530 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 12:14:37.973344 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 12:14:37.980095 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 12:14:37.980534
2029 12:14:37.980877
2030 12:14:37.983604 [Calibration Summary] 1600 Mbps
2031 12:14:37.984072 CH 0, Rank 0
2032 12:14:37.986901 SW Impedance : PASS
2033 12:14:37.987331 DUTY Scan : NO K
2034 12:14:37.990258 ZQ Calibration : PASS
2035 12:14:37.993639 Jitter Meter : NO K
2036 12:14:37.994073 CBT Training : PASS
2037 12:14:37.996777 Write leveling : PASS
2038 12:14:38.000329 RX DQS gating : PASS
2039 12:14:38.000759 RX DQ/DQS(RDDQC) : PASS
2040 12:14:38.003063 TX DQ/DQS : PASS
2041 12:14:38.006503 RX DATLAT : PASS
2042 12:14:38.006932 RX DQ/DQS(Engine): PASS
2043 12:14:38.010043 TX OE : NO K
2044 12:14:38.010542 All Pass.
2045 12:14:38.010926
2046 12:14:38.013449 CH 0, Rank 1
2047 12:14:38.013885 SW Impedance : PASS
2048 12:14:38.016264 DUTY Scan : NO K
2049 12:14:38.019795 ZQ Calibration : PASS
2050 12:14:38.020279 Jitter Meter : NO K
2051 12:14:38.023224 CBT Training : PASS
2052 12:14:38.026128 Write leveling : PASS
2053 12:14:38.026594 RX DQS gating : PASS
2054 12:14:38.029634 RX DQ/DQS(RDDQC) : PASS
2055 12:14:38.030056 TX DQ/DQS : PASS
2056 12:14:38.033160 RX DATLAT : PASS
2057 12:14:38.036840 RX DQ/DQS(Engine): PASS
2058 12:14:38.037264 TX OE : NO K
2059 12:14:38.039440 All Pass.
2060 12:14:38.039861
2061 12:14:38.040268 CH 1, Rank 0
2062 12:14:38.043047 SW Impedance : PASS
2063 12:14:38.043468 DUTY Scan : NO K
2064 12:14:38.046524 ZQ Calibration : PASS
2065 12:14:38.049876 Jitter Meter : NO K
2066 12:14:38.050297 CBT Training : PASS
2067 12:14:38.052954 Write leveling : PASS
2068 12:14:38.056492 RX DQS gating : PASS
2069 12:14:38.056915 RX DQ/DQS(RDDQC) : PASS
2070 12:14:38.059937 TX DQ/DQS : PASS
2071 12:14:38.062800 RX DATLAT : PASS
2072 12:14:38.063261 RX DQ/DQS(Engine): PASS
2073 12:14:38.066298 TX OE : NO K
2074 12:14:38.066722 All Pass.
2075 12:14:38.067058
2076 12:14:38.069354 CH 1, Rank 1
2077 12:14:38.069775 SW Impedance : PASS
2078 12:14:38.072755 DUTY Scan : NO K
2079 12:14:38.076109 ZQ Calibration : PASS
2080 12:14:38.076534 Jitter Meter : NO K
2081 12:14:38.079529 CBT Training : PASS
2082 12:14:38.079954 Write leveling : PASS
2083 12:14:38.082971 RX DQS gating : PASS
2084 12:14:38.086334 RX DQ/DQS(RDDQC) : PASS
2085 12:14:38.086757 TX DQ/DQS : PASS
2086 12:14:38.089777 RX DATLAT : PASS
2087 12:14:38.093029 RX DQ/DQS(Engine): PASS
2088 12:14:38.093451 TX OE : NO K
2089 12:14:38.096639 All Pass.
2090 12:14:38.097058
2091 12:14:38.097392 DramC Write-DBI off
2092 12:14:38.099243 PER_BANK_REFRESH: Hybrid Mode
2093 12:14:38.102606 TX_TRACKING: ON
2094 12:14:38.105943 [GetDramInforAfterCalByMRR] Vendor 6.
2095 12:14:38.109599 [GetDramInforAfterCalByMRR] Revision 606.
2096 12:14:38.113154 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 12:14:38.113574 MR0 0x3b3b
2098 12:14:38.113954 MR8 0x5151
2099 12:14:38.119269 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 12:14:38.119693
2101 12:14:38.120058 MR0 0x3b3b
2102 12:14:38.120518 MR8 0x5151
2103 12:14:38.122794 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 12:14:38.123218
2105 12:14:38.132794 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 12:14:38.136188 [FAST_K] Save calibration result to emmc
2107 12:14:38.139444 [FAST_K] Save calibration result to emmc
2108 12:14:38.142411 dram_init: config_dvfs: 1
2109 12:14:38.145893 dramc_set_vcore_voltage set vcore to 662500
2110 12:14:38.148917 Read voltage for 1200, 2
2111 12:14:38.149344 Vio18 = 0
2112 12:14:38.149685 Vcore = 662500
2113 12:14:38.152387 Vdram = 0
2114 12:14:38.152811 Vddq = 0
2115 12:14:38.153147 Vmddr = 0
2116 12:14:38.159248 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 12:14:38.162297 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 12:14:38.165639 MEM_TYPE=3, freq_sel=15
2119 12:14:38.169321 sv_algorithm_assistance_LP4_1600
2120 12:14:38.172177 ============ PULL DRAM RESETB DOWN ============
2121 12:14:38.178608 ========== PULL DRAM RESETB DOWN end =========
2122 12:14:38.182061 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 12:14:38.185371 ===================================
2124 12:14:38.188871 LPDDR4 DRAM CONFIGURATION
2125 12:14:38.192204 ===================================
2126 12:14:38.192714 EX_ROW_EN[0] = 0x0
2127 12:14:38.195751 EX_ROW_EN[1] = 0x0
2128 12:14:38.196218 LP4Y_EN = 0x0
2129 12:14:38.199012 WORK_FSP = 0x0
2130 12:14:38.199435 WL = 0x4
2131 12:14:38.202238 RL = 0x4
2132 12:14:38.202662 BL = 0x2
2133 12:14:38.205603 RPST = 0x0
2134 12:14:38.206033 RD_PRE = 0x0
2135 12:14:38.208931 WR_PRE = 0x1
2136 12:14:38.209361 WR_PST = 0x0
2137 12:14:38.211791 DBI_WR = 0x0
2138 12:14:38.215316 DBI_RD = 0x0
2139 12:14:38.215746 OTF = 0x1
2140 12:14:38.218754 ===================================
2141 12:14:38.222358 ===================================
2142 12:14:38.223030 ANA top config
2143 12:14:38.225713 ===================================
2144 12:14:38.229221 DLL_ASYNC_EN = 0
2145 12:14:38.232297 ALL_SLAVE_EN = 0
2146 12:14:38.235580 NEW_RANK_MODE = 1
2147 12:14:38.238909 DLL_IDLE_MODE = 1
2148 12:14:38.239590 LP45_APHY_COMB_EN = 1
2149 12:14:38.241706 TX_ODT_DIS = 1
2150 12:14:38.245310 NEW_8X_MODE = 1
2151 12:14:38.248677 ===================================
2152 12:14:38.251695 ===================================
2153 12:14:38.255415 data_rate = 2400
2154 12:14:38.258214 CKR = 1
2155 12:14:38.258653 DQ_P2S_RATIO = 8
2156 12:14:38.261556 ===================================
2157 12:14:38.265071 CA_P2S_RATIO = 8
2158 12:14:38.268471 DQ_CA_OPEN = 0
2159 12:14:38.271989 DQ_SEMI_OPEN = 0
2160 12:14:38.274960 CA_SEMI_OPEN = 0
2161 12:14:38.278525 CA_FULL_RATE = 0
2162 12:14:38.278908 DQ_CKDIV4_EN = 0
2163 12:14:38.281360 CA_CKDIV4_EN = 0
2164 12:14:38.284919 CA_PREDIV_EN = 0
2165 12:14:38.288185 PH8_DLY = 17
2166 12:14:38.291592 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 12:14:38.295158 DQ_AAMCK_DIV = 4
2168 12:14:38.295536 CA_AAMCK_DIV = 4
2169 12:14:38.298107 CA_ADMCK_DIV = 4
2170 12:14:38.301562 DQ_TRACK_CA_EN = 0
2171 12:14:38.304925 CA_PICK = 1200
2172 12:14:38.308261 CA_MCKIO = 1200
2173 12:14:38.311517 MCKIO_SEMI = 0
2174 12:14:38.314795 PLL_FREQ = 2366
2175 12:14:38.318272 DQ_UI_PI_RATIO = 32
2176 12:14:38.318845 CA_UI_PI_RATIO = 0
2177 12:14:38.321298 ===================================
2178 12:14:38.324820 ===================================
2179 12:14:38.328136 memory_type:LPDDR4
2180 12:14:38.331316 GP_NUM : 10
2181 12:14:38.331905 SRAM_EN : 1
2182 12:14:38.334665 MD32_EN : 0
2183 12:14:38.338161 ===================================
2184 12:14:38.340904 [ANA_INIT] >>>>>>>>>>>>>>
2185 12:14:38.344270 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 12:14:38.347686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 12:14:38.351217 ===================================
2188 12:14:38.351656 data_rate = 2400,PCW = 0X5b00
2189 12:14:38.354256 ===================================
2190 12:14:38.357348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 12:14:38.363855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 12:14:38.370498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 12:14:38.373790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 12:14:38.376944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 12:14:38.380571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 12:14:38.383530 [ANA_INIT] flow start
2197 12:14:38.386967 [ANA_INIT] PLL >>>>>>>>
2198 12:14:38.387057 [ANA_INIT] PLL <<<<<<<<
2199 12:14:38.390557 [ANA_INIT] MIDPI >>>>>>>>
2200 12:14:38.393968 [ANA_INIT] MIDPI <<<<<<<<
2201 12:14:38.394065 [ANA_INIT] DLL >>>>>>>>
2202 12:14:38.397448 [ANA_INIT] DLL <<<<<<<<
2203 12:14:38.400845 [ANA_INIT] flow end
2204 12:14:38.403628 ============ LP4 DIFF to SE enter ============
2205 12:14:38.407080 ============ LP4 DIFF to SE exit ============
2206 12:14:38.410398 [ANA_INIT] <<<<<<<<<<<<<
2207 12:14:38.414012 [Flow] Enable top DCM control >>>>>
2208 12:14:38.416842 [Flow] Enable top DCM control <<<<<
2209 12:14:38.420047 Enable DLL master slave shuffle
2210 12:14:38.423817 ==============================================================
2211 12:14:38.427223 Gating Mode config
2212 12:14:38.433747 ==============================================================
2213 12:14:38.433999 Config description:
2214 12:14:38.443420 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 12:14:38.450271 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 12:14:38.453338 SELPH_MODE 0: By rank 1: By Phase
2217 12:14:38.459762 ==============================================================
2218 12:14:38.463347 GAT_TRACK_EN = 1
2219 12:14:38.466872 RX_GATING_MODE = 2
2220 12:14:38.469742 RX_GATING_TRACK_MODE = 2
2221 12:14:38.473208 SELPH_MODE = 1
2222 12:14:38.476803 PICG_EARLY_EN = 1
2223 12:14:38.479638 VALID_LAT_VALUE = 1
2224 12:14:38.483142 ==============================================================
2225 12:14:38.486143 Enter into Gating configuration >>>>
2226 12:14:38.489921 Exit from Gating configuration <<<<
2227 12:14:38.493251 Enter into DVFS_PRE_config >>>>>
2228 12:14:38.506204 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 12:14:38.509176 Exit from DVFS_PRE_config <<<<<
2230 12:14:38.512494 Enter into PICG configuration >>>>
2231 12:14:38.512627 Exit from PICG configuration <<<<
2232 12:14:38.515774 [RX_INPUT] configuration >>>>>
2233 12:14:38.519081 [RX_INPUT] configuration <<<<<
2234 12:14:38.525936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 12:14:38.529544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 12:14:38.535765 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 12:14:38.542117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 12:14:38.548908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 12:14:38.555441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 12:14:38.559096 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 12:14:38.562156 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 12:14:38.569083 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 12:14:38.572199 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 12:14:38.575503 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 12:14:38.579132 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 12:14:38.585669 ===================================
2247 12:14:38.586160 LPDDR4 DRAM CONFIGURATION
2248 12:14:38.588520 ===================================
2249 12:14:38.591909 EX_ROW_EN[0] = 0x0
2250 12:14:38.592499 EX_ROW_EN[1] = 0x0
2251 12:14:38.595296 LP4Y_EN = 0x0
2252 12:14:38.595819 WORK_FSP = 0x0
2253 12:14:38.598784 WL = 0x4
2254 12:14:38.599215 RL = 0x4
2255 12:14:38.602148 BL = 0x2
2256 12:14:38.605124 RPST = 0x0
2257 12:14:38.605616 RD_PRE = 0x0
2258 12:14:38.608314 WR_PRE = 0x1
2259 12:14:38.608810 WR_PST = 0x0
2260 12:14:38.611524 DBI_WR = 0x0
2261 12:14:38.611977 DBI_RD = 0x0
2262 12:14:38.614996 OTF = 0x1
2263 12:14:38.618496 ===================================
2264 12:14:38.621879 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 12:14:38.624742 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 12:14:38.628214 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 12:14:38.631530 ===================================
2268 12:14:38.635079 LPDDR4 DRAM CONFIGURATION
2269 12:14:38.638000 ===================================
2270 12:14:38.641558 EX_ROW_EN[0] = 0x10
2271 12:14:38.641996 EX_ROW_EN[1] = 0x0
2272 12:14:38.645142 LP4Y_EN = 0x0
2273 12:14:38.645565 WORK_FSP = 0x0
2274 12:14:38.648314 WL = 0x4
2275 12:14:38.648793 RL = 0x4
2276 12:14:38.651666 BL = 0x2
2277 12:14:38.652190 RPST = 0x0
2278 12:14:38.654697 RD_PRE = 0x0
2279 12:14:38.658217 WR_PRE = 0x1
2280 12:14:38.658694 WR_PST = 0x0
2281 12:14:38.661756 DBI_WR = 0x0
2282 12:14:38.662254 DBI_RD = 0x0
2283 12:14:38.664468 OTF = 0x1
2284 12:14:38.668000 ===================================
2285 12:14:38.671509 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 12:14:38.674839 ==
2287 12:14:38.675302 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 12:14:38.681268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 12:14:38.681770 ==
2290 12:14:38.684834 [Duty_Offset_Calibration]
2291 12:14:38.685254 B0:2 B1:0 CA:4
2292 12:14:38.685670
2293 12:14:38.687731 [DutyScan_Calibration_Flow] k_type=0
2294 12:14:38.697309
2295 12:14:38.697773 ==CLK 0==
2296 12:14:38.700670 Final CLK duty delay cell = 0
2297 12:14:38.704179 [0] MAX Duty = 5156%(X100), DQS PI = 14
2298 12:14:38.707610 [0] MIN Duty = 4969%(X100), DQS PI = 8
2299 12:14:38.708234 [0] AVG Duty = 5062%(X100)
2300 12:14:38.710515
2301 12:14:38.713823 CH0 CLK Duty spec in!! Max-Min= 187%
2302 12:14:38.717099 [DutyScan_Calibration_Flow] ====Done====
2303 12:14:38.717557
2304 12:14:38.720529 [DutyScan_Calibration_Flow] k_type=1
2305 12:14:38.735838
2306 12:14:38.736325 ==DQS 0 ==
2307 12:14:38.739390 Final DQS duty delay cell = -4
2308 12:14:38.742870 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2309 12:14:38.745844 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2310 12:14:38.749331 [-4] AVG Duty = 4922%(X100)
2311 12:14:38.749835
2312 12:14:38.750172 ==DQS 1 ==
2313 12:14:38.752657 Final DQS duty delay cell = 0
2314 12:14:38.755871 [0] MAX Duty = 5125%(X100), DQS PI = 4
2315 12:14:38.758755 [0] MIN Duty = 5000%(X100), DQS PI = 0
2316 12:14:38.762249 [0] AVG Duty = 5062%(X100)
2317 12:14:38.762666
2318 12:14:38.765699 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2319 12:14:38.766117
2320 12:14:38.768750 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2321 12:14:38.772403 [DutyScan_Calibration_Flow] ====Done====
2322 12:14:38.773001
2323 12:14:38.775254 [DutyScan_Calibration_Flow] k_type=3
2324 12:14:38.792268
2325 12:14:38.792741 ==DQM 0 ==
2326 12:14:38.795650 Final DQM duty delay cell = 0
2327 12:14:38.799324 [0] MAX Duty = 5125%(X100), DQS PI = 20
2328 12:14:38.802340 [0] MIN Duty = 4844%(X100), DQS PI = 52
2329 12:14:38.802848 [0] AVG Duty = 4984%(X100)
2330 12:14:38.805781
2331 12:14:38.806281 ==DQM 1 ==
2332 12:14:38.809328 Final DQM duty delay cell = 0
2333 12:14:38.812687 [0] MAX Duty = 4969%(X100), DQS PI = 2
2334 12:14:38.815510 [0] MIN Duty = 4907%(X100), DQS PI = 12
2335 12:14:38.815962 [0] AVG Duty = 4938%(X100)
2336 12:14:38.819360
2337 12:14:38.822133 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2338 12:14:38.822554
2339 12:14:38.825487 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2340 12:14:38.829349 [DutyScan_Calibration_Flow] ====Done====
2341 12:14:38.829786
2342 12:14:38.832143 [DutyScan_Calibration_Flow] k_type=2
2343 12:14:38.849154
2344 12:14:38.849571 ==DQ 0 ==
2345 12:14:38.851902 Final DQ duty delay cell = 0
2346 12:14:38.855387 [0] MAX Duty = 5156%(X100), DQS PI = 18
2347 12:14:38.858771 [0] MIN Duty = 4969%(X100), DQS PI = 58
2348 12:14:38.859226 [0] AVG Duty = 5062%(X100)
2349 12:14:38.861941
2350 12:14:38.862390 ==DQ 1 ==
2351 12:14:38.865532 Final DQ duty delay cell = 0
2352 12:14:38.868885 [0] MAX Duty = 5125%(X100), DQS PI = 4
2353 12:14:38.871969 [0] MIN Duty = 4938%(X100), DQS PI = 16
2354 12:14:38.872425 [0] AVG Duty = 5031%(X100)
2355 12:14:38.872760
2356 12:14:38.875433 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2357 12:14:38.879027
2358 12:14:38.881924 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2359 12:14:38.885430 [DutyScan_Calibration_Flow] ====Done====
2360 12:14:38.885911 ==
2361 12:14:38.888325 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 12:14:38.891819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 12:14:38.892235 ==
2364 12:14:38.895570 [Duty_Offset_Calibration]
2365 12:14:38.896024 B0:0 B1:-1 CA:3
2366 12:14:38.896455
2367 12:14:38.898484 [DutyScan_Calibration_Flow] k_type=0
2368 12:14:38.908327
2369 12:14:38.908763 ==CLK 0==
2370 12:14:38.911150 Final CLK duty delay cell = -4
2371 12:14:38.914379 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2372 12:14:38.917875 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2373 12:14:38.921334 [-4] AVG Duty = 4938%(X100)
2374 12:14:38.921746
2375 12:14:38.924803 CH1 CLK Duty spec in!! Max-Min= 124%
2376 12:14:38.928325 [DutyScan_Calibration_Flow] ====Done====
2377 12:14:38.928878
2378 12:14:38.930902 [DutyScan_Calibration_Flow] k_type=1
2379 12:14:38.946337
2380 12:14:38.946424 ==DQS 0 ==
2381 12:14:38.949937 Final DQS duty delay cell = 0
2382 12:14:38.952798 [0] MAX Duty = 5187%(X100), DQS PI = 18
2383 12:14:38.956212 [0] MIN Duty = 4907%(X100), DQS PI = 38
2384 12:14:38.959722 [0] AVG Duty = 5047%(X100)
2385 12:14:38.959816
2386 12:14:38.959906 ==DQS 1 ==
2387 12:14:38.963012 Final DQS duty delay cell = -4
2388 12:14:38.966362 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2389 12:14:38.969849 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2390 12:14:38.972865 [-4] AVG Duty = 4953%(X100)
2391 12:14:38.972939
2392 12:14:38.976303 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2393 12:14:38.976378
2394 12:14:38.979792 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2395 12:14:38.982710 [DutyScan_Calibration_Flow] ====Done====
2396 12:14:38.982785
2397 12:14:38.986360 [DutyScan_Calibration_Flow] k_type=3
2398 12:14:39.004247
2399 12:14:39.004737 ==DQM 0 ==
2400 12:14:39.007639 Final DQM duty delay cell = 0
2401 12:14:39.011185 [0] MAX Duty = 5031%(X100), DQS PI = 28
2402 12:14:39.014736 [0] MIN Duty = 4782%(X100), DQS PI = 38
2403 12:14:39.015214 [0] AVG Duty = 4906%(X100)
2404 12:14:39.017661
2405 12:14:39.018062 ==DQM 1 ==
2406 12:14:39.021091 Final DQM duty delay cell = 4
2407 12:14:39.024425 [4] MAX Duty = 5187%(X100), DQS PI = 30
2408 12:14:39.027813 [4] MIN Duty = 5062%(X100), DQS PI = 0
2409 12:14:39.028368 [4] AVG Duty = 5124%(X100)
2410 12:14:39.030612
2411 12:14:39.034114 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2412 12:14:39.034594
2413 12:14:39.037415 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2414 12:14:39.040778 [DutyScan_Calibration_Flow] ====Done====
2415 12:14:39.041151
2416 12:14:39.043914 [DutyScan_Calibration_Flow] k_type=2
2417 12:14:39.059599
2418 12:14:39.059687 ==DQ 0 ==
2419 12:14:39.063112 Final DQ duty delay cell = -4
2420 12:14:39.066032 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2421 12:14:39.069339 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2422 12:14:39.073105 [-4] AVG Duty = 4937%(X100)
2423 12:14:39.073187
2424 12:14:39.073258 ==DQ 1 ==
2425 12:14:39.076184 Final DQ duty delay cell = 0
2426 12:14:39.079630 [0] MAX Duty = 5031%(X100), DQS PI = 34
2427 12:14:39.083046 [0] MIN Duty = 4844%(X100), DQS PI = 62
2428 12:14:39.086067 [0] AVG Duty = 4937%(X100)
2429 12:14:39.086177
2430 12:14:39.089579 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2431 12:14:39.089684
2432 12:14:39.092920 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2433 12:14:39.095960 [DutyScan_Calibration_Flow] ====Done====
2434 12:14:39.099575 nWR fixed to 30
2435 12:14:39.102557 [ModeRegInit_LP4] CH0 RK0
2436 12:14:39.102698 [ModeRegInit_LP4] CH0 RK1
2437 12:14:39.106140 [ModeRegInit_LP4] CH1 RK0
2438 12:14:39.109793 [ModeRegInit_LP4] CH1 RK1
2439 12:14:39.110037 match AC timing 7
2440 12:14:39.116517 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 12:14:39.119279 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 12:14:39.122735 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 12:14:39.129406 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 12:14:39.132442 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 12:14:39.132854 ==
2446 12:14:39.136255 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 12:14:39.139201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 12:14:39.139626 ==
2449 12:14:39.146153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 12:14:39.152492 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 12:14:39.160390 [CA 0] Center 39 (9~70) winsize 62
2452 12:14:39.163889 [CA 1] Center 39 (9~69) winsize 61
2453 12:14:39.166896 [CA 2] Center 35 (5~66) winsize 62
2454 12:14:39.170441 [CA 3] Center 35 (5~66) winsize 62
2455 12:14:39.173800 [CA 4] Center 33 (3~64) winsize 62
2456 12:14:39.176844 [CA 5] Center 33 (3~64) winsize 62
2457 12:14:39.177278
2458 12:14:39.180699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2459 12:14:39.181123
2460 12:14:39.183359 [CATrainingPosCal] consider 1 rank data
2461 12:14:39.186966 u2DelayCellTimex100 = 270/100 ps
2462 12:14:39.190225 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2463 12:14:39.193866 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2464 12:14:39.200322 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2465 12:14:39.203876 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2466 12:14:39.206400 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2467 12:14:39.209999 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2468 12:14:39.210081
2469 12:14:39.213427 CA PerBit enable=1, Macro0, CA PI delay=33
2470 12:14:39.213509
2471 12:14:39.216352 [CBTSetCACLKResult] CA Dly = 33
2472 12:14:39.216434 CS Dly: 7 (0~38)
2473 12:14:39.219905 ==
2474 12:14:39.220014 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 12:14:39.226628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 12:14:39.226711 ==
2477 12:14:39.230020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 12:14:39.236458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2479 12:14:39.245754 [CA 0] Center 39 (9~70) winsize 62
2480 12:14:39.248933 [CA 1] Center 39 (9~70) winsize 62
2481 12:14:39.252358 [CA 2] Center 35 (5~66) winsize 62
2482 12:14:39.255663 [CA 3] Center 35 (5~66) winsize 62
2483 12:14:39.259017 [CA 4] Center 34 (4~65) winsize 62
2484 12:14:39.262188 [CA 5] Center 33 (3~64) winsize 62
2485 12:14:39.262325
2486 12:14:39.265938 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2487 12:14:39.266076
2488 12:14:39.269379 [CATrainingPosCal] consider 2 rank data
2489 12:14:39.272045 u2DelayCellTimex100 = 270/100 ps
2490 12:14:39.275664 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2491 12:14:39.282135 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2492 12:14:39.285802 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2493 12:14:39.288612 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 12:14:39.292414 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2495 12:14:39.295498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2496 12:14:39.295946
2497 12:14:39.299066 CA PerBit enable=1, Macro0, CA PI delay=33
2498 12:14:39.299527
2499 12:14:39.302763 [CBTSetCACLKResult] CA Dly = 33
2500 12:14:39.305113 CS Dly: 8 (0~41)
2501 12:14:39.305566
2502 12:14:39.308604 ----->DramcWriteLeveling(PI) begin...
2503 12:14:39.309105 ==
2504 12:14:39.312165 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 12:14:39.315553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 12:14:39.316154 ==
2507 12:14:39.318525 Write leveling (Byte 0): 30 => 30
2508 12:14:39.322100 Write leveling (Byte 1): 26 => 26
2509 12:14:39.325502 DramcWriteLeveling(PI) end<-----
2510 12:14:39.325925
2511 12:14:39.326256 ==
2512 12:14:39.328990 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 12:14:39.331573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:14:39.332000 ==
2515 12:14:39.335026 [Gating] SW mode calibration
2516 12:14:39.342050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 12:14:39.348912 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 12:14:39.352135 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2519 12:14:39.355463 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2520 12:14:39.361997 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 12:14:39.365447 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 12:14:39.368539 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 12:14:39.374985 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 12:14:39.378670 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:14:39.382066 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2526 12:14:39.388288 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
2527 12:14:39.391556 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2528 12:14:39.395119 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 12:14:39.401470 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 12:14:39.405155 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 12:14:39.407993 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:14:39.415146 1 0 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
2533 12:14:39.418079 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2534 12:14:39.421839 1 1 0 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2535 12:14:39.428249 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 12:14:39.431754 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 12:14:39.434972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 12:14:39.441354 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 12:14:39.445077 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:14:39.448388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 12:14:39.454585 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 12:14:39.457865 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 12:14:39.461224 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:14:39.467995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:14:39.471190 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:14:39.474413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:14:39.477920 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:14:39.484957 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:14:39.487896 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:14:39.491198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:14:39.497942 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:14:39.500896 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:14:39.504363 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:14:39.510948 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:14:39.514278 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:14:39.517900 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2557 12:14:39.524368 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 12:14:39.527907 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 12:14:39.530741 Total UI for P1: 0, mck2ui 16
2560 12:14:39.534173 best dqsien dly found for B0: ( 1, 3, 26)
2561 12:14:39.537633 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:14:39.540428 Total UI for P1: 0, mck2ui 16
2563 12:14:39.543738 best dqsien dly found for B1: ( 1, 4, 0)
2564 12:14:39.547223 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2565 12:14:39.550763 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 12:14:39.553886
2567 12:14:39.557383 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2568 12:14:39.560903 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 12:14:39.564140 [Gating] SW calibration Done
2570 12:14:39.564696 ==
2571 12:14:39.567396 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 12:14:39.570286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 12:14:39.570750 ==
2574 12:14:39.571137 RX Vref Scan: 0
2575 12:14:39.571579
2576 12:14:39.574141 RX Vref 0 -> 0, step: 1
2577 12:14:39.574580
2578 12:14:39.577023 RX Delay -40 -> 252, step: 8
2579 12:14:39.580424 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 12:14:39.583862 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2581 12:14:39.590740 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 12:14:39.593589 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2583 12:14:39.596999 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2584 12:14:39.600370 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2585 12:14:39.603849 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 12:14:39.610437 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 12:14:39.614026 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2588 12:14:39.616932 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2589 12:14:39.620456 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2590 12:14:39.623387 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2591 12:14:39.630461 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2592 12:14:39.633875 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2593 12:14:39.636864 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2594 12:14:39.640342 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2595 12:14:39.640994 ==
2596 12:14:39.643940 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 12:14:39.647185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 12:14:39.650566 ==
2599 12:14:39.651043 DQS Delay:
2600 12:14:39.651404 DQS0 = 0, DQS1 = 0
2601 12:14:39.654064 DQM Delay:
2602 12:14:39.654575 DQM0 = 120, DQM1 = 106
2603 12:14:39.657569 DQ Delay:
2604 12:14:39.660192 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2605 12:14:39.663697 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2606 12:14:39.667280 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2607 12:14:39.670519 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2608 12:14:39.670949
2609 12:14:39.671289
2610 12:14:39.671803 ==
2611 12:14:39.673877 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 12:14:39.677274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 12:14:39.677730 ==
2614 12:14:39.678071
2615 12:14:39.678410
2616 12:14:39.680463 TX Vref Scan disable
2617 12:14:39.683830 == TX Byte 0 ==
2618 12:14:39.687162 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2619 12:14:39.690413 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2620 12:14:39.693359 == TX Byte 1 ==
2621 12:14:39.696905 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2622 12:14:39.700475 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2623 12:14:39.700921 ==
2624 12:14:39.703740 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 12:14:39.710036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 12:14:39.710467 ==
2627 12:14:39.720828 TX Vref=22, minBit 0, minWin=25, winSum=413
2628 12:14:39.724333 TX Vref=24, minBit 2, minWin=25, winSum=414
2629 12:14:39.727714 TX Vref=26, minBit 4, minWin=25, winSum=420
2630 12:14:39.730657 TX Vref=28, minBit 4, minWin=26, winSum=427
2631 12:14:39.734344 TX Vref=30, minBit 8, minWin=26, winSum=429
2632 12:14:39.740635 TX Vref=32, minBit 5, minWin=26, winSum=427
2633 12:14:39.744103 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
2634 12:14:39.744536
2635 12:14:39.747499 Final TX Range 1 Vref 30
2636 12:14:39.747929
2637 12:14:39.748328 ==
2638 12:14:39.750860 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 12:14:39.754194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 12:14:39.754831 ==
2641 12:14:39.757228
2642 12:14:39.757829
2643 12:14:39.758410 TX Vref Scan disable
2644 12:14:39.760368 == TX Byte 0 ==
2645 12:14:39.763737 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2646 12:14:39.770666 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2647 12:14:39.771209 == TX Byte 1 ==
2648 12:14:39.773583 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2649 12:14:39.780828 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2650 12:14:39.781423
2651 12:14:39.781976 [DATLAT]
2652 12:14:39.782517 Freq=1200, CH0 RK0
2653 12:14:39.783012
2654 12:14:39.783800 DATLAT Default: 0xd
2655 12:14:39.784335 0, 0xFFFF, sum = 0
2656 12:14:39.787315 1, 0xFFFF, sum = 0
2657 12:14:39.787859 2, 0xFFFF, sum = 0
2658 12:14:39.790764 3, 0xFFFF, sum = 0
2659 12:14:39.793946 4, 0xFFFF, sum = 0
2660 12:14:39.794530 5, 0xFFFF, sum = 0
2661 12:14:39.797128 6, 0xFFFF, sum = 0
2662 12:14:39.797587 7, 0xFFFF, sum = 0
2663 12:14:39.800328 8, 0xFFFF, sum = 0
2664 12:14:39.800769 9, 0xFFFF, sum = 0
2665 12:14:39.803360 10, 0xFFFF, sum = 0
2666 12:14:39.803818 11, 0xFFFF, sum = 0
2667 12:14:39.806935 12, 0x0, sum = 1
2668 12:14:39.807381 13, 0x0, sum = 2
2669 12:14:39.810530 14, 0x0, sum = 3
2670 12:14:39.810961 15, 0x0, sum = 4
2671 12:14:39.813967 best_step = 13
2672 12:14:39.814438
2673 12:14:39.814777 ==
2674 12:14:39.816876 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 12:14:39.819877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 12:14:39.820337 ==
2677 12:14:39.820681 RX Vref Scan: 1
2678 12:14:39.823684
2679 12:14:39.824168 Set Vref Range= 32 -> 127
2680 12:14:39.824520
2681 12:14:39.826650 RX Vref 32 -> 127, step: 1
2682 12:14:39.827179
2683 12:14:39.830107 RX Delay -21 -> 252, step: 4
2684 12:14:39.830615
2685 12:14:39.833110 Set Vref, RX VrefLevel [Byte0]: 32
2686 12:14:39.836752 [Byte1]: 32
2687 12:14:39.837298
2688 12:14:39.840169 Set Vref, RX VrefLevel [Byte0]: 33
2689 12:14:39.843196 [Byte1]: 33
2690 12:14:39.846716
2691 12:14:39.847283 Set Vref, RX VrefLevel [Byte0]: 34
2692 12:14:39.850513 [Byte1]: 34
2693 12:14:39.854986
2694 12:14:39.855393 Set Vref, RX VrefLevel [Byte0]: 35
2695 12:14:39.857902 [Byte1]: 35
2696 12:14:39.862765
2697 12:14:39.863162 Set Vref, RX VrefLevel [Byte0]: 36
2698 12:14:39.866338 [Byte1]: 36
2699 12:14:39.870458
2700 12:14:39.870547 Set Vref, RX VrefLevel [Byte0]: 37
2701 12:14:39.874020 [Byte1]: 37
2702 12:14:39.878672
2703 12:14:39.878774 Set Vref, RX VrefLevel [Byte0]: 38
2704 12:14:39.881474 [Byte1]: 38
2705 12:14:39.886041
2706 12:14:39.886138 Set Vref, RX VrefLevel [Byte0]: 39
2707 12:14:39.889607 [Byte1]: 39
2708 12:14:39.894510
2709 12:14:39.894584 Set Vref, RX VrefLevel [Byte0]: 40
2710 12:14:39.897328 [Byte1]: 40
2711 12:14:39.902053
2712 12:14:39.902162 Set Vref, RX VrefLevel [Byte0]: 41
2713 12:14:39.905781 [Byte1]: 41
2714 12:14:39.909835
2715 12:14:39.909913 Set Vref, RX VrefLevel [Byte0]: 42
2716 12:14:39.913472 [Byte1]: 42
2717 12:14:39.918107
2718 12:14:39.918184 Set Vref, RX VrefLevel [Byte0]: 43
2719 12:14:39.921064 [Byte1]: 43
2720 12:14:39.925853
2721 12:14:39.925961 Set Vref, RX VrefLevel [Byte0]: 44
2722 12:14:39.929470 [Byte1]: 44
2723 12:14:39.933715
2724 12:14:39.933794 Set Vref, RX VrefLevel [Byte0]: 45
2725 12:14:39.937350 [Byte1]: 45
2726 12:14:39.941704
2727 12:14:39.941780 Set Vref, RX VrefLevel [Byte0]: 46
2728 12:14:39.945214 [Byte1]: 46
2729 12:14:39.950090
2730 12:14:39.950197 Set Vref, RX VrefLevel [Byte0]: 47
2731 12:14:39.953041 [Byte1]: 47
2732 12:14:39.957783
2733 12:14:39.957865 Set Vref, RX VrefLevel [Byte0]: 48
2734 12:14:39.960711 [Byte1]: 48
2735 12:14:39.965412
2736 12:14:39.965509 Set Vref, RX VrefLevel [Byte0]: 49
2737 12:14:39.969031 [Byte1]: 49
2738 12:14:39.973179
2739 12:14:39.973263 Set Vref, RX VrefLevel [Byte0]: 50
2740 12:14:39.976474 [Byte1]: 50
2741 12:14:39.981649
2742 12:14:39.981759 Set Vref, RX VrefLevel [Byte0]: 51
2743 12:14:39.984515 [Byte1]: 51
2744 12:14:39.989163
2745 12:14:39.989263 Set Vref, RX VrefLevel [Byte0]: 52
2746 12:14:39.992760 [Byte1]: 52
2747 12:14:39.997166
2748 12:14:39.997250 Set Vref, RX VrefLevel [Byte0]: 53
2749 12:14:40.000695 [Byte1]: 53
2750 12:14:40.005284
2751 12:14:40.005373 Set Vref, RX VrefLevel [Byte0]: 54
2752 12:14:40.008396 [Byte1]: 54
2753 12:14:40.013386
2754 12:14:40.013470 Set Vref, RX VrefLevel [Byte0]: 55
2755 12:14:40.016390 [Byte1]: 55
2756 12:14:40.021057
2757 12:14:40.021141 Set Vref, RX VrefLevel [Byte0]: 56
2758 12:14:40.024044 [Byte1]: 56
2759 12:14:40.028919
2760 12:14:40.029002 Set Vref, RX VrefLevel [Byte0]: 57
2761 12:14:40.032476 [Byte1]: 57
2762 12:14:40.036732
2763 12:14:40.036815 Set Vref, RX VrefLevel [Byte0]: 58
2764 12:14:40.040283 [Byte1]: 58
2765 12:14:40.045220
2766 12:14:40.045304 Set Vref, RX VrefLevel [Byte0]: 59
2767 12:14:40.048119 [Byte1]: 59
2768 12:14:40.052975
2769 12:14:40.053057 Set Vref, RX VrefLevel [Byte0]: 60
2770 12:14:40.055943 [Byte1]: 60
2771 12:14:40.060811
2772 12:14:40.060912 Set Vref, RX VrefLevel [Byte0]: 61
2773 12:14:40.064194 [Byte1]: 61
2774 12:14:40.068731
2775 12:14:40.068819 Set Vref, RX VrefLevel [Byte0]: 62
2776 12:14:40.072201 [Byte1]: 62
2777 12:14:40.077010
2778 12:14:40.077106 Set Vref, RX VrefLevel [Byte0]: 63
2779 12:14:40.079838 [Byte1]: 63
2780 12:14:40.084701
2781 12:14:40.084815 Set Vref, RX VrefLevel [Byte0]: 64
2782 12:14:40.088230 [Byte1]: 64
2783 12:14:40.092564
2784 12:14:40.092776 Set Vref, RX VrefLevel [Byte0]: 65
2785 12:14:40.095881 [Byte1]: 65
2786 12:14:40.100288
2787 12:14:40.100523 Set Vref, RX VrefLevel [Byte0]: 66
2788 12:14:40.103904 [Byte1]: 66
2789 12:14:40.108338
2790 12:14:40.108550 Set Vref, RX VrefLevel [Byte0]: 67
2791 12:14:40.111621 [Byte1]: 67
2792 12:14:40.116463
2793 12:14:40.116720 Set Vref, RX VrefLevel [Byte0]: 68
2794 12:14:40.120126 [Byte1]: 68
2795 12:14:40.124616
2796 12:14:40.125033 Final RX Vref Byte 0 = 56 to rank0
2797 12:14:40.127643 Final RX Vref Byte 1 = 49 to rank0
2798 12:14:40.131277 Final RX Vref Byte 0 = 56 to rank1
2799 12:14:40.134696 Final RX Vref Byte 1 = 49 to rank1==
2800 12:14:40.137582 Dram Type= 6, Freq= 0, CH_0, rank 0
2801 12:14:40.144586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2802 12:14:40.145015 ==
2803 12:14:40.145354 DQS Delay:
2804 12:14:40.145668 DQS0 = 0, DQS1 = 0
2805 12:14:40.147545 DQM Delay:
2806 12:14:40.147970 DQM0 = 119, DQM1 = 106
2807 12:14:40.150950 DQ Delay:
2808 12:14:40.154482 DQ0 =120, DQ1 =118, DQ2 =116, DQ3 =116
2809 12:14:40.158069 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2810 12:14:40.160795 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =100
2811 12:14:40.164335 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2812 12:14:40.164793
2813 12:14:40.165209
2814 12:14:40.174117 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdf9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2815 12:14:40.174792 CH0 RK0: MR19=303, MR18=FDF9
2816 12:14:40.180994 CH0_RK0: MR19=0x303, MR18=0xFDF9, DQSOSC=411, MR23=63, INC=38, DEC=25
2817 12:14:40.181442
2818 12:14:40.184191 ----->DramcWriteLeveling(PI) begin...
2819 12:14:40.184652 ==
2820 12:14:40.187510 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 12:14:40.191136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 12:14:40.194403 ==
2823 12:14:40.197829 Write leveling (Byte 0): 29 => 29
2824 12:14:40.198256 Write leveling (Byte 1): 26 => 26
2825 12:14:40.200595 DramcWriteLeveling(PI) end<-----
2826 12:14:40.201028
2827 12:14:40.201399 ==
2828 12:14:40.204467 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 12:14:40.210639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 12:14:40.211209 ==
2831 12:14:40.213912 [Gating] SW mode calibration
2832 12:14:40.220500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2833 12:14:40.223789 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2834 12:14:40.230851 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2835 12:14:40.234283 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2836 12:14:40.237252 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 12:14:40.243551 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 12:14:40.247162 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 12:14:40.250206 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 12:14:40.257168 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2841 12:14:40.260109 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2842 12:14:40.263549 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2843 12:14:40.270594 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 12:14:40.273776 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 12:14:40.276676 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 12:14:40.283445 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 12:14:40.286997 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 12:14:40.289844 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
2849 12:14:40.296480 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2850 12:14:40.299828 1 1 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
2851 12:14:40.303558 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 12:14:40.306986 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 12:14:40.313335 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 12:14:40.316665 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 12:14:40.320020 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2856 12:14:40.326383 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2857 12:14:40.329953 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2858 12:14:40.333550 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2859 12:14:40.339780 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 12:14:40.342826 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 12:14:40.346307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:14:40.352954 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:14:40.355900 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:14:40.359474 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:14:40.365883 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:14:40.369361 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:14:40.372845 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:14:40.379150 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:14:40.382700 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:14:40.385907 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:14:40.392711 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:14:40.395623 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2873 12:14:40.398807 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2874 12:14:40.402289 Total UI for P1: 0, mck2ui 16
2875 12:14:40.405465 best dqsien dly found for B0: ( 1, 3, 24)
2876 12:14:40.412221 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2877 12:14:40.415577 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:14:40.418953 Total UI for P1: 0, mck2ui 16
2879 12:14:40.422491 best dqsien dly found for B1: ( 1, 3, 30)
2880 12:14:40.425420 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2881 12:14:40.428774 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2882 12:14:40.429075
2883 12:14:40.432483 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2884 12:14:40.436158 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2885 12:14:40.438894 [Gating] SW calibration Done
2886 12:14:40.439316 ==
2887 12:14:40.442435 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 12:14:40.448819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 12:14:40.449244 ==
2890 12:14:40.449583 RX Vref Scan: 0
2891 12:14:40.449897
2892 12:14:40.452311 RX Vref 0 -> 0, step: 1
2893 12:14:40.452732
2894 12:14:40.455819 RX Delay -40 -> 252, step: 8
2895 12:14:40.459295 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2896 12:14:40.462116 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2897 12:14:40.465742 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2898 12:14:40.469208 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2899 12:14:40.475680 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2900 12:14:40.478657 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2901 12:14:40.482206 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2902 12:14:40.485402 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2903 12:14:40.488674 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2904 12:14:40.495512 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2905 12:14:40.498384 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2906 12:14:40.501781 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2907 12:14:40.505329 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2908 12:14:40.508712 iDelay=200, Bit 13, Center 107 (40 ~ 175) 136
2909 12:14:40.515344 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2910 12:14:40.518192 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2911 12:14:40.518612 ==
2912 12:14:40.522235 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 12:14:40.525082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 12:14:40.525510 ==
2915 12:14:40.528436 DQS Delay:
2916 12:14:40.528858 DQS0 = 0, DQS1 = 0
2917 12:14:40.529199 DQM Delay:
2918 12:14:40.531740 DQM0 = 119, DQM1 = 105
2919 12:14:40.532213 DQ Delay:
2920 12:14:40.535337 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2921 12:14:40.538328 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2922 12:14:40.541770 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2923 12:14:40.548134 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =115
2924 12:14:40.548556
2925 12:14:40.548893
2926 12:14:40.549201 ==
2927 12:14:40.551625 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 12:14:40.555298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 12:14:40.555726 ==
2930 12:14:40.556103
2931 12:14:40.556429
2932 12:14:40.558105 TX Vref Scan disable
2933 12:14:40.558530 == TX Byte 0 ==
2934 12:14:40.565068 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2935 12:14:40.567771 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2936 12:14:40.567859 == TX Byte 1 ==
2937 12:14:40.574831 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2938 12:14:40.577617 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2939 12:14:40.577700 ==
2940 12:14:40.581434 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 12:14:40.584133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 12:14:40.584223 ==
2943 12:14:40.597794 TX Vref=22, minBit 10, minWin=25, winSum=418
2944 12:14:40.601110 TX Vref=24, minBit 10, minWin=25, winSum=424
2945 12:14:40.603989 TX Vref=26, minBit 1, minWin=26, winSum=424
2946 12:14:40.607523 TX Vref=28, minBit 2, minWin=26, winSum=430
2947 12:14:40.611239 TX Vref=30, minBit 10, minWin=26, winSum=430
2948 12:14:40.617560 TX Vref=32, minBit 4, minWin=26, winSum=430
2949 12:14:40.620928 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 28
2950 12:14:40.621012
2951 12:14:40.624206 Final TX Range 1 Vref 28
2952 12:14:40.624290
2953 12:14:40.624355 ==
2954 12:14:40.627550 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 12:14:40.630946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 12:14:40.634262 ==
2957 12:14:40.634344
2958 12:14:40.634409
2959 12:14:40.634468 TX Vref Scan disable
2960 12:14:40.637923 == TX Byte 0 ==
2961 12:14:40.640777 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2962 12:14:40.647678 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2963 12:14:40.647761 == TX Byte 1 ==
2964 12:14:40.651257 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2965 12:14:40.657642 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2966 12:14:40.657738
2967 12:14:40.657812 [DATLAT]
2968 12:14:40.657883 Freq=1200, CH0 RK1
2969 12:14:40.657950
2970 12:14:40.661491 DATLAT Default: 0xd
2971 12:14:40.661680 0, 0xFFFF, sum = 0
2972 12:14:40.664268 1, 0xFFFF, sum = 0
2973 12:14:40.667669 2, 0xFFFF, sum = 0
2974 12:14:40.667753 3, 0xFFFF, sum = 0
2975 12:14:40.671077 4, 0xFFFF, sum = 0
2976 12:14:40.671163 5, 0xFFFF, sum = 0
2977 12:14:40.673963 6, 0xFFFF, sum = 0
2978 12:14:40.674048 7, 0xFFFF, sum = 0
2979 12:14:40.677580 8, 0xFFFF, sum = 0
2980 12:14:40.677665 9, 0xFFFF, sum = 0
2981 12:14:40.681062 10, 0xFFFF, sum = 0
2982 12:14:40.681152 11, 0xFFFF, sum = 0
2983 12:14:40.683977 12, 0x0, sum = 1
2984 12:14:40.684081 13, 0x0, sum = 2
2985 12:14:40.687347 14, 0x0, sum = 3
2986 12:14:40.687443 15, 0x0, sum = 4
2987 12:14:40.690871 best_step = 13
2988 12:14:40.690972
2989 12:14:40.691054 ==
2990 12:14:40.693812 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 12:14:40.697275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 12:14:40.697358 ==
2993 12:14:40.697424 RX Vref Scan: 0
2994 12:14:40.697486
2995 12:14:40.700598 RX Vref 0 -> 0, step: 1
2996 12:14:40.700680
2997 12:14:40.704114 RX Delay -21 -> 252, step: 4
2998 12:14:40.707400 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
2999 12:14:40.713757 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3000 12:14:40.717264 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3001 12:14:40.720683 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3002 12:14:40.723977 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3003 12:14:40.727294 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3004 12:14:40.734092 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3005 12:14:40.737505 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3006 12:14:40.740410 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3007 12:14:40.743936 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3008 12:14:40.747564 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3009 12:14:40.753843 iDelay=195, Bit 11, Center 98 (35 ~ 162) 128
3010 12:14:40.757344 iDelay=195, Bit 12, Center 112 (51 ~ 174) 124
3011 12:14:40.760985 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3012 12:14:40.763863 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3013 12:14:40.767539 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3014 12:14:40.770906 ==
3015 12:14:40.771069 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:14:40.777327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:14:40.777768 ==
3018 12:14:40.778114 DQS Delay:
3019 12:14:40.780961 DQS0 = 0, DQS1 = 0
3020 12:14:40.781389 DQM Delay:
3021 12:14:40.784363 DQM0 = 117, DQM1 = 106
3022 12:14:40.784785 DQ Delay:
3023 12:14:40.787352 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3024 12:14:40.790779 DQ4 =120, DQ5 =112, DQ6 =128, DQ7 =122
3025 12:14:40.794367 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3026 12:14:40.797179 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3027 12:14:40.797605
3028 12:14:40.797938
3029 12:14:40.807260 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
3030 12:14:40.807690 CH0 RK1: MR19=403, MR18=FE
3031 12:14:40.813649 CH0_RK1: MR19=0x403, MR18=0xFE, DQSOSC=410, MR23=63, INC=39, DEC=26
3032 12:14:40.817104 [RxdqsGatingPostProcess] freq 1200
3033 12:14:40.824275 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3034 12:14:40.827096 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 12:14:40.830304 best DQS1 dly(2T, 0.5T) = (0, 12)
3036 12:14:40.833797 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 12:14:40.837218 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3038 12:14:40.837732 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 12:14:40.840567 best DQS1 dly(2T, 0.5T) = (0, 11)
3040 12:14:40.843850 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 12:14:40.846762 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3042 12:14:40.850365 Pre-setting of DQS Precalculation
3043 12:14:40.856611 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3044 12:14:40.857039 ==
3045 12:14:40.860130 Dram Type= 6, Freq= 0, CH_1, rank 0
3046 12:14:40.863566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 12:14:40.863994 ==
3048 12:14:40.870138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3049 12:14:40.876503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3050 12:14:40.883482 [CA 0] Center 38 (8~68) winsize 61
3051 12:14:40.886948 [CA 1] Center 37 (7~68) winsize 62
3052 12:14:40.890351 [CA 2] Center 35 (5~65) winsize 61
3053 12:14:40.893380 [CA 3] Center 34 (4~64) winsize 61
3054 12:14:40.896976 [CA 4] Center 34 (4~65) winsize 62
3055 12:14:40.900301 [CA 5] Center 34 (4~64) winsize 61
3056 12:14:40.900736
3057 12:14:40.903485 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3058 12:14:40.903919
3059 12:14:40.906928 [CATrainingPosCal] consider 1 rank data
3060 12:14:40.910207 u2DelayCellTimex100 = 270/100 ps
3061 12:14:40.913454 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3062 12:14:40.919834 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3063 12:14:40.923227 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3064 12:14:40.926604 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3065 12:14:40.929951 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3066 12:14:40.933333 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3067 12:14:40.933912
3068 12:14:40.936580 CA PerBit enable=1, Macro0, CA PI delay=34
3069 12:14:40.937012
3070 12:14:40.940028 [CBTSetCACLKResult] CA Dly = 34
3071 12:14:40.942992 CS Dly: 5 (0~36)
3072 12:14:40.943423 ==
3073 12:14:40.946344 Dram Type= 6, Freq= 0, CH_1, rank 1
3074 12:14:40.950188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3075 12:14:40.950727 ==
3076 12:14:40.956291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3077 12:14:40.959782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3078 12:14:40.969730 [CA 0] Center 37 (7~68) winsize 62
3079 12:14:40.973045 [CA 1] Center 38 (8~68) winsize 61
3080 12:14:40.976011 [CA 2] Center 35 (5~65) winsize 61
3081 12:14:40.979596 [CA 3] Center 34 (4~64) winsize 61
3082 12:14:40.982457 [CA 4] Center 34 (4~64) winsize 61
3083 12:14:40.985957 [CA 5] Center 33 (3~64) winsize 62
3084 12:14:40.986413
3085 12:14:40.989295 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3086 12:14:40.989747
3087 12:14:40.992216 [CATrainingPosCal] consider 2 rank data
3088 12:14:40.995628 u2DelayCellTimex100 = 270/100 ps
3089 12:14:40.999220 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3090 12:14:41.005514 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3091 12:14:41.009146 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3092 12:14:41.012321 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3093 12:14:41.015738 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3094 12:14:41.019079 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3095 12:14:41.019558
3096 12:14:41.022072 CA PerBit enable=1, Macro0, CA PI delay=34
3097 12:14:41.022641
3098 12:14:41.025535 [CBTSetCACLKResult] CA Dly = 34
3099 12:14:41.026081 CS Dly: 6 (0~39)
3100 12:14:41.029159
3101 12:14:41.032572 ----->DramcWriteLeveling(PI) begin...
3102 12:14:41.033167 ==
3103 12:14:41.035120 Dram Type= 6, Freq= 0, CH_1, rank 0
3104 12:14:41.038467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 12:14:41.038987 ==
3106 12:14:41.041843 Write leveling (Byte 0): 25 => 25
3107 12:14:41.045265 Write leveling (Byte 1): 26 => 26
3108 12:14:41.048721 DramcWriteLeveling(PI) end<-----
3109 12:14:41.049250
3110 12:14:41.049664 ==
3111 12:14:41.051922 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 12:14:41.055543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 12:14:41.056112 ==
3114 12:14:41.058591 [Gating] SW mode calibration
3115 12:14:41.064861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3116 12:14:41.071816 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3117 12:14:41.075225 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
3118 12:14:41.078271 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 12:14:41.085321 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 12:14:41.088562 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 12:14:41.091553 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 12:14:41.098571 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 12:14:41.101754 0 15 24 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
3124 12:14:41.105249 0 15 28 | B1->B0 | 2d2d 2626 | 0 0 | (1 0) (1 0)
3125 12:14:41.112085 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 12:14:41.114971 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 12:14:41.118149 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 12:14:41.125266 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:14:41.128632 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 12:14:41.131505 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 12:14:41.138177 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3132 12:14:41.141844 1 0 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
3133 12:14:41.145155 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:14:41.148446 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:14:41.155100 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:14:41.157972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:14:41.161648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 12:14:41.168434 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 12:14:41.171080 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 12:14:41.174528 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 12:14:41.181181 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 12:14:41.184201 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:14:41.187854 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:14:41.194170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:14:41.197736 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:14:41.201367 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:14:41.207835 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:14:41.210831 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:14:41.214230 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:14:41.221041 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:14:41.224273 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:14:41.227584 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:14:41.234428 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:14:41.237285 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:14:41.241143 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3156 12:14:41.247677 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3157 12:14:41.248152 Total UI for P1: 0, mck2ui 16
3158 12:14:41.254220 best dqsien dly found for B1: ( 1, 3, 26)
3159 12:14:41.257823 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:14:41.261140 Total UI for P1: 0, mck2ui 16
3161 12:14:41.264114 best dqsien dly found for B0: ( 1, 3, 26)
3162 12:14:41.267736 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3163 12:14:41.271162 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3164 12:14:41.271591
3165 12:14:41.273721 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3166 12:14:41.276989 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3167 12:14:41.280520 [Gating] SW calibration Done
3168 12:14:41.280604 ==
3169 12:14:41.284004 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 12:14:41.287119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 12:14:41.290561 ==
3172 12:14:41.290643 RX Vref Scan: 0
3173 12:14:41.290710
3174 12:14:41.294108 RX Vref 0 -> 0, step: 1
3175 12:14:41.294190
3176 12:14:41.297140 RX Delay -40 -> 252, step: 8
3177 12:14:41.300575 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3178 12:14:41.303671 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3179 12:14:41.307134 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3180 12:14:41.310092 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3181 12:14:41.316955 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3182 12:14:41.320330 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3183 12:14:41.323879 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3184 12:14:41.326832 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3185 12:14:41.330128 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3186 12:14:41.336822 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3187 12:14:41.340011 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3188 12:14:41.343498 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3189 12:14:41.346799 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3190 12:14:41.350174 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3191 12:14:41.357029 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3192 12:14:41.359861 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3193 12:14:41.359969 ==
3194 12:14:41.363702 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 12:14:41.366798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 12:14:41.366881 ==
3197 12:14:41.370260 DQS Delay:
3198 12:14:41.370342 DQS0 = 0, DQS1 = 0
3199 12:14:41.370407 DQM Delay:
3200 12:14:41.373200 DQM0 = 115, DQM1 = 112
3201 12:14:41.373283 DQ Delay:
3202 12:14:41.376826 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3203 12:14:41.379958 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3204 12:14:41.383576 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3205 12:14:41.390007 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3206 12:14:41.390090
3207 12:14:41.390155
3208 12:14:41.390216 ==
3209 12:14:41.393614 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 12:14:41.396484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 12:14:41.396568 ==
3212 12:14:41.396633
3213 12:14:41.396695
3214 12:14:41.399935 TX Vref Scan disable
3215 12:14:41.400051 == TX Byte 0 ==
3216 12:14:41.406453 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3217 12:14:41.409945 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3218 12:14:41.410028 == TX Byte 1 ==
3219 12:14:41.416484 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3220 12:14:41.420257 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3221 12:14:41.420341 ==
3222 12:14:41.422917 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 12:14:41.426479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 12:14:41.426563 ==
3225 12:14:41.438810 TX Vref=22, minBit 9, minWin=23, winSum=405
3226 12:14:41.442167 TX Vref=24, minBit 8, minWin=24, winSum=411
3227 12:14:41.445510 TX Vref=26, minBit 11, minWin=24, winSum=417
3228 12:14:41.448729 TX Vref=28, minBit 8, minWin=25, winSum=420
3229 12:14:41.452599 TX Vref=30, minBit 9, minWin=24, winSum=420
3230 12:14:41.458797 TX Vref=32, minBit 8, minWin=25, winSum=421
3231 12:14:41.462330 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 32
3232 12:14:41.462430
3233 12:14:41.465720 Final TX Range 1 Vref 32
3234 12:14:41.465803
3235 12:14:41.465869 ==
3236 12:14:41.468985 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 12:14:41.471899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 12:14:41.475526 ==
3239 12:14:41.475608
3240 12:14:41.475673
3241 12:14:41.475734 TX Vref Scan disable
3242 12:14:41.478981 == TX Byte 0 ==
3243 12:14:41.481876 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3244 12:14:41.488547 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3245 12:14:41.488631 == TX Byte 1 ==
3246 12:14:41.491999 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3247 12:14:41.498304 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3248 12:14:41.498387
3249 12:14:41.498452 [DATLAT]
3250 12:14:41.498515 Freq=1200, CH1 RK0
3251 12:14:41.498575
3252 12:14:41.501984 DATLAT Default: 0xd
3253 12:14:41.505460 0, 0xFFFF, sum = 0
3254 12:14:41.505550 1, 0xFFFF, sum = 0
3255 12:14:41.508993 2, 0xFFFF, sum = 0
3256 12:14:41.509082 3, 0xFFFF, sum = 0
3257 12:14:41.511937 4, 0xFFFF, sum = 0
3258 12:14:41.512069 5, 0xFFFF, sum = 0
3259 12:14:41.515272 6, 0xFFFF, sum = 0
3260 12:14:41.515377 7, 0xFFFF, sum = 0
3261 12:14:41.518395 8, 0xFFFF, sum = 0
3262 12:14:41.518499 9, 0xFFFF, sum = 0
3263 12:14:41.521910 10, 0xFFFF, sum = 0
3264 12:14:41.522024 11, 0xFFFF, sum = 0
3265 12:14:41.525197 12, 0x0, sum = 1
3266 12:14:41.525322 13, 0x0, sum = 2
3267 12:14:41.528257 14, 0x0, sum = 3
3268 12:14:41.528383 15, 0x0, sum = 4
3269 12:14:41.531656 best_step = 13
3270 12:14:41.531792
3271 12:14:41.531898 ==
3272 12:14:41.535333 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 12:14:41.538213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 12:14:41.538368 ==
3275 12:14:41.538489 RX Vref Scan: 1
3276 12:14:41.541802
3277 12:14:41.541976 Set Vref Range= 32 -> 127
3278 12:14:41.542114
3279 12:14:41.545127 RX Vref 32 -> 127, step: 1
3280 12:14:41.545332
3281 12:14:41.548521 RX Delay -13 -> 252, step: 4
3282 12:14:41.548723
3283 12:14:41.551894 Set Vref, RX VrefLevel [Byte0]: 32
3284 12:14:41.555209 [Byte1]: 32
3285 12:14:41.555614
3286 12:14:41.557994 Set Vref, RX VrefLevel [Byte0]: 33
3287 12:14:41.561788 [Byte1]: 33
3288 12:14:41.565551
3289 12:14:41.565971 Set Vref, RX VrefLevel [Byte0]: 34
3290 12:14:41.568905 [Byte1]: 34
3291 12:14:41.573365
3292 12:14:41.573788 Set Vref, RX VrefLevel [Byte0]: 35
3293 12:14:41.576873 [Byte1]: 35
3294 12:14:41.581360
3295 12:14:41.581784 Set Vref, RX VrefLevel [Byte0]: 36
3296 12:14:41.584458 [Byte1]: 36
3297 12:14:41.589042
3298 12:14:41.589464 Set Vref, RX VrefLevel [Byte0]: 37
3299 12:14:41.592414 [Byte1]: 37
3300 12:14:41.596953
3301 12:14:41.597367 Set Vref, RX VrefLevel [Byte0]: 38
3302 12:14:41.600453 [Byte1]: 38
3303 12:14:41.604687
3304 12:14:41.605102 Set Vref, RX VrefLevel [Byte0]: 39
3305 12:14:41.608150 [Byte1]: 39
3306 12:14:41.612735
3307 12:14:41.613150 Set Vref, RX VrefLevel [Byte0]: 40
3308 12:14:41.616271 [Byte1]: 40
3309 12:14:41.620332
3310 12:14:41.620623 Set Vref, RX VrefLevel [Byte0]: 41
3311 12:14:41.623769 [Byte1]: 41
3312 12:14:41.628379
3313 12:14:41.628671 Set Vref, RX VrefLevel [Byte0]: 42
3314 12:14:41.631798 [Byte1]: 42
3315 12:14:41.636258
3316 12:14:41.636551 Set Vref, RX VrefLevel [Byte0]: 43
3317 12:14:41.639714 [Byte1]: 43
3318 12:14:41.643856
3319 12:14:41.644176 Set Vref, RX VrefLevel [Byte0]: 44
3320 12:14:41.647402 [Byte1]: 44
3321 12:14:41.651944
3322 12:14:41.652271 Set Vref, RX VrefLevel [Byte0]: 45
3323 12:14:41.655387 [Byte1]: 45
3324 12:14:41.660112
3325 12:14:41.660527 Set Vref, RX VrefLevel [Byte0]: 46
3326 12:14:41.663425 [Byte1]: 46
3327 12:14:41.667739
3328 12:14:41.668192 Set Vref, RX VrefLevel [Byte0]: 47
3329 12:14:41.671048 [Byte1]: 47
3330 12:14:41.675844
3331 12:14:41.676289 Set Vref, RX VrefLevel [Byte0]: 48
3332 12:14:41.679280 [Byte1]: 48
3333 12:14:41.683952
3334 12:14:41.684407 Set Vref, RX VrefLevel [Byte0]: 49
3335 12:14:41.686998 [Byte1]: 49
3336 12:14:41.691553
3337 12:14:41.691971 Set Vref, RX VrefLevel [Byte0]: 50
3338 12:14:41.694994 [Byte1]: 50
3339 12:14:41.699770
3340 12:14:41.700298 Set Vref, RX VrefLevel [Byte0]: 51
3341 12:14:41.702581 [Byte1]: 51
3342 12:14:41.707384
3343 12:14:41.707802 Set Vref, RX VrefLevel [Byte0]: 52
3344 12:14:41.710675 [Byte1]: 52
3345 12:14:41.715287
3346 12:14:41.715705 Set Vref, RX VrefLevel [Byte0]: 53
3347 12:14:41.718241 [Byte1]: 53
3348 12:14:41.722826
3349 12:14:41.723441 Set Vref, RX VrefLevel [Byte0]: 54
3350 12:14:41.726317 [Byte1]: 54
3351 12:14:41.730917
3352 12:14:41.731336 Set Vref, RX VrefLevel [Byte0]: 55
3353 12:14:41.734504 [Byte1]: 55
3354 12:14:41.738607
3355 12:14:41.739025 Set Vref, RX VrefLevel [Byte0]: 56
3356 12:14:41.741969 [Byte1]: 56
3357 12:14:41.746864
3358 12:14:41.747280 Set Vref, RX VrefLevel [Byte0]: 57
3359 12:14:41.749754 [Byte1]: 57
3360 12:14:41.754389
3361 12:14:41.755050 Set Vref, RX VrefLevel [Byte0]: 58
3362 12:14:41.757894 [Byte1]: 58
3363 12:14:41.762418
3364 12:14:41.763009 Set Vref, RX VrefLevel [Byte0]: 59
3365 12:14:41.765838 [Byte1]: 59
3366 12:14:41.769927
3367 12:14:41.770043 Set Vref, RX VrefLevel [Byte0]: 60
3368 12:14:41.773204 [Byte1]: 60
3369 12:14:41.777601
3370 12:14:41.777711 Set Vref, RX VrefLevel [Byte0]: 61
3371 12:14:41.781001 [Byte1]: 61
3372 12:14:41.785783
3373 12:14:41.785858 Set Vref, RX VrefLevel [Byte0]: 62
3374 12:14:41.789186 [Byte1]: 62
3375 12:14:41.793816
3376 12:14:41.793924 Set Vref, RX VrefLevel [Byte0]: 63
3377 12:14:41.796769 [Byte1]: 63
3378 12:14:41.801516
3379 12:14:41.801597 Set Vref, RX VrefLevel [Byte0]: 64
3380 12:14:41.804786 [Byte1]: 64
3381 12:14:41.809685
3382 12:14:41.809778 Final RX Vref Byte 0 = 53 to rank0
3383 12:14:41.813057 Final RX Vref Byte 1 = 48 to rank0
3384 12:14:41.816858 Final RX Vref Byte 0 = 53 to rank1
3385 12:14:41.819652 Final RX Vref Byte 1 = 48 to rank1==
3386 12:14:41.823245 Dram Type= 6, Freq= 0, CH_1, rank 0
3387 12:14:41.829524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3388 12:14:41.830152 ==
3389 12:14:41.830506 DQS Delay:
3390 12:14:41.830817 DQS0 = 0, DQS1 = 0
3391 12:14:41.833170 DQM Delay:
3392 12:14:41.833588 DQM0 = 115, DQM1 = 111
3393 12:14:41.836021 DQ Delay:
3394 12:14:41.839728 DQ0 =122, DQ1 =112, DQ2 =106, DQ3 =114
3395 12:14:41.843167 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3396 12:14:41.846029 DQ8 =96, DQ9 =102, DQ10 =114, DQ11 =106
3397 12:14:41.849425 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3398 12:14:41.849845
3399 12:14:41.850173
3400 12:14:41.859308 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3401 12:14:41.859733 CH1 RK0: MR19=304, MR18=F400
3402 12:14:41.866239 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3403 12:14:41.866669
3404 12:14:41.869115 ----->DramcWriteLeveling(PI) begin...
3405 12:14:41.869538 ==
3406 12:14:41.872421 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 12:14:41.879015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 12:14:41.879436 ==
3409 12:14:41.882566 Write leveling (Byte 0): 26 => 26
3410 12:14:41.885739 Write leveling (Byte 1): 28 => 28
3411 12:14:41.886218 DramcWriteLeveling(PI) end<-----
3412 12:14:41.886613
3413 12:14:41.889187 ==
3414 12:14:41.892505 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 12:14:41.895844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 12:14:41.896378 ==
3417 12:14:41.899385 [Gating] SW mode calibration
3418 12:14:41.905718 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3419 12:14:41.909008 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3420 12:14:41.915400 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3421 12:14:41.918957 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3422 12:14:41.922386 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 12:14:41.928884 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 12:14:41.932395 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 12:14:41.935848 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3426 12:14:41.942372 0 15 24 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
3427 12:14:41.945283 0 15 28 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3428 12:14:41.949075 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3429 12:14:41.955217 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 12:14:41.958705 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 12:14:41.962725 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 12:14:41.968719 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 12:14:41.972114 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3434 12:14:41.975195 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3435 12:14:41.981837 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3436 12:14:41.985620 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3437 12:14:41.988703 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 12:14:41.995519 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 12:14:41.998713 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 12:14:42.001977 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 12:14:42.005214 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 12:14:42.011843 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3443 12:14:42.015411 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3444 12:14:42.018311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 12:14:42.025176 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 12:14:42.028287 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 12:14:42.035067 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 12:14:42.038616 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 12:14:42.041528 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 12:14:42.047804 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 12:14:42.051558 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 12:14:42.054925 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 12:14:42.061282 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 12:14:42.064867 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 12:14:42.067739 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:14:42.074689 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:14:42.077773 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3458 12:14:42.080930 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3459 12:14:42.087272 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3460 12:14:42.087354 Total UI for P1: 0, mck2ui 16
3461 12:14:42.090811 best dqsien dly found for B0: ( 1, 3, 22)
3462 12:14:42.097067 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 12:14:42.100829 Total UI for P1: 0, mck2ui 16
3464 12:14:42.103624 best dqsien dly found for B1: ( 1, 3, 28)
3465 12:14:42.106995 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3466 12:14:42.110099 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3467 12:14:42.110201
3468 12:14:42.113860 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3469 12:14:42.117359 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3470 12:14:42.120454 [Gating] SW calibration Done
3471 12:14:42.120579 ==
3472 12:14:42.123433 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 12:14:42.127124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 12:14:42.127640 ==
3475 12:14:42.130273 RX Vref Scan: 0
3476 12:14:42.130826
3477 12:14:42.133732 RX Vref 0 -> 0, step: 1
3478 12:14:42.134181
3479 12:14:42.134517 RX Delay -40 -> 252, step: 8
3480 12:14:42.140258 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3481 12:14:42.143493 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3482 12:14:42.147138 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3483 12:14:42.150604 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3484 12:14:42.156799 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3485 12:14:42.159881 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3486 12:14:42.163257 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3487 12:14:42.166679 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3488 12:14:42.170340 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3489 12:14:42.176252 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3490 12:14:42.179761 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3491 12:14:42.183257 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3492 12:14:42.186260 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3493 12:14:42.189764 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3494 12:14:42.196152 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3495 12:14:42.199454 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3496 12:14:42.199906 ==
3497 12:14:42.202647 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 12:14:42.206285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 12:14:42.206720 ==
3500 12:14:42.209384 DQS Delay:
3501 12:14:42.209829 DQS0 = 0, DQS1 = 0
3502 12:14:42.212722 DQM Delay:
3503 12:14:42.213168 DQM0 = 115, DQM1 = 111
3504 12:14:42.213529 DQ Delay:
3505 12:14:42.218966 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3506 12:14:42.222237 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =111
3507 12:14:42.225407 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3508 12:14:42.229220 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3509 12:14:42.229648
3510 12:14:42.229982
3511 12:14:42.230292 ==
3512 12:14:42.232005 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 12:14:42.235539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 12:14:42.235964 ==
3515 12:14:42.236336
3516 12:14:42.236644
3517 12:14:42.238461 TX Vref Scan disable
3518 12:14:42.241883 == TX Byte 0 ==
3519 12:14:42.245431 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3520 12:14:42.248449 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3521 12:14:42.251648 == TX Byte 1 ==
3522 12:14:42.255077 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3523 12:14:42.258207 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3524 12:14:42.258436 ==
3525 12:14:42.261849 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 12:14:42.268405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 12:14:42.268632 ==
3528 12:14:42.278275 TX Vref=22, minBit 2, minWin=25, winSum=417
3529 12:14:42.281837 TX Vref=24, minBit 9, minWin=25, winSum=422
3530 12:14:42.285287 TX Vref=26, minBit 3, minWin=25, winSum=424
3531 12:14:42.288275 TX Vref=28, minBit 1, minWin=26, winSum=431
3532 12:14:42.291944 TX Vref=30, minBit 1, minWin=26, winSum=428
3533 12:14:42.298459 TX Vref=32, minBit 2, minWin=26, winSum=428
3534 12:14:42.302045 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3535 12:14:42.302422
3536 12:14:42.304917 Final TX Range 1 Vref 28
3537 12:14:42.305340
3538 12:14:42.305680 ==
3539 12:14:42.308187 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 12:14:42.311470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 12:14:42.314920 ==
3542 12:14:42.315342
3543 12:14:42.315671
3544 12:14:42.315981 TX Vref Scan disable
3545 12:14:42.318199 == TX Byte 0 ==
3546 12:14:42.321816 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3547 12:14:42.328461 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3548 12:14:42.328895 == TX Byte 1 ==
3549 12:14:42.331667 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3550 12:14:42.338275 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3551 12:14:42.338836
3552 12:14:42.339336 [DATLAT]
3553 12:14:42.339795 Freq=1200, CH1 RK1
3554 12:14:42.340260
3555 12:14:42.341457 DATLAT Default: 0xd
3556 12:14:42.344789 0, 0xFFFF, sum = 0
3557 12:14:42.345220 1, 0xFFFF, sum = 0
3558 12:14:42.347649 2, 0xFFFF, sum = 0
3559 12:14:42.348118 3, 0xFFFF, sum = 0
3560 12:14:42.351226 4, 0xFFFF, sum = 0
3561 12:14:42.351650 5, 0xFFFF, sum = 0
3562 12:14:42.354706 6, 0xFFFF, sum = 0
3563 12:14:42.355076 7, 0xFFFF, sum = 0
3564 12:14:42.358094 8, 0xFFFF, sum = 0
3565 12:14:42.358524 9, 0xFFFF, sum = 0
3566 12:14:42.361176 10, 0xFFFF, sum = 0
3567 12:14:42.361621 11, 0xFFFF, sum = 0
3568 12:14:42.364443 12, 0x0, sum = 1
3569 12:14:42.365041 13, 0x0, sum = 2
3570 12:14:42.367282 14, 0x0, sum = 3
3571 12:14:42.367847 15, 0x0, sum = 4
3572 12:14:42.371056 best_step = 13
3573 12:14:42.371627
3574 12:14:42.372164 ==
3575 12:14:42.374301 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 12:14:42.377265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 12:14:42.377874 ==
3578 12:14:42.380655 RX Vref Scan: 0
3579 12:14:42.381204
3580 12:14:42.381756 RX Vref 0 -> 0, step: 1
3581 12:14:42.382286
3582 12:14:42.384230 RX Delay -13 -> 252, step: 4
3583 12:14:42.390723 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3584 12:14:42.393733 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3585 12:14:42.397234 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3586 12:14:42.400642 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3587 12:14:42.407158 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3588 12:14:42.410002 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3589 12:14:42.413627 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3590 12:14:42.416618 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3591 12:14:42.420397 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3592 12:14:42.426577 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3593 12:14:42.430203 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3594 12:14:42.433059 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3595 12:14:42.436382 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3596 12:14:42.443003 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3597 12:14:42.446213 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3598 12:14:42.449554 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3599 12:14:42.449987 ==
3600 12:14:42.452998 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 12:14:42.456274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 12:14:42.456709 ==
3603 12:14:42.459667 DQS Delay:
3604 12:14:42.460142 DQS0 = 0, DQS1 = 0
3605 12:14:42.462591 DQM Delay:
3606 12:14:42.463023 DQM0 = 114, DQM1 = 111
3607 12:14:42.465943 DQ Delay:
3608 12:14:42.469418 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3609 12:14:42.472300 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =112
3610 12:14:42.475574 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3611 12:14:42.479138 DQ12 =120, DQ13 =116, DQ14 =116, DQ15 =120
3612 12:14:42.479567
3613 12:14:42.479910
3614 12:14:42.485754 [DQSOSCAuto] RK1, (LSB)MR18= 0xf608, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3615 12:14:42.489273 CH1 RK1: MR19=304, MR18=F608
3616 12:14:42.495786 CH1_RK1: MR19=0x304, MR18=0xF608, DQSOSC=406, MR23=63, INC=39, DEC=26
3617 12:14:42.498637 [RxdqsGatingPostProcess] freq 1200
3618 12:14:42.505165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3619 12:14:42.508558 best DQS0 dly(2T, 0.5T) = (0, 11)
3620 12:14:42.512204 best DQS1 dly(2T, 0.5T) = (0, 11)
3621 12:14:42.515510 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3622 12:14:42.518259 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3623 12:14:42.518646 best DQS0 dly(2T, 0.5T) = (0, 11)
3624 12:14:42.521831 best DQS1 dly(2T, 0.5T) = (0, 11)
3625 12:14:42.525327 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3626 12:14:42.528182 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3627 12:14:42.531562 Pre-setting of DQS Precalculation
3628 12:14:42.538192 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3629 12:14:42.544727 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3630 12:14:42.551312 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3631 12:14:42.551786
3632 12:14:42.552302
3633 12:14:42.554697 [Calibration Summary] 2400 Mbps
3634 12:14:42.558033 CH 0, Rank 0
3635 12:14:42.558639 SW Impedance : PASS
3636 12:14:42.561467 DUTY Scan : NO K
3637 12:14:42.564866 ZQ Calibration : PASS
3638 12:14:42.565305 Jitter Meter : NO K
3639 12:14:42.567747 CBT Training : PASS
3640 12:14:42.571177 Write leveling : PASS
3641 12:14:42.571650 RX DQS gating : PASS
3642 12:14:42.574774 RX DQ/DQS(RDDQC) : PASS
3643 12:14:42.575222 TX DQ/DQS : PASS
3644 12:14:42.577516 RX DATLAT : PASS
3645 12:14:42.581171 RX DQ/DQS(Engine): PASS
3646 12:14:42.581599 TX OE : NO K
3647 12:14:42.584557 All Pass.
3648 12:14:42.585092
3649 12:14:42.585669 CH 0, Rank 1
3650 12:14:42.587683 SW Impedance : PASS
3651 12:14:42.588256 DUTY Scan : NO K
3652 12:14:42.590606 ZQ Calibration : PASS
3653 12:14:42.594104 Jitter Meter : NO K
3654 12:14:42.594553 CBT Training : PASS
3655 12:14:42.597758 Write leveling : PASS
3656 12:14:42.600765 RX DQS gating : PASS
3657 12:14:42.601294 RX DQ/DQS(RDDQC) : PASS
3658 12:14:42.603746 TX DQ/DQS : PASS
3659 12:14:42.607240 RX DATLAT : PASS
3660 12:14:42.607796 RX DQ/DQS(Engine): PASS
3661 12:14:42.610428 TX OE : NO K
3662 12:14:42.611014 All Pass.
3663 12:14:42.611496
3664 12:14:42.614085 CH 1, Rank 0
3665 12:14:42.614512 SW Impedance : PASS
3666 12:14:42.617059 DUTY Scan : NO K
3667 12:14:42.620379 ZQ Calibration : PASS
3668 12:14:42.620893 Jitter Meter : NO K
3669 12:14:42.623718 CBT Training : PASS
3670 12:14:42.627013 Write leveling : PASS
3671 12:14:42.627469 RX DQS gating : PASS
3672 12:14:42.630457 RX DQ/DQS(RDDQC) : PASS
3673 12:14:42.633407 TX DQ/DQS : PASS
3674 12:14:42.634003 RX DATLAT : PASS
3675 12:14:42.636852 RX DQ/DQS(Engine): PASS
3676 12:14:42.640123 TX OE : NO K
3677 12:14:42.640577 All Pass.
3678 12:14:42.640939
3679 12:14:42.641264 CH 1, Rank 1
3680 12:14:42.643431 SW Impedance : PASS
3681 12:14:42.646624 DUTY Scan : NO K
3682 12:14:42.647343 ZQ Calibration : PASS
3683 12:14:42.649871 Jitter Meter : NO K
3684 12:14:42.653088 CBT Training : PASS
3685 12:14:42.653658 Write leveling : PASS
3686 12:14:42.656340 RX DQS gating : PASS
3687 12:14:42.659600 RX DQ/DQS(RDDQC) : PASS
3688 12:14:42.660025 TX DQ/DQS : PASS
3689 12:14:42.663081 RX DATLAT : PASS
3690 12:14:42.666387 RX DQ/DQS(Engine): PASS
3691 12:14:42.666841 TX OE : NO K
3692 12:14:42.669799 All Pass.
3693 12:14:42.670219
3694 12:14:42.670550 DramC Write-DBI off
3695 12:14:42.672577 PER_BANK_REFRESH: Hybrid Mode
3696 12:14:42.673001 TX_TRACKING: ON
3697 12:14:42.682783 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3698 12:14:42.685969 [FAST_K] Save calibration result to emmc
3699 12:14:42.689438 dramc_set_vcore_voltage set vcore to 650000
3700 12:14:42.692582 Read voltage for 600, 5
3701 12:14:42.693009 Vio18 = 0
3702 12:14:42.695599 Vcore = 650000
3703 12:14:42.695681 Vdram = 0
3704 12:14:42.695746 Vddq = 0
3705 12:14:42.698973 Vmddr = 0
3706 12:14:42.702518 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3707 12:14:42.709058 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3708 12:14:42.709140 MEM_TYPE=3, freq_sel=19
3709 12:14:42.711884 sv_algorithm_assistance_LP4_1600
3710 12:14:42.718888 ============ PULL DRAM RESETB DOWN ============
3711 12:14:42.721907 ========== PULL DRAM RESETB DOWN end =========
3712 12:14:42.725379 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3713 12:14:42.728453 ===================================
3714 12:14:42.731500 LPDDR4 DRAM CONFIGURATION
3715 12:14:42.735104 ===================================
3716 12:14:42.738093 EX_ROW_EN[0] = 0x0
3717 12:14:42.738176 EX_ROW_EN[1] = 0x0
3718 12:14:42.741392 LP4Y_EN = 0x0
3719 12:14:42.741474 WORK_FSP = 0x0
3720 12:14:42.744807 WL = 0x2
3721 12:14:42.744895 RL = 0x2
3722 12:14:42.747997 BL = 0x2
3723 12:14:42.748100 RPST = 0x0
3724 12:14:42.751529 RD_PRE = 0x0
3725 12:14:42.751611 WR_PRE = 0x1
3726 12:14:42.754883 WR_PST = 0x0
3727 12:14:42.754964 DBI_WR = 0x0
3728 12:14:42.758339 DBI_RD = 0x0
3729 12:14:42.758421 OTF = 0x1
3730 12:14:42.761384 ===================================
3731 12:14:42.765004 ===================================
3732 12:14:42.767995 ANA top config
3733 12:14:42.771340 ===================================
3734 12:14:42.774851 DLL_ASYNC_EN = 0
3735 12:14:42.774932 ALL_SLAVE_EN = 1
3736 12:14:42.777709 NEW_RANK_MODE = 1
3737 12:14:42.781159 DLL_IDLE_MODE = 1
3738 12:14:42.784249 LP45_APHY_COMB_EN = 1
3739 12:14:42.787505 TX_ODT_DIS = 1
3740 12:14:42.787587 NEW_8X_MODE = 1
3741 12:14:42.791042 ===================================
3742 12:14:42.794045 ===================================
3743 12:14:42.797633 data_rate = 1200
3744 12:14:42.801103 CKR = 1
3745 12:14:42.804042 DQ_P2S_RATIO = 8
3746 12:14:42.807074 ===================================
3747 12:14:42.810443 CA_P2S_RATIO = 8
3748 12:14:42.813984 DQ_CA_OPEN = 0
3749 12:14:42.814087 DQ_SEMI_OPEN = 0
3750 12:14:42.817502 CA_SEMI_OPEN = 0
3751 12:14:42.820446 CA_FULL_RATE = 0
3752 12:14:42.824028 DQ_CKDIV4_EN = 1
3753 12:14:42.827060 CA_CKDIV4_EN = 1
3754 12:14:42.830373 CA_PREDIV_EN = 0
3755 12:14:42.830527 PH8_DLY = 0
3756 12:14:42.833665 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3757 12:14:42.837390 DQ_AAMCK_DIV = 4
3758 12:14:42.840342 CA_AAMCK_DIV = 4
3759 12:14:42.843399 CA_ADMCK_DIV = 4
3760 12:14:42.847239 DQ_TRACK_CA_EN = 0
3761 12:14:42.850458 CA_PICK = 600
3762 12:14:42.850770 CA_MCKIO = 600
3763 12:14:42.853600 MCKIO_SEMI = 0
3764 12:14:42.856466 PLL_FREQ = 2288
3765 12:14:42.859890 DQ_UI_PI_RATIO = 32
3766 12:14:42.863031 CA_UI_PI_RATIO = 0
3767 12:14:42.866727 ===================================
3768 12:14:42.870060 ===================================
3769 12:14:42.873527 memory_type:LPDDR4
3770 12:14:42.873610 GP_NUM : 10
3771 12:14:42.876847 SRAM_EN : 1
3772 12:14:42.876930 MD32_EN : 0
3773 12:14:42.879604 ===================================
3774 12:14:42.883061 [ANA_INIT] >>>>>>>>>>>>>>
3775 12:14:42.886600 <<<<<< [CONFIGURE PHASE]: ANA_TX
3776 12:14:42.889567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3777 12:14:42.893128 ===================================
3778 12:14:42.896648 data_rate = 1200,PCW = 0X5800
3779 12:14:42.899519 ===================================
3780 12:14:42.902994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3781 12:14:42.909617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3782 12:14:42.913192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3783 12:14:42.919480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3784 12:14:42.922380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3785 12:14:42.925790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3786 12:14:42.925944 [ANA_INIT] flow start
3787 12:14:42.929402 [ANA_INIT] PLL >>>>>>>>
3788 12:14:42.932783 [ANA_INIT] PLL <<<<<<<<
3789 12:14:42.935824 [ANA_INIT] MIDPI >>>>>>>>
3790 12:14:42.936105 [ANA_INIT] MIDPI <<<<<<<<
3791 12:14:42.939152 [ANA_INIT] DLL >>>>>>>>
3792 12:14:42.939427 [ANA_INIT] flow end
3793 12:14:42.946282 ============ LP4 DIFF to SE enter ============
3794 12:14:42.949287 ============ LP4 DIFF to SE exit ============
3795 12:14:42.952757 [ANA_INIT] <<<<<<<<<<<<<
3796 12:14:42.955710 [Flow] Enable top DCM control >>>>>
3797 12:14:42.958945 [Flow] Enable top DCM control <<<<<
3798 12:14:42.962572 Enable DLL master slave shuffle
3799 12:14:42.965812 ==============================================================
3800 12:14:42.969092 Gating Mode config
3801 12:14:42.975528 ==============================================================
3802 12:14:42.976080 Config description:
3803 12:14:42.985465 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3804 12:14:42.992226 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3805 12:14:42.995696 SELPH_MODE 0: By rank 1: By Phase
3806 12:14:43.002292 ==============================================================
3807 12:14:43.005299 GAT_TRACK_EN = 1
3808 12:14:43.008764 RX_GATING_MODE = 2
3809 12:14:43.011794 RX_GATING_TRACK_MODE = 2
3810 12:14:43.015253 SELPH_MODE = 1
3811 12:14:43.018237 PICG_EARLY_EN = 1
3812 12:14:43.021635 VALID_LAT_VALUE = 1
3813 12:14:43.025229 ==============================================================
3814 12:14:43.027869 Enter into Gating configuration >>>>
3815 12:14:43.031578 Exit from Gating configuration <<<<
3816 12:14:43.034962 Enter into DVFS_PRE_config >>>>>
3817 12:14:43.047629 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3818 12:14:43.050932 Exit from DVFS_PRE_config <<<<<
3819 12:14:43.054418 Enter into PICG configuration >>>>
3820 12:14:43.058192 Exit from PICG configuration <<<<
3821 12:14:43.058630 [RX_INPUT] configuration >>>>>
3822 12:14:43.061133 [RX_INPUT] configuration <<<<<
3823 12:14:43.067673 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3824 12:14:43.070990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3825 12:14:43.077658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3826 12:14:43.084373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3827 12:14:43.090786 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3828 12:14:43.097238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3829 12:14:43.100782 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3830 12:14:43.103827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3831 12:14:43.110544 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3832 12:14:43.113828 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3833 12:14:43.116832 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3834 12:14:43.123752 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3835 12:14:43.126877 ===================================
3836 12:14:43.127494 LPDDR4 DRAM CONFIGURATION
3837 12:14:43.130241 ===================================
3838 12:14:43.133624 EX_ROW_EN[0] = 0x0
3839 12:14:43.134210 EX_ROW_EN[1] = 0x0
3840 12:14:43.137178 LP4Y_EN = 0x0
3841 12:14:43.137663 WORK_FSP = 0x0
3842 12:14:43.140101 WL = 0x2
3843 12:14:43.143527 RL = 0x2
3844 12:14:43.144111 BL = 0x2
3845 12:14:43.146853 RPST = 0x0
3846 12:14:43.147377 RD_PRE = 0x0
3847 12:14:43.149759 WR_PRE = 0x1
3848 12:14:43.150301 WR_PST = 0x0
3849 12:14:43.153363 DBI_WR = 0x0
3850 12:14:43.153841 DBI_RD = 0x0
3851 12:14:43.156292 OTF = 0x1
3852 12:14:43.159890 ===================================
3853 12:14:43.162906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3854 12:14:43.166361 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3855 12:14:43.172991 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 12:14:43.176455 ===================================
3857 12:14:43.176924 LPDDR4 DRAM CONFIGURATION
3858 12:14:43.179322 ===================================
3859 12:14:43.182678 EX_ROW_EN[0] = 0x10
3860 12:14:43.185825 EX_ROW_EN[1] = 0x0
3861 12:14:43.186326 LP4Y_EN = 0x0
3862 12:14:43.189230 WORK_FSP = 0x0
3863 12:14:43.189671 WL = 0x2
3864 12:14:43.192571 RL = 0x2
3865 12:14:43.193031 BL = 0x2
3866 12:14:43.195926 RPST = 0x0
3867 12:14:43.196393 RD_PRE = 0x0
3868 12:14:43.199526 WR_PRE = 0x1
3869 12:14:43.199966 WR_PST = 0x0
3870 12:14:43.202726 DBI_WR = 0x0
3871 12:14:43.203179 DBI_RD = 0x0
3872 12:14:43.205805 OTF = 0x1
3873 12:14:43.209365 ===================================
3874 12:14:43.215838 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3875 12:14:43.218798 nWR fixed to 30
3876 12:14:43.222344 [ModeRegInit_LP4] CH0 RK0
3877 12:14:43.222767 [ModeRegInit_LP4] CH0 RK1
3878 12:14:43.225294 [ModeRegInit_LP4] CH1 RK0
3879 12:14:43.228810 [ModeRegInit_LP4] CH1 RK1
3880 12:14:43.229272 match AC timing 17
3881 12:14:43.235015 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3882 12:14:43.238551 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3883 12:14:43.242145 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3884 12:14:43.248533 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3885 12:14:43.251767 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3886 12:14:43.252218 ==
3887 12:14:43.255202 Dram Type= 6, Freq= 0, CH_0, rank 0
3888 12:14:43.258706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3889 12:14:43.259135 ==
3890 12:14:43.265012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3891 12:14:43.271172 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3892 12:14:43.274588 [CA 0] Center 36 (6~67) winsize 62
3893 12:14:43.278049 [CA 1] Center 36 (6~67) winsize 62
3894 12:14:43.281226 [CA 2] Center 34 (4~65) winsize 62
3895 12:14:43.284561 [CA 3] Center 34 (4~65) winsize 62
3896 12:14:43.288082 [CA 4] Center 33 (3~64) winsize 62
3897 12:14:43.291266 [CA 5] Center 33 (3~64) winsize 62
3898 12:14:43.291695
3899 12:14:43.294116 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3900 12:14:43.294541
3901 12:14:43.297957 [CATrainingPosCal] consider 1 rank data
3902 12:14:43.300749 u2DelayCellTimex100 = 270/100 ps
3903 12:14:43.304099 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3904 12:14:43.307849 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3905 12:14:43.310696 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3906 12:14:43.317659 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3907 12:14:43.320577 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3908 12:14:43.324133 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3909 12:14:43.324566
3910 12:14:43.327074 CA PerBit enable=1, Macro0, CA PI delay=33
3911 12:14:43.327505
3912 12:14:43.330641 [CBTSetCACLKResult] CA Dly = 33
3913 12:14:43.331073 CS Dly: 6 (0~37)
3914 12:14:43.331418 ==
3915 12:14:43.333654 Dram Type= 6, Freq= 0, CH_0, rank 1
3916 12:14:43.340339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3917 12:14:43.340790 ==
3918 12:14:43.343789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3919 12:14:43.350270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3920 12:14:43.353720 [CA 0] Center 36 (6~67) winsize 62
3921 12:14:43.357040 [CA 1] Center 36 (6~67) winsize 62
3922 12:14:43.360305 [CA 2] Center 34 (4~65) winsize 62
3923 12:14:43.363951 [CA 3] Center 34 (4~65) winsize 62
3924 12:14:43.366895 [CA 4] Center 34 (3~65) winsize 63
3925 12:14:43.370296 [CA 5] Center 34 (3~65) winsize 63
3926 12:14:43.371136
3927 12:14:43.373374 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3928 12:14:43.374152
3929 12:14:43.376641 [CATrainingPosCal] consider 2 rank data
3930 12:14:43.379974 u2DelayCellTimex100 = 270/100 ps
3931 12:14:43.383290 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3932 12:14:43.390086 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3933 12:14:43.393332 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3934 12:14:43.396692 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 12:14:43.399708 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3936 12:14:43.403094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3937 12:14:43.403526
3938 12:14:43.406198 CA PerBit enable=1, Macro0, CA PI delay=33
3939 12:14:43.406442
3940 12:14:43.409327 [CBTSetCACLKResult] CA Dly = 33
3941 12:14:43.412815 CS Dly: 6 (0~37)
3942 12:14:43.413095
3943 12:14:43.416232 ----->DramcWriteLeveling(PI) begin...
3944 12:14:43.416439 ==
3945 12:14:43.419351 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 12:14:43.422666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 12:14:43.422847 ==
3948 12:14:43.425719 Write leveling (Byte 0): 34 => 34
3949 12:14:43.429289 Write leveling (Byte 1): 30 => 30
3950 12:14:43.432889 DramcWriteLeveling(PI) end<-----
3951 12:14:43.432983
3952 12:14:43.433063 ==
3953 12:14:43.435531 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 12:14:43.439133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 12:14:43.439272 ==
3956 12:14:43.442118 [Gating] SW mode calibration
3957 12:14:43.448857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3958 12:14:43.455521 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3959 12:14:43.458535 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3960 12:14:43.461857 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3961 12:14:43.468512 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3962 12:14:43.471928 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
3963 12:14:43.478368 0 9 16 | B1->B0 | 2d2d 2929 | 1 1 | (1 1) (0 0)
3964 12:14:43.481767 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3965 12:14:43.485041 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 12:14:43.491888 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 12:14:43.494655 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 12:14:43.498060 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 12:14:43.504783 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 12:14:43.508132 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3971 12:14:43.511427 0 10 16 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
3972 12:14:43.517946 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3973 12:14:43.520992 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 12:14:43.524346 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 12:14:43.531357 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 12:14:43.534327 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 12:14:43.537839 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 12:14:43.544277 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 12:14:43.547931 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 12:14:43.550609 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 12:14:43.557697 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 12:14:43.560759 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 12:14:43.564005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 12:14:43.570667 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 12:14:43.574189 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 12:14:43.577038 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 12:14:43.583871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 12:14:43.587357 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 12:14:43.590461 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 12:14:43.597298 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:14:43.600297 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:14:43.603793 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:14:43.609980 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:14:43.613429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3995 12:14:43.616838 Total UI for P1: 0, mck2ui 16
3996 12:14:43.619922 best dqsien dly found for B0: ( 0, 13, 10)
3997 12:14:43.623469 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3998 12:14:43.629894 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 12:14:43.629977 Total UI for P1: 0, mck2ui 16
4000 12:14:43.633368 best dqsien dly found for B1: ( 0, 13, 14)
4001 12:14:43.639996 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4002 12:14:43.643388 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4003 12:14:43.643472
4004 12:14:43.646911 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4005 12:14:43.650019 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4006 12:14:43.653382 [Gating] SW calibration Done
4007 12:14:43.653464 ==
4008 12:14:43.656281 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 12:14:43.659712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 12:14:43.659850 ==
4011 12:14:43.663329 RX Vref Scan: 0
4012 12:14:43.663411
4013 12:14:43.663505 RX Vref 0 -> 0, step: 1
4014 12:14:43.663564
4015 12:14:43.666141 RX Delay -230 -> 252, step: 16
4016 12:14:43.673141 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4017 12:14:43.676256 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4018 12:14:43.679249 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4019 12:14:43.682683 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4020 12:14:43.685793 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4021 12:14:43.692630 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4022 12:14:43.695948 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4023 12:14:43.699508 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4024 12:14:43.702863 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4025 12:14:43.709206 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4026 12:14:43.712583 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4027 12:14:43.715857 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4028 12:14:43.719119 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4029 12:14:43.725748 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4030 12:14:43.728812 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4031 12:14:43.732213 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4032 12:14:43.732297 ==
4033 12:14:43.735825 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 12:14:43.738716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 12:14:43.742187 ==
4036 12:14:43.742270 DQS Delay:
4037 12:14:43.742336 DQS0 = 0, DQS1 = 0
4038 12:14:43.745233 DQM Delay:
4039 12:14:43.745315 DQM0 = 49, DQM1 = 38
4040 12:14:43.748685 DQ Delay:
4041 12:14:43.751865 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4042 12:14:43.751950 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4043 12:14:43.755496 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4044 12:14:43.758314 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4045 12:14:43.761731
4046 12:14:43.761814
4047 12:14:43.761880 ==
4048 12:14:43.765225 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 12:14:43.768696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 12:14:43.768788 ==
4051 12:14:43.768857
4052 12:14:43.768933
4053 12:14:43.771616 TX Vref Scan disable
4054 12:14:43.771700 == TX Byte 0 ==
4055 12:14:43.778436 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4056 12:14:43.781976 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4057 12:14:43.782061 == TX Byte 1 ==
4058 12:14:43.788288 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4059 12:14:43.791206 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4060 12:14:43.791282 ==
4061 12:14:43.794735 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 12:14:43.798025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 12:14:43.798103 ==
4064 12:14:43.801474
4065 12:14:43.801545
4066 12:14:43.801645 TX Vref Scan disable
4067 12:14:43.804874 == TX Byte 0 ==
4068 12:14:43.808004 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4069 12:14:43.815142 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4070 12:14:43.815228 == TX Byte 1 ==
4071 12:14:43.817960 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4072 12:14:43.824435 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4073 12:14:43.824521
4074 12:14:43.824588 [DATLAT]
4075 12:14:43.824651 Freq=600, CH0 RK0
4076 12:14:43.824711
4077 12:14:43.827893 DATLAT Default: 0x9
4078 12:14:43.831402 0, 0xFFFF, sum = 0
4079 12:14:43.831491 1, 0xFFFF, sum = 0
4080 12:14:43.834445 2, 0xFFFF, sum = 0
4081 12:14:43.834530 3, 0xFFFF, sum = 0
4082 12:14:43.837912 4, 0xFFFF, sum = 0
4083 12:14:43.837999 5, 0xFFFF, sum = 0
4084 12:14:43.840880 6, 0xFFFF, sum = 0
4085 12:14:43.840967 7, 0xFFFF, sum = 0
4086 12:14:43.844320 8, 0x0, sum = 1
4087 12:14:43.844407 9, 0x0, sum = 2
4088 12:14:43.847910 10, 0x0, sum = 3
4089 12:14:43.847995 11, 0x0, sum = 4
4090 12:14:43.848127 best_step = 9
4091 12:14:43.848189
4092 12:14:43.850768 ==
4093 12:14:43.854221 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 12:14:43.857727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 12:14:43.857812 ==
4096 12:14:43.857879 RX Vref Scan: 1
4097 12:14:43.857939
4098 12:14:43.860732 RX Vref 0 -> 0, step: 1
4099 12:14:43.860817
4100 12:14:43.864289 RX Delay -179 -> 252, step: 8
4101 12:14:43.864388
4102 12:14:43.867448 Set Vref, RX VrefLevel [Byte0]: 56
4103 12:14:43.870762 [Byte1]: 49
4104 12:14:43.870863
4105 12:14:43.873664 Final RX Vref Byte 0 = 56 to rank0
4106 12:14:43.877222 Final RX Vref Byte 1 = 49 to rank0
4107 12:14:43.880508 Final RX Vref Byte 0 = 56 to rank1
4108 12:14:43.883968 Final RX Vref Byte 1 = 49 to rank1==
4109 12:14:43.887009 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 12:14:43.893831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 12:14:43.893920 ==
4112 12:14:43.893989 DQS Delay:
4113 12:14:43.894051 DQS0 = 0, DQS1 = 0
4114 12:14:43.896870 DQM Delay:
4115 12:14:43.896954 DQM0 = 44, DQM1 = 36
4116 12:14:43.900166 DQ Delay:
4117 12:14:43.903695 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4118 12:14:43.907109 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4119 12:14:43.907212 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4120 12:14:43.913697 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4121 12:14:43.913778
4122 12:14:43.913845
4123 12:14:43.919946 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4124 12:14:43.923266 CH0 RK0: MR19=808, MR18=4C43
4125 12:14:43.930120 CH0_RK0: MR19=0x808, MR18=0x4C43, DQSOSC=395, MR23=63, INC=168, DEC=112
4126 12:14:43.930228
4127 12:14:43.933552 ----->DramcWriteLeveling(PI) begin...
4128 12:14:43.933628 ==
4129 12:14:43.936460 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 12:14:43.940188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 12:14:43.940269 ==
4132 12:14:43.943076 Write leveling (Byte 0): 34 => 34
4133 12:14:43.946492 Write leveling (Byte 1): 30 => 30
4134 12:14:43.950008 DramcWriteLeveling(PI) end<-----
4135 12:14:43.950080
4136 12:14:43.950143 ==
4137 12:14:43.952902 Dram Type= 6, Freq= 0, CH_0, rank 1
4138 12:14:43.956435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 12:14:43.956521 ==
4140 12:14:43.959836 [Gating] SW mode calibration
4141 12:14:43.966543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4142 12:14:43.972637 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4143 12:14:43.976307 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4144 12:14:43.982613 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4145 12:14:43.985984 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4146 12:14:43.989360 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4147 12:14:43.995938 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
4148 12:14:43.999214 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4149 12:14:44.002271 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 12:14:44.009107 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 12:14:44.012444 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 12:14:44.015291 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 12:14:44.022176 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 12:14:44.025641 0 10 12 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (0 0)
4155 12:14:44.028821 0 10 16 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
4156 12:14:44.035286 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4157 12:14:44.038826 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 12:14:44.041695 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 12:14:44.048313 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 12:14:44.051843 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 12:14:44.055265 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 12:14:44.061715 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 12:14:44.065260 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4164 12:14:44.068799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 12:14:44.075035 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 12:14:44.078400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 12:14:44.081175 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 12:14:44.087969 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 12:14:44.091561 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 12:14:44.094913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 12:14:44.101239 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 12:14:44.104572 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 12:14:44.107964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 12:14:44.114416 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:14:44.117725 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:14:44.120983 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:14:44.127369 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:14:44.130583 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4179 12:14:44.134065 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4180 12:14:44.137412 Total UI for P1: 0, mck2ui 16
4181 12:14:44.140888 best dqsien dly found for B0: ( 0, 13, 12)
4182 12:14:44.147439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 12:14:44.150455 Total UI for P1: 0, mck2ui 16
4184 12:14:44.153838 best dqsien dly found for B1: ( 0, 13, 14)
4185 12:14:44.157245 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4186 12:14:44.160289 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4187 12:14:44.160372
4188 12:14:44.163842 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4189 12:14:44.166977 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4190 12:14:44.170320 [Gating] SW calibration Done
4191 12:14:44.170404 ==
4192 12:14:44.173211 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 12:14:44.176544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 12:14:44.176627 ==
4195 12:14:44.180259 RX Vref Scan: 0
4196 12:14:44.180357
4197 12:14:44.183458 RX Vref 0 -> 0, step: 1
4198 12:14:44.183541
4199 12:14:44.186890 RX Delay -230 -> 252, step: 16
4200 12:14:44.189881 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4201 12:14:44.193405 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4202 12:14:44.196369 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4203 12:14:44.203184 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4204 12:14:44.206601 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4205 12:14:44.209767 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4206 12:14:44.213052 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4207 12:14:44.216502 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4208 12:14:44.222553 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4209 12:14:44.225895 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4210 12:14:44.229254 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4211 12:14:44.232722 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4212 12:14:44.239410 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4213 12:14:44.242920 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4214 12:14:44.245993 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4215 12:14:44.248978 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4216 12:14:44.252453 ==
4217 12:14:44.252538 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 12:14:44.259027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 12:14:44.259111 ==
4220 12:14:44.259176 DQS Delay:
4221 12:14:44.262396 DQS0 = 0, DQS1 = 0
4222 12:14:44.262478 DQM Delay:
4223 12:14:44.266053 DQM0 = 49, DQM1 = 38
4224 12:14:44.266136 DQ Delay:
4225 12:14:44.268839 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4226 12:14:44.272350 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4227 12:14:44.276001 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4228 12:14:44.278879 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4229 12:14:44.278962
4230 12:14:44.279027
4231 12:14:44.279087 ==
4232 12:14:44.282376 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 12:14:44.285392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 12:14:44.285476 ==
4235 12:14:44.285541
4236 12:14:44.285601
4237 12:14:44.288598 TX Vref Scan disable
4238 12:14:44.292068 == TX Byte 0 ==
4239 12:14:44.295107 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4240 12:14:44.298759 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4241 12:14:44.302140 == TX Byte 1 ==
4242 12:14:44.305449 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4243 12:14:44.308843 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4244 12:14:44.308940 ==
4245 12:14:44.311585 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 12:14:44.318724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 12:14:44.318807 ==
4248 12:14:44.318940
4249 12:14:44.318999
4250 12:14:44.319086 TX Vref Scan disable
4251 12:14:44.322969 == TX Byte 0 ==
4252 12:14:44.326221 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4253 12:14:44.332525 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4254 12:14:44.332624 == TX Byte 1 ==
4255 12:14:44.335890 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 12:14:44.342537 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 12:14:44.342651
4258 12:14:44.342746 [DATLAT]
4259 12:14:44.342857 Freq=600, CH0 RK1
4260 12:14:44.342979
4261 12:14:44.345859 DATLAT Default: 0x9
4262 12:14:44.349440 0, 0xFFFF, sum = 0
4263 12:14:44.349549 1, 0xFFFF, sum = 0
4264 12:14:44.352328 2, 0xFFFF, sum = 0
4265 12:14:44.352428 3, 0xFFFF, sum = 0
4266 12:14:44.355924 4, 0xFFFF, sum = 0
4267 12:14:44.356000 5, 0xFFFF, sum = 0
4268 12:14:44.358972 6, 0xFFFF, sum = 0
4269 12:14:44.359119 7, 0xFFFF, sum = 0
4270 12:14:44.362666 8, 0x0, sum = 1
4271 12:14:44.362785 9, 0x0, sum = 2
4272 12:14:44.365605 10, 0x0, sum = 3
4273 12:14:44.365725 11, 0x0, sum = 4
4274 12:14:44.365855 best_step = 9
4275 12:14:44.365946
4276 12:14:44.369263 ==
4277 12:14:44.371994 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 12:14:44.375536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 12:14:44.375653 ==
4280 12:14:44.375745 RX Vref Scan: 0
4281 12:14:44.375838
4282 12:14:44.378967 RX Vref 0 -> 0, step: 1
4283 12:14:44.379069
4284 12:14:44.381825 RX Delay -179 -> 252, step: 8
4285 12:14:44.388745 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4286 12:14:44.392283 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4287 12:14:44.395514 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4288 12:14:44.398423 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4289 12:14:44.402078 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4290 12:14:44.408757 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4291 12:14:44.411560 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4292 12:14:44.414972 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4293 12:14:44.418646 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4294 12:14:44.425052 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4295 12:14:44.428412 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4296 12:14:44.431806 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4297 12:14:44.435156 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4298 12:14:44.441310 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4299 12:14:44.444617 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4300 12:14:44.447871 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4301 12:14:44.447994 ==
4302 12:14:44.451463 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 12:14:44.454390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 12:14:44.454495 ==
4305 12:14:44.458012 DQS Delay:
4306 12:14:44.458117 DQS0 = 0, DQS1 = 0
4307 12:14:44.460926 DQM Delay:
4308 12:14:44.461025 DQM0 = 43, DQM1 = 37
4309 12:14:44.461119 DQ Delay:
4310 12:14:44.464281 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4311 12:14:44.467850 DQ4 =48, DQ5 =32, DQ6 =52, DQ7 =48
4312 12:14:44.471295 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4313 12:14:44.474335 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4314 12:14:44.474463
4315 12:14:44.477877
4316 12:14:44.484141 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4317 12:14:44.487719 CH0 RK1: MR19=808, MR18=3D38
4318 12:14:44.494140 CH0_RK1: MR19=0x808, MR18=0x3D38, DQSOSC=398, MR23=63, INC=165, DEC=110
4319 12:14:44.497061 [RxdqsGatingPostProcess] freq 600
4320 12:14:44.500980 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4321 12:14:44.503847 Pre-setting of DQS Precalculation
4322 12:14:44.510196 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4323 12:14:44.510305 ==
4324 12:14:44.513430 Dram Type= 6, Freq= 0, CH_1, rank 0
4325 12:14:44.516858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 12:14:44.516964 ==
4327 12:14:44.523375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4328 12:14:44.530425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4329 12:14:44.533217 [CA 0] Center 36 (6~66) winsize 61
4330 12:14:44.536618 [CA 1] Center 35 (5~66) winsize 62
4331 12:14:44.539927 [CA 2] Center 34 (4~65) winsize 62
4332 12:14:44.543173 [CA 3] Center 34 (3~65) winsize 63
4333 12:14:44.546561 [CA 4] Center 34 (4~65) winsize 62
4334 12:14:44.549845 [CA 5] Center 34 (3~65) winsize 63
4335 12:14:44.549929
4336 12:14:44.553224 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4337 12:14:44.553307
4338 12:14:44.557033 [CATrainingPosCal] consider 1 rank data
4339 12:14:44.559969 u2DelayCellTimex100 = 270/100 ps
4340 12:14:44.563549 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4341 12:14:44.566511 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4342 12:14:44.569837 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4343 12:14:44.573403 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4344 12:14:44.576742 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4345 12:14:44.579715 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4346 12:14:44.579799
4347 12:14:44.586161 CA PerBit enable=1, Macro0, CA PI delay=34
4348 12:14:44.586245
4349 12:14:44.586312 [CBTSetCACLKResult] CA Dly = 34
4350 12:14:44.589721 CS Dly: 4 (0~35)
4351 12:14:44.589804 ==
4352 12:14:44.593245 Dram Type= 6, Freq= 0, CH_1, rank 1
4353 12:14:44.596152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 12:14:44.596238 ==
4355 12:14:44.603028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 12:14:44.609508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4357 12:14:44.613085 [CA 0] Center 35 (5~66) winsize 62
4358 12:14:44.615806 [CA 1] Center 36 (6~66) winsize 61
4359 12:14:44.619227 [CA 2] Center 34 (4~65) winsize 62
4360 12:14:44.622536 [CA 3] Center 34 (3~65) winsize 63
4361 12:14:44.626145 [CA 4] Center 34 (4~65) winsize 62
4362 12:14:44.629046 [CA 5] Center 34 (3~65) winsize 63
4363 12:14:44.629132
4364 12:14:44.632321 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4365 12:14:44.632406
4366 12:14:44.635751 [CATrainingPosCal] consider 2 rank data
4367 12:14:44.639109 u2DelayCellTimex100 = 270/100 ps
4368 12:14:44.642401 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4369 12:14:44.645394 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4370 12:14:44.648812 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4371 12:14:44.652022 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4372 12:14:44.658941 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4373 12:14:44.661773 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4374 12:14:44.661875
4375 12:14:44.665299 CA PerBit enable=1, Macro0, CA PI delay=34
4376 12:14:44.665409
4377 12:14:44.668872 [CBTSetCACLKResult] CA Dly = 34
4378 12:14:44.668974 CS Dly: 4 (0~35)
4379 12:14:44.669066
4380 12:14:44.671590 ----->DramcWriteLeveling(PI) begin...
4381 12:14:44.671702 ==
4382 12:14:44.675244 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 12:14:44.681615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 12:14:44.681701 ==
4385 12:14:44.685025 Write leveling (Byte 0): 30 => 30
4386 12:14:44.688097 Write leveling (Byte 1): 30 => 30
4387 12:14:44.688196 DramcWriteLeveling(PI) end<-----
4388 12:14:44.691409
4389 12:14:44.691510 ==
4390 12:14:44.695034 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 12:14:44.697949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 12:14:44.698058 ==
4393 12:14:44.701421 [Gating] SW mode calibration
4394 12:14:44.707765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4395 12:14:44.711271 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4396 12:14:44.717654 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4397 12:14:44.721200 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4398 12:14:44.724425 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4399 12:14:44.731001 0 9 12 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
4400 12:14:44.734351 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4401 12:14:44.737844 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 12:14:44.744007 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 12:14:44.747400 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 12:14:44.750948 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 12:14:44.757531 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 12:14:44.761057 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 12:14:44.763959 0 10 12 | B1->B0 | 3232 3838 | 0 0 | (0 0) (1 1)
4408 12:14:44.770385 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4409 12:14:44.773585 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 12:14:44.780550 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 12:14:44.783629 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 12:14:44.787061 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 12:14:44.793387 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 12:14:44.796962 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 12:14:44.799823 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 12:14:44.806304 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4417 12:14:44.809898 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 12:14:44.813329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 12:14:44.820105 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 12:14:44.822930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 12:14:44.826586 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 12:14:44.832827 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 12:14:44.836452 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 12:14:44.839469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 12:14:44.845870 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 12:14:44.849354 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:14:44.852900 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:14:44.859400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:14:44.862955 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:14:44.865923 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:14:44.872482 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:14:44.875596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 12:14:44.879208 Total UI for P1: 0, mck2ui 16
4434 12:14:44.882881 best dqsien dly found for B0: ( 0, 13, 14)
4435 12:14:44.885875 Total UI for P1: 0, mck2ui 16
4436 12:14:44.888908 best dqsien dly found for B1: ( 0, 13, 14)
4437 12:14:44.892476 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4438 12:14:44.896072 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4439 12:14:44.896155
4440 12:14:44.899130 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4441 12:14:44.902102 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4442 12:14:44.905676 [Gating] SW calibration Done
4443 12:14:44.905761 ==
4444 12:14:44.908675 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 12:14:44.912209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 12:14:44.912315 ==
4447 12:14:44.915745 RX Vref Scan: 0
4448 12:14:44.915822
4449 12:14:44.919035 RX Vref 0 -> 0, step: 1
4450 12:14:44.919152
4451 12:14:44.922259 RX Delay -230 -> 252, step: 16
4452 12:14:44.925553 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4453 12:14:44.929023 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4454 12:14:44.931866 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4455 12:14:44.938444 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4456 12:14:44.941991 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4457 12:14:44.944932 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4458 12:14:44.947979 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4459 12:14:44.951679 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4460 12:14:44.958613 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4461 12:14:44.961539 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4462 12:14:44.964924 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4463 12:14:44.968452 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4464 12:14:44.974725 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4465 12:14:44.978441 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4466 12:14:44.981532 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4467 12:14:44.984566 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4468 12:14:44.988134 ==
4469 12:14:44.991229 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 12:14:44.994808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 12:14:44.994931 ==
4472 12:14:44.995032 DQS Delay:
4473 12:14:44.997610 DQS0 = 0, DQS1 = 0
4474 12:14:44.997731 DQM Delay:
4475 12:14:45.001175 DQM0 = 44, DQM1 = 39
4476 12:14:45.001315 DQ Delay:
4477 12:14:45.004056 DQ0 =57, DQ1 =33, DQ2 =33, DQ3 =41
4478 12:14:45.007873 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4479 12:14:45.010920 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4480 12:14:45.014173 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4481 12:14:45.014399
4482 12:14:45.014571
4483 12:14:45.014739 ==
4484 12:14:45.017756 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 12:14:45.020619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 12:14:45.020925 ==
4487 12:14:45.021152
4488 12:14:45.024198
4489 12:14:45.024523 TX Vref Scan disable
4490 12:14:45.027740 == TX Byte 0 ==
4491 12:14:45.030954 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4492 12:14:45.033998 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4493 12:14:45.037526 == TX Byte 1 ==
4494 12:14:45.041076 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4495 12:14:45.043989 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4496 12:14:45.044535 ==
4497 12:14:45.046991 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 12:14:45.054046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 12:14:45.054590 ==
4500 12:14:45.054948
4501 12:14:45.055261
4502 12:14:45.057013 TX Vref Scan disable
4503 12:14:45.057423 == TX Byte 0 ==
4504 12:14:45.063781 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4505 12:14:45.066646 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4506 12:14:45.067206 == TX Byte 1 ==
4507 12:14:45.073662 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 12:14:45.076691 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 12:14:45.077202
4510 12:14:45.077702 [DATLAT]
4511 12:14:45.080120 Freq=600, CH1 RK0
4512 12:14:45.080553
4513 12:14:45.081034 DATLAT Default: 0x9
4514 12:14:45.083210 0, 0xFFFF, sum = 0
4515 12:14:45.086683 1, 0xFFFF, sum = 0
4516 12:14:45.087237 2, 0xFFFF, sum = 0
4517 12:14:45.089695 3, 0xFFFF, sum = 0
4518 12:14:45.090524 4, 0xFFFF, sum = 0
4519 12:14:45.093246 5, 0xFFFF, sum = 0
4520 12:14:45.093893 6, 0xFFFF, sum = 0
4521 12:14:45.096803 7, 0xFFFF, sum = 0
4522 12:14:45.097326 8, 0x0, sum = 1
4523 12:14:45.099742 9, 0x0, sum = 2
4524 12:14:45.100384 10, 0x0, sum = 3
4525 12:14:45.100868 11, 0x0, sum = 4
4526 12:14:45.102706 best_step = 9
4527 12:14:45.103216
4528 12:14:45.103592 ==
4529 12:14:45.106472 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 12:14:45.109426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 12:14:45.109817 ==
4532 12:14:45.113025 RX Vref Scan: 1
4533 12:14:45.113425
4534 12:14:45.115992 RX Vref 0 -> 0, step: 1
4535 12:14:45.116417
4536 12:14:45.116725 RX Delay -179 -> 252, step: 8
4537 12:14:45.117010
4538 12:14:45.119852 Set Vref, RX VrefLevel [Byte0]: 53
4539 12:14:45.122784 [Byte1]: 48
4540 12:14:45.127386
4541 12:14:45.127810 Final RX Vref Byte 0 = 53 to rank0
4542 12:14:45.130558 Final RX Vref Byte 1 = 48 to rank0
4543 12:14:45.134111 Final RX Vref Byte 0 = 53 to rank1
4544 12:14:45.137348 Final RX Vref Byte 1 = 48 to rank1==
4545 12:14:45.140991 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 12:14:45.147159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 12:14:45.147674 ==
4548 12:14:45.147996 DQS Delay:
4549 12:14:45.150312 DQS0 = 0, DQS1 = 0
4550 12:14:45.150699 DQM Delay:
4551 12:14:45.151008 DQM0 = 40, DQM1 = 34
4552 12:14:45.154011 DQ Delay:
4553 12:14:45.157034 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4554 12:14:45.160311 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4555 12:14:45.163734 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4556 12:14:45.167336 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4557 12:14:45.167853
4558 12:14:45.168357
4559 12:14:45.173239 [DQSOSCAuto] RK0, (LSB)MR18= 0x2740, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4560 12:14:45.176765 CH1 RK0: MR19=808, MR18=2740
4561 12:14:45.183000 CH1_RK0: MR19=0x808, MR18=0x2740, DQSOSC=397, MR23=63, INC=166, DEC=110
4562 12:14:45.183472
4563 12:14:45.186586 ----->DramcWriteLeveling(PI) begin...
4564 12:14:45.187153 ==
4565 12:14:45.190221 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 12:14:45.193313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 12:14:45.193906 ==
4568 12:14:45.196999 Write leveling (Byte 0): 27 => 27
4569 12:14:45.199804 Write leveling (Byte 1): 30 => 30
4570 12:14:45.203415 DramcWriteLeveling(PI) end<-----
4571 12:14:45.203860
4572 12:14:45.204276 ==
4573 12:14:45.206345 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 12:14:45.209908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:14:45.213256 ==
4576 12:14:45.213647 [Gating] SW mode calibration
4577 12:14:45.223050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4578 12:14:45.226150 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4579 12:14:45.229665 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4580 12:14:45.235961 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4581 12:14:45.238980 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4582 12:14:45.242731 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 0)
4583 12:14:45.249137 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4584 12:14:45.252662 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 12:14:45.255675 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 12:14:45.262308 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 12:14:45.265797 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 12:14:45.269291 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 12:14:45.275764 0 10 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
4590 12:14:45.278672 0 10 12 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
4591 12:14:45.281993 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4592 12:14:45.288792 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 12:14:45.291775 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 12:14:45.295358 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 12:14:45.301772 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 12:14:45.305273 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 12:14:45.308177 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4598 12:14:45.314830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 12:14:45.318334 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 12:14:45.321900 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 12:14:45.328492 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 12:14:45.331376 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 12:14:45.334948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 12:14:45.341352 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 12:14:45.345031 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 12:14:45.347864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 12:14:45.354579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 12:14:45.357882 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 12:14:45.361253 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 12:14:45.367822 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:14:45.370772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:14:45.374342 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:14:45.380934 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4614 12:14:45.383880 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 12:14:45.387416 Total UI for P1: 0, mck2ui 16
4616 12:14:45.390753 best dqsien dly found for B0: ( 0, 13, 8)
4617 12:14:45.394269 Total UI for P1: 0, mck2ui 16
4618 12:14:45.397067 best dqsien dly found for B1: ( 0, 13, 10)
4619 12:14:45.400982 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4620 12:14:45.403671 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4621 12:14:45.404196
4622 12:14:45.407292 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4623 12:14:45.413793 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4624 12:14:45.414193 [Gating] SW calibration Done
4625 12:14:45.414591 ==
4626 12:14:45.417453 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 12:14:45.423554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 12:14:45.423993 ==
4629 12:14:45.424461 RX Vref Scan: 0
4630 12:14:45.424870
4631 12:14:45.427026 RX Vref 0 -> 0, step: 1
4632 12:14:45.427446
4633 12:14:45.430163 RX Delay -230 -> 252, step: 16
4634 12:14:45.433760 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4635 12:14:45.436649 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4636 12:14:45.443589 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4637 12:14:45.446567 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4638 12:14:45.450102 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4639 12:14:45.453177 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4640 12:14:45.460095 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4641 12:14:45.463022 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4642 12:14:45.466754 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4643 12:14:45.469463 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4644 12:14:45.473059 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4645 12:14:45.479459 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4646 12:14:45.482992 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4647 12:14:45.486099 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4648 12:14:45.492681 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4649 12:14:45.495855 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4650 12:14:45.496295 ==
4651 12:14:45.499545 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 12:14:45.502528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 12:14:45.502930 ==
4654 12:14:45.505942 DQS Delay:
4655 12:14:45.506336 DQS0 = 0, DQS1 = 0
4656 12:14:45.506732 DQM Delay:
4657 12:14:45.509087 DQM0 = 40, DQM1 = 39
4658 12:14:45.509486 DQ Delay:
4659 12:14:45.512552 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4660 12:14:45.515595 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4661 12:14:45.519199 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4662 12:14:45.522152 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4663 12:14:45.522550
4664 12:14:45.522948
4665 12:14:45.523326 ==
4666 12:14:45.525746 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 12:14:45.532402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 12:14:45.532801 ==
4669 12:14:45.533200
4670 12:14:45.533589
4671 12:14:45.534064 TX Vref Scan disable
4672 12:14:45.535934 == TX Byte 0 ==
4673 12:14:45.539134 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4674 12:14:45.545495 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4675 12:14:45.545887 == TX Byte 1 ==
4676 12:14:45.549080 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4677 12:14:45.555730 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4678 12:14:45.556154 ==
4679 12:14:45.558649 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 12:14:45.562413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 12:14:45.562840 ==
4682 12:14:45.563192
4683 12:14:45.563499
4684 12:14:45.565716 TX Vref Scan disable
4685 12:14:45.568747 == TX Byte 0 ==
4686 12:14:45.572305 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4687 12:14:45.575285 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4688 12:14:45.578778 == TX Byte 1 ==
4689 12:14:45.581702 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4690 12:14:45.585128 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4691 12:14:45.585528
4692 12:14:45.588575 [DATLAT]
4693 12:14:45.588964 Freq=600, CH1 RK1
4694 12:14:45.589275
4695 12:14:45.591422 DATLAT Default: 0x9
4696 12:14:45.591835 0, 0xFFFF, sum = 0
4697 12:14:45.595215 1, 0xFFFF, sum = 0
4698 12:14:45.595612 2, 0xFFFF, sum = 0
4699 12:14:45.598588 3, 0xFFFF, sum = 0
4700 12:14:45.598982 4, 0xFFFF, sum = 0
4701 12:14:45.601403 5, 0xFFFF, sum = 0
4702 12:14:45.601800 6, 0xFFFF, sum = 0
4703 12:14:45.605003 7, 0xFFFF, sum = 0
4704 12:14:45.605399 8, 0x0, sum = 1
4705 12:14:45.608685 9, 0x0, sum = 2
4706 12:14:45.609082 10, 0x0, sum = 3
4707 12:14:45.611493 11, 0x0, sum = 4
4708 12:14:45.611890 best_step = 9
4709 12:14:45.612258
4710 12:14:45.612554 ==
4711 12:14:45.614540 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 12:14:45.618301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 12:14:45.621080 ==
4714 12:14:45.621581 RX Vref Scan: 0
4715 12:14:45.621907
4716 12:14:45.624693 RX Vref 0 -> 0, step: 1
4717 12:14:45.625090
4718 12:14:45.627691 RX Delay -179 -> 252, step: 8
4719 12:14:45.631323 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4720 12:14:45.634363 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4721 12:14:45.640995 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4722 12:14:45.644404 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4723 12:14:45.647414 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4724 12:14:45.650548 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4725 12:14:45.657196 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4726 12:14:45.660606 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4727 12:14:45.663765 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4728 12:14:45.667140 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4729 12:14:45.673439 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4730 12:14:45.677257 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4731 12:14:45.680623 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4732 12:14:45.683566 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4733 12:14:45.690443 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4734 12:14:45.693682 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4735 12:14:45.694068 ==
4736 12:14:45.696565 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 12:14:45.700002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 12:14:45.700400 ==
4739 12:14:45.703219 DQS Delay:
4740 12:14:45.703694 DQS0 = 0, DQS1 = 0
4741 12:14:45.706612 DQM Delay:
4742 12:14:45.707006 DQM0 = 38, DQM1 = 34
4743 12:14:45.707320 DQ Delay:
4744 12:14:45.709823 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4745 12:14:45.713297 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4746 12:14:45.716448 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4747 12:14:45.720107 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4748 12:14:45.720585
4749 12:14:45.720941
4750 12:14:45.729603 [DQSOSCAuto] RK1, (LSB)MR18= 0x355a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4751 12:14:45.732682 CH1 RK1: MR19=808, MR18=355A
4752 12:14:45.739612 CH1_RK1: MR19=0x808, MR18=0x355A, DQSOSC=392, MR23=63, INC=170, DEC=113
4753 12:14:45.740072 [RxdqsGatingPostProcess] freq 600
4754 12:14:45.746353 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4755 12:14:45.749504 Pre-setting of DQS Precalculation
4756 12:14:45.756106 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4757 12:14:45.762519 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4758 12:14:45.769375 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4759 12:14:45.769802
4760 12:14:45.770156
4761 12:14:45.772091 [Calibration Summary] 1200 Mbps
4762 12:14:45.772567 CH 0, Rank 0
4763 12:14:45.775525 SW Impedance : PASS
4764 12:14:45.778987 DUTY Scan : NO K
4765 12:14:45.779494 ZQ Calibration : PASS
4766 12:14:45.782517 Jitter Meter : NO K
4767 12:14:45.782959 CBT Training : PASS
4768 12:14:45.785627 Write leveling : PASS
4769 12:14:45.788703 RX DQS gating : PASS
4770 12:14:45.789145 RX DQ/DQS(RDDQC) : PASS
4771 12:14:45.792156 TX DQ/DQS : PASS
4772 12:14:45.795621 RX DATLAT : PASS
4773 12:14:45.796014 RX DQ/DQS(Engine): PASS
4774 12:14:45.798680 TX OE : NO K
4775 12:14:45.799071 All Pass.
4776 12:14:45.799450
4777 12:14:45.802288 CH 0, Rank 1
4778 12:14:45.802727 SW Impedance : PASS
4779 12:14:45.805345 DUTY Scan : NO K
4780 12:14:45.808621 ZQ Calibration : PASS
4781 12:14:45.809084 Jitter Meter : NO K
4782 12:14:45.811929 CBT Training : PASS
4783 12:14:45.815383 Write leveling : PASS
4784 12:14:45.815809 RX DQS gating : PASS
4785 12:14:45.818223 RX DQ/DQS(RDDQC) : PASS
4786 12:14:45.821904 TX DQ/DQS : PASS
4787 12:14:45.822347 RX DATLAT : PASS
4788 12:14:45.825184 RX DQ/DQS(Engine): PASS
4789 12:14:45.828275 TX OE : NO K
4790 12:14:45.828776 All Pass.
4791 12:14:45.829147
4792 12:14:45.829465 CH 1, Rank 0
4793 12:14:45.831879 SW Impedance : PASS
4794 12:14:45.834956 DUTY Scan : NO K
4795 12:14:45.835348 ZQ Calibration : PASS
4796 12:14:45.838624 Jitter Meter : NO K
4797 12:14:45.841838 CBT Training : PASS
4798 12:14:45.842230 Write leveling : PASS
4799 12:14:45.844723 RX DQS gating : PASS
4800 12:14:45.848535 RX DQ/DQS(RDDQC) : PASS
4801 12:14:45.848984 TX DQ/DQS : PASS
4802 12:14:45.851438 RX DATLAT : PASS
4803 12:14:45.851837 RX DQ/DQS(Engine): PASS
4804 12:14:45.855148 TX OE : NO K
4805 12:14:45.855595 All Pass.
4806 12:14:45.855941
4807 12:14:45.858229 CH 1, Rank 1
4808 12:14:45.861892 SW Impedance : PASS
4809 12:14:45.862301 DUTY Scan : NO K
4810 12:14:45.864597 ZQ Calibration : PASS
4811 12:14:45.865117 Jitter Meter : NO K
4812 12:14:45.868117 CBT Training : PASS
4813 12:14:45.871743 Write leveling : PASS
4814 12:14:45.872172 RX DQS gating : PASS
4815 12:14:45.874608 RX DQ/DQS(RDDQC) : PASS
4816 12:14:45.877742 TX DQ/DQS : PASS
4817 12:14:45.878140 RX DATLAT : PASS
4818 12:14:45.881165 RX DQ/DQS(Engine): PASS
4819 12:14:45.884641 TX OE : NO K
4820 12:14:45.885092 All Pass.
4821 12:14:45.885464
4822 12:14:45.887650 DramC Write-DBI off
4823 12:14:45.888186 PER_BANK_REFRESH: Hybrid Mode
4824 12:14:45.891354 TX_TRACKING: ON
4825 12:14:45.900952 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4826 12:14:45.903886 [FAST_K] Save calibration result to emmc
4827 12:14:45.907295 dramc_set_vcore_voltage set vcore to 662500
4828 12:14:45.907378 Read voltage for 933, 3
4829 12:14:45.910212 Vio18 = 0
4830 12:14:45.910295 Vcore = 662500
4831 12:14:45.910361 Vdram = 0
4832 12:14:45.913739 Vddq = 0
4833 12:14:45.913821 Vmddr = 0
4834 12:14:45.920623 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4835 12:14:45.923445 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4836 12:14:45.926569 MEM_TYPE=3, freq_sel=17
4837 12:14:45.930165 sv_algorithm_assistance_LP4_1600
4838 12:14:45.933688 ============ PULL DRAM RESETB DOWN ============
4839 12:14:45.937127 ========== PULL DRAM RESETB DOWN end =========
4840 12:14:45.943680 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4841 12:14:45.946691 ===================================
4842 12:14:45.947219 LPDDR4 DRAM CONFIGURATION
4843 12:14:45.950241 ===================================
4844 12:14:45.953319 EX_ROW_EN[0] = 0x0
4845 12:14:45.956922 EX_ROW_EN[1] = 0x0
4846 12:14:45.957364 LP4Y_EN = 0x0
4847 12:14:45.960123 WORK_FSP = 0x0
4848 12:14:45.960655 WL = 0x3
4849 12:14:45.963482 RL = 0x3
4850 12:14:45.963939 BL = 0x2
4851 12:14:45.967069 RPST = 0x0
4852 12:14:45.967471 RD_PRE = 0x0
4853 12:14:45.969951 WR_PRE = 0x1
4854 12:14:45.970399 WR_PST = 0x0
4855 12:14:45.973201 DBI_WR = 0x0
4856 12:14:45.973674 DBI_RD = 0x0
4857 12:14:45.977053 OTF = 0x1
4858 12:14:45.979953 ===================================
4859 12:14:45.983365 ===================================
4860 12:14:45.983750 ANA top config
4861 12:14:45.986650 ===================================
4862 12:14:45.990432 DLL_ASYNC_EN = 0
4863 12:14:45.993403 ALL_SLAVE_EN = 1
4864 12:14:45.996303 NEW_RANK_MODE = 1
4865 12:14:45.997045 DLL_IDLE_MODE = 1
4866 12:14:45.999718 LP45_APHY_COMB_EN = 1
4867 12:14:46.003175 TX_ODT_DIS = 1
4868 12:14:46.006058 NEW_8X_MODE = 1
4869 12:14:46.009632 ===================================
4870 12:14:46.012697 ===================================
4871 12:14:46.016223 data_rate = 1866
4872 12:14:46.019303 CKR = 1
4873 12:14:46.019724 DQ_P2S_RATIO = 8
4874 12:14:46.022580 ===================================
4875 12:14:46.025986 CA_P2S_RATIO = 8
4876 12:14:46.029271 DQ_CA_OPEN = 0
4877 12:14:46.032166 DQ_SEMI_OPEN = 0
4878 12:14:46.036122 CA_SEMI_OPEN = 0
4879 12:14:46.039134 CA_FULL_RATE = 0
4880 12:14:46.039566 DQ_CKDIV4_EN = 1
4881 12:14:46.042065 CA_CKDIV4_EN = 1
4882 12:14:46.045762 CA_PREDIV_EN = 0
4883 12:14:46.049343 PH8_DLY = 0
4884 12:14:46.052359 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4885 12:14:46.055424 DQ_AAMCK_DIV = 4
4886 12:14:46.055960 CA_AAMCK_DIV = 4
4887 12:14:46.059155 CA_ADMCK_DIV = 4
4888 12:14:46.062126 DQ_TRACK_CA_EN = 0
4889 12:14:46.065164 CA_PICK = 933
4890 12:14:46.068701 CA_MCKIO = 933
4891 12:14:46.071620 MCKIO_SEMI = 0
4892 12:14:46.075341 PLL_FREQ = 3732
4893 12:14:46.078681 DQ_UI_PI_RATIO = 32
4894 12:14:46.079145 CA_UI_PI_RATIO = 0
4895 12:14:46.081630 ===================================
4896 12:14:46.085324 ===================================
4897 12:14:46.088157 memory_type:LPDDR4
4898 12:14:46.091505 GP_NUM : 10
4899 12:14:46.091963 SRAM_EN : 1
4900 12:14:46.095136 MD32_EN : 0
4901 12:14:46.097998 ===================================
4902 12:14:46.101554 [ANA_INIT] >>>>>>>>>>>>>>
4903 12:14:46.104523 <<<<<< [CONFIGURE PHASE]: ANA_TX
4904 12:14:46.108099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4905 12:14:46.111356 ===================================
4906 12:14:46.111779 data_rate = 1866,PCW = 0X8f00
4907 12:14:46.114466 ===================================
4908 12:14:46.118004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4909 12:14:46.124390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4910 12:14:46.131141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4911 12:14:46.134481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4912 12:14:46.137631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4913 12:14:46.140744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4914 12:14:46.143926 [ANA_INIT] flow start
4915 12:14:46.147528 [ANA_INIT] PLL >>>>>>>>
4916 12:14:46.148179 [ANA_INIT] PLL <<<<<<<<
4917 12:14:46.150562 [ANA_INIT] MIDPI >>>>>>>>
4918 12:14:46.154186 [ANA_INIT] MIDPI <<<<<<<<
4919 12:14:46.154788 [ANA_INIT] DLL >>>>>>>>
4920 12:14:46.157202 [ANA_INIT] flow end
4921 12:14:46.160854 ============ LP4 DIFF to SE enter ============
4922 12:14:46.167347 ============ LP4 DIFF to SE exit ============
4923 12:14:46.167901 [ANA_INIT] <<<<<<<<<<<<<
4924 12:14:46.170338 [Flow] Enable top DCM control >>>>>
4925 12:14:46.173957 [Flow] Enable top DCM control <<<<<
4926 12:14:46.176905 Enable DLL master slave shuffle
4927 12:14:46.183472 ==============================================================
4928 12:14:46.183899 Gating Mode config
4929 12:14:46.189993 ==============================================================
4930 12:14:46.193611 Config description:
4931 12:14:46.203628 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4932 12:14:46.210197 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4933 12:14:46.213094 SELPH_MODE 0: By rank 1: By Phase
4934 12:14:46.219726 ==============================================================
4935 12:14:46.223301 GAT_TRACK_EN = 1
4936 12:14:46.226585 RX_GATING_MODE = 2
4937 12:14:46.227175 RX_GATING_TRACK_MODE = 2
4938 12:14:46.229466 SELPH_MODE = 1
4939 12:14:46.233103 PICG_EARLY_EN = 1
4940 12:14:46.236019 VALID_LAT_VALUE = 1
4941 12:14:46.243090 ==============================================================
4942 12:14:46.246216 Enter into Gating configuration >>>>
4943 12:14:46.249300 Exit from Gating configuration <<<<
4944 12:14:46.252734 Enter into DVFS_PRE_config >>>>>
4945 12:14:46.262562 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4946 12:14:46.265794 Exit from DVFS_PRE_config <<<<<
4947 12:14:46.268828 Enter into PICG configuration >>>>
4948 12:14:46.271928 Exit from PICG configuration <<<<
4949 12:14:46.275419 [RX_INPUT] configuration >>>>>
4950 12:14:46.279089 [RX_INPUT] configuration <<<<<
4951 12:14:46.282073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4952 12:14:46.288973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4953 12:14:46.294970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4954 12:14:46.301861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4955 12:14:46.308498 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4956 12:14:46.315369 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4957 12:14:46.318653 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4958 12:14:46.321516 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4959 12:14:46.324770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4960 12:14:46.331658 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4961 12:14:46.334996 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4962 12:14:46.338506 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4963 12:14:46.341238 ===================================
4964 12:14:46.344654 LPDDR4 DRAM CONFIGURATION
4965 12:14:46.348463 ===================================
4966 12:14:46.348923 EX_ROW_EN[0] = 0x0
4967 12:14:46.351302 EX_ROW_EN[1] = 0x0
4968 12:14:46.354440 LP4Y_EN = 0x0
4969 12:14:46.354866 WORK_FSP = 0x0
4970 12:14:46.358035 WL = 0x3
4971 12:14:46.358467 RL = 0x3
4972 12:14:46.361159 BL = 0x2
4973 12:14:46.361611 RPST = 0x0
4974 12:14:46.364679 RD_PRE = 0x0
4975 12:14:46.365102 WR_PRE = 0x1
4976 12:14:46.367664 WR_PST = 0x0
4977 12:14:46.368122 DBI_WR = 0x0
4978 12:14:46.371242 DBI_RD = 0x0
4979 12:14:46.371618 OTF = 0x1
4980 12:14:46.374181 ===================================
4981 12:14:46.377867 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4982 12:14:46.384242 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4983 12:14:46.387856 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 12:14:46.390862 ===================================
4985 12:14:46.394395 LPDDR4 DRAM CONFIGURATION
4986 12:14:46.397401 ===================================
4987 12:14:46.397828 EX_ROW_EN[0] = 0x10
4988 12:14:46.401191 EX_ROW_EN[1] = 0x0
4989 12:14:46.404018 LP4Y_EN = 0x0
4990 12:14:46.404507 WORK_FSP = 0x0
4991 12:14:46.407278 WL = 0x3
4992 12:14:46.407704 RL = 0x3
4993 12:14:46.410527 BL = 0x2
4994 12:14:46.410952 RPST = 0x0
4995 12:14:46.414375 RD_PRE = 0x0
4996 12:14:46.414801 WR_PRE = 0x1
4997 12:14:46.417378 WR_PST = 0x0
4998 12:14:46.417878 DBI_WR = 0x0
4999 12:14:46.420817 DBI_RD = 0x0
5000 12:14:46.421242 OTF = 0x1
5001 12:14:46.423694 ===================================
5002 12:14:46.430805 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5003 12:14:46.435186 nWR fixed to 30
5004 12:14:46.438324 [ModeRegInit_LP4] CH0 RK0
5005 12:14:46.438778 [ModeRegInit_LP4] CH0 RK1
5006 12:14:46.441253 [ModeRegInit_LP4] CH1 RK0
5007 12:14:46.444896 [ModeRegInit_LP4] CH1 RK1
5008 12:14:46.445418 match AC timing 9
5009 12:14:46.451680 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5010 12:14:46.454905 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5011 12:14:46.457828 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5012 12:14:46.464130 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5013 12:14:46.467704 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5014 12:14:46.468330 ==
5015 12:14:46.471280 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 12:14:46.474363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5017 12:14:46.474818 ==
5018 12:14:46.481043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5019 12:14:46.487544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5020 12:14:46.491138 [CA 0] Center 38 (8~69) winsize 62
5021 12:14:46.494047 [CA 1] Center 37 (7~68) winsize 62
5022 12:14:46.497707 [CA 2] Center 34 (4~65) winsize 62
5023 12:14:46.500669 [CA 3] Center 34 (4~65) winsize 62
5024 12:14:46.504365 [CA 4] Center 33 (3~64) winsize 62
5025 12:14:46.507154 [CA 5] Center 33 (3~63) winsize 61
5026 12:14:46.507602
5027 12:14:46.510591 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5028 12:14:46.511177
5029 12:14:46.514008 [CATrainingPosCal] consider 1 rank data
5030 12:14:46.517075 u2DelayCellTimex100 = 270/100 ps
5031 12:14:46.520588 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5032 12:14:46.523632 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5033 12:14:46.527104 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5034 12:14:46.533751 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5035 12:14:46.536703 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5036 12:14:46.540288 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5037 12:14:46.540921
5038 12:14:46.543650 CA PerBit enable=1, Macro0, CA PI delay=33
5039 12:14:46.544219
5040 12:14:46.547273 [CBTSetCACLKResult] CA Dly = 33
5041 12:14:46.547825 CS Dly: 5 (0~36)
5042 12:14:46.548278 ==
5043 12:14:46.550526 Dram Type= 6, Freq= 0, CH_0, rank 1
5044 12:14:46.557120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5045 12:14:46.557560 ==
5046 12:14:46.560092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5047 12:14:46.566640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5048 12:14:46.570309 [CA 0] Center 38 (8~69) winsize 62
5049 12:14:46.573332 [CA 1] Center 38 (7~69) winsize 63
5050 12:14:46.576424 [CA 2] Center 35 (5~65) winsize 61
5051 12:14:46.580163 [CA 3] Center 34 (4~65) winsize 62
5052 12:14:46.582972 [CA 4] Center 33 (3~64) winsize 62
5053 12:14:46.586086 [CA 5] Center 33 (2~64) winsize 63
5054 12:14:46.586736
5055 12:14:46.589593 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5056 12:14:46.590128
5057 12:14:46.592768 [CATrainingPosCal] consider 2 rank data
5058 12:14:46.596218 u2DelayCellTimex100 = 270/100 ps
5059 12:14:46.599036 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5060 12:14:46.605841 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5061 12:14:46.609302 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5062 12:14:46.612522 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5063 12:14:46.615938 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5064 12:14:46.618938 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5065 12:14:46.619021
5066 12:14:46.622485 CA PerBit enable=1, Macro0, CA PI delay=33
5067 12:14:46.622575
5068 12:14:46.625656 [CBTSetCACLKResult] CA Dly = 33
5069 12:14:46.629331 CS Dly: 6 (0~39)
5070 12:14:46.629426
5071 12:14:46.632289 ----->DramcWriteLeveling(PI) begin...
5072 12:14:46.632393 ==
5073 12:14:46.635816 Dram Type= 6, Freq= 0, CH_0, rank 0
5074 12:14:46.638989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 12:14:46.639102 ==
5076 12:14:46.641980 Write leveling (Byte 0): 34 => 34
5077 12:14:46.645120 Write leveling (Byte 1): 24 => 24
5078 12:14:46.648429 DramcWriteLeveling(PI) end<-----
5079 12:14:46.648566
5080 12:14:46.648674 ==
5081 12:14:46.652044 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 12:14:46.655628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 12:14:46.655783 ==
5084 12:14:46.659174 [Gating] SW mode calibration
5085 12:14:46.665374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5086 12:14:46.671909 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5087 12:14:46.675430 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5088 12:14:46.682242 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5089 12:14:46.685069 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5090 12:14:46.688684 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5091 12:14:46.695125 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 12:14:46.698288 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 12:14:46.701337 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5094 12:14:46.707934 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5095 12:14:46.711327 0 15 0 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
5096 12:14:46.714461 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5097 12:14:46.721475 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5098 12:14:46.724418 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5099 12:14:46.727939 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 12:14:46.734482 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 12:14:46.737832 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 12:14:46.740995 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5103 12:14:46.747664 1 0 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
5104 12:14:46.750696 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5105 12:14:46.754453 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5106 12:14:46.760665 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 12:14:46.764111 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 12:14:46.767135 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 12:14:46.773579 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 12:14:46.777127 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5111 12:14:46.780153 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5112 12:14:46.787011 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 12:14:46.790502 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 12:14:46.793461 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 12:14:46.800312 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 12:14:46.804068 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 12:14:46.806752 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 12:14:46.813406 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 12:14:46.817107 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 12:14:46.820140 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 12:14:46.826510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 12:14:46.830350 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 12:14:46.833342 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 12:14:46.839734 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:14:46.843140 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5126 12:14:46.846639 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5127 12:14:46.849524 Total UI for P1: 0, mck2ui 16
5128 12:14:46.852591 best dqsien dly found for B0: ( 1, 2, 24)
5129 12:14:46.859350 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5130 12:14:46.862671 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 12:14:46.866297 Total UI for P1: 0, mck2ui 16
5132 12:14:46.869220 best dqsien dly found for B1: ( 1, 2, 30)
5133 12:14:46.872632 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5134 12:14:46.875695 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5135 12:14:46.876181
5136 12:14:46.879452 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5137 12:14:46.882433 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5138 12:14:46.886017 [Gating] SW calibration Done
5139 12:14:46.886443 ==
5140 12:14:46.889037 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 12:14:46.895610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 12:14:46.896057 ==
5143 12:14:46.896406 RX Vref Scan: 0
5144 12:14:46.896726
5145 12:14:46.899486 RX Vref 0 -> 0, step: 1
5146 12:14:46.899911
5147 12:14:46.902397 RX Delay -80 -> 252, step: 8
5148 12:14:46.905329 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5149 12:14:46.909071 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5150 12:14:46.912147 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5151 12:14:46.914948 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5152 12:14:46.921582 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5153 12:14:46.925179 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5154 12:14:46.928211 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5155 12:14:46.931542 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5156 12:14:46.935053 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5157 12:14:46.941894 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5158 12:14:46.944802 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5159 12:14:46.948272 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5160 12:14:46.951644 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5161 12:14:46.954684 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5162 12:14:46.961219 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5163 12:14:46.964852 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5164 12:14:46.965320 ==
5165 12:14:46.968148 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 12:14:46.970927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 12:14:46.971359 ==
5168 12:14:46.971702 DQS Delay:
5169 12:14:46.974271 DQS0 = 0, DQS1 = 0
5170 12:14:46.974702 DQM Delay:
5171 12:14:46.977711 DQM0 = 102, DQM1 = 88
5172 12:14:46.978141 DQ Delay:
5173 12:14:46.981351 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5174 12:14:46.984166 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =107
5175 12:14:46.987377 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5176 12:14:46.990832 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5177 12:14:46.991265
5178 12:14:46.991607
5179 12:14:46.991924 ==
5180 12:14:46.993833 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 12:14:47.001007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 12:14:47.001440 ==
5183 12:14:47.001783
5184 12:14:47.002124
5185 12:14:47.003897 TX Vref Scan disable
5186 12:14:47.004376 == TX Byte 0 ==
5187 12:14:47.007006 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5188 12:14:47.014063 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5189 12:14:47.014499 == TX Byte 1 ==
5190 12:14:47.020648 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5191 12:14:47.023695 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5192 12:14:47.024170 ==
5193 12:14:47.026830 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 12:14:47.030468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 12:14:47.030901 ==
5196 12:14:47.031244
5197 12:14:47.031561
5198 12:14:47.033477 TX Vref Scan disable
5199 12:14:47.036919 == TX Byte 0 ==
5200 12:14:47.040539 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5201 12:14:47.043484 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5202 12:14:47.046347 == TX Byte 1 ==
5203 12:14:47.049895 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5204 12:14:47.053013 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5205 12:14:47.053713
5206 12:14:47.056275 [DATLAT]
5207 12:14:47.056925 Freq=933, CH0 RK0
5208 12:14:47.057450
5209 12:14:47.059923 DATLAT Default: 0xd
5210 12:14:47.060356 0, 0xFFFF, sum = 0
5211 12:14:47.062997 1, 0xFFFF, sum = 0
5212 12:14:47.063612 2, 0xFFFF, sum = 0
5213 12:14:47.066387 3, 0xFFFF, sum = 0
5214 12:14:47.066969 4, 0xFFFF, sum = 0
5215 12:14:47.069996 5, 0xFFFF, sum = 0
5216 12:14:47.070572 6, 0xFFFF, sum = 0
5217 12:14:47.072935 7, 0xFFFF, sum = 0
5218 12:14:47.076362 8, 0xFFFF, sum = 0
5219 12:14:47.076795 9, 0xFFFF, sum = 0
5220 12:14:47.077218 10, 0x0, sum = 1
5221 12:14:47.079765 11, 0x0, sum = 2
5222 12:14:47.080276 12, 0x0, sum = 3
5223 12:14:47.083248 13, 0x0, sum = 4
5224 12:14:47.083709 best_step = 11
5225 12:14:47.084094
5226 12:14:47.084416 ==
5227 12:14:47.086106 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 12:14:47.092661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 12:14:47.093112 ==
5230 12:14:47.093446 RX Vref Scan: 1
5231 12:14:47.093756
5232 12:14:47.096213 RX Vref 0 -> 0, step: 1
5233 12:14:47.096632
5234 12:14:47.099416 RX Delay -69 -> 252, step: 4
5235 12:14:47.099838
5236 12:14:47.103082 Set Vref, RX VrefLevel [Byte0]: 56
5237 12:14:47.106088 [Byte1]: 49
5238 12:14:47.106513
5239 12:14:47.109090 Final RX Vref Byte 0 = 56 to rank0
5240 12:14:47.112551 Final RX Vref Byte 1 = 49 to rank0
5241 12:14:47.115460 Final RX Vref Byte 0 = 56 to rank1
5242 12:14:47.119144 Final RX Vref Byte 1 = 49 to rank1==
5243 12:14:47.122588 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 12:14:47.126170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 12:14:47.129159 ==
5246 12:14:47.129599 DQS Delay:
5247 12:14:47.129968 DQS0 = 0, DQS1 = 0
5248 12:14:47.132224 DQM Delay:
5249 12:14:47.132689 DQM0 = 102, DQM1 = 91
5250 12:14:47.135847 DQ Delay:
5251 12:14:47.138855 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =98
5252 12:14:47.142386 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5253 12:14:47.145424 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =88
5254 12:14:47.148445 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5255 12:14:47.149173
5256 12:14:47.149809
5257 12:14:47.155185 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5258 12:14:47.158649 CH0 RK0: MR19=505, MR18=1610
5259 12:14:47.165064 CH0_RK0: MR19=0x505, MR18=0x1610, DQSOSC=414, MR23=63, INC=63, DEC=42
5260 12:14:47.165518
5261 12:14:47.168428 ----->DramcWriteLeveling(PI) begin...
5262 12:14:47.168940 ==
5263 12:14:47.171652 Dram Type= 6, Freq= 0, CH_0, rank 1
5264 12:14:47.175189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 12:14:47.175793 ==
5266 12:14:47.178248 Write leveling (Byte 0): 30 => 30
5267 12:14:47.181486 Write leveling (Byte 1): 27 => 27
5268 12:14:47.185142 DramcWriteLeveling(PI) end<-----
5269 12:14:47.185603
5270 12:14:47.185939 ==
5271 12:14:47.187991 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 12:14:47.194439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 12:14:47.195026 ==
5274 12:14:47.195524 [Gating] SW mode calibration
5275 12:14:47.204729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5276 12:14:47.208339 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5277 12:14:47.211488 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5278 12:14:47.218185 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5279 12:14:47.221088 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5280 12:14:47.224144 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 12:14:47.231085 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 12:14:47.234287 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 12:14:47.240545 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 1)
5284 12:14:47.244086 0 14 28 | B1->B0 | 3434 2929 | 0 1 | (0 1) (1 0)
5285 12:14:47.247479 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
5286 12:14:47.254041 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5287 12:14:47.257207 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5288 12:14:47.260721 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 12:14:47.267238 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 12:14:47.270257 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 12:14:47.273886 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5292 12:14:47.280423 0 15 28 | B1->B0 | 2626 3939 | 1 0 | (0 0) (0 0)
5293 12:14:47.283923 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5294 12:14:47.286796 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5295 12:14:47.293690 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5296 12:14:47.296721 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 12:14:47.299808 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 12:14:47.306561 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 12:14:47.309638 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5300 12:14:47.313367 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5301 12:14:47.319912 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 12:14:47.323006 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 12:14:47.326497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 12:14:47.329403 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 12:14:47.336483 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 12:14:47.339506 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 12:14:47.343021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 12:14:47.349470 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 12:14:47.352522 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 12:14:47.359233 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 12:14:47.362675 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 12:14:47.365878 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 12:14:47.369190 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 12:14:47.375556 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:14:47.378716 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5316 12:14:47.382226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5317 12:14:47.385866 Total UI for P1: 0, mck2ui 16
5318 12:14:47.388717 best dqsien dly found for B0: ( 1, 2, 24)
5319 12:14:47.395602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5320 12:14:47.398421 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 12:14:47.401998 Total UI for P1: 0, mck2ui 16
5322 12:14:47.404989 best dqsien dly found for B1: ( 1, 2, 30)
5323 12:14:47.408579 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5324 12:14:47.411633 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5325 12:14:47.411743
5326 12:14:47.415268 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5327 12:14:47.421847 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5328 12:14:47.421928 [Gating] SW calibration Done
5329 12:14:47.424864 ==
5330 12:14:47.424945 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 12:14:47.431306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 12:14:47.431390 ==
5333 12:14:47.431455 RX Vref Scan: 0
5334 12:14:47.431516
5335 12:14:47.434990 RX Vref 0 -> 0, step: 1
5336 12:14:47.435070
5337 12:14:47.438057 RX Delay -80 -> 252, step: 8
5338 12:14:47.441603 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5339 12:14:47.444482 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5340 12:14:47.448236 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5341 12:14:47.454505 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5342 12:14:47.457651 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5343 12:14:47.461125 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5344 12:14:47.464027 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5345 12:14:47.467658 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5346 12:14:47.474136 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5347 12:14:47.477485 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5348 12:14:47.480954 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5349 12:14:47.483823 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5350 12:14:47.487329 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5351 12:14:47.490413 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5352 12:14:47.497379 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5353 12:14:47.500402 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5354 12:14:47.500506 ==
5355 12:14:47.503927 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 12:14:47.507397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 12:14:47.507499 ==
5358 12:14:47.510579 DQS Delay:
5359 12:14:47.510679 DQS0 = 0, DQS1 = 0
5360 12:14:47.510772 DQM Delay:
5361 12:14:47.514291 DQM0 = 101, DQM1 = 88
5362 12:14:47.514390 DQ Delay:
5363 12:14:47.517194 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =99
5364 12:14:47.520280 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =107
5365 12:14:47.523914 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5366 12:14:47.527000 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5367 12:14:47.527093
5368 12:14:47.527179
5369 12:14:47.527263 ==
5370 12:14:47.530580 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 12:14:47.537307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 12:14:47.537414 ==
5373 12:14:47.537506
5374 12:14:47.537597
5375 12:14:47.537682 TX Vref Scan disable
5376 12:14:47.540844 == TX Byte 0 ==
5377 12:14:47.544191 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5378 12:14:47.550908 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5379 12:14:47.551015 == TX Byte 1 ==
5380 12:14:47.553718 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5381 12:14:47.560659 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5382 12:14:47.560740 ==
5383 12:14:47.563683 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 12:14:47.567289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 12:14:47.567373 ==
5386 12:14:47.567439
5387 12:14:47.567500
5388 12:14:47.570265 TX Vref Scan disable
5389 12:14:47.573694 == TX Byte 0 ==
5390 12:14:47.576714 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5391 12:14:47.580561 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5392 12:14:47.583911 == TX Byte 1 ==
5393 12:14:47.587027 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5394 12:14:47.590472 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5395 12:14:47.590556
5396 12:14:47.590621 [DATLAT]
5397 12:14:47.593321 Freq=933, CH0 RK1
5398 12:14:47.593404
5399 12:14:47.596481 DATLAT Default: 0xb
5400 12:14:47.596563 0, 0xFFFF, sum = 0
5401 12:14:47.599952 1, 0xFFFF, sum = 0
5402 12:14:47.600058 2, 0xFFFF, sum = 0
5403 12:14:47.603377 3, 0xFFFF, sum = 0
5404 12:14:47.603461 4, 0xFFFF, sum = 0
5405 12:14:47.606944 5, 0xFFFF, sum = 0
5406 12:14:47.607031 6, 0xFFFF, sum = 0
5407 12:14:47.609760 7, 0xFFFF, sum = 0
5408 12:14:47.609846 8, 0xFFFF, sum = 0
5409 12:14:47.613652 9, 0xFFFF, sum = 0
5410 12:14:47.613739 10, 0x0, sum = 1
5411 12:14:47.616639 11, 0x0, sum = 2
5412 12:14:47.616712 12, 0x0, sum = 3
5413 12:14:47.619732 13, 0x0, sum = 4
5414 12:14:47.619833 best_step = 11
5415 12:14:47.619923
5416 12:14:47.620041 ==
5417 12:14:47.623188 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 12:14:47.626383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 12:14:47.630082 ==
5420 12:14:47.630184 RX Vref Scan: 0
5421 12:14:47.630278
5422 12:14:47.632883 RX Vref 0 -> 0, step: 1
5423 12:14:47.632980
5424 12:14:47.635909 RX Delay -61 -> 252, step: 4
5425 12:14:47.639709 iDelay=195, Bit 0, Center 102 (19 ~ 186) 168
5426 12:14:47.642429 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5427 12:14:47.649385 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5428 12:14:47.652329 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5429 12:14:47.656181 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5430 12:14:47.659042 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5431 12:14:47.662388 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5432 12:14:47.668856 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5433 12:14:47.672393 iDelay=195, Bit 8, Center 82 (-1 ~ 166) 168
5434 12:14:47.675570 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5435 12:14:47.679157 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5436 12:14:47.682004 iDelay=195, Bit 11, Center 82 (-1 ~ 166) 168
5437 12:14:47.688878 iDelay=195, Bit 12, Center 94 (11 ~ 178) 168
5438 12:14:47.691770 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5439 12:14:47.695362 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5440 12:14:47.698422 iDelay=195, Bit 15, Center 96 (15 ~ 178) 164
5441 12:14:47.698526 ==
5442 12:14:47.701585 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 12:14:47.708548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 12:14:47.708628 ==
5445 12:14:47.708697 DQS Delay:
5446 12:14:47.708757 DQS0 = 0, DQS1 = 0
5447 12:14:47.711916 DQM Delay:
5448 12:14:47.712014 DQM0 = 101, DQM1 = 90
5449 12:14:47.714735 DQ Delay:
5450 12:14:47.718227 DQ0 =102, DQ1 =102, DQ2 =96, DQ3 =98
5451 12:14:47.722038 DQ4 =104, DQ5 =92, DQ6 =110, DQ7 =108
5452 12:14:47.725156 DQ8 =82, DQ9 =76, DQ10 =94, DQ11 =82
5453 12:14:47.728043 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =96
5454 12:14:47.728114
5455 12:14:47.728175
5456 12:14:47.734797 [DQSOSCAuto] RK1, (LSB)MR18= 0x1511, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5457 12:14:47.738298 CH0 RK1: MR19=505, MR18=1511
5458 12:14:47.744443 CH0_RK1: MR19=0x505, MR18=0x1511, DQSOSC=415, MR23=63, INC=62, DEC=41
5459 12:14:47.748287 [RxdqsGatingPostProcess] freq 933
5460 12:14:47.754332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5461 12:14:47.757915 best DQS0 dly(2T, 0.5T) = (0, 10)
5462 12:14:47.758029 best DQS1 dly(2T, 0.5T) = (0, 10)
5463 12:14:47.760952 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5464 12:14:47.764430 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5465 12:14:47.767838 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 12:14:47.771083 best DQS1 dly(2T, 0.5T) = (0, 10)
5467 12:14:47.774189 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 12:14:47.777626 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5469 12:14:47.780737 Pre-setting of DQS Precalculation
5470 12:14:47.787482 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5471 12:14:47.787570 ==
5472 12:14:47.790768 Dram Type= 6, Freq= 0, CH_1, rank 0
5473 12:14:47.793817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 12:14:47.793919 ==
5475 12:14:47.800419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5476 12:14:47.806914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5477 12:14:47.810523 [CA 0] Center 36 (6~67) winsize 62
5478 12:14:47.813715 [CA 1] Center 36 (6~67) winsize 62
5479 12:14:47.817271 [CA 2] Center 34 (4~65) winsize 62
5480 12:14:47.820144 [CA 3] Center 33 (3~64) winsize 62
5481 12:14:47.823617 [CA 4] Center 34 (4~65) winsize 62
5482 12:14:47.826802 [CA 5] Center 33 (3~64) winsize 62
5483 12:14:47.826901
5484 12:14:47.829871 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5485 12:14:47.829961
5486 12:14:47.833478 [CATrainingPosCal] consider 1 rank data
5487 12:14:47.836542 u2DelayCellTimex100 = 270/100 ps
5488 12:14:47.840151 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5489 12:14:47.843225 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5490 12:14:47.846765 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5491 12:14:47.849906 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5492 12:14:47.852956 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5493 12:14:47.856453 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5494 12:14:47.856589
5495 12:14:47.862904 CA PerBit enable=1, Macro0, CA PI delay=33
5496 12:14:47.863058
5497 12:14:47.863200 [CBTSetCACLKResult] CA Dly = 33
5498 12:14:47.866623 CS Dly: 5 (0~36)
5499 12:14:47.866803 ==
5500 12:14:47.869450 Dram Type= 6, Freq= 0, CH_1, rank 1
5501 12:14:47.872631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 12:14:47.872714 ==
5503 12:14:47.879477 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 12:14:47.886098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5505 12:14:47.889618 [CA 0] Center 36 (6~67) winsize 62
5506 12:14:47.892588 [CA 1] Center 36 (6~67) winsize 62
5507 12:14:47.895978 [CA 2] Center 34 (4~64) winsize 61
5508 12:14:47.898914 [CA 3] Center 33 (3~64) winsize 62
5509 12:14:47.902280 [CA 4] Center 33 (3~64) winsize 62
5510 12:14:47.906026 [CA 5] Center 33 (3~64) winsize 62
5511 12:14:47.906149
5512 12:14:47.908890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5513 12:14:47.909013
5514 12:14:47.912415 [CATrainingPosCal] consider 2 rank data
5515 12:14:47.915270 u2DelayCellTimex100 = 270/100 ps
5516 12:14:47.918585 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 12:14:47.922199 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5518 12:14:47.925613 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 12:14:47.931642 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5520 12:14:47.934956 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5521 12:14:47.938689 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5522 12:14:47.938791
5523 12:14:47.941634 CA PerBit enable=1, Macro0, CA PI delay=33
5524 12:14:47.941705
5525 12:14:47.944623 [CBTSetCACLKResult] CA Dly = 33
5526 12:14:47.944692 CS Dly: 6 (0~38)
5527 12:14:47.944752
5528 12:14:47.948247 ----->DramcWriteLeveling(PI) begin...
5529 12:14:47.951346 ==
5530 12:14:47.954767 Dram Type= 6, Freq= 0, CH_1, rank 0
5531 12:14:47.957950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 12:14:47.958080 ==
5533 12:14:47.961346 Write leveling (Byte 0): 26 => 26
5534 12:14:47.964319 Write leveling (Byte 1): 29 => 29
5535 12:14:47.967913 DramcWriteLeveling(PI) end<-----
5536 12:14:47.968015
5537 12:14:47.968151 ==
5538 12:14:47.970951 Dram Type= 6, Freq= 0, CH_1, rank 0
5539 12:14:47.974433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5540 12:14:47.974536 ==
5541 12:14:47.977901 [Gating] SW mode calibration
5542 12:14:47.984270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5543 12:14:47.990998 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5544 12:14:47.993976 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5545 12:14:47.997594 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5546 12:14:48.003905 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 12:14:48.007393 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 12:14:48.010377 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 12:14:48.017021 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 12:14:48.020389 0 14 24 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5551 12:14:48.023864 0 14 28 | B1->B0 | 2929 2323 | 0 1 | (0 0) (1 1)
5552 12:14:48.030246 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5553 12:14:48.033856 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 12:14:48.036913 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 12:14:48.043646 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 12:14:48.046603 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 12:14:48.049689 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 12:14:48.056312 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 12:14:48.059866 0 15 28 | B1->B0 | 3333 3d3d | 1 0 | (0 0) (0 0)
5560 12:14:48.062705 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 12:14:48.069767 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 12:14:48.072674 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 12:14:48.076271 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 12:14:48.082487 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 12:14:48.085798 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 12:14:48.089374 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5567 12:14:48.095927 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5568 12:14:48.099277 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5569 12:14:48.102236 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 12:14:48.109187 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 12:14:48.112500 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 12:14:48.115609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 12:14:48.122522 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 12:14:48.125331 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:14:48.128967 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:14:48.135336 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:14:48.139036 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:14:48.142072 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:14:48.148792 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:14:48.151841 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:14:48.155475 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:14:48.161626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5583 12:14:48.165174 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5584 12:14:48.168082 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5585 12:14:48.171778 Total UI for P1: 0, mck2ui 16
5586 12:14:48.175252 best dqsien dly found for B0: ( 1, 2, 26)
5587 12:14:48.181257 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:14:48.184830 Total UI for P1: 0, mck2ui 16
5589 12:14:48.188147 best dqsien dly found for B1: ( 1, 2, 28)
5590 12:14:48.191472 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5591 12:14:48.194643 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5592 12:14:48.194726
5593 12:14:48.197988 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5594 12:14:48.201008 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5595 12:14:48.204403 [Gating] SW calibration Done
5596 12:14:48.204521 ==
5597 12:14:48.207804 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 12:14:48.210801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 12:14:48.210930 ==
5600 12:14:48.214097 RX Vref Scan: 0
5601 12:14:48.214199
5602 12:14:48.217775 RX Vref 0 -> 0, step: 1
5603 12:14:48.217883
5604 12:14:48.217977 RX Delay -80 -> 252, step: 8
5605 12:14:48.224040 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5606 12:14:48.227418 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5607 12:14:48.230812 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5608 12:14:48.234270 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5609 12:14:48.237676 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5610 12:14:48.244261 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5611 12:14:48.247372 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5612 12:14:48.250778 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5613 12:14:48.253865 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5614 12:14:48.257193 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5615 12:14:48.260416 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5616 12:14:48.267045 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5617 12:14:48.270849 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5618 12:14:48.273818 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5619 12:14:48.277213 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5620 12:14:48.280071 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5621 12:14:48.283798 ==
5622 12:14:48.286686 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 12:14:48.290386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 12:14:48.290548 ==
5625 12:14:48.290676 DQS Delay:
5626 12:14:48.293310 DQS0 = 0, DQS1 = 0
5627 12:14:48.293494 DQM Delay:
5628 12:14:48.296862 DQM0 = 99, DQM1 = 95
5629 12:14:48.297079 DQ Delay:
5630 12:14:48.300404 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5631 12:14:48.303437 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5632 12:14:48.307097 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5633 12:14:48.309992 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5634 12:14:48.310333
5635 12:14:48.310606
5636 12:14:48.310846 ==
5637 12:14:48.313354 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 12:14:48.317205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 12:14:48.320438 ==
5640 12:14:48.320865
5641 12:14:48.321200
5642 12:14:48.321510 TX Vref Scan disable
5643 12:14:48.323317 == TX Byte 0 ==
5644 12:14:48.327064 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5645 12:14:48.329913 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5646 12:14:48.333268 == TX Byte 1 ==
5647 12:14:48.336654 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5648 12:14:48.340326 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5649 12:14:48.343145 ==
5650 12:14:48.346800 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 12:14:48.349692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 12:14:48.350138 ==
5653 12:14:48.350586
5654 12:14:48.351113
5655 12:14:48.353403 TX Vref Scan disable
5656 12:14:48.353846 == TX Byte 0 ==
5657 12:14:48.359799 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5658 12:14:48.362967 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5659 12:14:48.363410 == TX Byte 1 ==
5660 12:14:48.369531 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5661 12:14:48.372662 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5662 12:14:48.373184
5663 12:14:48.373529 [DATLAT]
5664 12:14:48.376268 Freq=933, CH1 RK0
5665 12:14:48.376828
5666 12:14:48.377217 DATLAT Default: 0xd
5667 12:14:48.379680 0, 0xFFFF, sum = 0
5668 12:14:48.380273 1, 0xFFFF, sum = 0
5669 12:14:48.382555 2, 0xFFFF, sum = 0
5670 12:14:48.383107 3, 0xFFFF, sum = 0
5671 12:14:48.386257 4, 0xFFFF, sum = 0
5672 12:14:48.389712 5, 0xFFFF, sum = 0
5673 12:14:48.390327 6, 0xFFFF, sum = 0
5674 12:14:48.392544 7, 0xFFFF, sum = 0
5675 12:14:48.393190 8, 0xFFFF, sum = 0
5676 12:14:48.396240 9, 0xFFFF, sum = 0
5677 12:14:48.396820 10, 0x0, sum = 1
5678 12:14:48.399215 11, 0x0, sum = 2
5679 12:14:48.399676 12, 0x0, sum = 3
5680 12:14:48.402660 13, 0x0, sum = 4
5681 12:14:48.403228 best_step = 11
5682 12:14:48.403734
5683 12:14:48.404333 ==
5684 12:14:48.405619 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 12:14:48.408849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 12:14:48.409404 ==
5687 12:14:48.412510 RX Vref Scan: 1
5688 12:14:48.412932
5689 12:14:48.415778 RX Vref 0 -> 0, step: 1
5690 12:14:48.416246
5691 12:14:48.416584 RX Delay -53 -> 252, step: 4
5692 12:14:48.416896
5693 12:14:48.419212 Set Vref, RX VrefLevel [Byte0]: 53
5694 12:14:48.422256 [Byte1]: 48
5695 12:14:48.426808
5696 12:14:48.427231 Final RX Vref Byte 0 = 53 to rank0
5697 12:14:48.430380 Final RX Vref Byte 1 = 48 to rank0
5698 12:14:48.433378 Final RX Vref Byte 0 = 53 to rank1
5699 12:14:48.436849 Final RX Vref Byte 1 = 48 to rank1==
5700 12:14:48.440333 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:14:48.446565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:14:48.446994 ==
5703 12:14:48.447342 DQS Delay:
5704 12:14:48.450223 DQS0 = 0, DQS1 = 0
5705 12:14:48.450764 DQM Delay:
5706 12:14:48.451234 DQM0 = 97, DQM1 = 94
5707 12:14:48.453278 DQ Delay:
5708 12:14:48.456346 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5709 12:14:48.459888 DQ4 =94, DQ5 =108, DQ6 =108, DQ7 =94
5710 12:14:48.462961 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5711 12:14:48.466565 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =102
5712 12:14:48.467105
5713 12:14:48.467560
5714 12:14:48.473098 [DQSOSCAuto] RK0, (LSB)MR18= 0x918, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5715 12:14:48.476067 CH1 RK0: MR19=505, MR18=918
5716 12:14:48.482706 CH1_RK0: MR19=0x505, MR18=0x918, DQSOSC=414, MR23=63, INC=63, DEC=42
5717 12:14:48.483133
5718 12:14:48.486222 ----->DramcWriteLeveling(PI) begin...
5719 12:14:48.486653 ==
5720 12:14:48.489147 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 12:14:48.492563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 12:14:48.492995 ==
5723 12:14:48.496251 Write leveling (Byte 0): 26 => 26
5724 12:14:48.499306 Write leveling (Byte 1): 28 => 28
5725 12:14:48.502195 DramcWriteLeveling(PI) end<-----
5726 12:14:48.502619
5727 12:14:48.502953 ==
5728 12:14:48.505572 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 12:14:48.512098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 12:14:48.512526 ==
5731 12:14:48.515885 [Gating] SW mode calibration
5732 12:14:48.522258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5733 12:14:48.525871 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5734 12:14:48.532274 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5735 12:14:48.535364 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 12:14:48.538920 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 12:14:48.545558 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 12:14:48.548601 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 12:14:48.552066 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 12:14:48.558503 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)
5741 12:14:48.561524 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
5742 12:14:48.565252 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 12:14:48.571901 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 12:14:48.574831 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 12:14:48.578466 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 12:14:48.584585 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 12:14:48.588063 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 12:14:48.591291 0 15 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
5749 12:14:48.597740 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5750 12:14:48.601303 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 12:14:48.604384 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 12:14:48.611304 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 12:14:48.614237 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 12:14:48.617900 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 12:14:48.623962 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 12:14:48.627637 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 12:14:48.631209 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5758 12:14:48.637234 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5759 12:14:48.640343 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 12:14:48.643969 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 12:14:48.650127 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 12:14:48.653669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 12:14:48.656715 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 12:14:48.663522 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 12:14:48.667046 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 12:14:48.670054 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 12:14:48.676879 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:14:48.680377 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:14:48.683500 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:14:48.690064 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:14:48.693125 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:14:48.696491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5773 12:14:48.703142 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5774 12:14:48.706262 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5775 12:14:48.709295 Total UI for P1: 0, mck2ui 16
5776 12:14:48.712965 best dqsien dly found for B0: ( 1, 2, 26)
5777 12:14:48.716305 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:14:48.719590 Total UI for P1: 0, mck2ui 16
5779 12:14:48.722722 best dqsien dly found for B1: ( 1, 2, 30)
5780 12:14:48.726338 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5781 12:14:48.729458 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5782 12:14:48.729540
5783 12:14:48.735961 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5784 12:14:48.739504 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5785 12:14:48.742360 [Gating] SW calibration Done
5786 12:14:48.742477 ==
5787 12:14:48.745358 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 12:14:48.749144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 12:14:48.749256 ==
5790 12:14:48.749352 RX Vref Scan: 0
5791 12:14:48.749441
5792 12:14:48.752006 RX Vref 0 -> 0, step: 1
5793 12:14:48.752155
5794 12:14:48.755580 RX Delay -80 -> 252, step: 8
5795 12:14:48.758603 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5796 12:14:48.761825 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5797 12:14:48.768468 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5798 12:14:48.771743 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5799 12:14:48.775285 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5800 12:14:48.778280 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5801 12:14:48.782408 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5802 12:14:48.785348 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5803 12:14:48.791861 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5804 12:14:48.795384 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5805 12:14:48.798366 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5806 12:14:48.801910 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5807 12:14:48.805210 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5808 12:14:48.811829 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5809 12:14:48.814958 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5810 12:14:48.818551 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5811 12:14:48.818978 ==
5812 12:14:48.821393 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 12:14:48.824967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 12:14:48.825399 ==
5815 12:14:48.828688 DQS Delay:
5816 12:14:48.829142 DQS0 = 0, DQS1 = 0
5817 12:14:48.831476 DQM Delay:
5818 12:14:48.831902 DQM0 = 97, DQM1 = 94
5819 12:14:48.832341 DQ Delay:
5820 12:14:48.834424 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5821 12:14:48.838246 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5822 12:14:48.841424 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5823 12:14:48.844729 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5824 12:14:48.848192
5825 12:14:48.848613
5826 12:14:48.848952 ==
5827 12:14:48.851222 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 12:14:48.854841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 12:14:48.855275 ==
5830 12:14:48.855612
5831 12:14:48.855926
5832 12:14:48.858194 TX Vref Scan disable
5833 12:14:48.858618 == TX Byte 0 ==
5834 12:14:48.864336 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5835 12:14:48.867340 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5836 12:14:48.867911 == TX Byte 1 ==
5837 12:14:48.874132 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5838 12:14:48.877161 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5839 12:14:48.877602 ==
5840 12:14:48.880889 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 12:14:48.883723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 12:14:48.884183 ==
5843 12:14:48.887353
5844 12:14:48.887788
5845 12:14:48.888165 TX Vref Scan disable
5846 12:14:48.890484 == TX Byte 0 ==
5847 12:14:48.893818 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5848 12:14:48.900506 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5849 12:14:48.900908 == TX Byte 1 ==
5850 12:14:48.903528 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5851 12:14:48.910049 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5852 12:14:48.910557
5853 12:14:48.910931 [DATLAT]
5854 12:14:48.911295 Freq=933, CH1 RK1
5855 12:14:48.911602
5856 12:14:48.913542 DATLAT Default: 0xb
5857 12:14:48.917085 0, 0xFFFF, sum = 0
5858 12:14:48.917525 1, 0xFFFF, sum = 0
5859 12:14:48.920109 2, 0xFFFF, sum = 0
5860 12:14:48.920545 3, 0xFFFF, sum = 0
5861 12:14:48.923683 4, 0xFFFF, sum = 0
5862 12:14:48.924210 5, 0xFFFF, sum = 0
5863 12:14:48.926482 6, 0xFFFF, sum = 0
5864 12:14:48.927062 7, 0xFFFF, sum = 0
5865 12:14:48.929832 8, 0xFFFF, sum = 0
5866 12:14:48.930420 9, 0xFFFF, sum = 0
5867 12:14:48.933399 10, 0x0, sum = 1
5868 12:14:48.934002 11, 0x0, sum = 2
5869 12:14:48.936418 12, 0x0, sum = 3
5870 12:14:48.937003 13, 0x0, sum = 4
5871 12:14:48.939412 best_step = 11
5872 12:14:48.940001
5873 12:14:48.940604 ==
5874 12:14:48.942967 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 12:14:48.946537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 12:14:48.947128 ==
5877 12:14:48.949275 RX Vref Scan: 0
5878 12:14:48.949709
5879 12:14:48.950235 RX Vref 0 -> 0, step: 1
5880 12:14:48.950750
5881 12:14:48.952806 RX Delay -53 -> 252, step: 4
5882 12:14:48.959677 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5883 12:14:48.962874 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5884 12:14:48.965936 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5885 12:14:48.969537 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5886 12:14:48.972804 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5887 12:14:48.979401 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5888 12:14:48.982456 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5889 12:14:48.985380 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5890 12:14:48.989024 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5891 12:14:48.992130 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5892 12:14:48.998502 iDelay=199, Bit 10, Center 92 (3 ~ 182) 180
5893 12:14:49.002133 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5894 12:14:49.005144 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5895 12:14:49.008577 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5896 12:14:49.014834 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5897 12:14:49.018466 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5898 12:14:49.019027 ==
5899 12:14:49.021546 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 12:14:49.024976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 12:14:49.025476 ==
5902 12:14:49.026083 DQS Delay:
5903 12:14:49.027850 DQS0 = 0, DQS1 = 0
5904 12:14:49.028375 DQM Delay:
5905 12:14:49.031471 DQM0 = 97, DQM1 = 91
5906 12:14:49.032100 DQ Delay:
5907 12:14:49.034763 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =92
5908 12:14:49.038397 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5909 12:14:49.041423 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =82
5910 12:14:49.044812 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5911 12:14:49.045377
5912 12:14:49.045876
5913 12:14:49.054697 [DQSOSCAuto] RK1, (LSB)MR18= 0xb21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5914 12:14:49.058262 CH1 RK1: MR19=505, MR18=B21
5915 12:14:49.061174 CH1_RK1: MR19=0x505, MR18=0xB21, DQSOSC=411, MR23=63, INC=64, DEC=42
5916 12:14:49.064217 [RxdqsGatingPostProcess] freq 933
5917 12:14:49.070925 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5918 12:14:49.074710 best DQS0 dly(2T, 0.5T) = (0, 10)
5919 12:14:49.077473 best DQS1 dly(2T, 0.5T) = (0, 10)
5920 12:14:49.081039 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5921 12:14:49.084004 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5922 12:14:49.087690 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 12:14:49.090721 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 12:14:49.094337 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 12:14:49.097408 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 12:14:49.100505 Pre-setting of DQS Precalculation
5927 12:14:49.104145 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5928 12:14:49.110726 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5929 12:14:49.116752 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5930 12:14:49.120252
5931 12:14:49.120689
5932 12:14:49.121034 [Calibration Summary] 1866 Mbps
5933 12:14:49.124161 CH 0, Rank 0
5934 12:14:49.124604 SW Impedance : PASS
5935 12:14:49.127161 DUTY Scan : NO K
5936 12:14:49.130578 ZQ Calibration : PASS
5937 12:14:49.130999 Jitter Meter : NO K
5938 12:14:49.133519 CBT Training : PASS
5939 12:14:49.137070 Write leveling : PASS
5940 12:14:49.137554 RX DQS gating : PASS
5941 12:14:49.139942 RX DQ/DQS(RDDQC) : PASS
5942 12:14:49.143412 TX DQ/DQS : PASS
5943 12:14:49.144025 RX DATLAT : PASS
5944 12:14:49.146997 RX DQ/DQS(Engine): PASS
5945 12:14:49.149886 TX OE : NO K
5946 12:14:49.150383 All Pass.
5947 12:14:49.150884
5948 12:14:49.151343 CH 0, Rank 1
5949 12:14:49.153402 SW Impedance : PASS
5950 12:14:49.156138 DUTY Scan : NO K
5951 12:14:49.156582 ZQ Calibration : PASS
5952 12:14:49.159663 Jitter Meter : NO K
5953 12:14:49.163275 CBT Training : PASS
5954 12:14:49.163696 Write leveling : PASS
5955 12:14:49.166424 RX DQS gating : PASS
5956 12:14:49.169748 RX DQ/DQS(RDDQC) : PASS
5957 12:14:49.170176 TX DQ/DQS : PASS
5958 12:14:49.172737 RX DATLAT : PASS
5959 12:14:49.176171 RX DQ/DQS(Engine): PASS
5960 12:14:49.176666 TX OE : NO K
5961 12:14:49.179225 All Pass.
5962 12:14:49.179778
5963 12:14:49.180343 CH 1, Rank 0
5964 12:14:49.182674 SW Impedance : PASS
5965 12:14:49.183094 DUTY Scan : NO K
5966 12:14:49.185790 ZQ Calibration : PASS
5967 12:14:49.189364 Jitter Meter : NO K
5968 12:14:49.189787 CBT Training : PASS
5969 12:14:49.192332 Write leveling : PASS
5970 12:14:49.196147 RX DQS gating : PASS
5971 12:14:49.196569 RX DQ/DQS(RDDQC) : PASS
5972 12:14:49.199108 TX DQ/DQS : PASS
5973 12:14:49.199531 RX DATLAT : PASS
5974 12:14:49.202702 RX DQ/DQS(Engine): PASS
5975 12:14:49.205855 TX OE : NO K
5976 12:14:49.206374 All Pass.
5977 12:14:49.206715
5978 12:14:49.207030 CH 1, Rank 1
5979 12:14:49.209527 SW Impedance : PASS
5980 12:14:49.212514 DUTY Scan : NO K
5981 12:14:49.212917 ZQ Calibration : PASS
5982 12:14:49.216141 Jitter Meter : NO K
5983 12:14:49.219014 CBT Training : PASS
5984 12:14:49.219443 Write leveling : PASS
5985 12:14:49.222656 RX DQS gating : PASS
5986 12:14:49.225477 RX DQ/DQS(RDDQC) : PASS
5987 12:14:49.225907 TX DQ/DQS : PASS
5988 12:14:49.229051 RX DATLAT : PASS
5989 12:14:49.232242 RX DQ/DQS(Engine): PASS
5990 12:14:49.232672 TX OE : NO K
5991 12:14:49.235718 All Pass.
5992 12:14:49.236183
5993 12:14:49.236528 DramC Write-DBI off
5994 12:14:49.238742 PER_BANK_REFRESH: Hybrid Mode
5995 12:14:49.241812 TX_TRACKING: ON
5996 12:14:49.248729 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5997 12:14:49.251711 [FAST_K] Save calibration result to emmc
5998 12:14:49.258496 dramc_set_vcore_voltage set vcore to 650000
5999 12:14:49.259031 Read voltage for 400, 6
6000 12:14:49.259382 Vio18 = 0
6001 12:14:49.262153 Vcore = 650000
6002 12:14:49.262584 Vdram = 0
6003 12:14:49.262929 Vddq = 0
6004 12:14:49.264915 Vmddr = 0
6005 12:14:49.268405 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6006 12:14:49.275154 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6007 12:14:49.277955 MEM_TYPE=3, freq_sel=20
6008 12:14:49.278387 sv_algorithm_assistance_LP4_800
6009 12:14:49.284359 ============ PULL DRAM RESETB DOWN ============
6010 12:14:49.287703 ========== PULL DRAM RESETB DOWN end =========
6011 12:14:49.291411 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6012 12:14:49.294550 ===================================
6013 12:14:49.297469 LPDDR4 DRAM CONFIGURATION
6014 12:14:49.301119 ===================================
6015 12:14:49.304024 EX_ROW_EN[0] = 0x0
6016 12:14:49.304493 EX_ROW_EN[1] = 0x0
6017 12:14:49.307686 LP4Y_EN = 0x0
6018 12:14:49.308151 WORK_FSP = 0x0
6019 12:14:49.310798 WL = 0x2
6020 12:14:49.311235 RL = 0x2
6021 12:14:49.314311 BL = 0x2
6022 12:14:49.314737 RPST = 0x0
6023 12:14:49.317206 RD_PRE = 0x0
6024 12:14:49.320869 WR_PRE = 0x1
6025 12:14:49.321295 WR_PST = 0x0
6026 12:14:49.323734 DBI_WR = 0x0
6027 12:14:49.324184 DBI_RD = 0x0
6028 12:14:49.327249 OTF = 0x1
6029 12:14:49.330616 ===================================
6030 12:14:49.333559 ===================================
6031 12:14:49.333984 ANA top config
6032 12:14:49.337241 ===================================
6033 12:14:49.340263 DLL_ASYNC_EN = 0
6034 12:14:49.344019 ALL_SLAVE_EN = 1
6035 12:14:49.344472 NEW_RANK_MODE = 1
6036 12:14:49.346959 DLL_IDLE_MODE = 1
6037 12:14:49.350480 LP45_APHY_COMB_EN = 1
6038 12:14:49.353493 TX_ODT_DIS = 1
6039 12:14:49.356868 NEW_8X_MODE = 1
6040 12:14:49.359957 ===================================
6041 12:14:49.363312 ===================================
6042 12:14:49.363770 data_rate = 800
6043 12:14:49.366483 CKR = 1
6044 12:14:49.369955 DQ_P2S_RATIO = 4
6045 12:14:49.373637 ===================================
6046 12:14:49.376736 CA_P2S_RATIO = 4
6047 12:14:49.379684 DQ_CA_OPEN = 0
6048 12:14:49.383470 DQ_SEMI_OPEN = 1
6049 12:14:49.384059 CA_SEMI_OPEN = 1
6050 12:14:49.386341 CA_FULL_RATE = 0
6051 12:14:49.390084 DQ_CKDIV4_EN = 0
6052 12:14:49.393168 CA_CKDIV4_EN = 1
6053 12:14:49.396657 CA_PREDIV_EN = 0
6054 12:14:49.399659 PH8_DLY = 0
6055 12:14:49.403181 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6056 12:14:49.403604 DQ_AAMCK_DIV = 0
6057 12:14:49.406220 CA_AAMCK_DIV = 0
6058 12:14:49.409522 CA_ADMCK_DIV = 4
6059 12:14:49.412785 DQ_TRACK_CA_EN = 0
6060 12:14:49.416025 CA_PICK = 800
6061 12:14:49.419279 CA_MCKIO = 400
6062 12:14:49.419703 MCKIO_SEMI = 400
6063 12:14:49.422822 PLL_FREQ = 3016
6064 12:14:49.426359 DQ_UI_PI_RATIO = 32
6065 12:14:49.429401 CA_UI_PI_RATIO = 32
6066 12:14:49.432118 ===================================
6067 12:14:49.435538 ===================================
6068 12:14:49.439236 memory_type:LPDDR4
6069 12:14:49.442116 GP_NUM : 10
6070 12:14:49.442620 SRAM_EN : 1
6071 12:14:49.445572 MD32_EN : 0
6072 12:14:49.448662 ===================================
6073 12:14:49.452361 [ANA_INIT] >>>>>>>>>>>>>>
6074 12:14:49.452834 <<<<<< [CONFIGURE PHASE]: ANA_TX
6075 12:14:49.455095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6076 12:14:49.458663 ===================================
6077 12:14:49.461710 data_rate = 800,PCW = 0X7400
6078 12:14:49.465071 ===================================
6079 12:14:49.468611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6080 12:14:49.475276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 12:14:49.485447 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 12:14:49.491795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6083 12:14:49.494454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6084 12:14:49.498324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6085 12:14:49.501390 [ANA_INIT] flow start
6086 12:14:49.502040 [ANA_INIT] PLL >>>>>>>>
6087 12:14:49.505096 [ANA_INIT] PLL <<<<<<<<
6088 12:14:49.508146 [ANA_INIT] MIDPI >>>>>>>>
6089 12:14:49.508573 [ANA_INIT] MIDPI <<<<<<<<
6090 12:14:49.511187 [ANA_INIT] DLL >>>>>>>>
6091 12:14:49.514735 [ANA_INIT] flow end
6092 12:14:49.517653 ============ LP4 DIFF to SE enter ============
6093 12:14:49.521269 ============ LP4 DIFF to SE exit ============
6094 12:14:49.524266 [ANA_INIT] <<<<<<<<<<<<<
6095 12:14:49.527801 [Flow] Enable top DCM control >>>>>
6096 12:14:49.530759 [Flow] Enable top DCM control <<<<<
6097 12:14:49.534393 Enable DLL master slave shuffle
6098 12:14:49.538095 ==============================================================
6099 12:14:49.540869 Gating Mode config
6100 12:14:49.547133 ==============================================================
6101 12:14:49.547614 Config description:
6102 12:14:49.557317 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6103 12:14:49.563641 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6104 12:14:49.570815 SELPH_MODE 0: By rank 1: By Phase
6105 12:14:49.573816 ==============================================================
6106 12:14:49.577391 GAT_TRACK_EN = 0
6107 12:14:49.580635 RX_GATING_MODE = 2
6108 12:14:49.583576 RX_GATING_TRACK_MODE = 2
6109 12:14:49.587251 SELPH_MODE = 1
6110 12:14:49.590278 PICG_EARLY_EN = 1
6111 12:14:49.593677 VALID_LAT_VALUE = 1
6112 12:14:49.600198 ==============================================================
6113 12:14:49.603634 Enter into Gating configuration >>>>
6114 12:14:49.606572 Exit from Gating configuration <<<<
6115 12:14:49.607049 Enter into DVFS_PRE_config >>>>>
6116 12:14:49.620075 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6117 12:14:49.623107 Exit from DVFS_PRE_config <<<<<
6118 12:14:49.626225 Enter into PICG configuration >>>>
6119 12:14:49.629784 Exit from PICG configuration <<<<
6120 12:14:49.632935 [RX_INPUT] configuration >>>>>
6121 12:14:49.633507 [RX_INPUT] configuration <<<<<
6122 12:14:49.639821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6123 12:14:49.646187 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6124 12:14:49.649166 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6125 12:14:49.656271 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6126 12:14:49.662801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 12:14:49.669080 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 12:14:49.672190 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6129 12:14:49.675981 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6130 12:14:49.682331 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6131 12:14:49.685818 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6132 12:14:49.689060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6133 12:14:49.695695 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 12:14:49.698627 ===================================
6135 12:14:49.699048 LPDDR4 DRAM CONFIGURATION
6136 12:14:49.702141 ===================================
6137 12:14:49.705561 EX_ROW_EN[0] = 0x0
6138 12:14:49.708662 EX_ROW_EN[1] = 0x0
6139 12:14:49.709278 LP4Y_EN = 0x0
6140 12:14:49.711944 WORK_FSP = 0x0
6141 12:14:49.712666 WL = 0x2
6142 12:14:49.715156 RL = 0x2
6143 12:14:49.715717 BL = 0x2
6144 12:14:49.718607 RPST = 0x0
6145 12:14:49.719215 RD_PRE = 0x0
6146 12:14:49.722183 WR_PRE = 0x1
6147 12:14:49.722744 WR_PST = 0x0
6148 12:14:49.725209 DBI_WR = 0x0
6149 12:14:49.725774 DBI_RD = 0x0
6150 12:14:49.728311 OTF = 0x1
6151 12:14:49.731718 ===================================
6152 12:14:49.734865 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6153 12:14:49.738413 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6154 12:14:49.744956 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 12:14:49.748078 ===================================
6156 12:14:49.748510 LPDDR4 DRAM CONFIGURATION
6157 12:14:49.751501 ===================================
6158 12:14:49.754603 EX_ROW_EN[0] = 0x10
6159 12:14:49.758024 EX_ROW_EN[1] = 0x0
6160 12:14:49.758461 LP4Y_EN = 0x0
6161 12:14:49.760937 WORK_FSP = 0x0
6162 12:14:49.761377 WL = 0x2
6163 12:14:49.764486 RL = 0x2
6164 12:14:49.764922 BL = 0x2
6165 12:14:49.767586 RPST = 0x0
6166 12:14:49.768023 RD_PRE = 0x0
6167 12:14:49.770787 WR_PRE = 0x1
6168 12:14:49.771227 WR_PST = 0x0
6169 12:14:49.774471 DBI_WR = 0x0
6170 12:14:49.774908 DBI_RD = 0x0
6171 12:14:49.777517 OTF = 0x1
6172 12:14:49.781137 ===================================
6173 12:14:49.787716 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6174 12:14:49.790584 nWR fixed to 30
6175 12:14:49.794301 [ModeRegInit_LP4] CH0 RK0
6176 12:14:49.794743 [ModeRegInit_LP4] CH0 RK1
6177 12:14:49.797267 [ModeRegInit_LP4] CH1 RK0
6178 12:14:49.800749 [ModeRegInit_LP4] CH1 RK1
6179 12:14:49.801178 match AC timing 19
6180 12:14:49.806747 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6181 12:14:49.810050 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6182 12:14:49.813770 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6183 12:14:49.820092 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6184 12:14:49.823232 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6185 12:14:49.823314 ==
6186 12:14:49.826335 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 12:14:49.829817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6188 12:14:49.832961 ==
6189 12:14:49.836463 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6190 12:14:49.842946 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6191 12:14:49.846439 [CA 0] Center 36 (8~64) winsize 57
6192 12:14:49.849410 [CA 1] Center 36 (8~64) winsize 57
6193 12:14:49.853036 [CA 2] Center 36 (8~64) winsize 57
6194 12:14:49.856088 [CA 3] Center 36 (8~64) winsize 57
6195 12:14:49.859556 [CA 4] Center 36 (8~64) winsize 57
6196 12:14:49.862484 [CA 5] Center 36 (8~64) winsize 57
6197 12:14:49.862600
6198 12:14:49.866231 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6199 12:14:49.866370
6200 12:14:49.869222 [CATrainingPosCal] consider 1 rank data
6201 12:14:49.872256 u2DelayCellTimex100 = 270/100 ps
6202 12:14:49.876069 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 12:14:49.879063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 12:14:49.882769 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 12:14:49.885759 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 12:14:49.889233 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 12:14:49.892136 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 12:14:49.892228
6209 12:14:49.899063 CA PerBit enable=1, Macro0, CA PI delay=36
6210 12:14:49.899152
6211 12:14:49.902175 [CBTSetCACLKResult] CA Dly = 36
6212 12:14:49.902258 CS Dly: 1 (0~32)
6213 12:14:49.902325 ==
6214 12:14:49.905265 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 12:14:49.908516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 12:14:49.908601 ==
6217 12:14:49.915015 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 12:14:49.922038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6219 12:14:49.925072 [CA 0] Center 36 (8~64) winsize 57
6220 12:14:49.928716 [CA 1] Center 36 (8~64) winsize 57
6221 12:14:49.931787 [CA 2] Center 36 (8~64) winsize 57
6222 12:14:49.934874 [CA 3] Center 36 (8~64) winsize 57
6223 12:14:49.938377 [CA 4] Center 36 (8~64) winsize 57
6224 12:14:49.941307 [CA 5] Center 36 (8~64) winsize 57
6225 12:14:49.941385
6226 12:14:49.945034 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6227 12:14:49.945108
6228 12:14:49.948007 [CATrainingPosCal] consider 2 rank data
6229 12:14:49.951102 u2DelayCellTimex100 = 270/100 ps
6230 12:14:49.954782 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:14:49.958162 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:14:49.961163 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:14:49.964841 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:14:49.968234 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 12:14:49.971528 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 12:14:49.971610
6237 12:14:49.977992 CA PerBit enable=1, Macro0, CA PI delay=36
6238 12:14:49.978082
6239 12:14:49.980648 [CBTSetCACLKResult] CA Dly = 36
6240 12:14:49.980732 CS Dly: 1 (0~32)
6241 12:14:49.980797
6242 12:14:49.984328 ----->DramcWriteLeveling(PI) begin...
6243 12:14:49.984411 ==
6244 12:14:49.987319 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 12:14:49.991076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 12:14:49.991152 ==
6247 12:14:49.993993 Write leveling (Byte 0): 40 => 8
6248 12:14:49.997520 Write leveling (Byte 1): 40 => 8
6249 12:14:50.000877 DramcWriteLeveling(PI) end<-----
6250 12:14:50.000950
6251 12:14:50.001027 ==
6252 12:14:50.003707 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 12:14:50.010539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 12:14:50.010631 ==
6255 12:14:50.010699 [Gating] SW mode calibration
6256 12:14:50.020187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6257 12:14:50.023635 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6258 12:14:50.030031 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 12:14:50.033762 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 12:14:50.036770 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 12:14:50.043335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 12:14:50.046956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 12:14:50.049915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 12:14:50.056502 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 12:14:50.060003 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 12:14:50.062932 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 12:14:50.066595 Total UI for P1: 0, mck2ui 16
6268 12:14:50.069535 best dqsien dly found for B0: ( 0, 14, 24)
6269 12:14:50.073123 Total UI for P1: 0, mck2ui 16
6270 12:14:50.076023 best dqsien dly found for B1: ( 0, 14, 24)
6271 12:14:50.079836 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6272 12:14:50.082686 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6273 12:14:50.082788
6274 12:14:50.089153 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 12:14:50.092809 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 12:14:50.092917 [Gating] SW calibration Done
6277 12:14:50.095777 ==
6278 12:14:50.099196 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 12:14:50.102699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 12:14:50.102803 ==
6281 12:14:50.102905 RX Vref Scan: 0
6282 12:14:50.102995
6283 12:14:50.106007 RX Vref 0 -> 0, step: 1
6284 12:14:50.106119
6285 12:14:50.109227 RX Delay -410 -> 252, step: 16
6286 12:14:50.112296 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6287 12:14:50.119204 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6288 12:14:50.122139 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6289 12:14:50.125460 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6290 12:14:50.129290 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6291 12:14:50.135354 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6292 12:14:50.138996 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6293 12:14:50.141894 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6294 12:14:50.145647 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6295 12:14:50.152284 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6296 12:14:50.155175 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6297 12:14:50.158619 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6298 12:14:50.161511 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6299 12:14:50.168170 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6300 12:14:50.171798 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6301 12:14:50.174748 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6302 12:14:50.174861 ==
6303 12:14:50.178335 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 12:14:50.184891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 12:14:50.184998 ==
6306 12:14:50.185092 DQS Delay:
6307 12:14:50.188419 DQS0 = 35, DQS1 = 59
6308 12:14:50.188495 DQM Delay:
6309 12:14:50.191391 DQM0 = 5, DQM1 = 17
6310 12:14:50.191490 DQ Delay:
6311 12:14:50.194387 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6312 12:14:50.197975 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6313 12:14:50.198050 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6314 12:14:50.204530 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6315 12:14:50.204634
6316 12:14:50.204728
6317 12:14:50.204820 ==
6318 12:14:50.207520 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 12:14:50.210942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 12:14:50.211050 ==
6321 12:14:50.211143
6322 12:14:50.211234
6323 12:14:50.214673 TX Vref Scan disable
6324 12:14:50.214773 == TX Byte 0 ==
6325 12:14:50.221016 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 12:14:50.224371 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 12:14:50.224479 == TX Byte 1 ==
6328 12:14:50.230680 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 12:14:50.234231 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 12:14:50.234334 ==
6331 12:14:50.237305 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 12:14:50.240941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 12:14:50.241020 ==
6334 12:14:50.241084
6335 12:14:50.241144
6336 12:14:50.244253 TX Vref Scan disable
6337 12:14:50.244324 == TX Byte 0 ==
6338 12:14:50.250843 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 12:14:50.253809 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 12:14:50.253890 == TX Byte 1 ==
6341 12:14:50.260272 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 12:14:50.263900 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 12:14:50.264001
6344 12:14:50.264102 [DATLAT]
6345 12:14:50.266984 Freq=400, CH0 RK0
6346 12:14:50.267080
6347 12:14:50.267143 DATLAT Default: 0xf
6348 12:14:50.270026 0, 0xFFFF, sum = 0
6349 12:14:50.270148 1, 0xFFFF, sum = 0
6350 12:14:50.273702 2, 0xFFFF, sum = 0
6351 12:14:50.273809 3, 0xFFFF, sum = 0
6352 12:14:50.276624 4, 0xFFFF, sum = 0
6353 12:14:50.276738 5, 0xFFFF, sum = 0
6354 12:14:50.280106 6, 0xFFFF, sum = 0
6355 12:14:50.283615 7, 0xFFFF, sum = 0
6356 12:14:50.283721 8, 0xFFFF, sum = 0
6357 12:14:50.286549 9, 0xFFFF, sum = 0
6358 12:14:50.286649 10, 0xFFFF, sum = 0
6359 12:14:50.290003 11, 0xFFFF, sum = 0
6360 12:14:50.290109 12, 0xFFFF, sum = 0
6361 12:14:50.293385 13, 0x0, sum = 1
6362 12:14:50.293485 14, 0x0, sum = 2
6363 12:14:50.296963 15, 0x0, sum = 3
6364 12:14:50.297052 16, 0x0, sum = 4
6365 12:14:50.297151 best_step = 14
6366 12:14:50.299903
6367 12:14:50.299999 ==
6368 12:14:50.303649 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 12:14:50.306533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 12:14:50.306640 ==
6371 12:14:50.306733 RX Vref Scan: 1
6372 12:14:50.306822
6373 12:14:50.310103 RX Vref 0 -> 0, step: 1
6374 12:14:50.310213
6375 12:14:50.313162 RX Delay -359 -> 252, step: 8
6376 12:14:50.313245
6377 12:14:50.316636 Set Vref, RX VrefLevel [Byte0]: 56
6378 12:14:50.319631 [Byte1]: 49
6379 12:14:50.323714
6380 12:14:50.323820 Final RX Vref Byte 0 = 56 to rank0
6381 12:14:50.327100 Final RX Vref Byte 1 = 49 to rank0
6382 12:14:50.330856 Final RX Vref Byte 0 = 56 to rank1
6383 12:14:50.333607 Final RX Vref Byte 1 = 49 to rank1==
6384 12:14:50.337097 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 12:14:50.343659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 12:14:50.343768 ==
6387 12:14:50.343865 DQS Delay:
6388 12:14:50.347207 DQS0 = 44, DQS1 = 60
6389 12:14:50.347304 DQM Delay:
6390 12:14:50.347397 DQM0 = 11, DQM1 = 17
6391 12:14:50.350282 DQ Delay:
6392 12:14:50.353745 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6393 12:14:50.356935 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6394 12:14:50.359866 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6395 12:14:50.363261 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6396 12:14:50.363343
6397 12:14:50.363408
6398 12:14:50.369811 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6399 12:14:50.373435 CH0 RK0: MR19=C0C, MR18=8D81
6400 12:14:50.380217 CH0_RK0: MR19=0xC0C, MR18=0x8D81, DQSOSC=392, MR23=63, INC=384, DEC=256
6401 12:14:50.380300 ==
6402 12:14:50.382925 Dram Type= 6, Freq= 0, CH_0, rank 1
6403 12:14:50.386721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 12:14:50.386803 ==
6405 12:14:50.390131 [Gating] SW mode calibration
6406 12:14:50.396459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6407 12:14:50.402991 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6408 12:14:50.406081 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 12:14:50.409944 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 12:14:50.416196 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 12:14:50.419425 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 12:14:50.422482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 12:14:50.429435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 12:14:50.432566 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 12:14:50.436013 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 12:14:50.442933 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 12:14:50.445984 Total UI for P1: 0, mck2ui 16
6418 12:14:50.448998 best dqsien dly found for B0: ( 0, 14, 24)
6419 12:14:50.452724 Total UI for P1: 0, mck2ui 16
6420 12:14:50.455590 best dqsien dly found for B1: ( 0, 14, 24)
6421 12:14:50.459179 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6422 12:14:50.462210 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6423 12:14:50.462294
6424 12:14:50.465825 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 12:14:50.468755 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 12:14:50.472268 [Gating] SW calibration Done
6427 12:14:50.472343 ==
6428 12:14:50.475401 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 12:14:50.478920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 12:14:50.478994 ==
6431 12:14:50.481907 RX Vref Scan: 0
6432 12:14:50.481986
6433 12:14:50.485450 RX Vref 0 -> 0, step: 1
6434 12:14:50.485520
6435 12:14:50.488811 RX Delay -410 -> 252, step: 16
6436 12:14:50.491989 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6437 12:14:50.494984 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6438 12:14:50.498522 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6439 12:14:50.505087 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6440 12:14:50.508231 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6441 12:14:50.511789 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6442 12:14:50.514748 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6443 12:14:50.521200 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6444 12:14:50.524831 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6445 12:14:50.528363 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6446 12:14:50.531341 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6447 12:14:50.537610 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6448 12:14:50.541223 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6449 12:14:50.544577 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6450 12:14:50.551133 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6451 12:14:50.554210 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6452 12:14:50.554297 ==
6453 12:14:50.557737 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 12:14:50.560815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 12:14:50.560899 ==
6456 12:14:50.564338 DQS Delay:
6457 12:14:50.564421 DQS0 = 35, DQS1 = 51
6458 12:14:50.564516 DQM Delay:
6459 12:14:50.567954 DQM0 = 6, DQM1 = 10
6460 12:14:50.568049 DQ Delay:
6461 12:14:50.570873 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6462 12:14:50.574453 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6463 12:14:50.577439 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6464 12:14:50.580696 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6465 12:14:50.580779
6466 12:14:50.580844
6467 12:14:50.580904 ==
6468 12:14:50.584355 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 12:14:50.587517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 12:14:50.590959 ==
6471 12:14:50.591042
6472 12:14:50.591122
6473 12:14:50.591182 TX Vref Scan disable
6474 12:14:50.594033 == TX Byte 0 ==
6475 12:14:50.597441 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6476 12:14:50.600466 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6477 12:14:50.603615 == TX Byte 1 ==
6478 12:14:50.606949 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6479 12:14:50.610742 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6480 12:14:50.610859 ==
6481 12:14:50.613479 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 12:14:50.620191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 12:14:50.620306 ==
6484 12:14:50.620405
6485 12:14:50.620541
6486 12:14:50.620644 TX Vref Scan disable
6487 12:14:50.623215 == TX Byte 0 ==
6488 12:14:50.626474 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6489 12:14:50.630288 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6490 12:14:50.633357 == TX Byte 1 ==
6491 12:14:50.636768 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6492 12:14:50.639886 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6493 12:14:50.639994
6494 12:14:50.643351 [DATLAT]
6495 12:14:50.643439 Freq=400, CH0 RK1
6496 12:14:50.643509
6497 12:14:50.646383 DATLAT Default: 0xe
6498 12:14:50.646471 0, 0xFFFF, sum = 0
6499 12:14:50.649722 1, 0xFFFF, sum = 0
6500 12:14:50.649858 2, 0xFFFF, sum = 0
6501 12:14:50.653204 3, 0xFFFF, sum = 0
6502 12:14:50.653321 4, 0xFFFF, sum = 0
6503 12:14:50.656116 5, 0xFFFF, sum = 0
6504 12:14:50.656233 6, 0xFFFF, sum = 0
6505 12:14:50.659814 7, 0xFFFF, sum = 0
6506 12:14:50.659926 8, 0xFFFF, sum = 0
6507 12:14:50.662735 9, 0xFFFF, sum = 0
6508 12:14:50.666385 10, 0xFFFF, sum = 0
6509 12:14:50.666499 11, 0xFFFF, sum = 0
6510 12:14:50.669945 12, 0xFFFF, sum = 0
6511 12:14:50.670059 13, 0x0, sum = 1
6512 12:14:50.673053 14, 0x0, sum = 2
6513 12:14:50.673166 15, 0x0, sum = 3
6514 12:14:50.676108 16, 0x0, sum = 4
6515 12:14:50.676213 best_step = 14
6516 12:14:50.676305
6517 12:14:50.676395 ==
6518 12:14:50.679663 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 12:14:50.682674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 12:14:50.682759 ==
6521 12:14:50.686374 RX Vref Scan: 0
6522 12:14:50.686459
6523 12:14:50.689158 RX Vref 0 -> 0, step: 1
6524 12:14:50.689241
6525 12:14:50.689307 RX Delay -343 -> 252, step: 8
6526 12:14:50.698074 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6527 12:14:50.701653 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6528 12:14:50.704662 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6529 12:14:50.711203 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6530 12:14:50.714550 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6531 12:14:50.718114 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6532 12:14:50.721147 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6533 12:14:50.727618 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6534 12:14:50.730953 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6535 12:14:50.734461 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6536 12:14:50.737511 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6537 12:14:50.744674 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6538 12:14:50.747602 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6539 12:14:50.750568 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6540 12:14:50.754123 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6541 12:14:50.760759 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6542 12:14:50.760843 ==
6543 12:14:50.763592 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:14:50.766936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:14:50.767019 ==
6546 12:14:50.770346 DQS Delay:
6547 12:14:50.770435 DQS0 = 40, DQS1 = 60
6548 12:14:50.770502 DQM Delay:
6549 12:14:50.773484 DQM0 = 6, DQM1 = 15
6550 12:14:50.773557 DQ Delay:
6551 12:14:50.777124 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6552 12:14:50.779920 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6553 12:14:50.783620 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6554 12:14:50.786690 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6555 12:14:50.786791
6556 12:14:50.786882
6557 12:14:50.796820 [DQSOSCAuto] RK1, (LSB)MR18= 0x817c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6558 12:14:50.796927 CH0 RK1: MR19=C0C, MR18=817C
6559 12:14:50.803584 CH0_RK1: MR19=0xC0C, MR18=0x817C, DQSOSC=393, MR23=63, INC=382, DEC=254
6560 12:14:50.806487 [RxdqsGatingPostProcess] freq 400
6561 12:14:50.813087 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6562 12:14:50.816620 best DQS0 dly(2T, 0.5T) = (0, 10)
6563 12:14:50.819528 best DQS1 dly(2T, 0.5T) = (0, 10)
6564 12:14:50.823286 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6565 12:14:50.826157 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6566 12:14:50.829815 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 12:14:50.833189 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 12:14:50.835909 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 12:14:50.839557 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 12:14:50.839660 Pre-setting of DQS Precalculation
6571 12:14:50.845817 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6572 12:14:50.845921 ==
6573 12:14:50.849198 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 12:14:50.852272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 12:14:50.852347 ==
6576 12:14:50.858961 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6577 12:14:50.865429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6578 12:14:50.869112 [CA 0] Center 36 (8~64) winsize 57
6579 12:14:50.872662 [CA 1] Center 36 (8~64) winsize 57
6580 12:14:50.875691 [CA 2] Center 36 (8~64) winsize 57
6581 12:14:50.878626 [CA 3] Center 36 (8~64) winsize 57
6582 12:14:50.882287 [CA 4] Center 36 (8~64) winsize 57
6583 12:14:50.885420 [CA 5] Center 36 (8~64) winsize 57
6584 12:14:50.885523
6585 12:14:50.889052 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6586 12:14:50.889151
6587 12:14:50.892062 [CATrainingPosCal] consider 1 rank data
6588 12:14:50.895637 u2DelayCellTimex100 = 270/100 ps
6589 12:14:50.899336 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 12:14:50.902198 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 12:14:50.905190 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 12:14:50.908671 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 12:14:50.911807 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 12:14:50.915363 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 12:14:50.915448
6596 12:14:50.918406 CA PerBit enable=1, Macro0, CA PI delay=36
6597 12:14:50.921744
6598 12:14:50.921827 [CBTSetCACLKResult] CA Dly = 36
6599 12:14:50.925402 CS Dly: 1 (0~32)
6600 12:14:50.925486 ==
6601 12:14:50.928465 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 12:14:50.931458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 12:14:50.931553 ==
6604 12:14:50.938070 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 12:14:50.945269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6606 12:14:50.948020 [CA 0] Center 36 (8~64) winsize 57
6607 12:14:50.951733 [CA 1] Center 36 (8~64) winsize 57
6608 12:14:50.954686 [CA 2] Center 36 (8~64) winsize 57
6609 12:14:50.957878 [CA 3] Center 36 (8~64) winsize 57
6610 12:14:50.957984 [CA 4] Center 36 (8~64) winsize 57
6611 12:14:50.961445 [CA 5] Center 36 (8~64) winsize 57
6612 12:14:50.961546
6613 12:14:50.968262 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6614 12:14:50.968391
6615 12:14:50.971151 [CATrainingPosCal] consider 2 rank data
6616 12:14:50.974738 u2DelayCellTimex100 = 270/100 ps
6617 12:14:50.977868 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:14:50.981558 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:14:50.984349 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:14:50.987818 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:14:50.991057 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 12:14:50.994706 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 12:14:50.995013
6624 12:14:50.997997 CA PerBit enable=1, Macro0, CA PI delay=36
6625 12:14:50.998385
6626 12:14:51.001375 [CBTSetCACLKResult] CA Dly = 36
6627 12:14:51.004498 CS Dly: 1 (0~32)
6628 12:14:51.005041
6629 12:14:51.007619 ----->DramcWriteLeveling(PI) begin...
6630 12:14:51.008269 ==
6631 12:14:51.011040 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 12:14:51.014589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 12:14:51.015081 ==
6634 12:14:51.017674 Write leveling (Byte 0): 40 => 8
6635 12:14:51.021219 Write leveling (Byte 1): 40 => 8
6636 12:14:51.024000 DramcWriteLeveling(PI) end<-----
6637 12:14:51.024478
6638 12:14:51.024840 ==
6639 12:14:51.027520 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 12:14:51.030569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 12:14:51.031141 ==
6642 12:14:51.034189 [Gating] SW mode calibration
6643 12:14:51.040639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6644 12:14:51.047379 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6645 12:14:51.050441 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 12:14:51.056875 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 12:14:51.060319 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 12:14:51.063794 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 12:14:51.070202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 12:14:51.073553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 12:14:51.077213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 12:14:51.083235 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 12:14:51.086788 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 12:14:51.089880 Total UI for P1: 0, mck2ui 16
6655 12:14:51.093440 best dqsien dly found for B0: ( 0, 14, 24)
6656 12:14:51.096497 Total UI for P1: 0, mck2ui 16
6657 12:14:51.099975 best dqsien dly found for B1: ( 0, 14, 24)
6658 12:14:51.102958 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6659 12:14:51.106557 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6660 12:14:51.106982
6661 12:14:51.110148 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 12:14:51.113012 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 12:14:51.115940 [Gating] SW calibration Done
6664 12:14:51.116433 ==
6665 12:14:51.119391 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 12:14:51.126021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 12:14:51.126465 ==
6668 12:14:51.126805 RX Vref Scan: 0
6669 12:14:51.127122
6670 12:14:51.129481 RX Vref 0 -> 0, step: 1
6671 12:14:51.129905
6672 12:14:51.132800 RX Delay -410 -> 252, step: 16
6673 12:14:51.135855 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6674 12:14:51.138961 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6675 12:14:51.145940 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6676 12:14:51.148935 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6677 12:14:51.152270 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6678 12:14:51.155769 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6679 12:14:51.162355 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6680 12:14:51.165714 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6681 12:14:51.168701 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6682 12:14:51.172176 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6683 12:14:51.178817 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6684 12:14:51.181835 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6685 12:14:51.185507 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6686 12:14:51.192125 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6687 12:14:51.195016 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6688 12:14:51.198579 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6689 12:14:51.199009 ==
6690 12:14:51.201737 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 12:14:51.204629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 12:14:51.208190 ==
6693 12:14:51.208623 DQS Delay:
6694 12:14:51.208967 DQS0 = 43, DQS1 = 51
6695 12:14:51.211199 DQM Delay:
6696 12:14:51.211628 DQM0 = 13, DQM1 = 14
6697 12:14:51.214682 DQ Delay:
6698 12:14:51.217666 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6699 12:14:51.218099 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6700 12:14:51.221223 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6701 12:14:51.224906 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6702 12:14:51.225337
6703 12:14:51.227745
6704 12:14:51.228200 ==
6705 12:14:51.231320 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 12:14:51.234718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 12:14:51.235150 ==
6708 12:14:51.235491
6709 12:14:51.235809
6710 12:14:51.238142 TX Vref Scan disable
6711 12:14:51.238571 == TX Byte 0 ==
6712 12:14:51.241078 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 12:14:51.247685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 12:14:51.248196 == TX Byte 1 ==
6715 12:14:51.251229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 12:14:51.257319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 12:14:51.257772 ==
6718 12:14:51.260769 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 12:14:51.264277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 12:14:51.264790 ==
6721 12:14:51.265255
6722 12:14:51.265682
6723 12:14:51.267135 TX Vref Scan disable
6724 12:14:51.267565 == TX Byte 0 ==
6725 12:14:51.274096 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 12:14:51.277047 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 12:14:51.277472 == TX Byte 1 ==
6728 12:14:51.283522 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 12:14:51.287113 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 12:14:51.287538
6731 12:14:51.287872 [DATLAT]
6732 12:14:51.290436 Freq=400, CH1 RK0
6733 12:14:51.290865
6734 12:14:51.291199 DATLAT Default: 0xf
6735 12:14:51.293511 0, 0xFFFF, sum = 0
6736 12:14:51.293942 1, 0xFFFF, sum = 0
6737 12:14:51.297055 2, 0xFFFF, sum = 0
6738 12:14:51.297484 3, 0xFFFF, sum = 0
6739 12:14:51.300121 4, 0xFFFF, sum = 0
6740 12:14:51.300549 5, 0xFFFF, sum = 0
6741 12:14:51.303691 6, 0xFFFF, sum = 0
6742 12:14:51.304171 7, 0xFFFF, sum = 0
6743 12:14:51.306705 8, 0xFFFF, sum = 0
6744 12:14:51.307136 9, 0xFFFF, sum = 0
6745 12:14:51.309773 10, 0xFFFF, sum = 0
6746 12:14:51.313409 11, 0xFFFF, sum = 0
6747 12:14:51.313839 12, 0xFFFF, sum = 0
6748 12:14:51.316424 13, 0x0, sum = 1
6749 12:14:51.316854 14, 0x0, sum = 2
6750 12:14:51.319941 15, 0x0, sum = 3
6751 12:14:51.320398 16, 0x0, sum = 4
6752 12:14:51.320741 best_step = 14
6753 12:14:51.323409
6754 12:14:51.323829 ==
6755 12:14:51.326411 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 12:14:51.329969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 12:14:51.330399 ==
6758 12:14:51.330734 RX Vref Scan: 1
6759 12:14:51.331045
6760 12:14:51.332950 RX Vref 0 -> 0, step: 1
6761 12:14:51.333499
6762 12:14:51.336430 RX Delay -343 -> 252, step: 8
6763 12:14:51.336963
6764 12:14:51.339412 Set Vref, RX VrefLevel [Byte0]: 53
6765 12:14:51.342587 [Byte1]: 48
6766 12:14:51.346710
6767 12:14:51.347235 Final RX Vref Byte 0 = 53 to rank0
6768 12:14:51.350518 Final RX Vref Byte 1 = 48 to rank0
6769 12:14:51.353358 Final RX Vref Byte 0 = 53 to rank1
6770 12:14:51.356533 Final RX Vref Byte 1 = 48 to rank1==
6771 12:14:51.360144 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 12:14:51.366413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 12:14:51.366843 ==
6774 12:14:51.367182 DQS Delay:
6775 12:14:51.369644 DQS0 = 44, DQS1 = 56
6776 12:14:51.370074 DQM Delay:
6777 12:14:51.373052 DQM0 = 10, DQM1 = 14
6778 12:14:51.373483 DQ Delay:
6779 12:14:51.376421 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6780 12:14:51.379339 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6781 12:14:51.379963 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6782 12:14:51.386120 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6783 12:14:51.386609
6784 12:14:51.387045
6785 12:14:51.392542 [DQSOSCAuto] RK0, (LSB)MR18= 0x668b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6786 12:14:51.396306 CH1 RK0: MR19=C0C, MR18=668B
6787 12:14:51.402385 CH1_RK0: MR19=0xC0C, MR18=0x668B, DQSOSC=392, MR23=63, INC=384, DEC=256
6788 12:14:51.402987 ==
6789 12:14:51.406092 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 12:14:51.409053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 12:14:51.409486 ==
6792 12:14:51.412570 [Gating] SW mode calibration
6793 12:14:51.419153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6794 12:14:51.425875 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6795 12:14:51.428770 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 12:14:51.432279 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 12:14:51.438505 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 12:14:51.442084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 12:14:51.445051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 12:14:51.451657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 12:14:51.455295 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 12:14:51.461759 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 12:14:51.465032 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 12:14:51.468189 Total UI for P1: 0, mck2ui 16
6805 12:14:51.471816 best dqsien dly found for B0: ( 0, 14, 24)
6806 12:14:51.474960 Total UI for P1: 0, mck2ui 16
6807 12:14:51.478268 best dqsien dly found for B1: ( 0, 14, 24)
6808 12:14:51.481716 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6809 12:14:51.485174 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6810 12:14:51.485598
6811 12:14:51.488068 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 12:14:51.491562 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 12:14:51.495133 [Gating] SW calibration Done
6814 12:14:51.495620 ==
6815 12:14:51.498049 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 12:14:51.501110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 12:14:51.501900 ==
6818 12:14:51.504553 RX Vref Scan: 0
6819 12:14:51.504977
6820 12:14:51.508083 RX Vref 0 -> 0, step: 1
6821 12:14:51.508511
6822 12:14:51.511109 RX Delay -410 -> 252, step: 16
6823 12:14:51.514705 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6824 12:14:51.517849 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6825 12:14:51.521495 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6826 12:14:51.527577 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6827 12:14:51.531014 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6828 12:14:51.533970 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6829 12:14:51.537496 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6830 12:14:51.544118 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6831 12:14:51.547197 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6832 12:14:51.550479 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6833 12:14:51.554228 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6834 12:14:51.560228 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6835 12:14:51.563839 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6836 12:14:51.567214 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6837 12:14:51.573392 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6838 12:14:51.577008 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6839 12:14:51.577448 ==
6840 12:14:51.580234 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 12:14:51.583203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 12:14:51.583644 ==
6843 12:14:51.586666 DQS Delay:
6844 12:14:51.587102 DQS0 = 43, DQS1 = 51
6845 12:14:51.590061 DQM Delay:
6846 12:14:51.590498 DQM0 = 10, DQM1 = 13
6847 12:14:51.590932 DQ Delay:
6848 12:14:51.593029 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6849 12:14:51.596616 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6850 12:14:51.599544 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6851 12:14:51.603028 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6852 12:14:51.603536
6853 12:14:51.604077
6854 12:14:51.604422 ==
6855 12:14:51.606640 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 12:14:51.612872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 12:14:51.613305 ==
6858 12:14:51.613647
6859 12:14:51.613962
6860 12:14:51.614338 TX Vref Scan disable
6861 12:14:51.616586 == TX Byte 0 ==
6862 12:14:51.619415 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6863 12:14:51.623179 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6864 12:14:51.626038 == TX Byte 1 ==
6865 12:14:51.629707 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6866 12:14:51.632676 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6867 12:14:51.633115 ==
6868 12:14:51.636201 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 12:14:51.642620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 12:14:51.643053 ==
6871 12:14:51.643392
6872 12:14:51.643709
6873 12:14:51.645739 TX Vref Scan disable
6874 12:14:51.646168 == TX Byte 0 ==
6875 12:14:51.649369 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6876 12:14:51.652896 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6877 12:14:51.656222 == TX Byte 1 ==
6878 12:14:51.659436 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6879 12:14:51.662261 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6880 12:14:51.665850
6881 12:14:51.666276 [DATLAT]
6882 12:14:51.666620 Freq=400, CH1 RK1
6883 12:14:51.666941
6884 12:14:51.668964 DATLAT Default: 0xe
6885 12:14:51.669396 0, 0xFFFF, sum = 0
6886 12:14:51.672544 1, 0xFFFF, sum = 0
6887 12:14:51.673000 2, 0xFFFF, sum = 0
6888 12:14:51.675680 3, 0xFFFF, sum = 0
6889 12:14:51.678980 4, 0xFFFF, sum = 0
6890 12:14:51.679555 5, 0xFFFF, sum = 0
6891 12:14:51.682520 6, 0xFFFF, sum = 0
6892 12:14:51.682975 7, 0xFFFF, sum = 0
6893 12:14:51.685129 8, 0xFFFF, sum = 0
6894 12:14:51.685628 9, 0xFFFF, sum = 0
6895 12:14:51.688717 10, 0xFFFF, sum = 0
6896 12:14:51.689331 11, 0xFFFF, sum = 0
6897 12:14:51.691987 12, 0xFFFF, sum = 0
6898 12:14:51.692456 13, 0x0, sum = 1
6899 12:14:51.695263 14, 0x0, sum = 2
6900 12:14:51.695699 15, 0x0, sum = 3
6901 12:14:51.698410 16, 0x0, sum = 4
6902 12:14:51.698845 best_step = 14
6903 12:14:51.699182
6904 12:14:51.699498 ==
6905 12:14:51.702047 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 12:14:51.708491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 12:14:51.709032 ==
6908 12:14:51.709516 RX Vref Scan: 0
6909 12:14:51.709979
6910 12:14:51.711437 RX Vref 0 -> 0, step: 1
6911 12:14:51.711938
6912 12:14:51.715121 RX Delay -343 -> 252, step: 8
6913 12:14:51.721292 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6914 12:14:51.724630 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6915 12:14:51.728383 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6916 12:14:51.731417 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6917 12:14:51.737952 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6918 12:14:51.741512 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6919 12:14:51.744555 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6920 12:14:51.748185 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6921 12:14:51.754355 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6922 12:14:51.757926 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6923 12:14:51.761396 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6924 12:14:51.764172 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6925 12:14:51.770855 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6926 12:14:51.774585 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6927 12:14:51.777475 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6928 12:14:51.784152 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6929 12:14:51.784585 ==
6930 12:14:51.787542 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:14:51.790382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:14:51.790891 ==
6933 12:14:51.791264 DQS Delay:
6934 12:14:51.793825 DQS0 = 48, DQS1 = 56
6935 12:14:51.794298 DQM Delay:
6936 12:14:51.797407 DQM0 = 11, DQM1 = 14
6937 12:14:51.797837 DQ Delay:
6938 12:14:51.800167 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6939 12:14:51.803748 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6940 12:14:51.807279 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6941 12:14:51.810129 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6942 12:14:51.810770
6943 12:14:51.811278
6944 12:14:51.817192 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6945 12:14:51.820128 CH1 RK1: MR19=C0C, MR18=6EA6
6946 12:14:51.826918 CH1_RK1: MR19=0xC0C, MR18=0x6EA6, DQSOSC=389, MR23=63, INC=390, DEC=260
6947 12:14:51.830185 [RxdqsGatingPostProcess] freq 400
6948 12:14:51.836586 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6949 12:14:51.840246 best DQS0 dly(2T, 0.5T) = (0, 10)
6950 12:14:51.843412 best DQS1 dly(2T, 0.5T) = (0, 10)
6951 12:14:51.847083 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6952 12:14:51.849914 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6953 12:14:51.850348 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 12:14:51.853421 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 12:14:51.856287 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 12:14:51.860087 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 12:14:51.862854 Pre-setting of DQS Precalculation
6958 12:14:51.869635 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6959 12:14:51.876180 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6960 12:14:51.882750 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6961 12:14:51.883185
6962 12:14:51.883528
6963 12:14:51.886450 [Calibration Summary] 800 Mbps
6964 12:14:51.886882 CH 0, Rank 0
6965 12:14:51.889349 SW Impedance : PASS
6966 12:14:51.892892 DUTY Scan : NO K
6967 12:14:51.893348 ZQ Calibration : PASS
6968 12:14:51.895610 Jitter Meter : NO K
6969 12:14:51.899187 CBT Training : PASS
6970 12:14:51.899669 Write leveling : PASS
6971 12:14:51.902406 RX DQS gating : PASS
6972 12:14:51.905798 RX DQ/DQS(RDDQC) : PASS
6973 12:14:51.906269 TX DQ/DQS : PASS
6974 12:14:51.909416 RX DATLAT : PASS
6975 12:14:51.912410 RX DQ/DQS(Engine): PASS
6976 12:14:51.912890 TX OE : NO K
6977 12:14:51.915854 All Pass.
6978 12:14:51.916432
6979 12:14:51.916809 CH 0, Rank 1
6980 12:14:51.919310 SW Impedance : PASS
6981 12:14:51.919776 DUTY Scan : NO K
6982 12:14:51.922255 ZQ Calibration : PASS
6983 12:14:51.925733 Jitter Meter : NO K
6984 12:14:51.926289 CBT Training : PASS
6985 12:14:51.928801 Write leveling : NO K
6986 12:14:51.932392 RX DQS gating : PASS
6987 12:14:51.932843 RX DQ/DQS(RDDQC) : PASS
6988 12:14:51.935434 TX DQ/DQS : PASS
6989 12:14:51.938921 RX DATLAT : PASS
6990 12:14:51.939344 RX DQ/DQS(Engine): PASS
6991 12:14:51.942028 TX OE : NO K
6992 12:14:51.942621 All Pass.
6993 12:14:51.942968
6994 12:14:51.945564 CH 1, Rank 0
6995 12:14:51.946132 SW Impedance : PASS
6996 12:14:51.948525 DUTY Scan : NO K
6997 12:14:51.952233 ZQ Calibration : PASS
6998 12:14:51.952855 Jitter Meter : NO K
6999 12:14:51.954975 CBT Training : PASS
7000 12:14:51.955477 Write leveling : PASS
7001 12:14:51.958719 RX DQS gating : PASS
7002 12:14:51.961679 RX DQ/DQS(RDDQC) : PASS
7003 12:14:51.962172 TX DQ/DQS : PASS
7004 12:14:51.965165 RX DATLAT : PASS
7005 12:14:51.968704 RX DQ/DQS(Engine): PASS
7006 12:14:51.969138 TX OE : NO K
7007 12:14:51.971831 All Pass.
7008 12:14:51.972449
7009 12:14:51.972841 CH 1, Rank 1
7010 12:14:51.974807 SW Impedance : PASS
7011 12:14:51.975275 DUTY Scan : NO K
7012 12:14:51.978301 ZQ Calibration : PASS
7013 12:14:51.981504 Jitter Meter : NO K
7014 12:14:51.981601 CBT Training : PASS
7015 12:14:51.984600 Write leveling : NO K
7016 12:14:51.987638 RX DQS gating : PASS
7017 12:14:51.987744 RX DQ/DQS(RDDQC) : PASS
7018 12:14:51.991045 TX DQ/DQS : PASS
7019 12:14:51.994658 RX DATLAT : PASS
7020 12:14:51.994746 RX DQ/DQS(Engine): PASS
7021 12:14:51.998115 TX OE : NO K
7022 12:14:51.998200 All Pass.
7023 12:14:51.998268
7024 12:14:52.001046 DramC Write-DBI off
7025 12:14:52.004463 PER_BANK_REFRESH: Hybrid Mode
7026 12:14:52.004552 TX_TRACKING: ON
7027 12:14:52.014466 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7028 12:14:52.017399 [FAST_K] Save calibration result to emmc
7029 12:14:52.020655 dramc_set_vcore_voltage set vcore to 725000
7030 12:14:52.024178 Read voltage for 1600, 0
7031 12:14:52.024296 Vio18 = 0
7032 12:14:52.024383 Vcore = 725000
7033 12:14:52.027861 Vdram = 0
7034 12:14:52.028013 Vddq = 0
7035 12:14:52.028124 Vmddr = 0
7036 12:14:52.034519 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7037 12:14:52.037427 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7038 12:14:52.040503 MEM_TYPE=3, freq_sel=13
7039 12:14:52.044150 sv_algorithm_assistance_LP4_3733
7040 12:14:52.047015 ============ PULL DRAM RESETB DOWN ============
7041 12:14:52.053689 ========== PULL DRAM RESETB DOWN end =========
7042 12:14:52.057263 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7043 12:14:52.060753 ===================================
7044 12:14:52.063624 LPDDR4 DRAM CONFIGURATION
7045 12:14:52.066801 ===================================
7046 12:14:52.066921 EX_ROW_EN[0] = 0x0
7047 12:14:52.070376 EX_ROW_EN[1] = 0x0
7048 12:14:52.070460 LP4Y_EN = 0x0
7049 12:14:52.073882 WORK_FSP = 0x1
7050 12:14:52.073967 WL = 0x5
7051 12:14:52.077100 RL = 0x5
7052 12:14:52.077184 BL = 0x2
7053 12:14:52.080501 RPST = 0x0
7054 12:14:52.083604 RD_PRE = 0x0
7055 12:14:52.083714 WR_PRE = 0x1
7056 12:14:52.086719 WR_PST = 0x1
7057 12:14:52.086802 DBI_WR = 0x0
7058 12:14:52.090361 DBI_RD = 0x0
7059 12:14:52.090444 OTF = 0x1
7060 12:14:52.093240 ===================================
7061 12:14:52.096894 ===================================
7062 12:14:52.099859 ANA top config
7063 12:14:52.103383 ===================================
7064 12:14:52.103503 DLL_ASYNC_EN = 0
7065 12:14:52.106770 ALL_SLAVE_EN = 0
7066 12:14:52.109662 NEW_RANK_MODE = 1
7067 12:14:52.113194 DLL_IDLE_MODE = 1
7068 12:14:52.113297 LP45_APHY_COMB_EN = 1
7069 12:14:52.116018 TX_ODT_DIS = 0
7070 12:14:52.119589 NEW_8X_MODE = 1
7071 12:14:52.123194 ===================================
7072 12:14:52.126431 ===================================
7073 12:14:52.129516 data_rate = 3200
7074 12:14:52.132930 CKR = 1
7075 12:14:52.136541 DQ_P2S_RATIO = 8
7076 12:14:52.139576 ===================================
7077 12:14:52.143151 CA_P2S_RATIO = 8
7078 12:14:52.143707 DQ_CA_OPEN = 0
7079 12:14:52.146150 DQ_SEMI_OPEN = 0
7080 12:14:52.149765 CA_SEMI_OPEN = 0
7081 12:14:52.152789 CA_FULL_RATE = 0
7082 12:14:52.155857 DQ_CKDIV4_EN = 0
7083 12:14:52.159375 CA_CKDIV4_EN = 0
7084 12:14:52.159799 CA_PREDIV_EN = 0
7085 12:14:52.162365 PH8_DLY = 12
7086 12:14:52.165826 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7087 12:14:52.169364 DQ_AAMCK_DIV = 4
7088 12:14:52.172484 CA_AAMCK_DIV = 4
7089 12:14:52.175950 CA_ADMCK_DIV = 4
7090 12:14:52.176440 DQ_TRACK_CA_EN = 0
7091 12:14:52.179484 CA_PICK = 1600
7092 12:14:52.182382 CA_MCKIO = 1600
7093 12:14:52.185906 MCKIO_SEMI = 0
7094 12:14:52.189600 PLL_FREQ = 3068
7095 12:14:52.192631 DQ_UI_PI_RATIO = 32
7096 12:14:52.195475 CA_UI_PI_RATIO = 0
7097 12:14:52.199186 ===================================
7098 12:14:52.202190 ===================================
7099 12:14:52.202627 memory_type:LPDDR4
7100 12:14:52.205834 GP_NUM : 10
7101 12:14:52.208689 SRAM_EN : 1
7102 12:14:52.209114 MD32_EN : 0
7103 12:14:52.212206 ===================================
7104 12:14:52.215539 [ANA_INIT] >>>>>>>>>>>>>>
7105 12:14:52.218894 <<<<<< [CONFIGURE PHASE]: ANA_TX
7106 12:14:52.221976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7107 12:14:52.225170 ===================================
7108 12:14:52.228751 data_rate = 3200,PCW = 0X7600
7109 12:14:52.232023 ===================================
7110 12:14:52.234970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7111 12:14:52.238660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 12:14:52.245459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 12:14:52.251516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7114 12:14:52.255081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7115 12:14:52.258041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7116 12:14:52.258482 [ANA_INIT] flow start
7117 12:14:52.261627 [ANA_INIT] PLL >>>>>>>>
7118 12:14:52.264766 [ANA_INIT] PLL <<<<<<<<
7119 12:14:52.265240 [ANA_INIT] MIDPI >>>>>>>>
7120 12:14:52.268195 [ANA_INIT] MIDPI <<<<<<<<
7121 12:14:52.271656 [ANA_INIT] DLL >>>>>>>>
7122 12:14:52.272191 [ANA_INIT] DLL <<<<<<<<
7123 12:14:52.274694 [ANA_INIT] flow end
7124 12:14:52.278176 ============ LP4 DIFF to SE enter ============
7125 12:14:52.281101 ============ LP4 DIFF to SE exit ============
7126 12:14:52.284854 [ANA_INIT] <<<<<<<<<<<<<
7127 12:14:52.288167 [Flow] Enable top DCM control >>>>>
7128 12:14:52.291001 [Flow] Enable top DCM control <<<<<
7129 12:14:52.294450 Enable DLL master slave shuffle
7130 12:14:52.300993 ==============================================================
7131 12:14:52.301440 Gating Mode config
7132 12:14:52.307585 ==============================================================
7133 12:14:52.310651 Config description:
7134 12:14:52.320961 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7135 12:14:52.327313 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7136 12:14:52.330385 SELPH_MODE 0: By rank 1: By Phase
7137 12:14:52.337103 ==============================================================
7138 12:14:52.340732 GAT_TRACK_EN = 1
7139 12:14:52.341159 RX_GATING_MODE = 2
7140 12:14:52.343770 RX_GATING_TRACK_MODE = 2
7141 12:14:52.347288 SELPH_MODE = 1
7142 12:14:52.350304 PICG_EARLY_EN = 1
7143 12:14:52.353467 VALID_LAT_VALUE = 1
7144 12:14:52.360577 ==============================================================
7145 12:14:52.363521 Enter into Gating configuration >>>>
7146 12:14:52.367079 Exit from Gating configuration <<<<
7147 12:14:52.370163 Enter into DVFS_PRE_config >>>>>
7148 12:14:52.380228 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7149 12:14:52.383235 Exit from DVFS_PRE_config <<<<<
7150 12:14:52.386808 Enter into PICG configuration >>>>
7151 12:14:52.389673 Exit from PICG configuration <<<<
7152 12:14:52.393236 [RX_INPUT] configuration >>>>>
7153 12:14:52.396449 [RX_INPUT] configuration <<<<<
7154 12:14:52.400101 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7155 12:14:52.406123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7156 12:14:52.412795 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7157 12:14:52.419257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7158 12:14:52.425946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 12:14:52.429495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 12:14:52.435978 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7161 12:14:52.439734 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7162 12:14:52.442476 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7163 12:14:52.446153 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7164 12:14:52.452486 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7165 12:14:52.455636 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 12:14:52.459194 ===================================
7167 12:14:52.462342 LPDDR4 DRAM CONFIGURATION
7168 12:14:52.465721 ===================================
7169 12:14:52.466145 EX_ROW_EN[0] = 0x0
7170 12:14:52.468845 EX_ROW_EN[1] = 0x0
7171 12:14:52.469268 LP4Y_EN = 0x0
7172 12:14:52.472412 WORK_FSP = 0x1
7173 12:14:52.475429 WL = 0x5
7174 12:14:52.475850 RL = 0x5
7175 12:14:52.478557 BL = 0x2
7176 12:14:52.478640 RPST = 0x0
7177 12:14:52.481572 RD_PRE = 0x0
7178 12:14:52.481657 WR_PRE = 0x1
7179 12:14:52.485063 WR_PST = 0x1
7180 12:14:52.485145 DBI_WR = 0x0
7181 12:14:52.488000 DBI_RD = 0x0
7182 12:14:52.488104 OTF = 0x1
7183 12:14:52.491167 ===================================
7184 12:14:52.494928 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7185 12:14:52.501200 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7186 12:14:52.504841 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 12:14:52.507835 ===================================
7188 12:14:52.510936 LPDDR4 DRAM CONFIGURATION
7189 12:14:52.514350 ===================================
7190 12:14:52.514432 EX_ROW_EN[0] = 0x10
7191 12:14:52.517662 EX_ROW_EN[1] = 0x0
7192 12:14:52.520863 LP4Y_EN = 0x0
7193 12:14:52.520944 WORK_FSP = 0x1
7194 12:14:52.524455 WL = 0x5
7195 12:14:52.524537 RL = 0x5
7196 12:14:52.527459 BL = 0x2
7197 12:14:52.527541 RPST = 0x0
7198 12:14:52.530749 RD_PRE = 0x0
7199 12:14:52.530831 WR_PRE = 0x1
7200 12:14:52.534145 WR_PST = 0x1
7201 12:14:52.534227 DBI_WR = 0x0
7202 12:14:52.537172 DBI_RD = 0x0
7203 12:14:52.537254 OTF = 0x1
7204 12:14:52.540858 ===================================
7205 12:14:52.547323 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7206 12:14:52.547405 ==
7207 12:14:52.550177 Dram Type= 6, Freq= 0, CH_0, rank 0
7208 12:14:52.556922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7209 12:14:52.557004 ==
7210 12:14:52.557070 [Duty_Offset_Calibration]
7211 12:14:52.560336 B0:2 B1:0 CA:4
7212 12:14:52.560417
7213 12:14:52.563461 [DutyScan_Calibration_Flow] k_type=0
7214 12:14:52.571878
7215 12:14:52.571960 ==CLK 0==
7216 12:14:52.575340 Final CLK duty delay cell = -4
7217 12:14:52.578348 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7218 12:14:52.582018 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7219 12:14:52.585211 [-4] AVG Duty = 4922%(X100)
7220 12:14:52.585296
7221 12:14:52.588173 CH0 CLK Duty spec in!! Max-Min= 218%
7222 12:14:52.591855 [DutyScan_Calibration_Flow] ====Done====
7223 12:14:52.591965
7224 12:14:52.595147 [DutyScan_Calibration_Flow] k_type=1
7225 12:14:52.611371
7226 12:14:52.611453 ==DQS 0 ==
7227 12:14:52.614996 Final DQS duty delay cell = -4
7228 12:14:52.617903 [-4] MAX Duty = 4969%(X100), DQS PI = 48
7229 12:14:52.621552 [-4] MIN Duty = 4782%(X100), DQS PI = 4
7230 12:14:52.624622 [-4] AVG Duty = 4875%(X100)
7231 12:14:52.624695
7232 12:14:52.624757 ==DQS 1 ==
7233 12:14:52.628156 Final DQS duty delay cell = 0
7234 12:14:52.631023 [0] MAX Duty = 5187%(X100), DQS PI = 0
7235 12:14:52.634540 [0] MIN Duty = 4969%(X100), DQS PI = 10
7236 12:14:52.637481 [0] AVG Duty = 5078%(X100)
7237 12:14:52.637563
7238 12:14:52.640861 CH0 DQS 0 Duty spec in!! Max-Min= 187%
7239 12:14:52.640943
7240 12:14:52.644450 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7241 12:14:52.647431 [DutyScan_Calibration_Flow] ====Done====
7242 12:14:52.647513
7243 12:14:52.650436 [DutyScan_Calibration_Flow] k_type=3
7244 12:14:52.669033
7245 12:14:52.669152 ==DQM 0 ==
7246 12:14:52.671931 Final DQM duty delay cell = 0
7247 12:14:52.675415 [0] MAX Duty = 5124%(X100), DQS PI = 22
7248 12:14:52.679057 [0] MIN Duty = 4907%(X100), DQS PI = 50
7249 12:14:52.682121 [0] AVG Duty = 5015%(X100)
7250 12:14:52.682203
7251 12:14:52.682268 ==DQM 1 ==
7252 12:14:52.685065 Final DQM duty delay cell = 0
7253 12:14:52.688709 [0] MAX Duty = 4969%(X100), DQS PI = 0
7254 12:14:52.692161 [0] MIN Duty = 4844%(X100), DQS PI = 16
7255 12:14:52.695071 [0] AVG Duty = 4906%(X100)
7256 12:14:52.695155
7257 12:14:52.698976 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7258 12:14:52.699404
7259 12:14:52.702892 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7260 12:14:52.705818 [DutyScan_Calibration_Flow] ====Done====
7261 12:14:52.706247
7262 12:14:52.708715 [DutyScan_Calibration_Flow] k_type=2
7263 12:14:52.725986
7264 12:14:52.726449 ==DQ 0 ==
7265 12:14:52.729626 Final DQ duty delay cell = 0
7266 12:14:52.733206 [0] MAX Duty = 5124%(X100), DQS PI = 20
7267 12:14:52.736627 [0] MIN Duty = 4969%(X100), DQS PI = 10
7268 12:14:52.737129 [0] AVG Duty = 5046%(X100)
7269 12:14:52.739623
7270 12:14:52.740070 ==DQ 1 ==
7271 12:14:52.742930 Final DQ duty delay cell = 0
7272 12:14:52.746333 [0] MAX Duty = 5187%(X100), DQS PI = 2
7273 12:14:52.749393 [0] MIN Duty = 4938%(X100), DQS PI = 12
7274 12:14:52.749822 [0] AVG Duty = 5062%(X100)
7275 12:14:52.750158
7276 12:14:52.753045 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7277 12:14:52.756001
7278 12:14:52.759443 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7279 12:14:52.763052 [DutyScan_Calibration_Flow] ====Done====
7280 12:14:52.763480 ==
7281 12:14:52.766059 Dram Type= 6, Freq= 0, CH_1, rank 0
7282 12:14:52.769188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 12:14:52.769619 ==
7284 12:14:52.772189 [Duty_Offset_Calibration]
7285 12:14:52.772616 B0:0 B1:-1 CA:3
7286 12:14:52.772952
7287 12:14:52.776010 [DutyScan_Calibration_Flow] k_type=0
7288 12:14:52.785529
7289 12:14:52.785955 ==CLK 0==
7290 12:14:52.789052 Final CLK duty delay cell = -4
7291 12:14:52.792533 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7292 12:14:52.795919 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7293 12:14:52.798759 [-4] AVG Duty = 4922%(X100)
7294 12:14:52.799183
7295 12:14:52.802428 CH1 CLK Duty spec in!! Max-Min= 156%
7296 12:14:52.805395 [DutyScan_Calibration_Flow] ====Done====
7297 12:14:52.805822
7298 12:14:52.809089 [DutyScan_Calibration_Flow] k_type=1
7299 12:14:52.824888
7300 12:14:52.825309 ==DQS 0 ==
7301 12:14:52.828482 Final DQS duty delay cell = 0
7302 12:14:52.831541 [0] MAX Duty = 5250%(X100), DQS PI = 28
7303 12:14:52.835010 [0] MIN Duty = 4938%(X100), DQS PI = 40
7304 12:14:52.838040 [0] AVG Duty = 5094%(X100)
7305 12:14:52.838454
7306 12:14:52.838851 ==DQS 1 ==
7307 12:14:52.841452 Final DQS duty delay cell = -4
7308 12:14:52.844456 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7309 12:14:52.847830 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7310 12:14:52.851167 [-4] AVG Duty = 4922%(X100)
7311 12:14:52.851590
7312 12:14:52.854742 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7313 12:14:52.855160
7314 12:14:52.857731 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7315 12:14:52.861142 [DutyScan_Calibration_Flow] ====Done====
7316 12:14:52.861558
7317 12:14:52.864163 [DutyScan_Calibration_Flow] k_type=3
7318 12:14:52.882434
7319 12:14:52.882847 ==DQM 0 ==
7320 12:14:52.885445 Final DQM duty delay cell = 0
7321 12:14:52.889044 [0] MAX Duty = 5062%(X100), DQS PI = 30
7322 12:14:52.892010 [0] MIN Duty = 4782%(X100), DQS PI = 40
7323 12:14:52.895623 [0] AVG Duty = 4922%(X100)
7324 12:14:52.896071
7325 12:14:52.896414 ==DQM 1 ==
7326 12:14:52.898734 Final DQM duty delay cell = 0
7327 12:14:52.901999 [0] MAX Duty = 4969%(X100), DQS PI = 30
7328 12:14:52.905033 [0] MIN Duty = 4813%(X100), DQS PI = 12
7329 12:14:52.908679 [0] AVG Duty = 4891%(X100)
7330 12:14:52.909096
7331 12:14:52.911759 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7332 12:14:52.912201
7333 12:14:52.915420 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7334 12:14:52.918313 [DutyScan_Calibration_Flow] ====Done====
7335 12:14:52.918733
7336 12:14:52.921939 [DutyScan_Calibration_Flow] k_type=2
7337 12:14:52.938611
7338 12:14:52.939025 ==DQ 0 ==
7339 12:14:52.941443 Final DQ duty delay cell = -4
7340 12:14:52.945063 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7341 12:14:52.948363 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7342 12:14:52.951355 [-4] AVG Duty = 4891%(X100)
7343 12:14:52.951768
7344 12:14:52.952137 ==DQ 1 ==
7345 12:14:52.954804 Final DQ duty delay cell = 0
7346 12:14:52.958309 [0] MAX Duty = 5062%(X100), DQS PI = 32
7347 12:14:52.961368 [0] MIN Duty = 4875%(X100), DQS PI = 56
7348 12:14:52.964755 [0] AVG Duty = 4968%(X100)
7349 12:14:52.965174
7350 12:14:52.967977 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7351 12:14:52.968110
7352 12:14:52.971002 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7353 12:14:52.973985 [DutyScan_Calibration_Flow] ====Done====
7354 12:14:52.977675 nWR fixed to 30
7355 12:14:52.980602 [ModeRegInit_LP4] CH0 RK0
7356 12:14:52.980688 [ModeRegInit_LP4] CH0 RK1
7357 12:14:52.984313 [ModeRegInit_LP4] CH1 RK0
7358 12:14:52.987319 [ModeRegInit_LP4] CH1 RK1
7359 12:14:52.987399 match AC timing 5
7360 12:14:52.993962 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7361 12:14:52.997061 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7362 12:14:53.000929 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7363 12:14:53.007429 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7364 12:14:53.010996 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7365 12:14:53.014143 [MiockJmeterHQA]
7366 12:14:53.014554
7367 12:14:53.017584 [DramcMiockJmeter] u1RxGatingPI = 0
7368 12:14:53.018003 0 : 4257, 4030
7369 12:14:53.018343 4 : 4253, 4027
7370 12:14:53.020598 8 : 4252, 4027
7371 12:14:53.021022 12 : 4253, 4027
7372 12:14:53.024240 16 : 4363, 4138
7373 12:14:53.024712 20 : 4253, 4026
7374 12:14:53.027563 24 : 4252, 4027
7375 12:14:53.027985 28 : 4252, 4027
7376 12:14:53.028369 32 : 4255, 4029
7377 12:14:53.030936 36 : 4253, 4026
7378 12:14:53.031359 40 : 4252, 4027
7379 12:14:53.034081 44 : 4366, 4139
7380 12:14:53.034505 48 : 4253, 4026
7381 12:14:53.036925 52 : 4255, 4030
7382 12:14:53.037384 56 : 4252, 4027
7383 12:14:53.040466 60 : 4360, 4138
7384 12:14:53.040987 64 : 4249, 4027
7385 12:14:53.041512 68 : 4360, 4137
7386 12:14:53.044107 72 : 4250, 4027
7387 12:14:53.044613 76 : 4250, 4027
7388 12:14:53.047078 80 : 4250, 4027
7389 12:14:53.047503 84 : 4252, 4030
7390 12:14:53.050494 88 : 4360, 4137
7391 12:14:53.051054 92 : 4250, 4027
7392 12:14:53.053789 96 : 4361, 3616
7393 12:14:53.054245 100 : 4250, 0
7394 12:14:53.054755 104 : 4363, 0
7395 12:14:53.057365 108 : 4252, 0
7396 12:14:53.057950 112 : 4252, 0
7397 12:14:53.058471 116 : 4250, 0
7398 12:14:53.060632 120 : 4253, 0
7399 12:14:53.061070 124 : 4360, 0
7400 12:14:53.063656 128 : 4250, 0
7401 12:14:53.064228 132 : 4250, 0
7402 12:14:53.064582 136 : 4361, 0
7403 12:14:53.066631 140 : 4361, 0
7404 12:14:53.067051 144 : 4363, 0
7405 12:14:53.069950 148 : 4250, 0
7406 12:14:53.070376 152 : 4250, 0
7407 12:14:53.070714 156 : 4250, 0
7408 12:14:53.073716 160 : 4253, 0
7409 12:14:53.074137 164 : 4250, 0
7410 12:14:53.076672 168 : 4250, 0
7411 12:14:53.077096 172 : 4253, 0
7412 12:14:53.077432 176 : 4360, 0
7413 12:14:53.079765 180 : 4250, 0
7414 12:14:53.080300 184 : 4249, 0
7415 12:14:53.083394 188 : 4250, 0
7416 12:14:53.083822 192 : 4361, 0
7417 12:14:53.084208 196 : 4361, 0
7418 12:14:53.086948 200 : 4250, 0
7419 12:14:53.087372 204 : 4250, 0
7420 12:14:53.089870 208 : 4250, 0
7421 12:14:53.090296 212 : 4252, 0
7422 12:14:53.090659 216 : 4250, 0
7423 12:14:53.092909 220 : 4250, 394
7424 12:14:53.093334 224 : 4360, 4091
7425 12:14:53.096533 228 : 4250, 4027
7426 12:14:53.096970 232 : 4361, 4137
7427 12:14:53.099501 236 : 4250, 4027
7428 12:14:53.099932 240 : 4250, 4027
7429 12:14:53.103186 244 : 4250, 4027
7430 12:14:53.103639 248 : 4253, 4029
7431 12:14:53.106180 252 : 4250, 4026
7432 12:14:53.106629 256 : 4250, 4027
7433 12:14:53.106974 260 : 4250, 4027
7434 12:14:53.109394 264 : 4252, 4029
7435 12:14:53.109478 268 : 4250, 4026
7436 12:14:53.112422 272 : 4361, 4137
7437 12:14:53.112506 276 : 4360, 4137
7438 12:14:53.115895 280 : 4250, 4027
7439 12:14:53.115995 284 : 4363, 4140
7440 12:14:53.119455 288 : 4360, 4137
7441 12:14:53.119539 292 : 4250, 4027
7442 12:14:53.122431 296 : 4250, 4027
7443 12:14:53.122515 300 : 4252, 4029
7444 12:14:53.125892 304 : 4250, 4026
7445 12:14:53.125976 308 : 4253, 4029
7446 12:14:53.128868 312 : 4250, 4027
7447 12:14:53.128951 316 : 4253, 4029
7448 12:14:53.132330 320 : 4250, 4026
7449 12:14:53.132414 324 : 4361, 4137
7450 12:14:53.132480 328 : 4360, 4138
7451 12:14:53.135678 332 : 4250, 4014
7452 12:14:53.135762 336 : 4363, 2244
7453 12:14:53.139317 340 : 4360, 11
7454 12:14:53.139406
7455 12:14:53.142134 MIOCK jitter meter ch=0
7456 12:14:53.142216
7457 12:14:53.142310 1T = (340-100) = 240 dly cells
7458 12:14:53.148889 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7459 12:14:53.148973 ==
7460 12:14:53.152328 Dram Type= 6, Freq= 0, CH_0, rank 0
7461 12:14:53.158469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7462 12:14:53.158551 ==
7463 12:14:53.161938 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7464 12:14:53.168292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7465 12:14:53.171758 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7466 12:14:53.178437 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7467 12:14:53.185806 [CA 0] Center 43 (13~74) winsize 62
7468 12:14:53.189219 [CA 1] Center 43 (13~73) winsize 61
7469 12:14:53.192342 [CA 2] Center 39 (10~68) winsize 59
7470 12:14:53.195972 [CA 3] Center 38 (9~67) winsize 59
7471 12:14:53.199020 [CA 4] Center 36 (7~66) winsize 60
7472 12:14:53.202134 [CA 5] Center 36 (6~66) winsize 61
7473 12:14:53.202239
7474 12:14:53.205679 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7475 12:14:53.205754
7476 12:14:53.209326 [CATrainingPosCal] consider 1 rank data
7477 12:14:53.212383 u2DelayCellTimex100 = 271/100 ps
7478 12:14:53.218859 CA0 delay=43 (13~74),Diff = 7 PI (25 cell)
7479 12:14:53.222583 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7480 12:14:53.225573 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7481 12:14:53.228727 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7482 12:14:53.232303 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7483 12:14:53.235185 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7484 12:14:53.235279
7485 12:14:53.239058 CA PerBit enable=1, Macro0, CA PI delay=36
7486 12:14:53.239168
7487 12:14:53.242077 [CBTSetCACLKResult] CA Dly = 36
7488 12:14:53.245055 CS Dly: 10 (0~41)
7489 12:14:53.248515 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7490 12:14:53.251671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7491 12:14:53.251753 ==
7492 12:14:53.254996 Dram Type= 6, Freq= 0, CH_0, rank 1
7493 12:14:53.261395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 12:14:53.261479 ==
7495 12:14:53.264863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 12:14:53.271632 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 12:14:53.274416 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 12:14:53.281522 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 12:14:53.289351 [CA 0] Center 43 (13~74) winsize 62
7500 12:14:53.293057 [CA 1] Center 43 (13~73) winsize 61
7501 12:14:53.296021 [CA 2] Center 38 (9~68) winsize 60
7502 12:14:53.299865 [CA 3] Center 38 (9~68) winsize 60
7503 12:14:53.302733 [CA 4] Center 36 (6~67) winsize 62
7504 12:14:53.305802 [CA 5] Center 36 (6~66) winsize 61
7505 12:14:53.305898
7506 12:14:53.309317 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7507 12:14:53.309427
7508 12:14:53.315795 [CATrainingPosCal] consider 2 rank data
7509 12:14:53.315881 u2DelayCellTimex100 = 271/100 ps
7510 12:14:53.322512 CA0 delay=43 (13~74),Diff = 7 PI (25 cell)
7511 12:14:53.325961 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7512 12:14:53.329024 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7513 12:14:53.332181 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7514 12:14:53.335805 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7515 12:14:53.338758 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7516 12:14:53.338882
7517 12:14:53.342306 CA PerBit enable=1, Macro0, CA PI delay=36
7518 12:14:53.342388
7519 12:14:53.345547 [CBTSetCACLKResult] CA Dly = 36
7520 12:14:53.348433 CS Dly: 11 (0~44)
7521 12:14:53.352292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 12:14:53.355369 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 12:14:53.355451
7524 12:14:53.358954 ----->DramcWriteLeveling(PI) begin...
7525 12:14:53.361688 ==
7526 12:14:53.365273 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 12:14:53.368861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 12:14:53.368970 ==
7529 12:14:53.371769 Write leveling (Byte 0): 37 => 37
7530 12:14:53.375243 Write leveling (Byte 1): 27 => 27
7531 12:14:53.378189 DramcWriteLeveling(PI) end<-----
7532 12:14:53.378282
7533 12:14:53.378357 ==
7534 12:14:53.381886 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 12:14:53.385375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 12:14:53.385519 ==
7537 12:14:53.388392 [Gating] SW mode calibration
7538 12:14:53.394984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7539 12:14:53.401623 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7540 12:14:53.404501 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 12:14:53.408090 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 12:14:53.414934 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7543 12:14:53.417978 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7544 12:14:53.421405 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7545 12:14:53.428001 1 4 20 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7546 12:14:53.431112 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 12:14:53.434608 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 12:14:53.441066 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 12:14:53.444154 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 12:14:53.447587 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7551 12:14:53.454530 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7552 12:14:53.457676 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7553 12:14:53.460611 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7554 12:14:53.467528 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 12:14:53.470940 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 12:14:53.473846 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 12:14:53.480346 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 12:14:53.483903 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7559 12:14:53.486873 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7560 12:14:53.493913 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7561 12:14:53.496769 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
7562 12:14:53.500572 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 12:14:53.506618 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 12:14:53.510311 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 12:14:53.513382 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 12:14:53.519837 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 12:14:53.523376 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7568 12:14:53.526363 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 12:14:53.533496 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 12:14:53.536147 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 12:14:53.539789 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 12:14:53.546073 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 12:14:53.549758 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:14:53.552551 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:14:53.559067 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 12:14:53.562791 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:14:53.566220 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:14:53.572217 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:14:53.575864 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:14:53.578623 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:14:53.585089 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:14:53.588614 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:14:53.591890 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 12:14:53.598968 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7585 12:14:53.602057 Total UI for P1: 0, mck2ui 16
7586 12:14:53.605547 best dqsien dly found for B0: ( 1, 9, 12)
7587 12:14:53.608679 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 12:14:53.611845 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 12:14:53.615389 Total UI for P1: 0, mck2ui 16
7590 12:14:53.618401 best dqsien dly found for B1: ( 1, 9, 20)
7591 12:14:53.625111 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7592 12:14:53.628331 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7593 12:14:53.628516
7594 12:14:53.631356 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7595 12:14:53.635149 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7596 12:14:53.638088 [Gating] SW calibration Done
7597 12:14:53.638534 ==
7598 12:14:53.641554 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 12:14:53.645203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 12:14:53.645651 ==
7601 12:14:53.648229 RX Vref Scan: 0
7602 12:14:53.648651
7603 12:14:53.649036 RX Vref 0 -> 0, step: 1
7604 12:14:53.649356
7605 12:14:53.651866 RX Delay 0 -> 252, step: 8
7606 12:14:53.654784 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7607 12:14:53.661120 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7608 12:14:53.664711 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7609 12:14:53.667538 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7610 12:14:53.671091 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7611 12:14:53.674686 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7612 12:14:53.680927 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7613 12:14:53.684253 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7614 12:14:53.687386 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7615 12:14:53.690772 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7616 12:14:53.693976 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7617 12:14:53.700880 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7618 12:14:53.703924 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7619 12:14:53.707746 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7620 12:14:53.710751 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7621 12:14:53.717376 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7622 12:14:53.717823 ==
7623 12:14:53.720953 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 12:14:53.724017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 12:14:53.724476 ==
7626 12:14:53.724815 DQS Delay:
7627 12:14:53.727062 DQS0 = 0, DQS1 = 0
7628 12:14:53.727488 DQM Delay:
7629 12:14:53.730671 DQM0 = 131, DQM1 = 127
7630 12:14:53.731098 DQ Delay:
7631 12:14:53.733770 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7632 12:14:53.737377 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7633 12:14:53.740448 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7634 12:14:53.743422 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7635 12:14:53.743850
7636 12:14:53.746863
7637 12:14:53.747285 ==
7638 12:14:53.750458 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 12:14:53.753490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 12:14:53.753924 ==
7641 12:14:53.754265
7642 12:14:53.754582
7643 12:14:53.756497 TX Vref Scan disable
7644 12:14:53.757002 == TX Byte 0 ==
7645 12:14:53.763094 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7646 12:14:53.766541 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7647 12:14:53.766970 == TX Byte 1 ==
7648 12:14:53.773100 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7649 12:14:53.776747 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7650 12:14:53.777178 ==
7651 12:14:53.779667 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 12:14:53.783319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 12:14:53.783755 ==
7654 12:14:53.797684
7655 12:14:53.801063 TX Vref early break, caculate TX vref
7656 12:14:53.804535 TX Vref=16, minBit 1, minWin=22, winSum=363
7657 12:14:53.808232 TX Vref=18, minBit 0, minWin=22, winSum=373
7658 12:14:53.811183 TX Vref=20, minBit 7, minWin=22, winSum=385
7659 12:14:53.814723 TX Vref=22, minBit 1, minWin=23, winSum=397
7660 12:14:53.817792 TX Vref=24, minBit 1, minWin=24, winSum=407
7661 12:14:53.824307 TX Vref=26, minBit 1, minWin=24, winSum=410
7662 12:14:53.827831 TX Vref=28, minBit 4, minWin=24, winSum=417
7663 12:14:53.831382 TX Vref=30, minBit 1, minWin=24, winSum=412
7664 12:14:53.834094 TX Vref=32, minBit 4, minWin=23, winSum=401
7665 12:14:53.837394 TX Vref=34, minBit 4, minWin=23, winSum=393
7666 12:14:53.844276 [TxChooseVref] Worse bit 4, Min win 24, Win sum 417, Final Vref 28
7667 12:14:53.844785
7668 12:14:53.847050 Final TX Range 0 Vref 28
7669 12:14:53.847675
7670 12:14:53.848251 ==
7671 12:14:53.850536 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 12:14:53.854333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 12:14:53.854769 ==
7674 12:14:53.855122
7675 12:14:53.855460
7676 12:14:53.857212 TX Vref Scan disable
7677 12:14:53.863988 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7678 12:14:53.864501 == TX Byte 0 ==
7679 12:14:53.866851 u2DelayCellOfst[0]=10 cells (3 PI)
7680 12:14:53.870308 u2DelayCellOfst[1]=14 cells (4 PI)
7681 12:14:53.873779 u2DelayCellOfst[2]=10 cells (3 PI)
7682 12:14:53.876676 u2DelayCellOfst[3]=10 cells (3 PI)
7683 12:14:53.880507 u2DelayCellOfst[4]=7 cells (2 PI)
7684 12:14:53.883527 u2DelayCellOfst[5]=0 cells (0 PI)
7685 12:14:53.887081 u2DelayCellOfst[6]=18 cells (5 PI)
7686 12:14:53.889913 u2DelayCellOfst[7]=18 cells (5 PI)
7687 12:14:53.893554 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7688 12:14:53.897094 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7689 12:14:53.899921 == TX Byte 1 ==
7690 12:14:53.903581 u2DelayCellOfst[8]=0 cells (0 PI)
7691 12:14:53.906268 u2DelayCellOfst[9]=0 cells (0 PI)
7692 12:14:53.909427 u2DelayCellOfst[10]=7 cells (2 PI)
7693 12:14:53.909511 u2DelayCellOfst[11]=3 cells (1 PI)
7694 12:14:53.913093 u2DelayCellOfst[12]=10 cells (3 PI)
7695 12:14:53.916263 u2DelayCellOfst[13]=10 cells (3 PI)
7696 12:14:53.919480 u2DelayCellOfst[14]=14 cells (4 PI)
7697 12:14:53.922946 u2DelayCellOfst[15]=10 cells (3 PI)
7698 12:14:53.929677 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7699 12:14:53.932527 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7700 12:14:53.932610 DramC Write-DBI on
7701 12:14:53.936340 ==
7702 12:14:53.939249 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 12:14:53.942285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 12:14:53.942378 ==
7705 12:14:53.942450
7706 12:14:53.942516
7707 12:14:53.945894 TX Vref Scan disable
7708 12:14:53.946010 == TX Byte 0 ==
7709 12:14:53.952309 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7710 12:14:53.952414 == TX Byte 1 ==
7711 12:14:53.955686 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7712 12:14:53.959065 DramC Write-DBI off
7713 12:14:53.959179
7714 12:14:53.959270 [DATLAT]
7715 12:14:53.962210 Freq=1600, CH0 RK0
7716 12:14:53.962335
7717 12:14:53.962434 DATLAT Default: 0xf
7718 12:14:53.965771 0, 0xFFFF, sum = 0
7719 12:14:53.965915 1, 0xFFFF, sum = 0
7720 12:14:53.968943 2, 0xFFFF, sum = 0
7721 12:14:53.971925 3, 0xFFFF, sum = 0
7722 12:14:53.972095 4, 0xFFFF, sum = 0
7723 12:14:53.975472 5, 0xFFFF, sum = 0
7724 12:14:53.975564 6, 0xFFFF, sum = 0
7725 12:14:53.978742 7, 0xFFFF, sum = 0
7726 12:14:53.978828 8, 0xFFFF, sum = 0
7727 12:14:53.981956 9, 0xFFFF, sum = 0
7728 12:14:53.982071 10, 0xFFFF, sum = 0
7729 12:14:53.985358 11, 0xFFFF, sum = 0
7730 12:14:53.985444 12, 0xFFFF, sum = 0
7731 12:14:53.988949 13, 0xFFFF, sum = 0
7732 12:14:53.989033 14, 0x0, sum = 1
7733 12:14:53.991914 15, 0x0, sum = 2
7734 12:14:53.992006 16, 0x0, sum = 3
7735 12:14:53.994887 17, 0x0, sum = 4
7736 12:14:53.994972 best_step = 15
7737 12:14:53.995038
7738 12:14:53.995099 ==
7739 12:14:53.998442 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 12:14:54.004880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 12:14:54.004981 ==
7742 12:14:54.005080 RX Vref Scan: 1
7743 12:14:54.005174
7744 12:14:54.007995 Set Vref Range= 24 -> 127
7745 12:14:54.008113
7746 12:14:54.011624 RX Vref 24 -> 127, step: 1
7747 12:14:54.011730
7748 12:14:54.011837 RX Delay 11 -> 252, step: 4
7749 12:14:54.011963
7750 12:14:54.015269 Set Vref, RX VrefLevel [Byte0]: 24
7751 12:14:54.018407 [Byte1]: 24
7752 12:14:54.022839
7753 12:14:54.023019 Set Vref, RX VrefLevel [Byte0]: 25
7754 12:14:54.025842 [Byte1]: 25
7755 12:14:54.029881
7756 12:14:54.030033 Set Vref, RX VrefLevel [Byte0]: 26
7757 12:14:54.033595 [Byte1]: 26
7758 12:14:54.037999
7759 12:14:54.038201 Set Vref, RX VrefLevel [Byte0]: 27
7760 12:14:54.040762 [Byte1]: 27
7761 12:14:54.045176
7762 12:14:54.045520 Set Vref, RX VrefLevel [Byte0]: 28
7763 12:14:54.048949 [Byte1]: 28
7764 12:14:54.053082
7765 12:14:54.053488 Set Vref, RX VrefLevel [Byte0]: 29
7766 12:14:54.056668 [Byte1]: 29
7767 12:14:54.061351
7768 12:14:54.061775 Set Vref, RX VrefLevel [Byte0]: 30
7769 12:14:54.063996 [Byte1]: 30
7770 12:14:54.068125
7771 12:14:54.068551 Set Vref, RX VrefLevel [Byte0]: 31
7772 12:14:54.071717 [Byte1]: 31
7773 12:14:54.075949
7774 12:14:54.076433 Set Vref, RX VrefLevel [Byte0]: 32
7775 12:14:54.079471 [Byte1]: 32
7776 12:14:54.083489
7777 12:14:54.083911 Set Vref, RX VrefLevel [Byte0]: 33
7778 12:14:54.086980 [Byte1]: 33
7779 12:14:54.091146
7780 12:14:54.091565 Set Vref, RX VrefLevel [Byte0]: 34
7781 12:14:54.094145 [Byte1]: 34
7782 12:14:54.098985
7783 12:14:54.099403 Set Vref, RX VrefLevel [Byte0]: 35
7784 12:14:54.101990 [Byte1]: 35
7785 12:14:54.106172
7786 12:14:54.106592 Set Vref, RX VrefLevel [Byte0]: 36
7787 12:14:54.109448 [Byte1]: 36
7788 12:14:54.113780
7789 12:14:54.114200 Set Vref, RX VrefLevel [Byte0]: 37
7790 12:14:54.117382 [Byte1]: 37
7791 12:14:54.121611
7792 12:14:54.122103 Set Vref, RX VrefLevel [Byte0]: 38
7793 12:14:54.125033 [Byte1]: 38
7794 12:14:54.129321
7795 12:14:54.129742 Set Vref, RX VrefLevel [Byte0]: 39
7796 12:14:54.132434 [Byte1]: 39
7797 12:14:54.137117
7798 12:14:54.137555 Set Vref, RX VrefLevel [Byte0]: 40
7799 12:14:54.140020 [Byte1]: 40
7800 12:14:54.144205
7801 12:14:54.144653 Set Vref, RX VrefLevel [Byte0]: 41
7802 12:14:54.147850 [Byte1]: 41
7803 12:14:54.151987
7804 12:14:54.152470 Set Vref, RX VrefLevel [Byte0]: 42
7805 12:14:54.155083 [Byte1]: 42
7806 12:14:54.159697
7807 12:14:54.160302 Set Vref, RX VrefLevel [Byte0]: 43
7808 12:14:54.163084 [Byte1]: 43
7809 12:14:54.167409
7810 12:14:54.167829 Set Vref, RX VrefLevel [Byte0]: 44
7811 12:14:54.170764 [Byte1]: 44
7812 12:14:54.175189
7813 12:14:54.175621 Set Vref, RX VrefLevel [Byte0]: 45
7814 12:14:54.178035 [Byte1]: 45
7815 12:14:54.182271
7816 12:14:54.182695 Set Vref, RX VrefLevel [Byte0]: 46
7817 12:14:54.185620 [Byte1]: 46
7818 12:14:54.190416
7819 12:14:54.190837 Set Vref, RX VrefLevel [Byte0]: 47
7820 12:14:54.193473 [Byte1]: 47
7821 12:14:54.198219
7822 12:14:54.198657 Set Vref, RX VrefLevel [Byte0]: 48
7823 12:14:54.201330 [Byte1]: 48
7824 12:14:54.205265
7825 12:14:54.205735 Set Vref, RX VrefLevel [Byte0]: 49
7826 12:14:54.208802 [Byte1]: 49
7827 12:14:54.212711
7828 12:14:54.213135 Set Vref, RX VrefLevel [Byte0]: 50
7829 12:14:54.216343 [Byte1]: 50
7830 12:14:54.220877
7831 12:14:54.221380 Set Vref, RX VrefLevel [Byte0]: 51
7832 12:14:54.223656 [Byte1]: 51
7833 12:14:54.227926
7834 12:14:54.228388 Set Vref, RX VrefLevel [Byte0]: 52
7835 12:14:54.231384 [Byte1]: 52
7836 12:14:54.235598
7837 12:14:54.236203 Set Vref, RX VrefLevel [Byte0]: 53
7838 12:14:54.239230 [Byte1]: 53
7839 12:14:54.243604
7840 12:14:54.244211 Set Vref, RX VrefLevel [Byte0]: 54
7841 12:14:54.246670 [Byte1]: 54
7842 12:14:54.250831
7843 12:14:54.251323 Set Vref, RX VrefLevel [Byte0]: 55
7844 12:14:54.254591 [Byte1]: 55
7845 12:14:54.258758
7846 12:14:54.259223 Set Vref, RX VrefLevel [Byte0]: 56
7847 12:14:54.261795 [Byte1]: 56
7848 12:14:54.266098
7849 12:14:54.266559 Set Vref, RX VrefLevel [Byte0]: 57
7850 12:14:54.269569 [Byte1]: 57
7851 12:14:54.273778
7852 12:14:54.274279 Set Vref, RX VrefLevel [Byte0]: 58
7853 12:14:54.277419 [Byte1]: 58
7854 12:14:54.281565
7855 12:14:54.281986 Set Vref, RX VrefLevel [Byte0]: 59
7856 12:14:54.284517 [Byte1]: 59
7857 12:14:54.289301
7858 12:14:54.289813 Set Vref, RX VrefLevel [Byte0]: 60
7859 12:14:54.292671 [Byte1]: 60
7860 12:14:54.296879
7861 12:14:54.297359 Set Vref, RX VrefLevel [Byte0]: 61
7862 12:14:54.299783 [Byte1]: 61
7863 12:14:54.303956
7864 12:14:54.304531 Set Vref, RX VrefLevel [Byte0]: 62
7865 12:14:54.307500 [Byte1]: 62
7866 12:14:54.311791
7867 12:14:54.312375 Set Vref, RX VrefLevel [Byte0]: 63
7868 12:14:54.315242 [Byte1]: 63
7869 12:14:54.319488
7870 12:14:54.319916 Set Vref, RX VrefLevel [Byte0]: 64
7871 12:14:54.322875 [Byte1]: 64
7872 12:14:54.327069
7873 12:14:54.327498 Set Vref, RX VrefLevel [Byte0]: 65
7874 12:14:54.330174 [Byte1]: 65
7875 12:14:54.334996
7876 12:14:54.335424 Set Vref, RX VrefLevel [Byte0]: 66
7877 12:14:54.337869 [Byte1]: 66
7878 12:14:54.342160
7879 12:14:54.342661 Set Vref, RX VrefLevel [Byte0]: 67
7880 12:14:54.345861 [Byte1]: 67
7881 12:14:54.350058
7882 12:14:54.350667 Set Vref, RX VrefLevel [Byte0]: 68
7883 12:14:54.353599 [Byte1]: 68
7884 12:14:54.357292
7885 12:14:54.357733 Set Vref, RX VrefLevel [Byte0]: 69
7886 12:14:54.360731 [Byte1]: 69
7887 12:14:54.364916
7888 12:14:54.365335 Set Vref, RX VrefLevel [Byte0]: 70
7889 12:14:54.368496 [Byte1]: 70
7890 12:14:54.372640
7891 12:14:54.373065 Set Vref, RX VrefLevel [Byte0]: 71
7892 12:14:54.375826 [Byte1]: 71
7893 12:14:54.380532
7894 12:14:54.381215 Set Vref, RX VrefLevel [Byte0]: 72
7895 12:14:54.383383 [Byte1]: 72
7896 12:14:54.388289
7897 12:14:54.388988 Final RX Vref Byte 0 = 56 to rank0
7898 12:14:54.391179 Final RX Vref Byte 1 = 58 to rank0
7899 12:14:54.394698 Final RX Vref Byte 0 = 56 to rank1
7900 12:14:54.398129 Final RX Vref Byte 1 = 58 to rank1==
7901 12:14:54.400994 Dram Type= 6, Freq= 0, CH_0, rank 0
7902 12:14:54.407807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7903 12:14:54.408290 ==
7904 12:14:54.408640 DQS Delay:
7905 12:14:54.411416 DQS0 = 0, DQS1 = 0
7906 12:14:54.411843 DQM Delay:
7907 12:14:54.412472 DQM0 = 128, DQM1 = 123
7908 12:14:54.414131 DQ Delay:
7909 12:14:54.417641 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7910 12:14:54.420737 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7911 12:14:54.424134 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7912 12:14:54.427634 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7913 12:14:54.428326
7914 12:14:54.428751
7915 12:14:54.429080
7916 12:14:54.430677 [DramC_TX_OE_Calibration] TA2
7917 12:14:54.434099 Original DQ_B0 (3 6) =30, OEN = 27
7918 12:14:54.437226 Original DQ_B1 (3 6) =30, OEN = 27
7919 12:14:54.441019 24, 0x0, End_B0=24 End_B1=24
7920 12:14:54.443793 25, 0x0, End_B0=25 End_B1=25
7921 12:14:54.444312 26, 0x0, End_B0=26 End_B1=26
7922 12:14:54.447250 27, 0x0, End_B0=27 End_B1=27
7923 12:14:54.450303 28, 0x0, End_B0=28 End_B1=28
7924 12:14:54.453810 29, 0x0, End_B0=29 End_B1=29
7925 12:14:54.454120 30, 0x0, End_B0=30 End_B1=30
7926 12:14:54.456775 31, 0x4141, End_B0=30 End_B1=30
7927 12:14:54.460376 Byte0 end_step=30 best_step=27
7928 12:14:54.463518 Byte1 end_step=30 best_step=27
7929 12:14:54.466722 Byte0 TX OE(2T, 0.5T) = (3, 3)
7930 12:14:54.469645 Byte1 TX OE(2T, 0.5T) = (3, 3)
7931 12:14:54.469730
7932 12:14:54.469797
7933 12:14:54.476727 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7934 12:14:54.479710 CH0 RK0: MR19=303, MR18=1613
7935 12:14:54.485993 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
7936 12:14:54.486080
7937 12:14:54.489684 ----->DramcWriteLeveling(PI) begin...
7938 12:14:54.489776 ==
7939 12:14:54.492602 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 12:14:54.496085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 12:14:54.496189 ==
7942 12:14:54.499554 Write leveling (Byte 0): 34 => 34
7943 12:14:54.503064 Write leveling (Byte 1): 25 => 25
7944 12:14:54.506172 DramcWriteLeveling(PI) end<-----
7945 12:14:54.506287
7946 12:14:54.506378 ==
7947 12:14:54.509081 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 12:14:54.515842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 12:14:54.515987 ==
7950 12:14:54.516121 [Gating] SW mode calibration
7951 12:14:54.525893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7952 12:14:54.529308 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7953 12:14:54.535871 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7954 12:14:54.538573 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7955 12:14:54.542251 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7956 12:14:54.548371 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7957 12:14:54.551929 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7958 12:14:54.555070 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7959 12:14:54.561719 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7960 12:14:54.565186 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 12:14:54.568323 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7962 12:14:54.575015 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7963 12:14:54.578085 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7964 12:14:54.581726 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7965 12:14:54.588319 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7966 12:14:54.591307 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7967 12:14:54.594467 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 12:14:54.601242 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 12:14:54.604715 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 12:14:54.607483 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 12:14:54.614309 1 6 8 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7972 12:14:54.617951 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7973 12:14:54.620923 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7974 12:14:54.627789 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 12:14:54.630798 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 12:14:54.634392 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 12:14:54.640986 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 12:14:54.644372 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7979 12:14:54.647912 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7980 12:14:54.654020 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7981 12:14:54.657514 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7982 12:14:54.660481 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 12:14:54.667142 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7984 12:14:54.670753 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 12:14:54.673769 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 12:14:54.680353 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 12:14:54.683468 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 12:14:54.687061 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 12:14:54.693657 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 12:14:54.696496 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 12:14:54.700354 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 12:14:54.706830 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 12:14:54.709748 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 12:14:54.713201 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7995 12:14:54.720062 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7996 12:14:54.723036 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7997 12:14:54.726645 Total UI for P1: 0, mck2ui 16
7998 12:14:54.729566 best dqsien dly found for B0: ( 1, 9, 6)
7999 12:14:54.732841 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8000 12:14:54.739745 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8001 12:14:54.742785 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 12:14:54.746391 Total UI for P1: 0, mck2ui 16
8003 12:14:54.749818 best dqsien dly found for B1: ( 1, 9, 18)
8004 12:14:54.752619 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8005 12:14:54.756287 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8006 12:14:54.756716
8007 12:14:54.759346 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8008 12:14:54.766110 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8009 12:14:54.766707 [Gating] SW calibration Done
8010 12:14:54.767272 ==
8011 12:14:54.769578 Dram Type= 6, Freq= 0, CH_0, rank 1
8012 12:14:54.776190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8013 12:14:54.776640 ==
8014 12:14:54.776982 RX Vref Scan: 0
8015 12:14:54.777295
8016 12:14:54.779025 RX Vref 0 -> 0, step: 1
8017 12:14:54.779450
8018 12:14:54.782797 RX Delay 0 -> 252, step: 8
8019 12:14:54.785685 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8020 12:14:54.788880 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8021 12:14:54.792494 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8022 12:14:54.799025 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8023 12:14:54.801940 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8024 12:14:54.805554 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8025 12:14:54.808735 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8026 12:14:54.812112 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8027 12:14:54.818630 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8028 12:14:54.821640 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8029 12:14:54.825341 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8030 12:14:54.828525 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8031 12:14:54.831904 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8032 12:14:54.838296 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8033 12:14:54.841686 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8034 12:14:54.845097 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8035 12:14:54.845695 ==
8036 12:14:54.847965 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 12:14:54.854347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 12:14:54.854890 ==
8039 12:14:54.855368 DQS Delay:
8040 12:14:54.855879 DQS0 = 0, DQS1 = 0
8041 12:14:54.857665 DQM Delay:
8042 12:14:54.858101 DQM0 = 130, DQM1 = 127
8043 12:14:54.861238 DQ Delay:
8044 12:14:54.864148 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
8045 12:14:54.867847 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8046 12:14:54.870805 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
8047 12:14:54.874297 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8048 12:14:54.874760
8049 12:14:54.875277
8050 12:14:54.875697 ==
8051 12:14:54.877286 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 12:14:54.883797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 12:14:54.884355 ==
8054 12:14:54.884703
8055 12:14:54.885014
8056 12:14:54.885318 TX Vref Scan disable
8057 12:14:54.887369 == TX Byte 0 ==
8058 12:14:54.890614 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8059 12:14:54.897450 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8060 12:14:54.898001 == TX Byte 1 ==
8061 12:14:54.900379 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8062 12:14:54.907141 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8063 12:14:54.907847 ==
8064 12:14:54.910738 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 12:14:54.913531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 12:14:54.913963 ==
8067 12:14:54.927373
8068 12:14:54.930358 TX Vref early break, caculate TX vref
8069 12:14:54.933987 TX Vref=16, minBit 0, minWin=22, winSum=372
8070 12:14:54.936780 TX Vref=18, minBit 3, minWin=23, winSum=384
8071 12:14:54.940299 TX Vref=20, minBit 0, minWin=23, winSum=390
8072 12:14:54.943804 TX Vref=22, minBit 0, minWin=24, winSum=395
8073 12:14:54.946516 TX Vref=24, minBit 3, minWin=24, winSum=408
8074 12:14:54.953707 TX Vref=26, minBit 1, minWin=25, winSum=410
8075 12:14:54.956735 TX Vref=28, minBit 0, minWin=25, winSum=413
8076 12:14:54.959832 TX Vref=30, minBit 8, minWin=24, winSum=407
8077 12:14:54.963112 TX Vref=32, minBit 4, minWin=23, winSum=397
8078 12:14:54.966717 TX Vref=34, minBit 3, minWin=23, winSum=387
8079 12:14:54.973424 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8080 12:14:54.973853
8081 12:14:54.976279 Final TX Range 0 Vref 28
8082 12:14:54.976733
8083 12:14:54.977102 ==
8084 12:14:54.979774 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 12:14:54.983168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 12:14:54.983596 ==
8087 12:14:54.983932
8088 12:14:54.984288
8089 12:14:54.986183 TX Vref Scan disable
8090 12:14:54.992847 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8091 12:14:54.993271 == TX Byte 0 ==
8092 12:14:54.996125 u2DelayCellOfst[0]=14 cells (4 PI)
8093 12:14:54.999471 u2DelayCellOfst[1]=18 cells (5 PI)
8094 12:14:55.002603 u2DelayCellOfst[2]=10 cells (3 PI)
8095 12:14:55.006080 u2DelayCellOfst[3]=14 cells (4 PI)
8096 12:14:55.009113 u2DelayCellOfst[4]=10 cells (3 PI)
8097 12:14:55.012688 u2DelayCellOfst[5]=0 cells (0 PI)
8098 12:14:55.015655 u2DelayCellOfst[6]=18 cells (5 PI)
8099 12:14:55.019205 u2DelayCellOfst[7]=18 cells (5 PI)
8100 12:14:55.022252 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8101 12:14:55.025569 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8102 12:14:55.029297 == TX Byte 1 ==
8103 12:14:55.032381 u2DelayCellOfst[8]=0 cells (0 PI)
8104 12:14:55.035363 u2DelayCellOfst[9]=0 cells (0 PI)
8105 12:14:55.038821 u2DelayCellOfst[10]=7 cells (2 PI)
8106 12:14:55.042370 u2DelayCellOfst[11]=0 cells (0 PI)
8107 12:14:55.045206 u2DelayCellOfst[12]=7 cells (2 PI)
8108 12:14:55.048708 u2DelayCellOfst[13]=10 cells (3 PI)
8109 12:14:55.051794 u2DelayCellOfst[14]=14 cells (4 PI)
8110 12:14:55.052352 u2DelayCellOfst[15]=10 cells (3 PI)
8111 12:14:55.058672 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8112 12:14:55.061426 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8113 12:14:55.064944 DramC Write-DBI on
8114 12:14:55.065027 ==
8115 12:14:55.068285 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:14:55.071387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:14:55.071470 ==
8118 12:14:55.071534
8119 12:14:55.071593
8120 12:14:55.075068 TX Vref Scan disable
8121 12:14:55.078135 == TX Byte 0 ==
8122 12:14:55.081069 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8123 12:14:55.081152 == TX Byte 1 ==
8124 12:14:55.087746 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8125 12:14:55.087842 DramC Write-DBI off
8126 12:14:55.087913
8127 12:14:55.087978 [DATLAT]
8128 12:14:55.091583 Freq=1600, CH0 RK1
8129 12:14:55.092201
8130 12:14:55.094699 DATLAT Default: 0xf
8131 12:14:55.095200 0, 0xFFFF, sum = 0
8132 12:14:55.098392 1, 0xFFFF, sum = 0
8133 12:14:55.098830 2, 0xFFFF, sum = 0
8134 12:14:55.101406 3, 0xFFFF, sum = 0
8135 12:14:55.101835 4, 0xFFFF, sum = 0
8136 12:14:55.105081 5, 0xFFFF, sum = 0
8137 12:14:55.105515 6, 0xFFFF, sum = 0
8138 12:14:55.107858 7, 0xFFFF, sum = 0
8139 12:14:55.108489 8, 0xFFFF, sum = 0
8140 12:14:55.111413 9, 0xFFFF, sum = 0
8141 12:14:55.111844 10, 0xFFFF, sum = 0
8142 12:14:55.114270 11, 0xFFFF, sum = 0
8143 12:14:55.114710 12, 0xFFFF, sum = 0
8144 12:14:55.117420 13, 0xFFFF, sum = 0
8145 12:14:55.117504 14, 0x0, sum = 1
8146 12:14:55.120642 15, 0x0, sum = 2
8147 12:14:55.120726 16, 0x0, sum = 3
8148 12:14:55.124183 17, 0x0, sum = 4
8149 12:14:55.124267 best_step = 15
8150 12:14:55.124332
8151 12:14:55.124391 ==
8152 12:14:55.127298 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:14:55.133649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:14:55.133733 ==
8155 12:14:55.133797 RX Vref Scan: 0
8156 12:14:55.133891
8157 12:14:55.137360 RX Vref 0 -> 0, step: 1
8158 12:14:55.137442
8159 12:14:55.140299 RX Delay 11 -> 252, step: 4
8160 12:14:55.143935 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8161 12:14:55.147028 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8162 12:14:55.153878 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8163 12:14:55.156801 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8164 12:14:55.160197 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8165 12:14:55.163721 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8166 12:14:55.167122 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8167 12:14:55.173391 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8168 12:14:55.176995 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8169 12:14:55.180255 iDelay=191, Bit 9, Center 108 (55 ~ 162) 108
8170 12:14:55.183451 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8171 12:14:55.187194 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8172 12:14:55.193449 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8173 12:14:55.196655 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8174 12:14:55.200153 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8175 12:14:55.203432 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8176 12:14:55.203544 ==
8177 12:14:55.206492 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 12:14:55.213206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 12:14:55.213346 ==
8180 12:14:55.213456 DQS Delay:
8181 12:14:55.216901 DQS0 = 0, DQS1 = 0
8182 12:14:55.217041 DQM Delay:
8183 12:14:55.219647 DQM0 = 128, DQM1 = 123
8184 12:14:55.219799 DQ Delay:
8185 12:14:55.223173 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8186 12:14:55.226159 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8187 12:14:55.229817 DQ8 =114, DQ9 =108, DQ10 =126, DQ11 =118
8188 12:14:55.233294 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8189 12:14:55.233530
8190 12:14:55.233720
8191 12:14:55.233915
8192 12:14:55.236018 [DramC_TX_OE_Calibration] TA2
8193 12:14:55.239840 Original DQ_B0 (3 6) =30, OEN = 27
8194 12:14:55.243171 Original DQ_B1 (3 6) =30, OEN = 27
8195 12:14:55.246282 24, 0x0, End_B0=24 End_B1=24
8196 12:14:55.249746 25, 0x0, End_B0=25 End_B1=25
8197 12:14:55.250177 26, 0x0, End_B0=26 End_B1=26
8198 12:14:55.253273 27, 0x0, End_B0=27 End_B1=27
8199 12:14:55.256104 28, 0x0, End_B0=28 End_B1=28
8200 12:14:55.259750 29, 0x0, End_B0=29 End_B1=29
8201 12:14:55.260213 30, 0x0, End_B0=30 End_B1=30
8202 12:14:55.262707 31, 0x4141, End_B0=30 End_B1=30
8203 12:14:55.266031 Byte0 end_step=30 best_step=27
8204 12:14:55.269323 Byte1 end_step=30 best_step=27
8205 12:14:55.272886 Byte0 TX OE(2T, 0.5T) = (3, 3)
8206 12:14:55.276349 Byte1 TX OE(2T, 0.5T) = (3, 3)
8207 12:14:55.276772
8208 12:14:55.277105
8209 12:14:55.282905 [DQSOSCAuto] RK1, (LSB)MR18= 0x100f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8210 12:14:55.285903 CH0 RK1: MR19=303, MR18=100F
8211 12:14:55.292388 CH0_RK1: MR19=0x303, MR18=0x100F, DQSOSC=401, MR23=63, INC=22, DEC=15
8212 12:14:55.296014 [RxdqsGatingPostProcess] freq 1600
8213 12:14:55.302273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8214 12:14:55.305752 best DQS0 dly(2T, 0.5T) = (1, 1)
8215 12:14:55.306198 best DQS1 dly(2T, 0.5T) = (1, 1)
8216 12:14:55.308703 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8217 12:14:55.312265 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8218 12:14:55.315350 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 12:14:55.318996 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 12:14:55.321746 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 12:14:55.325067 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 12:14:55.328725 Pre-setting of DQS Precalculation
8223 12:14:55.331635 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8224 12:14:55.335409 ==
8225 12:14:55.338276 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 12:14:55.341731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 12:14:55.341834 ==
8228 12:14:55.344844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8229 12:14:55.351556 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8230 12:14:55.355017 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8231 12:14:55.361523 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8232 12:14:55.370061 [CA 0] Center 41 (11~72) winsize 62
8233 12:14:55.373562 [CA 1] Center 42 (12~72) winsize 61
8234 12:14:55.376420 [CA 2] Center 38 (9~67) winsize 59
8235 12:14:55.379874 [CA 3] Center 37 (8~66) winsize 59
8236 12:14:55.383453 [CA 4] Center 37 (7~68) winsize 62
8237 12:14:55.386428 [CA 5] Center 36 (7~66) winsize 60
8238 12:14:55.386859
8239 12:14:55.389874 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8240 12:14:55.390309
8241 12:14:55.392997 [CATrainingPosCal] consider 1 rank data
8242 12:14:55.396529 u2DelayCellTimex100 = 271/100 ps
8243 12:14:55.403398 CA0 delay=41 (11~72),Diff = 5 PI (18 cell)
8244 12:14:55.406231 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8245 12:14:55.409983 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8246 12:14:55.413052 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8247 12:14:55.415921 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8248 12:14:55.419733 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8249 12:14:55.420201
8250 12:14:55.422726 CA PerBit enable=1, Macro0, CA PI delay=36
8251 12:14:55.423156
8252 12:14:55.426226 [CBTSetCACLKResult] CA Dly = 36
8253 12:14:55.429302 CS Dly: 8 (0~39)
8254 12:14:55.432125 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8255 12:14:55.436028 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8256 12:14:55.436499 ==
8257 12:14:55.438861 Dram Type= 6, Freq= 0, CH_1, rank 1
8258 12:14:55.445346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 12:14:55.445780 ==
8260 12:14:55.448876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8261 12:14:55.455540 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8262 12:14:55.458447 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8263 12:14:55.464986 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8264 12:14:55.473289 [CA 0] Center 42 (12~72) winsize 61
8265 12:14:55.476611 [CA 1] Center 43 (14~72) winsize 59
8266 12:14:55.479275 [CA 2] Center 38 (9~68) winsize 60
8267 12:14:55.482920 [CA 3] Center 37 (8~66) winsize 59
8268 12:14:55.486465 [CA 4] Center 37 (7~67) winsize 61
8269 12:14:55.489260 [CA 5] Center 37 (8~67) winsize 60
8270 12:14:55.489826
8271 12:14:55.492772 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8272 12:14:55.493195
8273 12:14:55.499479 [CATrainingPosCal] consider 2 rank data
8274 12:14:55.499898 u2DelayCellTimex100 = 271/100 ps
8275 12:14:55.506121 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8276 12:14:55.509371 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8277 12:14:55.512431 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8278 12:14:55.515620 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8279 12:14:55.519066 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8280 12:14:55.522153 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8281 12:14:55.522732
8282 12:14:55.525679 CA PerBit enable=1, Macro0, CA PI delay=37
8283 12:14:55.526263
8284 12:14:55.528638 [CBTSetCACLKResult] CA Dly = 37
8285 12:14:55.532125 CS Dly: 9 (0~42)
8286 12:14:55.535703 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8287 12:14:55.538812 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8288 12:14:55.539246
8289 12:14:55.541932 ----->DramcWriteLeveling(PI) begin...
8290 12:14:55.542368 ==
8291 12:14:55.545555 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 12:14:55.551698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 12:14:55.552170 ==
8294 12:14:55.555443 Write leveling (Byte 0): 27 => 27
8295 12:14:55.558615 Write leveling (Byte 1): 27 => 27
8296 12:14:55.561596 DramcWriteLeveling(PI) end<-----
8297 12:14:55.562025
8298 12:14:55.562368 ==
8299 12:14:55.564988 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 12:14:55.568500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 12:14:55.569237 ==
8302 12:14:55.571889 [Gating] SW mode calibration
8303 12:14:55.577892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8304 12:14:55.584943 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8305 12:14:55.587718 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 12:14:55.591196 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 12:14:55.597498 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 12:14:55.601014 1 4 12 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
8309 12:14:55.604046 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 12:14:55.611085 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 12:14:55.614134 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 12:14:55.617784 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 12:14:55.624421 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 12:14:55.627509 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 12:14:55.630996 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8316 12:14:55.637703 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
8317 12:14:55.640537 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8318 12:14:55.644295 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 12:14:55.650303 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 12:14:55.653882 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 12:14:55.656973 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 12:14:55.663652 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 12:14:55.667309 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8324 12:14:55.670288 1 6 12 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
8325 12:14:55.676465 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 12:14:55.680286 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 12:14:55.683296 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 12:14:55.689930 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 12:14:55.693102 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 12:14:55.696534 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 12:14:55.703283 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 12:14:55.706528 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8333 12:14:55.709630 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8334 12:14:55.716167 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 12:14:55.719819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 12:14:55.722730 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 12:14:55.729465 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 12:14:55.732600 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 12:14:55.736185 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 12:14:55.742868 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 12:14:55.745780 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 12:14:55.749507 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 12:14:55.755378 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 12:14:55.758926 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 12:14:55.762421 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 12:14:55.769008 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 12:14:55.772008 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8348 12:14:55.775494 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8349 12:14:55.781891 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8350 12:14:55.782322 Total UI for P1: 0, mck2ui 16
8351 12:14:55.788353 best dqsien dly found for B0: ( 1, 9, 10)
8352 12:14:55.791881 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 12:14:55.795282 Total UI for P1: 0, mck2ui 16
8354 12:14:55.798864 best dqsien dly found for B1: ( 1, 9, 14)
8355 12:14:55.801779 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8356 12:14:55.805413 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8357 12:14:55.805833
8358 12:14:55.808973 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8359 12:14:55.812063 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8360 12:14:55.814989 [Gating] SW calibration Done
8361 12:14:55.815403 ==
8362 12:14:55.818578 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 12:14:55.824689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 12:14:55.825166 ==
8365 12:14:55.825673 RX Vref Scan: 0
8366 12:14:55.826075
8367 12:14:55.828400 RX Vref 0 -> 0, step: 1
8368 12:14:55.828822
8369 12:14:55.831564 RX Delay 0 -> 252, step: 8
8370 12:14:55.834842 iDelay=200, Bit 0, Center 147 (96 ~ 199) 104
8371 12:14:55.838029 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8372 12:14:55.841143 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8373 12:14:55.847959 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8374 12:14:55.851022 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8375 12:14:55.854489 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8376 12:14:55.857575 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8377 12:14:55.861389 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8378 12:14:55.867772 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8379 12:14:55.871373 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8380 12:14:55.874567 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8381 12:14:55.877528 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8382 12:14:55.881034 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8383 12:14:55.887340 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8384 12:14:55.890903 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8385 12:14:55.894165 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8386 12:14:55.894658 ==
8387 12:14:55.897562 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 12:14:55.900961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 12:14:55.904085 ==
8390 12:14:55.904510 DQS Delay:
8391 12:14:55.904845 DQS0 = 0, DQS1 = 0
8392 12:14:55.906934 DQM Delay:
8393 12:14:55.907416 DQM0 = 136, DQM1 = 131
8394 12:14:55.910497 DQ Delay:
8395 12:14:55.913582 DQ0 =147, DQ1 =131, DQ2 =123, DQ3 =135
8396 12:14:55.917120 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8397 12:14:55.920372 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8398 12:14:55.923895 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8399 12:14:55.924448
8400 12:14:55.924824
8401 12:14:55.925157 ==
8402 12:14:55.926733 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 12:14:55.930375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 12:14:55.930849 ==
8405 12:14:55.933482
8406 12:14:55.933900
8407 12:14:55.934296 TX Vref Scan disable
8408 12:14:55.937131 == TX Byte 0 ==
8409 12:14:55.940098 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8410 12:14:55.943097 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8411 12:14:55.946724 == TX Byte 1 ==
8412 12:14:55.950223 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8413 12:14:55.953143 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8414 12:14:55.956542 ==
8415 12:14:55.956972 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 12:14:55.962812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 12:14:55.963244 ==
8418 12:14:55.974883
8419 12:14:55.978467 TX Vref early break, caculate TX vref
8420 12:14:55.981437 TX Vref=16, minBit 8, minWin=21, winSum=363
8421 12:14:55.984952 TX Vref=18, minBit 8, minWin=21, winSum=374
8422 12:14:55.988008 TX Vref=20, minBit 3, minWin=23, winSum=386
8423 12:14:55.990993 TX Vref=22, minBit 8, minWin=22, winSum=394
8424 12:14:55.994383 TX Vref=24, minBit 8, minWin=24, winSum=403
8425 12:14:56.000995 TX Vref=26, minBit 3, minWin=25, winSum=412
8426 12:14:56.004662 TX Vref=28, minBit 9, minWin=25, winSum=416
8427 12:14:56.007925 TX Vref=30, minBit 0, minWin=25, winSum=418
8428 12:14:56.010958 TX Vref=32, minBit 8, minWin=24, winSum=407
8429 12:14:56.014455 TX Vref=34, minBit 9, minWin=23, winSum=396
8430 12:14:56.020917 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 30
8431 12:14:56.021462
8432 12:14:56.024618 Final TX Range 0 Vref 30
8433 12:14:56.025062
8434 12:14:56.025510 ==
8435 12:14:56.027557 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 12:14:56.031171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 12:14:56.031747 ==
8438 12:14:56.032280
8439 12:14:56.032699
8440 12:14:56.034247 TX Vref Scan disable
8441 12:14:56.040738 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8442 12:14:56.041238 == TX Byte 0 ==
8443 12:14:56.043692 u2DelayCellOfst[0]=18 cells (5 PI)
8444 12:14:56.047305 u2DelayCellOfst[1]=10 cells (3 PI)
8445 12:14:56.050279 u2DelayCellOfst[2]=0 cells (0 PI)
8446 12:14:56.054021 u2DelayCellOfst[3]=7 cells (2 PI)
8447 12:14:56.057076 u2DelayCellOfst[4]=7 cells (2 PI)
8448 12:14:56.060552 u2DelayCellOfst[5]=18 cells (5 PI)
8449 12:14:56.064151 u2DelayCellOfst[6]=18 cells (5 PI)
8450 12:14:56.067214 u2DelayCellOfst[7]=7 cells (2 PI)
8451 12:14:56.070350 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8452 12:14:56.073952 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8453 12:14:56.076691 == TX Byte 1 ==
8454 12:14:56.080360 u2DelayCellOfst[8]=0 cells (0 PI)
8455 12:14:56.083409 u2DelayCellOfst[9]=7 cells (2 PI)
8456 12:14:56.087035 u2DelayCellOfst[10]=14 cells (4 PI)
8457 12:14:56.087456 u2DelayCellOfst[11]=7 cells (2 PI)
8458 12:14:56.090134 u2DelayCellOfst[12]=14 cells (4 PI)
8459 12:14:56.093681 u2DelayCellOfst[13]=18 cells (5 PI)
8460 12:14:56.096516 u2DelayCellOfst[14]=18 cells (5 PI)
8461 12:14:56.099929 u2DelayCellOfst[15]=18 cells (5 PI)
8462 12:14:56.106397 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8463 12:14:56.110059 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8464 12:14:56.110545 DramC Write-DBI on
8465 12:14:56.113376 ==
8466 12:14:56.116190 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 12:14:56.119924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 12:14:56.120549 ==
8469 12:14:56.121098
8470 12:14:56.121676
8471 12:14:56.122699 TX Vref Scan disable
8472 12:14:56.123257 == TX Byte 0 ==
8473 12:14:56.129252 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8474 12:14:56.129905 == TX Byte 1 ==
8475 12:14:56.132924 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8476 12:14:56.135904 DramC Write-DBI off
8477 12:14:56.136378
8478 12:14:56.136715 [DATLAT]
8479 12:14:56.139665 Freq=1600, CH1 RK0
8480 12:14:56.140136
8481 12:14:56.140518 DATLAT Default: 0xf
8482 12:14:56.142561 0, 0xFFFF, sum = 0
8483 12:14:56.143114 1, 0xFFFF, sum = 0
8484 12:14:56.146270 2, 0xFFFF, sum = 0
8485 12:14:56.146698 3, 0xFFFF, sum = 0
8486 12:14:56.149251 4, 0xFFFF, sum = 0
8487 12:14:56.152220 5, 0xFFFF, sum = 0
8488 12:14:56.152651 6, 0xFFFF, sum = 0
8489 12:14:56.155794 7, 0xFFFF, sum = 0
8490 12:14:56.156324 8, 0xFFFF, sum = 0
8491 12:14:56.158734 9, 0xFFFF, sum = 0
8492 12:14:56.159158 10, 0xFFFF, sum = 0
8493 12:14:56.162330 11, 0xFFFF, sum = 0
8494 12:14:56.162782 12, 0xFFFF, sum = 0
8495 12:14:56.165431 13, 0xFFFF, sum = 0
8496 12:14:56.165860 14, 0x0, sum = 1
8497 12:14:56.168868 15, 0x0, sum = 2
8498 12:14:56.169297 16, 0x0, sum = 3
8499 12:14:56.171776 17, 0x0, sum = 4
8500 12:14:56.172231 best_step = 15
8501 12:14:56.172568
8502 12:14:56.172876 ==
8503 12:14:56.175592 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 12:14:56.182115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 12:14:56.182546 ==
8506 12:14:56.182885 RX Vref Scan: 1
8507 12:14:56.183197
8508 12:14:56.185512 Set Vref Range= 24 -> 127
8509 12:14:56.185938
8510 12:14:56.188491 RX Vref 24 -> 127, step: 1
8511 12:14:56.188912
8512 12:14:56.189243 RX Delay 19 -> 252, step: 4
8513 12:14:56.191456
8514 12:14:56.191877 Set Vref, RX VrefLevel [Byte0]: 24
8515 12:14:56.195273 [Byte1]: 24
8516 12:14:56.199180
8517 12:14:56.199604 Set Vref, RX VrefLevel [Byte0]: 25
8518 12:14:56.202675 [Byte1]: 25
8519 12:14:56.206632
8520 12:14:56.207078 Set Vref, RX VrefLevel [Byte0]: 26
8521 12:14:56.210177 [Byte1]: 26
8522 12:14:56.214147
8523 12:14:56.214633 Set Vref, RX VrefLevel [Byte0]: 27
8524 12:14:56.217632 [Byte1]: 27
8525 12:14:56.222202
8526 12:14:56.222659 Set Vref, RX VrefLevel [Byte0]: 28
8527 12:14:56.225213 [Byte1]: 28
8528 12:14:56.229280
8529 12:14:56.229754 Set Vref, RX VrefLevel [Byte0]: 29
8530 12:14:56.232860 [Byte1]: 29
8531 12:14:56.237019
8532 12:14:56.237441 Set Vref, RX VrefLevel [Byte0]: 30
8533 12:14:56.240603 [Byte1]: 30
8534 12:14:56.244892
8535 12:14:56.245464 Set Vref, RX VrefLevel [Byte0]: 31
8536 12:14:56.247779 [Byte1]: 31
8537 12:14:56.252153
8538 12:14:56.252568 Set Vref, RX VrefLevel [Byte0]: 32
8539 12:14:56.255350 [Byte1]: 32
8540 12:14:56.260082
8541 12:14:56.260675 Set Vref, RX VrefLevel [Byte0]: 33
8542 12:14:56.263032 [Byte1]: 33
8543 12:14:56.267452
8544 12:14:56.267872 Set Vref, RX VrefLevel [Byte0]: 34
8545 12:14:56.270533 [Byte1]: 34
8546 12:14:56.275147
8547 12:14:56.275570 Set Vref, RX VrefLevel [Byte0]: 35
8548 12:14:56.278152 [Byte1]: 35
8549 12:14:56.282513
8550 12:14:56.282948 Set Vref, RX VrefLevel [Byte0]: 36
8551 12:14:56.286195 [Byte1]: 36
8552 12:14:56.290014
8553 12:14:56.290434 Set Vref, RX VrefLevel [Byte0]: 37
8554 12:14:56.293582 [Byte1]: 37
8555 12:14:56.297726
8556 12:14:56.298163 Set Vref, RX VrefLevel [Byte0]: 38
8557 12:14:56.300783 [Byte1]: 38
8558 12:14:56.304947
8559 12:14:56.305381 Set Vref, RX VrefLevel [Byte0]: 39
8560 12:14:56.308528 [Byte1]: 39
8561 12:14:56.312661
8562 12:14:56.313090 Set Vref, RX VrefLevel [Byte0]: 40
8563 12:14:56.315905 [Byte1]: 40
8564 12:14:56.320617
8565 12:14:56.321073 Set Vref, RX VrefLevel [Byte0]: 41
8566 12:14:56.323416 [Byte1]: 41
8567 12:14:56.328218
8568 12:14:56.328737 Set Vref, RX VrefLevel [Byte0]: 42
8569 12:14:56.331038 [Byte1]: 42
8570 12:14:56.335672
8571 12:14:56.336162 Set Vref, RX VrefLevel [Byte0]: 43
8572 12:14:56.338953 [Byte1]: 43
8573 12:14:56.342895
8574 12:14:56.343493 Set Vref, RX VrefLevel [Byte0]: 44
8575 12:14:56.346595 [Byte1]: 44
8576 12:14:56.351029
8577 12:14:56.351583 Set Vref, RX VrefLevel [Byte0]: 45
8578 12:14:56.354115 [Byte1]: 45
8579 12:14:56.358116
8580 12:14:56.358562 Set Vref, RX VrefLevel [Byte0]: 46
8581 12:14:56.361815 [Byte1]: 46
8582 12:14:56.366263
8583 12:14:56.366802 Set Vref, RX VrefLevel [Byte0]: 47
8584 12:14:56.369133 [Byte1]: 47
8585 12:14:56.373430
8586 12:14:56.373866 Set Vref, RX VrefLevel [Byte0]: 48
8587 12:14:56.376885 [Byte1]: 48
8588 12:14:56.381114
8589 12:14:56.381602 Set Vref, RX VrefLevel [Byte0]: 49
8590 12:14:56.383974 [Byte1]: 49
8591 12:14:56.388781
8592 12:14:56.389358 Set Vref, RX VrefLevel [Byte0]: 50
8593 12:14:56.391563 [Byte1]: 50
8594 12:14:56.396361
8595 12:14:56.396805 Set Vref, RX VrefLevel [Byte0]: 51
8596 12:14:56.399431 [Byte1]: 51
8597 12:14:56.403714
8598 12:14:56.404453 Set Vref, RX VrefLevel [Byte0]: 52
8599 12:14:56.406736 [Byte1]: 52
8600 12:14:56.411339
8601 12:14:56.411645 Set Vref, RX VrefLevel [Byte0]: 53
8602 12:14:56.414610 [Byte1]: 53
8603 12:14:56.418716
8604 12:14:56.418947 Set Vref, RX VrefLevel [Byte0]: 54
8605 12:14:56.421976 [Byte1]: 54
8606 12:14:56.426356
8607 12:14:56.426512 Set Vref, RX VrefLevel [Byte0]: 55
8608 12:14:56.429143 [Byte1]: 55
8609 12:14:56.433821
8610 12:14:56.433965 Set Vref, RX VrefLevel [Byte0]: 56
8611 12:14:56.436736 [Byte1]: 56
8612 12:14:56.441412
8613 12:14:56.441521 Set Vref, RX VrefLevel [Byte0]: 57
8614 12:14:56.444306 [Byte1]: 57
8615 12:14:56.448554
8616 12:14:56.448650 Set Vref, RX VrefLevel [Byte0]: 58
8617 12:14:56.451991 [Byte1]: 58
8618 12:14:56.456355
8619 12:14:56.456444 Set Vref, RX VrefLevel [Byte0]: 59
8620 12:14:56.459814 [Byte1]: 59
8621 12:14:56.464209
8622 12:14:56.464311 Set Vref, RX VrefLevel [Byte0]: 60
8623 12:14:56.466983 [Byte1]: 60
8624 12:14:56.471310
8625 12:14:56.471430 Set Vref, RX VrefLevel [Byte0]: 61
8626 12:14:56.474477 [Byte1]: 61
8627 12:14:56.479151
8628 12:14:56.479247 Set Vref, RX VrefLevel [Byte0]: 62
8629 12:14:56.482082 [Byte1]: 62
8630 12:14:56.486603
8631 12:14:56.486691 Set Vref, RX VrefLevel [Byte0]: 63
8632 12:14:56.490104 [Byte1]: 63
8633 12:14:56.494281
8634 12:14:56.494370 Set Vref, RX VrefLevel [Byte0]: 64
8635 12:14:56.497563 [Byte1]: 64
8636 12:14:56.501781
8637 12:14:56.501871 Set Vref, RX VrefLevel [Byte0]: 65
8638 12:14:56.504791 [Byte1]: 65
8639 12:14:56.509484
8640 12:14:56.509577 Set Vref, RX VrefLevel [Byte0]: 66
8641 12:14:56.512386 [Byte1]: 66
8642 12:14:56.517182
8643 12:14:56.517278 Set Vref, RX VrefLevel [Byte0]: 67
8644 12:14:56.520002 [Byte1]: 67
8645 12:14:56.524656
8646 12:14:56.524766 Set Vref, RX VrefLevel [Byte0]: 68
8647 12:14:56.527899 [Byte1]: 68
8648 12:14:56.531838
8649 12:14:56.531992 Set Vref, RX VrefLevel [Byte0]: 69
8650 12:14:56.535425 [Byte1]: 69
8651 12:14:56.539461
8652 12:14:56.539549 Final RX Vref Byte 0 = 57 to rank0
8653 12:14:56.542841 Final RX Vref Byte 1 = 60 to rank0
8654 12:14:56.546410 Final RX Vref Byte 0 = 57 to rank1
8655 12:14:56.549399 Final RX Vref Byte 1 = 60 to rank1==
8656 12:14:56.553117 Dram Type= 6, Freq= 0, CH_1, rank 0
8657 12:14:56.559192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8658 12:14:56.559315 ==
8659 12:14:56.559389 DQS Delay:
8660 12:14:56.562831 DQS0 = 0, DQS1 = 0
8661 12:14:56.562914 DQM Delay:
8662 12:14:56.562979 DQM0 = 133, DQM1 = 130
8663 12:14:56.566330 DQ Delay:
8664 12:14:56.569462 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8665 12:14:56.572413 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8666 12:14:56.575824 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8667 12:14:56.578847 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8668 12:14:56.578933
8669 12:14:56.578999
8670 12:14:56.579060
8671 12:14:56.582487 [DramC_TX_OE_Calibration] TA2
8672 12:14:56.585438 Original DQ_B0 (3 6) =30, OEN = 27
8673 12:14:56.588932 Original DQ_B1 (3 6) =30, OEN = 27
8674 12:14:56.592514 24, 0x0, End_B0=24 End_B1=24
8675 12:14:56.595650 25, 0x0, End_B0=25 End_B1=25
8676 12:14:56.595764 26, 0x0, End_B0=26 End_B1=26
8677 12:14:56.598665 27, 0x0, End_B0=27 End_B1=27
8678 12:14:56.601893 28, 0x0, End_B0=28 End_B1=28
8679 12:14:56.605453 29, 0x0, End_B0=29 End_B1=29
8680 12:14:56.605540 30, 0x0, End_B0=30 End_B1=30
8681 12:14:56.609075 31, 0x5151, End_B0=30 End_B1=30
8682 12:14:56.611935 Byte0 end_step=30 best_step=27
8683 12:14:56.615531 Byte1 end_step=30 best_step=27
8684 12:14:56.618564 Byte0 TX OE(2T, 0.5T) = (3, 3)
8685 12:14:56.622199 Byte1 TX OE(2T, 0.5T) = (3, 3)
8686 12:14:56.622299
8687 12:14:56.622366
8688 12:14:56.628745 [DQSOSCAuto] RK0, (LSB)MR18= 0xa14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8689 12:14:56.632484 CH1 RK0: MR19=303, MR18=A14
8690 12:14:56.638734 CH1_RK0: MR19=0x303, MR18=0xA14, DQSOSC=399, MR23=63, INC=23, DEC=15
8691 12:14:56.638981
8692 12:14:56.642090 ----->DramcWriteLeveling(PI) begin...
8693 12:14:56.642339 ==
8694 12:14:56.645390 Dram Type= 6, Freq= 0, CH_1, rank 1
8695 12:14:56.648359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8696 12:14:56.648701 ==
8697 12:14:56.651653 Write leveling (Byte 0): 25 => 25
8698 12:14:56.655576 Write leveling (Byte 1): 26 => 26
8699 12:14:56.658751 DramcWriteLeveling(PI) end<-----
8700 12:14:56.659306
8701 12:14:56.659653 ==
8702 12:14:56.662308 Dram Type= 6, Freq= 0, CH_1, rank 1
8703 12:14:56.665318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8704 12:14:56.668615 ==
8705 12:14:56.669042 [Gating] SW mode calibration
8706 12:14:56.678378 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8707 12:14:56.681482 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8708 12:14:56.684624 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8709 12:14:56.691089 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8710 12:14:56.694862 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8711 12:14:56.698102 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8712 12:14:56.705039 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8713 12:14:56.707808 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8714 12:14:56.711291 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8715 12:14:56.718062 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8716 12:14:56.720997 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8717 12:14:56.724615 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8718 12:14:56.730689 1 5 8 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8719 12:14:56.734307 1 5 12 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8720 12:14:56.737828 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8721 12:14:56.744213 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8722 12:14:56.747550 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8723 12:14:56.750960 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8724 12:14:56.757113 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8725 12:14:56.760582 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8726 12:14:56.763595 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8727 12:14:56.770798 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8728 12:14:56.773983 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8729 12:14:56.776887 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8730 12:14:56.783586 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8731 12:14:56.786681 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8732 12:14:56.790230 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8733 12:14:56.796631 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8734 12:14:56.800315 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8735 12:14:56.803250 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8736 12:14:56.809898 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8737 12:14:56.813276 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8738 12:14:56.816309 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8739 12:14:56.822991 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8740 12:14:56.825982 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8741 12:14:56.829593 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8742 12:14:56.836391 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 12:14:56.839625 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 12:14:56.842744 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 12:14:56.849507 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 12:14:56.852415 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 12:14:56.856159 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 12:14:56.862407 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 12:14:56.865979 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8750 12:14:56.872321 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8751 12:14:56.875492 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8752 12:14:56.879308 Total UI for P1: 0, mck2ui 16
8753 12:14:56.882141 best dqsien dly found for B0: ( 1, 9, 6)
8754 12:14:56.885774 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8755 12:14:56.889002 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 12:14:56.891861 Total UI for P1: 0, mck2ui 16
8757 12:14:56.895497 best dqsien dly found for B1: ( 1, 9, 12)
8758 12:14:56.898934 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8759 12:14:56.905302 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8760 12:14:56.905776
8761 12:14:56.908968 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8762 12:14:56.911870 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8763 12:14:56.914933 [Gating] SW calibration Done
8764 12:14:56.915514 ==
8765 12:14:56.918383 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 12:14:56.921850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 12:14:56.922279 ==
8768 12:14:56.925468 RX Vref Scan: 0
8769 12:14:56.925892
8770 12:14:56.926227 RX Vref 0 -> 0, step: 1
8771 12:14:56.926542
8772 12:14:56.928436 RX Delay 0 -> 252, step: 8
8773 12:14:56.931872 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8774 12:14:56.938459 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8775 12:14:56.941564 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8776 12:14:56.944637 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8777 12:14:56.948025 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8778 12:14:56.951070 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8779 12:14:56.958063 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8780 12:14:56.961478 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8781 12:14:56.964131 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8782 12:14:56.967592 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8783 12:14:56.970968 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8784 12:14:56.977507 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8785 12:14:56.981093 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8786 12:14:56.984126 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8787 12:14:56.987596 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8788 12:14:56.994332 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8789 12:14:56.994774 ==
8790 12:14:56.997146 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 12:14:57.000799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 12:14:57.001335 ==
8793 12:14:57.001765 DQS Delay:
8794 12:14:57.003761 DQS0 = 0, DQS1 = 0
8795 12:14:57.004227 DQM Delay:
8796 12:14:57.007348 DQM0 = 136, DQM1 = 130
8797 12:14:57.007857 DQ Delay:
8798 12:14:57.010355 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8799 12:14:57.013889 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =135
8800 12:14:57.016927 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8801 12:14:57.020385 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8802 12:14:57.020861
8803 12:14:57.023457
8804 12:14:57.023937 ==
8805 12:14:57.026844 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 12:14:57.030478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 12:14:57.030903 ==
8808 12:14:57.031253
8809 12:14:57.031571
8810 12:14:57.033562 TX Vref Scan disable
8811 12:14:57.034173 == TX Byte 0 ==
8812 12:14:57.040112 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8813 12:14:57.043156 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8814 12:14:57.043681 == TX Byte 1 ==
8815 12:14:57.050137 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8816 12:14:57.052937 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8817 12:14:57.053365 ==
8818 12:14:57.056390 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 12:14:57.059849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 12:14:57.060402 ==
8821 12:14:57.074399
8822 12:14:57.078180 TX Vref early break, caculate TX vref
8823 12:14:57.080941 TX Vref=16, minBit 9, minWin=21, winSum=377
8824 12:14:57.083945 TX Vref=18, minBit 9, minWin=22, winSum=385
8825 12:14:57.087652 TX Vref=20, minBit 9, minWin=22, winSum=392
8826 12:14:57.090707 TX Vref=22, minBit 9, minWin=22, winSum=398
8827 12:14:57.093824 TX Vref=24, minBit 9, minWin=23, winSum=406
8828 12:14:57.100494 TX Vref=26, minBit 9, minWin=24, winSum=412
8829 12:14:57.103986 TX Vref=28, minBit 9, minWin=24, winSum=416
8830 12:14:57.106960 TX Vref=30, minBit 8, minWin=25, winSum=416
8831 12:14:57.110411 TX Vref=32, minBit 8, minWin=24, winSum=411
8832 12:14:57.113908 TX Vref=34, minBit 0, minWin=24, winSum=402
8833 12:14:57.120106 TX Vref=36, minBit 8, minWin=22, winSum=390
8834 12:14:57.123599 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 30
8835 12:14:57.124026
8836 12:14:57.127102 Final TX Range 0 Vref 30
8837 12:14:57.127530
8838 12:14:57.127865 ==
8839 12:14:57.130027 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 12:14:57.133402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 12:14:57.136489 ==
8842 12:14:57.136927
8843 12:14:57.137264
8844 12:14:57.137593 TX Vref Scan disable
8845 12:14:57.143805 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8846 12:14:57.144354 == TX Byte 0 ==
8847 12:14:57.146488 u2DelayCellOfst[0]=14 cells (4 PI)
8848 12:14:57.150182 u2DelayCellOfst[1]=10 cells (3 PI)
8849 12:14:57.153153 u2DelayCellOfst[2]=0 cells (0 PI)
8850 12:14:57.156369 u2DelayCellOfst[3]=7 cells (2 PI)
8851 12:14:57.160002 u2DelayCellOfst[4]=7 cells (2 PI)
8852 12:14:57.162951 u2DelayCellOfst[5]=14 cells (4 PI)
8853 12:14:57.166320 u2DelayCellOfst[6]=14 cells (4 PI)
8854 12:14:57.169815 u2DelayCellOfst[7]=7 cells (2 PI)
8855 12:14:57.173280 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8856 12:14:57.176695 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8857 12:14:57.179421 == TX Byte 1 ==
8858 12:14:57.182758 u2DelayCellOfst[8]=0 cells (0 PI)
8859 12:14:57.186297 u2DelayCellOfst[9]=3 cells (1 PI)
8860 12:14:57.189475 u2DelayCellOfst[10]=10 cells (3 PI)
8861 12:14:57.192432 u2DelayCellOfst[11]=7 cells (2 PI)
8862 12:14:57.195848 u2DelayCellOfst[12]=14 cells (4 PI)
8863 12:14:57.198940 u2DelayCellOfst[13]=18 cells (5 PI)
8864 12:14:57.202471 u2DelayCellOfst[14]=18 cells (5 PI)
8865 12:14:57.205412 u2DelayCellOfst[15]=18 cells (5 PI)
8866 12:14:57.209203 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8867 12:14:57.212186 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8868 12:14:57.215586 DramC Write-DBI on
8869 12:14:57.216061 ==
8870 12:14:57.219167 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 12:14:57.222259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 12:14:57.222658 ==
8873 12:14:57.223105
8874 12:14:57.223430
8875 12:14:57.225208 TX Vref Scan disable
8876 12:14:57.228801 == TX Byte 0 ==
8877 12:14:57.231771 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8878 12:14:57.232268 == TX Byte 1 ==
8879 12:14:57.238586 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8880 12:14:57.239069 DramC Write-DBI off
8881 12:14:57.239538
8882 12:14:57.240099 [DATLAT]
8883 12:14:57.242082 Freq=1600, CH1 RK1
8884 12:14:57.242650
8885 12:14:57.245131 DATLAT Default: 0xf
8886 12:14:57.245551 0, 0xFFFF, sum = 0
8887 12:14:57.248694 1, 0xFFFF, sum = 0
8888 12:14:57.249153 2, 0xFFFF, sum = 0
8889 12:14:57.251925 3, 0xFFFF, sum = 0
8890 12:14:57.252417 4, 0xFFFF, sum = 0
8891 12:14:57.254994 5, 0xFFFF, sum = 0
8892 12:14:57.255423 6, 0xFFFF, sum = 0
8893 12:14:57.258630 7, 0xFFFF, sum = 0
8894 12:14:57.259059 8, 0xFFFF, sum = 0
8895 12:14:57.261680 9, 0xFFFF, sum = 0
8896 12:14:57.262112 10, 0xFFFF, sum = 0
8897 12:14:57.264750 11, 0xFFFF, sum = 0
8898 12:14:57.265178 12, 0xFFFF, sum = 0
8899 12:14:57.268403 13, 0xFFFF, sum = 0
8900 12:14:57.268833 14, 0x0, sum = 1
8901 12:14:57.271574 15, 0x0, sum = 2
8902 12:14:57.272206 16, 0x0, sum = 3
8903 12:14:57.275084 17, 0x0, sum = 4
8904 12:14:57.275514 best_step = 15
8905 12:14:57.275907
8906 12:14:57.276275 ==
8907 12:14:57.278042 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 12:14:57.284780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 12:14:57.285232 ==
8910 12:14:57.285580 RX Vref Scan: 0
8911 12:14:57.285924
8912 12:14:57.288423 RX Vref 0 -> 0, step: 1
8913 12:14:57.288936
8914 12:14:57.291147 RX Delay 11 -> 252, step: 4
8915 12:14:57.294734 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8916 12:14:57.297664 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8917 12:14:57.304375 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8918 12:14:57.308019 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8919 12:14:57.310995 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8920 12:14:57.314491 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8921 12:14:57.317460 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8922 12:14:57.324483 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8923 12:14:57.327499 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8924 12:14:57.330544 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8925 12:14:57.334195 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8926 12:14:57.340538 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8927 12:14:57.343996 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8928 12:14:57.347033 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8929 12:14:57.350309 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8930 12:14:57.353770 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8931 12:14:57.356831 ==
8932 12:14:57.360375 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 12:14:57.363470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 12:14:57.363988 ==
8935 12:14:57.364389 DQS Delay:
8936 12:14:57.367068 DQS0 = 0, DQS1 = 0
8937 12:14:57.367512 DQM Delay:
8938 12:14:57.370260 DQM0 = 133, DQM1 = 128
8939 12:14:57.370687 DQ Delay:
8940 12:14:57.373761 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
8941 12:14:57.376744 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8942 12:14:57.380344 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8943 12:14:57.383150 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8944 12:14:57.383654
8945 12:14:57.384022
8946 12:14:57.384452
8947 12:14:57.386585 [DramC_TX_OE_Calibration] TA2
8948 12:14:57.389877 Original DQ_B0 (3 6) =30, OEN = 27
8949 12:14:57.393217 Original DQ_B1 (3 6) =30, OEN = 27
8950 12:14:57.396143 24, 0x0, End_B0=24 End_B1=24
8951 12:14:57.399884 25, 0x0, End_B0=25 End_B1=25
8952 12:14:57.402848 26, 0x0, End_B0=26 End_B1=26
8953 12:14:57.403434 27, 0x0, End_B0=27 End_B1=27
8954 12:14:57.406561 28, 0x0, End_B0=28 End_B1=28
8955 12:14:57.409329 29, 0x0, End_B0=29 End_B1=29
8956 12:14:57.413132 30, 0x0, End_B0=30 End_B1=30
8957 12:14:57.416086 31, 0x4141, End_B0=30 End_B1=30
8958 12:14:57.416519 Byte0 end_step=30 best_step=27
8959 12:14:57.419461 Byte1 end_step=30 best_step=27
8960 12:14:57.422493 Byte0 TX OE(2T, 0.5T) = (3, 3)
8961 12:14:57.426012 Byte1 TX OE(2T, 0.5T) = (3, 3)
8962 12:14:57.426427
8963 12:14:57.426761
8964 12:14:57.435843 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8965 12:14:57.436301 CH1 RK1: MR19=303, MR18=F1C
8966 12:14:57.442411 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8967 12:14:57.445801 [RxdqsGatingPostProcess] freq 1600
8968 12:14:57.452060 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8969 12:14:57.455155 best DQS0 dly(2T, 0.5T) = (1, 1)
8970 12:14:57.458783 best DQS1 dly(2T, 0.5T) = (1, 1)
8971 12:14:57.461993 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8972 12:14:57.465094 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8973 12:14:57.465294 best DQS0 dly(2T, 0.5T) = (1, 1)
8974 12:14:57.468284 best DQS1 dly(2T, 0.5T) = (1, 1)
8975 12:14:57.471330 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8976 12:14:57.474940 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8977 12:14:57.478576 Pre-setting of DQS Precalculation
8978 12:14:57.484902 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8979 12:14:57.491208 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8980 12:14:57.497621 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8981 12:14:57.497734
8982 12:14:57.497889
8983 12:14:57.501103 [Calibration Summary] 3200 Mbps
8984 12:14:57.501192 CH 0, Rank 0
8985 12:14:57.504274 SW Impedance : PASS
8986 12:14:57.507826 DUTY Scan : NO K
8987 12:14:57.507934 ZQ Calibration : PASS
8988 12:14:57.510756 Jitter Meter : NO K
8989 12:14:57.514521 CBT Training : PASS
8990 12:14:57.514608 Write leveling : PASS
8991 12:14:57.517689 RX DQS gating : PASS
8992 12:14:57.520687 RX DQ/DQS(RDDQC) : PASS
8993 12:14:57.520773 TX DQ/DQS : PASS
8994 12:14:57.524266 RX DATLAT : PASS
8995 12:14:57.527276 RX DQ/DQS(Engine): PASS
8996 12:14:57.527388 TX OE : PASS
8997 12:14:57.530823 All Pass.
8998 12:14:57.530906
8999 12:14:57.530972 CH 0, Rank 1
9000 12:14:57.534050 SW Impedance : PASS
9001 12:14:57.534134 DUTY Scan : NO K
9002 12:14:57.537129 ZQ Calibration : PASS
9003 12:14:57.540274 Jitter Meter : NO K
9004 12:14:57.540362 CBT Training : PASS
9005 12:14:57.543760 Write leveling : PASS
9006 12:14:57.546938 RX DQS gating : PASS
9007 12:14:57.547052 RX DQ/DQS(RDDQC) : PASS
9008 12:14:57.550369 TX DQ/DQS : PASS
9009 12:14:57.553644 RX DATLAT : PASS
9010 12:14:57.553728 RX DQ/DQS(Engine): PASS
9011 12:14:57.557218 TX OE : PASS
9012 12:14:57.557302 All Pass.
9013 12:14:57.557372
9014 12:14:57.560216 CH 1, Rank 0
9015 12:14:57.560299 SW Impedance : PASS
9016 12:14:57.563872 DUTY Scan : NO K
9017 12:14:57.566766 ZQ Calibration : PASS
9018 12:14:57.566848 Jitter Meter : NO K
9019 12:14:57.570462 CBT Training : PASS
9020 12:14:57.570545 Write leveling : PASS
9021 12:14:57.573400 RX DQS gating : PASS
9022 12:14:57.577103 RX DQ/DQS(RDDQC) : PASS
9023 12:14:57.577187 TX DQ/DQS : PASS
9024 12:14:57.579922 RX DATLAT : PASS
9025 12:14:57.582991 RX DQ/DQS(Engine): PASS
9026 12:14:57.583074 TX OE : PASS
9027 12:14:57.586627 All Pass.
9028 12:14:57.586710
9029 12:14:57.586775 CH 1, Rank 1
9030 12:14:57.589591 SW Impedance : PASS
9031 12:14:57.589674 DUTY Scan : NO K
9032 12:14:57.593045 ZQ Calibration : PASS
9033 12:14:57.596600 Jitter Meter : NO K
9034 12:14:57.596685 CBT Training : PASS
9035 12:14:57.599933 Write leveling : PASS
9036 12:14:57.602877 RX DQS gating : PASS
9037 12:14:57.602960 RX DQ/DQS(RDDQC) : PASS
9038 12:14:57.605942 TX DQ/DQS : PASS
9039 12:14:57.609593 RX DATLAT : PASS
9040 12:14:57.609676 RX DQ/DQS(Engine): PASS
9041 12:14:57.613144 TX OE : PASS
9042 12:14:57.613227 All Pass.
9043 12:14:57.613293
9044 12:14:57.616233 DramC Write-DBI on
9045 12:14:57.619219 PER_BANK_REFRESH: Hybrid Mode
9046 12:14:57.619302 TX_TRACKING: ON
9047 12:14:57.629051 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9048 12:14:57.635805 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9049 12:14:57.642214 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 12:14:57.649346 [FAST_K] Save calibration result to emmc
9051 12:14:57.649444 sync common calibartion params.
9052 12:14:57.652188 sync cbt_mode0:1, 1:1
9053 12:14:57.655854 dram_init: ddr_geometry: 2
9054 12:14:57.659239 dram_init: ddr_geometry: 2
9055 12:14:57.659328 dram_init: ddr_geometry: 2
9056 12:14:57.662060 0:dram_rank_size:100000000
9057 12:14:57.665683 1:dram_rank_size:100000000
9058 12:14:57.668703 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9059 12:14:57.672358 DFS_SHUFFLE_HW_MODE: ON
9060 12:14:57.675306 dramc_set_vcore_voltage set vcore to 725000
9061 12:14:57.679002 Read voltage for 1600, 0
9062 12:14:57.679087 Vio18 = 0
9063 12:14:57.681895 Vcore = 725000
9064 12:14:57.682007 Vdram = 0
9065 12:14:57.682109 Vddq = 0
9066 12:14:57.682170 Vmddr = 0
9067 12:14:57.685539 switch to 3200 Mbps bootup
9068 12:14:57.688474 [DramcRunTimeConfig]
9069 12:14:57.688561 PHYPLL
9070 12:14:57.691458 DPM_CONTROL_AFTERK: ON
9071 12:14:57.691550 PER_BANK_REFRESH: ON
9072 12:14:57.694782 REFRESH_OVERHEAD_REDUCTION: ON
9073 12:14:57.698186 CMD_PICG_NEW_MODE: OFF
9074 12:14:57.698271 XRTWTW_NEW_MODE: ON
9075 12:14:57.701613 XRTRTR_NEW_MODE: ON
9076 12:14:57.701697 TX_TRACKING: ON
9077 12:14:57.704558 RDSEL_TRACKING: OFF
9078 12:14:57.707910 DQS Precalculation for DVFS: ON
9079 12:14:57.708018 RX_TRACKING: OFF
9080 12:14:57.711526 HW_GATING DBG: ON
9081 12:14:57.711608 ZQCS_ENABLE_LP4: ON
9082 12:14:57.714733 RX_PICG_NEW_MODE: ON
9083 12:14:57.714815 TX_PICG_NEW_MODE: ON
9084 12:14:57.718375 ENABLE_RX_DCM_DPHY: ON
9085 12:14:57.721466 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9086 12:14:57.724866 DUMMY_READ_FOR_TRACKING: OFF
9087 12:14:57.724948 !!! SPM_CONTROL_AFTERK: OFF
9088 12:14:57.727904 !!! SPM could not control APHY
9089 12:14:57.731594 IMPEDANCE_TRACKING: ON
9090 12:14:57.731728 TEMP_SENSOR: ON
9091 12:14:57.734561 HW_SAVE_FOR_SR: OFF
9092 12:14:57.737662 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9093 12:14:57.740987 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9094 12:14:57.744684 Read ODT Tracking: ON
9095 12:14:57.744767 Refresh Rate DeBounce: ON
9096 12:14:57.747609 DFS_NO_QUEUE_FLUSH: ON
9097 12:14:57.750778 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9098 12:14:57.754184 ENABLE_DFS_RUNTIME_MRW: OFF
9099 12:14:57.754270 DDR_RESERVE_NEW_MODE: ON
9100 12:14:57.757641 MR_CBT_SWITCH_FREQ: ON
9101 12:14:57.760773 =========================
9102 12:14:57.778307 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9103 12:14:57.781884 dram_init: ddr_geometry: 2
9104 12:14:57.799720 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9105 12:14:57.803176 dram_init: dram init end (result: 0)
9106 12:14:57.809495 DRAM-K: Full calibration passed in 24381 msecs
9107 12:14:57.812933 MRC: failed to locate region type 0.
9108 12:14:57.813041 DRAM rank0 size:0x100000000,
9109 12:14:57.816429 DRAM rank1 size=0x100000000
9110 12:14:57.826016 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9111 12:14:57.832573 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9112 12:14:57.842724 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9113 12:14:57.849298 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9114 12:14:57.849411 DRAM rank0 size:0x100000000,
9115 12:14:57.852311 DRAM rank1 size=0x100000000
9116 12:14:57.852398 CBMEM:
9117 12:14:57.855963 IMD: root @ 0xfffff000 254 entries.
9118 12:14:57.859035 IMD: root @ 0xffffec00 62 entries.
9119 12:14:57.865530 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9120 12:14:57.868901 WARNING: RO_VPD is uninitialized or empty.
9121 12:14:57.871971 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9122 12:14:57.879725 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9123 12:14:57.892426 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9124 12:14:57.904386 BS: romstage times (exec / console): total (unknown) / 23923 ms
9125 12:14:57.904495
9126 12:14:57.904568
9127 12:14:57.914148 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9128 12:14:57.916934 ARM64: Exception handlers installed.
9129 12:14:57.920328 ARM64: Testing exception
9130 12:14:57.923457 ARM64: Done test exception
9131 12:14:57.923537 Enumerating buses...
9132 12:14:57.927048 Show all devs... Before device enumeration.
9133 12:14:57.929981 Root Device: enabled 1
9134 12:14:57.933687 CPU_CLUSTER: 0: enabled 1
9135 12:14:57.933765 CPU: 00: enabled 1
9136 12:14:57.936726 Compare with tree...
9137 12:14:57.936811 Root Device: enabled 1
9138 12:14:57.940383 CPU_CLUSTER: 0: enabled 1
9139 12:14:57.943270 CPU: 00: enabled 1
9140 12:14:57.943379 Root Device scanning...
9141 12:14:57.946960 scan_static_bus for Root Device
9142 12:14:57.949910 CPU_CLUSTER: 0 enabled
9143 12:14:57.953253 scan_static_bus for Root Device done
9144 12:14:57.956612 scan_bus: bus Root Device finished in 8 msecs
9145 12:14:57.956701 done
9146 12:14:57.963139 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9147 12:14:57.966283 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9148 12:14:57.973206 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9149 12:14:57.979947 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9150 12:14:57.980084 Allocating resources...
9151 12:14:57.982897 Reading resources...
9152 12:14:57.986465 Root Device read_resources bus 0 link: 0
9153 12:14:57.989653 DRAM rank0 size:0x100000000,
9154 12:14:57.989745 DRAM rank1 size=0x100000000
9155 12:14:57.996038 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9156 12:14:57.996126 CPU: 00 missing read_resources
9157 12:14:58.002754 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9158 12:14:58.006158 Root Device read_resources bus 0 link: 0 done
9159 12:14:58.009202 Done reading resources.
9160 12:14:58.012561 Show resources in subtree (Root Device)...After reading.
9161 12:14:58.015945 Root Device child on link 0 CPU_CLUSTER: 0
9162 12:14:58.018972 CPU_CLUSTER: 0 child on link 0 CPU: 00
9163 12:14:58.029262 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9164 12:14:58.029355 CPU: 00
9165 12:14:58.035928 Root Device assign_resources, bus 0 link: 0
9166 12:14:58.038991 CPU_CLUSTER: 0 missing set_resources
9167 12:14:58.042010 Root Device assign_resources, bus 0 link: 0 done
9168 12:14:58.045467 Done setting resources.
9169 12:14:58.048476 Show resources in subtree (Root Device)...After assigning values.
9170 12:14:58.055017 Root Device child on link 0 CPU_CLUSTER: 0
9171 12:14:58.058485 CPU_CLUSTER: 0 child on link 0 CPU: 00
9172 12:14:58.065120 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9173 12:14:58.068376 CPU: 00
9174 12:14:58.068469 Done allocating resources.
9175 12:14:58.074865 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9176 12:14:58.078220 Enabling resources...
9177 12:14:58.078296 done.
9178 12:14:58.081110 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9179 12:14:58.084848 Initializing devices...
9180 12:14:58.084938 Root Device init
9181 12:14:58.087816 init hardware done!
9182 12:14:58.091350 0x00000018: ctrlr->caps
9183 12:14:58.091438 52.000 MHz: ctrlr->f_max
9184 12:14:58.094534 0.400 MHz: ctrlr->f_min
9185 12:14:58.098035 0x40ff8080: ctrlr->voltages
9186 12:14:58.098113 sclk: 390625
9187 12:14:58.098186 Bus Width = 1
9188 12:14:58.101268 sclk: 390625
9189 12:14:58.101343 Bus Width = 1
9190 12:14:58.104199 Early init status = 3
9191 12:14:58.107767 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9192 12:14:58.112462 in-header: 03 fc 00 00 01 00 00 00
9193 12:14:58.115315 in-data: 00
9194 12:14:58.118822 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9195 12:14:58.124389 in-header: 03 fd 00 00 00 00 00 00
9196 12:14:58.127476 in-data:
9197 12:14:58.130651 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9198 12:14:58.135456 in-header: 03 fc 00 00 01 00 00 00
9199 12:14:58.139016 in-data: 00
9200 12:14:58.142000 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9201 12:14:58.147370 in-header: 03 fd 00 00 00 00 00 00
9202 12:14:58.150959 in-data:
9203 12:14:58.154003 [SSUSB] Setting up USB HOST controller...
9204 12:14:58.157636 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9205 12:14:58.160662 [SSUSB] phy power-on done.
9206 12:14:58.164191 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9207 12:14:58.170802 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9208 12:14:58.173860 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9209 12:14:58.180869 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9210 12:14:58.186879 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9211 12:14:58.193447 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9212 12:14:58.200192 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9213 12:14:58.206834 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9214 12:14:58.210316 SPM: binary array size = 0x9dc
9215 12:14:58.213378 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9216 12:14:58.220004 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9217 12:14:58.226463 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9218 12:14:58.233022 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9219 12:14:58.236533 configure_display: Starting display init
9220 12:14:58.270902 anx7625_power_on_init: Init interface.
9221 12:14:58.273947 anx7625_disable_pd_protocol: Disabled PD feature.
9222 12:14:58.277433 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9223 12:14:58.305445 anx7625_start_dp_work: Secure OCM version=00
9224 12:14:58.308370 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9225 12:14:58.323257 sp_tx_get_edid_block: EDID Block = 1
9226 12:14:58.425818 Extracted contents:
9227 12:14:58.429154 header: 00 ff ff ff ff ff ff 00
9228 12:14:58.432649 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9229 12:14:58.436025 version: 01 04
9230 12:14:58.438875 basic params: 95 1f 11 78 0a
9231 12:14:58.442612 chroma info: 76 90 94 55 54 90 27 21 50 54
9232 12:14:58.445490 established: 00 00 00
9233 12:14:58.452200 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9234 12:14:58.458767 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9235 12:14:58.462309 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9236 12:14:58.468952 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9237 12:14:58.475724 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9238 12:14:58.478557 extensions: 00
9239 12:14:58.478641 checksum: fb
9240 12:14:58.478706
9241 12:14:58.485220 Manufacturer: IVO Model 57d Serial Number 0
9242 12:14:58.485326 Made week 0 of 2020
9243 12:14:58.488687 EDID version: 1.4
9244 12:14:58.488796 Digital display
9245 12:14:58.491746 6 bits per primary color channel
9246 12:14:58.495055 DisplayPort interface
9247 12:14:58.495164 Maximum image size: 31 cm x 17 cm
9248 12:14:58.498010 Gamma: 220%
9249 12:14:58.498118 Check DPMS levels
9250 12:14:58.504661 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9251 12:14:58.508117 First detailed timing is preferred timing
9252 12:14:58.511241 Established timings supported:
9253 12:14:58.511350 Standard timings supported:
9254 12:14:58.514880 Detailed timings
9255 12:14:58.517963 Hex of detail: 383680a07038204018303c0035ae10000019
9256 12:14:58.524683 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9257 12:14:58.527626 0780 0798 07c8 0820 hborder 0
9258 12:14:58.531196 0438 043b 0447 0458 vborder 0
9259 12:14:58.534653 -hsync -vsync
9260 12:14:58.534736 Did detailed timing
9261 12:14:58.541104 Hex of detail: 000000000000000000000000000000000000
9262 12:14:58.544430 Manufacturer-specified data, tag 0
9263 12:14:58.547404 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9264 12:14:58.551113 ASCII string: InfoVision
9265 12:14:58.554054 Hex of detail: 000000fe00523134304e574635205248200a
9266 12:14:58.557636 ASCII string: R140NWF5 RH
9267 12:14:58.557720 Checksum
9268 12:14:58.560716 Checksum: 0xfb (valid)
9269 12:14:58.564297 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9270 12:14:58.567195 DSI data_rate: 832800000 bps
9271 12:14:58.573651 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9272 12:14:58.577301 anx7625_parse_edid: pixelclock(138800).
9273 12:14:58.580774 hactive(1920), hsync(48), hfp(24), hbp(88)
9274 12:14:58.583692 vactive(1080), vsync(12), vfp(3), vbp(17)
9275 12:14:58.587212 anx7625_dsi_config: config dsi.
9276 12:14:58.594029 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9277 12:14:58.607904 anx7625_dsi_config: success to config DSI
9278 12:14:58.611344 anx7625_dp_start: MIPI phy setup OK.
9279 12:14:58.614426 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9280 12:14:58.618022 mtk_ddp_mode_set invalid vrefresh 60
9281 12:14:58.621061 main_disp_path_setup
9282 12:14:58.621145 ovl_layer_smi_id_en
9283 12:14:58.623925 ovl_layer_smi_id_en
9284 12:14:58.624011 ccorr_config
9285 12:14:58.624101 aal_config
9286 12:14:58.627792 gamma_config
9287 12:14:58.627876 postmask_config
9288 12:14:58.630861 dither_config
9289 12:14:58.633846 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9290 12:14:58.640745 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9291 12:14:58.644006 Root Device init finished in 555 msecs
9292 12:14:58.647107 CPU_CLUSTER: 0 init
9293 12:14:58.654093 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9294 12:14:58.660247 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9295 12:14:58.660333 APU_MBOX 0x190000b0 = 0x10001
9296 12:14:58.663945 APU_MBOX 0x190001b0 = 0x10001
9297 12:14:58.666864 APU_MBOX 0x190005b0 = 0x10001
9298 12:14:58.670305 APU_MBOX 0x190006b0 = 0x10001
9299 12:14:58.676950 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9300 12:14:58.687056 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9301 12:14:58.699851 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9302 12:14:58.706168 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9303 12:14:58.717588 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9304 12:14:58.726783 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9305 12:14:58.730344 CPU_CLUSTER: 0 init finished in 81 msecs
9306 12:14:58.733395 Devices initialized
9307 12:14:58.736311 Show all devs... After init.
9308 12:14:58.736401 Root Device: enabled 1
9309 12:14:58.739792 CPU_CLUSTER: 0: enabled 1
9310 12:14:58.743271 CPU: 00: enabled 1
9311 12:14:58.746655 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9312 12:14:58.749635 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9313 12:14:58.752976 ELOG: NV offset 0x57f000 size 0x1000
9314 12:14:58.759974 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9315 12:14:58.766053 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9316 12:14:58.769724 ELOG: Event(17) added with size 13 at 2023-06-06 12:14:58 UTC
9317 12:14:58.776360 out: cmd=0x121: 03 db 21 01 00 00 00 00
9318 12:14:58.779338 in-header: 03 54 00 00 2c 00 00 00
9319 12:14:58.792571 in-data: 0b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9320 12:14:58.795552 ELOG: Event(A1) added with size 10 at 2023-06-06 12:14:58 UTC
9321 12:14:58.802557 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9322 12:14:58.809018 ELOG: Event(A0) added with size 9 at 2023-06-06 12:14:58 UTC
9323 12:14:58.812598 elog_add_boot_reason: Logged dev mode boot
9324 12:14:58.818723 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9325 12:14:58.818805 Finalize devices...
9326 12:14:58.822158 Devices finalized
9327 12:14:58.825144 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9328 12:14:58.828861 Writing coreboot table at 0xffe64000
9329 12:14:58.831914 0. 000000000010a000-0000000000113fff: RAMSTAGE
9330 12:14:58.838325 1. 0000000040000000-00000000400fffff: RAM
9331 12:14:58.841966 2. 0000000040100000-000000004032afff: RAMSTAGE
9332 12:14:58.845181 3. 000000004032b000-00000000545fffff: RAM
9333 12:14:58.848763 4. 0000000054600000-000000005465ffff: BL31
9334 12:14:58.851896 5. 0000000054660000-00000000ffe63fff: RAM
9335 12:14:58.858271 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9336 12:14:58.861587 7. 0000000100000000-000000023fffffff: RAM
9337 12:14:58.865092 Passing 5 GPIOs to payload:
9338 12:14:58.867954 NAME | PORT | POLARITY | VALUE
9339 12:14:58.874641 EC in RW | 0x000000aa | low | undefined
9340 12:14:58.878236 EC interrupt | 0x00000005 | low | undefined
9341 12:14:58.884987 TPM interrupt | 0x000000ab | high | undefined
9342 12:14:58.887792 SD card detect | 0x00000011 | high | undefined
9343 12:14:58.890965 speaker enable | 0x00000093 | high | undefined
9344 12:14:58.894460 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9345 12:14:58.898573 in-header: 03 f9 00 00 02 00 00 00
9346 12:14:58.902296 in-data: 02 00
9347 12:14:58.905543 ADC[4]: Raw value=901847 ID=7
9348 12:14:58.908727 ADC[3]: Raw value=213916 ID=1
9349 12:14:58.908810 RAM Code: 0x71
9350 12:14:58.912148 ADC[6]: Raw value=74630 ID=0
9351 12:14:58.915544 ADC[5]: Raw value=213546 ID=1
9352 12:14:58.915657 SKU Code: 0x1
9353 12:14:58.921831 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a51a
9354 12:14:58.921918 coreboot table: 964 bytes.
9355 12:14:58.925381 IMD ROOT 0. 0xfffff000 0x00001000
9356 12:14:58.929098 IMD SMALL 1. 0xffffe000 0x00001000
9357 12:14:58.931968 RO MCACHE 2. 0xffffc000 0x00001104
9358 12:14:58.935051 CONSOLE 3. 0xfff7c000 0x00080000
9359 12:14:58.938705 FMAP 4. 0xfff7b000 0x00000452
9360 12:14:58.941655 TIME STAMP 5. 0xfff7a000 0x00000910
9361 12:14:58.945127 VBOOT WORK 6. 0xfff66000 0x00014000
9362 12:14:58.948085 RAMOOPS 7. 0xffe66000 0x00100000
9363 12:14:58.951454 COREBOOT 8. 0xffe64000 0x00002000
9364 12:14:58.955003 IMD small region:
9365 12:14:58.958321 IMD ROOT 0. 0xffffec00 0x00000400
9366 12:14:58.961798 VPD 1. 0xffffeba0 0x0000004c
9367 12:14:58.964731 MMC STATUS 2. 0xffffeb80 0x00000004
9368 12:14:58.971560 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9369 12:14:58.971649 Probing TPM: done!
9370 12:14:58.978200 Connected to device vid:did:rid of 1ae0:0028:00
9371 12:14:58.984833 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9372 12:14:58.988406 Initialized TPM device CR50 revision 0
9373 12:14:58.991531 Checking cr50 for pending updates
9374 12:14:58.997008 Reading cr50 TPM mode
9375 12:14:59.005769 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9376 12:14:59.012357 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9377 12:14:59.052582 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9378 12:14:59.055490 Checking segment from ROM address 0x40100000
9379 12:14:59.059057 Checking segment from ROM address 0x4010001c
9380 12:14:59.065599 Loading segment from ROM address 0x40100000
9381 12:14:59.065719 code (compression=0)
9382 12:14:59.075616 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9383 12:14:59.082184 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9384 12:14:59.082279 it's not compressed!
9385 12:14:59.088890 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9386 12:14:59.095728 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9387 12:14:59.113273 Loading segment from ROM address 0x4010001c
9388 12:14:59.113404 Entry Point 0x80000000
9389 12:14:59.116440 Loaded segments
9390 12:14:59.119414 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9391 12:14:59.126300 Jumping to boot code at 0x80000000(0xffe64000)
9392 12:14:59.132995 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9393 12:14:59.139759 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9394 12:14:59.147388 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9395 12:14:59.150963 Checking segment from ROM address 0x40100000
9396 12:14:59.154145 Checking segment from ROM address 0x4010001c
9397 12:14:59.160511 Loading segment from ROM address 0x40100000
9398 12:14:59.161197 code (compression=1)
9399 12:14:59.167080 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9400 12:14:59.177052 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9401 12:14:59.177563 using LZMA
9402 12:14:59.186208 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9403 12:14:59.192419 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9404 12:14:59.196071 Loading segment from ROM address 0x4010001c
9405 12:14:59.196530 Entry Point 0x54601000
9406 12:14:59.198926 Loaded segments
9407 12:14:59.202656 NOTICE: MT8192 bl31_setup
9408 12:14:59.210055 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9409 12:14:59.213029 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9410 12:14:59.216577 WARNING: region 0:
9411 12:14:59.219464 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9412 12:14:59.220082 WARNING: region 1:
9413 12:14:59.226243 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9414 12:14:59.229270 WARNING: region 2:
9415 12:14:59.232934 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9416 12:14:59.236114 WARNING: region 3:
9417 12:14:59.239152 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9418 12:14:59.242770 WARNING: region 4:
9419 12:14:59.249073 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9420 12:14:59.249596 WARNING: region 5:
9421 12:14:59.252861 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9422 12:14:59.255945 WARNING: region 6:
9423 12:14:59.259399 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9424 12:14:59.262549 WARNING: region 7:
9425 12:14:59.266123 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9426 12:14:59.272314 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9427 12:14:59.276165 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9428 12:14:59.279083 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9429 12:14:59.285563 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9430 12:14:59.289375 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9431 12:14:59.292548 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9432 12:14:59.299320 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9433 12:14:59.302407 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9434 12:14:59.309210 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9435 12:14:59.312230 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9436 12:14:59.315824 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9437 12:14:59.322278 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9438 12:14:59.325458 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9439 12:14:59.332133 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9440 12:14:59.335691 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9441 12:14:59.339065 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9442 12:14:59.345404 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9443 12:14:59.348466 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9444 12:14:59.352316 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9445 12:14:59.358522 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9446 12:14:59.362275 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9447 12:14:59.368727 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9448 12:14:59.372157 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9449 12:14:59.375537 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9450 12:14:59.382330 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9451 12:14:59.385195 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9452 12:14:59.391605 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9453 12:14:59.395252 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9454 12:14:59.402042 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9455 12:14:59.405108 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9456 12:14:59.408498 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9457 12:14:59.415224 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9458 12:14:59.418323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9459 12:14:59.422057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9460 12:14:59.424889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9461 12:14:59.431547 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9462 12:14:59.435269 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9463 12:14:59.438125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9464 12:14:59.441526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9465 12:14:59.448345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9466 12:14:59.452100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9467 12:14:59.455075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9468 12:14:59.458140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9469 12:14:59.464906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9470 12:14:59.468473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9471 12:14:59.471610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9472 12:14:59.474576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9473 12:14:59.481571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9474 12:14:59.484543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9475 12:14:59.491455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9476 12:14:59.495090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9477 12:14:59.498285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9478 12:14:59.504375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9479 12:14:59.507967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9480 12:14:59.514701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9481 12:14:59.517815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9482 12:14:59.524505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9483 12:14:59.527394 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9484 12:14:59.534155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9485 12:14:59.537303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9486 12:14:59.541015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9487 12:14:59.547476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9488 12:14:59.550598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9489 12:14:59.557453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9490 12:14:59.560589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9491 12:14:59.567360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9492 12:14:59.571048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9493 12:14:59.577197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9494 12:14:59.580610 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9495 12:14:59.583660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9496 12:14:59.590661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9497 12:14:59.593926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9498 12:14:59.600628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9499 12:14:59.604105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9500 12:14:59.610341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9501 12:14:59.613918 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9502 12:14:59.616852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9503 12:14:59.623745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9504 12:14:59.627421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9505 12:14:59.633929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9506 12:14:59.636902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9507 12:14:59.643855 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9508 12:14:59.646816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9509 12:14:59.653819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9510 12:14:59.656949 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9511 12:14:59.660094 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9512 12:14:59.666977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9513 12:14:59.670030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9514 12:14:59.676724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9515 12:14:59.680467 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9516 12:14:59.686410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9517 12:14:59.690076 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9518 12:14:59.696362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9519 12:14:59.699993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9520 12:14:59.703567 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9521 12:14:59.709885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9522 12:14:59.712966 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9523 12:14:59.716675 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9524 12:14:59.723138 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9525 12:14:59.726348 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9526 12:14:59.730074 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9527 12:14:59.736100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9528 12:14:59.739563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9529 12:14:59.743044 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9530 12:14:59.750001 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9531 12:14:59.752860 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9532 12:14:59.759657 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9533 12:14:59.763240 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9534 12:14:59.766195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9535 12:14:59.773098 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9536 12:14:59.776012 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9537 12:14:59.783040 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9538 12:14:59.786148 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9539 12:14:59.789733 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9540 12:14:59.796344 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9541 12:14:59.799299 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9542 12:14:59.802993 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9543 12:14:59.809449 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9544 12:14:59.812679 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9545 12:14:59.816340 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9546 12:14:59.822448 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9547 12:14:59.826290 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9548 12:14:59.829357 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9549 12:14:59.832428 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9550 12:14:59.839852 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9551 12:14:59.842615 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9552 12:14:59.849132 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9553 12:14:59.852819 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9554 12:14:59.856206 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9555 12:14:59.862515 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9556 12:14:59.865669 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9557 12:14:59.872485 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9558 12:14:59.875549 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9559 12:14:59.878709 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9560 12:14:59.885521 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9561 12:14:59.888544 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9562 12:14:59.895168 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9563 12:14:59.899185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9564 12:14:59.902055 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9565 12:14:59.908831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9566 12:14:59.912311 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9567 12:14:59.915233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9568 12:14:59.922131 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9569 12:14:59.925186 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9570 12:14:59.932168 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9571 12:14:59.935286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9572 12:14:59.938354 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9573 12:14:59.945240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9574 12:14:59.948537 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9575 12:14:59.955370 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9576 12:14:59.958554 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9577 12:14:59.962270 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9578 12:14:59.968959 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9579 12:14:59.971849 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9580 12:14:59.978531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9581 12:14:59.981510 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9582 12:14:59.985289 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9583 12:14:59.991445 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9584 12:14:59.995089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9585 12:15:00.001486 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9586 12:15:00.005178 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9587 12:15:00.008309 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9588 12:15:00.014737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9589 12:15:00.018040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9590 12:15:00.024386 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9591 12:15:00.027964 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9592 12:15:00.031023 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9593 12:15:00.037707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9594 12:15:00.040767 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9595 12:15:00.047473 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9596 12:15:00.051108 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9597 12:15:00.054085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9598 12:15:00.060346 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9599 12:15:00.064103 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9600 12:15:00.070438 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9601 12:15:00.073613 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9602 12:15:00.077357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9603 12:15:00.083565 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9604 12:15:00.087342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9605 12:15:00.093129 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9606 12:15:00.097140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9607 12:15:00.099959 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9608 12:15:00.106706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9609 12:15:00.109808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9610 12:15:00.116521 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9611 12:15:00.119450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9612 12:15:00.122939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9613 12:15:00.129910 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9614 12:15:00.132685 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9615 12:15:00.139665 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9616 12:15:00.142673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9617 12:15:00.149047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9618 12:15:00.152765 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9619 12:15:00.155756 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9620 12:15:00.162366 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9621 12:15:00.165856 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9622 12:15:00.172074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9623 12:15:00.175573 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9624 12:15:00.182348 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9625 12:15:00.185552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9626 12:15:00.191596 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9627 12:15:00.195148 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9628 12:15:00.198514 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9629 12:15:00.205280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9630 12:15:00.208227 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9631 12:15:00.215046 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9632 12:15:00.218316 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9633 12:15:00.224329 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9634 12:15:00.227951 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9635 12:15:00.231430 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9636 12:15:00.237721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9637 12:15:00.241177 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9638 12:15:00.247612 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9639 12:15:00.251087 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9640 12:15:00.257696 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9641 12:15:00.260644 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9642 12:15:00.264146 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9643 12:15:00.270933 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9644 12:15:00.274060 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9645 12:15:00.280929 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9646 12:15:00.283960 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9647 12:15:00.290654 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9648 12:15:00.293896 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9649 12:15:00.296845 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9650 12:15:00.303507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9651 12:15:00.306544 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9652 12:15:00.313431 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9653 12:15:00.316413 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9654 12:15:00.323083 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9655 12:15:00.326734 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9656 12:15:00.329918 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9657 12:15:00.332952 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9658 12:15:00.339921 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9659 12:15:00.342778 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9660 12:15:00.346421 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9661 12:15:00.353399 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9662 12:15:00.356158 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9663 12:15:00.359298 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9664 12:15:00.366372 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9665 12:15:00.369488 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9666 12:15:00.372948 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9667 12:15:00.379105 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9668 12:15:00.382556 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9669 12:15:00.389293 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9670 12:15:00.392182 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9671 12:15:00.396059 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9672 12:15:00.401885 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9673 12:15:00.405888 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9674 12:15:00.408847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9675 12:15:00.415218 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9676 12:15:00.418877 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9677 12:15:00.425082 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9678 12:15:00.428564 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9679 12:15:00.431674 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9680 12:15:00.438416 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9681 12:15:00.441859 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9682 12:15:00.448563 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9683 12:15:00.451903 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9684 12:15:00.454904 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9685 12:15:00.461627 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9686 12:15:00.464591 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9687 12:15:00.467747 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9688 12:15:00.474579 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9689 12:15:00.477872 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9690 12:15:00.484606 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9691 12:15:00.487695 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9692 12:15:00.491259 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9693 12:15:00.497442 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9694 12:15:00.501001 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9695 12:15:00.504219 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9696 12:15:00.507775 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9697 12:15:00.514063 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9698 12:15:00.517590 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9699 12:15:00.520834 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9700 12:15:00.523875 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9701 12:15:00.530591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9702 12:15:00.534292 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9703 12:15:00.537283 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9704 12:15:00.540260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9705 12:15:00.546821 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9706 12:15:00.550311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9707 12:15:00.553370 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9708 12:15:00.559869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9709 12:15:00.563635 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9710 12:15:00.569656 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9711 12:15:00.573508 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9712 12:15:00.579473 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9713 12:15:00.583217 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9714 12:15:00.586417 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9715 12:15:00.593026 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9716 12:15:00.596447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9717 12:15:00.602715 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9718 12:15:00.606352 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9719 12:15:00.612831 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9720 12:15:00.615999 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9721 12:15:00.618963 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9722 12:15:00.625922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9723 12:15:00.629231 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9724 12:15:00.636017 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9725 12:15:00.639132 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9726 12:15:00.642122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9727 12:15:00.649122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9728 12:15:00.652495 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9729 12:15:00.658803 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9730 12:15:00.662351 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9731 12:15:00.665413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9732 12:15:00.671972 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9733 12:15:00.675176 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9734 12:15:00.681958 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9735 12:15:00.685000 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9736 12:15:00.691568 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9737 12:15:00.695255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9738 12:15:00.701524 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9739 12:15:00.704676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9740 12:15:00.708380 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9741 12:15:00.714505 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9742 12:15:00.718197 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9743 12:15:00.724288 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9744 12:15:00.728083 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9745 12:15:00.730956 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9746 12:15:00.737643 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9747 12:15:00.740718 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9748 12:15:00.747230 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9749 12:15:00.750671 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9750 12:15:00.756841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9751 12:15:00.760338 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9752 12:15:00.763831 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9753 12:15:00.770248 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9754 12:15:00.773896 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9755 12:15:00.779928 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9756 12:15:00.783675 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9757 12:15:00.786761 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9758 12:15:00.793057 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9759 12:15:00.796189 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9760 12:15:00.803229 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9761 12:15:00.806210 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9762 12:15:00.812928 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9763 12:15:00.815944 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9764 12:15:00.819673 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9765 12:15:00.825783 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9766 12:15:00.829309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9767 12:15:00.835832 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9768 12:15:00.839035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9769 12:15:00.845826 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9770 12:15:00.848828 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9771 12:15:00.852503 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9772 12:15:00.858633 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9773 12:15:00.862297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9774 12:15:00.868340 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9775 12:15:00.871787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9776 12:15:00.878481 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9777 12:15:00.881607 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9778 12:15:00.885217 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9779 12:15:00.891764 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9780 12:15:00.894886 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9781 12:15:00.901726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9782 12:15:00.904664 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9783 12:15:00.911165 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9784 12:15:00.914862 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9785 12:15:00.921639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9786 12:15:00.924706 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9787 12:15:00.927810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9788 12:15:00.934579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9789 12:15:00.937636 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9790 12:15:00.944349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9791 12:15:00.947290 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9792 12:15:00.953908 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9793 12:15:00.957097 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9794 12:15:00.963790 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9795 12:15:00.966808 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9796 12:15:00.970298 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9797 12:15:00.976872 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9798 12:15:00.980232 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9799 12:15:00.986454 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9800 12:15:00.990206 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9801 12:15:00.996499 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9802 12:15:01.000167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9803 12:15:01.006856 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9804 12:15:01.009973 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9805 12:15:01.013359 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9806 12:15:01.019591 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9807 12:15:01.023079 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9808 12:15:01.029325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9809 12:15:01.033446 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9810 12:15:01.039584 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9811 12:15:01.043163 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9812 12:15:01.050040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9813 12:15:01.053016 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9814 12:15:01.059223 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9815 12:15:01.062856 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9816 12:15:01.066122 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9817 12:15:01.072843 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9818 12:15:01.076142 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9819 12:15:01.082675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9820 12:15:01.086185 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9821 12:15:01.092441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9822 12:15:01.095610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9823 12:15:01.102180 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9824 12:15:01.105869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9825 12:15:01.112438 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9826 12:15:01.115414 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9827 12:15:01.118722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9828 12:15:01.125459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9829 12:15:01.128549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9830 12:15:01.135194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9831 12:15:01.138426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9832 12:15:01.144794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9833 12:15:01.148574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9834 12:15:01.154682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9835 12:15:01.158283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9836 12:15:01.165091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9837 12:15:01.168284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9838 12:15:01.174516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9839 12:15:01.177982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9840 12:15:01.184700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9841 12:15:01.188154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9842 12:15:01.191180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9843 12:15:01.197895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9844 12:15:01.200925 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9845 12:15:01.207722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9846 12:15:01.211270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9847 12:15:01.218008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9848 12:15:01.220739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9849 12:15:01.227167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9850 12:15:01.230963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9851 12:15:01.237409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9852 12:15:01.243392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9853 12:15:01.247080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9854 12:15:01.253323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9855 12:15:01.256971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9856 12:15:01.263586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9857 12:15:01.266685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9858 12:15:01.273360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9859 12:15:01.276450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9860 12:15:01.280096 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9861 12:15:01.283032 INFO: [APUAPC] vio 0
9862 12:15:01.290077 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9863 12:15:01.293248 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9864 12:15:01.296852 INFO: [APUAPC] D0_APC_0: 0x400510
9865 12:15:01.299801 INFO: [APUAPC] D0_APC_1: 0x0
9866 12:15:01.302984 INFO: [APUAPC] D0_APC_2: 0x1540
9867 12:15:01.306618 INFO: [APUAPC] D0_APC_3: 0x0
9868 12:15:01.309757 INFO: [APUAPC] D1_APC_0: 0xffffffff
9869 12:15:01.312840 INFO: [APUAPC] D1_APC_1: 0xffffffff
9870 12:15:01.316437 INFO: [APUAPC] D1_APC_2: 0x3fffff
9871 12:15:01.319563 INFO: [APUAPC] D1_APC_3: 0x0
9872 12:15:01.322934 INFO: [APUAPC] D2_APC_0: 0xffffffff
9873 12:15:01.326018 INFO: [APUAPC] D2_APC_1: 0xffffffff
9874 12:15:01.329674 INFO: [APUAPC] D2_APC_2: 0x3fffff
9875 12:15:01.330160 INFO: [APUAPC] D2_APC_3: 0x0
9876 12:15:01.335965 INFO: [APUAPC] D3_APC_0: 0xffffffff
9877 12:15:01.339660 INFO: [APUAPC] D3_APC_1: 0xffffffff
9878 12:15:01.342865 INFO: [APUAPC] D3_APC_2: 0x3fffff
9879 12:15:01.343210 INFO: [APUAPC] D3_APC_3: 0x0
9880 12:15:01.349409 INFO: [APUAPC] D4_APC_0: 0xffffffff
9881 12:15:01.352535 INFO: [APUAPC] D4_APC_1: 0xffffffff
9882 12:15:01.355557 INFO: [APUAPC] D4_APC_2: 0x3fffff
9883 12:15:01.356028 INFO: [APUAPC] D4_APC_3: 0x0
9884 12:15:01.359119 INFO: [APUAPC] D5_APC_0: 0xffffffff
9885 12:15:01.365295 INFO: [APUAPC] D5_APC_1: 0xffffffff
9886 12:15:01.368800 INFO: [APUAPC] D5_APC_2: 0x3fffff
9887 12:15:01.368905 INFO: [APUAPC] D5_APC_3: 0x0
9888 12:15:01.371869 INFO: [APUAPC] D6_APC_0: 0xffffffff
9889 12:15:01.374888 INFO: [APUAPC] D6_APC_1: 0xffffffff
9890 12:15:01.378574 INFO: [APUAPC] D6_APC_2: 0x3fffff
9891 12:15:01.381755 INFO: [APUAPC] D6_APC_3: 0x0
9892 12:15:01.385313 INFO: [APUAPC] D7_APC_0: 0xffffffff
9893 12:15:01.388195 INFO: [APUAPC] D7_APC_1: 0xffffffff
9894 12:15:01.391753 INFO: [APUAPC] D7_APC_2: 0x3fffff
9895 12:15:01.395223 INFO: [APUAPC] D7_APC_3: 0x0
9896 12:15:01.398067 INFO: [APUAPC] D8_APC_0: 0xffffffff
9897 12:15:01.401227 INFO: [APUAPC] D8_APC_1: 0xffffffff
9898 12:15:01.404885 INFO: [APUAPC] D8_APC_2: 0x3fffff
9899 12:15:01.407963 INFO: [APUAPC] D8_APC_3: 0x0
9900 12:15:01.411632 INFO: [APUAPC] D9_APC_0: 0xffffffff
9901 12:15:01.414596 INFO: [APUAPC] D9_APC_1: 0xffffffff
9902 12:15:01.417707 INFO: [APUAPC] D9_APC_2: 0x3fffff
9903 12:15:01.421159 INFO: [APUAPC] D9_APC_3: 0x0
9904 12:15:01.424934 INFO: [APUAPC] D10_APC_0: 0xffffffff
9905 12:15:01.427796 INFO: [APUAPC] D10_APC_1: 0xffffffff
9906 12:15:01.430882 INFO: [APUAPC] D10_APC_2: 0x3fffff
9907 12:15:01.434465 INFO: [APUAPC] D10_APC_3: 0x0
9908 12:15:01.437865 INFO: [APUAPC] D11_APC_0: 0xffffffff
9909 12:15:01.440941 INFO: [APUAPC] D11_APC_1: 0xffffffff
9910 12:15:01.444638 INFO: [APUAPC] D11_APC_2: 0x3fffff
9911 12:15:01.447573 INFO: [APUAPC] D11_APC_3: 0x0
9912 12:15:01.450675 INFO: [APUAPC] D12_APC_0: 0xffffffff
9913 12:15:01.454549 INFO: [APUAPC] D12_APC_1: 0xffffffff
9914 12:15:01.457626 INFO: [APUAPC] D12_APC_2: 0x3fffff
9915 12:15:01.460680 INFO: [APUAPC] D12_APC_3: 0x0
9916 12:15:01.464308 INFO: [APUAPC] D13_APC_0: 0xffffffff
9917 12:15:01.470953 INFO: [APUAPC] D13_APC_1: 0xffffffff
9918 12:15:01.473969 INFO: [APUAPC] D13_APC_2: 0x3fffff
9919 12:15:01.474058 INFO: [APUAPC] D13_APC_3: 0x0
9920 12:15:01.480185 INFO: [APUAPC] D14_APC_0: 0xffffffff
9921 12:15:01.483791 INFO: [APUAPC] D14_APC_1: 0xffffffff
9922 12:15:01.487559 INFO: [APUAPC] D14_APC_2: 0x3fffff
9923 12:15:01.487666 INFO: [APUAPC] D14_APC_3: 0x0
9924 12:15:01.493755 INFO: [APUAPC] D15_APC_0: 0xffffffff
9925 12:15:01.496782 INFO: [APUAPC] D15_APC_1: 0xffffffff
9926 12:15:01.500299 INFO: [APUAPC] D15_APC_2: 0x3fffff
9927 12:15:01.503423 INFO: [APUAPC] D15_APC_3: 0x0
9928 12:15:01.503552 INFO: [APUAPC] APC_CON: 0x4
9929 12:15:01.507229 INFO: [NOCDAPC] D0_APC_0: 0x0
9930 12:15:01.510145 INFO: [NOCDAPC] D0_APC_1: 0x0
9931 12:15:01.513276 INFO: [NOCDAPC] D1_APC_0: 0x0
9932 12:15:01.516999 INFO: [NOCDAPC] D1_APC_1: 0xfff
9933 12:15:01.520226 INFO: [NOCDAPC] D2_APC_0: 0x0
9934 12:15:01.523153 INFO: [NOCDAPC] D2_APC_1: 0xfff
9935 12:15:01.526584 INFO: [NOCDAPC] D3_APC_0: 0x0
9936 12:15:01.530133 INFO: [NOCDAPC] D3_APC_1: 0xfff
9937 12:15:01.533491 INFO: [NOCDAPC] D4_APC_0: 0x0
9938 12:15:01.536531 INFO: [NOCDAPC] D4_APC_1: 0xfff
9939 12:15:01.536858 INFO: [NOCDAPC] D5_APC_0: 0x0
9940 12:15:01.540007 INFO: [NOCDAPC] D5_APC_1: 0xfff
9941 12:15:01.543362 INFO: [NOCDAPC] D6_APC_0: 0x0
9942 12:15:01.546806 INFO: [NOCDAPC] D6_APC_1: 0xfff
9943 12:15:01.549992 INFO: [NOCDAPC] D7_APC_0: 0x0
9944 12:15:01.553039 INFO: [NOCDAPC] D7_APC_1: 0xfff
9945 12:15:01.556584 INFO: [NOCDAPC] D8_APC_0: 0x0
9946 12:15:01.559749 INFO: [NOCDAPC] D8_APC_1: 0xfff
9947 12:15:01.563359 INFO: [NOCDAPC] D9_APC_0: 0x0
9948 12:15:01.566425 INFO: [NOCDAPC] D9_APC_1: 0xfff
9949 12:15:01.569945 INFO: [NOCDAPC] D10_APC_0: 0x0
9950 12:15:01.572944 INFO: [NOCDAPC] D10_APC_1: 0xfff
9951 12:15:01.573377 INFO: [NOCDAPC] D11_APC_0: 0x0
9952 12:15:01.576149 INFO: [NOCDAPC] D11_APC_1: 0xfff
9953 12:15:01.579798 INFO: [NOCDAPC] D12_APC_0: 0x0
9954 12:15:01.582768 INFO: [NOCDAPC] D12_APC_1: 0xfff
9955 12:15:01.585852 INFO: [NOCDAPC] D13_APC_0: 0x0
9956 12:15:01.589324 INFO: [NOCDAPC] D13_APC_1: 0xfff
9957 12:15:01.593023 INFO: [NOCDAPC] D14_APC_0: 0x0
9958 12:15:01.595861 INFO: [NOCDAPC] D14_APC_1: 0xfff
9959 12:15:01.598806 INFO: [NOCDAPC] D15_APC_0: 0x0
9960 12:15:01.602409 INFO: [NOCDAPC] D15_APC_1: 0xfff
9961 12:15:01.605922 INFO: [NOCDAPC] APC_CON: 0x4
9962 12:15:01.608805 INFO: [APUAPC] set_apusys_apc done
9963 12:15:01.612578 INFO: [DEVAPC] devapc_init done
9964 12:15:01.615594 INFO: GICv3 without legacy support detected.
9965 12:15:01.618476 INFO: ARM GICv3 driver initialized in EL3
9966 12:15:01.621863 INFO: Maximum SPI INTID supported: 639
9967 12:15:01.628680 INFO: BL31: Initializing runtime services
9968 12:15:01.631966 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9969 12:15:01.635290 INFO: SPM: enable CPC mode
9970 12:15:01.641937 INFO: mcdi ready for mcusys-off-idle and system suspend
9971 12:15:01.645528 INFO: BL31: Preparing for EL3 exit to normal world
9972 12:15:01.649010 INFO: Entry point address = 0x80000000
9973 12:15:01.651749 INFO: SPSR = 0x8
9974 12:15:01.657866
9975 12:15:01.658293
9976 12:15:01.658638
9977 12:15:01.660830 Starting depthcharge on Spherion...
9978 12:15:01.661381
9979 12:15:01.661922 Wipe memory regions:
9980 12:15:01.662262
9981 12:15:01.665163 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9982 12:15:01.665774 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9983 12:15:01.666225 Setting prompt string to ['asurada:']
9984 12:15:01.666799 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9985 12:15:01.667759 [0x00000040000000, 0x00000054600000)
9986 12:15:01.785945
9987 12:15:01.786113 [0x00000054660000, 0x00000080000000)
9988 12:15:02.047001
9989 12:15:02.047544 [0x000000821a7280, 0x000000ffe64000)
9990 12:15:02.791677
9991 12:15:02.792394 [0x00000100000000, 0x00000240000000)
9992 12:15:04.682211
9993 12:15:04.685010 Initializing XHCI USB controller at 0x11200000.
9994 12:15:05.723157
9995 12:15:05.726050 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9996 12:15:05.726483
9997 12:15:05.726823
9998 12:15:05.727155
9999 12:15:05.727940 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10001 12:15:05.829184 asurada: tftpboot 192.168.201.1 10605425/tftp-deploy-3m5mim6z/kernel/image.itb 10605425/tftp-deploy-3m5mim6z/kernel/cmdline
10002 12:15:05.829806 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10003 12:15:05.830250 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10004 12:15:05.834876 tftpboot 192.168.201.1 10605425/tftp-deploy-3m5mim6z/kernel/image.ittp-deploy-3m5mim6z/kernel/cmdline
10005 12:15:05.835318
10006 12:15:05.835663 Waiting for link
10007 12:15:05.995626
10008 12:15:05.996223 R8152: Initializing
10009 12:15:05.996582
10010 12:15:05.998773 Version 6 (ocp_data = 5c30)
10011 12:15:05.999219
10012 12:15:06.002045 R8152: Done initializing
10013 12:15:06.002489
10014 12:15:06.002930 Adding net device
10015 12:15:07.870054
10016 12:15:07.870693 done.
10017 12:15:07.871175
10018 12:15:07.871514 MAC: 00:24:32:30:7c:7b
10019 12:15:07.871829
10020 12:15:07.873159 Sending DHCP discover... done.
10021 12:15:07.873589
10022 12:15:07.876328 Waiting for reply... done.
10023 12:15:07.876899
10024 12:15:07.879950 Sending DHCP request... done.
10025 12:15:07.880454
10026 12:15:07.880799 Waiting for reply... done.
10027 12:15:07.883080
10028 12:15:07.883510 My ip is 192.168.201.14
10029 12:15:07.883857
10030 12:15:07.886631 The DHCP server ip is 192.168.201.1
10031 12:15:07.887091
10032 12:15:07.889535 TFTP server IP predefined by user: 192.168.201.1
10033 12:15:07.889970
10034 12:15:07.896310 Bootfile predefined by user: 10605425/tftp-deploy-3m5mim6z/kernel/image.itb
10035 12:15:07.896747
10036 12:15:07.899821 Sending tftp read request... done.
10037 12:15:07.900365
10038 12:15:07.908259 Waiting for the transfer...
10039 12:15:07.908730
10040 12:15:08.566447 00000000 ################################################################
10041 12:15:08.566967
10042 12:15:09.164195 00080000 ################################################################
10043 12:15:09.164550
10044 12:15:09.777764 00100000 ################################################################
10045 12:15:09.777912
10046 12:15:10.375297 00180000 ################################################################
10047 12:15:10.375431
10048 12:15:10.969632 00200000 ################################################################
10049 12:15:10.969767
10050 12:15:11.558785 00280000 ################################################################
10051 12:15:11.558950
10052 12:15:12.175519 00300000 ################################################################
10053 12:15:12.175670
10054 12:15:12.759589 00380000 ################################################################
10055 12:15:12.759725
10056 12:15:13.307141 00400000 ################################################################
10057 12:15:13.307285
10058 12:15:13.873193 00480000 ################################################################
10059 12:15:13.873332
10060 12:15:14.466550 00500000 ################################################################
10061 12:15:14.466705
10062 12:15:15.069815 00580000 ################################################################
10063 12:15:15.069982
10064 12:15:15.609276 00600000 ################################################################
10065 12:15:15.609438
10066 12:15:16.160662 00680000 ################################################################
10067 12:15:16.160806
10068 12:15:16.690890 00700000 ################################################################
10069 12:15:16.691093
10070 12:15:17.229881 00780000 ################################################################
10071 12:15:17.230057
10072 12:15:17.772199 00800000 ################################################################
10073 12:15:17.772440
10074 12:15:18.313434 00880000 ################################################################
10075 12:15:18.313594
10076 12:15:18.841561 00900000 ################################################################
10077 12:15:18.841730
10078 12:15:19.371564 00980000 ################################################################
10079 12:15:19.371732
10080 12:15:19.897185 00a00000 ################################################################
10081 12:15:19.897354
10082 12:15:20.414814 00a80000 ################################################################
10083 12:15:20.414974
10084 12:15:20.933032 00b00000 ################################################################
10085 12:15:20.933174
10086 12:15:21.452226 00b80000 ################################################################
10087 12:15:21.452370
10088 12:15:21.970711 00c00000 ################################################################
10089 12:15:21.970863
10090 12:15:22.491848 00c80000 ################################################################
10091 12:15:22.491997
10092 12:15:23.060500 00d00000 ################################################################
10093 12:15:23.060669
10094 12:15:23.584687 00d80000 ################################################################
10095 12:15:23.584866
10096 12:15:24.106420 00e00000 ################################################################
10097 12:15:24.106561
10098 12:15:24.665028 00e80000 ################################################################
10099 12:15:24.665170
10100 12:15:25.189126 00f00000 ################################################################
10101 12:15:25.189270
10102 12:15:25.710535 00f80000 ################################################################
10103 12:15:25.710716
10104 12:15:26.241930 01000000 ################################################################
10105 12:15:26.242079
10106 12:15:26.779489 01080000 ################################################################
10107 12:15:26.779662
10108 12:15:27.358588 01100000 ################################################################
10109 12:15:27.358734
10110 12:15:27.932725 01180000 ################################################################
10111 12:15:27.932884
10112 12:15:28.505301 01200000 ################################################################
10113 12:15:28.505435
10114 12:15:29.062890 01280000 ################################################################
10115 12:15:29.063029
10116 12:15:29.658767 01300000 ################################################################
10117 12:15:29.658953
10118 12:15:30.322385 01380000 ################################################################
10119 12:15:30.322550
10120 12:15:30.924562 01400000 ################################################################
10121 12:15:30.925070
10122 12:15:31.611311 01480000 ################################################################
10123 12:15:31.611880
10124 12:15:32.301112 01500000 ################################################################
10125 12:15:32.301633
10126 12:15:32.989039 01580000 ################################################################
10127 12:15:32.989713
10128 12:15:33.625442 01600000 ################################################################
10129 12:15:33.625967
10130 12:15:34.313945 01680000 ################################################################
10131 12:15:34.314454
10132 12:15:34.915742 01700000 ################################################################
10133 12:15:34.915881
10134 12:15:35.510148 01780000 ################################################################
10135 12:15:35.510706
10136 12:15:36.187538 01800000 ################################################################
10137 12:15:36.188067
10138 12:15:36.797591 01880000 ################################################################
10139 12:15:36.797733
10140 12:15:37.445511 01900000 ################################################################
10141 12:15:37.446018
10142 12:15:37.999723 01980000 ################################################################
10143 12:15:37.999861
10144 12:15:38.591200 01a00000 ################################################################
10145 12:15:38.591713
10146 12:15:39.241034 01a80000 ################################################################
10147 12:15:39.241172
10148 12:15:39.854925 01b00000 ################################################################
10149 12:15:39.855429
10150 12:15:40.490389 01b80000 ################################################################
10151 12:15:40.490568
10152 12:15:41.054097 01c00000 ################################################################
10153 12:15:41.054260
10154 12:15:41.704567 01c80000 ################################################################
10155 12:15:41.705118
10156 12:15:42.385839 01d00000 ################################################################
10157 12:15:42.386405
10158 12:15:43.026779 01d80000 ################################################################
10159 12:15:43.026921
10160 12:15:43.655045 01e00000 ################################################################
10161 12:15:43.655730
10162 12:15:44.299212 01e80000 ################################################################
10163 12:15:44.299377
10164 12:15:44.944145 01f00000 ################################################################
10165 12:15:44.944667
10166 12:15:45.593198 01f80000 ################################################################
10167 12:15:45.593826
10168 12:15:46.262495 02000000 ################################################################
10169 12:15:46.262991
10170 12:15:46.809693 02080000 ################################################################
10171 12:15:46.809860
10172 12:15:47.382185 02100000 ################################################################
10173 12:15:47.382321
10174 12:15:47.929938 02180000 ################################################################
10175 12:15:47.930074
10176 12:15:48.462824 02200000 ################################################################
10177 12:15:48.462988
10178 12:15:49.071018 02280000 ################################################################
10179 12:15:49.071540
10180 12:15:49.764154 02300000 ################################################################
10181 12:15:49.764648
10182 12:15:50.461109 02380000 ################################################################
10183 12:15:50.461643
10184 12:15:51.166517 02400000 ################################################################
10185 12:15:51.167054
10186 12:15:51.861619 02480000 ################################################################
10187 12:15:51.861769
10188 12:15:52.546510 02500000 ################################################################
10189 12:15:52.547025
10190 12:15:53.249113 02580000 ################################################################
10191 12:15:53.249641
10192 12:15:53.952254 02600000 ################################################################
10193 12:15:53.952833
10194 12:15:54.584990 02680000 ################################################################
10195 12:15:54.585158
10196 12:15:55.182685 02700000 ################################################################
10197 12:15:55.182831
10198 12:15:55.816016 02780000 ################################################################
10199 12:15:55.816664
10200 12:15:56.369804 02800000 ################################################################
10201 12:15:56.369984
10202 12:15:56.910108 02880000 ################################################################
10203 12:15:56.910282
10204 12:15:57.477191 02900000 ################################################################
10205 12:15:57.477340
10206 12:15:58.057797 02980000 ################################################################
10207 12:15:58.058017
10208 12:15:58.750502 02a00000 ################################################################
10209 12:15:58.751185
10210 12:15:59.415156 02a80000 ################################################################
10211 12:15:59.415664
10212 12:16:00.111640 02b00000 ################################################################
10213 12:16:00.112194
10214 12:16:00.811027 02b80000 ################################################################
10215 12:16:00.811336
10216 12:16:01.509266 02c00000 ################################################################
10217 12:16:01.509785
10218 12:16:02.208806 02c80000 ################################################################
10219 12:16:02.209315
10220 12:16:02.919943 02d00000 ################################################################
10221 12:16:02.920547
10222 12:16:03.622272 02d80000 ################################################################
10223 12:16:03.622491
10224 12:16:04.242313 02e00000 ################################################################
10225 12:16:04.242495
10226 12:16:04.776592 02e80000 ################################################################
10227 12:16:04.776771
10228 12:16:05.319704 02f00000 ################################################################
10229 12:16:05.319880
10230 12:16:06.001414 02f80000 ################################################################
10231 12:16:06.001930
10232 12:16:06.655974 03000000 ################################################################
10233 12:16:06.656522
10234 12:16:07.252938 03080000 ################################################################
10235 12:16:07.253073
10236 12:16:07.794201 03100000 ################################################################
10237 12:16:07.794374
10238 12:16:08.329236 03180000 ################################################################
10239 12:16:08.329375
10240 12:16:08.870956 03200000 ################################################################
10241 12:16:08.871094
10242 12:16:09.409623 03280000 ################################################################
10243 12:16:09.409782
10244 12:16:09.931647 03300000 ################################################################
10245 12:16:09.931791
10246 12:16:10.473219 03380000 ################################################################
10247 12:16:10.473363
10248 12:16:11.142402 03400000 ################################################################
10249 12:16:11.142558
10250 12:16:11.802836 03480000 ################################################################
10251 12:16:11.802990
10252 12:16:12.335407 03500000 ################################################################
10253 12:16:12.335578
10254 12:16:12.900753 03580000 ################################################################
10255 12:16:12.900892
10256 12:16:13.449759 03600000 ################################################################
10257 12:16:13.449907
10258 12:16:13.983858 03680000 ################################################################
10259 12:16:13.983993
10260 12:16:14.520299 03700000 ################################################################
10261 12:16:14.520437
10262 12:16:15.060395 03780000 ################################################################
10263 12:16:15.060534
10264 12:16:15.609612 03800000 ################################################################
10265 12:16:15.609785
10266 12:16:16.155609 03880000 ################################################################
10267 12:16:16.155746
10268 12:16:16.700234 03900000 ################################################################
10269 12:16:16.700380
10270 12:16:17.239165 03980000 ################################################################
10271 12:16:17.239338
10272 12:16:17.791994 03a00000 ################################################################
10273 12:16:17.792194
10274 12:16:18.320577 03a80000 ################################################################
10275 12:16:18.320712
10276 12:16:18.859146 03b00000 ################################################################
10277 12:16:18.859330
10278 12:16:19.420003 03b80000 ################################################################
10279 12:16:19.420168
10280 12:16:20.003724 03c00000 ################################################################
10281 12:16:20.003871
10282 12:16:20.535124 03c80000 ################################################################
10283 12:16:20.535268
10284 12:16:21.060934 03d00000 ################################################################
10285 12:16:21.061071
10286 12:16:21.586203 03d80000 ################################################################
10287 12:16:21.586398
10288 12:16:22.125298 03e00000 ################################################################
10289 12:16:22.125435
10290 12:16:22.724482 03e80000 ################################################################
10291 12:16:22.724659
10292 12:16:23.296222 03f00000 ################################################################
10293 12:16:23.296393
10294 12:16:23.846108 03f80000 ################################################################
10295 12:16:23.846281
10296 12:16:24.393890 04000000 ################################################################
10297 12:16:24.394065
10298 12:16:24.945783 04080000 ################################################################
10299 12:16:24.945959
10300 12:16:25.487989 04100000 ################################################################
10301 12:16:25.488151
10302 12:16:26.066598 04180000 ################################################################
10303 12:16:26.066739
10304 12:16:26.649086 04200000 ################################################################
10305 12:16:26.649232
10306 12:16:27.222969 04280000 ################################################################
10307 12:16:27.223140
10308 12:16:27.789512 04300000 ################################################################
10309 12:16:27.789653
10310 12:16:28.441821 04380000 ################################################################
10311 12:16:28.442318
10312 12:16:29.133417 04400000 ################################################################
10313 12:16:29.133973
10314 12:16:29.819854 04480000 ################################################################
10315 12:16:29.820360
10316 12:16:30.486590 04500000 ################################################################
10317 12:16:30.487112
10318 12:16:31.199368 04580000 ################################################################
10319 12:16:31.199885
10320 12:16:31.894682 04600000 ################################################################
10321 12:16:31.895206
10322 12:16:32.611326 04680000 ################################################################
10323 12:16:32.611835
10324 12:16:33.327403 04700000 ################################################################
10325 12:16:33.327921
10326 12:16:34.034231 04780000 ################################################################
10327 12:16:34.034832
10328 12:16:34.730776 04800000 ################################################################
10329 12:16:34.731280
10330 12:16:35.384459 04880000 ################################################################
10331 12:16:35.384598
10332 12:16:36.035133 04900000 ################################################################
10333 12:16:36.035639
10334 12:16:36.714868 04980000 ################################################################
10335 12:16:36.715382
10336 12:16:37.399011 04a00000 ################################################################
10337 12:16:37.399638
10338 12:16:38.083839 04a80000 ################################################################
10339 12:16:38.084386
10340 12:16:38.774161 04b00000 ################################################################
10341 12:16:38.774841
10342 12:16:39.448248 04b80000 ################################################################
10343 12:16:39.448917
10344 12:16:39.996293 04c00000 ################################################################
10345 12:16:39.996454
10346 12:16:40.545032 04c80000 ################################################################
10347 12:16:40.545167
10348 12:16:41.070664 04d00000 ################################################################
10349 12:16:41.070805
10350 12:16:41.618009 04d80000 ################################################################
10351 12:16:41.618143
10352 12:16:42.169135 04e00000 ################################################################
10353 12:16:42.169275
10354 12:16:42.737245 04e80000 ################################################################
10355 12:16:42.737386
10356 12:16:43.286192 04f00000 ################################################################
10357 12:16:43.286372
10358 12:16:43.819308 04f80000 ################################################################
10359 12:16:43.819441
10360 12:16:44.375367 05000000 ################################################################
10361 12:16:44.375511
10362 12:16:44.948238 05080000 ################################################################
10363 12:16:44.948406
10364 12:16:45.486454 05100000 ################################################################
10365 12:16:45.486588
10366 12:16:46.020291 05180000 ################################################################
10367 12:16:46.020452
10368 12:16:46.550240 05200000 ################################################################
10369 12:16:46.550375
10370 12:16:47.080763 05280000 ################################################################
10371 12:16:47.080903
10372 12:16:47.628812 05300000 ################################################################
10373 12:16:47.628955
10374 12:16:48.188413 05380000 ################################################################
10375 12:16:48.188575
10376 12:16:48.724126 05400000 ################################################################
10377 12:16:48.724294
10378 12:16:49.288113 05480000 ################################################################
10379 12:16:49.288297
10380 12:16:49.825982 05500000 ################################################################
10381 12:16:49.826125
10382 12:16:50.355024 05580000 ################################################################
10383 12:16:50.355184
10384 12:16:50.886994 05600000 ################################################################
10385 12:16:50.887135
10386 12:16:51.452829 05680000 ################################################################
10387 12:16:51.452965
10388 12:16:52.025293 05700000 ################################################################
10389 12:16:52.025468
10390 12:16:52.571914 05780000 ################################################################
10391 12:16:52.572089
10392 12:16:53.091144 05800000 ################################################################
10393 12:16:53.091283
10394 12:16:53.624333 05880000 ################################################################
10395 12:16:53.624513
10396 12:16:54.159656 05900000 ################################################################
10397 12:16:54.159826
10398 12:16:54.694589 05980000 ################################################################
10399 12:16:54.694732
10400 12:16:55.233040 05a00000 ################################################################
10401 12:16:55.233215
10402 12:16:55.765780 05a80000 ################################################################
10403 12:16:55.765918
10404 12:16:56.307021 05b00000 ################################################################
10405 12:16:56.307182
10406 12:16:56.849530 05b80000 ################################################################
10407 12:16:56.849672
10408 12:16:57.388367 05c00000 ################################################################
10409 12:16:57.388520
10410 12:16:57.925898 05c80000 ################################################################
10411 12:16:57.926048
10412 12:16:58.463108 05d00000 ################################################################
10413 12:16:58.463259
10414 12:16:58.999783 05d80000 ################################################################
10415 12:16:58.999956
10416 12:16:59.528341 05e00000 ################################################################
10417 12:16:59.528484
10418 12:17:00.090835 05e80000 ################################################################
10419 12:17:00.090991
10420 12:17:00.658268 05f00000 ################################################################
10421 12:17:00.658419
10422 12:17:01.197981 05f80000 ################################################################
10423 12:17:01.198131
10424 12:17:01.730763 06000000 ################################################################
10425 12:17:01.730912
10426 12:17:02.253767 06080000 ################################################################
10427 12:17:02.253950
10428 12:17:02.783577 06100000 ################################################################
10429 12:17:02.783723
10430 12:17:03.300359 06180000 ################################################################
10431 12:17:03.300519
10432 12:17:03.823506 06200000 ################################################################
10433 12:17:03.823638
10434 12:17:04.376186 06280000 ################################################################
10435 12:17:04.376333
10436 12:17:04.934419 06300000 ################################################################
10437 12:17:04.934559
10438 12:17:05.485400 06380000 ################################################################
10439 12:17:05.485542
10440 12:17:06.046490 06400000 ################################################################
10441 12:17:06.046632
10442 12:17:06.612240 06480000 ################################################################
10443 12:17:06.612378
10444 12:17:07.179096 06500000 ################################################################
10445 12:17:07.179235
10446 12:17:07.759689 06580000 ################################################################
10447 12:17:07.759831
10448 12:17:08.359691 06600000 ################################################################
10449 12:17:08.360239
10450 12:17:09.049487 06680000 ################################################################
10451 12:17:09.049995
10452 12:17:09.414731 06700000 ################################## done.
10453 12:17:09.415234
10454 12:17:09.418176 The bootfile was 108275214 bytes long.
10455 12:17:09.418683
10456 12:17:09.421625 Sending tftp read request... done.
10457 12:17:09.422134
10458 12:17:09.424515 Waiting for the transfer...
10459 12:17:09.424943
10460 12:17:09.428018 00000000 # done.
10461 12:17:09.428494
10462 12:17:09.435030 Command line loaded dynamically from TFTP file: 10605425/tftp-deploy-3m5mim6z/kernel/cmdline
10463 12:17:09.435474
10464 12:17:09.447686 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10465 12:17:09.448147
10466 12:17:09.448491 Loading FIT.
10467 12:17:09.448809
10468 12:17:09.451021 Image ramdisk-1 has 98131634 bytes.
10469 12:17:09.451448
10470 12:17:09.454399 Image fdt-1 has 46924 bytes.
10471 12:17:09.454824
10472 12:17:09.457913 Image kernel-1 has 10094623 bytes.
10473 12:17:09.458342
10474 12:17:09.464190 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10475 12:17:09.464623
10476 12:17:09.483932 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10477 12:17:09.484407
10478 12:17:09.487339 Choosing best match conf-1 for compat google,spherion-rev2.
10479 12:17:09.492879
10480 12:17:09.497297 Connected to device vid:did:rid of 1ae0:0028:00
10481 12:17:09.505481
10482 12:17:09.508808 tpm_get_response: command 0x17b, return code 0x0
10483 12:17:09.509325
10484 12:17:09.511887 ec_init: CrosEC protocol v3 supported (256, 248)
10485 12:17:09.515902
10486 12:17:09.519302 tpm_cleanup: add release locality here.
10487 12:17:09.519740
10488 12:17:09.520241 Shutting down all USB controllers.
10489 12:17:09.522713
10490 12:17:09.523149 Removing current net device
10491 12:17:09.523571
10492 12:17:09.529502 Exiting depthcharge with code 4 at timestamp: 157074405
10493 12:17:09.529975
10494 12:17:09.532359 LZMA decompressing kernel-1 to 0x821a6718
10495 12:17:09.532867
10496 12:17:09.535848 LZMA decompressing kernel-1 to 0x40000000
10497 12:17:10.804393
10498 12:17:10.804891 jumping to kernel
10499 12:17:10.806605 end: 2.2.4 bootloader-commands (duration 00:02:09) [common]
10500 12:17:10.807138 start: 2.2.5 auto-login-action (timeout 00:02:16) [common]
10501 12:17:10.807529 Setting prompt string to ['Linux version [0-9]']
10502 12:17:10.807879 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10503 12:17:10.808319 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10504 12:17:10.886436
10505 12:17:10.889684 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10506 12:17:10.893197 start: 2.2.5.1 login-action (timeout 00:02:16) [common]
10507 12:17:10.893662 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10508 12:17:10.894103 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10509 12:17:10.894494 Using line separator: #'\n'#
10510 12:17:10.894843 No login prompt set.
10511 12:17:10.895287 Parsing kernel messages
10512 12:17:10.895597 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10513 12:17:10.896155 [login-action] Waiting for messages, (timeout 00:02:16)
10514 12:17:10.912169 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10515 12:17:10.915594 [ 0.000000] random: crng init done
10516 12:17:10.921795 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10517 12:17:10.925342 [ 0.000000] efi: UEFI not found.
10518 12:17:10.932090 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10519 12:17:10.938485 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10520 12:17:10.948292 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10521 12:17:10.958297 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10522 12:17:10.964609 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10523 12:17:10.971350 [ 0.000000] printk: bootconsole [mtk8250] enabled
10524 12:17:10.978185 [ 0.000000] NUMA: No NUMA configuration found
10525 12:17:10.984819 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10526 12:17:10.988133 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10527 12:17:10.991184 [ 0.000000] Zone ranges:
10528 12:17:10.997772 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10529 12:17:11.001300 [ 0.000000] DMA32 empty
10530 12:17:11.007687 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10531 12:17:11.011004 [ 0.000000] Movable zone start for each node
10532 12:17:11.014778 [ 0.000000] Early memory node ranges
10533 12:17:11.020600 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10534 12:17:11.027444 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10535 12:17:11.033797 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10536 12:17:11.040775 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10537 12:17:11.047476 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10538 12:17:11.053879 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10539 12:17:11.110300 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10540 12:17:11.116653 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10541 12:17:11.123664 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10542 12:17:11.126817 [ 0.000000] psci: probing for conduit method from DT.
10543 12:17:11.133119 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10544 12:17:11.136512 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10545 12:17:11.142961 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10546 12:17:11.146372 [ 0.000000] psci: SMC Calling Convention v1.2
10547 12:17:11.152687 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10548 12:17:11.156095 [ 0.000000] Detected VIPT I-cache on CPU0
10549 12:17:11.162625 [ 0.000000] CPU features: detected: GIC system register CPU interface
10550 12:17:11.169418 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10551 12:17:11.175904 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10552 12:17:11.182628 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10553 12:17:11.192181 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10554 12:17:11.198812 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10555 12:17:11.202069 [ 0.000000] alternatives: applying boot alternatives
10556 12:17:11.208800 [ 0.000000] Fallback order for Node 0: 0
10557 12:17:11.215619 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10558 12:17:11.219118 [ 0.000000] Policy zone: Normal
10559 12:17:11.228782 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10560 12:17:11.242026 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10561 12:17:11.252312 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10562 12:17:11.262310 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10563 12:17:11.268857 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10564 12:17:11.271595 <6>[ 0.000000] software IO TLB: area num 8.
10565 12:17:11.328020 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10566 12:17:11.476934 <6>[ 0.000000] Memory: 7877108K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 475660K reserved, 32768K cma-reserved)
10567 12:17:11.484079 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10568 12:17:11.490254 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10569 12:17:11.493868 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10570 12:17:11.500483 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10571 12:17:11.507206 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10572 12:17:11.509924 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10573 12:17:11.520122 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10574 12:17:11.527074 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10575 12:17:11.533696 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10576 12:17:11.539862 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10577 12:17:11.543389 <6>[ 0.000000] GICv3: 608 SPIs implemented
10578 12:17:11.547128 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10579 12:17:11.553018 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10580 12:17:11.556646 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10581 12:17:11.563059 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10582 12:17:11.576204 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10583 12:17:11.589656 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10584 12:17:11.595986 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10585 12:17:11.604014 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10586 12:17:11.617573 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10587 12:17:11.624012 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10588 12:17:11.630432 <6>[ 0.009178] Console: colour dummy device 80x25
10589 12:17:11.640401 <6>[ 0.013934] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10590 12:17:11.647329 <6>[ 0.024441] pid_max: default: 32768 minimum: 301
10591 12:17:11.650396 <6>[ 0.029312] LSM: Security Framework initializing
10592 12:17:11.657007 <6>[ 0.034280] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10593 12:17:11.666992 <6>[ 0.042093] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10594 12:17:11.676819 <6>[ 0.051518] cblist_init_generic: Setting adjustable number of callback queues.
10595 12:17:11.683203 <6>[ 0.058973] cblist_init_generic: Setting shift to 3 and lim to 1.
10596 12:17:11.686462 <6>[ 0.065312] cblist_init_generic: Setting shift to 3 and lim to 1.
10597 12:17:11.692957 <6>[ 0.071758] rcu: Hierarchical SRCU implementation.
10598 12:17:11.699960 <6>[ 0.076772] rcu: Max phase no-delay instances is 1000.
10599 12:17:11.706455 <6>[ 0.083820] EFI services will not be available.
10600 12:17:11.709199 <6>[ 0.088819] smp: Bringing up secondary CPUs ...
10601 12:17:11.717573 <6>[ 0.093872] Detected VIPT I-cache on CPU1
10602 12:17:11.724086 <6>[ 0.093944] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10603 12:17:11.730551 <6>[ 0.093976] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10604 12:17:11.734009 <6>[ 0.094308] Detected VIPT I-cache on CPU2
10605 12:17:11.743795 <6>[ 0.094357] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10606 12:17:11.750526 <6>[ 0.094372] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10607 12:17:11.753538 <6>[ 0.094629] Detected VIPT I-cache on CPU3
10608 12:17:11.760468 <6>[ 0.094675] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10609 12:17:11.766931 <6>[ 0.094689] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10610 12:17:11.770389 <6>[ 0.094993] CPU features: detected: Spectre-v4
10611 12:17:11.776691 <6>[ 0.095000] CPU features: detected: Spectre-BHB
10612 12:17:11.780085 <6>[ 0.095005] Detected PIPT I-cache on CPU4
10613 12:17:11.787083 <6>[ 0.095063] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10614 12:17:11.793428 <6>[ 0.095080] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10615 12:17:11.800025 <6>[ 0.095375] Detected PIPT I-cache on CPU5
10616 12:17:11.806336 <6>[ 0.095442] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10617 12:17:11.813291 <6>[ 0.095458] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10618 12:17:11.816115 <6>[ 0.095741] Detected PIPT I-cache on CPU6
10619 12:17:11.822876 <6>[ 0.095807] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10620 12:17:11.832676 <6>[ 0.095823] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10621 12:17:11.835971 <6>[ 0.096123] Detected PIPT I-cache on CPU7
10622 12:17:11.842832 <6>[ 0.096189] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10623 12:17:11.849564 <6>[ 0.096205] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10624 12:17:11.852383 <6>[ 0.096253] smp: Brought up 1 node, 8 CPUs
10625 12:17:11.859266 <6>[ 0.237541] SMP: Total of 8 processors activated.
10626 12:17:11.865695 <6>[ 0.242462] CPU features: detected: 32-bit EL0 Support
10627 12:17:11.872066 <6>[ 0.247826] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10628 12:17:11.879102 <6>[ 0.256625] CPU features: detected: Common not Private translations
10629 12:17:11.885295 <6>[ 0.263101] CPU features: detected: CRC32 instructions
10630 12:17:11.892224 <6>[ 0.268453] CPU features: detected: RCpc load-acquire (LDAPR)
10631 12:17:11.895088 <6>[ 0.274450] CPU features: detected: LSE atomic instructions
10632 12:17:11.901508 <6>[ 0.280231] CPU features: detected: Privileged Access Never
10633 12:17:11.908841 <6>[ 0.286010] CPU features: detected: RAS Extension Support
10634 12:17:11.915058 <6>[ 0.291619] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10635 12:17:11.918503 <6>[ 0.298841] CPU: All CPU(s) started at EL2
10636 12:17:11.924929 <6>[ 0.303184] alternatives: applying system-wide alternatives
10637 12:17:11.935407 <6>[ 0.313901] devtmpfs: initialized
10638 12:17:11.950599 <6>[ 0.322674] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10639 12:17:11.956998 <6>[ 0.332637] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10640 12:17:11.963811 <6>[ 0.340671] pinctrl core: initialized pinctrl subsystem
10641 12:17:11.966837 <6>[ 0.347329] DMI not present or invalid.
10642 12:17:11.973249 <6>[ 0.351742] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10643 12:17:11.983701 <6>[ 0.358598] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10644 12:17:11.989825 <6>[ 0.366177] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10645 12:17:11.999624 <6>[ 0.374390] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10646 12:17:12.002990 <6>[ 0.382636] audit: initializing netlink subsys (disabled)
10647 12:17:12.013262 <5>[ 0.388326] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10648 12:17:12.019552 <6>[ 0.389035] thermal_sys: Registered thermal governor 'step_wise'
10649 12:17:12.025954 <6>[ 0.396294] thermal_sys: Registered thermal governor 'power_allocator'
10650 12:17:12.029333 <6>[ 0.402550] cpuidle: using governor menu
10651 12:17:12.036099 <6>[ 0.413511] NET: Registered PF_QIPCRTR protocol family
10652 12:17:12.042561 <6>[ 0.418990] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10653 12:17:12.049288 <6>[ 0.426095] ASID allocator initialised with 32768 entries
10654 12:17:12.052586 <6>[ 0.432666] Serial: AMBA PL011 UART driver
10655 12:17:12.062191 <4>[ 0.441285] Trying to register duplicate clock ID: 134
10656 12:17:12.115949 <6>[ 0.498339] KASLR enabled
10657 12:17:12.130564 <6>[ 0.506072] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10658 12:17:12.137234 <6>[ 0.513085] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10659 12:17:12.143759 <6>[ 0.519575] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10660 12:17:12.150244 <6>[ 0.526583] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10661 12:17:12.156971 <6>[ 0.533071] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10662 12:17:12.163556 <6>[ 0.540077] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10663 12:17:12.170340 <6>[ 0.546566] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10664 12:17:12.176604 <6>[ 0.553570] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10665 12:17:12.180006 <6>[ 0.561080] ACPI: Interpreter disabled.
10666 12:17:12.189033 <6>[ 0.567457] iommu: Default domain type: Translated
10667 12:17:12.195206 <6>[ 0.572565] iommu: DMA domain TLB invalidation policy: strict mode
10668 12:17:12.198645 <5>[ 0.579222] SCSI subsystem initialized
10669 12:17:12.205120 <6>[ 0.583383] usbcore: registered new interface driver usbfs
10670 12:17:12.211875 <6>[ 0.589112] usbcore: registered new interface driver hub
10671 12:17:12.215258 <6>[ 0.594664] usbcore: registered new device driver usb
10672 12:17:12.222335 <6>[ 0.600740] pps_core: LinuxPPS API ver. 1 registered
10673 12:17:12.231863 <6>[ 0.605935] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10674 12:17:12.235307 <6>[ 0.615282] PTP clock support registered
10675 12:17:12.238097 <6>[ 0.619524] EDAC MC: Ver: 3.0.0
10676 12:17:12.245923 <6>[ 0.624663] FPGA manager framework
10677 12:17:12.252350 <6>[ 0.628341] Advanced Linux Sound Architecture Driver Initialized.
10678 12:17:12.255685 <6>[ 0.635106] vgaarb: loaded
10679 12:17:12.262539 <6>[ 0.638197] clocksource: Switched to clocksource arch_sys_counter
10680 12:17:12.265561 <5>[ 0.644630] VFS: Disk quotas dquot_6.6.0
10681 12:17:12.272505 <6>[ 0.648813] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10682 12:17:12.275427 <6>[ 0.656001] pnp: PnP ACPI: disabled
10683 12:17:12.284029 <6>[ 0.662743] NET: Registered PF_INET protocol family
10684 12:17:12.293868 <6>[ 0.668337] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10685 12:17:12.305336 <6>[ 0.680634] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10686 12:17:12.315049 <6>[ 0.689450] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10687 12:17:12.321838 <6>[ 0.697416] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10688 12:17:12.331111 <6>[ 0.706111] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10689 12:17:12.338110 <6>[ 0.715862] TCP: Hash tables configured (established 65536 bind 65536)
10690 12:17:12.344443 <6>[ 0.722728] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10691 12:17:12.354328 <6>[ 0.729931] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10692 12:17:12.360967 <6>[ 0.737632] NET: Registered PF_UNIX/PF_LOCAL protocol family
10693 12:17:12.367454 <6>[ 0.743707] RPC: Registered named UNIX socket transport module.
10694 12:17:12.371041 <6>[ 0.749858] RPC: Registered udp transport module.
10695 12:17:12.377488 <6>[ 0.754789] RPC: Registered tcp transport module.
10696 12:17:12.384369 <6>[ 0.759720] RPC: Registered tcp NFSv4.1 backchannel transport module.
10697 12:17:12.387695 <6>[ 0.766385] PCI: CLS 0 bytes, default 64
10698 12:17:12.390541 <6>[ 0.770688] Unpacking initramfs...
10699 12:17:12.407244 <6>[ 0.782768] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10700 12:17:12.417336 <6>[ 0.791412] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10701 12:17:12.420169 <6>[ 0.800221] kvm [1]: IPA Size Limit: 40 bits
10702 12:17:12.427116 <6>[ 0.804749] kvm [1]: GICv3: no GICV resource entry
10703 12:17:12.430492 <6>[ 0.809769] kvm [1]: disabling GICv2 emulation
10704 12:17:12.436707 <6>[ 0.814457] kvm [1]: GIC system register CPU interface enabled
10705 12:17:12.440223 <6>[ 0.820617] kvm [1]: vgic interrupt IRQ18
10706 12:17:12.446976 <6>[ 0.825002] kvm [1]: VHE mode initialized successfully
10707 12:17:12.453581 <5>[ 0.831531] Initialise system trusted keyrings
10708 12:17:12.460236 <6>[ 0.836365] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10709 12:17:12.467742 <6>[ 0.846482] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10710 12:17:12.474807 <5>[ 0.852878] NFS: Registering the id_resolver key type
10711 12:17:12.477962 <5>[ 0.858179] Key type id_resolver registered
10712 12:17:12.483992 <5>[ 0.862594] Key type id_legacy registered
10713 12:17:12.490825 <6>[ 0.866875] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10714 12:17:12.497812 <6>[ 0.873795] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10715 12:17:12.504148 <6>[ 0.881530] 9p: Installing v9fs 9p2000 file system support
10716 12:17:12.540927 <5>[ 0.919436] Key type asymmetric registered
10717 12:17:12.544401 <5>[ 0.923768] Asymmetric key parser 'x509' registered
10718 12:17:12.553888 <6>[ 0.928911] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10719 12:17:12.557645 <6>[ 0.936525] io scheduler mq-deadline registered
10720 12:17:12.560176 <6>[ 0.941285] io scheduler kyber registered
10721 12:17:12.579311 <6>[ 0.958184] EINJ: ACPI disabled.
10722 12:17:12.611889 <4>[ 0.983740] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10723 12:17:12.621454 <4>[ 0.994378] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10724 12:17:12.636500 <6>[ 1.015384] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10725 12:17:12.644720 <6>[ 1.023469] printk: console [ttyS0] disabled
10726 12:17:12.672677 <6>[ 1.048115] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10727 12:17:12.679677 <6>[ 1.057595] printk: console [ttyS0] enabled
10728 12:17:12.682731 <6>[ 1.057595] printk: console [ttyS0] enabled
10729 12:17:12.689349 <6>[ 1.066490] printk: bootconsole [mtk8250] disabled
10730 12:17:12.692348 <6>[ 1.066490] printk: bootconsole [mtk8250] disabled
10731 12:17:12.699041 <6>[ 1.077756] SuperH (H)SCI(F) driver initialized
10732 12:17:12.702623 <6>[ 1.083034] msm_serial: driver initialized
10733 12:17:12.716422 <6>[ 1.091895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10734 12:17:12.726581 <6>[ 1.100440] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10735 12:17:12.733007 <6>[ 1.108983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10736 12:17:12.742724 <6>[ 1.117613] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10737 12:17:12.749410 <6>[ 1.126319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10738 12:17:12.759592 <6>[ 1.135039] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10739 12:17:12.769506 <6>[ 1.143581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10740 12:17:12.776108 <6>[ 1.152400] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10741 12:17:12.786142 <6>[ 1.160943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10742 12:17:12.797111 <6>[ 1.176169] loop: module loaded
10743 12:17:12.804286 <6>[ 1.182173] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10744 12:17:12.827128 <4>[ 1.205619] mtk-pmic-keys: Failed to locate of_node [id: -1]
10745 12:17:12.833732 <6>[ 1.212597] megasas: 07.719.03.00-rc1
10746 12:17:12.843766 <6>[ 1.222316] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10747 12:17:12.850676 <6>[ 1.229594] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10748 12:17:12.867962 <6>[ 1.246398] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10749 12:17:12.924250 <6>[ 1.296770] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10750 12:17:16.400224 <6>[ 4.779799] Freeing initrd memory: 95828K
10751 12:17:16.410611 <6>[ 4.790156] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10752 12:17:16.421968 <6>[ 4.801228] tun: Universal TUN/TAP device driver, 1.6
10753 12:17:16.425572 <6>[ 4.807293] thunder_xcv, ver 1.0
10754 12:17:16.428175 <6>[ 4.810798] thunder_bgx, ver 1.0
10755 12:17:16.431732 <6>[ 4.814295] nicpf, ver 1.0
10756 12:17:16.442194 <6>[ 4.818306] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10757 12:17:16.445687 <6>[ 4.825782] hns3: Copyright (c) 2017 Huawei Corporation.
10758 12:17:16.452361 <6>[ 4.831369] hclge is initializing
10759 12:17:16.455790 <6>[ 4.834951] e1000: Intel(R) PRO/1000 Network Driver
10760 12:17:16.462648 <6>[ 4.840080] e1000: Copyright (c) 1999-2006 Intel Corporation.
10761 12:17:16.465454 <6>[ 4.846096] e1000e: Intel(R) PRO/1000 Network Driver
10762 12:17:16.471995 <6>[ 4.851311] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10763 12:17:16.478659 <6>[ 4.857498] igb: Intel(R) Gigabit Ethernet Network Driver
10764 12:17:16.485232 <6>[ 4.863148] igb: Copyright (c) 2007-2014 Intel Corporation.
10765 12:17:16.491900 <6>[ 4.868986] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10766 12:17:16.498652 <6>[ 4.875504] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10767 12:17:16.502241 <6>[ 4.881966] sky2: driver version 1.30
10768 12:17:16.508653 <6>[ 4.886950] VFIO - User Level meta-driver version: 0.3
10769 12:17:16.516088 <6>[ 4.895151] usbcore: registered new interface driver usb-storage
10770 12:17:16.522396 <6>[ 4.901591] usbcore: registered new device driver onboard-usb-hub
10771 12:17:16.531335 <6>[ 4.910715] mt6397-rtc mt6359-rtc: registered as rtc0
10772 12:17:16.541775 <6>[ 4.916183] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:17:16 UTC (1686053836)
10773 12:17:16.544569 <6>[ 4.925746] i2c_dev: i2c /dev entries driver
10774 12:17:16.561832 <6>[ 4.937519] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10775 12:17:16.568751 <6>[ 4.947743] sdhci: Secure Digital Host Controller Interface driver
10776 12:17:16.574884 <6>[ 4.954181] sdhci: Copyright(c) Pierre Ossman
10777 12:17:16.581478 <6>[ 4.959572] Synopsys Designware Multimedia Card Interface Driver
10778 12:17:16.584686 <6>[ 4.966198] mmc0: CQHCI version 5.10
10779 12:17:16.591239 <6>[ 4.966718] sdhci-pltfm: SDHCI platform and OF driver helper
10780 12:17:16.598846 <6>[ 4.978106] ledtrig-cpu: registered to indicate activity on CPUs
10781 12:17:16.609236 <6>[ 4.985476] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10782 12:17:16.616078 <6>[ 4.992878] usbcore: registered new interface driver usbhid
10783 12:17:16.619475 <6>[ 4.998711] usbhid: USB HID core driver
10784 12:17:16.625913 <6>[ 5.002970] spi_master spi0: will run message pump with realtime priority
10785 12:17:16.673243 <6>[ 5.045970] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10786 12:17:16.693201 <6>[ 5.062320] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10787 12:17:16.696868 <6>[ 5.075891] mmc0: Command Queue Engine enabled
10788 12:17:16.703808 <6>[ 5.078222] cros-ec-spi spi0.0: Chrome EC device registered
10789 12:17:16.710122 <6>[ 5.080631] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10790 12:17:16.713634 <6>[ 5.093864] mmcblk0: mmc0:0001 DA4128 116 GiB
10791 12:17:16.724650 <6>[ 5.103600] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10792 12:17:16.734445 <6>[ 5.103965] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10793 12:17:16.740694 <6>[ 5.110715] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10794 12:17:16.744440 <6>[ 5.120908] NET: Registered PF_PACKET protocol family
10795 12:17:16.751131 <6>[ 5.124746] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10796 12:17:16.754003 <6>[ 5.129468] 9pnet: Installing 9P2000 support
10797 12:17:16.760628 <6>[ 5.135335] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10798 12:17:16.767129 <5>[ 5.139181] Key type dns_resolver registered
10799 12:17:16.770943 <6>[ 5.150776] registered taskstats version 1
10800 12:17:16.777444 <5>[ 5.155186] Loading compiled-in X.509 certificates
10801 12:17:16.809819 <4>[ 5.182503] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10802 12:17:16.819452 <4>[ 5.193195] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10803 12:17:16.829995 <3>[ 5.205932] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10804 12:17:16.841984 <6>[ 5.221386] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10805 12:17:16.848901 <6>[ 5.228136] xhci-mtk 11200000.usb: xHCI Host Controller
10806 12:17:16.855741 <6>[ 5.233641] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10807 12:17:16.865399 <6>[ 5.241499] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10808 12:17:16.872414 <6>[ 5.250944] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10809 12:17:16.879016 <6>[ 5.257170] xhci-mtk 11200000.usb: xHCI Host Controller
10810 12:17:16.885486 <6>[ 5.262678] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10811 12:17:16.891714 <6>[ 5.270336] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10812 12:17:16.898883 <6>[ 5.278234] hub 1-0:1.0: USB hub found
10813 12:17:16.902283 <6>[ 5.282273] hub 1-0:1.0: 1 port detected
10814 12:17:16.912075 <6>[ 5.286622] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10815 12:17:16.915314 <6>[ 5.295432] hub 2-0:1.0: USB hub found
10816 12:17:16.918663 <6>[ 5.299470] hub 2-0:1.0: 1 port detected
10817 12:17:16.927273 <6>[ 5.306708] mtk-msdc 11f70000.mmc: Got CD GPIO
10818 12:17:16.944243 <6>[ 5.320316] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10819 12:17:16.950477 <6>[ 5.328345] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10820 12:17:16.961120 <4>[ 5.336312] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10821 12:17:16.970692 <6>[ 5.345965] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10822 12:17:16.977147 <6>[ 5.354047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10823 12:17:16.987059 <6>[ 5.362070] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10824 12:17:16.993473 <6>[ 5.369989] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10825 12:17:17.000254 <6>[ 5.377810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10826 12:17:17.010040 <6>[ 5.385640] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10827 12:17:17.019986 <6>[ 5.396302] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10828 12:17:17.030193 <6>[ 5.404671] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10829 12:17:17.036827 <6>[ 5.413026] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10830 12:17:17.047024 <6>[ 5.421370] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10831 12:17:17.053366 <6>[ 5.429714] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10832 12:17:17.063676 <6>[ 5.438056] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10833 12:17:17.070360 <6>[ 5.446400] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10834 12:17:17.080186 <6>[ 5.454743] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10835 12:17:17.086740 <6>[ 5.463087] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10836 12:17:17.096331 <6>[ 5.471436] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10837 12:17:17.103043 <6>[ 5.479780] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10838 12:17:17.112949 <6>[ 5.488125] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10839 12:17:17.119644 <6>[ 5.496472] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10840 12:17:17.129543 <6>[ 5.504816] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10841 12:17:17.135752 <6>[ 5.513161] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10842 12:17:17.142711 <6>[ 5.522050] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10843 12:17:17.150097 <6>[ 5.529490] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10844 12:17:17.157212 <6>[ 5.536546] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10845 12:17:17.167663 <6>[ 5.543642] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10846 12:17:17.174407 <6>[ 5.550925] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10847 12:17:17.184288 <6>[ 5.557824] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10848 12:17:17.190600 <6>[ 5.566966] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10849 12:17:17.200510 <6>[ 5.576093] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10850 12:17:17.210571 <6>[ 5.585395] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10851 12:17:17.220705 <6>[ 5.594871] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10852 12:17:17.230242 <6>[ 5.604346] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10853 12:17:17.240259 <6>[ 5.613473] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10854 12:17:17.246722 <6>[ 5.622948] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10855 12:17:17.256896 <6>[ 5.632075] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10856 12:17:17.266722 <6>[ 5.641383] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10857 12:17:17.276532 <6>[ 5.651549] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10858 12:17:17.286698 <6>[ 5.662996] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10859 12:17:17.310026 <6>[ 5.686465] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10860 12:17:17.337756 <6>[ 5.716958] hub 2-1:1.0: USB hub found
10861 12:17:17.340638 <6>[ 5.721369] hub 2-1:1.0: 3 ports detected
10862 12:17:17.462683 <6>[ 5.838480] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10863 12:17:17.616882 <6>[ 5.996180] hub 1-1:1.0: USB hub found
10864 12:17:17.620373 <6>[ 6.000632] hub 1-1:1.0: 4 ports detected
10865 12:17:17.694848 <6>[ 6.070722] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10866 12:17:17.942388 <6>[ 6.318478] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10867 12:17:18.075156 <6>[ 6.454606] hub 1-1.4:1.0: USB hub found
10868 12:17:18.078253 <6>[ 6.459254] hub 1-1.4:1.0: 2 ports detected
10869 12:17:18.373849 <6>[ 6.750476] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10870 12:17:18.566310 <6>[ 6.942479] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10871 12:17:29.578935 <6>[ 17.962884] ALSA device list:
10872 12:17:29.585476 <6>[ 17.966121] No soundcards found.
10873 12:17:29.597850 <6>[ 17.978543] Freeing unused kernel memory: 8384K
10874 12:17:29.601476 <6>[ 17.983457] Run /init as init process
10875 12:17:29.631573 <6>[ 18.012245] NET: Registered PF_INET6 protocol family
10876 12:17:29.638106 <6>[ 18.018400] Segment Routing with IPv6
10877 12:17:29.641464 <6>[ 18.022382] In-situ OAM (IOAM) with IPv6
10878 12:17:29.675814 <30>[ 18.036935] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10879 12:17:29.679242 <30>[ 18.060794] systemd[1]: Detected architecture arm64.
10880 12:17:29.682385
10881 12:17:29.685671 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10882 12:17:29.686264
10883 12:17:29.701589 <30>[ 18.082636] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10884 12:17:29.837036 <30>[ 18.214381] systemd[1]: Queued start job for default target Graphical Interface.
10885 12:17:29.882798 <30>[ 18.263827] systemd[1]: Created slice system-getty.slice.
10886 12:17:29.889237 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10887 12:17:29.905955 <30>[ 18.287058] systemd[1]: Created slice system-modprobe.slice.
10888 12:17:29.912464 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10889 12:17:29.930629 <30>[ 18.311620] systemd[1]: Created slice system-serial\x2dgetty.slice.
10890 12:17:29.940363 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10891 12:17:29.953866 <30>[ 18.334991] systemd[1]: Created slice User and Session Slice.
10892 12:17:29.960752 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10893 12:17:29.981357 <30>[ 18.359042] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10894 12:17:29.991132 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10895 12:17:30.009042 <30>[ 18.386642] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10896 12:17:30.015512 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10897 12:17:30.036103 <30>[ 18.410554] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10898 12:17:30.042707 <30>[ 18.422582] systemd[1]: Reached target Local Encrypted Volumes.
10899 12:17:30.049248 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10900 12:17:30.065889 <30>[ 18.446563] systemd[1]: Reached target Paths.
10901 12:17:30.069128 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10902 12:17:30.085507 <30>[ 18.466520] systemd[1]: Reached target Remote File Systems.
10903 12:17:30.092266 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10904 12:17:30.105578 <30>[ 18.486493] systemd[1]: Reached target Slices.
10905 12:17:30.112280 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10906 12:17:30.125674 <30>[ 18.506519] systemd[1]: Reached target Swap.
10907 12:17:30.128867 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10908 12:17:30.148789 <30>[ 18.526752] systemd[1]: Listening on initctl Compatibility Named Pipe.
10909 12:17:30.155601 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10910 12:17:30.162393 <30>[ 18.541504] systemd[1]: Listening on Journal Audit Socket.
10911 12:17:30.168461 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10912 12:17:30.181863 <30>[ 18.562784] systemd[1]: Listening on Journal Socket (/dev/log).
10913 12:17:30.188239 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10914 12:17:30.205758 <30>[ 18.586796] systemd[1]: Listening on Journal Socket.
10915 12:17:30.212338 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10916 12:17:30.225460 <30>[ 18.606786] systemd[1]: Listening on udev Control Socket.
10917 12:17:30.232008 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10918 12:17:30.250397 <30>[ 18.631154] systemd[1]: Listening on udev Kernel Socket.
10919 12:17:30.256475 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10920 12:17:30.293532 <30>[ 18.674690] systemd[1]: Mounting Huge Pages File System...
10921 12:17:30.299856 Mounting [0;1;39mHuge Pages File System[0m...
10922 12:17:30.315553 <30>[ 18.696524] systemd[1]: Mounting POSIX Message Queue File System...
10923 12:17:30.321880 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10924 12:17:30.339366 <30>[ 18.720456] systemd[1]: Mounting Kernel Debug File System...
10925 12:17:30.345966 Mounting [0;1;39mKernel Debug File System[0m...
10926 12:17:30.365049 <30>[ 18.742743] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10927 12:17:30.375912 <30>[ 18.753618] systemd[1]: Starting Create list of static device nodes for the current kernel...
10928 12:17:30.382506 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10929 12:17:30.399332 <30>[ 18.780758] systemd[1]: Starting Load Kernel Module configfs...
10930 12:17:30.405958 Starting [0;1;39mLoad Kernel Module configfs[0m...
10931 12:17:30.453759 <30>[ 18.834846] systemd[1]: Starting Load Kernel Module drm...
10932 12:17:30.460453 Starting [0;1;39mLoad Kernel Module drm[0m...
10933 12:17:30.477154 <30>[ 18.854690] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10934 12:17:30.487918 <30>[ 18.868339] systemd[1]: Starting Journal Service...
10935 12:17:30.490938 Starting [0;1;39mJournal Service[0m...
10936 12:17:30.508599 <30>[ 18.889101] systemd[1]: Starting Load Kernel Modules...
10937 12:17:30.514652 Starting [0;1;39mLoad Kernel Modules[0m...
10938 12:17:30.535631 <30>[ 18.913122] systemd[1]: Starting Remount Root and Kernel File Systems...
10939 12:17:30.541963 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10940 12:17:30.555805 <30>[ 18.936879] systemd[1]: Starting Coldplug All udev Devices...
10941 12:17:30.562338 Starting [0;1;39mColdplug All udev Devices[0m...
10942 12:17:30.580218 <30>[ 18.961202] systemd[1]: Mounted Huge Pages File System.
10943 12:17:30.586852 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10944 12:17:30.602254 <30>[ 18.983123] systemd[1]: Started Journal Service.
10945 12:17:30.608805 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10946 12:17:30.623019 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10947 12:17:30.639461 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10948 12:17:30.658073 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10949 12:17:30.675316 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10950 12:17:30.691304 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10951 12:17:30.707302 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10952 12:17:30.727193 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10953 12:17:30.741828 See 'systemctl status systemd-remount-fs.service' for details.
10954 12:17:30.794280 Mounting [0;1;39mKernel Configuration File System[0m...
10955 12:17:30.816581 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10956 12:17:30.834088 <46>[ 19.211473] systemd-journald[175]: Received client request to flush runtime journal.
10957 12:17:30.844639 Starting [0;1;39mLoad/Save Random Seed[0m...
10958 12:17:30.861574 Starting [0;1;39mApply Kernel Variables[0m...
10959 12:17:30.881015 Starting [0;1;39mCreate System Users[0m...
10960 12:17:30.896567 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10961 12:17:30.918352 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10962 12:17:30.930931 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10963 12:17:30.947309 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10964 12:17:30.962622 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10965 12:17:30.978722 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10966 12:17:31.014194 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10967 12:17:31.038147 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10968 12:17:31.053972 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10969 12:17:31.073875 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10970 12:17:31.130372 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10971 12:17:31.153790 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10972 12:17:31.174353 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10973 12:17:31.180932 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10974 12:17:31.204528 Starting [0;1;39mNetwork Time Synchronization[0m...
10975 12:17:31.224869 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10976 12:17:31.262243 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10977 12:17:31.316574 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10978 12:17:31.357870 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<6>[ 19.734841] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10979 12:17:31.358394 .
10980 12:17:31.378983 [[0;32m OK [0m] Reached targ<6>[ 19.757507] remoteproc remoteproc0: scp is available
10981 12:17:31.388501 et [0;1;39mSyst<4>[ 19.764227] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10982 12:17:31.395254 em Time Set[0m.<6>[ 19.775428] remoteproc remoteproc0: powering up scp
10983 12:17:31.395949
10984 12:17:31.404788 <4>[ 19.782151] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10985 12:17:31.414616 <3>[ 19.783778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10986 12:17:31.421139 <3>[ 19.792046] remoteproc remoteproc0: request_firmware failed: -2
10987 12:17:31.427850 <3>[ 19.800184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10988 12:17:31.437599 <3>[ 19.814545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10989 12:17:31.450940 [[0;32m OK [0m] Reached target [0;1;39mSyst<3>[ 19.826606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10990 12:17:31.457422 em Time Synchron<6>[ 19.829145] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10991 12:17:31.460769 ized[0m.
10992 12:17:31.467321 <3>[ 19.835940] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10993 12:17:31.477260 <6>[ 19.844558] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10994 12:17:31.483819 <6>[ 19.844574] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10995 12:17:31.494140 <3>[ 19.871252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10996 12:17:31.500295 <3>[ 19.879369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10997 12:17:31.510927 <3>[ 19.887595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10998 12:17:31.521321 <3>[ 19.898802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10999 12:17:31.528302 <4>[ 19.900408] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11000 12:17:31.534228 <6>[ 19.902420] mc: Linux media interface: v0.10
11001 12:17:31.540679 <6>[ 19.908376] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11002 12:17:31.547562 <3>[ 19.915492] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11003 12:17:31.557542 <4>[ 19.922708] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11004 12:17:31.564093 <3>[ 19.926811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11005 12:17:31.570410 <6>[ 19.947515] usbcore: registered new interface driver r8152
11006 12:17:31.577358 <6>[ 19.949254] videodev: Linux video capture interface: v2.00
11007 12:17:31.584549 <4>[ 19.949750] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11008 12:17:31.591281 <4>[ 19.949750] Fallback method does not support PEC.
11009 12:17:31.597945 <3>[ 19.950614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11010 12:17:31.607843 <3>[ 19.966799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 12:17:31.614627 <6>[ 19.984047] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11012 12:17:31.620933 <3>[ 19.990877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11013 12:17:31.630819 <3>[ 19.990902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11014 12:17:31.637566 <3>[ 19.990910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11015 12:17:31.647306 <3>[ 19.990921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11016 12:17:31.654216 <3>[ 19.990929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11017 12:17:31.661358 <3>[ 19.990980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11018 12:17:31.671708 <6>[ 20.030759] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11019 12:17:31.678118 <6>[ 20.031873] pci_bus 0000:00: root bus resource [bus 00-ff]
11020 12:17:31.684909 <6>[ 20.038476] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11021 12:17:31.694449 <6>[ 20.040335] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11022 12:17:31.704490 <6>[ 20.045313] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11023 12:17:31.710905 <3>[ 20.045880] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 12:17:31.721065 <3>[ 20.046889] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11025 12:17:31.727567 <6>[ 20.048051] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11026 12:17:31.737534 <4>[ 20.069690] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11027 12:17:31.747581 <6>[ 20.071206] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11028 12:17:31.757630 <4>[ 20.081009] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11029 12:17:31.760967 <6>[ 20.089904] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11030 12:17:31.767023 <6>[ 20.090267] usbcore: registered new interface driver cdc_ether
11031 12:17:31.770417 <6>[ 20.099315] Bluetooth: Core ver 2.22
11032 12:17:31.780681 <6>[ 20.107585] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11033 12:17:31.786807 <6>[ 20.107852] usbcore: registered new interface driver r8153_ecm
11034 12:17:31.790601 <6>[ 20.114819] NET: Registered PF_BLUETOOTH protocol family
11035 12:17:31.796933 <6>[ 20.124134] pci 0000:00:00.0: supports D1 D2
11036 12:17:31.803804 <6>[ 20.125081] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11037 12:17:31.816914 <6>[ 20.126630] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11038 12:17:31.820191 <6>[ 20.126777] usbcore: registered new interface driver uvcvideo
11039 12:17:31.826894 <6>[ 20.134161] Bluetooth: HCI device and connection manager initialized
11040 12:17:31.834509 <6>[ 20.141895] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11041 12:17:31.838200 <6>[ 20.148096] Bluetooth: HCI socket layer initialized
11042 12:17:31.844936 <6>[ 20.150298] r8152 2-1.3:1.0 eth0: v1.12.13
11043 12:17:31.852130 <6>[ 20.156256] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11044 12:17:31.858781 <6>[ 20.156554] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11045 12:17:31.865724 <6>[ 20.158033] Bluetooth: L2CAP socket layer initialized
11046 12:17:31.868893 <6>[ 20.160882] remoteproc remoteproc0: powering up scp
11047 12:17:31.879270 <4>[ 20.160941] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11048 12:17:31.885432 <3>[ 20.160955] remoteproc remoteproc0: request_firmware failed: -2
11049 12:17:31.892245 <3>[ 20.160958] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11050 12:17:31.898863 <6>[ 20.164021] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
11051 12:17:31.906214 <6>[ 20.165615] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11052 12:17:31.909474 <6>[ 20.171680] Bluetooth: SCO socket layer initialized
11053 12:17:31.916122 <6>[ 20.177155] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11054 12:17:31.926590 <3>[ 20.222040] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11055 12:17:31.932876 <6>[ 20.225762] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11056 12:17:31.939966 <6>[ 20.226421] usbcore: registered new interface driver btusb
11057 12:17:31.950685 <3>[ 20.230298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11058 12:17:31.960279 <4>[ 20.230586] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11059 12:17:31.963712 <3>[ 20.230596] Bluetooth: hci0: Failed to load firmware file (-2)
11060 12:17:31.970243 <3>[ 20.230599] Bluetooth: hci0: Failed to set up firmware (-2)
11061 12:17:31.981277 <4>[ 20.230603] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11062 12:17:31.991145 <3>[ 20.231017] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11063 12:17:31.997823 <6>[ 20.238371] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11064 12:17:32.005302 <3>[ 20.251069] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11065 12:17:32.011704 <6>[ 20.255437] pci 0000:01:00.0: supports D1 D2
11066 12:17:32.018919 <3>[ 20.292471] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11067 12:17:32.025694 <6>[ 20.296327] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11068 12:17:32.032367 <6>[ 20.306500] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11069 12:17:32.042156 <3>[ 20.333397] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11070 12:17:32.049428 <6>[ 20.334655] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11071 12:17:32.059621 <3>[ 20.366427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11072 12:17:32.066450 <6>[ 20.367486] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11073 12:17:32.076604 <6>[ 20.453135] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11074 12:17:32.083003 <6>[ 20.453152] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11075 12:17:32.089482 <6>[ 20.453168] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11076 12:17:32.096533 <6>[ 20.453184] pci 0000:00:00.0: PCI bridge to [bus 01]
11077 12:17:32.102953 <6>[ 20.482382] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11078 12:17:32.113103 Startin<6>[ 20.490594] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11079 12:17:32.119653 g [0;1;39mLoad/<6>[ 20.499105] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11080 12:17:32.126752 Save Screen …o<6>[ 20.506003] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11081 12:17:32.129414 f leds:white:kbd_backlight[0m...
11082 12:17:32.147475 <5>[ 20.524880] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11083 12:17:32.157765 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11084 12:17:32.167597 <5>[ 20.544976] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11085 12:17:32.174077 <4>[ 20.551915] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11086 12:17:32.180739 <6>[ 20.560811] cfg80211: failed to load regulatory.db
11087 12:17:32.186886 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11088 12:17:32.227866 <6>[ 20.605840] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11089 12:17:32.234633 <6>[ 20.613603] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11090 12:17:32.259527 <6>[ 20.640547] mt7921e 0000:01:00.0: ASIC revision: 79610010
11091 12:17:32.367884 <4>[ 20.742265] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11092 12:17:32.379260 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11093 12:17:32.394332 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11094 12:17:32.413609 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11095 12:17:32.429114 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11096 12:17:32.441246 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11097 12:17:32.461099 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11098 12:17:32.475588 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11099 12:17:32.485581 <4>[ 20.861423] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11100 12:17:32.492091 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11101 12:17:32.510332 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11102 12:17:32.550478 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11103 12:17:32.576974 Starting [0;1;39mUser Login Management[0m...
11104 12:17:32.597458 Starting [0;1;39mPermit User Sessions[0m...
11105 12:17:32.606722 <4>[ 20.982979] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11106 12:17:32.618681 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11107 12:17:32.632338 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11108 12:17:32.648387 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11109 12:17:32.666499 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11110 12:17:32.733952 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m..<4>[ 21.106534] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11111 12:17:32.734515 .
11112 12:17:32.752615 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11113 12:17:32.774979 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11114 12:17:32.782103 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11115 12:17:32.802077 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11116 12:17:32.845879 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11117 12:17:32.855507 <4>[ 21.231201] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11118 12:17:32.882376 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11119 12:17:32.901512
11120 12:17:32.901948
11121 12:17:32.904646 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11122 12:17:32.905159
11123 12:17:32.907942 debian-bullseye-arm64 login: root (automatic login)
11124 12:17:32.908404
11125 12:17:32.908749
11126 12:17:32.925039 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
11127 12:17:32.925532
11128 12:17:32.931391 The programs included with the Debian GNU/Linux system are free software;
11129 12:17:32.938490 the exact distribution terms for each program are described in the
11130 12:17:32.941414 individual files in /usr/share/doc/*/copyright.
11131 12:17:32.941844
11132 12:17:32.948024 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11133 12:17:32.948559 permitted by applicable law.
11134 12:17:32.951984 Matched prompt #10: / #
11136 12:17:32.953165 Setting prompt string to ['/ #']
11137 12:17:32.953613 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11139 12:17:32.954602 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11140 12:17:32.955109 start: 2.2.6 expect-shell-connection (timeout 00:01:54) [common]
11141 12:17:32.955479 Setting prompt string to ['/ #']
11142 12:17:32.955799 Forcing a shell prompt, looking for ['/ #']
11144 12:17:33.006629 / #
11145 12:17:33.007286 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11146 12:17:33.007742 Waiting using forced prompt support (timeout 00:02:30)
11147 12:17:33.008371 <4>[ 21.353048] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11148 12:17:33.013387
11149 12:17:33.014329 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11150 12:17:33.014894 start: 2.2.7 export-device-env (timeout 00:01:54) [common]
11151 12:17:33.015429 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11152 12:17:33.015929 end: 2.2 depthcharge-retry (duration 00:03:06) [common]
11153 12:17:33.016490 end: 2 depthcharge-action (duration 00:03:06) [common]
11154 12:17:33.016977 start: 3 lava-test-retry (timeout 00:05:00) [common]
11155 12:17:33.017456 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11156 12:17:33.017862 Using namespace: common
11158 12:17:33.119025 / # #
11159 12:17:33.119662 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11160 12:17:33.120430 #<4>[ 21.472421] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11161 12:17:33.124505
11162 12:17:33.125219 Using /lava-10605425
11164 12:17:33.226308 / # export SHELL=/bin/sh
11165 12:17:33.227062 export SHELL=/bin/sh<4>[ 21.588475] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11166 12:17:33.232494
11168 12:17:33.334146 / # . /lava-10605425/environment
11169 12:17:33.335103 . /lava-10605425/environment<4>[ 21.704760] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11170 12:17:33.340999
11172 12:17:33.485745 / # /lava-10605425/bin/lava-test-runner /lava-10605425/0
11173 12:17:33.486401 Test shell timeout: 10s (minimum of the action and connection timeout)
11174 12:17:33.487901 <4>[ 21.824317] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11175 12:17:33.491818 /lava-10605425/bin/lava-test-run
11176 12:17:33.532442 -sh: 5: /lava-10605425/bin/lava-test-run: not found
11177 12:17:33.557082 / # <3>[ 21.938433] mt7921e 0000:01:00.0: hardware init failed
11178 12:17:59.815309 <6>[ 48.202547] vpu: disabling
11179 12:17:59.818079 <6>[ 48.205602] vproc2: disabling
11180 12:17:59.821978 <6>[ 48.208881] vproc1: disabling
11181 12:17:59.825162 <6>[ 48.212142] vaud18: disabling
11182 12:17:59.828599 <6>[ 48.215546] vsram_others: disabling
11183 12:17:59.831596 <6>[ 48.219418] va09: disabling
11184 12:17:59.834923 <6>[ 48.222522] vsram_md: disabling
11185 12:17:59.838170 <6>[ 48.226007] Vgpu: disabling
11187 12:22:33.018454 end: 3.1 lava-test-shell (duration 00:05:00) [common]
11189 12:22:33.020494 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 300 seconds'
11191 12:22:33.021336 end: 3 lava-test-retry (duration 00:05:00) [common]
11193 12:22:33.022516 Cleaning after the job
11194 12:22:33.023003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/ramdisk
11195 12:22:33.058314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/kernel
11196 12:22:33.082032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/dtb
11197 12:22:33.082278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605425/tftp-deploy-3m5mim6z/modules
11198 12:22:33.087873 start: 4.1 power-off (timeout 00:00:30) [common]
11199 12:22:33.088059 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11200 12:22:33.164415 >> Command sent successfully.
11201 12:22:33.169408 Returned 0 in 0 seconds
11202 12:22:33.270380 end: 4.1 power-off (duration 00:00:00) [common]
11204 12:22:33.271884 start: 4.2 read-feedback (timeout 00:10:00) [common]
11205 12:22:33.273075 Listened to connection for namespace 'common' for up to 1s
11206 12:22:34.273761 Finalising connection for namespace 'common'
11207 12:22:34.274486 Disconnecting from shell: Finalise
11208 12:22:34.375468 end: 4.2 read-feedback (duration 00:00:01) [common]
11209 12:22:34.376155 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605425
11210 12:22:34.556232 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605425
11211 12:22:34.556437 TestError: A test failed to run, look at the error message.