Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 12:10:38.704187 lava-dispatcher, installed at version: 2023.05.1
2 12:10:38.704403 start: 0 validate
3 12:10:38.704548 Start time: 2023-06-06 12:10:38.704541+00:00 (UTC)
4 12:10:38.704684 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:10:38.704818 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 12:10:38.998722 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:10:38.998968 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:10:39.292266 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:10:39.292500 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:10:58.688452 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:10:58.688703 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:10:59.278015 validate duration: 20.57
14 12:10:59.278366 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:10:59.278497 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:10:59.278590 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:10:59.278724 Not decompressing ramdisk as can be used compressed.
18 12:10:59.278843 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 12:10:59.278945 saving as /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/ramdisk/rootfs.cpio.gz
20 12:10:59.279038 total size: 8186575 (7MB)
21 12:11:01.853856 progress 0% (0MB)
22 12:11:01.856360 progress 5% (0MB)
23 12:11:01.858613 progress 10% (0MB)
24 12:11:01.861032 progress 15% (1MB)
25 12:11:01.863305 progress 20% (1MB)
26 12:11:01.865725 progress 25% (1MB)
27 12:11:01.867947 progress 30% (2MB)
28 12:11:01.870346 progress 35% (2MB)
29 12:11:01.872669 progress 40% (3MB)
30 12:11:01.875113 progress 45% (3MB)
31 12:11:01.877370 progress 50% (3MB)
32 12:11:01.879730 progress 55% (4MB)
33 12:11:01.881864 progress 60% (4MB)
34 12:11:01.884367 progress 65% (5MB)
35 12:11:01.886517 progress 70% (5MB)
36 12:11:01.888846 progress 75% (5MB)
37 12:11:01.891011 progress 80% (6MB)
38 12:11:01.893360 progress 85% (6MB)
39 12:11:01.895570 progress 90% (7MB)
40 12:11:01.897926 progress 95% (7MB)
41 12:11:01.900125 progress 100% (7MB)
42 12:11:01.900381 7MB downloaded in 2.62s (2.98MB/s)
43 12:11:01.900582 end: 1.1.1 http-download (duration 00:00:03) [common]
45 12:11:01.900969 end: 1.1 download-retry (duration 00:00:03) [common]
46 12:11:01.901091 start: 1.2 download-retry (timeout 00:09:57) [common]
47 12:11:01.901215 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 12:11:01.901387 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:11:01.901490 saving as /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/kernel/Image
50 12:11:01.901581 total size: 45746688 (43MB)
51 12:11:01.901677 No compression specified
52 12:11:01.903095 progress 0% (0MB)
53 12:11:01.915760 progress 5% (2MB)
54 12:11:01.928510 progress 10% (4MB)
55 12:11:01.942028 progress 15% (6MB)
56 12:11:01.955494 progress 20% (8MB)
57 12:11:01.968608 progress 25% (10MB)
58 12:11:01.981147 progress 30% (13MB)
59 12:11:01.993965 progress 35% (15MB)
60 12:11:02.007419 progress 40% (17MB)
61 12:11:02.021913 progress 45% (19MB)
62 12:11:02.036321 progress 50% (21MB)
63 12:11:02.049843 progress 55% (24MB)
64 12:11:02.063284 progress 60% (26MB)
65 12:11:02.077413 progress 65% (28MB)
66 12:11:02.090625 progress 70% (30MB)
67 12:11:02.103386 progress 75% (32MB)
68 12:11:02.115901 progress 80% (34MB)
69 12:11:02.128579 progress 85% (37MB)
70 12:11:02.141324 progress 90% (39MB)
71 12:11:02.154004 progress 95% (41MB)
72 12:11:02.167370 progress 100% (43MB)
73 12:11:02.167581 43MB downloaded in 0.27s (164.02MB/s)
74 12:11:02.167790 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:11:02.168211 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:11:02.168346 start: 1.3 download-retry (timeout 00:09:57) [common]
78 12:11:02.168470 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 12:11:02.168664 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:11:02.168773 saving as /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/dtb/mt8192-asurada-spherion-r0.dtb
81 12:11:02.168870 total size: 46924 (0MB)
82 12:11:02.168981 No compression specified
83 12:11:02.170790 progress 69% (0MB)
84 12:11:02.171121 progress 100% (0MB)
85 12:11:02.171346 0MB downloaded in 0.00s (18.10MB/s)
86 12:11:02.171529 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:11:02.171824 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:11:02.171945 start: 1.4 download-retry (timeout 00:09:57) [common]
90 12:11:02.172078 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 12:11:02.172213 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:11:02.172290 saving as /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/modules/modules.tar
93 12:11:02.172354 total size: 8553528 (8MB)
94 12:11:02.172453 Using unxz to decompress xz
95 12:11:02.176347 progress 0% (0MB)
96 12:11:02.199367 progress 5% (0MB)
97 12:11:02.224574 progress 10% (0MB)
98 12:11:02.257012 progress 15% (1MB)
99 12:11:02.284952 progress 20% (1MB)
100 12:11:02.310256 progress 25% (2MB)
101 12:11:02.335475 progress 30% (2MB)
102 12:11:02.361656 progress 35% (2MB)
103 12:11:02.386660 progress 40% (3MB)
104 12:11:02.412392 progress 45% (3MB)
105 12:11:02.437652 progress 50% (4MB)
106 12:11:02.462658 progress 55% (4MB)
107 12:11:02.488106 progress 60% (4MB)
108 12:11:02.515430 progress 65% (5MB)
109 12:11:02.540848 progress 70% (5MB)
110 12:11:02.565486 progress 75% (6MB)
111 12:11:02.592049 progress 80% (6MB)
112 12:11:02.617385 progress 85% (6MB)
113 12:11:02.642556 progress 90% (7MB)
114 12:11:02.667911 progress 95% (7MB)
115 12:11:02.695641 progress 100% (8MB)
116 12:11:02.700401 8MB downloaded in 0.53s (15.45MB/s)
117 12:11:02.700771 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:11:02.701183 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:11:02.701314 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 12:11:02.701448 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 12:11:02.701566 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:11:02.701692 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 12:11:02.701964 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib
125 12:11:02.702144 makedir: /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin
126 12:11:02.702291 makedir: /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/tests
127 12:11:02.702451 makedir: /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/results
128 12:11:02.702610 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-add-keys
129 12:11:02.702808 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-add-sources
130 12:11:02.702974 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-background-process-start
131 12:11:02.703142 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-background-process-stop
132 12:11:02.703304 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-common-functions
133 12:11:02.703484 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-echo-ipv4
134 12:11:02.703644 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-install-packages
135 12:11:02.703800 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-installed-packages
136 12:11:02.703967 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-os-build
137 12:11:02.704140 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-probe-channel
138 12:11:02.704321 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-probe-ip
139 12:11:02.704488 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-target-ip
140 12:11:02.704652 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-target-mac
141 12:11:02.704813 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-target-storage
142 12:11:02.704975 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-case
143 12:11:02.705110 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-event
144 12:11:02.705277 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-feedback
145 12:11:02.705442 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-raise
146 12:11:02.705605 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-reference
147 12:11:02.705769 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-runner
148 12:11:02.705928 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-set
149 12:11:02.706089 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-test-shell
150 12:11:02.706253 Updating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-install-packages (oe)
151 12:11:02.706440 Updating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/bin/lava-installed-packages (oe)
152 12:11:02.706599 Creating /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/environment
153 12:11:02.706733 LAVA metadata
154 12:11:02.706841 - LAVA_JOB_ID=10605438
155 12:11:02.706940 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:11:02.707082 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:57) [common]
157 12:11:02.707184 skipped lava-vland-overlay
158 12:11:02.707294 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:11:02.707434 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:57) [common]
160 12:11:02.707528 skipped lava-multinode-overlay
161 12:11:02.707628 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:11:02.707712 start: 1.5.2.3 test-definition (timeout 00:09:57) [common]
163 12:11:02.707792 Loading test definitions
164 12:11:02.707893 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:57) [common]
165 12:11:02.707976 Using /lava-10605438 at stage 0
166 12:11:02.708420 uuid=10605438_1.5.2.3.1 testdef=None
167 12:11:02.708544 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:11:02.708663 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
169 12:11:02.709439 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:11:02.709811 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
172 12:11:02.710663 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:11:02.710902 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
175 12:11:02.711696 runner path: /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/0/tests/0_dmesg test_uuid 10605438_1.5.2.3.1
176 12:11:02.711898 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:11:02.712200 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:57) [common]
179 12:11:02.712311 Using /lava-10605438 at stage 1
180 12:11:02.712772 uuid=10605438_1.5.2.3.5 testdef=None
181 12:11:02.712894 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:11:02.713011 start: 1.5.2.3.6 test-overlay (timeout 00:09:57) [common]
183 12:11:02.713727 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:11:02.714098 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:57) [common]
186 12:11:02.715685 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 12:11:02.716081 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:57) [common]
189 12:11:02.717059 runner path: /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/1/tests/1_bootrr test_uuid 10605438_1.5.2.3.5
190 12:11:02.717260 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:11:02.717611 Creating lava-test-runner.conf files
193 12:11:02.717707 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/0 for stage 0
194 12:11:02.717829 - 0_dmesg
195 12:11:02.717939 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605438/lava-overlay-ceijjgib/lava-10605438/1 for stage 1
196 12:11:02.718065 - 1_bootrr
197 12:11:02.718192 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 12:11:02.718312 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
199 12:11:02.727604 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:11:02.727755 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
201 12:11:02.727877 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:11:02.728000 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 12:11:02.728138 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
204 12:11:02.983689 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:11:02.984102 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
206 12:11:02.984261 extracting modules file /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605438/extract-overlay-ramdisk-p475p2a2/ramdisk
207 12:11:03.289897 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:11:03.290113 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
209 12:11:03.290241 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605438/compress-overlay-do09fd5r/overlay-1.5.2.4.tar.gz to ramdisk
210 12:11:03.290349 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605438/compress-overlay-do09fd5r/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605438/extract-overlay-ramdisk-p475p2a2/ramdisk
211 12:11:03.303755 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:11:03.303935 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
213 12:11:03.304067 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:11:03.304197 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
215 12:11:03.304322 Building ramdisk /var/lib/lava/dispatcher/tmp/10605438/extract-overlay-ramdisk-p475p2a2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605438/extract-overlay-ramdisk-p475p2a2/ramdisk
216 12:11:03.656032 >> 143719 blocks
217 12:11:06.133896 rename /var/lib/lava/dispatcher/tmp/10605438/extract-overlay-ramdisk-p475p2a2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/ramdisk/ramdisk.cpio.gz
218 12:11:06.134384 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:11:06.134563 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
220 12:11:06.134712 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
221 12:11:06.134864 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/kernel/Image'
222 12:11:19.314891 Returned 0 in 13 seconds
223 12:11:19.415455 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/kernel/image.itb
224 12:11:19.874722 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:11:19.875102 output: Created: Tue Jun 6 13:11:19 2023
226 12:11:19.875210 output: Image 0 (kernel-1)
227 12:11:19.875314 output: Description:
228 12:11:19.875423 output: Created: Tue Jun 6 13:11:19 2023
229 12:11:19.875518 output: Type: Kernel Image
230 12:11:19.875614 output: Compression: lzma compressed
231 12:11:19.875708 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
232 12:11:19.875809 output: Architecture: AArch64
233 12:11:19.875904 output: OS: Linux
234 12:11:19.875995 output: Load Address: 0x00000000
235 12:11:19.876083 output: Entry Point: 0x00000000
236 12:11:19.876177 output: Hash algo: crc32
237 12:11:19.876270 output: Hash value: fd97082e
238 12:11:19.876356 output: Image 1 (fdt-1)
239 12:11:19.876444 output: Description: mt8192-asurada-spherion-r0
240 12:11:19.876531 output: Created: Tue Jun 6 13:11:19 2023
241 12:11:19.876617 output: Type: Flat Device Tree
242 12:11:19.876703 output: Compression: uncompressed
243 12:11:19.876788 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 12:11:19.876874 output: Architecture: AArch64
245 12:11:19.876960 output: Hash algo: crc32
246 12:11:19.877045 output: Hash value: 1df858fa
247 12:11:19.877130 output: Image 2 (ramdisk-1)
248 12:11:19.877215 output: Description: unavailable
249 12:11:19.877300 output: Created: Tue Jun 6 13:11:19 2023
250 12:11:19.877385 output: Type: RAMDisk Image
251 12:11:19.877470 output: Compression: Unknown Compression
252 12:11:19.877555 output: Data Size: 21247668 Bytes = 20749.68 KiB = 20.26 MiB
253 12:11:19.877641 output: Architecture: AArch64
254 12:11:19.877726 output: OS: Linux
255 12:11:19.877816 output: Load Address: unavailable
256 12:11:19.877904 output: Entry Point: unavailable
257 12:11:19.877989 output: Hash algo: crc32
258 12:11:19.878074 output: Hash value: 060cdaf5
259 12:11:19.878159 output: Default Configuration: 'conf-1'
260 12:11:19.878244 output: Configuration 0 (conf-1)
261 12:11:19.878328 output: Description: mt8192-asurada-spherion-r0
262 12:11:19.878413 output: Kernel: kernel-1
263 12:11:19.878498 output: Init Ramdisk: ramdisk-1
264 12:11:19.878583 output: FDT: fdt-1
265 12:11:19.878667 output: Loadables: kernel-1
266 12:11:19.878752 output:
267 12:11:19.878991 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 12:11:19.879122 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 12:11:19.879270 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 12:11:19.879410 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
271 12:11:19.879517 No LXC device requested
272 12:11:19.879630 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:11:19.879747 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
274 12:11:19.879856 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:11:19.879952 Checking files for TFTP limit of 4294967296 bytes.
276 12:11:19.880609 end: 1 tftp-deploy (duration 00:00:21) [common]
277 12:11:19.880750 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:11:19.880875 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:11:19.881039 substitutions:
280 12:11:19.881136 - {DTB}: 10605438/tftp-deploy-xxtps5kp/dtb/mt8192-asurada-spherion-r0.dtb
281 12:11:19.881229 - {INITRD}: 10605438/tftp-deploy-xxtps5kp/ramdisk/ramdisk.cpio.gz
282 12:11:19.881321 - {KERNEL}: 10605438/tftp-deploy-xxtps5kp/kernel/Image
283 12:11:19.881411 - {LAVA_MAC}: None
284 12:11:19.881499 - {PRESEED_CONFIG}: None
285 12:11:19.881588 - {PRESEED_LOCAL}: None
286 12:11:19.881675 - {RAMDISK}: 10605438/tftp-deploy-xxtps5kp/ramdisk/ramdisk.cpio.gz
287 12:11:19.881762 - {ROOT_PART}: None
288 12:11:19.881849 - {ROOT}: None
289 12:11:19.881935 - {SERVER_IP}: 192.168.201.1
290 12:11:19.882022 - {TEE}: None
291 12:11:19.882108 Parsed boot commands:
292 12:11:19.882193 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:11:19.882410 Parsed boot commands: tftpboot 192.168.201.1 10605438/tftp-deploy-xxtps5kp/kernel/image.itb 10605438/tftp-deploy-xxtps5kp/kernel/cmdline
294 12:11:19.882531 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:11:19.882662 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:11:19.882790 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:11:19.882911 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:11:19.883013 Not connected, no need to disconnect.
299 12:11:19.883127 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:11:19.883253 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:11:19.883373 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
302 12:11:19.887208 Setting prompt string to ['lava-test: # ']
303 12:11:19.887807 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:11:19.887921 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:11:19.888020 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:11:19.888122 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:11:19.888353 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 12:11:25.019652 >> Command sent successfully.
309 12:11:25.021943 Returned 0 in 5 seconds
310 12:11:25.122392 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:11:25.123026 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:11:25.123226 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:11:25.123411 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:11:25.123568 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:11:25.123716 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:11:25.124214 [Enter `^Ec?' for help]
318 12:11:25.295607
319 12:11:25.295762
320 12:11:25.295833 F0: 102B 0000
321 12:11:25.295901
322 12:11:25.295963 F3: 1001 0000 [0200]
323 12:11:25.298691
324 12:11:25.298778 F3: 1001 0000
325 12:11:25.298862
326 12:11:25.298954 F7: 102D 0000
327 12:11:25.299058
328 12:11:25.302187 F1: 0000 0000
329 12:11:25.302305
330 12:11:25.302392 V0: 0000 0000 [0001]
331 12:11:25.302501
332 12:11:25.305743 00: 0007 8000
333 12:11:25.305853
334 12:11:25.305956 01: 0000 0000
335 12:11:25.306060
336 12:11:25.309108 BP: 0C00 0209 [0000]
337 12:11:25.309217
338 12:11:25.309321 G0: 1182 0000
339 12:11:25.309423
340 12:11:25.312519 EC: 0000 0021 [4000]
341 12:11:25.312607
342 12:11:25.312713 S7: 0000 0000 [0000]
343 12:11:25.312819
344 12:11:25.315941 CC: 0000 0000 [0001]
345 12:11:25.316047
346 12:11:25.316151 T0: 0000 0040 [010F]
347 12:11:25.316253
348 12:11:25.316353 Jump to BL
349 12:11:25.316452
350 12:11:25.342987
351 12:11:25.343122
352 12:11:25.343229
353 12:11:25.349876 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:11:25.352632 ARM64: Exception handlers installed.
355 12:11:25.356727 ARM64: Testing exception
356 12:11:25.359507 ARM64: Done test exception
357 12:11:25.366649 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:11:25.377351 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:11:25.383814 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:11:25.393688 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:11:25.400847 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:11:25.407627 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:11:25.419748 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:11:25.425846 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:11:25.445579 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:11:25.448981 WDT: Last reset was cold boot
367 12:11:25.452578 SPI1(PAD0) initialized at 2873684 Hz
368 12:11:25.455232 SPI5(PAD0) initialized at 992727 Hz
369 12:11:25.458754 VBOOT: Loading verstage.
370 12:11:25.465415 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:11:25.470270 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:11:25.473519 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:11:25.476810 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:11:25.483262 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:11:25.490300 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:11:25.500812 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 12:11:25.500917
378 12:11:25.501000
379 12:11:25.510831 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:11:25.514232 ARM64: Exception handlers installed.
381 12:11:25.517697 ARM64: Testing exception
382 12:11:25.517827 ARM64: Done test exception
383 12:11:25.524467 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:11:25.527838 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:11:25.541306 Probing TPM: . done!
386 12:11:25.541407 TPM ready after 0 ms
387 12:11:25.548279 Connected to device vid:did:rid of 1ae0:0028:00
388 12:11:25.555792 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 12:11:25.617346 Initialized TPM device CR50 revision 0
390 12:11:25.626684 tlcl_send_startup: Startup return code is 0
391 12:11:25.626810 TPM: setup succeeded
392 12:11:25.638343 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:11:25.646665 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:11:25.658958 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:11:25.669320 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:11:25.672747 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:11:25.676146 in-header: 03 07 00 00 08 00 00 00
398 12:11:25.680290 in-data: aa e4 47 04 13 02 00 00
399 12:11:25.683781 Chrome EC: UHEPI supported
400 12:11:25.690901 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:11:25.691000 in-header: 03 95 00 00 08 00 00 00
402 12:11:25.695148 in-data: 18 20 20 08 00 00 00 00
403 12:11:25.695273 Phase 1
404 12:11:25.702823 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:11:25.706104 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:11:25.713827 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:11:25.713918 Recovery requested (1009000e)
408 12:11:25.726879 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:11:25.730193 tlcl_extend: response is 0
410 12:11:25.738930 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:11:25.744988 tlcl_extend: response is 0
412 12:11:25.751201 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:11:25.771076 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 12:11:25.777964 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:11:25.778059
416 12:11:25.778128
417 12:11:25.788181 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:11:25.791643 ARM64: Exception handlers installed.
419 12:11:25.794909 ARM64: Testing exception
420 12:11:25.795005 ARM64: Done test exception
421 12:11:25.817400 pmic_efuse_setting: Set efuses in 11 msecs
422 12:11:25.820669 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:11:25.827281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:11:25.830698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:11:25.837819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:11:25.841912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:11:25.845147 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:11:25.848643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:11:25.856123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:11:25.860090 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:11:25.863516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:11:25.867669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:11:25.874735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:11:25.878741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:11:25.882073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:11:25.889158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:11:25.896532 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:11:25.900416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:11:25.908050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:11:25.912010 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:11:25.919034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:11:25.922790 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:11:25.929973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:11:25.933881 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:11:25.941782 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:11:25.945608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:11:25.948943 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:11:25.956052 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:11:25.963223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:11:25.967253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:11:25.970804 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:11:25.974155 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:11:25.982062 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:11:25.985494 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:11:25.992896 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:11:25.996436 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:11:26.000525 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:11:26.007148 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:11:26.011220 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:11:26.014836 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:11:26.018820 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:11:26.026207 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:11:26.029490 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:11:26.033278 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:11:26.037068 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:11:26.041048 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:11:26.048303 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:11:26.052275 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:11:26.056153 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:11:26.060045 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:11:26.063438 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:11:26.066808 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:11:26.070766 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:11:26.078453 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:11:26.088761 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:11:26.092885 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:11:26.099824 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:11:26.111007 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:11:26.115204 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:11:26.119031 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:11:26.122423 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:11:26.130429 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
483 12:11:26.133924 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:11:26.138518 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 12:11:26.146077 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:11:26.154540 [RTC]rtc_get_frequency_meter,154: input=15, output=759
487 12:11:26.163843 [RTC]rtc_get_frequency_meter,154: input=23, output=941
488 12:11:26.173185 [RTC]rtc_get_frequency_meter,154: input=19, output=851
489 12:11:26.184032 [RTC]rtc_get_frequency_meter,154: input=17, output=805
490 12:11:26.192872 [RTC]rtc_get_frequency_meter,154: input=16, output=782
491 12:11:26.202625 [RTC]rtc_get_frequency_meter,154: input=16, output=783
492 12:11:26.211681 [RTC]rtc_get_frequency_meter,154: input=17, output=805
493 12:11:26.215574 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 12:11:26.219032 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 12:11:26.223061 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 12:11:26.230577 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 12:11:26.234622 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 12:11:26.238082 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 12:11:26.241531 ADC[4]: Raw value=906573 ID=7
500 12:11:26.241616 ADC[3]: Raw value=213810 ID=1
501 12:11:26.244980 RAM Code: 0x71
502 12:11:26.248890 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 12:11:26.252903 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 12:11:26.263971 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 12:11:26.271148 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 12:11:26.271294 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 12:11:26.275215 in-header: 03 07 00 00 08 00 00 00
508 12:11:26.279064 in-data: aa e4 47 04 13 02 00 00
509 12:11:26.282388 Chrome EC: UHEPI supported
510 12:11:26.289197 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 12:11:26.293467 in-header: 03 95 00 00 08 00 00 00
512 12:11:26.296824 in-data: 18 20 20 08 00 00 00 00
513 12:11:26.296926 MRC: failed to locate region type 0.
514 12:11:26.304517 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 12:11:26.307954 DRAM-K: Running full calibration
516 12:11:26.315287 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 12:11:26.315399 header.status = 0x0
518 12:11:26.319218 header.version = 0x6 (expected: 0x6)
519 12:11:26.322797 header.size = 0xd00 (expected: 0xd00)
520 12:11:26.322884 header.flags = 0x0
521 12:11:26.329648 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 12:11:26.349174 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 12:11:26.356704 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 12:11:26.356821 dram_init: ddr_geometry: 2
525 12:11:26.360747 [EMI] MDL number = 2
526 12:11:26.360859 [EMI] Get MDL freq = 0
527 12:11:26.363998 dram_init: ddr_type: 0
528 12:11:26.368008 is_discrete_lpddr4: 1
529 12:11:26.368111 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 12:11:26.368228
531 12:11:26.368294
532 12:11:26.371957 [Bian_co] ETT version 0.0.0.1
533 12:11:26.375940 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 12:11:26.376028
535 12:11:26.379908 dramc_set_vcore_voltage set vcore to 650000
536 12:11:26.383860 Read voltage for 800, 4
537 12:11:26.383964 Vio18 = 0
538 12:11:26.387010 Vcore = 650000
539 12:11:26.387186 Vdram = 0
540 12:11:26.387292 Vddq = 0
541 12:11:26.387414 Vmddr = 0
542 12:11:26.390916 dram_init: config_dvfs: 1
543 12:11:26.394816 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 12:11:26.402416 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 12:11:26.405726 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 12:11:26.409894 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 12:11:26.413483 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 12:11:26.417530 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 12:11:26.417636 MEM_TYPE=3, freq_sel=18
550 12:11:26.420892 sv_algorithm_assistance_LP4_1600
551 12:11:26.424210 ============ PULL DRAM RESETB DOWN ============
552 12:11:26.431464 ========== PULL DRAM RESETB DOWN end =========
553 12:11:26.434534 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 12:11:26.437914 ===================================
555 12:11:26.441159 LPDDR4 DRAM CONFIGURATION
556 12:11:26.445244 ===================================
557 12:11:26.445328 EX_ROW_EN[0] = 0x0
558 12:11:26.448804 EX_ROW_EN[1] = 0x0
559 12:11:26.448887 LP4Y_EN = 0x0
560 12:11:26.452721 WORK_FSP = 0x0
561 12:11:26.452805 WL = 0x2
562 12:11:26.456166 RL = 0x2
563 12:11:26.456274 BL = 0x2
564 12:11:26.456369 RPST = 0x0
565 12:11:26.459636 RD_PRE = 0x0
566 12:11:26.459719 WR_PRE = 0x1
567 12:11:26.463722 WR_PST = 0x0
568 12:11:26.463806 DBI_WR = 0x0
569 12:11:26.466906 DBI_RD = 0x0
570 12:11:26.467005 OTF = 0x1
571 12:11:26.470314 ===================================
572 12:11:26.473605 ===================================
573 12:11:26.476836 ANA top config
574 12:11:26.480370 ===================================
575 12:11:26.480456 DLL_ASYNC_EN = 0
576 12:11:26.483690 ALL_SLAVE_EN = 1
577 12:11:26.486955 NEW_RANK_MODE = 1
578 12:11:26.490442 DLL_IDLE_MODE = 1
579 12:11:26.493734 LP45_APHY_COMB_EN = 1
580 12:11:26.493820 TX_ODT_DIS = 1
581 12:11:26.497477 NEW_8X_MODE = 1
582 12:11:26.501211 ===================================
583 12:11:26.504556 ===================================
584 12:11:26.507957 data_rate = 1600
585 12:11:26.510718 CKR = 1
586 12:11:26.510804 DQ_P2S_RATIO = 8
587 12:11:26.514118 ===================================
588 12:11:26.517491 CA_P2S_RATIO = 8
589 12:11:26.520831 DQ_CA_OPEN = 0
590 12:11:26.524285 DQ_SEMI_OPEN = 0
591 12:11:26.527649 CA_SEMI_OPEN = 0
592 12:11:26.530969 CA_FULL_RATE = 0
593 12:11:26.531083 DQ_CKDIV4_EN = 1
594 12:11:26.534427 CA_CKDIV4_EN = 1
595 12:11:26.537826 CA_PREDIV_EN = 0
596 12:11:26.541265 PH8_DLY = 0
597 12:11:26.544514 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 12:11:26.544607 DQ_AAMCK_DIV = 4
599 12:11:26.547748 CA_AAMCK_DIV = 4
600 12:11:26.551402 CA_ADMCK_DIV = 4
601 12:11:26.553993 DQ_TRACK_CA_EN = 0
602 12:11:26.557563 CA_PICK = 800
603 12:11:26.561614 CA_MCKIO = 800
604 12:11:26.561701 MCKIO_SEMI = 0
605 12:11:26.565096 PLL_FREQ = 3068
606 12:11:26.568445 DQ_UI_PI_RATIO = 32
607 12:11:26.572529 CA_UI_PI_RATIO = 0
608 12:11:26.576577 ===================================
609 12:11:26.580455 ===================================
610 12:11:26.580542 memory_type:LPDDR4
611 12:11:26.584425 GP_NUM : 10
612 12:11:26.584513 SRAM_EN : 1
613 12:11:26.587808 MD32_EN : 0
614 12:11:26.591816 ===================================
615 12:11:26.591939 [ANA_INIT] >>>>>>>>>>>>>>
616 12:11:26.596006 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 12:11:26.598823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 12:11:26.602016 ===================================
619 12:11:26.605424 data_rate = 1600,PCW = 0X7600
620 12:11:26.609213 ===================================
621 12:11:26.612610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 12:11:26.616007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 12:11:26.622267 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 12:11:26.625623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 12:11:26.629000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 12:11:26.632205 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 12:11:26.635623 [ANA_INIT] flow start
628 12:11:26.638993 [ANA_INIT] PLL >>>>>>>>
629 12:11:26.639101 [ANA_INIT] PLL <<<<<<<<
630 12:11:26.642445 [ANA_INIT] MIDPI >>>>>>>>
631 12:11:26.645806 [ANA_INIT] MIDPI <<<<<<<<
632 12:11:26.645891 [ANA_INIT] DLL >>>>>>>>
633 12:11:26.648975 [ANA_INIT] flow end
634 12:11:26.652316 ============ LP4 DIFF to SE enter ============
635 12:11:26.655795 ============ LP4 DIFF to SE exit ============
636 12:11:26.659125 [ANA_INIT] <<<<<<<<<<<<<
637 12:11:26.662645 [Flow] Enable top DCM control >>>>>
638 12:11:26.666024 [Flow] Enable top DCM control <<<<<
639 12:11:26.669550 Enable DLL master slave shuffle
640 12:11:26.676272 ==============================================================
641 12:11:26.676357 Gating Mode config
642 12:11:26.682382 ==============================================================
643 12:11:26.682467 Config description:
644 12:11:26.693008 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 12:11:26.699723 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 12:11:26.706296 SELPH_MODE 0: By rank 1: By Phase
647 12:11:26.709583 ==============================================================
648 12:11:26.712998 GAT_TRACK_EN = 1
649 12:11:26.716235 RX_GATING_MODE = 2
650 12:11:26.719657 RX_GATING_TRACK_MODE = 2
651 12:11:26.723046 SELPH_MODE = 1
652 12:11:26.726403 PICG_EARLY_EN = 1
653 12:11:26.729921 VALID_LAT_VALUE = 1
654 12:11:26.732637 ==============================================================
655 12:11:26.736586 Enter into Gating configuration >>>>
656 12:11:26.739178 Exit from Gating configuration <<<<
657 12:11:26.742693 Enter into DVFS_PRE_config >>>>>
658 12:11:26.756500 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 12:11:26.759962 Exit from DVFS_PRE_config <<<<<
660 12:11:26.763298 Enter into PICG configuration >>>>
661 12:11:26.763429 Exit from PICG configuration <<<<
662 12:11:26.766108 [RX_INPUT] configuration >>>>>
663 12:11:26.770034 [RX_INPUT] configuration <<<<<
664 12:11:26.776169 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 12:11:26.779553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 12:11:26.786601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 12:11:26.793232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 12:11:26.799635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 12:11:26.806258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 12:11:26.809604 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 12:11:26.812882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 12:11:26.816165 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 12:11:26.822765 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 12:11:26.826744 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 12:11:26.829479 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 12:11:26.832915 ===================================
677 12:11:26.836370 LPDDR4 DRAM CONFIGURATION
678 12:11:26.839648 ===================================
679 12:11:26.839734 EX_ROW_EN[0] = 0x0
680 12:11:26.842918 EX_ROW_EN[1] = 0x0
681 12:11:26.846478 LP4Y_EN = 0x0
682 12:11:26.846564 WORK_FSP = 0x0
683 12:11:26.849756 WL = 0x2
684 12:11:26.849843 RL = 0x2
685 12:11:26.853117 BL = 0x2
686 12:11:26.853203 RPST = 0x0
687 12:11:26.856701 RD_PRE = 0x0
688 12:11:26.856786 WR_PRE = 0x1
689 12:11:26.859934 WR_PST = 0x0
690 12:11:26.860019 DBI_WR = 0x0
691 12:11:26.863261 DBI_RD = 0x0
692 12:11:26.863373 OTF = 0x1
693 12:11:26.866662 ===================================
694 12:11:26.869921 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 12:11:26.876711 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 12:11:26.880186 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:11:26.883468 ===================================
698 12:11:26.886718 LPDDR4 DRAM CONFIGURATION
699 12:11:26.890161 ===================================
700 12:11:26.890248 EX_ROW_EN[0] = 0x10
701 12:11:26.892958 EX_ROW_EN[1] = 0x0
702 12:11:26.893043 LP4Y_EN = 0x0
703 12:11:26.896458 WORK_FSP = 0x0
704 12:11:26.896546 WL = 0x2
705 12:11:26.899616 RL = 0x2
706 12:11:26.899702 BL = 0x2
707 12:11:26.903491 RPST = 0x0
708 12:11:26.903576 RD_PRE = 0x0
709 12:11:26.906772 WR_PRE = 0x1
710 12:11:26.906857 WR_PST = 0x0
711 12:11:26.910097 DBI_WR = 0x0
712 12:11:26.913419 DBI_RD = 0x0
713 12:11:26.913504 OTF = 0x1
714 12:11:26.916831 ===================================
715 12:11:26.923357 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 12:11:26.926667 nWR fixed to 40
717 12:11:26.929850 [ModeRegInit_LP4] CH0 RK0
718 12:11:26.929935 [ModeRegInit_LP4] CH0 RK1
719 12:11:26.933630 [ModeRegInit_LP4] CH1 RK0
720 12:11:26.936421 [ModeRegInit_LP4] CH1 RK1
721 12:11:26.936515 match AC timing 13
722 12:11:26.943210 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 12:11:26.946538 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 12:11:26.950335 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 12:11:26.957082 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 12:11:26.960524 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 12:11:26.960612 [EMI DOE] emi_dcm 0
728 12:11:26.967209 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 12:11:26.967297 ==
730 12:11:26.969988 Dram Type= 6, Freq= 0, CH_0, rank 0
731 12:11:26.973353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 12:11:26.973440 ==
733 12:11:26.980264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 12:11:26.983434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 12:11:26.994185 [CA 0] Center 36 (6~67) winsize 62
736 12:11:26.997671 [CA 1] Center 36 (6~67) winsize 62
737 12:11:27.000982 [CA 2] Center 34 (4~65) winsize 62
738 12:11:27.004449 [CA 3] Center 34 (4~64) winsize 61
739 12:11:27.007642 [CA 4] Center 33 (2~64) winsize 63
740 12:11:27.010869 [CA 5] Center 32 (2~62) winsize 61
741 12:11:27.010955
742 12:11:27.014226 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 12:11:27.014311
744 12:11:27.018105 [CATrainingPosCal] consider 1 rank data
745 12:11:27.021495 u2DelayCellTimex100 = 270/100 ps
746 12:11:27.024906 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
747 12:11:27.028063 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
748 12:11:27.031442 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
749 12:11:27.038007 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
750 12:11:27.041472 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
751 12:11:27.044759 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
752 12:11:27.044845
753 12:11:27.048227 CA PerBit enable=1, Macro0, CA PI delay=32
754 12:11:27.048314
755 12:11:27.051375 [CBTSetCACLKResult] CA Dly = 32
756 12:11:27.051461 CS Dly: 5 (0~36)
757 12:11:27.051529 ==
758 12:11:27.054682 Dram Type= 6, Freq= 0, CH_0, rank 1
759 12:11:27.058468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 12:11:27.061785 ==
761 12:11:27.064630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 12:11:27.071432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 12:11:27.080725 [CA 0] Center 36 (6~67) winsize 62
764 12:11:27.083569 [CA 1] Center 36 (6~67) winsize 62
765 12:11:27.086964 [CA 2] Center 34 (4~65) winsize 62
766 12:11:27.090210 [CA 3] Center 33 (3~64) winsize 62
767 12:11:27.093418 [CA 4] Center 32 (2~63) winsize 62
768 12:11:27.096963 [CA 5] Center 32 (2~63) winsize 62
769 12:11:27.097078
770 12:11:27.100256 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 12:11:27.100340
772 12:11:27.103633 [CATrainingPosCal] consider 2 rank data
773 12:11:27.106986 u2DelayCellTimex100 = 270/100 ps
774 12:11:27.110485 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
775 12:11:27.113973 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
776 12:11:27.120419 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
777 12:11:27.123693 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
778 12:11:27.127036 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
779 12:11:27.130790 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
780 12:11:27.130881
781 12:11:27.134046 CA PerBit enable=1, Macro0, CA PI delay=32
782 12:11:27.134122
783 12:11:27.137355 [CBTSetCACLKResult] CA Dly = 32
784 12:11:27.137435 CS Dly: 5 (0~37)
785 12:11:27.137501
786 12:11:27.140864 ----->DramcWriteLeveling(PI) begin...
787 12:11:27.140941 ==
788 12:11:27.144718 Dram Type= 6, Freq= 0, CH_0, rank 0
789 12:11:27.148135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 12:11:27.148224 ==
791 12:11:27.152194 Write leveling (Byte 0): 32 => 32
792 12:11:27.155674 Write leveling (Byte 1): 31 => 31
793 12:11:27.158961 DramcWriteLeveling(PI) end<-----
794 12:11:27.159085
795 12:11:27.159188 ==
796 12:11:27.162218 Dram Type= 6, Freq= 0, CH_0, rank 0
797 12:11:27.165599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 12:11:27.165876 ==
799 12:11:27.169554 [Gating] SW mode calibration
800 12:11:27.176538 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 12:11:27.183210 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 12:11:27.186719 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 12:11:27.190052 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 12:11:27.196722 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 12:11:27.200112 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:11:27.203590 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:11:27.207103 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:11:27.213795 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:11:27.217048 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:11:27.220643 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:11:27.227201 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:11:27.230401 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:11:27.233911 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:11:27.240446 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:11:27.243815 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:11:27.247164 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:11:27.253705 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:11:27.257015 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:11:27.260423 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 12:11:27.267093 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
821 12:11:27.270591 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 12:11:27.273985 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:11:27.277375 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:11:27.283750 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:11:27.287370 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:11:27.290119 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:11:27.296940 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:11:27.300354 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
829 12:11:27.303661 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
830 12:11:27.310606 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 12:11:27.314026 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 12:11:27.317450 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 12:11:27.324207 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 12:11:27.327565 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 12:11:27.330839 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
836 12:11:27.337385 0 10 8 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
837 12:11:27.340575 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 12:11:27.343921 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:11:27.347248 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:11:27.353904 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:11:27.357307 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:11:27.360581 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:11:27.367184 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:11:27.370542 0 11 8 | B1->B0 | 2f2f 4141 | 0 0 | (0 0) (0 0)
845 12:11:27.373841 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 12:11:27.380777 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:11:27.384197 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:11:27.387533 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 12:11:27.394262 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:11:27.397582 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 12:11:27.401058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 12:11:27.407858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
853 12:11:27.411224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:11:27.414644 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:11:27.417434 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:11:27.424275 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:11:27.427794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:11:27.431217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 12:11:27.438041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 12:11:27.441325 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 12:11:27.444404 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 12:11:27.451167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 12:11:27.454214 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 12:11:27.457633 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 12:11:27.464427 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 12:11:27.467711 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 12:11:27.470764 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 12:11:27.477857 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 12:11:27.477943 Total UI for P1: 0, mck2ui 16
870 12:11:27.484767 best dqsien dly found for B0: ( 0, 14, 4)
871 12:11:27.487582 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 12:11:27.490912 Total UI for P1: 0, mck2ui 16
873 12:11:27.494990 best dqsien dly found for B1: ( 0, 14, 8)
874 12:11:27.498389 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 12:11:27.501848 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 12:11:27.501933
877 12:11:27.505286 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 12:11:27.508604 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 12:11:27.512018 [Gating] SW calibration Done
880 12:11:27.512103 ==
881 12:11:27.515620 Dram Type= 6, Freq= 0, CH_0, rank 0
882 12:11:27.519019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 12:11:27.519146 ==
884 12:11:27.519245 RX Vref Scan: 0
885 12:11:27.519346
886 12:11:27.522383 RX Vref 0 -> 0, step: 1
887 12:11:27.522468
888 12:11:27.525730 RX Delay -130 -> 252, step: 16
889 12:11:27.529101 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 12:11:27.532547 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
891 12:11:27.538641 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 12:11:27.542018 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 12:11:27.545541 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 12:11:27.548764 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 12:11:27.552604 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 12:11:27.559066 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
897 12:11:27.562473 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
898 12:11:27.565674 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
899 12:11:27.569010 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
900 12:11:27.572136 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
901 12:11:27.579454 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 12:11:27.582490 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
903 12:11:27.585804 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
904 12:11:27.589316 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 12:11:27.589402 ==
906 12:11:27.592753 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:11:27.596066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:11:27.599350 ==
909 12:11:27.599448 DQS Delay:
910 12:11:27.599514 DQS0 = 0, DQS1 = 0
911 12:11:27.602918 DQM Delay:
912 12:11:27.603021 DQM0 = 89, DQM1 = 82
913 12:11:27.605693 DQ Delay:
914 12:11:27.605819 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
915 12:11:27.609079 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
916 12:11:27.612449 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
917 12:11:27.615763 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
918 12:11:27.619153
919 12:11:27.619262
920 12:11:27.619388 ==
921 12:11:27.622634 Dram Type= 6, Freq= 0, CH_0, rank 0
922 12:11:27.626023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 12:11:27.626121 ==
924 12:11:27.626189
925 12:11:27.626252
926 12:11:27.629463 TX Vref Scan disable
927 12:11:27.629549 == TX Byte 0 ==
928 12:11:27.635504 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 12:11:27.638916 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 12:11:27.639060 == TX Byte 1 ==
931 12:11:27.645695 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
932 12:11:27.649015 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
933 12:11:27.649100 ==
934 12:11:27.652545 Dram Type= 6, Freq= 0, CH_0, rank 0
935 12:11:27.655658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 12:11:27.655742 ==
937 12:11:27.669233 TX Vref=22, minBit 4, minWin=27, winSum=447
938 12:11:27.672661 TX Vref=24, minBit 10, minWin=27, winSum=452
939 12:11:27.675821 TX Vref=26, minBit 0, minWin=28, winSum=455
940 12:11:27.679735 TX Vref=28, minBit 8, minWin=28, winSum=459
941 12:11:27.682334 TX Vref=30, minBit 4, minWin=28, winSum=459
942 12:11:27.686200 TX Vref=32, minBit 0, minWin=28, winSum=455
943 12:11:27.692530 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
944 12:11:27.692616
945 12:11:27.696394 Final TX Range 1 Vref 28
946 12:11:27.696536
947 12:11:27.696617 ==
948 12:11:27.699121 Dram Type= 6, Freq= 0, CH_0, rank 0
949 12:11:27.702558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 12:11:27.702643 ==
951 12:11:27.702710
952 12:11:27.705820
953 12:11:27.705904 TX Vref Scan disable
954 12:11:27.709354 == TX Byte 0 ==
955 12:11:27.712887 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
956 12:11:27.716290 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
957 12:11:27.719736 == TX Byte 1 ==
958 12:11:27.722597 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
959 12:11:27.725964 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
960 12:11:27.726048
961 12:11:27.729395 [DATLAT]
962 12:11:27.729478 Freq=800, CH0 RK0
963 12:11:27.729545
964 12:11:27.732800 DATLAT Default: 0xa
965 12:11:27.732884 0, 0xFFFF, sum = 0
966 12:11:27.736166 1, 0xFFFF, sum = 0
967 12:11:27.736255 2, 0xFFFF, sum = 0
968 12:11:27.739659 3, 0xFFFF, sum = 0
969 12:11:27.739771 4, 0xFFFF, sum = 0
970 12:11:27.742447 5, 0xFFFF, sum = 0
971 12:11:27.742533 6, 0xFFFF, sum = 0
972 12:11:27.745912 7, 0xFFFF, sum = 0
973 12:11:27.749244 8, 0xFFFF, sum = 0
974 12:11:27.749330 9, 0x0, sum = 1
975 12:11:27.749399 10, 0x0, sum = 2
976 12:11:27.752674 11, 0x0, sum = 3
977 12:11:27.752762 12, 0x0, sum = 4
978 12:11:27.755972 best_step = 10
979 12:11:27.756056
980 12:11:27.756123 ==
981 12:11:27.759452 Dram Type= 6, Freq= 0, CH_0, rank 0
982 12:11:27.762809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 12:11:27.762894 ==
984 12:11:27.766216 RX Vref Scan: 1
985 12:11:27.766315
986 12:11:27.766396 Set Vref Range= 32 -> 127
987 12:11:27.766461
988 12:11:27.769474 RX Vref 32 -> 127, step: 1
989 12:11:27.769558
990 12:11:27.772822 RX Delay -79 -> 252, step: 8
991 12:11:27.772907
992 12:11:27.775925 Set Vref, RX VrefLevel [Byte0]: 32
993 12:11:27.779939 [Byte1]: 32
994 12:11:27.780030
995 12:11:27.782678 Set Vref, RX VrefLevel [Byte0]: 33
996 12:11:27.786430 [Byte1]: 33
997 12:11:27.789635
998 12:11:27.789750 Set Vref, RX VrefLevel [Byte0]: 34
999 12:11:27.792765 [Byte1]: 34
1000 12:11:27.796724
1001 12:11:27.796832 Set Vref, RX VrefLevel [Byte0]: 35
1002 12:11:27.800010 [Byte1]: 35
1003 12:11:27.805093
1004 12:11:27.805217 Set Vref, RX VrefLevel [Byte0]: 36
1005 12:11:27.808237 [Byte1]: 36
1006 12:11:27.812625
1007 12:11:27.812758 Set Vref, RX VrefLevel [Byte0]: 37
1008 12:11:27.815988 [Byte1]: 37
1009 12:11:27.820080
1010 12:11:27.820197 Set Vref, RX VrefLevel [Byte0]: 38
1011 12:11:27.823356 [Byte1]: 38
1012 12:11:27.828056
1013 12:11:27.828141 Set Vref, RX VrefLevel [Byte0]: 39
1014 12:11:27.830915 [Byte1]: 39
1015 12:11:27.834935
1016 12:11:27.835055 Set Vref, RX VrefLevel [Byte0]: 40
1017 12:11:27.838538 [Byte1]: 40
1018 12:11:27.842569
1019 12:11:27.842679 Set Vref, RX VrefLevel [Byte0]: 41
1020 12:11:27.845299 [Byte1]: 41
1021 12:11:27.850035
1022 12:11:27.850152 Set Vref, RX VrefLevel [Byte0]: 42
1023 12:11:27.853376 [Byte1]: 42
1024 12:11:27.857502
1025 12:11:27.857588 Set Vref, RX VrefLevel [Byte0]: 43
1026 12:11:27.860829 [Byte1]: 43
1027 12:11:27.864899
1028 12:11:27.865008 Set Vref, RX VrefLevel [Byte0]: 44
1029 12:11:27.868271 [Byte1]: 44
1030 12:11:27.872430
1031 12:11:27.872539 Set Vref, RX VrefLevel [Byte0]: 45
1032 12:11:27.875793 [Byte1]: 45
1033 12:11:27.879813
1034 12:11:27.879901 Set Vref, RX VrefLevel [Byte0]: 46
1035 12:11:27.883063 [Byte1]: 46
1036 12:11:27.887485
1037 12:11:27.887577 Set Vref, RX VrefLevel [Byte0]: 47
1038 12:11:27.890668 [Byte1]: 47
1039 12:11:27.895129
1040 12:11:27.895215 Set Vref, RX VrefLevel [Byte0]: 48
1041 12:11:27.898348 [Byte1]: 48
1042 12:11:27.902736
1043 12:11:27.902853 Set Vref, RX VrefLevel [Byte0]: 49
1044 12:11:27.905759 [Byte1]: 49
1045 12:11:27.910306
1046 12:11:27.910392 Set Vref, RX VrefLevel [Byte0]: 50
1047 12:11:27.913615 [Byte1]: 50
1048 12:11:27.918041
1049 12:11:27.918141 Set Vref, RX VrefLevel [Byte0]: 51
1050 12:11:27.921273 [Byte1]: 51
1051 12:11:27.925442
1052 12:11:27.925527 Set Vref, RX VrefLevel [Byte0]: 52
1053 12:11:27.928582 [Byte1]: 52
1054 12:11:27.932732
1055 12:11:27.932842 Set Vref, RX VrefLevel [Byte0]: 53
1056 12:11:27.936218 [Byte1]: 53
1057 12:11:27.940415
1058 12:11:27.940495 Set Vref, RX VrefLevel [Byte0]: 54
1059 12:11:27.943754 [Byte1]: 54
1060 12:11:27.947930
1061 12:11:27.948010 Set Vref, RX VrefLevel [Byte0]: 55
1062 12:11:27.951377 [Byte1]: 55
1063 12:11:27.955410
1064 12:11:27.955511 Set Vref, RX VrefLevel [Byte0]: 56
1065 12:11:27.958860 [Byte1]: 56
1066 12:11:27.962981
1067 12:11:27.963064 Set Vref, RX VrefLevel [Byte0]: 57
1068 12:11:27.966392 [Byte1]: 57
1069 12:11:27.970457
1070 12:11:27.970534 Set Vref, RX VrefLevel [Byte0]: 58
1071 12:11:27.973933 [Byte1]: 58
1072 12:11:27.978022
1073 12:11:27.978105 Set Vref, RX VrefLevel [Byte0]: 59
1074 12:11:27.981491 [Byte1]: 59
1075 12:11:27.985477
1076 12:11:27.985587 Set Vref, RX VrefLevel [Byte0]: 60
1077 12:11:27.988858 [Byte1]: 60
1078 12:11:27.993516
1079 12:11:27.993600 Set Vref, RX VrefLevel [Byte0]: 61
1080 12:11:27.996808 [Byte1]: 61
1081 12:11:28.000820
1082 12:11:28.000904 Set Vref, RX VrefLevel [Byte0]: 62
1083 12:11:28.004142 [Byte1]: 62
1084 12:11:28.008470
1085 12:11:28.008554 Set Vref, RX VrefLevel [Byte0]: 63
1086 12:11:28.011551 [Byte1]: 63
1087 12:11:28.015826
1088 12:11:28.015909 Set Vref, RX VrefLevel [Byte0]: 64
1089 12:11:28.019071 [Byte1]: 64
1090 12:11:28.023473
1091 12:11:28.023558 Set Vref, RX VrefLevel [Byte0]: 65
1092 12:11:28.026710 [Byte1]: 65
1093 12:11:28.030968
1094 12:11:28.031053 Set Vref, RX VrefLevel [Byte0]: 66
1095 12:11:28.034274 [Byte1]: 66
1096 12:11:28.038653
1097 12:11:28.038740 Set Vref, RX VrefLevel [Byte0]: 67
1098 12:11:28.042071 [Byte1]: 67
1099 12:11:28.046293
1100 12:11:28.046378 Set Vref, RX VrefLevel [Byte0]: 68
1101 12:11:28.049625 [Byte1]: 68
1102 12:11:28.053805
1103 12:11:28.053889 Set Vref, RX VrefLevel [Byte0]: 69
1104 12:11:28.057139 [Byte1]: 69
1105 12:11:28.061440
1106 12:11:28.061524 Set Vref, RX VrefLevel [Byte0]: 70
1107 12:11:28.064790 [Byte1]: 70
1108 12:11:28.068907
1109 12:11:28.068992 Set Vref, RX VrefLevel [Byte0]: 71
1110 12:11:28.072175 [Byte1]: 71
1111 12:11:28.076381
1112 12:11:28.076495 Set Vref, RX VrefLevel [Byte0]: 72
1113 12:11:28.079688 [Byte1]: 72
1114 12:11:28.083694
1115 12:11:28.083804 Set Vref, RX VrefLevel [Byte0]: 73
1116 12:11:28.087032 [Byte1]: 73
1117 12:11:28.091153
1118 12:11:28.091281 Set Vref, RX VrefLevel [Byte0]: 74
1119 12:11:28.094641 [Byte1]: 74
1120 12:11:28.098692
1121 12:11:28.098802 Set Vref, RX VrefLevel [Byte0]: 75
1122 12:11:28.101957 [Byte1]: 75
1123 12:11:28.106772
1124 12:11:28.106863 Set Vref, RX VrefLevel [Byte0]: 76
1125 12:11:28.109976 [Byte1]: 76
1126 12:11:28.113944
1127 12:11:28.114100 Final RX Vref Byte 0 = 61 to rank0
1128 12:11:28.117338 Final RX Vref Byte 1 = 58 to rank0
1129 12:11:28.120523 Final RX Vref Byte 0 = 61 to rank1
1130 12:11:28.124093 Final RX Vref Byte 1 = 58 to rank1==
1131 12:11:28.127290 Dram Type= 6, Freq= 0, CH_0, rank 0
1132 12:11:28.133897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 12:11:28.133982 ==
1134 12:11:28.134049 DQS Delay:
1135 12:11:28.134111 DQS0 = 0, DQS1 = 0
1136 12:11:28.137112 DQM Delay:
1137 12:11:28.137196 DQM0 = 91, DQM1 = 85
1138 12:11:28.140908 DQ Delay:
1139 12:11:28.144137 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1140 12:11:28.144220 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1141 12:11:28.147213 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1142 12:11:28.151231 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1143 12:11:28.154745
1144 12:11:28.154826
1145 12:11:28.160933 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1146 12:11:28.164245 CH0 RK0: MR19=606, MR18=4E45
1147 12:11:28.171129 CH0_RK0: MR19=0x606, MR18=0x4E45, DQSOSC=390, MR23=63, INC=97, DEC=64
1148 12:11:28.171213
1149 12:11:28.174443 ----->DramcWriteLeveling(PI) begin...
1150 12:11:28.174527 ==
1151 12:11:28.177865 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 12:11:28.181419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1153 12:11:28.181503 ==
1154 12:11:28.184758 Write leveling (Byte 0): 34 => 34
1155 12:11:28.187624 Write leveling (Byte 1): 28 => 28
1156 12:11:28.190951 DramcWriteLeveling(PI) end<-----
1157 12:11:28.191034
1158 12:11:28.191099 ==
1159 12:11:28.194320 Dram Type= 6, Freq= 0, CH_0, rank 1
1160 12:11:28.197641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1161 12:11:28.197775 ==
1162 12:11:28.200980 [Gating] SW mode calibration
1163 12:11:28.207703 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1164 12:11:28.214330 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1165 12:11:28.258646 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1166 12:11:28.259066 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1167 12:11:28.259140 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 12:11:28.259206 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:11:28.259269 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:11:28.259337 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:11:28.259411 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:11:28.259473 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:11:28.259531 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:11:28.259948 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:11:28.274127 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:11:28.274396 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:11:28.274467 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:11:28.277024 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:11:28.280293 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:11:28.283675 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:11:28.287099 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:11:28.293901 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:11:28.297407 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1184 12:11:28.300852 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1185 12:11:28.303584 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:11:28.310166 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:11:28.313785 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:11:28.317206 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:11:28.323780 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:11:28.327086 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1191 12:11:28.330283 0 9 8 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
1192 12:11:28.336691 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 12:11:28.340544 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 12:11:28.343778 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 12:11:28.350495 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 12:11:28.353412 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 12:11:28.356663 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 12:11:28.363410 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1199 12:11:28.367158 0 10 8 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
1200 12:11:28.370496 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:11:28.377267 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:11:28.380724 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:11:28.384738 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:11:28.388285 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:11:28.391664 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:11:28.399116 0 11 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
1207 12:11:28.402619 0 11 8 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (0 0)
1208 12:11:28.405420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 12:11:28.412733 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:11:28.416102 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 12:11:28.419624 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:11:28.422961 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 12:11:28.429419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 12:11:28.433157 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 12:11:28.436414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1216 12:11:28.443090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:11:28.446412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:11:28.449654 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:11:28.456208 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:11:28.459616 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:11:28.463017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:11:28.466527 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:11:28.472826 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:11:28.476552 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:11:28.479723 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:11:28.486631 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:11:28.489939 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:11:28.493433 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:11:28.499538 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:11:28.502833 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 12:11:28.506229 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1232 12:11:28.513188 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 12:11:28.513274 Total UI for P1: 0, mck2ui 16
1234 12:11:28.519972 best dqsien dly found for B0: ( 0, 14, 8)
1235 12:11:28.520085 Total UI for P1: 0, mck2ui 16
1236 12:11:28.526144 best dqsien dly found for B1: ( 0, 14, 8)
1237 12:11:28.529640 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1238 12:11:28.533015 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1239 12:11:28.533096
1240 12:11:28.536221 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1241 12:11:28.539488 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1242 12:11:28.542818 [Gating] SW calibration Done
1243 12:11:28.542902 ==
1244 12:11:28.546827 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 12:11:28.549937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 12:11:28.550016 ==
1247 12:11:28.553269 RX Vref Scan: 0
1248 12:11:28.553356
1249 12:11:28.553421 RX Vref 0 -> 0, step: 1
1250 12:11:28.553492
1251 12:11:28.556538 RX Delay -130 -> 252, step: 16
1252 12:11:28.559819 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1253 12:11:28.566563 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1254 12:11:28.569994 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1255 12:11:28.573339 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1256 12:11:28.576665 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1257 12:11:28.580962 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1258 12:11:28.583101 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1259 12:11:28.589623 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1260 12:11:28.592952 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1261 12:11:28.596400 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1262 12:11:28.599893 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1263 12:11:28.603176 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1264 12:11:28.610055 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1265 12:11:28.613484 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1266 12:11:28.616616 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1267 12:11:28.620056 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1268 12:11:28.620135 ==
1269 12:11:28.623504 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 12:11:28.630165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 12:11:28.630266 ==
1272 12:11:28.630338 DQS Delay:
1273 12:11:28.633541 DQS0 = 0, DQS1 = 0
1274 12:11:28.633653 DQM Delay:
1275 12:11:28.633749 DQM0 = 93, DQM1 = 86
1276 12:11:28.636408 DQ Delay:
1277 12:11:28.639786 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1278 12:11:28.643120 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1279 12:11:28.646464 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1280 12:11:28.650329 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1281 12:11:28.650415
1282 12:11:28.650482
1283 12:11:28.650545 ==
1284 12:11:28.653691 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:11:28.656932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:11:28.657018 ==
1287 12:11:28.657086
1288 12:11:28.657148
1289 12:11:28.660145 TX Vref Scan disable
1290 12:11:28.660230 == TX Byte 0 ==
1291 12:11:28.666499 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1292 12:11:28.670080 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1293 12:11:28.670157 == TX Byte 1 ==
1294 12:11:28.676725 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1295 12:11:28.680285 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1296 12:11:28.680368 ==
1297 12:11:28.683800 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 12:11:28.686975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 12:11:28.687131 ==
1300 12:11:28.701718 TX Vref=22, minBit 9, minWin=27, winSum=447
1301 12:11:28.704352 TX Vref=24, minBit 1, minWin=28, winSum=452
1302 12:11:28.707911 TX Vref=26, minBit 1, minWin=28, winSum=459
1303 12:11:28.711194 TX Vref=28, minBit 1, minWin=28, winSum=456
1304 12:11:28.714627 TX Vref=30, minBit 4, minWin=28, winSum=458
1305 12:11:28.718084 TX Vref=32, minBit 1, minWin=28, winSum=456
1306 12:11:28.724947 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 26
1307 12:11:28.725077
1308 12:11:28.728114 Final TX Range 1 Vref 26
1309 12:11:28.728198
1310 12:11:28.728262 ==
1311 12:11:28.731487 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 12:11:28.734878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 12:11:28.734981 ==
1314 12:11:28.735075
1315 12:11:28.735171
1316 12:11:28.738231 TX Vref Scan disable
1317 12:11:28.741690 == TX Byte 0 ==
1318 12:11:28.745150 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1319 12:11:28.748500 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1320 12:11:28.751930 == TX Byte 1 ==
1321 12:11:28.755098 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1322 12:11:28.758382 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1323 12:11:28.758509
1324 12:11:28.761730 [DATLAT]
1325 12:11:28.761839 Freq=800, CH0 RK1
1326 12:11:28.761933
1327 12:11:28.764982 DATLAT Default: 0xa
1328 12:11:28.765149 0, 0xFFFF, sum = 0
1329 12:11:28.768154 1, 0xFFFF, sum = 0
1330 12:11:28.768330 2, 0xFFFF, sum = 0
1331 12:11:28.771487 3, 0xFFFF, sum = 0
1332 12:11:28.771607 4, 0xFFFF, sum = 0
1333 12:11:28.774747 5, 0xFFFF, sum = 0
1334 12:11:28.774860 6, 0xFFFF, sum = 0
1335 12:11:28.778009 7, 0xFFFF, sum = 0
1336 12:11:28.778116 8, 0xFFFF, sum = 0
1337 12:11:28.782049 9, 0x0, sum = 1
1338 12:11:28.782155 10, 0x0, sum = 2
1339 12:11:28.784913 11, 0x0, sum = 3
1340 12:11:28.785028 12, 0x0, sum = 4
1341 12:11:28.788292 best_step = 10
1342 12:11:28.788402
1343 12:11:28.788498 ==
1344 12:11:28.791773 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 12:11:28.795046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 12:11:28.795155 ==
1347 12:11:28.798369 RX Vref Scan: 0
1348 12:11:28.798458
1349 12:11:28.798556 RX Vref 0 -> 0, step: 1
1350 12:11:28.798647
1351 12:11:28.801800 RX Delay -79 -> 252, step: 8
1352 12:11:28.808245 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1353 12:11:28.811665 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1354 12:11:28.814952 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1355 12:11:28.818393 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1356 12:11:28.821765 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1357 12:11:28.825134 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1358 12:11:28.831896 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1359 12:11:28.835169 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1360 12:11:28.838643 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1361 12:11:28.841990 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1362 12:11:28.845423 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1363 12:11:28.852218 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1364 12:11:28.854984 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1365 12:11:28.858302 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1366 12:11:28.861553 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1367 12:11:28.864907 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1368 12:11:28.868711 ==
1369 12:11:28.871956 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 12:11:28.875004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 12:11:28.875114 ==
1372 12:11:28.875208 DQS Delay:
1373 12:11:28.878246 DQS0 = 0, DQS1 = 0
1374 12:11:28.878356 DQM Delay:
1375 12:11:28.882136 DQM0 = 92, DQM1 = 83
1376 12:11:28.882245 DQ Delay:
1377 12:11:28.885308 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1378 12:11:28.888787 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1379 12:11:28.892212 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1380 12:11:28.894902 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =92
1381 12:11:28.895014
1382 12:11:28.895119
1383 12:11:28.902183 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1384 12:11:28.904945 CH0 RK1: MR19=606, MR18=4415
1385 12:11:28.911664 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1386 12:11:28.915049 [RxdqsGatingPostProcess] freq 800
1387 12:11:28.918864 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 12:11:28.921578 Pre-setting of DQS Precalculation
1389 12:11:28.928444 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 12:11:28.928530 ==
1391 12:11:28.931758 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 12:11:28.935577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 12:11:28.935663 ==
1394 12:11:28.942443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 12:11:28.948523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 12:11:28.956091 [CA 0] Center 36 (6~67) winsize 62
1397 12:11:28.959598 [CA 1] Center 36 (6~67) winsize 62
1398 12:11:28.962938 [CA 2] Center 35 (4~66) winsize 63
1399 12:11:28.966197 [CA 3] Center 34 (4~65) winsize 62
1400 12:11:28.969381 [CA 4] Center 35 (5~65) winsize 61
1401 12:11:28.973235 [CA 5] Center 34 (4~65) winsize 62
1402 12:11:28.973321
1403 12:11:28.976488 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 12:11:28.976590
1405 12:11:28.979774 [CATrainingPosCal] consider 1 rank data
1406 12:11:28.982980 u2DelayCellTimex100 = 270/100 ps
1407 12:11:28.986252 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 12:11:28.989428 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 12:11:28.996474 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1410 12:11:28.999640 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 12:11:29.003011 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1412 12:11:29.006237 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 12:11:29.006346
1414 12:11:29.009471 CA PerBit enable=1, Macro0, CA PI delay=34
1415 12:11:29.009572
1416 12:11:29.012868 [CBTSetCACLKResult] CA Dly = 34
1417 12:11:29.012966 CS Dly: 6 (0~37)
1418 12:11:29.013056 ==
1419 12:11:29.016318 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 12:11:29.022912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 12:11:29.023096 ==
1422 12:11:29.026155 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 12:11:29.033007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 12:11:29.042667 [CA 0] Center 36 (6~67) winsize 62
1425 12:11:29.046110 [CA 1] Center 37 (6~68) winsize 63
1426 12:11:29.049499 [CA 2] Center 35 (4~66) winsize 63
1427 12:11:29.052893 [CA 3] Center 34 (4~65) winsize 62
1428 12:11:29.057073 [CA 4] Center 35 (4~66) winsize 63
1429 12:11:29.060702 [CA 5] Center 34 (4~65) winsize 62
1430 12:11:29.060805
1431 12:11:29.064875 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 12:11:29.064983
1433 12:11:29.068831 [CATrainingPosCal] consider 2 rank data
1434 12:11:29.068992 u2DelayCellTimex100 = 270/100 ps
1435 12:11:29.072323 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 12:11:29.076309 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1437 12:11:29.080246 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1438 12:11:29.083575 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1439 12:11:29.086777 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1440 12:11:29.090711 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1441 12:11:29.090796
1442 12:11:29.097366 CA PerBit enable=1, Macro0, CA PI delay=34
1443 12:11:29.097451
1444 12:11:29.097516 [CBTSetCACLKResult] CA Dly = 34
1445 12:11:29.100782 CS Dly: 6 (0~38)
1446 12:11:29.100865
1447 12:11:29.104196 ----->DramcWriteLeveling(PI) begin...
1448 12:11:29.104280 ==
1449 12:11:29.107561 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 12:11:29.110850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 12:11:29.110941 ==
1452 12:11:29.114195 Write leveling (Byte 0): 25 => 25
1453 12:11:29.116928 Write leveling (Byte 1): 27 => 27
1454 12:11:29.120369 DramcWriteLeveling(PI) end<-----
1455 12:11:29.120453
1456 12:11:29.120522 ==
1457 12:11:29.123627 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 12:11:29.126964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 12:11:29.130193 ==
1460 12:11:29.130323 [Gating] SW mode calibration
1461 12:11:29.140429 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 12:11:29.143741 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 12:11:29.147067 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1464 12:11:29.153805 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1465 12:11:29.157163 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:11:29.160618 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:11:29.166885 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:11:29.170166 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:11:29.173656 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:11:29.180366 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:11:29.184250 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:11:29.187669 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:11:29.191247 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:11:29.197182 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:11:29.200415 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:11:29.204182 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:11:29.210598 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:11:29.213911 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:11:29.217263 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1480 12:11:29.224068 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1481 12:11:29.227572 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:11:29.231011 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:11:29.236930 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:11:29.240784 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:11:29.244445 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:11:29.250510 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:11:29.253849 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:11:29.257248 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1489 12:11:29.264196 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1490 12:11:29.267628 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 12:11:29.270963 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 12:11:29.274448 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:11:29.280634 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 12:11:29.284117 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 12:11:29.287468 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1496 12:11:29.294221 0 10 4 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
1497 12:11:29.297415 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1498 12:11:29.300594 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:11:29.307162 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:11:29.311050 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:11:29.314466 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:11:29.320996 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:11:29.324229 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1504 12:11:29.327653 0 11 4 | B1->B0 | 2a2a 3838 | 0 0 | (0 0) (0 0)
1505 12:11:29.334562 0 11 8 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
1506 12:11:29.338000 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 12:11:29.340658 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 12:11:29.344654 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:11:29.351164 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:11:29.354527 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:11:29.357993 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 12:11:29.364424 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1513 12:11:29.367850 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:11:29.370682 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:11:29.377607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:11:29.380968 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:11:29.384535 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:11:29.390690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:11:29.394689 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:11:29.397878 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:11:29.404534 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:11:29.407805 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:11:29.411014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:11:29.417652 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:11:29.421149 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:11:29.424274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:11:29.430933 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 12:11:29.434406 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1529 12:11:29.437855 Total UI for P1: 0, mck2ui 16
1530 12:11:29.441340 best dqsien dly found for B1: ( 0, 14, 2)
1531 12:11:29.444637 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 12:11:29.447975 Total UI for P1: 0, mck2ui 16
1533 12:11:29.451355 best dqsien dly found for B0: ( 0, 14, 4)
1534 12:11:29.454575 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1535 12:11:29.457971 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1536 12:11:29.458077
1537 12:11:29.461340 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1538 12:11:29.464666 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1539 12:11:29.467929 [Gating] SW calibration Done
1540 12:11:29.468035 ==
1541 12:11:29.471500 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 12:11:29.474980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 12:11:29.477799 ==
1544 12:11:29.477909 RX Vref Scan: 0
1545 12:11:29.478004
1546 12:11:29.481209 RX Vref 0 -> 0, step: 1
1547 12:11:29.481337
1548 12:11:29.484590 RX Delay -130 -> 252, step: 16
1549 12:11:29.488190 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1550 12:11:29.490962 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1551 12:11:29.494301 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1552 12:11:29.497741 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1553 12:11:29.504278 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1554 12:11:29.508242 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1555 12:11:29.511541 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1556 12:11:29.514841 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1557 12:11:29.518141 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1558 12:11:29.521473 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1559 12:11:29.527994 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1560 12:11:29.531208 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1561 12:11:29.534561 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1562 12:11:29.537843 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1563 12:11:29.544714 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1564 12:11:29.548202 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1565 12:11:29.548308 ==
1566 12:11:29.550960 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 12:11:29.554550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 12:11:29.554658 ==
1569 12:11:29.554759 DQS Delay:
1570 12:11:29.557844 DQS0 = 0, DQS1 = 0
1571 12:11:29.557952 DQM Delay:
1572 12:11:29.561026 DQM0 = 93, DQM1 = 91
1573 12:11:29.561135 DQ Delay:
1574 12:11:29.564296 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1575 12:11:29.567667 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1576 12:11:29.571151 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1577 12:11:29.574726 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1578 12:11:29.574831
1579 12:11:29.574930
1580 12:11:29.575021 ==
1581 12:11:29.578217 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:11:29.584553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:11:29.584661 ==
1584 12:11:29.584756
1585 12:11:29.584846
1586 12:11:29.584934 TX Vref Scan disable
1587 12:11:29.587984 == TX Byte 0 ==
1588 12:11:29.591356 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1589 12:11:29.594764 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1590 12:11:29.598130 == TX Byte 1 ==
1591 12:11:29.601603 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1592 12:11:29.604987 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1593 12:11:29.608322 ==
1594 12:11:29.608427 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 12:11:29.614987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 12:11:29.615092 ==
1597 12:11:29.627413 TX Vref=22, minBit 1, minWin=26, winSum=436
1598 12:11:29.631241 TX Vref=24, minBit 0, minWin=26, winSum=440
1599 12:11:29.634690 TX Vref=26, minBit 0, minWin=27, winSum=446
1600 12:11:29.637817 TX Vref=28, minBit 5, minWin=26, winSum=447
1601 12:11:29.641065 TX Vref=30, minBit 2, minWin=27, winSum=452
1602 12:11:29.644475 TX Vref=32, minBit 1, minWin=27, winSum=448
1603 12:11:29.651523 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1604 12:11:29.651605
1605 12:11:29.654851 Final TX Range 1 Vref 30
1606 12:11:29.654933
1607 12:11:29.654998 ==
1608 12:11:29.658269 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 12:11:29.660990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 12:11:29.661072 ==
1611 12:11:29.661138
1612 12:11:29.661197
1613 12:11:29.664928 TX Vref Scan disable
1614 12:11:29.668189 == TX Byte 0 ==
1615 12:11:29.671477 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1616 12:11:29.674799 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1617 12:11:29.678234 == TX Byte 1 ==
1618 12:11:29.681767 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1619 12:11:29.684482 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1620 12:11:29.684564
1621 12:11:29.687796 [DATLAT]
1622 12:11:29.687945 Freq=800, CH1 RK0
1623 12:11:29.688073
1624 12:11:29.691175 DATLAT Default: 0xa
1625 12:11:29.691257 0, 0xFFFF, sum = 0
1626 12:11:29.694673 1, 0xFFFF, sum = 0
1627 12:11:29.694755 2, 0xFFFF, sum = 0
1628 12:11:29.698018 3, 0xFFFF, sum = 0
1629 12:11:29.698101 4, 0xFFFF, sum = 0
1630 12:11:29.701559 5, 0xFFFF, sum = 0
1631 12:11:29.701648 6, 0xFFFF, sum = 0
1632 12:11:29.704989 7, 0xFFFF, sum = 0
1633 12:11:29.705098 8, 0xFFFF, sum = 0
1634 12:11:29.707863 9, 0x0, sum = 1
1635 12:11:29.707972 10, 0x0, sum = 2
1636 12:11:29.711218 11, 0x0, sum = 3
1637 12:11:29.711338 12, 0x0, sum = 4
1638 12:11:29.711450 best_step = 10
1639 12:11:29.715153
1640 12:11:29.715275 ==
1641 12:11:29.718442 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 12:11:29.721671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 12:11:29.721787 ==
1644 12:11:29.721889 RX Vref Scan: 1
1645 12:11:29.721979
1646 12:11:29.724685 Set Vref Range= 32 -> 127
1647 12:11:29.724796
1648 12:11:29.728358 RX Vref 32 -> 127, step: 1
1649 12:11:29.728472
1650 12:11:29.731717 RX Delay -79 -> 252, step: 8
1651 12:11:29.731818
1652 12:11:29.734932 Set Vref, RX VrefLevel [Byte0]: 32
1653 12:11:29.738203 [Byte1]: 32
1654 12:11:29.738272
1655 12:11:29.741216 Set Vref, RX VrefLevel [Byte0]: 33
1656 12:11:29.744984 [Byte1]: 33
1657 12:11:29.745066
1658 12:11:29.748254 Set Vref, RX VrefLevel [Byte0]: 34
1659 12:11:29.751520 [Byte1]: 34
1660 12:11:29.754725
1661 12:11:29.754806 Set Vref, RX VrefLevel [Byte0]: 35
1662 12:11:29.758016 [Byte1]: 35
1663 12:11:29.762154
1664 12:11:29.762236 Set Vref, RX VrefLevel [Byte0]: 36
1665 12:11:29.765524 [Byte1]: 36
1666 12:11:29.770220
1667 12:11:29.770302 Set Vref, RX VrefLevel [Byte0]: 37
1668 12:11:29.773687 [Byte1]: 37
1669 12:11:29.777662
1670 12:11:29.777744 Set Vref, RX VrefLevel [Byte0]: 38
1671 12:11:29.780986 [Byte1]: 38
1672 12:11:29.785062
1673 12:11:29.785143 Set Vref, RX VrefLevel [Byte0]: 39
1674 12:11:29.788507 [Byte1]: 39
1675 12:11:29.792633
1676 12:11:29.792718 Set Vref, RX VrefLevel [Byte0]: 40
1677 12:11:29.795997 [Byte1]: 40
1678 12:11:29.800033
1679 12:11:29.800115 Set Vref, RX VrefLevel [Byte0]: 41
1680 12:11:29.803279 [Byte1]: 41
1681 12:11:29.808071
1682 12:11:29.808154 Set Vref, RX VrefLevel [Byte0]: 42
1683 12:11:29.810893 [Byte1]: 42
1684 12:11:29.815784
1685 12:11:29.815867 Set Vref, RX VrefLevel [Byte0]: 43
1686 12:11:29.818431 [Byte1]: 43
1687 12:11:29.822584
1688 12:11:29.822666 Set Vref, RX VrefLevel [Byte0]: 44
1689 12:11:29.826018 [Byte1]: 44
1690 12:11:29.830595
1691 12:11:29.830718 Set Vref, RX VrefLevel [Byte0]: 45
1692 12:11:29.833598 [Byte1]: 45
1693 12:11:29.837615
1694 12:11:29.837698 Set Vref, RX VrefLevel [Byte0]: 46
1695 12:11:29.840941 [Byte1]: 46
1696 12:11:29.845640
1697 12:11:29.845760 Set Vref, RX VrefLevel [Byte0]: 47
1698 12:11:29.848880 [Byte1]: 47
1699 12:11:29.852972
1700 12:11:29.853084 Set Vref, RX VrefLevel [Byte0]: 48
1701 12:11:29.856211 [Byte1]: 48
1702 12:11:29.860979
1703 12:11:29.861061 Set Vref, RX VrefLevel [Byte0]: 49
1704 12:11:29.863586 [Byte1]: 49
1705 12:11:29.868367
1706 12:11:29.868472 Set Vref, RX VrefLevel [Byte0]: 50
1707 12:11:29.871074 [Byte1]: 50
1708 12:11:29.875799
1709 12:11:29.875923 Set Vref, RX VrefLevel [Byte0]: 51
1710 12:11:29.879100 [Byte1]: 51
1711 12:11:29.882917
1712 12:11:29.883034 Set Vref, RX VrefLevel [Byte0]: 52
1713 12:11:29.886230 [Byte1]: 52
1714 12:11:29.890451
1715 12:11:29.890539 Set Vref, RX VrefLevel [Byte0]: 53
1716 12:11:29.893834 [Byte1]: 53
1717 12:11:29.898008
1718 12:11:29.898123 Set Vref, RX VrefLevel [Byte0]: 54
1719 12:11:29.901388 [Byte1]: 54
1720 12:11:29.906155
1721 12:11:29.906265 Set Vref, RX VrefLevel [Byte0]: 55
1722 12:11:29.908974 [Byte1]: 55
1723 12:11:29.913751
1724 12:11:29.913861 Set Vref, RX VrefLevel [Byte0]: 56
1725 12:11:29.916409 [Byte1]: 56
1726 12:11:29.921151
1727 12:11:29.921268 Set Vref, RX VrefLevel [Byte0]: 57
1728 12:11:29.924560 [Byte1]: 57
1729 12:11:29.928664
1730 12:11:29.928779 Set Vref, RX VrefLevel [Byte0]: 58
1731 12:11:29.931964 [Byte1]: 58
1732 12:11:29.935710
1733 12:11:29.935821 Set Vref, RX VrefLevel [Byte0]: 59
1734 12:11:29.939102 [Byte1]: 59
1735 12:11:29.943524
1736 12:11:29.943634 Set Vref, RX VrefLevel [Byte0]: 60
1737 12:11:29.946851 [Byte1]: 60
1738 12:11:29.951246
1739 12:11:29.951395 Set Vref, RX VrefLevel [Byte0]: 61
1740 12:11:29.954575 [Byte1]: 61
1741 12:11:29.958453
1742 12:11:29.958569 Set Vref, RX VrefLevel [Byte0]: 62
1743 12:11:29.961779 [Byte1]: 62
1744 12:11:29.966517
1745 12:11:29.966622 Set Vref, RX VrefLevel [Byte0]: 63
1746 12:11:29.969731 [Byte1]: 63
1747 12:11:29.973867
1748 12:11:29.973953 Set Vref, RX VrefLevel [Byte0]: 64
1749 12:11:29.977261 [Byte1]: 64
1750 12:11:29.981368
1751 12:11:29.981482 Set Vref, RX VrefLevel [Byte0]: 65
1752 12:11:29.985068 [Byte1]: 65
1753 12:11:29.988904
1754 12:11:29.989030 Set Vref, RX VrefLevel [Byte0]: 66
1755 12:11:29.992156 [Byte1]: 66
1756 12:11:29.996662
1757 12:11:29.996777 Set Vref, RX VrefLevel [Byte0]: 67
1758 12:11:29.999957 [Byte1]: 67
1759 12:11:30.004020
1760 12:11:30.004129 Set Vref, RX VrefLevel [Byte0]: 68
1761 12:11:30.007549 [Byte1]: 68
1762 12:11:30.011726
1763 12:11:30.011847 Set Vref, RX VrefLevel [Byte0]: 69
1764 12:11:30.014496 [Byte1]: 69
1765 12:11:30.019450
1766 12:11:30.019560 Set Vref, RX VrefLevel [Byte0]: 70
1767 12:11:30.022029 [Byte1]: 70
1768 12:11:30.026884
1769 12:11:30.027006 Set Vref, RX VrefLevel [Byte0]: 71
1770 12:11:30.030224 [Byte1]: 71
1771 12:11:30.034438
1772 12:11:30.034550 Set Vref, RX VrefLevel [Byte0]: 72
1773 12:11:30.037838 [Byte1]: 72
1774 12:11:30.041892
1775 12:11:30.042004 Set Vref, RX VrefLevel [Byte0]: 73
1776 12:11:30.045257 [Byte1]: 73
1777 12:11:30.048959
1778 12:11:30.049049 Final RX Vref Byte 0 = 57 to rank0
1779 12:11:30.052735 Final RX Vref Byte 1 = 58 to rank0
1780 12:11:30.056017 Final RX Vref Byte 0 = 57 to rank1
1781 12:11:30.059367 Final RX Vref Byte 1 = 58 to rank1==
1782 12:11:30.062550 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 12:11:30.069054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 12:11:30.069141 ==
1785 12:11:30.069210 DQS Delay:
1786 12:11:30.069273 DQS0 = 0, DQS1 = 0
1787 12:11:30.072312 DQM Delay:
1788 12:11:30.072397 DQM0 = 96, DQM1 = 90
1789 12:11:30.076088 DQ Delay:
1790 12:11:30.079259 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =96
1791 12:11:30.082703 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1792 12:11:30.086102 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1793 12:11:30.089519 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =96
1794 12:11:30.089634
1795 12:11:30.089757
1796 12:11:30.096002 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1797 12:11:30.099195 CH1 RK0: MR19=606, MR18=2E4A
1798 12:11:30.106093 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1799 12:11:30.106202
1800 12:11:30.109645 ----->DramcWriteLeveling(PI) begin...
1801 12:11:30.109757 ==
1802 12:11:30.113162 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 12:11:30.116716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 12:11:30.116800 ==
1805 12:11:30.119422 Write leveling (Byte 0): 27 => 27
1806 12:11:30.122760 Write leveling (Byte 1): 28 => 28
1807 12:11:30.126169 DramcWriteLeveling(PI) end<-----
1808 12:11:30.126251
1809 12:11:30.126317 ==
1810 12:11:30.129659 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 12:11:30.133140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 12:11:30.133249 ==
1813 12:11:30.136462 [Gating] SW mode calibration
1814 12:11:30.143176 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 12:11:30.150066 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 12:11:30.153435 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 12:11:30.156782 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1818 12:11:30.163201 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:11:30.166528 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:11:30.169811 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:11:30.176744 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:11:30.180032 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:11:30.183322 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:11:30.186557 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:11:30.193326 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:11:30.196745 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:11:30.200146 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:11:30.206613 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:11:30.209957 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:11:30.213386 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:11:30.220214 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:11:30.223605 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 12:11:30.226968 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:11:30.233080 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:11:30.236629 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:11:30.240004 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:11:30.246985 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:11:30.249792 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:11:30.253132 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:11:30.259834 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:11:30.263164 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1842 12:11:30.266645 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1843 12:11:30.269795 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 12:11:30.276748 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 12:11:30.280018 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 12:11:30.283908 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 12:11:30.290343 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 12:11:30.293494 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 12:11:30.296760 0 10 4 | B1->B0 | 2b2b 3030 | 0 1 | (1 0) (1 0)
1850 12:11:30.303541 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1851 12:11:30.306929 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:11:30.310788 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:11:30.316830 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:11:30.320178 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:11:30.323667 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:11:30.327039 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1857 12:11:30.334040 0 11 4 | B1->B0 | 3636 2e2e | 0 0 | (0 0) (0 0)
1858 12:11:30.336869 0 11 8 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
1859 12:11:30.340156 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 12:11:30.347016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:11:30.350431 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 12:11:30.353897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:11:30.360674 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:11:30.364035 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:11:30.367487 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1866 12:11:30.373986 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:11:30.377463 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:11:30.380749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:11:30.387382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:11:30.390558 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:11:30.393812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:11:30.400426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:11:30.403648 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:11:30.406873 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:11:30.413665 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:11:30.416930 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:11:30.420244 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:11:30.423607 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:11:30.430469 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:11:30.433805 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:11:30.437273 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 12:11:30.440703 Total UI for P1: 0, mck2ui 16
1883 12:11:30.444112 best dqsien dly found for B0: ( 0, 14, 2)
1884 12:11:30.447493 Total UI for P1: 0, mck2ui 16
1885 12:11:30.450880 best dqsien dly found for B1: ( 0, 14, 2)
1886 12:11:30.454147 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1887 12:11:30.457517 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1888 12:11:30.457624
1889 12:11:30.463640 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1890 12:11:30.467065 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1891 12:11:30.467237 [Gating] SW calibration Done
1892 12:11:30.470515 ==
1893 12:11:30.470632 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 12:11:30.477258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 12:11:30.477368 ==
1896 12:11:30.477471 RX Vref Scan: 0
1897 12:11:30.477577
1898 12:11:30.480681 RX Vref 0 -> 0, step: 1
1899 12:11:30.480789
1900 12:11:30.484089 RX Delay -130 -> 252, step: 16
1901 12:11:30.487553 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1902 12:11:30.490871 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1903 12:11:30.494225 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1904 12:11:30.500868 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1905 12:11:30.504224 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1906 12:11:30.507156 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1907 12:11:30.510555 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1908 12:11:30.513817 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1909 12:11:30.520730 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1910 12:11:30.524124 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1911 12:11:30.527403 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1912 12:11:30.530604 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1913 12:11:30.534004 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1914 12:11:30.540923 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1915 12:11:30.544256 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1916 12:11:30.547710 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1917 12:11:30.547794 ==
1918 12:11:30.550404 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 12:11:30.553875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 12:11:30.553959 ==
1921 12:11:30.557361 DQS Delay:
1922 12:11:30.557485 DQS0 = 0, DQS1 = 0
1923 12:11:30.560833 DQM Delay:
1924 12:11:30.560957 DQM0 = 92, DQM1 = 90
1925 12:11:30.561056 DQ Delay:
1926 12:11:30.564289 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1927 12:11:30.567699 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1928 12:11:30.570458 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1929 12:11:30.573842 DQ12 =101, DQ13 =101, DQ14 =93, DQ15 =101
1930 12:11:30.573934
1931 12:11:30.577440
1932 12:11:30.577521 ==
1933 12:11:30.580738 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 12:11:30.584097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 12:11:30.584190 ==
1936 12:11:30.584258
1937 12:11:30.584322
1938 12:11:30.587457 TX Vref Scan disable
1939 12:11:30.587543 == TX Byte 0 ==
1940 12:11:30.594234 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 12:11:30.597548 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 12:11:30.597635 == TX Byte 1 ==
1943 12:11:30.604051 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1944 12:11:30.607461 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1945 12:11:30.607548 ==
1946 12:11:30.610865 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 12:11:30.614303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 12:11:30.614391 ==
1949 12:11:30.627182 TX Vref=22, minBit 1, minWin=26, winSum=444
1950 12:11:30.630610 TX Vref=24, minBit 3, minWin=26, winSum=448
1951 12:11:30.633853 TX Vref=26, minBit 2, minWin=27, winSum=449
1952 12:11:30.637802 TX Vref=28, minBit 2, minWin=27, winSum=448
1953 12:11:30.640878 TX Vref=30, minBit 2, minWin=27, winSum=450
1954 12:11:30.644368 TX Vref=32, minBit 2, minWin=27, winSum=448
1955 12:11:30.651212 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30
1956 12:11:30.651330
1957 12:11:30.653973 Final TX Range 1 Vref 30
1958 12:11:30.654059
1959 12:11:30.654126 ==
1960 12:11:30.657566 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 12:11:30.660972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 12:11:30.661058 ==
1963 12:11:30.661126
1964 12:11:30.661190
1965 12:11:30.664416 TX Vref Scan disable
1966 12:11:30.667634 == TX Byte 0 ==
1967 12:11:30.671027 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 12:11:30.674560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 12:11:30.677416 == TX Byte 1 ==
1970 12:11:30.680710 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1971 12:11:30.684177 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1972 12:11:30.684286
1973 12:11:30.687577 [DATLAT]
1974 12:11:30.687687 Freq=800, CH1 RK1
1975 12:11:30.687782
1976 12:11:30.690816 DATLAT Default: 0xa
1977 12:11:30.690922 0, 0xFFFF, sum = 0
1978 12:11:30.694393 1, 0xFFFF, sum = 0
1979 12:11:30.694489 2, 0xFFFF, sum = 0
1980 12:11:30.697708 3, 0xFFFF, sum = 0
1981 12:11:30.697794 4, 0xFFFF, sum = 0
1982 12:11:30.701040 5, 0xFFFF, sum = 0
1983 12:11:30.701123 6, 0xFFFF, sum = 0
1984 12:11:30.704251 7, 0xFFFF, sum = 0
1985 12:11:30.704342 8, 0xFFFF, sum = 0
1986 12:11:30.707467 9, 0x0, sum = 1
1987 12:11:30.707582 10, 0x0, sum = 2
1988 12:11:30.711264 11, 0x0, sum = 3
1989 12:11:30.711370 12, 0x0, sum = 4
1990 12:11:30.714670 best_step = 10
1991 12:11:30.714776
1992 12:11:30.714868 ==
1993 12:11:30.717910 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 12:11:30.721227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 12:11:30.721343 ==
1996 12:11:30.724731 RX Vref Scan: 0
1997 12:11:30.724813
1998 12:11:30.724879 RX Vref 0 -> 0, step: 1
1999 12:11:30.724940
2000 12:11:30.727486 RX Delay -79 -> 252, step: 8
2001 12:11:30.734243 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2002 12:11:30.737599 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2003 12:11:30.741008 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2004 12:11:30.744482 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2005 12:11:30.747560 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2006 12:11:30.750948 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2007 12:11:30.757832 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2008 12:11:30.761237 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2009 12:11:30.764700 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2010 12:11:30.768137 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2011 12:11:30.771531 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2012 12:11:30.774262 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2013 12:11:30.781073 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2014 12:11:30.784503 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2015 12:11:30.787939 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2016 12:11:30.791038 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2017 12:11:30.791137 ==
2018 12:11:30.794432 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 12:11:30.801408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 12:11:30.801493 ==
2021 12:11:30.801561 DQS Delay:
2022 12:11:30.801622 DQS0 = 0, DQS1 = 0
2023 12:11:30.804898 DQM Delay:
2024 12:11:30.804980 DQM0 = 97, DQM1 = 91
2025 12:11:30.808022 DQ Delay:
2026 12:11:30.811259 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2027 12:11:30.814531 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2028 12:11:30.817804 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2029 12:11:30.821030 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2030 12:11:30.821114
2031 12:11:30.821180
2032 12:11:30.828177 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2033 12:11:30.831017 CH1 RK1: MR19=606, MR18=4913
2034 12:11:30.837796 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2035 12:11:30.841180 [RxdqsGatingPostProcess] freq 800
2036 12:11:30.844539 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 12:11:30.847953 Pre-setting of DQS Precalculation
2038 12:11:30.854507 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 12:11:30.861071 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 12:11:30.867893 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 12:11:30.867980
2042 12:11:30.868046
2043 12:11:30.871387 [Calibration Summary] 1600 Mbps
2044 12:11:30.871470 CH 0, Rank 0
2045 12:11:30.874812 SW Impedance : PASS
2046 12:11:30.877575 DUTY Scan : NO K
2047 12:11:30.877660 ZQ Calibration : PASS
2048 12:11:30.880967 Jitter Meter : NO K
2049 12:11:30.884456 CBT Training : PASS
2050 12:11:30.884567 Write leveling : PASS
2051 12:11:30.887937 RX DQS gating : PASS
2052 12:11:30.888022 RX DQ/DQS(RDDQC) : PASS
2053 12:11:30.891349 TX DQ/DQS : PASS
2054 12:11:30.894792 RX DATLAT : PASS
2055 12:11:30.894887 RX DQ/DQS(Engine): PASS
2056 12:11:30.898134 TX OE : NO K
2057 12:11:30.898213 All Pass.
2058 12:11:30.898302
2059 12:11:30.901403 CH 0, Rank 1
2060 12:11:30.901484 SW Impedance : PASS
2061 12:11:30.905001 DUTY Scan : NO K
2062 12:11:30.907751 ZQ Calibration : PASS
2063 12:11:30.907847 Jitter Meter : NO K
2064 12:11:30.911697 CBT Training : PASS
2065 12:11:30.914922 Write leveling : PASS
2066 12:11:30.915002 RX DQS gating : PASS
2067 12:11:30.918021 RX DQ/DQS(RDDQC) : PASS
2068 12:11:30.921380 TX DQ/DQS : PASS
2069 12:11:30.921489 RX DATLAT : PASS
2070 12:11:30.924811 RX DQ/DQS(Engine): PASS
2071 12:11:30.927988 TX OE : NO K
2072 12:11:30.928077 All Pass.
2073 12:11:30.928161
2074 12:11:30.928234 CH 1, Rank 0
2075 12:11:30.931154 SW Impedance : PASS
2076 12:11:30.931275 DUTY Scan : NO K
2077 12:11:30.934426 ZQ Calibration : PASS
2078 12:11:30.937830 Jitter Meter : NO K
2079 12:11:30.937931 CBT Training : PASS
2080 12:11:30.941401 Write leveling : PASS
2081 12:11:30.944574 RX DQS gating : PASS
2082 12:11:30.944655 RX DQ/DQS(RDDQC) : PASS
2083 12:11:30.947903 TX DQ/DQS : PASS
2084 12:11:30.951285 RX DATLAT : PASS
2085 12:11:30.951400 RX DQ/DQS(Engine): PASS
2086 12:11:30.954713 TX OE : NO K
2087 12:11:30.954793 All Pass.
2088 12:11:30.954859
2089 12:11:30.958073 CH 1, Rank 1
2090 12:11:30.958152 SW Impedance : PASS
2091 12:11:30.961358 DUTY Scan : NO K
2092 12:11:30.964559 ZQ Calibration : PASS
2093 12:11:30.964670 Jitter Meter : NO K
2094 12:11:30.967811 CBT Training : PASS
2095 12:11:30.971231 Write leveling : PASS
2096 12:11:30.971344 RX DQS gating : PASS
2097 12:11:30.974651 RX DQ/DQS(RDDQC) : PASS
2098 12:11:30.974756 TX DQ/DQS : PASS
2099 12:11:30.978152 RX DATLAT : PASS
2100 12:11:30.981732 RX DQ/DQS(Engine): PASS
2101 12:11:30.981839 TX OE : NO K
2102 12:11:30.984428 All Pass.
2103 12:11:30.984534
2104 12:11:30.984643 DramC Write-DBI off
2105 12:11:30.988347 PER_BANK_REFRESH: Hybrid Mode
2106 12:11:30.990977 TX_TRACKING: ON
2107 12:11:30.994550 [GetDramInforAfterCalByMRR] Vendor 6.
2108 12:11:30.998151 [GetDramInforAfterCalByMRR] Revision 606.
2109 12:11:31.001562 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 12:11:31.001675 MR0 0x3b3b
2111 12:11:31.001771 MR8 0x5151
2112 12:11:31.008332 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 12:11:31.008413
2114 12:11:31.008478 MR0 0x3b3b
2115 12:11:31.008539 MR8 0x5151
2116 12:11:31.011093 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 12:11:31.011164
2118 12:11:31.021086 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 12:11:31.024289 [FAST_K] Save calibration result to emmc
2120 12:11:31.028107 [FAST_K] Save calibration result to emmc
2121 12:11:31.031279 dram_init: config_dvfs: 1
2122 12:11:31.034624 dramc_set_vcore_voltage set vcore to 662500
2123 12:11:31.037872 Read voltage for 1200, 2
2124 12:11:31.037976 Vio18 = 0
2125 12:11:31.038070 Vcore = 662500
2126 12:11:31.041060 Vdram = 0
2127 12:11:31.041164 Vddq = 0
2128 12:11:31.041257 Vmddr = 0
2129 12:11:31.047784 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 12:11:31.051009 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 12:11:31.054354 MEM_TYPE=3, freq_sel=15
2132 12:11:31.058361 sv_algorithm_assistance_LP4_1600
2133 12:11:31.061153 ============ PULL DRAM RESETB DOWN ============
2134 12:11:31.064444 ========== PULL DRAM RESETB DOWN end =========
2135 12:11:31.071237 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 12:11:31.074582 ===================================
2137 12:11:31.077794 LPDDR4 DRAM CONFIGURATION
2138 12:11:31.077882 ===================================
2139 12:11:31.081208 EX_ROW_EN[0] = 0x0
2140 12:11:31.084670 EX_ROW_EN[1] = 0x0
2141 12:11:31.084757 LP4Y_EN = 0x0
2142 12:11:31.088121 WORK_FSP = 0x0
2143 12:11:31.088232 WL = 0x4
2144 12:11:31.090873 RL = 0x4
2145 12:11:31.090988 BL = 0x2
2146 12:11:31.094343 RPST = 0x0
2147 12:11:31.094421 RD_PRE = 0x0
2148 12:11:31.097823 WR_PRE = 0x1
2149 12:11:31.097913 WR_PST = 0x0
2150 12:11:31.101345 DBI_WR = 0x0
2151 12:11:31.101430 DBI_RD = 0x0
2152 12:11:31.104851 OTF = 0x1
2153 12:11:31.107418 ===================================
2154 12:11:31.110829 ===================================
2155 12:11:31.110914 ANA top config
2156 12:11:31.114264 ===================================
2157 12:11:31.117851 DLL_ASYNC_EN = 0
2158 12:11:31.121267 ALL_SLAVE_EN = 0
2159 12:11:31.124069 NEW_RANK_MODE = 1
2160 12:11:31.124152 DLL_IDLE_MODE = 1
2161 12:11:31.127584 LP45_APHY_COMB_EN = 1
2162 12:11:31.131003 TX_ODT_DIS = 1
2163 12:11:31.134385 NEW_8X_MODE = 1
2164 12:11:31.137572 ===================================
2165 12:11:31.140946 ===================================
2166 12:11:31.144182 data_rate = 2400
2167 12:11:31.144261 CKR = 1
2168 12:11:31.148175 DQ_P2S_RATIO = 8
2169 12:11:31.151429 ===================================
2170 12:11:31.154630 CA_P2S_RATIO = 8
2171 12:11:31.157895 DQ_CA_OPEN = 0
2172 12:11:31.161237 DQ_SEMI_OPEN = 0
2173 12:11:31.164638 CA_SEMI_OPEN = 0
2174 12:11:31.164731 CA_FULL_RATE = 0
2175 12:11:31.167987 DQ_CKDIV4_EN = 0
2176 12:11:31.170765 CA_CKDIV4_EN = 0
2177 12:11:31.174266 CA_PREDIV_EN = 0
2178 12:11:31.177523 PH8_DLY = 17
2179 12:11:31.181409 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 12:11:31.181490 DQ_AAMCK_DIV = 4
2181 12:11:31.184653 CA_AAMCK_DIV = 4
2182 12:11:31.187880 CA_ADMCK_DIV = 4
2183 12:11:31.191249 DQ_TRACK_CA_EN = 0
2184 12:11:31.194004 CA_PICK = 1200
2185 12:11:31.197584 CA_MCKIO = 1200
2186 12:11:31.197664 MCKIO_SEMI = 0
2187 12:11:31.201024 PLL_FREQ = 2366
2188 12:11:31.204435 DQ_UI_PI_RATIO = 32
2189 12:11:31.207877 CA_UI_PI_RATIO = 0
2190 12:11:31.211218 ===================================
2191 12:11:31.214640 ===================================
2192 12:11:31.217399 memory_type:LPDDR4
2193 12:11:31.217481 GP_NUM : 10
2194 12:11:31.220985 SRAM_EN : 1
2195 12:11:31.224318 MD32_EN : 0
2196 12:11:31.227799 ===================================
2197 12:11:31.227906 [ANA_INIT] >>>>>>>>>>>>>>
2198 12:11:31.231213 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 12:11:31.234673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 12:11:31.237957 ===================================
2201 12:11:31.240782 data_rate = 2400,PCW = 0X5b00
2202 12:11:31.244613 ===================================
2203 12:11:31.247736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 12:11:31.254381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 12:11:31.257625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 12:11:31.264232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 12:11:31.267490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 12:11:31.270854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 12:11:31.270942 [ANA_INIT] flow start
2210 12:11:31.274238 [ANA_INIT] PLL >>>>>>>>
2211 12:11:31.277674 [ANA_INIT] PLL <<<<<<<<
2212 12:11:31.277771 [ANA_INIT] MIDPI >>>>>>>>
2213 12:11:31.281042 [ANA_INIT] MIDPI <<<<<<<<
2214 12:11:31.284345 [ANA_INIT] DLL >>>>>>>>
2215 12:11:31.287629 [ANA_INIT] DLL <<<<<<<<
2216 12:11:31.287712 [ANA_INIT] flow end
2217 12:11:31.290803 ============ LP4 DIFF to SE enter ============
2218 12:11:31.297547 ============ LP4 DIFF to SE exit ============
2219 12:11:31.297635 [ANA_INIT] <<<<<<<<<<<<<
2220 12:11:31.301004 [Flow] Enable top DCM control >>>>>
2221 12:11:31.304371 [Flow] Enable top DCM control <<<<<
2222 12:11:31.307716 Enable DLL master slave shuffle
2223 12:11:31.314555 ==============================================================
2224 12:11:31.314640 Gating Mode config
2225 12:11:31.321535 ==============================================================
2226 12:11:31.324232 Config description:
2227 12:11:31.331639 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 12:11:31.337604 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 12:11:31.344406 SELPH_MODE 0: By rank 1: By Phase
2230 12:11:31.347797 ==============================================================
2231 12:11:31.351169 GAT_TRACK_EN = 1
2232 12:11:31.354990 RX_GATING_MODE = 2
2233 12:11:31.358134 RX_GATING_TRACK_MODE = 2
2234 12:11:31.361407 SELPH_MODE = 1
2235 12:11:31.364731 PICG_EARLY_EN = 1
2236 12:11:31.368602 VALID_LAT_VALUE = 1
2237 12:11:31.371792 ==============================================================
2238 12:11:31.378406 Enter into Gating configuration >>>>
2239 12:11:31.378491 Exit from Gating configuration <<<<
2240 12:11:31.381532 Enter into DVFS_PRE_config >>>>>
2241 12:11:31.395023 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 12:11:31.398447 Exit from DVFS_PRE_config <<<<<
2243 12:11:31.401832 Enter into PICG configuration >>>>
2244 12:11:31.401916 Exit from PICG configuration <<<<
2245 12:11:31.404648 [RX_INPUT] configuration >>>>>
2246 12:11:31.407972 [RX_INPUT] configuration <<<<<
2247 12:11:31.414861 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 12:11:31.418303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 12:11:31.425292 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 12:11:31.431439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 12:11:31.438525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 12:11:31.445285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 12:11:31.448636 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 12:11:31.451286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 12:11:31.455334 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 12:11:31.461280 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 12:11:31.465211 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 12:11:31.468405 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 12:11:31.471647 ===================================
2260 12:11:31.474929 LPDDR4 DRAM CONFIGURATION
2261 12:11:31.478591 ===================================
2262 12:11:31.478672 EX_ROW_EN[0] = 0x0
2263 12:11:31.481734 EX_ROW_EN[1] = 0x0
2264 12:11:31.484897 LP4Y_EN = 0x0
2265 12:11:31.484973 WORK_FSP = 0x0
2266 12:11:31.488726 WL = 0x4
2267 12:11:31.488803 RL = 0x4
2268 12:11:31.492043 BL = 0x2
2269 12:11:31.492128 RPST = 0x0
2270 12:11:31.495504 RD_PRE = 0x0
2271 12:11:31.495583 WR_PRE = 0x1
2272 12:11:31.498197 WR_PST = 0x0
2273 12:11:31.498289 DBI_WR = 0x0
2274 12:11:31.501614 DBI_RD = 0x0
2275 12:11:31.501692 OTF = 0x1
2276 12:11:31.504838 ===================================
2277 12:11:31.508717 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 12:11:31.515014 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 12:11:31.518544 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 12:11:31.521884 ===================================
2281 12:11:31.525173 LPDDR4 DRAM CONFIGURATION
2282 12:11:31.528604 ===================================
2283 12:11:31.528685 EX_ROW_EN[0] = 0x10
2284 12:11:31.532067 EX_ROW_EN[1] = 0x0
2285 12:11:31.532157 LP4Y_EN = 0x0
2286 12:11:31.534812 WORK_FSP = 0x0
2287 12:11:31.534892 WL = 0x4
2288 12:11:31.538193 RL = 0x4
2289 12:11:31.538272 BL = 0x2
2290 12:11:31.541621 RPST = 0x0
2291 12:11:31.545116 RD_PRE = 0x0
2292 12:11:31.545258 WR_PRE = 0x1
2293 12:11:31.548654 WR_PST = 0x0
2294 12:11:31.548735 DBI_WR = 0x0
2295 12:11:31.551988 DBI_RD = 0x0
2296 12:11:31.552065 OTF = 0x1
2297 12:11:31.555462 ===================================
2298 12:11:31.561765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 12:11:31.561860 ==
2300 12:11:31.564982 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 12:11:31.568446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 12:11:31.568534 ==
2303 12:11:31.571837 [Duty_Offset_Calibration]
2304 12:11:31.571927 B0:2 B1:1 CA:1
2305 12:11:31.571999
2306 12:11:31.575612 [DutyScan_Calibration_Flow] k_type=0
2307 12:11:31.585945
2308 12:11:31.586051 ==CLK 0==
2309 12:11:31.589227 Final CLK duty delay cell = 0
2310 12:11:31.592920 [0] MAX Duty = 5218%(X100), DQS PI = 24
2311 12:11:31.596281 [0] MIN Duty = 4875%(X100), DQS PI = 0
2312 12:11:31.596372 [0] AVG Duty = 5046%(X100)
2313 12:11:31.596439
2314 12:11:31.599552 CH0 CLK Duty spec in!! Max-Min= 343%
2315 12:11:31.606450 [DutyScan_Calibration_Flow] ====Done====
2316 12:11:31.606530
2317 12:11:31.609857 [DutyScan_Calibration_Flow] k_type=1
2318 12:11:31.624032
2319 12:11:31.624120 ==DQS 0 ==
2320 12:11:31.627213 Final DQS duty delay cell = -4
2321 12:11:31.630702 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2322 12:11:31.633525 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2323 12:11:31.636909 [-4] AVG Duty = 4937%(X100)
2324 12:11:31.636991
2325 12:11:31.637056 ==DQS 1 ==
2326 12:11:31.640254 Final DQS duty delay cell = -4
2327 12:11:31.643693 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2328 12:11:31.647199 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2329 12:11:31.650540 [-4] AVG Duty = 4906%(X100)
2330 12:11:31.650621
2331 12:11:31.653738 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2332 12:11:31.653848
2333 12:11:31.657205 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2334 12:11:31.660586 [DutyScan_Calibration_Flow] ====Done====
2335 12:11:31.660663
2336 12:11:31.663875 [DutyScan_Calibration_Flow] k_type=3
2337 12:11:31.681235
2338 12:11:31.681351 ==DQM 0 ==
2339 12:11:31.684535 Final DQM duty delay cell = 0
2340 12:11:31.687825 [0] MAX Duty = 5156%(X100), DQS PI = 26
2341 12:11:31.691062 [0] MIN Duty = 4875%(X100), DQS PI = 58
2342 12:11:31.694528 [0] AVG Duty = 5015%(X100)
2343 12:11:31.694615
2344 12:11:31.694681 ==DQM 1 ==
2345 12:11:31.697739 Final DQM duty delay cell = 0
2346 12:11:31.700796 [0] MAX Duty = 5124%(X100), DQS PI = 10
2347 12:11:31.704106 [0] MIN Duty = 5031%(X100), DQS PI = 50
2348 12:11:31.707513 [0] AVG Duty = 5077%(X100)
2349 12:11:31.707595
2350 12:11:31.710774 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2351 12:11:31.710877
2352 12:11:31.714473 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2353 12:11:31.717142 [DutyScan_Calibration_Flow] ====Done====
2354 12:11:31.717222
2355 12:11:31.720513 [DutyScan_Calibration_Flow] k_type=2
2356 12:11:31.737596
2357 12:11:31.737685 ==DQ 0 ==
2358 12:11:31.740914 Final DQ duty delay cell = 0
2359 12:11:31.743879 [0] MAX Duty = 5031%(X100), DQS PI = 24
2360 12:11:31.747390 [0] MIN Duty = 4875%(X100), DQS PI = 62
2361 12:11:31.747465 [0] AVG Duty = 4953%(X100)
2362 12:11:31.747536
2363 12:11:31.750767 ==DQ 1 ==
2364 12:11:31.754154 Final DQ duty delay cell = 0
2365 12:11:31.757603 [0] MAX Duty = 5093%(X100), DQS PI = 24
2366 12:11:31.761089 [0] MIN Duty = 4938%(X100), DQS PI = 36
2367 12:11:31.761201 [0] AVG Duty = 5015%(X100)
2368 12:11:31.761294
2369 12:11:31.764502 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2370 12:11:31.767168
2371 12:11:31.770502 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2372 12:11:31.773844 [DutyScan_Calibration_Flow] ====Done====
2373 12:11:31.773926 ==
2374 12:11:31.777171 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 12:11:31.780567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 12:11:31.780666 ==
2377 12:11:31.783959 [Duty_Offset_Calibration]
2378 12:11:31.784029 B0:1 B1:0 CA:0
2379 12:11:31.784117
2380 12:11:31.787405 [DutyScan_Calibration_Flow] k_type=0
2381 12:11:31.796513
2382 12:11:31.796677 ==CLK 0==
2383 12:11:31.799584 Final CLK duty delay cell = -4
2384 12:11:31.803521 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2385 12:11:31.806706 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2386 12:11:31.809877 [-4] AVG Duty = 4969%(X100)
2387 12:11:31.809960
2388 12:11:31.813245 CH1 CLK Duty spec in!! Max-Min= 124%
2389 12:11:31.816668 [DutyScan_Calibration_Flow] ====Done====
2390 12:11:31.816751
2391 12:11:31.819521 [DutyScan_Calibration_Flow] k_type=1
2392 12:11:31.836866
2393 12:11:31.836950 ==DQS 0 ==
2394 12:11:31.839600 Final DQS duty delay cell = 0
2395 12:11:31.843715 [0] MAX Duty = 5094%(X100), DQS PI = 24
2396 12:11:31.846490 [0] MIN Duty = 4875%(X100), DQS PI = 0
2397 12:11:31.846591 [0] AVG Duty = 4984%(X100)
2398 12:11:31.849781
2399 12:11:31.849862 ==DQS 1 ==
2400 12:11:31.853146 Final DQS duty delay cell = 0
2401 12:11:31.856633 [0] MAX Duty = 5187%(X100), DQS PI = 20
2402 12:11:31.859950 [0] MIN Duty = 4969%(X100), DQS PI = 10
2403 12:11:31.860033 [0] AVG Duty = 5078%(X100)
2404 12:11:31.863451
2405 12:11:31.866804 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2406 12:11:31.866902
2407 12:11:31.870334 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2408 12:11:31.872950 [DutyScan_Calibration_Flow] ====Done====
2409 12:11:31.873032
2410 12:11:31.876328 [DutyScan_Calibration_Flow] k_type=3
2411 12:11:31.893191
2412 12:11:31.893286 ==DQM 0 ==
2413 12:11:31.896463 Final DQM duty delay cell = 0
2414 12:11:31.899709 [0] MAX Duty = 5156%(X100), DQS PI = 6
2415 12:11:31.902954 [0] MIN Duty = 5031%(X100), DQS PI = 0
2416 12:11:31.903062 [0] AVG Duty = 5093%(X100)
2417 12:11:31.903171
2418 12:11:31.906808 ==DQM 1 ==
2419 12:11:31.910055 Final DQM duty delay cell = 0
2420 12:11:31.913296 [0] MAX Duty = 5062%(X100), DQS PI = 26
2421 12:11:31.916562 [0] MIN Duty = 4907%(X100), DQS PI = 36
2422 12:11:31.916645 [0] AVG Duty = 4984%(X100)
2423 12:11:31.916711
2424 12:11:31.923197 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2425 12:11:31.923304
2426 12:11:31.926773 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2427 12:11:31.930149 [DutyScan_Calibration_Flow] ====Done====
2428 12:11:31.930231
2429 12:11:31.933343 [DutyScan_Calibration_Flow] k_type=2
2430 12:11:31.948886
2431 12:11:31.948979 ==DQ 0 ==
2432 12:11:31.952306 Final DQ duty delay cell = -4
2433 12:11:31.955816 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2434 12:11:31.959074 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2435 12:11:31.961848 [-4] AVG Duty = 5000%(X100)
2436 12:11:31.961930
2437 12:11:31.961996 ==DQ 1 ==
2438 12:11:31.965227 Final DQ duty delay cell = 0
2439 12:11:31.968752 [0] MAX Duty = 5125%(X100), DQS PI = 20
2440 12:11:31.972033 [0] MIN Duty = 4969%(X100), DQS PI = 12
2441 12:11:31.972116 [0] AVG Duty = 5047%(X100)
2442 12:11:31.975483
2443 12:11:31.978863 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2444 12:11:31.978945
2445 12:11:31.982061 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2446 12:11:31.985487 [DutyScan_Calibration_Flow] ====Done====
2447 12:11:31.988873 nWR fixed to 30
2448 12:11:31.988957 [ModeRegInit_LP4] CH0 RK0
2449 12:11:31.992365 [ModeRegInit_LP4] CH0 RK1
2450 12:11:31.995797 [ModeRegInit_LP4] CH1 RK0
2451 12:11:31.998604 [ModeRegInit_LP4] CH1 RK1
2452 12:11:31.998685 match AC timing 7
2453 12:11:32.001893 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 12:11:32.008668 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 12:11:32.012393 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 12:11:32.015639 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 12:11:32.022004 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 12:11:32.022088 ==
2459 12:11:32.025258 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 12:11:32.028648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 12:11:32.028733 ==
2462 12:11:32.035500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 12:11:32.041957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2464 12:11:32.048657 [CA 0] Center 39 (8~70) winsize 63
2465 12:11:32.052257 [CA 1] Center 39 (8~70) winsize 63
2466 12:11:32.055659 [CA 2] Center 35 (5~66) winsize 62
2467 12:11:32.059133 [CA 3] Center 34 (4~65) winsize 62
2468 12:11:32.062690 [CA 4] Center 33 (3~64) winsize 62
2469 12:11:32.065911 [CA 5] Center 32 (3~62) winsize 60
2470 12:11:32.066024
2471 12:11:32.069209 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2472 12:11:32.069313
2473 12:11:32.072551 [CATrainingPosCal] consider 1 rank data
2474 12:11:32.075925 u2DelayCellTimex100 = 270/100 ps
2475 12:11:32.078710 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2476 12:11:32.082116 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2477 12:11:32.089249 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2478 12:11:32.092815 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2479 12:11:32.096171 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2480 12:11:32.099544 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2481 12:11:32.099625
2482 12:11:32.102998 CA PerBit enable=1, Macro0, CA PI delay=32
2483 12:11:32.103105
2484 12:11:32.105671 [CBTSetCACLKResult] CA Dly = 32
2485 12:11:32.105775 CS Dly: 6 (0~37)
2486 12:11:32.105878 ==
2487 12:11:32.109124 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 12:11:32.115849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 12:11:32.115938 ==
2490 12:11:32.119067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 12:11:32.125793 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 12:11:32.134455 [CA 0] Center 38 (8~69) winsize 62
2493 12:11:32.137869 [CA 1] Center 38 (8~69) winsize 62
2494 12:11:32.141236 [CA 2] Center 35 (5~66) winsize 62
2495 12:11:32.145117 [CA 3] Center 34 (4~65) winsize 62
2496 12:11:32.148378 [CA 4] Center 33 (3~64) winsize 62
2497 12:11:32.151472 [CA 5] Center 32 (3~62) winsize 60
2498 12:11:32.151575
2499 12:11:32.154679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 12:11:32.154761
2501 12:11:32.158082 [CATrainingPosCal] consider 2 rank data
2502 12:11:32.161612 u2DelayCellTimex100 = 270/100 ps
2503 12:11:32.165068 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2504 12:11:32.168476 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2505 12:11:32.171889 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2506 12:11:32.178581 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2507 12:11:32.182017 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2508 12:11:32.184795 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2509 12:11:32.184900
2510 12:11:32.188150 CA PerBit enable=1, Macro0, CA PI delay=32
2511 12:11:32.188234
2512 12:11:32.191597 [CBTSetCACLKResult] CA Dly = 32
2513 12:11:32.191705 CS Dly: 7 (0~39)
2514 12:11:32.191814
2515 12:11:32.194815 ----->DramcWriteLeveling(PI) begin...
2516 12:11:32.198157 ==
2517 12:11:32.198244 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 12:11:32.205136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 12:11:32.205223 ==
2520 12:11:32.208580 Write leveling (Byte 0): 34 => 34
2521 12:11:32.211843 Write leveling (Byte 1): 28 => 28
2522 12:11:32.211925 DramcWriteLeveling(PI) end<-----
2523 12:11:32.214636
2524 12:11:32.214741 ==
2525 12:11:32.218648 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 12:11:32.221454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 12:11:32.221565 ==
2528 12:11:32.224717 [Gating] SW mode calibration
2529 12:11:32.231960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 12:11:32.235188 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 12:11:32.241877 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2532 12:11:32.245303 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2533 12:11:32.248660 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 12:11:32.255226 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 12:11:32.258239 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 12:11:32.261964 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 12:11:32.268525 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2538 12:11:32.272034 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
2539 12:11:32.275428 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2540 12:11:32.281433 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 12:11:32.284852 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 12:11:32.288245 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 12:11:32.294929 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 12:11:32.298343 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 12:11:32.301617 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2546 12:11:32.304914 1 0 28 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
2547 12:11:32.311824 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2548 12:11:32.315295 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:11:32.318707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 12:11:32.324939 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 12:11:32.328271 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:11:32.331626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 12:11:32.338215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 12:11:32.341465 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 12:11:32.344838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 12:11:32.352127 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:11:32.354879 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:11:32.358394 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:11:32.365165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:11:32.368412 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:11:32.372137 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:11:32.375535 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:11:32.381643 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:11:32.385029 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:11:32.388449 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:11:32.395189 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:11:32.398678 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:11:32.401847 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:11:32.408698 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 12:11:32.412082 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 12:11:32.415534 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 12:11:32.418842 Total UI for P1: 0, mck2ui 16
2573 12:11:32.421785 best dqsien dly found for B0: ( 1, 3, 26)
2574 12:11:32.428444 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 12:11:32.428570 Total UI for P1: 0, mck2ui 16
2576 12:11:32.435232 best dqsien dly found for B1: ( 1, 4, 0)
2577 12:11:32.438574 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2578 12:11:32.441794 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2579 12:11:32.441897
2580 12:11:32.445068 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2581 12:11:32.448210 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2582 12:11:32.452184 [Gating] SW calibration Done
2583 12:11:32.452292 ==
2584 12:11:32.455486 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 12:11:32.458834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 12:11:32.458918 ==
2587 12:11:32.462321 RX Vref Scan: 0
2588 12:11:32.462502
2589 12:11:32.462624 RX Vref 0 -> 0, step: 1
2590 12:11:32.462743
2591 12:11:32.465059 RX Delay -40 -> 252, step: 8
2592 12:11:32.468527 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2593 12:11:32.475231 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2594 12:11:32.478433 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2595 12:11:32.481514 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2596 12:11:32.485396 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2597 12:11:32.488612 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2598 12:11:32.495551 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2599 12:11:32.498772 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2600 12:11:32.502132 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2601 12:11:32.504853 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2602 12:11:32.508829 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2603 12:11:32.512158 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2604 12:11:32.518379 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2605 12:11:32.521688 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2606 12:11:32.525040 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2607 12:11:32.528463 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2608 12:11:32.528567 ==
2609 12:11:32.531826 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 12:11:32.538640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 12:11:32.538725 ==
2612 12:11:32.538791 DQS Delay:
2613 12:11:32.541903 DQS0 = 0, DQS1 = 0
2614 12:11:32.541985 DQM Delay:
2615 12:11:32.542052 DQM0 = 121, DQM1 = 113
2616 12:11:32.545430 DQ Delay:
2617 12:11:32.548562 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2618 12:11:32.551861 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2619 12:11:32.555625 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2620 12:11:32.558957 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2621 12:11:32.559039
2622 12:11:32.559104
2623 12:11:32.559164 ==
2624 12:11:32.562238 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 12:11:32.565566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 12:11:32.565654 ==
2627 12:11:32.568901
2628 12:11:32.568992
2629 12:11:32.569065 TX Vref Scan disable
2630 12:11:32.572208 == TX Byte 0 ==
2631 12:11:32.575653 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2632 12:11:32.578977 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2633 12:11:32.582402 == TX Byte 1 ==
2634 12:11:32.585752 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2635 12:11:32.588992 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2636 12:11:32.589099 ==
2637 12:11:32.592047 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 12:11:32.598720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 12:11:32.598946 ==
2640 12:11:32.609698 TX Vref=22, minBit 0, minWin=25, winSum=406
2641 12:11:32.612883 TX Vref=24, minBit 0, minWin=25, winSum=416
2642 12:11:32.616168 TX Vref=26, minBit 2, minWin=25, winSum=421
2643 12:11:32.619529 TX Vref=28, minBit 7, minWin=25, winSum=423
2644 12:11:32.622979 TX Vref=30, minBit 0, minWin=26, winSum=423
2645 12:11:32.626477 TX Vref=32, minBit 1, minWin=26, winSum=424
2646 12:11:32.633173 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
2647 12:11:32.633288
2648 12:11:32.636604 Final TX Range 1 Vref 32
2649 12:11:32.636686
2650 12:11:32.636759 ==
2651 12:11:32.639308 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 12:11:32.642754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 12:11:32.642829 ==
2654 12:11:32.642892
2655 12:11:32.646202
2656 12:11:32.646284 TX Vref Scan disable
2657 12:11:32.649651 == TX Byte 0 ==
2658 12:11:32.652844 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2659 12:11:32.656177 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2660 12:11:32.659510 == TX Byte 1 ==
2661 12:11:32.662828 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2662 12:11:32.666165 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2663 12:11:32.666248
2664 12:11:32.669473 [DATLAT]
2665 12:11:32.669583 Freq=1200, CH0 RK0
2666 12:11:32.669678
2667 12:11:32.673450 DATLAT Default: 0xd
2668 12:11:32.673552 0, 0xFFFF, sum = 0
2669 12:11:32.676717 1, 0xFFFF, sum = 0
2670 12:11:32.676801 2, 0xFFFF, sum = 0
2671 12:11:32.680253 3, 0xFFFF, sum = 0
2672 12:11:32.680337 4, 0xFFFF, sum = 0
2673 12:11:32.683075 5, 0xFFFF, sum = 0
2674 12:11:32.683185 6, 0xFFFF, sum = 0
2675 12:11:32.686613 7, 0xFFFF, sum = 0
2676 12:11:32.686692 8, 0xFFFF, sum = 0
2677 12:11:32.690001 9, 0xFFFF, sum = 0
2678 12:11:32.693331 10, 0xFFFF, sum = 0
2679 12:11:32.693495 11, 0xFFFF, sum = 0
2680 12:11:32.696563 12, 0x0, sum = 1
2681 12:11:32.696648 13, 0x0, sum = 2
2682 12:11:32.696715 14, 0x0, sum = 3
2683 12:11:32.699786 15, 0x0, sum = 4
2684 12:11:32.699868 best_step = 13
2685 12:11:32.699934
2686 12:11:32.699993 ==
2687 12:11:32.703380 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 12:11:32.709907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 12:11:32.709990 ==
2690 12:11:32.710055 RX Vref Scan: 1
2691 12:11:32.710116
2692 12:11:32.713290 Set Vref Range= 32 -> 127
2693 12:11:32.713390
2694 12:11:32.716582 RX Vref 32 -> 127, step: 1
2695 12:11:32.716669
2696 12:11:32.719944 RX Delay -13 -> 252, step: 4
2697 12:11:32.720030
2698 12:11:32.723219 Set Vref, RX VrefLevel [Byte0]: 32
2699 12:11:32.726687 [Byte1]: 32
2700 12:11:32.726773
2701 12:11:32.730155 Set Vref, RX VrefLevel [Byte0]: 33
2702 12:11:32.732872 [Byte1]: 33
2703 12:11:32.732961
2704 12:11:32.736260 Set Vref, RX VrefLevel [Byte0]: 34
2705 12:11:32.739613 [Byte1]: 34
2706 12:11:32.743793
2707 12:11:32.743879 Set Vref, RX VrefLevel [Byte0]: 35
2708 12:11:32.747231 [Byte1]: 35
2709 12:11:32.751460
2710 12:11:32.751548 Set Vref, RX VrefLevel [Byte0]: 36
2711 12:11:32.758170 [Byte1]: 36
2712 12:11:32.758256
2713 12:11:32.761507 Set Vref, RX VrefLevel [Byte0]: 37
2714 12:11:32.764819 [Byte1]: 37
2715 12:11:32.764907
2716 12:11:32.768026 Set Vref, RX VrefLevel [Byte0]: 38
2717 12:11:32.771460 [Byte1]: 38
2718 12:11:32.775529
2719 12:11:32.775615 Set Vref, RX VrefLevel [Byte0]: 39
2720 12:11:32.778934 [Byte1]: 39
2721 12:11:32.782964
2722 12:11:32.783071 Set Vref, RX VrefLevel [Byte0]: 40
2723 12:11:32.786374 [Byte1]: 40
2724 12:11:32.791167
2725 12:11:32.791249 Set Vref, RX VrefLevel [Byte0]: 41
2726 12:11:32.794615 [Byte1]: 41
2727 12:11:32.799145
2728 12:11:32.799261 Set Vref, RX VrefLevel [Byte0]: 42
2729 12:11:32.802608 [Byte1]: 42
2730 12:11:32.806700
2731 12:11:32.806780 Set Vref, RX VrefLevel [Byte0]: 43
2732 12:11:32.810023 [Byte1]: 43
2733 12:11:32.814522
2734 12:11:32.814630 Set Vref, RX VrefLevel [Byte0]: 44
2735 12:11:32.818129 [Byte1]: 44
2736 12:11:32.822844
2737 12:11:32.822938 Set Vref, RX VrefLevel [Byte0]: 45
2738 12:11:32.826076 [Byte1]: 45
2739 12:11:32.830722
2740 12:11:32.830801 Set Vref, RX VrefLevel [Byte0]: 46
2741 12:11:32.834032 [Byte1]: 46
2742 12:11:32.838112
2743 12:11:32.838195 Set Vref, RX VrefLevel [Byte0]: 47
2744 12:11:32.841621 [Byte1]: 47
2745 12:11:32.846420
2746 12:11:32.846502 Set Vref, RX VrefLevel [Byte0]: 48
2747 12:11:32.849842 [Byte1]: 48
2748 12:11:32.853948
2749 12:11:32.854030 Set Vref, RX VrefLevel [Byte0]: 49
2750 12:11:32.857462 [Byte1]: 49
2751 12:11:32.862496
2752 12:11:32.862576 Set Vref, RX VrefLevel [Byte0]: 50
2753 12:11:32.865221 [Byte1]: 50
2754 12:11:32.869771
2755 12:11:32.869850 Set Vref, RX VrefLevel [Byte0]: 51
2756 12:11:32.873559 [Byte1]: 51
2757 12:11:32.878086
2758 12:11:32.878173 Set Vref, RX VrefLevel [Byte0]: 52
2759 12:11:32.881340 [Byte1]: 52
2760 12:11:32.885884
2761 12:11:32.885970 Set Vref, RX VrefLevel [Byte0]: 53
2762 12:11:32.889252 [Byte1]: 53
2763 12:11:32.894064
2764 12:11:32.894170 Set Vref, RX VrefLevel [Byte0]: 54
2765 12:11:32.896921 [Byte1]: 54
2766 12:11:32.901574
2767 12:11:32.901660 Set Vref, RX VrefLevel [Byte0]: 55
2768 12:11:32.904815 [Byte1]: 55
2769 12:11:32.909565
2770 12:11:32.909655 Set Vref, RX VrefLevel [Byte0]: 56
2771 12:11:32.912992 [Byte1]: 56
2772 12:11:32.917644
2773 12:11:32.917729 Set Vref, RX VrefLevel [Byte0]: 57
2774 12:11:32.920896 [Byte1]: 57
2775 12:11:32.925316
2776 12:11:32.925398 Set Vref, RX VrefLevel [Byte0]: 58
2777 12:11:32.928538 [Byte1]: 58
2778 12:11:32.932975
2779 12:11:32.933077 Set Vref, RX VrefLevel [Byte0]: 59
2780 12:11:32.936777 [Byte1]: 59
2781 12:11:32.940782
2782 12:11:32.940860 Set Vref, RX VrefLevel [Byte0]: 60
2783 12:11:32.944185 [Byte1]: 60
2784 12:11:32.948941
2785 12:11:32.949024 Set Vref, RX VrefLevel [Byte0]: 61
2786 12:11:32.952307 [Byte1]: 61
2787 12:11:32.957075
2788 12:11:32.957157 Set Vref, RX VrefLevel [Byte0]: 62
2789 12:11:32.959880 [Byte1]: 62
2790 12:11:32.964496
2791 12:11:32.964588 Set Vref, RX VrefLevel [Byte0]: 63
2792 12:11:32.967822 [Byte1]: 63
2793 12:11:32.972643
2794 12:11:32.972725 Set Vref, RX VrefLevel [Byte0]: 64
2795 12:11:32.975915 [Byte1]: 64
2796 12:11:32.980594
2797 12:11:32.980692 Set Vref, RX VrefLevel [Byte0]: 65
2798 12:11:32.983872 [Byte1]: 65
2799 12:11:32.988215
2800 12:11:32.988325 Set Vref, RX VrefLevel [Byte0]: 66
2801 12:11:32.991442 [Byte1]: 66
2802 12:11:32.996149
2803 12:11:32.996233 Set Vref, RX VrefLevel [Byte0]: 67
2804 12:11:32.999482 [Byte1]: 67
2805 12:11:33.004314
2806 12:11:33.004398 Set Vref, RX VrefLevel [Byte0]: 68
2807 12:11:33.007447 [Byte1]: 68
2808 12:11:33.012162
2809 12:11:33.012261 Set Vref, RX VrefLevel [Byte0]: 69
2810 12:11:33.015536 [Byte1]: 69
2811 12:11:33.019639
2812 12:11:33.019721 Final RX Vref Byte 0 = 55 to rank0
2813 12:11:33.023213 Final RX Vref Byte 1 = 48 to rank0
2814 12:11:33.026573 Final RX Vref Byte 0 = 55 to rank1
2815 12:11:33.029871 Final RX Vref Byte 1 = 48 to rank1==
2816 12:11:33.032883 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 12:11:33.039880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 12:11:33.039981 ==
2819 12:11:33.040108 DQS Delay:
2820 12:11:33.040200 DQS0 = 0, DQS1 = 0
2821 12:11:33.043044 DQM Delay:
2822 12:11:33.043129 DQM0 = 120, DQM1 = 111
2823 12:11:33.046271 DQ Delay:
2824 12:11:33.049586 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2825 12:11:33.053010 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =124
2826 12:11:33.056400 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2827 12:11:33.059852 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2828 12:11:33.059943
2829 12:11:33.060012
2830 12:11:33.069563 [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2831 12:11:33.069670 CH0 RK0: MR19=404, MR18=120B
2832 12:11:33.076478 CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26
2833 12:11:33.076560
2834 12:11:33.079680 ----->DramcWriteLeveling(PI) begin...
2835 12:11:33.079760 ==
2836 12:11:33.083089 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 12:11:33.086499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 12:11:33.089897 ==
2839 12:11:33.089981 Write leveling (Byte 0): 34 => 34
2840 12:11:33.093197 Write leveling (Byte 1): 29 => 29
2841 12:11:33.096908 DramcWriteLeveling(PI) end<-----
2842 12:11:33.096994
2843 12:11:33.097060 ==
2844 12:11:33.100155 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 12:11:33.106646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 12:11:33.106735 ==
2847 12:11:33.106803 [Gating] SW mode calibration
2848 12:11:33.116652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 12:11:33.120055 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 12:11:33.123563 0 15 0 | B1->B0 | 3434 3130 | 0 1 | (0 0) (0 0)
2851 12:11:33.130307 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 12:11:33.133652 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 12:11:33.137076 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 12:11:33.143771 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 12:11:33.146917 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 12:11:33.150161 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 12:11:33.156785 0 15 28 | B1->B0 | 2f2f 2d2d | 0 0 | (0 1) (0 1)
2858 12:11:33.160004 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2859 12:11:33.163351 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 12:11:33.170420 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 12:11:33.173083 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 12:11:33.176528 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 12:11:33.183169 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 12:11:33.186519 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2865 12:11:33.189914 1 0 28 | B1->B0 | 3333 3737 | 0 0 | (0 0) (0 0)
2866 12:11:33.196819 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 12:11:33.200335 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 12:11:33.203621 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 12:11:33.209960 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 12:11:33.213410 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 12:11:33.216528 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 12:11:33.219858 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 12:11:33.226791 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2874 12:11:33.229708 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2875 12:11:33.233009 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:11:33.239677 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:11:33.243006 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:11:33.246524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:11:33.253338 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:11:33.256502 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:11:33.260244 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:11:33.266737 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:11:33.270245 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:11:33.273558 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:11:33.279812 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:11:33.283227 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:11:33.286658 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:11:33.293175 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:11:33.296617 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2890 12:11:33.300081 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 12:11:33.303580 Total UI for P1: 0, mck2ui 16
2892 12:11:33.306920 best dqsien dly found for B0: ( 1, 3, 28)
2893 12:11:33.310284 Total UI for P1: 0, mck2ui 16
2894 12:11:33.313606 best dqsien dly found for B1: ( 1, 3, 28)
2895 12:11:33.316891 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2896 12:11:33.320249 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2897 12:11:33.320335
2898 12:11:33.323608 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2899 12:11:33.326941 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2900 12:11:33.329945 [Gating] SW calibration Done
2901 12:11:33.330054 ==
2902 12:11:33.333136 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 12:11:33.340047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 12:11:33.340135 ==
2905 12:11:33.340221 RX Vref Scan: 0
2906 12:11:33.340300
2907 12:11:33.343350 RX Vref 0 -> 0, step: 1
2908 12:11:33.343447
2909 12:11:33.346438 RX Delay -40 -> 252, step: 8
2910 12:11:33.349999 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2911 12:11:33.353314 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2912 12:11:33.356623 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2913 12:11:33.360112 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2914 12:11:33.366631 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2915 12:11:33.369982 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2916 12:11:33.373260 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2917 12:11:33.376799 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2918 12:11:33.380145 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2919 12:11:33.383579 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2920 12:11:33.390349 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2921 12:11:33.393815 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2922 12:11:33.397134 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2923 12:11:33.400609 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2924 12:11:33.406807 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2925 12:11:33.410235 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2926 12:11:33.410333 ==
2927 12:11:33.413674 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 12:11:33.417029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 12:11:33.417113 ==
2930 12:11:33.417188 DQS Delay:
2931 12:11:33.420323 DQS0 = 0, DQS1 = 0
2932 12:11:33.420406 DQM Delay:
2933 12:11:33.423629 DQM0 = 122, DQM1 = 112
2934 12:11:33.423748 DQ Delay:
2935 12:11:33.426888 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2936 12:11:33.430426 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2937 12:11:33.433695 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2938 12:11:33.437011 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2939 12:11:33.440269
2940 12:11:33.440352
2941 12:11:33.440448 ==
2942 12:11:33.443563 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 12:11:33.446837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 12:11:33.447042 ==
2945 12:11:33.447137
2946 12:11:33.447258
2947 12:11:33.450714 TX Vref Scan disable
2948 12:11:33.450801 == TX Byte 0 ==
2949 12:11:33.456817 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2950 12:11:33.460522 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2951 12:11:33.460613 == TX Byte 1 ==
2952 12:11:33.467108 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2953 12:11:33.470259 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2954 12:11:33.470393 ==
2955 12:11:33.473651 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 12:11:33.476984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 12:11:33.477073 ==
2958 12:11:33.489949 TX Vref=22, minBit 2, minWin=25, winSum=417
2959 12:11:33.493307 TX Vref=24, minBit 3, minWin=25, winSum=423
2960 12:11:33.496614 TX Vref=26, minBit 0, minWin=26, winSum=426
2961 12:11:33.499951 TX Vref=28, minBit 1, minWin=26, winSum=430
2962 12:11:33.503314 TX Vref=30, minBit 1, minWin=26, winSum=431
2963 12:11:33.506638 TX Vref=32, minBit 5, minWin=25, winSum=425
2964 12:11:33.513500 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
2965 12:11:33.513619
2966 12:11:33.516919 Final TX Range 1 Vref 30
2967 12:11:33.517027
2968 12:11:33.517123 ==
2969 12:11:33.519628 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 12:11:33.523020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 12:11:33.523110 ==
2972 12:11:33.523212
2973 12:11:33.523310
2974 12:11:33.526389 TX Vref Scan disable
2975 12:11:33.529641 == TX Byte 0 ==
2976 12:11:33.533498 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2977 12:11:33.536643 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2978 12:11:33.539859 == TX Byte 1 ==
2979 12:11:33.543208 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2980 12:11:33.546971 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2981 12:11:33.547111
2982 12:11:33.550291 [DATLAT]
2983 12:11:33.550393 Freq=1200, CH0 RK1
2984 12:11:33.550480
2985 12:11:33.553478 DATLAT Default: 0xd
2986 12:11:33.553579 0, 0xFFFF, sum = 0
2987 12:11:33.556698 1, 0xFFFF, sum = 0
2988 12:11:33.556784 2, 0xFFFF, sum = 0
2989 12:11:33.560058 3, 0xFFFF, sum = 0
2990 12:11:33.560178 4, 0xFFFF, sum = 0
2991 12:11:33.563210 5, 0xFFFF, sum = 0
2992 12:11:33.563322 6, 0xFFFF, sum = 0
2993 12:11:33.566707 7, 0xFFFF, sum = 0
2994 12:11:33.566792 8, 0xFFFF, sum = 0
2995 12:11:33.570150 9, 0xFFFF, sum = 0
2996 12:11:33.570236 10, 0xFFFF, sum = 0
2997 12:11:33.573523 11, 0xFFFF, sum = 0
2998 12:11:33.573609 12, 0x0, sum = 1
2999 12:11:33.576835 13, 0x0, sum = 2
3000 12:11:33.576921 14, 0x0, sum = 3
3001 12:11:33.579875 15, 0x0, sum = 4
3002 12:11:33.579961 best_step = 13
3003 12:11:33.580044
3004 12:11:33.580123 ==
3005 12:11:33.583183 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 12:11:33.590048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 12:11:33.590157 ==
3008 12:11:33.590241 RX Vref Scan: 0
3009 12:11:33.590347
3010 12:11:33.593372 RX Vref 0 -> 0, step: 1
3011 12:11:33.593456
3012 12:11:33.596907 RX Delay -13 -> 252, step: 4
3013 12:11:33.600294 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3014 12:11:33.603071 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3015 12:11:33.609918 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3016 12:11:33.613317 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3017 12:11:33.616847 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3018 12:11:33.620237 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3019 12:11:33.623080 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3020 12:11:33.630006 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3021 12:11:33.633759 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3022 12:11:33.636497 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3023 12:11:33.640477 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3024 12:11:33.643789 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3025 12:11:33.649944 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3026 12:11:33.653194 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3027 12:11:33.656591 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3028 12:11:33.659789 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3029 12:11:33.659874 ==
3030 12:11:33.663627 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 12:11:33.666853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 12:11:33.670284 ==
3033 12:11:33.670398 DQS Delay:
3034 12:11:33.670469 DQS0 = 0, DQS1 = 0
3035 12:11:33.673709 DQM Delay:
3036 12:11:33.673809 DQM0 = 121, DQM1 = 109
3037 12:11:33.677220 DQ Delay:
3038 12:11:33.680539 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3039 12:11:33.683748 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3040 12:11:33.686803 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3041 12:11:33.690113 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =120
3042 12:11:33.690199
3043 12:11:33.690310
3044 12:11:33.696906 [DQSOSCAuto] RK1, (LSB)MR18= 0xded, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3045 12:11:33.700323 CH0 RK1: MR19=403, MR18=DED
3046 12:11:33.706467 CH0_RK1: MR19=0x403, MR18=0xDED, DQSOSC=405, MR23=63, INC=39, DEC=26
3047 12:11:33.709917 [RxdqsGatingPostProcess] freq 1200
3048 12:11:33.716766 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 12:11:33.716881 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 12:11:33.720241 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 12:11:33.723689 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 12:11:33.726572 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 12:11:33.729960 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 12:11:33.733539 best DQS1 dly(2T, 0.5T) = (0, 11)
3055 12:11:33.736743 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 12:11:33.739901 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3057 12:11:33.743096 Pre-setting of DQS Precalculation
3058 12:11:33.746821 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 12:11:33.749980 ==
3060 12:11:33.750067 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 12:11:33.756631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 12:11:33.756729 ==
3063 12:11:33.759940 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 12:11:33.766540 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3065 12:11:33.775573 [CA 0] Center 37 (7~68) winsize 62
3066 12:11:33.778957 [CA 1] Center 37 (7~68) winsize 62
3067 12:11:33.782385 [CA 2] Center 35 (5~65) winsize 61
3068 12:11:33.785764 [CA 3] Center 35 (5~65) winsize 61
3069 12:11:33.789105 [CA 4] Center 34 (4~64) winsize 61
3070 12:11:33.792328 [CA 5] Center 33 (3~63) winsize 61
3071 12:11:33.792421
3072 12:11:33.795554 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3073 12:11:33.795679
3074 12:11:33.798972 [CATrainingPosCal] consider 1 rank data
3075 12:11:33.802422 u2DelayCellTimex100 = 270/100 ps
3076 12:11:33.805789 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 12:11:33.809272 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3078 12:11:33.812557 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3079 12:11:33.819529 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3080 12:11:33.822814 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3081 12:11:33.826418 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3082 12:11:33.826494
3083 12:11:33.829096 CA PerBit enable=1, Macro0, CA PI delay=33
3084 12:11:33.829198
3085 12:11:33.832576 [CBTSetCACLKResult] CA Dly = 33
3086 12:11:33.832678 CS Dly: 7 (0~38)
3087 12:11:33.832770 ==
3088 12:11:33.835954 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 12:11:33.842756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 12:11:33.842864 ==
3091 12:11:33.846092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 12:11:33.852419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 12:11:33.861499 [CA 0] Center 37 (7~68) winsize 62
3094 12:11:33.864773 [CA 1] Center 38 (8~68) winsize 61
3095 12:11:33.868133 [CA 2] Center 35 (5~66) winsize 62
3096 12:11:33.871549 [CA 3] Center 34 (4~65) winsize 62
3097 12:11:33.874518 [CA 4] Center 34 (4~65) winsize 62
3098 12:11:33.877724 [CA 5] Center 34 (4~64) winsize 61
3099 12:11:33.877842
3100 12:11:33.881571 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 12:11:33.881673
3102 12:11:33.884849 [CATrainingPosCal] consider 2 rank data
3103 12:11:33.888252 u2DelayCellTimex100 = 270/100 ps
3104 12:11:33.891678 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 12:11:33.894465 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3106 12:11:33.901361 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 12:11:33.904394 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3108 12:11:33.907563 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3109 12:11:33.910979 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3110 12:11:33.911095
3111 12:11:33.914520 CA PerBit enable=1, Macro0, CA PI delay=33
3112 12:11:33.914705
3113 12:11:33.917774 [CBTSetCACLKResult] CA Dly = 33
3114 12:11:33.917873 CS Dly: 8 (0~40)
3115 12:11:33.917965
3116 12:11:33.921214 ----->DramcWriteLeveling(PI) begin...
3117 12:11:33.924586 ==
3118 12:11:33.928062 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 12:11:33.931464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 12:11:33.931554 ==
3121 12:11:33.934265 Write leveling (Byte 0): 26 => 26
3122 12:11:33.937752 Write leveling (Byte 1): 27 => 27
3123 12:11:33.941132 DramcWriteLeveling(PI) end<-----
3124 12:11:33.941230
3125 12:11:33.941324 ==
3126 12:11:33.944585 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 12:11:33.947973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 12:11:33.948130 ==
3129 12:11:33.951398 [Gating] SW mode calibration
3130 12:11:33.958014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 12:11:33.961306 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 12:11:33.967639 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 12:11:33.971421 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 12:11:33.974773 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 12:11:33.981306 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 12:11:33.984584 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 12:11:33.988028 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 12:11:33.994364 0 15 24 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (0 1)
3139 12:11:33.997783 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 12:11:34.001224 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 12:11:34.008304 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 12:11:34.011492 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 12:11:34.014576 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 12:11:34.021203 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 12:11:34.024586 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 12:11:34.028026 1 0 24 | B1->B0 | 3737 4343 | 0 1 | (0 0) (0 0)
3147 12:11:34.031332 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 12:11:34.038259 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 12:11:34.041695 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 12:11:34.045158 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 12:11:34.051256 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 12:11:34.054774 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 12:11:34.058044 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 12:11:34.064899 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 12:11:34.068128 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3156 12:11:34.071248 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:11:34.078390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:11:34.081594 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:11:34.084622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:11:34.091837 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:11:34.095128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:11:34.098272 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:11:34.105039 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:11:34.108536 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:11:34.111830 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:11:34.115023 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:11:34.121458 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:11:34.125289 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:11:34.128467 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:11:34.135319 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 12:11:34.138319 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 12:11:34.141721 Total UI for P1: 0, mck2ui 16
3173 12:11:34.145042 best dqsien dly found for B0: ( 1, 3, 24)
3174 12:11:34.148545 Total UI for P1: 0, mck2ui 16
3175 12:11:34.152032 best dqsien dly found for B1: ( 1, 3, 24)
3176 12:11:34.155352 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3177 12:11:34.158166 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3178 12:11:34.158276
3179 12:11:34.161810 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3180 12:11:34.165263 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3181 12:11:34.168595 [Gating] SW calibration Done
3182 12:11:34.168680 ==
3183 12:11:34.171977 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 12:11:34.175473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 12:11:34.178756 ==
3186 12:11:34.178855 RX Vref Scan: 0
3187 12:11:34.178952
3188 12:11:34.181896 RX Vref 0 -> 0, step: 1
3189 12:11:34.182032
3190 12:11:34.185046 RX Delay -40 -> 252, step: 8
3191 12:11:34.188243 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 12:11:34.192137 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 12:11:34.195242 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3194 12:11:34.198722 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3195 12:11:34.205339 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3196 12:11:34.208622 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3197 12:11:34.211813 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3198 12:11:34.215198 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3199 12:11:34.218666 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3200 12:11:34.221936 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3201 12:11:34.228659 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 12:11:34.231783 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3203 12:11:34.234918 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 12:11:34.238189 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3205 12:11:34.245086 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3206 12:11:34.248289 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3207 12:11:34.248402 ==
3208 12:11:34.251806 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 12:11:34.255081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 12:11:34.255191 ==
3211 12:11:34.255289 DQS Delay:
3212 12:11:34.258731 DQS0 = 0, DQS1 = 0
3213 12:11:34.258813 DQM Delay:
3214 12:11:34.262138 DQM0 = 119, DQM1 = 116
3215 12:11:34.262219 DQ Delay:
3216 12:11:34.265619 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3217 12:11:34.268420 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3218 12:11:34.271758 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3219 12:11:34.275168 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3220 12:11:34.278588
3221 12:11:34.278672
3222 12:11:34.278738 ==
3223 12:11:34.282128 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 12:11:34.285431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 12:11:34.285516 ==
3226 12:11:34.285584
3227 12:11:34.285646
3228 12:11:34.288783 TX Vref Scan disable
3229 12:11:34.288867 == TX Byte 0 ==
3230 12:11:34.295302 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3231 12:11:34.298486 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3232 12:11:34.298595 == TX Byte 1 ==
3233 12:11:34.301830 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3234 12:11:34.308406 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3235 12:11:34.308493 ==
3236 12:11:34.311789 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 12:11:34.315173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 12:11:34.315266 ==
3239 12:11:34.327074 TX Vref=22, minBit 9, minWin=24, winSum=409
3240 12:11:34.330607 TX Vref=24, minBit 9, minWin=25, winSum=419
3241 12:11:34.333843 TX Vref=26, minBit 9, minWin=25, winSum=424
3242 12:11:34.337067 TX Vref=28, minBit 9, minWin=25, winSum=425
3243 12:11:34.340797 TX Vref=30, minBit 9, minWin=25, winSum=431
3244 12:11:34.344041 TX Vref=32, minBit 9, minWin=26, winSum=434
3245 12:11:34.350276 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3246 12:11:34.350366
3247 12:11:34.353686 Final TX Range 1 Vref 32
3248 12:11:34.353772
3249 12:11:34.353839 ==
3250 12:11:34.357160 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 12:11:34.360548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 12:11:34.360635 ==
3253 12:11:34.360703
3254 12:11:34.360766
3255 12:11:34.363896 TX Vref Scan disable
3256 12:11:34.367252 == TX Byte 0 ==
3257 12:11:34.370757 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3258 12:11:34.374034 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3259 12:11:34.377520 == TX Byte 1 ==
3260 12:11:34.380961 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3261 12:11:34.383665 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3262 12:11:34.383775
3263 12:11:34.387547 [DATLAT]
3264 12:11:34.387669 Freq=1200, CH1 RK0
3265 12:11:34.387773
3266 12:11:34.390966 DATLAT Default: 0xd
3267 12:11:34.391079 0, 0xFFFF, sum = 0
3268 12:11:34.394348 1, 0xFFFF, sum = 0
3269 12:11:34.394460 2, 0xFFFF, sum = 0
3270 12:11:34.397718 3, 0xFFFF, sum = 0
3271 12:11:34.397837 4, 0xFFFF, sum = 0
3272 12:11:34.400910 5, 0xFFFF, sum = 0
3273 12:11:34.401024 6, 0xFFFF, sum = 0
3274 12:11:34.404548 7, 0xFFFF, sum = 0
3275 12:11:34.404661 8, 0xFFFF, sum = 0
3276 12:11:34.407695 9, 0xFFFF, sum = 0
3277 12:11:34.407806 10, 0xFFFF, sum = 0
3278 12:11:34.410411 11, 0xFFFF, sum = 0
3279 12:11:34.410536 12, 0x0, sum = 1
3280 12:11:34.414383 13, 0x0, sum = 2
3281 12:11:34.414499 14, 0x0, sum = 3
3282 12:11:34.417570 15, 0x0, sum = 4
3283 12:11:34.417679 best_step = 13
3284 12:11:34.417781
3285 12:11:34.417879 ==
3286 12:11:34.420937 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 12:11:34.427450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 12:11:34.427567 ==
3289 12:11:34.427665 RX Vref Scan: 1
3290 12:11:34.427764
3291 12:11:34.430771 Set Vref Range= 32 -> 127
3292 12:11:34.430899
3293 12:11:34.434015 RX Vref 32 -> 127, step: 1
3294 12:11:34.434130
3295 12:11:34.434230 RX Delay -5 -> 252, step: 4
3296 12:11:34.434324
3297 12:11:34.437513 Set Vref, RX VrefLevel [Byte0]: 32
3298 12:11:34.440906 [Byte1]: 32
3299 12:11:34.445489
3300 12:11:34.445604 Set Vref, RX VrefLevel [Byte0]: 33
3301 12:11:34.448816 [Byte1]: 33
3302 12:11:34.452769
3303 12:11:34.452886 Set Vref, RX VrefLevel [Byte0]: 34
3304 12:11:34.456168 [Byte1]: 34
3305 12:11:34.461040
3306 12:11:34.461158 Set Vref, RX VrefLevel [Byte0]: 35
3307 12:11:34.464423 [Byte1]: 35
3308 12:11:34.468562
3309 12:11:34.468649 Set Vref, RX VrefLevel [Byte0]: 36
3310 12:11:34.471893 [Byte1]: 36
3311 12:11:34.476837
3312 12:11:34.476924 Set Vref, RX VrefLevel [Byte0]: 37
3313 12:11:34.480168 [Byte1]: 37
3314 12:11:34.484329
3315 12:11:34.484414 Set Vref, RX VrefLevel [Byte0]: 38
3316 12:11:34.487861 [Byte1]: 38
3317 12:11:34.492619
3318 12:11:34.492704 Set Vref, RX VrefLevel [Byte0]: 39
3319 12:11:34.495334 [Byte1]: 39
3320 12:11:34.500111
3321 12:11:34.500200 Set Vref, RX VrefLevel [Byte0]: 40
3322 12:11:34.503583 [Byte1]: 40
3323 12:11:34.508209
3324 12:11:34.508294 Set Vref, RX VrefLevel [Byte0]: 41
3325 12:11:34.511446 [Byte1]: 41
3326 12:11:34.516112
3327 12:11:34.516199 Set Vref, RX VrefLevel [Byte0]: 42
3328 12:11:34.519429 [Byte1]: 42
3329 12:11:34.524080
3330 12:11:34.524166 Set Vref, RX VrefLevel [Byte0]: 43
3331 12:11:34.527396 [Byte1]: 43
3332 12:11:34.531398
3333 12:11:34.531512 Set Vref, RX VrefLevel [Byte0]: 44
3334 12:11:34.534647 [Byte1]: 44
3335 12:11:34.539234
3336 12:11:34.539346 Set Vref, RX VrefLevel [Byte0]: 45
3337 12:11:34.542708 [Byte1]: 45
3338 12:11:34.547489
3339 12:11:34.547572 Set Vref, RX VrefLevel [Byte0]: 46
3340 12:11:34.550522 [Byte1]: 46
3341 12:11:34.555182
3342 12:11:34.555296 Set Vref, RX VrefLevel [Byte0]: 47
3343 12:11:34.558606 [Byte1]: 47
3344 12:11:34.563306
3345 12:11:34.563426 Set Vref, RX VrefLevel [Byte0]: 48
3346 12:11:34.566102 [Byte1]: 48
3347 12:11:34.570915
3348 12:11:34.571033 Set Vref, RX VrefLevel [Byte0]: 49
3349 12:11:34.574364 [Byte1]: 49
3350 12:11:34.578514
3351 12:11:34.578597 Set Vref, RX VrefLevel [Byte0]: 50
3352 12:11:34.581893 [Byte1]: 50
3353 12:11:34.586697
3354 12:11:34.586780 Set Vref, RX VrefLevel [Byte0]: 51
3355 12:11:34.590027 [Byte1]: 51
3356 12:11:34.594167
3357 12:11:34.594253 Set Vref, RX VrefLevel [Byte0]: 52
3358 12:11:34.597753 [Byte1]: 52
3359 12:11:34.602367
3360 12:11:34.602458 Set Vref, RX VrefLevel [Byte0]: 53
3361 12:11:34.605789 [Byte1]: 53
3362 12:11:34.609894
3363 12:11:34.609978 Set Vref, RX VrefLevel [Byte0]: 54
3364 12:11:34.613399 [Byte1]: 54
3365 12:11:34.618102
3366 12:11:34.618189 Set Vref, RX VrefLevel [Byte0]: 55
3367 12:11:34.621382 [Byte1]: 55
3368 12:11:34.625925
3369 12:11:34.626042 Set Vref, RX VrefLevel [Byte0]: 56
3370 12:11:34.629154 [Byte1]: 56
3371 12:11:34.633891
3372 12:11:34.633978 Set Vref, RX VrefLevel [Byte0]: 57
3373 12:11:34.637048 [Byte1]: 57
3374 12:11:34.641801
3375 12:11:34.641924 Set Vref, RX VrefLevel [Byte0]: 58
3376 12:11:34.645130 [Byte1]: 58
3377 12:11:34.649413
3378 12:11:34.649517 Set Vref, RX VrefLevel [Byte0]: 59
3379 12:11:34.652742 [Byte1]: 59
3380 12:11:34.657333
3381 12:11:34.657446 Set Vref, RX VrefLevel [Byte0]: 60
3382 12:11:34.660491 [Byte1]: 60
3383 12:11:34.664933
3384 12:11:34.665050 Set Vref, RX VrefLevel [Byte0]: 61
3385 12:11:34.668270 [Byte1]: 61
3386 12:11:34.673059
3387 12:11:34.673183 Set Vref, RX VrefLevel [Byte0]: 62
3388 12:11:34.676492 [Byte1]: 62
3389 12:11:34.680559
3390 12:11:34.680673 Set Vref, RX VrefLevel [Byte0]: 63
3391 12:11:34.684090 [Byte1]: 63
3392 12:11:34.688322
3393 12:11:34.688431 Set Vref, RX VrefLevel [Byte0]: 64
3394 12:11:34.691578 [Byte1]: 64
3395 12:11:34.696323
3396 12:11:34.696435 Set Vref, RX VrefLevel [Byte0]: 65
3397 12:11:34.699811 [Byte1]: 65
3398 12:11:34.704650
3399 12:11:34.704737 Set Vref, RX VrefLevel [Byte0]: 66
3400 12:11:34.707463 [Byte1]: 66
3401 12:11:34.712328
3402 12:11:34.712441 Set Vref, RX VrefLevel [Byte0]: 67
3403 12:11:34.715747 [Byte1]: 67
3404 12:11:34.719798
3405 12:11:34.719906 Set Vref, RX VrefLevel [Byte0]: 68
3406 12:11:34.723050 [Byte1]: 68
3407 12:11:34.727636
3408 12:11:34.727726 Set Vref, RX VrefLevel [Byte0]: 69
3409 12:11:34.730776 [Byte1]: 69
3410 12:11:34.735497
3411 12:11:34.735579 Final RX Vref Byte 0 = 55 to rank0
3412 12:11:34.738837 Final RX Vref Byte 1 = 48 to rank0
3413 12:11:34.742677 Final RX Vref Byte 0 = 55 to rank1
3414 12:11:34.745459 Final RX Vref Byte 1 = 48 to rank1==
3415 12:11:34.748777 Dram Type= 6, Freq= 0, CH_1, rank 0
3416 12:11:34.755487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 12:11:34.755598 ==
3418 12:11:34.755694 DQS Delay:
3419 12:11:34.755785 DQS0 = 0, DQS1 = 0
3420 12:11:34.758777 DQM Delay:
3421 12:11:34.758875 DQM0 = 120, DQM1 = 116
3422 12:11:34.762566 DQ Delay:
3423 12:11:34.765941 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3424 12:11:34.769163 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3425 12:11:34.772401 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3426 12:11:34.775718 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3427 12:11:34.775809
3428 12:11:34.775877
3429 12:11:34.782531 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3430 12:11:34.785932 CH1 RK0: MR19=404, MR18=13
3431 12:11:34.792151 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3432 12:11:34.792241
3433 12:11:34.795630 ----->DramcWriteLeveling(PI) begin...
3434 12:11:34.795718 ==
3435 12:11:34.798895 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 12:11:34.802333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 12:11:34.802454 ==
3438 12:11:34.805722 Write leveling (Byte 0): 28 => 28
3439 12:11:34.809074 Write leveling (Byte 1): 28 => 28
3440 12:11:34.812564 DramcWriteLeveling(PI) end<-----
3441 12:11:34.812653
3442 12:11:34.812739 ==
3443 12:11:34.816069 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 12:11:34.818812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 12:11:34.822255 ==
3446 12:11:34.822342 [Gating] SW mode calibration
3447 12:11:34.828955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3448 12:11:34.835618 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3449 12:11:34.838876 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 12:11:34.845588 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 12:11:34.848958 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 12:11:34.852328 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 12:11:34.858998 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 12:11:34.862358 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3455 12:11:34.865730 0 15 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 0) (1 1)
3456 12:11:34.872722 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3457 12:11:34.875873 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 12:11:34.879232 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 12:11:34.882713 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 12:11:34.889659 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 12:11:34.892366 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 12:11:34.895803 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3463 12:11:34.902614 1 0 24 | B1->B0 | 4141 2727 | 0 0 | (1 1) (0 0)
3464 12:11:34.906024 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3465 12:11:34.909541 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 12:11:34.916152 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 12:11:34.919530 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 12:11:34.922993 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 12:11:34.929139 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 12:11:34.932566 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3471 12:11:34.935810 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3472 12:11:34.942877 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3473 12:11:34.945561 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:11:34.948867 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:11:34.956040 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:11:34.958721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:11:34.961986 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:11:34.968758 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:11:34.972088 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:11:34.975824 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:11:34.982386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:11:34.985635 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:11:34.989077 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:11:34.995804 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:11:34.998638 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:11:35.002081 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3487 12:11:35.005525 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3488 12:11:35.012509 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3489 12:11:35.015904 Total UI for P1: 0, mck2ui 16
3490 12:11:35.018655 best dqsien dly found for B1: ( 1, 3, 22)
3491 12:11:35.022117 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 12:11:35.025652 Total UI for P1: 0, mck2ui 16
3493 12:11:35.028943 best dqsien dly found for B0: ( 1, 3, 26)
3494 12:11:35.032473 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3495 12:11:35.035254 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3496 12:11:35.035351
3497 12:11:35.038605 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3498 12:11:35.041851 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3499 12:11:35.045664 [Gating] SW calibration Done
3500 12:11:35.045749 ==
3501 12:11:35.048814 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 12:11:35.055358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 12:11:35.055450 ==
3504 12:11:35.055520 RX Vref Scan: 0
3505 12:11:35.055586
3506 12:11:35.058634 RX Vref 0 -> 0, step: 1
3507 12:11:35.058753
3508 12:11:35.061811 RX Delay -40 -> 252, step: 8
3509 12:11:35.065161 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3510 12:11:35.068575 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3511 12:11:35.071984 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3512 12:11:35.075399 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3513 12:11:35.082044 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3514 12:11:35.085230 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3515 12:11:35.088352 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3516 12:11:35.092350 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3517 12:11:35.095540 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3518 12:11:35.102205 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3519 12:11:35.105010 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3520 12:11:35.108493 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3521 12:11:35.111790 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3522 12:11:35.115251 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3523 12:11:35.122162 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3524 12:11:35.125535 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3525 12:11:35.125637 ==
3526 12:11:35.128907 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 12:11:35.131632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 12:11:35.131734 ==
3529 12:11:35.135055 DQS Delay:
3530 12:11:35.135162 DQS0 = 0, DQS1 = 0
3531 12:11:35.135259 DQM Delay:
3532 12:11:35.138480 DQM0 = 121, DQM1 = 119
3533 12:11:35.138562 DQ Delay:
3534 12:11:35.141888 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3535 12:11:35.145477 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3536 12:11:35.148971 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3537 12:11:35.155499 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3538 12:11:35.155602
3539 12:11:35.155672
3540 12:11:35.155734 ==
3541 12:11:35.158616 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 12:11:35.161917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 12:11:35.162020 ==
3544 12:11:35.162117
3545 12:11:35.162206
3546 12:11:35.165134 TX Vref Scan disable
3547 12:11:35.165244 == TX Byte 0 ==
3548 12:11:35.171756 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3549 12:11:35.174918 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3550 12:11:35.175003 == TX Byte 1 ==
3551 12:11:35.181706 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3552 12:11:35.185107 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3553 12:11:35.185192 ==
3554 12:11:35.188555 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 12:11:35.191642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 12:11:35.191733 ==
3557 12:11:35.204491 TX Vref=22, minBit 1, minWin=25, winSum=415
3558 12:11:35.207725 TX Vref=24, minBit 1, minWin=26, winSum=424
3559 12:11:35.211115 TX Vref=26, minBit 2, minWin=26, winSum=431
3560 12:11:35.214491 TX Vref=28, minBit 9, minWin=26, winSum=430
3561 12:11:35.218018 TX Vref=30, minBit 1, minWin=26, winSum=432
3562 12:11:35.221420 TX Vref=32, minBit 1, minWin=26, winSum=426
3563 12:11:35.227581 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3564 12:11:35.227663
3565 12:11:35.230992 Final TX Range 1 Vref 30
3566 12:11:35.231075
3567 12:11:35.231157 ==
3568 12:11:35.234295 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 12:11:35.237790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 12:11:35.237872 ==
3571 12:11:35.241388
3572 12:11:35.241463
3573 12:11:35.241526 TX Vref Scan disable
3574 12:11:35.244081 == TX Byte 0 ==
3575 12:11:35.247468 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3576 12:11:35.250903 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3577 12:11:35.254309 == TX Byte 1 ==
3578 12:11:35.257643 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 12:11:35.260981 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 12:11:35.264201
3581 12:11:35.264290 [DATLAT]
3582 12:11:35.264356 Freq=1200, CH1 RK1
3583 12:11:35.264426
3584 12:11:35.267465 DATLAT Default: 0xd
3585 12:11:35.267544 0, 0xFFFF, sum = 0
3586 12:11:35.270680 1, 0xFFFF, sum = 0
3587 12:11:35.270766 2, 0xFFFF, sum = 0
3588 12:11:35.274033 3, 0xFFFF, sum = 0
3589 12:11:35.277301 4, 0xFFFF, sum = 0
3590 12:11:35.277384 5, 0xFFFF, sum = 0
3591 12:11:35.280524 6, 0xFFFF, sum = 0
3592 12:11:35.280606 7, 0xFFFF, sum = 0
3593 12:11:35.283722 8, 0xFFFF, sum = 0
3594 12:11:35.283807 9, 0xFFFF, sum = 0
3595 12:11:35.287123 10, 0xFFFF, sum = 0
3596 12:11:35.287244 11, 0xFFFF, sum = 0
3597 12:11:35.290576 12, 0x0, sum = 1
3598 12:11:35.290651 13, 0x0, sum = 2
3599 12:11:35.294031 14, 0x0, sum = 3
3600 12:11:35.294110 15, 0x0, sum = 4
3601 12:11:35.297450 best_step = 13
3602 12:11:35.297561
3603 12:11:35.297635 ==
3604 12:11:35.300653 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 12:11:35.303815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 12:11:35.303895 ==
3607 12:11:35.303963 RX Vref Scan: 0
3608 12:11:35.304026
3609 12:11:35.306927 RX Vref 0 -> 0, step: 1
3610 12:11:35.307009
3611 12:11:35.310845 RX Delay -5 -> 252, step: 4
3612 12:11:35.314215 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3613 12:11:35.320524 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3614 12:11:35.323899 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3615 12:11:35.327287 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3616 12:11:35.330697 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3617 12:11:35.333549 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3618 12:11:35.340408 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3619 12:11:35.343880 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3620 12:11:35.347292 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3621 12:11:35.350038 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3622 12:11:35.353497 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3623 12:11:35.360441 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3624 12:11:35.363198 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3625 12:11:35.367179 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3626 12:11:35.370591 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3627 12:11:35.373218 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3628 12:11:35.377098 ==
3629 12:11:35.380348 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 12:11:35.383675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 12:11:35.383757 ==
3632 12:11:35.383831 DQS Delay:
3633 12:11:35.386911 DQS0 = 0, DQS1 = 0
3634 12:11:35.386985 DQM Delay:
3635 12:11:35.390206 DQM0 = 120, DQM1 = 117
3636 12:11:35.390282 DQ Delay:
3637 12:11:35.393464 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3638 12:11:35.396875 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3639 12:11:35.400337 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3640 12:11:35.403791 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =126
3641 12:11:35.403869
3642 12:11:35.403938
3643 12:11:35.413471 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3644 12:11:35.416566 CH1 RK1: MR19=403, MR18=13F0
3645 12:11:35.420454 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3646 12:11:35.423803 [RxdqsGatingPostProcess] freq 1200
3647 12:11:35.430121 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3648 12:11:35.433447 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 12:11:35.436685 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 12:11:35.440080 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 12:11:35.443510 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 12:11:35.446958 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 12:11:35.449761 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 12:11:35.453119 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 12:11:35.456638 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 12:11:35.460013 Pre-setting of DQS Precalculation
3657 12:11:35.463444 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3658 12:11:35.470225 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3659 12:11:35.476272 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3660 12:11:35.476351
3661 12:11:35.479741
3662 12:11:35.479820 [Calibration Summary] 2400 Mbps
3663 12:11:35.482819 CH 0, Rank 0
3664 12:11:35.482903 SW Impedance : PASS
3665 12:11:35.486749 DUTY Scan : NO K
3666 12:11:35.490045 ZQ Calibration : PASS
3667 12:11:35.490128 Jitter Meter : NO K
3668 12:11:35.493397 CBT Training : PASS
3669 12:11:35.496648 Write leveling : PASS
3670 12:11:35.496765 RX DQS gating : PASS
3671 12:11:35.499894 RX DQ/DQS(RDDQC) : PASS
3672 12:11:35.503292 TX DQ/DQS : PASS
3673 12:11:35.503395 RX DATLAT : PASS
3674 12:11:35.506756 RX DQ/DQS(Engine): PASS
3675 12:11:35.506830 TX OE : NO K
3676 12:11:35.509602 All Pass.
3677 12:11:35.509674
3678 12:11:35.509737 CH 0, Rank 1
3679 12:11:35.512990 SW Impedance : PASS
3680 12:11:35.513067 DUTY Scan : NO K
3681 12:11:35.516153 ZQ Calibration : PASS
3682 12:11:35.519956 Jitter Meter : NO K
3683 12:11:35.520061 CBT Training : PASS
3684 12:11:35.523355 Write leveling : PASS
3685 12:11:35.526373 RX DQS gating : PASS
3686 12:11:35.526455 RX DQ/DQS(RDDQC) : PASS
3687 12:11:35.529552 TX DQ/DQS : PASS
3688 12:11:35.532811 RX DATLAT : PASS
3689 12:11:35.532895 RX DQ/DQS(Engine): PASS
3690 12:11:35.536004 TX OE : NO K
3691 12:11:35.536114 All Pass.
3692 12:11:35.536218
3693 12:11:35.539301 CH 1, Rank 0
3694 12:11:35.539412 SW Impedance : PASS
3695 12:11:35.542624 DUTY Scan : NO K
3696 12:11:35.546098 ZQ Calibration : PASS
3697 12:11:35.546178 Jitter Meter : NO K
3698 12:11:35.549592 CBT Training : PASS
3699 12:11:35.552984 Write leveling : PASS
3700 12:11:35.553059 RX DQS gating : PASS
3701 12:11:35.556341 RX DQ/DQS(RDDQC) : PASS
3702 12:11:35.559124 TX DQ/DQS : PASS
3703 12:11:35.559226 RX DATLAT : PASS
3704 12:11:35.562600 RX DQ/DQS(Engine): PASS
3705 12:11:35.566087 TX OE : NO K
3706 12:11:35.566160 All Pass.
3707 12:11:35.566224
3708 12:11:35.566289 CH 1, Rank 1
3709 12:11:35.569602 SW Impedance : PASS
3710 12:11:35.572314 DUTY Scan : NO K
3711 12:11:35.572387 ZQ Calibration : PASS
3712 12:11:35.575627 Jitter Meter : NO K
3713 12:11:35.575699 CBT Training : PASS
3714 12:11:35.579097 Write leveling : PASS
3715 12:11:35.582594 RX DQS gating : PASS
3716 12:11:35.582675 RX DQ/DQS(RDDQC) : PASS
3717 12:11:35.586034 TX DQ/DQS : PASS
3718 12:11:35.589237 RX DATLAT : PASS
3719 12:11:35.589312 RX DQ/DQS(Engine): PASS
3720 12:11:35.592536 TX OE : NO K
3721 12:11:35.592616 All Pass.
3722 12:11:35.592682
3723 12:11:35.595922 DramC Write-DBI off
3724 12:11:35.599155 PER_BANK_REFRESH: Hybrid Mode
3725 12:11:35.599263 TX_TRACKING: ON
3726 12:11:35.608966 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3727 12:11:35.612550 [FAST_K] Save calibration result to emmc
3728 12:11:35.615973 dramc_set_vcore_voltage set vcore to 650000
3729 12:11:35.619317 Read voltage for 600, 5
3730 12:11:35.619413 Vio18 = 0
3731 12:11:35.619479 Vcore = 650000
3732 12:11:35.622635 Vdram = 0
3733 12:11:35.622713 Vddq = 0
3734 12:11:35.622777 Vmddr = 0
3735 12:11:35.629072 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3736 12:11:35.632527 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3737 12:11:35.635765 MEM_TYPE=3, freq_sel=19
3738 12:11:35.638949 sv_algorithm_assistance_LP4_1600
3739 12:11:35.642767 ============ PULL DRAM RESETB DOWN ============
3740 12:11:35.646153 ========== PULL DRAM RESETB DOWN end =========
3741 12:11:35.652774 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 12:11:35.655597 ===================================
3743 12:11:35.655679 LPDDR4 DRAM CONFIGURATION
3744 12:11:35.659557 ===================================
3745 12:11:35.662273 EX_ROW_EN[0] = 0x0
3746 12:11:35.665703 EX_ROW_EN[1] = 0x0
3747 12:11:35.665780 LP4Y_EN = 0x0
3748 12:11:35.669065 WORK_FSP = 0x0
3749 12:11:35.669137 WL = 0x2
3750 12:11:35.672359 RL = 0x2
3751 12:11:35.672438 BL = 0x2
3752 12:11:35.675798 RPST = 0x0
3753 12:11:35.675869 RD_PRE = 0x0
3754 12:11:35.679121 WR_PRE = 0x1
3755 12:11:35.679222 WR_PST = 0x0
3756 12:11:35.682571 DBI_WR = 0x0
3757 12:11:35.682657 DBI_RD = 0x0
3758 12:11:35.685848 OTF = 0x1
3759 12:11:35.689263 ===================================
3760 12:11:35.692616 ===================================
3761 12:11:35.692691 ANA top config
3762 12:11:35.695897 ===================================
3763 12:11:35.698999 DLL_ASYNC_EN = 0
3764 12:11:35.702315 ALL_SLAVE_EN = 1
3765 12:11:35.705504 NEW_RANK_MODE = 1
3766 12:11:35.705586 DLL_IDLE_MODE = 1
3767 12:11:35.709321 LP45_APHY_COMB_EN = 1
3768 12:11:35.712532 TX_ODT_DIS = 1
3769 12:11:35.715969 NEW_8X_MODE = 1
3770 12:11:35.719461 ===================================
3771 12:11:35.722229 ===================================
3772 12:11:35.725679 data_rate = 1200
3773 12:11:35.725754 CKR = 1
3774 12:11:35.729097 DQ_P2S_RATIO = 8
3775 12:11:35.732388 ===================================
3776 12:11:35.735608 CA_P2S_RATIO = 8
3777 12:11:35.738852 DQ_CA_OPEN = 0
3778 12:11:35.742248 DQ_SEMI_OPEN = 0
3779 12:11:35.742326 CA_SEMI_OPEN = 0
3780 12:11:35.745555 CA_FULL_RATE = 0
3781 12:11:35.748851 DQ_CKDIV4_EN = 1
3782 12:11:35.752063 CA_CKDIV4_EN = 1
3783 12:11:35.756138 CA_PREDIV_EN = 0
3784 12:11:35.758910 PH8_DLY = 0
3785 12:11:35.759009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3786 12:11:35.762324 DQ_AAMCK_DIV = 4
3787 12:11:35.765716 CA_AAMCK_DIV = 4
3788 12:11:35.769113 CA_ADMCK_DIV = 4
3789 12:11:35.772473 DQ_TRACK_CA_EN = 0
3790 12:11:35.775799 CA_PICK = 600
3791 12:11:35.779220 CA_MCKIO = 600
3792 12:11:35.779329 MCKIO_SEMI = 0
3793 12:11:35.782474 PLL_FREQ = 2288
3794 12:11:35.785886 DQ_UI_PI_RATIO = 32
3795 12:11:35.789431 CA_UI_PI_RATIO = 0
3796 12:11:35.792761 ===================================
3797 12:11:35.795562 ===================================
3798 12:11:35.798986 memory_type:LPDDR4
3799 12:11:35.799100 GP_NUM : 10
3800 12:11:35.802386 SRAM_EN : 1
3801 12:11:35.802490 MD32_EN : 0
3802 12:11:35.805764 ===================================
3803 12:11:35.809078 [ANA_INIT] >>>>>>>>>>>>>>
3804 12:11:35.812365 <<<<<< [CONFIGURE PHASE]: ANA_TX
3805 12:11:35.815639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3806 12:11:35.818879 ===================================
3807 12:11:35.822107 data_rate = 1200,PCW = 0X5800
3808 12:11:35.825584 ===================================
3809 12:11:35.829207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3810 12:11:35.835826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 12:11:35.838915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 12:11:35.845672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3813 12:11:35.849037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3814 12:11:35.852510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3815 12:11:35.852613 [ANA_INIT] flow start
3816 12:11:35.855707 [ANA_INIT] PLL >>>>>>>>
3817 12:11:35.858904 [ANA_INIT] PLL <<<<<<<<
3818 12:11:35.859011 [ANA_INIT] MIDPI >>>>>>>>
3819 12:11:35.862220 [ANA_INIT] MIDPI <<<<<<<<
3820 12:11:35.865726 [ANA_INIT] DLL >>>>>>>>
3821 12:11:35.865833 [ANA_INIT] flow end
3822 12:11:35.872448 ============ LP4 DIFF to SE enter ============
3823 12:11:35.875882 ============ LP4 DIFF to SE exit ============
3824 12:11:35.878538 [ANA_INIT] <<<<<<<<<<<<<
3825 12:11:35.881967 [Flow] Enable top DCM control >>>>>
3826 12:11:35.885406 [Flow] Enable top DCM control <<<<<
3827 12:11:35.885514 Enable DLL master slave shuffle
3828 12:11:35.892120 ==============================================================
3829 12:11:35.895483 Gating Mode config
3830 12:11:35.899007 ==============================================================
3831 12:11:35.901791 Config description:
3832 12:11:35.911787 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3833 12:11:35.918246 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3834 12:11:35.921634 SELPH_MODE 0: By rank 1: By Phase
3835 12:11:35.928755 ==============================================================
3836 12:11:35.931942 GAT_TRACK_EN = 1
3837 12:11:35.935286 RX_GATING_MODE = 2
3838 12:11:35.938554 RX_GATING_TRACK_MODE = 2
3839 12:11:35.941946 SELPH_MODE = 1
3840 12:11:35.942054 PICG_EARLY_EN = 1
3841 12:11:35.945047 VALID_LAT_VALUE = 1
3842 12:11:35.951960 ==============================================================
3843 12:11:35.955412 Enter into Gating configuration >>>>
3844 12:11:35.958132 Exit from Gating configuration <<<<
3845 12:11:35.961424 Enter into DVFS_PRE_config >>>>>
3846 12:11:35.971950 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3847 12:11:35.974670 Exit from DVFS_PRE_config <<<<<
3848 12:11:35.978119 Enter into PICG configuration >>>>
3849 12:11:35.981560 Exit from PICG configuration <<<<
3850 12:11:35.985077 [RX_INPUT] configuration >>>>>
3851 12:11:35.988521 [RX_INPUT] configuration <<<<<
3852 12:11:35.991768 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3853 12:11:35.998691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3854 12:11:36.005021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 12:11:36.012019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 12:11:36.015195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 12:11:36.021719 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 12:11:36.024878 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3859 12:11:36.031964 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3860 12:11:36.035198 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3861 12:11:36.038578 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3862 12:11:36.041829 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3863 12:11:36.048335 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 12:11:36.051602 ===================================
3865 12:11:36.051681 LPDDR4 DRAM CONFIGURATION
3866 12:11:36.055024 ===================================
3867 12:11:36.058475 EX_ROW_EN[0] = 0x0
3868 12:11:36.061309 EX_ROW_EN[1] = 0x0
3869 12:11:36.061394 LP4Y_EN = 0x0
3870 12:11:36.064801 WORK_FSP = 0x0
3871 12:11:36.064886 WL = 0x2
3872 12:11:36.068121 RL = 0x2
3873 12:11:36.068206 BL = 0x2
3874 12:11:36.071416 RPST = 0x0
3875 12:11:36.071511 RD_PRE = 0x0
3876 12:11:36.075169 WR_PRE = 0x1
3877 12:11:36.075253 WR_PST = 0x0
3878 12:11:36.078432 DBI_WR = 0x0
3879 12:11:36.078516 DBI_RD = 0x0
3880 12:11:36.081824 OTF = 0x1
3881 12:11:36.084630 ===================================
3882 12:11:36.087999 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3883 12:11:36.091391 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3884 12:11:36.098039 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 12:11:36.101494 ===================================
3886 12:11:36.101581 LPDDR4 DRAM CONFIGURATION
3887 12:11:36.104819 ===================================
3888 12:11:36.108303 EX_ROW_EN[0] = 0x10
3889 12:11:36.111693 EX_ROW_EN[1] = 0x0
3890 12:11:36.111777 LP4Y_EN = 0x0
3891 12:11:36.114359 WORK_FSP = 0x0
3892 12:11:36.114468 WL = 0x2
3893 12:11:36.117736 RL = 0x2
3894 12:11:36.117820 BL = 0x2
3895 12:11:36.121229 RPST = 0x0
3896 12:11:36.121339 RD_PRE = 0x0
3897 12:11:36.124592 WR_PRE = 0x1
3898 12:11:36.124703 WR_PST = 0x0
3899 12:11:36.128004 DBI_WR = 0x0
3900 12:11:36.128088 DBI_RD = 0x0
3901 12:11:36.131260 OTF = 0x1
3902 12:11:36.134566 ===================================
3903 12:11:36.140973 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3904 12:11:36.144275 nWR fixed to 30
3905 12:11:36.148118 [ModeRegInit_LP4] CH0 RK0
3906 12:11:36.148203 [ModeRegInit_LP4] CH0 RK1
3907 12:11:36.151456 [ModeRegInit_LP4] CH1 RK0
3908 12:11:36.154602 [ModeRegInit_LP4] CH1 RK1
3909 12:11:36.154686 match AC timing 17
3910 12:11:36.160934 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3911 12:11:36.164346 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3912 12:11:36.167747 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3913 12:11:36.174584 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3914 12:11:36.177926 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3915 12:11:36.178036 ==
3916 12:11:36.181201 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 12:11:36.184736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 12:11:36.184836 ==
3919 12:11:36.191140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 12:11:36.197461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3921 12:11:36.201203 [CA 0] Center 35 (5~66) winsize 62
3922 12:11:36.204683 [CA 1] Center 35 (5~66) winsize 62
3923 12:11:36.207291 [CA 2] Center 33 (3~64) winsize 62
3924 12:11:36.210648 [CA 3] Center 33 (2~64) winsize 63
3925 12:11:36.214131 [CA 4] Center 33 (2~64) winsize 63
3926 12:11:36.217597 [CA 5] Center 32 (2~63) winsize 62
3927 12:11:36.217691
3928 12:11:36.220894 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3929 12:11:36.220981
3930 12:11:36.224201 [CATrainingPosCal] consider 1 rank data
3931 12:11:36.227621 u2DelayCellTimex100 = 270/100 ps
3932 12:11:36.231080 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3933 12:11:36.234482 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3934 12:11:36.237810 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3935 12:11:36.240498 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3936 12:11:36.244567 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3937 12:11:36.246968 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3938 12:11:36.247077
3939 12:11:36.254056 CA PerBit enable=1, Macro0, CA PI delay=32
3940 12:11:36.254168
3941 12:11:36.254277 [CBTSetCACLKResult] CA Dly = 32
3942 12:11:36.257328 CS Dly: 3 (0~34)
3943 12:11:36.257440 ==
3944 12:11:36.260527 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 12:11:36.263758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 12:11:36.263869 ==
3947 12:11:36.270795 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 12:11:36.277058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3949 12:11:36.280504 [CA 0] Center 35 (5~66) winsize 62
3950 12:11:36.283922 [CA 1] Center 35 (5~66) winsize 62
3951 12:11:36.287233 [CA 2] Center 34 (3~65) winsize 63
3952 12:11:36.290535 [CA 3] Center 33 (3~64) winsize 62
3953 12:11:36.293848 [CA 4] Center 33 (2~64) winsize 63
3954 12:11:36.297181 [CA 5] Center 32 (2~63) winsize 62
3955 12:11:36.297286
3956 12:11:36.300676 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3957 12:11:36.300790
3958 12:11:36.303417 [CATrainingPosCal] consider 2 rank data
3959 12:11:36.306691 u2DelayCellTimex100 = 270/100 ps
3960 12:11:36.310037 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3961 12:11:36.313494 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3962 12:11:36.316876 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3963 12:11:36.320367 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3964 12:11:36.323593 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3965 12:11:36.330502 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3966 12:11:36.330639
3967 12:11:36.333895 CA PerBit enable=1, Macro0, CA PI delay=32
3968 12:11:36.334010
3969 12:11:36.336551 [CBTSetCACLKResult] CA Dly = 32
3970 12:11:36.336662 CS Dly: 4 (0~36)
3971 12:11:36.336757
3972 12:11:36.340085 ----->DramcWriteLeveling(PI) begin...
3973 12:11:36.340197 ==
3974 12:11:36.343355 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 12:11:36.350128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 12:11:36.350279 ==
3977 12:11:36.353463 Write leveling (Byte 0): 36 => 36
3978 12:11:36.353572 Write leveling (Byte 1): 32 => 32
3979 12:11:36.356665 DramcWriteLeveling(PI) end<-----
3980 12:11:36.356782
3981 12:11:36.356879 ==
3982 12:11:36.359785 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 12:11:36.366799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 12:11:36.366911 ==
3985 12:11:36.369974 [Gating] SW mode calibration
3986 12:11:36.376400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 12:11:36.379702 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3988 12:11:36.386579 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 12:11:36.389830 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 12:11:36.393118 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 12:11:36.399977 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
3992 12:11:36.403216 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3993 12:11:36.406575 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 12:11:36.413430 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 12:11:36.416143 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 12:11:36.419540 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 12:11:36.426319 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 12:11:36.429764 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 12:11:36.433179 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4000 12:11:36.436618 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4001 12:11:36.442726 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 12:11:36.446612 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:11:36.449290 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 12:11:36.456023 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:11:36.459510 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 12:11:36.462725 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 12:11:36.469816 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4008 12:11:36.472980 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:11:36.476214 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:11:36.482854 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:11:36.486045 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:11:36.489450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:11:36.496167 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:11:36.499518 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:11:36.502830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:11:36.509449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:11:36.512717 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:11:36.516137 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:11:36.522807 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:11:36.526173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:11:36.529694 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:11:36.535860 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:11:36.539345 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4024 12:11:36.542625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:11:36.545924 Total UI for P1: 0, mck2ui 16
4026 12:11:36.549295 best dqsien dly found for B0: ( 0, 13, 12)
4027 12:11:36.552649 Total UI for P1: 0, mck2ui 16
4028 12:11:36.556035 best dqsien dly found for B1: ( 0, 13, 14)
4029 12:11:36.559534 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4030 12:11:36.562931 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4031 12:11:36.563040
4032 12:11:36.566367 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4033 12:11:36.572419 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4034 12:11:36.572527 [Gating] SW calibration Done
4035 12:11:36.572623 ==
4036 12:11:36.575886 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 12:11:36.582504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 12:11:36.582610 ==
4039 12:11:36.582707 RX Vref Scan: 0
4040 12:11:36.582799
4041 12:11:36.586330 RX Vref 0 -> 0, step: 1
4042 12:11:36.586408
4043 12:11:36.589685 RX Delay -230 -> 252, step: 16
4044 12:11:36.592970 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4045 12:11:36.596255 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4046 12:11:36.599642 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4047 12:11:36.606359 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4048 12:11:36.609074 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4049 12:11:36.612535 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4050 12:11:36.615799 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4051 12:11:36.622715 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4052 12:11:36.625891 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4053 12:11:36.629364 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4054 12:11:36.632201 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4055 12:11:36.639072 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4056 12:11:36.642426 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4057 12:11:36.645906 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4058 12:11:36.649126 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4059 12:11:36.652555 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4060 12:11:36.655924 ==
4061 12:11:36.659394 Dram Type= 6, Freq= 0, CH_0, rank 0
4062 12:11:36.662132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4063 12:11:36.662241 ==
4064 12:11:36.662335 DQS Delay:
4065 12:11:36.665532 DQS0 = 0, DQS1 = 0
4066 12:11:36.665639 DQM Delay:
4067 12:11:36.669016 DQM0 = 53, DQM1 = 47
4068 12:11:36.669114 DQ Delay:
4069 12:11:36.672271 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4070 12:11:36.675581 DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =57
4071 12:11:36.678941 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4072 12:11:36.682405 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4073 12:11:36.682488
4074 12:11:36.682554
4075 12:11:36.682617 ==
4076 12:11:36.685699 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 12:11:36.688847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 12:11:36.688923 ==
4079 12:11:36.688987
4080 12:11:36.689048
4081 12:11:36.692660 TX Vref Scan disable
4082 12:11:36.695386 == TX Byte 0 ==
4083 12:11:36.698757 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4084 12:11:36.702607 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4085 12:11:36.705846 == TX Byte 1 ==
4086 12:11:36.708517 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4087 12:11:36.712020 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4088 12:11:36.712129 ==
4089 12:11:36.715422 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 12:11:36.722217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 12:11:36.722334 ==
4092 12:11:36.722434
4093 12:11:36.722530
4094 12:11:36.722634 TX Vref Scan disable
4095 12:11:36.726132 == TX Byte 0 ==
4096 12:11:36.730062 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4097 12:11:36.736666 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4098 12:11:36.736779 == TX Byte 1 ==
4099 12:11:36.739415 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4100 12:11:36.746176 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4101 12:11:36.746290
4102 12:11:36.746391 [DATLAT]
4103 12:11:36.746484 Freq=600, CH0 RK0
4104 12:11:36.746577
4105 12:11:36.749509 DATLAT Default: 0x9
4106 12:11:36.749617 0, 0xFFFF, sum = 0
4107 12:11:36.752790 1, 0xFFFF, sum = 0
4108 12:11:36.752903 2, 0xFFFF, sum = 0
4109 12:11:36.756221 3, 0xFFFF, sum = 0
4110 12:11:36.756332 4, 0xFFFF, sum = 0
4111 12:11:36.759642 5, 0xFFFF, sum = 0
4112 12:11:36.762973 6, 0xFFFF, sum = 0
4113 12:11:36.763083 7, 0xFFFF, sum = 0
4114 12:11:36.763181 8, 0x0, sum = 1
4115 12:11:36.766410 9, 0x0, sum = 2
4116 12:11:36.766516 10, 0x0, sum = 3
4117 12:11:36.769781 11, 0x0, sum = 4
4118 12:11:36.769888 best_step = 9
4119 12:11:36.769984
4120 12:11:36.770074 ==
4121 12:11:36.773046 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 12:11:36.779413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 12:11:36.779524 ==
4124 12:11:36.779624 RX Vref Scan: 1
4125 12:11:36.779720
4126 12:11:36.782670 RX Vref 0 -> 0, step: 1
4127 12:11:36.782774
4128 12:11:36.785931 RX Delay -163 -> 252, step: 8
4129 12:11:36.786039
4130 12:11:36.789278 Set Vref, RX VrefLevel [Byte0]: 55
4131 12:11:36.792644 [Byte1]: 48
4132 12:11:36.792746
4133 12:11:36.795937 Final RX Vref Byte 0 = 55 to rank0
4134 12:11:36.799191 Final RX Vref Byte 1 = 48 to rank0
4135 12:11:36.802385 Final RX Vref Byte 0 = 55 to rank1
4136 12:11:36.806195 Final RX Vref Byte 1 = 48 to rank1==
4137 12:11:36.809355 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 12:11:36.812536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 12:11:36.812663 ==
4140 12:11:36.815944 DQS Delay:
4141 12:11:36.816054 DQS0 = 0, DQS1 = 0
4142 12:11:36.816152 DQM Delay:
4143 12:11:36.819400 DQM0 = 53, DQM1 = 46
4144 12:11:36.819520 DQ Delay:
4145 12:11:36.822832 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4146 12:11:36.825578 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =64
4147 12:11:36.828999 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4148 12:11:36.832234 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4149 12:11:36.832390
4150 12:11:36.832496
4151 12:11:36.842894 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4152 12:11:36.845516 CH0 RK0: MR19=808, MR18=6C5F
4153 12:11:36.848991 CH0_RK0: MR19=0x808, MR18=0x6C5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4154 12:11:36.852528
4155 12:11:36.855972 ----->DramcWriteLeveling(PI) begin...
4156 12:11:36.856094 ==
4157 12:11:36.859380 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 12:11:36.862069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 12:11:36.862171 ==
4160 12:11:36.865519 Write leveling (Byte 0): 34 => 34
4161 12:11:36.868955 Write leveling (Byte 1): 30 => 30
4162 12:11:36.872174 DramcWriteLeveling(PI) end<-----
4163 12:11:36.872294
4164 12:11:36.872390 ==
4165 12:11:36.875588 Dram Type= 6, Freq= 0, CH_0, rank 1
4166 12:11:36.879118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 12:11:36.879283 ==
4168 12:11:36.882587 [Gating] SW mode calibration
4169 12:11:36.889154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4170 12:11:36.895418 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4171 12:11:36.898795 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 12:11:36.902206 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 12:11:36.908649 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 12:11:36.912624 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4175 12:11:36.915772 0 9 16 | B1->B0 | 2929 2828 | 0 0 | (0 0) (1 1)
4176 12:11:36.918537 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 12:11:36.926024 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 12:11:36.928683 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 12:11:36.932141 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 12:11:36.938474 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 12:11:36.941742 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 12:11:36.945104 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4183 12:11:36.952107 0 10 16 | B1->B0 | 3a3a 4141 | 1 0 | (0 0) (0 0)
4184 12:11:36.955614 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 12:11:36.958979 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 12:11:36.965171 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 12:11:36.968595 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 12:11:36.971863 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 12:11:36.978874 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 12:11:36.982217 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:11:36.984991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:11:36.991645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:11:36.994942 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:11:36.998334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:11:37.005380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:11:37.008795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:11:37.011979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:11:37.018613 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:11:37.021781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:11:37.025206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:11:37.031974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:11:37.035350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:11:37.038086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:11:37.044824 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:11:37.048067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:11:37.051402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4207 12:11:37.058519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 12:11:37.058605 Total UI for P1: 0, mck2ui 16
4209 12:11:37.064616 best dqsien dly found for B0: ( 0, 13, 12)
4210 12:11:37.064706 Total UI for P1: 0, mck2ui 16
4211 12:11:37.068035 best dqsien dly found for B1: ( 0, 13, 14)
4212 12:11:37.075007 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4213 12:11:37.078566 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4214 12:11:37.078657
4215 12:11:37.081826 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4216 12:11:37.084477 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4217 12:11:37.087964 [Gating] SW calibration Done
4218 12:11:37.088046 ==
4219 12:11:37.091443 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 12:11:37.094770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 12:11:37.094843 ==
4222 12:11:37.098017 RX Vref Scan: 0
4223 12:11:37.098125
4224 12:11:37.098218 RX Vref 0 -> 0, step: 1
4225 12:11:37.098308
4226 12:11:37.101314 RX Delay -230 -> 252, step: 16
4227 12:11:37.104720 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4228 12:11:37.111620 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4229 12:11:37.115026 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4230 12:11:37.118366 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4231 12:11:37.121536 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4232 12:11:37.124812 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4233 12:11:37.131257 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4234 12:11:37.135072 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4235 12:11:37.137904 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4236 12:11:37.141401 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4237 12:11:37.148280 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4238 12:11:37.151517 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4239 12:11:37.154700 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4240 12:11:37.158136 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4241 12:11:37.164758 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4242 12:11:37.168072 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4243 12:11:37.168151 ==
4244 12:11:37.171581 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 12:11:37.174959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 12:11:37.175043 ==
4247 12:11:37.178277 DQS Delay:
4248 12:11:37.178386 DQS0 = 0, DQS1 = 0
4249 12:11:37.178480 DQM Delay:
4250 12:11:37.181586 DQM0 = 52, DQM1 = 43
4251 12:11:37.181670 DQ Delay:
4252 12:11:37.184417 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4253 12:11:37.187746 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4254 12:11:37.191084 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4255 12:11:37.194553 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4256 12:11:37.194681
4257 12:11:37.194802
4258 12:11:37.194901 ==
4259 12:11:37.197994 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 12:11:37.204624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 12:11:37.204737 ==
4262 12:11:37.204817
4263 12:11:37.204889
4264 12:11:37.204949 TX Vref Scan disable
4265 12:11:37.207891 == TX Byte 0 ==
4266 12:11:37.211195 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4267 12:11:37.218045 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4268 12:11:37.218161 == TX Byte 1 ==
4269 12:11:37.221533 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4270 12:11:37.228090 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4271 12:11:37.228177 ==
4272 12:11:37.231498 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 12:11:37.234744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 12:11:37.234839 ==
4275 12:11:37.234912
4276 12:11:37.234980
4277 12:11:37.238002 TX Vref Scan disable
4278 12:11:37.241321 == TX Byte 0 ==
4279 12:11:37.244825 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4280 12:11:37.247581 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4281 12:11:37.251031 == TX Byte 1 ==
4282 12:11:37.254468 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4283 12:11:37.257860 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4284 12:11:37.257958
4285 12:11:37.258028 [DATLAT]
4286 12:11:37.261190 Freq=600, CH0 RK1
4287 12:11:37.261277
4288 12:11:37.264607 DATLAT Default: 0x9
4289 12:11:37.264695 0, 0xFFFF, sum = 0
4290 12:11:37.267973 1, 0xFFFF, sum = 0
4291 12:11:37.268059 2, 0xFFFF, sum = 0
4292 12:11:37.271241 3, 0xFFFF, sum = 0
4293 12:11:37.271362 4, 0xFFFF, sum = 0
4294 12:11:37.274573 5, 0xFFFF, sum = 0
4295 12:11:37.274667 6, 0xFFFF, sum = 0
4296 12:11:37.277884 7, 0xFFFF, sum = 0
4297 12:11:37.277986 8, 0x0, sum = 1
4298 12:11:37.281151 9, 0x0, sum = 2
4299 12:11:37.281245 10, 0x0, sum = 3
4300 12:11:37.281314 11, 0x0, sum = 4
4301 12:11:37.284565 best_step = 9
4302 12:11:37.284646
4303 12:11:37.284715 ==
4304 12:11:37.287962 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 12:11:37.291189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 12:11:37.291297 ==
4307 12:11:37.294588 RX Vref Scan: 0
4308 12:11:37.294669
4309 12:11:37.294742 RX Vref 0 -> 0, step: 1
4310 12:11:37.294836
4311 12:11:37.298010 RX Delay -163 -> 252, step: 8
4312 12:11:37.304922 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4313 12:11:37.308265 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4314 12:11:37.311493 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4315 12:11:37.314836 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4316 12:11:37.318273 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4317 12:11:37.324676 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4318 12:11:37.328016 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4319 12:11:37.331779 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4320 12:11:37.335088 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4321 12:11:37.341525 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4322 12:11:37.344703 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4323 12:11:37.348176 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4324 12:11:37.351581 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4325 12:11:37.354894 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4326 12:11:37.361012 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4327 12:11:37.364881 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4328 12:11:37.364994 ==
4329 12:11:37.367668 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 12:11:37.371128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 12:11:37.371246 ==
4332 12:11:37.374661 DQS Delay:
4333 12:11:37.374767 DQS0 = 0, DQS1 = 0
4334 12:11:37.374859 DQM Delay:
4335 12:11:37.377959 DQM0 = 54, DQM1 = 46
4336 12:11:37.378054 DQ Delay:
4337 12:11:37.381201 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4338 12:11:37.384607 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4339 12:11:37.388153 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4340 12:11:37.391367 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4341 12:11:37.391455
4342 12:11:37.391530
4343 12:11:37.401025 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4344 12:11:37.401156 CH0 RK1: MR19=808, MR18=5F20
4345 12:11:37.407830 CH0_RK1: MR19=0x808, MR18=0x5F20, DQSOSC=391, MR23=63, INC=171, DEC=114
4346 12:11:37.411196 [RxdqsGatingPostProcess] freq 600
4347 12:11:37.417710 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4348 12:11:37.421207 Pre-setting of DQS Precalculation
4349 12:11:37.424694 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4350 12:11:37.424783 ==
4351 12:11:37.428091 Dram Type= 6, Freq= 0, CH_1, rank 0
4352 12:11:37.434212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 12:11:37.434303 ==
4354 12:11:37.437753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4355 12:11:37.444589 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4356 12:11:37.447732 [CA 0] Center 36 (5~67) winsize 63
4357 12:11:37.451025 [CA 1] Center 36 (5~67) winsize 63
4358 12:11:37.454510 [CA 2] Center 34 (4~65) winsize 62
4359 12:11:37.457462 [CA 3] Center 34 (4~65) winsize 62
4360 12:11:37.460862 [CA 4] Center 34 (4~65) winsize 62
4361 12:11:37.464309 [CA 5] Center 33 (3~64) winsize 62
4362 12:11:37.464405
4363 12:11:37.467551 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4364 12:11:37.467631
4365 12:11:37.470565 [CATrainingPosCal] consider 1 rank data
4366 12:11:37.473949 u2DelayCellTimex100 = 270/100 ps
4367 12:11:37.477384 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4368 12:11:37.480756 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4369 12:11:37.487220 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4370 12:11:37.490707 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 12:11:37.494171 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 12:11:37.497716 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4373 12:11:37.497833
4374 12:11:37.501080 CA PerBit enable=1, Macro0, CA PI delay=33
4375 12:11:37.501173
4376 12:11:37.503729 [CBTSetCACLKResult] CA Dly = 33
4377 12:11:37.503859 CS Dly: 6 (0~37)
4378 12:11:37.503946 ==
4379 12:11:37.507142 Dram Type= 6, Freq= 0, CH_1, rank 1
4380 12:11:37.514021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4381 12:11:37.514147 ==
4382 12:11:37.517225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4383 12:11:37.524131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4384 12:11:37.527630 [CA 0] Center 36 (5~67) winsize 63
4385 12:11:37.530937 [CA 1] Center 36 (5~67) winsize 63
4386 12:11:37.534408 [CA 2] Center 35 (4~66) winsize 63
4387 12:11:37.537790 [CA 3] Center 34 (4~65) winsize 62
4388 12:11:37.540526 [CA 4] Center 34 (4~65) winsize 62
4389 12:11:37.544040 [CA 5] Center 34 (3~65) winsize 63
4390 12:11:37.544129
4391 12:11:37.547350 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4392 12:11:37.547455
4393 12:11:37.550800 [CATrainingPosCal] consider 2 rank data
4394 12:11:37.554117 u2DelayCellTimex100 = 270/100 ps
4395 12:11:37.557388 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4396 12:11:37.563856 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4397 12:11:37.567544 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 12:11:37.570798 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 12:11:37.574118 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 12:11:37.577428 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4401 12:11:37.577545
4402 12:11:37.580863 CA PerBit enable=1, Macro0, CA PI delay=33
4403 12:11:37.580946
4404 12:11:37.584216 [CBTSetCACLKResult] CA Dly = 33
4405 12:11:37.584326 CS Dly: 6 (0~37)
4406 12:11:37.587578
4407 12:11:37.590209 ----->DramcWriteLeveling(PI) begin...
4408 12:11:37.590297 ==
4409 12:11:37.594094 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 12:11:37.597444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 12:11:37.597586 ==
4412 12:11:37.600800 Write leveling (Byte 0): 30 => 30
4413 12:11:37.604225 Write leveling (Byte 1): 30 => 30
4414 12:11:37.606942 DramcWriteLeveling(PI) end<-----
4415 12:11:37.607057
4416 12:11:37.607153 ==
4417 12:11:37.610363 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 12:11:37.613699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 12:11:37.613808 ==
4420 12:11:37.617242 [Gating] SW mode calibration
4421 12:11:37.623952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4422 12:11:37.629957 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4423 12:11:37.633471 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 12:11:37.637021 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 12:11:37.643178 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 12:11:37.646816 0 9 12 | B1->B0 | 2f2f 2d2d | 0 1 | (1 0) (0 0)
4427 12:11:37.650295 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 12:11:37.656982 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 12:11:37.660468 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 12:11:37.663702 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 12:11:37.669797 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 12:11:37.673044 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:11:37.676375 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 12:11:37.683520 0 10 12 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
4435 12:11:37.686863 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 12:11:37.690303 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 12:11:37.693066 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 12:11:37.699901 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 12:11:37.703523 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:11:37.706848 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:11:37.713459 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 12:11:37.717016 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4443 12:11:37.719761 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:11:37.726639 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:11:37.729983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:11:37.733502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:11:37.740240 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:11:37.743675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:11:37.747062 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:11:37.753320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:11:37.756488 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:11:37.760019 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:11:37.767112 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:11:37.770316 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:11:37.773484 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:11:37.779843 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:11:37.783312 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4458 12:11:37.786448 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4459 12:11:37.789732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 12:11:37.793028 Total UI for P1: 0, mck2ui 16
4461 12:11:37.796488 best dqsien dly found for B0: ( 0, 13, 10)
4462 12:11:37.799819 Total UI for P1: 0, mck2ui 16
4463 12:11:37.803363 best dqsien dly found for B1: ( 0, 13, 10)
4464 12:11:37.806581 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4465 12:11:37.813073 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4466 12:11:37.813201
4467 12:11:37.816371 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4468 12:11:37.819746 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4469 12:11:37.823125 [Gating] SW calibration Done
4470 12:11:37.823262 ==
4471 12:11:37.826593 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 12:11:37.829491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 12:11:37.829606 ==
4474 12:11:37.832906 RX Vref Scan: 0
4475 12:11:37.832996
4476 12:11:37.833064 RX Vref 0 -> 0, step: 1
4477 12:11:37.833127
4478 12:11:37.836306 RX Delay -230 -> 252, step: 16
4479 12:11:37.839649 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4480 12:11:37.846549 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4481 12:11:37.849368 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4482 12:11:37.852671 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4483 12:11:37.855942 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4484 12:11:37.863100 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4485 12:11:37.865781 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4486 12:11:37.869144 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4487 12:11:37.872611 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4488 12:11:37.875969 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4489 12:11:37.882986 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4490 12:11:37.885951 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4491 12:11:37.889091 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4492 12:11:37.892377 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4493 12:11:37.899032 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4494 12:11:37.902981 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4495 12:11:37.903123 ==
4496 12:11:37.905539 Dram Type= 6, Freq= 0, CH_1, rank 0
4497 12:11:37.909092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 12:11:37.909183 ==
4499 12:11:37.912450 DQS Delay:
4500 12:11:37.912539 DQS0 = 0, DQS1 = 0
4501 12:11:37.912607 DQM Delay:
4502 12:11:37.915666 DQM0 = 50, DQM1 = 50
4503 12:11:37.915753 DQ Delay:
4504 12:11:37.918890 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4505 12:11:37.922795 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41
4506 12:11:37.925630 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4507 12:11:37.928928 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4508 12:11:37.929021
4509 12:11:37.929090
4510 12:11:37.929190 ==
4511 12:11:37.932295 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 12:11:37.935610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 12:11:37.939059 ==
4514 12:11:37.939176
4515 12:11:37.939272
4516 12:11:37.939376 TX Vref Scan disable
4517 12:11:37.942533 == TX Byte 0 ==
4518 12:11:37.946011 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4519 12:11:37.949496 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4520 12:11:37.952766 == TX Byte 1 ==
4521 12:11:37.955569 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 12:11:37.958945 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 12:11:37.962207 ==
4524 12:11:37.966209 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 12:11:37.969437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 12:11:37.969560 ==
4527 12:11:37.969655
4528 12:11:37.969752
4529 12:11:37.972300 TX Vref Scan disable
4530 12:11:37.972424 == TX Byte 0 ==
4531 12:11:37.979199 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4532 12:11:37.982621 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4533 12:11:37.982714 == TX Byte 1 ==
4534 12:11:37.989119 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4535 12:11:37.992393 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4536 12:11:37.992490
4537 12:11:37.992557 [DATLAT]
4538 12:11:37.995517 Freq=600, CH1 RK0
4539 12:11:37.995603
4540 12:11:37.995670 DATLAT Default: 0x9
4541 12:11:37.998744 0, 0xFFFF, sum = 0
4542 12:11:37.998832 1, 0xFFFF, sum = 0
4543 12:11:38.001976 2, 0xFFFF, sum = 0
4544 12:11:38.002067 3, 0xFFFF, sum = 0
4545 12:11:38.005966 4, 0xFFFF, sum = 0
4546 12:11:38.009066 5, 0xFFFF, sum = 0
4547 12:11:38.009189 6, 0xFFFF, sum = 0
4548 12:11:38.012536 7, 0xFFFF, sum = 0
4549 12:11:38.012623 8, 0x0, sum = 1
4550 12:11:38.012691 9, 0x0, sum = 2
4551 12:11:38.015357 10, 0x0, sum = 3
4552 12:11:38.015436 11, 0x0, sum = 4
4553 12:11:38.018736 best_step = 9
4554 12:11:38.018818
4555 12:11:38.018889 ==
4556 12:11:38.021998 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 12:11:38.025194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 12:11:38.025279 ==
4559 12:11:38.029097 RX Vref Scan: 1
4560 12:11:38.029213
4561 12:11:38.029294 RX Vref 0 -> 0, step: 1
4562 12:11:38.029360
4563 12:11:38.031833 RX Delay -163 -> 252, step: 8
4564 12:11:38.031918
4565 12:11:38.035152 Set Vref, RX VrefLevel [Byte0]: 55
4566 12:11:38.038577 [Byte1]: 48
4567 12:11:38.042645
4568 12:11:38.042761 Final RX Vref Byte 0 = 55 to rank0
4569 12:11:38.046070 Final RX Vref Byte 1 = 48 to rank0
4570 12:11:38.049523 Final RX Vref Byte 0 = 55 to rank1
4571 12:11:38.052272 Final RX Vref Byte 1 = 48 to rank1==
4572 12:11:38.055729 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 12:11:38.062432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 12:11:38.062530 ==
4575 12:11:38.062604 DQS Delay:
4576 12:11:38.062668 DQS0 = 0, DQS1 = 0
4577 12:11:38.065862 DQM Delay:
4578 12:11:38.065954 DQM0 = 48, DQM1 = 45
4579 12:11:38.069377 DQ Delay:
4580 12:11:38.072479 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4581 12:11:38.072570 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4582 12:11:38.075945 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4583 12:11:38.082838 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4584 12:11:38.082940
4585 12:11:38.083009
4586 12:11:38.089515 [DQSOSCAuto] RK0, (LSB)MR18= 0x4368, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4587 12:11:38.092779 CH1 RK0: MR19=808, MR18=4368
4588 12:11:38.099505 CH1_RK0: MR19=0x808, MR18=0x4368, DQSOSC=390, MR23=63, INC=172, DEC=114
4589 12:11:38.099616
4590 12:11:38.102861 ----->DramcWriteLeveling(PI) begin...
4591 12:11:38.102964 ==
4592 12:11:38.106014 Dram Type= 6, Freq= 0, CH_1, rank 1
4593 12:11:38.109335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:11:38.109436 ==
4595 12:11:38.112578 Write leveling (Byte 0): 30 => 30
4596 12:11:38.115856 Write leveling (Byte 1): 31 => 31
4597 12:11:38.119150 DramcWriteLeveling(PI) end<-----
4598 12:11:38.119252
4599 12:11:38.119322 ==
4600 12:11:38.122559 Dram Type= 6, Freq= 0, CH_1, rank 1
4601 12:11:38.125993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 12:11:38.126084 ==
4603 12:11:38.129175 [Gating] SW mode calibration
4604 12:11:38.135698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4605 12:11:38.142290 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4606 12:11:38.145583 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 12:11:38.148956 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 12:11:38.155929 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4609 12:11:38.158651 0 9 12 | B1->B0 | 2f2f 3131 | 0 0 | (1 1) (0 1)
4610 12:11:38.162214 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4611 12:11:38.168939 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 12:11:38.172369 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 12:11:38.175626 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 12:11:38.182361 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 12:11:38.185771 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 12:11:38.188443 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 12:11:38.195197 0 10 12 | B1->B0 | 3737 3737 | 0 0 | (0 0) (1 1)
4618 12:11:38.198506 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 12:11:38.202377 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 12:11:38.208526 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 12:11:38.211859 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:11:38.214989 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:11:38.221880 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 12:11:38.225060 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 12:11:38.228970 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4626 12:11:38.234932 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4627 12:11:38.238887 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:11:38.242120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:11:38.248717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:11:38.252070 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:11:38.255512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:11:38.261683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:11:38.265192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:11:38.268612 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:11:38.275355 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:11:38.278613 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:11:38.281930 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:11:38.288201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:11:38.291554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:11:38.295026 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:11:38.298570 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4642 12:11:38.305063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 12:11:38.308572 Total UI for P1: 0, mck2ui 16
4644 12:11:38.311971 best dqsien dly found for B0: ( 0, 13, 12)
4645 12:11:38.314690 Total UI for P1: 0, mck2ui 16
4646 12:11:38.318126 best dqsien dly found for B1: ( 0, 13, 12)
4647 12:11:38.321509 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4648 12:11:38.324843 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4649 12:11:38.324936
4650 12:11:38.328270 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4651 12:11:38.331580 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4652 12:11:38.334695 [Gating] SW calibration Done
4653 12:11:38.334805 ==
4654 12:11:38.337804 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 12:11:38.341291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 12:11:38.341411 ==
4657 12:11:38.344863 RX Vref Scan: 0
4658 12:11:38.344951
4659 12:11:38.348085 RX Vref 0 -> 0, step: 1
4660 12:11:38.348212
4661 12:11:38.348287 RX Delay -230 -> 252, step: 16
4662 12:11:38.354866 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4663 12:11:38.358146 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4664 12:11:38.361510 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4665 12:11:38.364911 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4666 12:11:38.371131 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4667 12:11:38.374670 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4668 12:11:38.378200 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4669 12:11:38.381370 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4670 12:11:38.384838 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4671 12:11:38.391101 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4672 12:11:38.394398 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4673 12:11:38.397918 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4674 12:11:38.401188 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4675 12:11:38.407703 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4676 12:11:38.411059 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4677 12:11:38.414516 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4678 12:11:38.414616 ==
4679 12:11:38.418053 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 12:11:38.421457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 12:11:38.424754 ==
4682 12:11:38.424855 DQS Delay:
4683 12:11:38.424946 DQS0 = 0, DQS1 = 0
4684 12:11:38.428022 DQM Delay:
4685 12:11:38.428113 DQM0 = 51, DQM1 = 50
4686 12:11:38.431505 DQ Delay:
4687 12:11:38.431600 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4688 12:11:38.434353 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4689 12:11:38.437621 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4690 12:11:38.441440 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4691 12:11:38.444597
4692 12:11:38.444697
4693 12:11:38.444801 ==
4694 12:11:38.447546 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 12:11:38.450795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 12:11:38.450899 ==
4697 12:11:38.450988
4698 12:11:38.451071
4699 12:11:38.454156 TX Vref Scan disable
4700 12:11:38.454245 == TX Byte 0 ==
4701 12:11:38.461503 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4702 12:11:38.464837 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4703 12:11:38.464954 == TX Byte 1 ==
4704 12:11:38.471339 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 12:11:38.474801 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 12:11:38.474929 ==
4707 12:11:38.477582 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 12:11:38.481002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 12:11:38.481096 ==
4710 12:11:38.481187
4711 12:11:38.481276
4712 12:11:38.484409 TX Vref Scan disable
4713 12:11:38.487870 == TX Byte 0 ==
4714 12:11:38.491221 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 12:11:38.494666 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 12:11:38.497463 == TX Byte 1 ==
4717 12:11:38.500917 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4718 12:11:38.504236 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4719 12:11:38.504343
4720 12:11:38.507660 [DATLAT]
4721 12:11:38.507754 Freq=600, CH1 RK1
4722 12:11:38.507824
4723 12:11:38.511038 DATLAT Default: 0x9
4724 12:11:38.511128 0, 0xFFFF, sum = 0
4725 12:11:38.514426 1, 0xFFFF, sum = 0
4726 12:11:38.514518 2, 0xFFFF, sum = 0
4727 12:11:38.517901 3, 0xFFFF, sum = 0
4728 12:11:38.517992 4, 0xFFFF, sum = 0
4729 12:11:38.520626 5, 0xFFFF, sum = 0
4730 12:11:38.520717 6, 0xFFFF, sum = 0
4731 12:11:38.524623 7, 0xFFFF, sum = 0
4732 12:11:38.524718 8, 0x0, sum = 1
4733 12:11:38.527379 9, 0x0, sum = 2
4734 12:11:38.527467 10, 0x0, sum = 3
4735 12:11:38.530723 11, 0x0, sum = 4
4736 12:11:38.530819 best_step = 9
4737 12:11:38.530888
4738 12:11:38.530952 ==
4739 12:11:38.534101 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 12:11:38.537652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 12:11:38.540951 ==
4742 12:11:38.541044 RX Vref Scan: 0
4743 12:11:38.541111
4744 12:11:38.544450 RX Vref 0 -> 0, step: 1
4745 12:11:38.544545
4746 12:11:38.547841 RX Delay -163 -> 252, step: 8
4747 12:11:38.551143 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4748 12:11:38.553693 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4749 12:11:38.560333 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4750 12:11:38.564383 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4751 12:11:38.567503 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4752 12:11:38.570792 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4753 12:11:38.574038 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4754 12:11:38.580828 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4755 12:11:38.584180 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4756 12:11:38.587594 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4757 12:11:38.590968 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4758 12:11:38.596988 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4759 12:11:38.600438 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4760 12:11:38.603868 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4761 12:11:38.607342 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4762 12:11:38.610772 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4763 12:11:38.610902 ==
4764 12:11:38.614055 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 12:11:38.620863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 12:11:38.621004 ==
4767 12:11:38.621098 DQS Delay:
4768 12:11:38.624159 DQS0 = 0, DQS1 = 0
4769 12:11:38.624261 DQM Delay:
4770 12:11:38.624350 DQM0 = 49, DQM1 = 46
4771 12:11:38.627663 DQ Delay:
4772 12:11:38.630345 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4773 12:11:38.633751 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4774 12:11:38.637012 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4775 12:11:38.640315 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4776 12:11:38.640439
4777 12:11:38.640534
4778 12:11:38.647177 [DQSOSCAuto] RK1, (LSB)MR18= 0x651d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4779 12:11:38.650507 CH1 RK1: MR19=808, MR18=651D
4780 12:11:38.657097 CH1_RK1: MR19=0x808, MR18=0x651D, DQSOSC=390, MR23=63, INC=172, DEC=114
4781 12:11:38.660519 [RxdqsGatingPostProcess] freq 600
4782 12:11:38.663903 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4783 12:11:38.667244 Pre-setting of DQS Precalculation
4784 12:11:38.673926 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4785 12:11:38.680379 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4786 12:11:38.686923 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4787 12:11:38.687108
4788 12:11:38.687211
4789 12:11:38.690063 [Calibration Summary] 1200 Mbps
4790 12:11:38.690178 CH 0, Rank 0
4791 12:11:38.693485 SW Impedance : PASS
4792 12:11:38.696896 DUTY Scan : NO K
4793 12:11:38.697018 ZQ Calibration : PASS
4794 12:11:38.700109 Jitter Meter : NO K
4795 12:11:38.703570 CBT Training : PASS
4796 12:11:38.703698 Write leveling : PASS
4797 12:11:38.706923 RX DQS gating : PASS
4798 12:11:38.710362 RX DQ/DQS(RDDQC) : PASS
4799 12:11:38.710475 TX DQ/DQS : PASS
4800 12:11:38.713762 RX DATLAT : PASS
4801 12:11:38.716576 RX DQ/DQS(Engine): PASS
4802 12:11:38.716692 TX OE : NO K
4803 12:11:38.719967 All Pass.
4804 12:11:38.720075
4805 12:11:38.720148 CH 0, Rank 1
4806 12:11:38.723259 SW Impedance : PASS
4807 12:11:38.723392 DUTY Scan : NO K
4808 12:11:38.726555 ZQ Calibration : PASS
4809 12:11:38.729968 Jitter Meter : NO K
4810 12:11:38.730105 CBT Training : PASS
4811 12:11:38.733436 Write leveling : PASS
4812 12:11:38.733577 RX DQS gating : PASS
4813 12:11:38.736837 RX DQ/DQS(RDDQC) : PASS
4814 12:11:38.740394 TX DQ/DQS : PASS
4815 12:11:38.740557 RX DATLAT : PASS
4816 12:11:38.743775 RX DQ/DQS(Engine): PASS
4817 12:11:38.746412 TX OE : NO K
4818 12:11:38.746529 All Pass.
4819 12:11:38.746600
4820 12:11:38.746663 CH 1, Rank 0
4821 12:11:38.750058 SW Impedance : PASS
4822 12:11:38.753465 DUTY Scan : NO K
4823 12:11:38.753586 ZQ Calibration : PASS
4824 12:11:38.756764 Jitter Meter : NO K
4825 12:11:38.759943 CBT Training : PASS
4826 12:11:38.760050 Write leveling : PASS
4827 12:11:38.763226 RX DQS gating : PASS
4828 12:11:38.766688 RX DQ/DQS(RDDQC) : PASS
4829 12:11:38.766793 TX DQ/DQS : PASS
4830 12:11:38.769931 RX DATLAT : PASS
4831 12:11:38.773298 RX DQ/DQS(Engine): PASS
4832 12:11:38.773426 TX OE : NO K
4833 12:11:38.773495 All Pass.
4834 12:11:38.776856
4835 12:11:38.776956 CH 1, Rank 1
4836 12:11:38.780130 SW Impedance : PASS
4837 12:11:38.780217 DUTY Scan : NO K
4838 12:11:38.783454 ZQ Calibration : PASS
4839 12:11:38.786703 Jitter Meter : NO K
4840 12:11:38.786822 CBT Training : PASS
4841 12:11:38.789918 Write leveling : PASS
4842 12:11:38.790029 RX DQS gating : PASS
4843 12:11:38.793284 RX DQ/DQS(RDDQC) : PASS
4844 12:11:38.796499 TX DQ/DQS : PASS
4845 12:11:38.796621 RX DATLAT : PASS
4846 12:11:38.799653 RX DQ/DQS(Engine): PASS
4847 12:11:38.802916 TX OE : NO K
4848 12:11:38.803037 All Pass.
4849 12:11:38.803133
4850 12:11:38.806266 DramC Write-DBI off
4851 12:11:38.806401 PER_BANK_REFRESH: Hybrid Mode
4852 12:11:38.809630 TX_TRACKING: ON
4853 12:11:38.816346 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4854 12:11:38.822713 [FAST_K] Save calibration result to emmc
4855 12:11:38.826577 dramc_set_vcore_voltage set vcore to 662500
4856 12:11:38.826671 Read voltage for 933, 3
4857 12:11:38.829911 Vio18 = 0
4858 12:11:38.830002 Vcore = 662500
4859 12:11:38.830087 Vdram = 0
4860 12:11:38.832756 Vddq = 0
4861 12:11:38.832844 Vmddr = 0
4862 12:11:38.836082 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4863 12:11:38.843038 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4864 12:11:38.846367 MEM_TYPE=3, freq_sel=17
4865 12:11:38.849704 sv_algorithm_assistance_LP4_1600
4866 12:11:38.853177 ============ PULL DRAM RESETB DOWN ============
4867 12:11:38.855851 ========== PULL DRAM RESETB DOWN end =========
4868 12:11:38.863017 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4869 12:11:38.866359 ===================================
4870 12:11:38.866462 LPDDR4 DRAM CONFIGURATION
4871 12:11:38.869769 ===================================
4872 12:11:38.872568 EX_ROW_EN[0] = 0x0
4873 12:11:38.872665 EX_ROW_EN[1] = 0x0
4874 12:11:38.875847 LP4Y_EN = 0x0
4875 12:11:38.875938 WORK_FSP = 0x0
4876 12:11:38.879743 WL = 0x3
4877 12:11:38.882387 RL = 0x3
4878 12:11:38.882499 BL = 0x2
4879 12:11:38.885817 RPST = 0x0
4880 12:11:38.885921 RD_PRE = 0x0
4881 12:11:38.889191 WR_PRE = 0x1
4882 12:11:38.889298 WR_PST = 0x0
4883 12:11:38.892539 DBI_WR = 0x0
4884 12:11:38.892622 DBI_RD = 0x0
4885 12:11:38.895725 OTF = 0x1
4886 12:11:38.899320 ===================================
4887 12:11:38.902851 ===================================
4888 12:11:38.902978 ANA top config
4889 12:11:38.906042 ===================================
4890 12:11:38.909363 DLL_ASYNC_EN = 0
4891 12:11:38.912723 ALL_SLAVE_EN = 1
4892 12:11:38.912813 NEW_RANK_MODE = 1
4893 12:11:38.916131 DLL_IDLE_MODE = 1
4894 12:11:38.919632 LP45_APHY_COMB_EN = 1
4895 12:11:38.922347 TX_ODT_DIS = 1
4896 12:11:38.922432 NEW_8X_MODE = 1
4897 12:11:38.925711 ===================================
4898 12:11:38.929170 ===================================
4899 12:11:38.932455 data_rate = 1866
4900 12:11:38.935926 CKR = 1
4901 12:11:38.939319 DQ_P2S_RATIO = 8
4902 12:11:38.942709 ===================================
4903 12:11:38.945497 CA_P2S_RATIO = 8
4904 12:11:38.949085 DQ_CA_OPEN = 0
4905 12:11:38.949176 DQ_SEMI_OPEN = 0
4906 12:11:38.952426 CA_SEMI_OPEN = 0
4907 12:11:38.955688 CA_FULL_RATE = 0
4908 12:11:38.959078 DQ_CKDIV4_EN = 1
4909 12:11:38.962575 CA_CKDIV4_EN = 1
4910 12:11:38.965819 CA_PREDIV_EN = 0
4911 12:11:38.965915 PH8_DLY = 0
4912 12:11:38.969070 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4913 12:11:38.972613 DQ_AAMCK_DIV = 4
4914 12:11:38.976080 CA_AAMCK_DIV = 4
4915 12:11:38.979310 CA_ADMCK_DIV = 4
4916 12:11:38.982734 DQ_TRACK_CA_EN = 0
4917 12:11:38.982820 CA_PICK = 933
4918 12:11:38.985881 CA_MCKIO = 933
4919 12:11:38.989207 MCKIO_SEMI = 0
4920 12:11:38.992612 PLL_FREQ = 3732
4921 12:11:38.995862 DQ_UI_PI_RATIO = 32
4922 12:11:38.998645 CA_UI_PI_RATIO = 0
4923 12:11:39.001882 ===================================
4924 12:11:39.005897 ===================================
4925 12:11:39.009243 memory_type:LPDDR4
4926 12:11:39.009348 GP_NUM : 10
4927 12:11:39.012517 SRAM_EN : 1
4928 12:11:39.012609 MD32_EN : 0
4929 12:11:39.015806 ===================================
4930 12:11:39.019000 [ANA_INIT] >>>>>>>>>>>>>>
4931 12:11:39.022429 <<<<<< [CONFIGURE PHASE]: ANA_TX
4932 12:11:39.025795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4933 12:11:39.029253 ===================================
4934 12:11:39.032594 data_rate = 1866,PCW = 0X8f00
4935 12:11:39.035914 ===================================
4936 12:11:39.039162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4937 12:11:39.042582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 12:11:39.048718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 12:11:39.052686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4940 12:11:39.055623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4941 12:11:39.062384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4942 12:11:39.062504 [ANA_INIT] flow start
4943 12:11:39.065884 [ANA_INIT] PLL >>>>>>>>
4944 12:11:39.065973 [ANA_INIT] PLL <<<<<<<<
4945 12:11:39.069125 [ANA_INIT] MIDPI >>>>>>>>
4946 12:11:39.072308 [ANA_INIT] MIDPI <<<<<<<<
4947 12:11:39.075795 [ANA_INIT] DLL >>>>>>>>
4948 12:11:39.075889 [ANA_INIT] flow end
4949 12:11:39.079020 ============ LP4 DIFF to SE enter ============
4950 12:11:39.085769 ============ LP4 DIFF to SE exit ============
4951 12:11:39.085877 [ANA_INIT] <<<<<<<<<<<<<
4952 12:11:39.088431 [Flow] Enable top DCM control >>>>>
4953 12:11:39.092213 [Flow] Enable top DCM control <<<<<
4954 12:11:39.095702 Enable DLL master slave shuffle
4955 12:11:39.102220 ==============================================================
4956 12:11:39.102342 Gating Mode config
4957 12:11:39.109007 ==============================================================
4958 12:11:39.112392 Config description:
4959 12:11:39.122031 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4960 12:11:39.128734 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4961 12:11:39.132150 SELPH_MODE 0: By rank 1: By Phase
4962 12:11:39.138842 ==============================================================
4963 12:11:39.142156 GAT_TRACK_EN = 1
4964 12:11:39.142287 RX_GATING_MODE = 2
4965 12:11:39.145532 RX_GATING_TRACK_MODE = 2
4966 12:11:39.148892 SELPH_MODE = 1
4967 12:11:39.152353 PICG_EARLY_EN = 1
4968 12:11:39.155661 VALID_LAT_VALUE = 1
4969 12:11:39.162375 ==============================================================
4970 12:11:39.165610 Enter into Gating configuration >>>>
4971 12:11:39.169010 Exit from Gating configuration <<<<
4972 12:11:39.171864 Enter into DVFS_PRE_config >>>>>
4973 12:11:39.182350 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4974 12:11:39.185065 Exit from DVFS_PRE_config <<<<<
4975 12:11:39.188562 Enter into PICG configuration >>>>
4976 12:11:39.191987 Exit from PICG configuration <<<<
4977 12:11:39.195187 [RX_INPUT] configuration >>>>>
4978 12:11:39.198355 [RX_INPUT] configuration <<<<<
4979 12:11:39.201813 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4980 12:11:39.208438 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4981 12:11:39.215153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 12:11:39.218598 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 12:11:39.224976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 12:11:39.231544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 12:11:39.234859 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4986 12:11:39.238436 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4987 12:11:39.244997 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4988 12:11:39.248393 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4989 12:11:39.251599 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4990 12:11:39.258311 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4991 12:11:39.261708 ===================================
4992 12:11:39.261811 LPDDR4 DRAM CONFIGURATION
4993 12:11:39.265098 ===================================
4994 12:11:39.268461 EX_ROW_EN[0] = 0x0
4995 12:11:39.268561 EX_ROW_EN[1] = 0x0
4996 12:11:39.271944 LP4Y_EN = 0x0
4997 12:11:39.275236 WORK_FSP = 0x0
4998 12:11:39.275334 WL = 0x3
4999 12:11:39.278617 RL = 0x3
5000 12:11:39.278700 BL = 0x2
5001 12:11:39.281947 RPST = 0x0
5002 12:11:39.282042 RD_PRE = 0x0
5003 12:11:39.285407 WR_PRE = 0x1
5004 12:11:39.285531 WR_PST = 0x0
5005 12:11:39.288695 DBI_WR = 0x0
5006 12:11:39.288786 DBI_RD = 0x0
5007 12:11:39.291481 OTF = 0x1
5008 12:11:39.295027 ===================================
5009 12:11:39.298456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5010 12:11:39.301817 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5011 12:11:39.308253 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 12:11:39.311655 ===================================
5013 12:11:39.311765 LPDDR4 DRAM CONFIGURATION
5014 12:11:39.315031 ===================================
5015 12:11:39.318333 EX_ROW_EN[0] = 0x10
5016 12:11:39.318464 EX_ROW_EN[1] = 0x0
5017 12:11:39.321830 LP4Y_EN = 0x0
5018 12:11:39.321938 WORK_FSP = 0x0
5019 12:11:39.325223 WL = 0x3
5020 12:11:39.325338 RL = 0x3
5021 12:11:39.328471 BL = 0x2
5022 12:11:39.331405 RPST = 0x0
5023 12:11:39.331524 RD_PRE = 0x0
5024 12:11:39.334818 WR_PRE = 0x1
5025 12:11:39.334930 WR_PST = 0x0
5026 12:11:39.338005 DBI_WR = 0x0
5027 12:11:39.338118 DBI_RD = 0x0
5028 12:11:39.341387 OTF = 0x1
5029 12:11:39.344736 ===================================
5030 12:11:39.348108 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5031 12:11:39.353448 nWR fixed to 30
5032 12:11:39.356752 [ModeRegInit_LP4] CH0 RK0
5033 12:11:39.356859 [ModeRegInit_LP4] CH0 RK1
5034 12:11:39.360309 [ModeRegInit_LP4] CH1 RK0
5035 12:11:39.363794 [ModeRegInit_LP4] CH1 RK1
5036 12:11:39.363887 match AC timing 9
5037 12:11:39.370569 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5038 12:11:39.373376 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5039 12:11:39.376691 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5040 12:11:39.383232 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5041 12:11:39.386625 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5042 12:11:39.386737 ==
5043 12:11:39.389934 Dram Type= 6, Freq= 0, CH_0, rank 0
5044 12:11:39.393292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5045 12:11:39.393383 ==
5046 12:11:39.400116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5047 12:11:39.406848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5048 12:11:39.410149 [CA 0] Center 37 (6~68) winsize 63
5049 12:11:39.413442 [CA 1] Center 37 (7~68) winsize 62
5050 12:11:39.417292 [CA 2] Center 34 (4~65) winsize 62
5051 12:11:39.420451 [CA 3] Center 34 (3~65) winsize 63
5052 12:11:39.423848 [CA 4] Center 33 (3~64) winsize 62
5053 12:11:39.426616 [CA 5] Center 32 (2~62) winsize 61
5054 12:11:39.426737
5055 12:11:39.429977 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5056 12:11:39.430093
5057 12:11:39.433366 [CATrainingPosCal] consider 1 rank data
5058 12:11:39.436573 u2DelayCellTimex100 = 270/100 ps
5059 12:11:39.440434 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5060 12:11:39.443086 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5061 12:11:39.446859 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5062 12:11:39.450180 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5063 12:11:39.453660 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5064 12:11:39.456389 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5065 12:11:39.459620
5066 12:11:39.462929 CA PerBit enable=1, Macro0, CA PI delay=32
5067 12:11:39.463048
5068 12:11:39.466463 [CBTSetCACLKResult] CA Dly = 32
5069 12:11:39.466578 CS Dly: 5 (0~36)
5070 12:11:39.466677 ==
5071 12:11:39.470016 Dram Type= 6, Freq= 0, CH_0, rank 1
5072 12:11:39.473424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 12:11:39.473547 ==
5074 12:11:39.479442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5075 12:11:39.486407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5076 12:11:39.489657 [CA 0] Center 37 (6~68) winsize 63
5077 12:11:39.492991 [CA 1] Center 37 (7~68) winsize 62
5078 12:11:39.496466 [CA 2] Center 34 (4~65) winsize 62
5079 12:11:39.499388 [CA 3] Center 34 (3~65) winsize 63
5080 12:11:39.502667 [CA 4] Center 33 (3~64) winsize 62
5081 12:11:39.506140 [CA 5] Center 32 (2~62) winsize 61
5082 12:11:39.506268
5083 12:11:39.509588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5084 12:11:39.509705
5085 12:11:39.513024 [CATrainingPosCal] consider 2 rank data
5086 12:11:39.516388 u2DelayCellTimex100 = 270/100 ps
5087 12:11:39.519793 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5088 12:11:39.523042 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5089 12:11:39.526374 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5090 12:11:39.529855 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5091 12:11:39.536520 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5092 12:11:39.539188 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5093 12:11:39.539314
5094 12:11:39.542566 CA PerBit enable=1, Macro0, CA PI delay=32
5095 12:11:39.542678
5096 12:11:39.545824 [CBTSetCACLKResult] CA Dly = 32
5097 12:11:39.545919 CS Dly: 5 (0~37)
5098 12:11:39.545990
5099 12:11:39.549785 ----->DramcWriteLeveling(PI) begin...
5100 12:11:39.549879 ==
5101 12:11:39.552879 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 12:11:39.559504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 12:11:39.559630 ==
5104 12:11:39.562785 Write leveling (Byte 0): 31 => 31
5105 12:11:39.562878 Write leveling (Byte 1): 27 => 27
5106 12:11:39.566255 DramcWriteLeveling(PI) end<-----
5107 12:11:39.566369
5108 12:11:39.569648 ==
5109 12:11:39.569743 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 12:11:39.576366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 12:11:39.576512 ==
5112 12:11:39.579621 [Gating] SW mode calibration
5113 12:11:39.586341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5114 12:11:39.589698 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5115 12:11:39.596217 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5116 12:11:39.599676 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 12:11:39.602490 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 12:11:39.609380 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 12:11:39.612797 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 12:11:39.616183 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 12:11:39.619513 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5122 12:11:39.626290 0 14 28 | B1->B0 | 3434 2d2d | 0 1 | (0 1) (0 0)
5123 12:11:39.629609 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5124 12:11:39.632830 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 12:11:39.639520 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 12:11:39.642966 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 12:11:39.645878 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 12:11:39.653053 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 12:11:39.656204 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5130 12:11:39.659577 0 15 28 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
5131 12:11:39.666253 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
5132 12:11:39.669545 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 12:11:39.672888 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 12:11:39.679089 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 12:11:39.682385 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 12:11:39.685699 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 12:11:39.692615 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 12:11:39.695988 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5139 12:11:39.699261 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 12:11:39.705537 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:11:39.708977 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:11:39.712306 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:11:39.719146 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:11:39.722595 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:11:39.725360 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:11:39.732307 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:11:39.735532 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:11:39.738884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:11:39.745196 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:11:39.748623 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:11:39.752029 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:11:39.758886 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:11:39.762045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5154 12:11:39.765147 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5155 12:11:39.768329 Total UI for P1: 0, mck2ui 16
5156 12:11:39.771671 best dqsien dly found for B0: ( 1, 2, 24)
5157 12:11:39.778354 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5158 12:11:39.782097 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 12:11:39.784853 Total UI for P1: 0, mck2ui 16
5160 12:11:39.788322 best dqsien dly found for B1: ( 1, 2, 30)
5161 12:11:39.791643 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5162 12:11:39.795113 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5163 12:11:39.795231
5164 12:11:39.798564 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5165 12:11:39.801950 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5166 12:11:39.804660 [Gating] SW calibration Done
5167 12:11:39.804767 ==
5168 12:11:39.808161 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 12:11:39.811622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 12:11:39.811733 ==
5171 12:11:39.815117 RX Vref Scan: 0
5172 12:11:39.815231
5173 12:11:39.817987 RX Vref 0 -> 0, step: 1
5174 12:11:39.818092
5175 12:11:39.818196 RX Delay -80 -> 252, step: 8
5176 12:11:39.824934 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5177 12:11:39.828151 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5178 12:11:39.831631 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5179 12:11:39.834998 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5180 12:11:39.838490 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5181 12:11:39.841880 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5182 12:11:39.848347 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5183 12:11:39.851650 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5184 12:11:39.854477 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5185 12:11:39.857809 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5186 12:11:39.861407 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5187 12:11:39.868017 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5188 12:11:39.871130 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5189 12:11:39.874440 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5190 12:11:39.878353 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5191 12:11:39.880929 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5192 12:11:39.881045 ==
5193 12:11:39.885023 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 12:11:39.891463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 12:11:39.891620 ==
5196 12:11:39.891734 DQS Delay:
5197 12:11:39.894766 DQS0 = 0, DQS1 = 0
5198 12:11:39.894877 DQM Delay:
5199 12:11:39.894971 DQM0 = 103, DQM1 = 94
5200 12:11:39.898280 DQ Delay:
5201 12:11:39.901035 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5202 12:11:39.904407 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =115
5203 12:11:39.908355 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5204 12:11:39.911067 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5205 12:11:39.911197
5206 12:11:39.911300
5207 12:11:39.911406 ==
5208 12:11:39.914505 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 12:11:39.917967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 12:11:39.918088 ==
5211 12:11:39.918194
5212 12:11:39.918307
5213 12:11:39.921459 TX Vref Scan disable
5214 12:11:39.924920 == TX Byte 0 ==
5215 12:11:39.928377 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5216 12:11:39.931150 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5217 12:11:39.934665 == TX Byte 1 ==
5218 12:11:39.937534 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5219 12:11:39.940941 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5220 12:11:39.941071 ==
5221 12:11:39.944377 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 12:11:39.950953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 12:11:39.951089 ==
5224 12:11:39.951161
5225 12:11:39.951236
5226 12:11:39.951299 TX Vref Scan disable
5227 12:11:39.954995 == TX Byte 0 ==
5228 12:11:39.958498 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5229 12:11:39.964530 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5230 12:11:39.964671 == TX Byte 1 ==
5231 12:11:39.967945 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5232 12:11:39.974834 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5233 12:11:39.974960
5234 12:11:39.975030 [DATLAT]
5235 12:11:39.975094 Freq=933, CH0 RK0
5236 12:11:39.975155
5237 12:11:39.978201 DATLAT Default: 0xd
5238 12:11:39.978301 0, 0xFFFF, sum = 0
5239 12:11:39.981297 1, 0xFFFF, sum = 0
5240 12:11:39.984521 2, 0xFFFF, sum = 0
5241 12:11:39.984653 3, 0xFFFF, sum = 0
5242 12:11:39.987988 4, 0xFFFF, sum = 0
5243 12:11:39.988102 5, 0xFFFF, sum = 0
5244 12:11:39.991748 6, 0xFFFF, sum = 0
5245 12:11:39.991866 7, 0xFFFF, sum = 0
5246 12:11:39.994865 8, 0xFFFF, sum = 0
5247 12:11:39.994952 9, 0xFFFF, sum = 0
5248 12:11:39.998130 10, 0x0, sum = 1
5249 12:11:39.998250 11, 0x0, sum = 2
5250 12:11:40.001363 12, 0x0, sum = 3
5251 12:11:40.001494 13, 0x0, sum = 4
5252 12:11:40.001592 best_step = 11
5253 12:11:40.001683
5254 12:11:40.004627 ==
5255 12:11:40.008006 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 12:11:40.011412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 12:11:40.011526 ==
5258 12:11:40.011595 RX Vref Scan: 1
5259 12:11:40.011659
5260 12:11:40.014621 RX Vref 0 -> 0, step: 1
5261 12:11:40.014720
5262 12:11:40.018116 RX Delay -53 -> 252, step: 4
5263 12:11:40.018236
5264 12:11:40.021556 Set Vref, RX VrefLevel [Byte0]: 55
5265 12:11:40.024854 [Byte1]: 48
5266 12:11:40.024947
5267 12:11:40.028289 Final RX Vref Byte 0 = 55 to rank0
5268 12:11:40.030957 Final RX Vref Byte 1 = 48 to rank0
5269 12:11:40.034421 Final RX Vref Byte 0 = 55 to rank1
5270 12:11:40.037784 Final RX Vref Byte 1 = 48 to rank1==
5271 12:11:40.041281 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 12:11:40.044741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 12:11:40.048016 ==
5274 12:11:40.048127 DQS Delay:
5275 12:11:40.048208 DQS0 = 0, DQS1 = 0
5276 12:11:40.051422 DQM Delay:
5277 12:11:40.051515 DQM0 = 104, DQM1 = 94
5278 12:11:40.054771 DQ Delay:
5279 12:11:40.058001 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5280 12:11:40.061295 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5281 12:11:40.064559 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5282 12:11:40.067863 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5283 12:11:40.067962
5284 12:11:40.068037
5285 12:11:40.074785 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5286 12:11:40.077609 CH0 RK0: MR19=505, MR18=3028
5287 12:11:40.084325 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5288 12:11:40.084443
5289 12:11:40.087601 ----->DramcWriteLeveling(PI) begin...
5290 12:11:40.087693 ==
5291 12:11:40.090891 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 12:11:40.094074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 12:11:40.094183 ==
5294 12:11:40.097798 Write leveling (Byte 0): 34 => 34
5295 12:11:40.101198 Write leveling (Byte 1): 32 => 32
5296 12:11:40.104433 DramcWriteLeveling(PI) end<-----
5297 12:11:40.104574
5298 12:11:40.104671 ==
5299 12:11:40.107585 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 12:11:40.110780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 12:11:40.113993 ==
5302 12:11:40.114133 [Gating] SW mode calibration
5303 12:11:40.120893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5304 12:11:40.127601 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5305 12:11:40.131028 0 14 0 | B1->B0 | 3232 3030 | 1 0 | (1 1) (0 0)
5306 12:11:40.137247 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 12:11:40.140726 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 12:11:40.144042 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 12:11:40.150925 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 12:11:40.154312 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 12:11:40.157758 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5312 12:11:40.164249 0 14 28 | B1->B0 | 2b2b 2f2f | 0 0 | (1 0) (1 0)
5313 12:11:40.167587 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
5314 12:11:40.170816 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 12:11:40.177464 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 12:11:40.180932 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:11:40.183648 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 12:11:40.187122 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 12:11:40.193964 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5320 12:11:40.197272 0 15 28 | B1->B0 | 4040 3a3a | 1 0 | (0 0) (0 0)
5321 12:11:40.200614 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5322 12:11:40.207584 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 12:11:40.210719 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 12:11:40.214109 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 12:11:40.220650 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 12:11:40.223850 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 12:11:40.227076 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:11:40.233754 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5329 12:11:40.237156 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:11:40.240644 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:11:40.247423 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:11:40.250678 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:11:40.254121 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:11:40.260299 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:11:40.263561 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:11:40.267021 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:11:40.273511 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:11:40.276914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:11:40.280230 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:11:40.287053 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:11:40.290404 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:11:40.293885 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:11:40.300674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:11:40.303501 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5345 12:11:40.306799 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:11:40.309996 Total UI for P1: 0, mck2ui 16
5347 12:11:40.313820 best dqsien dly found for B0: ( 1, 2, 28)
5348 12:11:40.317054 Total UI for P1: 0, mck2ui 16
5349 12:11:40.320405 best dqsien dly found for B1: ( 1, 2, 30)
5350 12:11:40.323567 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5351 12:11:40.326858 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5352 12:11:40.327001
5353 12:11:40.330085 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5354 12:11:40.336571 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5355 12:11:40.336697 [Gating] SW calibration Done
5356 12:11:40.336767 ==
5357 12:11:40.340366 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 12:11:40.347002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 12:11:40.347165 ==
5360 12:11:40.347265 RX Vref Scan: 0
5361 12:11:40.347367
5362 12:11:40.349800 RX Vref 0 -> 0, step: 1
5363 12:11:40.349902
5364 12:11:40.353199 RX Delay -80 -> 252, step: 8
5365 12:11:40.356531 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5366 12:11:40.359905 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5367 12:11:40.363471 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5368 12:11:40.366868 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5369 12:11:40.373065 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5370 12:11:40.376353 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5371 12:11:40.379549 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5372 12:11:40.382811 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5373 12:11:40.386170 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5374 12:11:40.393037 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5375 12:11:40.396483 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5376 12:11:40.399824 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5377 12:11:40.403202 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5378 12:11:40.406644 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5379 12:11:40.409462 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5380 12:11:40.416211 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5381 12:11:40.416380 ==
5382 12:11:40.419536 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 12:11:40.422713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 12:11:40.422841 ==
5385 12:11:40.422937 DQS Delay:
5386 12:11:40.426598 DQS0 = 0, DQS1 = 0
5387 12:11:40.426726 DQM Delay:
5388 12:11:40.429859 DQM0 = 104, DQM1 = 94
5389 12:11:40.429983 DQ Delay:
5390 12:11:40.433044 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5391 12:11:40.436137 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5392 12:11:40.439422 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5393 12:11:40.442801 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5394 12:11:40.442931
5395 12:11:40.443026
5396 12:11:40.443120 ==
5397 12:11:40.446422 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 12:11:40.449558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 12:11:40.452808 ==
5400 12:11:40.452912
5401 12:11:40.452982
5402 12:11:40.453045 TX Vref Scan disable
5403 12:11:40.456203 == TX Byte 0 ==
5404 12:11:40.459634 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5405 12:11:40.463104 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5406 12:11:40.466491 == TX Byte 1 ==
5407 12:11:40.469424 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5408 12:11:40.472767 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5409 12:11:40.476314 ==
5410 12:11:40.479687 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 12:11:40.483024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 12:11:40.483177 ==
5413 12:11:40.483306
5414 12:11:40.483389
5415 12:11:40.486419 TX Vref Scan disable
5416 12:11:40.486549 == TX Byte 0 ==
5417 12:11:40.492437 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5418 12:11:40.495831 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5419 12:11:40.495964 == TX Byte 1 ==
5420 12:11:40.502833 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5421 12:11:40.505635 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5422 12:11:40.505730
5423 12:11:40.505797 [DATLAT]
5424 12:11:40.509768 Freq=933, CH0 RK1
5425 12:11:40.509892
5426 12:11:40.509964 DATLAT Default: 0xb
5427 12:11:40.512457 0, 0xFFFF, sum = 0
5428 12:11:40.512541 1, 0xFFFF, sum = 0
5429 12:11:40.515913 2, 0xFFFF, sum = 0
5430 12:11:40.516006 3, 0xFFFF, sum = 0
5431 12:11:40.519344 4, 0xFFFF, sum = 0
5432 12:11:40.519449 5, 0xFFFF, sum = 0
5433 12:11:40.522763 6, 0xFFFF, sum = 0
5434 12:11:40.522848 7, 0xFFFF, sum = 0
5435 12:11:40.526123 8, 0xFFFF, sum = 0
5436 12:11:40.529522 9, 0xFFFF, sum = 0
5437 12:11:40.529620 10, 0x0, sum = 1
5438 12:11:40.529691 11, 0x0, sum = 2
5439 12:11:40.532636 12, 0x0, sum = 3
5440 12:11:40.532737 13, 0x0, sum = 4
5441 12:11:40.535809 best_step = 11
5442 12:11:40.535892
5443 12:11:40.535957 ==
5444 12:11:40.539048 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 12:11:40.542380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 12:11:40.542475 ==
5447 12:11:40.546003 RX Vref Scan: 0
5448 12:11:40.546114
5449 12:11:40.546181 RX Vref 0 -> 0, step: 1
5450 12:11:40.546241
5451 12:11:40.549251 RX Delay -45 -> 252, step: 4
5452 12:11:40.556521 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5453 12:11:40.559716 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5454 12:11:40.562992 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5455 12:11:40.566175 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5456 12:11:40.569638 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5457 12:11:40.575866 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5458 12:11:40.579276 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5459 12:11:40.582675 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5460 12:11:40.586257 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5461 12:11:40.589819 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5462 12:11:40.596261 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5463 12:11:40.599493 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5464 12:11:40.602891 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5465 12:11:40.606292 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5466 12:11:40.609007 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5467 12:11:40.615796 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5468 12:11:40.615928 ==
5469 12:11:40.619143 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 12:11:40.622586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 12:11:40.622687 ==
5472 12:11:40.622776 DQS Delay:
5473 12:11:40.626070 DQS0 = 0, DQS1 = 0
5474 12:11:40.626166 DQM Delay:
5475 12:11:40.629521 DQM0 = 105, DQM1 = 94
5476 12:11:40.629621 DQ Delay:
5477 12:11:40.632315 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5478 12:11:40.635726 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5479 12:11:40.638838 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5480 12:11:40.642593 DQ12 =98, DQ13 =100, DQ14 =106, DQ15 =102
5481 12:11:40.642705
5482 12:11:40.642797
5483 12:11:40.652327 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5484 12:11:40.655462 CH0 RK1: MR19=505, MR18=2B03
5485 12:11:40.659168 CH0_RK1: MR19=0x505, MR18=0x2B03, DQSOSC=408, MR23=63, INC=65, DEC=43
5486 12:11:40.662378 [RxdqsGatingPostProcess] freq 933
5487 12:11:40.668753 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5488 12:11:40.671926 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 12:11:40.675911 best DQS1 dly(2T, 0.5T) = (0, 10)
5490 12:11:40.678707 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 12:11:40.682133 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5492 12:11:40.685622 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 12:11:40.689079 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 12:11:40.691864 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 12:11:40.695218 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 12:11:40.698574 Pre-setting of DQS Precalculation
5497 12:11:40.702473 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5498 12:11:40.702605 ==
5499 12:11:40.705186 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 12:11:40.708541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 12:11:40.708655 ==
5502 12:11:40.715266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5503 12:11:40.722038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5504 12:11:40.725567 [CA 0] Center 36 (6~67) winsize 62
5505 12:11:40.728320 [CA 1] Center 36 (6~67) winsize 62
5506 12:11:40.731838 [CA 2] Center 34 (4~65) winsize 62
5507 12:11:40.735213 [CA 3] Center 34 (4~65) winsize 62
5508 12:11:40.738741 [CA 4] Center 34 (4~65) winsize 62
5509 12:11:40.742073 [CA 5] Center 33 (3~64) winsize 62
5510 12:11:40.742180
5511 12:11:40.745467 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5512 12:11:40.745565
5513 12:11:40.748833 [CATrainingPosCal] consider 1 rank data
5514 12:11:40.751946 u2DelayCellTimex100 = 270/100 ps
5515 12:11:40.755221 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5516 12:11:40.758263 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5517 12:11:40.761525 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5518 12:11:40.764891 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5519 12:11:40.768199 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5520 12:11:40.772062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5521 12:11:40.775274
5522 12:11:40.778492 CA PerBit enable=1, Macro0, CA PI delay=33
5523 12:11:40.778596
5524 12:11:40.781832 [CBTSetCACLKResult] CA Dly = 33
5525 12:11:40.781930 CS Dly: 6 (0~37)
5526 12:11:40.782019 ==
5527 12:11:40.785172 Dram Type= 6, Freq= 0, CH_1, rank 1
5528 12:11:40.788434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 12:11:40.788572 ==
5530 12:11:40.794739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5531 12:11:40.801522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5532 12:11:40.804779 [CA 0] Center 36 (6~67) winsize 62
5533 12:11:40.808084 [CA 1] Center 37 (6~68) winsize 63
5534 12:11:40.811346 [CA 2] Center 35 (4~66) winsize 63
5535 12:11:40.814807 [CA 3] Center 34 (4~65) winsize 62
5536 12:11:40.817657 [CA 4] Center 34 (4~65) winsize 62
5537 12:11:40.821653 [CA 5] Center 33 (3~64) winsize 62
5538 12:11:40.821789
5539 12:11:40.824382 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5540 12:11:40.824498
5541 12:11:40.827652 [CATrainingPosCal] consider 2 rank data
5542 12:11:40.831068 u2DelayCellTimex100 = 270/100 ps
5543 12:11:40.834428 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5544 12:11:40.837829 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5545 12:11:40.841300 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 12:11:40.847403 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5547 12:11:40.850810 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5548 12:11:40.854169 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5549 12:11:40.854304
5550 12:11:40.857624 CA PerBit enable=1, Macro0, CA PI delay=33
5551 12:11:40.857743
5552 12:11:40.860808 [CBTSetCACLKResult] CA Dly = 33
5553 12:11:40.860924 CS Dly: 7 (0~39)
5554 12:11:40.861029
5555 12:11:40.863986 ----->DramcWriteLeveling(PI) begin...
5556 12:11:40.864108 ==
5557 12:11:40.867449 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 12:11:40.873954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 12:11:40.874113 ==
5560 12:11:40.877778 Write leveling (Byte 0): 23 => 23
5561 12:11:40.881139 Write leveling (Byte 1): 28 => 28
5562 12:11:40.881268 DramcWriteLeveling(PI) end<-----
5563 12:11:40.884331
5564 12:11:40.884447 ==
5565 12:11:40.887621 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 12:11:40.890939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:11:40.891076 ==
5568 12:11:40.894343 [Gating] SW mode calibration
5569 12:11:40.900591 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5570 12:11:40.903910 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5571 12:11:40.910695 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 12:11:40.914048 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 12:11:40.917322 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 12:11:40.923922 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:11:40.927380 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 12:11:40.930605 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 12:11:40.937325 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5578 12:11:40.940818 0 14 28 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
5579 12:11:40.944224 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 12:11:40.950809 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 12:11:40.953899 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 12:11:40.957090 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:11:40.963850 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 12:11:40.967058 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 12:11:40.970312 0 15 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5586 12:11:40.977382 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5587 12:11:40.980526 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:11:40.983776 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 12:11:40.990405 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 12:11:40.993690 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:11:40.997053 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:11:41.003320 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 12:11:41.007314 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5594 12:11:41.010029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5595 12:11:41.017003 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:11:41.020333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:11:41.023497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:11:41.030041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:11:41.033230 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:11:41.036669 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:11:41.039986 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:11:41.046922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:11:41.050387 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:11:41.053076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:11:41.059825 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:11:41.063164 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:11:41.066466 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:11:41.073346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:11:41.076589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5610 12:11:41.079767 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5611 12:11:41.082922 Total UI for P1: 0, mck2ui 16
5612 12:11:41.086707 best dqsien dly found for B1: ( 1, 2, 24)
5613 12:11:41.093411 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:11:41.096366 Total UI for P1: 0, mck2ui 16
5615 12:11:41.099594 best dqsien dly found for B0: ( 1, 2, 28)
5616 12:11:41.102790 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5617 12:11:41.106092 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5618 12:11:41.106228
5619 12:11:41.109598 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5620 12:11:41.113012 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5621 12:11:41.116428 [Gating] SW calibration Done
5622 12:11:41.116551 ==
5623 12:11:41.119927 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 12:11:41.123427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 12:11:41.123547 ==
5626 12:11:41.126175 RX Vref Scan: 0
5627 12:11:41.126274
5628 12:11:41.126341 RX Vref 0 -> 0, step: 1
5629 12:11:41.126403
5630 12:11:41.129388 RX Delay -80 -> 252, step: 8
5631 12:11:41.136364 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5632 12:11:41.139698 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5633 12:11:41.142926 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5634 12:11:41.146391 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5635 12:11:41.149218 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5636 12:11:41.152579 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5637 12:11:41.159452 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5638 12:11:41.162900 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5639 12:11:41.166166 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5640 12:11:41.169564 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5641 12:11:41.172362 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5642 12:11:41.175804 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5643 12:11:41.182516 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5644 12:11:41.185903 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5645 12:11:41.189493 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5646 12:11:41.192446 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5647 12:11:41.192553 ==
5648 12:11:41.195621 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 12:11:41.202666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 12:11:41.202801 ==
5651 12:11:41.202873 DQS Delay:
5652 12:11:41.202937 DQS0 = 0, DQS1 = 0
5653 12:11:41.205870 DQM Delay:
5654 12:11:41.205983 DQM0 = 102, DQM1 = 98
5655 12:11:41.208996 DQ Delay:
5656 12:11:41.212167 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5657 12:11:41.216012 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5658 12:11:41.219473 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5659 12:11:41.222196 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5660 12:11:41.222331
5661 12:11:41.222429
5662 12:11:41.222520 ==
5663 12:11:41.225673 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 12:11:41.229121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 12:11:41.229233 ==
5666 12:11:41.229303
5667 12:11:41.229367
5668 12:11:41.232458 TX Vref Scan disable
5669 12:11:41.235844 == TX Byte 0 ==
5670 12:11:41.239080 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5671 12:11:41.242417 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5672 12:11:41.245330 == TX Byte 1 ==
5673 12:11:41.249275 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 12:11:41.252075 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 12:11:41.252206 ==
5676 12:11:41.255356 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 12:11:41.258838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 12:11:41.262192 ==
5679 12:11:41.262322
5680 12:11:41.262423
5681 12:11:41.262520 TX Vref Scan disable
5682 12:11:41.265666 == TX Byte 0 ==
5683 12:11:41.269060 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5684 12:11:41.275567 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5685 12:11:41.275727 == TX Byte 1 ==
5686 12:11:41.278997 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5687 12:11:41.285935 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5688 12:11:41.286066
5689 12:11:41.286162 [DATLAT]
5690 12:11:41.286228 Freq=933, CH1 RK0
5691 12:11:41.286303
5692 12:11:41.289280 DATLAT Default: 0xd
5693 12:11:41.289366 0, 0xFFFF, sum = 0
5694 12:11:41.292621 1, 0xFFFF, sum = 0
5695 12:11:41.296086 2, 0xFFFF, sum = 0
5696 12:11:41.296194 3, 0xFFFF, sum = 0
5697 12:11:41.298749 4, 0xFFFF, sum = 0
5698 12:11:41.298841 5, 0xFFFF, sum = 0
5699 12:11:41.302003 6, 0xFFFF, sum = 0
5700 12:11:41.302102 7, 0xFFFF, sum = 0
5701 12:11:41.305828 8, 0xFFFF, sum = 0
5702 12:11:41.305928 9, 0xFFFF, sum = 0
5703 12:11:41.309214 10, 0x0, sum = 1
5704 12:11:41.309363 11, 0x0, sum = 2
5705 12:11:41.312552 12, 0x0, sum = 3
5706 12:11:41.312660 13, 0x0, sum = 4
5707 12:11:41.312733 best_step = 11
5708 12:11:41.312799
5709 12:11:41.315784 ==
5710 12:11:41.319097 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 12:11:41.322407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 12:11:41.322511 ==
5713 12:11:41.322585 RX Vref Scan: 1
5714 12:11:41.322649
5715 12:11:41.325805 RX Vref 0 -> 0, step: 1
5716 12:11:41.325893
5717 12:11:41.328464 RX Delay -45 -> 252, step: 4
5718 12:11:41.328554
5719 12:11:41.331921 Set Vref, RX VrefLevel [Byte0]: 55
5720 12:11:41.335423 [Byte1]: 48
5721 12:11:41.335524
5722 12:11:41.338810 Final RX Vref Byte 0 = 55 to rank0
5723 12:11:41.342368 Final RX Vref Byte 1 = 48 to rank0
5724 12:11:41.344985 Final RX Vref Byte 0 = 55 to rank1
5725 12:11:41.348894 Final RX Vref Byte 1 = 48 to rank1==
5726 12:11:41.352257 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 12:11:41.354960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 12:11:41.358475 ==
5729 12:11:41.358578 DQS Delay:
5730 12:11:41.358649 DQS0 = 0, DQS1 = 0
5731 12:11:41.361971 DQM Delay:
5732 12:11:41.362091 DQM0 = 104, DQM1 = 100
5733 12:11:41.365409 DQ Delay:
5734 12:11:41.368240 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5735 12:11:41.371535 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =104
5736 12:11:41.375404 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =92
5737 12:11:41.378069 DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =110
5738 12:11:41.378208
5739 12:11:41.378307
5740 12:11:41.385022 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5741 12:11:41.388445 CH1 RK0: MR19=505, MR18=162E
5742 12:11:41.395045 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5743 12:11:41.395211
5744 12:11:41.398518 ----->DramcWriteLeveling(PI) begin...
5745 12:11:41.398639 ==
5746 12:11:41.401898 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 12:11:41.405330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 12:11:41.405427 ==
5749 12:11:41.408711 Write leveling (Byte 0): 26 => 26
5750 12:11:41.411829 Write leveling (Byte 1): 31 => 31
5751 12:11:41.414998 DramcWriteLeveling(PI) end<-----
5752 12:11:41.415115
5753 12:11:41.415215 ==
5754 12:11:41.418914 Dram Type= 6, Freq= 0, CH_1, rank 1
5755 12:11:41.421530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 12:11:41.424913 ==
5757 12:11:41.425019 [Gating] SW mode calibration
5758 12:11:41.435097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5759 12:11:41.438454 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5760 12:11:41.441766 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 12:11:41.448032 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 12:11:41.451522 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 12:11:41.454835 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 12:11:41.461546 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 12:11:41.464954 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5766 12:11:41.468472 0 14 24 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (1 0)
5767 12:11:41.474511 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5768 12:11:41.477857 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5769 12:11:41.481103 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 12:11:41.487913 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:11:41.491280 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 12:11:41.494857 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 12:11:41.501521 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 12:11:41.504945 0 15 24 | B1->B0 | 3333 2a2a | 0 0 | (1 1) (0 0)
5775 12:11:41.508219 0 15 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5776 12:11:41.515061 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 12:11:41.518373 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:11:41.521495 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:11:41.524651 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 12:11:41.531119 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:11:41.534950 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 12:11:41.538134 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5783 12:11:41.544725 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:11:41.548052 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:11:41.551422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:11:41.558328 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:11:41.561639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:11:41.564855 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:11:41.571061 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:11:41.574461 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:11:41.577988 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:11:41.584654 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:11:41.588012 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:11:41.591447 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:11:41.598221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:11:41.601624 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:11:41.604938 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:11:41.611543 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5799 12:11:41.614327 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5800 12:11:41.617821 Total UI for P1: 0, mck2ui 16
5801 12:11:41.621128 best dqsien dly found for B1: ( 1, 2, 24)
5802 12:11:41.624617 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:11:41.627852 Total UI for P1: 0, mck2ui 16
5804 12:11:41.630883 best dqsien dly found for B0: ( 1, 2, 26)
5805 12:11:41.634134 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5806 12:11:41.638021 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5807 12:11:41.638138
5808 12:11:41.641268 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5809 12:11:41.647550 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5810 12:11:41.647682 [Gating] SW calibration Done
5811 12:11:41.650785 ==
5812 12:11:41.650884 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 12:11:41.657436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 12:11:41.657602 ==
5815 12:11:41.657681 RX Vref Scan: 0
5816 12:11:41.657746
5817 12:11:41.660867 RX Vref 0 -> 0, step: 1
5818 12:11:41.660959
5819 12:11:41.664459 RX Delay -80 -> 252, step: 8
5820 12:11:41.667755 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5821 12:11:41.670945 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5822 12:11:41.674112 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5823 12:11:41.677418 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5824 12:11:41.684134 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5825 12:11:41.687483 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5826 12:11:41.690689 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5827 12:11:41.694087 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5828 12:11:41.697698 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5829 12:11:41.700478 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5830 12:11:41.707147 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5831 12:11:41.710466 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5832 12:11:41.713794 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5833 12:11:41.717198 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5834 12:11:41.720771 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5835 12:11:41.727526 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5836 12:11:41.727689 ==
5837 12:11:41.730894 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 12:11:41.734423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 12:11:41.734523 ==
5840 12:11:41.734594 DQS Delay:
5841 12:11:41.737109 DQS0 = 0, DQS1 = 0
5842 12:11:41.737200 DQM Delay:
5843 12:11:41.740974 DQM0 = 102, DQM1 = 98
5844 12:11:41.741075 DQ Delay:
5845 12:11:41.744121 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5846 12:11:41.747244 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5847 12:11:41.750512 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5848 12:11:41.753895 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5849 12:11:41.754005
5850 12:11:41.754077
5851 12:11:41.754140 ==
5852 12:11:41.757715 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 12:11:41.760921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 12:11:41.764331 ==
5855 12:11:41.764429
5856 12:11:41.764512
5857 12:11:41.764577 TX Vref Scan disable
5858 12:11:41.767644 == TX Byte 0 ==
5859 12:11:41.770960 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 12:11:41.774206 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 12:11:41.777689 == TX Byte 1 ==
5862 12:11:41.780876 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5863 12:11:41.784102 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5864 12:11:41.787598 ==
5865 12:11:41.790991 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 12:11:41.794087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 12:11:41.794198 ==
5868 12:11:41.794271
5869 12:11:41.794334
5870 12:11:41.797598 TX Vref Scan disable
5871 12:11:41.797695 == TX Byte 0 ==
5872 12:11:41.803719 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5873 12:11:41.807064 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5874 12:11:41.807179 == TX Byte 1 ==
5875 12:11:41.813976 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5876 12:11:41.817390 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5877 12:11:41.817533
5878 12:11:41.817603 [DATLAT]
5879 12:11:41.820698 Freq=933, CH1 RK1
5880 12:11:41.820814
5881 12:11:41.820909 DATLAT Default: 0xb
5882 12:11:41.823594 0, 0xFFFF, sum = 0
5883 12:11:41.823686 1, 0xFFFF, sum = 0
5884 12:11:41.826902 2, 0xFFFF, sum = 0
5885 12:11:41.826998 3, 0xFFFF, sum = 0
5886 12:11:41.830417 4, 0xFFFF, sum = 0
5887 12:11:41.830518 5, 0xFFFF, sum = 0
5888 12:11:41.833874 6, 0xFFFF, sum = 0
5889 12:11:41.833987 7, 0xFFFF, sum = 0
5890 12:11:41.837244 8, 0xFFFF, sum = 0
5891 12:11:41.840584 9, 0xFFFF, sum = 0
5892 12:11:41.840690 10, 0x0, sum = 1
5893 12:11:41.840762 11, 0x0, sum = 2
5894 12:11:41.843952 12, 0x0, sum = 3
5895 12:11:41.844046 13, 0x0, sum = 4
5896 12:11:41.847301 best_step = 11
5897 12:11:41.847421
5898 12:11:41.847493 ==
5899 12:11:41.850640 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 12:11:41.853857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 12:11:41.853957 ==
5902 12:11:41.857425 RX Vref Scan: 0
5903 12:11:41.857527
5904 12:11:41.857596 RX Vref 0 -> 0, step: 1
5905 12:11:41.857660
5906 12:11:41.860117 RX Delay -45 -> 252, step: 4
5907 12:11:41.867289 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5908 12:11:41.870760 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5909 12:11:41.874137 iDelay=203, Bit 2, Center 96 (15 ~ 178) 164
5910 12:11:41.877622 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5911 12:11:41.880941 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5912 12:11:41.887670 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5913 12:11:41.890863 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5914 12:11:41.894293 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5915 12:11:41.897812 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5916 12:11:41.901043 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5917 12:11:41.907807 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5918 12:11:41.910564 iDelay=203, Bit 11, Center 96 (15 ~ 178) 164
5919 12:11:41.913955 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5920 12:11:41.917546 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5921 12:11:41.920796 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5922 12:11:41.927570 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5923 12:11:41.927697 ==
5924 12:11:41.931085 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 12:11:41.933888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 12:11:41.933985 ==
5927 12:11:41.934053 DQS Delay:
5928 12:11:41.937361 DQS0 = 0, DQS1 = 0
5929 12:11:41.937450 DQM Delay:
5930 12:11:41.940682 DQM0 = 105, DQM1 = 99
5931 12:11:41.940822 DQ Delay:
5932 12:11:41.944151 DQ0 =110, DQ1 =100, DQ2 =96, DQ3 =100
5933 12:11:41.947579 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5934 12:11:41.951067 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =96
5935 12:11:41.953884 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =108
5936 12:11:41.953976
5937 12:11:41.954088
5938 12:11:41.964283 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5939 12:11:41.967555 CH1 RK1: MR19=505, MR18=2D00
5940 12:11:41.970686 CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43
5941 12:11:41.973906 [RxdqsGatingPostProcess] freq 933
5942 12:11:41.980465 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5943 12:11:41.983807 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 12:11:41.987283 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 12:11:41.990535 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 12:11:41.993914 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 12:11:41.997211 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 12:11:42.000391 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 12:11:42.003733 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 12:11:42.007103 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 12:11:42.007232 Pre-setting of DQS Precalculation
5952 12:11:42.013853 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5953 12:11:42.020709 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5954 12:11:42.027493 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5955 12:11:42.027637
5956 12:11:42.027707
5957 12:11:42.030117 [Calibration Summary] 1866 Mbps
5958 12:11:42.033505 CH 0, Rank 0
5959 12:11:42.033624 SW Impedance : PASS
5960 12:11:42.037030 DUTY Scan : NO K
5961 12:11:42.040389 ZQ Calibration : PASS
5962 12:11:42.040516 Jitter Meter : NO K
5963 12:11:42.043776 CBT Training : PASS
5964 12:11:42.043904 Write leveling : PASS
5965 12:11:42.047200 RX DQS gating : PASS
5966 12:11:42.050644 RX DQ/DQS(RDDQC) : PASS
5967 12:11:42.050744 TX DQ/DQS : PASS
5968 12:11:42.053511 RX DATLAT : PASS
5969 12:11:42.056900 RX DQ/DQS(Engine): PASS
5970 12:11:42.057022 TX OE : NO K
5971 12:11:42.060317 All Pass.
5972 12:11:42.060446
5973 12:11:42.060530 CH 0, Rank 1
5974 12:11:42.063684 SW Impedance : PASS
5975 12:11:42.063769 DUTY Scan : NO K
5976 12:11:42.067065 ZQ Calibration : PASS
5977 12:11:42.070529 Jitter Meter : NO K
5978 12:11:42.070632 CBT Training : PASS
5979 12:11:42.073821 Write leveling : PASS
5980 12:11:42.077096 RX DQS gating : PASS
5981 12:11:42.077239 RX DQ/DQS(RDDQC) : PASS
5982 12:11:42.080345 TX DQ/DQS : PASS
5983 12:11:42.083471 RX DATLAT : PASS
5984 12:11:42.083589 RX DQ/DQS(Engine): PASS
5985 12:11:42.086825 TX OE : NO K
5986 12:11:42.086960 All Pass.
5987 12:11:42.087060
5988 12:11:42.090149 CH 1, Rank 0
5989 12:11:42.090267 SW Impedance : PASS
5990 12:11:42.093601 DUTY Scan : NO K
5991 12:11:42.097103 ZQ Calibration : PASS
5992 12:11:42.097209 Jitter Meter : NO K
5993 12:11:42.099870 CBT Training : PASS
5994 12:11:42.103183 Write leveling : PASS
5995 12:11:42.103317 RX DQS gating : PASS
5996 12:11:42.106433 RX DQ/DQS(RDDQC) : PASS
5997 12:11:42.109639 TX DQ/DQS : PASS
5998 12:11:42.109785 RX DATLAT : PASS
5999 12:11:42.112905 RX DQ/DQS(Engine): PASS
6000 12:11:42.113037 TX OE : NO K
6001 12:11:42.116946 All Pass.
6002 12:11:42.117073
6003 12:11:42.117171 CH 1, Rank 1
6004 12:11:42.119665 SW Impedance : PASS
6005 12:11:42.119778 DUTY Scan : NO K
6006 12:11:42.123099 ZQ Calibration : PASS
6007 12:11:42.126577 Jitter Meter : NO K
6008 12:11:42.126701 CBT Training : PASS
6009 12:11:42.129936 Write leveling : PASS
6010 12:11:42.133487 RX DQS gating : PASS
6011 12:11:42.133620 RX DQ/DQS(RDDQC) : PASS
6012 12:11:42.136770 TX DQ/DQS : PASS
6013 12:11:42.139571 RX DATLAT : PASS
6014 12:11:42.139694 RX DQ/DQS(Engine): PASS
6015 12:11:42.142834 TX OE : NO K
6016 12:11:42.142957 All Pass.
6017 12:11:42.143055
6018 12:11:42.146339 DramC Write-DBI off
6019 12:11:42.149570 PER_BANK_REFRESH: Hybrid Mode
6020 12:11:42.149694 TX_TRACKING: ON
6021 12:11:42.159898 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6022 12:11:42.162540 [FAST_K] Save calibration result to emmc
6023 12:11:42.165960 dramc_set_vcore_voltage set vcore to 650000
6024 12:11:42.169781 Read voltage for 400, 6
6025 12:11:42.169923 Vio18 = 0
6026 12:11:42.170024 Vcore = 650000
6027 12:11:42.173160 Vdram = 0
6028 12:11:42.173284 Vddq = 0
6029 12:11:42.173381 Vmddr = 0
6030 12:11:42.179711 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6031 12:11:42.182937 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6032 12:11:42.186348 MEM_TYPE=3, freq_sel=20
6033 12:11:42.189496 sv_algorithm_assistance_LP4_800
6034 12:11:42.192868 ============ PULL DRAM RESETB DOWN ============
6035 12:11:42.196159 ========== PULL DRAM RESETB DOWN end =========
6036 12:11:42.202931 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6037 12:11:42.206262 ===================================
6038 12:11:42.206403 LPDDR4 DRAM CONFIGURATION
6039 12:11:42.209741 ===================================
6040 12:11:42.212444 EX_ROW_EN[0] = 0x0
6041 12:11:42.216338 EX_ROW_EN[1] = 0x0
6042 12:11:42.216479 LP4Y_EN = 0x0
6043 12:11:42.219414 WORK_FSP = 0x0
6044 12:11:42.219534 WL = 0x2
6045 12:11:42.222514 RL = 0x2
6046 12:11:42.222633 BL = 0x2
6047 12:11:42.225773 RPST = 0x0
6048 12:11:42.225902 RD_PRE = 0x0
6049 12:11:42.229205 WR_PRE = 0x1
6050 12:11:42.229333 WR_PST = 0x0
6051 12:11:42.232649 DBI_WR = 0x0
6052 12:11:42.232772 DBI_RD = 0x0
6053 12:11:42.236006 OTF = 0x1
6054 12:11:42.239485 ===================================
6055 12:11:42.242860 ===================================
6056 12:11:42.242992 ANA top config
6057 12:11:42.246181 ===================================
6058 12:11:42.249658 DLL_ASYNC_EN = 0
6059 12:11:42.252466 ALL_SLAVE_EN = 1
6060 12:11:42.255888 NEW_RANK_MODE = 1
6061 12:11:42.256021 DLL_IDLE_MODE = 1
6062 12:11:42.259332 LP45_APHY_COMB_EN = 1
6063 12:11:42.262809 TX_ODT_DIS = 1
6064 12:11:42.266223 NEW_8X_MODE = 1
6065 12:11:42.269533 ===================================
6066 12:11:42.272900 ===================================
6067 12:11:42.273040 data_rate = 800
6068 12:11:42.276351 CKR = 1
6069 12:11:42.279702 DQ_P2S_RATIO = 4
6070 12:11:42.283146 ===================================
6071 12:11:42.285833 CA_P2S_RATIO = 4
6072 12:11:42.289620 DQ_CA_OPEN = 0
6073 12:11:42.292876 DQ_SEMI_OPEN = 1
6074 12:11:42.293008 CA_SEMI_OPEN = 1
6075 12:11:42.296149 CA_FULL_RATE = 0
6076 12:11:42.299289 DQ_CKDIV4_EN = 0
6077 12:11:42.302595 CA_CKDIV4_EN = 1
6078 12:11:42.305873 CA_PREDIV_EN = 0
6079 12:11:42.309298 PH8_DLY = 0
6080 12:11:42.309432 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6081 12:11:42.312681 DQ_AAMCK_DIV = 0
6082 12:11:42.316051 CA_AAMCK_DIV = 0
6083 12:11:42.319520 CA_ADMCK_DIV = 4
6084 12:11:42.322806 DQ_TRACK_CA_EN = 0
6085 12:11:42.326044 CA_PICK = 800
6086 12:11:42.329394 CA_MCKIO = 400
6087 12:11:42.329528 MCKIO_SEMI = 400
6088 12:11:42.332763 PLL_FREQ = 3016
6089 12:11:42.335893 DQ_UI_PI_RATIO = 32
6090 12:11:42.339165 CA_UI_PI_RATIO = 32
6091 12:11:42.342555 ===================================
6092 12:11:42.346085 ===================================
6093 12:11:42.349515 memory_type:LPDDR4
6094 12:11:42.349656 GP_NUM : 10
6095 12:11:42.352387 SRAM_EN : 1
6096 12:11:42.355827 MD32_EN : 0
6097 12:11:42.359205 ===================================
6098 12:11:42.359340 [ANA_INIT] >>>>>>>>>>>>>>
6099 12:11:42.362851 <<<<<< [CONFIGURE PHASE]: ANA_TX
6100 12:11:42.365570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6101 12:11:42.368870 ===================================
6102 12:11:42.372321 data_rate = 800,PCW = 0X7400
6103 12:11:42.375713 ===================================
6104 12:11:42.379649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6105 12:11:42.385833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6106 12:11:42.395812 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 12:11:42.398963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6108 12:11:42.402217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6109 12:11:42.409278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6110 12:11:42.409445 [ANA_INIT] flow start
6111 12:11:42.412462 [ANA_INIT] PLL >>>>>>>>
6112 12:11:42.412600 [ANA_INIT] PLL <<<<<<<<
6113 12:11:42.415819 [ANA_INIT] MIDPI >>>>>>>>
6114 12:11:42.419225 [ANA_INIT] MIDPI <<<<<<<<
6115 12:11:42.422754 [ANA_INIT] DLL >>>>>>>>
6116 12:11:42.422882 [ANA_INIT] flow end
6117 12:11:42.425575 ============ LP4 DIFF to SE enter ============
6118 12:11:42.432175 ============ LP4 DIFF to SE exit ============
6119 12:11:42.432343 [ANA_INIT] <<<<<<<<<<<<<
6120 12:11:42.435481 [Flow] Enable top DCM control >>>>>
6121 12:11:42.438864 [Flow] Enable top DCM control <<<<<
6122 12:11:42.442199 Enable DLL master slave shuffle
6123 12:11:42.448809 ==============================================================
6124 12:11:42.448979 Gating Mode config
6125 12:11:42.455671 ==============================================================
6126 12:11:42.459005 Config description:
6127 12:11:42.468581 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6128 12:11:42.475457 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6129 12:11:42.478828 SELPH_MODE 0: By rank 1: By Phase
6130 12:11:42.485603 ==============================================================
6131 12:11:42.488998 GAT_TRACK_EN = 0
6132 12:11:42.491823 RX_GATING_MODE = 2
6133 12:11:42.491954 RX_GATING_TRACK_MODE = 2
6134 12:11:42.495136 SELPH_MODE = 1
6135 12:11:42.498648 PICG_EARLY_EN = 1
6136 12:11:42.501784 VALID_LAT_VALUE = 1
6137 12:11:42.508865 ==============================================================
6138 12:11:42.512050 Enter into Gating configuration >>>>
6139 12:11:42.515174 Exit from Gating configuration <<<<
6140 12:11:42.518386 Enter into DVFS_PRE_config >>>>>
6141 12:11:42.528647 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6142 12:11:42.531990 Exit from DVFS_PRE_config <<<<<
6143 12:11:42.535237 Enter into PICG configuration >>>>
6144 12:11:42.538533 Exit from PICG configuration <<<<
6145 12:11:42.541801 [RX_INPUT] configuration >>>>>
6146 12:11:42.545216 [RX_INPUT] configuration <<<<<
6147 12:11:42.548516 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6148 12:11:42.554931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6149 12:11:42.561579 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 12:11:42.564887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 12:11:42.571692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 12:11:42.578680 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 12:11:42.582231 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6154 12:11:42.588729 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6155 12:11:42.591554 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6156 12:11:42.594949 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6157 12:11:42.598324 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6158 12:11:42.605095 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 12:11:42.608603 ===================================
6160 12:11:42.608701 LPDDR4 DRAM CONFIGURATION
6161 12:11:42.611895 ===================================
6162 12:11:42.615130 EX_ROW_EN[0] = 0x0
6163 12:11:42.618195 EX_ROW_EN[1] = 0x0
6164 12:11:42.618315 LP4Y_EN = 0x0
6165 12:11:42.621342 WORK_FSP = 0x0
6166 12:11:42.621468 WL = 0x2
6167 12:11:42.624624 RL = 0x2
6168 12:11:42.624719 BL = 0x2
6169 12:11:42.628440 RPST = 0x0
6170 12:11:42.628567 RD_PRE = 0x0
6171 12:11:42.631671 WR_PRE = 0x1
6172 12:11:42.631790 WR_PST = 0x0
6173 12:11:42.635000 DBI_WR = 0x0
6174 12:11:42.635114 DBI_RD = 0x0
6175 12:11:42.638497 OTF = 0x1
6176 12:11:42.641781 ===================================
6177 12:11:42.645056 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6178 12:11:42.647874 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6179 12:11:42.654606 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 12:11:42.658157 ===================================
6181 12:11:42.658287 LPDDR4 DRAM CONFIGURATION
6182 12:11:42.661125 ===================================
6183 12:11:42.665143 EX_ROW_EN[0] = 0x10
6184 12:11:42.665292 EX_ROW_EN[1] = 0x0
6185 12:11:42.668434 LP4Y_EN = 0x0
6186 12:11:42.671847 WORK_FSP = 0x0
6187 12:11:42.671948 WL = 0x2
6188 12:11:42.674577 RL = 0x2
6189 12:11:42.674671 BL = 0x2
6190 12:11:42.678198 RPST = 0x0
6191 12:11:42.678288 RD_PRE = 0x0
6192 12:11:42.681641 WR_PRE = 0x1
6193 12:11:42.681736 WR_PST = 0x0
6194 12:11:42.684996 DBI_WR = 0x0
6195 12:11:42.685088 DBI_RD = 0x0
6196 12:11:42.688374 OTF = 0x1
6197 12:11:42.691575 ===================================
6198 12:11:42.697796 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6199 12:11:42.701196 nWR fixed to 30
6200 12:11:42.701319 [ModeRegInit_LP4] CH0 RK0
6201 12:11:42.704548 [ModeRegInit_LP4] CH0 RK1
6202 12:11:42.707954 [ModeRegInit_LP4] CH1 RK0
6203 12:11:42.708048 [ModeRegInit_LP4] CH1 RK1
6204 12:11:42.711522 match AC timing 19
6205 12:11:42.714332 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6206 12:11:42.718294 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6207 12:11:42.724787 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6208 12:11:42.728022 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6209 12:11:42.734433 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6210 12:11:42.734562 ==
6211 12:11:42.737759 Dram Type= 6, Freq= 0, CH_0, rank 0
6212 12:11:42.740955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6213 12:11:42.741076 ==
6214 12:11:42.748126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6215 12:11:42.751427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6216 12:11:42.754748 [CA 0] Center 36 (8~64) winsize 57
6217 12:11:42.757585 [CA 1] Center 36 (8~64) winsize 57
6218 12:11:42.760964 [CA 2] Center 36 (8~64) winsize 57
6219 12:11:42.764435 [CA 3] Center 36 (8~64) winsize 57
6220 12:11:42.767915 [CA 4] Center 36 (8~64) winsize 57
6221 12:11:42.771117 [CA 5] Center 36 (8~64) winsize 57
6222 12:11:42.771232
6223 12:11:42.774332 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6224 12:11:42.774461
6225 12:11:42.777640 [CATrainingPosCal] consider 1 rank data
6226 12:11:42.781066 u2DelayCellTimex100 = 270/100 ps
6227 12:11:42.784585 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 12:11:42.787991 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 12:11:42.791519 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:11:42.798147 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:11:42.801567 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:11:42.804986 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:11:42.805121
6234 12:11:42.808275 CA PerBit enable=1, Macro0, CA PI delay=36
6235 12:11:42.808401
6236 12:11:42.811134 [CBTSetCACLKResult] CA Dly = 36
6237 12:11:42.811280 CS Dly: 1 (0~32)
6238 12:11:42.811396 ==
6239 12:11:42.814632 Dram Type= 6, Freq= 0, CH_0, rank 1
6240 12:11:42.821614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6241 12:11:42.821783 ==
6242 12:11:42.824749 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6243 12:11:42.830916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6244 12:11:42.834151 [CA 0] Center 36 (8~64) winsize 57
6245 12:11:42.837842 [CA 1] Center 36 (8~64) winsize 57
6246 12:11:42.841137 [CA 2] Center 36 (8~64) winsize 57
6247 12:11:42.844377 [CA 3] Center 36 (8~64) winsize 57
6248 12:11:42.847679 [CA 4] Center 36 (8~64) winsize 57
6249 12:11:42.851078 [CA 5] Center 36 (8~64) winsize 57
6250 12:11:42.851211
6251 12:11:42.854455 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6252 12:11:42.854582
6253 12:11:42.857796 [CATrainingPosCal] consider 2 rank data
6254 12:11:42.861175 u2DelayCellTimex100 = 270/100 ps
6255 12:11:42.863975 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:11:42.867407 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:11:42.870665 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:11:42.874035 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:11:42.877430 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:11:42.880699 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:11:42.883822
6262 12:11:42.887403 CA PerBit enable=1, Macro0, CA PI delay=36
6263 12:11:42.887547
6264 12:11:42.890838 [CBTSetCACLKResult] CA Dly = 36
6265 12:11:42.890977 CS Dly: 1 (0~32)
6266 12:11:42.891088
6267 12:11:42.893697 ----->DramcWriteLeveling(PI) begin...
6268 12:11:42.893818 ==
6269 12:11:42.897664 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 12:11:42.900875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 12:11:42.904274 ==
6272 12:11:42.904409 Write leveling (Byte 0): 40 => 8
6273 12:11:42.906980 Write leveling (Byte 1): 40 => 8
6274 12:11:42.910225 DramcWriteLeveling(PI) end<-----
6275 12:11:42.910354
6276 12:11:42.910463 ==
6277 12:11:42.913768 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 12:11:42.920788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:11:42.920956 ==
6280 12:11:42.921067 [Gating] SW mode calibration
6281 12:11:42.930326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6282 12:11:42.934319 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6283 12:11:42.937163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6284 12:11:42.944429 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 12:11:42.947546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6286 12:11:42.950439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 12:11:42.957657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 12:11:42.960989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 12:11:42.964164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 12:11:42.970351 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 12:11:42.973701 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 12:11:42.977145 Total UI for P1: 0, mck2ui 16
6293 12:11:42.980477 best dqsien dly found for B0: ( 0, 14, 24)
6294 12:11:42.983835 Total UI for P1: 0, mck2ui 16
6295 12:11:42.987201 best dqsien dly found for B1: ( 0, 14, 24)
6296 12:11:42.990436 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6297 12:11:42.993689 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6298 12:11:42.993829
6299 12:11:42.997314 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6300 12:11:43.000719 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 12:11:43.004063 [Gating] SW calibration Done
6302 12:11:43.004198 ==
6303 12:11:43.007523 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 12:11:43.010280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 12:11:43.010400 ==
6306 12:11:43.013617 RX Vref Scan: 0
6307 12:11:43.013755
6308 12:11:43.017007 RX Vref 0 -> 0, step: 1
6309 12:11:43.017132
6310 12:11:43.020483 RX Delay -410 -> 252, step: 16
6311 12:11:43.023898 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6312 12:11:43.027419 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6313 12:11:43.030742 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6314 12:11:43.037398 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6315 12:11:43.040106 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6316 12:11:43.043659 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6317 12:11:43.046888 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6318 12:11:43.053409 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6319 12:11:43.057286 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6320 12:11:43.060643 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6321 12:11:43.063989 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6322 12:11:43.070114 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6323 12:11:43.073508 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6324 12:11:43.076938 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6325 12:11:43.080337 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6326 12:11:43.087175 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6327 12:11:43.087301 ==
6328 12:11:43.089876 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 12:11:43.093282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 12:11:43.093400 ==
6331 12:11:43.093499 DQS Delay:
6332 12:11:43.096582 DQS0 = 27, DQS1 = 35
6333 12:11:43.096663 DQM Delay:
6334 12:11:43.100457 DQM0 = 10, DQM1 = 12
6335 12:11:43.100553 DQ Delay:
6336 12:11:43.103797 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6337 12:11:43.107008 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6338 12:11:43.110200 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6339 12:11:43.113432 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6340 12:11:43.113540
6341 12:11:43.113607
6342 12:11:43.113672 ==
6343 12:11:43.116893 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 12:11:43.120265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 12:11:43.120352 ==
6346 12:11:43.120415
6347 12:11:43.120474
6348 12:11:43.123728 TX Vref Scan disable
6349 12:11:43.127046 == TX Byte 0 ==
6350 12:11:43.129878 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 12:11:43.133199 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 12:11:43.133320 == TX Byte 1 ==
6353 12:11:43.140087 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 12:11:43.143596 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 12:11:43.143724 ==
6356 12:11:43.146934 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 12:11:43.150357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 12:11:43.150481 ==
6359 12:11:43.150577
6360 12:11:43.150666
6361 12:11:43.153080 TX Vref Scan disable
6362 12:11:43.156567 == TX Byte 0 ==
6363 12:11:43.159783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 12:11:43.163029 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 12:11:43.166969 == TX Byte 1 ==
6366 12:11:43.170392 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 12:11:43.173592 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 12:11:43.173710
6369 12:11:43.173807 [DATLAT]
6370 12:11:43.177015 Freq=400, CH0 RK0
6371 12:11:43.177140
6372 12:11:43.177233 DATLAT Default: 0xf
6373 12:11:43.180426 0, 0xFFFF, sum = 0
6374 12:11:43.180550 1, 0xFFFF, sum = 0
6375 12:11:43.183668 2, 0xFFFF, sum = 0
6376 12:11:43.183747 3, 0xFFFF, sum = 0
6377 12:11:43.186398 4, 0xFFFF, sum = 0
6378 12:11:43.186512 5, 0xFFFF, sum = 0
6379 12:11:43.189831 6, 0xFFFF, sum = 0
6380 12:11:43.193276 7, 0xFFFF, sum = 0
6381 12:11:43.193376 8, 0xFFFF, sum = 0
6382 12:11:43.196612 9, 0xFFFF, sum = 0
6383 12:11:43.196701 10, 0xFFFF, sum = 0
6384 12:11:43.199982 11, 0xFFFF, sum = 0
6385 12:11:43.200070 12, 0xFFFF, sum = 0
6386 12:11:43.203384 13, 0x0, sum = 1
6387 12:11:43.203508 14, 0x0, sum = 2
6388 12:11:43.206706 15, 0x0, sum = 3
6389 12:11:43.206821 16, 0x0, sum = 4
6390 12:11:43.209995 best_step = 14
6391 12:11:43.210122
6392 12:11:43.210224 ==
6393 12:11:43.213137 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:11:43.216353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:11:43.216460 ==
6396 12:11:43.216539 RX Vref Scan: 1
6397 12:11:43.216601
6398 12:11:43.219805 RX Vref 0 -> 0, step: 1
6399 12:11:43.219916
6400 12:11:43.223088 RX Delay -311 -> 252, step: 8
6401 12:11:43.223200
6402 12:11:43.226661 Set Vref, RX VrefLevel [Byte0]: 55
6403 12:11:43.230060 [Byte1]: 48
6404 12:11:43.233665
6405 12:11:43.233755 Final RX Vref Byte 0 = 55 to rank0
6406 12:11:43.237125 Final RX Vref Byte 1 = 48 to rank0
6407 12:11:43.239941 Final RX Vref Byte 0 = 55 to rank1
6408 12:11:43.243319 Final RX Vref Byte 1 = 48 to rank1==
6409 12:11:43.247330 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 12:11:43.253762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 12:11:43.253890 ==
6412 12:11:43.253966 DQS Delay:
6413 12:11:43.257162 DQS0 = 28, DQS1 = 32
6414 12:11:43.257260 DQM Delay:
6415 12:11:43.257329 DQM0 = 11, DQM1 = 9
6416 12:11:43.260542 DQ Delay:
6417 12:11:43.263815 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6418 12:11:43.263920 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6419 12:11:43.266989 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6420 12:11:43.270343 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6421 12:11:43.270443
6422 12:11:43.270518
6423 12:11:43.280323 [DQSOSCAuto] RK0, (LSB)MR18= 0xc7b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6424 12:11:43.283567 CH0 RK0: MR19=C0C, MR18=C7B3
6425 12:11:43.290254 CH0_RK0: MR19=0xC0C, MR18=0xC7B3, DQSOSC=385, MR23=63, INC=398, DEC=265
6426 12:11:43.290404 ==
6427 12:11:43.293787 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 12:11:43.297279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 12:11:43.297373 ==
6430 12:11:43.300711 [Gating] SW mode calibration
6431 12:11:43.306846 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6432 12:11:43.310261 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6433 12:11:43.316932 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6434 12:11:43.320289 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 12:11:43.323418 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6436 12:11:43.330270 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 12:11:43.333646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 12:11:43.337032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 12:11:43.343217 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 12:11:43.346513 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 12:11:43.349803 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 12:11:43.353192 Total UI for P1: 0, mck2ui 16
6443 12:11:43.356667 best dqsien dly found for B0: ( 0, 14, 24)
6444 12:11:43.360043 Total UI for P1: 0, mck2ui 16
6445 12:11:43.363443 best dqsien dly found for B1: ( 0, 14, 24)
6446 12:11:43.366931 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6447 12:11:43.370184 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6448 12:11:43.370284
6449 12:11:43.376526 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6450 12:11:43.379859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 12:11:43.383074 [Gating] SW calibration Done
6452 12:11:43.383202 ==
6453 12:11:43.386429 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 12:11:43.389855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 12:11:43.390010 ==
6456 12:11:43.390118 RX Vref Scan: 0
6457 12:11:43.390239
6458 12:11:43.393091 RX Vref 0 -> 0, step: 1
6459 12:11:43.393206
6460 12:11:43.396462 RX Delay -410 -> 252, step: 16
6461 12:11:43.399862 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6462 12:11:43.406685 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6463 12:11:43.409970 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6464 12:11:43.413217 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6465 12:11:43.416664 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6466 12:11:43.420174 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6467 12:11:43.426815 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6468 12:11:43.429953 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6469 12:11:43.433070 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6470 12:11:43.436406 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6471 12:11:43.443204 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6472 12:11:43.446707 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6473 12:11:43.450006 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6474 12:11:43.453523 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6475 12:11:43.460168 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6476 12:11:43.463592 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6477 12:11:43.463695 ==
6478 12:11:43.466900 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 12:11:43.469707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 12:11:43.469797 ==
6481 12:11:43.473114 DQS Delay:
6482 12:11:43.473198 DQS0 = 27, DQS1 = 35
6483 12:11:43.476457 DQM Delay:
6484 12:11:43.476547 DQM0 = 12, DQM1 = 12
6485 12:11:43.476614 DQ Delay:
6486 12:11:43.479900 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6487 12:11:43.483128 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6488 12:11:43.486365 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6489 12:11:43.489650 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6490 12:11:43.489771
6491 12:11:43.489843
6492 12:11:43.489906 ==
6493 12:11:43.493584 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 12:11:43.500182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 12:11:43.500321 ==
6496 12:11:43.500395
6497 12:11:43.500459
6498 12:11:43.500520 TX Vref Scan disable
6499 12:11:43.503518 == TX Byte 0 ==
6500 12:11:43.506939 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 12:11:43.509608 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 12:11:43.513178 == TX Byte 1 ==
6503 12:11:43.516556 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6504 12:11:43.519811 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6505 12:11:43.519926 ==
6506 12:11:43.523210 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 12:11:43.530013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 12:11:43.530179 ==
6509 12:11:43.530285
6510 12:11:43.530377
6511 12:11:43.530467 TX Vref Scan disable
6512 12:11:43.533476 == TX Byte 0 ==
6513 12:11:43.536630 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6514 12:11:43.539746 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6515 12:11:43.542766 == TX Byte 1 ==
6516 12:11:43.546099 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6517 12:11:43.549521 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6518 12:11:43.549626
6519 12:11:43.552931 [DATLAT]
6520 12:11:43.553073 Freq=400, CH0 RK1
6521 12:11:43.553177
6522 12:11:43.556359 DATLAT Default: 0xe
6523 12:11:43.556487 0, 0xFFFF, sum = 0
6524 12:11:43.559671 1, 0xFFFF, sum = 0
6525 12:11:43.559786 2, 0xFFFF, sum = 0
6526 12:11:43.563087 3, 0xFFFF, sum = 0
6527 12:11:43.563207 4, 0xFFFF, sum = 0
6528 12:11:43.566629 5, 0xFFFF, sum = 0
6529 12:11:43.566724 6, 0xFFFF, sum = 0
6530 12:11:43.569354 7, 0xFFFF, sum = 0
6531 12:11:43.569464 8, 0xFFFF, sum = 0
6532 12:11:43.572882 9, 0xFFFF, sum = 0
6533 12:11:43.572964 10, 0xFFFF, sum = 0
6534 12:11:43.576221 11, 0xFFFF, sum = 0
6535 12:11:43.576316 12, 0xFFFF, sum = 0
6536 12:11:43.579634 13, 0x0, sum = 1
6537 12:11:43.579731 14, 0x0, sum = 2
6538 12:11:43.583088 15, 0x0, sum = 3
6539 12:11:43.583183 16, 0x0, sum = 4
6540 12:11:43.586410 best_step = 14
6541 12:11:43.586532
6542 12:11:43.586609 ==
6543 12:11:43.589753 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:11:43.593016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:11:43.593118 ==
6546 12:11:43.596341 RX Vref Scan: 0
6547 12:11:43.596439
6548 12:11:43.596507 RX Vref 0 -> 0, step: 1
6549 12:11:43.596571
6550 12:11:43.599618 RX Delay -311 -> 252, step: 8
6551 12:11:43.607626 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6552 12:11:43.610884 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6553 12:11:43.614369 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6554 12:11:43.617673 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6555 12:11:43.624176 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6556 12:11:43.627472 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6557 12:11:43.631011 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6558 12:11:43.634369 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6559 12:11:43.640625 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6560 12:11:43.643876 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6561 12:11:43.647216 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6562 12:11:43.650535 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6563 12:11:43.657190 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6564 12:11:43.660432 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6565 12:11:43.663865 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6566 12:11:43.670560 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6567 12:11:43.670708 ==
6568 12:11:43.674026 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 12:11:43.677379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 12:11:43.677480 ==
6571 12:11:43.677568 DQS Delay:
6572 12:11:43.680875 DQS0 = 24, DQS1 = 32
6573 12:11:43.680969 DQM Delay:
6574 12:11:43.684310 DQM0 = 9, DQM1 = 11
6575 12:11:43.684394 DQ Delay:
6576 12:11:43.687052 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6577 12:11:43.690511 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6578 12:11:43.693749 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6579 12:11:43.697027 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6580 12:11:43.697158
6581 12:11:43.697254
6582 12:11:43.704058 [DQSOSCAuto] RK1, (LSB)MR18= 0xb656, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6583 12:11:43.707441 CH0 RK1: MR19=C0C, MR18=B656
6584 12:11:43.713802 CH0_RK1: MR19=0xC0C, MR18=0xB656, DQSOSC=387, MR23=63, INC=394, DEC=262
6585 12:11:43.717161 [RxdqsGatingPostProcess] freq 400
6586 12:11:43.720746 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6587 12:11:43.723858 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 12:11:43.727206 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 12:11:43.730543 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 12:11:43.733989 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 12:11:43.736810 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 12:11:43.740196 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 12:11:43.743667 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 12:11:43.746983 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 12:11:43.750354 Pre-setting of DQS Precalculation
6596 12:11:43.753777 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6597 12:11:43.757047 ==
6598 12:11:43.760433 Dram Type= 6, Freq= 0, CH_1, rank 0
6599 12:11:43.763876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 12:11:43.763983 ==
6601 12:11:43.767232 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6602 12:11:43.773847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6603 12:11:43.777227 [CA 0] Center 36 (8~64) winsize 57
6604 12:11:43.779901 [CA 1] Center 36 (8~64) winsize 57
6605 12:11:43.783296 [CA 2] Center 36 (8~64) winsize 57
6606 12:11:43.786863 [CA 3] Center 36 (8~64) winsize 57
6607 12:11:43.790271 [CA 4] Center 36 (8~64) winsize 57
6608 12:11:43.793010 [CA 5] Center 36 (8~64) winsize 57
6609 12:11:43.793111
6610 12:11:43.796320 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6611 12:11:43.796450
6612 12:11:43.799865 [CATrainingPosCal] consider 1 rank data
6613 12:11:43.803167 u2DelayCellTimex100 = 270/100 ps
6614 12:11:43.806361 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 12:11:43.809534 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 12:11:43.812814 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:11:43.819635 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:11:43.822781 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:11:43.826204 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:11:43.826315
6621 12:11:43.829711 CA PerBit enable=1, Macro0, CA PI delay=36
6622 12:11:43.829810
6623 12:11:43.833071 [CBTSetCACLKResult] CA Dly = 36
6624 12:11:43.833229 CS Dly: 1 (0~32)
6625 12:11:43.833375 ==
6626 12:11:43.836506 Dram Type= 6, Freq= 0, CH_1, rank 1
6627 12:11:43.842745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 12:11:43.842913 ==
6629 12:11:43.846167 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6630 12:11:43.852879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6631 12:11:43.856114 [CA 0] Center 36 (8~64) winsize 57
6632 12:11:43.859510 [CA 1] Center 36 (8~64) winsize 57
6633 12:11:43.862869 [CA 2] Center 36 (8~64) winsize 57
6634 12:11:43.866167 [CA 3] Center 36 (8~64) winsize 57
6635 12:11:43.869414 [CA 4] Center 36 (8~64) winsize 57
6636 12:11:43.872524 [CA 5] Center 36 (8~64) winsize 57
6637 12:11:43.872662
6638 12:11:43.875810 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6639 12:11:43.875955
6640 12:11:43.879231 [CATrainingPosCal] consider 2 rank data
6641 12:11:43.882640 u2DelayCellTimex100 = 270/100 ps
6642 12:11:43.886067 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:11:43.889575 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:11:43.892901 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:11:43.895707 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:11:43.899242 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:11:43.902543 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:11:43.905924
6649 12:11:43.909154 CA PerBit enable=1, Macro0, CA PI delay=36
6650 12:11:43.909303
6651 12:11:43.912512 [CBTSetCACLKResult] CA Dly = 36
6652 12:11:43.912662 CS Dly: 1 (0~32)
6653 12:11:43.912764
6654 12:11:43.915895 ----->DramcWriteLeveling(PI) begin...
6655 12:11:43.916053 ==
6656 12:11:43.919133 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 12:11:43.922828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 12:11:43.922966 ==
6659 12:11:43.925552 Write leveling (Byte 0): 40 => 8
6660 12:11:43.928898 Write leveling (Byte 1): 40 => 8
6661 12:11:43.932718 DramcWriteLeveling(PI) end<-----
6662 12:11:43.932874
6663 12:11:43.932982 ==
6664 12:11:43.935487 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 12:11:43.942276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:11:43.942446 ==
6667 12:11:43.942572 [Gating] SW mode calibration
6668 12:11:43.952583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6669 12:11:43.956039 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6670 12:11:43.959412 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6671 12:11:43.965450 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 12:11:43.968911 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6673 12:11:43.972240 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 12:11:43.979193 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 12:11:43.982428 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 12:11:43.985967 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 12:11:43.992212 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 12:11:43.995385 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 12:11:43.998833 Total UI for P1: 0, mck2ui 16
6680 12:11:44.002525 best dqsien dly found for B0: ( 0, 14, 24)
6681 12:11:44.005940 Total UI for P1: 0, mck2ui 16
6682 12:11:44.009314 best dqsien dly found for B1: ( 0, 14, 24)
6683 12:11:44.012020 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6684 12:11:44.015385 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6685 12:11:44.015517
6686 12:11:44.018713 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6687 12:11:44.022136 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 12:11:44.025321 [Gating] SW calibration Done
6689 12:11:44.025420 ==
6690 12:11:44.029289 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 12:11:44.032445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 12:11:44.035745 ==
6693 12:11:44.035849 RX Vref Scan: 0
6694 12:11:44.035917
6695 12:11:44.039038 RX Vref 0 -> 0, step: 1
6696 12:11:44.039135
6697 12:11:44.042190 RX Delay -410 -> 252, step: 16
6698 12:11:44.045457 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6699 12:11:44.048912 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6700 12:11:44.052382 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6701 12:11:44.059121 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6702 12:11:44.062527 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6703 12:11:44.065938 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6704 12:11:44.068716 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6705 12:11:44.075537 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6706 12:11:44.078844 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6707 12:11:44.082223 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6708 12:11:44.085555 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6709 12:11:44.091974 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6710 12:11:44.095457 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6711 12:11:44.098814 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6712 12:11:44.102341 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6713 12:11:44.108490 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6714 12:11:44.108655 ==
6715 12:11:44.111845 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 12:11:44.115430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 12:11:44.115551 ==
6718 12:11:44.115621 DQS Delay:
6719 12:11:44.118981 DQS0 = 35, DQS1 = 35
6720 12:11:44.119097 DQM Delay:
6721 12:11:44.121763 DQM0 = 17, DQM1 = 13
6722 12:11:44.121885 DQ Delay:
6723 12:11:44.125935 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6724 12:11:44.128565 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6725 12:11:44.132301 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6726 12:11:44.135469 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6727 12:11:44.135568
6728 12:11:44.135637
6729 12:11:44.135699 ==
6730 12:11:44.138814 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 12:11:44.142133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 12:11:44.142249 ==
6733 12:11:44.142344
6734 12:11:44.142442
6735 12:11:44.145501 TX Vref Scan disable
6736 12:11:44.148888 == TX Byte 0 ==
6737 12:11:44.152101 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 12:11:44.155574 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 12:11:44.158307 == TX Byte 1 ==
6740 12:11:44.161760 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 12:11:44.165165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 12:11:44.165286 ==
6743 12:11:44.168438 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 12:11:44.171754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 12:11:44.171849 ==
6746 12:11:44.175094
6747 12:11:44.175206
6748 12:11:44.175298 TX Vref Scan disable
6749 12:11:44.178498 == TX Byte 0 ==
6750 12:11:44.181975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 12:11:44.185388 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 12:11:44.188875 == TX Byte 1 ==
6753 12:11:44.192076 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 12:11:44.195460 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 12:11:44.195590
6756 12:11:44.195684 [DATLAT]
6757 12:11:44.198694 Freq=400, CH1 RK0
6758 12:11:44.198779
6759 12:11:44.198845 DATLAT Default: 0xf
6760 12:11:44.201880 0, 0xFFFF, sum = 0
6761 12:11:44.205290 1, 0xFFFF, sum = 0
6762 12:11:44.205382 2, 0xFFFF, sum = 0
6763 12:11:44.208746 3, 0xFFFF, sum = 0
6764 12:11:44.208841 4, 0xFFFF, sum = 0
6765 12:11:44.211493 5, 0xFFFF, sum = 0
6766 12:11:44.211582 6, 0xFFFF, sum = 0
6767 12:11:44.214934 7, 0xFFFF, sum = 0
6768 12:11:44.215074 8, 0xFFFF, sum = 0
6769 12:11:44.218341 9, 0xFFFF, sum = 0
6770 12:11:44.218435 10, 0xFFFF, sum = 0
6771 12:11:44.221777 11, 0xFFFF, sum = 0
6772 12:11:44.221871 12, 0xFFFF, sum = 0
6773 12:11:44.224642 13, 0x0, sum = 1
6774 12:11:44.224733 14, 0x0, sum = 2
6775 12:11:44.227953 15, 0x0, sum = 3
6776 12:11:44.228045 16, 0x0, sum = 4
6777 12:11:44.231380 best_step = 14
6778 12:11:44.231472
6779 12:11:44.231540 ==
6780 12:11:44.234765 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:11:44.238045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:11:44.238140 ==
6783 12:11:44.241134 RX Vref Scan: 1
6784 12:11:44.241226
6785 12:11:44.241294 RX Vref 0 -> 0, step: 1
6786 12:11:44.241357
6787 12:11:44.244933 RX Delay -311 -> 252, step: 8
6788 12:11:44.245049
6789 12:11:44.248059 Set Vref, RX VrefLevel [Byte0]: 55
6790 12:11:44.251428 [Byte1]: 48
6791 12:11:44.255867
6792 12:11:44.255971 Final RX Vref Byte 0 = 55 to rank0
6793 12:11:44.258941 Final RX Vref Byte 1 = 48 to rank0
6794 12:11:44.262264 Final RX Vref Byte 0 = 55 to rank1
6795 12:11:44.265677 Final RX Vref Byte 1 = 48 to rank1==
6796 12:11:44.269083 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 12:11:44.275913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 12:11:44.276071 ==
6799 12:11:44.276170 DQS Delay:
6800 12:11:44.278738 DQS0 = 28, DQS1 = 32
6801 12:11:44.278830 DQM Delay:
6802 12:11:44.278896 DQM0 = 9, DQM1 = 11
6803 12:11:44.282212 DQ Delay:
6804 12:11:44.282299 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6805 12:11:44.285591 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6806 12:11:44.289145 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6807 12:11:44.292594 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6808 12:11:44.292704
6809 12:11:44.292777
6810 12:11:44.302718 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6811 12:11:44.306008 CH1 RK0: MR19=C0C, MR18=93CB
6812 12:11:44.309351 CH1_RK0: MR19=0xC0C, MR18=0x93CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6813 12:11:44.312545 ==
6814 12:11:44.315895 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 12:11:44.319342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 12:11:44.319475 ==
6817 12:11:44.322722 [Gating] SW mode calibration
6818 12:11:44.328936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6819 12:11:44.332376 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6820 12:11:44.339188 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6821 12:11:44.342502 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 12:11:44.345822 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6823 12:11:44.352205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 12:11:44.355405 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 12:11:44.358659 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 12:11:44.365732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 12:11:44.369084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 12:11:44.372322 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 12:11:44.375722 Total UI for P1: 0, mck2ui 16
6830 12:11:44.378991 best dqsien dly found for B0: ( 0, 14, 24)
6831 12:11:44.382327 Total UI for P1: 0, mck2ui 16
6832 12:11:44.385715 best dqsien dly found for B1: ( 0, 14, 24)
6833 12:11:44.389193 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6834 12:11:44.392611 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6835 12:11:44.392718
6836 12:11:44.395925 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6837 12:11:44.402434 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 12:11:44.402585 [Gating] SW calibration Done
6839 12:11:44.405866 ==
6840 12:11:44.406004 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 12:11:44.412070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 12:11:44.412214 ==
6843 12:11:44.412321 RX Vref Scan: 0
6844 12:11:44.412413
6845 12:11:44.415506 RX Vref 0 -> 0, step: 1
6846 12:11:44.415603
6847 12:11:44.418596 RX Delay -410 -> 252, step: 16
6848 12:11:44.422010 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6849 12:11:44.425465 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6850 12:11:44.432299 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6851 12:11:44.435804 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6852 12:11:44.438502 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6853 12:11:44.441998 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6854 12:11:44.448576 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6855 12:11:44.451948 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6856 12:11:44.455452 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6857 12:11:44.458731 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6858 12:11:44.465627 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6859 12:11:44.468805 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6860 12:11:44.472175 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6861 12:11:44.475353 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6862 12:11:44.481855 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6863 12:11:44.485129 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6864 12:11:44.485260 ==
6865 12:11:44.488404 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 12:11:44.491760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 12:11:44.491862 ==
6868 12:11:44.495358 DQS Delay:
6869 12:11:44.495452 DQS0 = 35, DQS1 = 35
6870 12:11:44.498689 DQM Delay:
6871 12:11:44.498784 DQM0 = 18, DQM1 = 13
6872 12:11:44.498854 DQ Delay:
6873 12:11:44.502019 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6874 12:11:44.505199 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6875 12:11:44.508679 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6876 12:11:44.511992 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6877 12:11:44.512095
6878 12:11:44.512165
6879 12:11:44.512228 ==
6880 12:11:44.515280 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 12:11:44.521879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 12:11:44.522034 ==
6883 12:11:44.522130
6884 12:11:44.522221
6885 12:11:44.522311 TX Vref Scan disable
6886 12:11:44.525115 == TX Byte 0 ==
6887 12:11:44.528525 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 12:11:44.532008 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 12:11:44.535515 == TX Byte 1 ==
6890 12:11:44.538317 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6891 12:11:44.541786 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6892 12:11:44.541874 ==
6893 12:11:44.545246 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 12:11:44.551882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 12:11:44.551997 ==
6896 12:11:44.552067
6897 12:11:44.552129
6898 12:11:44.552190 TX Vref Scan disable
6899 12:11:44.555205 == TX Byte 0 ==
6900 12:11:44.557970 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 12:11:44.561338 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 12:11:44.564664 == TX Byte 1 ==
6903 12:11:44.567993 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6904 12:11:44.571897 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6905 12:11:44.572003
6906 12:11:44.575124 [DATLAT]
6907 12:11:44.575252 Freq=400, CH1 RK1
6908 12:11:44.575359
6909 12:11:44.578428 DATLAT Default: 0xe
6910 12:11:44.578542 0, 0xFFFF, sum = 0
6911 12:11:44.581775 1, 0xFFFF, sum = 0
6912 12:11:44.581863 2, 0xFFFF, sum = 0
6913 12:11:44.585077 3, 0xFFFF, sum = 0
6914 12:11:44.585169 4, 0xFFFF, sum = 0
6915 12:11:44.588406 5, 0xFFFF, sum = 0
6916 12:11:44.588494 6, 0xFFFF, sum = 0
6917 12:11:44.591453 7, 0xFFFF, sum = 0
6918 12:11:44.591541 8, 0xFFFF, sum = 0
6919 12:11:44.594662 9, 0xFFFF, sum = 0
6920 12:11:44.598546 10, 0xFFFF, sum = 0
6921 12:11:44.598636 11, 0xFFFF, sum = 0
6922 12:11:44.601728 12, 0xFFFF, sum = 0
6923 12:11:44.601843 13, 0x0, sum = 1
6924 12:11:44.605194 14, 0x0, sum = 2
6925 12:11:44.605272 15, 0x0, sum = 3
6926 12:11:44.605337 16, 0x0, sum = 4
6927 12:11:44.608519 best_step = 14
6928 12:11:44.608595
6929 12:11:44.608672 ==
6930 12:11:44.611776 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:11:44.614525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:11:44.614641 ==
6933 12:11:44.617994 RX Vref Scan: 0
6934 12:11:44.618103
6935 12:11:44.618199 RX Vref 0 -> 0, step: 1
6936 12:11:44.621525
6937 12:11:44.621647 RX Delay -311 -> 252, step: 8
6938 12:11:44.629541 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6939 12:11:44.633293 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6940 12:11:44.636729 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6941 12:11:44.640120 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6942 12:11:44.646759 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6943 12:11:44.649668 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6944 12:11:44.653035 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6945 12:11:44.656349 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6946 12:11:44.663047 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6947 12:11:44.666477 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6948 12:11:44.669829 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6949 12:11:44.672671 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6950 12:11:44.679499 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6951 12:11:44.682615 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6952 12:11:44.685932 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6953 12:11:44.693022 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6954 12:11:44.693114 ==
6955 12:11:44.696327 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 12:11:44.699491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 12:11:44.699573 ==
6958 12:11:44.699639 DQS Delay:
6959 12:11:44.702696 DQS0 = 28, DQS1 = 32
6960 12:11:44.702778 DQM Delay:
6961 12:11:44.705972 DQM0 = 11, DQM1 = 12
6962 12:11:44.706048 DQ Delay:
6963 12:11:44.709112 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6964 12:11:44.712474 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6965 12:11:44.715903 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6966 12:11:44.719205 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6967 12:11:44.719317
6968 12:11:44.719397
6969 12:11:44.726270 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6970 12:11:44.729563 CH1 RK1: MR19=C0C, MR18=C456
6971 12:11:44.735758 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
6972 12:11:44.739082 [RxdqsGatingPostProcess] freq 400
6973 12:11:44.745735 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6974 12:11:44.745863 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 12:11:44.749127 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 12:11:44.752548 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 12:11:44.755972 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 12:11:44.759364 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 12:11:44.762712 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 12:11:44.765980 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 12:11:44.769319 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 12:11:44.772736 Pre-setting of DQS Precalculation
6983 12:11:44.775528 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6984 12:11:44.785775 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6985 12:11:44.792132 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6986 12:11:44.792238
6987 12:11:44.792326
6988 12:11:44.796071 [Calibration Summary] 800 Mbps
6989 12:11:44.796156 CH 0, Rank 0
6990 12:11:44.799453 SW Impedance : PASS
6991 12:11:44.799555 DUTY Scan : NO K
6992 12:11:44.802719 ZQ Calibration : PASS
6993 12:11:44.805997 Jitter Meter : NO K
6994 12:11:44.806122 CBT Training : PASS
6995 12:11:44.809618 Write leveling : PASS
6996 12:11:44.812745 RX DQS gating : PASS
6997 12:11:44.812861 RX DQ/DQS(RDDQC) : PASS
6998 12:11:44.816025 TX DQ/DQS : PASS
6999 12:11:44.819306 RX DATLAT : PASS
7000 12:11:44.819412 RX DQ/DQS(Engine): PASS
7001 12:11:44.822512 TX OE : NO K
7002 12:11:44.822601 All Pass.
7003 12:11:44.822669
7004 12:11:44.825712 CH 0, Rank 1
7005 12:11:44.825798 SW Impedance : PASS
7006 12:11:44.828931 DUTY Scan : NO K
7007 12:11:44.832421 ZQ Calibration : PASS
7008 12:11:44.832511 Jitter Meter : NO K
7009 12:11:44.836005 CBT Training : PASS
7010 12:11:44.838670 Write leveling : NO K
7011 12:11:44.838784 RX DQS gating : PASS
7012 12:11:44.842056 RX DQ/DQS(RDDQC) : PASS
7013 12:11:44.842147 TX DQ/DQS : PASS
7014 12:11:44.845405 RX DATLAT : PASS
7015 12:11:44.848657 RX DQ/DQS(Engine): PASS
7016 12:11:44.848745 TX OE : NO K
7017 12:11:44.852070 All Pass.
7018 12:11:44.852159
7019 12:11:44.852227 CH 1, Rank 0
7020 12:11:44.855518 SW Impedance : PASS
7021 12:11:44.855615 DUTY Scan : NO K
7022 12:11:44.858842 ZQ Calibration : PASS
7023 12:11:44.862127 Jitter Meter : NO K
7024 12:11:44.862217 CBT Training : PASS
7025 12:11:44.865467 Write leveling : PASS
7026 12:11:44.868663 RX DQS gating : PASS
7027 12:11:44.868750 RX DQ/DQS(RDDQC) : PASS
7028 12:11:44.872029 TX DQ/DQS : PASS
7029 12:11:44.875488 RX DATLAT : PASS
7030 12:11:44.875618 RX DQ/DQS(Engine): PASS
7031 12:11:44.878811 TX OE : NO K
7032 12:11:44.878919 All Pass.
7033 12:11:44.879012
7034 12:11:44.882292 CH 1, Rank 1
7035 12:11:44.882409 SW Impedance : PASS
7036 12:11:44.885764 DUTY Scan : NO K
7037 12:11:44.888498 ZQ Calibration : PASS
7038 12:11:44.888581 Jitter Meter : NO K
7039 12:11:44.891894 CBT Training : PASS
7040 12:11:44.891981 Write leveling : NO K
7041 12:11:44.895240 RX DQS gating : PASS
7042 12:11:44.898445 RX DQ/DQS(RDDQC) : PASS
7043 12:11:44.898527 TX DQ/DQS : PASS
7044 12:11:44.901698 RX DATLAT : PASS
7045 12:11:44.905660 RX DQ/DQS(Engine): PASS
7046 12:11:44.905773 TX OE : NO K
7047 12:11:44.908927 All Pass.
7048 12:11:44.909035
7049 12:11:44.909129 DramC Write-DBI off
7050 12:11:44.911713 PER_BANK_REFRESH: Hybrid Mode
7051 12:11:44.915066 TX_TRACKING: ON
7052 12:11:44.921816 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7053 12:11:44.925073 [FAST_K] Save calibration result to emmc
7054 12:11:44.928824 dramc_set_vcore_voltage set vcore to 725000
7055 12:11:44.931977 Read voltage for 1600, 0
7056 12:11:44.932067 Vio18 = 0
7057 12:11:44.935321 Vcore = 725000
7058 12:11:44.935420 Vdram = 0
7059 12:11:44.935484 Vddq = 0
7060 12:11:44.938762 Vmddr = 0
7061 12:11:44.941536 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7062 12:11:44.948382 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7063 12:11:44.948490 MEM_TYPE=3, freq_sel=13
7064 12:11:44.951801 sv_algorithm_assistance_LP4_3733
7065 12:11:44.958564 ============ PULL DRAM RESETB DOWN ============
7066 12:11:44.961982 ========== PULL DRAM RESETB DOWN end =========
7067 12:11:44.965385 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7068 12:11:44.968118 ===================================
7069 12:11:44.971502 LPDDR4 DRAM CONFIGURATION
7070 12:11:44.974796 ===================================
7071 12:11:44.978098 EX_ROW_EN[0] = 0x0
7072 12:11:44.978190 EX_ROW_EN[1] = 0x0
7073 12:11:44.981528 LP4Y_EN = 0x0
7074 12:11:44.981616 WORK_FSP = 0x1
7075 12:11:44.984803 WL = 0x5
7076 12:11:44.984917 RL = 0x5
7077 12:11:44.988345 BL = 0x2
7078 12:11:44.988450 RPST = 0x0
7079 12:11:44.991734 RD_PRE = 0x0
7080 12:11:44.991839 WR_PRE = 0x1
7081 12:11:44.995153 WR_PST = 0x1
7082 12:11:44.995266 DBI_WR = 0x0
7083 12:11:44.997894 DBI_RD = 0x0
7084 12:11:44.998009 OTF = 0x1
7085 12:11:45.001370 ===================================
7086 12:11:45.004623 ===================================
7087 12:11:45.008463 ANA top config
7088 12:11:45.011768 ===================================
7089 12:11:45.014887 DLL_ASYNC_EN = 0
7090 12:11:45.015015 ALL_SLAVE_EN = 0
7091 12:11:45.018144 NEW_RANK_MODE = 1
7092 12:11:45.021481 DLL_IDLE_MODE = 1
7093 12:11:45.024826 LP45_APHY_COMB_EN = 1
7094 12:11:45.024941 TX_ODT_DIS = 0
7095 12:11:45.028265 NEW_8X_MODE = 1
7096 12:11:45.031550 ===================================
7097 12:11:45.034828 ===================================
7098 12:11:45.038038 data_rate = 3200
7099 12:11:45.041575 CKR = 1
7100 12:11:45.044735 DQ_P2S_RATIO = 8
7101 12:11:45.048207 ===================================
7102 12:11:45.051686 CA_P2S_RATIO = 8
7103 12:11:45.051768 DQ_CA_OPEN = 0
7104 12:11:45.054450 DQ_SEMI_OPEN = 0
7105 12:11:45.058363 CA_SEMI_OPEN = 0
7106 12:11:45.061703 CA_FULL_RATE = 0
7107 12:11:45.064982 DQ_CKDIV4_EN = 0
7108 12:11:45.065073 CA_CKDIV4_EN = 0
7109 12:11:45.068564 CA_PREDIV_EN = 0
7110 12:11:45.071415 PH8_DLY = 12
7111 12:11:45.074846 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7112 12:11:45.078235 DQ_AAMCK_DIV = 4
7113 12:11:45.081584 CA_AAMCK_DIV = 4
7114 12:11:45.081673 CA_ADMCK_DIV = 4
7115 12:11:45.085082 DQ_TRACK_CA_EN = 0
7116 12:11:45.088446 CA_PICK = 1600
7117 12:11:45.091155 CA_MCKIO = 1600
7118 12:11:45.094698 MCKIO_SEMI = 0
7119 12:11:45.098069 PLL_FREQ = 3068
7120 12:11:45.101555 DQ_UI_PI_RATIO = 32
7121 12:11:45.104870 CA_UI_PI_RATIO = 0
7122 12:11:45.108204 ===================================
7123 12:11:45.111556 ===================================
7124 12:11:45.111644 memory_type:LPDDR4
7125 12:11:45.114334 GP_NUM : 10
7126 12:11:45.118250 SRAM_EN : 1
7127 12:11:45.118382 MD32_EN : 0
7128 12:11:45.121438 ===================================
7129 12:11:45.124652 [ANA_INIT] >>>>>>>>>>>>>>
7130 12:11:45.127934 <<<<<< [CONFIGURE PHASE]: ANA_TX
7131 12:11:45.131244 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7132 12:11:45.134531 ===================================
7133 12:11:45.137722 data_rate = 3200,PCW = 0X7600
7134 12:11:45.141084 ===================================
7135 12:11:45.144388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7136 12:11:45.147481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7137 12:11:45.154698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 12:11:45.157524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7139 12:11:45.160955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7140 12:11:45.164448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7141 12:11:45.167570 [ANA_INIT] flow start
7142 12:11:45.170724 [ANA_INIT] PLL >>>>>>>>
7143 12:11:45.170812 [ANA_INIT] PLL <<<<<<<<
7144 12:11:45.174232 [ANA_INIT] MIDPI >>>>>>>>
7145 12:11:45.177773 [ANA_INIT] MIDPI <<<<<<<<
7146 12:11:45.177876 [ANA_INIT] DLL >>>>>>>>
7147 12:11:45.180977 [ANA_INIT] DLL <<<<<<<<
7148 12:11:45.184464 [ANA_INIT] flow end
7149 12:11:45.187157 ============ LP4 DIFF to SE enter ============
7150 12:11:45.190779 ============ LP4 DIFF to SE exit ============
7151 12:11:45.194028 [ANA_INIT] <<<<<<<<<<<<<
7152 12:11:45.197465 [Flow] Enable top DCM control >>>>>
7153 12:11:45.200936 [Flow] Enable top DCM control <<<<<
7154 12:11:45.204417 Enable DLL master slave shuffle
7155 12:11:45.207146 ==============================================================
7156 12:11:45.210654 Gating Mode config
7157 12:11:45.217568 ==============================================================
7158 12:11:45.217697 Config description:
7159 12:11:45.227078 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7160 12:11:45.234162 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7161 12:11:45.240772 SELPH_MODE 0: By rank 1: By Phase
7162 12:11:45.243990 ==============================================================
7163 12:11:45.247239 GAT_TRACK_EN = 1
7164 12:11:45.250569 RX_GATING_MODE = 2
7165 12:11:45.253833 RX_GATING_TRACK_MODE = 2
7166 12:11:45.257081 SELPH_MODE = 1
7167 12:11:45.260323 PICG_EARLY_EN = 1
7168 12:11:45.264327 VALID_LAT_VALUE = 1
7169 12:11:45.266937 ==============================================================
7170 12:11:45.270347 Enter into Gating configuration >>>>
7171 12:11:45.273553 Exit from Gating configuration <<<<
7172 12:11:45.276967 Enter into DVFS_PRE_config >>>>>
7173 12:11:45.290231 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7174 12:11:45.293611 Exit from DVFS_PRE_config <<<<<
7175 12:11:45.293708 Enter into PICG configuration >>>>
7176 12:11:45.297092 Exit from PICG configuration <<<<
7177 12:11:45.300554 [RX_INPUT] configuration >>>>>
7178 12:11:45.303306 [RX_INPUT] configuration <<<<<
7179 12:11:45.310203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7180 12:11:45.313553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7181 12:11:45.320455 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 12:11:45.326470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 12:11:45.333441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 12:11:45.340110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 12:11:45.343216 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7186 12:11:45.346988 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7187 12:11:45.350210 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7188 12:11:45.356538 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7189 12:11:45.359990 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7190 12:11:45.363121 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 12:11:45.366519 ===================================
7192 12:11:45.370434 LPDDR4 DRAM CONFIGURATION
7193 12:11:45.373070 ===================================
7194 12:11:45.376613 EX_ROW_EN[0] = 0x0
7195 12:11:45.376703 EX_ROW_EN[1] = 0x0
7196 12:11:45.380075 LP4Y_EN = 0x0
7197 12:11:45.380161 WORK_FSP = 0x1
7198 12:11:45.383171 WL = 0x5
7199 12:11:45.383256 RL = 0x5
7200 12:11:45.386504 BL = 0x2
7201 12:11:45.386590 RPST = 0x0
7202 12:11:45.389843 RD_PRE = 0x0
7203 12:11:45.389931 WR_PRE = 0x1
7204 12:11:45.393171 WR_PST = 0x1
7205 12:11:45.393259 DBI_WR = 0x0
7206 12:11:45.396564 DBI_RD = 0x0
7207 12:11:45.396650 OTF = 0x1
7208 12:11:45.400088 ===================================
7209 12:11:45.403691 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7210 12:11:45.409684 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7211 12:11:45.413206 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 12:11:45.416722 ===================================
7213 12:11:45.420075 LPDDR4 DRAM CONFIGURATION
7214 12:11:45.423600 ===================================
7215 12:11:45.423689 EX_ROW_EN[0] = 0x10
7216 12:11:45.427029 EX_ROW_EN[1] = 0x0
7217 12:11:45.429681 LP4Y_EN = 0x0
7218 12:11:45.429768 WORK_FSP = 0x1
7219 12:11:45.433211 WL = 0x5
7220 12:11:45.433298 RL = 0x5
7221 12:11:45.436626 BL = 0x2
7222 12:11:45.436715 RPST = 0x0
7223 12:11:45.440065 RD_PRE = 0x0
7224 12:11:45.440152 WR_PRE = 0x1
7225 12:11:45.443500 WR_PST = 0x1
7226 12:11:45.443586 DBI_WR = 0x0
7227 12:11:45.446913 DBI_RD = 0x0
7228 12:11:45.447000 OTF = 0x1
7229 12:11:45.450168 ===================================
7230 12:11:45.456596 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7231 12:11:45.456698 ==
7232 12:11:45.459665 Dram Type= 6, Freq= 0, CH_0, rank 0
7233 12:11:45.463521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7234 12:11:45.463615 ==
7235 12:11:45.466748 [Duty_Offset_Calibration]
7236 12:11:45.470155 B0:2 B1:1 CA:1
7237 12:11:45.470258
7238 12:11:45.473315 [DutyScan_Calibration_Flow] k_type=0
7239 12:11:45.481558
7240 12:11:45.481691 ==CLK 0==
7241 12:11:45.484965 Final CLK duty delay cell = 0
7242 12:11:45.488378 [0] MAX Duty = 5156%(X100), DQS PI = 22
7243 12:11:45.491608 [0] MIN Duty = 4876%(X100), DQS PI = 48
7244 12:11:45.491729 [0] AVG Duty = 5016%(X100)
7245 12:11:45.495460
7246 12:11:45.498709 CH0 CLK Duty spec in!! Max-Min= 280%
7247 12:11:45.502063 [DutyScan_Calibration_Flow] ====Done====
7248 12:11:45.502171
7249 12:11:45.504950 [DutyScan_Calibration_Flow] k_type=1
7250 12:11:45.521161
7251 12:11:45.521300 ==DQS 0 ==
7252 12:11:45.524495 Final DQS duty delay cell = -4
7253 12:11:45.527876 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7254 12:11:45.530657 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7255 12:11:45.534049 [-4] AVG Duty = 4891%(X100)
7256 12:11:45.534138
7257 12:11:45.534212 ==DQS 1 ==
7258 12:11:45.537542 Final DQS duty delay cell = 0
7259 12:11:45.541080 [0] MAX Duty = 5187%(X100), DQS PI = 20
7260 12:11:45.544400 [0] MIN Duty = 5031%(X100), DQS PI = 52
7261 12:11:45.547795 [0] AVG Duty = 5109%(X100)
7262 12:11:45.547882
7263 12:11:45.550534 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7264 12:11:45.550619
7265 12:11:45.553929 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7266 12:11:45.557399 [DutyScan_Calibration_Flow] ====Done====
7267 12:11:45.557487
7268 12:11:45.560775 [DutyScan_Calibration_Flow] k_type=3
7269 12:11:45.577728
7270 12:11:45.577905 ==DQM 0 ==
7271 12:11:45.580779 Final DQM duty delay cell = 0
7272 12:11:45.584158 [0] MAX Duty = 5218%(X100), DQS PI = 32
7273 12:11:45.587510 [0] MIN Duty = 4907%(X100), DQS PI = 54
7274 12:11:45.587600 [0] AVG Duty = 5062%(X100)
7275 12:11:45.591182
7276 12:11:45.591271 ==DQM 1 ==
7277 12:11:45.594558 Final DQM duty delay cell = -4
7278 12:11:45.597370 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7279 12:11:45.601348 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7280 12:11:45.604530 [-4] AVG Duty = 4922%(X100)
7281 12:11:45.604622
7282 12:11:45.607818 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7283 12:11:45.607905
7284 12:11:45.611182 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7285 12:11:45.614455 [DutyScan_Calibration_Flow] ====Done====
7286 12:11:45.614563
7287 12:11:45.617949 [DutyScan_Calibration_Flow] k_type=2
7288 12:11:45.635092
7289 12:11:45.635258 ==DQ 0 ==
7290 12:11:45.638564 Final DQ duty delay cell = 0
7291 12:11:45.641960 [0] MAX Duty = 5062%(X100), DQS PI = 24
7292 12:11:45.645426 [0] MIN Duty = 4907%(X100), DQS PI = 0
7293 12:11:45.645507 [0] AVG Duty = 4984%(X100)
7294 12:11:45.648122
7295 12:11:45.648195 ==DQ 1 ==
7296 12:11:45.651704 Final DQ duty delay cell = 0
7297 12:11:45.655102 [0] MAX Duty = 5156%(X100), DQS PI = 22
7298 12:11:45.658404 [0] MIN Duty = 4969%(X100), DQS PI = 12
7299 12:11:45.658515 [0] AVG Duty = 5062%(X100)
7300 12:11:45.658610
7301 12:11:45.664604 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7302 12:11:45.664702
7303 12:11:45.668051 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7304 12:11:45.671442 [DutyScan_Calibration_Flow] ====Done====
7305 12:11:45.671532 ==
7306 12:11:45.674756 Dram Type= 6, Freq= 0, CH_1, rank 0
7307 12:11:45.678557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7308 12:11:45.678669 ==
7309 12:11:45.681659 [Duty_Offset_Calibration]
7310 12:11:45.681779 B0:1 B1:0 CA:1
7311 12:11:45.681878
7312 12:11:45.684810 [DutyScan_Calibration_Flow] k_type=0
7313 12:11:45.694676
7314 12:11:45.694831 ==CLK 0==
7315 12:11:45.697793 Final CLK duty delay cell = -4
7316 12:11:45.701010 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7317 12:11:45.704504 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7318 12:11:45.707587 [-4] AVG Duty = 4938%(X100)
7319 12:11:45.707669
7320 12:11:45.710690 CH1 CLK Duty spec in!! Max-Min= 124%
7321 12:11:45.714040 [DutyScan_Calibration_Flow] ====Done====
7322 12:11:45.714121
7323 12:11:45.717294 [DutyScan_Calibration_Flow] k_type=1
7324 12:11:45.734365
7325 12:11:45.734528 ==DQS 0 ==
7326 12:11:45.737810 Final DQS duty delay cell = 0
7327 12:11:45.741181 [0] MAX Duty = 5094%(X100), DQS PI = 16
7328 12:11:45.744566 [0] MIN Duty = 4875%(X100), DQS PI = 0
7329 12:11:45.744694 [0] AVG Duty = 4984%(X100)
7330 12:11:45.748012
7331 12:11:45.748141 ==DQS 1 ==
7332 12:11:45.751508 Final DQS duty delay cell = 0
7333 12:11:45.754363 [0] MAX Duty = 5249%(X100), DQS PI = 16
7334 12:11:45.757632 [0] MIN Duty = 4969%(X100), DQS PI = 6
7335 12:11:45.757741 [0] AVG Duty = 5109%(X100)
7336 12:11:45.761036
7337 12:11:45.764469 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7338 12:11:45.764581
7339 12:11:45.767739 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7340 12:11:45.771344 [DutyScan_Calibration_Flow] ====Done====
7341 12:11:45.771437
7342 12:11:45.774025 [DutyScan_Calibration_Flow] k_type=3
7343 12:11:45.791236
7344 12:11:45.791392 ==DQM 0 ==
7345 12:11:45.794572 Final DQM duty delay cell = 0
7346 12:11:45.797875 [0] MAX Duty = 5218%(X100), DQS PI = 8
7347 12:11:45.801051 [0] MIN Duty = 5000%(X100), DQS PI = 48
7348 12:11:45.801141 [0] AVG Duty = 5109%(X100)
7349 12:11:45.804326
7350 12:11:45.804403 ==DQM 1 ==
7351 12:11:45.808198 Final DQM duty delay cell = 0
7352 12:11:45.811289 [0] MAX Duty = 5093%(X100), DQS PI = 16
7353 12:11:45.814505 [0] MIN Duty = 4907%(X100), DQS PI = 52
7354 12:11:45.814590 [0] AVG Duty = 5000%(X100)
7355 12:11:45.817854
7356 12:11:45.821002 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7357 12:11:45.821115
7358 12:11:45.824783 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7359 12:11:45.827969 [DutyScan_Calibration_Flow] ====Done====
7360 12:11:45.828058
7361 12:11:45.830768 [DutyScan_Calibration_Flow] k_type=2
7362 12:11:45.847102
7363 12:11:45.847238 ==DQ 0 ==
7364 12:11:45.850485 Final DQ duty delay cell = -4
7365 12:11:45.853856 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7366 12:11:45.857292 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7367 12:11:45.860686 [-4] AVG Duty = 4968%(X100)
7368 12:11:45.860775
7369 12:11:45.860840 ==DQ 1 ==
7370 12:11:45.864045 Final DQ duty delay cell = 0
7371 12:11:45.867279 [0] MAX Duty = 5124%(X100), DQS PI = 16
7372 12:11:45.870664 [0] MIN Duty = 4938%(X100), DQS PI = 8
7373 12:11:45.870752 [0] AVG Duty = 5031%(X100)
7374 12:11:45.874028
7375 12:11:45.877498 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7376 12:11:45.877585
7377 12:11:45.880905 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7378 12:11:45.884152 [DutyScan_Calibration_Flow] ====Done====
7379 12:11:45.887696 nWR fixed to 30
7380 12:11:45.887825 [ModeRegInit_LP4] CH0 RK0
7381 12:11:45.891044 [ModeRegInit_LP4] CH0 RK1
7382 12:11:45.893725 [ModeRegInit_LP4] CH1 RK0
7383 12:11:45.896982 [ModeRegInit_LP4] CH1 RK1
7384 12:11:45.897072 match AC timing 5
7385 12:11:45.903842 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7386 12:11:45.907042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7387 12:11:45.910827 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7388 12:11:45.917445 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7389 12:11:45.920709 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7390 12:11:45.920808 [MiockJmeterHQA]
7391 12:11:45.920885
7392 12:11:45.923577 [DramcMiockJmeter] u1RxGatingPI = 0
7393 12:11:45.927531 0 : 4252, 4027
7394 12:11:45.927623 4 : 4363, 4138
7395 12:11:45.930702 8 : 4252, 4027
7396 12:11:45.930794 12 : 4250, 4027
7397 12:11:45.930865 16 : 4254, 4029
7398 12:11:45.934210 20 : 4252, 4027
7399 12:11:45.934300 24 : 4363, 4137
7400 12:11:45.937461 28 : 4363, 4137
7401 12:11:45.937550 32 : 4252, 4027
7402 12:11:45.940697 36 : 4253, 4026
7403 12:11:45.940784 40 : 4252, 4027
7404 12:11:45.940854 44 : 4252, 4027
7405 12:11:45.944051 48 : 4255, 4030
7406 12:11:45.944139 52 : 4363, 4137
7407 12:11:45.947540 56 : 4252, 4027
7408 12:11:45.947627 60 : 4252, 4027
7409 12:11:45.950394 64 : 4252, 4027
7410 12:11:45.950482 68 : 4253, 4029
7411 12:11:45.953743 72 : 4249, 4027
7412 12:11:45.953857 76 : 4363, 4137
7413 12:11:45.953954 80 : 4360, 4138
7414 12:11:45.957309 84 : 4250, 4027
7415 12:11:45.957396 88 : 4250, 84
7416 12:11:45.960667 92 : 4249, 0
7417 12:11:45.960755 96 : 4252, 0
7418 12:11:45.960825 100 : 4361, 0
7419 12:11:45.964167 104 : 4361, 0
7420 12:11:45.964256 108 : 4252, 0
7421 12:11:45.966960 112 : 4250, 0
7422 12:11:45.967074 116 : 4252, 0
7423 12:11:45.967172 120 : 4360, 0
7424 12:11:45.970359 124 : 4361, 0
7425 12:11:45.970446 128 : 4250, 0
7426 12:11:45.970514 132 : 4250, 0
7427 12:11:45.973679 136 : 4252, 0
7428 12:11:45.973767 140 : 4250, 0
7429 12:11:45.977147 144 : 4250, 0
7430 12:11:45.977235 148 : 4250, 0
7431 12:11:45.977305 152 : 4361, 0
7432 12:11:45.980661 156 : 4360, 0
7433 12:11:45.980750 160 : 4249, 0
7434 12:11:45.984094 164 : 4250, 0
7435 12:11:45.984182 168 : 4253, 0
7436 12:11:45.984252 172 : 4360, 0
7437 12:11:45.986806 176 : 4250, 0
7438 12:11:45.986893 180 : 4250, 0
7439 12:11:45.990203 184 : 4252, 0
7440 12:11:45.990321 188 : 4360, 0
7441 12:11:45.990419 192 : 4250, 0
7442 12:11:45.993655 196 : 4250, 0
7443 12:11:45.993742 200 : 4249, 0
7444 12:11:45.997003 204 : 4361, 1383
7445 12:11:45.997091 208 : 4250, 4025
7446 12:11:46.000392 212 : 4360, 4137
7447 12:11:46.000481 216 : 4250, 4026
7448 12:11:46.000549 220 : 4361, 4137
7449 12:11:46.003634 224 : 4361, 4137
7450 12:11:46.003756 228 : 4250, 4027
7451 12:11:46.006851 232 : 4250, 4027
7452 12:11:46.006954 236 : 4363, 4140
7453 12:11:46.010038 240 : 4250, 4027
7454 12:11:46.010119 244 : 4250, 4027
7455 12:11:46.013742 248 : 4252, 4026
7456 12:11:46.013825 252 : 4253, 4029
7457 12:11:46.016817 256 : 4250, 4027
7458 12:11:46.016946 260 : 4250, 4027
7459 12:11:46.020162 264 : 4360, 4137
7460 12:11:46.020249 268 : 4250, 4027
7461 12:11:46.023316 272 : 4250, 4027
7462 12:11:46.023411 276 : 4360, 4138
7463 12:11:46.023488 280 : 4250, 4027
7464 12:11:46.026635 284 : 4250, 4026
7465 12:11:46.026728 288 : 4363, 4140
7466 12:11:46.030028 292 : 4250, 4027
7467 12:11:46.030144 296 : 4249, 4027
7468 12:11:46.033337 300 : 4250, 4026
7469 12:11:46.033418 304 : 4253, 4029
7470 12:11:46.036647 308 : 4250, 3987
7471 12:11:46.036729 312 : 4250, 1960
7472 12:11:46.036800
7473 12:11:46.039982 MIOCK jitter meter ch=0
7474 12:11:46.040080
7475 12:11:46.043366 1T = (312-88) = 224 dly cells
7476 12:11:46.050058 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7477 12:11:46.050188 ==
7478 12:11:46.053432 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 12:11:46.056269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7480 12:11:46.056375 ==
7481 12:11:46.063151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7482 12:11:46.066578 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7483 12:11:46.069946 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7484 12:11:46.076555 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7485 12:11:46.085435 [CA 0] Center 42 (12~73) winsize 62
7486 12:11:46.088099 [CA 1] Center 42 (12~73) winsize 62
7487 12:11:46.091514 [CA 2] Center 38 (8~68) winsize 61
7488 12:11:46.094881 [CA 3] Center 37 (8~67) winsize 60
7489 12:11:46.098415 [CA 4] Center 36 (6~66) winsize 61
7490 12:11:46.101817 [CA 5] Center 35 (6~64) winsize 59
7491 12:11:46.101912
7492 12:11:46.105173 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7493 12:11:46.105287
7494 12:11:46.108559 [CATrainingPosCal] consider 1 rank data
7495 12:11:46.111772 u2DelayCellTimex100 = 290/100 ps
7496 12:11:46.115159 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7497 12:11:46.121730 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7498 12:11:46.124987 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7499 12:11:46.128087 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7500 12:11:46.131432 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7501 12:11:46.134545 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7502 12:11:46.134632
7503 12:11:46.138303 CA PerBit enable=1, Macro0, CA PI delay=35
7504 12:11:46.138390
7505 12:11:46.141550 [CBTSetCACLKResult] CA Dly = 35
7506 12:11:46.144833 CS Dly: 9 (0~40)
7507 12:11:46.148087 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7508 12:11:46.151377 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7509 12:11:46.151500 ==
7510 12:11:46.154630 Dram Type= 6, Freq= 0, CH_0, rank 1
7511 12:11:46.158076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 12:11:46.158166 ==
7513 12:11:46.164968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 12:11:46.167759 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 12:11:46.174432 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 12:11:46.177890 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 12:11:46.188180 [CA 0] Center 43 (13~73) winsize 61
7518 12:11:46.191627 [CA 1] Center 43 (13~73) winsize 61
7519 12:11:46.194997 [CA 2] Center 38 (8~68) winsize 61
7520 12:11:46.198413 [CA 3] Center 38 (8~68) winsize 61
7521 12:11:46.201085 [CA 4] Center 36 (6~66) winsize 61
7522 12:11:46.204600 [CA 5] Center 35 (6~65) winsize 60
7523 12:11:46.204688
7524 12:11:46.208044 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7525 12:11:46.208131
7526 12:11:46.211319 [CATrainingPosCal] consider 2 rank data
7527 12:11:46.214532 u2DelayCellTimex100 = 290/100 ps
7528 12:11:46.221500 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7529 12:11:46.224800 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7530 12:11:46.228185 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7531 12:11:46.231352 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7532 12:11:46.234591 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7533 12:11:46.237790 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7534 12:11:46.237913
7535 12:11:46.241609 CA PerBit enable=1, Macro0, CA PI delay=35
7536 12:11:46.241725
7537 12:11:46.244847 [CBTSetCACLKResult] CA Dly = 35
7538 12:11:46.247968 CS Dly: 10 (0~42)
7539 12:11:46.251308 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 12:11:46.254533 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 12:11:46.254622
7542 12:11:46.257698 ----->DramcWriteLeveling(PI) begin...
7543 12:11:46.257816 ==
7544 12:11:46.260972 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 12:11:46.268134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 12:11:46.268248 ==
7547 12:11:46.270967 Write leveling (Byte 0): 34 => 34
7548 12:11:46.271073 Write leveling (Byte 1): 26 => 26
7549 12:11:46.274365 DramcWriteLeveling(PI) end<-----
7550 12:11:46.274478
7551 12:11:46.277790 ==
7552 12:11:46.277896 Dram Type= 6, Freq= 0, CH_0, rank 0
7553 12:11:46.284541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 12:11:46.284658 ==
7555 12:11:46.287931 [Gating] SW mode calibration
7556 12:11:46.293981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7557 12:11:46.297490 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7558 12:11:46.304184 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (1 1)
7559 12:11:46.307514 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7560 12:11:46.310969 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7561 12:11:46.317618 1 4 12 | B1->B0 | 2323 3736 | 0 1 | (0 0) (0 0)
7562 12:11:46.320887 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7563 12:11:46.324299 1 4 20 | B1->B0 | 3333 3535 | 1 0 | (1 1) (0 0)
7564 12:11:46.331084 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7565 12:11:46.334570 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7566 12:11:46.337900 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7567 12:11:46.344433 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7568 12:11:46.347803 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 1)
7569 12:11:46.350974 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7570 12:11:46.357698 1 5 16 | B1->B0 | 3434 2929 | 0 1 | (0 0) (1 0)
7571 12:11:46.361088 1 5 20 | B1->B0 | 2b2b 2625 | 0 1 | (1 0) (0 0)
7572 12:11:46.364468 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7573 12:11:46.367582 1 5 28 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7574 12:11:46.374084 1 6 0 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7575 12:11:46.377482 1 6 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7576 12:11:46.380825 1 6 8 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (1 1)
7577 12:11:46.386930 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7578 12:11:46.390285 1 6 16 | B1->B0 | 2e2e 4645 | 0 1 | (0 0) (0 0)
7579 12:11:46.393592 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7580 12:11:46.400706 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7581 12:11:46.404011 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 12:11:46.407470 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 12:11:46.413650 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 12:11:46.417113 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 12:11:46.420413 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 12:11:46.426894 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7587 12:11:46.430279 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7588 12:11:46.433684 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:11:46.440511 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 12:11:46.443965 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 12:11:46.447271 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 12:11:46.453765 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 12:11:46.457061 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 12:11:46.460201 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 12:11:46.467484 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 12:11:46.470661 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:11:46.474046 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 12:11:46.477426 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:11:46.484042 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:11:46.487599 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7601 12:11:46.490311 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 12:11:46.497115 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 12:11:46.500502 Total UI for P1: 0, mck2ui 16
7604 12:11:46.503921 best dqsien dly found for B0: ( 1, 9, 10)
7605 12:11:46.507450 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7606 12:11:46.510843 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 12:11:46.514199 Total UI for P1: 0, mck2ui 16
7608 12:11:46.516888 best dqsien dly found for B1: ( 1, 9, 18)
7609 12:11:46.520416 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7610 12:11:46.524286 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7611 12:11:46.524430
7612 12:11:46.530539 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7613 12:11:46.533986 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7614 12:11:46.536739 [Gating] SW calibration Done
7615 12:11:46.536866 ==
7616 12:11:46.540171 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 12:11:46.543429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 12:11:46.543560 ==
7619 12:11:46.543678 RX Vref Scan: 0
7620 12:11:46.546757
7621 12:11:46.546873 RX Vref 0 -> 0, step: 1
7622 12:11:46.546989
7623 12:11:46.550093 RX Delay 0 -> 252, step: 8
7624 12:11:46.553548 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7625 12:11:46.556851 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7626 12:11:46.563271 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7627 12:11:46.567139 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7628 12:11:46.570479 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7629 12:11:46.573736 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7630 12:11:46.576982 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7631 12:11:46.580350 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7632 12:11:46.586871 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7633 12:11:46.590340 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7634 12:11:46.593720 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7635 12:11:46.596541 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7636 12:11:46.603348 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7637 12:11:46.606598 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7638 12:11:46.610023 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7639 12:11:46.613482 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7640 12:11:46.613607 ==
7641 12:11:46.616345 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 12:11:46.623194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 12:11:46.623370 ==
7644 12:11:46.623479 DQS Delay:
7645 12:11:46.623583 DQS0 = 0, DQS1 = 0
7646 12:11:46.626652 DQM Delay:
7647 12:11:46.626750 DQM0 = 137, DQM1 = 129
7648 12:11:46.630216 DQ Delay:
7649 12:11:46.633399 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7650 12:11:46.636853 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7651 12:11:46.640298 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7652 12:11:46.643695 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7653 12:11:46.643810
7654 12:11:46.643914
7655 12:11:46.644011 ==
7656 12:11:46.647022 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 12:11:46.649761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 12:11:46.649859 ==
7659 12:11:46.649927
7660 12:11:46.653214
7661 12:11:46.653319 TX Vref Scan disable
7662 12:11:46.656602 == TX Byte 0 ==
7663 12:11:46.660104 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7664 12:11:46.663236 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7665 12:11:46.666595 == TX Byte 1 ==
7666 12:11:46.669928 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7667 12:11:46.673197 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7668 12:11:46.673288 ==
7669 12:11:46.676463 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 12:11:46.683010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 12:11:46.683164 ==
7672 12:11:46.694138
7673 12:11:46.697532 TX Vref early break, caculate TX vref
7674 12:11:46.701562 TX Vref=16, minBit 0, minWin=23, winSum=382
7675 12:11:46.704182 TX Vref=18, minBit 3, minWin=23, winSum=387
7676 12:11:46.708092 TX Vref=20, minBit 7, minWin=24, winSum=407
7677 12:11:46.710845 TX Vref=22, minBit 7, minWin=24, winSum=409
7678 12:11:46.714292 TX Vref=24, minBit 6, minWin=25, winSum=418
7679 12:11:46.721397 TX Vref=26, minBit 7, minWin=25, winSum=428
7680 12:11:46.724099 TX Vref=28, minBit 1, minWin=25, winSum=424
7681 12:11:46.727499 TX Vref=30, minBit 6, minWin=24, winSum=415
7682 12:11:46.730839 TX Vref=32, minBit 1, minWin=24, winSum=405
7683 12:11:46.737735 [TxChooseVref] Worse bit 7, Min win 25, Win sum 428, Final Vref 26
7684 12:11:46.737844
7685 12:11:46.741241 Final TX Range 0 Vref 26
7686 12:11:46.741330
7687 12:11:46.741398 ==
7688 12:11:46.744499 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 12:11:46.747339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 12:11:46.747459 ==
7691 12:11:46.747554
7692 12:11:46.747644
7693 12:11:46.750690 TX Vref Scan disable
7694 12:11:46.754077 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7695 12:11:46.757456 == TX Byte 0 ==
7696 12:11:46.760897 u2DelayCellOfst[0]=10 cells (3 PI)
7697 12:11:46.764453 u2DelayCellOfst[1]=13 cells (4 PI)
7698 12:11:46.767822 u2DelayCellOfst[2]=10 cells (3 PI)
7699 12:11:46.771047 u2DelayCellOfst[3]=10 cells (3 PI)
7700 12:11:46.774320 u2DelayCellOfst[4]=6 cells (2 PI)
7701 12:11:46.774441 u2DelayCellOfst[5]=0 cells (0 PI)
7702 12:11:46.777630 u2DelayCellOfst[6]=16 cells (5 PI)
7703 12:11:46.780851 u2DelayCellOfst[7]=13 cells (4 PI)
7704 12:11:46.787543 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7705 12:11:46.790666 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7706 12:11:46.790796 == TX Byte 1 ==
7707 12:11:46.793881 u2DelayCellOfst[8]=3 cells (1 PI)
7708 12:11:46.797187 u2DelayCellOfst[9]=0 cells (0 PI)
7709 12:11:46.801002 u2DelayCellOfst[10]=6 cells (2 PI)
7710 12:11:46.804215 u2DelayCellOfst[11]=3 cells (1 PI)
7711 12:11:46.807545 u2DelayCellOfst[12]=10 cells (3 PI)
7712 12:11:46.810907 u2DelayCellOfst[13]=13 cells (4 PI)
7713 12:11:46.814263 u2DelayCellOfst[14]=16 cells (5 PI)
7714 12:11:46.817076 u2DelayCellOfst[15]=10 cells (3 PI)
7715 12:11:46.820525 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7716 12:11:46.823878 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7717 12:11:46.827296 DramC Write-DBI on
7718 12:11:46.827427 ==
7719 12:11:46.830825 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 12:11:46.833565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 12:11:46.833676 ==
7722 12:11:46.833775
7723 12:11:46.833866
7724 12:11:46.837059 TX Vref Scan disable
7725 12:11:46.840548 == TX Byte 0 ==
7726 12:11:46.843830 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7727 12:11:46.847318 == TX Byte 1 ==
7728 12:11:46.850165 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7729 12:11:46.850276 DramC Write-DBI off
7730 12:11:46.850377
7731 12:11:46.853669 [DATLAT]
7732 12:11:46.853785 Freq=1600, CH0 RK0
7733 12:11:46.853883
7734 12:11:46.856915 DATLAT Default: 0xf
7735 12:11:46.857026 0, 0xFFFF, sum = 0
7736 12:11:46.860243 1, 0xFFFF, sum = 0
7737 12:11:46.860359 2, 0xFFFF, sum = 0
7738 12:11:46.863683 3, 0xFFFF, sum = 0
7739 12:11:46.863792 4, 0xFFFF, sum = 0
7740 12:11:46.867119 5, 0xFFFF, sum = 0
7741 12:11:46.867200 6, 0xFFFF, sum = 0
7742 12:11:46.870567 7, 0xFFFF, sum = 0
7743 12:11:46.873919 8, 0xFFFF, sum = 0
7744 12:11:46.874050 9, 0xFFFF, sum = 0
7745 12:11:46.877217 10, 0xFFFF, sum = 0
7746 12:11:46.877307 11, 0xFFFF, sum = 0
7747 12:11:46.880544 12, 0xFFFF, sum = 0
7748 12:11:46.880659 13, 0xFFFF, sum = 0
7749 12:11:46.883562 14, 0x0, sum = 1
7750 12:11:46.883647 15, 0x0, sum = 2
7751 12:11:46.886880 16, 0x0, sum = 3
7752 12:11:46.886998 17, 0x0, sum = 4
7753 12:11:46.887117 best_step = 15
7754 12:11:46.890059
7755 12:11:46.890175 ==
7756 12:11:46.893340 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 12:11:46.896712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 12:11:46.896830 ==
7759 12:11:46.896926 RX Vref Scan: 1
7760 12:11:46.897017
7761 12:11:46.899999 Set Vref Range= 24 -> 127
7762 12:11:46.900093
7763 12:11:46.903444 RX Vref 24 -> 127, step: 1
7764 12:11:46.903530
7765 12:11:46.906726 RX Delay 19 -> 252, step: 4
7766 12:11:46.906806
7767 12:11:46.909893 Set Vref, RX VrefLevel [Byte0]: 24
7768 12:11:46.913185 [Byte1]: 24
7769 12:11:46.913297
7770 12:11:46.916571 Set Vref, RX VrefLevel [Byte0]: 25
7771 12:11:46.920026 [Byte1]: 25
7772 12:11:46.920141
7773 12:11:46.923494 Set Vref, RX VrefLevel [Byte0]: 26
7774 12:11:46.926874 [Byte1]: 26
7775 12:11:46.930203
7776 12:11:46.930320 Set Vref, RX VrefLevel [Byte0]: 27
7777 12:11:46.933640 [Byte1]: 27
7778 12:11:46.937833
7779 12:11:46.937963 Set Vref, RX VrefLevel [Byte0]: 28
7780 12:11:46.941188 [Byte1]: 28
7781 12:11:46.945792
7782 12:11:46.945925 Set Vref, RX VrefLevel [Byte0]: 29
7783 12:11:46.949223 [Byte1]: 29
7784 12:11:46.953208
7785 12:11:46.953353 Set Vref, RX VrefLevel [Byte0]: 30
7786 12:11:46.956585 [Byte1]: 30
7787 12:11:46.960617
7788 12:11:46.960712 Set Vref, RX VrefLevel [Byte0]: 31
7789 12:11:46.964010 [Byte1]: 31
7790 12:11:46.968192
7791 12:11:46.968287 Set Vref, RX VrefLevel [Byte0]: 32
7792 12:11:46.971586 [Byte1]: 32
7793 12:11:46.975500
7794 12:11:46.975616 Set Vref, RX VrefLevel [Byte0]: 33
7795 12:11:46.978901 [Byte1]: 33
7796 12:11:46.983711
7797 12:11:46.983857 Set Vref, RX VrefLevel [Byte0]: 34
7798 12:11:46.986971 [Byte1]: 34
7799 12:11:46.990772
7800 12:11:46.990898 Set Vref, RX VrefLevel [Byte0]: 35
7801 12:11:46.994116 [Byte1]: 35
7802 12:11:46.998755
7803 12:11:46.998885 Set Vref, RX VrefLevel [Byte0]: 36
7804 12:11:47.001962 [Byte1]: 36
7805 12:11:47.005955
7806 12:11:47.006086 Set Vref, RX VrefLevel [Byte0]: 37
7807 12:11:47.009240 [Byte1]: 37
7808 12:11:47.013858
7809 12:11:47.014008 Set Vref, RX VrefLevel [Byte0]: 38
7810 12:11:47.017533 [Byte1]: 38
7811 12:11:47.021502
7812 12:11:47.021648 Set Vref, RX VrefLevel [Byte0]: 39
7813 12:11:47.024273 [Byte1]: 39
7814 12:11:47.029079
7815 12:11:47.029179 Set Vref, RX VrefLevel [Byte0]: 40
7816 12:11:47.032332 [Byte1]: 40
7817 12:11:47.036413
7818 12:11:47.036534 Set Vref, RX VrefLevel [Byte0]: 41
7819 12:11:47.039884 [Byte1]: 41
7820 12:11:47.043859
7821 12:11:47.043972 Set Vref, RX VrefLevel [Byte0]: 42
7822 12:11:47.047370 [Byte1]: 42
7823 12:11:47.051270
7824 12:11:47.051386 Set Vref, RX VrefLevel [Byte0]: 43
7825 12:11:47.054731 [Byte1]: 43
7826 12:11:47.058899
7827 12:11:47.058996 Set Vref, RX VrefLevel [Byte0]: 44
7828 12:11:47.062418 [Byte1]: 44
7829 12:11:47.066388
7830 12:11:47.066503 Set Vref, RX VrefLevel [Byte0]: 45
7831 12:11:47.069832 [Byte1]: 45
7832 12:11:47.074602
7833 12:11:47.074721 Set Vref, RX VrefLevel [Byte0]: 46
7834 12:11:47.077285 [Byte1]: 46
7835 12:11:47.081443
7836 12:11:47.084882 Set Vref, RX VrefLevel [Byte0]: 47
7837 12:11:47.088315 [Byte1]: 47
7838 12:11:47.088442
7839 12:11:47.091671 Set Vref, RX VrefLevel [Byte0]: 48
7840 12:11:47.094939 [Byte1]: 48
7841 12:11:47.095037
7842 12:11:47.098051 Set Vref, RX VrefLevel [Byte0]: 49
7843 12:11:47.101917 [Byte1]: 49
7844 12:11:47.102013
7845 12:11:47.105214 Set Vref, RX VrefLevel [Byte0]: 50
7846 12:11:47.108404 [Byte1]: 50
7847 12:11:47.112367
7848 12:11:47.112462 Set Vref, RX VrefLevel [Byte0]: 51
7849 12:11:47.115734 [Byte1]: 51
7850 12:11:47.119520
7851 12:11:47.119629 Set Vref, RX VrefLevel [Byte0]: 52
7852 12:11:47.122904 [Byte1]: 52
7853 12:11:47.126995
7854 12:11:47.127118 Set Vref, RX VrefLevel [Byte0]: 53
7855 12:11:47.130357 [Byte1]: 53
7856 12:11:47.135016
7857 12:11:47.135138 Set Vref, RX VrefLevel [Byte0]: 54
7858 12:11:47.138402 [Byte1]: 54
7859 12:11:47.142434
7860 12:11:47.142527 Set Vref, RX VrefLevel [Byte0]: 55
7861 12:11:47.145862 [Byte1]: 55
7862 12:11:47.149792
7863 12:11:47.149921 Set Vref, RX VrefLevel [Byte0]: 56
7864 12:11:47.153200 [Byte1]: 56
7865 12:11:47.157210
7866 12:11:47.157330 Set Vref, RX VrefLevel [Byte0]: 57
7867 12:11:47.160613 [Byte1]: 57
7868 12:11:47.165336
7869 12:11:47.165459 Set Vref, RX VrefLevel [Byte0]: 58
7870 12:11:47.168621 [Byte1]: 58
7871 12:11:47.172721
7872 12:11:47.172839 Set Vref, RX VrefLevel [Byte0]: 59
7873 12:11:47.176111 [Byte1]: 59
7874 12:11:47.180099
7875 12:11:47.180218 Set Vref, RX VrefLevel [Byte0]: 60
7876 12:11:47.183618 [Byte1]: 60
7877 12:11:47.187630
7878 12:11:47.187729 Set Vref, RX VrefLevel [Byte0]: 61
7879 12:11:47.190932 [Byte1]: 61
7880 12:11:47.195047
7881 12:11:47.195159 Set Vref, RX VrefLevel [Byte0]: 62
7882 12:11:47.198516 [Byte1]: 62
7883 12:11:47.203154
7884 12:11:47.203273 Set Vref, RX VrefLevel [Byte0]: 63
7885 12:11:47.206466 [Byte1]: 63
7886 12:11:47.210344
7887 12:11:47.210459 Set Vref, RX VrefLevel [Byte0]: 64
7888 12:11:47.213675 [Byte1]: 64
7889 12:11:47.218158
7890 12:11:47.218283 Set Vref, RX VrefLevel [Byte0]: 65
7891 12:11:47.221378 [Byte1]: 65
7892 12:11:47.225992
7893 12:11:47.226083 Set Vref, RX VrefLevel [Byte0]: 66
7894 12:11:47.228655 [Byte1]: 66
7895 12:11:47.233156
7896 12:11:47.233273 Set Vref, RX VrefLevel [Byte0]: 67
7897 12:11:47.236465 [Byte1]: 67
7898 12:11:47.240533
7899 12:11:47.240646 Set Vref, RX VrefLevel [Byte0]: 68
7900 12:11:47.243970 [Byte1]: 68
7901 12:11:47.248088
7902 12:11:47.248170 Set Vref, RX VrefLevel [Byte0]: 69
7903 12:11:47.251546 [Byte1]: 69
7904 12:11:47.256325
7905 12:11:47.256446 Set Vref, RX VrefLevel [Byte0]: 70
7906 12:11:47.259695 [Byte1]: 70
7907 12:11:47.263643
7908 12:11:47.263736 Set Vref, RX VrefLevel [Byte0]: 71
7909 12:11:47.266933 [Byte1]: 71
7910 12:11:47.271073
7911 12:11:47.271179 Set Vref, RX VrefLevel [Byte0]: 72
7912 12:11:47.274455 [Byte1]: 72
7913 12:11:47.278583
7914 12:11:47.278671 Set Vref, RX VrefLevel [Byte0]: 73
7915 12:11:47.281934 [Byte1]: 73
7916 12:11:47.286087
7917 12:11:47.286174 Set Vref, RX VrefLevel [Byte0]: 74
7918 12:11:47.289562 [Byte1]: 74
7919 12:11:47.293655
7920 12:11:47.293741 Set Vref, RX VrefLevel [Byte0]: 75
7921 12:11:47.297028 [Byte1]: 75
7922 12:11:47.301330
7923 12:11:47.301420 Final RX Vref Byte 0 = 56 to rank0
7924 12:11:47.304754 Final RX Vref Byte 1 = 62 to rank0
7925 12:11:47.308296 Final RX Vref Byte 0 = 56 to rank1
7926 12:11:47.311513 Final RX Vref Byte 1 = 62 to rank1==
7927 12:11:47.314727 Dram Type= 6, Freq= 0, CH_0, rank 0
7928 12:11:47.321283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7929 12:11:47.321396 ==
7930 12:11:47.321474 DQS Delay:
7931 12:11:47.321568 DQS0 = 0, DQS1 = 0
7932 12:11:47.324602 DQM Delay:
7933 12:11:47.324691 DQM0 = 134, DQM1 = 128
7934 12:11:47.327976 DQ Delay:
7935 12:11:47.331148 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7936 12:11:47.334479 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7937 12:11:47.337671 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7938 12:11:47.340929 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7939 12:11:47.341056
7940 12:11:47.341158
7941 12:11:47.341253
7942 12:11:47.344290 [DramC_TX_OE_Calibration] TA2
7943 12:11:47.347686 Original DQ_B0 (3 6) =30, OEN = 27
7944 12:11:47.351145 Original DQ_B1 (3 6) =30, OEN = 27
7945 12:11:47.354465 24, 0x0, End_B0=24 End_B1=24
7946 12:11:47.354600 25, 0x0, End_B0=25 End_B1=25
7947 12:11:47.357922 26, 0x0, End_B0=26 End_B1=26
7948 12:11:47.361426 27, 0x0, End_B0=27 End_B1=27
7949 12:11:47.364734 28, 0x0, End_B0=28 End_B1=28
7950 12:11:47.364855 29, 0x0, End_B0=29 End_B1=29
7951 12:11:47.368045 30, 0x0, End_B0=30 End_B1=30
7952 12:11:47.370844 31, 0x4141, End_B0=30 End_B1=30
7953 12:11:47.374291 Byte0 end_step=30 best_step=27
7954 12:11:47.377754 Byte1 end_step=30 best_step=27
7955 12:11:47.380880 Byte0 TX OE(2T, 0.5T) = (3, 3)
7956 12:11:47.384286 Byte1 TX OE(2T, 0.5T) = (3, 3)
7957 12:11:47.384393
7958 12:11:47.384478
7959 12:11:47.390995 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7960 12:11:47.394506 CH0 RK0: MR19=303, MR18=2622
7961 12:11:47.401297 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7962 12:11:47.401428
7963 12:11:47.403993 ----->DramcWriteLeveling(PI) begin...
7964 12:11:47.404099 ==
7965 12:11:47.407503 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 12:11:47.410979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 12:11:47.411103 ==
7968 12:11:47.414423 Write leveling (Byte 0): 34 => 34
7969 12:11:47.417719 Write leveling (Byte 1): 28 => 28
7970 12:11:47.420928 DramcWriteLeveling(PI) end<-----
7971 12:11:47.421049
7972 12:11:47.421125 ==
7973 12:11:47.424090 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 12:11:47.427371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 12:11:47.427529 ==
7976 12:11:47.430571 [Gating] SW mode calibration
7977 12:11:47.437542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7978 12:11:47.444100 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7979 12:11:47.447367 1 4 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7980 12:11:47.450770 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7981 12:11:47.457592 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 12:11:47.461031 1 4 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7983 12:11:47.463710 1 4 16 | B1->B0 | 3434 3535 | 0 0 | (0 0) (0 0)
7984 12:11:47.470460 1 4 20 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7985 12:11:47.473785 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7986 12:11:47.477267 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7987 12:11:47.483889 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 12:11:47.487138 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7989 12:11:47.490507 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 0) (1 0)
7990 12:11:47.497415 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (0 1)
7991 12:11:47.500854 1 5 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 1)
7992 12:11:47.503655 1 5 20 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7993 12:11:47.510662 1 5 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7994 12:11:47.514079 1 5 28 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7995 12:11:47.517496 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7996 12:11:47.523602 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7997 12:11:47.527320 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7998 12:11:47.530515 1 6 12 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7999 12:11:47.536991 1 6 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8000 12:11:47.540374 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 12:11:47.543593 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 12:11:47.550109 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 12:11:47.554055 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 12:11:47.556683 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 12:11:47.563561 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 12:11:47.566971 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8007 12:11:47.570454 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8008 12:11:47.577108 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:11:47.580557 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:11:47.583275 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:11:47.586695 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:11:47.593398 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:11:47.596814 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:11:47.600211 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:11:47.606951 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 12:11:47.610457 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 12:11:47.613669 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 12:11:47.620490 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 12:11:47.623470 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 12:11:47.626753 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 12:11:47.633457 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8022 12:11:47.636753 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8023 12:11:47.640624 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8024 12:11:47.647280 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 12:11:47.647413 Total UI for P1: 0, mck2ui 16
8026 12:11:47.653663 best dqsien dly found for B0: ( 1, 9, 14)
8027 12:11:47.653796 Total UI for P1: 0, mck2ui 16
8028 12:11:47.657047 best dqsien dly found for B1: ( 1, 9, 12)
8029 12:11:47.663524 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8030 12:11:47.666880 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8031 12:11:47.667024
8032 12:11:47.670424 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8033 12:11:47.673705 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8034 12:11:47.677118 [Gating] SW calibration Done
8035 12:11:47.677251 ==
8036 12:11:47.680542 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 12:11:47.683729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 12:11:47.683829 ==
8039 12:11:47.687113 RX Vref Scan: 0
8040 12:11:47.687224
8041 12:11:47.687319 RX Vref 0 -> 0, step: 1
8042 12:11:47.687412
8043 12:11:47.690510 RX Delay 0 -> 252, step: 8
8044 12:11:47.693152 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8045 12:11:47.699878 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8046 12:11:47.703413 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8047 12:11:47.706749 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8048 12:11:47.710096 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8049 12:11:47.713534 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8050 12:11:47.719700 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8051 12:11:47.723086 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8052 12:11:47.726436 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8053 12:11:47.730066 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8054 12:11:47.733502 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8055 12:11:47.740135 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8056 12:11:47.743254 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8057 12:11:47.746630 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8058 12:11:47.749843 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8059 12:11:47.753210 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8060 12:11:47.753334 ==
8061 12:11:47.756539 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 12:11:47.763103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 12:11:47.763244 ==
8064 12:11:47.763348 DQS Delay:
8065 12:11:47.766331 DQS0 = 0, DQS1 = 0
8066 12:11:47.766442 DQM Delay:
8067 12:11:47.769639 DQM0 = 136, DQM1 = 128
8068 12:11:47.769744 DQ Delay:
8069 12:11:47.772838 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8070 12:11:47.776178 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8071 12:11:47.779663 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8072 12:11:47.782875 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8073 12:11:47.782989
8074 12:11:47.783087
8075 12:11:47.783178 ==
8076 12:11:47.786249 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 12:11:47.793184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 12:11:47.793340 ==
8079 12:11:47.793440
8080 12:11:47.793535
8081 12:11:47.793631 TX Vref Scan disable
8082 12:11:47.796716 == TX Byte 0 ==
8083 12:11:47.799932 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8084 12:11:47.806785 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8085 12:11:47.806917 == TX Byte 1 ==
8086 12:11:47.809461 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8087 12:11:47.816397 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8088 12:11:47.816530 ==
8089 12:11:47.819984 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 12:11:47.822807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 12:11:47.822927 ==
8092 12:11:47.835007
8093 12:11:47.838538 TX Vref early break, caculate TX vref
8094 12:11:47.842006 TX Vref=16, minBit 1, minWin=23, winSum=389
8095 12:11:47.844803 TX Vref=18, minBit 0, minWin=23, winSum=399
8096 12:11:47.848074 TX Vref=20, minBit 1, minWin=24, winSum=407
8097 12:11:47.851204 TX Vref=22, minBit 1, minWin=24, winSum=414
8098 12:11:47.855061 TX Vref=24, minBit 1, minWin=24, winSum=423
8099 12:11:47.861550 TX Vref=26, minBit 7, minWin=25, winSum=433
8100 12:11:47.864849 TX Vref=28, minBit 7, minWin=25, winSum=426
8101 12:11:47.868220 TX Vref=30, minBit 2, minWin=25, winSum=419
8102 12:11:47.871663 TX Vref=32, minBit 0, minWin=25, winSum=410
8103 12:11:47.878198 [TxChooseVref] Worse bit 7, Min win 25, Win sum 433, Final Vref 26
8104 12:11:47.878336
8105 12:11:47.881294 Final TX Range 0 Vref 26
8106 12:11:47.881429
8107 12:11:47.881518 ==
8108 12:11:47.884612 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 12:11:47.888150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 12:11:47.888261 ==
8111 12:11:47.888330
8112 12:11:47.888392
8113 12:11:47.891206 TX Vref Scan disable
8114 12:11:47.894633 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8115 12:11:47.898018 == TX Byte 0 ==
8116 12:11:47.901442 u2DelayCellOfst[0]=13 cells (4 PI)
8117 12:11:47.904842 u2DelayCellOfst[1]=13 cells (4 PI)
8118 12:11:47.908183 u2DelayCellOfst[2]=10 cells (3 PI)
8119 12:11:47.911582 u2DelayCellOfst[3]=10 cells (3 PI)
8120 12:11:47.914905 u2DelayCellOfst[4]=6 cells (2 PI)
8121 12:11:47.915017 u2DelayCellOfst[5]=0 cells (0 PI)
8122 12:11:47.917810 u2DelayCellOfst[6]=16 cells (5 PI)
8123 12:11:47.921279 u2DelayCellOfst[7]=16 cells (5 PI)
8124 12:11:47.928153 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8125 12:11:47.931601 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8126 12:11:47.931699 == TX Byte 1 ==
8127 12:11:47.934996 u2DelayCellOfst[8]=3 cells (1 PI)
8128 12:11:47.938321 u2DelayCellOfst[9]=0 cells (0 PI)
8129 12:11:47.941149 u2DelayCellOfst[10]=6 cells (2 PI)
8130 12:11:47.944577 u2DelayCellOfst[11]=6 cells (2 PI)
8131 12:11:47.948043 u2DelayCellOfst[12]=10 cells (3 PI)
8132 12:11:47.951489 u2DelayCellOfst[13]=10 cells (3 PI)
8133 12:11:47.954841 u2DelayCellOfst[14]=13 cells (4 PI)
8134 12:11:47.957974 u2DelayCellOfst[15]=10 cells (3 PI)
8135 12:11:47.961088 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8136 12:11:47.964798 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8137 12:11:47.968119 DramC Write-DBI on
8138 12:11:47.968223 ==
8139 12:11:47.971344 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 12:11:47.974607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 12:11:47.974703 ==
8142 12:11:47.974772
8143 12:11:47.974835
8144 12:11:47.977937 TX Vref Scan disable
8145 12:11:47.981336 == TX Byte 0 ==
8146 12:11:47.984608 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8147 12:11:47.988037 == TX Byte 1 ==
8148 12:11:47.991103 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8149 12:11:47.991220 DramC Write-DBI off
8150 12:11:47.991316
8151 12:11:47.994516 [DATLAT]
8152 12:11:47.994593 Freq=1600, CH0 RK1
8153 12:11:47.994662
8154 12:11:47.997795 DATLAT Default: 0xf
8155 12:11:47.997903 0, 0xFFFF, sum = 0
8156 12:11:48.001108 1, 0xFFFF, sum = 0
8157 12:11:48.001223 2, 0xFFFF, sum = 0
8158 12:11:48.004588 3, 0xFFFF, sum = 0
8159 12:11:48.004704 4, 0xFFFF, sum = 0
8160 12:11:48.008032 5, 0xFFFF, sum = 0
8161 12:11:48.008145 6, 0xFFFF, sum = 0
8162 12:11:48.011483 7, 0xFFFF, sum = 0
8163 12:11:48.011601 8, 0xFFFF, sum = 0
8164 12:11:48.014189 9, 0xFFFF, sum = 0
8165 12:11:48.014297 10, 0xFFFF, sum = 0
8166 12:11:48.017517 11, 0xFFFF, sum = 0
8167 12:11:48.020761 12, 0xFFFF, sum = 0
8168 12:11:48.020886 13, 0xFFFF, sum = 0
8169 12:11:48.024328 14, 0x0, sum = 1
8170 12:11:48.024443 15, 0x0, sum = 2
8171 12:11:48.027767 16, 0x0, sum = 3
8172 12:11:48.027855 17, 0x0, sum = 4
8173 12:11:48.027923 best_step = 15
8174 12:11:48.027986
8175 12:11:48.031210 ==
8176 12:11:48.033960 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 12:11:48.037338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 12:11:48.037444 ==
8179 12:11:48.037529 RX Vref Scan: 0
8180 12:11:48.037595
8181 12:11:48.040682 RX Vref 0 -> 0, step: 1
8182 12:11:48.040772
8183 12:11:48.044161 RX Delay 19 -> 252, step: 4
8184 12:11:48.047541 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8185 12:11:48.050850 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8186 12:11:48.057104 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8187 12:11:48.060403 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8188 12:11:48.063786 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8189 12:11:48.066957 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8190 12:11:48.070811 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8191 12:11:48.077262 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8192 12:11:48.080450 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8193 12:11:48.083644 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8194 12:11:48.087603 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8195 12:11:48.090901 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8196 12:11:48.096994 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8197 12:11:48.100892 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8198 12:11:48.104025 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8199 12:11:48.107404 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8200 12:11:48.107500 ==
8201 12:11:48.110861 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 12:11:48.116858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 12:11:48.116954 ==
8204 12:11:48.117023 DQS Delay:
8205 12:11:48.120455 DQS0 = 0, DQS1 = 0
8206 12:11:48.120581 DQM Delay:
8207 12:11:48.120682 DQM0 = 134, DQM1 = 127
8208 12:11:48.123713 DQ Delay:
8209 12:11:48.127128 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8210 12:11:48.130556 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8211 12:11:48.133889 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8212 12:11:48.137278 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8213 12:11:48.137385
8214 12:11:48.137488
8215 12:11:48.137581
8216 12:11:48.140707 [DramC_TX_OE_Calibration] TA2
8217 12:11:48.143451 Original DQ_B0 (3 6) =30, OEN = 27
8218 12:11:48.146930 Original DQ_B1 (3 6) =30, OEN = 27
8219 12:11:48.150283 24, 0x0, End_B0=24 End_B1=24
8220 12:11:48.150392 25, 0x0, End_B0=25 End_B1=25
8221 12:11:48.153750 26, 0x0, End_B0=26 End_B1=26
8222 12:11:48.157344 27, 0x0, End_B0=27 End_B1=27
8223 12:11:48.160772 28, 0x0, End_B0=28 End_B1=28
8224 12:11:48.163504 29, 0x0, End_B0=29 End_B1=29
8225 12:11:48.163623 30, 0x0, End_B0=30 End_B1=30
8226 12:11:48.166812 31, 0x4141, End_B0=30 End_B1=30
8227 12:11:48.170709 Byte0 end_step=30 best_step=27
8228 12:11:48.174028 Byte1 end_step=30 best_step=27
8229 12:11:48.177373 Byte0 TX OE(2T, 0.5T) = (3, 3)
8230 12:11:48.180483 Byte1 TX OE(2T, 0.5T) = (3, 3)
8231 12:11:48.180594
8232 12:11:48.180688
8233 12:11:48.187136 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8234 12:11:48.190326 CH0 RK1: MR19=303, MR18=2109
8235 12:11:48.197367 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8236 12:11:48.200705 [RxdqsGatingPostProcess] freq 1600
8237 12:11:48.204018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8238 12:11:48.207035 best DQS0 dly(2T, 0.5T) = (1, 1)
8239 12:11:48.211044 best DQS1 dly(2T, 0.5T) = (1, 1)
8240 12:11:48.214178 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8241 12:11:48.217576 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8242 12:11:48.220937 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 12:11:48.224131 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 12:11:48.227635 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 12:11:48.230323 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 12:11:48.230429 Pre-setting of DQS Precalculation
8247 12:11:48.237131 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8248 12:11:48.237245 ==
8249 12:11:48.240603 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 12:11:48.244086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 12:11:48.244179 ==
8252 12:11:48.250932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8253 12:11:48.253778 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8254 12:11:48.257231 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8255 12:11:48.264027 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8256 12:11:48.273531 [CA 0] Center 42 (13~72) winsize 60
8257 12:11:48.276745 [CA 1] Center 42 (12~72) winsize 61
8258 12:11:48.279915 [CA 2] Center 39 (9~69) winsize 61
8259 12:11:48.283342 [CA 3] Center 38 (9~67) winsize 59
8260 12:11:48.286625 [CA 4] Center 38 (9~68) winsize 60
8261 12:11:48.289801 [CA 5] Center 37 (8~67) winsize 60
8262 12:11:48.289883
8263 12:11:48.293686 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8264 12:11:48.293801
8265 12:11:48.297038 [CATrainingPosCal] consider 1 rank data
8266 12:11:48.300248 u2DelayCellTimex100 = 290/100 ps
8267 12:11:48.303558 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8268 12:11:48.310028 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8269 12:11:48.313346 CA2 delay=39 (9~69),Diff = 2 PI (6 cell)
8270 12:11:48.316767 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8271 12:11:48.320093 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8272 12:11:48.323426 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8273 12:11:48.323529
8274 12:11:48.326707 CA PerBit enable=1, Macro0, CA PI delay=37
8275 12:11:48.326793
8276 12:11:48.329953 [CBTSetCACLKResult] CA Dly = 37
8277 12:11:48.333484 CS Dly: 11 (0~42)
8278 12:11:48.336829 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8279 12:11:48.340188 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8280 12:11:48.340277 ==
8281 12:11:48.343533 Dram Type= 6, Freq= 0, CH_1, rank 1
8282 12:11:48.346201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 12:11:48.349619 ==
8284 12:11:48.353008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 12:11:48.356438 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 12:11:48.363208 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 12:11:48.366710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 12:11:48.376857 [CA 0] Center 42 (12~72) winsize 61
8289 12:11:48.380182 [CA 1] Center 41 (12~71) winsize 60
8290 12:11:48.383544 [CA 2] Center 38 (9~68) winsize 60
8291 12:11:48.386924 [CA 3] Center 37 (8~67) winsize 60
8292 12:11:48.390286 [CA 4] Center 38 (9~68) winsize 60
8293 12:11:48.393454 [CA 5] Center 37 (8~67) winsize 60
8294 12:11:48.393560
8295 12:11:48.396983 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8296 12:11:48.397087
8297 12:11:48.400021 [CATrainingPosCal] consider 2 rank data
8298 12:11:48.403495 u2DelayCellTimex100 = 290/100 ps
8299 12:11:48.406698 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8300 12:11:48.413487 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8301 12:11:48.416763 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8302 12:11:48.420048 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8303 12:11:48.423259 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8304 12:11:48.426334 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8305 12:11:48.426422
8306 12:11:48.429713 CA PerBit enable=1, Macro0, CA PI delay=37
8307 12:11:48.429796
8308 12:11:48.433649 [CBTSetCACLKResult] CA Dly = 37
8309 12:11:48.436284 CS Dly: 12 (0~44)
8310 12:11:48.439706 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 12:11:48.443049 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 12:11:48.443171
8313 12:11:48.446555 ----->DramcWriteLeveling(PI) begin...
8314 12:11:48.446673 ==
8315 12:11:48.450074 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 12:11:48.453544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 12:11:48.456315 ==
8318 12:11:48.456432 Write leveling (Byte 0): 24 => 24
8319 12:11:48.459735 Write leveling (Byte 1): 28 => 28
8320 12:11:48.463048 DramcWriteLeveling(PI) end<-----
8321 12:11:48.463162
8322 12:11:48.463255 ==
8323 12:11:48.466494 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 12:11:48.473528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 12:11:48.473616 ==
8326 12:11:48.473682 [Gating] SW mode calibration
8327 12:11:48.483157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8328 12:11:48.486567 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8329 12:11:48.493247 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 12:11:48.496588 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 12:11:48.499754 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8332 12:11:48.503100 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8333 12:11:48.509685 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 12:11:48.512926 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 12:11:48.516080 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 12:11:48.522804 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 12:11:48.526248 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 12:11:48.529522 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 12:11:48.536453 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
8340 12:11:48.539800 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8341 12:11:48.543072 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8342 12:11:48.549930 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:11:48.553404 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:11:48.556778 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 12:11:48.562762 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 12:11:48.566302 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 12:11:48.569733 1 6 8 | B1->B0 | 2525 3f3f | 0 0 | (0 0) (0 0)
8348 12:11:48.575951 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8349 12:11:48.579395 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 12:11:48.582829 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 12:11:48.589616 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:11:48.592899 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 12:11:48.596324 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 12:11:48.602986 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 12:11:48.606243 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8356 12:11:48.609348 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8357 12:11:48.612614 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:11:48.619753 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:11:48.622958 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:11:48.626337 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:11:48.633031 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:11:48.636476 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:11:48.639813 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:11:48.646351 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:11:48.649765 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:11:48.653091 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:11:48.659153 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 12:11:48.662626 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 12:11:48.666337 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 12:11:48.673051 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 12:11:48.675790 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 12:11:48.679130 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8373 12:11:48.686020 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 12:11:48.686144 Total UI for P1: 0, mck2ui 16
8375 12:11:48.692900 best dqsien dly found for B0: ( 1, 9, 12)
8376 12:11:48.693023 Total UI for P1: 0, mck2ui 16
8377 12:11:48.699537 best dqsien dly found for B1: ( 1, 9, 12)
8378 12:11:48.702280 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8379 12:11:48.705811 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8380 12:11:48.705925
8381 12:11:48.709215 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8382 12:11:48.712530 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8383 12:11:48.715758 [Gating] SW calibration Done
8384 12:11:48.715874 ==
8385 12:11:48.719073 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 12:11:48.722423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 12:11:48.722549 ==
8388 12:11:48.726328 RX Vref Scan: 0
8389 12:11:48.726443
8390 12:11:48.726542 RX Vref 0 -> 0, step: 1
8391 12:11:48.726637
8392 12:11:48.729585 RX Delay 0 -> 252, step: 8
8393 12:11:48.732954 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8394 12:11:48.739519 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8395 12:11:48.742954 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8396 12:11:48.745681 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8397 12:11:48.748995 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8398 12:11:48.752301 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8399 12:11:48.756071 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8400 12:11:48.762761 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8401 12:11:48.765799 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8402 12:11:48.769329 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8403 12:11:48.772725 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8404 12:11:48.776190 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8405 12:11:48.782469 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8406 12:11:48.785838 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8407 12:11:48.789096 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8408 12:11:48.792548 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8409 12:11:48.792663 ==
8410 12:11:48.796021 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 12:11:48.802113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 12:11:48.802230 ==
8413 12:11:48.802330 DQS Delay:
8414 12:11:48.805481 DQS0 = 0, DQS1 = 0
8415 12:11:48.805593 DQM Delay:
8416 12:11:48.805694 DQM0 = 137, DQM1 = 133
8417 12:11:48.808916 DQ Delay:
8418 12:11:48.812454 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8419 12:11:48.815766 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8420 12:11:48.819200 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8421 12:11:48.822497 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8422 12:11:48.822618
8423 12:11:48.822716
8424 12:11:48.822812 ==
8425 12:11:48.825739 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:11:48.829030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:11:48.832372 ==
8428 12:11:48.832485
8429 12:11:48.832584
8430 12:11:48.832678 TX Vref Scan disable
8431 12:11:48.835659 == TX Byte 0 ==
8432 12:11:48.839031 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8433 12:11:48.842281 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8434 12:11:48.845832 == TX Byte 1 ==
8435 12:11:48.849170 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8436 12:11:48.851976 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8437 12:11:48.855343 ==
8438 12:11:48.855457 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 12:11:48.862244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 12:11:48.862368 ==
8441 12:11:48.874389
8442 12:11:48.877848 TX Vref early break, caculate TX vref
8443 12:11:48.881284 TX Vref=16, minBit 11, minWin=22, winSum=379
8444 12:11:48.884117 TX Vref=18, minBit 0, minWin=23, winSum=383
8445 12:11:48.887540 TX Vref=20, minBit 0, minWin=23, winSum=395
8446 12:11:48.890949 TX Vref=22, minBit 9, minWin=24, winSum=406
8447 12:11:48.894481 TX Vref=24, minBit 1, minWin=25, winSum=418
8448 12:11:48.901347 TX Vref=26, minBit 0, minWin=25, winSum=427
8449 12:11:48.904677 TX Vref=28, minBit 0, minWin=26, winSum=430
8450 12:11:48.907461 TX Vref=30, minBit 0, minWin=26, winSum=421
8451 12:11:48.910783 TX Vref=32, minBit 0, minWin=24, winSum=414
8452 12:11:48.914254 TX Vref=34, minBit 0, minWin=24, winSum=403
8453 12:11:48.921121 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8454 12:11:48.921241
8455 12:11:48.924491 Final TX Range 0 Vref 28
8456 12:11:48.924610
8457 12:11:48.924709 ==
8458 12:11:48.927759 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 12:11:48.931071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 12:11:48.931184 ==
8461 12:11:48.931281
8462 12:11:48.931387
8463 12:11:48.934299 TX Vref Scan disable
8464 12:11:48.940964 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8465 12:11:48.941081 == TX Byte 0 ==
8466 12:11:48.944132 u2DelayCellOfst[0]=16 cells (5 PI)
8467 12:11:48.947479 u2DelayCellOfst[1]=10 cells (3 PI)
8468 12:11:48.950601 u2DelayCellOfst[2]=0 cells (0 PI)
8469 12:11:48.953917 u2DelayCellOfst[3]=6 cells (2 PI)
8470 12:11:48.957463 u2DelayCellOfst[4]=10 cells (3 PI)
8471 12:11:48.960833 u2DelayCellOfst[5]=16 cells (5 PI)
8472 12:11:48.964323 u2DelayCellOfst[6]=16 cells (5 PI)
8473 12:11:48.964438 u2DelayCellOfst[7]=6 cells (2 PI)
8474 12:11:48.971128 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8475 12:11:48.974398 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8476 12:11:48.974511 == TX Byte 1 ==
8477 12:11:48.977504 u2DelayCellOfst[8]=0 cells (0 PI)
8478 12:11:48.980751 u2DelayCellOfst[9]=3 cells (1 PI)
8479 12:11:48.984096 u2DelayCellOfst[10]=10 cells (3 PI)
8480 12:11:48.987575 u2DelayCellOfst[11]=3 cells (1 PI)
8481 12:11:48.990847 u2DelayCellOfst[12]=13 cells (4 PI)
8482 12:11:48.994278 u2DelayCellOfst[13]=13 cells (4 PI)
8483 12:11:48.997669 u2DelayCellOfst[14]=16 cells (5 PI)
8484 12:11:49.001188 u2DelayCellOfst[15]=13 cells (4 PI)
8485 12:11:49.003902 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8486 12:11:49.007293 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8487 12:11:49.010554 DramC Write-DBI on
8488 12:11:49.010666 ==
8489 12:11:49.013947 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 12:11:49.017452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 12:11:49.017564 ==
8492 12:11:49.017661
8493 12:11:49.020706
8494 12:11:49.020816 TX Vref Scan disable
8495 12:11:49.024079 == TX Byte 0 ==
8496 12:11:49.027542 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8497 12:11:49.030814 == TX Byte 1 ==
8498 12:11:49.034313 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8499 12:11:49.034405 DramC Write-DBI off
8500 12:11:49.034473
8501 12:11:49.037639 [DATLAT]
8502 12:11:49.037724 Freq=1600, CH1 RK0
8503 12:11:49.037792
8504 12:11:49.040808 DATLAT Default: 0xf
8505 12:11:49.040892 0, 0xFFFF, sum = 0
8506 12:11:49.043933 1, 0xFFFF, sum = 0
8507 12:11:49.044047 2, 0xFFFF, sum = 0
8508 12:11:49.047274 3, 0xFFFF, sum = 0
8509 12:11:49.047373 4, 0xFFFF, sum = 0
8510 12:11:49.050488 5, 0xFFFF, sum = 0
8511 12:11:49.050577 6, 0xFFFF, sum = 0
8512 12:11:49.054383 7, 0xFFFF, sum = 0
8513 12:11:49.057605 8, 0xFFFF, sum = 0
8514 12:11:49.057695 9, 0xFFFF, sum = 0
8515 12:11:49.060960 10, 0xFFFF, sum = 0
8516 12:11:49.061048 11, 0xFFFF, sum = 0
8517 12:11:49.064311 12, 0xFFFF, sum = 0
8518 12:11:49.064398 13, 0xFFFF, sum = 0
8519 12:11:49.066965 14, 0x0, sum = 1
8520 12:11:49.067062 15, 0x0, sum = 2
8521 12:11:49.070453 16, 0x0, sum = 3
8522 12:11:49.070569 17, 0x0, sum = 4
8523 12:11:49.073775 best_step = 15
8524 12:11:49.073884
8525 12:11:49.073978 ==
8526 12:11:49.077106 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 12:11:49.080513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 12:11:49.080601 ==
8529 12:11:49.080668 RX Vref Scan: 1
8530 12:11:49.083751
8531 12:11:49.083837 Set Vref Range= 24 -> 127
8532 12:11:49.083905
8533 12:11:49.087012 RX Vref 24 -> 127, step: 1
8534 12:11:49.087097
8535 12:11:49.090736 RX Delay 27 -> 252, step: 4
8536 12:11:49.090823
8537 12:11:49.093907 Set Vref, RX VrefLevel [Byte0]: 24
8538 12:11:49.097207 [Byte1]: 24
8539 12:11:49.097294
8540 12:11:49.100583 Set Vref, RX VrefLevel [Byte0]: 25
8541 12:11:49.103992 [Byte1]: 25
8542 12:11:49.104079
8543 12:11:49.106764 Set Vref, RX VrefLevel [Byte0]: 26
8544 12:11:49.110247 [Byte1]: 26
8545 12:11:49.114300
8546 12:11:49.114387 Set Vref, RX VrefLevel [Byte0]: 27
8547 12:11:49.117017 [Byte1]: 27
8548 12:11:49.121742
8549 12:11:49.121831 Set Vref, RX VrefLevel [Byte0]: 28
8550 12:11:49.124546 [Byte1]: 28
8551 12:11:49.129201
8552 12:11:49.129292 Set Vref, RX VrefLevel [Byte0]: 29
8553 12:11:49.132584 [Byte1]: 29
8554 12:11:49.136674
8555 12:11:49.136761 Set Vref, RX VrefLevel [Byte0]: 30
8556 12:11:49.139937 [Byte1]: 30
8557 12:11:49.144136
8558 12:11:49.144223 Set Vref, RX VrefLevel [Byte0]: 31
8559 12:11:49.147465 [Byte1]: 31
8560 12:11:49.151294
8561 12:11:49.151403 Set Vref, RX VrefLevel [Byte0]: 32
8562 12:11:49.155065 [Byte1]: 32
8563 12:11:49.158881
8564 12:11:49.158972 Set Vref, RX VrefLevel [Byte0]: 33
8565 12:11:49.162812 [Byte1]: 33
8566 12:11:49.166816
8567 12:11:49.166904 Set Vref, RX VrefLevel [Byte0]: 34
8568 12:11:49.170077 [Byte1]: 34
8569 12:11:49.173951
8570 12:11:49.174041 Set Vref, RX VrefLevel [Byte0]: 35
8571 12:11:49.177366 [Byte1]: 35
8572 12:11:49.181429
8573 12:11:49.181540 Set Vref, RX VrefLevel [Byte0]: 36
8574 12:11:49.184758 [Byte1]: 36
8575 12:11:49.189610
8576 12:11:49.189697 Set Vref, RX VrefLevel [Byte0]: 37
8577 12:11:49.192379 [Byte1]: 37
8578 12:11:49.196931
8579 12:11:49.197017 Set Vref, RX VrefLevel [Byte0]: 38
8580 12:11:49.200305 [Byte1]: 38
8581 12:11:49.204136
8582 12:11:49.204222 Set Vref, RX VrefLevel [Byte0]: 39
8583 12:11:49.207455 [Byte1]: 39
8584 12:11:49.211613
8585 12:11:49.211699 Set Vref, RX VrefLevel [Byte0]: 40
8586 12:11:49.215541 [Byte1]: 40
8587 12:11:49.219384
8588 12:11:49.219498 Set Vref, RX VrefLevel [Byte0]: 41
8589 12:11:49.222835 [Byte1]: 41
8590 12:11:49.226966
8591 12:11:49.227055 Set Vref, RX VrefLevel [Byte0]: 42
8592 12:11:49.230306 [Byte1]: 42
8593 12:11:49.234361
8594 12:11:49.234447 Set Vref, RX VrefLevel [Byte0]: 43
8595 12:11:49.237802 [Byte1]: 43
8596 12:11:49.241860
8597 12:11:49.241947 Set Vref, RX VrefLevel [Byte0]: 44
8598 12:11:49.245190 [Byte1]: 44
8599 12:11:49.249450
8600 12:11:49.249562 Set Vref, RX VrefLevel [Byte0]: 45
8601 12:11:49.252775 [Byte1]: 45
8602 12:11:49.257484
8603 12:11:49.257571 Set Vref, RX VrefLevel [Byte0]: 46
8604 12:11:49.260122 [Byte1]: 46
8605 12:11:49.264707
8606 12:11:49.264795 Set Vref, RX VrefLevel [Byte0]: 47
8607 12:11:49.267865 [Byte1]: 47
8608 12:11:49.272242
8609 12:11:49.272358 Set Vref, RX VrefLevel [Byte0]: 48
8610 12:11:49.275566 [Byte1]: 48
8611 12:11:49.279707
8612 12:11:49.279794 Set Vref, RX VrefLevel [Byte0]: 49
8613 12:11:49.282661 [Byte1]: 49
8614 12:11:49.287287
8615 12:11:49.287387 Set Vref, RX VrefLevel [Byte0]: 50
8616 12:11:49.290770 [Byte1]: 50
8617 12:11:49.294982
8618 12:11:49.295096 Set Vref, RX VrefLevel [Byte0]: 51
8619 12:11:49.298169 [Byte1]: 51
8620 12:11:49.302219
8621 12:11:49.302329 Set Vref, RX VrefLevel [Byte0]: 52
8622 12:11:49.305605 [Byte1]: 52
8623 12:11:49.309664
8624 12:11:49.309749 Set Vref, RX VrefLevel [Byte0]: 53
8625 12:11:49.312902 [Byte1]: 53
8626 12:11:49.317074
8627 12:11:49.317191 Set Vref, RX VrefLevel [Byte0]: 54
8628 12:11:49.320431 [Byte1]: 54
8629 12:11:49.325002
8630 12:11:49.325121 Set Vref, RX VrefLevel [Byte0]: 55
8631 12:11:49.328175 [Byte1]: 55
8632 12:11:49.332231
8633 12:11:49.332345 Set Vref, RX VrefLevel [Byte0]: 56
8634 12:11:49.335631 [Byte1]: 56
8635 12:11:49.339699
8636 12:11:49.339810 Set Vref, RX VrefLevel [Byte0]: 57
8637 12:11:49.343192 [Byte1]: 57
8638 12:11:49.347170
8639 12:11:49.347280 Set Vref, RX VrefLevel [Byte0]: 58
8640 12:11:49.350603 [Byte1]: 58
8641 12:11:49.355373
8642 12:11:49.355496 Set Vref, RX VrefLevel [Byte0]: 59
8643 12:11:49.358045 [Byte1]: 59
8644 12:11:49.362715
8645 12:11:49.362828 Set Vref, RX VrefLevel [Byte0]: 60
8646 12:11:49.366165 [Byte1]: 60
8647 12:11:49.370384
8648 12:11:49.370471 Set Vref, RX VrefLevel [Byte0]: 61
8649 12:11:49.373544 [Byte1]: 61
8650 12:11:49.377358
8651 12:11:49.377446 Set Vref, RX VrefLevel [Byte0]: 62
8652 12:11:49.381070 [Byte1]: 62
8653 12:11:49.385356
8654 12:11:49.385476 Set Vref, RX VrefLevel [Byte0]: 63
8655 12:11:49.388119 [Byte1]: 63
8656 12:11:49.392841
8657 12:11:49.392966 Set Vref, RX VrefLevel [Byte0]: 64
8658 12:11:49.396276 [Byte1]: 64
8659 12:11:49.400408
8660 12:11:49.400502 Set Vref, RX VrefLevel [Byte0]: 65
8661 12:11:49.403657 [Byte1]: 65
8662 12:11:49.407739
8663 12:11:49.407828 Set Vref, RX VrefLevel [Byte0]: 66
8664 12:11:49.411125 [Byte1]: 66
8665 12:11:49.415087
8666 12:11:49.415217 Set Vref, RX VrefLevel [Byte0]: 67
8667 12:11:49.418337 [Byte1]: 67
8668 12:11:49.422469
8669 12:11:49.422608 Set Vref, RX VrefLevel [Byte0]: 68
8670 12:11:49.425832 [Byte1]: 68
8671 12:11:49.430420
8672 12:11:49.430516 Set Vref, RX VrefLevel [Byte0]: 69
8673 12:11:49.433834 [Byte1]: 69
8674 12:11:49.438068
8675 12:11:49.438171 Set Vref, RX VrefLevel [Byte0]: 70
8676 12:11:49.441522 [Byte1]: 70
8677 12:11:49.445557
8678 12:11:49.445652 Set Vref, RX VrefLevel [Byte0]: 71
8679 12:11:49.448939 [Byte1]: 71
8680 12:11:49.453150
8681 12:11:49.453238 Set Vref, RX VrefLevel [Byte0]: 72
8682 12:11:49.456581 [Byte1]: 72
8683 12:11:49.460685
8684 12:11:49.460773 Set Vref, RX VrefLevel [Byte0]: 73
8685 12:11:49.463433 [Byte1]: 73
8686 12:11:49.468019
8687 12:11:49.468110 Set Vref, RX VrefLevel [Byte0]: 74
8688 12:11:49.471472 [Byte1]: 74
8689 12:11:49.475564
8690 12:11:49.475661 Set Vref, RX VrefLevel [Byte0]: 75
8691 12:11:49.478926 [Byte1]: 75
8692 12:11:49.482882
8693 12:11:49.482989 Set Vref, RX VrefLevel [Byte0]: 76
8694 12:11:49.486146 [Byte1]: 76
8695 12:11:49.490839
8696 12:11:49.490951 Final RX Vref Byte 0 = 57 to rank0
8697 12:11:49.494116 Final RX Vref Byte 1 = 54 to rank0
8698 12:11:49.497453 Final RX Vref Byte 0 = 57 to rank1
8699 12:11:49.500678 Final RX Vref Byte 1 = 54 to rank1==
8700 12:11:49.503933 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 12:11:49.510711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 12:11:49.510867 ==
8703 12:11:49.510972 DQS Delay:
8704 12:11:49.511064 DQS0 = 0, DQS1 = 0
8705 12:11:49.514030 DQM Delay:
8706 12:11:49.514138 DQM0 = 134, DQM1 = 131
8707 12:11:49.517505 DQ Delay:
8708 12:11:49.520305 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8709 12:11:49.523979 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8710 12:11:49.526812 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8711 12:11:49.530107 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8712 12:11:49.530233
8713 12:11:49.530329
8714 12:11:49.530420
8715 12:11:49.533985 [DramC_TX_OE_Calibration] TA2
8716 12:11:49.537328 Original DQ_B0 (3 6) =30, OEN = 27
8717 12:11:49.540753 Original DQ_B1 (3 6) =30, OEN = 27
8718 12:11:49.543507 24, 0x0, End_B0=24 End_B1=24
8719 12:11:49.543643 25, 0x0, End_B0=25 End_B1=25
8720 12:11:49.546955 26, 0x0, End_B0=26 End_B1=26
8721 12:11:49.550338 27, 0x0, End_B0=27 End_B1=27
8722 12:11:49.553843 28, 0x0, End_B0=28 End_B1=28
8723 12:11:49.557304 29, 0x0, End_B0=29 End_B1=29
8724 12:11:49.557432 30, 0x0, End_B0=30 End_B1=30
8725 12:11:49.559968 31, 0x5151, End_B0=30 End_B1=30
8726 12:11:49.563480 Byte0 end_step=30 best_step=27
8727 12:11:49.566763 Byte1 end_step=30 best_step=27
8728 12:11:49.570188 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 12:11:49.573502 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 12:11:49.573598
8731 12:11:49.573666
8732 12:11:49.580251 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8733 12:11:49.583778 CH1 RK0: MR19=303, MR18=1826
8734 12:11:49.590215 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8735 12:11:49.590399
8736 12:11:49.593639 ----->DramcWriteLeveling(PI) begin...
8737 12:11:49.593789 ==
8738 12:11:49.597052 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 12:11:49.600336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 12:11:49.600489 ==
8741 12:11:49.603273 Write leveling (Byte 0): 26 => 26
8742 12:11:49.606637 Write leveling (Byte 1): 28 => 28
8743 12:11:49.610401 DramcWriteLeveling(PI) end<-----
8744 12:11:49.610561
8745 12:11:49.610691 ==
8746 12:11:49.613466 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 12:11:49.616750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 12:11:49.616896 ==
8749 12:11:49.620135 [Gating] SW mode calibration
8750 12:11:49.626938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 12:11:49.633588 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 12:11:49.636880 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 12:11:49.640241 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 12:11:49.646952 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8755 12:11:49.650494 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8756 12:11:49.653240 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 12:11:49.659991 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 12:11:49.663320 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 12:11:49.666816 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 12:11:49.673659 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 12:11:49.676773 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8762 12:11:49.680284 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 0)
8763 12:11:49.686579 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 12:11:49.689947 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:11:49.693157 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 12:11:49.700018 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 12:11:49.703425 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 12:11:49.706693 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 12:11:49.713386 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 12:11:49.716636 1 6 8 | B1->B0 | 3c3c 2626 | 0 0 | (0 0) (0 0)
8771 12:11:49.719383 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8772 12:11:49.726610 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 12:11:49.730052 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 12:11:49.732738 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 12:11:49.739879 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 12:11:49.743204 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:11:49.746361 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 12:11:49.752837 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8779 12:11:49.756224 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8780 12:11:49.759746 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:11:49.765950 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:11:49.769333 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:11:49.772772 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:11:49.776335 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:11:49.783047 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:11:49.785775 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:11:49.789359 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:11:49.796006 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:11:49.799112 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:11:49.802647 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:11:49.809568 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:11:49.812826 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:11:49.816171 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8794 12:11:49.822677 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8795 12:11:49.826176 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8796 12:11:49.829241 Total UI for P1: 0, mck2ui 16
8797 12:11:49.832385 best dqsien dly found for B1: ( 1, 9, 6)
8798 12:11:49.835774 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 12:11:49.839044 Total UI for P1: 0, mck2ui 16
8800 12:11:49.842305 best dqsien dly found for B0: ( 1, 9, 14)
8801 12:11:49.846184 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8802 12:11:49.849441 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8803 12:11:49.849554
8804 12:11:49.856023 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8805 12:11:49.859557 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8806 12:11:49.859663 [Gating] SW calibration Done
8807 12:11:49.862879 ==
8808 12:11:49.865674 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 12:11:49.869035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 12:11:49.869143 ==
8811 12:11:49.869221 RX Vref Scan: 0
8812 12:11:49.869285
8813 12:11:49.872447 RX Vref 0 -> 0, step: 1
8814 12:11:49.872552
8815 12:11:49.875921 RX Delay 0 -> 252, step: 8
8816 12:11:49.879206 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8817 12:11:49.882644 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8818 12:11:49.885809 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8819 12:11:49.892628 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8820 12:11:49.895344 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8821 12:11:49.898691 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8822 12:11:49.902051 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8823 12:11:49.905563 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8824 12:11:49.911741 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8825 12:11:49.915320 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8826 12:11:49.918643 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8827 12:11:49.922463 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8828 12:11:49.925744 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8829 12:11:49.931826 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8830 12:11:49.935619 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8831 12:11:49.938941 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8832 12:11:49.939051 ==
8833 12:11:49.941755 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 12:11:49.945072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 12:11:49.948635 ==
8836 12:11:49.948730 DQS Delay:
8837 12:11:49.948798 DQS0 = 0, DQS1 = 0
8838 12:11:49.951940 DQM Delay:
8839 12:11:49.952022 DQM0 = 136, DQM1 = 133
8840 12:11:49.955146 DQ Delay:
8841 12:11:49.958431 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8842 12:11:49.962317 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8843 12:11:49.965742 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8844 12:11:49.968422 DQ12 =143, DQ13 =143, DQ14 =135, DQ15 =143
8845 12:11:49.968518
8846 12:11:49.968609
8847 12:11:49.968676 ==
8848 12:11:49.971779 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 12:11:49.975269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 12:11:49.975381 ==
8851 12:11:49.975453
8852 12:11:49.978664
8853 12:11:49.978759 TX Vref Scan disable
8854 12:11:49.982031 == TX Byte 0 ==
8855 12:11:49.985506 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8856 12:11:49.988928 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8857 12:11:49.991596 == TX Byte 1 ==
8858 12:11:49.994953 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8859 12:11:49.998402 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8860 12:11:49.998513 ==
8861 12:11:50.001841 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 12:11:50.008617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 12:11:50.008750 ==
8864 12:11:50.020860
8865 12:11:50.024226 TX Vref early break, caculate TX vref
8866 12:11:50.027510 TX Vref=16, minBit 0, minWin=23, winSum=383
8867 12:11:50.030802 TX Vref=18, minBit 0, minWin=23, winSum=391
8868 12:11:50.034087 TX Vref=20, minBit 13, minWin=24, winSum=407
8869 12:11:50.037388 TX Vref=22, minBit 0, minWin=24, winSum=409
8870 12:11:50.040672 TX Vref=24, minBit 0, minWin=25, winSum=419
8871 12:11:50.047919 TX Vref=26, minBit 0, minWin=25, winSum=424
8872 12:11:50.050550 TX Vref=28, minBit 0, minWin=26, winSum=429
8873 12:11:50.053910 TX Vref=30, minBit 0, minWin=25, winSum=422
8874 12:11:50.057564 TX Vref=32, minBit 1, minWin=24, winSum=414
8875 12:11:50.060762 TX Vref=34, minBit 6, minWin=24, winSum=407
8876 12:11:50.063959 TX Vref=36, minBit 0, minWin=24, winSum=399
8877 12:11:50.070522 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8878 12:11:50.070673
8879 12:11:50.074042 Final TX Range 0 Vref 28
8880 12:11:50.074138
8881 12:11:50.074207 ==
8882 12:11:50.077494 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 12:11:50.080868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 12:11:50.080962 ==
8885 12:11:50.081032
8886 12:11:50.081094
8887 12:11:50.084400 TX Vref Scan disable
8888 12:11:50.090569 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8889 12:11:50.090678 == TX Byte 0 ==
8890 12:11:50.093891 u2DelayCellOfst[0]=16 cells (5 PI)
8891 12:11:50.097177 u2DelayCellOfst[1]=10 cells (3 PI)
8892 12:11:50.100563 u2DelayCellOfst[2]=0 cells (0 PI)
8893 12:11:50.104041 u2DelayCellOfst[3]=6 cells (2 PI)
8894 12:11:50.107493 u2DelayCellOfst[4]=6 cells (2 PI)
8895 12:11:50.110240 u2DelayCellOfst[5]=16 cells (5 PI)
8896 12:11:50.113558 u2DelayCellOfst[6]=16 cells (5 PI)
8897 12:11:50.116931 u2DelayCellOfst[7]=6 cells (2 PI)
8898 12:11:50.120506 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8899 12:11:50.123908 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 12:11:50.127290 == TX Byte 1 ==
8901 12:11:50.130655 u2DelayCellOfst[8]=0 cells (0 PI)
8902 12:11:50.133440 u2DelayCellOfst[9]=3 cells (1 PI)
8903 12:11:50.133532 u2DelayCellOfst[10]=10 cells (3 PI)
8904 12:11:50.136566 u2DelayCellOfst[11]=3 cells (1 PI)
8905 12:11:50.140570 u2DelayCellOfst[12]=13 cells (4 PI)
8906 12:11:50.143899 u2DelayCellOfst[13]=16 cells (5 PI)
8907 12:11:50.147174 u2DelayCellOfst[14]=16 cells (5 PI)
8908 12:11:50.150344 u2DelayCellOfst[15]=16 cells (5 PI)
8909 12:11:50.157021 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8910 12:11:50.159857 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8911 12:11:50.159955 DramC Write-DBI on
8912 12:11:50.160023 ==
8913 12:11:50.163288 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 12:11:50.169919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 12:11:50.170010 ==
8916 12:11:50.170079
8917 12:11:50.170142
8918 12:11:50.170202 TX Vref Scan disable
8919 12:11:50.174113 == TX Byte 0 ==
8920 12:11:50.177440 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8921 12:11:50.180975 == TX Byte 1 ==
8922 12:11:50.184205 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8923 12:11:50.184333 DramC Write-DBI off
8924 12:11:50.187516
8925 12:11:50.187605 [DATLAT]
8926 12:11:50.187682 Freq=1600, CH1 RK1
8927 12:11:50.187758
8928 12:11:50.190950 DATLAT Default: 0xf
8929 12:11:50.191038 0, 0xFFFF, sum = 0
8930 12:11:50.194396 1, 0xFFFF, sum = 0
8931 12:11:50.194479 2, 0xFFFF, sum = 0
8932 12:11:50.197779 3, 0xFFFF, sum = 0
8933 12:11:50.197876 4, 0xFFFF, sum = 0
8934 12:11:50.201098 5, 0xFFFF, sum = 0
8935 12:11:50.204535 6, 0xFFFF, sum = 0
8936 12:11:50.204635 7, 0xFFFF, sum = 0
8937 12:11:50.207860 8, 0xFFFF, sum = 0
8938 12:11:50.207948 9, 0xFFFF, sum = 0
8939 12:11:50.210651 10, 0xFFFF, sum = 0
8940 12:11:50.210727 11, 0xFFFF, sum = 0
8941 12:11:50.214032 12, 0xFFFF, sum = 0
8942 12:11:50.214111 13, 0xFFFF, sum = 0
8943 12:11:50.217341 14, 0x0, sum = 1
8944 12:11:50.217429 15, 0x0, sum = 2
8945 12:11:50.220763 16, 0x0, sum = 3
8946 12:11:50.220848 17, 0x0, sum = 4
8947 12:11:50.224297 best_step = 15
8948 12:11:50.224384
8949 12:11:50.224463 ==
8950 12:11:50.227051 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 12:11:50.230467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 12:11:50.230547 ==
8953 12:11:50.230632 RX Vref Scan: 0
8954 12:11:50.233831
8955 12:11:50.233907 RX Vref 0 -> 0, step: 1
8956 12:11:50.233980
8957 12:11:50.237150 RX Delay 19 -> 252, step: 4
8958 12:11:50.240607 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8959 12:11:50.247118 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8960 12:11:50.250440 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
8961 12:11:50.253770 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8962 12:11:50.256913 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8963 12:11:50.260403 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8964 12:11:50.263635 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8965 12:11:50.270384 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8966 12:11:50.273831 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8967 12:11:50.277089 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8968 12:11:50.280702 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8969 12:11:50.283768 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8970 12:11:50.290547 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8971 12:11:50.293868 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8972 12:11:50.297387 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8973 12:11:50.300112 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8974 12:11:50.300259 ==
8975 12:11:50.303550 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 12:11:50.310131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 12:11:50.310287 ==
8978 12:11:50.310381 DQS Delay:
8979 12:11:50.313547 DQS0 = 0, DQS1 = 0
8980 12:11:50.313661 DQM Delay:
8981 12:11:50.313765 DQM0 = 134, DQM1 = 130
8982 12:11:50.316971 DQ Delay:
8983 12:11:50.320386 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =130
8984 12:11:50.323707 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8985 12:11:50.327024 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8986 12:11:50.330435 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8987 12:11:50.330577
8988 12:11:50.330676
8989 12:11:50.330782
8990 12:11:50.333852 [DramC_TX_OE_Calibration] TA2
8991 12:11:50.336678 Original DQ_B0 (3 6) =30, OEN = 27
8992 12:11:50.340108 Original DQ_B1 (3 6) =30, OEN = 27
8993 12:11:50.343581 24, 0x0, End_B0=24 End_B1=24
8994 12:11:50.343674 25, 0x0, End_B0=25 End_B1=25
8995 12:11:50.346980 26, 0x0, End_B0=26 End_B1=26
8996 12:11:50.350293 27, 0x0, End_B0=27 End_B1=27
8997 12:11:50.353614 28, 0x0, End_B0=28 End_B1=28
8998 12:11:50.356993 29, 0x0, End_B0=29 End_B1=29
8999 12:11:50.357107 30, 0x0, End_B0=30 End_B1=30
9000 12:11:50.360290 31, 0x4141, End_B0=30 End_B1=30
9001 12:11:50.363563 Byte0 end_step=30 best_step=27
9002 12:11:50.366889 Byte1 end_step=30 best_step=27
9003 12:11:50.370123 Byte0 TX OE(2T, 0.5T) = (3, 3)
9004 12:11:50.373525 Byte1 TX OE(2T, 0.5T) = (3, 3)
9005 12:11:50.373609
9006 12:11:50.373676
9007 12:11:50.379753 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
9008 12:11:50.383285 CH1 RK1: MR19=303, MR18=220A
9009 12:11:50.389717 CH1_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
9010 12:11:50.393556 [RxdqsGatingPostProcess] freq 1600
9011 12:11:50.396883 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9012 12:11:50.400364 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 12:11:50.403017 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 12:11:50.406496 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 12:11:50.409788 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 12:11:50.413125 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 12:11:50.416494 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 12:11:50.419936 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 12:11:50.423137 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 12:11:50.426501 Pre-setting of DQS Precalculation
9021 12:11:50.429791 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9022 12:11:50.436491 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9023 12:11:50.443175 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9024 12:11:50.443307
9025 12:11:50.446787
9026 12:11:50.446897 [Calibration Summary] 3200 Mbps
9027 12:11:50.450182 CH 0, Rank 0
9028 12:11:50.450302 SW Impedance : PASS
9029 12:11:50.453576 DUTY Scan : NO K
9030 12:11:50.456969 ZQ Calibration : PASS
9031 12:11:50.457083 Jitter Meter : NO K
9032 12:11:50.460338 CBT Training : PASS
9033 12:11:50.463657 Write leveling : PASS
9034 12:11:50.463762 RX DQS gating : PASS
9035 12:11:50.466905 RX DQ/DQS(RDDQC) : PASS
9036 12:11:50.470007 TX DQ/DQS : PASS
9037 12:11:50.470102 RX DATLAT : PASS
9038 12:11:50.473181 RX DQ/DQS(Engine): PASS
9039 12:11:50.473270 TX OE : PASS
9040 12:11:50.476438 All Pass.
9041 12:11:50.476560
9042 12:11:50.476664 CH 0, Rank 1
9043 12:11:50.479844 SW Impedance : PASS
9044 12:11:50.483219 DUTY Scan : NO K
9045 12:11:50.483331 ZQ Calibration : PASS
9046 12:11:50.486587 Jitter Meter : NO K
9047 12:11:50.486691 CBT Training : PASS
9048 12:11:50.489986 Write leveling : PASS
9049 12:11:50.493271 RX DQS gating : PASS
9050 12:11:50.493389 RX DQ/DQS(RDDQC) : PASS
9051 12:11:50.496465 TX DQ/DQS : PASS
9052 12:11:50.499796 RX DATLAT : PASS
9053 12:11:50.499914 RX DQ/DQS(Engine): PASS
9054 12:11:50.503113 TX OE : PASS
9055 12:11:50.503228 All Pass.
9056 12:11:50.503341
9057 12:11:50.506414 CH 1, Rank 0
9058 12:11:50.506528 SW Impedance : PASS
9059 12:11:50.509840 DUTY Scan : NO K
9060 12:11:50.513246 ZQ Calibration : PASS
9061 12:11:50.513354 Jitter Meter : NO K
9062 12:11:50.516497 CBT Training : PASS
9063 12:11:50.519873 Write leveling : PASS
9064 12:11:50.519977 RX DQS gating : PASS
9065 12:11:50.523299 RX DQ/DQS(RDDQC) : PASS
9066 12:11:50.526626 TX DQ/DQS : PASS
9067 12:11:50.526717 RX DATLAT : PASS
9068 12:11:50.529938 RX DQ/DQS(Engine): PASS
9069 12:11:50.530041 TX OE : PASS
9070 12:11:50.533141 All Pass.
9071 12:11:50.533250
9072 12:11:50.533346 CH 1, Rank 1
9073 12:11:50.536515 SW Impedance : PASS
9074 12:11:50.536619 DUTY Scan : NO K
9075 12:11:50.539888 ZQ Calibration : PASS
9076 12:11:50.543303 Jitter Meter : NO K
9077 12:11:50.543450 CBT Training : PASS
9078 12:11:50.546788 Write leveling : PASS
9079 12:11:50.549543 RX DQS gating : PASS
9080 12:11:50.549659 RX DQ/DQS(RDDQC) : PASS
9081 12:11:50.553002 TX DQ/DQS : PASS
9082 12:11:50.556390 RX DATLAT : PASS
9083 12:11:50.556500 RX DQ/DQS(Engine): PASS
9084 12:11:50.559948 TX OE : PASS
9085 12:11:50.560070 All Pass.
9086 12:11:50.560168
9087 12:11:50.563267 DramC Write-DBI on
9088 12:11:50.566537 PER_BANK_REFRESH: Hybrid Mode
9089 12:11:50.566646 TX_TRACKING: ON
9090 12:11:50.576458 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9091 12:11:50.583023 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9092 12:11:50.589900 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 12:11:50.592660 [FAST_K] Save calibration result to emmc
9094 12:11:50.595984 sync common calibartion params.
9095 12:11:50.599860 sync cbt_mode0:1, 1:1
9096 12:11:50.602624 dram_init: ddr_geometry: 2
9097 12:11:50.602739 dram_init: ddr_geometry: 2
9098 12:11:50.606066 dram_init: ddr_geometry: 2
9099 12:11:50.609460 0:dram_rank_size:100000000
9100 12:11:50.612640 1:dram_rank_size:100000000
9101 12:11:50.616003 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9102 12:11:50.619291 DFS_SHUFFLE_HW_MODE: ON
9103 12:11:50.622711 dramc_set_vcore_voltage set vcore to 725000
9104 12:11:50.626195 Read voltage for 1600, 0
9105 12:11:50.626309 Vio18 = 0
9106 12:11:50.626377 Vcore = 725000
9107 12:11:50.629630 Vdram = 0
9108 12:11:50.629790 Vddq = 0
9109 12:11:50.629916 Vmddr = 0
9110 12:11:50.633084 switch to 3200 Mbps bootup
9111 12:11:50.635910 [DramcRunTimeConfig]
9112 12:11:50.636023 PHYPLL
9113 12:11:50.636117 DPM_CONTROL_AFTERK: ON
9114 12:11:50.639865 PER_BANK_REFRESH: ON
9115 12:11:50.642576 REFRESH_OVERHEAD_REDUCTION: ON
9116 12:11:50.642656 CMD_PICG_NEW_MODE: OFF
9117 12:11:50.645875 XRTWTW_NEW_MODE: ON
9118 12:11:50.645952 XRTRTR_NEW_MODE: ON
9119 12:11:50.649461 TX_TRACKING: ON
9120 12:11:50.649547 RDSEL_TRACKING: OFF
9121 12:11:50.652933 DQS Precalculation for DVFS: ON
9122 12:11:50.656365 RX_TRACKING: OFF
9123 12:11:50.656459 HW_GATING DBG: ON
9124 12:11:50.659154 ZQCS_ENABLE_LP4: ON
9125 12:11:50.659256 RX_PICG_NEW_MODE: ON
9126 12:11:50.662574 TX_PICG_NEW_MODE: ON
9127 12:11:50.666021 ENABLE_RX_DCM_DPHY: ON
9128 12:11:50.666114 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9129 12:11:50.669396 DUMMY_READ_FOR_TRACKING: OFF
9130 12:11:50.672750 !!! SPM_CONTROL_AFTERK: OFF
9131 12:11:50.676186 !!! SPM could not control APHY
9132 12:11:50.676274 IMPEDANCE_TRACKING: ON
9133 12:11:50.679666 TEMP_SENSOR: ON
9134 12:11:50.679752 HW_SAVE_FOR_SR: OFF
9135 12:11:50.682803 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9136 12:11:50.686266 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9137 12:11:50.689502 Read ODT Tracking: ON
9138 12:11:50.692862 Refresh Rate DeBounce: ON
9139 12:11:50.692965 DFS_NO_QUEUE_FLUSH: ON
9140 12:11:50.696104 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9141 12:11:50.699554 ENABLE_DFS_RUNTIME_MRW: OFF
9142 12:11:50.702926 DDR_RESERVE_NEW_MODE: ON
9143 12:11:50.703017 MR_CBT_SWITCH_FREQ: ON
9144 12:11:50.706305 =========================
9145 12:11:50.725079 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9146 12:11:50.728519 dram_init: ddr_geometry: 2
9147 12:11:50.746872 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9148 12:11:50.750409 dram_init: dram init end (result: 0)
9149 12:11:50.756587 DRAM-K: Full calibration passed in 24436 msecs
9150 12:11:50.759964 MRC: failed to locate region type 0.
9151 12:11:50.760053 DRAM rank0 size:0x100000000,
9152 12:11:50.763647 DRAM rank1 size=0x100000000
9153 12:11:50.773337 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9154 12:11:50.779744 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9155 12:11:50.786601 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9156 12:11:50.793172 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9157 12:11:50.796524 DRAM rank0 size:0x100000000,
9158 12:11:50.799827 DRAM rank1 size=0x100000000
9159 12:11:50.799949 CBMEM:
9160 12:11:50.803194 IMD: root @ 0xfffff000 254 entries.
9161 12:11:50.806005 IMD: root @ 0xffffec00 62 entries.
9162 12:11:50.809362 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9163 12:11:50.812647 WARNING: RO_VPD is uninitialized or empty.
9164 12:11:50.819654 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9165 12:11:50.826475 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9166 12:11:50.839291 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9167 12:11:50.850868 BS: romstage times (exec / console): total (unknown) / 23971 ms
9168 12:11:50.850996
9169 12:11:50.851091
9170 12:11:50.860549 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9171 12:11:50.864045 ARM64: Exception handlers installed.
9172 12:11:50.867498 ARM64: Testing exception
9173 12:11:50.870806 ARM64: Done test exception
9174 12:11:50.870883 Enumerating buses...
9175 12:11:50.874406 Show all devs... Before device enumeration.
9176 12:11:50.877180 Root Device: enabled 1
9177 12:11:50.880492 CPU_CLUSTER: 0: enabled 1
9178 12:11:50.880593 CPU: 00: enabled 1
9179 12:11:50.884016 Compare with tree...
9180 12:11:50.884092 Root Device: enabled 1
9181 12:11:50.887256 CPU_CLUSTER: 0: enabled 1
9182 12:11:50.890674 CPU: 00: enabled 1
9183 12:11:50.890751 Root Device scanning...
9184 12:11:50.894100 scan_static_bus for Root Device
9185 12:11:50.897329 CPU_CLUSTER: 0 enabled
9186 12:11:50.900737 scan_static_bus for Root Device done
9187 12:11:50.903943 scan_bus: bus Root Device finished in 8 msecs
9188 12:11:50.904024 done
9189 12:11:50.910620 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9190 12:11:50.913820 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9191 12:11:50.920692 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9192 12:11:50.923585 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9193 12:11:50.927602 Allocating resources...
9194 12:11:50.930313 Reading resources...
9195 12:11:50.933556 Root Device read_resources bus 0 link: 0
9196 12:11:50.933669 DRAM rank0 size:0x100000000,
9197 12:11:50.937508 DRAM rank1 size=0x100000000
9198 12:11:50.940852 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9199 12:11:50.943564 CPU: 00 missing read_resources
9200 12:11:50.947096 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9201 12:11:50.953911 Root Device read_resources bus 0 link: 0 done
9202 12:11:50.954037 Done reading resources.
9203 12:11:50.960120 Show resources in subtree (Root Device)...After reading.
9204 12:11:50.963587 Root Device child on link 0 CPU_CLUSTER: 0
9205 12:11:50.967061 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 12:11:50.976740 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 12:11:50.976903 CPU: 00
9208 12:11:50.980249 Root Device assign_resources, bus 0 link: 0
9209 12:11:50.983642 CPU_CLUSTER: 0 missing set_resources
9210 12:11:50.990359 Root Device assign_resources, bus 0 link: 0 done
9211 12:11:50.990524 Done setting resources.
9212 12:11:50.996934 Show resources in subtree (Root Device)...After assigning values.
9213 12:11:51.000202 Root Device child on link 0 CPU_CLUSTER: 0
9214 12:11:51.003617 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 12:11:51.013636 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 12:11:51.013807 CPU: 00
9217 12:11:51.016986 Done allocating resources.
9218 12:11:51.020157 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9219 12:11:51.023477 Enabling resources...
9220 12:11:51.023586 done.
9221 12:11:51.030334 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9222 12:11:51.030428 Initializing devices...
9223 12:11:51.033853 Root Device init
9224 12:11:51.033951 init hardware done!
9225 12:11:51.036715 0x00000018: ctrlr->caps
9226 12:11:51.040132 52.000 MHz: ctrlr->f_max
9227 12:11:51.040235 0.400 MHz: ctrlr->f_min
9228 12:11:51.043471 0x40ff8080: ctrlr->voltages
9229 12:11:51.043570 sclk: 390625
9230 12:11:51.046668 Bus Width = 1
9231 12:11:51.046771 sclk: 390625
9232 12:11:51.049782 Bus Width = 1
9233 12:11:51.049885 Early init status = 3
9234 12:11:51.056497 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9235 12:11:51.059931 in-header: 03 fb 00 00 01 00 00 00
9236 12:11:51.060027 in-data: 01
9237 12:11:51.066981 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9238 12:11:51.070342 in-header: 03 fb 00 00 01 00 00 00
9239 12:11:51.070431 in-data: 01
9240 12:11:51.073748 [SSUSB] Setting up USB HOST controller...
9241 12:11:51.079886 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9242 12:11:51.080040 [SSUSB] phy power-on done.
9243 12:11:51.086759 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9244 12:11:51.090133 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9245 12:11:51.096950 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9246 12:11:51.103753 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9247 12:11:51.106540 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9248 12:11:51.114368 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9249 12:11:51.121075 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9250 12:11:51.127938 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9251 12:11:51.131225 SPM: binary array size = 0x9dc
9252 12:11:51.138008 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9253 12:11:51.140720 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9254 12:11:51.147720 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9255 12:11:51.154483 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9256 12:11:51.157804 configure_display: Starting display init
9257 12:11:51.192392 anx7625_power_on_init: Init interface.
9258 12:11:51.195201 anx7625_disable_pd_protocol: Disabled PD feature.
9259 12:11:51.198492 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9260 12:11:51.226744 anx7625_start_dp_work: Secure OCM version=00
9261 12:11:51.230062 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9262 12:11:51.244952 sp_tx_get_edid_block: EDID Block = 1
9263 12:11:51.347503 Extracted contents:
9264 12:11:51.351032 header: 00 ff ff ff ff ff ff 00
9265 12:11:51.353691 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9266 12:11:51.357189 version: 01 04
9267 12:11:51.360631 basic params: 95 1f 11 78 0a
9268 12:11:51.364120 chroma info: 76 90 94 55 54 90 27 21 50 54
9269 12:11:51.366889 established: 00 00 00
9270 12:11:51.373604 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9271 12:11:51.377387 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9272 12:11:51.383550 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9273 12:11:51.390389 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9274 12:11:51.397408 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9275 12:11:51.400084 extensions: 00
9276 12:11:51.400190 checksum: fb
9277 12:11:51.400283
9278 12:11:51.403542 Manufacturer: IVO Model 57d Serial Number 0
9279 12:11:51.406932 Made week 0 of 2020
9280 12:11:51.407035 EDID version: 1.4
9281 12:11:51.410446 Digital display
9282 12:11:51.413919 6 bits per primary color channel
9283 12:11:51.413995 DisplayPort interface
9284 12:11:51.417404 Maximum image size: 31 cm x 17 cm
9285 12:11:51.420867 Gamma: 220%
9286 12:11:51.420967 Check DPMS levels
9287 12:11:51.423473 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9288 12:11:51.427317 First detailed timing is preferred timing
9289 12:11:51.430714 Established timings supported:
9290 12:11:51.434114 Standard timings supported:
9291 12:11:51.434220 Detailed timings
9292 12:11:51.440111 Hex of detail: 383680a07038204018303c0035ae10000019
9293 12:11:51.443552 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9294 12:11:51.450121 0780 0798 07c8 0820 hborder 0
9295 12:11:51.453534 0438 043b 0447 0458 vborder 0
9296 12:11:51.453612 -hsync -vsync
9297 12:11:51.456825 Did detailed timing
9298 12:11:51.460232 Hex of detail: 000000000000000000000000000000000000
9299 12:11:51.463647 Manufacturer-specified data, tag 0
9300 12:11:51.470459 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9301 12:11:51.470541 ASCII string: InfoVision
9302 12:11:51.476599 Hex of detail: 000000fe00523134304e574635205248200a
9303 12:11:51.480667 ASCII string: R140NWF5 RH
9304 12:11:51.480770 Checksum
9305 12:11:51.480862 Checksum: 0xfb (valid)
9306 12:11:51.487090 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9307 12:11:51.489894 DSI data_rate: 832800000 bps
9308 12:11:51.493273 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9309 12:11:51.496600 anx7625_parse_edid: pixelclock(138800).
9310 12:11:51.503470 hactive(1920), hsync(48), hfp(24), hbp(88)
9311 12:11:51.506872 vactive(1080), vsync(12), vfp(3), vbp(17)
9312 12:11:51.510312 anx7625_dsi_config: config dsi.
9313 12:11:51.516573 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9314 12:11:51.529457 anx7625_dsi_config: success to config DSI
9315 12:11:51.532752 anx7625_dp_start: MIPI phy setup OK.
9316 12:11:51.536012 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9317 12:11:51.539510 mtk_ddp_mode_set invalid vrefresh 60
9318 12:11:51.542885 main_disp_path_setup
9319 12:11:51.542983 ovl_layer_smi_id_en
9320 12:11:51.546156 ovl_layer_smi_id_en
9321 12:11:51.546258 ccorr_config
9322 12:11:51.546348 aal_config
9323 12:11:51.549527 gamma_config
9324 12:11:51.549630 postmask_config
9325 12:11:51.552800 dither_config
9326 12:11:51.556263 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9327 12:11:51.562870 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9328 12:11:51.565595 Root Device init finished in 529 msecs
9329 12:11:51.565694 CPU_CLUSTER: 0 init
9330 12:11:51.575849 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9331 12:11:51.579359 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9332 12:11:51.582103 APU_MBOX 0x190000b0 = 0x10001
9333 12:11:51.585662 APU_MBOX 0x190001b0 = 0x10001
9334 12:11:51.588792 APU_MBOX 0x190005b0 = 0x10001
9335 12:11:51.592261 APU_MBOX 0x190006b0 = 0x10001
9336 12:11:51.595552 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9337 12:11:51.608626 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9338 12:11:51.620458 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9339 12:11:51.627320 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9340 12:11:51.638907 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9341 12:11:51.648159 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9342 12:11:51.651628 CPU_CLUSTER: 0 init finished in 81 msecs
9343 12:11:51.654829 Devices initialized
9344 12:11:51.658083 Show all devs... After init.
9345 12:11:51.658167 Root Device: enabled 1
9346 12:11:51.661557 CPU_CLUSTER: 0: enabled 1
9347 12:11:51.664608 CPU: 00: enabled 1
9348 12:11:51.667954 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9349 12:11:51.671308 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9350 12:11:51.674709 ELOG: NV offset 0x57f000 size 0x1000
9351 12:11:51.681085 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9352 12:11:51.687897 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9353 12:11:51.691183 ELOG: Event(17) added with size 13 at 2023-06-06 12:11:45 UTC
9354 12:11:51.694654 out: cmd=0x121: 03 db 21 01 00 00 00 00
9355 12:11:51.698045 in-header: 03 06 00 00 2c 00 00 00
9356 12:11:51.712024 in-data: 59 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 12:11:51.718169 ELOG: Event(A1) added with size 10 at 2023-06-06 12:11:45 UTC
9358 12:11:51.724974 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9359 12:11:51.731297 ELOG: Event(A0) added with size 9 at 2023-06-06 12:11:45 UTC
9360 12:11:51.734637 elog_add_boot_reason: Logged dev mode boot
9361 12:11:51.738220 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9362 12:11:51.741544 Finalize devices...
9363 12:11:51.741659 Devices finalized
9364 12:11:51.747794 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9365 12:11:51.751087 Writing coreboot table at 0xffe64000
9366 12:11:51.754408 0. 000000000010a000-0000000000113fff: RAMSTAGE
9367 12:11:51.757825 1. 0000000040000000-00000000400fffff: RAM
9368 12:11:51.764543 2. 0000000040100000-000000004032afff: RAMSTAGE
9369 12:11:51.767749 3. 000000004032b000-00000000545fffff: RAM
9370 12:11:51.771135 4. 0000000054600000-000000005465ffff: BL31
9371 12:11:51.774462 5. 0000000054660000-00000000ffe63fff: RAM
9372 12:11:51.781186 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9373 12:11:51.784524 7. 0000000100000000-000000023fffffff: RAM
9374 12:11:51.784610 Passing 5 GPIOs to payload:
9375 12:11:51.791474 NAME | PORT | POLARITY | VALUE
9376 12:11:51.794139 EC in RW | 0x000000aa | low | undefined
9377 12:11:51.800891 EC interrupt | 0x00000005 | low | undefined
9378 12:11:51.804464 TPM interrupt | 0x000000ab | high | undefined
9379 12:11:51.810781 SD card detect | 0x00000011 | high | undefined
9380 12:11:51.814251 speaker enable | 0x00000093 | high | undefined
9381 12:11:51.817618 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9382 12:11:51.821163 in-header: 03 f9 00 00 02 00 00 00
9383 12:11:51.821275 in-data: 02 00
9384 12:11:51.823903 ADC[4]: Raw value=905096 ID=7
9385 12:11:51.827625 ADC[3]: Raw value=213441 ID=1
9386 12:11:51.830972 RAM Code: 0x71
9387 12:11:51.831085 ADC[6]: Raw value=75701 ID=0
9388 12:11:51.833914 ADC[5]: Raw value=213072 ID=1
9389 12:11:51.837302 SKU Code: 0x1
9390 12:11:51.840722 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9391 12:11:51.844140 coreboot table: 964 bytes.
9392 12:11:51.847533 IMD ROOT 0. 0xfffff000 0x00001000
9393 12:11:51.850981 IMD SMALL 1. 0xffffe000 0x00001000
9394 12:11:51.853650 RO MCACHE 2. 0xffffc000 0x00001104
9395 12:11:51.857560 CONSOLE 3. 0xfff7c000 0x00080000
9396 12:11:51.860290 FMAP 4. 0xfff7b000 0x00000452
9397 12:11:51.863576 TIME STAMP 5. 0xfff7a000 0x00000910
9398 12:11:51.867026 VBOOT WORK 6. 0xfff66000 0x00014000
9399 12:11:51.870198 RAMOOPS 7. 0xffe66000 0x00100000
9400 12:11:51.874192 COREBOOT 8. 0xffe64000 0x00002000
9401 12:11:51.874278 IMD small region:
9402 12:11:51.877365 IMD ROOT 0. 0xffffec00 0x00000400
9403 12:11:51.880729 VPD 1. 0xffffeba0 0x0000004c
9404 12:11:51.883988 MMC STATUS 2. 0xffffeb80 0x00000004
9405 12:11:51.890208 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9406 12:11:51.893718 Probing TPM: done!
9407 12:11:51.897288 Connected to device vid:did:rid of 1ae0:0028:00
9408 12:11:51.907232 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9409 12:11:51.910066 Initialized TPM device CR50 revision 0
9410 12:11:51.914232 Checking cr50 for pending updates
9411 12:11:51.917492 Reading cr50 TPM mode
9412 12:11:51.926797 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9413 12:11:51.932860 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9414 12:11:51.973129 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9415 12:11:51.976388 Checking segment from ROM address 0x40100000
9416 12:11:51.979850 Checking segment from ROM address 0x4010001c
9417 12:11:51.986562 Loading segment from ROM address 0x40100000
9418 12:11:51.986677 code (compression=0)
9419 12:11:51.992861 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9420 12:11:52.003291 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9421 12:11:52.003399 it's not compressed!
9422 12:11:52.010081 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9423 12:11:52.012900 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9424 12:11:52.033291 Loading segment from ROM address 0x4010001c
9425 12:11:52.033449 Entry Point 0x80000000
9426 12:11:52.036751 Loaded segments
9427 12:11:52.040114 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9428 12:11:52.047002 Jumping to boot code at 0x80000000(0xffe64000)
9429 12:11:52.053257 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9430 12:11:52.060278 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9431 12:11:52.067734 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9432 12:11:52.071722 Checking segment from ROM address 0x40100000
9433 12:11:52.074533 Checking segment from ROM address 0x4010001c
9434 12:11:52.081256 Loading segment from ROM address 0x40100000
9435 12:11:52.081384 code (compression=1)
9436 12:11:52.087892 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9437 12:11:52.097584 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9438 12:11:52.097711 using LZMA
9439 12:11:52.106553 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9440 12:11:52.113308 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9441 12:11:52.116031 Loading segment from ROM address 0x4010001c
9442 12:11:52.116146 Entry Point 0x54601000
9443 12:11:52.119449 Loaded segments
9444 12:11:52.123104 NOTICE: MT8192 bl31_setup
9445 12:11:52.130052 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9446 12:11:52.133384 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9447 12:11:52.136775 WARNING: region 0:
9448 12:11:52.140082 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 12:11:52.140201 WARNING: region 1:
9450 12:11:52.146697 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9451 12:11:52.150099 WARNING: region 2:
9452 12:11:52.153527 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9453 12:11:52.156331 WARNING: region 3:
9454 12:11:52.160480 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 12:11:52.163235 WARNING: region 4:
9456 12:11:52.166685 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 12:11:52.170143 WARNING: region 5:
9458 12:11:52.173507 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 12:11:52.176881 WARNING: region 6:
9460 12:11:52.180128 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 12:11:52.180209 WARNING: region 7:
9462 12:11:52.186695 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 12:11:52.193816 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9464 12:11:52.197104 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9465 12:11:52.200449 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9466 12:11:52.207022 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9467 12:11:52.210392 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9468 12:11:52.213898 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9469 12:11:52.220526 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9470 12:11:52.223811 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9471 12:11:52.227152 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9472 12:11:52.233420 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9473 12:11:52.236977 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9474 12:11:52.240506 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9475 12:11:52.247253 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9476 12:11:52.250707 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9477 12:11:52.256824 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9478 12:11:52.260314 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9479 12:11:52.263949 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9480 12:11:52.270632 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9481 12:11:52.273501 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9482 12:11:52.276937 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9483 12:11:52.283654 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9484 12:11:52.286941 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9485 12:11:52.293938 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9486 12:11:52.297292 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9487 12:11:52.300681 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9488 12:11:52.307278 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9489 12:11:52.310461 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9490 12:11:52.317123 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9491 12:11:52.320465 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9492 12:11:52.323929 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9493 12:11:52.330161 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9494 12:11:52.333726 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9495 12:11:52.337087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9496 12:11:52.343995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9497 12:11:52.347485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9498 12:11:52.350725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9499 12:11:52.353979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9500 12:11:52.360860 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9501 12:11:52.364316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9502 12:11:52.367228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9503 12:11:52.370590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9504 12:11:52.374015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9505 12:11:52.380958 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9506 12:11:52.383767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9507 12:11:52.387170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9508 12:11:52.393878 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9509 12:11:52.397315 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9510 12:11:52.400716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9511 12:11:52.407560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9512 12:11:52.410882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9513 12:11:52.414293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9514 12:11:52.420634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9515 12:11:52.423843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9516 12:11:52.431004 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9517 12:11:52.433769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9518 12:11:52.437291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9519 12:11:52.444322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9520 12:11:52.447231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9521 12:11:52.454010 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9522 12:11:52.456879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9523 12:11:52.463462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9524 12:11:52.466902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9525 12:11:52.473944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9526 12:11:52.477566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9527 12:11:52.480314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9528 12:11:52.487120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9529 12:11:52.490522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9530 12:11:52.497262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9531 12:11:52.500633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9532 12:11:52.507505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9533 12:11:52.510737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9534 12:11:52.514100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9535 12:11:52.520828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9536 12:11:52.523564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9537 12:11:52.530167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9538 12:11:52.533525 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9539 12:11:52.540201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9540 12:11:52.543670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9541 12:11:52.550609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9542 12:11:52.553967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9543 12:11:52.556818 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9544 12:11:52.563663 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9545 12:11:52.567079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9546 12:11:52.573858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9547 12:11:52.577352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9548 12:11:52.580203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9549 12:11:52.587198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9550 12:11:52.590568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9551 12:11:52.596901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9552 12:11:52.600516 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9553 12:11:52.607058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9554 12:11:52.610510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9555 12:11:52.617148 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9556 12:11:52.620542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9557 12:11:52.623852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9558 12:11:52.630464 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9559 12:11:52.633768 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9560 12:11:52.637141 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9561 12:11:52.643855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9562 12:11:52.647252 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9563 12:11:52.650610 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9564 12:11:52.653446 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9565 12:11:52.660412 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9566 12:11:52.663890 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9567 12:11:52.670100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9568 12:11:52.673415 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9569 12:11:52.676715 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9570 12:11:52.683523 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9571 12:11:52.687086 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9572 12:11:52.693296 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9573 12:11:52.696797 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9574 12:11:52.703675 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9575 12:11:52.707148 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9576 12:11:52.710526 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9577 12:11:52.717031 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9578 12:11:52.720302 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9579 12:11:52.723730 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9580 12:11:52.730254 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9581 12:11:52.733527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9582 12:11:52.736780 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9583 12:11:52.740232 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9584 12:11:52.747140 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9585 12:11:52.750512 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9586 12:11:52.753839 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9587 12:11:52.760720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9588 12:11:52.763988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9589 12:11:52.767432 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9590 12:11:52.773955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9591 12:11:52.777330 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9592 12:11:52.780606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9593 12:11:52.787530 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9594 12:11:52.790127 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9595 12:11:52.797114 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9596 12:11:52.800536 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9597 12:11:52.804152 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9598 12:11:52.810413 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9599 12:11:52.813838 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9600 12:11:52.817157 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9601 12:11:52.823699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9602 12:11:52.827096 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9603 12:11:52.834234 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9604 12:11:52.837562 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9605 12:11:52.840917 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9606 12:11:52.847231 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9607 12:11:52.850667 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9608 12:11:52.857383 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9609 12:11:52.860861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9610 12:11:52.864168 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9611 12:11:52.871027 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9612 12:11:52.873859 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9613 12:11:52.877473 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9614 12:11:52.884194 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9615 12:11:52.887487 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9616 12:11:52.894250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9617 12:11:52.897621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9618 12:11:52.901121 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9619 12:11:52.907376 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9620 12:11:52.910867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9621 12:11:52.914357 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9622 12:11:52.920551 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9623 12:11:52.923873 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9624 12:11:52.930622 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9625 12:11:52.933963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9626 12:11:52.937305 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9627 12:11:52.943777 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9628 12:11:52.947080 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9629 12:11:52.953842 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9630 12:11:52.957125 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9631 12:11:52.960669 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9632 12:11:52.967313 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9633 12:11:52.970741 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9634 12:11:52.977185 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9635 12:11:52.980702 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9636 12:11:52.984209 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9637 12:11:52.990393 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9638 12:11:52.993861 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9639 12:11:53.000326 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9640 12:11:53.003647 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9641 12:11:53.007064 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9642 12:11:53.014143 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9643 12:11:53.017652 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9644 12:11:53.020308 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9645 12:11:53.027129 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9646 12:11:53.030487 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9647 12:11:53.037324 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9648 12:11:53.040549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9649 12:11:53.044007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9650 12:11:53.050452 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9651 12:11:53.053491 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9652 12:11:53.060663 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9653 12:11:53.063932 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9654 12:11:53.066749 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9655 12:11:53.073877 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9656 12:11:53.076529 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9657 12:11:53.083535 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9658 12:11:53.086453 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9659 12:11:53.093303 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9660 12:11:53.096702 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9661 12:11:53.100127 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9662 12:11:53.106712 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9663 12:11:53.110067 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9664 12:11:53.117014 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9665 12:11:53.120466 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9666 12:11:53.123206 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9667 12:11:53.130232 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9668 12:11:53.133682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9669 12:11:53.139756 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9670 12:11:53.143135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9671 12:11:53.149846 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9672 12:11:53.153244 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9673 12:11:53.156484 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9674 12:11:53.162977 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9675 12:11:53.166861 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9676 12:11:53.173348 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9677 12:11:53.176572 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9678 12:11:53.179939 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9679 12:11:53.186604 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9680 12:11:53.190069 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9681 12:11:53.196489 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9682 12:11:53.199842 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9683 12:11:53.206612 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9684 12:11:53.210164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9685 12:11:53.212891 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9686 12:11:53.219659 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9687 12:11:53.223011 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9688 12:11:53.229969 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9689 12:11:53.233492 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9690 12:11:53.236299 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9691 12:11:53.243194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9692 12:11:53.246632 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9693 12:11:53.249413 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9694 12:11:53.252744 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9695 12:11:53.259385 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9696 12:11:53.262694 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9697 12:11:53.266002 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9698 12:11:53.273102 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9699 12:11:53.276112 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9700 12:11:53.282523 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9701 12:11:53.285856 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9702 12:11:53.289260 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9703 12:11:53.295786 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9704 12:11:53.299301 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9705 12:11:53.302625 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9706 12:11:53.309566 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9707 12:11:53.313058 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9708 12:11:53.315772 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9709 12:11:53.322523 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9710 12:11:53.325930 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9711 12:11:53.329490 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9712 12:11:53.335677 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9713 12:11:53.339223 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9714 12:11:53.346013 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9715 12:11:53.349484 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9716 12:11:53.352809 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9717 12:11:53.359003 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9718 12:11:53.362483 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9719 12:11:53.365837 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9720 12:11:53.372484 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9721 12:11:53.375776 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9722 12:11:53.378975 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9723 12:11:53.385668 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9724 12:11:53.388776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9725 12:11:53.395516 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9726 12:11:53.398788 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9727 12:11:53.402069 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9728 12:11:53.408737 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9729 12:11:53.412092 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9730 12:11:53.415473 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9731 12:11:53.422437 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9732 12:11:53.425846 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9733 12:11:53.429044 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9734 12:11:53.431845 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9735 12:11:53.438823 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9736 12:11:53.442380 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9737 12:11:53.445132 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9738 12:11:53.448502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9739 12:11:53.455482 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9740 12:11:53.458827 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9741 12:11:53.461695 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9742 12:11:53.465081 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9743 12:11:53.471974 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9744 12:11:53.475263 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9745 12:11:53.478480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9746 12:11:53.485240 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9747 12:11:53.488674 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9748 12:11:53.495172 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9749 12:11:53.498464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9750 12:11:53.501727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9751 12:11:53.508927 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9752 12:11:53.512116 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9753 12:11:53.518801 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9754 12:11:53.522225 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9755 12:11:53.525048 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9756 12:11:53.531916 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9757 12:11:53.535132 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9758 12:11:53.542083 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9759 12:11:53.544958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9760 12:11:53.548458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9761 12:11:53.555538 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9762 12:11:53.558215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9763 12:11:53.565035 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9764 12:11:53.568497 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9765 12:11:53.575480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9766 12:11:53.578228 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9767 12:11:53.581722 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9768 12:11:53.588297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9769 12:11:53.591744 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9770 12:11:53.598133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9771 12:11:53.601466 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9772 12:11:53.605353 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9773 12:11:53.611465 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9774 12:11:53.615328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9775 12:11:53.621475 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9776 12:11:53.624623 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9777 12:11:53.628100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9778 12:11:53.634998 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9779 12:11:53.638414 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9780 12:11:53.645136 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9781 12:11:53.648587 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9782 12:11:53.651981 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9783 12:11:53.658306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9784 12:11:53.661896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9785 12:11:53.665276 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9786 12:11:53.671557 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9787 12:11:53.675110 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9788 12:11:53.681836 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9789 12:11:53.685488 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9790 12:11:53.691674 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9791 12:11:53.695001 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9792 12:11:53.698320 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9793 12:11:53.705080 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9794 12:11:53.708407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9795 12:11:53.714758 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9796 12:11:53.718022 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9797 12:11:53.721456 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9798 12:11:53.728695 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9799 12:11:53.731916 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9800 12:11:53.738172 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9801 12:11:53.741602 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9802 12:11:53.745098 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9803 12:11:53.751744 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9804 12:11:53.755258 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9805 12:11:53.761876 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9806 12:11:53.765284 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9807 12:11:53.768069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9808 12:11:53.775115 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9809 12:11:53.777964 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9810 12:11:53.784800 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9811 12:11:53.788228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9812 12:11:53.791725 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9813 12:11:53.798057 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9814 12:11:53.801343 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9815 12:11:53.808627 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9816 12:11:53.811279 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9817 12:11:53.814658 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9818 12:11:53.821340 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9819 12:11:53.824644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9820 12:11:53.831791 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9821 12:11:53.834940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9822 12:11:53.841468 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9823 12:11:53.844831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9824 12:11:53.848257 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9825 12:11:53.854818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9826 12:11:53.858112 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9827 12:11:53.864897 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9828 12:11:53.868426 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9829 12:11:53.874818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9830 12:11:53.878367 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9831 12:11:53.884633 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9832 12:11:53.888058 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9833 12:11:53.891501 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9834 12:11:53.897708 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9835 12:11:53.901101 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9836 12:11:53.908057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9837 12:11:53.911370 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9838 12:11:53.917859 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9839 12:11:53.921172 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9840 12:11:53.924542 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9841 12:11:53.931042 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9842 12:11:53.934300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9843 12:11:53.941025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9844 12:11:53.944297 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9845 12:11:53.951237 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9846 12:11:53.954631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9847 12:11:53.961346 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9848 12:11:53.964628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9849 12:11:53.968084 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9850 12:11:53.974437 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9851 12:11:53.977810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9852 12:11:53.984595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9853 12:11:53.987993 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9854 12:11:53.994306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9855 12:11:53.997771 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9856 12:11:54.001149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9857 12:11:54.007361 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9858 12:11:54.010924 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9859 12:11:54.017223 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9860 12:11:54.020600 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9861 12:11:54.027194 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9862 12:11:54.030671 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9863 12:11:54.033813 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9864 12:11:54.040529 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9865 12:11:54.043895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9866 12:11:54.051113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9867 12:11:54.054268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9868 12:11:54.060737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9869 12:11:54.064081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9870 12:11:54.067308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9871 12:11:54.074030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9872 12:11:54.077560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9873 12:11:54.083850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9874 12:11:54.087300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9875 12:11:54.093572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9876 12:11:54.096904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9877 12:11:54.103701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9878 12:11:54.107272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9879 12:11:54.113496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9880 12:11:54.116887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9881 12:11:54.123902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9882 12:11:54.126760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9883 12:11:54.133677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9884 12:11:54.136950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9885 12:11:54.143434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9886 12:11:54.146801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9887 12:11:54.153303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9888 12:11:54.157310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9889 12:11:54.163765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9890 12:11:54.166802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9891 12:11:54.173425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9892 12:11:54.176805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9893 12:11:54.183725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9894 12:11:54.186549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9895 12:11:54.193521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9896 12:11:54.196868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9897 12:11:54.200301 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9898 12:11:54.203128 INFO: [APUAPC] vio 0
9899 12:11:54.209979 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9900 12:11:54.213472 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9901 12:11:54.216841 INFO: [APUAPC] D0_APC_0: 0x400510
9902 12:11:54.220100 INFO: [APUAPC] D0_APC_1: 0x0
9903 12:11:54.223553 INFO: [APUAPC] D0_APC_2: 0x1540
9904 12:11:54.226971 INFO: [APUAPC] D0_APC_3: 0x0
9905 12:11:54.229711 INFO: [APUAPC] D1_APC_0: 0xffffffff
9906 12:11:54.233123 INFO: [APUAPC] D1_APC_1: 0xffffffff
9907 12:11:54.236537 INFO: [APUAPC] D1_APC_2: 0x3fffff
9908 12:11:54.239865 INFO: [APUAPC] D1_APC_3: 0x0
9909 12:11:54.243154 INFO: [APUAPC] D2_APC_0: 0xffffffff
9910 12:11:54.246849 INFO: [APUAPC] D2_APC_1: 0xffffffff
9911 12:11:54.250176 INFO: [APUAPC] D2_APC_2: 0x3fffff
9912 12:11:54.250285 INFO: [APUAPC] D2_APC_3: 0x0
9913 12:11:54.253637 INFO: [APUAPC] D3_APC_0: 0xffffffff
9914 12:11:54.257123 INFO: [APUAPC] D3_APC_1: 0xffffffff
9915 12:11:54.260358 INFO: [APUAPC] D3_APC_2: 0x3fffff
9916 12:11:54.263606 INFO: [APUAPC] D3_APC_3: 0x0
9917 12:11:54.266869 INFO: [APUAPC] D4_APC_0: 0xffffffff
9918 12:11:54.270147 INFO: [APUAPC] D4_APC_1: 0xffffffff
9919 12:11:54.273473 INFO: [APUAPC] D4_APC_2: 0x3fffff
9920 12:11:54.276753 INFO: [APUAPC] D4_APC_3: 0x0
9921 12:11:54.279927 INFO: [APUAPC] D5_APC_0: 0xffffffff
9922 12:11:54.283237 INFO: [APUAPC] D5_APC_1: 0xffffffff
9923 12:11:54.286541 INFO: [APUAPC] D5_APC_2: 0x3fffff
9924 12:11:54.289768 INFO: [APUAPC] D5_APC_3: 0x0
9925 12:11:54.293133 INFO: [APUAPC] D6_APC_0: 0xffffffff
9926 12:11:54.296668 INFO: [APUAPC] D6_APC_1: 0xffffffff
9927 12:11:54.300172 INFO: [APUAPC] D6_APC_2: 0x3fffff
9928 12:11:54.303574 INFO: [APUAPC] D6_APC_3: 0x0
9929 12:11:54.306408 INFO: [APUAPC] D7_APC_0: 0xffffffff
9930 12:11:54.309814 INFO: [APUAPC] D7_APC_1: 0xffffffff
9931 12:11:54.313163 INFO: [APUAPC] D7_APC_2: 0x3fffff
9932 12:11:54.316606 INFO: [APUAPC] D7_APC_3: 0x0
9933 12:11:54.319989 INFO: [APUAPC] D8_APC_0: 0xffffffff
9934 12:11:54.322903 INFO: [APUAPC] D8_APC_1: 0xffffffff
9935 12:11:54.326586 INFO: [APUAPC] D8_APC_2: 0x3fffff
9936 12:11:54.330028 INFO: [APUAPC] D8_APC_3: 0x0
9937 12:11:54.333570 INFO: [APUAPC] D9_APC_0: 0xffffffff
9938 12:11:54.336380 INFO: [APUAPC] D9_APC_1: 0xffffffff
9939 12:11:54.339878 INFO: [APUAPC] D9_APC_2: 0x3fffff
9940 12:11:54.343270 INFO: [APUAPC] D9_APC_3: 0x0
9941 12:11:54.346736 INFO: [APUAPC] D10_APC_0: 0xffffffff
9942 12:11:54.350131 INFO: [APUAPC] D10_APC_1: 0xffffffff
9943 12:11:54.353522 INFO: [APUAPC] D10_APC_2: 0x3fffff
9944 12:11:54.356261 INFO: [APUAPC] D10_APC_3: 0x0
9945 12:11:54.359688 INFO: [APUAPC] D11_APC_0: 0xffffffff
9946 12:11:54.363037 INFO: [APUAPC] D11_APC_1: 0xffffffff
9947 12:11:54.366383 INFO: [APUAPC] D11_APC_2: 0x3fffff
9948 12:11:54.369814 INFO: [APUAPC] D11_APC_3: 0x0
9949 12:11:54.373239 INFO: [APUAPC] D12_APC_0: 0xffffffff
9950 12:11:54.376555 INFO: [APUAPC] D12_APC_1: 0xffffffff
9951 12:11:54.379861 INFO: [APUAPC] D12_APC_2: 0x3fffff
9952 12:11:54.383345 INFO: [APUAPC] D12_APC_3: 0x0
9953 12:11:54.386623 INFO: [APUAPC] D13_APC_0: 0xffffffff
9954 12:11:54.389808 INFO: [APUAPC] D13_APC_1: 0xffffffff
9955 12:11:54.393141 INFO: [APUAPC] D13_APC_2: 0x3fffff
9956 12:11:54.396487 INFO: [APUAPC] D13_APC_3: 0x0
9957 12:11:54.399845 INFO: [APUAPC] D14_APC_0: 0xffffffff
9958 12:11:54.402587 INFO: [APUAPC] D14_APC_1: 0xffffffff
9959 12:11:54.406021 INFO: [APUAPC] D14_APC_2: 0x3fffff
9960 12:11:54.409706 INFO: [APUAPC] D14_APC_3: 0x0
9961 12:11:54.413165 INFO: [APUAPC] D15_APC_0: 0xffffffff
9962 12:11:54.416049 INFO: [APUAPC] D15_APC_1: 0xffffffff
9963 12:11:54.419635 INFO: [APUAPC] D15_APC_2: 0x3fffff
9964 12:11:54.422947 INFO: [APUAPC] D15_APC_3: 0x0
9965 12:11:54.426488 INFO: [APUAPC] APC_CON: 0x4
9966 12:11:54.429106 INFO: [NOCDAPC] D0_APC_0: 0x0
9967 12:11:54.432690 INFO: [NOCDAPC] D0_APC_1: 0x0
9968 12:11:54.432798 INFO: [NOCDAPC] D1_APC_0: 0x0
9969 12:11:54.436146 INFO: [NOCDAPC] D1_APC_1: 0xfff
9970 12:11:54.439672 INFO: [NOCDAPC] D2_APC_0: 0x0
9971 12:11:54.442481 INFO: [NOCDAPC] D2_APC_1: 0xfff
9972 12:11:54.445936 INFO: [NOCDAPC] D3_APC_0: 0x0
9973 12:11:54.449544 INFO: [NOCDAPC] D3_APC_1: 0xfff
9974 12:11:54.452978 INFO: [NOCDAPC] D4_APC_0: 0x0
9975 12:11:54.455709 INFO: [NOCDAPC] D4_APC_1: 0xfff
9976 12:11:54.459070 INFO: [NOCDAPC] D5_APC_0: 0x0
9977 12:11:54.462368 INFO: [NOCDAPC] D5_APC_1: 0xfff
9978 12:11:54.465710 INFO: [NOCDAPC] D6_APC_0: 0x0
9979 12:11:54.465821 INFO: [NOCDAPC] D6_APC_1: 0xfff
9980 12:11:54.469155 INFO: [NOCDAPC] D7_APC_0: 0x0
9981 12:11:54.472394 INFO: [NOCDAPC] D7_APC_1: 0xfff
9982 12:11:54.475749 INFO: [NOCDAPC] D8_APC_0: 0x0
9983 12:11:54.479059 INFO: [NOCDAPC] D8_APC_1: 0xfff
9984 12:11:54.482385 INFO: [NOCDAPC] D9_APC_0: 0x0
9985 12:11:54.485790 INFO: [NOCDAPC] D9_APC_1: 0xfff
9986 12:11:54.489189 INFO: [NOCDAPC] D10_APC_0: 0x0
9987 12:11:54.492531 INFO: [NOCDAPC] D10_APC_1: 0xfff
9988 12:11:54.496046 INFO: [NOCDAPC] D11_APC_0: 0x0
9989 12:11:54.498783 INFO: [NOCDAPC] D11_APC_1: 0xfff
9990 12:11:54.502136 INFO: [NOCDAPC] D12_APC_0: 0x0
9991 12:11:54.505378 INFO: [NOCDAPC] D12_APC_1: 0xfff
9992 12:11:54.505488 INFO: [NOCDAPC] D13_APC_0: 0x0
9993 12:11:54.508806 INFO: [NOCDAPC] D13_APC_1: 0xfff
9994 12:11:54.512285 INFO: [NOCDAPC] D14_APC_0: 0x0
9995 12:11:54.515731 INFO: [NOCDAPC] D14_APC_1: 0xfff
9996 12:11:54.519097 INFO: [NOCDAPC] D15_APC_0: 0x0
9997 12:11:54.522546 INFO: [NOCDAPC] D15_APC_1: 0xfff
9998 12:11:54.525403 INFO: [NOCDAPC] APC_CON: 0x4
9999 12:11:54.528871 INFO: [APUAPC] set_apusys_apc done
10000 12:11:54.532344 INFO: [DEVAPC] devapc_init done
10001 12:11:54.535523 INFO: GICv3 without legacy support detected.
10002 12:11:54.538864 INFO: ARM GICv3 driver initialized in EL3
10003 12:11:54.545937 INFO: Maximum SPI INTID supported: 639
10004 12:11:54.549388 INFO: BL31: Initializing runtime services
10005 12:11:54.552184 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10006 12:11:54.555634 INFO: SPM: enable CPC mode
10007 12:11:54.562485 INFO: mcdi ready for mcusys-off-idle and system suspend
10008 12:11:54.565825 INFO: BL31: Preparing for EL3 exit to normal world
10009 12:11:54.569240 INFO: Entry point address = 0x80000000
10010 12:11:54.572544 INFO: SPSR = 0x8
10011 12:11:54.577829
10012 12:11:54.577943
10013 12:11:54.578052
10014 12:11:54.581093 Starting depthcharge on Spherion...
10015 12:11:54.581178
10016 12:11:54.581246 Wipe memory regions:
10017 12:11:54.581309
10018 12:11:54.581926 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10019 12:11:54.582036 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10020 12:11:54.582124 Setting prompt string to ['asurada:']
10021 12:11:54.582209 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10022 12:11:54.584539 [0x00000040000000, 0x00000054600000)
10023 12:11:54.706827
10024 12:11:54.707008 [0x00000054660000, 0x00000080000000)
10025 12:11:54.966998
10026 12:11:54.967190 [0x000000821a7280, 0x000000ffe64000)
10027 12:11:55.711912
10028 12:11:55.712111 [0x00000100000000, 0x00000240000000)
10029 12:11:57.600964
10030 12:11:57.604347 Initializing XHCI USB controller at 0x11200000.
10031 12:11:58.641919
10032 12:11:58.645241 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10033 12:11:58.645353
10034 12:11:58.645451
10035 12:11:58.645548
10036 12:11:58.645877 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 12:11:58.746285 asurada: tftpboot 192.168.201.1 10605438/tftp-deploy-xxtps5kp/kernel/image.itb 10605438/tftp-deploy-xxtps5kp/kernel/cmdline
10039 12:11:58.746479 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 12:11:58.746606 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10041 12:11:58.750879 tftpboot 192.168.201.1 10605438/tftp-deploy-xxtps5kp/kernel/image.ittp-deploy-xxtps5kp/kernel/cmdline
10042 12:11:58.750988
10043 12:11:58.751092 Waiting for link
10044 12:11:58.911139
10045 12:11:58.911317 R8152: Initializing
10046 12:11:58.911401
10047 12:11:58.914534 Version 9 (ocp_data = 6010)
10048 12:11:58.914619
10049 12:11:58.918149 R8152: Done initializing
10050 12:11:58.918321
10051 12:11:58.918424 Adding net device
10052 12:12:00.790167
10053 12:12:00.790317 done.
10054 12:12:00.790398
10055 12:12:00.790466 MAC: 00:e0:4c:78:7a:aa
10056 12:12:00.790529
10057 12:12:00.793794 Sending DHCP discover... done.
10058 12:12:00.793869
10059 12:12:00.797144 Waiting for reply... done.
10060 12:12:00.797237
10061 12:12:00.799791 Sending DHCP request... done.
10062 12:12:00.799907
10063 12:12:00.805750 Waiting for reply... done.
10064 12:12:00.805856
10065 12:12:00.805946 My ip is 192.168.201.12
10066 12:12:00.806017
10067 12:12:00.809064 The DHCP server ip is 192.168.201.1
10068 12:12:00.809156
10069 12:12:00.816018 TFTP server IP predefined by user: 192.168.201.1
10070 12:12:00.816118
10071 12:12:00.822739 Bootfile predefined by user: 10605438/tftp-deploy-xxtps5kp/kernel/image.itb
10072 12:12:00.822815
10073 12:12:00.822879 Sending tftp read request... done.
10074 12:12:00.826104
10075 12:12:00.826191 Waiting for the transfer...
10076 12:12:00.829407
10077 12:12:01.078479 00000000 ################################################################
10078 12:12:01.078651
10079 12:12:01.325787 00080000 ################################################################
10080 12:12:01.325967
10081 12:12:01.573976 00100000 ################################################################
10082 12:12:01.574127
10083 12:12:01.822988 00180000 ################################################################
10084 12:12:01.823141
10085 12:12:02.070972 00200000 ################################################################
10086 12:12:02.071146
10087 12:12:02.322973 00280000 ################################################################
10088 12:12:02.323146
10089 12:12:02.576071 00300000 ################################################################
10090 12:12:02.576246
10091 12:12:02.834870 00380000 ################################################################
10092 12:12:02.835021
10093 12:12:03.080899 00400000 ################################################################
10094 12:12:03.081037
10095 12:12:03.327441 00480000 ################################################################
10096 12:12:03.327616
10097 12:12:03.577820 00500000 ################################################################
10098 12:12:03.577998
10099 12:12:03.824229 00580000 ################################################################
10100 12:12:03.824404
10101 12:12:04.069996 00600000 ################################################################
10102 12:12:04.070171
10103 12:12:04.325541 00680000 ################################################################
10104 12:12:04.325697
10105 12:12:04.587067 00700000 ################################################################
10106 12:12:04.587224
10107 12:12:04.840065 00780000 ################################################################
10108 12:12:04.840220
10109 12:12:05.092787 00800000 ################################################################
10110 12:12:05.092933
10111 12:12:05.339238 00880000 ################################################################
10112 12:12:05.339413
10113 12:12:05.583080 00900000 ################################################################
10114 12:12:05.583232
10115 12:12:05.841435 00980000 ################################################################
10116 12:12:05.841575
10117 12:12:06.094712 00a00000 ################################################################
10118 12:12:06.094855
10119 12:12:06.337580 00a80000 ################################################################
10120 12:12:06.337717
10121 12:12:06.584485 00b00000 ################################################################
10122 12:12:06.584656
10123 12:12:06.827557 00b80000 ################################################################
10124 12:12:06.827693
10125 12:12:07.070413 00c00000 ################################################################
10126 12:12:07.070576
10127 12:12:07.314093 00c80000 ################################################################
10128 12:12:07.314255
10129 12:12:07.565595 00d00000 ################################################################
10130 12:12:07.565734
10131 12:12:07.814840 00d80000 ################################################################
10132 12:12:07.814988
10133 12:12:08.059131 00e00000 ################################################################
10134 12:12:08.059304
10135 12:12:08.307023 00e80000 ################################################################
10136 12:12:08.307201
10137 12:12:08.572216 00f00000 ################################################################
10138 12:12:08.572366
10139 12:12:08.830071 00f80000 ################################################################
10140 12:12:08.830207
10141 12:12:09.085241 01000000 ################################################################
10142 12:12:09.085376
10143 12:12:09.330743 01080000 ################################################################
10144 12:12:09.330886
10145 12:12:09.576196 01100000 ################################################################
10146 12:12:09.576374
10147 12:12:09.818604 01180000 ################################################################
10148 12:12:09.818740
10149 12:12:10.058877 01200000 ################################################################
10150 12:12:10.059063
10151 12:12:10.308888 01280000 ################################################################
10152 12:12:10.309063
10153 12:12:10.555276 01300000 ################################################################
10154 12:12:10.555441
10155 12:12:10.797796 01380000 ################################################################
10156 12:12:10.797962
10157 12:12:11.052458 01400000 ################################################################
10158 12:12:11.052625
10159 12:12:11.298701 01480000 ################################################################
10160 12:12:11.298872
10161 12:12:11.541150 01500000 ################################################################
10162 12:12:11.541326
10163 12:12:11.782313 01580000 ################################################################
10164 12:12:11.782492
10165 12:12:12.023165 01600000 ################################################################
10166 12:12:12.023346
10167 12:12:12.264131 01680000 ################################################################
10168 12:12:12.264295
10169 12:12:12.517891 01700000 ################################################################
10170 12:12:12.518028
10171 12:12:12.776994 01780000 ################################################################
10172 12:12:12.777136
10173 12:12:13.039064 01800000 ################################################################
10174 12:12:13.039205
10175 12:12:13.291563 01880000 ################################################################
10176 12:12:13.291697
10177 12:12:13.538985 01900000 ################################################################
10178 12:12:13.539126
10179 12:12:13.783354 01980000 ################################################################
10180 12:12:13.783496
10181 12:12:14.020592 01a00000 ################################################################
10182 12:12:14.020729
10183 12:12:14.268049 01a80000 ################################################################
10184 12:12:14.268191
10185 12:12:14.522545 01b00000 ################################################################
10186 12:12:14.522713
10187 12:12:14.756792 01b80000 ################################################################
10188 12:12:14.756978
10189 12:12:14.997509 01c00000 ################################################################
10190 12:12:14.997674
10191 12:12:15.233819 01c80000 ################################################################
10192 12:12:15.233978
10193 12:12:15.473859 01d00000 ################################################################
10194 12:12:15.474024
10195 12:12:15.681491 01d80000 ######################################################## done.
10196 12:12:15.681636
10197 12:12:15.684666 The bootfile was 31391246 bytes long.
10198 12:12:15.684791
10199 12:12:15.688210 Sending tftp read request... done.
10200 12:12:15.688308
10201 12:12:15.688421 Waiting for the transfer...
10202 12:12:15.688550
10203 12:12:15.690898 00000000 # done.
10204 12:12:15.691023
10205 12:12:15.697941 Command line loaded dynamically from TFTP file: 10605438/tftp-deploy-xxtps5kp/kernel/cmdline
10206 12:12:15.698067
10207 12:12:15.711234 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10208 12:12:15.711381
10209 12:12:15.711478 Loading FIT.
10210 12:12:15.711568
10211 12:12:15.714062 Image ramdisk-1 has 21247668 bytes.
10212 12:12:15.714147
10213 12:12:15.717436 Image fdt-1 has 46924 bytes.
10214 12:12:15.717580
10215 12:12:15.720821 Image kernel-1 has 10094623 bytes.
10216 12:12:15.720906
10217 12:12:15.727650 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10218 12:12:15.730597
10219 12:12:15.747622 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10220 12:12:15.747750
10221 12:12:15.750927 Choosing best match conf-1 for compat google,spherion-rev2.
10222 12:12:15.755986
10223 12:12:15.760680 Connected to device vid:did:rid of 1ae0:0028:00
10224 12:12:15.768971
10225 12:12:15.772586 tpm_get_response: command 0x17b, return code 0x0
10226 12:12:15.772696
10227 12:12:15.778705 ec_init: CrosEC protocol v3 supported (256, 248)
10228 12:12:15.778812
10229 12:12:15.782345 tpm_cleanup: add release locality here.
10230 12:12:15.782452
10231 12:12:15.785208 Shutting down all USB controllers.
10232 12:12:15.785282
10233 12:12:15.788536 Removing current net device
10234 12:12:15.788628
10235 12:12:15.791904 Exiting depthcharge with code 4 at timestamp: 50448527
10236 12:12:15.795172
10237 12:12:15.798700 LZMA decompressing kernel-1 to 0x821a6718
10238 12:12:15.798793
10239 12:12:15.802111 LZMA decompressing kernel-1 to 0x40000000
10240 12:12:17.069872
10241 12:12:17.070011 jumping to kernel
10242 12:12:17.070415 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10243 12:12:17.070519 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10244 12:12:17.070597 Setting prompt string to ['Linux version [0-9]']
10245 12:12:17.070667 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10246 12:12:17.070758 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10247 12:12:17.151200
10248 12:12:17.154776 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10249 12:12:17.158528 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10250 12:12:17.158649 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10251 12:12:17.158788 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10252 12:12:17.158913 Using line separator: #'\n'#
10253 12:12:17.159002 No login prompt set.
10254 12:12:17.159095 Parsing kernel messages
10255 12:12:17.159180 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10256 12:12:17.159375 [login-action] Waiting for messages, (timeout 00:04:03)
10257 12:12:17.178128 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10258 12:12:17.180789 [ 0.000000] random: crng init done
10259 12:12:17.184215 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10260 12:12:17.187531 [ 0.000000] efi: UEFI not found.
10261 12:12:17.197299 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10262 12:12:17.204577 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10263 12:12:17.214141 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10264 12:12:17.223914 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10265 12:12:17.230474 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10266 12:12:17.233960 [ 0.000000] printk: bootconsole [mtk8250] enabled
10267 12:12:17.242774 [ 0.000000] NUMA: No NUMA configuration found
10268 12:12:17.249605 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10269 12:12:17.256054 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10270 12:12:17.256155 [ 0.000000] Zone ranges:
10271 12:12:17.263052 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10272 12:12:17.266423 [ 0.000000] DMA32 empty
10273 12:12:17.272921 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10274 12:12:17.276400 [ 0.000000] Movable zone start for each node
10275 12:12:17.279303 [ 0.000000] Early memory node ranges
10276 12:12:17.285751 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10277 12:12:17.292796 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10278 12:12:17.299444 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10279 12:12:17.306211 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10280 12:12:17.312428 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10281 12:12:17.319026 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10282 12:12:17.375311 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10283 12:12:17.381817 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10284 12:12:17.388633 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10285 12:12:17.391973 [ 0.000000] psci: probing for conduit method from DT.
10286 12:12:17.398879 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10287 12:12:17.402323 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10288 12:12:17.408387 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10289 12:12:17.411597 [ 0.000000] psci: SMC Calling Convention v1.2
10290 12:12:17.418264 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10291 12:12:17.421809 [ 0.000000] Detected VIPT I-cache on CPU0
10292 12:12:17.428733 [ 0.000000] CPU features: detected: GIC system register CPU interface
10293 12:12:17.435074 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10294 12:12:17.441913 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10295 12:12:17.448173 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10296 12:12:17.454971 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10297 12:12:17.464868 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10298 12:12:17.468405 [ 0.000000] alternatives: applying boot alternatives
10299 12:12:17.471691 [ 0.000000] Fallback order for Node 0: 0
10300 12:12:17.481931 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10301 12:12:17.482014 [ 0.000000] Policy zone: Normal
10302 12:12:17.495058 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10303 12:12:17.504665 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10304 12:12:17.517197 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10305 12:12:17.527507 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10306 12:12:17.534231 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10307 12:12:17.537521 <6>[ 0.000000] software IO TLB: area num 8.
10308 12:12:17.593501 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10309 12:12:17.742527 <6>[ 0.000000] Memory: 7952188K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400580K reserved, 32768K cma-reserved)
10310 12:12:17.749356 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10311 12:12:17.755786 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10312 12:12:17.759138 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10313 12:12:17.765917 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10314 12:12:17.772331 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10315 12:12:17.775746 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10316 12:12:17.785928 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10317 12:12:17.792349 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10318 12:12:17.798875 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10319 12:12:17.805256 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10320 12:12:17.808743 <6>[ 0.000000] GICv3: 608 SPIs implemented
10321 12:12:17.812231 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10322 12:12:17.818467 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10323 12:12:17.822188 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10324 12:12:17.828505 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10325 12:12:17.841721 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10326 12:12:17.851770 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10327 12:12:17.861949 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10328 12:12:17.868914 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10329 12:12:17.882479 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10330 12:12:17.888612 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10331 12:12:17.895610 <6>[ 0.009175] Console: colour dummy device 80x25
10332 12:12:17.905548 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10333 12:12:17.911945 <6>[ 0.024409] pid_max: default: 32768 minimum: 301
10334 12:12:17.915411 <6>[ 0.029312] LSM: Security Framework initializing
10335 12:12:17.922433 <6>[ 0.034212] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10336 12:12:17.932441 <6>[ 0.042025] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10337 12:12:17.938756 <6>[ 0.051375] cblist_init_generic: Setting adjustable number of callback queues.
10338 12:12:17.945629 <6>[ 0.058827] cblist_init_generic: Setting shift to 3 and lim to 1.
10339 12:12:17.951939 <6>[ 0.065165] cblist_init_generic: Setting shift to 3 and lim to 1.
10340 12:12:17.958616 <6>[ 0.071611] rcu: Hierarchical SRCU implementation.
10341 12:12:17.961915 <6>[ 0.076655] rcu: Max phase no-delay instances is 1000.
10342 12:12:17.970103 <6>[ 0.083680] EFI services will not be available.
10343 12:12:17.973642 <6>[ 0.088648] smp: Bringing up secondary CPUs ...
10344 12:12:17.982338 <6>[ 0.093700] Detected VIPT I-cache on CPU1
10345 12:12:17.989015 <6>[ 0.093772] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10346 12:12:17.995953 <6>[ 0.093803] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10347 12:12:17.998627 <6>[ 0.094128] Detected VIPT I-cache on CPU2
10348 12:12:18.005811 <6>[ 0.094177] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10349 12:12:18.012000 <6>[ 0.094192] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10350 12:12:18.019069 <6>[ 0.094447] Detected VIPT I-cache on CPU3
10351 12:12:18.025885 <6>[ 0.094494] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10352 12:12:18.032334 <6>[ 0.094508] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10353 12:12:18.035203 <6>[ 0.094811] CPU features: detected: Spectre-v4
10354 12:12:18.042204 <6>[ 0.094818] CPU features: detected: Spectre-BHB
10355 12:12:18.044981 <6>[ 0.094824] Detected PIPT I-cache on CPU4
10356 12:12:18.052158 <6>[ 0.094881] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10357 12:12:18.058481 <6>[ 0.094898] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10358 12:12:18.065193 <6>[ 0.095189] Detected PIPT I-cache on CPU5
10359 12:12:18.071685 <6>[ 0.095251] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10360 12:12:18.078378 <6>[ 0.095268] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10361 12:12:18.081792 <6>[ 0.095546] Detected PIPT I-cache on CPU6
10362 12:12:18.088674 <6>[ 0.095612] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10363 12:12:18.095114 <6>[ 0.095628] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10364 12:12:18.101347 <6>[ 0.095925] Detected PIPT I-cache on CPU7
10365 12:12:18.108118 <6>[ 0.095989] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10366 12:12:18.115046 <6>[ 0.096005] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10367 12:12:18.117956 <6>[ 0.096052] smp: Brought up 1 node, 8 CPUs
10368 12:12:18.124770 <6>[ 0.237342] SMP: Total of 8 processors activated.
10369 12:12:18.128151 <6>[ 0.242262] CPU features: detected: 32-bit EL0 Support
10370 12:12:18.138109 <6>[ 0.247626] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10371 12:12:18.145016 <6>[ 0.256426] CPU features: detected: Common not Private translations
10372 12:12:18.148461 <6>[ 0.262902] CPU features: detected: CRC32 instructions
10373 12:12:18.154761 <6>[ 0.268286] CPU features: detected: RCpc load-acquire (LDAPR)
10374 12:12:18.161205 <6>[ 0.274246] CPU features: detected: LSE atomic instructions
10375 12:12:18.167566 <6>[ 0.280027] CPU features: detected: Privileged Access Never
10376 12:12:18.171156 <6>[ 0.285808] CPU features: detected: RAS Extension Support
10377 12:12:18.180964 <6>[ 0.291451] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10378 12:12:18.184311 <6>[ 0.298715] CPU: All CPU(s) started at EL2
10379 12:12:18.191028 <6>[ 0.303031] alternatives: applying system-wide alternatives
10380 12:12:18.199906 <6>[ 0.313742] devtmpfs: initialized
10381 12:12:18.211990 <6>[ 0.322551] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10382 12:12:18.222226 <6>[ 0.332516] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10383 12:12:18.228675 <6>[ 0.340727] pinctrl core: initialized pinctrl subsystem
10384 12:12:18.231952 <6>[ 0.347399] DMI not present or invalid.
10385 12:12:18.238430 <6>[ 0.351815] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10386 12:12:18.248246 <6>[ 0.358687] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10387 12:12:18.255236 <6>[ 0.366271] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10388 12:12:18.265153 <6>[ 0.374495] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10389 12:12:18.268039 <6>[ 0.382742] audit: initializing netlink subsys (disabled)
10390 12:12:18.277949 <5>[ 0.388442] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10391 12:12:18.284859 <6>[ 0.389169] thermal_sys: Registered thermal governor 'step_wise'
10392 12:12:18.291574 <6>[ 0.396408] thermal_sys: Registered thermal governor 'power_allocator'
10393 12:12:18.294903 <6>[ 0.402660] cpuidle: using governor menu
10394 12:12:18.301397 <6>[ 0.413617] NET: Registered PF_QIPCRTR protocol family
10395 12:12:18.308270 <6>[ 0.419105] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10396 12:12:18.314369 <6>[ 0.426206] ASID allocator initialised with 32768 entries
10397 12:12:18.317662 <6>[ 0.432781] Serial: AMBA PL011 UART driver
10398 12:12:18.327720 <4>[ 0.441473] Trying to register duplicate clock ID: 134
10399 12:12:18.381793 <6>[ 0.498754] KASLR enabled
10400 12:12:18.395940 <6>[ 0.506428] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10401 12:12:18.402589 <6>[ 0.513437] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10402 12:12:18.409279 <6>[ 0.519926] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10403 12:12:18.415855 <6>[ 0.526932] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10404 12:12:18.422507 <6>[ 0.533419] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10405 12:12:18.429249 <6>[ 0.540424] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10406 12:12:18.435469 <6>[ 0.546912] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10407 12:12:18.442401 <6>[ 0.553917] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10408 12:12:18.445866 <6>[ 0.561393] ACPI: Interpreter disabled.
10409 12:12:18.454287 <6>[ 0.567831] iommu: Default domain type: Translated
10410 12:12:18.460696 <6>[ 0.572944] iommu: DMA domain TLB invalidation policy: strict mode
10411 12:12:18.464115 <5>[ 0.579608] SCSI subsystem initialized
10412 12:12:18.470346 <6>[ 0.583846] usbcore: registered new interface driver usbfs
10413 12:12:18.477534 <6>[ 0.589575] usbcore: registered new interface driver hub
10414 12:12:18.480408 <6>[ 0.595127] usbcore: registered new device driver usb
10415 12:12:18.489719 <6>[ 0.601229] pps_core: LinuxPPS API ver. 1 registered
10416 12:12:18.497347 <6>[ 0.606421] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10417 12:12:18.501226 <6>[ 0.615767] PTP clock support registered
10418 12:12:18.504318 <6>[ 0.620007] EDAC MC: Ver: 3.0.0
10419 12:12:18.511688 <6>[ 0.625208] FPGA manager framework
10420 12:12:18.515071 <6>[ 0.628885] Advanced Linux Sound Architecture Driver Initialized.
10421 12:12:18.518337 <6>[ 0.635657] vgaarb: loaded
10422 12:12:18.524873 <6>[ 0.638813] clocksource: Switched to clocksource arch_sys_counter
10423 12:12:18.531612 <5>[ 0.645260] VFS: Disk quotas dquot_6.6.0
10424 12:12:18.538381 <6>[ 0.649448] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10425 12:12:18.541788 <6>[ 0.656641] pnp: PnP ACPI: disabled
10426 12:12:18.549245 <6>[ 0.663293] NET: Registered PF_INET protocol family
10427 12:12:18.559336 <6>[ 0.668876] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10428 12:12:18.570703 <6>[ 0.681171] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10429 12:12:18.580607 <6>[ 0.689988] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10430 12:12:18.587610 <6>[ 0.697961] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10431 12:12:18.594137 <6>[ 0.706658] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10432 12:12:18.602476 <6>[ 0.716401] TCP: Hash tables configured (established 65536 bind 65536)
10433 12:12:18.612541 <6>[ 0.723258] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10434 12:12:18.619478 <6>[ 0.730458] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10435 12:12:18.626085 <6>[ 0.738132] NET: Registered PF_UNIX/PF_LOCAL protocol family
10436 12:12:18.632241 <6>[ 0.744297] RPC: Registered named UNIX socket transport module.
10437 12:12:18.636050 <6>[ 0.750451] RPC: Registered udp transport module.
10438 12:12:18.642807 <6>[ 0.755384] RPC: Registered tcp transport module.
10439 12:12:18.649038 <6>[ 0.760317] RPC: Registered tcp NFSv4.1 backchannel transport module.
10440 12:12:18.652529 <6>[ 0.766986] PCI: CLS 0 bytes, default 64
10441 12:12:18.655841 <6>[ 0.771364] Unpacking initramfs...
10442 12:12:18.676837 <6>[ 0.787464] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10443 12:12:18.686837 <6>[ 0.796111] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10444 12:12:18.690369 <6>[ 0.804903] kvm [1]: IPA Size Limit: 40 bits
10445 12:12:18.696901 <6>[ 0.809430] kvm [1]: GICv3: no GICV resource entry
10446 12:12:18.700476 <6>[ 0.814449] kvm [1]: disabling GICv2 emulation
10447 12:12:18.706618 <6>[ 0.819132] kvm [1]: GIC system register CPU interface enabled
10448 12:12:18.709993 <6>[ 0.825279] kvm [1]: vgic interrupt IRQ18
10449 12:12:18.716991 <6>[ 0.829629] kvm [1]: VHE mode initialized successfully
10450 12:12:18.723449 <5>[ 0.836100] Initialise system trusted keyrings
10451 12:12:18.730248 <6>[ 0.840909] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10452 12:12:18.736942 <6>[ 0.850954] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10453 12:12:18.744163 <5>[ 0.857333] NFS: Registering the id_resolver key type
10454 12:12:18.746853 <5>[ 0.862636] Key type id_resolver registered
10455 12:12:18.753581 <5>[ 0.867053] Key type id_legacy registered
10456 12:12:18.760624 <6>[ 0.871334] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10457 12:12:18.767177 <6>[ 0.878255] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10458 12:12:18.773227 <6>[ 0.885970] 9p: Installing v9fs 9p2000 file system support
10459 12:12:18.810072 <5>[ 0.923571] Key type asymmetric registered
10460 12:12:18.812906 <5>[ 0.927902] Asymmetric key parser 'x509' registered
10461 12:12:18.822767 <6>[ 0.933046] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10462 12:12:18.826322 <6>[ 0.940656] io scheduler mq-deadline registered
10463 12:12:18.829779 <6>[ 0.945433] io scheduler kyber registered
10464 12:12:18.848528 <6>[ 0.962237] EINJ: ACPI disabled.
10465 12:12:18.880155 <4>[ 0.987681] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10466 12:12:18.890536 <4>[ 0.998323] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10467 12:12:18.905336 <6>[ 1.018957] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10468 12:12:18.912922 <6>[ 1.026964] printk: console [ttyS0] disabled
10469 12:12:18.940977 <6>[ 1.051612] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10470 12:12:18.948005 <6>[ 1.061091] printk: console [ttyS0] enabled
10471 12:12:18.951370 <6>[ 1.061091] printk: console [ttyS0] enabled
10472 12:12:18.957432 <6>[ 1.069983] printk: bootconsole [mtk8250] disabled
10473 12:12:18.960787 <6>[ 1.069983] printk: bootconsole [mtk8250] disabled
10474 12:12:18.967658 <6>[ 1.081313] SuperH (H)SCI(F) driver initialized
10475 12:12:18.971077 <6>[ 1.086600] msm_serial: driver initialized
10476 12:12:18.985399 <6>[ 1.095524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10477 12:12:18.994888 <6>[ 1.104069] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10478 12:12:19.001308 <6>[ 1.112612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10479 12:12:19.011913 <6>[ 1.121240] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10480 12:12:19.018317 <6>[ 1.129946] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10481 12:12:19.028346 <6>[ 1.138665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10482 12:12:19.038147 <6>[ 1.147205] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10483 12:12:19.044560 <6>[ 1.156004] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10484 12:12:19.054404 <6>[ 1.164545] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10485 12:12:19.066507 <6>[ 1.180046] loop: module loaded
10486 12:12:19.072925 <6>[ 1.186072] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10487 12:12:19.095542 <4>[ 1.209381] mtk-pmic-keys: Failed to locate of_node [id: -1]
10488 12:12:19.102399 <6>[ 1.216069] megasas: 07.719.03.00-rc1
10489 12:12:19.111600 <6>[ 1.225446] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10490 12:12:19.120504 <6>[ 1.234206] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10491 12:12:19.137360 <6>[ 1.251255] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10492 12:12:19.194751 <6>[ 1.301791] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10493 12:12:19.578724 <6>[ 1.692784] Freeing initrd memory: 20744K
10494 12:12:19.594688 <6>[ 1.708569] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10495 12:12:19.605331 <6>[ 1.719423] tun: Universal TUN/TAP device driver, 1.6
10496 12:12:19.608758 <6>[ 1.725466] thunder_xcv, ver 1.0
10497 12:12:19.612210 <6>[ 1.728969] thunder_bgx, ver 1.0
10498 12:12:19.615448 <6>[ 1.732462] nicpf, ver 1.0
10499 12:12:19.625856 <6>[ 1.736459] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10500 12:12:19.629351 <6>[ 1.743935] hns3: Copyright (c) 2017 Huawei Corporation.
10501 12:12:19.632712 <6>[ 1.749521] hclge is initializing
10502 12:12:19.639241 <6>[ 1.753103] e1000: Intel(R) PRO/1000 Network Driver
10503 12:12:19.646173 <6>[ 1.758232] e1000: Copyright (c) 1999-2006 Intel Corporation.
10504 12:12:19.649551 <6>[ 1.764245] e1000e: Intel(R) PRO/1000 Network Driver
10505 12:12:19.656079 <6>[ 1.769460] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10506 12:12:19.662293 <6>[ 1.775651] igb: Intel(R) Gigabit Ethernet Network Driver
10507 12:12:19.668775 <6>[ 1.781301] igb: Copyright (c) 2007-2014 Intel Corporation.
10508 12:12:19.675862 <6>[ 1.787136] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10509 12:12:19.682185 <6>[ 1.793653] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10510 12:12:19.685680 <6>[ 1.800111] sky2: driver version 1.30
10511 12:12:19.692169 <6>[ 1.805082] VFIO - User Level meta-driver version: 0.3
10512 12:12:19.699192 <6>[ 1.813270] usbcore: registered new interface driver usb-storage
10513 12:12:19.706332 <6>[ 1.819708] usbcore: registered new device driver onboard-usb-hub
10514 12:12:19.715155 <6>[ 1.828762] mt6397-rtc mt6359-rtc: registered as rtc0
10515 12:12:19.724868 <6>[ 1.834224] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:12:13 UTC (1686053533)
10516 12:12:19.728220 <6>[ 1.843776] i2c_dev: i2c /dev entries driver
10517 12:12:19.744939 <6>[ 1.855420] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10518 12:12:19.751588 <6>[ 1.865568] sdhci: Secure Digital Host Controller Interface driver
10519 12:12:19.758402 <6>[ 1.872024] sdhci: Copyright(c) Pierre Ossman
10520 12:12:19.764947 <6>[ 1.877419] Synopsys Designware Multimedia Card Interface Driver
10521 12:12:19.768727 <6>[ 1.884045] mmc0: CQHCI version 5.10
10522 12:12:19.775037 <6>[ 1.884570] sdhci-pltfm: SDHCI platform and OF driver helper
10523 12:12:19.782248 <6>[ 1.895904] ledtrig-cpu: registered to indicate activity on CPUs
10524 12:12:19.792847 <6>[ 1.903279] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10525 12:12:19.796240 <6>[ 1.910672] usbcore: registered new interface driver usbhid
10526 12:12:19.802894 <6>[ 1.916506] usbhid: USB HID core driver
10527 12:12:19.809359 <6>[ 1.920742] spi_master spi0: will run message pump with realtime priority
10528 12:12:19.852731 <6>[ 1.959868] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10529 12:12:19.867829 <6>[ 1.974915] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10530 12:12:19.875291 <6>[ 1.988470] mmc0: Command Queue Engine enabled
10531 12:12:19.878741 <6>[ 1.990414] cros-ec-spi spi0.0: Chrome EC device registered
10532 12:12:19.885772 <6>[ 1.993221] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10533 12:12:19.892087 <6>[ 2.006358] mmcblk0: mmc0:0001 DA4128 116 GiB
10534 12:12:19.901480 <6>[ 2.015241] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10535 12:12:19.911390 <6>[ 2.016001] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10536 12:12:19.918397 <6>[ 2.022518] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10537 12:12:19.921233 <6>[ 2.032551] NET: Registered PF_PACKET protocol family
10538 12:12:19.928055 <6>[ 2.036379] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10539 12:12:19.931649 <6>[ 2.041111] 9pnet: Installing 9P2000 support
10540 12:12:19.937976 <6>[ 2.046932] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10541 12:12:19.941507 <5>[ 2.050792] Key type dns_resolver registered
10542 12:12:19.948031 <6>[ 2.062120] registered taskstats version 1
10543 12:12:19.951198 <5>[ 2.066506] Loading compiled-in X.509 certificates
10544 12:12:19.986210 <4>[ 2.093414] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 12:12:19.995828 <4>[ 2.104086] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 12:12:20.006441 <3>[ 2.116801] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10547 12:12:20.017953 <6>[ 2.132290] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10548 12:12:20.025561 <6>[ 2.139063] xhci-mtk 11200000.usb: xHCI Host Controller
10549 12:12:20.031721 <6>[ 2.144563] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10550 12:12:20.041735 <6>[ 2.152418] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10551 12:12:20.048861 <6>[ 2.161842] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10552 12:12:20.055148 <6>[ 2.168015] xhci-mtk 11200000.usb: xHCI Host Controller
10553 12:12:20.061782 <6>[ 2.173514] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10554 12:12:20.068664 <6>[ 2.181181] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10555 12:12:20.075455 <6>[ 2.189082] hub 1-0:1.0: USB hub found
10556 12:12:20.078842 <6>[ 2.193116] hub 1-0:1.0: 1 port detected
10557 12:12:20.085446 <6>[ 2.197458] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10558 12:12:20.092690 <6>[ 2.206256] hub 2-0:1.0: USB hub found
10559 12:12:20.095521 <6>[ 2.210293] hub 2-0:1.0: 1 port detected
10560 12:12:20.103633 <6>[ 2.217453] mtk-msdc 11f70000.mmc: Got CD GPIO
10561 12:12:20.120563 <6>[ 2.231100] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10562 12:12:20.127168 <6>[ 2.239226] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10563 12:12:20.137308 <4>[ 2.247220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10564 12:12:20.147224 <6>[ 2.256911] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10565 12:12:20.153599 <6>[ 2.264999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10566 12:12:20.160637 <6>[ 2.273054] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10567 12:12:20.170441 <6>[ 2.280976] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10568 12:12:20.177129 <6>[ 2.288832] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10569 12:12:20.186647 <6>[ 2.296657] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10570 12:12:20.196868 <6>[ 2.307414] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10571 12:12:20.203542 <6>[ 2.315781] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10572 12:12:20.213711 <6>[ 2.324178] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10573 12:12:20.223478 <6>[ 2.332524] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10574 12:12:20.230602 <6>[ 2.340895] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10575 12:12:20.240427 <6>[ 2.349240] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10576 12:12:20.246802 <6>[ 2.357608] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10577 12:12:20.256659 <6>[ 2.365952] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10578 12:12:20.263598 <6>[ 2.374321] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10579 12:12:20.273257 <6>[ 2.382666] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10580 12:12:20.279947 <6>[ 2.391009] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10581 12:12:20.289956 <6>[ 2.399352] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10582 12:12:20.296229 <6>[ 2.407696] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10583 12:12:20.306588 <6>[ 2.416039] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10584 12:12:20.312801 <6>[ 2.424384] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10585 12:12:20.319663 <6>[ 2.433284] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10586 12:12:20.326910 <6>[ 2.440724] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10587 12:12:20.334010 <6>[ 2.447794] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10588 12:12:20.344522 <6>[ 2.454945] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10589 12:12:20.350980 <6>[ 2.462271] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10590 12:12:20.357992 <6>[ 2.469177] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10591 12:12:20.367792 <6>[ 2.478324] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10592 12:12:20.377744 <6>[ 2.487482] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10593 12:12:20.387622 <6>[ 2.496796] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10594 12:12:20.397477 <6>[ 2.506273] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10595 12:12:20.404792 <6>[ 2.515747] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10596 12:12:20.414345 <6>[ 2.524874] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10597 12:12:20.424666 <6>[ 2.534349] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10598 12:12:20.434001 <6>[ 2.543475] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10599 12:12:20.444520 <6>[ 2.552776] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10600 12:12:20.454381 <6>[ 2.562942] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10601 12:12:20.464095 <6>[ 2.574361] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10602 12:12:20.484254 <6>[ 2.595259] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10603 12:12:20.511810 <6>[ 2.625499] hub 2-1:1.0: USB hub found
10604 12:12:20.514568 <6>[ 2.629916] hub 2-1:1.0: 3 ports detected
10605 12:12:20.636534 <6>[ 2.747026] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10606 12:12:20.790450 <6>[ 2.904771] hub 1-1:1.0: USB hub found
10607 12:12:20.794002 <6>[ 2.909198] hub 1-1:1.0: 4 ports detected
10608 12:12:20.868556 <6>[ 2.979331] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10609 12:12:21.116078 <6>[ 3.227090] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10610 12:12:21.248819 <6>[ 3.362694] hub 1-1.4:1.0: USB hub found
10611 12:12:21.252229 <6>[ 3.367342] hub 1-1.4:1.0: 2 ports detected
10612 12:12:21.548236 <6>[ 3.659084] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10613 12:12:21.740574 <6>[ 3.851087] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10614 12:12:32.741417 <6>[ 14.859726] ALSA device list:
10615 12:12:32.748077 <6>[ 14.862976] No soundcards found.
10616 12:12:32.759945 <6>[ 14.875331] Freeing unused kernel memory: 8384K
10617 12:12:32.763276 <6>[ 14.880241] Run /init as init process
10618 12:12:32.789525 Starting syslogd: OK
10619 12:12:32.794174 Starting klogd: OK
10620 12:12:32.803893 Running sysctl: OK
10621 12:12:32.813405 Populating /dev using udev: <30>[ 14.927602] udevd[185]: starting version 3.2.9
10622 12:12:32.820144 <27>[ 14.935493] udevd[185]: specified user 'tss' unknown
10623 12:12:32.826974 <27>[ 14.940936] udevd[185]: specified group 'tss' unknown
10624 12:12:32.830270 <30>[ 14.947397] udevd[186]: starting eudev-3.2.9
10625 12:12:32.861489 <27>[ 14.976295] udevd[186]: specified user 'tss' unknown
10626 12:12:32.867705 <27>[ 14.981680] udevd[186]: specified group 'tss' unknown
10627 12:12:33.061692 <6>[ 15.173552] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10628 12:12:33.071152 <6>[ 15.181676] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10629 12:12:33.077840 <6>[ 15.190433] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10630 12:12:33.084690 <6>[ 15.196075] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10631 12:12:33.103465 <6>[ 15.218991] remoteproc remoteproc0: scp is available
10632 12:12:33.113525 <4>[ 15.224408] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10633 12:12:33.123289 <4>[ 15.234993] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10634 12:12:33.126731 <6>[ 15.242457] remoteproc remoteproc0: powering up scp
10635 12:12:33.136893 <4>[ 15.247677] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10636 12:12:33.146971 <3>[ 15.249769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 12:12:33.149735 <3>[ 15.257654] remoteproc remoteproc0: request_firmware failed: -2
10638 12:12:33.159984 <4>[ 15.263962] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10639 12:12:33.166771 <3>[ 15.265621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10640 12:12:33.169529 <6>[ 15.268164] mc: Linux media interface: v0.10
10641 12:12:33.180171 <6>[ 15.269382] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10642 12:12:33.183050 <6>[ 15.288444] usbcore: registered new interface driver r8152
10643 12:12:33.193620 <3>[ 15.291690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10644 12:12:33.200446 <3>[ 15.291787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10645 12:12:33.210671 <4>[ 15.295274] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10646 12:12:33.214089 <4>[ 15.295274] Fallback method does not support PEC.
10647 12:12:33.223880 <6>[ 15.315511] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10648 12:12:33.230830 <6>[ 15.320319] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10649 12:12:33.237905 <6>[ 15.320347] pci_bus 0000:00: root bus resource [bus 00-ff]
10650 12:12:33.244649 <6>[ 15.320354] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10651 12:12:33.254737 <6>[ 15.320360] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10652 12:12:33.261153 <6>[ 15.320402] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10653 12:12:33.268034 <6>[ 15.320423] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10654 12:12:33.271504 <6>[ 15.320503] pci 0000:00:00.0: supports D1 D2
10655 12:12:33.281555 <6>[ 15.320507] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10656 12:12:33.287607 <3>[ 15.321307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 12:12:33.294688 <6>[ 15.322105] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10658 12:12:33.300959 <6>[ 15.322226] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10659 12:12:33.311222 <6>[ 15.322259] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10660 12:12:33.318335 <6>[ 15.322279] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10661 12:12:33.324604 <6>[ 15.322298] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10662 12:12:33.331030 <6>[ 15.322419] pci 0000:01:00.0: supports D1 D2
10663 12:12:33.338110 <6>[ 15.322423] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10664 12:12:33.344499 <6>[ 15.334963] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10665 12:12:33.351428 <3>[ 15.335147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 12:12:33.361206 <6>[ 15.335615] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10667 12:12:33.370875 <3>[ 15.345048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 12:12:33.377516 <3>[ 15.345062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 12:12:33.384448 <3>[ 15.345073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 12:12:33.394269 <3>[ 15.345120] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 12:12:33.401013 <6>[ 15.352189] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10672 12:12:33.411381 <3>[ 15.357089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10673 12:12:33.417517 <3>[ 15.357780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 12:12:33.428113 <6>[ 15.364931] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10675 12:12:33.437827 <6>[ 15.370044] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10676 12:12:33.444127 <3>[ 15.374809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 12:12:33.453917 <3>[ 15.374823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 12:12:33.460812 <3>[ 15.374912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 12:12:33.467423 <6>[ 15.381144] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10680 12:12:33.477508 <3>[ 15.388583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 12:12:33.483699 <3>[ 15.388590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 12:12:33.493906 <3>[ 15.388598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 12:12:33.497290 <6>[ 15.391472] videodev: Linux video capture interface: v2.00
10684 12:12:33.507003 <6>[ 15.393507] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10685 12:12:33.514201 <3>[ 15.400003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 12:12:33.520742 <3>[ 15.400052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 12:12:33.530751 <6>[ 15.402590] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10688 12:12:33.536980 <6>[ 15.402613] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10689 12:12:33.544018 <6>[ 15.402637] pci 0000:00:00.0: PCI bridge to [bus 01]
10690 12:12:33.550248 <6>[ 15.402647] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10691 12:12:33.557231 <6>[ 15.404113] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10692 12:12:33.563462 <6>[ 15.408069] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10693 12:12:33.570545 <6>[ 15.408711] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10694 12:12:33.576644 <6>[ 15.431565] usbcore: registered new interface driver cdc_ether
10695 12:12:33.583406 <4>[ 15.432247] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10696 12:12:33.593063 <4>[ 15.432260] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10697 12:12:33.596524 <6>[ 15.446564] Bluetooth: Core ver 2.22
10698 12:12:33.603580 <6>[ 15.457460] usbcore: registered new interface driver r8153_ecm
10699 12:12:33.609777 <6>[ 15.464069] NET: Registered PF_BLUETOOTH protocol family
10700 12:12:33.616644 <6>[ 15.489966] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10701 12:12:33.623164 <6>[ 15.491694] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10702 12:12:33.629697 <5>[ 15.493112] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10703 12:12:33.636363 <6>[ 15.497438] remoteproc remoteproc0: powering up scp
10704 12:12:33.646126 <4>[ 15.497481] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10705 12:12:33.649788 <3>[ 15.497491] remoteproc remoteproc0: request_firmware failed: -2
10706 12:12:33.659849 <3>[ 15.497495] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10707 12:12:33.666025 <6>[ 15.497978] Bluetooth: HCI device and connection manager initialized
10708 12:12:33.675887 <6>[ 15.507618] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10709 12:12:33.682686 <6>[ 15.514238] Bluetooth: HCI socket layer initialized
10710 12:12:33.685952 <6>[ 15.514949] r8152 2-1.3:1.0 eth0: v1.12.13
10711 12:12:33.693096 <5>[ 15.517501] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10712 12:12:33.702775 <4>[ 15.517586] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10713 12:12:33.709630 <6>[ 15.517595] cfg80211: failed to load regulatory.db
10714 12:12:33.712481 <6>[ 15.522499] usbcore: registered new interface driver uvcvideo
10715 12:12:33.719194 <6>[ 15.531298] Bluetooth: L2CAP socket layer initialized
10716 12:12:33.725704 <6>[ 15.623788] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10717 12:12:33.732398 <6>[ 15.625918] Bluetooth: SCO socket layer initialized
10718 12:12:33.738644 <6>[ 15.634092] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10719 12:12:33.742574 <6>[ 15.690296] usbcore: registered new interface driver btusb
10720 12:12:33.755178 <4>[ 15.691021] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10721 12:12:33.758647 <3>[ 15.691033] Bluetooth: hci0: Failed to load firmware file (-2)
10722 12:12:33.765754 <3>[ 15.691037] Bluetooth: hci0: Failed to set up firmware (-2)
10723 12:12:33.775435 <4>[ 15.691041] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10724 12:12:33.781799 <6>[ 15.715079] mt7921e 0000:01:00.0: ASIC revision: 79610010
10725 12:12:33.886465 <4>[ 15.994703] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10726 12:12:33.887178 done
10727 12:12:33.906725 Saving random seed: OK
10728 12:12:33.923392 Starting network: OK
10729 12:12:33.961251 Starting dropbear sshd: <6>[ 16.076496] NET: Registered PF_INET6 protocol family
10730 12:12:33.968152 <6>[ 16.082913] Segment Routing with IPv6
10731 12:12:33.971549 <6>[ 16.086858] In-situ OAM (IOAM) with IPv6
10732 12:12:33.974961 OK
10733 12:12:33.984941 /bin/sh: can't access tty; job control turned off
10734 12:12:33.986031 Matched prompt #10: / #
10736 12:12:33.987318 Setting prompt string to ['/ #']
10737 12:12:33.987856 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10739 12:12:33.988962 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10740 12:12:33.989439 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
10741 12:12:33.989823 Setting prompt string to ['/ #']
10742 12:12:33.990172 Forcing a shell prompt, looking for ['/ #']
10744 12:12:34.040996 / #
10745 12:12:34.041560 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10746 12:12:34.042000 Waiting using forced prompt support (timeout 00:02:30)
10747 12:12:34.042501 <4>[ 16.125514] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 12:12:34.046822
10749 12:12:34.047712 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10750 12:12:34.048237 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
10751 12:12:34.048706 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10752 12:12:34.049136 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
10753 12:12:34.049609 end: 2 depthcharge-action (duration 00:01:14) [common]
10754 12:12:34.050068 start: 3 lava-test-retry (timeout 00:01:00) [common]
10755 12:12:34.050516 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10756 12:12:34.050935 Using namespace: common
10758 12:12:34.152020 / # #
10759 12:12:34.152584 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10760 12:12:34.153115 #<4>[ 16.245172] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 12:12:34.158094
10762 12:12:34.158883 Using /lava-10605438
10764 12:12:34.259865 / # export SHELL=/bin/sh
10765 12:12:34.260147 export SHELL=/bin/sh<4>[ 16.365333] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 12:12:34.265907
10768 12:12:34.366801 / # . /lava-10605438/environment
10769 12:12:34.411836 . /lava-10605438/environment<4>[ 16.485396] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 12:12:34.412372
10772 12:12:34.513598 / # /lava-10605438/bin/lava-test-runner /lava-10605438/0
10773 12:12:34.514047 Test shell timeout: 10s (minimum of the action and connection timeout)
10774 12:12:34.515491 /lava-10605438/bin/lava-test-runner /lava-10605438/0<4>[ 16.605283] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 12:12:34.519984
10776 12:12:34.563667 + export 'TESTRUN_ID=0_dmesg'
10777 12:12:34.564105 +<8>[ 16.657239] <LAVA_SIGNAL_STARTRUN 0_dmesg 10605438_1.5.2.3.1>
10778 12:12:34.564451 cd /lava-10605438/0/tests/0_dmesg
10779 12:12:34.564765 + cat uuid
10780 12:12:34.565332 Received signal: <STARTRUN> 0_dmesg 10605438_1.5.2.3.1
10781 12:12:34.565760 Starting test lava.0_dmesg (10605438_1.5.2.3.1)
10782 12:12:34.566157 Skipping test definition patterns.
10783 12:12:34.566640 + UUID=10605438_1.5.2.3.1
10784 12:12:34.567101 + set +x
10785 12:12:34.567465 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10786 12:12:34.567844 <8>[ 16.677232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10787 12:12:34.568411 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10789 12:12:34.585674 <8>[ 16.697492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10790 12:12:34.586341 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10792 12:12:34.619145 <4>[ 16.727580] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 12:12:34.626024 <8>[ 16.728186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10794 12:12:34.626707 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10796 12:12:34.632329 + set +x
10797 12:12:34.635625 <8>[ 16.750945] <LAVA_SIGNAL_ENDRUN 0_dmesg 10605438_1.5.2.3.1>
10798 12:12:34.636315 Received signal: <ENDRUN> 0_dmesg 10605438_1.5.2.3.1
10799 12:12:34.636728 Ending use of test pattern.
10800 12:12:34.637064 Ending test lava.0_dmesg (10605438_1.5.2.3.1), duration 0.07
10802 12:12:34.639788 <LAVA_TEST_RUNNER EXIT>
10803 12:12:34.640455 ok: lava_test_shell seems to have completed
10804 12:12:34.640989 alert: pass
crit: pass
emerg: pass
10805 12:12:34.641404 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10806 12:12:34.641817 end: 3 lava-test-retry (duration 00:00:01) [common]
10807 12:12:34.642235 start: 4 lava-test-retry (timeout 00:01:00) [common]
10808 12:12:34.642645 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10809 12:12:34.642973 Using namespace: common
10811 12:12:34.743972 / # #
10812 12:12:34.744537 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10813 12:12:34.745046 Using /lava-10605438
10815 12:12:34.845954 export SHELL=/bin/sh
10816 12:12:34.846213 #<4>[ 16.845433] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 12:12:34.846324
10819 12:12:34.946948 / # export SHELL=/bin/sh. /lava-10605438/environment
10820 12:12:34.947953 <4>[ 16.965521] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 12:12:34.948500
10823 12:12:35.050137 / # . /lava-10605438/environment/lava-10605438/bin/lava-test-runner /lava-10605438/1
10824 12:12:35.050769 Test shell timeout: 10s (minimum of the action and connection timeout)
10825 12:12:35.051442
10826 12:12:35.052008 / # <4>[ 17.085819] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 12:12:35.056183 /lava-10605438/bin/lava-test-runner /lava-10605438/1
10828 12:12:35.099465 + export 'TESTRUN_ID=1_bootrr'
10829 12:12:35.099559 + cd /lava-10605438/1/tests/1_bo<8>[ 17.195386] <LAVA_SIGNAL_STARTRUN 1_bootrr 10605438_1.5.2.3.5>
10830 12:12:35.099647 otrr
10831 12:12:35.099722 + cat uuid
10832 12:12:35.099801 + UUID=1060543<3>[ 17.204529] mt7921e 0000:01:00.0: hardware init failed
10833 12:12:35.099900 8_1.5.2.3.5
10834 12:12:35.100003 + set +x
10835 12:12:35.100273 Received signal: <STARTRUN> 1_bootrr 10605438_1.5.2.3.5
10836 12:12:35.100365 Starting test lava.1_bootrr (10605438_1.5.2.3.5)
10837 12:12:35.100484 Skipping test definition patterns.
10838 12:12:35.108788 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10605438/1/../bin:/sbin:/usr/sbin<8>[ 17.219747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10839 12:12:35.108875 :/bin:/usr/bin'
10840 12:12:35.109111 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10842 12:12:35.111970 + cd /opt/bootrr/libexec/bootrr
10843 12:12:35.115455 + sh helpers/bootrr-auto
10844 12:12:35.118881 /lava-10605438/1/../bin/lava-test-case
10845 12:12:35.125541 /lava-106054<8>[ 17.239435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10846 12:12:35.125795 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10848 12:12:35.128981 38/1/../bin/lava-test-case
10849 12:12:35.132489 /usr/bin/tpm2_getcap
10850 12:12:35.166294 /lava-10605438/1/../bin/lava-test-case
10851 12:12:35.172733 <8>[ 17.285125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10852 12:12:35.173054 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10854 12:12:35.188824 /lava-10605438/1/../bin/lava-test-case
10855 12:12:35.195103 <8>[ 17.307590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10856 12:12:35.195700 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10858 12:12:35.206577 /lava-10605438/1/../bin/lava-test-case
10859 12:12:35.213374 <8>[ 17.325598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10860 12:12:35.214059 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10862 12:12:35.224980 /lava-10605438/1/../bin/lava-test-case
10863 12:12:35.231140 <8>[ 17.343427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10864 12:12:35.231870 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10866 12:12:35.242577 /lava-10605438/1/../bin/lava-test-case
10867 12:12:35.249074 <8>[ 17.361279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10868 12:12:35.249755 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10870 12:12:35.261515 /lava-10605438/1/../bin/lava-test-case
10871 12:12:35.267806 <8>[ 17.379836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10872 12:12:35.268564 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10874 12:12:35.277128 /lava-10605438/1/../bin/lava-test-case
10875 12:12:35.284006 <8>[ 17.395811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10876 12:12:35.284745 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10878 12:12:35.295431 /lava-10605438/1/../bin/lava-test-case
10879 12:12:35.301630 <8>[ 17.414092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10880 12:12:35.302319 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10882 12:12:35.310887 /lava-10605438/1/../bin/lava-test-case
10883 12:12:35.317549 <8>[ 17.429292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10884 12:12:35.318237 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10886 12:12:35.330577 /lava-10605438/1/../bin/lava-test-case
10887 12:12:35.336810 <8>[ 17.449570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10888 12:12:35.337509 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10890 12:12:35.349329 /lava-10605438/1/../bin/lava-test-case
10891 12:12:35.355876 <8>[ 17.468162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10892 12:12:35.356128 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10894 12:12:35.368269 /lava-10605438/1/../bin/lava-test-case
10895 12:12:35.375293 <8>[ 17.486747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10896 12:12:35.375587 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10898 12:12:35.386859 /lava-10605438/1/../bin/lava-test-case
10899 12:12:35.393185 <8>[ 17.505846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10900 12:12:35.393438 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10902 12:12:35.403656 /lava-10605438/1/../bin/lava-test-case
10903 12:12:35.410747 <8>[ 17.522558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10904 12:12:35.411000 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10906 12:12:35.422162 /lava-10605438/1/../bin/lava-test-case
10907 12:12:35.428760 <8>[ 17.540690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10908 12:12:35.429014 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10910 12:12:35.437534 /lava-10605438/1/../bin/lava-test-case
10911 12:12:35.444496 <8>[ 17.556841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10912 12:12:35.444749 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10914 12:12:35.455997 /lava-10605438/1/../bin/lava-test-case
10915 12:12:35.463126 <8>[ 17.575242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10916 12:12:35.463348 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10918 12:12:35.471982 /lava-10605438/1/../bin/lava-test-case
10919 12:12:35.478991 <8>[ 17.591211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10920 12:12:35.479245 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10922 12:12:35.489963 /lava-10605438/1/../bin/lava-test-case
10923 12:12:35.496326 <8>[ 17.609066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10924 12:12:35.496615 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10926 12:12:35.505339 /lava-10605438/1/../bin/lava-test-case
10927 12:12:35.512350 <8>[ 17.624344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10928 12:12:35.512622 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10930 12:12:35.524643 /lava-10605438/1/../bin/lava-test-case
10931 12:12:35.530735 <8>[ 17.643026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10932 12:12:35.530987 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10934 12:12:35.539911 /lava-10605438/1/../bin/lava-test-case
10935 12:12:35.547037 <8>[ 17.659342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10936 12:12:35.547289 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10938 12:12:35.558825 /lava-10605438/1/../bin/lava-test-case
10939 12:12:35.565618 <8>[ 17.677827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10940 12:12:35.566501 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10942 12:12:35.577535 /lava-10605438/1/../bin/lava-test-case
10943 12:12:35.583727 <8>[ 17.695984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10944 12:12:35.584647 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10946 12:12:35.593079 /lava-10605438/1/../bin/lava-test-case
10947 12:12:35.599828 <8>[ 17.711854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10948 12:12:35.600498 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10950 12:12:35.611776 /lava-10605438/1/../bin/lava-test-case
10951 12:12:35.618130 <8>[ 17.729981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10952 12:12:35.618981 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10954 12:12:35.627749 /lava-10605438/1/../bin/lava-test-case
10955 12:12:35.633922 <8>[ 17.746311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10956 12:12:35.634771 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10958 12:12:35.646613 /lava-10605438/1/../bin/lava-test-case
10959 12:12:35.652937 <8>[ 17.765697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10960 12:12:35.653669 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10962 12:12:35.664712 /lava-10605438/1/../bin/lava-test-case
10963 12:12:35.671564 <8>[ 17.783570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10964 12:12:35.672275 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10966 12:12:35.683376 /lava-10605438/1/../bin/lava-test-case
10967 12:12:35.689518 <8>[ 17.802248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10968 12:12:35.690318 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10970 12:12:35.701320 /lava-10605438/1/../bin/lava-test-case
10971 12:12:35.708090 <8>[ 17.820481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10972 12:12:35.708789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10974 12:12:35.717805 /lava-10605438/1/../bin/lava-test-case
10975 12:12:35.724420 <8>[ 17.836697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10976 12:12:35.724678 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10978 12:12:35.736415 /lava-10605438/1/../bin/lava-test-case
10979 12:12:35.743398 <8>[ 17.855329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10980 12:12:35.743655 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10982 12:12:35.754448 /lava-10605438/1/../bin/lava-test-case
10983 12:12:35.760806 <8>[ 17.873439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10984 12:12:35.761063 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10986 12:12:35.770310 /lava-10605438/1/../bin/lava-test-case
10987 12:12:35.777084 <8>[ 17.889268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10988 12:12:35.777338 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10990 12:12:35.789039 /lava-10605438/1/../bin/lava-test-case
10991 12:12:35.795725 <8>[ 17.907887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10992 12:12:35.795982 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10994 12:12:35.805463 /lava-10605438/1/../bin/lava-test-case
10995 12:12:35.811788 <8>[ 17.923952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10996 12:12:35.812040 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10998 12:12:35.823739 /lava-10605438/1/../bin/lava-test-case
10999 12:12:35.830639 <8>[ 17.943010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11000 12:12:35.830903 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11002 12:12:35.840161 /lava-10605438/1/../bin/lava-test-case
11003 12:12:35.846681 <8>[ 17.959200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11004 12:12:35.846931 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11006 12:12:35.858908 /lava-10605438/1/../bin/lava-test-case
11007 12:12:35.865348 <8>[ 17.978142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11008 12:12:35.865597 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11010 12:12:35.874663 /lava-10605438/1/../bin/lava-test-case
11011 12:12:35.881385 <8>[ 17.993836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11012 12:12:35.881642 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11014 12:12:35.894117 /lava-10605438/1/../bin/lava-test-case
11015 12:12:35.900631 <8>[ 18.013099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11016 12:12:35.900892 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11018 12:12:35.910970 /lava-10605438/1/../bin/lava-test-case
11019 12:12:35.917235 <8>[ 18.029431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11020 12:12:35.917563 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11022 12:12:35.929469 /lava-10605438/1/../bin/lava-test-case
11023 12:12:35.936453 <8>[ 18.048266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11024 12:12:35.937410 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11026 12:12:35.945368 /lava-10605438/1/../bin/lava-test-case
11027 12:12:35.951599 <8>[ 18.064026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11028 12:12:35.952841 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11030 12:12:35.963197 /lava-10605438/1/../bin/lava-test-case
11031 12:12:35.969286 <8>[ 18.082160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11032 12:12:35.970129 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11034 12:12:35.978600 /lava-10605438/1/../bin/lava-test-case
11035 12:12:35.985426 <8>[ 18.098051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11036 12:12:35.986277 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11038 12:12:35.998160 /lava-10605438/1/../bin/lava-test-case
11039 12:12:36.004575 <8>[ 18.116735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11040 12:12:36.005250 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11042 12:12:36.016784 /lava-10605438/1/../bin/lava-test-case
11043 12:12:36.022895 <8>[ 18.135565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11044 12:12:36.023601 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11046 12:12:37.035064 /lava-10605438/1/../bin/lava-test-case
11047 12:12:37.041337 <8>[ 19.154669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11048 12:12:37.041983 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11050 12:12:38.054834 /lava-10605438/1/../bin/lava-test-case
11051 12:12:38.061499 <8>[ 20.174679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11052 12:12:38.062182 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11053 12:12:38.062605 Bad test result: blocked
11054 12:12:38.071838 /lava-10605438/1/../bin/lava-test-case
11055 12:12:38.078269 <8>[ 20.190957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11056 12:12:38.078939 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11058 12:12:38.089946 /lava-10605438/1/../bin/lava-test-case
11059 12:12:38.096314 <8>[ 20.208500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11060 12:12:38.096978 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11062 12:12:38.107358 /lava-10605438/1/../bin/lava-test-case
11063 12:12:38.113617 <8>[ 20.226164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11064 12:12:38.114284 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11066 12:12:38.125490 /lava-10605438/1/../bin/lava-test-case
11067 12:12:38.131529 <8>[ 20.244080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11068 12:12:38.132216 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11070 12:12:38.142490 /lava-10605438/1/../bin/lava-test-case
11071 12:12:38.149237 <8>[ 20.262050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11072 12:12:38.149750 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11074 12:12:38.160574 /lava-10605438/1/../bin/lava-test-case
11075 12:12:38.167253 <8>[ 20.280210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11076 12:12:38.167586 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11078 12:12:38.176914 /lava-10605438/1/../bin/lava-test-case
11079 12:12:38.183069 <8>[ 20.296111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11080 12:12:38.183354 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11082 12:12:38.194641 /lava-10605438/1/../bin/lava-test-case
11083 12:12:38.201382 <8>[ 20.314119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11084 12:12:38.201661 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11086 12:12:38.212437 /lava-10605438/1/../bin/lava-test-case
11087 12:12:38.218727 <8>[ 20.331410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11088 12:12:38.219026 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11090 12:12:38.227879 /lava-10605438/1/../bin/lava-test-case
11091 12:12:38.234059 <8>[ 20.347149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11092 12:12:38.234321 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11094 12:12:38.242790 /lava-10605438/1/../bin/lava-test-case
11095 12:12:38.252908 <8>[ 20.365133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11096 12:12:38.253156 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11098 12:12:38.261266 /lava-10605438/1/../bin/lava-test-case
11099 12:12:38.268173 <8>[ 20.381031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11100 12:12:38.268431 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11102 12:12:38.279970 /lava-10605438/1/../bin/lava-test-case
11103 12:12:38.286092 <8>[ 20.399470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11104 12:12:38.286351 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11106 12:12:38.295568 /lava-10605438/1/../bin/lava-test-case
11107 12:12:38.302305 <8>[ 20.414932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11108 12:12:38.302612 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11110 12:12:38.314276 /lava-10605438/1/../bin/lava-test-case
11111 12:12:38.320461 <8>[ 20.433861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11112 12:12:38.320752 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11114 12:12:38.332039 /lava-10605438/1/../bin/lava-test-case
11115 12:12:38.338934 <8>[ 20.451279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11116 12:12:38.339189 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11118 12:12:38.349705 /lava-10605438/1/../bin/lava-test-case
11119 12:12:38.356603 <8>[ 20.469721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11120 12:12:38.356886 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11122 12:12:38.367543 /lava-10605438/1/../bin/lava-test-case
11123 12:12:38.374206 <8>[ 20.487564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11124 12:12:38.374544 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11126 12:12:38.386630 /lava-10605438/1/../bin/lava-test-case
11127 12:12:38.393184 <8>[ 20.505733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11128 12:12:38.393863 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11130 12:12:38.403870 /lava-10605438/1/../bin/lava-test-case
11131 12:12:38.410499 <8>[ 20.523167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11132 12:12:38.411322 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11134 12:12:38.421619 /lava-10605438/1/../bin/lava-test-case
11135 12:12:38.427842 <8>[ 20.541004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11136 12:12:38.428686 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11138 12:12:38.439730 /lava-10605438/1/../bin/lava-test-case
11139 12:12:38.446062 <8>[ 20.558278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11140 12:12:38.446833 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11142 12:12:38.456767 /lava-10605438/1/../bin/lava-test-case
11143 12:12:38.463829 <8>[ 20.576798] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11144 12:12:38.464510 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11146 12:12:38.475746 /lava-10605438/1/../bin/lava-test-case
11147 12:12:38.482337 <8>[ 20.595029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11148 12:12:38.483013 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11150 12:12:38.493868 /lava-10605438/1/../bin/lava-test-case
11151 12:12:38.500618 <8>[ 20.612635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11152 12:12:38.501353 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11154 12:12:38.511582 /lava-10605438/1/../bin/lava-test-case
11155 12:12:38.517892 <8>[ 20.630832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11156 12:12:38.518594 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11158 12:12:38.528862 /lava-10605438/1/../bin/lava-test-case
11159 12:12:38.535933 <8>[ 20.647967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11160 12:12:38.536695 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11162 12:12:38.546852 /lava-10605438/1/../bin/lava-test-case
11163 12:12:38.553131 <8>[ 20.665616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11164 12:12:38.554082 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11166 12:12:38.563982 /lava-10605438/1/../bin/lava-test-case
11167 12:12:38.570420 <8>[ 20.683074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11168 12:12:38.571093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11170 12:12:38.579859 /lava-10605438/1/../bin/lava-test-case
11171 12:12:38.586643 <8>[ 20.698767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11172 12:12:38.587481 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11174 12:12:38.597715 /lava-10605438/1/../bin/lava-test-case
11175 12:12:38.603951 <8>[ 20.716703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11176 12:12:38.604692 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11178 12:12:38.613029 /lava-10605438/1/../bin/lava-test-case
11179 12:12:38.619559 <8>[ 20.732236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11180 12:12:38.620621 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11182 12:12:38.631260 /lava-10605438/1/../bin/lava-test-case
11183 12:12:38.638457 <8>[ 20.750422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11184 12:12:38.639141 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11186 12:12:38.647109 /lava-10605438/1/../bin/lava-test-case
11187 12:12:38.653372 <8>[ 20.766089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11188 12:12:38.653753 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11190 12:12:38.665821 /lava-10605438/1/../bin/lava-test-case
11191 12:12:38.672348 <8>[ 20.784732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11192 12:12:38.672629 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11194 12:12:38.681820 /lava-10605438/1/../bin/lava-test-case
11195 12:12:38.688052 <8>[ 20.800734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11196 12:12:38.688339 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11198 12:12:38.699536 /lava-10605438/1/../bin/lava-test-case
11199 12:12:38.706634 <8>[ 20.818852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11200 12:12:38.706891 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11202 12:12:38.715044 /lava-10605438/1/../bin/lava-test-case
11203 12:12:38.722027 <8>[ 20.834571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11204 12:12:38.722290 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11206 12:12:38.733419 /lava-10605438/1/../bin/lava-test-case
11207 12:12:38.740261 <8>[ 20.852796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11208 12:12:38.740522 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11210 12:12:38.748650 /lava-10605438/1/../bin/lava-test-case
11211 12:12:38.754849 <8>[ 20.868328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11212 12:12:38.755095 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11214 12:12:38.768115 /lava-10605438/1/../bin/lava-test-case
11215 12:12:38.774346 <8>[ 20.886690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11216 12:12:38.774596 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11218 12:12:38.785576 /lava-10605438/1/../bin/lava-test-case
11219 12:12:38.792388 <8>[ 20.905217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11220 12:12:38.792642 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11222 12:12:38.801840 /lava-10605438/1/../bin/lava-test-case
11223 12:12:38.808427 <8>[ 20.921647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11224 12:12:38.808683 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11226 12:12:38.820716 /lava-10605438/1/../bin/lava-test-case
11227 12:12:38.826952 <8>[ 20.940305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11228 12:12:38.827208 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11230 12:12:38.836317 /lava-10605438/1/../bin/lava-test-case
11231 12:12:38.842409 <8>[ 20.955720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11232 12:12:38.842658 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11234 12:12:38.853394 /lava-10605438/1/../bin/lava-test-case
11235 12:12:38.860484 <8>[ 20.972971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11236 12:12:38.860736 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11238 12:12:38.868246 /lava-10605438/1/../bin/lava-test-case
11239 12:12:38.875283 <8>[ 20.988167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11240 12:12:38.875592 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11242 12:12:39.888776 /lava-10605438/1/../bin/lava-test-case
11243 12:12:39.895539 <8>[ 22.008791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11244 12:12:39.895812 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11246 12:12:39.904576 /lava-10605438/1/../bin/lava-test-case
11247 12:12:39.911218 <8>[ 22.024592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11248 12:12:39.911534 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11250 12:12:40.926269 /lava-10605438/1/../bin/lava-test-case
11251 12:12:40.932296 <8>[ 23.046646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11252 12:12:40.932607 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11254 12:12:40.942989 /lava-10605438/1/../bin/lava-test-case
11255 12:12:40.949304 <8>[ 23.062683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11256 12:12:40.949715 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11258 12:12:41.963389 /lava-10605438/1/../bin/lava-test-case
11259 12:12:41.970235 <8>[ 24.084233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11260 12:12:41.970549 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11262 12:12:41.980692 /lava-10605438/1/../bin/lava-test-case
11263 12:12:41.987167 <8>[ 24.100456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11264 12:12:41.987452 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11266 12:12:43.000446 /lava-10605438/1/../bin/lava-test-case
11267 12:12:43.007093 <8>[ 25.121499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11268 12:12:43.007400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11270 12:12:43.017305 /lava-10605438/1/../bin/lava-test-case
11271 12:12:43.024024 <8>[ 25.136971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11272 12:12:43.024270 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11274 12:12:44.037291 /lava-10605438/1/../bin/lava-test-case
11275 12:12:44.043550 <8>[ 26.158047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11276 12:12:44.043845 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11278 12:12:44.053864 /lava-10605438/1/../bin/lava-test-case
11279 12:12:44.060464 <8>[ 26.174126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11280 12:12:44.060751 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11282 12:12:45.074668 /lava-10605438/1/../bin/lava-test-case
11283 12:12:45.081344 <8>[ 27.196038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11284 12:12:45.081621 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11286 12:12:45.092434 /lava-10605438/1/../bin/lava-test-case
11287 12:12:45.098387 <8>[ 27.212839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11288 12:12:45.098671 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11290 12:12:46.113679 /lava-10605438/1/../bin/lava-test-case
11291 12:12:46.120038 <8>[ 28.234577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11292 12:12:46.120351 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11294 12:12:46.130460 /lava-10605438/1/../bin/lava-test-case
11295 12:12:46.136922 <8>[ 28.250515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11296 12:12:46.137218 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11298 12:12:46.146715 /lava-10605438/1/../bin/lava-test-case
11299 12:12:46.152963 <8>[ 28.266636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11300 12:12:46.153242 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11302 12:12:47.168047 /lava-10605438/1/../bin/lava-test-case
11303 12:12:47.174160 <8>[ 29.289161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11304 12:12:47.174423 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11306 12:12:47.185319 /lava-10605438/1/../bin/lava-test-case
11307 12:12:47.191480 <8>[ 29.306051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11308 12:12:47.191747 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11310 12:12:47.204558 /lava-10605438/1/../bin/lava-test-case
11311 12:12:47.210833 <8>[ 29.325345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11312 12:12:47.211127 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11314 12:12:47.220447 /lava-10605438/1/../bin/lava-test-case
11315 12:12:47.226848 <8>[ 29.341300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11316 12:12:47.227135 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11318 12:12:47.239571 /lava-10605438/1/../bin/lava-test-case
11319 12:12:47.246353 <8>[ 29.360639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11320 12:12:47.246610 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11322 12:12:47.258200 /lava-10605438/1/../bin/lava-test-case
11323 12:12:47.264639 <8>[ 29.379086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11324 12:12:47.264897 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11326 12:12:47.276506 /lava-10605438/1/../bin/lava-test-case
11327 12:12:47.283292 <8>[ 29.397549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11328 12:12:47.283573 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11330 12:12:47.293428 /lava-10605438/1/../bin/lava-test-case
11331 12:12:47.300263 <8>[ 29.413755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11332 12:12:47.300538 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11334 12:12:47.312985 /lava-10605438/1/../bin/lava-test-case
11335 12:12:47.319228 <8>[ 29.433419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11336 12:12:47.319482 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11338 12:12:47.331849 /lava-10605438/1/../bin/lava-test-case
11339 12:12:47.338062 <8>[ 29.452336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11340 12:12:47.338315 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11342 12:12:47.348477 /lava-10605438/1/../bin/lava-test-case
11343 12:12:47.354732 <8>[ 29.468627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11344 12:12:47.354980 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11346 12:12:47.366635 /lava-10605438/1/../bin/lava-test-case
11347 12:12:47.373184 <8>[ 29.487116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11348 12:12:47.373436 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11350 12:12:47.383002 /lava-10605438/1/../bin/lava-test-case
11351 12:12:47.389444 <8>[ 29.503077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11352 12:12:47.389742 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11354 12:12:47.402185 /lava-10605438/1/../bin/lava-test-case
11355 12:12:47.408541 <8>[ 29.522738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11356 12:12:47.408817 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11358 12:12:47.418360 /lava-10605438/1/../bin/lava-test-case
11359 12:12:47.425363 <8>[ 29.539365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11360 12:12:47.425650 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11362 12:12:47.438369 /lava-10605438/1/../bin/lava-test-case
11363 12:12:47.444798 <8>[ 29.558616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11364 12:12:47.445058 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11366 12:12:47.454786 /lava-10605438/1/../bin/lava-test-case
11367 12:12:47.461280 <8>[ 29.575414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11368 12:12:47.461534 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11370 12:12:47.474455 /lava-10605438/1/../bin/lava-test-case
11371 12:12:47.480913 <8>[ 29.594534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11372 12:12:47.481195 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11374 12:12:47.490789 /lava-10605438/1/../bin/lava-test-case
11375 12:12:47.497357 <8>[ 29.611339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11376 12:12:47.497640 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11378 12:12:47.508988 /lava-10605438/1/../bin/lava-test-case
11379 12:12:47.515807 <8>[ 29.629199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11380 12:12:47.516062 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11382 12:12:47.524802 /lava-10605438/1/../bin/lava-test-case
11383 12:12:47.531070 <8>[ 29.645522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11384 12:12:47.531331 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11386 12:12:48.544877 /lava-10605438/1/../bin/lava-test-case
11387 12:12:48.551783 <8>[ 30.665734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11388 12:12:48.552053 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11390 12:12:49.565305 /lava-10605438/1/../bin/lava-test-case
11391 12:12:49.572074 <8>[ 31.687165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11392 12:12:49.572898 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11394 12:12:49.582214 /lava-10605438/1/../bin/lava-test-case
11395 12:12:49.588872 <8>[ 31.703010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11396 12:12:49.589588 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11398 12:12:49.600936 /lava-10605438/1/../bin/lava-test-case
11399 12:12:49.607919 <8>[ 31.721581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11400 12:12:49.608705 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11402 12:12:49.616780 /lava-10605438/1/../bin/lava-test-case
11403 12:12:49.622971 <8>[ 31.737225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11404 12:12:49.623679 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11406 12:12:49.635672 /lava-10605438/1/../bin/lava-test-case
11407 12:12:49.642479 <8>[ 31.756192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11408 12:12:49.643379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11410 12:12:49.650764 /lava-10605438/1/../bin/lava-test-case
11411 12:12:49.657657 <8>[ 31.771812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11412 12:12:49.658356 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11414 12:12:49.669163 /lava-10605438/1/../bin/lava-test-case
11415 12:12:49.675876 <8>[ 31.789710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11416 12:12:49.676548 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11418 12:12:49.684521 /lava-10605438/1/../bin/lava-test-case
11419 12:12:49.690771 <8>[ 31.805053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11420 12:12:49.691635 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11422 12:12:49.702597 /lava-10605438/1/../bin/lava-test-case
11423 12:12:49.709123 <8>[ 31.823366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11424 12:12:49.709916 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11426 12:12:49.718202 /lava-10605438/1/../bin/lava-test-case
11427 12:12:49.724281 <8>[ 31.838774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11428 12:12:49.725133 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11430 12:12:49.736240 /lava-10605438/1/../bin/lava-test-case
11431 12:12:49.743092 <8>[ 31.857005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11432 12:12:49.743924 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11434 12:12:49.751650 /lava-10605438/1/../bin/lava-test-case
11435 12:12:49.757864 <8>[ 31.872250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11436 12:12:49.758745 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11438 12:12:49.770023 /lava-10605438/1/../bin/lava-test-case
11439 12:12:49.776804 <8>[ 31.890709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11440 12:12:49.777716 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11442 12:12:49.785559 /lava-10605438/1/../bin/lava-test-case
11443 12:12:49.792609 <8>[ 31.905875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11444 12:12:49.793444 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11446 12:12:49.803792 /lava-10605438/1/../bin/lava-test-case
11447 12:12:49.810009 <8>[ 31.924195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11448 12:12:49.810825 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11450 12:12:49.818639 /lava-10605438/1/../bin/lava-test-case
11451 12:12:49.825453 <8>[ 31.938814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11452 12:12:49.826291 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11454 12:12:49.836804 /lava-10605438/1/../bin/lava-test-case
11455 12:12:49.842897 <8>[ 31.956762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11456 12:12:49.843774 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11458 12:12:49.851737 /lava-10605438/1/../bin/lava-test-case
11459 12:12:49.858535 <8>[ 31.971979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11460 12:12:49.859422 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11462 12:12:49.869655 /lava-10605438/1/../bin/lava-test-case
11463 12:12:49.875624 <8>[ 31.989540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11464 12:12:49.876330 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11466 12:12:49.884307 /lava-10605438/1/../bin/lava-test-case
11467 12:12:49.890842 <8>[ 32.005127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11468 12:12:49.891525 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11470 12:12:49.902528 /lava-10605438/1/../bin/lava-test-case
11471 12:12:49.909512 <8>[ 32.023180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11472 12:12:49.910434 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11474 12:12:50.920042 /lava-10605438/1/../bin/lava-test-case
11475 12:12:50.926971 <8>[ 33.042134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11476 12:12:50.927238 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11478 12:12:51.939622 /lava-10605438/1/../bin/lava-test-case
11479 12:12:51.946641 <8>[ 34.061825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11480 12:12:51.946908 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11481 12:12:51.946991 Bad test result: blocked
11482 12:12:51.957153 /lava-10605438/1/../bin/lava-test-case
11483 12:12:51.963851 <8>[ 34.078156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11484 12:12:51.964131 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11486 12:12:52.976587 /lava-10605438/1/../bin/lava-test-case
11487 12:12:52.982807 <8>[ 35.097960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11488 12:12:52.983081 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11490 12:12:52.992390 /lava-10605438/1/../bin/lava-test-case
11491 12:12:52.998857 <8>[ 35.112906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11492 12:12:52.999137 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11494 12:12:53.010502 /lava-10605438/1/../bin/lava-test-case
11495 12:12:53.016527 <8>[ 35.130726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11496 12:12:53.016867 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11498 12:12:53.027216 /lava-10605438/1/../bin/lava-test-case
11499 12:12:53.033888 <8>[ 35.148478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11500 12:12:53.034433 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11502 12:12:53.042624 /lava-10605438/1/../bin/lava-test-case
11503 12:12:53.049418 <8>[ 35.163725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11504 12:12:53.050335 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11506 12:12:53.060968 /lava-10605438/1/../bin/lava-test-case
11507 12:12:53.067116 <8>[ 35.181593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11508 12:12:53.067889 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11510 12:12:53.076133 /lava-10605438/1/../bin/lava-test-case
11511 12:12:53.082487 <8>[ 35.197061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11512 12:12:53.083237 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11514 12:12:54.097254 /lava-10605438/1/../bin/lava-test-case
11515 12:12:54.103792 <8>[ 36.218791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11516 12:12:54.104503 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11518 12:12:54.113556 /lava-10605438/1/../bin/lava-test-case
11519 12:12:54.119771 <8>[ 36.234470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11520 12:12:54.120452 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11522 12:12:55.132670 /lava-10605438/1/../bin/lava-test-case
11523 12:12:55.139617 <8>[ 37.253893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11524 12:12:55.140300 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11526 12:12:55.147832 /lava-10605438/1/../bin/lava-test-case
11527 12:12:55.154098 <8>[ 37.269307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11528 12:12:55.154764 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11530 12:12:56.167831 /lava-10605438/1/../bin/lava-test-case
11531 12:12:56.174452 <8>[ 38.290395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11532 12:12:56.174727 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11534 12:12:56.184324 /lava-10605438/1/../bin/lava-test-case
11535 12:12:56.191023 <8>[ 38.305840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11536 12:12:56.191293 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11538 12:12:57.204631 /lava-10605438/1/../bin/lava-test-case
11539 12:12:57.211027 <8>[ 39.326671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11540 12:12:57.211768 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11542 12:12:57.222329 /lava-10605438/1/../bin/lava-test-case
11543 12:12:57.228789 <8>[ 39.343131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11544 12:12:57.229465 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11546 12:12:57.239739 /lava-10605438/1/../bin/lava-test-case
11547 12:12:57.245842 <8>[ 39.360949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11548 12:12:57.246515 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11550 12:12:57.256562 /lava-10605438/1/../bin/lava-test-case
11551 12:12:57.263232 <8>[ 39.377876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11552 12:12:57.263965 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11554 12:12:57.271538 /lava-10605438/1/../bin/lava-test-case
11555 12:12:57.277980 <8>[ 39.392982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11556 12:12:57.278261 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11558 12:12:57.289691 /lava-10605438/1/../bin/lava-test-case
11559 12:12:57.296156 <8>[ 39.411046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11560 12:12:57.296441 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11562 12:12:57.305110 /lava-10605438/1/../bin/lava-test-case
11563 12:12:57.311645 <8>[ 39.426085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11564 12:12:57.311929 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11566 12:12:57.322306 /lava-10605438/1/../bin/lava-test-case
11567 12:12:57.328995 <8>[ 39.444437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11568 12:12:57.329289 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11570 12:12:57.338484 /lava-10605438/1/../bin/lava-test-case
11571 12:12:57.345300 <8>[ 39.459973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11572 12:12:57.345588 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11574 12:12:58.359787 /lava-10605438/1/../bin/lava-test-case
11575 12:12:58.366069 <8>[ 40.481520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11576 12:12:58.366999 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11578 12:12:58.370046 + set +x
11579 12:12:58.373841 Received signal: <ENDRUN> 1_bootrr 10605438_1.5.2.3.5
11580 12:12:58.374468 Ending use of test pattern.
11581 12:12:58.375007 Ending test lava.1_bootrr (10605438_1.5.2.3.5), duration 23.27
11583 12:12:58.378047 <8>[ 40.491765] <LAVA_SIGNAL_ENDRUN 1_bootrr 10605438_1.5.2.3.5>
11584 12:12:58.378968 ok: lava_test_shell seems to have completed
11585 12:12:58.388091 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11586 12:12:58.388766 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11587 12:12:58.389244 end: 4 lava-test-retry (duration 00:00:24) [common]
11588 12:12:58.389737 start: 5 finalize (timeout 00:08:01) [common]
11589 12:12:58.390186 start: 5.1 power-off (timeout 00:00:30) [common]
11590 12:12:58.390925 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11591 12:12:58.483138 >> Command sent successfully.
11592 12:12:58.485452 Returned 0 in 0 seconds
11593 12:12:58.585873 end: 5.1 power-off (duration 00:00:00) [common]
11595 12:12:58.586284 start: 5.2 read-feedback (timeout 00:08:01) [common]
11597 12:12:58.586843 Listened to connection for namespace 'common' for up to 1s
11598 12:12:59.587598 Finalising connection for namespace 'common'
11599 12:12:59.588223 Disconnecting from shell: Finalise
11600 12:12:59.588607 / #
11601 12:12:59.689528 end: 5.2 read-feedback (duration 00:00:01) [common]
11602 12:12:59.690171 end: 5 finalize (duration 00:00:01) [common]
11603 12:12:59.690726 Cleaning after the job
11604 12:12:59.691219 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/ramdisk
11605 12:12:59.702029 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/kernel
11606 12:12:59.720917 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/dtb
11607 12:12:59.721298 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605438/tftp-deploy-xxtps5kp/modules
11608 12:12:59.730622 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605438
11609 12:12:59.771979 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605438
11610 12:12:59.772146 Job finished correctly