Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 44
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 12:10:16.837127 lava-dispatcher, installed at version: 2023.05.1
2 12:10:16.837364 start: 0 validate
3 12:10:16.837497 Start time: 2023-06-06 12:10:16.837490+00:00 (UTC)
4 12:10:16.837637 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:10:16.837792 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 12:10:17.128941 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:10:17.129142 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:10:47.128850 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:10:47.129022 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:10:47.422664 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:10:47.422848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:10:48.008265 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:10:48.008431 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1320-g1ddf4b637f785%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:10:54.513610 validate duration: 37.68
16 12:10:54.513871 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:10:54.513970 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:10:54.514060 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:10:54.514179 Not decompressing ramdisk as can be used compressed.
20 12:10:54.514262 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 12:10:54.514328 saving as /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/ramdisk/initrd.cpio.gz
22 12:10:54.514390 total size: 4665395 (4MB)
23 12:10:54.810708 progress 0% (0MB)
24 12:10:54.812300 progress 5% (0MB)
25 12:10:54.813594 progress 10% (0MB)
26 12:10:54.814908 progress 15% (0MB)
27 12:10:54.816217 progress 20% (0MB)
28 12:10:54.817435 progress 25% (1MB)
29 12:10:54.818644 progress 30% (1MB)
30 12:10:54.819850 progress 35% (1MB)
31 12:10:54.821095 progress 40% (1MB)
32 12:10:54.822587 progress 45% (2MB)
33 12:10:54.823900 progress 50% (2MB)
34 12:10:54.825207 progress 55% (2MB)
35 12:10:54.826510 progress 60% (2MB)
36 12:10:54.827809 progress 65% (2MB)
37 12:10:54.829137 progress 70% (3MB)
38 12:10:54.830433 progress 75% (3MB)
39 12:10:54.831717 progress 80% (3MB)
40 12:10:54.833175 progress 85% (3MB)
41 12:10:54.834410 progress 90% (4MB)
42 12:10:54.835699 progress 95% (4MB)
43 12:10:54.836994 progress 100% (4MB)
44 12:10:54.837153 4MB downloaded in 0.32s (13.79MB/s)
45 12:10:54.837306 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:10:54.837554 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:10:54.837644 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:10:54.837736 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:10:54.837879 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:10:54.837951 saving as /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/kernel/Image
52 12:10:54.838014 total size: 45746688 (43MB)
53 12:10:54.838075 No compression specified
54 12:10:54.839558 progress 0% (0MB)
55 12:10:54.851530 progress 5% (2MB)
56 12:10:54.863735 progress 10% (4MB)
57 12:10:54.875451 progress 15% (6MB)
58 12:10:54.887628 progress 20% (8MB)
59 12:10:54.899897 progress 25% (10MB)
60 12:10:54.912000 progress 30% (13MB)
61 12:10:54.924147 progress 35% (15MB)
62 12:10:54.936491 progress 40% (17MB)
63 12:10:54.948749 progress 45% (19MB)
64 12:10:54.961053 progress 50% (21MB)
65 12:10:54.972976 progress 55% (24MB)
66 12:10:54.985378 progress 60% (26MB)
67 12:10:54.997801 progress 65% (28MB)
68 12:10:55.010144 progress 70% (30MB)
69 12:10:55.022219 progress 75% (32MB)
70 12:10:55.034253 progress 80% (34MB)
71 12:10:55.046472 progress 85% (37MB)
72 12:10:55.058499 progress 90% (39MB)
73 12:10:55.070379 progress 95% (41MB)
74 12:10:55.081791 progress 100% (43MB)
75 12:10:55.081969 43MB downloaded in 0.24s (178.84MB/s)
76 12:10:55.082126 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:10:55.082371 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:10:55.082462 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:10:55.082554 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:10:55.082688 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:10:55.082760 saving as /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/dtb/mt8192-asurada-spherion-r0.dtb
83 12:10:55.082824 total size: 46924 (0MB)
84 12:10:55.082884 No compression specified
85 12:10:55.083990 progress 69% (0MB)
86 12:10:55.084278 progress 100% (0MB)
87 12:10:55.084435 0MB downloaded in 0.00s (27.81MB/s)
88 12:10:55.084557 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:10:55.084786 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:10:55.084874 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:10:55.084958 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:10:55.085073 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 12:10:55.085142 saving as /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/nfsrootfs/full.rootfs.tar
95 12:10:55.085204 total size: 125267308 (119MB)
96 12:10:55.085265 Using unxz to decompress xz
97 12:10:55.088724 progress 0% (0MB)
98 12:10:55.423706 progress 5% (6MB)
99 12:10:55.757320 progress 10% (11MB)
100 12:10:56.090445 progress 15% (17MB)
101 12:10:56.278904 progress 20% (23MB)
102 12:10:56.462456 progress 25% (29MB)
103 12:10:56.832189 progress 30% (35MB)
104 12:10:57.202758 progress 35% (41MB)
105 12:10:57.600379 progress 40% (47MB)
106 12:10:57.989971 progress 45% (53MB)
107 12:10:58.381178 progress 50% (59MB)
108 12:10:58.743180 progress 55% (65MB)
109 12:10:59.111524 progress 60% (71MB)
110 12:10:59.465312 progress 65% (77MB)
111 12:10:59.844598 progress 70% (83MB)
112 12:11:00.253193 progress 75% (89MB)
113 12:11:00.693563 progress 80% (95MB)
114 12:11:01.141361 progress 85% (101MB)
115 12:11:01.396736 progress 90% (107MB)
116 12:11:01.751945 progress 95% (113MB)
117 12:11:02.132304 progress 100% (119MB)
118 12:11:02.138692 119MB downloaded in 7.05s (16.94MB/s)
119 12:11:02.139041 end: 1.4.1 http-download (duration 00:00:07) [common]
121 12:11:02.139318 end: 1.4 download-retry (duration 00:00:07) [common]
122 12:11:02.139414 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:11:02.139504 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:11:02.139650 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1320-g1ddf4b637f785/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:11:02.139725 saving as /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/modules/modules.tar
126 12:11:02.139789 total size: 8553528 (8MB)
127 12:11:02.139854 Using unxz to decompress xz
128 12:11:02.437846 progress 0% (0MB)
129 12:11:02.461313 progress 5% (0MB)
130 12:11:02.486925 progress 10% (0MB)
131 12:11:02.519630 progress 15% (1MB)
132 12:11:02.546662 progress 20% (1MB)
133 12:11:02.573099 progress 25% (2MB)
134 12:11:02.599232 progress 30% (2MB)
135 12:11:02.626764 progress 35% (2MB)
136 12:11:02.653120 progress 40% (3MB)
137 12:11:02.679756 progress 45% (3MB)
138 12:11:02.705923 progress 50% (4MB)
139 12:11:02.731785 progress 55% (4MB)
140 12:11:02.756298 progress 60% (4MB)
141 12:11:02.782851 progress 65% (5MB)
142 12:11:02.809801 progress 70% (5MB)
143 12:11:02.835567 progress 75% (6MB)
144 12:11:02.862835 progress 80% (6MB)
145 12:11:02.888535 progress 85% (6MB)
146 12:11:02.914351 progress 90% (7MB)
147 12:11:02.938792 progress 95% (7MB)
148 12:11:02.965896 progress 100% (8MB)
149 12:11:02.970742 8MB downloaded in 0.83s (9.82MB/s)
150 12:11:02.971063 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:11:02.971343 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:11:02.971441 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 12:11:02.971538 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 12:11:05.068382 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae
156 12:11:05.068587 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:11:05.068696 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 12:11:05.068868 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130
159 12:11:05.069005 makedir: /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin
160 12:11:05.069115 makedir: /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/tests
161 12:11:05.069219 makedir: /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/results
162 12:11:05.069324 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-add-keys
163 12:11:05.069475 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-add-sources
164 12:11:05.069600 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-background-process-start
165 12:11:05.069725 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-background-process-stop
166 12:11:05.069849 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-common-functions
167 12:11:05.069979 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-echo-ipv4
168 12:11:05.070104 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-install-packages
169 12:11:05.070225 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-installed-packages
170 12:11:05.070347 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-os-build
171 12:11:05.070478 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-probe-channel
172 12:11:05.070601 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-probe-ip
173 12:11:05.070727 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-target-ip
174 12:11:05.070854 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-target-mac
175 12:11:05.070975 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-target-storage
176 12:11:05.071098 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-case
177 12:11:05.071223 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-event
178 12:11:05.071345 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-feedback
179 12:11:05.071466 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-raise
180 12:11:05.071587 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-reference
181 12:11:05.071709 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-runner
182 12:11:05.071854 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-set
183 12:11:05.072010 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-test-shell
184 12:11:05.072156 Updating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-install-packages (oe)
185 12:11:05.072321 Updating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/bin/lava-installed-packages (oe)
186 12:11:05.072443 Creating /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/environment
187 12:11:05.072548 LAVA metadata
188 12:11:05.072620 - LAVA_JOB_ID=10605430
189 12:11:05.072684 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:11:05.072804 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 12:11:05.072874 skipped lava-vland-overlay
192 12:11:05.072952 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:11:05.073033 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 12:11:05.073097 skipped lava-multinode-overlay
195 12:11:05.073171 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:11:05.073251 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 12:11:05.073331 Loading test definitions
198 12:11:05.073427 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 12:11:05.073502 Using /lava-10605430 at stage 0
200 12:11:05.073807 uuid=10605430_1.6.2.3.1 testdef=None
201 12:11:05.073898 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:11:05.074019 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 12:11:05.074756 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:11:05.075122 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 12:11:05.075770 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:11:05.076299 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 12:11:05.077030 runner path: /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/0/tests/0_dmesg test_uuid 10605430_1.6.2.3.1
210 12:11:05.077229 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:11:05.077605 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 12:11:05.077711 Using /lava-10605430 at stage 1
214 12:11:05.078153 uuid=10605430_1.6.2.3.5 testdef=None
215 12:11:05.078274 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 12:11:05.078394 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 12:11:05.078883 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 12:11:05.079245 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 12:11:05.080152 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 12:11:05.080505 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 12:11:05.081453 runner path: /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/1/tests/1_bootrr test_uuid 10605430_1.6.2.3.5
224 12:11:05.081645 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 12:11:05.081995 Creating lava-test-runner.conf files
227 12:11:05.082091 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/0 for stage 0
228 12:11:05.082215 - 0_dmesg
229 12:11:05.082328 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10605430/lava-overlay-rlph8130/lava-10605430/1 for stage 1
230 12:11:05.082451 - 1_bootrr
231 12:11:05.082583 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 12:11:05.082704 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 12:11:05.091142 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 12:11:05.091316 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 12:11:05.091442 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 12:11:05.091568 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 12:11:05.091687 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 12:11:05.213137 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 12:11:05.213518 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 12:11:05.213661 extracting modules file /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae
241 12:11:05.428142 extracting modules file /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10605430/extract-overlay-ramdisk-1_1cmyf8/ramdisk
242 12:11:05.672096 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 12:11:05.672292 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 12:11:05.672402 [common] Applying overlay to NFS
245 12:11:05.672477 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10605430/compress-overlay-8i4epza8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae
246 12:11:05.680347 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 12:11:05.680497 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 12:11:05.680597 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 12:11:05.680692 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 12:11:05.680781 Building ramdisk /var/lib/lava/dispatcher/tmp/10605430/extract-overlay-ramdisk-1_1cmyf8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10605430/extract-overlay-ramdisk-1_1cmyf8/ramdisk
251 12:11:05.957148 >> 117807 blocks
252 12:11:07.899677 rename /var/lib/lava/dispatcher/tmp/10605430/extract-overlay-ramdisk-1_1cmyf8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/ramdisk/ramdisk.cpio.gz
253 12:11:07.900154 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 12:11:07.900285 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 12:11:07.900393 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 12:11:07.900505 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/kernel/Image'
257 12:11:20.438805 Returned 0 in 12 seconds
258 12:11:20.539467 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/kernel/image.itb
259 12:11:20.850970 output: FIT description: Kernel Image image with one or more FDT blobs
260 12:11:20.851371 output: Created: Tue Jun 6 13:11:20 2023
261 12:11:20.851500 output: Image 0 (kernel-1)
262 12:11:20.851610 output: Description:
263 12:11:20.851709 output: Created: Tue Jun 6 13:11:20 2023
264 12:11:20.851818 output: Type: Kernel Image
265 12:11:20.851915 output: Compression: lzma compressed
266 12:11:20.852015 output: Data Size: 10094623 Bytes = 9858.03 KiB = 9.63 MiB
267 12:11:20.852097 output: Architecture: AArch64
268 12:11:20.852160 output: OS: Linux
269 12:11:20.852245 output: Load Address: 0x00000000
270 12:11:20.852323 output: Entry Point: 0x00000000
271 12:11:20.852392 output: Hash algo: crc32
272 12:11:20.852457 output: Hash value: fd97082e
273 12:11:20.852535 output: Image 1 (fdt-1)
274 12:11:20.852632 output: Description: mt8192-asurada-spherion-r0
275 12:11:20.852724 output: Created: Tue Jun 6 13:11:20 2023
276 12:11:20.852813 output: Type: Flat Device Tree
277 12:11:20.852899 output: Compression: uncompressed
278 12:11:20.852995 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 12:11:20.853090 output: Architecture: AArch64
280 12:11:20.853178 output: Hash algo: crc32
281 12:11:20.853273 output: Hash value: 1df858fa
282 12:11:20.853371 output: Image 2 (ramdisk-1)
283 12:11:20.853460 output: Description: unavailable
284 12:11:20.853546 output: Created: Tue Jun 6 13:11:20 2023
285 12:11:20.853642 output: Type: RAMDisk Image
286 12:11:20.853738 output: Compression: Unknown Compression
287 12:11:20.853834 output: Data Size: 17636166 Bytes = 17222.82 KiB = 16.82 MiB
288 12:11:20.853921 output: Architecture: AArch64
289 12:11:20.854007 output: OS: Linux
290 12:11:20.854097 output: Load Address: unavailable
291 12:11:20.854198 output: Entry Point: unavailable
292 12:11:20.854285 output: Hash algo: crc32
293 12:11:20.854380 output: Hash value: 370ff61b
294 12:11:20.854466 output: Default Configuration: 'conf-1'
295 12:11:20.854555 output: Configuration 0 (conf-1)
296 12:11:20.854647 output: Description: mt8192-asurada-spherion-r0
297 12:11:20.854743 output: Kernel: kernel-1
298 12:11:20.854830 output: Init Ramdisk: ramdisk-1
299 12:11:20.854915 output: FDT: fdt-1
300 12:11:20.855001 output: Loadables: kernel-1
301 12:11:20.855087 output:
302 12:11:20.855294 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 12:11:20.855396 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 12:11:20.855500 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 12:11:20.855594 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 12:11:20.855678 No LXC device requested
307 12:11:20.855780 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 12:11:20.855906 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 12:11:20.856029 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 12:11:20.856137 Checking files for TFTP limit of 4294967296 bytes.
311 12:11:20.856821 end: 1 tftp-deploy (duration 00:00:26) [common]
312 12:11:20.856970 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 12:11:20.857102 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 12:11:20.857278 substitutions:
315 12:11:20.857378 - {DTB}: 10605430/tftp-deploy-ez8uklv8/dtb/mt8192-asurada-spherion-r0.dtb
316 12:11:20.857474 - {INITRD}: 10605430/tftp-deploy-ez8uklv8/ramdisk/ramdisk.cpio.gz
317 12:11:20.857571 - {KERNEL}: 10605430/tftp-deploy-ez8uklv8/kernel/Image
318 12:11:20.857669 - {LAVA_MAC}: None
319 12:11:20.857760 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae
320 12:11:20.857860 - {NFS_SERVER_IP}: 192.168.201.1
321 12:11:20.857959 - {PRESEED_CONFIG}: None
322 12:11:20.858041 - {PRESEED_LOCAL}: None
323 12:11:20.858103 - {RAMDISK}: 10605430/tftp-deploy-ez8uklv8/ramdisk/ramdisk.cpio.gz
324 12:11:20.858196 - {ROOT_PART}: None
325 12:11:20.858260 - {ROOT}: None
326 12:11:20.858319 - {SERVER_IP}: 192.168.201.1
327 12:11:20.858377 - {TEE}: None
328 12:11:20.858436 Parsed boot commands:
329 12:11:20.858493 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 12:11:20.858708 Parsed boot commands: tftpboot 192.168.201.1 10605430/tftp-deploy-ez8uklv8/kernel/image.itb 10605430/tftp-deploy-ez8uklv8/kernel/cmdline
331 12:11:20.858831 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 12:11:20.858951 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 12:11:20.859087 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 12:11:20.859211 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 12:11:20.859312 Not connected, no need to disconnect.
336 12:11:20.859424 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 12:11:20.859541 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 12:11:20.859643 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
339 12:11:20.863013 Setting prompt string to ['lava-test: # ']
340 12:11:20.863394 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 12:11:20.863537 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 12:11:20.863672 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 12:11:20.863806 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 12:11:20.864088 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
345 12:11:25.997445 >> Command sent successfully.
346 12:11:26.000076 Returned 0 in 5 seconds
347 12:11:26.100507 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 12:11:26.100903 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 12:11:26.101015 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 12:11:26.101136 Setting prompt string to 'Starting depthcharge on Spherion...'
352 12:11:26.101211 Changing prompt to 'Starting depthcharge on Spherion...'
353 12:11:26.101297 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 12:11:26.101681 [Enter `^Ec?' for help]
355 12:11:26.274488
356 12:11:26.274676
357 12:11:26.274788 F0: 102B 0000
358 12:11:26.274884
359 12:11:26.274978 F3: 1001 0000 [0200]
360 12:11:26.275074
361 12:11:26.278312 F3: 1001 0000
362 12:11:26.278435
363 12:11:26.278532 F7: 102D 0000
364 12:11:26.278627
365 12:11:26.278721 F1: 0000 0000
366 12:11:26.278813
367 12:11:26.281573 V0: 0000 0000 [0001]
368 12:11:26.281686
369 12:11:26.281784 00: 0007 8000
370 12:11:26.281887
371 12:11:26.285435 01: 0000 0000
372 12:11:26.285561
373 12:11:26.285659 BP: 0C00 0209 [0000]
374 12:11:26.285757
375 12:11:26.288766 G0: 1182 0000
376 12:11:26.288882
377 12:11:26.288982 EC: 0000 0021 [4000]
378 12:11:26.289081
379 12:11:26.292154 S7: 0000 0000 [0000]
380 12:11:26.292246
381 12:11:26.292314 CC: 0000 0000 [0001]
382 12:11:26.292383
383 12:11:26.295307 T0: 0000 0040 [010F]
384 12:11:26.295387
385 12:11:26.295489 Jump to BL
386 12:11:26.295582
387 12:11:26.321339
388 12:11:26.321526
389 12:11:26.321637
390 12:11:26.329132 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 12:11:26.332324 ARM64: Exception handlers installed.
392 12:11:26.336003 ARM64: Testing exception
393 12:11:26.339609 ARM64: Done test exception
394 12:11:26.347344 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 12:11:26.353700 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 12:11:26.364257 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 12:11:26.373967 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 12:11:26.380274 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 12:11:26.387405 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 12:11:26.397370 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 12:11:26.404189 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 12:11:26.423983 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 12:11:26.426977 WDT: Last reset was cold boot
404 12:11:26.430245 SPI1(PAD0) initialized at 2873684 Hz
405 12:11:26.433441 SPI5(PAD0) initialized at 992727 Hz
406 12:11:26.437181 VBOOT: Loading verstage.
407 12:11:26.443829 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 12:11:26.446495 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 12:11:26.450246 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 12:11:26.453378 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 12:11:26.461576 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 12:11:26.467743 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 12:11:26.479077 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 12:11:26.479247
415 12:11:26.479355
416 12:11:26.488745 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 12:11:26.491931 ARM64: Exception handlers installed.
418 12:11:26.495194 ARM64: Testing exception
419 12:11:26.498902 ARM64: Done test exception
420 12:11:26.502596 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 12:11:26.505641 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:11:26.519951 Probing TPM: . done!
423 12:11:26.520117 TPM ready after 0 ms
424 12:11:26.526557 Connected to device vid:did:rid of 1ae0:0028:00
425 12:11:26.533645 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
426 12:11:26.592152 Initialized TPM device CR50 revision 0
427 12:11:26.603571 tlcl_send_startup: Startup return code is 0
428 12:11:26.603789 TPM: setup succeeded
429 12:11:26.616014 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 12:11:26.624477 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 12:11:26.637241 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 12:11:26.645047 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 12:11:26.648098 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 12:11:26.654411 in-header: 03 07 00 00 08 00 00 00
435 12:11:26.658292 in-data: aa e4 47 04 13 02 00 00
436 12:11:26.661948 Chrome EC: UHEPI supported
437 12:11:26.669016 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 12:11:26.672868 in-header: 03 95 00 00 08 00 00 00
439 12:11:26.676055 in-data: 18 20 20 08 00 00 00 00
440 12:11:26.676177 Phase 1
441 12:11:26.680350 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 12:11:26.687681 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 12:11:26.691009 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 12:11:26.695075 Recovery requested (1009000e)
445 12:11:26.702617 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 12:11:26.708242 tlcl_extend: response is 0
447 12:11:26.717651 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 12:11:26.723506 tlcl_extend: response is 0
449 12:11:26.730651 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 12:11:26.749994 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 12:11:26.756797 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 12:11:26.756951
453 12:11:26.757031
454 12:11:26.766978 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 12:11:26.770136 ARM64: Exception handlers installed.
456 12:11:26.773326 ARM64: Testing exception
457 12:11:26.773464 ARM64: Done test exception
458 12:11:26.796024 pmic_efuse_setting: Set efuses in 11 msecs
459 12:11:26.799269 pmwrap_interface_init: Select PMIF_VLD_RDY
460 12:11:26.805626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 12:11:26.808739 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 12:11:26.815692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 12:11:26.819570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 12:11:26.823446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 12:11:26.830954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 12:11:26.835054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 12:11:26.838264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 12:11:26.842418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 12:11:26.849435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 12:11:26.853079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 12:11:26.856697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 12:11:26.860449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 12:11:26.868021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 12:11:26.875748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 12:11:26.878910 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 12:11:26.886369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 12:11:26.890342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 12:11:26.897926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 12:11:26.901752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 12:11:26.908748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 12:11:26.912506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 12:11:26.919985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 12:11:26.923919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 12:11:26.930941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 12:11:26.934831 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 12:11:26.938536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 12:11:26.945685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 12:11:26.949798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 12:11:26.953472 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 12:11:26.960541 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 12:11:26.964278 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 12:11:26.971447 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 12:11:26.975192 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 12:11:26.979061 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 12:11:26.986068 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 12:11:26.989843 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 12:11:26.993547 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 12:11:26.997434 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 12:11:27.005020 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 12:11:27.008244 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 12:11:27.012152 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 12:11:27.015966 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 12:11:27.019141 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 12:11:27.026676 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 12:11:27.030532 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 12:11:27.034314 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 12:11:27.037603 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 12:11:27.041497 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 12:11:27.045249 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 12:11:27.052689 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 12:11:27.060324 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 12:11:27.067049 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 12:11:27.070686 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 12:11:27.078185 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 12:11:27.089482 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 12:11:27.093185 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 12:11:27.096995 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 12:11:27.100088 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 12:11:27.108899 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
520 12:11:27.112821 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 12:11:27.120871 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
522 12:11:27.123968 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 12:11:27.132724 [RTC]rtc_get_frequency_meter,154: input=15, output=852
524 12:11:27.142932 [RTC]rtc_get_frequency_meter,154: input=7, output=724
525 12:11:27.152277 [RTC]rtc_get_frequency_meter,154: input=11, output=789
526 12:11:27.161337 [RTC]rtc_get_frequency_meter,154: input=13, output=821
527 12:11:27.171503 [RTC]rtc_get_frequency_meter,154: input=12, output=804
528 12:11:27.180936 [RTC]rtc_get_frequency_meter,154: input=11, output=789
529 12:11:27.190471 [RTC]rtc_get_frequency_meter,154: input=12, output=803
530 12:11:27.194875 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
531 12:11:27.197987 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
532 12:11:27.202156 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 12:11:27.209042 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 12:11:27.212921 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 12:11:27.216290 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 12:11:27.220146 ADC[4]: Raw value=903694 ID=7
537 12:11:27.220247 ADC[3]: Raw value=213546 ID=1
538 12:11:27.224027 RAM Code: 0x71
539 12:11:27.227888 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 12:11:27.231153 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 12:11:27.242681 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 12:11:27.246405 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 12:11:27.249666 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 12:11:27.253441 in-header: 03 07 00 00 08 00 00 00
545 12:11:27.257111 in-data: aa e4 47 04 13 02 00 00
546 12:11:27.261058 Chrome EC: UHEPI supported
547 12:11:27.268467 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 12:11:27.272076 in-header: 03 95 00 00 08 00 00 00
549 12:11:27.272195 in-data: 18 20 20 08 00 00 00 00
550 12:11:27.275707 MRC: failed to locate region type 0.
551 12:11:27.283171 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 12:11:27.287244 DRAM-K: Running full calibration
553 12:11:27.294088 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:11:27.294240 header.status = 0x0
555 12:11:27.297589 header.version = 0x6 (expected: 0x6)
556 12:11:27.301379 header.size = 0xd00 (expected: 0xd00)
557 12:11:27.301510 header.flags = 0x0
558 12:11:27.308209 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 12:11:27.327463 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 12:11:27.334614 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 12:11:27.338224 dram_init: ddr_geometry: 2
562 12:11:27.338366 [EMI] MDL number = 2
563 12:11:27.342130 [EMI] Get MDL freq = 0
564 12:11:27.342252 dram_init: ddr_type: 0
565 12:11:27.345885 is_discrete_lpddr4: 1
566 12:11:27.349926 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 12:11:27.350067
568 12:11:27.350170
569 12:11:27.350264 [Bian_co] ETT version 0.0.0.1
570 12:11:27.356896 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 12:11:27.357050
572 12:11:27.360235 dramc_set_vcore_voltage set vcore to 650000
573 12:11:27.360336 Read voltage for 800, 4
574 12:11:27.363385 Vio18 = 0
575 12:11:27.363483 Vcore = 650000
576 12:11:27.363582 Vdram = 0
577 12:11:27.367143 Vddq = 0
578 12:11:27.367278 Vmddr = 0
579 12:11:27.370236 dram_init: config_dvfs: 1
580 12:11:27.373819 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 12:11:27.381101 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 12:11:27.384589 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
583 12:11:27.388365 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
584 12:11:27.391915 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
585 12:11:27.395054 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
586 12:11:27.398763 MEM_TYPE=3, freq_sel=18
587 12:11:27.398911 sv_algorithm_assistance_LP4_1600
588 12:11:27.405456 ============ PULL DRAM RESETB DOWN ============
589 12:11:27.408198 ========== PULL DRAM RESETB DOWN end =========
590 12:11:27.412360 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 12:11:27.415718 ===================================
592 12:11:27.419661 LPDDR4 DRAM CONFIGURATION
593 12:11:27.422802 ===================================
594 12:11:27.422914 EX_ROW_EN[0] = 0x0
595 12:11:27.426590 EX_ROW_EN[1] = 0x0
596 12:11:27.426720 LP4Y_EN = 0x0
597 12:11:27.429837 WORK_FSP = 0x0
598 12:11:27.429956 WL = 0x2
599 12:11:27.433030 RL = 0x2
600 12:11:27.433143 BL = 0x2
601 12:11:27.436261 RPST = 0x0
602 12:11:27.436350 RD_PRE = 0x0
603 12:11:27.439896 WR_PRE = 0x1
604 12:11:27.440017 WR_PST = 0x0
605 12:11:27.443058 DBI_WR = 0x0
606 12:11:27.446318 DBI_RD = 0x0
607 12:11:27.446438 OTF = 0x1
608 12:11:27.449475 ===================================
609 12:11:27.453174 ===================================
610 12:11:27.453267 ANA top config
611 12:11:27.456366 ===================================
612 12:11:27.459567 DLL_ASYNC_EN = 0
613 12:11:27.462853 ALL_SLAVE_EN = 1
614 12:11:27.466057 NEW_RANK_MODE = 1
615 12:11:27.466190 DLL_IDLE_MODE = 1
616 12:11:27.469247 LP45_APHY_COMB_EN = 1
617 12:11:27.473040 TX_ODT_DIS = 1
618 12:11:27.476148 NEW_8X_MODE = 1
619 12:11:27.479669 ===================================
620 12:11:27.482827 ===================================
621 12:11:27.485881 data_rate = 1600
622 12:11:27.489390 CKR = 1
623 12:11:27.489522 DQ_P2S_RATIO = 8
624 12:11:27.493000 ===================================
625 12:11:27.495901 CA_P2S_RATIO = 8
626 12:11:27.499611 DQ_CA_OPEN = 0
627 12:11:27.503280 DQ_SEMI_OPEN = 0
628 12:11:27.503416 CA_SEMI_OPEN = 0
629 12:11:27.506951 CA_FULL_RATE = 0
630 12:11:27.510126 DQ_CKDIV4_EN = 1
631 12:11:27.513609 CA_CKDIV4_EN = 1
632 12:11:27.516516 CA_PREDIV_EN = 0
633 12:11:27.520102 PH8_DLY = 0
634 12:11:27.520233 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 12:11:27.523271 DQ_AAMCK_DIV = 4
636 12:11:27.526535 CA_AAMCK_DIV = 4
637 12:11:27.530411 CA_ADMCK_DIV = 4
638 12:11:27.533621 DQ_TRACK_CA_EN = 0
639 12:11:27.536837 CA_PICK = 800
640 12:11:27.540005 CA_MCKIO = 800
641 12:11:27.540134 MCKIO_SEMI = 0
642 12:11:27.543765 PLL_FREQ = 3068
643 12:11:27.547610 DQ_UI_PI_RATIO = 32
644 12:11:27.550807 CA_UI_PI_RATIO = 0
645 12:11:27.554676 ===================================
646 12:11:27.554816 ===================================
647 12:11:27.558388 memory_type:LPDDR4
648 12:11:27.562202 GP_NUM : 10
649 12:11:27.562335 SRAM_EN : 1
650 12:11:27.565926 MD32_EN : 0
651 12:11:27.569983 ===================================
652 12:11:27.570125 [ANA_INIT] >>>>>>>>>>>>>>
653 12:11:27.573228 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 12:11:27.577084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 12:11:27.580249 ===================================
656 12:11:27.583308 data_rate = 1600,PCW = 0X7600
657 12:11:27.586887 ===================================
658 12:11:27.590518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 12:11:27.593458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 12:11:27.600621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 12:11:27.603576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 12:11:27.610173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 12:11:27.613781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 12:11:27.613925 [ANA_INIT] flow start
665 12:11:27.616917 [ANA_INIT] PLL >>>>>>>>
666 12:11:27.620401 [ANA_INIT] PLL <<<<<<<<
667 12:11:27.620528 [ANA_INIT] MIDPI >>>>>>>>
668 12:11:27.623700 [ANA_INIT] MIDPI <<<<<<<<
669 12:11:27.626852 [ANA_INIT] DLL >>>>>>>>
670 12:11:27.626979 [ANA_INIT] flow end
671 12:11:27.629983 ============ LP4 DIFF to SE enter ============
672 12:11:27.636751 ============ LP4 DIFF to SE exit ============
673 12:11:27.636900 [ANA_INIT] <<<<<<<<<<<<<
674 12:11:27.639950 [Flow] Enable top DCM control >>>>>
675 12:11:27.643066 [Flow] Enable top DCM control <<<<<
676 12:11:27.646948 Enable DLL master slave shuffle
677 12:11:27.653741 ==============================================================
678 12:11:27.653895 Gating Mode config
679 12:11:27.660114 ==============================================================
680 12:11:27.663319 Config description:
681 12:11:27.673101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 12:11:27.680082 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 12:11:27.683192 SELPH_MODE 0: By rank 1: By Phase
684 12:11:27.689978 ==============================================================
685 12:11:27.693078 GAT_TRACK_EN = 1
686 12:11:27.696575 RX_GATING_MODE = 2
687 12:11:27.696710 RX_GATING_TRACK_MODE = 2
688 12:11:27.700114 SELPH_MODE = 1
689 12:11:27.703122 PICG_EARLY_EN = 1
690 12:11:27.706530 VALID_LAT_VALUE = 1
691 12:11:27.713304 ==============================================================
692 12:11:27.716284 Enter into Gating configuration >>>>
693 12:11:27.719435 Exit from Gating configuration <<<<
694 12:11:27.723151 Enter into DVFS_PRE_config >>>>>
695 12:11:27.732476 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 12:11:27.735720 Exit from DVFS_PRE_config <<<<<
697 12:11:27.739024 Enter into PICG configuration >>>>
698 12:11:27.742819 Exit from PICG configuration <<<<
699 12:11:27.745939 [RX_INPUT] configuration >>>>>
700 12:11:27.749115 [RX_INPUT] configuration <<<<<
701 12:11:27.752348 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 12:11:27.759309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 12:11:27.765733 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 12:11:27.772103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 12:11:27.779241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 12:11:27.782470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 12:11:27.788698 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 12:11:27.791912 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 12:11:27.795664 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 12:11:27.798877 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 12:11:27.805218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 12:11:27.808776 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 12:11:27.812236 ===================================
714 12:11:27.815273 LPDDR4 DRAM CONFIGURATION
715 12:11:27.818781 ===================================
716 12:11:27.818913 EX_ROW_EN[0] = 0x0
717 12:11:27.822228 EX_ROW_EN[1] = 0x0
718 12:11:27.822350 LP4Y_EN = 0x0
719 12:11:27.825182 WORK_FSP = 0x0
720 12:11:27.825304 WL = 0x2
721 12:11:27.828794 RL = 0x2
722 12:11:27.828918 BL = 0x2
723 12:11:27.831798 RPST = 0x0
724 12:11:27.831917 RD_PRE = 0x0
725 12:11:27.835399 WR_PRE = 0x1
726 12:11:27.835521 WR_PST = 0x0
727 12:11:27.838764 DBI_WR = 0x0
728 12:11:27.842226 DBI_RD = 0x0
729 12:11:27.842355 OTF = 0x1
730 12:11:27.845294 ===================================
731 12:11:27.849160 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 12:11:27.852366 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 12:11:27.858730 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 12:11:27.861911 ===================================
735 12:11:27.865156 LPDDR4 DRAM CONFIGURATION
736 12:11:27.868946 ===================================
737 12:11:27.869080 EX_ROW_EN[0] = 0x10
738 12:11:27.872158 EX_ROW_EN[1] = 0x0
739 12:11:27.872306 LP4Y_EN = 0x0
740 12:11:27.875361 WORK_FSP = 0x0
741 12:11:27.875488 WL = 0x2
742 12:11:27.878464 RL = 0x2
743 12:11:27.878582 BL = 0x2
744 12:11:27.881686 RPST = 0x0
745 12:11:27.881841 RD_PRE = 0x0
746 12:11:27.885527 WR_PRE = 0x1
747 12:11:27.885643 WR_PST = 0x0
748 12:11:27.888571 DBI_WR = 0x0
749 12:11:27.888686 DBI_RD = 0x0
750 12:11:27.891724 OTF = 0x1
751 12:11:27.895643 ===================================
752 12:11:27.901792 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 12:11:27.904929 nWR fixed to 40
754 12:11:27.908789 [ModeRegInit_LP4] CH0 RK0
755 12:11:27.908926 [ModeRegInit_LP4] CH0 RK1
756 12:11:27.911868 [ModeRegInit_LP4] CH1 RK0
757 12:11:27.915501 [ModeRegInit_LP4] CH1 RK1
758 12:11:27.915625 match AC timing 13
759 12:11:27.921761 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 12:11:27.924737 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 12:11:27.928295 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 12:11:27.934929 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 12:11:27.938075 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 12:11:27.941667 [EMI DOE] emi_dcm 0
765 12:11:27.944565 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 12:11:27.944697 ==
767 12:11:27.947976 Dram Type= 6, Freq= 0, CH_0, rank 0
768 12:11:27.951339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 12:11:27.951469 ==
770 12:11:27.958099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 12:11:27.964440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 12:11:27.972780 [CA 0] Center 37 (7~68) winsize 62
773 12:11:27.975981 [CA 1] Center 37 (6~68) winsize 63
774 12:11:27.979231 [CA 2] Center 35 (5~65) winsize 61
775 12:11:27.982444 [CA 3] Center 35 (4~66) winsize 63
776 12:11:27.985687 [CA 4] Center 33 (3~64) winsize 62
777 12:11:27.988776 [CA 5] Center 33 (3~64) winsize 62
778 12:11:27.988901
779 12:11:27.992475 [CmdBusTrainingLP45] Vref(ca) range 1: 32
780 12:11:27.992599
781 12:11:27.995599 [CATrainingPosCal] consider 1 rank data
782 12:11:27.998741 u2DelayCellTimex100 = 270/100 ps
783 12:11:28.002020 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 12:11:28.008521 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 12:11:28.012222 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
786 12:11:28.015403 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
787 12:11:28.018478 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 12:11:28.022205 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
789 12:11:28.022339
790 12:11:28.025220 CA PerBit enable=1, Macro0, CA PI delay=33
791 12:11:28.025339
792 12:11:28.028820 [CBTSetCACLKResult] CA Dly = 33
793 12:11:28.032227 CS Dly: 5 (0~36)
794 12:11:28.032365 ==
795 12:11:28.035571 Dram Type= 6, Freq= 0, CH_0, rank 1
796 12:11:28.038579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 12:11:28.038711 ==
798 12:11:28.045556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 12:11:28.048488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 12:11:28.059089 [CA 0] Center 38 (7~69) winsize 63
801 12:11:28.062312 [CA 1] Center 37 (7~68) winsize 62
802 12:11:28.065390 [CA 2] Center 35 (4~66) winsize 63
803 12:11:28.069198 [CA 3] Center 35 (4~66) winsize 63
804 12:11:28.072387 [CA 4] Center 34 (3~65) winsize 63
805 12:11:28.075643 [CA 5] Center 33 (3~64) winsize 62
806 12:11:28.075769
807 12:11:28.078866 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 12:11:28.078986
809 12:11:28.082078 [CATrainingPosCal] consider 2 rank data
810 12:11:28.085248 u2DelayCellTimex100 = 270/100 ps
811 12:11:28.089109 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 12:11:28.095532 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
813 12:11:28.098702 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
814 12:11:28.101926 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
815 12:11:28.105820 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 12:11:28.108984 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
817 12:11:28.109115
818 12:11:28.112046 CA PerBit enable=1, Macro0, CA PI delay=33
819 12:11:28.112163
820 12:11:28.115351 [CBTSetCACLKResult] CA Dly = 33
821 12:11:28.115468 CS Dly: 6 (0~38)
822 12:11:28.119021
823 12:11:28.122697 ----->DramcWriteLeveling(PI) begin...
824 12:11:28.122832 ==
825 12:11:28.125854 Dram Type= 6, Freq= 0, CH_0, rank 0
826 12:11:28.129763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 12:11:28.129894 ==
828 12:11:28.132818 Write leveling (Byte 0): 29 => 29
829 12:11:28.132943 Write leveling (Byte 1): 28 => 28
830 12:11:28.137056 DramcWriteLeveling(PI) end<-----
831 12:11:28.137186
832 12:11:28.137289 ==
833 12:11:28.140632 Dram Type= 6, Freq= 0, CH_0, rank 0
834 12:11:28.143616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 12:11:28.147004 ==
836 12:11:28.147141 [Gating] SW mode calibration
837 12:11:28.154303 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 12:11:28.160885 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 12:11:28.163955 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 12:11:28.170817 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 12:11:28.174240 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 12:11:28.177456 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:11:28.184429 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:11:28.187615 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:11:28.190703 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:11:28.197718 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:11:28.200888 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:11:28.203920 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:11:28.207189 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 12:11:28.214093 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:11:28.217453 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:11:28.220644 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:11:28.227522 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:11:28.230771 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:11:28.234002 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:11:28.240325 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 12:11:28.243835 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:11:28.247248 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:11:28.253859 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:11:28.256817 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:11:28.260576 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:11:28.267203 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:11:28.270636 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:11:28.273751 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:11:28.280134 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
866 12:11:28.283605 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
867 12:11:28.286932 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 12:11:28.294039 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 12:11:28.297135 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 12:11:28.300227 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 12:11:28.306593 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 12:11:28.310497 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
873 12:11:28.313575 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
874 12:11:28.319970 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
875 12:11:28.323158 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:11:28.326941 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:11:28.333099 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:11:28.336883 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:11:28.340068 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 12:11:28.346241 0 11 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
881 12:11:28.349941 0 11 8 | B1->B0 | 2c2c 4040 | 0 0 | (0 0) (0 0)
882 12:11:28.353096 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
883 12:11:28.359977 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 12:11:28.363110 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 12:11:28.366558 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 12:11:28.373236 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 12:11:28.376120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 12:11:28.379994 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 12:11:28.383012 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
890 12:11:28.389444 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 12:11:28.392600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 12:11:28.395933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 12:11:28.402899 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 12:11:28.406004 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 12:11:28.409326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 12:11:28.416297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 12:11:28.419403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 12:11:28.422722 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:11:28.429162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:11:28.432859 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:11:28.435989 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:11:28.442438 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:11:28.446259 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:11:28.449321 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
905 12:11:28.455832 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
906 12:11:28.459015 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
907 12:11:28.462871 Total UI for P1: 0, mck2ui 16
908 12:11:28.466143 best dqsien dly found for B0: ( 0, 14, 6)
909 12:11:28.469575 Total UI for P1: 0, mck2ui 16
910 12:11:28.472623 best dqsien dly found for B1: ( 0, 14, 10)
911 12:11:28.476071 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
912 12:11:28.479155 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
913 12:11:28.479283
914 12:11:28.482794 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
915 12:11:28.485704 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
916 12:11:28.489164 [Gating] SW calibration Done
917 12:11:28.489290 ==
918 12:11:28.492612 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:11:28.495751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:11:28.495878 ==
921 12:11:28.499564 RX Vref Scan: 0
922 12:11:28.499691
923 12:11:28.502779 RX Vref 0 -> 0, step: 1
924 12:11:28.502902
925 12:11:28.503005 RX Delay -130 -> 252, step: 16
926 12:11:28.509858 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
927 12:11:28.513094 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
928 12:11:28.516224 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
929 12:11:28.519395 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
930 12:11:28.522517 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
931 12:11:28.529705 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
932 12:11:28.532671 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
933 12:11:28.535740 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
934 12:11:28.538889 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
935 12:11:28.545892 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
936 12:11:28.548998 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
937 12:11:28.552845 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
938 12:11:28.555953 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
939 12:11:28.558967 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
940 12:11:28.565978 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
941 12:11:28.569189 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
942 12:11:28.569327 ==
943 12:11:28.572354 Dram Type= 6, Freq= 0, CH_0, rank 0
944 12:11:28.575448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 12:11:28.575571 ==
946 12:11:28.579165 DQS Delay:
947 12:11:28.579289 DQS0 = 0, DQS1 = 0
948 12:11:28.579390 DQM Delay:
949 12:11:28.582094 DQM0 = 88, DQM1 = 76
950 12:11:28.582209 DQ Delay:
951 12:11:28.585805 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
952 12:11:28.588759 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
953 12:11:28.592309 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
954 12:11:28.595854 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
955 12:11:28.595982
956 12:11:28.596091
957 12:11:28.596188 ==
958 12:11:28.599287 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:11:28.605504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:11:28.605651 ==
961 12:11:28.605758
962 12:11:28.605854
963 12:11:28.605949 TX Vref Scan disable
964 12:11:28.609184 == TX Byte 0 ==
965 12:11:28.612400 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
966 12:11:28.618930 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
967 12:11:28.619078 == TX Byte 1 ==
968 12:11:28.622112 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
969 12:11:28.629085 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
970 12:11:28.629240 ==
971 12:11:28.632215 Dram Type= 6, Freq= 0, CH_0, rank 0
972 12:11:28.635503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 12:11:28.635625 ==
974 12:11:28.648021 TX Vref=22, minBit 0, minWin=27, winSum=438
975 12:11:28.651113 TX Vref=24, minBit 0, minWin=27, winSum=441
976 12:11:28.654394 TX Vref=26, minBit 3, minWin=27, winSum=447
977 12:11:28.658163 TX Vref=28, minBit 1, minWin=27, winSum=450
978 12:11:28.661172 TX Vref=30, minBit 1, minWin=27, winSum=452
979 12:11:28.668120 TX Vref=32, minBit 2, minWin=27, winSum=446
980 12:11:28.671376 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
981 12:11:28.671514
982 12:11:28.674406 Final TX Range 1 Vref 30
983 12:11:28.674523
984 12:11:28.674624 ==
985 12:11:28.677635 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:11:28.680796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:11:28.684364 ==
988 12:11:28.684490
989 12:11:28.684591
990 12:11:28.684687 TX Vref Scan disable
991 12:11:28.687905 == TX Byte 0 ==
992 12:11:28.691462 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
993 12:11:28.697926 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
994 12:11:28.698076 == TX Byte 1 ==
995 12:11:28.700937 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
996 12:11:28.708061 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
997 12:11:28.708230
998 12:11:28.708341 [DATLAT]
999 12:11:28.708439 Freq=800, CH0 RK0
1000 12:11:28.708534
1001 12:11:28.711044 DATLAT Default: 0xa
1002 12:11:28.711157 0, 0xFFFF, sum = 0
1003 12:11:28.714136 1, 0xFFFF, sum = 0
1004 12:11:28.717946 2, 0xFFFF, sum = 0
1005 12:11:28.718072 3, 0xFFFF, sum = 0
1006 12:11:28.721165 4, 0xFFFF, sum = 0
1007 12:11:28.721282 5, 0xFFFF, sum = 0
1008 12:11:28.724377 6, 0xFFFF, sum = 0
1009 12:11:28.724494 7, 0xFFFF, sum = 0
1010 12:11:28.727586 8, 0xFFFF, sum = 0
1011 12:11:28.727705 9, 0x0, sum = 1
1012 12:11:28.730807 10, 0x0, sum = 2
1013 12:11:28.730923 11, 0x0, sum = 3
1014 12:11:28.731025 12, 0x0, sum = 4
1015 12:11:28.734085 best_step = 10
1016 12:11:28.734198
1017 12:11:28.734297 ==
1018 12:11:28.737274 Dram Type= 6, Freq= 0, CH_0, rank 0
1019 12:11:28.740566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1020 12:11:28.740689 ==
1021 12:11:28.744203 RX Vref Scan: 1
1022 12:11:28.744318
1023 12:11:28.747240 Set Vref Range= 32 -> 127
1024 12:11:28.747354
1025 12:11:28.747459 RX Vref 32 -> 127, step: 1
1026 12:11:28.747556
1027 12:11:28.750392 RX Delay -111 -> 252, step: 8
1028 12:11:28.750507
1029 12:11:28.754181 Set Vref, RX VrefLevel [Byte0]: 32
1030 12:11:28.757319 [Byte1]: 32
1031 12:11:28.761059
1032 12:11:28.761184 Set Vref, RX VrefLevel [Byte0]: 33
1033 12:11:28.764188 [Byte1]: 33
1034 12:11:28.768575
1035 12:11:28.768717 Set Vref, RX VrefLevel [Byte0]: 34
1036 12:11:28.771631 [Byte1]: 34
1037 12:11:28.776168
1038 12:11:28.776304 Set Vref, RX VrefLevel [Byte0]: 35
1039 12:11:28.779256 [Byte1]: 35
1040 12:11:28.783725
1041 12:11:28.783863 Set Vref, RX VrefLevel [Byte0]: 36
1042 12:11:28.786944 [Byte1]: 36
1043 12:11:28.791404
1044 12:11:28.791547 Set Vref, RX VrefLevel [Byte0]: 37
1045 12:11:28.794586 [Byte1]: 37
1046 12:11:28.798805
1047 12:11:28.798944 Set Vref, RX VrefLevel [Byte0]: 38
1048 12:11:28.802474 [Byte1]: 38
1049 12:11:28.806750
1050 12:11:28.806888 Set Vref, RX VrefLevel [Byte0]: 39
1051 12:11:28.810157 [Byte1]: 39
1052 12:11:28.814336
1053 12:11:28.814478 Set Vref, RX VrefLevel [Byte0]: 40
1054 12:11:28.818133 [Byte1]: 40
1055 12:11:28.822602
1056 12:11:28.822743 Set Vref, RX VrefLevel [Byte0]: 41
1057 12:11:28.825699 [Byte1]: 41
1058 12:11:28.829565
1059 12:11:28.829700 Set Vref, RX VrefLevel [Byte0]: 42
1060 12:11:28.832744 [Byte1]: 42
1061 12:11:28.837161
1062 12:11:28.837296 Set Vref, RX VrefLevel [Byte0]: 43
1063 12:11:28.840222 [Byte1]: 43
1064 12:11:28.844862
1065 12:11:28.844996 Set Vref, RX VrefLevel [Byte0]: 44
1066 12:11:28.848049 [Byte1]: 44
1067 12:11:28.852165
1068 12:11:28.852297 Set Vref, RX VrefLevel [Byte0]: 45
1069 12:11:28.855941 [Byte1]: 45
1070 12:11:28.860475
1071 12:11:28.860609 Set Vref, RX VrefLevel [Byte0]: 46
1072 12:11:28.863660 [Byte1]: 46
1073 12:11:28.868105
1074 12:11:28.868251 Set Vref, RX VrefLevel [Byte0]: 47
1075 12:11:28.871208 [Byte1]: 47
1076 12:11:28.875535
1077 12:11:28.875670 Set Vref, RX VrefLevel [Byte0]: 48
1078 12:11:28.878779 [Byte1]: 48
1079 12:11:28.883050
1080 12:11:28.883180 Set Vref, RX VrefLevel [Byte0]: 49
1081 12:11:28.886265 [Byte1]: 49
1082 12:11:28.890683
1083 12:11:28.890815 Set Vref, RX VrefLevel [Byte0]: 50
1084 12:11:28.893950 [Byte1]: 50
1085 12:11:28.898102
1086 12:11:28.898232 Set Vref, RX VrefLevel [Byte0]: 51
1087 12:11:28.901670 [Byte1]: 51
1088 12:11:28.906002
1089 12:11:28.906134 Set Vref, RX VrefLevel [Byte0]: 52
1090 12:11:28.909058 [Byte1]: 52
1091 12:11:28.913748
1092 12:11:28.913887 Set Vref, RX VrefLevel [Byte0]: 53
1093 12:11:28.916601 [Byte1]: 53
1094 12:11:28.921418
1095 12:11:28.921552 Set Vref, RX VrefLevel [Byte0]: 54
1096 12:11:28.924497 [Byte1]: 54
1097 12:11:28.929094
1098 12:11:28.929230 Set Vref, RX VrefLevel [Byte0]: 55
1099 12:11:28.932147 [Byte1]: 55
1100 12:11:28.936555
1101 12:11:28.936692 Set Vref, RX VrefLevel [Byte0]: 56
1102 12:11:28.939781 [Byte1]: 56
1103 12:11:28.944331
1104 12:11:28.944463 Set Vref, RX VrefLevel [Byte0]: 57
1105 12:11:28.947479 [Byte1]: 57
1106 12:11:28.951958
1107 12:11:28.952094 Set Vref, RX VrefLevel [Byte0]: 58
1108 12:11:28.954965 [Byte1]: 58
1109 12:11:28.959241
1110 12:11:28.959378 Set Vref, RX VrefLevel [Byte0]: 59
1111 12:11:28.962965 [Byte1]: 59
1112 12:11:28.967376
1113 12:11:28.967520 Set Vref, RX VrefLevel [Byte0]: 60
1114 12:11:28.970546 [Byte1]: 60
1115 12:11:28.974872
1116 12:11:28.975003 Set Vref, RX VrefLevel [Byte0]: 61
1117 12:11:28.978003 [Byte1]: 61
1118 12:11:28.982398
1119 12:11:28.982533 Set Vref, RX VrefLevel [Byte0]: 62
1120 12:11:28.985651 [Byte1]: 62
1121 12:11:28.989959
1122 12:11:28.990089 Set Vref, RX VrefLevel [Byte0]: 63
1123 12:11:28.993338 [Byte1]: 63
1124 12:11:28.997821
1125 12:11:28.997962 Set Vref, RX VrefLevel [Byte0]: 64
1126 12:11:29.000973 [Byte1]: 64
1127 12:11:29.005420
1128 12:11:29.005551 Set Vref, RX VrefLevel [Byte0]: 65
1129 12:11:29.008481 [Byte1]: 65
1130 12:11:29.012653
1131 12:11:29.012785 Set Vref, RX VrefLevel [Byte0]: 66
1132 12:11:29.016166 [Byte1]: 66
1133 12:11:29.020364
1134 12:11:29.020476 Set Vref, RX VrefLevel [Byte0]: 67
1135 12:11:29.023907 [Byte1]: 67
1136 12:11:29.028092
1137 12:11:29.028201 Set Vref, RX VrefLevel [Byte0]: 68
1138 12:11:29.031256 [Byte1]: 68
1139 12:11:29.035682
1140 12:11:29.035791 Set Vref, RX VrefLevel [Byte0]: 69
1141 12:11:29.039147 [Byte1]: 69
1142 12:11:29.043544
1143 12:11:29.043650 Set Vref, RX VrefLevel [Byte0]: 70
1144 12:11:29.046734 [Byte1]: 70
1145 12:11:29.051308
1146 12:11:29.051420 Set Vref, RX VrefLevel [Byte0]: 71
1147 12:11:29.054431 [Byte1]: 71
1148 12:11:29.058603
1149 12:11:29.058714 Set Vref, RX VrefLevel [Byte0]: 72
1150 12:11:29.062317 [Byte1]: 72
1151 12:11:29.066557
1152 12:11:29.066675 Set Vref, RX VrefLevel [Byte0]: 73
1153 12:11:29.069591 [Byte1]: 73
1154 12:11:29.073976
1155 12:11:29.074085 Set Vref, RX VrefLevel [Byte0]: 74
1156 12:11:29.077197 [Byte1]: 74
1157 12:11:29.081710
1158 12:11:29.081826 Final RX Vref Byte 0 = 54 to rank0
1159 12:11:29.085275 Final RX Vref Byte 1 = 59 to rank0
1160 12:11:29.088546 Final RX Vref Byte 0 = 54 to rank1
1161 12:11:29.091752 Final RX Vref Byte 1 = 59 to rank1==
1162 12:11:29.095140 Dram Type= 6, Freq= 0, CH_0, rank 0
1163 12:11:29.101522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 12:11:29.101638 ==
1165 12:11:29.101734 DQS Delay:
1166 12:11:29.104656 DQS0 = 0, DQS1 = 0
1167 12:11:29.104762 DQM Delay:
1168 12:11:29.104859 DQM0 = 88, DQM1 = 77
1169 12:11:29.107834 DQ Delay:
1170 12:11:29.111735 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1171 12:11:29.114524 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1172 12:11:29.118203 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1173 12:11:29.121282 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1174 12:11:29.121386
1175 12:11:29.121475
1176 12:11:29.127880 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1177 12:11:29.131431 CH0 RK0: MR19=606, MR18=2B25
1178 12:11:29.137892 CH0_RK0: MR19=0x606, MR18=0x2B25, DQSOSC=398, MR23=63, INC=93, DEC=62
1179 12:11:29.138006
1180 12:11:29.140937 ----->DramcWriteLeveling(PI) begin...
1181 12:11:29.141048 ==
1182 12:11:29.144728 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 12:11:29.147902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 12:11:29.148012 ==
1185 12:11:29.151135 Write leveling (Byte 0): 29 => 29
1186 12:11:29.154279 Write leveling (Byte 1): 29 => 29
1187 12:11:29.157441 DramcWriteLeveling(PI) end<-----
1188 12:11:29.157551
1189 12:11:29.157647 ==
1190 12:11:29.160644 Dram Type= 6, Freq= 0, CH_0, rank 1
1191 12:11:29.164408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 12:11:29.167394 ==
1193 12:11:29.167509 [Gating] SW mode calibration
1194 12:11:29.174168 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1195 12:11:29.180524 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1196 12:11:29.184428 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1197 12:11:29.228492 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1198 12:11:29.228879 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 12:11:29.228991 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 12:11:29.229083 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:11:29.229171 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:11:29.229271 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:11:29.229359 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:11:29.229456 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:11:29.229738 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:11:29.229841 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:11:29.232861 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:11:29.239462 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:11:29.242800 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:11:29.246221 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:11:29.249282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:11:29.256163 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:11:29.259331 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1214 12:11:29.262410 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:11:29.269288 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1216 12:11:29.272931 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:11:29.276016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:11:29.282353 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:11:29.286171 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:11:29.289260 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:11:29.296037 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1222 12:11:29.299228 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
1223 12:11:29.302447 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1224 12:11:29.309404 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 12:11:29.312659 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 12:11:29.315924 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 12:11:29.322319 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 12:11:29.326149 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 12:11:29.329015 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1230 12:11:29.335660 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
1231 12:11:29.339005 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:11:29.342107 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:11:29.349088 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:11:29.351935 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:11:29.355383 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:11:29.362281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:11:29.365505 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1238 12:11:29.369306 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1239 12:11:29.372563 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1240 12:11:29.380186 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 12:11:29.383882 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 12:11:29.386478 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 12:11:29.390213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 12:11:29.396563 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 12:11:29.400260 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1246 12:11:29.403936 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1247 12:11:29.410944 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 12:11:29.414198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 12:11:29.417443 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 12:11:29.423610 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 12:11:29.427554 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 12:11:29.430635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 12:11:29.437249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 12:11:29.440591 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 12:11:29.443630 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 12:11:29.450317 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 12:11:29.453855 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 12:11:29.456807 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:11:29.460551 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:11:29.467350 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:11:29.470614 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1262 12:11:29.473663 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1263 12:11:29.476928 Total UI for P1: 0, mck2ui 16
1264 12:11:29.480076 best dqsien dly found for B0: ( 0, 14, 4)
1265 12:11:29.486821 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 12:11:29.486937 Total UI for P1: 0, mck2ui 16
1267 12:11:29.493852 best dqsien dly found for B1: ( 0, 14, 8)
1268 12:11:29.497152 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1269 12:11:29.500130 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1270 12:11:29.500239
1271 12:11:29.503636 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1272 12:11:29.507322 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1273 12:11:29.510392 [Gating] SW calibration Done
1274 12:11:29.510505 ==
1275 12:11:29.513636 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 12:11:29.516887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 12:11:29.516998 ==
1278 12:11:29.520000 RX Vref Scan: 0
1279 12:11:29.520127
1280 12:11:29.520248 RX Vref 0 -> 0, step: 1
1281 12:11:29.520339
1282 12:11:29.523728 RX Delay -130 -> 252, step: 16
1283 12:11:29.526935 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1284 12:11:29.533858 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1285 12:11:29.537045 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1286 12:11:29.540165 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1287 12:11:29.543307 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1288 12:11:29.546945 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1289 12:11:29.553490 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1290 12:11:29.557085 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1291 12:11:29.560170 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1292 12:11:29.563278 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1293 12:11:29.566875 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1294 12:11:29.573192 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1295 12:11:29.576347 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1296 12:11:29.580158 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1297 12:11:29.583335 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1298 12:11:29.590096 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1299 12:11:29.590219 ==
1300 12:11:29.593133 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 12:11:29.596481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 12:11:29.596595 ==
1303 12:11:29.596694 DQS Delay:
1304 12:11:29.599665 DQS0 = 0, DQS1 = 0
1305 12:11:29.599775 DQM Delay:
1306 12:11:29.603670 DQM0 = 86, DQM1 = 77
1307 12:11:29.603776 DQ Delay:
1308 12:11:29.606547 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1309 12:11:29.610039 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1310 12:11:29.613312 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1311 12:11:29.616540 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1312 12:11:29.616653
1313 12:11:29.616751
1314 12:11:29.616845 ==
1315 12:11:29.619812 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 12:11:29.622971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 12:11:29.623082 ==
1318 12:11:29.623176
1319 12:11:29.623266
1320 12:11:29.626190 TX Vref Scan disable
1321 12:11:29.629934 == TX Byte 0 ==
1322 12:11:29.632996 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1323 12:11:29.636271 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1324 12:11:29.639316 == TX Byte 1 ==
1325 12:11:29.643151 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1326 12:11:29.646252 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1327 12:11:29.646357 ==
1328 12:11:29.649913 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 12:11:29.655922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 12:11:29.656038 ==
1331 12:11:29.667884 TX Vref=22, minBit 2, minWin=26, winSum=443
1332 12:11:29.671069 TX Vref=24, minBit 1, minWin=27, winSum=443
1333 12:11:29.674129 TX Vref=26, minBit 3, minWin=27, winSum=448
1334 12:11:29.677795 TX Vref=28, minBit 3, minWin=27, winSum=448
1335 12:11:29.681116 TX Vref=30, minBit 6, minWin=27, winSum=448
1336 12:11:29.687749 TX Vref=32, minBit 6, minWin=27, winSum=449
1337 12:11:29.690888 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 32
1338 12:11:29.690978
1339 12:11:29.693956 Final TX Range 1 Vref 32
1340 12:11:29.694038
1341 12:11:29.694112 ==
1342 12:11:29.697845 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 12:11:29.700930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 12:11:29.701010 ==
1345 12:11:29.704106
1346 12:11:29.704194
1347 12:11:29.704266 TX Vref Scan disable
1348 12:11:29.707320 == TX Byte 0 ==
1349 12:11:29.711076 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1350 12:11:29.717662 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1351 12:11:29.717750 == TX Byte 1 ==
1352 12:11:29.720920 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1353 12:11:29.727255 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1354 12:11:29.727345
1355 12:11:29.727419 [DATLAT]
1356 12:11:29.727481 Freq=800, CH0 RK1
1357 12:11:29.727541
1358 12:11:29.731112 DATLAT Default: 0xa
1359 12:11:29.731221 0, 0xFFFF, sum = 0
1360 12:11:29.734303 1, 0xFFFF, sum = 0
1361 12:11:29.734388 2, 0xFFFF, sum = 0
1362 12:11:29.737487 3, 0xFFFF, sum = 0
1363 12:11:29.737569 4, 0xFFFF, sum = 0
1364 12:11:29.740727 5, 0xFFFF, sum = 0
1365 12:11:29.744417 6, 0xFFFF, sum = 0
1366 12:11:29.744507 7, 0xFFFF, sum = 0
1367 12:11:29.747647 8, 0xFFFF, sum = 0
1368 12:11:29.747743 9, 0x0, sum = 1
1369 12:11:29.747814 10, 0x0, sum = 2
1370 12:11:29.750950 11, 0x0, sum = 3
1371 12:11:29.751039 12, 0x0, sum = 4
1372 12:11:29.753994 best_step = 10
1373 12:11:29.754079
1374 12:11:29.754144 ==
1375 12:11:29.757534 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 12:11:29.760712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 12:11:29.760797 ==
1378 12:11:29.764401 RX Vref Scan: 0
1379 12:11:29.764490
1380 12:11:29.764557 RX Vref 0 -> 0, step: 1
1381 12:11:29.764626
1382 12:11:29.767194 RX Delay -95 -> 252, step: 8
1383 12:11:29.774428 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1384 12:11:29.777424 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1385 12:11:29.781040 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1386 12:11:29.784148 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1387 12:11:29.787697 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1388 12:11:29.794170 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1389 12:11:29.797661 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1390 12:11:29.800957 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1391 12:11:29.803979 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1392 12:11:29.807788 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1393 12:11:29.814181 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1394 12:11:29.817180 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1395 12:11:29.820804 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1396 12:11:29.823999 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1397 12:11:29.827860 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1398 12:11:29.834299 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1399 12:11:29.834388 ==
1400 12:11:29.837604 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 12:11:29.840713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 12:11:29.840799 ==
1403 12:11:29.840867 DQS Delay:
1404 12:11:29.843837 DQS0 = 0, DQS1 = 0
1405 12:11:29.843921 DQM Delay:
1406 12:11:29.847711 DQM0 = 86, DQM1 = 77
1407 12:11:29.847823 DQ Delay:
1408 12:11:29.850765 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1409 12:11:29.854023 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1410 12:11:29.857099 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1411 12:11:29.860375 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =84
1412 12:11:29.860456
1413 12:11:29.860524
1414 12:11:29.870308 [DQSOSCAuto] RK1, (LSB)MR18= 0x2926, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1415 12:11:29.870409 CH0 RK1: MR19=606, MR18=2926
1416 12:11:29.877086 CH0_RK1: MR19=0x606, MR18=0x2926, DQSOSC=399, MR23=63, INC=92, DEC=61
1417 12:11:29.880005 [RxdqsGatingPostProcess] freq 800
1418 12:11:29.887128 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1419 12:11:29.890028 Pre-setting of DQS Precalculation
1420 12:11:29.893696 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1421 12:11:29.893776 ==
1422 12:11:29.896896 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 12:11:29.903676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 12:11:29.903762 ==
1425 12:11:29.906790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 12:11:29.913557 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 12:11:29.922514 [CA 0] Center 37 (6~68) winsize 63
1428 12:11:29.926179 [CA 1] Center 37 (6~68) winsize 63
1429 12:11:29.929443 [CA 2] Center 35 (5~66) winsize 62
1430 12:11:29.932574 [CA 3] Center 34 (4~65) winsize 62
1431 12:11:29.935890 [CA 4] Center 35 (4~66) winsize 63
1432 12:11:29.939148 [CA 5] Center 34 (4~65) winsize 62
1433 12:11:29.939254
1434 12:11:29.942862 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 12:11:29.942983
1436 12:11:29.945995 [CATrainingPosCal] consider 1 rank data
1437 12:11:29.949188 u2DelayCellTimex100 = 270/100 ps
1438 12:11:29.952290 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1439 12:11:29.955502 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1440 12:11:29.962453 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1441 12:11:29.965577 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 12:11:29.969237 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1443 12:11:29.972276 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1444 12:11:29.972395
1445 12:11:29.975882 CA PerBit enable=1, Macro0, CA PI delay=34
1446 12:11:29.975994
1447 12:11:29.978982 [CBTSetCACLKResult] CA Dly = 34
1448 12:11:29.979092 CS Dly: 4 (0~35)
1449 12:11:29.982699 ==
1450 12:11:29.985669 Dram Type= 6, Freq= 0, CH_1, rank 1
1451 12:11:29.988559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 12:11:29.988682 ==
1453 12:11:29.991928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 12:11:29.998547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 12:11:30.008459 [CA 0] Center 36 (6~67) winsize 62
1456 12:11:30.012271 [CA 1] Center 36 (6~67) winsize 62
1457 12:11:30.015368 [CA 2] Center 34 (4~65) winsize 62
1458 12:11:30.018610 [CA 3] Center 34 (4~65) winsize 62
1459 12:11:30.021772 [CA 4] Center 34 (4~65) winsize 62
1460 12:11:30.025470 [CA 5] Center 34 (4~65) winsize 62
1461 12:11:30.025580
1462 12:11:30.028543 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1463 12:11:30.028652
1464 12:11:30.031817 [CATrainingPosCal] consider 2 rank data
1465 12:11:30.035619 u2DelayCellTimex100 = 270/100 ps
1466 12:11:30.039439 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 12:11:30.042575 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1468 12:11:30.046465 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 12:11:30.050138 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 12:11:30.053925 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 12:11:30.057607 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 12:11:30.057718
1473 12:11:30.061560 CA PerBit enable=1, Macro0, CA PI delay=34
1474 12:11:30.061653
1475 12:11:30.065533 [CBTSetCACLKResult] CA Dly = 34
1476 12:11:30.065624 CS Dly: 5 (0~37)
1477 12:11:30.065695
1478 12:11:30.069326 ----->DramcWriteLeveling(PI) begin...
1479 12:11:30.069422 ==
1480 12:11:30.072554 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 12:11:30.079183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 12:11:30.079302 ==
1483 12:11:30.082346 Write leveling (Byte 0): 27 => 27
1484 12:11:30.086012 Write leveling (Byte 1): 27 => 27
1485 12:11:30.086106 DramcWriteLeveling(PI) end<-----
1486 12:11:30.086176
1487 12:11:30.089175 ==
1488 12:11:30.092858 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 12:11:30.095780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 12:11:30.095898 ==
1491 12:11:30.099262 [Gating] SW mode calibration
1492 12:11:30.105969 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1493 12:11:30.108980 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1494 12:11:30.115602 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1495 12:11:30.119444 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1496 12:11:30.122750 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:11:30.129140 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:11:30.131947 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:11:30.135705 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:11:30.142213 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:11:30.145447 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:11:30.149269 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:11:30.155418 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:11:30.159282 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:11:30.162538 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:11:30.165741 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:11:30.172044 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:11:30.175196 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:11:30.178913 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:11:30.185703 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1511 12:11:30.188707 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1512 12:11:30.192360 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:11:30.198997 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:11:30.202029 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:11:30.205094 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:11:30.211797 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:11:30.215414 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:11:30.218347 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:11:30.225319 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:11:30.228512 0 9 8 | B1->B0 | 2c2c 3030 | 1 1 | (1 1) (1 1)
1521 12:11:30.231678 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 12:11:30.238576 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 12:11:30.241775 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 12:11:30.244980 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 12:11:30.251862 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 12:11:30.255092 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 12:11:30.258329 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
1528 12:11:30.264740 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1529 12:11:30.267951 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:11:30.271872 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:11:30.278191 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:11:30.281416 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:11:30.284556 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:11:30.291270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:11:30.295028 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1536 12:11:30.298167 0 11 8 | B1->B0 | 3a3a 4343 | 0 1 | (0 0) (0 0)
1537 12:11:30.304655 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 12:11:30.307797 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 12:11:30.311418 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 12:11:30.317836 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 12:11:30.321486 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 12:11:30.324544 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 12:11:30.331223 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1544 12:11:30.334434 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 12:11:30.337563 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 12:11:30.344567 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 12:11:30.347737 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 12:11:30.350890 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 12:11:30.357788 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 12:11:30.361034 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 12:11:30.364170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 12:11:30.371142 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 12:11:30.374455 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 12:11:30.377701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 12:11:30.380742 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:11:30.387752 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:11:30.390986 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:11:30.393996 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:11:30.400611 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1560 12:11:30.404237 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:11:30.407697 Total UI for P1: 0, mck2ui 16
1562 12:11:30.410748 best dqsien dly found for B0: ( 0, 14, 4)
1563 12:11:30.414364 Total UI for P1: 0, mck2ui 16
1564 12:11:30.417448 best dqsien dly found for B1: ( 0, 14, 4)
1565 12:11:30.421111 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1566 12:11:30.424512 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1567 12:11:30.424624
1568 12:11:30.427450 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1569 12:11:30.431156 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1570 12:11:30.434139 [Gating] SW calibration Done
1571 12:11:30.434269 ==
1572 12:11:30.437200 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 12:11:30.441048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 12:11:30.443981 ==
1575 12:11:30.444079 RX Vref Scan: 0
1576 12:11:30.444147
1577 12:11:30.447104 RX Vref 0 -> 0, step: 1
1578 12:11:30.447190
1579 12:11:30.451009 RX Delay -130 -> 252, step: 16
1580 12:11:30.454155 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1581 12:11:30.457270 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1582 12:11:30.461148 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1583 12:11:30.464357 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1584 12:11:30.470747 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1585 12:11:30.473871 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1586 12:11:30.477160 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1587 12:11:30.480393 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1588 12:11:30.484093 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1589 12:11:30.490473 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1590 12:11:30.493770 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1591 12:11:30.497495 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1592 12:11:30.500678 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1593 12:11:30.503784 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1594 12:11:30.510304 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1595 12:11:30.514084 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1596 12:11:30.514205 ==
1597 12:11:30.517083 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 12:11:30.520221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 12:11:30.520331 ==
1600 12:11:30.523811 DQS Delay:
1601 12:11:30.523920 DQS0 = 0, DQS1 = 0
1602 12:11:30.526890 DQM Delay:
1603 12:11:30.527002 DQM0 = 88, DQM1 = 79
1604 12:11:30.527103 DQ Delay:
1605 12:11:30.530321 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1606 12:11:30.533964 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1607 12:11:30.537105 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1608 12:11:30.540701 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1609 12:11:30.540826
1610 12:11:30.540924
1611 12:11:30.543914 ==
1612 12:11:30.544021 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 12:11:30.550128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 12:11:30.550252 ==
1615 12:11:30.550359
1616 12:11:30.550458
1617 12:11:30.553304 TX Vref Scan disable
1618 12:11:30.553415 == TX Byte 0 ==
1619 12:11:30.556634 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1620 12:11:30.563638 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1621 12:11:30.563757 == TX Byte 1 ==
1622 12:11:30.566858 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1623 12:11:30.573724 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1624 12:11:30.573856 ==
1625 12:11:30.577039 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 12:11:30.579672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 12:11:30.579782 ==
1628 12:11:30.593000 TX Vref=22, minBit 5, minWin=26, winSum=438
1629 12:11:30.596291 TX Vref=24, minBit 0, minWin=27, winSum=443
1630 12:11:30.600090 TX Vref=26, minBit 0, minWin=27, winSum=445
1631 12:11:30.603243 TX Vref=28, minBit 1, minWin=27, winSum=453
1632 12:11:30.606424 TX Vref=30, minBit 0, minWin=27, winSum=453
1633 12:11:30.609495 TX Vref=32, minBit 0, minWin=27, winSum=449
1634 12:11:30.616505 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1635 12:11:30.616641
1636 12:11:30.620608 Final TX Range 1 Vref 28
1637 12:11:30.620737
1638 12:11:30.620836 ==
1639 12:11:30.623777 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 12:11:30.627193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 12:11:30.627327 ==
1642 12:11:30.627427
1643 12:11:30.627525
1644 12:11:30.630241 TX Vref Scan disable
1645 12:11:30.633776 == TX Byte 0 ==
1646 12:11:30.636843 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1647 12:11:30.640248 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1648 12:11:30.643889 == TX Byte 1 ==
1649 12:11:30.646739 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1650 12:11:30.649931 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1651 12:11:30.650040
1652 12:11:30.653441 [DATLAT]
1653 12:11:30.653551 Freq=800, CH1 RK0
1654 12:11:30.653653
1655 12:11:30.656625 DATLAT Default: 0xa
1656 12:11:30.656749 0, 0xFFFF, sum = 0
1657 12:11:30.660536 1, 0xFFFF, sum = 0
1658 12:11:30.660649 2, 0xFFFF, sum = 0
1659 12:11:30.663549 3, 0xFFFF, sum = 0
1660 12:11:30.663660 4, 0xFFFF, sum = 0
1661 12:11:30.666729 5, 0xFFFF, sum = 0
1662 12:11:30.666851 6, 0xFFFF, sum = 0
1663 12:11:30.669900 7, 0xFFFF, sum = 0
1664 12:11:30.670018 8, 0xFFFF, sum = 0
1665 12:11:30.673155 9, 0x0, sum = 1
1666 12:11:30.673271 10, 0x0, sum = 2
1667 12:11:30.676349 11, 0x0, sum = 3
1668 12:11:30.676462 12, 0x0, sum = 4
1669 12:11:30.680184 best_step = 10
1670 12:11:30.680290
1671 12:11:30.680392 ==
1672 12:11:30.683336 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 12:11:30.686598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 12:11:30.686720 ==
1675 12:11:30.689728 RX Vref Scan: 1
1676 12:11:30.689836
1677 12:11:30.689944 Set Vref Range= 32 -> 127
1678 12:11:30.690038
1679 12:11:30.693000 RX Vref 32 -> 127, step: 1
1680 12:11:30.693109
1681 12:11:30.696796 RX Delay -95 -> 252, step: 8
1682 12:11:30.696906
1683 12:11:30.700001 Set Vref, RX VrefLevel [Byte0]: 32
1684 12:11:30.703098 [Byte1]: 32
1685 12:11:30.703219
1686 12:11:30.706332 Set Vref, RX VrefLevel [Byte0]: 33
1687 12:11:30.709541 [Byte1]: 33
1688 12:11:30.713337
1689 12:11:30.713462 Set Vref, RX VrefLevel [Byte0]: 34
1690 12:11:30.716562 [Byte1]: 34
1691 12:11:30.720774
1692 12:11:30.720895 Set Vref, RX VrefLevel [Byte0]: 35
1693 12:11:30.724581 [Byte1]: 35
1694 12:11:30.728781
1695 12:11:30.728902 Set Vref, RX VrefLevel [Byte0]: 36
1696 12:11:30.731548 [Byte1]: 36
1697 12:11:30.735821
1698 12:11:30.735943 Set Vref, RX VrefLevel [Byte0]: 37
1699 12:11:30.739337 [Byte1]: 37
1700 12:11:30.743453
1701 12:11:30.746459 Set Vref, RX VrefLevel [Byte0]: 38
1702 12:11:30.749949 [Byte1]: 38
1703 12:11:30.750181
1704 12:11:30.753531 Set Vref, RX VrefLevel [Byte0]: 39
1705 12:11:30.756579 [Byte1]: 39
1706 12:11:30.756696
1707 12:11:30.760080 Set Vref, RX VrefLevel [Byte0]: 40
1708 12:11:30.763141 [Byte1]: 40
1709 12:11:30.766887
1710 12:11:30.767007 Set Vref, RX VrefLevel [Byte0]: 41
1711 12:11:30.770315 [Byte1]: 41
1712 12:11:30.773991
1713 12:11:30.774105 Set Vref, RX VrefLevel [Byte0]: 42
1714 12:11:30.777772 [Byte1]: 42
1715 12:11:30.781646
1716 12:11:30.781771 Set Vref, RX VrefLevel [Byte0]: 43
1717 12:11:30.784975 [Byte1]: 43
1718 12:11:30.789314
1719 12:11:30.789427 Set Vref, RX VrefLevel [Byte0]: 44
1720 12:11:30.793146 [Byte1]: 44
1721 12:11:30.796845
1722 12:11:30.796955 Set Vref, RX VrefLevel [Byte0]: 45
1723 12:11:30.799964 [Byte1]: 45
1724 12:11:30.804392
1725 12:11:30.804531 Set Vref, RX VrefLevel [Byte0]: 46
1726 12:11:30.807609 [Byte1]: 46
1727 12:11:30.812054
1728 12:11:30.812165 Set Vref, RX VrefLevel [Byte0]: 47
1729 12:11:30.815239 [Byte1]: 47
1730 12:11:30.819646
1731 12:11:30.819756 Set Vref, RX VrefLevel [Byte0]: 48
1732 12:11:30.822815 [Byte1]: 48
1733 12:11:30.827189
1734 12:11:30.827282 Set Vref, RX VrefLevel [Byte0]: 49
1735 12:11:30.830336 [Byte1]: 49
1736 12:11:30.834926
1737 12:11:30.835048 Set Vref, RX VrefLevel [Byte0]: 50
1738 12:11:30.838080 [Byte1]: 50
1739 12:11:30.842387
1740 12:11:30.842532 Set Vref, RX VrefLevel [Byte0]: 51
1741 12:11:30.845980 [Byte1]: 51
1742 12:11:30.850184
1743 12:11:30.850309 Set Vref, RX VrefLevel [Byte0]: 52
1744 12:11:30.853586 [Byte1]: 52
1745 12:11:30.857712
1746 12:11:30.857838 Set Vref, RX VrefLevel [Byte0]: 53
1747 12:11:30.860942 [Byte1]: 53
1748 12:11:30.865564
1749 12:11:30.865679 Set Vref, RX VrefLevel [Byte0]: 54
1750 12:11:30.868566 [Byte1]: 54
1751 12:11:30.872846
1752 12:11:30.872987 Set Vref, RX VrefLevel [Byte0]: 55
1753 12:11:30.875921 [Byte1]: 55
1754 12:11:30.880448
1755 12:11:30.880557 Set Vref, RX VrefLevel [Byte0]: 56
1756 12:11:30.883568 [Byte1]: 56
1757 12:11:30.887999
1758 12:11:30.888116 Set Vref, RX VrefLevel [Byte0]: 57
1759 12:11:30.891246 [Byte1]: 57
1760 12:11:30.895609
1761 12:11:30.895729 Set Vref, RX VrefLevel [Byte0]: 58
1762 12:11:30.898727 [Byte1]: 58
1763 12:11:30.903252
1764 12:11:30.903365 Set Vref, RX VrefLevel [Byte0]: 59
1765 12:11:30.906621 [Byte1]: 59
1766 12:11:30.911065
1767 12:11:30.911187 Set Vref, RX VrefLevel [Byte0]: 60
1768 12:11:30.914187 [Byte1]: 60
1769 12:11:30.918525
1770 12:11:30.918645 Set Vref, RX VrefLevel [Byte0]: 61
1771 12:11:30.921623 [Byte1]: 61
1772 12:11:30.926037
1773 12:11:30.926153 Set Vref, RX VrefLevel [Byte0]: 62
1774 12:11:30.929095 [Byte1]: 62
1775 12:11:30.933573
1776 12:11:30.933692 Set Vref, RX VrefLevel [Byte0]: 63
1777 12:11:30.936793 [Byte1]: 63
1778 12:11:30.941863
1779 12:11:30.941982 Set Vref, RX VrefLevel [Byte0]: 64
1780 12:11:30.944401 [Byte1]: 64
1781 12:11:30.948854
1782 12:11:30.948973 Set Vref, RX VrefLevel [Byte0]: 65
1783 12:11:30.952221 [Byte1]: 65
1784 12:11:30.956192
1785 12:11:30.956316 Set Vref, RX VrefLevel [Byte0]: 66
1786 12:11:30.959661 [Byte1]: 66
1787 12:11:30.963755
1788 12:11:30.963876 Set Vref, RX VrefLevel [Byte0]: 67
1789 12:11:30.967362 [Byte1]: 67
1790 12:11:30.971647
1791 12:11:30.971783 Set Vref, RX VrefLevel [Byte0]: 68
1792 12:11:30.974675 [Byte1]: 68
1793 12:11:30.978991
1794 12:11:30.979113 Set Vref, RX VrefLevel [Byte0]: 69
1795 12:11:30.982953 [Byte1]: 69
1796 12:11:30.986781
1797 12:11:30.986932 Set Vref, RX VrefLevel [Byte0]: 70
1798 12:11:30.989994 [Byte1]: 70
1799 12:11:30.994497
1800 12:11:30.994625 Set Vref, RX VrefLevel [Byte0]: 71
1801 12:11:30.997784 [Byte1]: 71
1802 12:11:31.001626
1803 12:11:31.001753 Set Vref, RX VrefLevel [Byte0]: 72
1804 12:11:31.005556 [Byte1]: 72
1805 12:11:31.009275
1806 12:11:31.009400 Set Vref, RX VrefLevel [Byte0]: 73
1807 12:11:31.012544 [Byte1]: 73
1808 12:11:31.016917
1809 12:11:31.017008 Set Vref, RX VrefLevel [Byte0]: 74
1810 12:11:31.020092 [Byte1]: 74
1811 12:11:31.024567
1812 12:11:31.024649 Final RX Vref Byte 0 = 59 to rank0
1813 12:11:31.027835 Final RX Vref Byte 1 = 58 to rank0
1814 12:11:31.031765 Final RX Vref Byte 0 = 59 to rank1
1815 12:11:31.034652 Final RX Vref Byte 1 = 58 to rank1==
1816 12:11:31.037868 Dram Type= 6, Freq= 0, CH_1, rank 0
1817 12:11:31.044781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 12:11:31.044875 ==
1819 12:11:31.044958 DQS Delay:
1820 12:11:31.045060 DQS0 = 0, DQS1 = 0
1821 12:11:31.047717 DQM Delay:
1822 12:11:31.047830 DQM0 = 86, DQM1 = 81
1823 12:11:31.051330 DQ Delay:
1824 12:11:31.054449 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1825 12:11:31.057998 DQ4 =80, DQ5 =96, DQ6 =100, DQ7 =84
1826 12:11:31.061036 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1827 12:11:31.064802 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1828 12:11:31.064896
1829 12:11:31.064965
1830 12:11:31.071236 [DQSOSCAuto] RK0, (LSB)MR18= 0x172a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1831 12:11:31.074229 CH1 RK0: MR19=606, MR18=172A
1832 12:11:31.080924 CH1_RK0: MR19=0x606, MR18=0x172A, DQSOSC=399, MR23=63, INC=92, DEC=61
1833 12:11:31.081052
1834 12:11:31.083994 ----->DramcWriteLeveling(PI) begin...
1835 12:11:31.084110 ==
1836 12:11:31.087881 Dram Type= 6, Freq= 0, CH_1, rank 1
1837 12:11:31.091120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1838 12:11:31.091214 ==
1839 12:11:31.094325 Write leveling (Byte 0): 26 => 26
1840 12:11:31.097501 Write leveling (Byte 1): 27 => 27
1841 12:11:31.100557 DramcWriteLeveling(PI) end<-----
1842 12:11:31.100683
1843 12:11:31.100779 ==
1844 12:11:31.103911 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 12:11:31.107836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 12:11:31.107957 ==
1847 12:11:31.110819 [Gating] SW mode calibration
1848 12:11:31.117671 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1849 12:11:31.123869 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1850 12:11:31.127126 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1851 12:11:31.133605 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:11:31.137336 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1853 12:11:31.140584 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:11:31.146861 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:11:31.150655 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:11:31.153880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:11:31.160188 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:11:31.163588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:11:31.167302 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:11:31.173256 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:11:31.176718 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:11:31.180040 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:11:31.186538 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:11:31.190008 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:11:31.193743 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:11:31.200198 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1867 12:11:31.203331 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:11:31.206571 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1869 12:11:31.210305 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:11:31.216585 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:11:31.220391 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:11:31.223355 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:11:31.230190 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:11:31.233406 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:11:31.236575 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:11:31.242869 0 9 8 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
1877 12:11:31.246763 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 12:11:31.249915 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 12:11:31.256243 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1880 12:11:31.259549 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1881 12:11:31.262740 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1882 12:11:31.269365 0 10 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1883 12:11:31.273039 0 10 4 | B1->B0 | 3232 2b2b | 1 0 | (1 0) (0 0)
1884 12:11:31.276073 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
1885 12:11:31.282712 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:11:31.286291 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:11:31.289482 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:11:31.296140 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:11:31.299758 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:11:31.302794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:11:31.309326 0 11 4 | B1->B0 | 2727 3737 | 0 0 | (1 1) (0 0)
1892 12:11:31.312601 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1893 12:11:31.315656 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 12:11:31.322676 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 12:11:31.325898 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1896 12:11:31.328993 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1897 12:11:31.335905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1898 12:11:31.339096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1899 12:11:31.342242 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1900 12:11:31.349057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1901 12:11:31.352233 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 12:11:31.355936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 12:11:31.362426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 12:11:31.365637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 12:11:31.368901 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 12:11:31.375709 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 12:11:31.378663 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 12:11:31.382231 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 12:11:31.388625 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 12:11:31.392317 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 12:11:31.395133 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 12:11:31.402203 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:11:31.405073 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:11:31.408567 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:11:31.415447 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1916 12:11:31.418588 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 12:11:31.421773 Total UI for P1: 0, mck2ui 16
1918 12:11:31.425569 best dqsien dly found for B0: ( 0, 14, 4)
1919 12:11:31.428749 Total UI for P1: 0, mck2ui 16
1920 12:11:31.431921 best dqsien dly found for B1: ( 0, 14, 6)
1921 12:11:31.435123 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1922 12:11:31.438933 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1923 12:11:31.439045
1924 12:11:31.442087 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1925 12:11:31.445276 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1926 12:11:31.448602 [Gating] SW calibration Done
1927 12:11:31.448725 ==
1928 12:11:31.451650 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 12:11:31.454957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 12:11:31.455067 ==
1931 12:11:31.458735 RX Vref Scan: 0
1932 12:11:31.458846
1933 12:11:31.462074 RX Vref 0 -> 0, step: 1
1934 12:11:31.462187
1935 12:11:31.462290 RX Delay -130 -> 252, step: 16
1936 12:11:31.468521 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1937 12:11:31.471654 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1938 12:11:31.474897 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1939 12:11:31.478492 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1940 12:11:31.481676 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1941 12:11:31.488226 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1942 12:11:31.491867 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1943 12:11:31.494723 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1944 12:11:31.498109 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1945 12:11:31.501882 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1946 12:11:31.508212 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1947 12:11:31.511614 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1948 12:11:31.514625 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1949 12:11:31.518106 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1950 12:11:31.521140 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1951 12:11:31.528108 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1952 12:11:31.528194 ==
1953 12:11:31.531275 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 12:11:31.534469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 12:11:31.534576 ==
1956 12:11:31.534680 DQS Delay:
1957 12:11:31.537766 DQS0 = 0, DQS1 = 0
1958 12:11:31.537871 DQM Delay:
1959 12:11:31.541608 DQM0 = 82, DQM1 = 79
1960 12:11:31.541714 DQ Delay:
1961 12:11:31.544740 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1962 12:11:31.547884 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1963 12:11:31.551032 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1964 12:11:31.554704 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1965 12:11:31.554815
1966 12:11:31.554912
1967 12:11:31.555002 ==
1968 12:11:31.558052 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 12:11:31.561211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 12:11:31.564450 ==
1971 12:11:31.564559
1972 12:11:31.564662
1973 12:11:31.564757 TX Vref Scan disable
1974 12:11:31.567621 == TX Byte 0 ==
1975 12:11:31.570867 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1976 12:11:31.574098 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1977 12:11:31.577887 == TX Byte 1 ==
1978 12:11:31.581129 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1979 12:11:31.584363 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1980 12:11:31.587642 ==
1981 12:11:31.590751 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 12:11:31.594273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 12:11:31.594382 ==
1984 12:11:31.606552 TX Vref=22, minBit 1, minWin=26, winSum=440
1985 12:11:31.610228 TX Vref=24, minBit 1, minWin=27, winSum=447
1986 12:11:31.613133 TX Vref=26, minBit 1, minWin=27, winSum=451
1987 12:11:31.616679 TX Vref=28, minBit 3, minWin=27, winSum=452
1988 12:11:31.619577 TX Vref=30, minBit 2, minWin=27, winSum=453
1989 12:11:31.626638 TX Vref=32, minBit 3, minWin=27, winSum=450
1990 12:11:31.629661 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
1991 12:11:31.629780
1992 12:11:31.633330 Final TX Range 1 Vref 30
1993 12:11:31.633455
1994 12:11:31.633553 ==
1995 12:11:31.636525 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 12:11:31.639722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 12:11:31.639839 ==
1998 12:11:31.639936
1999 12:11:31.642863
2000 12:11:31.642973 TX Vref Scan disable
2001 12:11:31.646660 == TX Byte 0 ==
2002 12:11:31.649917 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2003 12:11:31.656090 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2004 12:11:31.656214 == TX Byte 1 ==
2005 12:11:31.660015 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 12:11:31.666372 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 12:11:31.666490
2008 12:11:31.666588 [DATLAT]
2009 12:11:31.666690 Freq=800, CH1 RK1
2010 12:11:31.666789
2011 12:11:31.669592 DATLAT Default: 0xa
2012 12:11:31.669702 0, 0xFFFF, sum = 0
2013 12:11:31.672919 1, 0xFFFF, sum = 0
2014 12:11:31.673041 2, 0xFFFF, sum = 0
2015 12:11:31.676044 3, 0xFFFF, sum = 0
2016 12:11:31.679942 4, 0xFFFF, sum = 0
2017 12:11:31.680065 5, 0xFFFF, sum = 0
2018 12:11:31.683122 6, 0xFFFF, sum = 0
2019 12:11:31.683228 7, 0xFFFF, sum = 0
2020 12:11:31.686313 8, 0xFFFF, sum = 0
2021 12:11:31.686422 9, 0x0, sum = 1
2022 12:11:31.689499 10, 0x0, sum = 2
2023 12:11:31.689611 11, 0x0, sum = 3
2024 12:11:31.689713 12, 0x0, sum = 4
2025 12:11:31.692733 best_step = 10
2026 12:11:31.692837
2027 12:11:31.692941 ==
2028 12:11:31.696406 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 12:11:31.699560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 12:11:31.699672 ==
2031 12:11:31.702584 RX Vref Scan: 0
2032 12:11:31.702695
2033 12:11:31.706354 RX Vref 0 -> 0, step: 1
2034 12:11:31.706476
2035 12:11:31.706575 RX Delay -95 -> 252, step: 8
2036 12:11:31.713375 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2037 12:11:31.716369 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2038 12:11:31.719552 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2039 12:11:31.722887 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
2040 12:11:31.726324 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2041 12:11:31.732795 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2042 12:11:31.736254 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2043 12:11:31.739765 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2044 12:11:31.742701 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2045 12:11:31.746371 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2046 12:11:31.752908 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2047 12:11:31.756075 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2048 12:11:31.759112 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2049 12:11:31.762450 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2050 12:11:31.769500 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2051 12:11:31.772667 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2052 12:11:31.772808 ==
2053 12:11:31.775869 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 12:11:31.779114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 12:11:31.779239 ==
2056 12:11:31.782532 DQS Delay:
2057 12:11:31.782643 DQS0 = 0, DQS1 = 0
2058 12:11:31.782753 DQM Delay:
2059 12:11:31.785674 DQM0 = 87, DQM1 = 83
2060 12:11:31.785781 DQ Delay:
2061 12:11:31.788946 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2062 12:11:31.792704 DQ4 =88, DQ5 =96, DQ6 =96, DQ7 =84
2063 12:11:31.795311 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
2064 12:11:31.798567 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2065 12:11:31.798678
2066 12:11:31.798779
2067 12:11:31.808622 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 403 ps
2068 12:11:31.812124 CH1 RK1: MR19=606, MR18=1B37
2069 12:11:31.815268 CH1_RK1: MR19=0x606, MR18=0x1B37, DQSOSC=395, MR23=63, INC=94, DEC=63
2070 12:11:31.818681 [RxdqsGatingPostProcess] freq 800
2071 12:11:31.825459 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2072 12:11:31.828483 Pre-setting of DQS Precalculation
2073 12:11:31.831974 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2074 12:11:31.841724 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2075 12:11:31.848253 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2076 12:11:31.848352
2077 12:11:31.848425
2078 12:11:31.851550 [Calibration Summary] 1600 Mbps
2079 12:11:31.851651 CH 0, Rank 0
2080 12:11:31.855279 SW Impedance : PASS
2081 12:11:31.855382 DUTY Scan : NO K
2082 12:11:31.858418 ZQ Calibration : PASS
2083 12:11:31.861993 Jitter Meter : NO K
2084 12:11:31.862097 CBT Training : PASS
2085 12:11:31.865266 Write leveling : PASS
2086 12:11:31.868460 RX DQS gating : PASS
2087 12:11:31.868569 RX DQ/DQS(RDDQC) : PASS
2088 12:11:31.871588 TX DQ/DQS : PASS
2089 12:11:31.874783 RX DATLAT : PASS
2090 12:11:31.874895 RX DQ/DQS(Engine): PASS
2091 12:11:31.878018 TX OE : NO K
2092 12:11:31.878127 All Pass.
2093 12:11:31.878234
2094 12:11:31.881318 CH 0, Rank 1
2095 12:11:31.881423 SW Impedance : PASS
2096 12:11:31.885230 DUTY Scan : NO K
2097 12:11:31.888441 ZQ Calibration : PASS
2098 12:11:31.888548 Jitter Meter : NO K
2099 12:11:31.891586 CBT Training : PASS
2100 12:11:31.894801 Write leveling : PASS
2101 12:11:31.894905 RX DQS gating : PASS
2102 12:11:31.897960 RX DQ/DQS(RDDQC) : PASS
2103 12:11:31.898064 TX DQ/DQS : PASS
2104 12:11:31.901793 RX DATLAT : PASS
2105 12:11:31.904878 RX DQ/DQS(Engine): PASS
2106 12:11:31.904967 TX OE : NO K
2107 12:11:31.908147 All Pass.
2108 12:11:31.908257
2109 12:11:31.908362 CH 1, Rank 0
2110 12:11:31.911278 SW Impedance : PASS
2111 12:11:31.911356 DUTY Scan : NO K
2112 12:11:31.914915 ZQ Calibration : PASS
2113 12:11:31.917995 Jitter Meter : NO K
2114 12:11:31.918086 CBT Training : PASS
2115 12:11:31.921354 Write leveling : PASS
2116 12:11:31.924731 RX DQS gating : PASS
2117 12:11:31.924820 RX DQ/DQS(RDDQC) : PASS
2118 12:11:31.928181 TX DQ/DQS : PASS
2119 12:11:31.931380 RX DATLAT : PASS
2120 12:11:31.931469 RX DQ/DQS(Engine): PASS
2121 12:11:31.934975 TX OE : NO K
2122 12:11:31.935090 All Pass.
2123 12:11:31.935178
2124 12:11:31.937972 CH 1, Rank 1
2125 12:11:31.938062 SW Impedance : PASS
2126 12:11:31.941536 DUTY Scan : NO K
2127 12:11:31.944287 ZQ Calibration : PASS
2128 12:11:31.944376 Jitter Meter : NO K
2129 12:11:31.947913 CBT Training : PASS
2130 12:11:31.951412 Write leveling : PASS
2131 12:11:31.951511 RX DQS gating : PASS
2132 12:11:31.954424 RX DQ/DQS(RDDQC) : PASS
2133 12:11:31.954541 TX DQ/DQS : PASS
2134 12:11:31.958007 RX DATLAT : PASS
2135 12:11:31.960944 RX DQ/DQS(Engine): PASS
2136 12:11:31.961024 TX OE : NO K
2137 12:11:31.964741 All Pass.
2138 12:11:31.964826
2139 12:11:31.964895 DramC Write-DBI off
2140 12:11:31.967869 PER_BANK_REFRESH: Hybrid Mode
2141 12:11:31.971070 TX_TRACKING: ON
2142 12:11:31.974240 [GetDramInforAfterCalByMRR] Vendor 6.
2143 12:11:31.977508 [GetDramInforAfterCalByMRR] Revision 606.
2144 12:11:31.980810 [GetDramInforAfterCalByMRR] Revision 2 0.
2145 12:11:31.980901 MR0 0x3b3b
2146 12:11:31.980970 MR8 0x5151
2147 12:11:31.987876 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 12:11:31.987986
2149 12:11:31.988081 MR0 0x3b3b
2150 12:11:31.988150 MR8 0x5151
2151 12:11:31.991055 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2152 12:11:31.991147
2153 12:11:32.000691 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2154 12:11:32.003913 [FAST_K] Save calibration result to emmc
2155 12:11:32.007153 [FAST_K] Save calibration result to emmc
2156 12:11:32.010966 dram_init: config_dvfs: 1
2157 12:11:32.014017 dramc_set_vcore_voltage set vcore to 662500
2158 12:11:32.017753 Read voltage for 1200, 2
2159 12:11:32.017837 Vio18 = 0
2160 12:11:32.017911 Vcore = 662500
2161 12:11:32.020720 Vdram = 0
2162 12:11:32.020803 Vddq = 0
2163 12:11:32.020888 Vmddr = 0
2164 12:11:32.027794 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2165 12:11:32.030564 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2166 12:11:32.034159 MEM_TYPE=3, freq_sel=15
2167 12:11:32.037177 sv_algorithm_assistance_LP4_1600
2168 12:11:32.040834 ============ PULL DRAM RESETB DOWN ============
2169 12:11:32.047152 ========== PULL DRAM RESETB DOWN end =========
2170 12:11:32.050687 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2171 12:11:32.054194 ===================================
2172 12:11:32.057221 LPDDR4 DRAM CONFIGURATION
2173 12:11:32.060828 ===================================
2174 12:11:32.060916 EX_ROW_EN[0] = 0x0
2175 12:11:32.063842 EX_ROW_EN[1] = 0x0
2176 12:11:32.063928 LP4Y_EN = 0x0
2177 12:11:32.066896 WORK_FSP = 0x0
2178 12:11:32.066983 WL = 0x4
2179 12:11:32.070297 RL = 0x4
2180 12:11:32.070388 BL = 0x2
2181 12:11:32.074049 RPST = 0x0
2182 12:11:32.077206 RD_PRE = 0x0
2183 12:11:32.077295 WR_PRE = 0x1
2184 12:11:32.080467 WR_PST = 0x0
2185 12:11:32.080553 DBI_WR = 0x0
2186 12:11:32.083623 DBI_RD = 0x0
2187 12:11:32.083712 OTF = 0x1
2188 12:11:32.086858 ===================================
2189 12:11:32.090110 ===================================
2190 12:11:32.093268 ANA top config
2191 12:11:32.096478 ===================================
2192 12:11:32.096565 DLL_ASYNC_EN = 0
2193 12:11:32.100158 ALL_SLAVE_EN = 0
2194 12:11:32.103477 NEW_RANK_MODE = 1
2195 12:11:32.106546 DLL_IDLE_MODE = 1
2196 12:11:32.106633 LP45_APHY_COMB_EN = 1
2197 12:11:32.109698 TX_ODT_DIS = 1
2198 12:11:32.113439 NEW_8X_MODE = 1
2199 12:11:32.116847 ===================================
2200 12:11:32.120081 ===================================
2201 12:11:32.123200 data_rate = 2400
2202 12:11:32.127036 CKR = 1
2203 12:11:32.127123 DQ_P2S_RATIO = 8
2204 12:11:32.130154 ===================================
2205 12:11:32.133318 CA_P2S_RATIO = 8
2206 12:11:32.136463 DQ_CA_OPEN = 0
2207 12:11:32.140105 DQ_SEMI_OPEN = 0
2208 12:11:32.143437 CA_SEMI_OPEN = 0
2209 12:11:32.146448 CA_FULL_RATE = 0
2210 12:11:32.149613 DQ_CKDIV4_EN = 0
2211 12:11:32.149726 CA_CKDIV4_EN = 0
2212 12:11:32.153075 CA_PREDIV_EN = 0
2213 12:11:32.156745 PH8_DLY = 17
2214 12:11:32.159705 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2215 12:11:32.162779 DQ_AAMCK_DIV = 4
2216 12:11:32.166594 CA_AAMCK_DIV = 4
2217 12:11:32.166705 CA_ADMCK_DIV = 4
2218 12:11:32.169397 DQ_TRACK_CA_EN = 0
2219 12:11:32.172988 CA_PICK = 1200
2220 12:11:32.175988 CA_MCKIO = 1200
2221 12:11:32.179770 MCKIO_SEMI = 0
2222 12:11:32.182881 PLL_FREQ = 2366
2223 12:11:32.186121 DQ_UI_PI_RATIO = 32
2224 12:11:32.186232 CA_UI_PI_RATIO = 0
2225 12:11:32.189318 ===================================
2226 12:11:32.192557 ===================================
2227 12:11:32.196351 memory_type:LPDDR4
2228 12:11:32.199556 GP_NUM : 10
2229 12:11:32.199664 SRAM_EN : 1
2230 12:11:32.202861 MD32_EN : 0
2231 12:11:32.206083 ===================================
2232 12:11:32.209272 [ANA_INIT] >>>>>>>>>>>>>>
2233 12:11:32.213012 <<<<<< [CONFIGURE PHASE]: ANA_TX
2234 12:11:32.216146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2235 12:11:32.219136 ===================================
2236 12:11:32.219242 data_rate = 2400,PCW = 0X5b00
2237 12:11:32.222350 ===================================
2238 12:11:32.226134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2239 12:11:32.232388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2240 12:11:32.239415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2241 12:11:32.242637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2242 12:11:32.246033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2243 12:11:32.249223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2244 12:11:32.252842 [ANA_INIT] flow start
2245 12:11:32.256427 [ANA_INIT] PLL >>>>>>>>
2246 12:11:32.256544 [ANA_INIT] PLL <<<<<<<<
2247 12:11:32.259155 [ANA_INIT] MIDPI >>>>>>>>
2248 12:11:32.262506 [ANA_INIT] MIDPI <<<<<<<<
2249 12:11:32.262616 [ANA_INIT] DLL >>>>>>>>
2250 12:11:32.266156 [ANA_INIT] DLL <<<<<<<<
2251 12:11:32.268987 [ANA_INIT] flow end
2252 12:11:32.272649 ============ LP4 DIFF to SE enter ============
2253 12:11:32.276015 ============ LP4 DIFF to SE exit ============
2254 12:11:32.279505 [ANA_INIT] <<<<<<<<<<<<<
2255 12:11:32.282380 [Flow] Enable top DCM control >>>>>
2256 12:11:32.285942 [Flow] Enable top DCM control <<<<<
2257 12:11:32.288907 Enable DLL master slave shuffle
2258 12:11:32.292735 ==============================================================
2259 12:11:32.295912 Gating Mode config
2260 12:11:32.302342 ==============================================================
2261 12:11:32.302437 Config description:
2262 12:11:32.312459 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2263 12:11:32.319234 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2264 12:11:32.322507 SELPH_MODE 0: By rank 1: By Phase
2265 12:11:32.329023 ==============================================================
2266 12:11:32.332254 GAT_TRACK_EN = 1
2267 12:11:32.335340 RX_GATING_MODE = 2
2268 12:11:32.338613 RX_GATING_TRACK_MODE = 2
2269 12:11:32.342412 SELPH_MODE = 1
2270 12:11:32.345559 PICG_EARLY_EN = 1
2271 12:11:32.348696 VALID_LAT_VALUE = 1
2272 12:11:32.352569 ==============================================================
2273 12:11:32.355481 Enter into Gating configuration >>>>
2274 12:11:32.358644 Exit from Gating configuration <<<<
2275 12:11:32.361871 Enter into DVFS_PRE_config >>>>>
2276 12:11:32.375533 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2277 12:11:32.375656 Exit from DVFS_PRE_config <<<<<
2278 12:11:32.378483 Enter into PICG configuration >>>>
2279 12:11:32.381957 Exit from PICG configuration <<<<
2280 12:11:32.385443 [RX_INPUT] configuration >>>>>
2281 12:11:32.388257 [RX_INPUT] configuration <<<<<
2282 12:11:32.395290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2283 12:11:32.398384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2284 12:11:32.405500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2285 12:11:32.412007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2286 12:11:32.418231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2287 12:11:32.425030 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2288 12:11:32.428312 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2289 12:11:32.431578 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2290 12:11:32.435358 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2291 12:11:32.441727 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2292 12:11:32.444885 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2293 12:11:32.448119 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2294 12:11:32.451644 ===================================
2295 12:11:32.454846 LPDDR4 DRAM CONFIGURATION
2296 12:11:32.458284 ===================================
2297 12:11:32.458380 EX_ROW_EN[0] = 0x0
2298 12:11:32.461377 EX_ROW_EN[1] = 0x0
2299 12:11:32.464641 LP4Y_EN = 0x0
2300 12:11:32.464729 WORK_FSP = 0x0
2301 12:11:32.467861 WL = 0x4
2302 12:11:32.467942 RL = 0x4
2303 12:11:32.471588 BL = 0x2
2304 12:11:32.471694 RPST = 0x0
2305 12:11:32.474738 RD_PRE = 0x0
2306 12:11:32.474820 WR_PRE = 0x1
2307 12:11:32.478150 WR_PST = 0x0
2308 12:11:32.478231 DBI_WR = 0x0
2309 12:11:32.481260 DBI_RD = 0x0
2310 12:11:32.481351 OTF = 0x1
2311 12:11:32.484385 ===================================
2312 12:11:32.487833 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2313 12:11:32.494401 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2314 12:11:32.497953 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 12:11:32.500897 ===================================
2316 12:11:32.504490 LPDDR4 DRAM CONFIGURATION
2317 12:11:32.507680 ===================================
2318 12:11:32.507762 EX_ROW_EN[0] = 0x10
2319 12:11:32.510883 EX_ROW_EN[1] = 0x0
2320 12:11:32.514715 LP4Y_EN = 0x0
2321 12:11:32.514798 WORK_FSP = 0x0
2322 12:11:32.517910 WL = 0x4
2323 12:11:32.517991 RL = 0x4
2324 12:11:32.521081 BL = 0x2
2325 12:11:32.521167 RPST = 0x0
2326 12:11:32.524741 RD_PRE = 0x0
2327 12:11:32.524815 WR_PRE = 0x1
2328 12:11:32.527879 WR_PST = 0x0
2329 12:11:32.527951 DBI_WR = 0x0
2330 12:11:32.531046 DBI_RD = 0x0
2331 12:11:32.531135 OTF = 0x1
2332 12:11:32.534208 ===================================
2333 12:11:32.541090 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2334 12:11:32.541180 ==
2335 12:11:32.544200 Dram Type= 6, Freq= 0, CH_0, rank 0
2336 12:11:32.547399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2337 12:11:32.551176 ==
2338 12:11:32.551263 [Duty_Offset_Calibration]
2339 12:11:32.554394 B0:2 B1:0 CA:4
2340 12:11:32.554480
2341 12:11:32.557514 [DutyScan_Calibration_Flow] k_type=0
2342 12:11:32.566188
2343 12:11:32.566284 ==CLK 0==
2344 12:11:32.569285 Final CLK duty delay cell = 0
2345 12:11:32.572268 [0] MAX Duty = 5156%(X100), DQS PI = 14
2346 12:11:32.575944 [0] MIN Duty = 5000%(X100), DQS PI = 8
2347 12:11:32.578975 [0] AVG Duty = 5078%(X100)
2348 12:11:32.579063
2349 12:11:32.582133 CH0 CLK Duty spec in!! Max-Min= 156%
2350 12:11:32.585715 [DutyScan_Calibration_Flow] ====Done====
2351 12:11:32.585825
2352 12:11:32.589106 [DutyScan_Calibration_Flow] k_type=1
2353 12:11:32.605212
2354 12:11:32.605327 ==DQS 0 ==
2355 12:11:32.608224 Final DQS duty delay cell = 0
2356 12:11:32.612124 [0] MAX Duty = 5156%(X100), DQS PI = 4
2357 12:11:32.615339 [0] MIN Duty = 5093%(X100), DQS PI = 2
2358 12:11:32.615425 [0] AVG Duty = 5124%(X100)
2359 12:11:32.618405
2360 12:11:32.618488 ==DQS 1 ==
2361 12:11:32.621653 Final DQS duty delay cell = 0
2362 12:11:32.625361 [0] MAX Duty = 5125%(X100), DQS PI = 6
2363 12:11:32.628673 [0] MIN Duty = 5000%(X100), DQS PI = 0
2364 12:11:32.628760 [0] AVG Duty = 5062%(X100)
2365 12:11:32.631727
2366 12:11:32.634928 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2367 12:11:32.635015
2368 12:11:32.638095 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2369 12:11:32.641897 [DutyScan_Calibration_Flow] ====Done====
2370 12:11:32.641983
2371 12:11:32.644956 [DutyScan_Calibration_Flow] k_type=3
2372 12:11:32.661697
2373 12:11:32.661814 ==DQM 0 ==
2374 12:11:32.664886 Final DQM duty delay cell = 0
2375 12:11:32.668017 [0] MAX Duty = 5125%(X100), DQS PI = 20
2376 12:11:32.671184 [0] MIN Duty = 4844%(X100), DQS PI = 54
2377 12:11:32.674417 [0] AVG Duty = 4984%(X100)
2378 12:11:32.674511
2379 12:11:32.674579 ==DQM 1 ==
2380 12:11:32.678131 Final DQM duty delay cell = 0
2381 12:11:32.681365 [0] MAX Duty = 4969%(X100), DQS PI = 2
2382 12:11:32.684370 [0] MIN Duty = 4876%(X100), DQS PI = 28
2383 12:11:32.687587 [0] AVG Duty = 4922%(X100)
2384 12:11:32.687675
2385 12:11:32.691397 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2386 12:11:32.691482
2387 12:11:32.694335 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2388 12:11:32.697457 [DutyScan_Calibration_Flow] ====Done====
2389 12:11:32.697545
2390 12:11:32.700861 [DutyScan_Calibration_Flow] k_type=2
2391 12:11:32.717931
2392 12:11:32.718059 ==DQ 0 ==
2393 12:11:32.721107 Final DQ duty delay cell = 0
2394 12:11:32.724367 [0] MAX Duty = 5125%(X100), DQS PI = 18
2395 12:11:32.727505 [0] MIN Duty = 5000%(X100), DQS PI = 10
2396 12:11:32.727586 [0] AVG Duty = 5062%(X100)
2397 12:11:32.727675
2398 12:11:32.731268 ==DQ 1 ==
2399 12:11:32.734333 Final DQ duty delay cell = 0
2400 12:11:32.737480 [0] MAX Duty = 5125%(X100), DQS PI = 4
2401 12:11:32.740752 [0] MIN Duty = 4938%(X100), DQS PI = 14
2402 12:11:32.740840 [0] AVG Duty = 5031%(X100)
2403 12:11:32.740907
2404 12:11:32.744653 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2405 12:11:32.747834
2406 12:11:32.751084 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2407 12:11:32.754072 [DutyScan_Calibration_Flow] ====Done====
2408 12:11:32.754181 ==
2409 12:11:32.757826 Dram Type= 6, Freq= 0, CH_1, rank 0
2410 12:11:32.761024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2411 12:11:32.761114 ==
2412 12:11:32.763985 [Duty_Offset_Calibration]
2413 12:11:32.764083 B0:0 B1:-1 CA:3
2414 12:11:32.764153
2415 12:11:32.767207 [DutyScan_Calibration_Flow] k_type=0
2416 12:11:32.776657
2417 12:11:32.776768 ==CLK 0==
2418 12:11:32.780608 Final CLK duty delay cell = -4
2419 12:11:32.783681 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2420 12:11:32.786911 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2421 12:11:32.789949 [-4] AVG Duty = 4938%(X100)
2422 12:11:32.790055
2423 12:11:32.793163 CH1 CLK Duty spec in!! Max-Min= 124%
2424 12:11:32.796883 [DutyScan_Calibration_Flow] ====Done====
2425 12:11:32.796990
2426 12:11:32.799804 [DutyScan_Calibration_Flow] k_type=1
2427 12:11:32.816331
2428 12:11:32.816479 ==DQS 0 ==
2429 12:11:32.818669 Final DQS duty delay cell = 0
2430 12:11:32.822267 [0] MAX Duty = 5187%(X100), DQS PI = 18
2431 12:11:32.825487 [0] MIN Duty = 4907%(X100), DQS PI = 38
2432 12:11:32.829311 [0] AVG Duty = 5047%(X100)
2433 12:11:32.829401
2434 12:11:32.829470 ==DQS 1 ==
2435 12:11:32.832372 Final DQS duty delay cell = -4
2436 12:11:32.835615 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2437 12:11:32.838934 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2438 12:11:32.842168 [-4] AVG Duty = 4937%(X100)
2439 12:11:32.842257
2440 12:11:32.845276 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2441 12:11:32.845363
2442 12:11:32.848470 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2443 12:11:32.852223 [DutyScan_Calibration_Flow] ====Done====
2444 12:11:32.852313
2445 12:11:32.855356 [DutyScan_Calibration_Flow] k_type=3
2446 12:11:32.872674
2447 12:11:32.872807 ==DQM 0 ==
2448 12:11:32.875716 Final DQM duty delay cell = 0
2449 12:11:32.878851 [0] MAX Duty = 5031%(X100), DQS PI = 26
2450 12:11:32.882575 [0] MIN Duty = 4813%(X100), DQS PI = 38
2451 12:11:32.885622 [0] AVG Duty = 4922%(X100)
2452 12:11:32.885717
2453 12:11:32.885786 ==DQM 1 ==
2454 12:11:32.889360 Final DQM duty delay cell = 0
2455 12:11:32.892530 [0] MAX Duty = 5000%(X100), DQS PI = 34
2456 12:11:32.895886 [0] MIN Duty = 4844%(X100), DQS PI = 0
2457 12:11:32.899208 [0] AVG Duty = 4922%(X100)
2458 12:11:32.899295
2459 12:11:32.902369 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2460 12:11:32.902504
2461 12:11:32.905345 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2462 12:11:32.908913 [DutyScan_Calibration_Flow] ====Done====
2463 12:11:32.909022
2464 12:11:32.911865 [DutyScan_Calibration_Flow] k_type=2
2465 12:11:32.927776
2466 12:11:32.927899 ==DQ 0 ==
2467 12:11:32.931413 Final DQ duty delay cell = -4
2468 12:11:32.934428 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2469 12:11:32.937675 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2470 12:11:32.941492 [-4] AVG Duty = 4937%(X100)
2471 12:11:32.941587
2472 12:11:32.941687 ==DQ 1 ==
2473 12:11:32.944657 Final DQ duty delay cell = 0
2474 12:11:32.947777 [0] MAX Duty = 5062%(X100), DQS PI = 34
2475 12:11:32.950966 [0] MIN Duty = 4844%(X100), DQS PI = 62
2476 12:11:32.954242 [0] AVG Duty = 4953%(X100)
2477 12:11:32.954329
2478 12:11:32.958073 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2479 12:11:32.958160
2480 12:11:32.961172 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2481 12:11:32.964393 [DutyScan_Calibration_Flow] ====Done====
2482 12:11:32.968165 nWR fixed to 30
2483 12:11:32.971409 [ModeRegInit_LP4] CH0 RK0
2484 12:11:32.971497 [ModeRegInit_LP4] CH0 RK1
2485 12:11:32.974680 [ModeRegInit_LP4] CH1 RK0
2486 12:11:32.977835 [ModeRegInit_LP4] CH1 RK1
2487 12:11:32.977923 match AC timing 7
2488 12:11:32.984809 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2489 12:11:32.987931 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2490 12:11:32.991048 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2491 12:11:32.998194 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2492 12:11:33.001307 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2493 12:11:33.001400 ==
2494 12:11:33.004518 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 12:11:33.008232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 12:11:33.008326 ==
2497 12:11:33.014972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 12:11:33.020988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2499 12:11:33.028631 [CA 0] Center 39 (9~70) winsize 62
2500 12:11:33.031636 [CA 1] Center 38 (8~69) winsize 62
2501 12:11:33.034629 [CA 2] Center 35 (5~66) winsize 62
2502 12:11:33.038033 [CA 3] Center 35 (5~66) winsize 62
2503 12:11:33.041293 [CA 4] Center 34 (3~65) winsize 63
2504 12:11:33.045165 [CA 5] Center 33 (3~63) winsize 61
2505 12:11:33.045257
2506 12:11:33.048409 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2507 12:11:33.048497
2508 12:11:33.051639 [CATrainingPosCal] consider 1 rank data
2509 12:11:33.054914 u2DelayCellTimex100 = 270/100 ps
2510 12:11:33.058099 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 12:11:33.061863 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2512 12:11:33.068650 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 12:11:33.071849 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 12:11:33.075074 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2515 12:11:33.078294 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2516 12:11:33.078379
2517 12:11:33.081424 CA PerBit enable=1, Macro0, CA PI delay=33
2518 12:11:33.081553
2519 12:11:33.085076 [CBTSetCACLKResult] CA Dly = 33
2520 12:11:33.085190 CS Dly: 7 (0~38)
2521 12:11:33.085305 ==
2522 12:11:33.088182 Dram Type= 6, Freq= 0, CH_0, rank 1
2523 12:11:33.095108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 12:11:33.095243 ==
2525 12:11:33.098303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 12:11:33.105163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2527 12:11:33.113992 [CA 0] Center 39 (9~70) winsize 62
2528 12:11:33.117229 [CA 1] Center 39 (9~70) winsize 62
2529 12:11:33.121046 [CA 2] Center 35 (5~66) winsize 62
2530 12:11:33.123814 [CA 3] Center 35 (5~66) winsize 62
2531 12:11:33.127457 [CA 4] Center 34 (4~65) winsize 62
2532 12:11:33.130901 [CA 5] Center 33 (3~64) winsize 62
2533 12:11:33.131012
2534 12:11:33.133860 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2535 12:11:33.133969
2536 12:11:33.137482 [CATrainingPosCal] consider 2 rank data
2537 12:11:33.140404 u2DelayCellTimex100 = 270/100 ps
2538 12:11:33.143886 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2539 12:11:33.150134 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2540 12:11:33.153908 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 12:11:33.157163 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2542 12:11:33.160429 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2543 12:11:33.163611 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2544 12:11:33.163721
2545 12:11:33.167077 CA PerBit enable=1, Macro0, CA PI delay=33
2546 12:11:33.167190
2547 12:11:33.170231 [CBTSetCACLKResult] CA Dly = 33
2548 12:11:33.173496 CS Dly: 8 (0~41)
2549 12:11:33.173615
2550 12:11:33.176877 ----->DramcWriteLeveling(PI) begin...
2551 12:11:33.177011 ==
2552 12:11:33.179956 Dram Type= 6, Freq= 0, CH_0, rank 0
2553 12:11:33.183173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 12:11:33.183251 ==
2555 12:11:33.186911 Write leveling (Byte 0): 31 => 31
2556 12:11:33.189975 Write leveling (Byte 1): 26 => 26
2557 12:11:33.193209 DramcWriteLeveling(PI) end<-----
2558 12:11:33.193314
2559 12:11:33.193407 ==
2560 12:11:33.196910 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 12:11:33.200055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 12:11:33.200134 ==
2563 12:11:33.203320 [Gating] SW mode calibration
2564 12:11:33.209691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2565 12:11:33.216023 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2566 12:11:33.219276 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2567 12:11:33.223197 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2568 12:11:33.229157 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 12:11:33.232834 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 12:11:33.236202 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2571 12:11:33.242704 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2572 12:11:33.246318 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2573 12:11:33.249307 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2574 12:11:33.255983 1 0 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
2575 12:11:33.259200 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 12:11:33.262408 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 12:11:33.269386 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 12:11:33.272448 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2579 12:11:33.276065 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2580 12:11:33.282486 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2581 12:11:33.285675 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2582 12:11:33.288902 1 1 0 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
2583 12:11:33.295613 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 12:11:33.299414 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 12:11:33.302550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 12:11:33.308922 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 12:11:33.312619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2588 12:11:33.315734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2589 12:11:33.322230 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2590 12:11:33.325371 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2591 12:11:33.328590 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 12:11:33.335382 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 12:11:33.338832 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 12:11:33.341933 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 12:11:33.349016 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 12:11:33.352005 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 12:11:33.354992 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 12:11:33.361823 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 12:11:33.364964 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 12:11:33.368683 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 12:11:33.375238 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 12:11:33.378127 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 12:11:33.381909 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:11:33.388115 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2605 12:11:33.391979 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2606 12:11:33.395087 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2607 12:11:33.398372 Total UI for P1: 0, mck2ui 16
2608 12:11:33.401319 best dqsien dly found for B0: ( 1, 3, 26)
2609 12:11:33.408255 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 12:11:33.408356 Total UI for P1: 0, mck2ui 16
2611 12:11:33.411369 best dqsien dly found for B1: ( 1, 4, 0)
2612 12:11:33.418344 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2613 12:11:33.421529 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2614 12:11:33.421622
2615 12:11:33.424730 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2616 12:11:33.428436 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2617 12:11:33.431595 [Gating] SW calibration Done
2618 12:11:33.431685 ==
2619 12:11:33.434924 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 12:11:33.438172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 12:11:33.438261 ==
2622 12:11:33.441292 RX Vref Scan: 0
2623 12:11:33.441380
2624 12:11:33.441450 RX Vref 0 -> 0, step: 1
2625 12:11:33.441514
2626 12:11:33.444827 RX Delay -40 -> 252, step: 8
2627 12:11:33.447776 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2628 12:11:33.454439 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2629 12:11:33.457607 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2630 12:11:33.461259 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2631 12:11:33.464197 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2632 12:11:33.467420 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2633 12:11:33.474541 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2634 12:11:33.477640 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2635 12:11:33.481235 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2636 12:11:33.484396 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2637 12:11:33.487430 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2638 12:11:33.490703 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2639 12:11:33.497686 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2640 12:11:33.500884 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2641 12:11:33.503973 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2642 12:11:33.507579 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2643 12:11:33.510665 ==
2644 12:11:33.513928 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 12:11:33.516985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 12:11:33.517068 ==
2647 12:11:33.517151 DQS Delay:
2648 12:11:33.520403 DQS0 = 0, DQS1 = 0
2649 12:11:33.520484 DQM Delay:
2650 12:11:33.524156 DQM0 = 120, DQM1 = 107
2651 12:11:33.524242 DQ Delay:
2652 12:11:33.527447 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2653 12:11:33.530717 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2654 12:11:33.533878 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2655 12:11:33.537150 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2656 12:11:33.537228
2657 12:11:33.537294
2658 12:11:33.537364 ==
2659 12:11:33.540259 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 12:11:33.547034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 12:11:33.547114 ==
2662 12:11:33.547187
2663 12:11:33.547249
2664 12:11:33.547309 TX Vref Scan disable
2665 12:11:33.550606 == TX Byte 0 ==
2666 12:11:33.554212 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2667 12:11:33.560848 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2668 12:11:33.560939 == TX Byte 1 ==
2669 12:11:33.563843 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2670 12:11:33.570625 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2671 12:11:33.570719 ==
2672 12:11:33.573775 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:11:33.577020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:11:33.577105 ==
2675 12:11:33.588822 TX Vref=22, minBit 1, minWin=25, winSum=412
2676 12:11:33.591883 TX Vref=24, minBit 3, minWin=25, winSum=416
2677 12:11:33.595191 TX Vref=26, minBit 15, minWin=25, winSum=422
2678 12:11:33.598877 TX Vref=28, minBit 0, minWin=26, winSum=424
2679 12:11:33.602116 TX Vref=30, minBit 2, minWin=26, winSum=428
2680 12:11:33.608587 TX Vref=32, minBit 0, minWin=26, winSum=427
2681 12:11:33.612231 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30
2682 12:11:33.612320
2683 12:11:33.615267 Final TX Range 1 Vref 30
2684 12:11:33.615354
2685 12:11:33.615421 ==
2686 12:11:33.618372 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 12:11:33.622205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 12:11:33.622289 ==
2689 12:11:33.625507
2690 12:11:33.625597
2691 12:11:33.625675 TX Vref Scan disable
2692 12:11:33.628673 == TX Byte 0 ==
2693 12:11:33.631839 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2694 12:11:33.638850 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2695 12:11:33.638941 == TX Byte 1 ==
2696 12:11:33.642116 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2697 12:11:33.648524 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2698 12:11:33.648612
2699 12:11:33.648687 [DATLAT]
2700 12:11:33.648765 Freq=1200, CH0 RK0
2701 12:11:33.648830
2702 12:11:33.651607 DATLAT Default: 0xd
2703 12:11:33.651683 0, 0xFFFF, sum = 0
2704 12:11:33.654798 1, 0xFFFF, sum = 0
2705 12:11:33.654879 2, 0xFFFF, sum = 0
2706 12:11:33.658190 3, 0xFFFF, sum = 0
2707 12:11:33.661862 4, 0xFFFF, sum = 0
2708 12:11:33.661948 5, 0xFFFF, sum = 0
2709 12:11:33.665408 6, 0xFFFF, sum = 0
2710 12:11:33.665531 7, 0xFFFF, sum = 0
2711 12:11:33.668436 8, 0xFFFF, sum = 0
2712 12:11:33.668522 9, 0xFFFF, sum = 0
2713 12:11:33.671384 10, 0xFFFF, sum = 0
2714 12:11:33.671506 11, 0xFFFF, sum = 0
2715 12:11:33.675190 12, 0x0, sum = 1
2716 12:11:33.675314 13, 0x0, sum = 2
2717 12:11:33.678318 14, 0x0, sum = 3
2718 12:11:33.678401 15, 0x0, sum = 4
2719 12:11:33.681455 best_step = 13
2720 12:11:33.681530
2721 12:11:33.681594 ==
2722 12:11:33.684545 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 12:11:33.688461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 12:11:33.688550 ==
2725 12:11:33.688629 RX Vref Scan: 1
2726 12:11:33.691665
2727 12:11:33.691739 Set Vref Range= 32 -> 127
2728 12:11:33.691803
2729 12:11:33.694777 RX Vref 32 -> 127, step: 1
2730 12:11:33.694855
2731 12:11:33.698576 RX Delay -21 -> 252, step: 4
2732 12:11:33.698654
2733 12:11:33.701566 Set Vref, RX VrefLevel [Byte0]: 32
2734 12:11:33.704782 [Byte1]: 32
2735 12:11:33.704864
2736 12:11:33.707930 Set Vref, RX VrefLevel [Byte0]: 33
2737 12:11:33.711197 [Byte1]: 33
2738 12:11:33.715011
2739 12:11:33.715086 Set Vref, RX VrefLevel [Byte0]: 34
2740 12:11:33.718558 [Byte1]: 34
2741 12:11:33.723118
2742 12:11:33.723203 Set Vref, RX VrefLevel [Byte0]: 35
2743 12:11:33.726167 [Byte1]: 35
2744 12:11:33.731201
2745 12:11:33.731284 Set Vref, RX VrefLevel [Byte0]: 36
2746 12:11:33.734470 [Byte1]: 36
2747 12:11:33.738902
2748 12:11:33.738982 Set Vref, RX VrefLevel [Byte0]: 37
2749 12:11:33.741980 [Byte1]: 37
2750 12:11:33.746469
2751 12:11:33.746547 Set Vref, RX VrefLevel [Byte0]: 38
2752 12:11:33.750226 [Byte1]: 38
2753 12:11:33.754562
2754 12:11:33.754640 Set Vref, RX VrefLevel [Byte0]: 39
2755 12:11:33.757797 [Byte1]: 39
2756 12:11:33.762655
2757 12:11:33.762738 Set Vref, RX VrefLevel [Byte0]: 40
2758 12:11:33.765714 [Byte1]: 40
2759 12:11:33.770784
2760 12:11:33.770868 Set Vref, RX VrefLevel [Byte0]: 41
2761 12:11:33.773694 [Byte1]: 41
2762 12:11:33.778451
2763 12:11:33.778562 Set Vref, RX VrefLevel [Byte0]: 42
2764 12:11:33.781696 [Byte1]: 42
2765 12:11:33.786449
2766 12:11:33.786555 Set Vref, RX VrefLevel [Byte0]: 43
2767 12:11:33.789413 [Byte1]: 43
2768 12:11:33.794451
2769 12:11:33.794554 Set Vref, RX VrefLevel [Byte0]: 44
2770 12:11:33.797545 [Byte1]: 44
2771 12:11:33.802377
2772 12:11:33.802492 Set Vref, RX VrefLevel [Byte0]: 45
2773 12:11:33.805638 [Byte1]: 45
2774 12:11:33.810076
2775 12:11:33.810187 Set Vref, RX VrefLevel [Byte0]: 46
2776 12:11:33.813180 [Byte1]: 46
2777 12:11:33.818347
2778 12:11:33.818458 Set Vref, RX VrefLevel [Byte0]: 47
2779 12:11:33.821477 [Byte1]: 47
2780 12:11:33.826371
2781 12:11:33.826482 Set Vref, RX VrefLevel [Byte0]: 48
2782 12:11:33.829008 [Byte1]: 48
2783 12:11:33.834078
2784 12:11:33.834188 Set Vref, RX VrefLevel [Byte0]: 49
2785 12:11:33.837232 [Byte1]: 49
2786 12:11:33.841729
2787 12:11:33.841841 Set Vref, RX VrefLevel [Byte0]: 50
2788 12:11:33.844895 [Byte1]: 50
2789 12:11:33.849897
2790 12:11:33.850029 Set Vref, RX VrefLevel [Byte0]: 51
2791 12:11:33.852966 [Byte1]: 51
2792 12:11:33.857571
2793 12:11:33.857690 Set Vref, RX VrefLevel [Byte0]: 52
2794 12:11:33.860671 [Byte1]: 52
2795 12:11:33.865669
2796 12:11:33.865804 Set Vref, RX VrefLevel [Byte0]: 53
2797 12:11:33.868738 [Byte1]: 53
2798 12:11:33.873494
2799 12:11:33.873615 Set Vref, RX VrefLevel [Byte0]: 54
2800 12:11:33.876924 [Byte1]: 54
2801 12:11:33.881666
2802 12:11:33.881869 Set Vref, RX VrefLevel [Byte0]: 55
2803 12:11:33.884700 [Byte1]: 55
2804 12:11:33.889436
2805 12:11:33.889603 Set Vref, RX VrefLevel [Byte0]: 56
2806 12:11:33.893002 [Byte1]: 56
2807 12:11:33.897136
2808 12:11:33.897255 Set Vref, RX VrefLevel [Byte0]: 57
2809 12:11:33.900340 [Byte1]: 57
2810 12:11:33.905309
2811 12:11:33.905398 Set Vref, RX VrefLevel [Byte0]: 58
2812 12:11:33.908475 [Byte1]: 58
2813 12:11:33.912983
2814 12:11:33.913071 Set Vref, RX VrefLevel [Byte0]: 59
2815 12:11:33.916756 [Byte1]: 59
2816 12:11:33.921343
2817 12:11:33.921430 Set Vref, RX VrefLevel [Byte0]: 60
2818 12:11:33.924542 [Byte1]: 60
2819 12:11:33.929397
2820 12:11:33.929483 Set Vref, RX VrefLevel [Byte0]: 61
2821 12:11:33.932232 [Byte1]: 61
2822 12:11:33.936753
2823 12:11:33.936838 Set Vref, RX VrefLevel [Byte0]: 62
2824 12:11:33.940615 [Byte1]: 62
2825 12:11:33.945204
2826 12:11:33.945290 Set Vref, RX VrefLevel [Byte0]: 63
2827 12:11:33.948298 [Byte1]: 63
2828 12:11:33.952671
2829 12:11:33.952777 Set Vref, RX VrefLevel [Byte0]: 64
2830 12:11:33.955860 [Byte1]: 64
2831 12:11:33.961043
2832 12:11:33.961129 Set Vref, RX VrefLevel [Byte0]: 65
2833 12:11:33.964157 [Byte1]: 65
2834 12:11:33.968712
2835 12:11:33.968797 Set Vref, RX VrefLevel [Byte0]: 66
2836 12:11:33.971852 [Byte1]: 66
2837 12:11:33.976809
2838 12:11:33.976897 Set Vref, RX VrefLevel [Byte0]: 67
2839 12:11:33.979802 [Byte1]: 67
2840 12:11:33.984490
2841 12:11:33.984578 Final RX Vref Byte 0 = 57 to rank0
2842 12:11:33.988127 Final RX Vref Byte 1 = 49 to rank0
2843 12:11:33.991008 Final RX Vref Byte 0 = 57 to rank1
2844 12:11:33.994509 Final RX Vref Byte 1 = 49 to rank1==
2845 12:11:33.997967 Dram Type= 6, Freq= 0, CH_0, rank 0
2846 12:11:34.004491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 12:11:34.004585 ==
2848 12:11:34.004665 DQS Delay:
2849 12:11:34.004731 DQS0 = 0, DQS1 = 0
2850 12:11:34.007531 DQM Delay:
2851 12:11:34.007636 DQM0 = 119, DQM1 = 105
2852 12:11:34.011280 DQ Delay:
2853 12:11:34.014217 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2854 12:11:34.017392 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2855 12:11:34.021244 DQ8 =96, DQ9 =90, DQ10 =106, DQ11 =100
2856 12:11:34.024630 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2857 12:11:34.024718
2858 12:11:34.024787
2859 12:11:34.030935 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2860 12:11:34.034479 CH0 RK0: MR19=403, MR18=FC
2861 12:11:34.040855 CH0_RK0: MR19=0x403, MR18=0xFC, DQSOSC=410, MR23=63, INC=39, DEC=26
2862 12:11:34.040948
2863 12:11:34.043994 ----->DramcWriteLeveling(PI) begin...
2864 12:11:34.044104 ==
2865 12:11:34.047236 Dram Type= 6, Freq= 0, CH_0, rank 1
2866 12:11:34.051034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2867 12:11:34.051132 ==
2868 12:11:34.054324 Write leveling (Byte 0): 33 => 33
2869 12:11:34.057404 Write leveling (Byte 1): 27 => 27
2870 12:11:34.060569 DramcWriteLeveling(PI) end<-----
2871 12:11:34.060644
2872 12:11:34.060708 ==
2873 12:11:34.063828 Dram Type= 6, Freq= 0, CH_0, rank 1
2874 12:11:34.070884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2875 12:11:34.070970 ==
2876 12:11:34.071039 [Gating] SW mode calibration
2877 12:11:34.080866 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2878 12:11:34.084100 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2879 12:11:34.087200 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2880 12:11:34.093753 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 12:11:34.096907 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 12:11:34.100633 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 12:11:34.107491 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 12:11:34.110507 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 12:11:34.114072 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2886 12:11:34.120614 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
2887 12:11:34.123949 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2888 12:11:34.126898 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 12:11:34.133711 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 12:11:34.136865 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 12:11:34.140512 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 12:11:34.146891 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 12:11:34.150067 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2894 12:11:34.153956 1 0 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2895 12:11:34.160224 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2896 12:11:34.163569 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 12:11:34.166609 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 12:11:34.173444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 12:11:34.176642 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 12:11:34.179908 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2901 12:11:34.186389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2902 12:11:34.190158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2903 12:11:34.193135 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2904 12:11:34.199597 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 12:11:34.203200 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 12:11:34.206154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 12:11:34.213071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 12:11:34.216627 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 12:11:34.219645 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 12:11:34.226196 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 12:11:34.229429 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 12:11:34.232667 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 12:11:34.239320 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 12:11:34.242493 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 12:11:34.246274 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 12:11:34.252565 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:11:34.255906 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2918 12:11:34.259670 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2919 12:11:34.262864 Total UI for P1: 0, mck2ui 16
2920 12:11:34.265895 best dqsien dly found for B0: ( 1, 3, 24)
2921 12:11:34.272255 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 12:11:34.272346 Total UI for P1: 0, mck2ui 16
2923 12:11:34.279278 best dqsien dly found for B1: ( 1, 3, 28)
2924 12:11:34.282391 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2925 12:11:34.285592 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2926 12:11:34.285678
2927 12:11:34.288885 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2928 12:11:34.292104 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2929 12:11:34.295775 [Gating] SW calibration Done
2930 12:11:34.295889 ==
2931 12:11:34.298886 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 12:11:34.302195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 12:11:34.302281 ==
2934 12:11:34.305799 RX Vref Scan: 0
2935 12:11:34.305913
2936 12:11:34.306013 RX Vref 0 -> 0, step: 1
2937 12:11:34.306118
2938 12:11:34.309178 RX Delay -40 -> 252, step: 8
2939 12:11:34.312056 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2940 12:11:34.318637 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2941 12:11:34.322273 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2942 12:11:34.325407 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2943 12:11:34.328898 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2944 12:11:34.331976 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2945 12:11:34.338987 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2946 12:11:34.341999 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2947 12:11:34.345259 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2948 12:11:34.348920 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2949 12:11:34.352099 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2950 12:11:34.358567 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2951 12:11:34.361852 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2952 12:11:34.365010 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2953 12:11:34.368828 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2954 12:11:34.371955 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2955 12:11:34.375150 ==
2956 12:11:34.378383 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 12:11:34.381587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 12:11:34.381700 ==
2959 12:11:34.381798 DQS Delay:
2960 12:11:34.385385 DQS0 = 0, DQS1 = 0
2961 12:11:34.385493 DQM Delay:
2962 12:11:34.388550 DQM0 = 118, DQM1 = 106
2963 12:11:34.388657 DQ Delay:
2964 12:11:34.391787 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2965 12:11:34.394965 DQ4 =123, DQ5 =107, DQ6 =127, DQ7 =127
2966 12:11:34.398165 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2967 12:11:34.401600 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2968 12:11:34.401717
2969 12:11:34.401814
2970 12:11:34.401928 ==
2971 12:11:34.404856 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 12:11:34.411861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 12:11:34.411977 ==
2974 12:11:34.412105
2975 12:11:34.412180
2976 12:11:34.412278 TX Vref Scan disable
2977 12:11:34.414946 == TX Byte 0 ==
2978 12:11:34.418512 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2979 12:11:34.425105 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2980 12:11:34.425222 == TX Byte 1 ==
2981 12:11:34.428716 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2982 12:11:34.434837 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2983 12:11:34.434949 ==
2984 12:11:34.438393 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 12:11:34.441389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 12:11:34.441498 ==
2987 12:11:34.453590 TX Vref=22, minBit 13, minWin=25, winSum=421
2988 12:11:34.456639 TX Vref=24, minBit 0, minWin=26, winSum=424
2989 12:11:34.459925 TX Vref=26, minBit 2, minWin=26, winSum=428
2990 12:11:34.463117 TX Vref=28, minBit 10, minWin=26, winSum=428
2991 12:11:34.466935 TX Vref=30, minBit 12, minWin=26, winSum=433
2992 12:11:34.473355 TX Vref=32, minBit 10, minWin=26, winSum=427
2993 12:11:34.476606 [TxChooseVref] Worse bit 12, Min win 26, Win sum 433, Final Vref 30
2994 12:11:34.476718
2995 12:11:34.479763 Final TX Range 1 Vref 30
2996 12:11:34.479879
2997 12:11:34.479978 ==
2998 12:11:34.482922 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 12:11:34.489470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 12:11:34.489557 ==
3001 12:11:34.489625
3002 12:11:34.489690
3003 12:11:34.489751 TX Vref Scan disable
3004 12:11:34.493819 == TX Byte 0 ==
3005 12:11:34.497060 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3006 12:11:34.500311 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3007 12:11:34.503459 == TX Byte 1 ==
3008 12:11:34.506945 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3009 12:11:34.513849 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3010 12:11:34.513962
3011 12:11:34.514039 [DATLAT]
3012 12:11:34.514121 Freq=1200, CH0 RK1
3013 12:11:34.514221
3014 12:11:34.517065 DATLAT Default: 0xd
3015 12:11:34.517181 0, 0xFFFF, sum = 0
3016 12:11:34.520293 1, 0xFFFF, sum = 0
3017 12:11:34.523713 2, 0xFFFF, sum = 0
3018 12:11:34.523823 3, 0xFFFF, sum = 0
3019 12:11:34.526572 4, 0xFFFF, sum = 0
3020 12:11:34.526689 5, 0xFFFF, sum = 0
3021 12:11:34.530185 6, 0xFFFF, sum = 0
3022 12:11:34.530310 7, 0xFFFF, sum = 0
3023 12:11:34.533717 8, 0xFFFF, sum = 0
3024 12:11:34.533861 9, 0xFFFF, sum = 0
3025 12:11:34.536743 10, 0xFFFF, sum = 0
3026 12:11:34.536877 11, 0xFFFF, sum = 0
3027 12:11:34.539832 12, 0x0, sum = 1
3028 12:11:34.539945 13, 0x0, sum = 2
3029 12:11:34.543378 14, 0x0, sum = 3
3030 12:11:34.543493 15, 0x0, sum = 4
3031 12:11:34.546507 best_step = 13
3032 12:11:34.546615
3033 12:11:34.546710 ==
3034 12:11:34.549916 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 12:11:34.553699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 12:11:34.553840 ==
3037 12:11:34.553950 RX Vref Scan: 0
3038 12:11:34.554049
3039 12:11:34.556855 RX Vref 0 -> 0, step: 1
3040 12:11:34.556964
3041 12:11:34.559878 RX Delay -21 -> 252, step: 4
3042 12:11:34.563215 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3043 12:11:34.569818 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3044 12:11:34.573702 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3045 12:11:34.576948 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3046 12:11:34.580130 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3047 12:11:34.583386 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3048 12:11:34.589946 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3049 12:11:34.593231 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3050 12:11:34.596629 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3051 12:11:34.599854 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3052 12:11:34.603097 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3053 12:11:34.610009 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3054 12:11:34.613087 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3055 12:11:34.616316 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3056 12:11:34.620012 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3057 12:11:34.623389 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3058 12:11:34.626505 ==
3059 12:11:34.629615 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 12:11:34.633296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 12:11:34.633385 ==
3062 12:11:34.633472 DQS Delay:
3063 12:11:34.636430 DQS0 = 0, DQS1 = 0
3064 12:11:34.636516 DQM Delay:
3065 12:11:34.639619 DQM0 = 117, DQM1 = 106
3066 12:11:34.639705 DQ Delay:
3067 12:11:34.642777 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3068 12:11:34.646529 DQ4 =120, DQ5 =112, DQ6 =128, DQ7 =122
3069 12:11:34.649590 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3070 12:11:34.653105 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3071 12:11:34.653196
3072 12:11:34.653298
3073 12:11:34.662919 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3074 12:11:34.665977 CH0 RK1: MR19=303, MR18=FEFC
3075 12:11:34.669081 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3076 12:11:34.672306 [RxdqsGatingPostProcess] freq 1200
3077 12:11:34.679472 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3078 12:11:34.682632 best DQS0 dly(2T, 0.5T) = (0, 11)
3079 12:11:34.685848 best DQS1 dly(2T, 0.5T) = (0, 12)
3080 12:11:34.689216 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3081 12:11:34.692242 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3082 12:11:34.695603 best DQS0 dly(2T, 0.5T) = (0, 11)
3083 12:11:34.698888 best DQS1 dly(2T, 0.5T) = (0, 11)
3084 12:11:34.702218 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3085 12:11:34.705323 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3086 12:11:34.708635 Pre-setting of DQS Precalculation
3087 12:11:34.712425 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3088 12:11:34.712503 ==
3089 12:11:34.715466 Dram Type= 6, Freq= 0, CH_1, rank 0
3090 12:11:34.719038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 12:11:34.719113 ==
3092 12:11:34.725490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 12:11:34.731848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3094 12:11:34.740000 [CA 0] Center 38 (8~68) winsize 61
3095 12:11:34.743039 [CA 1] Center 37 (7~68) winsize 62
3096 12:11:34.746604 [CA 2] Center 35 (5~65) winsize 61
3097 12:11:34.749745 [CA 3] Center 34 (4~64) winsize 61
3098 12:11:34.752880 [CA 4] Center 34 (4~65) winsize 62
3099 12:11:34.756631 [CA 5] Center 33 (4~63) winsize 60
3100 12:11:34.756717
3101 12:11:34.759647 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 12:11:34.759733
3103 12:11:34.763261 [CATrainingPosCal] consider 1 rank data
3104 12:11:34.766307 u2DelayCellTimex100 = 270/100 ps
3105 12:11:34.769624 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3106 12:11:34.776280 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3107 12:11:34.779536 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3108 12:11:34.782665 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3109 12:11:34.786029 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3110 12:11:34.789824 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3111 12:11:34.789913
3112 12:11:34.792924 CA PerBit enable=1, Macro0, CA PI delay=33
3113 12:11:34.793012
3114 12:11:34.796097 [CBTSetCACLKResult] CA Dly = 33
3115 12:11:34.796179 CS Dly: 4 (0~35)
3116 12:11:34.799398 ==
3117 12:11:34.802659 Dram Type= 6, Freq= 0, CH_1, rank 1
3118 12:11:34.806006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 12:11:34.806092 ==
3120 12:11:34.809174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3121 12:11:34.816133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3122 12:11:34.825596 [CA 0] Center 37 (7~68) winsize 62
3123 12:11:34.828873 [CA 1] Center 38 (8~68) winsize 61
3124 12:11:34.832131 [CA 2] Center 35 (5~65) winsize 61
3125 12:11:34.835254 [CA 3] Center 33 (3~64) winsize 62
3126 12:11:34.838615 [CA 4] Center 34 (4~64) winsize 61
3127 12:11:34.841938 [CA 5] Center 33 (3~63) winsize 61
3128 12:11:34.842023
3129 12:11:34.845170 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3130 12:11:34.845257
3131 12:11:34.848718 [CATrainingPosCal] consider 2 rank data
3132 12:11:34.851783 u2DelayCellTimex100 = 270/100 ps
3133 12:11:34.855520 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3134 12:11:34.861730 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3135 12:11:34.865336 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3136 12:11:34.868390 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 12:11:34.871550 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 12:11:34.875226 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3139 12:11:34.875316
3140 12:11:34.878240 CA PerBit enable=1, Macro0, CA PI delay=33
3141 12:11:34.878359
3142 12:11:34.882035 [CBTSetCACLKResult] CA Dly = 33
3143 12:11:34.884674 CS Dly: 6 (0~39)
3144 12:11:34.884753
3145 12:11:34.888470 ----->DramcWriteLeveling(PI) begin...
3146 12:11:34.888584 ==
3147 12:11:34.891593 Dram Type= 6, Freq= 0, CH_1, rank 0
3148 12:11:34.894845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 12:11:34.894926 ==
3150 12:11:34.898028 Write leveling (Byte 0): 25 => 25
3151 12:11:34.901330 Write leveling (Byte 1): 27 => 27
3152 12:11:34.905230 DramcWriteLeveling(PI) end<-----
3153 12:11:34.905313
3154 12:11:34.905401 ==
3155 12:11:34.908582 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 12:11:34.911773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 12:11:34.911885 ==
3158 12:11:34.915185 [Gating] SW mode calibration
3159 12:11:34.921402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3160 12:11:34.928288 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3161 12:11:34.931459 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3162 12:11:34.934806 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 12:11:34.941883 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 12:11:34.945210 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 12:11:34.948446 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 12:11:34.954814 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 12:11:34.957983 0 15 24 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
3168 12:11:34.961524 0 15 28 | B1->B0 | 2c2c 2929 | 0 0 | (1 0) (0 1)
3169 12:11:34.968173 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 12:11:34.971277 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 12:11:34.974928 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 12:11:34.978173 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 12:11:34.984878 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 12:11:34.987884 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 12:11:34.991256 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3176 12:11:34.997952 1 0 28 | B1->B0 | 3c3c 4545 | 0 0 | (1 1) (0 0)
3177 12:11:35.001157 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3178 12:11:35.004441 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 12:11:35.011086 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 12:11:35.014977 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 12:11:35.018112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 12:11:35.024551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 12:11:35.027746 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3184 12:11:35.031178 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3185 12:11:35.037852 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3186 12:11:35.041076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 12:11:35.044197 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 12:11:35.051477 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 12:11:35.054152 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 12:11:35.057952 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 12:11:35.064287 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 12:11:35.067821 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 12:11:35.070776 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 12:11:35.077554 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 12:11:35.081183 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 12:11:35.084152 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 12:11:35.090831 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 12:11:35.093921 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:11:35.097694 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3200 12:11:35.104285 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3201 12:11:35.107598 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 12:11:35.110807 Total UI for P1: 0, mck2ui 16
3203 12:11:35.113993 best dqsien dly found for B0: ( 1, 3, 26)
3204 12:11:35.117275 Total UI for P1: 0, mck2ui 16
3205 12:11:35.120589 best dqsien dly found for B1: ( 1, 3, 28)
3206 12:11:35.124441 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3207 12:11:35.127130 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3208 12:11:35.127211
3209 12:11:35.130945 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3210 12:11:35.134040 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3211 12:11:35.137098 [Gating] SW calibration Done
3212 12:11:35.137207 ==
3213 12:11:35.140853 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 12:11:35.144149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 12:11:35.144230 ==
3216 12:11:35.147300 RX Vref Scan: 0
3217 12:11:35.147403
3218 12:11:35.150470 RX Vref 0 -> 0, step: 1
3219 12:11:35.150571
3220 12:11:35.150671 RX Delay -40 -> 252, step: 8
3221 12:11:35.157028 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3222 12:11:35.160314 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3223 12:11:35.163602 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3224 12:11:35.167321 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3225 12:11:35.170392 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3226 12:11:35.177133 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3227 12:11:35.180781 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3228 12:11:35.183836 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3229 12:11:35.186985 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3230 12:11:35.190606 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3231 12:11:35.197265 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3232 12:11:35.200337 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3233 12:11:35.203617 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3234 12:11:35.206963 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3235 12:11:35.213991 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3236 12:11:35.217174 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3237 12:11:35.217251 ==
3238 12:11:35.220607 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 12:11:35.223870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 12:11:35.223975 ==
3241 12:11:35.224070 DQS Delay:
3242 12:11:35.227236 DQS0 = 0, DQS1 = 0
3243 12:11:35.227334 DQM Delay:
3244 12:11:35.230489 DQM0 = 115, DQM1 = 112
3245 12:11:35.230594 DQ Delay:
3246 12:11:35.233735 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3247 12:11:35.236791 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3248 12:11:35.239821 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3249 12:11:35.246854 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3250 12:11:35.246937
3251 12:11:35.247005
3252 12:11:35.247068 ==
3253 12:11:35.250113 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 12:11:35.253568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 12:11:35.253653 ==
3256 12:11:35.253720
3257 12:11:35.253810
3258 12:11:35.256660 TX Vref Scan disable
3259 12:11:35.256746 == TX Byte 0 ==
3260 12:11:35.262966 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3261 12:11:35.266320 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3262 12:11:35.266414 == TX Byte 1 ==
3263 12:11:35.273326 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3264 12:11:35.276601 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3265 12:11:35.276683 ==
3266 12:11:35.279703 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 12:11:35.283191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 12:11:35.283295 ==
3269 12:11:35.295628 TX Vref=22, minBit 8, minWin=24, winSum=404
3270 12:11:35.298720 TX Vref=24, minBit 8, minWin=24, winSum=411
3271 12:11:35.302420 TX Vref=26, minBit 3, minWin=24, winSum=419
3272 12:11:35.305512 TX Vref=28, minBit 9, minWin=24, winSum=421
3273 12:11:35.308563 TX Vref=30, minBit 9, minWin=25, winSum=423
3274 12:11:35.315212 TX Vref=32, minBit 11, minWin=25, winSum=424
3275 12:11:35.318529 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 32
3276 12:11:35.318627
3277 12:11:35.321842 Final TX Range 1 Vref 32
3278 12:11:35.321928
3279 12:11:35.321997 ==
3280 12:11:35.325604 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 12:11:35.328892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 12:11:35.332132 ==
3283 12:11:35.332245
3284 12:11:35.332340
3285 12:11:35.332431 TX Vref Scan disable
3286 12:11:35.335414 == TX Byte 0 ==
3287 12:11:35.338536 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3288 12:11:35.345299 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3289 12:11:35.345386 == TX Byte 1 ==
3290 12:11:35.349162 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3291 12:11:35.355599 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3292 12:11:35.355686
3293 12:11:35.355754 [DATLAT]
3294 12:11:35.355818 Freq=1200, CH1 RK0
3295 12:11:35.355879
3296 12:11:35.358871 DATLAT Default: 0xd
3297 12:11:35.358956 0, 0xFFFF, sum = 0
3298 12:11:35.362149 1, 0xFFFF, sum = 0
3299 12:11:35.362236 2, 0xFFFF, sum = 0
3300 12:11:35.365494 3, 0xFFFF, sum = 0
3301 12:11:35.368776 4, 0xFFFF, sum = 0
3302 12:11:35.368863 5, 0xFFFF, sum = 0
3303 12:11:35.371972 6, 0xFFFF, sum = 0
3304 12:11:35.372066 7, 0xFFFF, sum = 0
3305 12:11:35.374957 8, 0xFFFF, sum = 0
3306 12:11:35.375044 9, 0xFFFF, sum = 0
3307 12:11:35.378256 10, 0xFFFF, sum = 0
3308 12:11:35.378343 11, 0xFFFF, sum = 0
3309 12:11:35.382066 12, 0x0, sum = 1
3310 12:11:35.382152 13, 0x0, sum = 2
3311 12:11:35.385187 14, 0x0, sum = 3
3312 12:11:35.385276 15, 0x0, sum = 4
3313 12:11:35.388338 best_step = 13
3314 12:11:35.388423
3315 12:11:35.388491 ==
3316 12:11:35.391962 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 12:11:35.395013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 12:11:35.395099 ==
3319 12:11:35.395168 RX Vref Scan: 1
3320 12:11:35.398581
3321 12:11:35.398665 Set Vref Range= 32 -> 127
3322 12:11:35.398734
3323 12:11:35.401679 RX Vref 32 -> 127, step: 1
3324 12:11:35.401770
3325 12:11:35.404684 RX Delay -13 -> 252, step: 4
3326 12:11:35.404769
3327 12:11:35.408370 Set Vref, RX VrefLevel [Byte0]: 32
3328 12:11:35.411407 [Byte1]: 32
3329 12:11:35.411492
3330 12:11:35.415113 Set Vref, RX VrefLevel [Byte0]: 33
3331 12:11:35.418421 [Byte1]: 33
3332 12:11:35.421643
3333 12:11:35.421728 Set Vref, RX VrefLevel [Byte0]: 34
3334 12:11:35.424988 [Byte1]: 34
3335 12:11:35.430066
3336 12:11:35.430151 Set Vref, RX VrefLevel [Byte0]: 35
3337 12:11:35.433384 [Byte1]: 35
3338 12:11:35.437936
3339 12:11:35.438049 Set Vref, RX VrefLevel [Byte0]: 36
3340 12:11:35.441111 [Byte1]: 36
3341 12:11:35.445487
3342 12:11:35.445590 Set Vref, RX VrefLevel [Byte0]: 37
3343 12:11:35.448587 [Byte1]: 37
3344 12:11:35.453570
3345 12:11:35.453650 Set Vref, RX VrefLevel [Byte0]: 38
3346 12:11:35.456879 [Byte1]: 38
3347 12:11:35.461537
3348 12:11:35.461640 Set Vref, RX VrefLevel [Byte0]: 39
3349 12:11:35.464285 [Byte1]: 39
3350 12:11:35.469509
3351 12:11:35.469613 Set Vref, RX VrefLevel [Byte0]: 40
3352 12:11:35.472189 [Byte1]: 40
3353 12:11:35.477226
3354 12:11:35.477332 Set Vref, RX VrefLevel [Byte0]: 41
3355 12:11:35.480554 [Byte1]: 41
3356 12:11:35.484895
3357 12:11:35.484978 Set Vref, RX VrefLevel [Byte0]: 42
3358 12:11:35.488149 [Byte1]: 42
3359 12:11:35.492758
3360 12:11:35.492840 Set Vref, RX VrefLevel [Byte0]: 43
3361 12:11:35.496323 [Byte1]: 43
3362 12:11:35.500890
3363 12:11:35.500972 Set Vref, RX VrefLevel [Byte0]: 44
3364 12:11:35.503925 [Byte1]: 44
3365 12:11:35.508797
3366 12:11:35.508881 Set Vref, RX VrefLevel [Byte0]: 45
3367 12:11:35.511908 [Byte1]: 45
3368 12:11:35.516153
3369 12:11:35.516263 Set Vref, RX VrefLevel [Byte0]: 46
3370 12:11:35.519810 [Byte1]: 46
3371 12:11:35.524358
3372 12:11:35.524471 Set Vref, RX VrefLevel [Byte0]: 47
3373 12:11:35.527562 [Byte1]: 47
3374 12:11:35.532122
3375 12:11:35.532196 Set Vref, RX VrefLevel [Byte0]: 48
3376 12:11:35.535514 [Byte1]: 48
3377 12:11:35.540013
3378 12:11:35.540125 Set Vref, RX VrefLevel [Byte0]: 49
3379 12:11:35.543170 [Byte1]: 49
3380 12:11:35.547774
3381 12:11:35.547848 Set Vref, RX VrefLevel [Byte0]: 50
3382 12:11:35.550907 [Byte1]: 50
3383 12:11:35.555953
3384 12:11:35.556070 Set Vref, RX VrefLevel [Byte0]: 51
3385 12:11:35.558897 [Byte1]: 51
3386 12:11:35.564055
3387 12:11:35.564161 Set Vref, RX VrefLevel [Byte0]: 52
3388 12:11:35.566717 [Byte1]: 52
3389 12:11:35.571250
3390 12:11:35.571350 Set Vref, RX VrefLevel [Byte0]: 53
3391 12:11:35.574598 [Byte1]: 53
3392 12:11:35.579575
3393 12:11:35.579653 Set Vref, RX VrefLevel [Byte0]: 54
3394 12:11:35.582832 [Byte1]: 54
3395 12:11:35.587304
3396 12:11:35.587413 Set Vref, RX VrefLevel [Byte0]: 55
3397 12:11:35.590668 [Byte1]: 55
3398 12:11:35.595095
3399 12:11:35.595198 Set Vref, RX VrefLevel [Byte0]: 56
3400 12:11:35.598217 [Byte1]: 56
3401 12:11:35.603094
3402 12:11:35.603177 Set Vref, RX VrefLevel [Byte0]: 57
3403 12:11:35.606264 [Byte1]: 57
3404 12:11:35.610939
3405 12:11:35.611053 Set Vref, RX VrefLevel [Byte0]: 58
3406 12:11:35.614465 [Byte1]: 58
3407 12:11:35.618664
3408 12:11:35.618766 Set Vref, RX VrefLevel [Byte0]: 59
3409 12:11:35.622259 [Byte1]: 59
3410 12:11:35.627050
3411 12:11:35.627137 Set Vref, RX VrefLevel [Byte0]: 60
3412 12:11:35.630262 [Byte1]: 60
3413 12:11:35.634778
3414 12:11:35.634864 Set Vref, RX VrefLevel [Byte0]: 61
3415 12:11:35.637859 [Byte1]: 61
3416 12:11:35.642302
3417 12:11:35.642381 Set Vref, RX VrefLevel [Byte0]: 62
3418 12:11:35.645579 [Byte1]: 62
3419 12:11:35.650113
3420 12:11:35.650199 Set Vref, RX VrefLevel [Byte0]: 63
3421 12:11:35.653481 [Byte1]: 63
3422 12:11:35.658589
3423 12:11:35.658718 Set Vref, RX VrefLevel [Byte0]: 64
3424 12:11:35.661674 [Byte1]: 64
3425 12:11:35.666085
3426 12:11:35.666217 Set Vref, RX VrefLevel [Byte0]: 65
3427 12:11:35.669325 [Byte1]: 65
3428 12:11:35.673941
3429 12:11:35.674063 Final RX Vref Byte 0 = 52 to rank0
3430 12:11:35.677259 Final RX Vref Byte 1 = 49 to rank0
3431 12:11:35.680461 Final RX Vref Byte 0 = 52 to rank1
3432 12:11:35.683703 Final RX Vref Byte 1 = 49 to rank1==
3433 12:11:35.687485 Dram Type= 6, Freq= 0, CH_1, rank 0
3434 12:11:35.694065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 12:11:35.694177 ==
3436 12:11:35.694327 DQS Delay:
3437 12:11:35.694423 DQS0 = 0, DQS1 = 0
3438 12:11:35.697376 DQM Delay:
3439 12:11:35.697469 DQM0 = 114, DQM1 = 112
3440 12:11:35.700612 DQ Delay:
3441 12:11:35.703878 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3442 12:11:35.707156 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3443 12:11:35.710154 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3444 12:11:35.713663 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3445 12:11:35.713753
3446 12:11:35.713840
3447 12:11:35.723731 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3448 12:11:35.723852 CH1 RK0: MR19=304, MR18=F703
3449 12:11:35.730313 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3450 12:11:35.730424
3451 12:11:35.733330 ----->DramcWriteLeveling(PI) begin...
3452 12:11:35.733454 ==
3453 12:11:35.736752 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 12:11:35.743251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 12:11:35.743367 ==
3456 12:11:35.747205 Write leveling (Byte 0): 26 => 26
3457 12:11:35.750372 Write leveling (Byte 1): 29 => 29
3458 12:11:35.750479 DramcWriteLeveling(PI) end<-----
3459 12:11:35.750594
3460 12:11:35.753530 ==
3461 12:11:35.753641 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 12:11:35.760080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 12:11:35.760179 ==
3464 12:11:35.763177 [Gating] SW mode calibration
3465 12:11:35.769898 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3466 12:11:35.773775 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3467 12:11:35.780204 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3468 12:11:35.783363 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 12:11:35.786721 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 12:11:35.793862 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3471 12:11:35.797246 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3472 12:11:35.799909 0 15 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3473 12:11:35.806558 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 1)
3474 12:11:35.810255 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3475 12:11:35.813714 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 12:11:35.819907 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 12:11:35.823461 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 12:11:35.826563 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3479 12:11:35.833083 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3480 12:11:35.836570 1 0 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3481 12:11:35.839636 1 0 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3482 12:11:35.846296 1 0 28 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3483 12:11:35.849991 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 12:11:35.853158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 12:11:35.856202 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 12:11:35.863249 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 12:11:35.866414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3488 12:11:35.869701 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 12:11:35.876375 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3490 12:11:35.879469 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3491 12:11:35.882756 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:11:35.889804 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:11:35.892902 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:11:35.896156 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:11:35.902595 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:11:35.905878 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:11:35.909037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:11:35.916246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:11:35.919490 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:11:35.922785 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:11:35.929173 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 12:11:35.932188 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:11:35.935856 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 12:11:35.941934 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 12:11:35.945514 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3506 12:11:35.948556 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3507 12:11:35.952268 Total UI for P1: 0, mck2ui 16
3508 12:11:35.955374 best dqsien dly found for B0: ( 1, 3, 24)
3509 12:11:35.962148 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 12:11:35.965243 Total UI for P1: 0, mck2ui 16
3511 12:11:35.968427 best dqsien dly found for B1: ( 1, 3, 26)
3512 12:11:35.971751 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3513 12:11:35.975422 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3514 12:11:35.975539
3515 12:11:35.978435 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3516 12:11:35.981637 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3517 12:11:35.985305 [Gating] SW calibration Done
3518 12:11:35.985395 ==
3519 12:11:35.988429 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 12:11:35.991662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 12:11:35.991750 ==
3522 12:11:35.994877 RX Vref Scan: 0
3523 12:11:35.994964
3524 12:11:35.998118 RX Vref 0 -> 0, step: 1
3525 12:11:35.998203
3526 12:11:35.998273 RX Delay -40 -> 252, step: 8
3527 12:11:36.004701 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3528 12:11:36.007966 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3529 12:11:36.011304 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3530 12:11:36.014583 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3531 12:11:36.021190 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3532 12:11:36.024323 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3533 12:11:36.027618 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3534 12:11:36.030882 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3535 12:11:36.034237 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3536 12:11:36.037890 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3537 12:11:36.044237 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3538 12:11:36.047253 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3539 12:11:36.050866 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3540 12:11:36.053728 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3541 12:11:36.060986 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3542 12:11:36.064051 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3543 12:11:36.064138 ==
3544 12:11:36.067134 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 12:11:36.070671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 12:11:36.070758 ==
3547 12:11:36.073991 DQS Delay:
3548 12:11:36.074076 DQS0 = 0, DQS1 = 0
3549 12:11:36.074149 DQM Delay:
3550 12:11:36.077230 DQM0 = 115, DQM1 = 111
3551 12:11:36.077315 DQ Delay:
3552 12:11:36.080278 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3553 12:11:36.083340 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3554 12:11:36.090078 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3555 12:11:36.093394 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3556 12:11:36.093492
3557 12:11:36.093561
3558 12:11:36.093626 ==
3559 12:11:36.096606 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 12:11:36.099923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 12:11:36.100048 ==
3562 12:11:36.100122
3563 12:11:36.100187
3564 12:11:36.103262 TX Vref Scan disable
3565 12:11:36.106656 == TX Byte 0 ==
3566 12:11:36.109903 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 12:11:36.113205 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 12:11:36.116333 == TX Byte 1 ==
3569 12:11:36.119459 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3570 12:11:36.123297 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3571 12:11:36.123404 ==
3572 12:11:36.126541 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 12:11:36.133022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 12:11:36.133130 ==
3575 12:11:36.143348 TX Vref=22, minBit 9, minWin=25, winSum=417
3576 12:11:36.146742 TX Vref=24, minBit 3, minWin=25, winSum=423
3577 12:11:36.149958 TX Vref=26, minBit 1, minWin=26, winSum=426
3578 12:11:36.153139 TX Vref=28, minBit 9, minWin=26, winSum=430
3579 12:11:36.156707 TX Vref=30, minBit 1, minWin=26, winSum=432
3580 12:11:36.163234 TX Vref=32, minBit 1, minWin=26, winSum=432
3581 12:11:36.166138 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3582 12:11:36.166219
3583 12:11:36.169823 Final TX Range 1 Vref 30
3584 12:11:36.169900
3585 12:11:36.169969 ==
3586 12:11:36.172886 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 12:11:36.175902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 12:11:36.179272 ==
3589 12:11:36.179380
3590 12:11:36.179474
3591 12:11:36.179569 TX Vref Scan disable
3592 12:11:36.182631 == TX Byte 0 ==
3593 12:11:36.186077 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3594 12:11:36.189788 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3595 12:11:36.192881 == TX Byte 1 ==
3596 12:11:36.196202 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3597 12:11:36.202550 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3598 12:11:36.202636
3599 12:11:36.202704 [DATLAT]
3600 12:11:36.202775 Freq=1200, CH1 RK1
3601 12:11:36.202837
3602 12:11:36.205976 DATLAT Default: 0xd
3603 12:11:36.206069 0, 0xFFFF, sum = 0
3604 12:11:36.209253 1, 0xFFFF, sum = 0
3605 12:11:36.212610 2, 0xFFFF, sum = 0
3606 12:11:36.212696 3, 0xFFFF, sum = 0
3607 12:11:36.215843 4, 0xFFFF, sum = 0
3608 12:11:36.215929 5, 0xFFFF, sum = 0
3609 12:11:36.219199 6, 0xFFFF, sum = 0
3610 12:11:36.219285 7, 0xFFFF, sum = 0
3611 12:11:36.222947 8, 0xFFFF, sum = 0
3612 12:11:36.223033 9, 0xFFFF, sum = 0
3613 12:11:36.225517 10, 0xFFFF, sum = 0
3614 12:11:36.225606 11, 0xFFFF, sum = 0
3615 12:11:36.228825 12, 0x0, sum = 1
3616 12:11:36.228911 13, 0x0, sum = 2
3617 12:11:36.232131 14, 0x0, sum = 3
3618 12:11:36.232216 15, 0x0, sum = 4
3619 12:11:36.235870 best_step = 13
3620 12:11:36.235978
3621 12:11:36.236085 ==
3622 12:11:36.238550 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 12:11:36.241887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 12:11:36.241994 ==
3625 12:11:36.245411 RX Vref Scan: 0
3626 12:11:36.245514
3627 12:11:36.245620 RX Vref 0 -> 0, step: 1
3628 12:11:36.245717
3629 12:11:36.248721 RX Delay -13 -> 252, step: 4
3630 12:11:36.255223 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3631 12:11:36.258318 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3632 12:11:36.261893 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3633 12:11:36.264991 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3634 12:11:36.268156 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3635 12:11:36.274870 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3636 12:11:36.278606 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3637 12:11:36.281530 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3638 12:11:36.284553 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3639 12:11:36.288125 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3640 12:11:36.294840 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3641 12:11:36.297970 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3642 12:11:36.301403 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3643 12:11:36.304522 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3644 12:11:36.311078 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3645 12:11:36.314290 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3646 12:11:36.314411 ==
3647 12:11:36.317549 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 12:11:36.320886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 12:11:36.320973 ==
3650 12:11:36.324289 DQS Delay:
3651 12:11:36.324374 DQS0 = 0, DQS1 = 0
3652 12:11:36.324441 DQM Delay:
3653 12:11:36.327483 DQM0 = 115, DQM1 = 112
3654 12:11:36.327567 DQ Delay:
3655 12:11:36.330772 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3656 12:11:36.334148 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3657 12:11:36.341199 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3658 12:11:36.344540 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3659 12:11:36.344625
3660 12:11:36.344692
3661 12:11:36.350914 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3662 12:11:36.354203 CH1 RK1: MR19=304, MR18=F90B
3663 12:11:36.360684 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3664 12:11:36.364026 [RxdqsGatingPostProcess] freq 1200
3665 12:11:36.370430 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3666 12:11:36.370515 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 12:11:36.373967 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 12:11:36.377114 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 12:11:36.380558 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 12:11:36.383575 best DQS0 dly(2T, 0.5T) = (0, 11)
3671 12:11:36.387171 best DQS1 dly(2T, 0.5T) = (0, 11)
3672 12:11:36.390233 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3673 12:11:36.393311 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3674 12:11:36.396928 Pre-setting of DQS Precalculation
3675 12:11:36.403376 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3676 12:11:36.410125 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3677 12:11:36.416379 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3678 12:11:36.416465
3679 12:11:36.416562
3680 12:11:36.419602 [Calibration Summary] 2400 Mbps
3681 12:11:36.419689 CH 0, Rank 0
3682 12:11:36.423515 SW Impedance : PASS
3683 12:11:36.426888 DUTY Scan : NO K
3684 12:11:36.426978 ZQ Calibration : PASS
3685 12:11:36.430096 Jitter Meter : NO K
3686 12:11:36.433259 CBT Training : PASS
3687 12:11:36.433339 Write leveling : PASS
3688 12:11:36.436560 RX DQS gating : PASS
3689 12:11:36.439823 RX DQ/DQS(RDDQC) : PASS
3690 12:11:36.439944 TX DQ/DQS : PASS
3691 12:11:36.442981 RX DATLAT : PASS
3692 12:11:36.446270 RX DQ/DQS(Engine): PASS
3693 12:11:36.446364 TX OE : NO K
3694 12:11:36.446432 All Pass.
3695 12:11:36.449518
3696 12:11:36.449595 CH 0, Rank 1
3697 12:11:36.453135 SW Impedance : PASS
3698 12:11:36.453211 DUTY Scan : NO K
3699 12:11:36.456356 ZQ Calibration : PASS
3700 12:11:36.459593 Jitter Meter : NO K
3701 12:11:36.459675 CBT Training : PASS
3702 12:11:36.462737 Write leveling : PASS
3703 12:11:36.462814 RX DQS gating : PASS
3704 12:11:36.466108 RX DQ/DQS(RDDQC) : PASS
3705 12:11:36.469345 TX DQ/DQS : PASS
3706 12:11:36.469438 RX DATLAT : PASS
3707 12:11:36.472518 RX DQ/DQS(Engine): PASS
3708 12:11:36.475750 TX OE : NO K
3709 12:11:36.475844 All Pass.
3710 12:11:36.475914
3711 12:11:36.475978 CH 1, Rank 0
3712 12:11:36.479015 SW Impedance : PASS
3713 12:11:36.482717 DUTY Scan : NO K
3714 12:11:36.482832 ZQ Calibration : PASS
3715 12:11:36.485717 Jitter Meter : NO K
3716 12:11:36.489295 CBT Training : PASS
3717 12:11:36.489384 Write leveling : PASS
3718 12:11:36.492267 RX DQS gating : PASS
3719 12:11:36.495351 RX DQ/DQS(RDDQC) : PASS
3720 12:11:36.495476 TX DQ/DQS : PASS
3721 12:11:36.498865 RX DATLAT : PASS
3722 12:11:36.502158 RX DQ/DQS(Engine): PASS
3723 12:11:36.502236 TX OE : NO K
3724 12:11:36.505564 All Pass.
3725 12:11:36.505638
3726 12:11:36.505703 CH 1, Rank 1
3727 12:11:36.509179 SW Impedance : PASS
3728 12:11:36.509259 DUTY Scan : NO K
3729 12:11:36.512069 ZQ Calibration : PASS
3730 12:11:36.515313 Jitter Meter : NO K
3731 12:11:36.515390 CBT Training : PASS
3732 12:11:36.518759 Write leveling : PASS
3733 12:11:36.522023 RX DQS gating : PASS
3734 12:11:36.522112 RX DQ/DQS(RDDQC) : PASS
3735 12:11:36.525273 TX DQ/DQS : PASS
3736 12:11:36.529133 RX DATLAT : PASS
3737 12:11:36.529221 RX DQ/DQS(Engine): PASS
3738 12:11:36.532232 TX OE : NO K
3739 12:11:36.532318 All Pass.
3740 12:11:36.532386
3741 12:11:36.535464 DramC Write-DBI off
3742 12:11:36.538652 PER_BANK_REFRESH: Hybrid Mode
3743 12:11:36.538738 TX_TRACKING: ON
3744 12:11:36.548476 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3745 12:11:36.551614 [FAST_K] Save calibration result to emmc
3746 12:11:36.555432 dramc_set_vcore_voltage set vcore to 650000
3747 12:11:36.558443 Read voltage for 600, 5
3748 12:11:36.558527 Vio18 = 0
3749 12:11:36.558597 Vcore = 650000
3750 12:11:36.561840 Vdram = 0
3751 12:11:36.561921 Vddq = 0
3752 12:11:36.561985 Vmddr = 0
3753 12:11:36.568370 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3754 12:11:36.571558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3755 12:11:36.574956 MEM_TYPE=3, freq_sel=19
3756 12:11:36.578102 sv_algorithm_assistance_LP4_1600
3757 12:11:36.581290 ============ PULL DRAM RESETB DOWN ============
3758 12:11:36.584603 ========== PULL DRAM RESETB DOWN end =========
3759 12:11:36.591039 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3760 12:11:36.594791 ===================================
3761 12:11:36.597762 LPDDR4 DRAM CONFIGURATION
3762 12:11:36.601190 ===================================
3763 12:11:36.601271 EX_ROW_EN[0] = 0x0
3764 12:11:36.604152 EX_ROW_EN[1] = 0x0
3765 12:11:36.604233 LP4Y_EN = 0x0
3766 12:11:36.607793 WORK_FSP = 0x0
3767 12:11:36.607876 WL = 0x2
3768 12:11:36.610815 RL = 0x2
3769 12:11:36.610906 BL = 0x2
3770 12:11:36.614362 RPST = 0x0
3771 12:11:36.614439 RD_PRE = 0x0
3772 12:11:36.617337 WR_PRE = 0x1
3773 12:11:36.617448 WR_PST = 0x0
3774 12:11:36.621025 DBI_WR = 0x0
3775 12:11:36.624082 DBI_RD = 0x0
3776 12:11:36.624167 OTF = 0x1
3777 12:11:36.627071 ===================================
3778 12:11:36.630686 ===================================
3779 12:11:36.630772 ANA top config
3780 12:11:36.633925 ===================================
3781 12:11:36.637243 DLL_ASYNC_EN = 0
3782 12:11:36.640504 ALL_SLAVE_EN = 1
3783 12:11:36.643858 NEW_RANK_MODE = 1
3784 12:11:36.647148 DLL_IDLE_MODE = 1
3785 12:11:36.647246 LP45_APHY_COMB_EN = 1
3786 12:11:36.650355 TX_ODT_DIS = 1
3787 12:11:36.653622 NEW_8X_MODE = 1
3788 12:11:36.656822 ===================================
3789 12:11:36.659977 ===================================
3790 12:11:36.663848 data_rate = 1200
3791 12:11:36.666984 CKR = 1
3792 12:11:36.670286 DQ_P2S_RATIO = 8
3793 12:11:36.673530 ===================================
3794 12:11:36.673644 CA_P2S_RATIO = 8
3795 12:11:36.676894 DQ_CA_OPEN = 0
3796 12:11:36.680232 DQ_SEMI_OPEN = 0
3797 12:11:36.683368 CA_SEMI_OPEN = 0
3798 12:11:36.686682 CA_FULL_RATE = 0
3799 12:11:36.689956 DQ_CKDIV4_EN = 1
3800 12:11:36.690056 CA_CKDIV4_EN = 1
3801 12:11:36.693110 CA_PREDIV_EN = 0
3802 12:11:36.696342 PH8_DLY = 0
3803 12:11:36.699638 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3804 12:11:36.702754 DQ_AAMCK_DIV = 4
3805 12:11:36.706373 CA_AAMCK_DIV = 4
3806 12:11:36.706477 CA_ADMCK_DIV = 4
3807 12:11:36.709326 DQ_TRACK_CA_EN = 0
3808 12:11:36.713024 CA_PICK = 600
3809 12:11:36.715838 CA_MCKIO = 600
3810 12:11:36.719319 MCKIO_SEMI = 0
3811 12:11:36.722301 PLL_FREQ = 2288
3812 12:11:36.725920 DQ_UI_PI_RATIO = 32
3813 12:11:36.729262 CA_UI_PI_RATIO = 0
3814 12:11:36.732678 ===================================
3815 12:11:36.735718 ===================================
3816 12:11:36.735851 memory_type:LPDDR4
3817 12:11:36.739189 GP_NUM : 10
3818 12:11:36.742264 SRAM_EN : 1
3819 12:11:36.742394 MD32_EN : 0
3820 12:11:36.745615 ===================================
3821 12:11:36.748836 [ANA_INIT] >>>>>>>>>>>>>>
3822 12:11:36.752223 <<<<<< [CONFIGURE PHASE]: ANA_TX
3823 12:11:36.755398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3824 12:11:36.758607 ===================================
3825 12:11:36.761918 data_rate = 1200,PCW = 0X5800
3826 12:11:36.765083 ===================================
3827 12:11:36.768760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3828 12:11:36.772028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3829 12:11:36.778514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3830 12:11:36.781969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3831 12:11:36.785190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3832 12:11:36.788414 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3833 12:11:36.792402 [ANA_INIT] flow start
3834 12:11:36.795739 [ANA_INIT] PLL >>>>>>>>
3835 12:11:36.795812 [ANA_INIT] PLL <<<<<<<<
3836 12:11:36.798723 [ANA_INIT] MIDPI >>>>>>>>
3837 12:11:36.802041 [ANA_INIT] MIDPI <<<<<<<<
3838 12:11:36.805290 [ANA_INIT] DLL >>>>>>>>
3839 12:11:36.805390 [ANA_INIT] flow end
3840 12:11:36.808486 ============ LP4 DIFF to SE enter ============
3841 12:11:36.815186 ============ LP4 DIFF to SE exit ============
3842 12:11:36.815266 [ANA_INIT] <<<<<<<<<<<<<
3843 12:11:36.818036 [Flow] Enable top DCM control >>>>>
3844 12:11:36.821849 [Flow] Enable top DCM control <<<<<
3845 12:11:36.825235 Enable DLL master slave shuffle
3846 12:11:36.831784 ==============================================================
3847 12:11:36.831896 Gating Mode config
3848 12:11:36.838011 ==============================================================
3849 12:11:36.841564 Config description:
3850 12:11:36.851411 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3851 12:11:36.857902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3852 12:11:36.861136 SELPH_MODE 0: By rank 1: By Phase
3853 12:11:36.867542 ==============================================================
3854 12:11:36.871263 GAT_TRACK_EN = 1
3855 12:11:36.874473 RX_GATING_MODE = 2
3856 12:11:36.874558 RX_GATING_TRACK_MODE = 2
3857 12:11:36.877695 SELPH_MODE = 1
3858 12:11:36.880955 PICG_EARLY_EN = 1
3859 12:11:36.884221 VALID_LAT_VALUE = 1
3860 12:11:36.890729 ==============================================================
3861 12:11:36.893814 Enter into Gating configuration >>>>
3862 12:11:36.897645 Exit from Gating configuration <<<<
3863 12:11:36.900918 Enter into DVFS_PRE_config >>>>>
3864 12:11:36.910633 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3865 12:11:36.913899 Exit from DVFS_PRE_config <<<<<
3866 12:11:36.917024 Enter into PICG configuration >>>>
3867 12:11:36.920063 Exit from PICG configuration <<<<
3868 12:11:36.923938 [RX_INPUT] configuration >>>>>
3869 12:11:36.927060 [RX_INPUT] configuration <<<<<
3870 12:11:36.929969 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3871 12:11:36.936779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3872 12:11:36.943270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 12:11:36.949951 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 12:11:36.956662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3875 12:11:36.963032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3876 12:11:36.966273 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3877 12:11:36.969608 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3878 12:11:36.973221 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3879 12:11:36.976254 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3880 12:11:36.982874 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3881 12:11:36.986154 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 12:11:36.990040 ===================================
3883 12:11:36.992698 LPDDR4 DRAM CONFIGURATION
3884 12:11:36.996538 ===================================
3885 12:11:36.996624 EX_ROW_EN[0] = 0x0
3886 12:11:36.999800 EX_ROW_EN[1] = 0x0
3887 12:11:36.999888 LP4Y_EN = 0x0
3888 12:11:37.003049 WORK_FSP = 0x0
3889 12:11:37.006133 WL = 0x2
3890 12:11:37.006218 RL = 0x2
3891 12:11:37.009379 BL = 0x2
3892 12:11:37.009464 RPST = 0x0
3893 12:11:37.012645 RD_PRE = 0x0
3894 12:11:37.012731 WR_PRE = 0x1
3895 12:11:37.015963 WR_PST = 0x0
3896 12:11:37.016080 DBI_WR = 0x0
3897 12:11:37.019160 DBI_RD = 0x0
3898 12:11:37.019245 OTF = 0x1
3899 12:11:37.022188 ===================================
3900 12:11:37.025995 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3901 12:11:37.032194 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3902 12:11:37.035326 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3903 12:11:37.039001 ===================================
3904 12:11:37.042059 LPDDR4 DRAM CONFIGURATION
3905 12:11:37.045170 ===================================
3906 12:11:37.045252 EX_ROW_EN[0] = 0x10
3907 12:11:37.048726 EX_ROW_EN[1] = 0x0
3908 12:11:37.051787 LP4Y_EN = 0x0
3909 12:11:37.051902 WORK_FSP = 0x0
3910 12:11:37.055151 WL = 0x2
3911 12:11:37.055261 RL = 0x2
3912 12:11:37.058217 BL = 0x2
3913 12:11:37.058308 RPST = 0x0
3914 12:11:37.061414 RD_PRE = 0x0
3915 12:11:37.061492 WR_PRE = 0x1
3916 12:11:37.065117 WR_PST = 0x0
3917 12:11:37.065206 DBI_WR = 0x0
3918 12:11:37.068567 DBI_RD = 0x0
3919 12:11:37.068644 OTF = 0x1
3920 12:11:37.071914 ===================================
3921 12:11:37.078421 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3922 12:11:37.082718 nWR fixed to 30
3923 12:11:37.085961 [ModeRegInit_LP4] CH0 RK0
3924 12:11:37.086038 [ModeRegInit_LP4] CH0 RK1
3925 12:11:37.089258 [ModeRegInit_LP4] CH1 RK0
3926 12:11:37.092418 [ModeRegInit_LP4] CH1 RK1
3927 12:11:37.092508 match AC timing 17
3928 12:11:37.099008 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3929 12:11:37.102881 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3930 12:11:37.105541 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3931 12:11:37.112590 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3932 12:11:37.115839 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3933 12:11:37.115951 ==
3934 12:11:37.119161 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 12:11:37.122382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 12:11:37.122471 ==
3937 12:11:37.129315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 12:11:37.135396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3939 12:11:37.139101 [CA 0] Center 36 (6~67) winsize 62
3940 12:11:37.142253 [CA 1] Center 36 (6~66) winsize 61
3941 12:11:37.145392 [CA 2] Center 34 (4~65) winsize 62
3942 12:11:37.148397 [CA 3] Center 34 (4~65) winsize 62
3943 12:11:37.152054 [CA 4] Center 33 (3~64) winsize 62
3944 12:11:37.155017 [CA 5] Center 33 (3~64) winsize 62
3945 12:11:37.155097
3946 12:11:37.158607 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3947 12:11:37.158684
3948 12:11:37.161580 [CATrainingPosCal] consider 1 rank data
3949 12:11:37.165518 u2DelayCellTimex100 = 270/100 ps
3950 12:11:37.168693 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3951 12:11:37.171901 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3952 12:11:37.175212 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3953 12:11:37.181670 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 12:11:37.184873 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 12:11:37.188735 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 12:11:37.188817
3957 12:11:37.191310 CA PerBit enable=1, Macro0, CA PI delay=33
3958 12:11:37.191385
3959 12:11:37.195143 [CBTSetCACLKResult] CA Dly = 33
3960 12:11:37.195220 CS Dly: 5 (0~36)
3961 12:11:37.195289 ==
3962 12:11:37.197865 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 12:11:37.204910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 12:11:37.204992 ==
3965 12:11:37.208156 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 12:11:37.214249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3967 12:11:37.218047 [CA 0] Center 36 (6~67) winsize 62
3968 12:11:37.221958 [CA 1] Center 36 (6~67) winsize 62
3969 12:11:37.224580 [CA 2] Center 34 (4~65) winsize 62
3970 12:11:37.228402 [CA 3] Center 34 (4~65) winsize 62
3971 12:11:37.231689 [CA 4] Center 34 (3~65) winsize 63
3972 12:11:37.234809 [CA 5] Center 34 (3~65) winsize 63
3973 12:11:37.234895
3974 12:11:37.237713 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3975 12:11:37.237793
3976 12:11:37.241587 [CATrainingPosCal] consider 2 rank data
3977 12:11:37.244946 u2DelayCellTimex100 = 270/100 ps
3978 12:11:37.247658 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3979 12:11:37.254509 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3980 12:11:37.257782 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3981 12:11:37.260716 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3982 12:11:37.264449 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3983 12:11:37.267525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3984 12:11:37.267609
3985 12:11:37.270550 CA PerBit enable=1, Macro0, CA PI delay=33
3986 12:11:37.270625
3987 12:11:37.274079 [CBTSetCACLKResult] CA Dly = 33
3988 12:11:37.277424 CS Dly: 5 (0~37)
3989 12:11:37.277498
3990 12:11:37.280440 ----->DramcWriteLeveling(PI) begin...
3991 12:11:37.280525 ==
3992 12:11:37.283851 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 12:11:37.286964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 12:11:37.287039 ==
3995 12:11:37.290604 Write leveling (Byte 0): 32 => 32
3996 12:11:37.293800 Write leveling (Byte 1): 29 => 29
3997 12:11:37.297047 DramcWriteLeveling(PI) end<-----
3998 12:11:37.297134
3999 12:11:37.297232 ==
4000 12:11:37.300270 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 12:11:37.303550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 12:11:37.303633 ==
4003 12:11:37.306805 [Gating] SW mode calibration
4004 12:11:37.313886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4005 12:11:37.320308 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4006 12:11:37.323607 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 12:11:37.330166 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4008 12:11:37.333476 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4009 12:11:37.336509 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (0 1)
4010 12:11:37.343287 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (1 1) (0 0)
4011 12:11:37.346561 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4012 12:11:37.349771 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 12:11:37.356207 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 12:11:37.359280 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 12:11:37.362975 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4016 12:11:37.369236 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4017 12:11:37.372362 0 10 12 | B1->B0 | 2727 3030 | 0 1 | (0 0) (0 0)
4018 12:11:37.376057 0 10 16 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
4019 12:11:37.382863 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:11:37.385965 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 12:11:37.389103 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 12:11:37.395426 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 12:11:37.399275 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 12:11:37.402619 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:11:37.409172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 12:11:37.412321 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4027 12:11:37.415553 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:11:37.421962 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:11:37.425221 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:11:37.428444 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:11:37.435046 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:11:37.438978 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:11:37.442154 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:11:37.448370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:11:37.451609 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:11:37.454841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:11:37.461414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 12:11:37.465176 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:11:37.468238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:11:37.475143 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:11:37.478050 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4042 12:11:37.481618 Total UI for P1: 0, mck2ui 16
4043 12:11:37.484706 best dqsien dly found for B0: ( 0, 13, 10)
4044 12:11:37.488324 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4045 12:11:37.494390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 12:11:37.494479 Total UI for P1: 0, mck2ui 16
4047 12:11:37.501089 best dqsien dly found for B1: ( 0, 13, 14)
4048 12:11:37.504523 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4049 12:11:37.507865 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4050 12:11:37.507952
4051 12:11:37.511084 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4052 12:11:37.514279 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4053 12:11:37.517646 [Gating] SW calibration Done
4054 12:11:37.517736 ==
4055 12:11:37.520975 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 12:11:37.524240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 12:11:37.524329 ==
4058 12:11:37.527415 RX Vref Scan: 0
4059 12:11:37.527503
4060 12:11:37.527591 RX Vref 0 -> 0, step: 1
4061 12:11:37.530751
4062 12:11:37.530838 RX Delay -230 -> 252, step: 16
4063 12:11:37.537274 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4064 12:11:37.540599 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4065 12:11:37.543831 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4066 12:11:37.547127 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4067 12:11:37.554115 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4068 12:11:37.556786 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4069 12:11:37.560670 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4070 12:11:37.563945 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4071 12:11:37.570262 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4072 12:11:37.573263 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4073 12:11:37.576972 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4074 12:11:37.580225 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4075 12:11:37.586451 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4076 12:11:37.590080 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4077 12:11:37.592966 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4078 12:11:37.596870 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4079 12:11:37.596959 ==
4080 12:11:37.599909 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 12:11:37.606465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 12:11:37.606580 ==
4083 12:11:37.606687 DQS Delay:
4084 12:11:37.609554 DQS0 = 0, DQS1 = 0
4085 12:11:37.609668 DQM Delay:
4086 12:11:37.609777 DQM0 = 44, DQM1 = 35
4087 12:11:37.612675 DQ Delay:
4088 12:11:37.615946 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4089 12:11:37.619148 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =57
4090 12:11:37.622434 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4091 12:11:37.626221 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4092 12:11:37.626309
4093 12:11:37.626395
4094 12:11:37.626477 ==
4095 12:11:37.629439 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 12:11:37.632587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 12:11:37.632708 ==
4098 12:11:37.632808
4099 12:11:37.632911
4100 12:11:37.635835 TX Vref Scan disable
4101 12:11:37.639059 == TX Byte 0 ==
4102 12:11:37.642233 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4103 12:11:37.645422 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4104 12:11:37.649225 == TX Byte 1 ==
4105 12:11:37.652440 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4106 12:11:37.655809 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4107 12:11:37.655933 ==
4108 12:11:37.658802 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 12:11:37.665441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 12:11:37.665524 ==
4111 12:11:37.665589
4112 12:11:37.665659
4113 12:11:37.665716 TX Vref Scan disable
4114 12:11:37.669971 == TX Byte 0 ==
4115 12:11:37.673137 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4116 12:11:37.679888 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4117 12:11:37.679991 == TX Byte 1 ==
4118 12:11:37.683032 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4119 12:11:37.689625 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4120 12:11:37.689709
4121 12:11:37.689775 [DATLAT]
4122 12:11:37.689837 Freq=600, CH0 RK0
4123 12:11:37.689897
4124 12:11:37.692857 DATLAT Default: 0x9
4125 12:11:37.692940 0, 0xFFFF, sum = 0
4126 12:11:37.696405 1, 0xFFFF, sum = 0
4127 12:11:37.699489 2, 0xFFFF, sum = 0
4128 12:11:37.699574 3, 0xFFFF, sum = 0
4129 12:11:37.702514 4, 0xFFFF, sum = 0
4130 12:11:37.702598 5, 0xFFFF, sum = 0
4131 12:11:37.706066 6, 0xFFFF, sum = 0
4132 12:11:37.706152 7, 0xFFFF, sum = 0
4133 12:11:37.709245 8, 0x0, sum = 1
4134 12:11:37.709325 9, 0x0, sum = 2
4135 12:11:37.709391 10, 0x0, sum = 3
4136 12:11:37.712930 11, 0x0, sum = 4
4137 12:11:37.713013 best_step = 9
4138 12:11:37.713078
4139 12:11:37.713137 ==
4140 12:11:37.715795 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 12:11:37.722566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:11:37.722663 ==
4143 12:11:37.722729 RX Vref Scan: 1
4144 12:11:37.722802
4145 12:11:37.725834 RX Vref 0 -> 0, step: 1
4146 12:11:37.725912
4147 12:11:37.729066 RX Delay -195 -> 252, step: 8
4148 12:11:37.729144
4149 12:11:37.732370 Set Vref, RX VrefLevel [Byte0]: 57
4150 12:11:37.735633 [Byte1]: 49
4151 12:11:37.735717
4152 12:11:37.738828 Final RX Vref Byte 0 = 57 to rank0
4153 12:11:37.742093 Final RX Vref Byte 1 = 49 to rank0
4154 12:11:37.745289 Final RX Vref Byte 0 = 57 to rank1
4155 12:11:37.749098 Final RX Vref Byte 1 = 49 to rank1==
4156 12:11:37.752260 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 12:11:37.755439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 12:11:37.758880 ==
4159 12:11:37.758961 DQS Delay:
4160 12:11:37.759028 DQS0 = 0, DQS1 = 0
4161 12:11:37.761967 DQM Delay:
4162 12:11:37.762040 DQM0 = 44, DQM1 = 37
4163 12:11:37.765143 DQ Delay:
4164 12:11:37.768466 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4165 12:11:37.768539 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4166 12:11:37.771770 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4167 12:11:37.778073 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4168 12:11:37.778156
4169 12:11:37.778222
4170 12:11:37.784945 [DQSOSCAuto] RK0, (LSB)MR18= 0x453d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4171 12:11:37.788265 CH0 RK0: MR19=808, MR18=453D
4172 12:11:37.794764 CH0_RK0: MR19=0x808, MR18=0x453D, DQSOSC=396, MR23=63, INC=167, DEC=111
4173 12:11:37.794843
4174 12:11:37.797984 ----->DramcWriteLeveling(PI) begin...
4175 12:11:37.798069 ==
4176 12:11:37.801170 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 12:11:37.804888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 12:11:37.804962 ==
4179 12:11:37.807958 Write leveling (Byte 0): 32 => 32
4180 12:11:37.811552 Write leveling (Byte 1): 32 => 32
4181 12:11:37.814653 DramcWriteLeveling(PI) end<-----
4182 12:11:37.814726
4183 12:11:37.814788 ==
4184 12:11:37.817663 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 12:11:37.821335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 12:11:37.824248 ==
4187 12:11:37.824332 [Gating] SW mode calibration
4188 12:11:37.834653 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4189 12:11:37.837793 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4190 12:11:37.841037 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4191 12:11:37.847454 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4192 12:11:37.850722 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4193 12:11:37.853945 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4194 12:11:37.860360 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4195 12:11:37.864078 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 12:11:37.867243 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 12:11:37.873693 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 12:11:37.876987 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 12:11:37.880186 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4200 12:11:37.887090 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4201 12:11:37.890131 0 10 12 | B1->B0 | 2424 3535 | 1 0 | (0 0) (0 0)
4202 12:11:37.894031 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4203 12:11:37.900497 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 12:11:37.903465 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 12:11:37.906802 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 12:11:37.913301 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 12:11:37.917079 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4208 12:11:37.919965 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4209 12:11:37.926880 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4210 12:11:37.929783 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4211 12:11:37.933343 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:11:37.939872 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:11:37.943104 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:11:37.946322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:11:37.952748 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:11:37.955969 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:11:37.959269 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:11:37.966298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:11:37.969455 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:11:37.972605 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 12:11:37.979284 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 12:11:37.982499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:11:37.986161 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 12:11:37.992249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:11:37.996178 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4226 12:11:37.999298 Total UI for P1: 0, mck2ui 16
4227 12:11:38.002542 best dqsien dly found for B0: ( 0, 13, 10)
4228 12:11:38.005693 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4229 12:11:38.012124 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 12:11:38.015404 Total UI for P1: 0, mck2ui 16
4231 12:11:38.018539 best dqsien dly found for B1: ( 0, 13, 14)
4232 12:11:38.021696 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4233 12:11:38.025449 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4234 12:11:38.025566
4235 12:11:38.028598 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4236 12:11:38.031812 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4237 12:11:38.035273 [Gating] SW calibration Done
4238 12:11:38.035448 ==
4239 12:11:38.038392 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 12:11:38.042001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 12:11:38.042143 ==
4242 12:11:38.045030 RX Vref Scan: 0
4243 12:11:38.045114
4244 12:11:38.048037 RX Vref 0 -> 0, step: 1
4245 12:11:38.048125
4246 12:11:38.048188 RX Delay -230 -> 252, step: 16
4247 12:11:38.055038 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4248 12:11:38.058322 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4249 12:11:38.061565 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4250 12:11:38.064988 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4251 12:11:38.071532 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4252 12:11:38.074661 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4253 12:11:38.077850 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4254 12:11:38.081163 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4255 12:11:38.087864 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4256 12:11:38.090886 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4257 12:11:38.094585 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4258 12:11:38.097636 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4259 12:11:38.104205 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4260 12:11:38.107244 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4261 12:11:38.110575 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4262 12:11:38.114178 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4263 12:11:38.117481 ==
4264 12:11:38.117595 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 12:11:38.124139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 12:11:38.124270 ==
4267 12:11:38.124379 DQS Delay:
4268 12:11:38.127287 DQS0 = 0, DQS1 = 0
4269 12:11:38.127419 DQM Delay:
4270 12:11:38.130341 DQM0 = 50, DQM1 = 37
4271 12:11:38.130445 DQ Delay:
4272 12:11:38.133663 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4273 12:11:38.136949 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4274 12:11:38.140625 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4275 12:11:38.143600 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4276 12:11:38.143700
4277 12:11:38.143782
4278 12:11:38.143844 ==
4279 12:11:38.147126 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 12:11:38.150379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 12:11:38.150464 ==
4282 12:11:38.150532
4283 12:11:38.150593
4284 12:11:38.153555 TX Vref Scan disable
4285 12:11:38.157096 == TX Byte 0 ==
4286 12:11:38.160165 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4287 12:11:38.163897 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4288 12:11:38.167135 == TX Byte 1 ==
4289 12:11:38.169801 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4290 12:11:38.173668 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4291 12:11:38.173779 ==
4292 12:11:38.176746 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 12:11:38.183151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 12:11:38.183266 ==
4295 12:11:38.183367
4296 12:11:38.183464
4297 12:11:38.183554 TX Vref Scan disable
4298 12:11:38.187886 == TX Byte 0 ==
4299 12:11:38.191235 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4300 12:11:38.197333 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4301 12:11:38.197437 == TX Byte 1 ==
4302 12:11:38.200415 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4303 12:11:38.206929 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4304 12:11:38.207038
4305 12:11:38.207138 [DATLAT]
4306 12:11:38.207278 Freq=600, CH0 RK1
4307 12:11:38.207372
4308 12:11:38.210761 DATLAT Default: 0x9
4309 12:11:38.214137 0, 0xFFFF, sum = 0
4310 12:11:38.214247 1, 0xFFFF, sum = 0
4311 12:11:38.217306 2, 0xFFFF, sum = 0
4312 12:11:38.217407 3, 0xFFFF, sum = 0
4313 12:11:38.220532 4, 0xFFFF, sum = 0
4314 12:11:38.220631 5, 0xFFFF, sum = 0
4315 12:11:38.223740 6, 0xFFFF, sum = 0
4316 12:11:38.223825 7, 0xFFFF, sum = 0
4317 12:11:38.226870 8, 0x0, sum = 1
4318 12:11:38.226954 9, 0x0, sum = 2
4319 12:11:38.230202 10, 0x0, sum = 3
4320 12:11:38.230286 11, 0x0, sum = 4
4321 12:11:38.230408 best_step = 9
4322 12:11:38.230491
4323 12:11:38.233937 ==
4324 12:11:38.236903 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 12:11:38.240196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 12:11:38.240279 ==
4327 12:11:38.240345 RX Vref Scan: 0
4328 12:11:38.240421
4329 12:11:38.243514 RX Vref 0 -> 0, step: 1
4330 12:11:38.243628
4331 12:11:38.246513 RX Delay -179 -> 252, step: 8
4332 12:11:38.253045 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4333 12:11:38.256625 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4334 12:11:38.259734 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4335 12:11:38.262781 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4336 12:11:38.269418 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4337 12:11:38.272696 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4338 12:11:38.275968 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4339 12:11:38.279771 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4340 12:11:38.282993 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4341 12:11:38.289576 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4342 12:11:38.292905 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4343 12:11:38.296114 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4344 12:11:38.299188 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4345 12:11:38.305948 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4346 12:11:38.309153 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4347 12:11:38.312471 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4348 12:11:38.312552 ==
4349 12:11:38.315823 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 12:11:38.322089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 12:11:38.322171 ==
4352 12:11:38.322236 DQS Delay:
4353 12:11:38.322295 DQS0 = 0, DQS1 = 0
4354 12:11:38.325282 DQM Delay:
4355 12:11:38.325362 DQM0 = 43, DQM1 = 37
4356 12:11:38.328590 DQ Delay:
4357 12:11:38.331840 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4358 12:11:38.335051 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4359 12:11:38.338962 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4360 12:11:38.342201 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4361 12:11:38.342282
4362 12:11:38.342346
4363 12:11:38.348637 [DQSOSCAuto] RK1, (LSB)MR18= 0x403c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4364 12:11:38.351831 CH0 RK1: MR19=808, MR18=403C
4365 12:11:38.358143 CH0_RK1: MR19=0x808, MR18=0x403C, DQSOSC=397, MR23=63, INC=166, DEC=110
4366 12:11:38.361900 [RxdqsGatingPostProcess] freq 600
4367 12:11:38.364617 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4368 12:11:38.368068 Pre-setting of DQS Precalculation
4369 12:11:38.374827 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4370 12:11:38.374907 ==
4371 12:11:38.378163 Dram Type= 6, Freq= 0, CH_1, rank 0
4372 12:11:38.381364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 12:11:38.381448 ==
4374 12:11:38.388137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 12:11:38.394557 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4376 12:11:38.397852 [CA 0] Center 35 (5~66) winsize 62
4377 12:11:38.400945 [CA 1] Center 35 (5~66) winsize 62
4378 12:11:38.404044 [CA 2] Center 35 (5~65) winsize 61
4379 12:11:38.407947 [CA 3] Center 34 (4~65) winsize 62
4380 12:11:38.411045 [CA 4] Center 34 (4~65) winsize 62
4381 12:11:38.414240 [CA 5] Center 33 (3~64) winsize 62
4382 12:11:38.414349
4383 12:11:38.417440 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4384 12:11:38.417521
4385 12:11:38.420805 [CATrainingPosCal] consider 1 rank data
4386 12:11:38.424112 u2DelayCellTimex100 = 270/100 ps
4387 12:11:38.427210 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4388 12:11:38.430382 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4389 12:11:38.433612 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4390 12:11:38.437237 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4391 12:11:38.440541 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4392 12:11:38.446736 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4393 12:11:38.446820
4394 12:11:38.450584 CA PerBit enable=1, Macro0, CA PI delay=33
4395 12:11:38.450667
4396 12:11:38.453892 [CBTSetCACLKResult] CA Dly = 33
4397 12:11:38.453974 CS Dly: 4 (0~35)
4398 12:11:38.454041 ==
4399 12:11:38.456651 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 12:11:38.463147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:11:38.463230 ==
4402 12:11:38.467059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 12:11:38.473163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4404 12:11:38.476449 [CA 0] Center 36 (6~66) winsize 61
4405 12:11:38.479935 [CA 1] Center 36 (6~66) winsize 61
4406 12:11:38.483090 [CA 2] Center 34 (4~65) winsize 62
4407 12:11:38.486851 [CA 3] Center 34 (3~65) winsize 63
4408 12:11:38.489885 [CA 4] Center 34 (4~65) winsize 62
4409 12:11:38.493089 [CA 5] Center 34 (3~65) winsize 63
4410 12:11:38.493193
4411 12:11:38.496438 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4412 12:11:38.496540
4413 12:11:38.499690 [CATrainingPosCal] consider 2 rank data
4414 12:11:38.502832 u2DelayCellTimex100 = 270/100 ps
4415 12:11:38.506075 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4416 12:11:38.512926 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4417 12:11:38.516572 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4418 12:11:38.519229 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 12:11:38.522641 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 12:11:38.525822 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 12:11:38.525919
4422 12:11:38.529669 CA PerBit enable=1, Macro0, CA PI delay=33
4423 12:11:38.529794
4424 12:11:38.532615 [CBTSetCACLKResult] CA Dly = 33
4425 12:11:38.535864 CS Dly: 4 (0~36)
4426 12:11:38.535960
4427 12:11:38.539067 ----->DramcWriteLeveling(PI) begin...
4428 12:11:38.539180 ==
4429 12:11:38.542327 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 12:11:38.546258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 12:11:38.546356 ==
4432 12:11:38.549425 Write leveling (Byte 0): 29 => 29
4433 12:11:38.552618 Write leveling (Byte 1): 30 => 30
4434 12:11:38.555990 DramcWriteLeveling(PI) end<-----
4435 12:11:38.556096
4436 12:11:38.556200 ==
4437 12:11:38.559151 Dram Type= 6, Freq= 0, CH_1, rank 0
4438 12:11:38.562213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 12:11:38.562313 ==
4440 12:11:38.565576 [Gating] SW mode calibration
4441 12:11:38.571981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4442 12:11:38.578728 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4443 12:11:38.581776 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4444 12:11:38.585430 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4445 12:11:38.592137 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4446 12:11:38.595285 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 1) (1 1)
4447 12:11:38.598457 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 12:11:38.605019 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 12:11:38.608294 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 12:11:38.611495 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 12:11:38.618273 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4452 12:11:38.622097 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 12:11:38.624750 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 12:11:38.631871 0 10 12 | B1->B0 | 3131 3535 | 1 0 | (0 0) (0 0)
4455 12:11:38.635075 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 12:11:38.638141 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 12:11:38.644442 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 12:11:38.647683 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 12:11:38.650884 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 12:11:38.657763 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 12:11:38.660981 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 12:11:38.664236 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4463 12:11:38.670775 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:11:38.674009 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:11:38.677173 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:11:38.684177 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:11:38.687010 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:11:38.690725 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:11:38.697330 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:11:38.700416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:11:38.707052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:11:38.710267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:11:38.713523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 12:11:38.719902 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 12:11:38.723073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:11:38.727018 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:11:38.733320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:11:38.736636 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4479 12:11:38.739715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 12:11:38.742778 Total UI for P1: 0, mck2ui 16
4481 12:11:38.746477 best dqsien dly found for B0: ( 0, 13, 12)
4482 12:11:38.749864 Total UI for P1: 0, mck2ui 16
4483 12:11:38.753287 best dqsien dly found for B1: ( 0, 13, 14)
4484 12:11:38.756396 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4485 12:11:38.759526 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4486 12:11:38.759609
4487 12:11:38.766662 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4488 12:11:38.769835 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4489 12:11:38.769918 [Gating] SW calibration Done
4490 12:11:38.773118 ==
4491 12:11:38.776254 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 12:11:38.779526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 12:11:38.779609 ==
4494 12:11:38.779675 RX Vref Scan: 0
4495 12:11:38.779737
4496 12:11:38.782795 RX Vref 0 -> 0, step: 1
4497 12:11:38.782878
4498 12:11:38.785991 RX Delay -230 -> 252, step: 16
4499 12:11:38.789182 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4500 12:11:38.792439 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4501 12:11:38.798977 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4502 12:11:38.802035 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4503 12:11:38.805584 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4504 12:11:38.808789 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4505 12:11:38.815805 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4506 12:11:38.818897 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4507 12:11:38.822297 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4508 12:11:38.825418 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4509 12:11:38.831694 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4510 12:11:38.835024 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4511 12:11:38.838832 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4512 12:11:38.841878 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4513 12:11:38.848233 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4514 12:11:38.851913 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4515 12:11:38.852012 ==
4516 12:11:38.855204 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 12:11:38.858484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 12:11:38.858581 ==
4519 12:11:38.861628 DQS Delay:
4520 12:11:38.861728 DQS0 = 0, DQS1 = 0
4521 12:11:38.861818 DQM Delay:
4522 12:11:38.864760 DQM0 = 44, DQM1 = 40
4523 12:11:38.864830 DQ Delay:
4524 12:11:38.867930 DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =41
4525 12:11:38.871125 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4526 12:11:38.874408 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4527 12:11:38.877655 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4528 12:11:38.877738
4529 12:11:38.877805
4530 12:11:38.877866 ==
4531 12:11:38.881721 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 12:11:38.888028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 12:11:38.888177 ==
4534 12:11:38.888244
4535 12:11:38.888304
4536 12:11:38.888363 TX Vref Scan disable
4537 12:11:38.891816 == TX Byte 0 ==
4538 12:11:38.895177 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 12:11:38.901340 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 12:11:38.901424 == TX Byte 1 ==
4541 12:11:38.904992 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4542 12:11:38.910972 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4543 12:11:38.911056 ==
4544 12:11:38.914718 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 12:11:38.917774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 12:11:38.917858 ==
4547 12:11:38.917924
4548 12:11:38.917985
4549 12:11:38.920938 TX Vref Scan disable
4550 12:11:38.924724 == TX Byte 0 ==
4551 12:11:38.927970 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4552 12:11:38.931107 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4553 12:11:38.934252 == TX Byte 1 ==
4554 12:11:38.937551 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 12:11:38.940791 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 12:11:38.940899
4557 12:11:38.944148 [DATLAT]
4558 12:11:38.944300 Freq=600, CH1 RK0
4559 12:11:38.944407
4560 12:11:38.947443 DATLAT Default: 0x9
4561 12:11:38.947547 0, 0xFFFF, sum = 0
4562 12:11:38.950625 1, 0xFFFF, sum = 0
4563 12:11:38.950732 2, 0xFFFF, sum = 0
4564 12:11:38.954317 3, 0xFFFF, sum = 0
4565 12:11:38.954396 4, 0xFFFF, sum = 0
4566 12:11:38.957631 5, 0xFFFF, sum = 0
4567 12:11:38.957717 6, 0xFFFF, sum = 0
4568 12:11:38.960955 7, 0xFFFF, sum = 0
4569 12:11:38.961041 8, 0x0, sum = 1
4570 12:11:38.964125 9, 0x0, sum = 2
4571 12:11:38.964210 10, 0x0, sum = 3
4572 12:11:38.967226 11, 0x0, sum = 4
4573 12:11:38.967311 best_step = 9
4574 12:11:38.967378
4575 12:11:38.967440 ==
4576 12:11:38.970409 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 12:11:38.973734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 12:11:38.977006 ==
4579 12:11:38.977095 RX Vref Scan: 1
4580 12:11:38.977161
4581 12:11:38.980201 RX Vref 0 -> 0, step: 1
4582 12:11:38.980286
4583 12:11:38.983339 RX Delay -179 -> 252, step: 8
4584 12:11:38.983424
4585 12:11:38.987112 Set Vref, RX VrefLevel [Byte0]: 52
4586 12:11:38.990323 [Byte1]: 49
4587 12:11:38.990407
4588 12:11:38.993662 Final RX Vref Byte 0 = 52 to rank0
4589 12:11:38.996939 Final RX Vref Byte 1 = 49 to rank0
4590 12:11:39.000387 Final RX Vref Byte 0 = 52 to rank1
4591 12:11:39.003629 Final RX Vref Byte 1 = 49 to rank1==
4592 12:11:39.006719 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:11:39.009732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:11:39.009835 ==
4595 12:11:39.013322 DQS Delay:
4596 12:11:39.013426 DQS0 = 0, DQS1 = 0
4597 12:11:39.013518 DQM Delay:
4598 12:11:39.016202 DQM0 = 42, DQM1 = 34
4599 12:11:39.016277 DQ Delay:
4600 12:11:39.020021 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4601 12:11:39.023070 DQ4 =36, DQ5 =52, DQ6 =56, DQ7 =36
4602 12:11:39.026061 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4603 12:11:39.029935 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4604 12:11:39.030038
4605 12:11:39.030130
4606 12:11:39.039183 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
4607 12:11:39.042419 CH1 RK0: MR19=808, MR18=2A43
4608 12:11:39.046232 CH1_RK0: MR19=0x808, MR18=0x2A43, DQSOSC=397, MR23=63, INC=166, DEC=110
4609 12:11:39.049502
4610 12:11:39.052707 ----->DramcWriteLeveling(PI) begin...
4611 12:11:39.052816 ==
4612 12:11:39.055966 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 12:11:39.058995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 12:11:39.059094 ==
4615 12:11:39.062871 Write leveling (Byte 0): 30 => 30
4616 12:11:39.066083 Write leveling (Byte 1): 31 => 31
4617 12:11:39.069332 DramcWriteLeveling(PI) end<-----
4618 12:11:39.069471
4619 12:11:39.069563 ==
4620 12:11:39.072357 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 12:11:39.075596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 12:11:39.075703 ==
4623 12:11:39.078942 [Gating] SW mode calibration
4624 12:11:39.085519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4625 12:11:39.092161 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4626 12:11:39.095488 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4627 12:11:39.098802 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4628 12:11:39.105374 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4629 12:11:39.108575 0 9 12 | B1->B0 | 3232 2a2a | 1 1 | (1 0) (0 0)
4630 12:11:39.111751 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4631 12:11:39.118688 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 12:11:39.121695 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 12:11:39.125265 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 12:11:39.131897 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4635 12:11:39.135092 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 12:11:39.138253 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4637 12:11:39.144723 0 10 12 | B1->B0 | 2d2d 3939 | 0 0 | (0 0) (0 0)
4638 12:11:39.148553 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 12:11:39.151829 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 12:11:39.158235 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 12:11:39.161587 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 12:11:39.164683 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 12:11:39.171250 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 12:11:39.174388 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 12:11:39.178333 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4646 12:11:39.184824 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:11:39.188182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:11:39.190912 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:11:39.197473 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:11:39.200762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:11:39.204006 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:11:39.210664 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:11:39.213944 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:11:39.217101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:11:39.223798 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:11:39.227394 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 12:11:39.230337 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:11:39.237239 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:11:39.240355 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:11:39.243566 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4661 12:11:39.250464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4662 12:11:39.253831 Total UI for P1: 0, mck2ui 16
4663 12:11:39.256946 best dqsien dly found for B0: ( 0, 13, 8)
4664 12:11:39.260199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 12:11:39.263376 Total UI for P1: 0, mck2ui 16
4666 12:11:39.267124 best dqsien dly found for B1: ( 0, 13, 12)
4667 12:11:39.270279 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4668 12:11:39.273670 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4669 12:11:39.273754
4670 12:11:39.277058 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4671 12:11:39.280252 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4672 12:11:39.283315 [Gating] SW calibration Done
4673 12:11:39.283401 ==
4674 12:11:39.287094 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 12:11:39.292963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 12:11:39.293068 ==
4677 12:11:39.293136 RX Vref Scan: 0
4678 12:11:39.293199
4679 12:11:39.296897 RX Vref 0 -> 0, step: 1
4680 12:11:39.296980
4681 12:11:39.300057 RX Delay -230 -> 252, step: 16
4682 12:11:39.303341 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4683 12:11:39.306619 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4684 12:11:39.309925 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4685 12:11:39.316467 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4686 12:11:39.319757 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4687 12:11:39.322850 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4688 12:11:39.326361 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4689 12:11:39.332958 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4690 12:11:39.335911 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4691 12:11:39.339642 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4692 12:11:39.342657 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4693 12:11:39.349284 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4694 12:11:39.352433 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4695 12:11:39.356299 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4696 12:11:39.358862 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4697 12:11:39.366090 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4698 12:11:39.366174 ==
4699 12:11:39.369353 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 12:11:39.372436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 12:11:39.372520 ==
4702 12:11:39.372587 DQS Delay:
4703 12:11:39.375566 DQS0 = 0, DQS1 = 0
4704 12:11:39.375650 DQM Delay:
4705 12:11:39.378820 DQM0 = 42, DQM1 = 41
4706 12:11:39.378904 DQ Delay:
4707 12:11:39.382176 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4708 12:11:39.386000 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4709 12:11:39.389001 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4710 12:11:39.392210 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4711 12:11:39.392294
4712 12:11:39.392360
4713 12:11:39.392422 ==
4714 12:11:39.395339 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 12:11:39.398606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 12:11:39.398690 ==
4717 12:11:39.398757
4718 12:11:39.401794
4719 12:11:39.401877 TX Vref Scan disable
4720 12:11:39.405615 == TX Byte 0 ==
4721 12:11:39.408936 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4722 12:11:39.412280 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4723 12:11:39.415365 == TX Byte 1 ==
4724 12:11:39.418774 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4725 12:11:39.421926 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4726 12:11:39.425235 ==
4727 12:11:39.425319 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 12:11:39.431642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 12:11:39.431727 ==
4730 12:11:39.431794
4731 12:11:39.431885
4732 12:11:39.435210 TX Vref Scan disable
4733 12:11:39.435294 == TX Byte 0 ==
4734 12:11:39.441584 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 12:11:39.444677 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 12:11:39.444762 == TX Byte 1 ==
4737 12:11:39.451478 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 12:11:39.455050 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 12:11:39.455177
4740 12:11:39.455273 [DATLAT]
4741 12:11:39.457939 Freq=600, CH1 RK1
4742 12:11:39.458023
4743 12:11:39.458090 DATLAT Default: 0x9
4744 12:11:39.461625 0, 0xFFFF, sum = 0
4745 12:11:39.461710 1, 0xFFFF, sum = 0
4746 12:11:39.464708 2, 0xFFFF, sum = 0
4747 12:11:39.467916 3, 0xFFFF, sum = 0
4748 12:11:39.468001 4, 0xFFFF, sum = 0
4749 12:11:39.471152 5, 0xFFFF, sum = 0
4750 12:11:39.471236 6, 0xFFFF, sum = 0
4751 12:11:39.474313 7, 0xFFFF, sum = 0
4752 12:11:39.474398 8, 0x0, sum = 1
4753 12:11:39.474466 9, 0x0, sum = 2
4754 12:11:39.478053 10, 0x0, sum = 3
4755 12:11:39.478138 11, 0x0, sum = 4
4756 12:11:39.481289 best_step = 9
4757 12:11:39.481399
4758 12:11:39.481465 ==
4759 12:11:39.484674 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 12:11:39.487766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 12:11:39.487878 ==
4762 12:11:39.490964 RX Vref Scan: 0
4763 12:11:39.491065
4764 12:11:39.491159 RX Vref 0 -> 0, step: 1
4765 12:11:39.494003
4766 12:11:39.494074 RX Delay -179 -> 252, step: 8
4767 12:11:39.502228 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4768 12:11:39.505494 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4769 12:11:39.508926 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4770 12:11:39.512204 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4771 12:11:39.518699 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4772 12:11:39.521992 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4773 12:11:39.524580 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4774 12:11:39.527984 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4775 12:11:39.535042 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4776 12:11:39.538356 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4777 12:11:39.540993 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4778 12:11:39.544662 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4779 12:11:39.551374 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4780 12:11:39.554277 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4781 12:11:39.557501 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4782 12:11:39.561034 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4783 12:11:39.561162 ==
4784 12:11:39.564228 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 12:11:39.571109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 12:11:39.571216 ==
4787 12:11:39.571325 DQS Delay:
4788 12:11:39.574043 DQS0 = 0, DQS1 = 0
4789 12:11:39.574177 DQM Delay:
4790 12:11:39.577314 DQM0 = 37, DQM1 = 36
4791 12:11:39.577460 DQ Delay:
4792 12:11:39.580567 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4793 12:11:39.583802 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4794 12:11:39.587217 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4795 12:11:39.590335 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4796 12:11:39.590467
4797 12:11:39.590586
4798 12:11:39.597509 [DQSOSCAuto] RK1, (LSB)MR18= 0x395e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4799 12:11:39.600483 CH1 RK1: MR19=808, MR18=395E
4800 12:11:39.607030 CH1_RK1: MR19=0x808, MR18=0x395E, DQSOSC=392, MR23=63, INC=170, DEC=113
4801 12:11:39.610173 [RxdqsGatingPostProcess] freq 600
4802 12:11:39.617219 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4803 12:11:39.619866 Pre-setting of DQS Precalculation
4804 12:11:39.623193 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4805 12:11:39.629754 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4806 12:11:39.636895 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4807 12:11:39.637020
4808 12:11:39.637131
4809 12:11:39.639499 [Calibration Summary] 1200 Mbps
4810 12:11:39.642905 CH 0, Rank 0
4811 12:11:39.643014 SW Impedance : PASS
4812 12:11:39.646176 DUTY Scan : NO K
4813 12:11:39.649974 ZQ Calibration : PASS
4814 12:11:39.650061 Jitter Meter : NO K
4815 12:11:39.653233 CBT Training : PASS
4816 12:11:39.656374 Write leveling : PASS
4817 12:11:39.656490 RX DQS gating : PASS
4818 12:11:39.659582 RX DQ/DQS(RDDQC) : PASS
4819 12:11:39.662782 TX DQ/DQS : PASS
4820 12:11:39.662896 RX DATLAT : PASS
4821 12:11:39.666055 RX DQ/DQS(Engine): PASS
4822 12:11:39.669714 TX OE : NO K
4823 12:11:39.669837 All Pass.
4824 12:11:39.669938
4825 12:11:39.670039 CH 0, Rank 1
4826 12:11:39.672978 SW Impedance : PASS
4827 12:11:39.676172 DUTY Scan : NO K
4828 12:11:39.676288 ZQ Calibration : PASS
4829 12:11:39.679402 Jitter Meter : NO K
4830 12:11:39.682490 CBT Training : PASS
4831 12:11:39.682578 Write leveling : PASS
4832 12:11:39.686279 RX DQS gating : PASS
4833 12:11:39.686383 RX DQ/DQS(RDDQC) : PASS
4834 12:11:39.689023 TX DQ/DQS : PASS
4835 12:11:39.692385 RX DATLAT : PASS
4836 12:11:39.692524 RX DQ/DQS(Engine): PASS
4837 12:11:39.695843 TX OE : NO K
4838 12:11:39.695970 All Pass.
4839 12:11:39.696090
4840 12:11:39.699115 CH 1, Rank 0
4841 12:11:39.699238 SW Impedance : PASS
4842 12:11:39.702540 DUTY Scan : NO K
4843 12:11:39.705678 ZQ Calibration : PASS
4844 12:11:39.705801 Jitter Meter : NO K
4845 12:11:39.708944 CBT Training : PASS
4846 12:11:39.712441 Write leveling : PASS
4847 12:11:39.712555 RX DQS gating : PASS
4848 12:11:39.715614 RX DQ/DQS(RDDQC) : PASS
4849 12:11:39.718897 TX DQ/DQS : PASS
4850 12:11:39.719012 RX DATLAT : PASS
4851 12:11:39.722104 RX DQ/DQS(Engine): PASS
4852 12:11:39.725447 TX OE : NO K
4853 12:11:39.725536 All Pass.
4854 12:11:39.725605
4855 12:11:39.725673 CH 1, Rank 1
4856 12:11:39.728820 SW Impedance : PASS
4857 12:11:39.731953 DUTY Scan : NO K
4858 12:11:39.732070 ZQ Calibration : PASS
4859 12:11:39.735278 Jitter Meter : NO K
4860 12:11:39.738571 CBT Training : PASS
4861 12:11:39.738658 Write leveling : PASS
4862 12:11:39.741914 RX DQS gating : PASS
4863 12:11:39.745174 RX DQ/DQS(RDDQC) : PASS
4864 12:11:39.745248 TX DQ/DQS : PASS
4865 12:11:39.748282 RX DATLAT : PASS
4866 12:11:39.751687 RX DQ/DQS(Engine): PASS
4867 12:11:39.751772 TX OE : NO K
4868 12:11:39.755072 All Pass.
4869 12:11:39.755156
4870 12:11:39.755223 DramC Write-DBI off
4871 12:11:39.758217 PER_BANK_REFRESH: Hybrid Mode
4872 12:11:39.758292 TX_TRACKING: ON
4873 12:11:39.768115 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4874 12:11:39.771103 [FAST_K] Save calibration result to emmc
4875 12:11:39.774894 dramc_set_vcore_voltage set vcore to 662500
4876 12:11:39.777950 Read voltage for 933, 3
4877 12:11:39.778057 Vio18 = 0
4878 12:11:39.781040 Vcore = 662500
4879 12:11:39.781141 Vdram = 0
4880 12:11:39.781232 Vddq = 0
4881 12:11:39.784830 Vmddr = 0
4882 12:11:39.787885 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4883 12:11:39.794257 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4884 12:11:39.794345 MEM_TYPE=3, freq_sel=17
4885 12:11:39.797534 sv_algorithm_assistance_LP4_1600
4886 12:11:39.804112 ============ PULL DRAM RESETB DOWN ============
4887 12:11:39.807868 ========== PULL DRAM RESETB DOWN end =========
4888 12:11:39.810795 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4889 12:11:39.814220 ===================================
4890 12:11:39.817424 LPDDR4 DRAM CONFIGURATION
4891 12:11:39.820665 ===================================
4892 12:11:39.824574 EX_ROW_EN[0] = 0x0
4893 12:11:39.824659 EX_ROW_EN[1] = 0x0
4894 12:11:39.827155 LP4Y_EN = 0x0
4895 12:11:39.827240 WORK_FSP = 0x0
4896 12:11:39.830580 WL = 0x3
4897 12:11:39.830667 RL = 0x3
4898 12:11:39.833881 BL = 0x2
4899 12:11:39.833966 RPST = 0x0
4900 12:11:39.837215 RD_PRE = 0x0
4901 12:11:39.837300 WR_PRE = 0x1
4902 12:11:39.840432 WR_PST = 0x0
4903 12:11:39.840516 DBI_WR = 0x0
4904 12:11:39.843727 DBI_RD = 0x0
4905 12:11:39.843813 OTF = 0x1
4906 12:11:39.847040 ===================================
4907 12:11:39.850339 ===================================
4908 12:11:39.853653 ANA top config
4909 12:11:39.856861 ===================================
4910 12:11:39.860497 DLL_ASYNC_EN = 0
4911 12:11:39.860604 ALL_SLAVE_EN = 1
4912 12:11:39.863830 NEW_RANK_MODE = 1
4913 12:11:39.866807 DLL_IDLE_MODE = 1
4914 12:11:39.870570 LP45_APHY_COMB_EN = 1
4915 12:11:39.873607 TX_ODT_DIS = 1
4916 12:11:39.873719 NEW_8X_MODE = 1
4917 12:11:39.876763 ===================================
4918 12:11:39.879940 ===================================
4919 12:11:39.883517 data_rate = 1866
4920 12:11:39.886748 CKR = 1
4921 12:11:39.889866 DQ_P2S_RATIO = 8
4922 12:11:39.893112 ===================================
4923 12:11:39.896438 CA_P2S_RATIO = 8
4924 12:11:39.899666 DQ_CA_OPEN = 0
4925 12:11:39.899797 DQ_SEMI_OPEN = 0
4926 12:11:39.902996 CA_SEMI_OPEN = 0
4927 12:11:39.906333 CA_FULL_RATE = 0
4928 12:11:39.909661 DQ_CKDIV4_EN = 1
4929 12:11:39.913092 CA_CKDIV4_EN = 1
4930 12:11:39.916223 CA_PREDIV_EN = 0
4931 12:11:39.916307 PH8_DLY = 0
4932 12:11:39.919590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4933 12:11:39.922891 DQ_AAMCK_DIV = 4
4934 12:11:39.926083 CA_AAMCK_DIV = 4
4935 12:11:39.929306 CA_ADMCK_DIV = 4
4936 12:11:39.932606 DQ_TRACK_CA_EN = 0
4937 12:11:39.935930 CA_PICK = 933
4938 12:11:39.936044 CA_MCKIO = 933
4939 12:11:39.939251 MCKIO_SEMI = 0
4940 12:11:39.942360 PLL_FREQ = 3732
4941 12:11:39.945694 DQ_UI_PI_RATIO = 32
4942 12:11:39.948891 CA_UI_PI_RATIO = 0
4943 12:11:39.952183 ===================================
4944 12:11:39.955378 ===================================
4945 12:11:39.959336 memory_type:LPDDR4
4946 12:11:39.959418 GP_NUM : 10
4947 12:11:39.962524 SRAM_EN : 1
4948 12:11:39.962631 MD32_EN : 0
4949 12:11:39.965469 ===================================
4950 12:11:39.968672 [ANA_INIT] >>>>>>>>>>>>>>
4951 12:11:39.972385 <<<<<< [CONFIGURE PHASE]: ANA_TX
4952 12:11:39.975617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4953 12:11:39.978642 ===================================
4954 12:11:39.981778 data_rate = 1866,PCW = 0X8f00
4955 12:11:39.985111 ===================================
4956 12:11:39.988362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4957 12:11:39.995058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4958 12:11:39.998145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4959 12:11:40.005005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4960 12:11:40.008346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4961 12:11:40.011589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4962 12:11:40.011728 [ANA_INIT] flow start
4963 12:11:40.014871 [ANA_INIT] PLL >>>>>>>>
4964 12:11:40.018022 [ANA_INIT] PLL <<<<<<<<
4965 12:11:40.021237 [ANA_INIT] MIDPI >>>>>>>>
4966 12:11:40.021348 [ANA_INIT] MIDPI <<<<<<<<
4967 12:11:40.024404 [ANA_INIT] DLL >>>>>>>>
4968 12:11:40.027596 [ANA_INIT] flow end
4969 12:11:40.030968 ============ LP4 DIFF to SE enter ============
4970 12:11:40.034157 ============ LP4 DIFF to SE exit ============
4971 12:11:40.037580 [ANA_INIT] <<<<<<<<<<<<<
4972 12:11:40.040899 [Flow] Enable top DCM control >>>>>
4973 12:11:40.044017 [Flow] Enable top DCM control <<<<<
4974 12:11:40.047335 Enable DLL master slave shuffle
4975 12:11:40.050623 ==============================================================
4976 12:11:40.053913 Gating Mode config
4977 12:11:40.060608 ==============================================================
4978 12:11:40.060734 Config description:
4979 12:11:40.070631 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4980 12:11:40.077025 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4981 12:11:40.083635 SELPH_MODE 0: By rank 1: By Phase
4982 12:11:40.086722 ==============================================================
4983 12:11:40.090556 GAT_TRACK_EN = 1
4984 12:11:40.093649 RX_GATING_MODE = 2
4985 12:11:40.096790 RX_GATING_TRACK_MODE = 2
4986 12:11:40.100012 SELPH_MODE = 1
4987 12:11:40.103150 PICG_EARLY_EN = 1
4988 12:11:40.106872 VALID_LAT_VALUE = 1
4989 12:11:40.113242 ==============================================================
4990 12:11:40.116400 Enter into Gating configuration >>>>
4991 12:11:40.119680 Exit from Gating configuration <<<<
4992 12:11:40.119785 Enter into DVFS_PRE_config >>>>>
4993 12:11:40.132768 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4994 12:11:40.135992 Exit from DVFS_PRE_config <<<<<
4995 12:11:40.139310 Enter into PICG configuration >>>>
4996 12:11:40.142582 Exit from PICG configuration <<<<
4997 12:11:40.145973 [RX_INPUT] configuration >>>>>
4998 12:11:40.146060 [RX_INPUT] configuration <<<<<
4999 12:11:40.152537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5000 12:11:40.159771 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5001 12:11:40.162962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 12:11:40.169381 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 12:11:40.175839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5004 12:11:40.182335 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5005 12:11:40.185546 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5006 12:11:40.189165 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5007 12:11:40.195510 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5008 12:11:40.198628 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5009 12:11:40.202004 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5010 12:11:40.208865 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5011 12:11:40.211818 ===================================
5012 12:11:40.211946 LPDDR4 DRAM CONFIGURATION
5013 12:11:40.215029 ===================================
5014 12:11:40.219026 EX_ROW_EN[0] = 0x0
5015 12:11:40.221501 EX_ROW_EN[1] = 0x0
5016 12:11:40.221613 LP4Y_EN = 0x0
5017 12:11:40.224756 WORK_FSP = 0x0
5018 12:11:40.224867 WL = 0x3
5019 12:11:40.228644 RL = 0x3
5020 12:11:40.228753 BL = 0x2
5021 12:11:40.231936 RPST = 0x0
5022 12:11:40.232046 RD_PRE = 0x0
5023 12:11:40.235238 WR_PRE = 0x1
5024 12:11:40.235318 WR_PST = 0x0
5025 12:11:40.238630 DBI_WR = 0x0
5026 12:11:40.238731 DBI_RD = 0x0
5027 12:11:40.241839 OTF = 0x1
5028 12:11:40.244612 ===================================
5029 12:11:40.248004 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5030 12:11:40.251393 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5031 12:11:40.258032 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5032 12:11:40.261394 ===================================
5033 12:11:40.261477 LPDDR4 DRAM CONFIGURATION
5034 12:11:40.264560 ===================================
5035 12:11:40.267779 EX_ROW_EN[0] = 0x10
5036 12:11:40.270985 EX_ROW_EN[1] = 0x0
5037 12:11:40.271074 LP4Y_EN = 0x0
5038 12:11:40.274924 WORK_FSP = 0x0
5039 12:11:40.275049 WL = 0x3
5040 12:11:40.277544 RL = 0x3
5041 12:11:40.277628 BL = 0x2
5042 12:11:40.281179 RPST = 0x0
5043 12:11:40.281270 RD_PRE = 0x0
5044 12:11:40.284362 WR_PRE = 0x1
5045 12:11:40.284462 WR_PST = 0x0
5046 12:11:40.287569 DBI_WR = 0x0
5047 12:11:40.287694 DBI_RD = 0x0
5048 12:11:40.290825 OTF = 0x1
5049 12:11:40.293951 ===================================
5050 12:11:40.300901 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5051 12:11:40.304216 nWR fixed to 30
5052 12:11:40.307242 [ModeRegInit_LP4] CH0 RK0
5053 12:11:40.307357 [ModeRegInit_LP4] CH0 RK1
5054 12:11:40.310407 [ModeRegInit_LP4] CH1 RK0
5055 12:11:40.313669 [ModeRegInit_LP4] CH1 RK1
5056 12:11:40.313780 match AC timing 9
5057 12:11:40.320523 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5058 12:11:40.323767 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5059 12:11:40.327053 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5060 12:11:40.333420 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5061 12:11:40.336789 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5062 12:11:40.336877 ==
5063 12:11:40.340147 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 12:11:40.343449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 12:11:40.343528 ==
5066 12:11:40.350073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 12:11:40.356503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5068 12:11:40.359859 [CA 0] Center 37 (7~68) winsize 62
5069 12:11:40.362969 [CA 1] Center 37 (7~68) winsize 62
5070 12:11:40.366946 [CA 2] Center 35 (5~65) winsize 61
5071 12:11:40.370147 [CA 3] Center 34 (4~65) winsize 62
5072 12:11:40.373020 [CA 4] Center 33 (3~64) winsize 62
5073 12:11:40.376055 [CA 5] Center 33 (3~63) winsize 61
5074 12:11:40.376142
5075 12:11:40.379981 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5076 12:11:40.380105
5077 12:11:40.383173 [CATrainingPosCal] consider 1 rank data
5078 12:11:40.386181 u2DelayCellTimex100 = 270/100 ps
5079 12:11:40.389592 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5080 12:11:40.393244 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5081 12:11:40.396220 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5082 12:11:40.403166 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5083 12:11:40.406384 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5084 12:11:40.409351 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5085 12:11:40.409436
5086 12:11:40.412435 CA PerBit enable=1, Macro0, CA PI delay=33
5087 12:11:40.412521
5088 12:11:40.415933 [CBTSetCACLKResult] CA Dly = 33
5089 12:11:40.416052 CS Dly: 6 (0~37)
5090 12:11:40.416123 ==
5091 12:11:40.419173 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 12:11:40.426091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 12:11:40.426180 ==
5094 12:11:40.429308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5095 12:11:40.435657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5096 12:11:40.438878 [CA 0] Center 38 (8~68) winsize 61
5097 12:11:40.442302 [CA 1] Center 38 (7~69) winsize 63
5098 12:11:40.445708 [CA 2] Center 35 (5~65) winsize 61
5099 12:11:40.449069 [CA 3] Center 34 (4~65) winsize 62
5100 12:11:40.452326 [CA 4] Center 33 (3~64) winsize 62
5101 12:11:40.455498 [CA 5] Center 33 (2~64) winsize 63
5102 12:11:40.455603
5103 12:11:40.458850 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5104 12:11:40.458974
5105 12:11:40.462214 [CATrainingPosCal] consider 2 rank data
5106 12:11:40.465563 u2DelayCellTimex100 = 270/100 ps
5107 12:11:40.468991 CA0 delay=38 (8~68),Diff = 5 PI (31 cell)
5108 12:11:40.475608 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5109 12:11:40.478799 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5110 12:11:40.482144 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5111 12:11:40.485230 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5112 12:11:40.488538 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5113 12:11:40.488645
5114 12:11:40.491610 CA PerBit enable=1, Macro0, CA PI delay=33
5115 12:11:40.491716
5116 12:11:40.494844 [CBTSetCACLKResult] CA Dly = 33
5117 12:11:40.498599 CS Dly: 7 (0~39)
5118 12:11:40.498790
5119 12:11:40.501924 ----->DramcWriteLeveling(PI) begin...
5120 12:11:40.502034 ==
5121 12:11:40.504999 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 12:11:40.508133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 12:11:40.508214 ==
5124 12:11:40.511433 Write leveling (Byte 0): 30 => 30
5125 12:11:40.515327 Write leveling (Byte 1): 27 => 27
5126 12:11:40.518394 DramcWriteLeveling(PI) end<-----
5127 12:11:40.518500
5128 12:11:40.518599 ==
5129 12:11:40.521334 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 12:11:40.525169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 12:11:40.525272 ==
5132 12:11:40.528185 [Gating] SW mode calibration
5133 12:11:40.534912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5134 12:11:40.541423 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5135 12:11:40.544632 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5136 12:11:40.547865 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 12:11:40.554494 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 12:11:40.557763 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 12:11:40.561048 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 12:11:40.567412 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 12:11:40.570786 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5142 12:11:40.574102 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
5143 12:11:40.580933 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
5144 12:11:40.584147 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 12:11:40.587365 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 12:11:40.594036 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 12:11:40.597188 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 12:11:40.600295 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 12:11:40.607063 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 12:11:40.610820 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5151 12:11:40.614000 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
5152 12:11:40.620284 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 12:11:40.623976 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 12:11:40.626981 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 12:11:40.633812 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 12:11:40.636557 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 12:11:40.640524 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 12:11:40.646915 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5159 12:11:40.650171 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5160 12:11:40.653520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:11:40.660119 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:11:40.663386 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:11:40.666637 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:11:40.673126 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:11:40.676312 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:11:40.679612 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:11:40.686058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:11:40.689192 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:11:40.693102 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:11:40.699346 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 12:11:40.702543 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 12:11:40.705721 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 12:11:40.712405 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5174 12:11:40.715584 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5175 12:11:40.718808 Total UI for P1: 0, mck2ui 16
5176 12:11:40.722722 best dqsien dly found for B0: ( 1, 2, 24)
5177 12:11:40.725733 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5178 12:11:40.732192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5179 12:11:40.735415 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 12:11:40.738555 Total UI for P1: 0, mck2ui 16
5181 12:11:40.741907 best dqsien dly found for B1: ( 1, 3, 2)
5182 12:11:40.745107 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5183 12:11:40.748472 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5184 12:11:40.748555
5185 12:11:40.752441 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5186 12:11:40.758210 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5187 12:11:40.758293 [Gating] SW calibration Done
5188 12:11:40.758360 ==
5189 12:11:40.761537 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 12:11:40.768201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 12:11:40.768284 ==
5192 12:11:40.768351 RX Vref Scan: 0
5193 12:11:40.768412
5194 12:11:40.771523 RX Vref 0 -> 0, step: 1
5195 12:11:40.771642
5196 12:11:40.774741 RX Delay -80 -> 252, step: 8
5197 12:11:40.778127 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5198 12:11:40.781352 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5199 12:11:40.784693 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5200 12:11:40.791564 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5201 12:11:40.794901 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5202 12:11:40.798161 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5203 12:11:40.801531 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5204 12:11:40.804717 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5205 12:11:40.810974 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5206 12:11:40.814219 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5207 12:11:40.817372 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5208 12:11:40.821128 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5209 12:11:40.824175 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5210 12:11:40.831113 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5211 12:11:40.834363 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5212 12:11:40.837423 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5213 12:11:40.837564 ==
5214 12:11:40.840600 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 12:11:40.843906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 12:11:40.844028 ==
5217 12:11:40.847145 DQS Delay:
5218 12:11:40.847245 DQS0 = 0, DQS1 = 0
5219 12:11:40.850344 DQM Delay:
5220 12:11:40.850451 DQM0 = 103, DQM1 = 88
5221 12:11:40.850566 DQ Delay:
5222 12:11:40.853484 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5223 12:11:40.856838 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =107
5224 12:11:40.860173 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5225 12:11:40.864080 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5226 12:11:40.866631
5227 12:11:40.866737
5228 12:11:40.866846 ==
5229 12:11:40.869972 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 12:11:40.873800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 12:11:40.873910 ==
5232 12:11:40.874007
5233 12:11:40.874104
5234 12:11:40.876562 TX Vref Scan disable
5235 12:11:40.876639 == TX Byte 0 ==
5236 12:11:40.883220 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5237 12:11:40.886501 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5238 12:11:40.886611 == TX Byte 1 ==
5239 12:11:40.893523 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5240 12:11:40.896733 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5241 12:11:40.896866 ==
5242 12:11:40.899523 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 12:11:40.903482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 12:11:40.903599 ==
5245 12:11:40.903703
5246 12:11:40.903816
5247 12:11:40.906099 TX Vref Scan disable
5248 12:11:40.910067 == TX Byte 0 ==
5249 12:11:40.913356 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5250 12:11:40.916461 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5251 12:11:40.919627 == TX Byte 1 ==
5252 12:11:40.922885 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5253 12:11:40.926559 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5254 12:11:40.926645
5255 12:11:40.929834 [DATLAT]
5256 12:11:40.929919 Freq=933, CH0 RK0
5257 12:11:40.929988
5258 12:11:40.932986 DATLAT Default: 0xd
5259 12:11:40.933073 0, 0xFFFF, sum = 0
5260 12:11:40.935924 1, 0xFFFF, sum = 0
5261 12:11:40.936046 2, 0xFFFF, sum = 0
5262 12:11:40.939174 3, 0xFFFF, sum = 0
5263 12:11:40.939287 4, 0xFFFF, sum = 0
5264 12:11:40.943021 5, 0xFFFF, sum = 0
5265 12:11:40.946250 6, 0xFFFF, sum = 0
5266 12:11:40.946336 7, 0xFFFF, sum = 0
5267 12:11:40.949541 8, 0xFFFF, sum = 0
5268 12:11:40.949616 9, 0xFFFF, sum = 0
5269 12:11:40.952985 10, 0x0, sum = 1
5270 12:11:40.953070 11, 0x0, sum = 2
5271 12:11:40.955652 12, 0x0, sum = 3
5272 12:11:40.955738 13, 0x0, sum = 4
5273 12:11:40.955807 best_step = 11
5274 12:11:40.955869
5275 12:11:40.958934 ==
5276 12:11:40.962197 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 12:11:40.965589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 12:11:40.965701 ==
5279 12:11:40.965798 RX Vref Scan: 1
5280 12:11:40.965889
5281 12:11:40.968828 RX Vref 0 -> 0, step: 1
5282 12:11:40.968901
5283 12:11:40.972197 RX Delay -61 -> 252, step: 4
5284 12:11:40.972281
5285 12:11:40.975370 Set Vref, RX VrefLevel [Byte0]: 57
5286 12:11:40.978749 [Byte1]: 49
5287 12:11:40.978859
5288 12:11:40.981973 Final RX Vref Byte 0 = 57 to rank0
5289 12:11:40.985188 Final RX Vref Byte 1 = 49 to rank0
5290 12:11:40.989031 Final RX Vref Byte 0 = 57 to rank1
5291 12:11:40.991915 Final RX Vref Byte 1 = 49 to rank1==
5292 12:11:40.995790 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 12:11:41.002217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 12:11:41.002327 ==
5295 12:11:41.002436 DQS Delay:
5296 12:11:41.002531 DQS0 = 0, DQS1 = 0
5297 12:11:41.005635 DQM Delay:
5298 12:11:41.005749 DQM0 = 103, DQM1 = 90
5299 12:11:41.008858 DQ Delay:
5300 12:11:41.012184 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5301 12:11:41.015395 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5302 12:11:41.018748 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =84
5303 12:11:41.021906 DQ12 =98, DQ13 =92, DQ14 =100, DQ15 =100
5304 12:11:41.021987
5305 12:11:41.022053
5306 12:11:41.028218 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5307 12:11:41.032013 CH0 RK0: MR19=505, MR18=1B15
5308 12:11:41.038241 CH0_RK0: MR19=0x505, MR18=0x1B15, DQSOSC=413, MR23=63, INC=63, DEC=42
5309 12:11:41.038329
5310 12:11:41.041341 ----->DramcWriteLeveling(PI) begin...
5311 12:11:41.041423 ==
5312 12:11:41.044714 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 12:11:41.048485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 12:11:41.048602 ==
5315 12:11:41.051704 Write leveling (Byte 0): 33 => 33
5316 12:11:41.055053 Write leveling (Byte 1): 27 => 27
5317 12:11:41.057732 DramcWriteLeveling(PI) end<-----
5318 12:11:41.057832
5319 12:11:41.057911 ==
5320 12:11:41.061711 Dram Type= 6, Freq= 0, CH_0, rank 1
5321 12:11:41.068185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 12:11:41.068286 ==
5323 12:11:41.068356 [Gating] SW mode calibration
5324 12:11:41.078166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5325 12:11:41.081552 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5326 12:11:41.088009 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5327 12:11:41.091277 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 12:11:41.094678 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 12:11:41.097884 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 12:11:41.104506 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 12:11:41.107773 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 12:11:41.114229 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5333 12:11:41.117396 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 1)
5334 12:11:41.120520 0 15 0 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (1 1)
5335 12:11:41.127387 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5336 12:11:41.130472 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 12:11:41.134205 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 12:11:41.140500 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 12:11:41.143628 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 12:11:41.146748 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 12:11:41.153657 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
5342 12:11:41.156968 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5343 12:11:41.160166 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 12:11:41.166543 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 12:11:41.169798 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:11:41.173744 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 12:11:41.180190 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 12:11:41.183438 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 12:11:41.186834 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 12:11:41.193119 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5351 12:11:41.196438 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:11:41.199580 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:11:41.206404 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:11:41.209658 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:11:41.212854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:11:41.219257 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:11:41.222557 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:11:41.225752 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:11:41.232491 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:11:41.236191 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 12:11:41.239236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:11:41.245976 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:11:41.249120 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:11:41.252174 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:11:41.258904 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5366 12:11:41.259009 Total UI for P1: 0, mck2ui 16
5367 12:11:41.265478 best dqsien dly found for B0: ( 1, 2, 26)
5368 12:11:41.268651 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5369 12:11:41.272408 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 12:11:41.275677 Total UI for P1: 0, mck2ui 16
5371 12:11:41.278922 best dqsien dly found for B1: ( 1, 2, 30)
5372 12:11:41.282250 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5373 12:11:41.285442 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5374 12:11:41.285518
5375 12:11:41.291833 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5376 12:11:41.295245 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5377 12:11:41.298293 [Gating] SW calibration Done
5378 12:11:41.298410 ==
5379 12:11:41.301593 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 12:11:41.304802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 12:11:41.304918 ==
5382 12:11:41.305015 RX Vref Scan: 0
5383 12:11:41.305109
5384 12:11:41.308022 RX Vref 0 -> 0, step: 1
5385 12:11:41.308138
5386 12:11:41.311284 RX Delay -80 -> 252, step: 8
5387 12:11:41.314683 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5388 12:11:41.317772 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5389 12:11:41.324262 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5390 12:11:41.328121 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5391 12:11:41.331310 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5392 12:11:41.334483 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5393 12:11:41.337642 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5394 12:11:41.341268 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5395 12:11:41.347438 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5396 12:11:41.350555 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5397 12:11:41.353851 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5398 12:11:41.357608 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5399 12:11:41.360512 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5400 12:11:41.367532 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5401 12:11:41.370248 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5402 12:11:41.374058 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5403 12:11:41.374162 ==
5404 12:11:41.377061 Dram Type= 6, Freq= 0, CH_0, rank 1
5405 12:11:41.380350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5406 12:11:41.380453 ==
5407 12:11:41.383674 DQS Delay:
5408 12:11:41.383776 DQS0 = 0, DQS1 = 0
5409 12:11:41.386870 DQM Delay:
5410 12:11:41.386981 DQM0 = 100, DQM1 = 88
5411 12:11:41.387075 DQ Delay:
5412 12:11:41.390243 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =95
5413 12:11:41.393587 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5414 12:11:41.396956 DQ8 =79, DQ9 =71, DQ10 =91, DQ11 =83
5415 12:11:41.400259 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5416 12:11:41.403596
5417 12:11:41.403679
5418 12:11:41.403747 ==
5419 12:11:41.406852 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 12:11:41.410191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 12:11:41.410277 ==
5422 12:11:41.410344
5423 12:11:41.410406
5424 12:11:41.413289 TX Vref Scan disable
5425 12:11:41.413372 == TX Byte 0 ==
5426 12:11:41.419693 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5427 12:11:41.423126 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5428 12:11:41.423214 == TX Byte 1 ==
5429 12:11:41.429599 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5430 12:11:41.433485 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5431 12:11:41.433571 ==
5432 12:11:41.436437 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 12:11:41.439510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 12:11:41.439590 ==
5435 12:11:41.439668
5436 12:11:41.442782
5437 12:11:41.442893 TX Vref Scan disable
5438 12:11:41.446378 == TX Byte 0 ==
5439 12:11:41.449585 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5440 12:11:41.452737 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5441 12:11:41.456195 == TX Byte 1 ==
5442 12:11:41.459393 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5443 12:11:41.463009 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5444 12:11:41.466197
5445 12:11:41.466325 [DATLAT]
5446 12:11:41.466438 Freq=933, CH0 RK1
5447 12:11:41.466531
5448 12:11:41.469427 DATLAT Default: 0xb
5449 12:11:41.469607 0, 0xFFFF, sum = 0
5450 12:11:41.472614 1, 0xFFFF, sum = 0
5451 12:11:41.472730 2, 0xFFFF, sum = 0
5452 12:11:41.475861 3, 0xFFFF, sum = 0
5453 12:11:41.479111 4, 0xFFFF, sum = 0
5454 12:11:41.479270 5, 0xFFFF, sum = 0
5455 12:11:41.482280 6, 0xFFFF, sum = 0
5456 12:11:41.482430 7, 0xFFFF, sum = 0
5457 12:11:41.485564 8, 0xFFFF, sum = 0
5458 12:11:41.485726 9, 0xFFFF, sum = 0
5459 12:11:41.488880 10, 0x0, sum = 1
5460 12:11:41.488997 11, 0x0, sum = 2
5461 12:11:41.492138 12, 0x0, sum = 3
5462 12:11:41.492249 13, 0x0, sum = 4
5463 12:11:41.492349 best_step = 11
5464 12:11:41.495434
5465 12:11:41.495511 ==
5466 12:11:41.498744 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 12:11:41.501945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 12:11:41.502103 ==
5469 12:11:41.502205 RX Vref Scan: 0
5470 12:11:41.502303
5471 12:11:41.505923 RX Vref 0 -> 0, step: 1
5472 12:11:41.506018
5473 12:11:41.509150 RX Delay -69 -> 252, step: 4
5474 12:11:41.515771 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5475 12:11:41.519147 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5476 12:11:41.521816 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5477 12:11:41.525119 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5478 12:11:41.528369 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5479 12:11:41.531819 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5480 12:11:41.538679 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5481 12:11:41.541776 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5482 12:11:41.545030 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5483 12:11:41.548338 iDelay=195, Bit 9, Center 80 (-5 ~ 166) 172
5484 12:11:41.551501 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5485 12:11:41.558504 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5486 12:11:41.561238 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5487 12:11:41.565018 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5488 12:11:41.568061 iDelay=195, Bit 14, Center 102 (15 ~ 190) 176
5489 12:11:41.571222 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5490 12:11:41.574566 ==
5491 12:11:41.577889 Dram Type= 6, Freq= 0, CH_0, rank 1
5492 12:11:41.581115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 12:11:41.581225 ==
5494 12:11:41.581320 DQS Delay:
5495 12:11:41.584517 DQS0 = 0, DQS1 = 0
5496 12:11:41.584637 DQM Delay:
5497 12:11:41.587760 DQM0 = 101, DQM1 = 90
5498 12:11:41.587873 DQ Delay:
5499 12:11:41.591023 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5500 12:11:41.594264 DQ4 =104, DQ5 =92, DQ6 =108, DQ7 =108
5501 12:11:41.597536 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
5502 12:11:41.600739 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =96
5503 12:11:41.600839
5504 12:11:41.600910
5505 12:11:41.611080 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5506 12:11:41.611178 CH0 RK1: MR19=505, MR18=1411
5507 12:11:41.617578 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5508 12:11:41.620842 [RxdqsGatingPostProcess] freq 933
5509 12:11:41.627414 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5510 12:11:41.630657 best DQS0 dly(2T, 0.5T) = (0, 10)
5511 12:11:41.634151 best DQS1 dly(2T, 0.5T) = (0, 11)
5512 12:11:41.637353 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5513 12:11:41.640687 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5514 12:11:41.643943 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 12:11:41.644065 best DQS1 dly(2T, 0.5T) = (0, 10)
5516 12:11:41.647112 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 12:11:41.650280 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5518 12:11:41.653609 Pre-setting of DQS Precalculation
5519 12:11:41.660307 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5520 12:11:41.660392 ==
5521 12:11:41.663546 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 12:11:41.666835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 12:11:41.666923 ==
5524 12:11:41.673718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5525 12:11:41.680063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5526 12:11:41.683475 [CA 0] Center 36 (6~67) winsize 62
5527 12:11:41.686704 [CA 1] Center 36 (6~67) winsize 62
5528 12:11:41.689881 [CA 2] Center 34 (4~65) winsize 62
5529 12:11:41.693181 [CA 3] Center 33 (3~64) winsize 62
5530 12:11:41.696446 [CA 4] Center 33 (3~64) winsize 62
5531 12:11:41.699817 [CA 5] Center 33 (3~64) winsize 62
5532 12:11:41.699899
5533 12:11:41.703027 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5534 12:11:41.703105
5535 12:11:41.706315 [CATrainingPosCal] consider 1 rank data
5536 12:11:41.709731 u2DelayCellTimex100 = 270/100 ps
5537 12:11:41.712951 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5538 12:11:41.716250 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 12:11:41.719454 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5540 12:11:41.722814 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 12:11:41.729431 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 12:11:41.732824 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5543 12:11:41.732902
5544 12:11:41.735476 CA PerBit enable=1, Macro0, CA PI delay=33
5545 12:11:41.735555
5546 12:11:41.738797 [CBTSetCACLKResult] CA Dly = 33
5547 12:11:41.738871 CS Dly: 5 (0~36)
5548 12:11:41.738935 ==
5549 12:11:41.742869 Dram Type= 6, Freq= 0, CH_1, rank 1
5550 12:11:41.749333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 12:11:41.749413 ==
5552 12:11:41.752316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5553 12:11:41.758599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5554 12:11:41.761906 [CA 0] Center 36 (6~67) winsize 62
5555 12:11:41.765629 [CA 1] Center 36 (6~67) winsize 62
5556 12:11:41.769123 [CA 2] Center 34 (4~65) winsize 62
5557 12:11:41.772235 [CA 3] Center 33 (3~64) winsize 62
5558 12:11:41.775453 [CA 4] Center 33 (3~64) winsize 62
5559 12:11:41.778808 [CA 5] Center 33 (3~64) winsize 62
5560 12:11:41.778885
5561 12:11:41.782069 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5562 12:11:41.782144
5563 12:11:41.785389 [CATrainingPosCal] consider 2 rank data
5564 12:11:41.788685 u2DelayCellTimex100 = 270/100 ps
5565 12:11:41.791857 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 12:11:41.795251 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5567 12:11:41.801966 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 12:11:41.805348 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5569 12:11:41.808591 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 12:11:41.811760 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5571 12:11:41.811878
5572 12:11:41.814923 CA PerBit enable=1, Macro0, CA PI delay=33
5573 12:11:41.815009
5574 12:11:41.818158 [CBTSetCACLKResult] CA Dly = 33
5575 12:11:41.818245 CS Dly: 6 (0~38)
5576 12:11:41.821373
5577 12:11:41.824480 ----->DramcWriteLeveling(PI) begin...
5578 12:11:41.824567 ==
5579 12:11:41.828448 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 12:11:41.831072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 12:11:41.831159 ==
5582 12:11:41.834866 Write leveling (Byte 0): 27 => 27
5583 12:11:41.838229 Write leveling (Byte 1): 27 => 27
5584 12:11:41.841546 DramcWriteLeveling(PI) end<-----
5585 12:11:41.841631
5586 12:11:41.841698 ==
5587 12:11:41.844884 Dram Type= 6, Freq= 0, CH_1, rank 0
5588 12:11:41.848157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 12:11:41.848244 ==
5590 12:11:41.850769 [Gating] SW mode calibration
5591 12:11:41.857893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5592 12:11:41.864201 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5593 12:11:41.867435 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 12:11:41.870572 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 12:11:41.877352 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 12:11:41.880410 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 12:11:41.884024 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 12:11:41.890405 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 12:11:41.893828 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5600 12:11:41.896905 0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (1 0)
5601 12:11:41.903574 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 12:11:41.906836 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 12:11:41.909985 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 12:11:41.916832 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 12:11:41.920108 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 12:11:41.923432 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 12:11:41.930113 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5608 12:11:41.933344 0 15 28 | B1->B0 | 3a3a 4040 | 0 0 | (1 1) (0 0)
5609 12:11:41.939523 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 12:11:41.942795 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 12:11:41.946089 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 12:11:41.952636 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:11:41.955871 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:11:41.959224 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 12:11:41.965607 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5616 12:11:41.969530 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5617 12:11:41.972758 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5618 12:11:41.979291 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:11:41.982402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:11:41.985533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:11:41.992214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:11:41.995449 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:11:41.998760 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:11:42.005060 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:11:42.008907 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:11:42.012225 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:11:42.018679 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:11:42.021868 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:11:42.025093 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:11:42.031508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:11:42.034877 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 12:11:42.038126 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5633 12:11:42.044812 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5634 12:11:42.044928 Total UI for P1: 0, mck2ui 16
5635 12:11:42.051329 best dqsien dly found for B0: ( 1, 2, 26)
5636 12:11:42.054575 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 12:11:42.057936 Total UI for P1: 0, mck2ui 16
5638 12:11:42.061645 best dqsien dly found for B1: ( 1, 2, 28)
5639 12:11:42.064885 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5640 12:11:42.068139 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5641 12:11:42.068225
5642 12:11:42.071259 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5643 12:11:42.074446 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5644 12:11:42.077640 [Gating] SW calibration Done
5645 12:11:42.077727 ==
5646 12:11:42.081291 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 12:11:42.084209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 12:11:42.087850 ==
5649 12:11:42.087941 RX Vref Scan: 0
5650 12:11:42.088012
5651 12:11:42.090892 RX Vref 0 -> 0, step: 1
5652 12:11:42.090978
5653 12:11:42.094512 RX Delay -80 -> 252, step: 8
5654 12:11:42.097695 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5655 12:11:42.100994 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5656 12:11:42.104217 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5657 12:11:42.107444 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5658 12:11:42.111163 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5659 12:11:42.117658 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5660 12:11:42.120915 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5661 12:11:42.124155 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5662 12:11:42.127284 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5663 12:11:42.130467 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5664 12:11:42.134160 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5665 12:11:42.140825 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5666 12:11:42.144027 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5667 12:11:42.146884 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5668 12:11:42.150115 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5669 12:11:42.153371 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5670 12:11:42.157176 ==
5671 12:11:42.160413 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 12:11:42.163548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 12:11:42.163660 ==
5674 12:11:42.163773 DQS Delay:
5675 12:11:42.166799 DQS0 = 0, DQS1 = 0
5676 12:11:42.166912 DQM Delay:
5677 12:11:42.170096 DQM0 = 98, DQM1 = 95
5678 12:11:42.170205 DQ Delay:
5679 12:11:42.173336 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5680 12:11:42.176437 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5681 12:11:42.180216 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =91
5682 12:11:42.183533 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5683 12:11:42.183639
5684 12:11:42.183744
5685 12:11:42.183837 ==
5686 12:11:42.186616 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 12:11:42.189670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 12:11:42.193190 ==
5689 12:11:42.193278
5690 12:11:42.193345
5691 12:11:42.193440 TX Vref Scan disable
5692 12:11:42.196227 == TX Byte 0 ==
5693 12:11:42.199747 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5694 12:11:42.202965 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5695 12:11:42.206096 == TX Byte 1 ==
5696 12:11:42.209876 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5697 12:11:42.213185 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5698 12:11:42.216389 ==
5699 12:11:42.219612 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 12:11:42.222768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 12:11:42.222877 ==
5702 12:11:42.222972
5703 12:11:42.223065
5704 12:11:42.226138 TX Vref Scan disable
5705 12:11:42.226237 == TX Byte 0 ==
5706 12:11:42.232656 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5707 12:11:42.235810 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5708 12:11:42.235923 == TX Byte 1 ==
5709 12:11:42.242366 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5710 12:11:42.246208 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5711 12:11:42.246318
5712 12:11:42.246417 [DATLAT]
5713 12:11:42.249530 Freq=933, CH1 RK0
5714 12:11:42.249629
5715 12:11:42.249720 DATLAT Default: 0xd
5716 12:11:42.252582 0, 0xFFFF, sum = 0
5717 12:11:42.252660 1, 0xFFFF, sum = 0
5718 12:11:42.255580 2, 0xFFFF, sum = 0
5719 12:11:42.255652 3, 0xFFFF, sum = 0
5720 12:11:42.258968 4, 0xFFFF, sum = 0
5721 12:11:42.262224 5, 0xFFFF, sum = 0
5722 12:11:42.262341 6, 0xFFFF, sum = 0
5723 12:11:42.265494 7, 0xFFFF, sum = 0
5724 12:11:42.265579 8, 0xFFFF, sum = 0
5725 12:11:42.269342 9, 0xFFFF, sum = 0
5726 12:11:42.269435 10, 0x0, sum = 1
5727 12:11:42.272624 11, 0x0, sum = 2
5728 12:11:42.272708 12, 0x0, sum = 3
5729 12:11:42.272776 13, 0x0, sum = 4
5730 12:11:42.275964 best_step = 11
5731 12:11:42.276085
5732 12:11:42.276207 ==
5733 12:11:42.278664 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 12:11:42.282601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 12:11:42.282685 ==
5736 12:11:42.285878 RX Vref Scan: 1
5737 12:11:42.285971
5738 12:11:42.289083 RX Vref 0 -> 0, step: 1
5739 12:11:42.289167
5740 12:11:42.289234 RX Delay -61 -> 252, step: 4
5741 12:11:42.289296
5742 12:11:42.292225 Set Vref, RX VrefLevel [Byte0]: 52
5743 12:11:42.295110 [Byte1]: 49
5744 12:11:42.299981
5745 12:11:42.300108 Final RX Vref Byte 0 = 52 to rank0
5746 12:11:42.303127 Final RX Vref Byte 1 = 49 to rank0
5747 12:11:42.306612 Final RX Vref Byte 0 = 52 to rank1
5748 12:11:42.309597 Final RX Vref Byte 1 = 49 to rank1==
5749 12:11:42.313429 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 12:11:42.319847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 12:11:42.319934 ==
5752 12:11:42.320003 DQS Delay:
5753 12:11:42.323018 DQS0 = 0, DQS1 = 0
5754 12:11:42.323103 DQM Delay:
5755 12:11:42.323199 DQM0 = 98, DQM1 = 94
5756 12:11:42.326242 DQ Delay:
5757 12:11:42.329479 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5758 12:11:42.332655 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5759 12:11:42.335819 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5760 12:11:42.339119 DQ12 =104, DQ13 =104, DQ14 =100, DQ15 =102
5761 12:11:42.339214
5762 12:11:42.339281
5763 12:11:42.346224 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5764 12:11:42.349543 CH1 RK0: MR19=505, MR18=919
5765 12:11:42.356009 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5766 12:11:42.356127
5767 12:11:42.358753 ----->DramcWriteLeveling(PI) begin...
5768 12:11:42.358841 ==
5769 12:11:42.362593 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 12:11:42.365723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 12:11:42.368950 ==
5772 12:11:42.369030 Write leveling (Byte 0): 26 => 26
5773 12:11:42.372221 Write leveling (Byte 1): 28 => 28
5774 12:11:42.375588 DramcWriteLeveling(PI) end<-----
5775 12:11:42.375661
5776 12:11:42.375732 ==
5777 12:11:42.378943 Dram Type= 6, Freq= 0, CH_1, rank 1
5778 12:11:42.385291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 12:11:42.385370 ==
5780 12:11:42.388599 [Gating] SW mode calibration
5781 12:11:42.395131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5782 12:11:42.398302 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5783 12:11:42.405390 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5784 12:11:42.408432 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 12:11:42.411453 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 12:11:42.418150 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 12:11:42.421340 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 12:11:42.425041 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 12:11:42.431562 0 14 24 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5790 12:11:42.434740 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5791 12:11:42.437900 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5792 12:11:42.444449 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 12:11:42.447796 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 12:11:42.451014 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 12:11:42.457389 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 12:11:42.460722 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 12:11:42.463910 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5798 12:11:42.471051 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
5799 12:11:42.474261 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5800 12:11:42.477567 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 12:11:42.484087 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 12:11:42.487301 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:11:42.490591 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 12:11:42.497064 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 12:11:42.500218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 12:11:42.503315 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5807 12:11:42.510111 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:11:42.513784 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:11:42.516990 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:11:42.523122 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:11:42.526794 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:11:42.529761 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:11:42.536558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:11:42.539610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:11:42.542932 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:11:42.549907 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:11:42.553191 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:11:42.556506 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:11:42.562905 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:11:42.566217 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:11:42.569301 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5822 12:11:42.575782 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5823 12:11:42.579671 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 12:11:42.582944 Total UI for P1: 0, mck2ui 16
5825 12:11:42.586197 best dqsien dly found for B0: ( 1, 2, 26)
5826 12:11:42.589401 Total UI for P1: 0, mck2ui 16
5827 12:11:42.592672 best dqsien dly found for B1: ( 1, 2, 28)
5828 12:11:42.595833 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5829 12:11:42.599238 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5830 12:11:42.599364
5831 12:11:42.602380 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5832 12:11:42.605550 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5833 12:11:42.608696 [Gating] SW calibration Done
5834 12:11:42.608797 ==
5835 12:11:42.612240 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 12:11:42.619037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 12:11:42.619123 ==
5838 12:11:42.619190 RX Vref Scan: 0
5839 12:11:42.619270
5840 12:11:42.622389 RX Vref 0 -> 0, step: 1
5841 12:11:42.622472
5842 12:11:42.625584 RX Delay -80 -> 252, step: 8
5843 12:11:42.628509 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5844 12:11:42.632005 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5845 12:11:42.635246 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5846 12:11:42.641932 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5847 12:11:42.645184 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5848 12:11:42.648326 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5849 12:11:42.651533 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5850 12:11:42.654904 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5851 12:11:42.658055 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5852 12:11:42.664548 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5853 12:11:42.667844 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5854 12:11:42.671586 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5855 12:11:42.674317 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5856 12:11:42.677560 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5857 12:11:42.684211 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5858 12:11:42.688072 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5859 12:11:42.688194 ==
5860 12:11:42.691295 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 12:11:42.694518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 12:11:42.694634 ==
5863 12:11:42.694759 DQS Delay:
5864 12:11:42.697636 DQS0 = 0, DQS1 = 0
5865 12:11:42.697758 DQM Delay:
5866 12:11:42.700927 DQM0 = 97, DQM1 = 93
5867 12:11:42.701042 DQ Delay:
5868 12:11:42.704096 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5869 12:11:42.707357 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5870 12:11:42.710535 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5871 12:11:42.714223 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5872 12:11:42.714355
5873 12:11:42.714459
5874 12:11:42.714559 ==
5875 12:11:42.717250 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 12:11:42.723576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 12:11:42.723690 ==
5878 12:11:42.723793
5879 12:11:42.723890
5880 12:11:42.723982 TX Vref Scan disable
5881 12:11:42.727399 == TX Byte 0 ==
5882 12:11:42.730653 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5883 12:11:42.737468 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5884 12:11:42.737594 == TX Byte 1 ==
5885 12:11:42.740567 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5886 12:11:42.747577 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5887 12:11:42.747693 ==
5888 12:11:42.750409 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 12:11:42.753652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 12:11:42.753756 ==
5891 12:11:42.753855
5892 12:11:42.753947
5893 12:11:42.756954 TX Vref Scan disable
5894 12:11:42.760651 == TX Byte 0 ==
5895 12:11:42.763949 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5896 12:11:42.767136 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5897 12:11:42.770281 == TX Byte 1 ==
5898 12:11:42.773393 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5899 12:11:42.776466 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5900 12:11:42.776541
5901 12:11:42.776612 [DATLAT]
5902 12:11:42.780340 Freq=933, CH1 RK1
5903 12:11:42.780414
5904 12:11:42.783528 DATLAT Default: 0xb
5905 12:11:42.783619 0, 0xFFFF, sum = 0
5906 12:11:42.786805 1, 0xFFFF, sum = 0
5907 12:11:42.786910 2, 0xFFFF, sum = 0
5908 12:11:42.790104 3, 0xFFFF, sum = 0
5909 12:11:42.790220 4, 0xFFFF, sum = 0
5910 12:11:42.793341 5, 0xFFFF, sum = 0
5911 12:11:42.793454 6, 0xFFFF, sum = 0
5912 12:11:42.796633 7, 0xFFFF, sum = 0
5913 12:11:42.796747 8, 0xFFFF, sum = 0
5914 12:11:42.799811 9, 0xFFFF, sum = 0
5915 12:11:42.799933 10, 0x0, sum = 1
5916 12:11:42.803032 11, 0x0, sum = 2
5917 12:11:42.803152 12, 0x0, sum = 3
5918 12:11:42.806281 13, 0x0, sum = 4
5919 12:11:42.806395 best_step = 11
5920 12:11:42.806495
5921 12:11:42.806605 ==
5922 12:11:42.809550 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 12:11:42.812808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 12:11:42.816037 ==
5925 12:11:42.816155 RX Vref Scan: 0
5926 12:11:42.816260
5927 12:11:42.819777 RX Vref 0 -> 0, step: 1
5928 12:11:42.819904
5929 12:11:42.822746 RX Delay -53 -> 252, step: 4
5930 12:11:42.825809 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5931 12:11:42.829501 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5932 12:11:42.835835 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5933 12:11:42.838883 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5934 12:11:42.842551 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5935 12:11:42.845738 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5936 12:11:42.848848 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5937 12:11:42.855783 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5938 12:11:42.859024 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5939 12:11:42.862351 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5940 12:11:42.865573 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5941 12:11:42.868908 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5942 12:11:42.875334 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5943 12:11:42.878613 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5944 12:11:42.881757 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5945 12:11:42.885018 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5946 12:11:42.885135 ==
5947 12:11:42.888326 Dram Type= 6, Freq= 0, CH_1, rank 1
5948 12:11:42.895579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5949 12:11:42.895692 ==
5950 12:11:42.895800 DQS Delay:
5951 12:11:42.895909 DQS0 = 0, DQS1 = 0
5952 12:11:42.898837 DQM Delay:
5953 12:11:42.898953 DQM0 = 97, DQM1 = 92
5954 12:11:42.902029 DQ Delay:
5955 12:11:42.905245 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5956 12:11:42.908412 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =94
5957 12:11:42.911645 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =86
5958 12:11:42.914841 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5959 12:11:42.914962
5960 12:11:42.915077
5961 12:11:42.922035 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5962 12:11:42.925024 CH1 RK1: MR19=505, MR18=B22
5963 12:11:42.931800 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5964 12:11:42.934998 [RxdqsGatingPostProcess] freq 933
5965 12:11:42.938161 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5966 12:11:42.941148 best DQS0 dly(2T, 0.5T) = (0, 10)
5967 12:11:42.944866 best DQS1 dly(2T, 0.5T) = (0, 10)
5968 12:11:42.947857 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5969 12:11:42.950970 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5970 12:11:42.954132 best DQS0 dly(2T, 0.5T) = (0, 10)
5971 12:11:42.958015 best DQS1 dly(2T, 0.5T) = (0, 10)
5972 12:11:42.961077 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5973 12:11:42.964671 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5974 12:11:42.967761 Pre-setting of DQS Precalculation
5975 12:11:42.974205 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5976 12:11:42.980519 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5977 12:11:42.987045 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5978 12:11:42.987152
5979 12:11:42.987248
5980 12:11:42.990349 [Calibration Summary] 1866 Mbps
5981 12:11:42.990462 CH 0, Rank 0
5982 12:11:42.994244 SW Impedance : PASS
5983 12:11:42.997472 DUTY Scan : NO K
5984 12:11:42.997583 ZQ Calibration : PASS
5985 12:11:43.000242 Jitter Meter : NO K
5986 12:11:43.003596 CBT Training : PASS
5987 12:11:43.003702 Write leveling : PASS
5988 12:11:43.006903 RX DQS gating : PASS
5989 12:11:43.010102 RX DQ/DQS(RDDQC) : PASS
5990 12:11:43.010206 TX DQ/DQS : PASS
5991 12:11:43.013894 RX DATLAT : PASS
5992 12:11:43.013997 RX DQ/DQS(Engine): PASS
5993 12:11:43.016928 TX OE : NO K
5994 12:11:43.017036 All Pass.
5995 12:11:43.017130
5996 12:11:43.020148 CH 0, Rank 1
5997 12:11:43.020221 SW Impedance : PASS
5998 12:11:43.023566 DUTY Scan : NO K
5999 12:11:43.026594 ZQ Calibration : PASS
6000 12:11:43.026694 Jitter Meter : NO K
6001 12:11:43.030269 CBT Training : PASS
6002 12:11:43.033312 Write leveling : PASS
6003 12:11:43.033426 RX DQS gating : PASS
6004 12:11:43.036447 RX DQ/DQS(RDDQC) : PASS
6005 12:11:43.039835 TX DQ/DQS : PASS
6006 12:11:43.039936 RX DATLAT : PASS
6007 12:11:43.042979 RX DQ/DQS(Engine): PASS
6008 12:11:43.046134 TX OE : NO K
6009 12:11:43.046237 All Pass.
6010 12:11:43.046330
6011 12:11:43.046420 CH 1, Rank 0
6012 12:11:43.049949 SW Impedance : PASS
6013 12:11:43.052854 DUTY Scan : NO K
6014 12:11:43.052941 ZQ Calibration : PASS
6015 12:11:43.056608 Jitter Meter : NO K
6016 12:11:43.059740 CBT Training : PASS
6017 12:11:43.059826 Write leveling : PASS
6018 12:11:43.062954 RX DQS gating : PASS
6019 12:11:43.066067 RX DQ/DQS(RDDQC) : PASS
6020 12:11:43.066154 TX DQ/DQS : PASS
6021 12:11:43.069306 RX DATLAT : PASS
6022 12:11:43.072620 RX DQ/DQS(Engine): PASS
6023 12:11:43.072706 TX OE : NO K
6024 12:11:43.075828 All Pass.
6025 12:11:43.075943
6026 12:11:43.076050 CH 1, Rank 1
6027 12:11:43.078981 SW Impedance : PASS
6028 12:11:43.079085 DUTY Scan : NO K
6029 12:11:43.082813 ZQ Calibration : PASS
6030 12:11:43.086000 Jitter Meter : NO K
6031 12:11:43.086108 CBT Training : PASS
6032 12:11:43.089294 Write leveling : PASS
6033 12:11:43.092620 RX DQS gating : PASS
6034 12:11:43.092732 RX DQ/DQS(RDDQC) : PASS
6035 12:11:43.095872 TX DQ/DQS : PASS
6036 12:11:43.099186 RX DATLAT : PASS
6037 12:11:43.099300 RX DQ/DQS(Engine): PASS
6038 12:11:43.102402 TX OE : NO K
6039 12:11:43.102509 All Pass.
6040 12:11:43.102607
6041 12:11:43.105114 DramC Write-DBI off
6042 12:11:43.108898 PER_BANK_REFRESH: Hybrid Mode
6043 12:11:43.109008 TX_TRACKING: ON
6044 12:11:43.118552 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6045 12:11:43.121545 [FAST_K] Save calibration result to emmc
6046 12:11:43.125337 dramc_set_vcore_voltage set vcore to 650000
6047 12:11:43.128532 Read voltage for 400, 6
6048 12:11:43.128622 Vio18 = 0
6049 12:11:43.128720 Vcore = 650000
6050 12:11:43.131733 Vdram = 0
6051 12:11:43.131853 Vddq = 0
6052 12:11:43.131962 Vmddr = 0
6053 12:11:43.137992 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6054 12:11:43.141804 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6055 12:11:43.144986 MEM_TYPE=3, freq_sel=20
6056 12:11:43.147916 sv_algorithm_assistance_LP4_800
6057 12:11:43.151175 ============ PULL DRAM RESETB DOWN ============
6058 12:11:43.154811 ========== PULL DRAM RESETB DOWN end =========
6059 12:11:43.161613 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6060 12:11:43.164608 ===================================
6061 12:11:43.167723 LPDDR4 DRAM CONFIGURATION
6062 12:11:43.171527 ===================================
6063 12:11:43.171615 EX_ROW_EN[0] = 0x0
6064 12:11:43.174806 EX_ROW_EN[1] = 0x0
6065 12:11:43.174923 LP4Y_EN = 0x0
6066 12:11:43.178105 WORK_FSP = 0x0
6067 12:11:43.178217 WL = 0x2
6068 12:11:43.181366 RL = 0x2
6069 12:11:43.181475 BL = 0x2
6070 12:11:43.184517 RPST = 0x0
6071 12:11:43.184625 RD_PRE = 0x0
6072 12:11:43.187741 WR_PRE = 0x1
6073 12:11:43.191011 WR_PST = 0x0
6074 12:11:43.191129 DBI_WR = 0x0
6075 12:11:43.194256 DBI_RD = 0x0
6076 12:11:43.194344 OTF = 0x1
6077 12:11:43.197498 ===================================
6078 12:11:43.200805 ===================================
6079 12:11:43.200903 ANA top config
6080 12:11:43.207340 ===================================
6081 12:11:43.207423 DLL_ASYNC_EN = 0
6082 12:11:43.210635 ALL_SLAVE_EN = 1
6083 12:11:43.213943 NEW_RANK_MODE = 1
6084 12:11:43.217168 DLL_IDLE_MODE = 1
6085 12:11:43.217247 LP45_APHY_COMB_EN = 1
6086 12:11:43.220509 TX_ODT_DIS = 1
6087 12:11:43.223836 NEW_8X_MODE = 1
6088 12:11:43.226904 ===================================
6089 12:11:43.230556 ===================================
6090 12:11:43.233883 data_rate = 800
6091 12:11:43.237095 CKR = 1
6092 12:11:43.239958 DQ_P2S_RATIO = 4
6093 12:11:43.243655 ===================================
6094 12:11:43.243740 CA_P2S_RATIO = 4
6095 12:11:43.246883 DQ_CA_OPEN = 0
6096 12:11:43.250055 DQ_SEMI_OPEN = 1
6097 12:11:43.253875 CA_SEMI_OPEN = 1
6098 12:11:43.256834 CA_FULL_RATE = 0
6099 12:11:43.259814 DQ_CKDIV4_EN = 0
6100 12:11:43.259897 CA_CKDIV4_EN = 1
6101 12:11:43.263401 CA_PREDIV_EN = 0
6102 12:11:43.266361 PH8_DLY = 0
6103 12:11:43.270042 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6104 12:11:43.273183 DQ_AAMCK_DIV = 0
6105 12:11:43.276206 CA_AAMCK_DIV = 0
6106 12:11:43.276289 CA_ADMCK_DIV = 4
6107 12:11:43.279558 DQ_TRACK_CA_EN = 0
6108 12:11:43.282705 CA_PICK = 800
6109 12:11:43.286432 CA_MCKIO = 400
6110 12:11:43.289774 MCKIO_SEMI = 400
6111 12:11:43.293072 PLL_FREQ = 3016
6112 12:11:43.296298 DQ_UI_PI_RATIO = 32
6113 12:11:43.299584 CA_UI_PI_RATIO = 32
6114 12:11:43.302819 ===================================
6115 12:11:43.306255 ===================================
6116 12:11:43.306341 memory_type:LPDDR4
6117 12:11:43.309555 GP_NUM : 10
6118 12:11:43.312133 SRAM_EN : 1
6119 12:11:43.312216 MD32_EN : 0
6120 12:11:43.316160 ===================================
6121 12:11:43.319389 [ANA_INIT] >>>>>>>>>>>>>>
6122 12:11:43.322613 <<<<<< [CONFIGURE PHASE]: ANA_TX
6123 12:11:43.325930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6124 12:11:43.329220 ===================================
6125 12:11:43.332481 data_rate = 800,PCW = 0X7400
6126 12:11:43.335641 ===================================
6127 12:11:43.338798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6128 12:11:43.341923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6129 12:11:43.355280 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 12:11:43.358423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6131 12:11:43.361509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6132 12:11:43.365186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6133 12:11:43.368331 [ANA_INIT] flow start
6134 12:11:43.371915 [ANA_INIT] PLL >>>>>>>>
6135 12:11:43.372078 [ANA_INIT] PLL <<<<<<<<
6136 12:11:43.374970 [ANA_INIT] MIDPI >>>>>>>>
6137 12:11:43.378096 [ANA_INIT] MIDPI <<<<<<<<
6138 12:11:43.381246 [ANA_INIT] DLL >>>>>>>>
6139 12:11:43.381356 [ANA_INIT] flow end
6140 12:11:43.385081 ============ LP4 DIFF to SE enter ============
6141 12:11:43.391275 ============ LP4 DIFF to SE exit ============
6142 12:11:43.391397 [ANA_INIT] <<<<<<<<<<<<<
6143 12:11:43.394678 [Flow] Enable top DCM control >>>>>
6144 12:11:43.397792 [Flow] Enable top DCM control <<<<<
6145 12:11:43.401141 Enable DLL master slave shuffle
6146 12:11:43.407631 ==============================================================
6147 12:11:43.407715 Gating Mode config
6148 12:11:43.414085 ==============================================================
6149 12:11:43.417432 Config description:
6150 12:11:43.427776 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6151 12:11:43.434174 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6152 12:11:43.437525 SELPH_MODE 0: By rank 1: By Phase
6153 12:11:43.443736 ==============================================================
6154 12:11:43.447280 GAT_TRACK_EN = 0
6155 12:11:43.450391 RX_GATING_MODE = 2
6156 12:11:43.454099 RX_GATING_TRACK_MODE = 2
6157 12:11:43.454196 SELPH_MODE = 1
6158 12:11:43.456789 PICG_EARLY_EN = 1
6159 12:11:43.460415 VALID_LAT_VALUE = 1
6160 12:11:43.467174 ==============================================================
6161 12:11:43.470297 Enter into Gating configuration >>>>
6162 12:11:43.473430 Exit from Gating configuration <<<<
6163 12:11:43.476652 Enter into DVFS_PRE_config >>>>>
6164 12:11:43.486719 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6165 12:11:43.489736 Exit from DVFS_PRE_config <<<<<
6166 12:11:43.493032 Enter into PICG configuration >>>>
6167 12:11:43.496304 Exit from PICG configuration <<<<
6168 12:11:43.500166 [RX_INPUT] configuration >>>>>
6169 12:11:43.503501 [RX_INPUT] configuration <<<<<
6170 12:11:43.506772 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6171 12:11:43.513366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6172 12:11:43.519873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 12:11:43.525854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 12:11:43.532832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 12:11:43.539352 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 12:11:43.542583 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6177 12:11:43.545801 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6178 12:11:43.549652 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6179 12:11:43.556136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6180 12:11:43.559065 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6181 12:11:43.562290 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 12:11:43.565461 ===================================
6183 12:11:43.569061 LPDDR4 DRAM CONFIGURATION
6184 12:11:43.571985 ===================================
6185 12:11:43.572108 EX_ROW_EN[0] = 0x0
6186 12:11:43.575828 EX_ROW_EN[1] = 0x0
6187 12:11:43.579171 LP4Y_EN = 0x0
6188 12:11:43.579258 WORK_FSP = 0x0
6189 12:11:43.582107 WL = 0x2
6190 12:11:43.582194 RL = 0x2
6191 12:11:43.585263 BL = 0x2
6192 12:11:43.585352 RPST = 0x0
6193 12:11:43.589090 RD_PRE = 0x0
6194 12:11:43.589193 WR_PRE = 0x1
6195 12:11:43.592241 WR_PST = 0x0
6196 12:11:43.592361 DBI_WR = 0x0
6197 12:11:43.595632 DBI_RD = 0x0
6198 12:11:43.595719 OTF = 0x1
6199 12:11:43.598914 ===================================
6200 12:11:43.605014 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6201 12:11:43.608285 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6202 12:11:43.611643 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 12:11:43.614994 ===================================
6204 12:11:43.618308 LPDDR4 DRAM CONFIGURATION
6205 12:11:43.621600 ===================================
6206 12:11:43.624898 EX_ROW_EN[0] = 0x10
6207 12:11:43.624978 EX_ROW_EN[1] = 0x0
6208 12:11:43.628638 LP4Y_EN = 0x0
6209 12:11:43.628715 WORK_FSP = 0x0
6210 12:11:43.631811 WL = 0x2
6211 12:11:43.631896 RL = 0x2
6212 12:11:43.635040 BL = 0x2
6213 12:11:43.635121 RPST = 0x0
6214 12:11:43.638269 RD_PRE = 0x0
6215 12:11:43.638347 WR_PRE = 0x1
6216 12:11:43.641483 WR_PST = 0x0
6217 12:11:43.641643 DBI_WR = 0x0
6218 12:11:43.644583 DBI_RD = 0x0
6219 12:11:43.644690 OTF = 0x1
6220 12:11:43.647759 ===================================
6221 12:11:43.654296 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6222 12:11:43.659497 nWR fixed to 30
6223 12:11:43.662525 [ModeRegInit_LP4] CH0 RK0
6224 12:11:43.662609 [ModeRegInit_LP4] CH0 RK1
6225 12:11:43.665952 [ModeRegInit_LP4] CH1 RK0
6226 12:11:43.669015 [ModeRegInit_LP4] CH1 RK1
6227 12:11:43.669098 match AC timing 19
6228 12:11:43.676297 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6229 12:11:43.679218 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6230 12:11:43.682273 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6231 12:11:43.689065 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6232 12:11:43.692097 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6233 12:11:43.692182 ==
6234 12:11:43.695770 Dram Type= 6, Freq= 0, CH_0, rank 0
6235 12:11:43.698858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 12:11:43.698942 ==
6237 12:11:43.705712 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 12:11:43.712136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6239 12:11:43.715330 [CA 0] Center 36 (8~64) winsize 57
6240 12:11:43.718525 [CA 1] Center 36 (8~64) winsize 57
6241 12:11:43.721750 [CA 2] Center 36 (8~64) winsize 57
6242 12:11:43.725092 [CA 3] Center 36 (8~64) winsize 57
6243 12:11:43.728357 [CA 4] Center 36 (8~64) winsize 57
6244 12:11:43.731602 [CA 5] Center 36 (8~64) winsize 57
6245 12:11:43.731787
6246 12:11:43.735419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6247 12:11:43.735528
6248 12:11:43.738676 [CATrainingPosCal] consider 1 rank data
6249 12:11:43.741828 u2DelayCellTimex100 = 270/100 ps
6250 12:11:43.744872 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 12:11:43.748222 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:11:43.751470 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:11:43.754587 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:11:43.757932 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 12:11:43.761126 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:11:43.761230
6257 12:11:43.768346 CA PerBit enable=1, Macro0, CA PI delay=36
6258 12:11:43.768451
6259 12:11:43.768548 [CBTSetCACLKResult] CA Dly = 36
6260 12:11:43.771203 CS Dly: 1 (0~32)
6261 12:11:43.771304 ==
6262 12:11:43.774729 Dram Type= 6, Freq= 0, CH_0, rank 1
6263 12:11:43.777771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 12:11:43.777878 ==
6265 12:11:43.784614 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6266 12:11:43.791255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6267 12:11:43.794330 [CA 0] Center 36 (8~64) winsize 57
6268 12:11:43.797383 [CA 1] Center 36 (8~64) winsize 57
6269 12:11:43.800984 [CA 2] Center 36 (8~64) winsize 57
6270 12:11:43.803949 [CA 3] Center 36 (8~64) winsize 57
6271 12:11:43.807506 [CA 4] Center 36 (8~64) winsize 57
6272 12:11:43.807587 [CA 5] Center 36 (8~64) winsize 57
6273 12:11:43.810709
6274 12:11:43.814087 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6275 12:11:43.814162
6276 12:11:43.817373 [CATrainingPosCal] consider 2 rank data
6277 12:11:43.820613 u2DelayCellTimex100 = 270/100 ps
6278 12:11:43.823994 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 12:11:43.827200 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:11:43.830503 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:11:43.833880 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:11:43.836930 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:11:43.840287 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:11:43.840384
6285 12:11:43.843440 CA PerBit enable=1, Macro0, CA PI delay=36
6286 12:11:43.847439
6287 12:11:43.847525 [CBTSetCACLKResult] CA Dly = 36
6288 12:11:43.850601 CS Dly: 1 (0~32)
6289 12:11:43.850687
6290 12:11:43.853771 ----->DramcWriteLeveling(PI) begin...
6291 12:11:43.853858 ==
6292 12:11:43.857090 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 12:11:43.860227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 12:11:43.860313 ==
6295 12:11:43.863425 Write leveling (Byte 0): 40 => 8
6296 12:11:43.866686 Write leveling (Byte 1): 40 => 8
6297 12:11:43.869958 DramcWriteLeveling(PI) end<-----
6298 12:11:43.870044
6299 12:11:43.870146 ==
6300 12:11:43.873692 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 12:11:43.876818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 12:11:43.876904 ==
6303 12:11:43.879885 [Gating] SW mode calibration
6304 12:11:43.886582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6305 12:11:43.893341 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6306 12:11:43.896427 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6307 12:11:43.903174 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 12:11:43.906245 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 12:11:43.909857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 12:11:43.916274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 12:11:43.919580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 12:11:43.922899 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 12:11:43.929370 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 12:11:43.932542 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6315 12:11:43.935806 Total UI for P1: 0, mck2ui 16
6316 12:11:43.939060 best dqsien dly found for B0: ( 0, 14, 24)
6317 12:11:43.942382 Total UI for P1: 0, mck2ui 16
6318 12:11:43.945567 best dqsien dly found for B1: ( 0, 14, 24)
6319 12:11:43.948993 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6320 12:11:43.952180 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6321 12:11:43.952271
6322 12:11:43.955347 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6323 12:11:43.962465 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 12:11:43.962566 [Gating] SW calibration Done
6325 12:11:43.962647 ==
6326 12:11:43.965770 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 12:11:43.972234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 12:11:43.972317 ==
6329 12:11:43.972383 RX Vref Scan: 0
6330 12:11:43.972459
6331 12:11:43.975686 RX Vref 0 -> 0, step: 1
6332 12:11:43.975783
6333 12:11:43.978656 RX Delay -410 -> 252, step: 16
6334 12:11:43.982207 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6335 12:11:43.985351 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6336 12:11:43.991975 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6337 12:11:43.995043 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6338 12:11:43.998108 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6339 12:11:44.001788 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6340 12:11:44.007998 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6341 12:11:44.011766 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6342 12:11:44.014923 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6343 12:11:44.018105 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6344 12:11:44.024436 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6345 12:11:44.027773 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6346 12:11:44.031033 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6347 12:11:44.037629 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6348 12:11:44.040840 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6349 12:11:44.044051 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6350 12:11:44.044185 ==
6351 12:11:44.047368 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 12:11:44.054424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 12:11:44.054533 ==
6354 12:11:44.054637 DQS Delay:
6355 12:11:44.057563 DQS0 = 35, DQS1 = 59
6356 12:11:44.057669 DQM Delay:
6357 12:11:44.057762 DQM0 = 5, DQM1 = 16
6358 12:11:44.060886 DQ Delay:
6359 12:11:44.061012 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6360 12:11:44.064122 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6361 12:11:44.067361 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6362 12:11:44.070639 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6363 12:11:44.070762
6364 12:11:44.070868
6365 12:11:44.073737 ==
6366 12:11:44.077093 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 12:11:44.080699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 12:11:44.080810 ==
6369 12:11:44.080908
6370 12:11:44.081000
6371 12:11:44.083803 TX Vref Scan disable
6372 12:11:44.083918 == TX Byte 0 ==
6373 12:11:44.087080 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 12:11:44.093995 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 12:11:44.094165 == TX Byte 1 ==
6376 12:11:44.096887 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 12:11:44.103722 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 12:11:44.103838 ==
6379 12:11:44.106732 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 12:11:44.110299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 12:11:44.110418 ==
6382 12:11:44.110516
6383 12:11:44.110621
6384 12:11:44.113523 TX Vref Scan disable
6385 12:11:44.113636 == TX Byte 0 ==
6386 12:11:44.117184 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 12:11:44.123311 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 12:11:44.123427 == TX Byte 1 ==
6389 12:11:44.126429 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 12:11:44.133028 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 12:11:44.133151
6392 12:11:44.133248 [DATLAT]
6393 12:11:44.136297 Freq=400, CH0 RK0
6394 12:11:44.136411
6395 12:11:44.136518 DATLAT Default: 0xf
6396 12:11:44.139592 0, 0xFFFF, sum = 0
6397 12:11:44.139698 1, 0xFFFF, sum = 0
6398 12:11:44.143008 2, 0xFFFF, sum = 0
6399 12:11:44.143107 3, 0xFFFF, sum = 0
6400 12:11:44.146260 4, 0xFFFF, sum = 0
6401 12:11:44.146376 5, 0xFFFF, sum = 0
6402 12:11:44.150042 6, 0xFFFF, sum = 0
6403 12:11:44.150155 7, 0xFFFF, sum = 0
6404 12:11:44.153284 8, 0xFFFF, sum = 0
6405 12:11:44.153389 9, 0xFFFF, sum = 0
6406 12:11:44.156561 10, 0xFFFF, sum = 0
6407 12:11:44.156668 11, 0xFFFF, sum = 0
6408 12:11:44.159691 12, 0xFFFF, sum = 0
6409 12:11:44.159796 13, 0x0, sum = 1
6410 12:11:44.163032 14, 0x0, sum = 2
6411 12:11:44.163140 15, 0x0, sum = 3
6412 12:11:44.166306 16, 0x0, sum = 4
6413 12:11:44.166408 best_step = 14
6414 12:11:44.166502
6415 12:11:44.166595 ==
6416 12:11:44.169690 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 12:11:44.176146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:11:44.176252 ==
6419 12:11:44.176348 RX Vref Scan: 1
6420 12:11:44.176441
6421 12:11:44.179390 RX Vref 0 -> 0, step: 1
6422 12:11:44.179489
6423 12:11:44.182616 RX Delay -359 -> 252, step: 8
6424 12:11:44.182719
6425 12:11:44.185679 Set Vref, RX VrefLevel [Byte0]: 57
6426 12:11:44.189379 [Byte1]: 49
6427 12:11:44.192587
6428 12:11:44.192700 Final RX Vref Byte 0 = 57 to rank0
6429 12:11:44.196360 Final RX Vref Byte 1 = 49 to rank0
6430 12:11:44.199374 Final RX Vref Byte 0 = 57 to rank1
6431 12:11:44.202500 Final RX Vref Byte 1 = 49 to rank1==
6432 12:11:44.205604 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 12:11:44.212352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 12:11:44.212461 ==
6435 12:11:44.212564 DQS Delay:
6436 12:11:44.216186 DQS0 = 44, DQS1 = 60
6437 12:11:44.216290 DQM Delay:
6438 12:11:44.216386 DQM0 = 10, DQM1 = 16
6439 12:11:44.219265 DQ Delay:
6440 12:11:44.222258 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6441 12:11:44.225537 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6442 12:11:44.228611 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6443 12:11:44.231949 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6444 12:11:44.232066
6445 12:11:44.232160
6446 12:11:44.239113 [DQSOSCAuto] RK0, (LSB)MR18= 0x9487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6447 12:11:44.241806 CH0 RK0: MR19=C0C, MR18=9487
6448 12:11:44.248692 CH0_RK0: MR19=0xC0C, MR18=0x9487, DQSOSC=391, MR23=63, INC=386, DEC=257
6449 12:11:44.248800 ==
6450 12:11:44.251963 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 12:11:44.255110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 12:11:44.255220 ==
6453 12:11:44.258417 [Gating] SW mode calibration
6454 12:11:44.264946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6455 12:11:44.272046 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6456 12:11:44.275219 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6457 12:11:44.278475 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 12:11:44.284772 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 12:11:44.288066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 12:11:44.291130 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 12:11:44.297883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 12:11:44.301100 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 12:11:44.304722 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 12:11:44.311555 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 12:11:44.314794 Total UI for P1: 0, mck2ui 16
6466 12:11:44.317869 best dqsien dly found for B0: ( 0, 14, 24)
6467 12:11:44.321065 Total UI for P1: 0, mck2ui 16
6468 12:11:44.324638 best dqsien dly found for B1: ( 0, 14, 24)
6469 12:11:44.327662 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6470 12:11:44.330847 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6471 12:11:44.330932
6472 12:11:44.334127 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6473 12:11:44.337585 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 12:11:44.340848 [Gating] SW calibration Done
6475 12:11:44.340944 ==
6476 12:11:44.344019 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 12:11:44.347248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 12:11:44.347335 ==
6479 12:11:44.351201 RX Vref Scan: 0
6480 12:11:44.351287
6481 12:11:44.354209 RX Vref 0 -> 0, step: 1
6482 12:11:44.354294
6483 12:11:44.357589 RX Delay -410 -> 252, step: 16
6484 12:11:44.360958 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6485 12:11:44.364205 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6486 12:11:44.367597 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6487 12:11:44.374117 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6488 12:11:44.377369 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6489 12:11:44.380684 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6490 12:11:44.383894 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6491 12:11:44.390220 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6492 12:11:44.393613 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6493 12:11:44.396871 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6494 12:11:44.400449 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6495 12:11:44.407012 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6496 12:11:44.410132 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6497 12:11:44.413196 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6498 12:11:44.419797 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6499 12:11:44.422952 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6500 12:11:44.423072 ==
6501 12:11:44.426741 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 12:11:44.429860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 12:11:44.429974 ==
6504 12:11:44.432927 DQS Delay:
6505 12:11:44.433043 DQS0 = 35, DQS1 = 59
6506 12:11:44.436232 DQM Delay:
6507 12:11:44.436340 DQM0 = 6, DQM1 = 18
6508 12:11:44.436440 DQ Delay:
6509 12:11:44.439566 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6510 12:11:44.442835 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6511 12:11:44.445992 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6512 12:11:44.449955 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6513 12:11:44.450064
6514 12:11:44.450159
6515 12:11:44.450254 ==
6516 12:11:44.453144 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 12:11:44.456332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 12:11:44.459539 ==
6519 12:11:44.459639
6520 12:11:44.459735
6521 12:11:44.459824 TX Vref Scan disable
6522 12:11:44.462882 == TX Byte 0 ==
6523 12:11:44.466031 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6524 12:11:44.469341 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6525 12:11:44.472585 == TX Byte 1 ==
6526 12:11:44.475890 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6527 12:11:44.479256 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6528 12:11:44.479364 ==
6529 12:11:44.482475 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 12:11:44.489336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 12:11:44.489420 ==
6532 12:11:44.489489
6533 12:11:44.489571
6534 12:11:44.489634 TX Vref Scan disable
6535 12:11:44.492609 == TX Byte 0 ==
6536 12:11:44.495826 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6537 12:11:44.498996 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6538 12:11:44.502293 == TX Byte 1 ==
6539 12:11:44.505416 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6540 12:11:44.509202 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6541 12:11:44.509300
6542 12:11:44.512273 [DATLAT]
6543 12:11:44.512372 Freq=400, CH0 RK1
6544 12:11:44.512441
6545 12:11:44.515379 DATLAT Default: 0xe
6546 12:11:44.515469 0, 0xFFFF, sum = 0
6547 12:11:44.518526 1, 0xFFFF, sum = 0
6548 12:11:44.518606 2, 0xFFFF, sum = 0
6549 12:11:44.522278 3, 0xFFFF, sum = 0
6550 12:11:44.522359 4, 0xFFFF, sum = 0
6551 12:11:44.525399 5, 0xFFFF, sum = 0
6552 12:11:44.525502 6, 0xFFFF, sum = 0
6553 12:11:44.528675 7, 0xFFFF, sum = 0
6554 12:11:44.528758 8, 0xFFFF, sum = 0
6555 12:11:44.532267 9, 0xFFFF, sum = 0
6556 12:11:44.535157 10, 0xFFFF, sum = 0
6557 12:11:44.535251 11, 0xFFFF, sum = 0
6558 12:11:44.538439 12, 0xFFFF, sum = 0
6559 12:11:44.538517 13, 0x0, sum = 1
6560 12:11:44.541603 14, 0x0, sum = 2
6561 12:11:44.541682 15, 0x0, sum = 3
6562 12:11:44.544866 16, 0x0, sum = 4
6563 12:11:44.544956 best_step = 14
6564 12:11:44.545022
6565 12:11:44.545084 ==
6566 12:11:44.548709 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 12:11:44.552100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 12:11:44.552206 ==
6569 12:11:44.555208 RX Vref Scan: 0
6570 12:11:44.555285
6571 12:11:44.558461 RX Vref 0 -> 0, step: 1
6572 12:11:44.558539
6573 12:11:44.558618 RX Delay -359 -> 252, step: 8
6574 12:11:44.567261 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6575 12:11:44.570554 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6576 12:11:44.573905 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6577 12:11:44.580412 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6578 12:11:44.583673 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6579 12:11:44.586839 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6580 12:11:44.590263 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6581 12:11:44.597116 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6582 12:11:44.600233 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6583 12:11:44.603574 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6584 12:11:44.606765 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6585 12:11:44.613164 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6586 12:11:44.616223 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6587 12:11:44.619917 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6588 12:11:44.623007 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6589 12:11:44.629794 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6590 12:11:44.629873 ==
6591 12:11:44.633091 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 12:11:44.636227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 12:11:44.636308 ==
6594 12:11:44.639846 DQS Delay:
6595 12:11:44.639927 DQS0 = 44, DQS1 = 60
6596 12:11:44.639996 DQM Delay:
6597 12:11:44.642808 DQM0 = 9, DQM1 = 14
6598 12:11:44.642885 DQ Delay:
6599 12:11:44.646003 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6600 12:11:44.649239 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =12
6601 12:11:44.653147 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6602 12:11:44.656341 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6603 12:11:44.656416
6604 12:11:44.656488
6605 12:11:44.665957 [DQSOSCAuto] RK1, (LSB)MR18= 0x857e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6606 12:11:44.666058 CH0 RK1: MR19=C0C, MR18=857E
6607 12:11:44.672345 CH0_RK1: MR19=0xC0C, MR18=0x857E, DQSOSC=393, MR23=63, INC=382, DEC=254
6608 12:11:44.675569 [RxdqsGatingPostProcess] freq 400
6609 12:11:44.682184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6610 12:11:44.685520 best DQS0 dly(2T, 0.5T) = (0, 10)
6611 12:11:44.688791 best DQS1 dly(2T, 0.5T) = (0, 10)
6612 12:11:44.692110 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6613 12:11:44.695277 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6614 12:11:44.698724 best DQS0 dly(2T, 0.5T) = (0, 10)
6615 12:11:44.702338 best DQS1 dly(2T, 0.5T) = (0, 10)
6616 12:11:44.705574 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6617 12:11:44.708826 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6618 12:11:44.708900 Pre-setting of DQS Precalculation
6619 12:11:44.715132 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6620 12:11:44.715210 ==
6621 12:11:44.718167 Dram Type= 6, Freq= 0, CH_1, rank 0
6622 12:11:44.722005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 12:11:44.722083 ==
6624 12:11:44.728714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 12:11:44.735193 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6626 12:11:44.738443 [CA 0] Center 36 (8~64) winsize 57
6627 12:11:44.741537 [CA 1] Center 36 (8~64) winsize 57
6628 12:11:44.745124 [CA 2] Center 36 (8~64) winsize 57
6629 12:11:44.748104 [CA 3] Center 36 (8~64) winsize 57
6630 12:11:44.751360 [CA 4] Center 36 (8~64) winsize 57
6631 12:11:44.751450 [CA 5] Center 36 (8~64) winsize 57
6632 12:11:44.754561
6633 12:11:44.757899 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6634 12:11:44.757984
6635 12:11:44.761666 [CATrainingPosCal] consider 1 rank data
6636 12:11:44.765028 u2DelayCellTimex100 = 270/100 ps
6637 12:11:44.768222 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 12:11:44.771461 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:11:44.774750 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:11:44.778040 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:11:44.781354 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 12:11:44.784601 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:11:44.784686
6644 12:11:44.787947 CA PerBit enable=1, Macro0, CA PI delay=36
6645 12:11:44.788036
6646 12:11:44.791143 [CBTSetCACLKResult] CA Dly = 36
6647 12:11:44.794418 CS Dly: 1 (0~32)
6648 12:11:44.794504 ==
6649 12:11:44.797537 Dram Type= 6, Freq= 0, CH_1, rank 1
6650 12:11:44.800841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 12:11:44.800925 ==
6652 12:11:44.807714 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6653 12:11:44.814181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6654 12:11:44.817532 [CA 0] Center 36 (8~64) winsize 57
6655 12:11:44.820530 [CA 1] Center 36 (8~64) winsize 57
6656 12:11:44.824221 [CA 2] Center 36 (8~64) winsize 57
6657 12:11:44.824308 [CA 3] Center 36 (8~64) winsize 57
6658 12:11:44.827413 [CA 4] Center 36 (8~64) winsize 57
6659 12:11:44.830390 [CA 5] Center 36 (8~64) winsize 57
6660 12:11:44.830482
6661 12:11:44.837086 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6662 12:11:44.837206
6663 12:11:44.840331 [CATrainingPosCal] consider 2 rank data
6664 12:11:44.843481 u2DelayCellTimex100 = 270/100 ps
6665 12:11:44.847062 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 12:11:44.850468 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:11:44.853588 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:11:44.856842 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:11:44.859902 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:11:44.863173 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:11:44.863256
6672 12:11:44.866516 CA PerBit enable=1, Macro0, CA PI delay=36
6673 12:11:44.866613
6674 12:11:44.869834 [CBTSetCACLKResult] CA Dly = 36
6675 12:11:44.872965 CS Dly: 1 (0~32)
6676 12:11:44.873052
6677 12:11:44.876346 ----->DramcWriteLeveling(PI) begin...
6678 12:11:44.876433 ==
6679 12:11:44.879630 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 12:11:44.882977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 12:11:44.883061 ==
6682 12:11:44.886263 Write leveling (Byte 0): 40 => 8
6683 12:11:44.889589 Write leveling (Byte 1): 40 => 8
6684 12:11:44.892929 DramcWriteLeveling(PI) end<-----
6685 12:11:44.893013
6686 12:11:44.893078 ==
6687 12:11:44.896188 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 12:11:44.899928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 12:11:44.900059 ==
6690 12:11:44.903239 [Gating] SW mode calibration
6691 12:11:44.909736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6692 12:11:44.915921 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6693 12:11:44.919203 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6694 12:11:44.926018 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6695 12:11:44.929055 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 12:11:44.932216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 12:11:44.939033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 12:11:44.941977 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 12:11:44.945266 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 12:11:44.952006 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 12:11:44.955253 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6702 12:11:44.959015 Total UI for P1: 0, mck2ui 16
6703 12:11:44.962084 best dqsien dly found for B0: ( 0, 14, 24)
6704 12:11:44.965226 Total UI for P1: 0, mck2ui 16
6705 12:11:44.968395 best dqsien dly found for B1: ( 0, 14, 24)
6706 12:11:44.971590 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6707 12:11:44.974861 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6708 12:11:44.974961
6709 12:11:44.977977 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6710 12:11:44.985241 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 12:11:44.985342 [Gating] SW calibration Done
6712 12:11:44.985440 ==
6713 12:11:44.988572 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 12:11:44.995024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 12:11:44.995130 ==
6716 12:11:44.995228 RX Vref Scan: 0
6717 12:11:44.995320
6718 12:11:44.998360 RX Vref 0 -> 0, step: 1
6719 12:11:44.998475
6720 12:11:45.001544 RX Delay -410 -> 252, step: 16
6721 12:11:45.004770 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6722 12:11:45.007998 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6723 12:11:45.014403 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6724 12:11:45.017577 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6725 12:11:45.020843 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6726 12:11:45.024598 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6727 12:11:45.030919 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6728 12:11:45.034121 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6729 12:11:45.037915 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6730 12:11:45.040874 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6731 12:11:45.047470 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6732 12:11:45.050685 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6733 12:11:45.054604 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6734 12:11:45.057513 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6735 12:11:45.064388 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6736 12:11:45.067466 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6737 12:11:45.067580 ==
6738 12:11:45.070649 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 12:11:45.073946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 12:11:45.077148 ==
6741 12:11:45.077254 DQS Delay:
6742 12:11:45.077362 DQS0 = 35, DQS1 = 51
6743 12:11:45.080542 DQM Delay:
6744 12:11:45.080664 DQM0 = 6, DQM1 = 13
6745 12:11:45.083725 DQ Delay:
6746 12:11:45.083832 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6747 12:11:45.087041 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6748 12:11:45.090336 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6749 12:11:45.093585 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6750 12:11:45.093696
6751 12:11:45.093793
6752 12:11:45.093893 ==
6753 12:11:45.096850 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 12:11:45.103360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 12:11:45.103447 ==
6756 12:11:45.103543
6757 12:11:45.103634
6758 12:11:45.103722 TX Vref Scan disable
6759 12:11:45.107103 == TX Byte 0 ==
6760 12:11:45.110349 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 12:11:45.113673 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 12:11:45.116765 == TX Byte 1 ==
6763 12:11:45.119931 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 12:11:45.123067 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 12:11:45.126818 ==
6766 12:11:45.130083 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 12:11:45.133312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 12:11:45.133421 ==
6769 12:11:45.133514
6770 12:11:45.133603
6771 12:11:45.136307 TX Vref Scan disable
6772 12:11:45.136416 == TX Byte 0 ==
6773 12:11:45.140115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 12:11:45.146183 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 12:11:45.146310 == TX Byte 1 ==
6776 12:11:45.149804 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 12:11:45.156716 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 12:11:45.156824
6779 12:11:45.156921 [DATLAT]
6780 12:11:45.157013 Freq=400, CH1 RK0
6781 12:11:45.157104
6782 12:11:45.159836 DATLAT Default: 0xf
6783 12:11:45.163125 0, 0xFFFF, sum = 0
6784 12:11:45.163229 1, 0xFFFF, sum = 0
6785 12:11:45.166348 2, 0xFFFF, sum = 0
6786 12:11:45.166463 3, 0xFFFF, sum = 0
6787 12:11:45.169574 4, 0xFFFF, sum = 0
6788 12:11:45.169682 5, 0xFFFF, sum = 0
6789 12:11:45.172569 6, 0xFFFF, sum = 0
6790 12:11:45.172675 7, 0xFFFF, sum = 0
6791 12:11:45.175822 8, 0xFFFF, sum = 0
6792 12:11:45.175968 9, 0xFFFF, sum = 0
6793 12:11:45.179013 10, 0xFFFF, sum = 0
6794 12:11:45.179120 11, 0xFFFF, sum = 0
6795 12:11:45.182856 12, 0xFFFF, sum = 0
6796 12:11:45.183004 13, 0x0, sum = 1
6797 12:11:45.185509 14, 0x0, sum = 2
6798 12:11:45.185620 15, 0x0, sum = 3
6799 12:11:45.188818 16, 0x0, sum = 4
6800 12:11:45.188902 best_step = 14
6801 12:11:45.188965
6802 12:11:45.189060 ==
6803 12:11:45.192190 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 12:11:45.198826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:11:45.198940 ==
6806 12:11:45.199007 RX Vref Scan: 1
6807 12:11:45.199069
6808 12:11:45.202211 RX Vref 0 -> 0, step: 1
6809 12:11:45.202295
6810 12:11:45.205980 RX Delay -343 -> 252, step: 8
6811 12:11:45.206073
6812 12:11:45.209192 Set Vref, RX VrefLevel [Byte0]: 52
6813 12:11:45.212353 [Byte1]: 49
6814 12:11:45.215622
6815 12:11:45.215716 Final RX Vref Byte 0 = 52 to rank0
6816 12:11:45.218951 Final RX Vref Byte 1 = 49 to rank0
6817 12:11:45.222274 Final RX Vref Byte 0 = 52 to rank1
6818 12:11:45.225423 Final RX Vref Byte 1 = 49 to rank1==
6819 12:11:45.228644 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 12:11:45.235073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 12:11:45.235207 ==
6822 12:11:45.235277 DQS Delay:
6823 12:11:45.238377 DQS0 = 44, DQS1 = 56
6824 12:11:45.238453 DQM Delay:
6825 12:11:45.238522 DQM0 = 11, DQM1 = 13
6826 12:11:45.242033 DQ Delay:
6827 12:11:45.245118 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6828 12:11:45.248240 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6829 12:11:45.248313 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6830 12:11:45.251853 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6831 12:11:45.254662
6832 12:11:45.254737
6833 12:11:45.261661 [DQSOSCAuto] RK0, (LSB)MR18= 0x6086, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 397 ps
6834 12:11:45.265284 CH1 RK0: MR19=C0C, MR18=6086
6835 12:11:45.271675 CH1_RK0: MR19=0xC0C, MR18=0x6086, DQSOSC=393, MR23=63, INC=382, DEC=254
6836 12:11:45.271764 ==
6837 12:11:45.274904 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 12:11:45.278032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 12:11:45.278107 ==
6840 12:11:45.281116 [Gating] SW mode calibration
6841 12:11:45.287931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6842 12:11:45.294485 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6843 12:11:45.297709 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6844 12:11:45.301188 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6845 12:11:45.307530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 12:11:45.310820 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 12:11:45.313979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 12:11:45.320410 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 12:11:45.323560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 12:11:45.326883 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 12:11:45.333656 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6852 12:11:45.336994 Total UI for P1: 0, mck2ui 16
6853 12:11:45.340103 best dqsien dly found for B0: ( 0, 14, 24)
6854 12:11:45.343312 Total UI for P1: 0, mck2ui 16
6855 12:11:45.347017 best dqsien dly found for B1: ( 0, 14, 24)
6856 12:11:45.349986 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6857 12:11:45.353765 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6858 12:11:45.353851
6859 12:11:45.356854 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6860 12:11:45.359873 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 12:11:45.363576 [Gating] SW calibration Done
6862 12:11:45.363660 ==
6863 12:11:45.366728 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 12:11:45.369815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 12:11:45.373528 ==
6866 12:11:45.373612 RX Vref Scan: 0
6867 12:11:45.373679
6868 12:11:45.376613 RX Vref 0 -> 0, step: 1
6869 12:11:45.376710
6870 12:11:45.379852 RX Delay -410 -> 252, step: 16
6871 12:11:45.382905 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6872 12:11:45.386703 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6873 12:11:45.389931 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6874 12:11:45.396456 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6875 12:11:45.399811 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6876 12:11:45.403220 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6877 12:11:45.406549 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6878 12:11:45.413031 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6879 12:11:45.416131 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6880 12:11:45.419317 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6881 12:11:45.422618 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6882 12:11:45.429020 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6883 12:11:45.432815 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6884 12:11:45.436158 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6885 12:11:45.442393 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6886 12:11:45.445688 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6887 12:11:45.445775 ==
6888 12:11:45.448833 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 12:11:45.451866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 12:11:45.451952 ==
6891 12:11:45.455601 DQS Delay:
6892 12:11:45.455714 DQS0 = 43, DQS1 = 51
6893 12:11:45.458531 DQM Delay:
6894 12:11:45.458641 DQM0 = 10, DQM1 = 12
6895 12:11:45.458708 DQ Delay:
6896 12:11:45.461798 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6897 12:11:45.465269 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6898 12:11:45.468409 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6899 12:11:45.472176 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6900 12:11:45.472262
6901 12:11:45.472330
6902 12:11:45.472393 ==
6903 12:11:45.475301 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 12:11:45.482053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 12:11:45.482207 ==
6906 12:11:45.482307
6907 12:11:45.482406
6908 12:11:45.482515 TX Vref Scan disable
6909 12:11:45.485249 == TX Byte 0 ==
6910 12:11:45.488625 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6911 12:11:45.491869 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6912 12:11:45.495220 == TX Byte 1 ==
6913 12:11:45.498426 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6914 12:11:45.501769 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6915 12:11:45.501891 ==
6916 12:11:45.505037 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 12:11:45.511354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 12:11:45.511459 ==
6919 12:11:45.511560
6920 12:11:45.511652
6921 12:11:45.514553 TX Vref Scan disable
6922 12:11:45.514674 == TX Byte 0 ==
6923 12:11:45.517645 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6924 12:11:45.521414 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6925 12:11:45.524716 == TX Byte 1 ==
6926 12:11:45.527840 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6927 12:11:45.531019 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6928 12:11:45.534116
6929 12:11:45.534216 [DATLAT]
6930 12:11:45.534281 Freq=400, CH1 RK1
6931 12:11:45.534342
6932 12:11:45.537891 DATLAT Default: 0xe
6933 12:11:45.537978 0, 0xFFFF, sum = 0
6934 12:11:45.541184 1, 0xFFFF, sum = 0
6935 12:11:45.541279 2, 0xFFFF, sum = 0
6936 12:11:45.544162 3, 0xFFFF, sum = 0
6937 12:11:45.547364 4, 0xFFFF, sum = 0
6938 12:11:45.547440 5, 0xFFFF, sum = 0
6939 12:11:45.550616 6, 0xFFFF, sum = 0
6940 12:11:45.550697 7, 0xFFFF, sum = 0
6941 12:11:45.553989 8, 0xFFFF, sum = 0
6942 12:11:45.554069 9, 0xFFFF, sum = 0
6943 12:11:45.557051 10, 0xFFFF, sum = 0
6944 12:11:45.557125 11, 0xFFFF, sum = 0
6945 12:11:45.560511 12, 0xFFFF, sum = 0
6946 12:11:45.560599 13, 0x0, sum = 1
6947 12:11:45.563663 14, 0x0, sum = 2
6948 12:11:45.563736 15, 0x0, sum = 3
6949 12:11:45.567409 16, 0x0, sum = 4
6950 12:11:45.567494 best_step = 14
6951 12:11:45.567562
6952 12:11:45.567630 ==
6953 12:11:45.570419 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 12:11:45.573572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 12:11:45.577223 ==
6956 12:11:45.577308 RX Vref Scan: 0
6957 12:11:45.577376
6958 12:11:45.580319 RX Vref 0 -> 0, step: 1
6959 12:11:45.580409
6960 12:11:45.583488 RX Delay -343 -> 252, step: 8
6961 12:11:45.590514 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6962 12:11:45.593120 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6963 12:11:45.597008 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6964 12:11:45.600439 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6965 12:11:45.606917 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6966 12:11:45.610162 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6967 12:11:45.613479 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6968 12:11:45.616793 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6969 12:11:45.623255 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6970 12:11:45.626533 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6971 12:11:45.629834 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6972 12:11:45.633084 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6973 12:11:45.639683 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6974 12:11:45.642954 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6975 12:11:45.646262 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6976 12:11:45.652571 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6977 12:11:45.652656 ==
6978 12:11:45.655738 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 12:11:45.658974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 12:11:45.659060 ==
6981 12:11:45.659129 DQS Delay:
6982 12:11:45.662823 DQS0 = 48, DQS1 = 56
6983 12:11:45.662908 DQM Delay:
6984 12:11:45.665814 DQM0 = 12, DQM1 = 14
6985 12:11:45.665899 DQ Delay:
6986 12:11:45.668807 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6987 12:11:45.672631 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6988 12:11:45.675661 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6989 12:11:45.679348 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6990 12:11:45.679461
6991 12:11:45.679557
6992 12:11:45.685429 [DQSOSCAuto] RK1, (LSB)MR18= 0x72aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6993 12:11:45.689216 CH1 RK1: MR19=C0C, MR18=72AA
6994 12:11:45.695765 CH1_RK1: MR19=0xC0C, MR18=0x72AA, DQSOSC=388, MR23=63, INC=392, DEC=261
6995 12:11:45.699143 [RxdqsGatingPostProcess] freq 400
6996 12:11:45.705626 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6997 12:11:45.708940 best DQS0 dly(2T, 0.5T) = (0, 10)
6998 12:11:45.712245 best DQS1 dly(2T, 0.5T) = (0, 10)
6999 12:11:45.715636 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7000 12:11:45.718893 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7001 12:11:45.719008 best DQS0 dly(2T, 0.5T) = (0, 10)
7002 12:11:45.722133 best DQS1 dly(2T, 0.5T) = (0, 10)
7003 12:11:45.725356 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7004 12:11:45.728604 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7005 12:11:45.731821 Pre-setting of DQS Precalculation
7006 12:11:45.738197 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7007 12:11:45.744661 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7008 12:11:45.751731 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7009 12:11:45.751845
7010 12:11:45.751945
7011 12:11:45.754929 [Calibration Summary] 800 Mbps
7012 12:11:45.755032 CH 0, Rank 0
7013 12:11:45.758279 SW Impedance : PASS
7014 12:11:45.761531 DUTY Scan : NO K
7015 12:11:45.761636 ZQ Calibration : PASS
7016 12:11:45.764767 Jitter Meter : NO K
7017 12:11:45.767912 CBT Training : PASS
7018 12:11:45.768040 Write leveling : PASS
7019 12:11:45.771051 RX DQS gating : PASS
7020 12:11:45.774738 RX DQ/DQS(RDDQC) : PASS
7021 12:11:45.774850 TX DQ/DQS : PASS
7022 12:11:45.777863 RX DATLAT : PASS
7023 12:11:45.780990 RX DQ/DQS(Engine): PASS
7024 12:11:45.781097 TX OE : NO K
7025 12:11:45.783909 All Pass.
7026 12:11:45.784013
7027 12:11:45.784106 CH 0, Rank 1
7028 12:11:45.787658 SW Impedance : PASS
7029 12:11:45.787759 DUTY Scan : NO K
7030 12:11:45.790835 ZQ Calibration : PASS
7031 12:11:45.793814 Jitter Meter : NO K
7032 12:11:45.793926 CBT Training : PASS
7033 12:11:45.797611 Write leveling : NO K
7034 12:11:45.800803 RX DQS gating : PASS
7035 12:11:45.800877 RX DQ/DQS(RDDQC) : PASS
7036 12:11:45.804163 TX DQ/DQS : PASS
7037 12:11:45.807619 RX DATLAT : PASS
7038 12:11:45.807722 RX DQ/DQS(Engine): PASS
7039 12:11:45.810237 TX OE : NO K
7040 12:11:45.810311 All Pass.
7041 12:11:45.810374
7042 12:11:45.813609 CH 1, Rank 0
7043 12:11:45.813681 SW Impedance : PASS
7044 12:11:45.816795 DUTY Scan : NO K
7045 12:11:45.820570 ZQ Calibration : PASS
7046 12:11:45.820655 Jitter Meter : NO K
7047 12:11:45.823817 CBT Training : PASS
7048 12:11:45.826934 Write leveling : PASS
7049 12:11:45.827019 RX DQS gating : PASS
7050 12:11:45.830171 RX DQ/DQS(RDDQC) : PASS
7051 12:11:45.833256 TX DQ/DQS : PASS
7052 12:11:45.833349 RX DATLAT : PASS
7053 12:11:45.836606 RX DQ/DQS(Engine): PASS
7054 12:11:45.840396 TX OE : NO K
7055 12:11:45.840482 All Pass.
7056 12:11:45.840558
7057 12:11:45.840623 CH 1, Rank 1
7058 12:11:45.843598 SW Impedance : PASS
7059 12:11:45.846836 DUTY Scan : NO K
7060 12:11:45.846942 ZQ Calibration : PASS
7061 12:11:45.850091 Jitter Meter : NO K
7062 12:11:45.853271 CBT Training : PASS
7063 12:11:45.853356 Write leveling : NO K
7064 12:11:45.856395 RX DQS gating : PASS
7065 12:11:45.856480 RX DQ/DQS(RDDQC) : PASS
7066 12:11:45.859603 TX DQ/DQS : PASS
7067 12:11:45.863362 RX DATLAT : PASS
7068 12:11:45.863468 RX DQ/DQS(Engine): PASS
7069 12:11:45.866022 TX OE : NO K
7070 12:11:45.866099 All Pass.
7071 12:11:45.866163
7072 12:11:45.869827 DramC Write-DBI off
7073 12:11:45.872953 PER_BANK_REFRESH: Hybrid Mode
7074 12:11:45.873038 TX_TRACKING: ON
7075 12:11:45.882886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7076 12:11:45.885949 [FAST_K] Save calibration result to emmc
7077 12:11:45.889604 dramc_set_vcore_voltage set vcore to 725000
7078 12:11:45.892776 Read voltage for 1600, 0
7079 12:11:45.892866 Vio18 = 0
7080 12:11:45.895826 Vcore = 725000
7081 12:11:45.895911 Vdram = 0
7082 12:11:45.895980 Vddq = 0
7083 12:11:45.896052 Vmddr = 0
7084 12:11:45.902625 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7085 12:11:45.909414 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7086 12:11:45.909500 MEM_TYPE=3, freq_sel=13
7087 12:11:45.912609 sv_algorithm_assistance_LP4_3733
7088 12:11:45.919098 ============ PULL DRAM RESETB DOWN ============
7089 12:11:45.922350 ========== PULL DRAM RESETB DOWN end =========
7090 12:11:45.925642 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7091 12:11:45.928837 ===================================
7092 12:11:45.932102 LPDDR4 DRAM CONFIGURATION
7093 12:11:45.935284 ===================================
7094 12:11:45.935363 EX_ROW_EN[0] = 0x0
7095 12:11:45.938555 EX_ROW_EN[1] = 0x0
7096 12:11:45.941794 LP4Y_EN = 0x0
7097 12:11:45.941883 WORK_FSP = 0x1
7098 12:11:45.945141 WL = 0x5
7099 12:11:45.945229 RL = 0x5
7100 12:11:45.948902 BL = 0x2
7101 12:11:45.948989 RPST = 0x0
7102 12:11:45.952070 RD_PRE = 0x0
7103 12:11:45.952157 WR_PRE = 0x1
7104 12:11:45.955314 WR_PST = 0x1
7105 12:11:45.955401 DBI_WR = 0x0
7106 12:11:45.958583 DBI_RD = 0x0
7107 12:11:45.958671 OTF = 0x1
7108 12:11:45.961736 ===================================
7109 12:11:45.964955 ===================================
7110 12:11:45.968210 ANA top config
7111 12:11:45.971460 ===================================
7112 12:11:45.974785 DLL_ASYNC_EN = 0
7113 12:11:45.974865 ALL_SLAVE_EN = 0
7114 12:11:45.978099 NEW_RANK_MODE = 1
7115 12:11:45.981166 DLL_IDLE_MODE = 1
7116 12:11:45.984730 LP45_APHY_COMB_EN = 1
7117 12:11:45.984810 TX_ODT_DIS = 0
7118 12:11:45.987737 NEW_8X_MODE = 1
7119 12:11:45.991485 ===================================
7120 12:11:45.994498 ===================================
7121 12:11:45.997660 data_rate = 3200
7122 12:11:46.000897 CKR = 1
7123 12:11:46.004582 DQ_P2S_RATIO = 8
7124 12:11:46.007806 ===================================
7125 12:11:46.010914 CA_P2S_RATIO = 8
7126 12:11:46.014261 DQ_CA_OPEN = 0
7127 12:11:46.014375 DQ_SEMI_OPEN = 0
7128 12:11:46.017571 CA_SEMI_OPEN = 0
7129 12:11:46.020927 CA_FULL_RATE = 0
7130 12:11:46.024136 DQ_CKDIV4_EN = 0
7131 12:11:46.027472 CA_CKDIV4_EN = 0
7132 12:11:46.030550 CA_PREDIV_EN = 0
7133 12:11:46.030627 PH8_DLY = 12
7134 12:11:46.033759 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7135 12:11:46.037680 DQ_AAMCK_DIV = 4
7136 12:11:46.040923 CA_AAMCK_DIV = 4
7137 12:11:46.044029 CA_ADMCK_DIV = 4
7138 12:11:46.047269 DQ_TRACK_CA_EN = 0
7139 12:11:46.047345 CA_PICK = 1600
7140 12:11:46.050432 CA_MCKIO = 1600
7141 12:11:46.053688 MCKIO_SEMI = 0
7142 12:11:46.056939 PLL_FREQ = 3068
7143 12:11:46.060318 DQ_UI_PI_RATIO = 32
7144 12:11:46.063564 CA_UI_PI_RATIO = 0
7145 12:11:46.066635 ===================================
7146 12:11:46.070274 ===================================
7147 12:11:46.073436 memory_type:LPDDR4
7148 12:11:46.073518 GP_NUM : 10
7149 12:11:46.076631 SRAM_EN : 1
7150 12:11:46.076744 MD32_EN : 0
7151 12:11:46.079834 ===================================
7152 12:11:46.083089 [ANA_INIT] >>>>>>>>>>>>>>
7153 12:11:46.086859 <<<<<< [CONFIGURE PHASE]: ANA_TX
7154 12:11:46.089999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7155 12:11:46.092964 ===================================
7156 12:11:46.096643 data_rate = 3200,PCW = 0X7600
7157 12:11:46.099890 ===================================
7158 12:11:46.102894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7159 12:11:46.109839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7160 12:11:46.112854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 12:11:46.119575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7162 12:11:46.122583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7163 12:11:46.126509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7164 12:11:46.126595 [ANA_INIT] flow start
7165 12:11:46.129625 [ANA_INIT] PLL >>>>>>>>
7166 12:11:46.132918 [ANA_INIT] PLL <<<<<<<<
7167 12:11:46.136123 [ANA_INIT] MIDPI >>>>>>>>
7168 12:11:46.136211 [ANA_INIT] MIDPI <<<<<<<<
7169 12:11:46.139189 [ANA_INIT] DLL >>>>>>>>
7170 12:11:46.142570 [ANA_INIT] DLL <<<<<<<<
7171 12:11:46.142684 [ANA_INIT] flow end
7172 12:11:46.145815 ============ LP4 DIFF to SE enter ============
7173 12:11:46.152949 ============ LP4 DIFF to SE exit ============
7174 12:11:46.153058 [ANA_INIT] <<<<<<<<<<<<<
7175 12:11:46.155585 [Flow] Enable top DCM control >>>>>
7176 12:11:46.159428 [Flow] Enable top DCM control <<<<<
7177 12:11:46.162656 Enable DLL master slave shuffle
7178 12:11:46.169191 ==============================================================
7179 12:11:46.172242 Gating Mode config
7180 12:11:46.175911 ==============================================================
7181 12:11:46.179083 Config description:
7182 12:11:46.188679 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7183 12:11:46.194947 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7184 12:11:46.198404 SELPH_MODE 0: By rank 1: By Phase
7185 12:11:46.205182 ==============================================================
7186 12:11:46.208133 GAT_TRACK_EN = 1
7187 12:11:46.211943 RX_GATING_MODE = 2
7188 12:11:46.215200 RX_GATING_TRACK_MODE = 2
7189 12:11:46.218401 SELPH_MODE = 1
7190 12:11:46.218507 PICG_EARLY_EN = 1
7191 12:11:46.221555 VALID_LAT_VALUE = 1
7192 12:11:46.228105 ==============================================================
7193 12:11:46.231398 Enter into Gating configuration >>>>
7194 12:11:46.234667 Exit from Gating configuration <<<<
7195 12:11:46.237934 Enter into DVFS_PRE_config >>>>>
7196 12:11:46.247693 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7197 12:11:46.250855 Exit from DVFS_PRE_config <<<<<
7198 12:11:46.254077 Enter into PICG configuration >>>>
7199 12:11:46.257376 Exit from PICG configuration <<<<
7200 12:11:46.261124 [RX_INPUT] configuration >>>>>
7201 12:11:46.264541 [RX_INPUT] configuration <<<<<
7202 12:11:46.270952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7203 12:11:46.274130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7204 12:11:46.280755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 12:11:46.287630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 12:11:46.294013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 12:11:46.300319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 12:11:46.303964 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7209 12:11:46.307279 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7210 12:11:46.310459 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7211 12:11:46.316552 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7212 12:11:46.320423 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7213 12:11:46.324048 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 12:11:46.326599 ===================================
7215 12:11:46.329631 LPDDR4 DRAM CONFIGURATION
7216 12:11:46.333595 ===================================
7217 12:11:46.336803 EX_ROW_EN[0] = 0x0
7218 12:11:46.336882 EX_ROW_EN[1] = 0x0
7219 12:11:46.340070 LP4Y_EN = 0x0
7220 12:11:46.340181 WORK_FSP = 0x1
7221 12:11:46.343439 WL = 0x5
7222 12:11:46.343530 RL = 0x5
7223 12:11:46.346765 BL = 0x2
7224 12:11:46.346869 RPST = 0x0
7225 12:11:46.349939 RD_PRE = 0x0
7226 12:11:46.350018 WR_PRE = 0x1
7227 12:11:46.353218 WR_PST = 0x1
7228 12:11:46.353294 DBI_WR = 0x0
7229 12:11:46.356581 DBI_RD = 0x0
7230 12:11:46.356672 OTF = 0x1
7231 12:11:46.363000 ===================================
7232 12:11:46.366173 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7233 12:11:46.369491 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7234 12:11:46.372808 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 12:11:46.375967 ===================================
7236 12:11:46.379146 LPDDR4 DRAM CONFIGURATION
7237 12:11:46.382943 ===================================
7238 12:11:46.386022 EX_ROW_EN[0] = 0x10
7239 12:11:46.386100 EX_ROW_EN[1] = 0x0
7240 12:11:46.389217 LP4Y_EN = 0x0
7241 12:11:46.389303 WORK_FSP = 0x1
7242 12:11:46.392395 WL = 0x5
7243 12:11:46.392488 RL = 0x5
7244 12:11:46.395614 BL = 0x2
7245 12:11:46.395701 RPST = 0x0
7246 12:11:46.398798 RD_PRE = 0x0
7247 12:11:46.401985 WR_PRE = 0x1
7248 12:11:46.402061 WR_PST = 0x1
7249 12:11:46.405638 DBI_WR = 0x0
7250 12:11:46.405725 DBI_RD = 0x0
7251 12:11:46.408638 OTF = 0x1
7252 12:11:46.411788 ===================================
7253 12:11:46.415546 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7254 12:11:46.418648 ==
7255 12:11:46.421738 Dram Type= 6, Freq= 0, CH_0, rank 0
7256 12:11:46.424849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7257 12:11:46.424951 ==
7258 12:11:46.428198 [Duty_Offset_Calibration]
7259 12:11:46.428271 B0:2 B1:0 CA:4
7260 12:11:46.428339
7261 12:11:46.431976 [DutyScan_Calibration_Flow] k_type=0
7262 12:11:46.441071
7263 12:11:46.441175 ==CLK 0==
7264 12:11:46.444264 Final CLK duty delay cell = -4
7265 12:11:46.447340 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7266 12:11:46.450653 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7267 12:11:46.453927 [-4] AVG Duty = 4937%(X100)
7268 12:11:46.454033
7269 12:11:46.457731 CH0 CLK Duty spec in!! Max-Min= 187%
7270 12:11:46.461081 [DutyScan_Calibration_Flow] ====Done====
7271 12:11:46.461195
7272 12:11:46.464242 [DutyScan_Calibration_Flow] k_type=1
7273 12:11:46.480857
7274 12:11:46.480975 ==DQS 0 ==
7275 12:11:46.484020 Final DQS duty delay cell = -4
7276 12:11:46.487155 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7277 12:11:46.490756 [-4] MIN Duty = 4782%(X100), DQS PI = 4
7278 12:11:46.493919 [-4] AVG Duty = 4860%(X100)
7279 12:11:46.494024
7280 12:11:46.494118 ==DQS 1 ==
7281 12:11:46.497201 Final DQS duty delay cell = 0
7282 12:11:46.500537 [0] MAX Duty = 5187%(X100), DQS PI = 0
7283 12:11:46.503615 [0] MIN Duty = 4969%(X100), DQS PI = 12
7284 12:11:46.506910 [0] AVG Duty = 5078%(X100)
7285 12:11:46.507015
7286 12:11:46.510083 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7287 12:11:46.510186
7288 12:11:46.513189 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7289 12:11:46.516871 [DutyScan_Calibration_Flow] ====Done====
7290 12:11:46.516992
7291 12:11:46.519938 [DutyScan_Calibration_Flow] k_type=3
7292 12:11:46.537705
7293 12:11:46.537830 ==DQM 0 ==
7294 12:11:46.541350 Final DQM duty delay cell = 0
7295 12:11:46.544678 [0] MAX Duty = 5124%(X100), DQS PI = 20
7296 12:11:46.547922 [0] MIN Duty = 4875%(X100), DQS PI = 54
7297 12:11:46.551161 [0] AVG Duty = 4999%(X100)
7298 12:11:46.551268
7299 12:11:46.551405 ==DQM 1 ==
7300 12:11:46.554426 Final DQM duty delay cell = 0
7301 12:11:46.557648 [0] MAX Duty = 4969%(X100), DQS PI = 2
7302 12:11:46.560916 [0] MIN Duty = 4844%(X100), DQS PI = 16
7303 12:11:46.564175 [0] AVG Duty = 4906%(X100)
7304 12:11:46.564280
7305 12:11:46.567360 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7306 12:11:46.567465
7307 12:11:46.570589 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7308 12:11:46.573832 [DutyScan_Calibration_Flow] ====Done====
7309 12:11:46.573982
7310 12:11:46.577015 [DutyScan_Calibration_Flow] k_type=2
7311 12:11:46.594923
7312 12:11:46.595053 ==DQ 0 ==
7313 12:11:46.598625 Final DQ duty delay cell = 0
7314 12:11:46.601809 [0] MAX Duty = 5124%(X100), DQS PI = 20
7315 12:11:46.605044 [0] MIN Duty = 4938%(X100), DQS PI = 12
7316 12:11:46.608363 [0] AVG Duty = 5031%(X100)
7317 12:11:46.608435
7318 12:11:46.608509 ==DQ 1 ==
7319 12:11:46.611528 Final DQ duty delay cell = 0
7320 12:11:46.614803 [0] MAX Duty = 5187%(X100), DQS PI = 4
7321 12:11:46.617807 [0] MIN Duty = 4938%(X100), DQS PI = 12
7322 12:11:46.621586 [0] AVG Duty = 5062%(X100)
7323 12:11:46.621701
7324 12:11:46.624563 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7325 12:11:46.624663
7326 12:11:46.627569 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7327 12:11:46.631454 [DutyScan_Calibration_Flow] ====Done====
7328 12:11:46.631596 ==
7329 12:11:46.634720 Dram Type= 6, Freq= 0, CH_1, rank 0
7330 12:11:46.638158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7331 12:11:46.638318 ==
7332 12:11:46.641280 [Duty_Offset_Calibration]
7333 12:11:46.641383 B0:0 B1:-1 CA:3
7334 12:11:46.641471
7335 12:11:46.644526 [DutyScan_Calibration_Flow] k_type=0
7336 12:11:46.654274
7337 12:11:46.654362 ==CLK 0==
7338 12:11:46.657980 Final CLK duty delay cell = -4
7339 12:11:46.661220 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7340 12:11:46.664501 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7341 12:11:46.667676 [-4] AVG Duty = 4953%(X100)
7342 12:11:46.667757
7343 12:11:46.670883 CH1 CLK Duty spec in!! Max-Min= 156%
7344 12:11:46.674138 [DutyScan_Calibration_Flow] ====Done====
7345 12:11:46.674213
7346 12:11:46.677369 [DutyScan_Calibration_Flow] k_type=1
7347 12:11:46.693684
7348 12:11:46.693803 ==DQS 0 ==
7349 12:11:46.696913 Final DQS duty delay cell = 0
7350 12:11:46.700669 [0] MAX Duty = 5250%(X100), DQS PI = 30
7351 12:11:46.703580 [0] MIN Duty = 4907%(X100), DQS PI = 56
7352 12:11:46.706801 [0] AVG Duty = 5078%(X100)
7353 12:11:46.706879
7354 12:11:46.706965 ==DQS 1 ==
7355 12:11:46.710183 Final DQS duty delay cell = -4
7356 12:11:46.713379 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7357 12:11:46.716561 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7358 12:11:46.720242 [-4] AVG Duty = 4906%(X100)
7359 12:11:46.720336
7360 12:11:46.723382 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7361 12:11:46.723470
7362 12:11:46.726465 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7363 12:11:46.730058 [DutyScan_Calibration_Flow] ====Done====
7364 12:11:46.730135
7365 12:11:46.733060 [DutyScan_Calibration_Flow] k_type=3
7366 12:11:46.750961
7367 12:11:46.751094 ==DQM 0 ==
7368 12:11:46.754341 Final DQM duty delay cell = 0
7369 12:11:46.757623 [0] MAX Duty = 5062%(X100), DQS PI = 30
7370 12:11:46.760899 [0] MIN Duty = 4782%(X100), DQS PI = 40
7371 12:11:46.763967 [0] AVG Duty = 4922%(X100)
7372 12:11:46.764092
7373 12:11:46.764175 ==DQM 1 ==
7374 12:11:46.767424 Final DQM duty delay cell = 0
7375 12:11:46.770604 [0] MAX Duty = 5000%(X100), DQS PI = 30
7376 12:11:46.773922 [0] MIN Duty = 4813%(X100), DQS PI = 14
7377 12:11:46.777141 [0] AVG Duty = 4906%(X100)
7378 12:11:46.777219
7379 12:11:46.780266 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7380 12:11:46.780355
7381 12:11:46.783632 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7382 12:11:46.787010 [DutyScan_Calibration_Flow] ====Done====
7383 12:11:46.787126
7384 12:11:46.790291 [DutyScan_Calibration_Flow] k_type=2
7385 12:11:46.807220
7386 12:11:46.807315 ==DQ 0 ==
7387 12:11:46.810324 Final DQ duty delay cell = -4
7388 12:11:46.813579 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7389 12:11:46.816842 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7390 12:11:46.820086 [-4] AVG Duty = 4875%(X100)
7391 12:11:46.820172
7392 12:11:46.820253 ==DQ 1 ==
7393 12:11:46.823790 Final DQ duty delay cell = 0
7394 12:11:46.826876 [0] MAX Duty = 5062%(X100), DQS PI = 32
7395 12:11:46.830132 [0] MIN Duty = 4875%(X100), DQS PI = 54
7396 12:11:46.833198 [0] AVG Duty = 4968%(X100)
7397 12:11:46.833274
7398 12:11:46.836979 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7399 12:11:46.837086
7400 12:11:46.839987 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7401 12:11:46.843122 [DutyScan_Calibration_Flow] ====Done====
7402 12:11:46.846974 nWR fixed to 30
7403 12:11:46.850231 [ModeRegInit_LP4] CH0 RK0
7404 12:11:46.850339 [ModeRegInit_LP4] CH0 RK1
7405 12:11:46.853580 [ModeRegInit_LP4] CH1 RK0
7406 12:11:46.856895 [ModeRegInit_LP4] CH1 RK1
7407 12:11:46.856998 match AC timing 5
7408 12:11:46.863385 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7409 12:11:46.866597 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7410 12:11:46.869948 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7411 12:11:46.876471 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7412 12:11:46.879688 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7413 12:11:46.882902 [MiockJmeterHQA]
7414 12:11:46.883021
7415 12:11:46.886156 [DramcMiockJmeter] u1RxGatingPI = 0
7416 12:11:46.886274 0 : 4365, 4138
7417 12:11:46.886374 4 : 4255, 4030
7418 12:11:46.889294 8 : 4367, 4137
7419 12:11:46.889409 12 : 4368, 4140
7420 12:11:46.892538 16 : 4255, 4027
7421 12:11:46.892637 20 : 4363, 4137
7422 12:11:46.896282 24 : 4252, 4027
7423 12:11:46.896360 28 : 4257, 4030
7424 12:11:46.896432 32 : 4255, 4027
7425 12:11:46.899589 36 : 4257, 4029
7426 12:11:46.899714 40 : 4365, 4140
7427 12:11:46.902784 44 : 4257, 4029
7428 12:11:46.902889 48 : 4365, 4140
7429 12:11:46.905884 52 : 4255, 4027
7430 12:11:46.905996 56 : 4258, 4029
7431 12:11:46.909064 60 : 4255, 4030
7432 12:11:46.909171 64 : 4365, 4137
7433 12:11:46.909281 68 : 4255, 4027
7434 12:11:46.912106 72 : 4257, 4029
7435 12:11:46.912227 76 : 4257, 4029
7436 12:11:46.915911 80 : 4252, 4027
7437 12:11:46.916022 84 : 4257, 4029
7438 12:11:46.919176 88 : 4253, 4027
7439 12:11:46.919278 92 : 4363, 4137
7440 12:11:46.922400 96 : 4257, 3223
7441 12:11:46.922506 100 : 4368, 0
7442 12:11:46.922599 104 : 4253, 0
7443 12:11:46.925518 108 : 4257, 0
7444 12:11:46.925617 112 : 4254, 0
7445 12:11:46.928566 116 : 4252, 0
7446 12:11:46.928669 120 : 4253, 0
7447 12:11:46.928763 124 : 4250, 0
7448 12:11:46.932197 128 : 4252, 0
7449 12:11:46.932271 132 : 4252, 0
7450 12:11:46.935335 136 : 4250, 0
7451 12:11:46.935537 140 : 4252, 0
7452 12:11:46.935647 144 : 4360, 0
7453 12:11:46.938880 148 : 4361, 0
7454 12:11:46.938990 152 : 4362, 0
7455 12:11:46.939086 156 : 4250, 0
7456 12:11:46.941919 160 : 4250, 0
7457 12:11:46.942025 164 : 4250, 0
7458 12:11:46.945771 168 : 4250, 0
7459 12:11:46.945879 172 : 4250, 0
7460 12:11:46.945974 176 : 4250, 0
7461 12:11:46.948279 180 : 4253, 0
7462 12:11:46.948388 184 : 4361, 0
7463 12:11:46.952012 188 : 4250, 0
7464 12:11:46.952129 192 : 4249, 0
7465 12:11:46.952248 196 : 4250, 0
7466 12:11:46.955224 200 : 4361, 0
7467 12:11:46.955337 204 : 4360, 0
7468 12:11:46.958383 208 : 4250, 0
7469 12:11:46.958506 212 : 4250, 0
7470 12:11:46.958613 216 : 4250, 0
7471 12:11:46.961641 220 : 4252, 596
7472 12:11:46.961765 224 : 4250, 3990
7473 12:11:46.964794 228 : 4250, 4026
7474 12:11:46.964908 232 : 4250, 4027
7475 12:11:46.968597 236 : 4250, 4027
7476 12:11:46.968707 240 : 4249, 4027
7477 12:11:46.971885 244 : 4250, 4026
7478 12:11:46.971997 248 : 4361, 4137
7479 12:11:46.975098 252 : 4250, 4027
7480 12:11:46.975204 256 : 4249, 4027
7481 12:11:46.978421 260 : 4360, 4137
7482 12:11:46.978528 264 : 4250, 4026
7483 12:11:46.978625 268 : 4252, 4027
7484 12:11:46.981597 272 : 4363, 4140
7485 12:11:46.981699 276 : 4249, 4027
7486 12:11:46.984873 280 : 4250, 4026
7487 12:11:46.984980 284 : 4250, 4027
7488 12:11:46.988028 288 : 4252, 4030
7489 12:11:46.988114 292 : 4249, 4027
7490 12:11:46.991263 296 : 4250, 4026
7491 12:11:46.991365 300 : 4361, 4137
7492 12:11:46.994530 304 : 4250, 4027
7493 12:11:46.994635 308 : 4249, 4027
7494 12:11:46.997771 312 : 4360, 4137
7495 12:11:46.997882 316 : 4250, 4026
7496 12:11:47.000994 320 : 4252, 4027
7497 12:11:47.001099 324 : 4363, 4140
7498 12:11:47.004860 328 : 4249, 4027
7499 12:11:47.004971 332 : 4250, 4023
7500 12:11:47.005074 336 : 4250, 2141
7501 12:11:47.007996 340 : 4252, 18
7502 12:11:47.008092
7503 12:11:47.011357 MIOCK jitter meter ch=0
7504 12:11:47.011477
7505 12:11:47.014466 1T = (340-100) = 240 dly cells
7506 12:11:47.017585 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7507 12:11:47.017698 ==
7508 12:11:47.020773 Dram Type= 6, Freq= 0, CH_0, rank 0
7509 12:11:47.027880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7510 12:11:47.027987 ==
7511 12:11:47.031021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7512 12:11:47.037238 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7513 12:11:47.041069 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7514 12:11:47.047761 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7515 12:11:47.055072 [CA 0] Center 43 (13~73) winsize 61
7516 12:11:47.058112 [CA 1] Center 42 (12~73) winsize 62
7517 12:11:47.062001 [CA 2] Center 37 (8~67) winsize 60
7518 12:11:47.065224 [CA 3] Center 37 (8~67) winsize 60
7519 12:11:47.068566 [CA 4] Center 36 (6~66) winsize 61
7520 12:11:47.071793 [CA 5] Center 35 (5~66) winsize 62
7521 12:11:47.071898
7522 12:11:47.075148 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7523 12:11:47.075281
7524 12:11:47.081439 [CATrainingPosCal] consider 1 rank data
7525 12:11:47.081566 u2DelayCellTimex100 = 271/100 ps
7526 12:11:47.087943 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7527 12:11:47.091156 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7528 12:11:47.094283 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7529 12:11:47.097498 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7530 12:11:47.100797 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7531 12:11:47.104642 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7532 12:11:47.104783
7533 12:11:47.107703 CA PerBit enable=1, Macro0, CA PI delay=35
7534 12:11:47.107873
7535 12:11:47.110863 [CBTSetCACLKResult] CA Dly = 35
7536 12:11:47.114084 CS Dly: 10 (0~41)
7537 12:11:47.117957 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7538 12:11:47.121011 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7539 12:11:47.121110 ==
7540 12:11:47.124155 Dram Type= 6, Freq= 0, CH_0, rank 1
7541 12:11:47.130732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 12:11:47.130846 ==
7543 12:11:47.134060 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7544 12:11:47.140804 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7545 12:11:47.143883 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7546 12:11:47.150671 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7547 12:11:47.158181 [CA 0] Center 43 (13~74) winsize 62
7548 12:11:47.162059 [CA 1] Center 43 (13~73) winsize 61
7549 12:11:47.165238 [CA 2] Center 38 (9~68) winsize 60
7550 12:11:47.168376 [CA 3] Center 38 (9~68) winsize 60
7551 12:11:47.171644 [CA 4] Center 37 (7~67) winsize 61
7552 12:11:47.174904 [CA 5] Center 36 (6~66) winsize 61
7553 12:11:47.174988
7554 12:11:47.178080 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7555 12:11:47.178192
7556 12:11:47.184566 [CATrainingPosCal] consider 2 rank data
7557 12:11:47.184652 u2DelayCellTimex100 = 271/100 ps
7558 12:11:47.191013 CA0 delay=43 (13~73),Diff = 7 PI (25 cell)
7559 12:11:47.194287 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7560 12:11:47.197533 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7561 12:11:47.200731 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7562 12:11:47.203946 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7563 12:11:47.207260 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7564 12:11:47.207362
7565 12:11:47.210962 CA PerBit enable=1, Macro0, CA PI delay=36
7566 12:11:47.211048
7567 12:11:47.214240 [CBTSetCACLKResult] CA Dly = 36
7568 12:11:47.217531 CS Dly: 11 (0~44)
7569 12:11:47.220724 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7570 12:11:47.223908 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7571 12:11:47.223993
7572 12:11:47.226910 ----->DramcWriteLeveling(PI) begin...
7573 12:11:47.230140 ==
7574 12:11:47.233563 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 12:11:47.236699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 12:11:47.236785 ==
7577 12:11:47.240582 Write leveling (Byte 0): 35 => 35
7578 12:11:47.243622 Write leveling (Byte 1): 26 => 26
7579 12:11:47.246898 DramcWriteLeveling(PI) end<-----
7580 12:11:47.246980
7581 12:11:47.247047 ==
7582 12:11:47.249915 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 12:11:47.253784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 12:11:47.253868 ==
7585 12:11:47.256853 [Gating] SW mode calibration
7586 12:11:47.263659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7587 12:11:47.270104 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7588 12:11:47.273374 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 12:11:47.276528 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 12:11:47.283022 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 12:11:47.286334 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7592 12:11:47.289592 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7593 12:11:47.296046 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7594 12:11:47.299429 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7595 12:11:47.302683 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 12:11:47.309145 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 12:11:47.312390 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 12:11:47.315619 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7599 12:11:47.322799 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7600 12:11:47.326026 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7601 12:11:47.329165 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7602 12:11:47.335443 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7603 12:11:47.338857 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:11:47.341953 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 12:11:47.348466 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 12:11:47.352147 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7607 12:11:47.355087 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7608 12:11:47.361968 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7609 12:11:47.364935 1 6 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7610 12:11:47.368270 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:11:47.375191 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:11:47.378416 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 12:11:47.381650 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 12:11:47.388246 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7615 12:11:47.391612 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7616 12:11:47.394934 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7617 12:11:47.401511 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7618 12:11:47.404660 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7619 12:11:47.407793 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:11:47.414276 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:11:47.417539 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:11:47.420893 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:11:47.427334 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:11:47.430696 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:11:47.437520 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:11:47.440814 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:11:47.444151 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:11:47.450385 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:11:47.453584 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:11:47.457342 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 12:11:47.463619 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 12:11:47.466675 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7633 12:11:47.470534 Total UI for P1: 0, mck2ui 16
7634 12:11:47.473761 best dqsien dly found for B0: ( 1, 9, 10)
7635 12:11:47.476607 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 12:11:47.479983 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 12:11:47.483323 Total UI for P1: 0, mck2ui 16
7638 12:11:47.486514 best dqsien dly found for B1: ( 1, 9, 20)
7639 12:11:47.493015 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7640 12:11:47.496842 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7641 12:11:47.496925
7642 12:11:47.499563 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7643 12:11:47.502926 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7644 12:11:47.506671 [Gating] SW calibration Done
7645 12:11:47.506822 ==
7646 12:11:47.509911 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 12:11:47.513111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 12:11:47.513187 ==
7649 12:11:47.516338 RX Vref Scan: 0
7650 12:11:47.516443
7651 12:11:47.516516 RX Vref 0 -> 0, step: 1
7652 12:11:47.516581
7653 12:11:47.519582 RX Delay 0 -> 252, step: 8
7654 12:11:47.522887 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7655 12:11:47.529028 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7656 12:11:47.532294 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7657 12:11:47.536102 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7658 12:11:47.539418 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7659 12:11:47.542557 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7660 12:11:47.548935 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7661 12:11:47.552727 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7662 12:11:47.555720 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7663 12:11:47.558902 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7664 12:11:47.562554 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7665 12:11:47.568764 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7666 12:11:47.572475 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7667 12:11:47.575052 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7668 12:11:47.578766 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7669 12:11:47.585073 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7670 12:11:47.585196 ==
7671 12:11:47.588917 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 12:11:47.591558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 12:11:47.591662 ==
7674 12:11:47.591760 DQS Delay:
7675 12:11:47.594948 DQS0 = 0, DQS1 = 0
7676 12:11:47.595050 DQM Delay:
7677 12:11:47.598782 DQM0 = 131, DQM1 = 127
7678 12:11:47.598893 DQ Delay:
7679 12:11:47.602094 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7680 12:11:47.605098 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7681 12:11:47.608450 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7682 12:11:47.614892 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =135
7683 12:11:47.615001
7684 12:11:47.615098
7685 12:11:47.615165 ==
7686 12:11:47.618192 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 12:11:47.621386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 12:11:47.621491 ==
7689 12:11:47.621591
7690 12:11:47.621684
7691 12:11:47.624776 TX Vref Scan disable
7692 12:11:47.624877 == TX Byte 0 ==
7693 12:11:47.631064 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7694 12:11:47.634379 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7695 12:11:47.634469 == TX Byte 1 ==
7696 12:11:47.640889 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7697 12:11:47.644116 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7698 12:11:47.644206 ==
7699 12:11:47.647990 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 12:11:47.650634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 12:11:47.650710 ==
7702 12:11:47.665583
7703 12:11:47.669333 TX Vref early break, caculate TX vref
7704 12:11:47.672508 TX Vref=16, minBit 3, minWin=21, winSum=365
7705 12:11:47.675442 TX Vref=18, minBit 7, minWin=21, winSum=375
7706 12:11:47.679153 TX Vref=20, minBit 1, minWin=22, winSum=377
7707 12:11:47.682395 TX Vref=22, minBit 0, minWin=23, winSum=388
7708 12:11:47.685576 TX Vref=24, minBit 1, minWin=23, winSum=400
7709 12:11:47.692172 TX Vref=26, minBit 1, minWin=23, winSum=405
7710 12:11:47.695452 TX Vref=28, minBit 0, minWin=24, winSum=411
7711 12:11:47.698616 TX Vref=30, minBit 0, minWin=24, winSum=407
7712 12:11:47.701965 TX Vref=32, minBit 7, minWin=23, winSum=403
7713 12:11:47.705255 TX Vref=34, minBit 4, minWin=21, winSum=384
7714 12:11:47.711639 [TxChooseVref] Worse bit 0, Min win 24, Win sum 411, Final Vref 28
7715 12:11:47.711753
7716 12:11:47.715326 Final TX Range 0 Vref 28
7717 12:11:47.715412
7718 12:11:47.715476 ==
7719 12:11:47.718559 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 12:11:47.721751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 12:11:47.721858 ==
7722 12:11:47.721949
7723 12:11:47.722043
7724 12:11:47.724982 TX Vref Scan disable
7725 12:11:47.731673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7726 12:11:47.731756 == TX Byte 0 ==
7727 12:11:47.734772 u2DelayCellOfst[0]=14 cells (4 PI)
7728 12:11:47.738015 u2DelayCellOfst[1]=14 cells (4 PI)
7729 12:11:47.741254 u2DelayCellOfst[2]=10 cells (3 PI)
7730 12:11:47.744557 u2DelayCellOfst[3]=10 cells (3 PI)
7731 12:11:47.747694 u2DelayCellOfst[4]=10 cells (3 PI)
7732 12:11:47.751532 u2DelayCellOfst[5]=0 cells (0 PI)
7733 12:11:47.754944 u2DelayCellOfst[6]=18 cells (5 PI)
7734 12:11:47.758149 u2DelayCellOfst[7]=18 cells (5 PI)
7735 12:11:47.761212 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7736 12:11:47.764255 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7737 12:11:47.767783 == TX Byte 1 ==
7738 12:11:47.770960 u2DelayCellOfst[8]=0 cells (0 PI)
7739 12:11:47.774568 u2DelayCellOfst[9]=0 cells (0 PI)
7740 12:11:47.777744 u2DelayCellOfst[10]=7 cells (2 PI)
7741 12:11:47.780838 u2DelayCellOfst[11]=0 cells (0 PI)
7742 12:11:47.783840 u2DelayCellOfst[12]=10 cells (3 PI)
7743 12:11:47.787581 u2DelayCellOfst[13]=10 cells (3 PI)
7744 12:11:47.790668 u2DelayCellOfst[14]=14 cells (4 PI)
7745 12:11:47.793774 u2DelayCellOfst[15]=10 cells (3 PI)
7746 12:11:47.796950 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7747 12:11:47.800261 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7748 12:11:47.803561 DramC Write-DBI on
7749 12:11:47.803639 ==
7750 12:11:47.806958 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 12:11:47.810709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 12:11:47.810785 ==
7753 12:11:47.810864
7754 12:11:47.810934
7755 12:11:47.814036 TX Vref Scan disable
7756 12:11:47.817333 == TX Byte 0 ==
7757 12:11:47.820644 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7758 12:11:47.820737 == TX Byte 1 ==
7759 12:11:47.826981 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7760 12:11:47.827084 DramC Write-DBI off
7761 12:11:47.827160
7762 12:11:47.827224 [DATLAT]
7763 12:11:47.830123 Freq=1600, CH0 RK0
7764 12:11:47.830230
7765 12:11:47.833340 DATLAT Default: 0xf
7766 12:11:47.833448 0, 0xFFFF, sum = 0
7767 12:11:47.836613 1, 0xFFFF, sum = 0
7768 12:11:47.836693 2, 0xFFFF, sum = 0
7769 12:11:47.839741 3, 0xFFFF, sum = 0
7770 12:11:47.839832 4, 0xFFFF, sum = 0
7771 12:11:47.843542 5, 0xFFFF, sum = 0
7772 12:11:47.843628 6, 0xFFFF, sum = 0
7773 12:11:47.846929 7, 0xFFFF, sum = 0
7774 12:11:47.847030 8, 0xFFFF, sum = 0
7775 12:11:47.850142 9, 0xFFFF, sum = 0
7776 12:11:47.850226 10, 0xFFFF, sum = 0
7777 12:11:47.853330 11, 0xFFFF, sum = 0
7778 12:11:47.853429 12, 0xFFFF, sum = 0
7779 12:11:47.856552 13, 0xFFFF, sum = 0
7780 12:11:47.856637 14, 0x0, sum = 1
7781 12:11:47.859850 15, 0x0, sum = 2
7782 12:11:47.859978 16, 0x0, sum = 3
7783 12:11:47.863036 17, 0x0, sum = 4
7784 12:11:47.863164 best_step = 15
7785 12:11:47.863231
7786 12:11:47.863293 ==
7787 12:11:47.866533 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 12:11:47.872980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 12:11:47.873064 ==
7790 12:11:47.873131 RX Vref Scan: 1
7791 12:11:47.873192
7792 12:11:47.876283 Set Vref Range= 24 -> 127
7793 12:11:47.876382
7794 12:11:47.879808 RX Vref 24 -> 127, step: 1
7795 12:11:47.879893
7796 12:11:47.882937 RX Delay 11 -> 252, step: 4
7797 12:11:47.883023
7798 12:11:47.886092 Set Vref, RX VrefLevel [Byte0]: 24
7799 12:11:47.889649 [Byte1]: 24
7800 12:11:47.889731
7801 12:11:47.892603 Set Vref, RX VrefLevel [Byte0]: 25
7802 12:11:47.895758 [Byte1]: 25
7803 12:11:47.895843
7804 12:11:47.899046 Set Vref, RX VrefLevel [Byte0]: 26
7805 12:11:47.902298 [Byte1]: 26
7806 12:11:47.906255
7807 12:11:47.906338 Set Vref, RX VrefLevel [Byte0]: 27
7808 12:11:47.908969 [Byte1]: 27
7809 12:11:47.913589
7810 12:11:47.913675 Set Vref, RX VrefLevel [Byte0]: 28
7811 12:11:47.916841 [Byte1]: 28
7812 12:11:47.921312
7813 12:11:47.921395 Set Vref, RX VrefLevel [Byte0]: 29
7814 12:11:47.924592 [Byte1]: 29
7815 12:11:47.928569
7816 12:11:47.928652 Set Vref, RX VrefLevel [Byte0]: 30
7817 12:11:47.931841 [Byte1]: 30
7818 12:11:47.936238
7819 12:11:47.936321 Set Vref, RX VrefLevel [Byte0]: 31
7820 12:11:47.939394 [Byte1]: 31
7821 12:11:47.943846
7822 12:11:47.943931 Set Vref, RX VrefLevel [Byte0]: 32
7823 12:11:47.947112 [Byte1]: 32
7824 12:11:47.951581
7825 12:11:47.951681 Set Vref, RX VrefLevel [Byte0]: 33
7826 12:11:47.954937 [Byte1]: 33
7827 12:11:47.959175
7828 12:11:47.959308 Set Vref, RX VrefLevel [Byte0]: 34
7829 12:11:47.962536 [Byte1]: 34
7830 12:11:47.966960
7831 12:11:47.967044 Set Vref, RX VrefLevel [Byte0]: 35
7832 12:11:47.970063 [Byte1]: 35
7833 12:11:47.974362
7834 12:11:47.974446 Set Vref, RX VrefLevel [Byte0]: 36
7835 12:11:47.978002 [Byte1]: 36
7836 12:11:47.981815
7837 12:11:47.981898 Set Vref, RX VrefLevel [Byte0]: 37
7838 12:11:47.985504 [Byte1]: 37
7839 12:11:47.990062
7840 12:11:47.990191 Set Vref, RX VrefLevel [Byte0]: 38
7841 12:11:47.992962 [Byte1]: 38
7842 12:11:47.997204
7843 12:11:47.997294 Set Vref, RX VrefLevel [Byte0]: 39
7844 12:11:48.000435 [Byte1]: 39
7845 12:11:48.004795
7846 12:11:48.004870 Set Vref, RX VrefLevel [Byte0]: 40
7847 12:11:48.008177 [Byte1]: 40
7848 12:11:48.012754
7849 12:11:48.012837 Set Vref, RX VrefLevel [Byte0]: 41
7850 12:11:48.015905 [Byte1]: 41
7851 12:11:48.020727
7852 12:11:48.020810 Set Vref, RX VrefLevel [Byte0]: 42
7853 12:11:48.023394 [Byte1]: 42
7854 12:11:48.027824
7855 12:11:48.027907 Set Vref, RX VrefLevel [Byte0]: 43
7856 12:11:48.031200 [Byte1]: 43
7857 12:11:48.035107
7858 12:11:48.035191 Set Vref, RX VrefLevel [Byte0]: 44
7859 12:11:48.038306 [Byte1]: 44
7860 12:11:48.043050
7861 12:11:48.043134 Set Vref, RX VrefLevel [Byte0]: 45
7862 12:11:48.046180 [Byte1]: 45
7863 12:11:48.050809
7864 12:11:48.050892 Set Vref, RX VrefLevel [Byte0]: 46
7865 12:11:48.054105 [Byte1]: 46
7866 12:11:48.057873
7867 12:11:48.057956 Set Vref, RX VrefLevel [Byte0]: 47
7868 12:11:48.061161 [Byte1]: 47
7869 12:11:48.065597
7870 12:11:48.065740 Set Vref, RX VrefLevel [Byte0]: 48
7871 12:11:48.068963 [Byte1]: 48
7872 12:11:48.073190
7873 12:11:48.073303 Set Vref, RX VrefLevel [Byte0]: 49
7874 12:11:48.076494 [Byte1]: 49
7875 12:11:48.080833
7876 12:11:48.080934 Set Vref, RX VrefLevel [Byte0]: 50
7877 12:11:48.083958 [Byte1]: 50
7878 12:11:48.088476
7879 12:11:48.088580 Set Vref, RX VrefLevel [Byte0]: 51
7880 12:11:48.091719 [Byte1]: 51
7881 12:11:48.096188
7882 12:11:48.096316 Set Vref, RX VrefLevel [Byte0]: 52
7883 12:11:48.099244 [Byte1]: 52
7884 12:11:48.103673
7885 12:11:48.103780 Set Vref, RX VrefLevel [Byte0]: 53
7886 12:11:48.106854 [Byte1]: 53
7887 12:11:48.111267
7888 12:11:48.111386 Set Vref, RX VrefLevel [Byte0]: 54
7889 12:11:48.114470 [Byte1]: 54
7890 12:11:48.118967
7891 12:11:48.119101 Set Vref, RX VrefLevel [Byte0]: 55
7892 12:11:48.122124 [Byte1]: 55
7893 12:11:48.126849
7894 12:11:48.127003 Set Vref, RX VrefLevel [Byte0]: 56
7895 12:11:48.129959 [Byte1]: 56
7896 12:11:48.134513
7897 12:11:48.134615 Set Vref, RX VrefLevel [Byte0]: 57
7898 12:11:48.137563 [Byte1]: 57
7899 12:11:48.142119
7900 12:11:48.142223 Set Vref, RX VrefLevel [Byte0]: 58
7901 12:11:48.144824 [Byte1]: 58
7902 12:11:48.149225
7903 12:11:48.149327 Set Vref, RX VrefLevel [Byte0]: 59
7904 12:11:48.152574 [Byte1]: 59
7905 12:11:48.157244
7906 12:11:48.157347 Set Vref, RX VrefLevel [Byte0]: 60
7907 12:11:48.160389 [Byte1]: 60
7908 12:11:48.165019
7909 12:11:48.165118 Set Vref, RX VrefLevel [Byte0]: 61
7910 12:11:48.168124 [Byte1]: 61
7911 12:11:48.172133
7912 12:11:48.172235 Set Vref, RX VrefLevel [Byte0]: 62
7913 12:11:48.175980 [Byte1]: 62
7914 12:11:48.179631
7915 12:11:48.179734 Set Vref, RX VrefLevel [Byte0]: 63
7916 12:11:48.183461 [Byte1]: 63
7917 12:11:48.187251
7918 12:11:48.187377 Set Vref, RX VrefLevel [Byte0]: 64
7919 12:11:48.191012 [Byte1]: 64
7920 12:11:48.195552
7921 12:11:48.195663 Set Vref, RX VrefLevel [Byte0]: 65
7922 12:11:48.198568 [Byte1]: 65
7923 12:11:48.202861
7924 12:11:48.202945 Set Vref, RX VrefLevel [Byte0]: 66
7925 12:11:48.206092 [Byte1]: 66
7926 12:11:48.210427
7927 12:11:48.210537 Set Vref, RX VrefLevel [Byte0]: 67
7928 12:11:48.213629 [Byte1]: 67
7929 12:11:48.218113
7930 12:11:48.218219 Set Vref, RX VrefLevel [Byte0]: 68
7931 12:11:48.221360 [Byte1]: 68
7932 12:11:48.225967
7933 12:11:48.226051 Set Vref, RX VrefLevel [Byte0]: 69
7934 12:11:48.229319 [Byte1]: 69
7935 12:11:48.233043
7936 12:11:48.236227 Set Vref, RX VrefLevel [Byte0]: 70
7937 12:11:48.239513 [Byte1]: 70
7938 12:11:48.239600
7939 12:11:48.242684 Set Vref, RX VrefLevel [Byte0]: 71
7940 12:11:48.246499 [Byte1]: 71
7941 12:11:48.246596
7942 12:11:48.249743 Set Vref, RX VrefLevel [Byte0]: 72
7943 12:11:48.252908 [Byte1]: 72
7944 12:11:48.256201
7945 12:11:48.256286 Set Vref, RX VrefLevel [Byte0]: 73
7946 12:11:48.259462 [Byte1]: 73
7947 12:11:48.264043
7948 12:11:48.264141 Set Vref, RX VrefLevel [Byte0]: 74
7949 12:11:48.266691 [Byte1]: 74
7950 12:11:48.271157
7951 12:11:48.271241 Set Vref, RX VrefLevel [Byte0]: 75
7952 12:11:48.274321 [Byte1]: 75
7953 12:11:48.278894
7954 12:11:48.278977 Set Vref, RX VrefLevel [Byte0]: 76
7955 12:11:48.282141 [Byte1]: 76
7956 12:11:48.286514
7957 12:11:48.286614 Set Vref, RX VrefLevel [Byte0]: 77
7958 12:11:48.289813 [Byte1]: 77
7959 12:11:48.294081
7960 12:11:48.294165 Set Vref, RX VrefLevel [Byte0]: 78
7961 12:11:48.297316 [Byte1]: 78
7962 12:11:48.301750
7963 12:11:48.301866 Final RX Vref Byte 0 = 53 to rank0
7964 12:11:48.304802 Final RX Vref Byte 1 = 56 to rank0
7965 12:11:48.308468 Final RX Vref Byte 0 = 53 to rank1
7966 12:11:48.311566 Final RX Vref Byte 1 = 56 to rank1==
7967 12:11:48.314646 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 12:11:48.321052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 12:11:48.321209 ==
7970 12:11:48.321340 DQS Delay:
7971 12:11:48.324331 DQS0 = 0, DQS1 = 0
7972 12:11:48.324434 DQM Delay:
7973 12:11:48.328155 DQM0 = 129, DQM1 = 124
7974 12:11:48.328247 DQ Delay:
7975 12:11:48.331567 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =126
7976 12:11:48.334714 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
7977 12:11:48.337922 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7978 12:11:48.341233 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7979 12:11:48.341335
7980 12:11:48.341419
7981 12:11:48.341533
7982 12:11:48.344437 [DramC_TX_OE_Calibration] TA2
7983 12:11:48.347820 Original DQ_B0 (3 6) =30, OEN = 27
7984 12:11:48.351091 Original DQ_B1 (3 6) =30, OEN = 27
7985 12:11:48.354280 24, 0x0, End_B0=24 End_B1=24
7986 12:11:48.357496 25, 0x0, End_B0=25 End_B1=25
7987 12:11:48.357581 26, 0x0, End_B0=26 End_B1=26
7988 12:11:48.360776 27, 0x0, End_B0=27 End_B1=27
7989 12:11:48.364682 28, 0x0, End_B0=28 End_B1=28
7990 12:11:48.367885 29, 0x0, End_B0=29 End_B1=29
7991 12:11:48.367965 30, 0x0, End_B0=30 End_B1=30
7992 12:11:48.371247 31, 0x5151, End_B0=30 End_B1=30
7993 12:11:48.374374 Byte0 end_step=30 best_step=27
7994 12:11:48.377603 Byte1 end_step=30 best_step=27
7995 12:11:48.380953 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 12:11:48.384124 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 12:11:48.384213
7998 12:11:48.384279
7999 12:11:48.390598 [DQSOSCAuto] RK0, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8000 12:11:48.393864 CH0 RK0: MR19=303, MR18=1412
8001 12:11:48.400615 CH0_RK0: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8002 12:11:48.400703
8003 12:11:48.403745 ----->DramcWriteLeveling(PI) begin...
8004 12:11:48.403831 ==
8005 12:11:48.406915 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 12:11:48.410615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 12:11:48.410701 ==
8008 12:11:48.413742 Write leveling (Byte 0): 37 => 37
8009 12:11:48.416780 Write leveling (Byte 1): 28 => 28
8010 12:11:48.420390 DramcWriteLeveling(PI) end<-----
8011 12:11:48.420475
8012 12:11:48.420543 ==
8013 12:11:48.423645 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 12:11:48.430042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 12:11:48.430129 ==
8016 12:11:48.430209 [Gating] SW mode calibration
8017 12:11:48.439931 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 12:11:48.443834 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 12:11:48.447017 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:11:48.453467 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 12:11:48.456796 1 4 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8022 12:11:48.460108 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8023 12:11:48.466636 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
8024 12:11:48.469878 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 12:11:48.473170 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 12:11:48.479959 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 12:11:48.483306 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 12:11:48.486620 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 12:11:48.493068 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8030 12:11:48.496140 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8031 12:11:48.499406 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8032 12:11:48.506119 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8033 12:11:48.509150 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:11:48.515567 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 12:11:48.519172 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 12:11:48.522314 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8037 12:11:48.525590 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8038 12:11:48.532520 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8039 12:11:48.535889 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8040 12:11:48.538964 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:11:48.545552 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 12:11:48.548714 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:11:48.555156 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 12:11:48.558430 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 12:11:48.561813 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 12:11:48.568406 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 12:11:48.571853 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8048 12:11:48.575156 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 12:11:48.581297 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 12:11:48.585146 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:11:48.588264 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:11:48.594869 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:11:48.597869 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:11:48.601521 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:11:48.607868 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:11:48.611005 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:11:48.614655 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:11:48.620869 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:11:48.624548 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:11:48.627587 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:11:48.633855 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 12:11:48.637199 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8063 12:11:48.640592 Total UI for P1: 0, mck2ui 16
8064 12:11:48.643700 best dqsien dly found for B0: ( 1, 9, 8)
8065 12:11:48.647575 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8066 12:11:48.654078 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 12:11:48.657170 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 12:11:48.660443 Total UI for P1: 0, mck2ui 16
8069 12:11:48.663698 best dqsien dly found for B1: ( 1, 9, 20)
8070 12:11:48.667047 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8071 12:11:48.670388 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8072 12:11:48.670473
8073 12:11:48.673679 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8074 12:11:48.676884 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8075 12:11:48.680268 [Gating] SW calibration Done
8076 12:11:48.680352 ==
8077 12:11:48.683327 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 12:11:48.689844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 12:11:48.689929 ==
8080 12:11:48.690017 RX Vref Scan: 0
8081 12:11:48.690108
8082 12:11:48.693106 RX Vref 0 -> 0, step: 1
8083 12:11:48.693190
8084 12:11:48.696355 RX Delay 0 -> 252, step: 8
8085 12:11:48.699637 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8086 12:11:48.703313 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8087 12:11:48.706352 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8088 12:11:48.709380 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8089 12:11:48.716268 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8090 12:11:48.719337 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8091 12:11:48.722549 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8092 12:11:48.726236 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8093 12:11:48.729277 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8094 12:11:48.736088 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8095 12:11:48.739188 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8096 12:11:48.742259 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8097 12:11:48.745528 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8098 12:11:48.752682 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8099 12:11:48.755551 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8100 12:11:48.758885 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8101 12:11:48.758962 ==
8102 12:11:48.762659 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 12:11:48.765928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 12:11:48.766012 ==
8105 12:11:48.769164 DQS Delay:
8106 12:11:48.769247 DQS0 = 0, DQS1 = 0
8107 12:11:48.772314 DQM Delay:
8108 12:11:48.772397 DQM0 = 132, DQM1 = 125
8109 12:11:48.775633 DQ Delay:
8110 12:11:48.778832 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8111 12:11:48.782055 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8112 12:11:48.785423 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8113 12:11:48.788606 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8114 12:11:48.788689
8115 12:11:48.788755
8116 12:11:48.788851 ==
8117 12:11:48.791829 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 12:11:48.794920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 12:11:48.795022 ==
8120 12:11:48.795117
8121 12:11:48.798818
8122 12:11:48.798909 TX Vref Scan disable
8123 12:11:48.802038 == TX Byte 0 ==
8124 12:11:48.804705 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8125 12:11:48.808486 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8126 12:11:48.811627 == TX Byte 1 ==
8127 12:11:48.815237 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8128 12:11:48.818364 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8129 12:11:48.818498 ==
8130 12:11:48.821597 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:11:48.828251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:11:48.828370 ==
8133 12:11:48.842722
8134 12:11:48.845798 TX Vref early break, caculate TX vref
8135 12:11:48.849086 TX Vref=16, minBit 0, minWin=23, winSum=384
8136 12:11:48.852269 TX Vref=18, minBit 3, minWin=23, winSum=387
8137 12:11:48.855611 TX Vref=20, minBit 7, minWin=24, winSum=399
8138 12:11:48.858736 TX Vref=22, minBit 0, minWin=25, winSum=410
8139 12:11:48.861856 TX Vref=24, minBit 1, minWin=25, winSum=416
8140 12:11:48.868546 TX Vref=26, minBit 3, minWin=25, winSum=419
8141 12:11:48.871690 TX Vref=28, minBit 4, minWin=25, winSum=418
8142 12:11:48.874892 TX Vref=30, minBit 1, minWin=25, winSum=417
8143 12:11:48.878271 TX Vref=32, minBit 1, minWin=24, winSum=405
8144 12:11:48.881550 TX Vref=34, minBit 0, minWin=24, winSum=402
8145 12:11:48.888099 TX Vref=36, minBit 0, minWin=23, winSum=390
8146 12:11:48.891460 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 26
8147 12:11:48.891533
8148 12:11:48.894747 Final TX Range 0 Vref 26
8149 12:11:48.894831
8150 12:11:48.894904 ==
8151 12:11:48.898012 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 12:11:48.901246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 12:11:48.904639 ==
8154 12:11:48.904714
8155 12:11:48.904778
8156 12:11:48.904838 TX Vref Scan disable
8157 12:11:48.911572 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8158 12:11:48.911651 == TX Byte 0 ==
8159 12:11:48.914653 u2DelayCellOfst[0]=14 cells (4 PI)
8160 12:11:48.917869 u2DelayCellOfst[1]=18 cells (5 PI)
8161 12:11:48.921477 u2DelayCellOfst[2]=10 cells (3 PI)
8162 12:11:48.924816 u2DelayCellOfst[3]=14 cells (4 PI)
8163 12:11:48.927874 u2DelayCellOfst[4]=10 cells (3 PI)
8164 12:11:48.931047 u2DelayCellOfst[5]=0 cells (0 PI)
8165 12:11:48.934709 u2DelayCellOfst[6]=18 cells (5 PI)
8166 12:11:48.937797 u2DelayCellOfst[7]=18 cells (5 PI)
8167 12:11:48.940951 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8168 12:11:48.947719 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8169 12:11:48.947808 == TX Byte 1 ==
8170 12:11:48.950730 u2DelayCellOfst[8]=3 cells (1 PI)
8171 12:11:48.953869 u2DelayCellOfst[9]=0 cells (0 PI)
8172 12:11:48.957194 u2DelayCellOfst[10]=7 cells (2 PI)
8173 12:11:48.961051 u2DelayCellOfst[11]=7 cells (2 PI)
8174 12:11:48.964164 u2DelayCellOfst[12]=14 cells (4 PI)
8175 12:11:48.967476 u2DelayCellOfst[13]=14 cells (4 PI)
8176 12:11:48.970786 u2DelayCellOfst[14]=18 cells (5 PI)
8177 12:11:48.974026 u2DelayCellOfst[15]=14 cells (4 PI)
8178 12:11:48.977221 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8179 12:11:48.980493 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8180 12:11:48.983851 DramC Write-DBI on
8181 12:11:48.983946 ==
8182 12:11:48.987250 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 12:11:48.990427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 12:11:48.990516 ==
8185 12:11:48.990583
8186 12:11:48.990646
8187 12:11:48.993767 TX Vref Scan disable
8188 12:11:48.996976 == TX Byte 0 ==
8189 12:11:49.000316 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8190 12:11:49.000397 == TX Byte 1 ==
8191 12:11:49.006787 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8192 12:11:49.006872 DramC Write-DBI off
8193 12:11:49.006939
8194 12:11:49.010109 [DATLAT]
8195 12:11:49.010184 Freq=1600, CH0 RK1
8196 12:11:49.010248
8197 12:11:49.013303 DATLAT Default: 0xf
8198 12:11:49.013374 0, 0xFFFF, sum = 0
8199 12:11:49.016557 1, 0xFFFF, sum = 0
8200 12:11:49.016644 2, 0xFFFF, sum = 0
8201 12:11:49.019737 3, 0xFFFF, sum = 0
8202 12:11:49.019841 4, 0xFFFF, sum = 0
8203 12:11:49.023308 5, 0xFFFF, sum = 0
8204 12:11:49.023393 6, 0xFFFF, sum = 0
8205 12:11:49.026340 7, 0xFFFF, sum = 0
8206 12:11:49.026444 8, 0xFFFF, sum = 0
8207 12:11:49.029558 9, 0xFFFF, sum = 0
8208 12:11:49.029659 10, 0xFFFF, sum = 0
8209 12:11:49.033141 11, 0xFFFF, sum = 0
8210 12:11:49.036331 12, 0xFFFF, sum = 0
8211 12:11:49.036406 13, 0xFFFF, sum = 0
8212 12:11:49.039955 14, 0x0, sum = 1
8213 12:11:49.040040 15, 0x0, sum = 2
8214 12:11:49.040119 16, 0x0, sum = 3
8215 12:11:49.043033 17, 0x0, sum = 4
8216 12:11:49.043119 best_step = 15
8217 12:11:49.043190
8218 12:11:49.046083 ==
8219 12:11:49.049543 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 12:11:49.052703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 12:11:49.052807 ==
8222 12:11:49.052908 RX Vref Scan: 0
8223 12:11:49.052973
8224 12:11:49.056405 RX Vref 0 -> 0, step: 1
8225 12:11:49.056482
8226 12:11:49.059611 RX Delay 11 -> 252, step: 4
8227 12:11:49.062520 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8228 12:11:49.065711 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8229 12:11:49.072272 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8230 12:11:49.075560 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8231 12:11:49.078794 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8232 12:11:49.082638 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8233 12:11:49.085925 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8234 12:11:49.092203 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8235 12:11:49.095656 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8236 12:11:49.098933 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8237 12:11:49.102179 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8238 12:11:49.108628 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8239 12:11:49.111956 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8240 12:11:49.115077 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8241 12:11:49.118332 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8242 12:11:49.121594 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8243 12:11:49.125365 ==
8244 12:11:49.128320 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 12:11:49.131974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 12:11:49.132080 ==
8247 12:11:49.132153 DQS Delay:
8248 12:11:49.135124 DQS0 = 0, DQS1 = 0
8249 12:11:49.135201 DQM Delay:
8250 12:11:49.138134 DQM0 = 128, DQM1 = 124
8251 12:11:49.138237 DQ Delay:
8252 12:11:49.141764 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8253 12:11:49.145039 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8254 12:11:49.147954 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =120
8255 12:11:49.151761 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130
8256 12:11:49.151882
8257 12:11:49.151992
8258 12:11:49.152114
8259 12:11:49.154960 [DramC_TX_OE_Calibration] TA2
8260 12:11:49.158023 Original DQ_B0 (3 6) =30, OEN = 27
8261 12:11:49.161118 Original DQ_B1 (3 6) =30, OEN = 27
8262 12:11:49.164743 24, 0x0, End_B0=24 End_B1=24
8263 12:11:49.167956 25, 0x0, End_B0=25 End_B1=25
8264 12:11:49.171236 26, 0x0, End_B0=26 End_B1=26
8265 12:11:49.171342 27, 0x0, End_B0=27 End_B1=27
8266 12:11:49.174541 28, 0x0, End_B0=28 End_B1=28
8267 12:11:49.177867 29, 0x0, End_B0=29 End_B1=29
8268 12:11:49.181177 30, 0x0, End_B0=30 End_B1=30
8269 12:11:49.184400 31, 0x4141, End_B0=30 End_B1=30
8270 12:11:49.184520 Byte0 end_step=30 best_step=27
8271 12:11:49.187777 Byte1 end_step=30 best_step=27
8272 12:11:49.190930 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 12:11:49.194156 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 12:11:49.194260
8275 12:11:49.194368
8276 12:11:49.204133 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
8277 12:11:49.204251 CH0 RK1: MR19=303, MR18=1411
8278 12:11:49.211018 CH0_RK1: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
8279 12:11:49.214216 [RxdqsGatingPostProcess] freq 1600
8280 12:11:49.220725 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 12:11:49.223929 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 12:11:49.227245 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 12:11:49.230568 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 12:11:49.230679 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 12:11:49.233580 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 12:11:49.237230 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 12:11:49.240372 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 12:11:49.243536 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 12:11:49.247155 Pre-setting of DQS Precalculation
8290 12:11:49.253562 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 12:11:49.253670 ==
8292 12:11:49.257133 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 12:11:49.260180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 12:11:49.260289 ==
8295 12:11:49.266530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 12:11:49.270237 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 12:11:49.273439 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 12:11:49.279895 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 12:11:49.288514 [CA 0] Center 42 (13~72) winsize 60
8300 12:11:49.291874 [CA 1] Center 42 (12~72) winsize 61
8301 12:11:49.295143 [CA 2] Center 38 (9~68) winsize 60
8302 12:11:49.298334 [CA 3] Center 37 (8~67) winsize 60
8303 12:11:49.301765 [CA 4] Center 38 (9~68) winsize 60
8304 12:11:49.305012 [CA 5] Center 37 (7~67) winsize 61
8305 12:11:49.305120
8306 12:11:49.308319 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 12:11:49.308427
8308 12:11:49.314738 [CATrainingPosCal] consider 1 rank data
8309 12:11:49.314865 u2DelayCellTimex100 = 271/100 ps
8310 12:11:49.321674 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8311 12:11:49.324975 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8312 12:11:49.328124 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8313 12:11:49.331400 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8314 12:11:49.334635 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8315 12:11:49.337836 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8316 12:11:49.337947
8317 12:11:49.341487 CA PerBit enable=1, Macro0, CA PI delay=37
8318 12:11:49.341616
8319 12:11:49.344759 [CBTSetCACLKResult] CA Dly = 37
8320 12:11:49.347844 CS Dly: 7 (0~38)
8321 12:11:49.351000 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 12:11:49.354236 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 12:11:49.354339 ==
8324 12:11:49.358011 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 12:11:49.364529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 12:11:49.364606 ==
8327 12:11:49.367522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 12:11:49.374409 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 12:11:49.377633 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 12:11:49.384024 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 12:11:49.392081 [CA 0] Center 42 (12~72) winsize 61
8332 12:11:49.395343 [CA 1] Center 43 (14~72) winsize 59
8333 12:11:49.398540 [CA 2] Center 38 (9~68) winsize 60
8334 12:11:49.401868 [CA 3] Center 36 (7~66) winsize 60
8335 12:11:49.405202 [CA 4] Center 38 (8~68) winsize 61
8336 12:11:49.408411 [CA 5] Center 37 (7~67) winsize 61
8337 12:11:49.408494
8338 12:11:49.411586 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8339 12:11:49.411669
8340 12:11:49.418132 [CATrainingPosCal] consider 2 rank data
8341 12:11:49.418216 u2DelayCellTimex100 = 271/100 ps
8342 12:11:49.424582 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8343 12:11:49.427735 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8344 12:11:49.431010 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8345 12:11:49.434822 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8346 12:11:49.438123 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8347 12:11:49.441247 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8348 12:11:49.441343
8349 12:11:49.444312 CA PerBit enable=1, Macro0, CA PI delay=37
8350 12:11:49.444394
8351 12:11:49.447894 [CBTSetCACLKResult] CA Dly = 37
8352 12:11:49.451195 CS Dly: 9 (0~42)
8353 12:11:49.454273 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 12:11:49.457289 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 12:11:49.457370
8356 12:11:49.461175 ----->DramcWriteLeveling(PI) begin...
8357 12:11:49.461258 ==
8358 12:11:49.464437 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 12:11:49.470648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 12:11:49.470729 ==
8361 12:11:49.474090 Write leveling (Byte 0): 25 => 25
8362 12:11:49.477211 Write leveling (Byte 1): 27 => 27
8363 12:11:49.480400 DramcWriteLeveling(PI) end<-----
8364 12:11:49.480481
8365 12:11:49.480545 ==
8366 12:11:49.483619 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 12:11:49.486853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 12:11:49.486940 ==
8369 12:11:49.490686 [Gating] SW mode calibration
8370 12:11:49.497380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 12:11:49.503808 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 12:11:49.507160 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:11:49.509812 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:11:49.516844 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8375 12:11:49.520185 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8376 12:11:49.523379 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8377 12:11:49.529728 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:11:49.532896 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:11:49.536165 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:11:49.543305 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:11:49.546412 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 12:11:49.549478 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8383 12:11:49.556256 1 5 12 | B1->B0 | 3333 2626 | 0 0 | (0 0) (1 0)
8384 12:11:49.559191 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8385 12:11:49.563014 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:11:49.569387 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:11:49.572673 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:11:49.576283 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:11:49.582459 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 12:11:49.585753 1 6 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8391 12:11:49.589004 1 6 12 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
8392 12:11:49.595549 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:11:49.598808 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:11:49.601997 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:11:49.608735 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:11:49.611860 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:11:49.615218 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:11:49.621623 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:11:49.624947 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 12:11:49.628270 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 12:11:49.635032 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:11:49.638259 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:11:49.641487 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:11:49.648179 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:11:49.651409 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:11:49.654485 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:11:49.661421 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:11:49.664450 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:11:49.668074 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:11:49.674318 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:11:49.677996 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:11:49.681015 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:11:49.687355 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:11:49.691120 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:11:49.694409 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 12:11:49.700980 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8417 12:11:49.701068 Total UI for P1: 0, mck2ui 16
8418 12:11:49.707478 best dqsien dly found for B0: ( 1, 9, 12)
8419 12:11:49.710865 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 12:11:49.713939 Total UI for P1: 0, mck2ui 16
8421 12:11:49.717246 best dqsien dly found for B1: ( 1, 9, 14)
8422 12:11:49.720476 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8423 12:11:49.723657 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8424 12:11:49.723780
8425 12:11:49.726843 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8426 12:11:49.733981 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8427 12:11:49.734106 [Gating] SW calibration Done
8428 12:11:49.734217 ==
8429 12:11:49.737168 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 12:11:49.744009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 12:11:49.744115 ==
8432 12:11:49.744181 RX Vref Scan: 0
8433 12:11:49.744242
8434 12:11:49.746974 RX Vref 0 -> 0, step: 1
8435 12:11:49.747103
8436 12:11:49.750252 RX Delay 0 -> 252, step: 8
8437 12:11:49.753514 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8438 12:11:49.756683 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8439 12:11:49.759829 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8440 12:11:49.766525 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8441 12:11:49.769633 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8442 12:11:49.773353 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8443 12:11:49.776496 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8444 12:11:49.779585 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8445 12:11:49.786399 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8446 12:11:49.789478 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8447 12:11:49.792757 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8448 12:11:49.796023 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8449 12:11:49.799204 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8450 12:11:49.806109 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8451 12:11:49.809422 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8452 12:11:49.812691 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8453 12:11:49.812778 ==
8454 12:11:49.815970 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 12:11:49.819211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 12:11:49.822572 ==
8457 12:11:49.822660 DQS Delay:
8458 12:11:49.822728 DQS0 = 0, DQS1 = 0
8459 12:11:49.825742 DQM Delay:
8460 12:11:49.825832 DQM0 = 134, DQM1 = 131
8461 12:11:49.829046 DQ Delay:
8462 12:11:49.832289 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8463 12:11:49.835326 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8464 12:11:49.839169 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8465 12:11:49.841839 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8466 12:11:49.841915
8467 12:11:49.841981
8468 12:11:49.842052 ==
8469 12:11:49.845685 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 12:11:49.849005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 12:11:49.851873 ==
8472 12:11:49.851990
8473 12:11:49.852088
8474 12:11:49.852168 TX Vref Scan disable
8475 12:11:49.855037 == TX Byte 0 ==
8476 12:11:49.859028 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8477 12:11:49.862156 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 12:11:49.865062 == TX Byte 1 ==
8479 12:11:49.868294 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8480 12:11:49.872012 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8481 12:11:49.875152 ==
8482 12:11:49.878335 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 12:11:49.881482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 12:11:49.881591 ==
8485 12:11:49.893621
8486 12:11:49.896811 TX Vref early break, caculate TX vref
8487 12:11:49.900128 TX Vref=16, minBit 8, minWin=21, winSum=365
8488 12:11:49.904020 TX Vref=18, minBit 8, minWin=22, winSum=377
8489 12:11:49.907307 TX Vref=20, minBit 9, minWin=22, winSum=384
8490 12:11:49.910500 TX Vref=22, minBit 3, minWin=24, winSum=399
8491 12:11:49.913790 TX Vref=24, minBit 3, minWin=24, winSum=403
8492 12:11:49.920281 TX Vref=26, minBit 6, minWin=25, winSum=414
8493 12:11:49.923548 TX Vref=28, minBit 0, minWin=25, winSum=418
8494 12:11:49.926716 TX Vref=30, minBit 9, minWin=24, winSum=411
8495 12:11:49.929975 TX Vref=32, minBit 9, minWin=23, winSum=407
8496 12:11:49.933210 TX Vref=34, minBit 0, minWin=23, winSum=396
8497 12:11:49.940326 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8498 12:11:49.940409
8499 12:11:49.943591 Final TX Range 0 Vref 28
8500 12:11:49.943678
8501 12:11:49.943745 ==
8502 12:11:49.946915 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 12:11:49.949570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 12:11:49.949662 ==
8505 12:11:49.949729
8506 12:11:49.949790
8507 12:11:49.952873 TX Vref Scan disable
8508 12:11:49.959564 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8509 12:11:49.959661 == TX Byte 0 ==
8510 12:11:49.962732 u2DelayCellOfst[0]=18 cells (5 PI)
8511 12:11:49.966400 u2DelayCellOfst[1]=10 cells (3 PI)
8512 12:11:49.969422 u2DelayCellOfst[2]=0 cells (0 PI)
8513 12:11:49.972585 u2DelayCellOfst[3]=7 cells (2 PI)
8514 12:11:49.976196 u2DelayCellOfst[4]=10 cells (3 PI)
8515 12:11:49.979521 u2DelayCellOfst[5]=18 cells (5 PI)
8516 12:11:49.982614 u2DelayCellOfst[6]=18 cells (5 PI)
8517 12:11:49.985661 u2DelayCellOfst[7]=7 cells (2 PI)
8518 12:11:49.989209 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8519 12:11:49.992390 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8520 12:11:49.995996 == TX Byte 1 ==
8521 12:11:49.999082 u2DelayCellOfst[8]=0 cells (0 PI)
8522 12:11:50.002330 u2DelayCellOfst[9]=7 cells (2 PI)
8523 12:11:50.005582 u2DelayCellOfst[10]=14 cells (4 PI)
8524 12:11:50.005698 u2DelayCellOfst[11]=7 cells (2 PI)
8525 12:11:50.008947 u2DelayCellOfst[12]=14 cells (4 PI)
8526 12:11:50.012128 u2DelayCellOfst[13]=14 cells (4 PI)
8527 12:11:50.015349 u2DelayCellOfst[14]=18 cells (5 PI)
8528 12:11:50.018557 u2DelayCellOfst[15]=18 cells (5 PI)
8529 12:11:50.025542 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8530 12:11:50.028834 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8531 12:11:50.028919 DramC Write-DBI on
8532 12:11:50.032083 ==
8533 12:11:50.035328 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 12:11:50.038544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 12:11:50.038630 ==
8536 12:11:50.038703
8537 12:11:50.038767
8538 12:11:50.041812 TX Vref Scan disable
8539 12:11:50.041898 == TX Byte 0 ==
8540 12:11:50.048439 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8541 12:11:50.048525 == TX Byte 1 ==
8542 12:11:50.051652 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8543 12:11:50.054946 DramC Write-DBI off
8544 12:11:50.055032
8545 12:11:50.055103 [DATLAT]
8546 12:11:50.058266 Freq=1600, CH1 RK0
8547 12:11:50.058352
8548 12:11:50.058419 DATLAT Default: 0xf
8549 12:11:50.061398 0, 0xFFFF, sum = 0
8550 12:11:50.061485 1, 0xFFFF, sum = 0
8551 12:11:50.064960 2, 0xFFFF, sum = 0
8552 12:11:50.065046 3, 0xFFFF, sum = 0
8553 12:11:50.067994 4, 0xFFFF, sum = 0
8554 12:11:50.071811 5, 0xFFFF, sum = 0
8555 12:11:50.071897 6, 0xFFFF, sum = 0
8556 12:11:50.074824 7, 0xFFFF, sum = 0
8557 12:11:50.074911 8, 0xFFFF, sum = 0
8558 12:11:50.078000 9, 0xFFFF, sum = 0
8559 12:11:50.078086 10, 0xFFFF, sum = 0
8560 12:11:50.081114 11, 0xFFFF, sum = 0
8561 12:11:50.081201 12, 0xFFFF, sum = 0
8562 12:11:50.084915 13, 0xFFFF, sum = 0
8563 12:11:50.085001 14, 0x0, sum = 1
8564 12:11:50.087512 15, 0x0, sum = 2
8565 12:11:50.087597 16, 0x0, sum = 3
8566 12:11:50.091161 17, 0x0, sum = 4
8567 12:11:50.091248 best_step = 15
8568 12:11:50.091320
8569 12:11:50.091387 ==
8570 12:11:50.094193 Dram Type= 6, Freq= 0, CH_1, rank 0
8571 12:11:50.101005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8572 12:11:50.101096 ==
8573 12:11:50.101165 RX Vref Scan: 1
8574 12:11:50.101228
8575 12:11:50.104014 Set Vref Range= 24 -> 127
8576 12:11:50.104132
8577 12:11:50.107354 RX Vref 24 -> 127, step: 1
8578 12:11:50.107439
8579 12:11:50.107519 RX Delay 19 -> 252, step: 4
8580 12:11:50.107626
8581 12:11:50.111308 Set Vref, RX VrefLevel [Byte0]: 24
8582 12:11:50.114424 [Byte1]: 24
8583 12:11:50.118327
8584 12:11:50.118430 Set Vref, RX VrefLevel [Byte0]: 25
8585 12:11:50.121619 [Byte1]: 25
8586 12:11:50.125605
8587 12:11:50.125704 Set Vref, RX VrefLevel [Byte0]: 26
8588 12:11:50.129411 [Byte1]: 26
8589 12:11:50.133331
8590 12:11:50.133436 Set Vref, RX VrefLevel [Byte0]: 27
8591 12:11:50.136461 [Byte1]: 27
8592 12:11:50.141118
8593 12:11:50.141237 Set Vref, RX VrefLevel [Byte0]: 28
8594 12:11:50.144094 [Byte1]: 28
8595 12:11:50.148623
8596 12:11:50.148775 Set Vref, RX VrefLevel [Byte0]: 29
8597 12:11:50.151827 [Byte1]: 29
8598 12:11:50.156325
8599 12:11:50.156431 Set Vref, RX VrefLevel [Byte0]: 30
8600 12:11:50.159537 [Byte1]: 30
8601 12:11:50.163497
8602 12:11:50.163603 Set Vref, RX VrefLevel [Byte0]: 31
8603 12:11:50.167131 [Byte1]: 31
8604 12:11:50.171005
8605 12:11:50.171093 Set Vref, RX VrefLevel [Byte0]: 32
8606 12:11:50.174630 [Byte1]: 32
8607 12:11:50.179073
8608 12:11:50.179159 Set Vref, RX VrefLevel [Byte0]: 33
8609 12:11:50.182163 [Byte1]: 33
8610 12:11:50.186489
8611 12:11:50.186596 Set Vref, RX VrefLevel [Byte0]: 34
8612 12:11:50.189635 [Byte1]: 34
8613 12:11:50.194077
8614 12:11:50.194158 Set Vref, RX VrefLevel [Byte0]: 35
8615 12:11:50.197094 [Byte1]: 35
8616 12:11:50.201393
8617 12:11:50.201505 Set Vref, RX VrefLevel [Byte0]: 36
8618 12:11:50.204498 [Byte1]: 36
8619 12:11:50.208996
8620 12:11:50.209073 Set Vref, RX VrefLevel [Byte0]: 37
8621 12:11:50.212344 [Byte1]: 37
8622 12:11:50.216963
8623 12:11:50.217058 Set Vref, RX VrefLevel [Byte0]: 38
8624 12:11:50.220174 [Byte1]: 38
8625 12:11:50.224018
8626 12:11:50.224160 Set Vref, RX VrefLevel [Byte0]: 39
8627 12:11:50.227427 [Byte1]: 39
8628 12:11:50.232018
8629 12:11:50.232140 Set Vref, RX VrefLevel [Byte0]: 40
8630 12:11:50.235239 [Byte1]: 40
8631 12:11:50.239081
8632 12:11:50.239184 Set Vref, RX VrefLevel [Byte0]: 41
8633 12:11:50.242350 [Byte1]: 41
8634 12:11:50.246778
8635 12:11:50.246860 Set Vref, RX VrefLevel [Byte0]: 42
8636 12:11:50.249973 [Byte1]: 42
8637 12:11:50.254566
8638 12:11:50.254670 Set Vref, RX VrefLevel [Byte0]: 43
8639 12:11:50.257620 [Byte1]: 43
8640 12:11:50.262182
8641 12:11:50.262261 Set Vref, RX VrefLevel [Byte0]: 44
8642 12:11:50.265464 [Byte1]: 44
8643 12:11:50.269278
8644 12:11:50.269353 Set Vref, RX VrefLevel [Byte0]: 45
8645 12:11:50.272666 [Byte1]: 45
8646 12:11:50.277135
8647 12:11:50.277244 Set Vref, RX VrefLevel [Byte0]: 46
8648 12:11:50.280370 [Byte1]: 46
8649 12:11:50.284574
8650 12:11:50.284680 Set Vref, RX VrefLevel [Byte0]: 47
8651 12:11:50.288373 [Byte1]: 47
8652 12:11:50.292471
8653 12:11:50.292549 Set Vref, RX VrefLevel [Byte0]: 48
8654 12:11:50.295488 [Byte1]: 48
8655 12:11:50.299783
8656 12:11:50.299893 Set Vref, RX VrefLevel [Byte0]: 49
8657 12:11:50.302971 [Byte1]: 49
8658 12:11:50.307306
8659 12:11:50.307419 Set Vref, RX VrefLevel [Byte0]: 50
8660 12:11:50.310999 [Byte1]: 50
8661 12:11:50.315383
8662 12:11:50.315490 Set Vref, RX VrefLevel [Byte0]: 51
8663 12:11:50.318558 [Byte1]: 51
8664 12:11:50.322487
8665 12:11:50.322609 Set Vref, RX VrefLevel [Byte0]: 52
8666 12:11:50.325765 [Byte1]: 52
8667 12:11:50.330364
8668 12:11:50.330470 Set Vref, RX VrefLevel [Byte0]: 53
8669 12:11:50.333444 [Byte1]: 53
8670 12:11:50.337433
8671 12:11:50.337546 Set Vref, RX VrefLevel [Byte0]: 54
8672 12:11:50.341324 [Byte1]: 54
8673 12:11:50.345072
8674 12:11:50.345185 Set Vref, RX VrefLevel [Byte0]: 55
8675 12:11:50.348926 [Byte1]: 55
8676 12:11:50.352803
8677 12:11:50.352909 Set Vref, RX VrefLevel [Byte0]: 56
8678 12:11:50.355938 [Byte1]: 56
8679 12:11:50.360509
8680 12:11:50.360617 Set Vref, RX VrefLevel [Byte0]: 57
8681 12:11:50.363773 [Byte1]: 57
8682 12:11:50.368325
8683 12:11:50.368430 Set Vref, RX VrefLevel [Byte0]: 58
8684 12:11:50.371514 [Byte1]: 58
8685 12:11:50.375483
8686 12:11:50.375600 Set Vref, RX VrefLevel [Byte0]: 59
8687 12:11:50.378722 [Byte1]: 59
8688 12:11:50.383265
8689 12:11:50.383375 Set Vref, RX VrefLevel [Byte0]: 60
8690 12:11:50.386518 [Byte1]: 60
8691 12:11:50.390840
8692 12:11:50.390952 Set Vref, RX VrefLevel [Byte0]: 61
8693 12:11:50.393924 [Byte1]: 61
8694 12:11:50.398358
8695 12:11:50.398464 Set Vref, RX VrefLevel [Byte0]: 62
8696 12:11:50.401345 [Byte1]: 62
8697 12:11:50.406133
8698 12:11:50.406246 Set Vref, RX VrefLevel [Byte0]: 63
8699 12:11:50.409106 [Byte1]: 63
8700 12:11:50.413547
8701 12:11:50.413655 Set Vref, RX VrefLevel [Byte0]: 64
8702 12:11:50.416644 [Byte1]: 64
8703 12:11:50.420934
8704 12:11:50.421051 Set Vref, RX VrefLevel [Byte0]: 65
8705 12:11:50.424176 [Byte1]: 65
8706 12:11:50.428792
8707 12:11:50.428902 Set Vref, RX VrefLevel [Byte0]: 66
8708 12:11:50.431991 [Byte1]: 66
8709 12:11:50.436627
8710 12:11:50.436702 Set Vref, RX VrefLevel [Byte0]: 67
8711 12:11:50.439853 [Byte1]: 67
8712 12:11:50.443771
8713 12:11:50.443881 Set Vref, RX VrefLevel [Byte0]: 68
8714 12:11:50.446851 [Byte1]: 68
8715 12:11:50.451334
8716 12:11:50.451443 Set Vref, RX VrefLevel [Byte0]: 69
8717 12:11:50.454494 [Byte1]: 69
8718 12:11:50.459090
8719 12:11:50.459197 Set Vref, RX VrefLevel [Byte0]: 70
8720 12:11:50.462522 [Byte1]: 70
8721 12:11:50.466325
8722 12:11:50.466431 Set Vref, RX VrefLevel [Byte0]: 71
8723 12:11:50.469513 [Byte1]: 71
8724 12:11:50.474105
8725 12:11:50.474215 Final RX Vref Byte 0 = 55 to rank0
8726 12:11:50.477351 Final RX Vref Byte 1 = 61 to rank0
8727 12:11:50.480489 Final RX Vref Byte 0 = 55 to rank1
8728 12:11:50.483744 Final RX Vref Byte 1 = 61 to rank1==
8729 12:11:50.487037 Dram Type= 6, Freq= 0, CH_1, rank 0
8730 12:11:50.493833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 12:11:50.493936 ==
8732 12:11:50.494039 DQS Delay:
8733 12:11:50.496881 DQS0 = 0, DQS1 = 0
8734 12:11:50.496982 DQM Delay:
8735 12:11:50.497074 DQM0 = 133, DQM1 = 130
8736 12:11:50.500765 DQ Delay:
8737 12:11:50.503904 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8738 12:11:50.507073 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =126
8739 12:11:50.510193 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8740 12:11:50.513936 DQ12 =142, DQ13 =140, DQ14 =136, DQ15 =140
8741 12:11:50.514041
8742 12:11:50.514134
8743 12:11:50.514233
8744 12:11:50.516814 [DramC_TX_OE_Calibration] TA2
8745 12:11:50.519900 Original DQ_B0 (3 6) =30, OEN = 27
8746 12:11:50.523612 Original DQ_B1 (3 6) =30, OEN = 27
8747 12:11:50.526753 24, 0x0, End_B0=24 End_B1=24
8748 12:11:50.529972 25, 0x0, End_B0=25 End_B1=25
8749 12:11:50.530083 26, 0x0, End_B0=26 End_B1=26
8750 12:11:50.533164 27, 0x0, End_B0=27 End_B1=27
8751 12:11:50.536459 28, 0x0, End_B0=28 End_B1=28
8752 12:11:50.539654 29, 0x0, End_B0=29 End_B1=29
8753 12:11:50.542769 30, 0x0, End_B0=30 End_B1=30
8754 12:11:50.542873 31, 0x4141, End_B0=30 End_B1=30
8755 12:11:50.546522 Byte0 end_step=30 best_step=27
8756 12:11:50.549844 Byte1 end_step=30 best_step=27
8757 12:11:50.552901 Byte0 TX OE(2T, 0.5T) = (3, 3)
8758 12:11:50.556121 Byte1 TX OE(2T, 0.5T) = (3, 3)
8759 12:11:50.556197
8760 12:11:50.556266
8761 12:11:50.563292 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8762 12:11:50.565882 CH1 RK0: MR19=303, MR18=D17
8763 12:11:50.572515 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8764 12:11:50.572601
8765 12:11:50.576329 ----->DramcWriteLeveling(PI) begin...
8766 12:11:50.576428 ==
8767 12:11:50.578888 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 12:11:50.582732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8769 12:11:50.582837 ==
8770 12:11:50.585896 Write leveling (Byte 0): 25 => 25
8771 12:11:50.589202 Write leveling (Byte 1): 25 => 25
8772 12:11:50.592532 DramcWriteLeveling(PI) end<-----
8773 12:11:50.592629
8774 12:11:50.592719 ==
8775 12:11:50.595669 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 12:11:50.601951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 12:11:50.602063 ==
8778 12:11:50.602159 [Gating] SW mode calibration
8779 12:11:50.612274 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8780 12:11:50.615451 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8781 12:11:50.622093 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 12:11:50.625127 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 12:11:50.628367 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8784 12:11:50.634816 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8785 12:11:50.638140 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 12:11:50.642111 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 12:11:50.648564 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 12:11:50.651693 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 12:11:50.654933 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 12:11:50.661228 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8791 12:11:50.664548 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8792 12:11:50.667759 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8793 12:11:50.674902 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8794 12:11:50.678135 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 12:11:50.681438 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 12:11:50.687768 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 12:11:50.691052 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 12:11:50.694263 1 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8799 12:11:50.698070 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8800 12:11:50.704491 1 6 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8801 12:11:50.707639 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 12:11:50.711108 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 12:11:50.717807 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 12:11:50.720806 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:11:50.723960 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 12:11:50.730735 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8807 12:11:50.734319 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8808 12:11:50.737405 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8809 12:11:50.744317 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 12:11:50.747577 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:11:50.750703 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:11:50.757126 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:11:50.760394 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:11:50.766862 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:11:50.770099 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:11:50.773424 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:11:50.779967 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:11:50.783356 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:11:50.786434 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:11:50.793624 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:11:50.796852 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:11:50.800165 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:11:50.806740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8824 12:11:50.809891 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8825 12:11:50.813092 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8826 12:11:50.816193 Total UI for P1: 0, mck2ui 16
8827 12:11:50.819593 best dqsien dly found for B0: ( 1, 9, 10)
8828 12:11:50.822670 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 12:11:50.826129 Total UI for P1: 0, mck2ui 16
8830 12:11:50.829221 best dqsien dly found for B1: ( 1, 9, 14)
8831 12:11:50.835956 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8832 12:11:50.839035 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8833 12:11:50.839118
8834 12:11:50.842883 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8835 12:11:50.845810 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8836 12:11:50.848946 [Gating] SW calibration Done
8837 12:11:50.849030 ==
8838 12:11:50.852835 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 12:11:50.855885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 12:11:50.855970 ==
8841 12:11:50.859163 RX Vref Scan: 0
8842 12:11:50.859272
8843 12:11:50.859395 RX Vref 0 -> 0, step: 1
8844 12:11:50.859487
8845 12:11:50.862453 RX Delay 0 -> 252, step: 8
8846 12:11:50.865622 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8847 12:11:50.872555 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8848 12:11:50.875263 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8849 12:11:50.878482 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8850 12:11:50.882320 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8851 12:11:50.885653 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8852 12:11:50.892289 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8853 12:11:50.895543 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8854 12:11:50.898864 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8855 12:11:50.902150 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8856 12:11:50.908627 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8857 12:11:50.911869 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8858 12:11:50.915109 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8859 12:11:50.918303 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8860 12:11:50.921357 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8861 12:11:50.927961 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8862 12:11:50.928069 ==
8863 12:11:50.931642 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 12:11:50.934642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 12:11:50.934726 ==
8866 12:11:50.934792 DQS Delay:
8867 12:11:50.937690 DQS0 = 0, DQS1 = 0
8868 12:11:50.937774 DQM Delay:
8869 12:11:50.941428 DQM0 = 136, DQM1 = 130
8870 12:11:50.941510 DQ Delay:
8871 12:11:50.944442 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8872 12:11:50.948185 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8873 12:11:50.951059 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8874 12:11:50.958041 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8875 12:11:50.958123
8876 12:11:50.958189
8877 12:11:50.958250 ==
8878 12:11:50.961215 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 12:11:50.964671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 12:11:50.964757 ==
8881 12:11:50.964825
8882 12:11:50.964888
8883 12:11:50.967746 TX Vref Scan disable
8884 12:11:50.967831 == TX Byte 0 ==
8885 12:11:50.974276 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8886 12:11:50.977571 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8887 12:11:50.977656 == TX Byte 1 ==
8888 12:11:50.984165 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8889 12:11:50.987554 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8890 12:11:50.987640 ==
8891 12:11:50.990917 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 12:11:50.994156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 12:11:50.994241 ==
8894 12:11:51.008969
8895 12:11:51.012256 TX Vref early break, caculate TX vref
8896 12:11:51.015539 TX Vref=16, minBit 9, minWin=22, winSum=381
8897 12:11:51.018805 TX Vref=18, minBit 9, minWin=22, winSum=382
8898 12:11:51.021925 TX Vref=20, minBit 9, minWin=22, winSum=389
8899 12:11:51.025123 TX Vref=22, minBit 9, minWin=23, winSum=399
8900 12:11:51.028088 TX Vref=24, minBit 9, minWin=24, winSum=409
8901 12:11:51.034735 TX Vref=26, minBit 9, minWin=24, winSum=415
8902 12:11:51.038503 TX Vref=28, minBit 9, minWin=24, winSum=418
8903 12:11:51.041595 TX Vref=30, minBit 9, minWin=24, winSum=417
8904 12:11:51.045222 TX Vref=32, minBit 1, minWin=25, winSum=411
8905 12:11:51.048241 TX Vref=34, minBit 0, minWin=24, winSum=405
8906 12:11:51.054834 TX Vref=36, minBit 8, minWin=23, winSum=395
8907 12:11:51.057782 [TxChooseVref] Worse bit 1, Min win 25, Win sum 411, Final Vref 32
8908 12:11:51.057866
8909 12:11:51.061423 Final TX Range 0 Vref 32
8910 12:11:51.061522
8911 12:11:51.061602 ==
8912 12:11:51.064620 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 12:11:51.067904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 12:11:51.071205 ==
8915 12:11:51.071282
8916 12:11:51.071346
8917 12:11:51.071407 TX Vref Scan disable
8918 12:11:51.077669 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8919 12:11:51.077749 == TX Byte 0 ==
8920 12:11:51.080943 u2DelayCellOfst[0]=14 cells (4 PI)
8921 12:11:51.084305 u2DelayCellOfst[1]=10 cells (3 PI)
8922 12:11:51.087483 u2DelayCellOfst[2]=0 cells (0 PI)
8923 12:11:51.091438 u2DelayCellOfst[3]=7 cells (2 PI)
8924 12:11:51.094593 u2DelayCellOfst[4]=7 cells (2 PI)
8925 12:11:51.097904 u2DelayCellOfst[5]=14 cells (4 PI)
8926 12:11:51.100641 u2DelayCellOfst[6]=14 cells (4 PI)
8927 12:11:51.104613 u2DelayCellOfst[7]=3 cells (1 PI)
8928 12:11:51.107693 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8929 12:11:51.111009 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8930 12:11:51.114405 == TX Byte 1 ==
8931 12:11:51.117026 u2DelayCellOfst[8]=0 cells (0 PI)
8932 12:11:51.120987 u2DelayCellOfst[9]=3 cells (1 PI)
8933 12:11:51.123646 u2DelayCellOfst[10]=10 cells (3 PI)
8934 12:11:51.126878 u2DelayCellOfst[11]=3 cells (1 PI)
8935 12:11:51.130634 u2DelayCellOfst[12]=14 cells (4 PI)
8936 12:11:51.133904 u2DelayCellOfst[13]=14 cells (4 PI)
8937 12:11:51.136884 u2DelayCellOfst[14]=18 cells (5 PI)
8938 12:11:51.136968 u2DelayCellOfst[15]=18 cells (5 PI)
8939 12:11:51.143749 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8940 12:11:51.146749 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8941 12:11:51.150572 DramC Write-DBI on
8942 12:11:51.150657 ==
8943 12:11:51.153655 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 12:11:51.156795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 12:11:51.156905 ==
8946 12:11:51.157000
8947 12:11:51.157127
8948 12:11:51.159888 TX Vref Scan disable
8949 12:11:51.160000 == TX Byte 0 ==
8950 12:11:51.166723 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8951 12:11:51.166810 == TX Byte 1 ==
8952 12:11:51.169820 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8953 12:11:51.173035 DramC Write-DBI off
8954 12:11:51.173129
8955 12:11:51.173196 [DATLAT]
8956 12:11:51.177106 Freq=1600, CH1 RK1
8957 12:11:51.177190
8958 12:11:51.177256 DATLAT Default: 0xf
8959 12:11:51.180277 0, 0xFFFF, sum = 0
8960 12:11:51.180362 1, 0xFFFF, sum = 0
8961 12:11:51.183571 2, 0xFFFF, sum = 0
8962 12:11:51.186696 3, 0xFFFF, sum = 0
8963 12:11:51.186780 4, 0xFFFF, sum = 0
8964 12:11:51.189810 5, 0xFFFF, sum = 0
8965 12:11:51.189906 6, 0xFFFF, sum = 0
8966 12:11:51.193153 7, 0xFFFF, sum = 0
8967 12:11:51.193238 8, 0xFFFF, sum = 0
8968 12:11:51.196347 9, 0xFFFF, sum = 0
8969 12:11:51.196442 10, 0xFFFF, sum = 0
8970 12:11:51.199658 11, 0xFFFF, sum = 0
8971 12:11:51.199752 12, 0xFFFF, sum = 0
8972 12:11:51.202962 13, 0xFFFF, sum = 0
8973 12:11:51.203042 14, 0x0, sum = 1
8974 12:11:51.206243 15, 0x0, sum = 2
8975 12:11:51.206324 16, 0x0, sum = 3
8976 12:11:51.209328 17, 0x0, sum = 4
8977 12:11:51.209399 best_step = 15
8978 12:11:51.209461
8979 12:11:51.209587 ==
8980 12:11:51.212644 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 12:11:51.219195 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 12:11:51.219308 ==
8983 12:11:51.219403 RX Vref Scan: 0
8984 12:11:51.219502
8985 12:11:51.222462 RX Vref 0 -> 0, step: 1
8986 12:11:51.222535
8987 12:11:51.225820 RX Delay 19 -> 252, step: 4
8988 12:11:51.229067 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8989 12:11:51.232155 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8990 12:11:51.238799 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8991 12:11:51.242460 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8992 12:11:51.245581 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8993 12:11:51.248676 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8994 12:11:51.252299 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8995 12:11:51.258431 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8996 12:11:51.262305 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8997 12:11:51.265234 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8998 12:11:51.268272 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8999 12:11:51.271526 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9000 12:11:51.278432 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9001 12:11:51.281579 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9002 12:11:51.284864 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9003 12:11:51.287937 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9004 12:11:51.291726 ==
9005 12:11:51.291835 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 12:11:51.298233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 12:11:51.298330 ==
9008 12:11:51.298399 DQS Delay:
9009 12:11:51.301581 DQS0 = 0, DQS1 = 0
9010 12:11:51.301660 DQM Delay:
9011 12:11:51.304218 DQM0 = 132, DQM1 = 128
9012 12:11:51.304294 DQ Delay:
9013 12:11:51.307574 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =128
9014 12:11:51.310822 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =128
9015 12:11:51.314154 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9016 12:11:51.317490 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9017 12:11:51.317603
9018 12:11:51.317666
9019 12:11:51.317725
9020 12:11:51.320787 [DramC_TX_OE_Calibration] TA2
9021 12:11:51.324061 Original DQ_B0 (3 6) =30, OEN = 27
9022 12:11:51.327345 Original DQ_B1 (3 6) =30, OEN = 27
9023 12:11:51.330648 24, 0x0, End_B0=24 End_B1=24
9024 12:11:51.333916 25, 0x0, End_B0=25 End_B1=25
9025 12:11:51.337100 26, 0x0, End_B0=26 End_B1=26
9026 12:11:51.337212 27, 0x0, End_B0=27 End_B1=27
9027 12:11:51.340755 28, 0x0, End_B0=28 End_B1=28
9028 12:11:51.343771 29, 0x0, End_B0=29 End_B1=29
9029 12:11:51.347472 30, 0x0, End_B0=30 End_B1=30
9030 12:11:51.350661 31, 0x5151, End_B0=30 End_B1=30
9031 12:11:51.350748 Byte0 end_step=30 best_step=27
9032 12:11:51.353864 Byte1 end_step=30 best_step=27
9033 12:11:51.356962 Byte0 TX OE(2T, 0.5T) = (3, 3)
9034 12:11:51.360079 Byte1 TX OE(2T, 0.5T) = (3, 3)
9035 12:11:51.360164
9036 12:11:51.360231
9037 12:11:51.369888 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9038 12:11:51.369983 CH1 RK1: MR19=303, MR18=101D
9039 12:11:51.376668 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
9040 12:11:51.379767 [RxdqsGatingPostProcess] freq 1600
9041 12:11:51.386976 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9042 12:11:51.390128 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 12:11:51.393316 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 12:11:51.396654 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 12:11:51.399709 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 12:11:51.399794 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 12:11:51.403124 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 12:11:51.406465 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 12:11:51.409723 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 12:11:51.412977 Pre-setting of DQS Precalculation
9051 12:11:51.419563 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9052 12:11:51.426174 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9053 12:11:51.432912 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 12:11:51.433024
9055 12:11:51.433124
9056 12:11:51.436082 [Calibration Summary] 3200 Mbps
9057 12:11:51.436167 CH 0, Rank 0
9058 12:11:51.439408 SW Impedance : PASS
9059 12:11:51.442503 DUTY Scan : NO K
9060 12:11:51.442588 ZQ Calibration : PASS
9061 12:11:51.445599 Jitter Meter : NO K
9062 12:11:51.448736 CBT Training : PASS
9063 12:11:51.448821 Write leveling : PASS
9064 12:11:51.452408 RX DQS gating : PASS
9065 12:11:51.455559 RX DQ/DQS(RDDQC) : PASS
9066 12:11:51.455644 TX DQ/DQS : PASS
9067 12:11:51.458632 RX DATLAT : PASS
9068 12:11:51.462322 RX DQ/DQS(Engine): PASS
9069 12:11:51.462408 TX OE : PASS
9070 12:11:51.465366 All Pass.
9071 12:11:51.465466
9072 12:11:51.465536 CH 0, Rank 1
9073 12:11:51.468511 SW Impedance : PASS
9074 12:11:51.468596 DUTY Scan : NO K
9075 12:11:51.472267 ZQ Calibration : PASS
9076 12:11:51.475372 Jitter Meter : NO K
9077 12:11:51.475458 CBT Training : PASS
9078 12:11:51.478512 Write leveling : PASS
9079 12:11:51.482269 RX DQS gating : PASS
9080 12:11:51.482355 RX DQ/DQS(RDDQC) : PASS
9081 12:11:51.485351 TX DQ/DQS : PASS
9082 12:11:51.488452 RX DATLAT : PASS
9083 12:11:51.488537 RX DQ/DQS(Engine): PASS
9084 12:11:51.491661 TX OE : PASS
9085 12:11:51.491751 All Pass.
9086 12:11:51.491818
9087 12:11:51.495562 CH 1, Rank 0
9088 12:11:51.495646 SW Impedance : PASS
9089 12:11:51.498854 DUTY Scan : NO K
9090 12:11:51.498967 ZQ Calibration : PASS
9091 12:11:51.501864 Jitter Meter : NO K
9092 12:11:51.505291 CBT Training : PASS
9093 12:11:51.505376 Write leveling : PASS
9094 12:11:51.508591 RX DQS gating : PASS
9095 12:11:51.511846 RX DQ/DQS(RDDQC) : PASS
9096 12:11:51.511957 TX DQ/DQS : PASS
9097 12:11:51.515054 RX DATLAT : PASS
9098 12:11:51.518275 RX DQ/DQS(Engine): PASS
9099 12:11:51.518360 TX OE : PASS
9100 12:11:51.521551 All Pass.
9101 12:11:51.521635
9102 12:11:51.521703 CH 1, Rank 1
9103 12:11:51.524778 SW Impedance : PASS
9104 12:11:51.524863 DUTY Scan : NO K
9105 12:11:51.527938 ZQ Calibration : PASS
9106 12:11:51.531238 Jitter Meter : NO K
9107 12:11:51.531323 CBT Training : PASS
9108 12:11:51.534350 Write leveling : PASS
9109 12:11:51.537609 RX DQS gating : PASS
9110 12:11:51.537693 RX DQ/DQS(RDDQC) : PASS
9111 12:11:51.541403 TX DQ/DQS : PASS
9112 12:11:51.544614 RX DATLAT : PASS
9113 12:11:51.544698 RX DQ/DQS(Engine): PASS
9114 12:11:51.547703 TX OE : PASS
9115 12:11:51.547804 All Pass.
9116 12:11:51.547873
9117 12:11:51.551316 DramC Write-DBI on
9118 12:11:51.554327 PER_BANK_REFRESH: Hybrid Mode
9119 12:11:51.554440 TX_TRACKING: ON
9120 12:11:51.564124 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9121 12:11:51.570550 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9122 12:11:51.577303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 12:11:51.584049 [FAST_K] Save calibration result to emmc
9124 12:11:51.584144 sync common calibartion params.
9125 12:11:51.587397 sync cbt_mode0:1, 1:1
9126 12:11:51.590332 dram_init: ddr_geometry: 2
9127 12:11:51.593548 dram_init: ddr_geometry: 2
9128 12:11:51.593633 dram_init: ddr_geometry: 2
9129 12:11:51.597302 0:dram_rank_size:100000000
9130 12:11:51.600587 1:dram_rank_size:100000000
9131 12:11:51.603694 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9132 12:11:51.606945 DFS_SHUFFLE_HW_MODE: ON
9133 12:11:51.610135 dramc_set_vcore_voltage set vcore to 725000
9134 12:11:51.613386 Read voltage for 1600, 0
9135 12:11:51.613491 Vio18 = 0
9136 12:11:51.616547 Vcore = 725000
9137 12:11:51.616638 Vdram = 0
9138 12:11:51.616707 Vddq = 0
9139 12:11:51.616771 Vmddr = 0
9140 12:11:51.619808 switch to 3200 Mbps bootup
9141 12:11:51.623753 [DramcRunTimeConfig]
9142 12:11:51.623837 PHYPLL
9143 12:11:51.626428 DPM_CONTROL_AFTERK: ON
9144 12:11:51.626539 PER_BANK_REFRESH: ON
9145 12:11:51.629705 REFRESH_OVERHEAD_REDUCTION: ON
9146 12:11:51.633148 CMD_PICG_NEW_MODE: OFF
9147 12:11:51.633262 XRTWTW_NEW_MODE: ON
9148 12:11:51.636219 XRTRTR_NEW_MODE: ON
9149 12:11:51.636307 TX_TRACKING: ON
9150 12:11:51.639433 RDSEL_TRACKING: OFF
9151 12:11:51.642823 DQS Precalculation for DVFS: ON
9152 12:11:51.642930 RX_TRACKING: OFF
9153 12:11:51.646071 HW_GATING DBG: ON
9154 12:11:51.646180 ZQCS_ENABLE_LP4: ON
9155 12:11:51.649818 RX_PICG_NEW_MODE: ON
9156 12:11:51.649895 TX_PICG_NEW_MODE: ON
9157 12:11:51.652935 ENABLE_RX_DCM_DPHY: ON
9158 12:11:51.656704 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9159 12:11:51.659821 DUMMY_READ_FOR_TRACKING: OFF
9160 12:11:51.659941 !!! SPM_CONTROL_AFTERK: OFF
9161 12:11:51.662836 !!! SPM could not control APHY
9162 12:11:51.665957 IMPEDANCE_TRACKING: ON
9163 12:11:51.666059 TEMP_SENSOR: ON
9164 12:11:51.669529 HW_SAVE_FOR_SR: OFF
9165 12:11:51.672617 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9166 12:11:51.675780 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9167 12:11:51.679023 Read ODT Tracking: ON
9168 12:11:51.679099 Refresh Rate DeBounce: ON
9169 12:11:51.682681 DFS_NO_QUEUE_FLUSH: ON
9170 12:11:51.685726 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9171 12:11:51.688827 ENABLE_DFS_RUNTIME_MRW: OFF
9172 12:11:51.688904 DDR_RESERVE_NEW_MODE: ON
9173 12:11:51.692109 MR_CBT_SWITCH_FREQ: ON
9174 12:11:51.695197 =========================
9175 12:11:51.713094 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9176 12:11:51.716385 dram_init: ddr_geometry: 2
9177 12:11:51.734647 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9178 12:11:51.737787 dram_init: dram init end (result: 0)
9179 12:11:51.744897 DRAM-K: Full calibration passed in 24446 msecs
9180 12:11:51.748020 MRC: failed to locate region type 0.
9181 12:11:51.748110 DRAM rank0 size:0x100000000,
9182 12:11:51.751383 DRAM rank1 size=0x100000000
9183 12:11:51.761009 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9184 12:11:51.767333 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9185 12:11:51.777317 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9186 12:11:51.783789 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9187 12:11:51.783877 DRAM rank0 size:0x100000000,
9188 12:11:51.787453 DRAM rank1 size=0x100000000
9189 12:11:51.787534 CBMEM:
9190 12:11:51.790547 IMD: root @ 0xfffff000 254 entries.
9191 12:11:51.793622 IMD: root @ 0xffffec00 62 entries.
9192 12:11:51.800551 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9193 12:11:51.803738 WARNING: RO_VPD is uninitialized or empty.
9194 12:11:51.806716 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9195 12:11:51.814639 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9196 12:11:51.827715 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9197 12:11:51.838655 BS: romstage times (exec / console): total (unknown) / 23975 ms
9198 12:11:51.838770
9199 12:11:51.838869
9200 12:11:51.848561 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9201 12:11:51.852296 ARM64: Exception handlers installed.
9202 12:11:51.855608 ARM64: Testing exception
9203 12:11:51.858702 ARM64: Done test exception
9204 12:11:51.858831 Enumerating buses...
9205 12:11:51.861932 Show all devs... Before device enumeration.
9206 12:11:51.865520 Root Device: enabled 1
9207 12:11:51.868580 CPU_CLUSTER: 0: enabled 1
9208 12:11:51.868666 CPU: 00: enabled 1
9209 12:11:51.871576 Compare with tree...
9210 12:11:51.871667 Root Device: enabled 1
9211 12:11:51.875254 CPU_CLUSTER: 0: enabled 1
9212 12:11:51.878264 CPU: 00: enabled 1
9213 12:11:51.878366 Root Device scanning...
9214 12:11:51.881937 scan_static_bus for Root Device
9215 12:11:51.885020 CPU_CLUSTER: 0 enabled
9216 12:11:51.888222 scan_static_bus for Root Device done
9217 12:11:51.891414 scan_bus: bus Root Device finished in 8 msecs
9218 12:11:51.891521 done
9219 12:11:51.898247 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9220 12:11:51.901566 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9221 12:11:51.907883 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9222 12:11:51.914983 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9223 12:11:51.915100 Allocating resources...
9224 12:11:51.917715 Reading resources...
9225 12:11:51.921128 Root Device read_resources bus 0 link: 0
9226 12:11:51.924356 DRAM rank0 size:0x100000000,
9227 12:11:51.924496 DRAM rank1 size=0x100000000
9228 12:11:51.930804 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9229 12:11:51.930926 CPU: 00 missing read_resources
9230 12:11:51.937549 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9231 12:11:51.940872 Root Device read_resources bus 0 link: 0 done
9232 12:11:51.944231 Done reading resources.
9233 12:11:51.947526 Show resources in subtree (Root Device)...After reading.
9234 12:11:51.950794 Root Device child on link 0 CPU_CLUSTER: 0
9235 12:11:51.954070 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 12:11:51.963799 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 12:11:51.963893 CPU: 00
9238 12:11:51.970518 Root Device assign_resources, bus 0 link: 0
9239 12:11:51.973567 CPU_CLUSTER: 0 missing set_resources
9240 12:11:51.977242 Root Device assign_resources, bus 0 link: 0 done
9241 12:11:51.980301 Done setting resources.
9242 12:11:51.983476 Show resources in subtree (Root Device)...After assigning values.
9243 12:11:51.990329 Root Device child on link 0 CPU_CLUSTER: 0
9244 12:11:51.993476 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 12:11:51.999700 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 12:11:52.003485 CPU: 00
9247 12:11:52.003586 Done allocating resources.
9248 12:11:52.009622 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9249 12:11:52.009719 Enabling resources...
9250 12:11:52.013318 done.
9251 12:11:52.016507 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9252 12:11:52.019773 Initializing devices...
9253 12:11:52.019859 Root Device init
9254 12:11:52.023140 init hardware done!
9255 12:11:52.023228 0x00000018: ctrlr->caps
9256 12:11:52.026352 52.000 MHz: ctrlr->f_max
9257 12:11:52.029659 0.400 MHz: ctrlr->f_min
9258 12:11:52.032906 0x40ff8080: ctrlr->voltages
9259 12:11:52.032997 sclk: 390625
9260 12:11:52.033075 Bus Width = 1
9261 12:11:52.036309 sclk: 390625
9262 12:11:52.036387 Bus Width = 1
9263 12:11:52.039573 Early init status = 3
9264 12:11:52.042745 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9265 12:11:52.046782 in-header: 03 fc 00 00 01 00 00 00
9266 12:11:52.049508 in-data: 00
9267 12:11:52.052826 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9268 12:11:52.058018 in-header: 03 fd 00 00 00 00 00 00
9269 12:11:52.061136 in-data:
9270 12:11:52.064470 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 12:11:52.068919 in-header: 03 fc 00 00 01 00 00 00
9272 12:11:52.071987 in-data: 00
9273 12:11:52.075006 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9274 12:11:52.080625 in-header: 03 fd 00 00 00 00 00 00
9275 12:11:52.084189 in-data:
9276 12:11:52.087318 [SSUSB] Setting up USB HOST controller...
9277 12:11:52.090488 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9278 12:11:52.094271 [SSUSB] phy power-on done.
9279 12:11:52.097548 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9280 12:11:52.103738 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9281 12:11:52.107371 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9282 12:11:52.113777 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9283 12:11:52.120754 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9284 12:11:52.127162 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9285 12:11:52.133672 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9286 12:11:52.140376 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9287 12:11:52.143706 SPM: binary array size = 0x9dc
9288 12:11:52.146809 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9289 12:11:52.153404 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9290 12:11:52.159866 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9291 12:11:52.166489 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9292 12:11:52.170174 configure_display: Starting display init
9293 12:11:52.204215 anx7625_power_on_init: Init interface.
9294 12:11:52.207382 anx7625_disable_pd_protocol: Disabled PD feature.
9295 12:11:52.210447 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9296 12:11:52.238181 anx7625_start_dp_work: Secure OCM version=00
9297 12:11:52.241441 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9298 12:11:52.256479 sp_tx_get_edid_block: EDID Block = 1
9299 12:11:52.359160 Extracted contents:
9300 12:11:52.362343 header: 00 ff ff ff ff ff ff 00
9301 12:11:52.365643 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9302 12:11:52.368935 version: 01 04
9303 12:11:52.372116 basic params: 95 1f 11 78 0a
9304 12:11:52.375314 chroma info: 76 90 94 55 54 90 27 21 50 54
9305 12:11:52.378753 established: 00 00 00
9306 12:11:52.385685 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9307 12:11:52.391810 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9308 12:11:52.395518 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9309 12:11:52.401786 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9310 12:11:52.408659 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9311 12:11:52.411820 extensions: 00
9312 12:11:52.411949 checksum: fb
9313 12:11:52.412055
9314 12:11:52.418660 Manufacturer: IVO Model 57d Serial Number 0
9315 12:11:52.418786 Made week 0 of 2020
9316 12:11:52.421716 EDID version: 1.4
9317 12:11:52.421820 Digital display
9318 12:11:52.425311 6 bits per primary color channel
9319 12:11:52.428562 DisplayPort interface
9320 12:11:52.428642 Maximum image size: 31 cm x 17 cm
9321 12:11:52.431709 Gamma: 220%
9322 12:11:52.431825 Check DPMS levels
9323 12:11:52.438154 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9324 12:11:52.441532 First detailed timing is preferred timing
9325 12:11:52.444938 Established timings supported:
9326 12:11:52.445044 Standard timings supported:
9327 12:11:52.448188 Detailed timings
9328 12:11:52.451493 Hex of detail: 383680a07038204018303c0035ae10000019
9329 12:11:52.457511 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9330 12:11:52.460840 0780 0798 07c8 0820 hborder 0
9331 12:11:52.464568 0438 043b 0447 0458 vborder 0
9332 12:11:52.467934 -hsync -vsync
9333 12:11:52.468060 Did detailed timing
9334 12:11:52.474311 Hex of detail: 000000000000000000000000000000000000
9335 12:11:52.477538 Manufacturer-specified data, tag 0
9336 12:11:52.480792 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9337 12:11:52.484136 ASCII string: InfoVision
9338 12:11:52.487459 Hex of detail: 000000fe00523134304e574635205248200a
9339 12:11:52.490872 ASCII string: R140NWF5 RH
9340 12:11:52.490945 Checksum
9341 12:11:52.493991 Checksum: 0xfb (valid)
9342 12:11:52.497079 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9343 12:11:52.500861 DSI data_rate: 832800000 bps
9344 12:11:52.507108 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9345 12:11:52.510237 anx7625_parse_edid: pixelclock(138800).
9346 12:11:52.514007 hactive(1920), hsync(48), hfp(24), hbp(88)
9347 12:11:52.517134 vactive(1080), vsync(12), vfp(3), vbp(17)
9348 12:11:52.520299 anx7625_dsi_config: config dsi.
9349 12:11:52.526966 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9350 12:11:52.541396 anx7625_dsi_config: success to config DSI
9351 12:11:52.544737 anx7625_dp_start: MIPI phy setup OK.
9352 12:11:52.547854 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9353 12:11:52.551153 mtk_ddp_mode_set invalid vrefresh 60
9354 12:11:52.554447 main_disp_path_setup
9355 12:11:52.554553 ovl_layer_smi_id_en
9356 12:11:52.557661 ovl_layer_smi_id_en
9357 12:11:52.557778 ccorr_config
9358 12:11:52.557888 aal_config
9359 12:11:52.561029 gamma_config
9360 12:11:52.561106 postmask_config
9361 12:11:52.564233 dither_config
9362 12:11:52.567410 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9363 12:11:52.574057 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9364 12:11:52.577268 Root Device init finished in 553 msecs
9365 12:11:52.580537 CPU_CLUSTER: 0 init
9366 12:11:52.586981 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9367 12:11:52.593948 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9368 12:11:52.594075 APU_MBOX 0x190000b0 = 0x10001
9369 12:11:52.597138 APU_MBOX 0x190001b0 = 0x10001
9370 12:11:52.600124 APU_MBOX 0x190005b0 = 0x10001
9371 12:11:52.603255 APU_MBOX 0x190006b0 = 0x10001
9372 12:11:52.610201 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9373 12:11:52.619883 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9374 12:11:52.632609 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9375 12:11:52.638982 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9376 12:11:52.650469 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9377 12:11:52.659840 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9378 12:11:52.663092 CPU_CLUSTER: 0 init finished in 81 msecs
9379 12:11:52.666507 Devices initialized
9380 12:11:52.669715 Show all devs... After init.
9381 12:11:52.669810 Root Device: enabled 1
9382 12:11:52.672806 CPU_CLUSTER: 0: enabled 1
9383 12:11:52.676110 CPU: 00: enabled 1
9384 12:11:52.679539 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9385 12:11:52.682785 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9386 12:11:52.686036 ELOG: NV offset 0x57f000 size 0x1000
9387 12:11:52.693170 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9388 12:11:52.699583 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9389 12:11:52.702781 ELOG: Event(17) added with size 13 at 2023-06-06 12:11:58 UTC
9390 12:11:52.709807 out: cmd=0x121: 03 db 21 01 00 00 00 00
9391 12:11:52.712943 in-header: 03 16 00 00 2c 00 00 00
9392 12:11:52.722990 in-data: 49 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 12:11:52.729310 ELOG: Event(A1) added with size 10 at 2023-06-06 12:11:58 UTC
9394 12:11:52.735972 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9395 12:11:52.742830 ELOG: Event(A0) added with size 9 at 2023-06-06 12:11:58 UTC
9396 12:11:52.746150 elog_add_boot_reason: Logged dev mode boot
9397 12:11:52.752802 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9398 12:11:52.752891 Finalize devices...
9399 12:11:52.755949 Devices finalized
9400 12:11:52.759221 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9401 12:11:52.762506 Writing coreboot table at 0xffe64000
9402 12:11:52.765839 0. 000000000010a000-0000000000113fff: RAMSTAGE
9403 12:11:52.772481 1. 0000000040000000-00000000400fffff: RAM
9404 12:11:52.775837 2. 0000000040100000-000000004032afff: RAMSTAGE
9405 12:11:52.778902 3. 000000004032b000-00000000545fffff: RAM
9406 12:11:52.782234 4. 0000000054600000-000000005465ffff: BL31
9407 12:11:52.785425 5. 0000000054660000-00000000ffe63fff: RAM
9408 12:11:52.792139 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9409 12:11:52.795465 7. 0000000100000000-000000023fffffff: RAM
9410 12:11:52.798640 Passing 5 GPIOs to payload:
9411 12:11:52.801670 NAME | PORT | POLARITY | VALUE
9412 12:11:52.808139 EC in RW | 0x000000aa | low | undefined
9413 12:11:52.811650 EC interrupt | 0x00000005 | low | undefined
9414 12:11:52.817963 TPM interrupt | 0x000000ab | high | undefined
9415 12:11:52.821600 SD card detect | 0x00000011 | high | undefined
9416 12:11:52.824705 speaker enable | 0x00000093 | high | undefined
9417 12:11:52.827745 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9418 12:11:52.832198 in-header: 03 f9 00 00 02 00 00 00
9419 12:11:52.836017 in-data: 02 00
9420 12:11:52.838952 ADC[4]: Raw value=902955 ID=7
9421 12:11:52.842085 ADC[3]: Raw value=213916 ID=1
9422 12:11:52.842217 RAM Code: 0x71
9423 12:11:52.845758 ADC[6]: Raw value=75000 ID=0
9424 12:11:52.848986 ADC[5]: Raw value=213546 ID=1
9425 12:11:52.849075 SKU Code: 0x1
9426 12:11:52.855513 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a51a
9427 12:11:52.855610 coreboot table: 964 bytes.
9428 12:11:52.858754 IMD ROOT 0. 0xfffff000 0x00001000
9429 12:11:52.862086 IMD SMALL 1. 0xffffe000 0x00001000
9430 12:11:52.865303 RO MCACHE 2. 0xffffc000 0x00001104
9431 12:11:52.868462 CONSOLE 3. 0xfff7c000 0x00080000
9432 12:11:52.871823 FMAP 4. 0xfff7b000 0x00000452
9433 12:11:52.875168 TIME STAMP 5. 0xfff7a000 0x00000910
9434 12:11:52.878477 VBOOT WORK 6. 0xfff66000 0x00014000
9435 12:11:52.881725 RAMOOPS 7. 0xffe66000 0x00100000
9436 12:11:52.884840 COREBOOT 8. 0xffe64000 0x00002000
9437 12:11:52.888725 IMD small region:
9438 12:11:52.891928 IMD ROOT 0. 0xffffec00 0x00000400
9439 12:11:52.895167 VPD 1. 0xffffeba0 0x0000004c
9440 12:11:52.898519 MMC STATUS 2. 0xffffeb80 0x00000004
9441 12:11:52.905011 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9442 12:11:52.905127 Probing TPM: done!
9443 12:11:52.911798 Connected to device vid:did:rid of 1ae0:0028:00
9444 12:11:52.918566 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9445 12:11:52.921696 Initialized TPM device CR50 revision 0
9446 12:11:52.925314 Checking cr50 for pending updates
9447 12:11:52.930711 Reading cr50 TPM mode
9448 12:11:52.938880 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9449 12:11:52.945605 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9450 12:11:52.986364 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9451 12:11:52.989582 Checking segment from ROM address 0x40100000
9452 12:11:52.992745 Checking segment from ROM address 0x4010001c
9453 12:11:52.999395 Loading segment from ROM address 0x40100000
9454 12:11:52.999483 code (compression=0)
9455 12:11:53.009245 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9456 12:11:53.015561 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9457 12:11:53.015679 it's not compressed!
9458 12:11:53.022287 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9459 12:11:53.029115 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9460 12:11:53.046254 Loading segment from ROM address 0x4010001c
9461 12:11:53.046392 Entry Point 0x80000000
9462 12:11:53.050063 Loaded segments
9463 12:11:53.053165 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9464 12:11:53.059489 Jumping to boot code at 0x80000000(0xffe64000)
9465 12:11:53.066118 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9466 12:11:53.072685 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9467 12:11:53.080529 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9468 12:11:53.084334 Checking segment from ROM address 0x40100000
9469 12:11:53.087524 Checking segment from ROM address 0x4010001c
9470 12:11:53.094010 Loading segment from ROM address 0x40100000
9471 12:11:53.094098 code (compression=1)
9472 12:11:53.101090 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9473 12:11:53.110538 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9474 12:11:53.110732 using LZMA
9475 12:11:53.119472 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9476 12:11:53.125728 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9477 12:11:53.128932 Loading segment from ROM address 0x4010001c
9478 12:11:53.129040 Entry Point 0x54601000
9479 12:11:53.132557 Loaded segments
9480 12:11:53.135606 NOTICE: MT8192 bl31_setup
9481 12:11:53.142643 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9482 12:11:53.145916 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9483 12:11:53.149077 WARNING: region 0:
9484 12:11:53.152643 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 12:11:53.152765 WARNING: region 1:
9486 12:11:53.159593 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9487 12:11:53.162648 WARNING: region 2:
9488 12:11:53.165971 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9489 12:11:53.169140 WARNING: region 3:
9490 12:11:53.172420 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 12:11:53.175664 WARNING: region 4:
9492 12:11:53.182249 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 12:11:53.182334 WARNING: region 5:
9494 12:11:53.185591 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 12:11:53.189316 WARNING: region 6:
9496 12:11:53.192462 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 12:11:53.195633 WARNING: region 7:
9498 12:11:53.198839 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 12:11:53.205552 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9500 12:11:53.208847 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9501 12:11:53.212707 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9502 12:11:53.219043 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9503 12:11:53.222339 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9504 12:11:53.229048 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9505 12:11:53.232388 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9506 12:11:53.235563 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9507 12:11:53.242291 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9508 12:11:53.245416 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9509 12:11:53.249067 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9510 12:11:53.255381 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9511 12:11:53.259058 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9512 12:11:53.265356 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9513 12:11:53.268501 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9514 12:11:53.271811 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9515 12:11:53.279106 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9516 12:11:53.282453 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9517 12:11:53.285060 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9518 12:11:53.292048 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9519 12:11:53.295286 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9520 12:11:53.301857 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9521 12:11:53.305095 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9522 12:11:53.308509 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9523 12:11:53.315006 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9524 12:11:53.318277 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9525 12:11:53.324726 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9526 12:11:53.328007 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9527 12:11:53.334939 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9528 12:11:53.338042 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9529 12:11:53.341843 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9530 12:11:53.347860 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9531 12:11:53.351565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9532 12:11:53.354599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9533 12:11:53.357871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9534 12:11:53.364476 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9535 12:11:53.367970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9536 12:11:53.371231 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9537 12:11:53.374610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9538 12:11:53.381107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9539 12:11:53.384385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9540 12:11:53.387689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9541 12:11:53.391567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9542 12:11:53.398078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9543 12:11:53.401374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9544 12:11:53.404662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9545 12:11:53.411209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9546 12:11:53.414405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9547 12:11:53.417606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9548 12:11:53.423973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9549 12:11:53.427897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9550 12:11:53.434197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9551 12:11:53.437853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9552 12:11:53.440863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9553 12:11:53.447701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9554 12:11:53.450716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9555 12:11:53.457311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9556 12:11:53.460925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9557 12:11:53.467077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9558 12:11:53.470803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9559 12:11:53.477237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9560 12:11:53.480555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9561 12:11:53.483678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9562 12:11:53.490854 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9563 12:11:53.494123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9564 12:11:53.500752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9565 12:11:53.503937 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9566 12:11:53.510546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9567 12:11:53.513844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9568 12:11:53.517106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9569 12:11:53.523561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9570 12:11:53.526840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9571 12:11:53.534031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9572 12:11:53.537339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9573 12:11:53.543732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9574 12:11:53.546846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9575 12:11:53.553614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9576 12:11:53.556754 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9577 12:11:53.560630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9578 12:11:53.566817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9579 12:11:53.570475 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9580 12:11:53.576873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9581 12:11:53.580644 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9582 12:11:53.583826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9583 12:11:53.590335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9584 12:11:53.593553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9585 12:11:53.600054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9586 12:11:53.603434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9587 12:11:53.609953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9588 12:11:53.613909 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9589 12:11:53.620312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9590 12:11:53.623409 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9591 12:11:53.626588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9592 12:11:53.633671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9593 12:11:53.636928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9594 12:11:53.643334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9595 12:11:53.646610 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9596 12:11:53.649851 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9597 12:11:53.656347 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9598 12:11:53.660195 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9599 12:11:53.663257 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9600 12:11:53.669630 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9601 12:11:53.672804 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9602 12:11:53.676559 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9603 12:11:53.682631 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9604 12:11:53.686506 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9605 12:11:53.692893 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9606 12:11:53.696251 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9607 12:11:53.699498 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9608 12:11:53.705868 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9609 12:11:53.709640 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9610 12:11:53.716325 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9611 12:11:53.719466 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9612 12:11:53.722856 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9613 12:11:53.729235 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9614 12:11:53.732462 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9615 12:11:53.735754 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9616 12:11:53.742359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9617 12:11:53.746220 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9618 12:11:53.749431 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9619 12:11:53.755870 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9620 12:11:53.758958 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9621 12:11:53.762554 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9622 12:11:53.765751 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9623 12:11:53.772523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9624 12:11:53.775720 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9625 12:11:53.781913 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9626 12:11:53.785774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9627 12:11:53.788905 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9628 12:11:53.795374 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9629 12:11:53.798825 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9630 12:11:53.805849 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9631 12:11:53.809126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9632 12:11:53.812417 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9633 12:11:53.818852 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9634 12:11:53.822009 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9635 12:11:53.828562 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9636 12:11:53.831810 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9637 12:11:53.835559 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9638 12:11:53.842007 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9639 12:11:53.845205 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9640 12:11:53.848588 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9641 12:11:53.855117 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9642 12:11:53.858284 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9643 12:11:53.865266 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9644 12:11:53.868224 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9645 12:11:53.871657 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9646 12:11:53.878582 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9647 12:11:53.881828 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9648 12:11:53.888496 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9649 12:11:53.891586 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9650 12:11:53.894866 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9651 12:11:53.901493 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9652 12:11:53.904650 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9653 12:11:53.911770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9654 12:11:53.915089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9655 12:11:53.918383 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9656 12:11:53.924751 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9657 12:11:53.927852 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9658 12:11:53.934587 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9659 12:11:53.937761 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9660 12:11:53.941029 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9661 12:11:53.947976 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9662 12:11:53.951318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9663 12:11:53.957897 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9664 12:11:53.961057 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9665 12:11:53.964376 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9666 12:11:53.970614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9667 12:11:53.974307 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9668 12:11:53.980626 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9669 12:11:53.983802 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9670 12:11:53.987504 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9671 12:11:53.994328 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9672 12:11:53.997524 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9673 12:11:54.003989 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9674 12:11:54.007106 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9675 12:11:54.010190 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9676 12:11:54.016899 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9677 12:11:54.020118 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9678 12:11:54.026777 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9679 12:11:54.030034 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9680 12:11:54.033218 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9681 12:11:54.040176 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9682 12:11:54.043531 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9683 12:11:54.050206 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9684 12:11:54.053914 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9685 12:11:54.056627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9686 12:11:54.063090 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9687 12:11:54.066384 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9688 12:11:54.072702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9689 12:11:54.076261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9690 12:11:54.082520 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9691 12:11:54.086151 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9692 12:11:54.089394 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9693 12:11:54.096237 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9694 12:11:54.099296 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9695 12:11:54.106365 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9696 12:11:54.109444 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9697 12:11:54.115476 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9698 12:11:54.118905 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9699 12:11:54.122710 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9700 12:11:54.129100 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9701 12:11:54.132256 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9702 12:11:54.138845 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9703 12:11:54.142149 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9704 12:11:54.148598 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9705 12:11:54.151844 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9706 12:11:54.155045 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9707 12:11:54.162202 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9708 12:11:54.165246 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9709 12:11:54.171813 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9710 12:11:54.174919 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9711 12:11:54.181681 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9712 12:11:54.184811 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9713 12:11:54.187813 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9714 12:11:54.194894 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9715 12:11:54.197901 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9716 12:11:54.204849 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9717 12:11:54.207899 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9718 12:11:54.214347 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9719 12:11:54.217584 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9720 12:11:54.220897 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9721 12:11:54.227446 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9722 12:11:54.230643 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9723 12:11:54.237713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9724 12:11:54.240919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9725 12:11:54.247380 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9726 12:11:54.250625 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9727 12:11:54.253885 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9728 12:11:54.260150 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9729 12:11:54.264142 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9730 12:11:54.266777 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9731 12:11:54.270656 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9732 12:11:54.277283 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9733 12:11:54.280343 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9734 12:11:54.283315 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9735 12:11:54.290357 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9736 12:11:54.293493 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9737 12:11:54.296744 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9738 12:11:54.303575 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9739 12:11:54.306653 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9740 12:11:54.313580 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9741 12:11:54.316730 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9742 12:11:54.320102 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9743 12:11:54.326831 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9744 12:11:54.330138 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9745 12:11:54.333217 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9746 12:11:54.339749 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9747 12:11:54.342923 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9748 12:11:54.349359 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9749 12:11:54.352617 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9750 12:11:54.356400 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9751 12:11:54.362887 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9752 12:11:54.366142 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9753 12:11:54.369278 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9754 12:11:54.375855 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9755 12:11:54.379188 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9756 12:11:54.385488 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9757 12:11:54.389088 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9758 12:11:54.392247 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9759 12:11:54.399266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9760 12:11:54.402413 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9761 12:11:54.409063 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9762 12:11:54.412327 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9763 12:11:54.415412 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9764 12:11:54.421824 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9765 12:11:54.425081 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9766 12:11:54.428383 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9767 12:11:54.435004 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9768 12:11:54.438836 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9769 12:11:54.442000 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9770 12:11:54.445287 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9771 12:11:54.451583 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9772 12:11:54.454839 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9773 12:11:54.458097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9774 12:11:54.461297 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9775 12:11:54.468400 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9776 12:11:54.471673 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9777 12:11:54.474870 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9778 12:11:54.478099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9779 12:11:54.484537 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9780 12:11:54.487635 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9781 12:11:54.491470 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9782 12:11:54.497608 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9783 12:11:54.500787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9784 12:11:54.507686 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9785 12:11:54.510756 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9786 12:11:54.517648 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9787 12:11:54.520810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9788 12:11:54.523944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9789 12:11:54.530575 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9790 12:11:54.533923 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9791 12:11:54.540965 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9792 12:11:54.544012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9793 12:11:54.550770 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9794 12:11:54.553858 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9795 12:11:54.557023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9796 12:11:54.563584 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9797 12:11:54.567490 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9798 12:11:54.573812 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9799 12:11:54.576990 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9800 12:11:54.580189 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9801 12:11:54.586692 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9802 12:11:54.589804 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9803 12:11:54.596754 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9804 12:11:54.599890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9805 12:11:54.606759 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9806 12:11:54.609912 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9807 12:11:54.613023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9808 12:11:54.619247 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9809 12:11:54.623152 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9810 12:11:54.629591 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9811 12:11:54.632841 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9812 12:11:54.636151 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9813 12:11:54.642617 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9814 12:11:54.645984 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9815 12:11:54.652175 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9816 12:11:54.656043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9817 12:11:54.662419 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9818 12:11:54.665719 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9819 12:11:54.668805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9820 12:11:54.675247 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9821 12:11:54.679153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9822 12:11:54.685635 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9823 12:11:54.688936 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9824 12:11:54.692099 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9825 12:11:54.698708 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9826 12:11:54.702168 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9827 12:11:54.708471 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9828 12:11:54.711600 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9829 12:11:54.718528 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9830 12:11:54.721433 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9831 12:11:54.725252 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9832 12:11:54.731451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9833 12:11:54.735324 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9834 12:11:54.741746 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9835 12:11:54.744954 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9836 12:11:54.748162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9837 12:11:54.754760 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9838 12:11:54.758074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9839 12:11:54.764982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9840 12:11:54.767977 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9841 12:11:54.774454 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9842 12:11:54.777720 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9843 12:11:54.784121 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9844 12:11:54.787377 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9845 12:11:54.791366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9846 12:11:54.797651 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9847 12:11:54.800974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9848 12:11:54.807184 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9849 12:11:54.810188 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9850 12:11:54.817206 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9851 12:11:54.820167 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9852 12:11:54.823857 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9853 12:11:54.830108 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9854 12:11:54.833796 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9855 12:11:54.840167 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9856 12:11:54.843204 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9857 12:11:54.849832 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9858 12:11:54.853580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9859 12:11:54.856777 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9860 12:11:54.863238 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9861 12:11:54.866629 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9862 12:11:54.873068 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9863 12:11:54.876343 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9864 12:11:54.882850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9865 12:11:54.886102 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9866 12:11:54.893159 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9867 12:11:54.896403 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9868 12:11:54.899615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9869 12:11:54.906193 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9870 12:11:54.909293 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9871 12:11:54.916178 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9872 12:11:54.919275 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9873 12:11:54.925707 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9874 12:11:54.929399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9875 12:11:54.935805 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9876 12:11:54.938911 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9877 12:11:54.941972 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9878 12:11:54.948913 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9879 12:11:54.952052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9880 12:11:54.958598 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9881 12:11:54.961768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9882 12:11:54.968337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9883 12:11:54.971460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9884 12:11:54.977904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9885 12:11:54.981833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9886 12:11:54.988227 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9887 12:11:54.991473 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9888 12:11:54.994585 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9889 12:11:55.000997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9890 12:11:55.004885 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9891 12:11:55.011309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9892 12:11:55.014525 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9893 12:11:55.020908 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9894 12:11:55.024776 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9895 12:11:55.028343 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9896 12:11:55.034350 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9897 12:11:55.037653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9898 12:11:55.044551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9899 12:11:55.047390 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9900 12:11:55.053926 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9901 12:11:55.057077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9902 12:11:55.060868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9903 12:11:55.067297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9904 12:11:55.070643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9905 12:11:55.077192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9906 12:11:55.080574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9907 12:11:55.087081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9908 12:11:55.090397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9909 12:11:55.096804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9910 12:11:55.100051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9911 12:11:55.106561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9912 12:11:55.109928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9913 12:11:55.116880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9914 12:11:55.119947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9915 12:11:55.126827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9916 12:11:55.130103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9917 12:11:55.136360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9918 12:11:55.140026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9919 12:11:55.146345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9920 12:11:55.149982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9921 12:11:55.156474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9922 12:11:55.159866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9923 12:11:55.166293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9924 12:11:55.169519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9925 12:11:55.175903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9926 12:11:55.179135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9927 12:11:55.185632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9928 12:11:55.188867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9929 12:11:55.196143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9930 12:11:55.198758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9931 12:11:55.205878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9932 12:11:55.209030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9933 12:11:55.215520 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9934 12:11:55.215600 INFO: [APUAPC] vio 0
9935 12:11:55.222556 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9936 12:11:55.226351 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9937 12:11:55.229425 INFO: [APUAPC] D0_APC_0: 0x400510
9938 12:11:55.232599 INFO: [APUAPC] D0_APC_1: 0x0
9939 12:11:55.235935 INFO: [APUAPC] D0_APC_2: 0x1540
9940 12:11:55.239207 INFO: [APUAPC] D0_APC_3: 0x0
9941 12:11:55.242256 INFO: [APUAPC] D1_APC_0: 0xffffffff
9942 12:11:55.246114 INFO: [APUAPC] D1_APC_1: 0xffffffff
9943 12:11:55.249468 INFO: [APUAPC] D1_APC_2: 0x3fffff
9944 12:11:55.252562 INFO: [APUAPC] D1_APC_3: 0x0
9945 12:11:55.255586 INFO: [APUAPC] D2_APC_0: 0xffffffff
9946 12:11:55.258988 INFO: [APUAPC] D2_APC_1: 0xffffffff
9947 12:11:55.262101 INFO: [APUAPC] D2_APC_2: 0x3fffff
9948 12:11:55.265340 INFO: [APUAPC] D2_APC_3: 0x0
9949 12:11:55.268525 INFO: [APUAPC] D3_APC_0: 0xffffffff
9950 12:11:55.271881 INFO: [APUAPC] D3_APC_1: 0xffffffff
9951 12:11:55.275177 INFO: [APUAPC] D3_APC_2: 0x3fffff
9952 12:11:55.278986 INFO: [APUAPC] D3_APC_3: 0x0
9953 12:11:55.282176 INFO: [APUAPC] D4_APC_0: 0xffffffff
9954 12:11:55.285498 INFO: [APUAPC] D4_APC_1: 0xffffffff
9955 12:11:55.288634 INFO: [APUAPC] D4_APC_2: 0x3fffff
9956 12:11:55.291941 INFO: [APUAPC] D4_APC_3: 0x0
9957 12:11:55.295302 INFO: [APUAPC] D5_APC_0: 0xffffffff
9958 12:11:55.298481 INFO: [APUAPC] D5_APC_1: 0xffffffff
9959 12:11:55.301725 INFO: [APUAPC] D5_APC_2: 0x3fffff
9960 12:11:55.304935 INFO: [APUAPC] D5_APC_3: 0x0
9961 12:11:55.307996 INFO: [APUAPC] D6_APC_0: 0xffffffff
9962 12:11:55.311416 INFO: [APUAPC] D6_APC_1: 0xffffffff
9963 12:11:55.314652 INFO: [APUAPC] D6_APC_2: 0x3fffff
9964 12:11:55.314736 INFO: [APUAPC] D6_APC_3: 0x0
9965 12:11:55.321187 INFO: [APUAPC] D7_APC_0: 0xffffffff
9966 12:11:55.324825 INFO: [APUAPC] D7_APC_1: 0xffffffff
9967 12:11:55.327964 INFO: [APUAPC] D7_APC_2: 0x3fffff
9968 12:11:55.328095 INFO: [APUAPC] D7_APC_3: 0x0
9969 12:11:55.331074 INFO: [APUAPC] D8_APC_0: 0xffffffff
9970 12:11:55.338129 INFO: [APUAPC] D8_APC_1: 0xffffffff
9971 12:11:55.341390 INFO: [APUAPC] D8_APC_2: 0x3fffff
9972 12:11:55.341474 INFO: [APUAPC] D8_APC_3: 0x0
9973 12:11:55.344507 INFO: [APUAPC] D9_APC_0: 0xffffffff
9974 12:11:55.348113 INFO: [APUAPC] D9_APC_1: 0xffffffff
9975 12:11:55.351160 INFO: [APUAPC] D9_APC_2: 0x3fffff
9976 12:11:55.354463 INFO: [APUAPC] D9_APC_3: 0x0
9977 12:11:55.357414 INFO: [APUAPC] D10_APC_0: 0xffffffff
9978 12:11:55.361184 INFO: [APUAPC] D10_APC_1: 0xffffffff
9979 12:11:55.367793 INFO: [APUAPC] D10_APC_2: 0x3fffff
9980 12:11:55.367888 INFO: [APUAPC] D10_APC_3: 0x0
9981 12:11:55.370825 INFO: [APUAPC] D11_APC_0: 0xffffffff
9982 12:11:55.377407 INFO: [APUAPC] D11_APC_1: 0xffffffff
9983 12:11:55.380760 INFO: [APUAPC] D11_APC_2: 0x3fffff
9984 12:11:55.380848 INFO: [APUAPC] D11_APC_3: 0x0
9985 12:11:55.387185 INFO: [APUAPC] D12_APC_0: 0xffffffff
9986 12:11:55.390319 INFO: [APUAPC] D12_APC_1: 0xffffffff
9987 12:11:55.393650 INFO: [APUAPC] D12_APC_2: 0x3fffff
9988 12:11:55.397148 INFO: [APUAPC] D12_APC_3: 0x0
9989 12:11:55.400307 INFO: [APUAPC] D13_APC_0: 0xffffffff
9990 12:11:55.403579 INFO: [APUAPC] D13_APC_1: 0xffffffff
9991 12:11:55.406740 INFO: [APUAPC] D13_APC_2: 0x3fffff
9992 12:11:55.410143 INFO: [APUAPC] D13_APC_3: 0x0
9993 12:11:55.413453 INFO: [APUAPC] D14_APC_0: 0xffffffff
9994 12:11:55.416898 INFO: [APUAPC] D14_APC_1: 0xffffffff
9995 12:11:55.420169 INFO: [APUAPC] D14_APC_2: 0x3fffff
9996 12:11:55.423505 INFO: [APUAPC] D14_APC_3: 0x0
9997 12:11:55.426713 INFO: [APUAPC] D15_APC_0: 0xffffffff
9998 12:11:55.430506 INFO: [APUAPC] D15_APC_1: 0xffffffff
9999 12:11:55.433654 INFO: [APUAPC] D15_APC_2: 0x3fffff
10000 12:11:55.436722 INFO: [APUAPC] D15_APC_3: 0x0
10001 12:11:55.436806 INFO: [APUAPC] APC_CON: 0x4
10002 12:11:55.440371 INFO: [NOCDAPC] D0_APC_0: 0x0
10003 12:11:55.443518 INFO: [NOCDAPC] D0_APC_1: 0x0
10004 12:11:55.446535 INFO: [NOCDAPC] D1_APC_0: 0x0
10005 12:11:55.449808 INFO: [NOCDAPC] D1_APC_1: 0xfff
10006 12:11:55.452895 INFO: [NOCDAPC] D2_APC_0: 0x0
10007 12:11:55.456482 INFO: [NOCDAPC] D2_APC_1: 0xfff
10008 12:11:55.459633 INFO: [NOCDAPC] D3_APC_0: 0x0
10009 12:11:55.462834 INFO: [NOCDAPC] D3_APC_1: 0xfff
10010 12:11:55.466700 INFO: [NOCDAPC] D4_APC_0: 0x0
10011 12:11:55.469956 INFO: [NOCDAPC] D4_APC_1: 0xfff
10012 12:11:55.470031 INFO: [NOCDAPC] D5_APC_0: 0x0
10013 12:11:55.473128 INFO: [NOCDAPC] D5_APC_1: 0xfff
10014 12:11:55.476485 INFO: [NOCDAPC] D6_APC_0: 0x0
10015 12:11:55.479641 INFO: [NOCDAPC] D6_APC_1: 0xfff
10016 12:11:55.482916 INFO: [NOCDAPC] D7_APC_0: 0x0
10017 12:11:55.486174 INFO: [NOCDAPC] D7_APC_1: 0xfff
10018 12:11:55.489474 INFO: [NOCDAPC] D8_APC_0: 0x0
10019 12:11:55.492848 INFO: [NOCDAPC] D8_APC_1: 0xfff
10020 12:11:55.495943 INFO: [NOCDAPC] D9_APC_0: 0x0
10021 12:11:55.499315 INFO: [NOCDAPC] D9_APC_1: 0xfff
10022 12:11:55.502670 INFO: [NOCDAPC] D10_APC_0: 0x0
10023 12:11:55.505996 INFO: [NOCDAPC] D10_APC_1: 0xfff
10024 12:11:55.509099 INFO: [NOCDAPC] D11_APC_0: 0x0
10025 12:11:55.512230 INFO: [NOCDAPC] D11_APC_1: 0xfff
10026 12:11:55.512308 INFO: [NOCDAPC] D12_APC_0: 0x0
10027 12:11:55.516075 INFO: [NOCDAPC] D12_APC_1: 0xfff
10028 12:11:55.519363 INFO: [NOCDAPC] D13_APC_0: 0x0
10029 12:11:55.522563 INFO: [NOCDAPC] D13_APC_1: 0xfff
10030 12:11:55.525778 INFO: [NOCDAPC] D14_APC_0: 0x0
10031 12:11:55.529029 INFO: [NOCDAPC] D14_APC_1: 0xfff
10032 12:11:55.532316 INFO: [NOCDAPC] D15_APC_0: 0x0
10033 12:11:55.535967 INFO: [NOCDAPC] D15_APC_1: 0xfff
10034 12:11:55.539171 INFO: [NOCDAPC] APC_CON: 0x4
10035 12:11:55.542360 INFO: [APUAPC] set_apusys_apc done
10036 12:11:55.545533 INFO: [DEVAPC] devapc_init done
10037 12:11:55.548717 INFO: GICv3 without legacy support detected.
10038 12:11:55.551933 INFO: ARM GICv3 driver initialized in EL3
10039 12:11:55.555880 INFO: Maximum SPI INTID supported: 639
10040 12:11:55.562015 INFO: BL31: Initializing runtime services
10041 12:11:55.565681 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10042 12:11:55.568792 INFO: SPM: enable CPC mode
10043 12:11:55.575127 INFO: mcdi ready for mcusys-off-idle and system suspend
10044 12:11:55.578528 INFO: BL31: Preparing for EL3 exit to normal world
10045 12:11:55.582293 INFO: Entry point address = 0x80000000
10046 12:11:55.585572 INFO: SPSR = 0x8
10047 12:11:55.590857
10048 12:11:55.590928
10049 12:11:55.590995
10050 12:11:55.594102 Starting depthcharge on Spherion...
10051 12:11:55.594171
10052 12:11:55.594232 Wipe memory regions:
10053 12:11:55.594291
10054 12:11:55.594902 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10055 12:11:55.595002 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10056 12:11:55.595089 Setting prompt string to ['asurada:']
10057 12:11:55.595387 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10058 12:11:55.597302 [0x00000040000000, 0x00000054600000)
10059 12:11:55.719243
10060 12:11:55.719381 [0x00000054660000, 0x00000080000000)
10061 12:11:55.979360
10062 12:11:55.979497 [0x000000821a7280, 0x000000ffe64000)
10063 12:11:56.723177
10064 12:11:56.723314 [0x00000100000000, 0x00000240000000)
10065 12:11:58.610636
10066 12:11:58.614036 Initializing XHCI USB controller at 0x11200000.
10067 12:11:59.652973
10068 12:11:59.655760 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10069 12:11:59.655882
10070 12:11:59.655982
10071 12:11:59.656084
10072 12:11:59.656378 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 12:11:59.756721 asurada: tftpboot 192.168.201.1 10605430/tftp-deploy-ez8uklv8/kernel/image.itb 10605430/tftp-deploy-ez8uklv8/kernel/cmdline
10075 12:11:59.756901 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10076 12:11:59.757012 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10077 12:11:59.761526 tftpboot 192.168.201.1 10605430/tftp-deploy-ez8uklv8/kernel/image.itp-deploy-ez8uklv8/kernel/cmdline
10078 12:11:59.761616
10079 12:11:59.761685 Waiting for link
10080 12:11:59.922310
10081 12:11:59.922447 R8152: Initializing
10082 12:11:59.922532
10083 12:11:59.925330 Version 6 (ocp_data = 5c30)
10084 12:11:59.925451
10085 12:11:59.928356 R8152: Done initializing
10086 12:11:59.928460
10087 12:11:59.928554 Adding net device
10088 12:12:01.862445
10089 12:12:01.862603 done.
10090 12:12:01.862712
10091 12:12:01.862780 MAC: 00:24:32:30:7c:7b
10092 12:12:01.862844
10093 12:12:01.865987 Sending DHCP discover... done.
10094 12:12:01.866075
10095 12:12:01.869502 Waiting for reply... done.
10096 12:12:01.869593
10097 12:12:01.872388 Sending DHCP request... done.
10098 12:12:01.872471
10099 12:12:01.872542 Waiting for reply... done.
10100 12:12:01.872619
10101 12:12:01.875815 My ip is 192.168.201.14
10102 12:12:01.875937
10103 12:12:01.878928 The DHCP server ip is 192.168.201.1
10104 12:12:01.879054
10105 12:12:01.882491 TFTP server IP predefined by user: 192.168.201.1
10106 12:12:01.882618
10107 12:12:01.888690 Bootfile predefined by user: 10605430/tftp-deploy-ez8uklv8/kernel/image.itb
10108 12:12:01.888799
10109 12:12:01.892320 Sending tftp read request... done.
10110 12:12:01.892417
10111 12:12:01.895322 Waiting for the transfer...
10112 12:12:01.895435
10113 12:12:02.442486 00000000 ################################################################
10114 12:12:02.442654
10115 12:12:02.988460 00080000 ################################################################
10116 12:12:02.988619
10117 12:12:03.524798 00100000 ################################################################
10118 12:12:03.524945
10119 12:12:04.050257 00180000 ################################################################
10120 12:12:04.050451
10121 12:12:04.624979 00200000 ################################################################
10122 12:12:04.625136
10123 12:12:05.169732 00280000 ################################################################
10124 12:12:05.169872
10125 12:12:05.711830 00300000 ################################################################
10126 12:12:05.712055
10127 12:12:06.249439 00380000 ################################################################
10128 12:12:06.249648
10129 12:12:06.793269 00400000 ################################################################
10130 12:12:06.793426
10131 12:12:07.335769 00480000 ################################################################
10132 12:12:07.335957
10133 12:12:07.925221 00500000 ################################################################
10134 12:12:07.925359
10135 12:12:08.460150 00580000 ################################################################
10136 12:12:08.460292
10137 12:12:09.011063 00600000 ################################################################
10138 12:12:09.011590
10139 12:12:09.661585 00680000 ################################################################
10140 12:12:09.661738
10141 12:12:10.247852 00700000 ################################################################
10142 12:12:10.248001
10143 12:12:10.814144 00780000 ################################################################
10144 12:12:10.814291
10145 12:12:11.434699 00800000 ################################################################
10146 12:12:11.434884
10147 12:12:11.990712 00880000 ################################################################
10148 12:12:11.990873
10149 12:12:12.632689 00900000 ################################################################
10150 12:12:12.633250
10151 12:12:13.270269 00980000 ################################################################
10152 12:12:13.270412
10153 12:12:13.943310 00a00000 ################################################################
10154 12:12:13.943815
10155 12:12:14.549993 00a80000 ################################################################
10156 12:12:14.550146
10157 12:12:15.136141 00b00000 ################################################################
10158 12:12:15.136782
10159 12:12:15.752504 00b80000 ################################################################
10160 12:12:15.752681
10161 12:12:16.333888 00c00000 ################################################################
10162 12:12:16.334417
10163 12:12:16.984944 00c80000 ################################################################
10164 12:12:16.985472
10165 12:12:17.595798 00d00000 ################################################################
10166 12:12:17.596374
10167 12:12:18.177563 00d80000 ################################################################
10168 12:12:18.177746
10169 12:12:18.775089 00e00000 ################################################################
10170 12:12:18.775615
10171 12:12:19.399903 00e80000 ################################################################
10172 12:12:19.400057
10173 12:12:19.979503 00f00000 ################################################################
10174 12:12:19.979656
10175 12:12:20.547611 00f80000 ################################################################
10176 12:12:20.547790
10177 12:12:21.092006 01000000 ################################################################
10178 12:12:21.092210
10179 12:12:21.641276 01080000 ################################################################
10180 12:12:21.641430
10181 12:12:22.197784 01100000 ################################################################
10182 12:12:22.198039
10183 12:12:22.742528 01180000 ################################################################
10184 12:12:22.743217
10185 12:12:23.317074 01200000 ################################################################
10186 12:12:23.317211
10187 12:12:23.842456 01280000 ################################################################
10188 12:12:23.842598
10189 12:12:24.382685 01300000 ################################################################
10190 12:12:24.382853
10191 12:12:24.919083 01380000 ################################################################
10192 12:12:24.919233
10193 12:12:25.449764 01400000 ################################################################
10194 12:12:25.449917
10195 12:12:25.986154 01480000 ################################################################
10196 12:12:25.986304
10197 12:12:26.588898 01500000 ################################################################
10198 12:12:26.589533
10199 12:12:27.204495 01580000 ################################################################
10200 12:12:27.205008
10201 12:12:27.767487 01600000 ################################################################
10202 12:12:27.767656
10203 12:12:28.316276 01680000 ################################################################
10204 12:12:28.316471
10205 12:12:28.841116 01700000 ################################################################
10206 12:12:28.841298
10207 12:12:29.381535 01780000 ################################################################
10208 12:12:29.381737
10209 12:12:29.919956 01800000 ################################################################
10210 12:12:29.920131
10211 12:12:30.455237 01880000 ################################################################
10212 12:12:30.455381
10213 12:12:30.992554 01900000 ################################################################
10214 12:12:30.992714
10215 12:12:31.573895 01980000 ################################################################
10216 12:12:31.574091
10217 12:12:32.133007 01a00000 ################################################################ done.
10218 12:12:32.133165
10219 12:12:32.136214 The bootfile was 27779746 bytes long.
10220 12:12:32.136294
10221 12:12:32.139552 Sending tftp read request... done.
10222 12:12:32.139637
10223 12:12:32.142848 Waiting for the transfer...
10224 12:12:32.142938
10225 12:12:32.143007 00000000 # done.
10226 12:12:32.143073
10227 12:12:32.152658 Command line loaded dynamically from TFTP file: 10605430/tftp-deploy-ez8uklv8/kernel/cmdline
10228 12:12:32.152753
10229 12:12:32.169184 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10230 12:12:32.172583
10231 12:12:32.172739 Loading FIT.
10232 12:12:32.172846
10233 12:12:32.175889 Image ramdisk-1 has 17636166 bytes.
10234 12:12:32.176000
10235 12:12:32.179122 Image fdt-1 has 46924 bytes.
10236 12:12:32.179205
10237 12:12:32.182523 Image kernel-1 has 10094623 bytes.
10238 12:12:32.182608
10239 12:12:32.189087 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10240 12:12:32.189183
10241 12:12:32.208833 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10242 12:12:32.208937
10243 12:12:32.212477 Choosing best match conf-1 for compat google,spherion-rev2.
10244 12:12:32.216705
10245 12:12:32.221641 Connected to device vid:did:rid of 1ae0:0028:00
10246 12:12:32.228290
10247 12:12:32.231690 tpm_get_response: command 0x17b, return code 0x0
10248 12:12:32.231836
10249 12:12:32.234880 ec_init: CrosEC protocol v3 supported (256, 248)
10250 12:12:32.240274
10251 12:12:32.243360 tpm_cleanup: add release locality here.
10252 12:12:32.243501
10253 12:12:32.243611 Shutting down all USB controllers.
10254 12:12:32.246708
10255 12:12:32.246825 Removing current net device
10256 12:12:32.246923
10257 12:12:32.253194 Exiting depthcharge with code 4 at timestamp: 65928660
10258 12:12:32.253306
10259 12:12:32.256518 LZMA decompressing kernel-1 to 0x821a6718
10260 12:12:32.256634
10261 12:12:32.259856 LZMA decompressing kernel-1 to 0x40000000
10262 12:12:33.527581
10263 12:12:33.527782 jumping to kernel
10264 12:12:33.528246 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10265 12:12:33.528359 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10266 12:12:33.528441 Setting prompt string to ['Linux version [0-9]']
10267 12:12:33.528513 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10268 12:12:33.528587 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10269 12:12:33.609692
10270 12:12:33.612730 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10271 12:12:33.616535 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10272 12:12:33.616775 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10273 12:12:33.616909 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10274 12:12:33.617032 Using line separator: #'\n'#
10275 12:12:33.617102 No login prompt set.
10276 12:12:33.617165 Parsing kernel messages
10277 12:12:33.617224 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10278 12:12:33.617334 [login-action] Waiting for messages, (timeout 00:03:47)
10279 12:12:33.635817 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1614807-arm64-gcc-10-defconfig-arm64-chromebook-v94q4) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023
10280 12:12:33.638840 [ 0.000000] random: crng init done
10281 12:12:33.642478 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10282 12:12:33.645342 [ 0.000000] efi: UEFI not found.
10283 12:12:33.655794 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10284 12:12:33.662515 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10285 12:12:33.672063 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10286 12:12:33.682041 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10287 12:12:33.688611 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10288 12:12:33.694857 [ 0.000000] printk: bootconsole [mtk8250] enabled
10289 12:12:33.701838 [ 0.000000] NUMA: No NUMA configuration found
10290 12:12:33.708535 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10291 12:12:33.711465 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10292 12:12:33.714662 [ 0.000000] Zone ranges:
10293 12:12:33.721118 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10294 12:12:33.724517 [ 0.000000] DMA32 empty
10295 12:12:33.731125 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10296 12:12:33.734843 [ 0.000000] Movable zone start for each node
10297 12:12:33.737760 [ 0.000000] Early memory node ranges
10298 12:12:33.744378 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10299 12:12:33.750868 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10300 12:12:33.757428 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10301 12:12:33.764055 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10302 12:12:33.770731 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10303 12:12:33.777411 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10304 12:12:33.833555 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10305 12:12:33.840371 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10306 12:12:33.846329 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10307 12:12:33.849753 [ 0.000000] psci: probing for conduit method from DT.
10308 12:12:33.856367 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10309 12:12:33.860009 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10310 12:12:33.866558 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10311 12:12:33.869578 [ 0.000000] psci: SMC Calling Convention v1.2
10312 12:12:33.876050 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10313 12:12:33.879607 [ 0.000000] Detected VIPT I-cache on CPU0
10314 12:12:33.886400 [ 0.000000] CPU features: detected: GIC system register CPU interface
10315 12:12:33.892408 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10316 12:12:33.899592 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10317 12:12:33.905803 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10318 12:12:33.915537 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10319 12:12:33.922436 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10320 12:12:33.925517 [ 0.000000] alternatives: applying boot alternatives
10321 12:12:33.932463 [ 0.000000] Fallback order for Node 0: 0
10322 12:12:33.938898 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10323 12:12:33.942377 [ 0.000000] Policy zone: Normal
10324 12:12:33.961815 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10325 12:12:33.971928 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10326 12:12:33.983264 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10327 12:12:33.993538 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10328 12:12:33.999490 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10329 12:12:34.003012 <6>[ 0.000000] software IO TLB: area num 8.
10330 12:12:34.059609 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10331 12:12:34.208964 <6>[ 0.000000] Memory: 7955724K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397044K reserved, 32768K cma-reserved)
10332 12:12:34.215308 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10333 12:12:34.222251 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10334 12:12:34.225652 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10335 12:12:34.231967 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10336 12:12:34.238301 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10337 12:12:34.241795 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10338 12:12:34.251812 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10339 12:12:34.258433 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10340 12:12:34.264796 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10341 12:12:34.271484 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10342 12:12:34.274484 <6>[ 0.000000] GICv3: 608 SPIs implemented
10343 12:12:34.278035 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10344 12:12:34.284518 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10345 12:12:34.287532 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10346 12:12:34.294300 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10347 12:12:34.307931 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10348 12:12:34.320723 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10349 12:12:34.327594 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10350 12:12:34.335883 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10351 12:12:34.348684 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10352 12:12:34.355557 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10353 12:12:34.362266 <6>[ 0.009227] Console: colour dummy device 80x25
10354 12:12:34.371909 <6>[ 0.013954] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10355 12:12:34.378331 <6>[ 0.024396] pid_max: default: 32768 minimum: 301
10356 12:12:34.382038 <6>[ 0.029263] LSM: Security Framework initializing
10357 12:12:34.388625 <6>[ 0.034200] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10358 12:12:34.398141 <6>[ 0.042014] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10359 12:12:34.407913 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10360 12:12:34.414498 <6>[ 0.058898] cblist_init_generic: Setting shift to 3 and lim to 1.
10361 12:12:34.418070 <6>[ 0.065236] cblist_init_generic: Setting shift to 3 and lim to 1.
10362 12:12:34.424374 <6>[ 0.071684] rcu: Hierarchical SRCU implementation.
10363 12:12:34.430989 <6>[ 0.076729] rcu: Max phase no-delay instances is 1000.
10364 12:12:34.437709 <6>[ 0.083747] EFI services will not be available.
10365 12:12:34.441187 <6>[ 0.088748] smp: Bringing up secondary CPUs ...
10366 12:12:34.448923 <6>[ 0.093828] Detected VIPT I-cache on CPU1
10367 12:12:34.455753 <6>[ 0.093899] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10368 12:12:34.462096 <6>[ 0.093930] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10369 12:12:34.465754 <6>[ 0.094262] Detected VIPT I-cache on CPU2
10370 12:12:34.472305 <6>[ 0.094311] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10371 12:12:34.481927 <6>[ 0.094326] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10372 12:12:34.485685 <6>[ 0.094582] Detected VIPT I-cache on CPU3
10373 12:12:34.491739 <6>[ 0.094627] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10374 12:12:34.498333 <6>[ 0.094641] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10375 12:12:34.501705 <6>[ 0.094948] CPU features: detected: Spectre-v4
10376 12:12:34.508503 <6>[ 0.094955] CPU features: detected: Spectre-BHB
10377 12:12:34.511516 <6>[ 0.094961] Detected PIPT I-cache on CPU4
10378 12:12:34.517940 <6>[ 0.095018] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10379 12:12:34.524637 <6>[ 0.095034] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10380 12:12:34.531324 <6>[ 0.095333] Detected PIPT I-cache on CPU5
10381 12:12:34.538106 <6>[ 0.095396] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10382 12:12:34.544397 <6>[ 0.095412] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10383 12:12:34.547706 <6>[ 0.095700] Detected PIPT I-cache on CPU6
10384 12:12:34.557451 <6>[ 0.095765] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10385 12:12:34.564356 <6>[ 0.095781] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10386 12:12:34.567294 <6>[ 0.096082] Detected PIPT I-cache on CPU7
10387 12:12:34.573838 <6>[ 0.096142] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10388 12:12:34.580553 <6>[ 0.096158] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10389 12:12:34.584080 <6>[ 0.096205] smp: Brought up 1 node, 8 CPUs
10390 12:12:34.590779 <6>[ 0.237495] SMP: Total of 8 processors activated.
10391 12:12:34.597007 <6>[ 0.242446] CPU features: detected: 32-bit EL0 Support
10392 12:12:34.603823 <6>[ 0.247809] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10393 12:12:34.610596 <6>[ 0.256609] CPU features: detected: Common not Private translations
10394 12:12:34.617061 <6>[ 0.263125] CPU features: detected: CRC32 instructions
10395 12:12:34.623620 <6>[ 0.268476] CPU features: detected: RCpc load-acquire (LDAPR)
10396 12:12:34.626723 <6>[ 0.274436] CPU features: detected: LSE atomic instructions
10397 12:12:34.633412 <6>[ 0.280217] CPU features: detected: Privileged Access Never
10398 12:12:34.640370 <6>[ 0.285997] CPU features: detected: RAS Extension Support
10399 12:12:34.646349 <6>[ 0.291605] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10400 12:12:34.649861 <6>[ 0.298828] CPU: All CPU(s) started at EL2
10401 12:12:34.656097 <6>[ 0.303171] alternatives: applying system-wide alternatives
10402 12:12:34.666389 <6>[ 0.313878] devtmpfs: initialized
10403 12:12:34.682173 <6>[ 0.322699] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10404 12:12:34.688379 <6>[ 0.332664] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10405 12:12:34.694929 <6>[ 0.340886] pinctrl core: initialized pinctrl subsystem
10406 12:12:34.698519 <6>[ 0.347541] DMI not present or invalid.
10407 12:12:34.705001 <6>[ 0.351946] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10408 12:12:34.714732 <6>[ 0.358835] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10409 12:12:34.721256 <6>[ 0.366417] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10410 12:12:34.731515 <6>[ 0.374640] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10411 12:12:34.738065 <6>[ 0.382877] audit: initializing netlink subsys (disabled)
10412 12:12:34.744492 <5>[ 0.388574] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10413 12:12:34.751006 <6>[ 0.389285] thermal_sys: Registered thermal governor 'step_wise'
10414 12:12:34.757429 <6>[ 0.396541] thermal_sys: Registered thermal governor 'power_allocator'
10415 12:12:34.760891 <6>[ 0.402797] cpuidle: using governor menu
10416 12:12:34.767357 <6>[ 0.413756] NET: Registered PF_QIPCRTR protocol family
10417 12:12:34.774080 <6>[ 0.419251] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10418 12:12:34.780445 <6>[ 0.426352] ASID allocator initialised with 32768 entries
10419 12:12:34.784229 <6>[ 0.432911] Serial: AMBA PL011 UART driver
10420 12:12:34.794382 <4>[ 0.441582] Trying to register duplicate clock ID: 134
10421 12:12:34.848312 <6>[ 0.498639] KASLR enabled
10422 12:12:34.862396 <6>[ 0.506316] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10423 12:12:34.868753 <6>[ 0.513329] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10424 12:12:34.875657 <6>[ 0.519816] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10425 12:12:34.882022 <6>[ 0.526824] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10426 12:12:34.888643 <6>[ 0.533314] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10427 12:12:34.895087 <6>[ 0.540317] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10428 12:12:34.901838 <6>[ 0.546802] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10429 12:12:34.908607 <6>[ 0.553805] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10430 12:12:34.911514 <6>[ 0.561270] ACPI: Interpreter disabled.
10431 12:12:34.920636 <6>[ 0.567670] iommu: Default domain type: Translated
10432 12:12:34.927410 <6>[ 0.572784] iommu: DMA domain TLB invalidation policy: strict mode
10433 12:12:34.930449 <5>[ 0.579445] SCSI subsystem initialized
10434 12:12:34.936935 <6>[ 0.583678] usbcore: registered new interface driver usbfs
10435 12:12:34.943603 <6>[ 0.589410] usbcore: registered new interface driver hub
10436 12:12:34.946702 <6>[ 0.594961] usbcore: registered new device driver usb
10437 12:12:34.954020 <6>[ 0.601069] pps_core: LinuxPPS API ver. 1 registered
10438 12:12:34.963914 <6>[ 0.606265] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10439 12:12:34.966964 <6>[ 0.615607] PTP clock support registered
10440 12:12:34.970318 <6>[ 0.619846] EDAC MC: Ver: 3.0.0
10441 12:12:34.977619 <6>[ 0.625026] FPGA manager framework
10442 12:12:34.984459 <6>[ 0.628703] Advanced Linux Sound Architecture Driver Initialized.
10443 12:12:34.987381 <6>[ 0.635470] vgaarb: loaded
10444 12:12:34.994600 <6>[ 0.638643] clocksource: Switched to clocksource arch_sys_counter
10445 12:12:34.997651 <5>[ 0.645094] VFS: Disk quotas dquot_6.6.0
10446 12:12:35.004217 <6>[ 0.649276] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10447 12:12:35.007655 <6>[ 0.656465] pnp: PnP ACPI: disabled
10448 12:12:35.015610 <6>[ 0.663106] NET: Registered PF_INET protocol family
10449 12:12:35.025728 <6>[ 0.668688] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10450 12:12:35.037080 <6>[ 0.680960] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10451 12:12:35.046746 <6>[ 0.689774] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10452 12:12:35.053126 <6>[ 0.697743] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10453 12:12:35.063415 <6>[ 0.706440] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10454 12:12:35.069603 <6>[ 0.716182] TCP: Hash tables configured (established 65536 bind 65536)
10455 12:12:35.076682 <6>[ 0.723040] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10456 12:12:35.086660 <6>[ 0.730239] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10457 12:12:35.093114 <6>[ 0.737936] NET: Registered PF_UNIX/PF_LOCAL protocol family
10458 12:12:35.099675 <6>[ 0.744100] RPC: Registered named UNIX socket transport module.
10459 12:12:35.102657 <6>[ 0.750251] RPC: Registered udp transport module.
10460 12:12:35.106051 <6>[ 0.755180] RPC: Registered tcp transport module.
10461 12:12:35.116549 <6>[ 0.760111] RPC: Registered tcp NFSv4.1 backchannel transport module.
10462 12:12:35.119573 <6>[ 0.766778] PCI: CLS 0 bytes, default 64
10463 12:12:35.122593 <6>[ 0.771150] Unpacking initramfs...
10464 12:12:35.139629 <6>[ 0.783213] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10465 12:12:35.149136 <6>[ 0.791876] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10466 12:12:35.152863 <6>[ 0.800692] kvm [1]: IPA Size Limit: 40 bits
10467 12:12:35.159229 <6>[ 0.805217] kvm [1]: GICv3: no GICV resource entry
10468 12:12:35.162185 <6>[ 0.810239] kvm [1]: disabling GICv2 emulation
10469 12:12:35.169047 <6>[ 0.814924] kvm [1]: GIC system register CPU interface enabled
10470 12:12:35.172426 <6>[ 0.821098] kvm [1]: vgic interrupt IRQ18
10471 12:12:35.179300 <6>[ 0.826750] kvm [1]: VHE mode initialized successfully
10472 12:12:35.186054 <5>[ 0.833144] Initialise system trusted keyrings
10473 12:12:35.192897 <6>[ 0.837942] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10474 12:12:35.201219 <6>[ 0.847944] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10475 12:12:35.207522 <5>[ 0.854332] NFS: Registering the id_resolver key type
10476 12:12:35.210666 <5>[ 0.859632] Key type id_resolver registered
10477 12:12:35.217327 <5>[ 0.864047] Key type id_legacy registered
10478 12:12:35.224133 <6>[ 0.868327] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10479 12:12:35.230666 <6>[ 0.875251] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10480 12:12:35.237263 <6>[ 0.882982] 9p: Installing v9fs 9p2000 file system support
10481 12:12:35.274275 <5>[ 0.921725] Key type asymmetric registered
10482 12:12:35.277661 <5>[ 0.926055] Asymmetric key parser 'x509' registered
10483 12:12:35.287504 <6>[ 0.931204] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10484 12:12:35.290835 <6>[ 0.938849] io scheduler mq-deadline registered
10485 12:12:35.294246 <6>[ 0.943617] io scheduler kyber registered
10486 12:12:35.312923 <6>[ 0.960525] EINJ: ACPI disabled.
10487 12:12:35.345058 <4>[ 0.985624] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10488 12:12:35.354695 <4>[ 0.996256] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10489 12:12:35.369898 <6>[ 1.016959] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10490 12:12:35.377768 <6>[ 1.025011] printk: console [ttyS0] disabled
10491 12:12:35.405584 <6>[ 1.049659] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10492 12:12:35.411887 <6>[ 1.059138] printk: console [ttyS0] enabled
10493 12:12:35.415396 <6>[ 1.059138] printk: console [ttyS0] enabled
10494 12:12:35.421975 <6>[ 1.068035] printk: bootconsole [mtk8250] disabled
10495 12:12:35.425531 <6>[ 1.068035] printk: bootconsole [mtk8250] disabled
10496 12:12:35.432152 <6>[ 1.079280] SuperH (H)SCI(F) driver initialized
10497 12:12:35.435406 <6>[ 1.084548] msm_serial: driver initialized
10498 12:12:35.449696 <6>[ 1.093495] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10499 12:12:35.459392 <6>[ 1.102048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10500 12:12:35.465959 <6>[ 1.110597] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10501 12:12:35.476218 <6>[ 1.119224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10502 12:12:35.485538 <6>[ 1.127930] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10503 12:12:35.492408 <6>[ 1.136643] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10504 12:12:35.502129 <6>[ 1.145184] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10505 12:12:35.508641 <6>[ 1.153989] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10506 12:12:35.518777 <6>[ 1.162531] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10507 12:12:35.530479 <6>[ 1.178122] loop: module loaded
10508 12:12:35.537243 <6>[ 1.184239] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10509 12:12:35.560734 <4>[ 1.207764] mtk-pmic-keys: Failed to locate of_node [id: -1]
10510 12:12:35.567390 <6>[ 1.214808] megasas: 07.719.03.00-rc1
10511 12:12:35.576814 <6>[ 1.224503] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10512 12:12:35.587041 <6>[ 1.234021] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10513 12:12:35.603856 <6>[ 1.250832] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10514 12:12:35.660555 <6>[ 1.301165] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10515 12:12:35.856807 <6>[ 1.503641] Freeing initrd memory: 17216K
10516 12:12:35.867263 <6>[ 1.513958] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10517 12:12:35.878055 <6>[ 1.524939] tun: Universal TUN/TAP device driver, 1.6
10518 12:12:35.881111 <6>[ 1.531011] thunder_xcv, ver 1.0
10519 12:12:35.884533 <6>[ 1.534506] thunder_bgx, ver 1.0
10520 12:12:35.887683 <6>[ 1.538004] nicpf, ver 1.0
10521 12:12:35.898044 <6>[ 1.542011] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10522 12:12:35.901687 <6>[ 1.549487] hns3: Copyright (c) 2017 Huawei Corporation.
10523 12:12:35.908643 <6>[ 1.555074] hclge is initializing
10524 12:12:35.911912 <6>[ 1.558655] e1000: Intel(R) PRO/1000 Network Driver
10525 12:12:35.918407 <6>[ 1.563785] e1000: Copyright (c) 1999-2006 Intel Corporation.
10526 12:12:35.921723 <6>[ 1.569797] e1000e: Intel(R) PRO/1000 Network Driver
10527 12:12:35.927996 <6>[ 1.575013] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10528 12:12:35.934993 <6>[ 1.581200] igb: Intel(R) Gigabit Ethernet Network Driver
10529 12:12:35.941714 <6>[ 1.586850] igb: Copyright (c) 2007-2014 Intel Corporation.
10530 12:12:35.948332 <6>[ 1.592686] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10531 12:12:35.954863 <6>[ 1.599205] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10532 12:12:35.957997 <6>[ 1.605665] sky2: driver version 1.30
10533 12:12:35.964539 <6>[ 1.610649] VFIO - User Level meta-driver version: 0.3
10534 12:12:35.971947 <6>[ 1.618862] usbcore: registered new interface driver usb-storage
10535 12:12:35.978484 <6>[ 1.625303] usbcore: registered new device driver onboard-usb-hub
10536 12:12:35.986889 <6>[ 1.634393] mt6397-rtc mt6359-rtc: registered as rtc0
10537 12:12:35.997160 <6>[ 1.639859] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-06T12:12:41 UTC (1686053561)
10538 12:12:36.000021 <6>[ 1.649412] i2c_dev: i2c /dev entries driver
10539 12:12:36.016857 <6>[ 1.660980] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10540 12:12:36.023695 <6>[ 1.671162] sdhci: Secure Digital Host Controller Interface driver
10541 12:12:36.030208 <6>[ 1.677601] sdhci: Copyright(c) Pierre Ossman
10542 12:12:36.037268 <6>[ 1.682994] Synopsys Designware Multimedia Card Interface Driver
10543 12:12:36.040281 <6>[ 1.689602] mmc0: CQHCI version 5.10
10544 12:12:36.047226 <6>[ 1.690137] sdhci-pltfm: SDHCI platform and OF driver helper
10545 12:12:36.054398 <6>[ 1.701445] ledtrig-cpu: registered to indicate activity on CPUs
10546 12:12:36.065050 <6>[ 1.708781] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10547 12:12:36.068108 <6>[ 1.716171] usbcore: registered new interface driver usbhid
10548 12:12:36.075101 <6>[ 1.722003] usbhid: USB HID core driver
10549 12:12:36.081963 <6>[ 1.726243] spi_master spi0: will run message pump with realtime priority
10550 12:12:36.126600 <6>[ 1.767312] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10551 12:12:36.145733 <6>[ 1.782909] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10552 12:12:36.149318 <6>[ 1.796499] mmc0: Command Queue Engine enabled
10553 12:12:36.155919 <6>[ 1.798102] cros-ec-spi spi0.0: Chrome EC device registered
10554 12:12:36.162757 <6>[ 1.801237] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10555 12:12:36.165763 <6>[ 1.814388] mmcblk0: mmc0:0001 DA4128 116 GiB
10556 12:12:36.177168 <6>[ 1.824755] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10557 12:12:36.187319 <6>[ 1.825279] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10558 12:12:36.193948 <6>[ 1.832148] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10559 12:12:36.197590 <6>[ 1.842137] NET: Registered PF_PACKET protocol family
10560 12:12:36.203698 <6>[ 1.845901] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10561 12:12:36.207157 <6>[ 1.850671] 9pnet: Installing 9P2000 support
10562 12:12:36.213483 <6>[ 1.856374] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10563 12:12:36.220520 <5>[ 1.860322] Key type dns_resolver registered
10564 12:12:36.223884 <6>[ 1.872023] registered taskstats version 1
10565 12:12:36.230365 <5>[ 1.876470] Loading compiled-in X.509 certificates
10566 12:12:36.267335 <4>[ 1.908255] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10567 12:12:36.277593 <4>[ 1.918974] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 12:12:36.287780 <3>[ 1.932047] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10569 12:12:36.300554 <6>[ 1.947611] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10570 12:12:36.307147 <6>[ 1.954429] xhci-mtk 11200000.usb: xHCI Host Controller
10571 12:12:36.313539 <6>[ 1.959937] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10572 12:12:36.323994 <6>[ 1.967809] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10573 12:12:36.330821 <6>[ 1.977253] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10574 12:12:36.337415 <6>[ 1.983341] xhci-mtk 11200000.usb: xHCI Host Controller
10575 12:12:36.343616 <6>[ 1.988925] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10576 12:12:36.350152 <6>[ 1.996595] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10577 12:12:36.357279 <6>[ 2.004497] hub 1-0:1.0: USB hub found
10578 12:12:36.360359 <6>[ 2.008537] hub 1-0:1.0: 1 port detected
10579 12:12:36.370480 <6>[ 2.012887] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10580 12:12:36.373622 <6>[ 2.021708] hub 2-0:1.0: USB hub found
10581 12:12:36.376707 <6>[ 2.025744] hub 2-0:1.0: 1 port detected
10582 12:12:36.385690 <6>[ 2.032844] mtk-msdc 11f70000.mmc: Got CD GPIO
10583 12:12:36.403046 <6>[ 2.047149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10584 12:12:36.409603 <6>[ 2.055171] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10585 12:12:36.419635 <4>[ 2.063160] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10586 12:12:36.429590 <6>[ 2.072813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10587 12:12:36.436330 <6>[ 2.080895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10588 12:12:36.445879 <6>[ 2.088935] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10589 12:12:36.452471 <6>[ 2.096853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10590 12:12:36.459015 <6>[ 2.104674] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10591 12:12:36.469308 <6>[ 2.112502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10592 12:12:36.478989 <6>[ 2.123283] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10593 12:12:36.485873 <6>[ 2.131674] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10594 12:12:36.496021 <6>[ 2.140019] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10595 12:12:36.505792 <6>[ 2.148363] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10596 12:12:36.512464 <6>[ 2.156705] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10597 12:12:36.522550 <6>[ 2.165048] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10598 12:12:36.528858 <6>[ 2.173391] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10599 12:12:36.538788 <6>[ 2.181734] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10600 12:12:36.545687 <6>[ 2.190077] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10601 12:12:36.555418 <6>[ 2.198420] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10602 12:12:36.562972 <6>[ 2.206764] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10603 12:12:36.572493 <6>[ 2.215107] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10604 12:12:36.579212 <6>[ 2.223451] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10605 12:12:36.589570 <6>[ 2.231795] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10606 12:12:36.595897 <6>[ 2.240144] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10607 12:12:36.602473 <6>[ 2.249055] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10608 12:12:36.609565 <6>[ 2.256485] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10609 12:12:36.616460 <6>[ 2.263497] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10610 12:12:36.626636 <6>[ 2.270575] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10611 12:12:36.633728 <6>[ 2.277842] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10612 12:12:36.643161 <6>[ 2.284799] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10613 12:12:36.650136 <6>[ 2.293952] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10614 12:12:36.659898 <6>[ 2.303078] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10615 12:12:36.669721 <6>[ 2.312382] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10616 12:12:36.679410 <6>[ 2.321859] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10617 12:12:36.689626 <6>[ 2.331335] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10618 12:12:36.699100 <6>[ 2.340461] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10619 12:12:36.705810 <6>[ 2.349935] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10620 12:12:36.715886 <6>[ 2.359066] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10621 12:12:36.726162 <6>[ 2.368386] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10622 12:12:36.735729 <6>[ 2.378553] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10623 12:12:36.747249 <6>[ 2.391012] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10624 12:12:36.754179 <6>[ 2.401208] Trying to probe devices needed for running init ...
10625 12:12:36.766970 <6>[ 2.411107] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10626 12:12:36.796139 <6>[ 2.443037] hub 2-1:1.0: USB hub found
10627 12:12:36.799210 <6>[ 2.447548] hub 2-1:1.0: 3 ports detected
10628 12:12:36.918594 <6>[ 2.562888] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10629 12:12:37.071617 <6>[ 2.719288] hub 1-1:1.0: USB hub found
10630 12:12:37.074992 <6>[ 2.723637] hub 1-1:1.0: 4 ports detected
10631 12:12:37.150798 <6>[ 2.795121] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10632 12:12:37.395164 <6>[ 3.038886] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10633 12:12:37.526469 <6>[ 3.173436] hub 1-1.4:1.0: USB hub found
10634 12:12:37.529225 <6>[ 3.177980] hub 1-1.4:1.0: 2 ports detected
10635 12:12:37.826386 <6>[ 3.470907] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10636 12:12:38.010462 <6>[ 3.654885] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10637 12:12:49.047387 <6>[ 14.699466] ALSA device list:
10638 12:12:49.053766 <6>[ 14.702726] No soundcards found.
10639 12:12:49.066294 <6>[ 14.715087] Freeing unused kernel memory: 8384K
10640 12:12:49.069494 <6>[ 14.720001] Run /init as init process
10641 12:12:49.079719 Loading, please wait...
10642 12:12:49.099943 Starting version 247.3-7+deb11u2
10643 12:12:49.436642 <6>[ 15.082169] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10644 12:12:49.443302 <3>[ 15.083900] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10645 12:12:49.452706 <3>[ 15.097683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10646 12:12:49.459891 <3>[ 15.105782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10647 12:12:49.466213 <6>[ 15.106806] remoteproc remoteproc0: scp is available
10648 12:12:49.472501 <6>[ 15.118885] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10649 12:12:49.479509 <3>[ 15.118944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10650 12:12:49.489433 <3>[ 15.118963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10651 12:12:49.496116 <3>[ 15.118971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10652 12:12:49.505775 <3>[ 15.118981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10653 12:12:49.512283 <3>[ 15.118988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 12:12:49.522518 <3>[ 15.119063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 12:12:49.529068 <3>[ 15.119132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 12:12:49.538659 <4>[ 15.119232] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10657 12:12:49.545260 <6>[ 15.119244] remoteproc remoteproc0: powering up scp
10658 12:12:49.555840 <4>[ 15.119276] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10659 12:12:49.561950 <3>[ 15.119281] remoteproc remoteproc0: request_firmware failed: -2
10660 12:12:49.568663 <6>[ 15.126933] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10661 12:12:49.574988 <4>[ 15.133995] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10662 12:12:49.585485 <3>[ 15.134883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 12:12:49.591860 <6>[ 15.142865] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10664 12:12:49.601998 <4>[ 15.173131] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10665 12:12:49.608506 <3>[ 15.175290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 12:12:49.615020 <6>[ 15.199675] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10667 12:12:49.622434 <6>[ 15.207585] mc: Linux media interface: v0.10
10668 12:12:49.629163 <3>[ 15.208208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 12:12:49.635790 <6>[ 15.215814] usbcore: registered new interface driver r8152
10670 12:12:49.642529 <3>[ 15.223184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 12:12:49.652580 <4>[ 15.224442] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10672 12:12:49.655508 <4>[ 15.224442] Fallback method does not support PEC.
10673 12:12:49.665744 <3>[ 15.242529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10674 12:12:49.672085 <3>[ 15.247214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 12:12:49.681845 <3>[ 15.247242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 12:12:49.688644 <3>[ 15.247250] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 12:12:49.698388 <3>[ 15.247385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 12:12:49.705450 <6>[ 15.268004] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10679 12:12:49.712053 <3>[ 15.281834] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10680 12:12:49.718612 <6>[ 15.282909] pci_bus 0000:00: root bus resource [bus 00-ff]
10681 12:12:49.728794 <6>[ 15.293810] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10682 12:12:49.735480 <6>[ 15.296724] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10683 12:12:49.745145 <6>[ 15.296731] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10684 12:12:49.751700 <6>[ 15.296777] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10685 12:12:49.761790 <6>[ 15.312186] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10686 12:12:49.768451 <6>[ 15.319191] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10687 12:12:49.778532 <6>[ 15.327607] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10688 12:12:49.781351 <6>[ 15.335634] pci 0000:00:00.0: supports D1 D2
10689 12:12:49.791805 <6>[ 15.335661] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 12:12:49.794593 <6>[ 15.359481] videodev: Linux video capture interface: v2.00
10691 12:12:49.804199 <4>[ 15.362240] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10692 12:12:49.814179 <4>[ 15.362249] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10693 12:12:49.820719 <6>[ 15.367204] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10694 12:12:49.824438 <6>[ 15.367717] usbcore: registered new interface driver cdc_ether
10695 12:12:49.834280 <6>[ 15.369289] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10696 12:12:49.840704 <6>[ 15.369898] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10697 12:12:49.847306 <6>[ 15.369971] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10698 12:12:49.853824 <6>[ 15.370035] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10699 12:12:49.863952 <6>[ 15.370070] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10700 12:12:49.867009 <6>[ 15.370364] pci 0000:01:00.0: supports D1 D2
10701 12:12:49.873476 <6>[ 15.370375] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10702 12:12:49.880013 <6>[ 15.387021] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10703 12:12:49.883359 <6>[ 15.390741] Bluetooth: Core ver 2.22
10704 12:12:49.893204 <6>[ 15.399401] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10705 12:12:49.900234 <6>[ 15.405680] NET: Registered PF_BLUETOOTH protocol family
10706 12:12:49.903560 <6>[ 15.406036] usbcore: registered new interface driver r8153_ecm
10707 12:12:49.913456 <6>[ 15.415699] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10708 12:12:49.919866 <6>[ 15.423179] Bluetooth: HCI device and connection manager initialized
10709 12:12:49.923398 <6>[ 15.426791] r8152 2-1.3:1.0 eth0: v1.12.13
10710 12:12:49.932897 <6>[ 15.432249] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10711 12:12:49.936503 <6>[ 15.434755] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10712 12:12:49.943261 <6>[ 15.436774] Bluetooth: HCI socket layer initialized
10713 12:12:49.949825 <6>[ 15.437988] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10714 12:12:49.962544 <6>[ 15.439084] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10715 12:12:49.969121 <6>[ 15.439225] usbcore: registered new interface driver uvcvideo
10716 12:12:49.975672 <6>[ 15.443897] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10717 12:12:49.982283 <6>[ 15.449628] Bluetooth: L2CAP socket layer initialized
10718 12:12:49.989284 <6>[ 15.458674] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10719 12:12:49.995713 <6>[ 15.466755] Bluetooth: SCO socket layer initialized
10720 12:12:50.002343 <6>[ 15.467353] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10721 12:12:50.005883 <6>[ 15.473624] pci 0000:00:00.0: PCI bridge to [bus 01]
10722 12:12:50.012253 <6>[ 15.521873] usbcore: registered new interface driver btusb
10723 12:12:50.018764 <6>[ 15.528048] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10724 12:12:50.025524 <6>[ 15.528294] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10725 12:12:50.035126 <4>[ 15.535277] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10726 12:12:50.041706 <6>[ 15.539635] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10727 12:12:50.048465 <3>[ 15.546896] Bluetooth: hci0: Failed to load firmware file (-2)
10728 12:12:50.055116 <6>[ 15.553068] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10729 12:12:50.061536 <3>[ 15.558572] Bluetooth: hci0: Failed to set up firmware (-2)
10730 12:12:50.071340 <4>[ 15.558577] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10731 12:12:50.090470 <5>[ 15.736189] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10732 12:12:50.109707 <5>[ 15.755434] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10733 12:12:50.116679 <4>[ 15.762388] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10734 12:12:50.122673 <6>[ 15.771277] cfg80211: failed to load regulatory.db
10735 12:12:50.169933 <6>[ 15.815886] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10736 12:12:50.176519 <6>[ 15.823409] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10737 12:12:50.201703 <6>[ 15.850204] mt7921e 0000:01:00.0: ASIC revision: 79610010
10738 12:12:50.308974 <4>[ 15.951210] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10739 12:12:50.311898 Begin: Loading essential drivers ... done.
10740 12:12:50.315733 Begin: Running /scripts/init-premount ... done.
10741 12:12:50.325039 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10742 12:12:50.332216 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10743 12:12:50.335164 Device /sys/class/net/enx002432307c7b found
10744 12:12:50.338139 done.
10745 12:12:50.393166 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10746 12:12:50.434418 <4>[ 16.076950] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 12:12:50.550281 <4>[ 16.192467] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 12:12:50.665792 <4>[ 16.308345] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10749 12:12:50.781519 <4>[ 16.424214] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10750 12:12:50.897504 <4>[ 16.540134] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 12:12:51.013905 <4>[ 16.656302] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 12:12:51.129536 <4>[ 16.772141] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10753 12:12:51.245818 <4>[ 16.888160] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10754 12:12:51.361501 <4>[ 17.004027] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10755 12:12:51.413774 <6>[ 17.062876] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10756 12:12:51.469000 <3>[ 17.118073] mt7921e 0000:01:00.0: hardware init failed
10757 12:12:51.490539 IP-Config: no response after 2 secs - giving up
10758 12:12:51.533229 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10759 12:12:51.536320 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10760 12:12:51.543092 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10761 12:12:51.552517 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10762 12:12:51.559541 host : mt8192-asurada-spherion-r0-cbg-2
10763 12:12:51.566088 domain : lava-rack
10764 12:12:51.568859 rootserver: 192.168.201.1 rootpath:
10765 12:12:51.568995 filename :
10766 12:12:51.573340 done.
10767 12:12:51.581414 Begin: Running /scripts/nfs-bottom ... done.
10768 12:12:51.598579 Begin: Running /scripts/init-bottom ... done.
10769 12:12:52.719889 <6>[ 18.369498] NET: Registered PF_INET6 protocol family
10770 12:12:52.726994 <6>[ 18.376412] Segment Routing with IPv6
10771 12:12:52.730261 <6>[ 18.380402] In-situ OAM (IOAM) with IPv6
10772 12:12:52.842431 <30>[ 18.471732] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10773 12:12:52.845352 <30>[ 18.495519] systemd[1]: Detected architecture arm64.
10774 12:12:52.864957
10775 12:12:52.867870 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10776 12:12:52.868003
10777 12:12:52.883608 <30>[ 18.533038] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10778 12:12:53.483498 <30>[ 19.129673] systemd[1]: Queued start job for default target Graphical Interface.
10779 12:12:53.506725 <30>[ 19.156120] systemd[1]: Created slice system-getty.slice.
10780 12:12:53.513296 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10781 12:12:53.530198 <30>[ 19.179672] systemd[1]: Created slice system-modprobe.slice.
10782 12:12:53.536771 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10783 12:12:53.554673 <30>[ 19.204098] systemd[1]: Created slice system-serial\x2dgetty.slice.
10784 12:12:53.564914 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10785 12:12:53.577777 <30>[ 19.227444] systemd[1]: Created slice User and Session Slice.
10786 12:12:53.584820 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10787 12:12:53.605496 <30>[ 19.251490] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10788 12:12:53.614918 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10789 12:12:53.632825 <30>[ 19.279088] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10790 12:12:53.639495 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10791 12:12:53.660533 <30>[ 19.303000] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10792 12:12:53.666850 <30>[ 19.315058] systemd[1]: Reached target Local Encrypted Volumes.
10793 12:12:53.673242 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10794 12:12:53.689834 <30>[ 19.339266] systemd[1]: Reached target Paths.
10795 12:12:53.696070 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10796 12:12:53.709311 <30>[ 19.358970] systemd[1]: Reached target Remote File Systems.
10797 12:12:53.716021 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10798 12:12:53.733519 <30>[ 19.383189] systemd[1]: Reached target Slices.
10799 12:12:53.740047 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10800 12:12:53.753691 <30>[ 19.402987] systemd[1]: Reached target Swap.
10801 12:12:53.757008 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10802 12:12:53.776913 <30>[ 19.423278] systemd[1]: Listening on initctl Compatibility Named Pipe.
10803 12:12:53.783775 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10804 12:12:53.790540 <30>[ 19.438837] systemd[1]: Listening on Journal Audit Socket.
10805 12:12:53.796914 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10806 12:12:53.810695 <30>[ 19.459962] systemd[1]: Listening on Journal Socket (/dev/log).
10807 12:12:53.816729 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10808 12:12:53.834274 <30>[ 19.483727] systemd[1]: Listening on Journal Socket.
10809 12:12:53.840925 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10810 12:12:53.858252 <30>[ 19.504403] systemd[1]: Listening on Network Service Netlink Socket.
10811 12:12:53.864912 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10812 12:12:53.880583 <30>[ 19.529965] systemd[1]: Listening on udev Control Socket.
10813 12:12:53.886981 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10814 12:12:53.902005 <30>[ 19.551217] systemd[1]: Listening on udev Kernel Socket.
10815 12:12:53.908419 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10816 12:12:53.953590 <30>[ 19.603205] systemd[1]: Mounting Huge Pages File System...
10817 12:12:53.960267 Mounting [0;1;39mHuge Pages File System[0m...
10818 12:12:53.976554 <30>[ 19.625695] systemd[1]: Mounting POSIX Message Queue File System...
10819 12:12:53.983056 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10820 12:12:53.999845 <30>[ 19.649292] systemd[1]: Mounting Kernel Debug File System...
10821 12:12:54.006497 Mounting [0;1;39mKernel Debug File System[0m...
10822 12:12:54.024853 <30>[ 19.671319] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10823 12:12:54.043428 <30>[ 19.689630] systemd[1]: Starting Create list of static device nodes for the current kernel...
10824 12:12:54.050225 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10825 12:12:54.068339 <30>[ 19.717460] systemd[1]: Starting Load Kernel Module configfs...
10826 12:12:54.074264 Starting [0;1;39mLoad Kernel Module configfs[0m...
10827 12:12:54.091856 <30>[ 19.741354] systemd[1]: Starting Load Kernel Module drm...
10828 12:12:54.098436 Starting [0;1;39mLoad Kernel Module drm[0m...
10829 12:12:54.115937 <30>[ 19.765599] systemd[1]: Starting Load Kernel Module fuse...
10830 12:12:54.122502 Starting [0;1;39mLoad Kernel Module fuse[0m...
10831 12:12:54.155174 <6>[ 19.804698] fuse: init (API version 7.37)
10832 12:12:54.165336 <30>[ 19.807246] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10833 12:12:54.194034 <30>[ 19.843522] systemd[1]: Starting Journal Service...
10834 12:12:54.200376 Starting [0;1;39mJournal Service[0m...
10835 12:12:54.221927 <30>[ 19.871431] systemd[1]: Starting Load Kernel Modules...
10836 12:12:54.228432 Starting [0;1;39mLoad Kernel Modules[0m...
10837 12:12:54.247344 <30>[ 19.893570] systemd[1]: Starting Remount Root and Kernel File Systems...
10838 12:12:54.254090 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10839 12:12:54.269307 <30>[ 19.918507] systemd[1]: Starting Coldplug All udev Devices...
10840 12:12:54.275713 Starting [0;1;39mColdplug All udev Devices[0m...
10841 12:12:54.292598 <30>[ 19.942284] systemd[1]: Mounted Huge Pages File System.
10842 12:12:54.299666 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10843 12:12:54.317572 <30>[ 19.967357] systemd[1]: Mounted POSIX Message Queue File System.
10844 12:12:54.324530 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10845 12:12:54.342365 <30>[ 19.991522] systemd[1]: Mounted Kernel Debug File System.
10846 12:12:54.348679 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10847 12:12:54.360821 <3>[ 20.007147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10848 12:12:54.371097 <30>[ 20.017007] systemd[1]: Finished Create list of static device nodes for the current kernel.
10849 12:12:54.381193 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10850 12:12:54.391281 <3>[ 20.036946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 12:12:54.397895 <30>[ 20.046799] systemd[1]: modprobe@configfs.service: Succeeded.
10852 12:12:54.404227 <30>[ 20.053505] systemd[1]: Finished Load Kernel Module configfs.
10853 12:12:54.410894 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10854 12:12:54.426023 <30>[ 20.075769] systemd[1]: modprobe@drm.service: Succeeded.
10855 12:12:54.433162 <30>[ 20.082293] systemd[1]: Finished Load Kernel Module drm.
10856 12:12:54.443014 <3>[ 20.084162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 12:12:54.449435 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10858 12:12:54.466367 <30>[ 20.115797] systemd[1]: modprobe@fuse.service: Succeeded.
10859 12:12:54.476320 <3>[ 20.119184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 12:12:54.482882 <30>[ 20.122340] systemd[1]: Finished Load Kernel Module fuse.
10861 12:12:54.486554 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10862 12:12:54.502698 <30>[ 20.152201] systemd[1]: Finished Load Kernel Modules.
10863 12:12:54.512803 <3>[ 20.153381] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 12:12:54.519053 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10865 12:12:54.538189 <30>[ 20.184048] systemd[1]: Finished Remount Root and Kernel File Systems.
10866 12:12:54.544499 <3>[ 20.188945] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 12:12:54.550956 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10868 12:12:54.576323 <3>[ 20.222619] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 12:12:54.597839 <30>[ 20.246711] systemd[1]: Mounting FUSE Control File System...
10870 12:12:54.607538 Mountin<3>[ 20.253571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 12:12:54.611150 g [0;1;39mFUSE Control File System[0m...
10872 12:12:54.629244 <30>[ 20.277675] systemd[1]: Mounting Kernel Configuration File System...
10873 12:12:54.638838 <3>[ 20.284304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 12:12:54.645658 Mounting [0;1;39mKernel Configuration File System[0m...
10875 12:12:54.668008 <3>[ 20.314123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:12:54.677770 <30>[ 20.317776] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10877 12:12:54.688172 <30>[ 20.331950] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10878 12:12:54.699532 <3>[ 20.345527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 12:12:54.729511 <3>[ 20.375410] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 12:12:54.736154 <30>[ 20.375600] systemd[1]: Starting Load/Save Random Seed...
10881 12:12:54.739206 Starting [0;1;39mLoad/Save Random Seed[0m...
10882 12:12:54.755863 <3>[ 20.401898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 12:12:54.764745 <30>[ 20.413662] systemd[1]: Starting Apply Kernel Variables...
10884 12:12:54.774307 <3>[ 20.419217] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 12:12:54.777847 Starting [0;1;39mApply Kernel Variables[0m...
10886 12:12:54.797259 <30>[ 20.446901] systemd[1]: Starting Create System Users...
10887 12:12:54.804310 Starting [0;1;39mCreate System Users[0m...
10888 12:12:54.818205 <3>[ 20.464396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:12:54.828209 <3>[ 20.465312] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10890 12:12:54.831571 <30>[ 20.475025] systemd[1]: Mounted FUSE Control File System.
10891 12:12:54.848463 <4>[ 20.481478] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10892 12:12:54.854801 <3>[ 20.481484] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10893 12:12:54.864794 <3>[ 20.495085] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 12:12:54.871514 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10895 12:12:54.890163 <29>[ 20.535704] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10896 12:12:54.900305 <28>[ 20.545851] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10897 12:12:54.906824 <27>[ 20.554664] systemd[1]: Failed to start Coldplug All udev Devices.
10898 12:12:54.913617 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10899 12:12:54.929470 See 'systemctl status systemd-udev-trigger.service' for details.
10900 12:12:54.945955 <30>[ 20.595511] systemd[1]: Mounted Kernel Configuration File System.
10901 12:12:54.952599 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10902 12:12:54.970704 <30>[ 20.619951] systemd[1]: Finished Load/Save Random Seed.
10903 12:12:54.977292 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10904 12:12:54.993572 <30>[ 20.643388] systemd[1]: Started Journal Service.
10905 12:12:55.000201 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10906 12:12:55.015244 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10907 12:12:55.030235 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10908 12:12:55.082486 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10909 12:12:55.099751 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10910 12:12:55.145747 <46>[ 20.792149] systemd-journald[296]: Received client request to flush runtime journal.
10911 12:12:55.895823 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10912 12:12:55.909544 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10913 12:12:55.925570 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10914 12:12:55.977278 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10915 12:12:56.527949 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10916 12:12:56.570391 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10917 12:12:56.610862 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10918 12:12:56.662193 Starting [0;1;39mNetwork Service[0m...
10919 12:12:56.938062 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10920 12:12:56.957866 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10921 12:12:57.009761 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10922 12:12:57.238674 <6>[ 22.888469] remoteproc remoteproc0: powering up scp
10923 12:12:57.271895 <4>[ 22.918339] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10924 12:12:57.278540 <3>[ 22.928256] remoteproc remoteproc0: request_firmware failed: -2
10925 12:12:57.288531 <3>[ 22.934442] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10926 12:12:57.369941 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10927 12:12:57.402176 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10928 12:12:57.431306 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10929 12:12:57.463979 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10930 12:12:57.480529 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10931 12:12:57.537811 Starting [0;1;39mNetwork Name Resolution[0m...
10932 12:12:57.561799 Starting [0;1;39mNetwork Time Synchronization[0m...
10933 12:12:57.579651 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10934 12:12:57.600833 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10935 12:12:57.631688 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10936 12:12:57.645638 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10937 12:12:57.791038 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10938 12:12:57.809291 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10939 12:12:57.832885 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10940 12:12:57.845561 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10941 12:12:57.861474 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10942 12:12:58.017583 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10943 12:12:58.046277 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10944 12:12:58.073598 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10945 12:12:58.095148 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10946 12:12:58.109050 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10947 12:12:58.365982 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10948 12:12:58.377231 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10949 12:12:58.393355 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10950 12:12:58.437219 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10951 12:12:58.839977 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10952 12:12:59.181767 Starting [0;1;39mUser Login Management[0m...
10953 12:12:59.197994 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10954 12:12:59.214612 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10955 12:12:59.232649 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10956 12:12:59.277746 Starting [0;1;39mPermit User Sessions[0m...
10957 12:12:59.391747 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10958 12:12:59.435067 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10959 12:12:59.451607 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10960 12:12:59.469090 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10961 12:12:59.489882 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10962 12:12:59.522148 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10963 12:12:59.537671 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10964 12:12:59.553124 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10965 12:12:59.589227 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10966 12:12:59.632260 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10967 12:12:59.686895
10968 12:12:59.687055
10969 12:12:59.690167 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10970 12:12:59.690264
10971 12:12:59.693748 debian-bullseye-arm64 login: root (automatic login)
10972 12:12:59.693836
10973 12:12:59.693904
10974 12:12:59.967539 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Tue Jun 6 11:57:40 UTC 2023 aarch64
10975 12:12:59.967690
10976 12:12:59.973673 The programs included with the Debian GNU/Linux system are free software;
10977 12:12:59.980438 the exact distribution terms for each program are described in the
10978 12:12:59.983587 individual files in /usr/share/doc/*/copyright.
10979 12:12:59.983706
10980 12:12:59.990277 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10981 12:12:59.993940 permitted by applicable law.
10982 12:13:00.085988 Matched prompt #10: / #
10984 12:13:00.086409 Setting prompt string to ['/ #']
10985 12:13:00.086537 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10987 12:13:00.086847 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10988 12:13:00.086966 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
10989 12:13:00.087068 Setting prompt string to ['/ #']
10990 12:13:00.087160 Forcing a shell prompt, looking for ['/ #']
10992 12:13:00.137417 / #
10993 12:13:00.137618 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10994 12:13:00.137736 Waiting using forced prompt support (timeout 00:02:30)
10995 12:13:00.142342
10996 12:13:00.142681 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10997 12:13:00.142806 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
10999 12:13:00.243207 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae'
11000 12:13:00.247885 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10605430/extract-nfsrootfs-bgeneuae'
11002 12:13:00.348446 / # export NFS_SERVER_IP='192.168.201.1'
11003 12:13:00.353762 export NFS_SERVER_IP='192.168.201.1'
11004 12:13:00.354096 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11005 12:13:00.354232 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11006 12:13:00.354352 end: 2 depthcharge-action (duration 00:01:39) [common]
11007 12:13:00.354487 start: 3 lava-test-retry (timeout 00:01:00) [common]
11008 12:13:00.354611 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11009 12:13:00.354717 Using namespace: common
11011 12:13:00.455096 / # #
11012 12:13:00.455323 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11013 12:13:00.460245 #
11014 12:13:00.460557 Using /lava-10605430
11016 12:13:00.560926 / # export SHELL=/bin/sh
11017 12:13:00.566299 export SHELL=/bin/sh
11019 12:13:00.666859 / # . /lava-10605430/environment
11020 12:13:00.671767 . /lava-10605430/environment
11022 12:13:00.777357 / # /lava-10605430/bin/lava-test-runner /lava-10605430/0
11023 12:13:00.777535 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 12:13:00.782606 /lava-10605430/bin/lava-test-runner /lava-10605430/0
11025 12:13:01.007767 + export TESTRUN_ID=0_dmesg
11026 12:13:01.010673 + cd /lava-10605430/0/tests/0_dmesg
11027 12:13:01.013665 + cat uuid
11028 12:13:01.025606 + UUID=10605430_1.<8>[ 26.672282] <LAVA_SIGNAL_STARTRUN 0_dmesg 10605430_1.6.2.3.1>
11029 12:13:01.025697 6.2.3.1
11030 12:13:01.025768 + set +x
11031 12:13:01.026008 Received signal: <STARTRUN> 0_dmesg 10605430_1.6.2.3.1
11032 12:13:01.026118 Starting test lava.0_dmesg (10605430_1.6.2.3.1)
11033 12:13:01.026207 Skipping test definition patterns.
11034 12:13:01.031691 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11035 12:13:01.132605 <8>[ 26.779790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11036 12:13:01.132953 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11038 12:13:01.207935 <8>[ 26.855199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11039 12:13:01.208294 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11041 12:13:01.292151 <8>[ 26.939364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11042 12:13:01.292474 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11044 12:13:01.298809 + <8>[ 26.948729] <LAVA_SIGNAL_ENDRUN 0_dmesg 10605430_1.6.2.3.1>
11045 12:13:01.298898 set +x
11046 12:13:01.299136 Received signal: <ENDRUN> 0_dmesg 10605430_1.6.2.3.1
11047 12:13:01.299224 Ending use of test pattern.
11048 12:13:01.299286 Ending test lava.0_dmesg (10605430_1.6.2.3.1), duration 0.27
11050 12:13:01.306910 <LAVA_TEST_RUNNER EXIT>
11051 12:13:01.307170 ok: lava_test_shell seems to have completed
11052 12:13:01.307280 alert: pass
crit: pass
emerg: pass
11053 12:13:01.307407 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11054 12:13:01.307493 end: 3 lava-test-retry (duration 00:00:01) [common]
11055 12:13:01.307602 start: 4 lava-test-retry (timeout 00:01:00) [common]
11056 12:13:01.307700 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11057 12:13:01.307783 Using namespace: common
11059 12:13:01.408104 / # #
11060 12:13:01.408322 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11061 12:13:01.408530 Using /lava-10605430
11063 12:13:01.508832 export SHELL=/bin/sh
11064 12:13:01.509060 #
11066 12:13:01.609578 / # export SHELL=/bin/sh. /lava-10605430/environment
11067 12:13:01.609817
11069 12:13:01.710440 / # . /lava-10605430/environment/lava-10605430/bin/lava-test-runner /lava-10605430/1
11070 12:13:01.710620 Test shell timeout: 10s (minimum of the action and connection timeout)
11071 12:13:01.710744
11072 12:13:01.715681 / # /lava-10605430/bin/lava-test-runner /lava-10605430/1
11073 12:13:01.838569 + export TESTRUN_ID=1_bootrr
11074 12:13:01.842041 + cd /lava-10605430/1/tests/1_bootrr
11075 12:13:01.844881 + cat uuid
11076 12:13:01.856432 + UUID=10605430_1.<8>[ 27.503879] <LAVA_SIGNAL_STARTRUN 1_bootrr 10605430_1.6.2.3.5>
11077 12:13:01.856525 6.2.3.5
11078 12:13:01.856595 + set +x
11079 12:13:01.856866 Received signal: <STARTRUN> 1_bootrr 10605430_1.6.2.3.5
11080 12:13:01.856935 Starting test lava.1_bootrr (10605430_1.6.2.3.5)
11081 12:13:01.857055 Skipping test definition patterns.
11082 12:13:01.869911 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10605430/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11083 12:13:01.872916 + cd /opt/bootrr/libexec/bootrr
11084 12:13:01.872993 + sh helpers/bootrr-auto
11085 12:13:01.935831 /lava-10605430/1/../bin/lava-test-case
11086 12:13:01.964293 <8>[ 27.611406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11087 12:13:01.964621 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11089 12:13:02.007576 /lava-10605430/1/../bin/lava-test-case
11090 12:13:02.035774 <8>[ 27.682754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11091 12:13:02.036127 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11093 12:13:02.060743 /lava-10605430/1/../bin/lava-test-case
11094 12:13:02.088410 <8>[ 27.735711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11095 12:13:02.088762 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11097 12:13:02.143602 /lava-10605430/1/../bin/lava-test-case
11098 12:13:02.171834 <8>[ 27.818802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11099 12:13:02.172129 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11101 12:13:02.216786 /lava-10605430/1/../bin/lava-test-case
11102 12:13:02.245783 <8>[ 27.892706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11103 12:13:02.246078 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11105 12:13:02.282124 /lava-10605430/1/../bin/lava-test-case
11106 12:13:02.311719 <8>[ 27.958548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11107 12:13:02.312007 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11109 12:13:02.345541 /lava-10605430/1/../bin/lava-test-case
11110 12:13:02.371828 <8>[ 28.018880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11111 12:13:02.372113 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11113 12:13:02.408461 /lava-10605430/1/../bin/lava-test-case
11114 12:13:02.435707 <8>[ 28.082487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11115 12:13:02.436016 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11117 12:13:02.457034 /lava-10605430/1/../bin/lava-test-case
11118 12:13:02.485103 <8>[ 28.132229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11119 12:13:02.485375 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11121 12:13:02.520392 /lava-10605430/1/../bin/lava-test-case
11122 12:13:02.548243 <8>[ 28.195148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11123 12:13:02.548547 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11125 12:13:02.578031 /lava-10605430/1/../bin/lava-test-case
11126 12:13:02.605271 <8>[ 28.252399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11127 12:13:02.605542 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11129 12:13:02.640873 /lava-10605430/1/../bin/lava-test-case
11130 12:13:02.666468 <8>[ 28.313619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11131 12:13:02.666753 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11133 12:13:02.702787 /lava-10605430/1/../bin/lava-test-case
11134 12:13:02.729803 <8>[ 28.376888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11135 12:13:02.730118 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11137 12:13:02.766319 /lava-10605430/1/../bin/lava-test-case
11138 12:13:02.794169 <8>[ 28.441098] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11139 12:13:02.794485 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11141 12:13:02.828315 /lava-10605430/1/../bin/lava-test-case
11142 12:13:02.855233 <8>[ 28.502832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11143 12:13:02.855526 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11145 12:13:02.888891 /lava-10605430/1/../bin/lava-test-case
11146 12:13:02.915729 <8>[ 28.562958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11147 12:13:02.916025 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11149 12:13:02.947418 /lava-10605430/1/../bin/lava-test-case
11150 12:13:02.974477 <8>[ 28.621600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11151 12:13:02.974795 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11153 12:13:02.995782 /lava-10605430/1/../bin/lava-test-case
11154 12:13:03.022225 <8>[ 28.669712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11155 12:13:03.022507 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11157 12:13:03.054540 /lava-10605430/1/../bin/lava-test-case
11158 12:13:03.080882 <8>[ 28.728140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11159 12:13:03.081192 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11161 12:13:03.106334 /lava-10605430/1/../bin/lava-test-case
11162 12:13:03.132662 <8>[ 28.779930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11163 12:13:03.132931 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11165 12:13:03.164455 /lava-10605430/1/../bin/lava-test-case
11166 12:13:03.191968 <8>[ 28.839016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11167 12:13:03.192373 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11169 12:13:03.218740 /lava-10605430/1/../bin/lava-test-case
11170 12:13:03.245025 <8>[ 28.892406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11171 12:13:03.245330 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11173 12:13:03.279228 /lava-10605430/1/../bin/lava-test-case
11174 12:13:03.306123 <8>[ 28.953645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11175 12:13:03.306418 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11177 12:13:03.329177 /lava-10605430/1/../bin/lava-test-case
11178 12:13:03.358149 <8>[ 29.005243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11179 12:13:03.358420 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11181 12:13:03.393608 /lava-10605430/1/../bin/lava-test-case
11182 12:13:03.420946 <8>[ 29.068439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11183 12:13:03.421267 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11185 12:13:03.455207 /lava-10605430/1/../bin/lava-test-case
11186 12:13:03.484576 <8>[ 29.131370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11187 12:13:03.484889 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11189 12:13:03.506179 /lava-10605430/1/../bin/lava-test-case
11190 12:13:03.534289 <8>[ 29.181747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11191 12:13:03.534626 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11193 12:13:03.575210 /lava-10605430/1/../bin/lava-test-case
11194 12:13:03.599792 <8>[ 29.247104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11195 12:13:03.600112 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11197 12:13:03.622427 /lava-10605430/1/../bin/lava-test-case
11198 12:13:03.648712 <8>[ 29.296359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11199 12:13:03.649018 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11201 12:13:03.683815 /lava-10605430/1/../bin/lava-test-case
11202 12:13:03.711760 <8>[ 29.359173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11203 12:13:03.712087 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11205 12:13:03.744938 /lava-10605430/1/../bin/lava-test-case
11206 12:13:03.771919 <8>[ 29.419207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11207 12:13:03.772269 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11209 12:13:03.808278 /lava-10605430/1/../bin/lava-test-case
11210 12:13:03.836156 <8>[ 29.483740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11211 12:13:03.836531 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11213 12:13:03.874727 /lava-10605430/1/../bin/lava-test-case
11214 12:13:03.905698 <8>[ 29.553016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11215 12:13:03.905999 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11217 12:13:03.933672 /lava-10605430/1/../bin/lava-test-case
11218 12:13:03.962818 <8>[ 29.610291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11219 12:13:03.963092 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11221 12:13:03.999551 /lava-10605430/1/../bin/lava-test-case
11222 12:13:04.027611 <8>[ 29.675236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11223 12:13:04.027897 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11225 12:13:04.059194 /lava-10605430/1/../bin/lava-test-case
11226 12:13:04.087423 <8>[ 29.734448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11227 12:13:04.087704 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11229 12:13:04.110489 /lava-10605430/1/../bin/lava-test-case
11230 12:13:04.143827 <8>[ 29.791150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11231 12:13:04.144157 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11233 12:13:04.177825 /lava-10605430/1/../bin/lava-test-case
11234 12:13:04.205647 <8>[ 29.853199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11235 12:13:04.205928 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11237 12:13:04.227418 /lava-10605430/1/../bin/lava-test-case
11238 12:13:04.259280 <8>[ 29.906516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11239 12:13:04.259577 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11241 12:13:04.302417 /lava-10605430/1/../bin/lava-test-case
11242 12:13:04.335762 <8>[ 29.982819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11243 12:13:04.336073 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11245 12:13:04.360653 /lava-10605430/1/../bin/lava-test-case
11246 12:13:04.389146 <8>[ 30.036722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11247 12:13:04.389440 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11249 12:13:04.424192 /lava-10605430/1/../bin/lava-test-case
11250 12:13:04.449388 <8>[ 30.096733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11251 12:13:04.449678 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11253 12:13:04.469790 /lava-10605430/1/../bin/lava-test-case
11254 12:13:04.499171 <8>[ 30.146626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11255 12:13:04.499448 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11257 12:13:04.535069 /lava-10605430/1/../bin/lava-test-case
11258 12:13:04.562735 <8>[ 30.210208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11259 12:13:04.563027 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11261 12:13:04.584849 /lava-10605430/1/../bin/lava-test-case
11262 12:13:04.613728 <8>[ 30.261056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11263 12:13:04.614013 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11265 12:13:04.652885 /lava-10605430/1/../bin/lava-test-case
11266 12:13:04.679443 <8>[ 30.326730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11267 12:13:04.679720 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11269 12:13:04.702585 /lava-10605430/1/../bin/lava-test-case
11270 12:13:04.731761 <8>[ 30.378907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11271 12:13:04.732184 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11273 12:13:04.772895 /lava-10605430/1/../bin/lava-test-case
11274 12:13:04.802715 <8>[ 30.450127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11275 12:13:04.803026 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11277 12:13:04.823672 /lava-10605430/1/../bin/lava-test-case
11278 12:13:04.851374 <8>[ 30.498622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11279 12:13:04.851685 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11281 12:13:04.890940 /lava-10605430/1/../bin/lava-test-case
11282 12:13:04.918918 <8>[ 30.566069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11283 12:13:04.919206 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11285 12:13:04.949735 /lava-10605430/1/../bin/lava-test-case
11286 12:13:04.977322 <8>[ 30.624527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11287 12:13:04.977638 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11289 12:13:06.025459 /lava-10605430/1/../bin/lava-test-case
11290 12:13:06.052794 <8>[ 31.700465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11291 12:13:06.053154 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11293 12:13:07.087182 /lava-10605430/1/../bin/lava-test-case
11294 12:13:07.120812 <8>[ 32.768569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11295 12:13:07.121125 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11296 12:13:07.121229 Bad test result: blocked
11297 12:13:07.143088 /lava-10605430/1/../bin/lava-test-case
11298 12:13:07.170113 <8>[ 32.817513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11299 12:13:07.170424 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11301 12:13:07.205871 /lava-10605430/1/../bin/lava-test-case
11302 12:13:07.232515 <8>[ 32.879967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11303 12:13:07.232817 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11305 12:13:07.267787 /lava-10605430/1/../bin/lava-test-case
11306 12:13:07.294662 <8>[ 32.942141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11307 12:13:07.294961 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11309 12:13:07.328371 /lava-10605430/1/../bin/lava-test-case
11310 12:13:07.356765 <8>[ 33.004593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11311 12:13:07.357062 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11313 12:13:07.396915 /lava-10605430/1/../bin/lava-test-case
11314 12:13:07.432338 <8>[ 33.080251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11315 12:13:07.432644 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11317 12:13:07.476885 /lava-10605430/1/../bin/lava-test-case
11318 12:13:07.510522 <8>[ 33.158582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11319 12:13:07.510859 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11321 12:13:07.536817 /lava-10605430/1/../bin/lava-test-case
11322 12:13:07.567991 <8>[ 33.215751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11323 12:13:07.568382 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11325 12:13:07.608938 /lava-10605430/1/../bin/lava-test-case
11326 12:13:07.636806 <8>[ 33.284619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11327 12:13:07.637170 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11329 12:13:07.670057 /lava-10605430/1/../bin/lava-test-case
11330 12:13:07.696584 <8>[ 33.344623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11331 12:13:07.696893 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11333 12:13:07.716316 /lava-10605430/1/../bin/lava-test-case
11334 12:13:07.744499 <8>[ 33.392028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11335 12:13:07.744809 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11337 12:13:07.777338 /lava-10605430/1/../bin/lava-test-case
11338 12:13:07.803638 <8>[ 33.451298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11339 12:13:07.803938 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11341 12:13:07.832721 /lava-10605430/1/../bin/lava-test-case
11342 12:13:07.858646 <8>[ 33.506549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11343 12:13:07.858978 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11345 12:13:07.892760 /lava-10605430/1/../bin/lava-test-case
11346 12:13:07.919766 <8>[ 33.567605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11347 12:13:07.920056 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11349 12:13:07.943112 /lava-10605430/1/../bin/lava-test-case
11350 12:13:07.969661 <8>[ 33.617592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11351 12:13:07.969957 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11353 12:13:08.005260 /lava-10605430/1/../bin/lava-test-case
11354 12:13:08.032177 <8>[ 33.679693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11355 12:13:08.032461 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11357 12:13:08.065789 /lava-10605430/1/../bin/lava-test-case
11358 12:13:08.092207 <8>[ 33.739884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11359 12:13:08.092514 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11361 12:13:08.123138 /lava-10605430/1/../bin/lava-test-case
11362 12:13:08.150202 <8>[ 33.798172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11363 12:13:08.150540 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11365 12:13:08.191875 /lava-10605430/1/../bin/lava-test-case
11366 12:13:08.217178 <8>[ 33.864840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11367 12:13:08.217511 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11369 12:13:08.250177 /lava-10605430/1/../bin/lava-test-case
11370 12:13:08.276239 <8>[ 33.924255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11371 12:13:08.276532 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11373 12:13:08.310898 /lava-10605430/1/../bin/lava-test-case
11374 12:13:08.337964 <8>[ 33.986003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11375 12:13:08.338252 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11377 12:13:08.371289 /lava-10605430/1/../bin/lava-test-case
11378 12:13:08.399867 <8>[ 34.047819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11379 12:13:08.400155 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11381 12:13:08.435628 /lava-10605430/1/../bin/lava-test-case
11382 12:13:08.463712 <8>[ 34.111679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11383 12:13:08.464007 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11385 12:13:08.497609 /lava-10605430/1/../bin/lava-test-case
11386 12:13:08.523945 <8>[ 34.171701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11387 12:13:08.524235 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11389 12:13:08.566457 /lava-10605430/1/../bin/lava-test-case
11390 12:13:08.592415 <8>[ 34.240536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11391 12:13:08.592722 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11393 12:13:08.628890 /lava-10605430/1/../bin/lava-test-case
11394 12:13:08.656541 <8>[ 34.304578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11395 12:13:08.656844 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11397 12:13:08.695631 /lava-10605430/1/../bin/lava-test-case
11398 12:13:08.725550 <8>[ 34.373129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11399 12:13:08.725849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11401 12:13:08.758010 /lava-10605430/1/../bin/lava-test-case
11402 12:13:08.784562 <8>[ 34.432592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11403 12:13:08.784852 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11405 12:13:08.821694 /lava-10605430/1/../bin/lava-test-case
11406 12:13:08.850757 <8>[ 34.498791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11407 12:13:08.851075 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11409 12:13:08.894098 /lava-10605430/1/../bin/lava-test-case
11410 12:13:08.924612 <8>[ 34.572584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11411 12:13:08.924937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11413 12:13:08.949120 /lava-10605430/1/../bin/lava-test-case
11414 12:13:08.976551 <8>[ 34.624383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11415 12:13:08.976838 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11417 12:13:09.011618 /lava-10605430/1/../bin/lava-test-case
11418 12:13:09.038770 <8>[ 34.686784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11419 12:13:09.039102 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11421 12:13:09.062591 /lava-10605430/1/../bin/lava-test-case
11422 12:13:09.089415 <8>[ 34.737150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11423 12:13:09.089715 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11425 12:13:09.127524 /lava-10605430/1/../bin/lava-test-case
11426 12:13:09.154124 <8>[ 34.801818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11427 12:13:09.154431 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11429 12:13:09.177331 /lava-10605430/1/../bin/lava-test-case
11430 12:13:09.203305 <8>[ 34.851119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11431 12:13:09.203597 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11433 12:13:09.244957 /lava-10605430/1/../bin/lava-test-case
11434 12:13:09.271023 <8>[ 34.919046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11435 12:13:09.271319 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11437 12:13:09.293734 /lava-10605430/1/../bin/lava-test-case
11438 12:13:09.322130 <8>[ 34.969958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11439 12:13:09.322414 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11441 12:13:09.358506 /lava-10605430/1/../bin/lava-test-case
11442 12:13:09.386869 <8>[ 35.034800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11443 12:13:09.387164 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11445 12:13:09.407239 /lava-10605430/1/../bin/lava-test-case
11446 12:13:09.440301 <8>[ 35.087997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11447 12:13:09.440574 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11449 12:13:09.471551 /lava-10605430/1/../bin/lava-test-case
11450 12:13:09.496800 <8>[ 35.144785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11451 12:13:09.497100 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11453 12:13:09.521071 /lava-10605430/1/../bin/lava-test-case
11454 12:13:09.554815 <8>[ 35.202586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11455 12:13:09.555132 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11457 12:13:09.597380 /lava-10605430/1/../bin/lava-test-case
11458 12:13:09.623350 <8>[ 35.271447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11459 12:13:09.623667 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11461 12:13:09.656119 /lava-10605430/1/../bin/lava-test-case
11462 12:13:09.680279 <8>[ 35.328538] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11463 12:13:09.680608 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11465 12:13:09.702486 /lava-10605430/1/../bin/lava-test-case
11466 12:13:09.728475 <8>[ 35.376487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11467 12:13:09.728786 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11469 12:13:09.762236 /lava-10605430/1/../bin/lava-test-case
11470 12:13:09.790408 <8>[ 35.438521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11471 12:13:09.790739 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11473 12:13:09.814647 /lava-10605430/1/../bin/lava-test-case
11474 12:13:09.842320 <8>[ 35.490246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11475 12:13:09.842612 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11477 12:13:09.875757 /lava-10605430/1/../bin/lava-test-case
11478 12:13:09.901139 <8>[ 35.549412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11479 12:13:09.901432 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11481 12:13:09.930720 /lava-10605430/1/../bin/lava-test-case
11482 12:13:09.957962 <8>[ 35.606220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11483 12:13:09.958301 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11485 12:13:11.002512 /lava-10605430/1/../bin/lava-test-case
11486 12:13:11.035090 <8>[ 36.683565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11487 12:13:11.035397 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11489 12:13:11.059639 /lava-10605430/1/../bin/lava-test-case
11490 12:13:11.089356 <8>[ 36.737829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11491 12:13:11.089719 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11493 12:13:12.133484 /lava-10605430/1/../bin/lava-test-case
11494 12:13:12.162934 <8>[ 37.811427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11495 12:13:12.163276 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11497 12:13:12.183327 /lava-10605430/1/../bin/lava-test-case
11498 12:13:12.214440 <8>[ 37.862837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11499 12:13:12.214768 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11501 12:13:13.255729 /lava-10605430/1/../bin/lava-test-case
11502 12:13:13.295811 <8>[ 38.944439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11503 12:13:13.296125 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11505 12:13:13.318099 /lava-10605430/1/../bin/lava-test-case
11506 12:13:13.341903 <8>[ 38.990429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11507 12:13:13.342248 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11509 12:13:14.389685 /lava-10605430/1/../bin/lava-test-case
11510 12:13:14.421321 <8>[ 40.069840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11511 12:13:14.421638 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11513 12:13:14.443122 /lava-10605430/1/../bin/lava-test-case
11514 12:13:14.470566 <8>[ 40.119158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11515 12:13:14.470903 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11517 12:13:15.510505 /lava-10605430/1/../bin/lava-test-case
11518 12:13:15.537254 <8>[ 41.186249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11519 12:13:15.537551 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11521 12:13:15.557321 /lava-10605430/1/../bin/lava-test-case
11522 12:13:15.586216 <8>[ 41.234624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11523 12:13:15.586530 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11525 12:13:16.629573 /lava-10605430/1/../bin/lava-test-case
11526 12:13:16.658933 <8>[ 42.307605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11527 12:13:16.659260 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11529 12:13:16.680872 /lava-10605430/1/../bin/lava-test-case
11530 12:13:16.706821 <8>[ 42.355905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11531 12:13:16.707135 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11533 12:13:17.751277 /lava-10605430/1/../bin/lava-test-case
11534 12:13:17.786788 <8>[ 43.435636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11535 12:13:17.787135 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11537 12:13:17.812434 /lava-10605430/1/../bin/lava-test-case
11538 12:13:17.843361 <8>[ 43.492518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11539 12:13:17.843673 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11541 12:13:17.870188 /lava-10605430/1/../bin/lava-test-case
11542 12:13:17.906225 <8>[ 43.555074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11543 12:13:17.906565 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11545 12:13:18.950433 /lava-10605430/1/../bin/lava-test-case
11546 12:13:18.976612 <8>[ 44.625409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11547 12:13:18.976916 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11549 12:13:18.999693 /lava-10605430/1/../bin/lava-test-case
11550 12:13:19.027680 <8>[ 44.676724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11551 12:13:19.027981 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11553 12:13:19.061764 /lava-10605430/1/../bin/lava-test-case
11554 12:13:19.089579 <8>[ 44.738674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11555 12:13:19.089879 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11557 12:13:19.113697 /lava-10605430/1/../bin/lava-test-case
11558 12:13:19.141362 <8>[ 44.790570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11559 12:13:19.141647 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11561 12:13:19.175601 /lava-10605430/1/../bin/lava-test-case
11562 12:13:19.205040 <8>[ 44.854036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11563 12:13:19.205344 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11565 12:13:19.236988 /lava-10605430/1/../bin/lava-test-case
11566 12:13:19.264567 <8>[ 44.913566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11567 12:13:19.264883 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11569 12:13:19.305747 /lava-10605430/1/../bin/lava-test-case
11570 12:13:19.332879 <8>[ 44.982223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11571 12:13:19.333220 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11573 12:13:19.355893 /lava-10605430/1/../bin/lava-test-case
11574 12:13:19.384993 <8>[ 45.033786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11575 12:13:19.385299 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11577 12:13:19.416497 /lava-10605430/1/../bin/lava-test-case
11578 12:13:19.445906 <8>[ 45.095106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11579 12:13:19.446221 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11581 12:13:19.483107 /lava-10605430/1/../bin/lava-test-case
11582 12:13:19.509376 <8>[ 45.158366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11583 12:13:19.509689 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11585 12:13:19.531703 /lava-10605430/1/../bin/lava-test-case
11586 12:13:19.563968 <8>[ 45.213053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11587 12:13:19.564317 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11589 12:13:19.597004 /lava-10605430/1/../bin/lava-test-case
11590 12:13:19.628704 <8>[ 45.278043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11591 12:13:19.629006 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11593 12:13:19.649372 /lava-10605430/1/../bin/lava-test-case
11594 12:13:19.676445 <8>[ 45.325856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11595 12:13:19.676743 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11597 12:13:19.712028 /lava-10605430/1/../bin/lava-test-case
11598 12:13:19.739220 <8>[ 45.388639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11599 12:13:19.739554 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11601 12:13:19.759187 /lava-10605430/1/../bin/lava-test-case
11602 12:13:19.786657 <8>[ 45.435784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11603 12:13:19.787013 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11605 12:13:19.819527 /lava-10605430/1/../bin/lava-test-case
11606 12:13:19.844275 <8>[ 45.493703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11607 12:13:19.844560 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11609 12:13:19.865902 /lava-10605430/1/../bin/lava-test-case
11610 12:13:19.891914 <8>[ 45.540990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11611 12:13:19.892282 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11613 12:13:19.939236 /lava-10605430/1/../bin/lava-test-case
11614 12:13:19.966513 <8>[ 45.615539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11615 12:13:19.966873 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11617 12:13:19.989976 /lava-10605430/1/../bin/lava-test-case
11618 12:13:20.019837 <8>[ 45.669048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11619 12:13:20.020157 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11621 12:13:20.055149 /lava-10605430/1/../bin/lava-test-case
11622 12:13:20.085257 <8>[ 45.734302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11623 12:13:20.085607 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11625 12:13:20.106409 /lava-10605430/1/../bin/lava-test-case
11626 12:13:20.136449 <8>[ 45.785315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11627 12:13:20.136763 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11629 12:13:20.499605 <6>[ 46.154937] vpu: disabling
11630 12:13:20.502636 <6>[ 46.157996] vproc2: disabling
11631 12:13:20.505718 <6>[ 46.161267] vproc1: disabling
11632 12:13:20.509408 <6>[ 46.164529] vaud18: disabling
11633 12:13:20.515473 <6>[ 46.167936] vsram_others: disabling
11634 12:13:20.519114 <6>[ 46.171805] va09: disabling
11635 12:13:20.522067 <6>[ 46.174908] vsram_md: disabling
11636 12:13:20.525044 <6>[ 46.178394] Vgpu: disabling
11637 12:13:21.181007 /lava-10605430/1/../bin/lava-test-case
11638 12:13:21.213755 <8>[ 46.863228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11639 12:13:21.214079 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11641 12:13:22.259969 /lava-10605430/1/../bin/lava-test-case
11642 12:13:22.286962 <8>[ 47.936488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11643 12:13:22.287273 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11645 12:13:22.306258 /lava-10605430/1/../bin/lava-test-case
11646 12:13:22.332768 <8>[ 47.982594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11647 12:13:22.333071 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11649 12:13:22.368752 /lava-10605430/1/../bin/lava-test-case
11650 12:13:22.396309 <8>[ 48.045709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11651 12:13:22.396627 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11653 12:13:22.417593 /lava-10605430/1/../bin/lava-test-case
11654 12:13:22.443186 <8>[ 48.092450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11655 12:13:22.443494 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11657 12:13:22.479120 /lava-10605430/1/../bin/lava-test-case
11658 12:13:22.505557 <8>[ 48.155076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11659 12:13:22.505898 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11661 12:13:22.525705 /lava-10605430/1/../bin/lava-test-case
11662 12:13:22.552610 <8>[ 48.201964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11663 12:13:22.552953 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11665 12:13:22.593061 /lava-10605430/1/../bin/lava-test-case
11666 12:13:22.618807 <8>[ 48.268491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11667 12:13:22.619151 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11669 12:13:22.639638 /lava-10605430/1/../bin/lava-test-case
11670 12:13:22.667036 <8>[ 48.316694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11671 12:13:22.667370 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11673 12:13:22.699898 /lava-10605430/1/../bin/lava-test-case
11674 12:13:22.730134 <8>[ 48.379947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11675 12:13:22.730486 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11677 12:13:22.751876 /lava-10605430/1/../bin/lava-test-case
11678 12:13:22.779254 <8>[ 48.428545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11679 12:13:22.779607 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11681 12:13:22.816199 /lava-10605430/1/../bin/lava-test-case
11682 12:13:22.845170 <8>[ 48.494536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11683 12:13:22.845475 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11685 12:13:22.865210 /lava-10605430/1/../bin/lava-test-case
11686 12:13:22.897745 <8>[ 48.547038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11687 12:13:22.898101 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11689 12:13:22.935810 /lava-10605430/1/../bin/lava-test-case
11690 12:13:22.959178 <8>[ 48.608651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11691 12:13:22.959497 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11693 12:13:22.980454 /lava-10605430/1/../bin/lava-test-case
11694 12:13:23.008027 <8>[ 48.657298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11695 12:13:23.008349 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11697 12:13:23.040919 /lava-10605430/1/../bin/lava-test-case
11698 12:13:23.067442 <8>[ 48.717026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11699 12:13:23.067721 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11701 12:13:23.091068 /lava-10605430/1/../bin/lava-test-case
11702 12:13:23.119187 <8>[ 48.768752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11703 12:13:23.119487 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11705 12:13:23.154980 /lava-10605430/1/../bin/lava-test-case
11706 12:13:23.180440 <8>[ 48.830248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11707 12:13:23.180735 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11709 12:13:23.202502 /lava-10605430/1/../bin/lava-test-case
11710 12:13:23.228808 <8>[ 48.878598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11711 12:13:23.229104 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11713 12:13:23.269017 /lava-10605430/1/../bin/lava-test-case
11714 12:13:23.294676 <8>[ 48.943976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11715 12:13:23.294998 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11717 12:13:23.314681 /lava-10605430/1/../bin/lava-test-case
11718 12:13:23.341387 <8>[ 48.991124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11719 12:13:23.341691 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11721 12:13:23.374427 /lava-10605430/1/../bin/lava-test-case
11722 12:13:23.400009 <8>[ 49.049320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11723 12:13:23.400359 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11725 12:13:24.432864 /lava-10605430/1/../bin/lava-test-case
11726 12:13:24.459449 <8>[ 50.109046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11727 12:13:24.459774 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11729 12:13:25.496146 /lava-10605430/1/../bin/lava-test-case
11730 12:13:25.524626 <8>[ 51.174362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11731 12:13:25.524924 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11732 12:13:25.525014 Bad test result: blocked
11733 12:13:25.551786 /lava-10605430/1/../bin/lava-test-case
11734 12:13:25.578450 <8>[ 51.228352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11735 12:13:25.578731 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11737 12:13:26.621838 /lava-10605430/1/../bin/lava-test-case
11738 12:13:26.652854 <8>[ 52.302445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11739 12:13:26.653149 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11741 12:13:26.678817 /lava-10605430/1/../bin/lava-test-case
11742 12:13:26.704716 <8>[ 52.354562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11743 12:13:26.705030 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11745 12:13:26.737505 /lava-10605430/1/../bin/lava-test-case
11746 12:13:26.764916 <8>[ 52.414868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11747 12:13:26.765228 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11749 12:13:26.795634 /lava-10605430/1/../bin/lava-test-case
11750 12:13:26.820835 <8>[ 52.470529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11751 12:13:26.821125 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11753 12:13:26.841887 /lava-10605430/1/../bin/lava-test-case
11754 12:13:26.875812 <8>[ 52.525841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11755 12:13:26.876161 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11757 12:13:26.910464 /lava-10605430/1/../bin/lava-test-case
11758 12:13:26.936802 <8>[ 52.586566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11759 12:13:26.937087 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11761 12:13:26.963964 /lava-10605430/1/../bin/lava-test-case
11762 12:13:26.990461 <8>[ 52.640332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11763 12:13:26.990756 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11765 12:13:28.039059 /lava-10605430/1/../bin/lava-test-case
11766 12:13:28.071259 <8>[ 53.721535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11767 12:13:28.071551 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11769 12:13:28.094784 /lava-10605430/1/../bin/lava-test-case
11770 12:13:28.125427 <8>[ 53.775948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11771 12:13:28.125718 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11773 12:13:29.172890 /lava-10605430/1/../bin/lava-test-case
11774 12:13:29.202560 <8>[ 54.853044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11775 12:13:29.202872 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11777 12:13:29.224690 /lava-10605430/1/../bin/lava-test-case
11778 12:13:29.251593 <8>[ 54.901956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11779 12:13:29.251942 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11781 12:13:30.294015 /lava-10605430/1/../bin/lava-test-case
11782 12:13:30.324529 <8>[ 55.975148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11783 12:13:30.324879 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11785 12:13:30.348981 /lava-10605430/1/../bin/lava-test-case
11786 12:13:30.386601 <8>[ 56.037291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11787 12:13:30.386942 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11789 12:13:31.437765 /lava-10605430/1/../bin/lava-test-case
11790 12:13:31.466269 <8>[ 57.117136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11791 12:13:31.466632 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11793 12:13:31.488522 /lava-10605430/1/../bin/lava-test-case
11794 12:13:31.513150 <8>[ 57.164036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11795 12:13:31.513519 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11797 12:13:31.546382 /lava-10605430/1/../bin/lava-test-case
11798 12:13:31.574112 <8>[ 57.224525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11799 12:13:31.574469 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11801 12:13:31.603814 /lava-10605430/1/../bin/lava-test-case
11802 12:13:31.630512 <8>[ 57.281327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11803 12:13:31.630876 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11805 12:13:31.654253 /lava-10605430/1/../bin/lava-test-case
11806 12:13:31.681432 <8>[ 57.332205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11807 12:13:31.681761 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11809 12:13:31.716318 /lava-10605430/1/../bin/lava-test-case
11810 12:13:31.742014 <8>[ 57.392642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11811 12:13:31.742340 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11813 12:13:31.770605 /lava-10605430/1/../bin/lava-test-case
11814 12:13:31.799262 <8>[ 57.450112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11815 12:13:31.799595 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11817 12:13:31.833806 /lava-10605430/1/../bin/lava-test-case
11818 12:13:31.862407 <8>[ 57.512981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11819 12:13:31.862738 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11821 12:13:31.885967 /lava-10605430/1/../bin/lava-test-case
11822 12:13:31.912779 <8>[ 57.563610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11823 12:13:31.913109 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11825 12:13:32.958459 /lava-10605430/1/../bin/lava-test-case
11826 12:13:32.992019 <8>[ 58.642719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11827 12:13:32.992371 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11829 12:13:33.000434 + <8>[ 58.654739] <LAVA_SIGNAL_ENDRUN 1_bootrr 10605430_1.6.2.3.5>
11830 12:13:33.000691 Received signal: <ENDRUN> 1_bootrr 10605430_1.6.2.3.5
11831 12:13:33.000773 Ending use of test pattern.
11832 12:13:33.000839 Ending test lava.1_bootrr (10605430_1.6.2.3.5), duration 31.14
11834 12:13:33.004107 set +x
11835 12:13:33.008454 <LAVA_TEST_RUNNER EXIT>
11836 12:13:33.008736 ok: lava_test_shell seems to have completed
11837 12:13:33.010949 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11838 12:13:33.011131 end: 4.1 lava-test-shell (duration 00:00:32) [common]
11839 12:13:33.011252 end: 4 lava-test-retry (duration 00:00:32) [common]
11840 12:13:33.011373 start: 5 finalize (timeout 00:07:22) [common]
11841 12:13:33.011496 start: 5.1 power-off (timeout 00:00:30) [common]
11842 12:13:33.011821 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11843 12:13:33.086988 >> Command sent successfully.
11844 12:13:33.089308 Returned 0 in 0 seconds
11845 12:13:33.189739 end: 5.1 power-off (duration 00:00:00) [common]
11847 12:13:33.190261 start: 5.2 read-feedback (timeout 00:07:21) [common]
11848 12:13:33.190570 Listened to connection for namespace 'common' for up to 1s
11849 12:13:34.191485 Finalising connection for namespace 'common'
11850 12:13:34.191680 Disconnecting from shell: Finalise
11851 12:13:34.191797 / #
11852 12:13:34.292142 end: 5.2 read-feedback (duration 00:00:01) [common]
11853 12:13:34.292351 end: 5 finalize (duration 00:00:01) [common]
11854 12:13:34.292514 Cleaning after the job
11855 12:13:34.292653 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/ramdisk
11856 12:13:34.294676 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/kernel
11857 12:13:34.303096 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/dtb
11858 12:13:34.303326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/nfsrootfs
11859 12:13:34.355501 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10605430/tftp-deploy-ez8uklv8/modules
11860 12:13:34.360820 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10605430
11861 12:13:34.687353 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10605430
11862 12:13:34.687581 Job finished correctly